Merge "Upgrade to valgrind 3.13.0 (15 June 2017)." am: 84dd75ab14
am: b2c798d6de
Change-Id: I5d4640b762722fd7f2e3c31f5b16aa64b1447743
diff --git a/ANDROID_PATCH_AGAINST_UPSTREAM.txt b/ANDROID_PATCH_AGAINST_UPSTREAM.txt
index 35deacb..99775b1 100644
--- a/ANDROID_PATCH_AGAINST_UPSTREAM.txt
+++ b/ANDROID_PATCH_AGAINST_UPSTREAM.txt
@@ -6,9 +6,9 @@
Only in /huge-ssd/aosp-arm64/external/valgrind/: Android.mk
Only in /huge-ssd/aosp-arm64/external/valgrind/: ANDROID_PATCH_AGAINST_UPSTREAM.txt
Only in /huge-ssd/aosp-arm64/external/valgrind/: Android.test.mk
-diff '--exclude=.git' -ru ./config.h /huge-ssd/aosp-arm64/external/valgrind/config.h
---- ./config.h 2016-10-21 03:42:48.000000000 -0700
-+++ /huge-ssd/aosp-arm64/external/valgrind/config.h 2017-04-18 17:15:06.884303094 -0700
+diff '--exclude=.git' -ru valgrind-3.13.0/config.h /huge-ssd/aosp-arm64/external/valgrind/config.h
+--- valgrind-3.13.0/config.h 2017-06-21 14:11:07.177545261 -0700
++++ /huge-ssd/aosp-arm64/external/valgrind/config.h 2017-06-21 14:07:44.786099941 -0700
@@ -45,10 +45,14 @@
/* Define to 1 if index() and strlen() have been optimized heavily (x86 glibc
@@ -33,12 +33,12 @@
+#endif
/* Define to 1 if the system has the type `Elf32_Chdr'. */
--#define HAVE_ELF32_CHDR 1
-+/* #undef HAVE_ELF32_CHDR */
+-/* #undef HAVE_ELF32_CHDR */
++//#define HAVE_ELF32_CHDR 1
/* Define to 1 if the system has the type `Elf64_Chdr'. */
--#define HAVE_ELF64_CHDR 1
-+/* #undef HAVE_ELF64_CHDR */
+-/* #undef HAVE_ELF64_CHDR */
++//#define HAVE_ELF64_CHDR 1
/* Define to 1 if you have the <endian.h> header file. */
#define HAVE_ENDIAN_H 1
@@ -72,8 +72,8 @@
/* Define to 1 if you have the `signalfd' function. */
#define HAVE_SIGNALFD 1
-@@ -450,7 +462,11 @@
- #define VERSION "3.12.0"
+@@ -456,7 +468,11 @@
+ #define VERSION "3.13.0"
/* Temporary files directory */
+#ifdef __ANDROID__
@@ -84,9 +84,9 @@
/* Define to `int' if <sys/types.h> doesn't define. */
/* #undef gid_t */
-diff '--exclude=.git' -ru ./coregrind/m_coredump/coredump-elf.c /huge-ssd/aosp-arm64/external/valgrind/coregrind/m_coredump/coredump-elf.c
---- ./coregrind/m_coredump/coredump-elf.c 2016-10-21 03:37:40.000000000 -0700
-+++ /huge-ssd/aosp-arm64/external/valgrind/coregrind/m_coredump/coredump-elf.c 2017-04-18 17:46:05.683070839 -0700
+diff '--exclude=.git' -ru valgrind-3.13.0/coregrind/m_coredump/coredump-elf.c /huge-ssd/aosp-arm64/external/valgrind/coregrind/m_coredump/coredump-elf.c
+--- valgrind-3.13.0/coregrind/m_coredump/coredump-elf.c 2017-05-31 08:14:48.000000000 -0700
++++ /huge-ssd/aosp-arm64/external/valgrind/coregrind/m_coredump/coredump-elf.c 2017-06-21 14:08:45.497933443 -0700
@@ -135,6 +135,7 @@
phdr->p_align = VKI_PAGE_SIZE;
}
@@ -103,85 +103,41 @@
struct note {
struct note *next;
-diff '--exclude=.git' -ru ./coregrind/m_main.c /huge-ssd/aosp-arm64/external/valgrind/coregrind/m_main.c
---- ./coregrind/m_main.c 2016-10-21 03:37:40.000000000 -0700
-+++ /huge-ssd/aosp-arm64/external/valgrind/coregrind/m_main.c 2017-04-19 10:42:08.740064299 -0700
-@@ -2943,6 +2943,47 @@
- VG_(printf)("Something called __aeabi_unwind_cpp_pr1()\n");
- vg_assert(0);
- }
-+
-+#if defined(__ANDROID__) && defined(__clang__)
-+/* Replace __aeabi_memcpy* functions with vgPlain_memcpy. */
-+void* __aeabi_memcpy(void *dest, const void *src, SizeT n);
-+void* __aeabi_memcpy(void *dest, const void *src, SizeT n)
-+{
-+ return VG_(memcpy)(dest, src, n);
-+}
-+
-+void* __aeabi_memcpy4(void *dest, const void *src, SizeT n);
-+void* __aeabi_memcpy4(void *dest, const void *src, SizeT n)
-+{
-+ return VG_(memcpy)(dest, src, n);
-+}
-+
-+void* __aeabi_memcpy8(void *dest, const void *src, SizeT n);
-+void* __aeabi_memcpy8(void *dest, const void *src, SizeT n)
-+{
-+ return VG_(memcpy)(dest, src, n);
-+}
-+
-+/* Replace __aeabi_memclr* functions with vgPlain_memset. */
-+void* __aeabi_memclr(void *dest, SizeT n);
-+void* __aeabi_memclr(void *dest, SizeT n)
-+{
-+ return VG_(memset)(dest, 0, n);
-+}
-+
-+void* __aeabi_memclr4(void *dest, SizeT n);
-+void* __aeabi_memclr4(void *dest, SizeT n)
-+{
-+ return VG_(memset)(dest, 0, n);
-+}
-+
-+void* __aeabi_memclr8(void *dest, SizeT n);
-+void* __aeabi_memclr8(void *dest, SizeT n)
-+{
-+ return VG_(memset)(dest, 0, n);
-+}
-+#endif /* __ANDROID__ __clang__ */
-+
- #endif
-
- /* ---------------- Requirement 2 ---------------- */
-diff '--exclude=.git' -ru ./coregrind/vgdb.c /huge-ssd/aosp-arm64/external/valgrind/coregrind/vgdb.c
---- ./coregrind/vgdb.c 2016-10-21 03:37:39.000000000 -0700
-+++ /huge-ssd/aosp-arm64/external/valgrind/coregrind/vgdb.c 2017-04-18 18:08:21.647243892 -0700
-@@ -682,7 +682,8 @@
+diff '--exclude=.git' -ru valgrind-3.13.0/coregrind/vgdb.c /huge-ssd/aosp-arm64/external/valgrind/coregrind/vgdb.c
+--- valgrind-3.13.0/coregrind/vgdb.c 2017-05-31 08:14:29.000000000 -0700
++++ /huge-ssd/aosp-arm64/external/valgrind/coregrind/vgdb.c 2017-06-21 14:17:48.668450889 -0700
+@@ -682,10 +682,7 @@
sigpipe++;
} else if (signum == SIGALRM) {
sigalrm++;
-#if defined(VGPV_arm_linux_android) \
-+#if defined(VGPV_amd64_linux_android) \
-+ || defined(VGPV_arm_linux_android) \
- || defined(VGPV_x86_linux_android) \
- || defined(VGPV_mips32_linux_android) \
- || defined(VGPV_arm64_linux_android)
-diff '--exclude=.git' -ru ./coregrind/vg_preloaded.c /huge-ssd/aosp-arm64/external/valgrind/coregrind/vg_preloaded.c
---- ./coregrind/vg_preloaded.c 2016-10-21 03:37:40.000000000 -0700
-+++ /huge-ssd/aosp-arm64/external/valgrind/coregrind/vg_preloaded.c 2017-04-19 09:41:12.242842176 -0700
-@@ -58,6 +58,7 @@
+- || defined(VGPV_x86_linux_android) \
+- || defined(VGPV_mips32_linux_android) \
+- || defined(VGPV_arm64_linux_android)
++#if defined(__BIONIC__)
+ /* Android has no pthread_cancel. As it also does not have
+ an invoker implementation, there is no need for cleanup action.
+ So, we just do nothing. */
+diff '--exclude=.git' -ru valgrind-3.13.0/coregrind/vg_preloaded.c /huge-ssd/aosp-arm64/external/valgrind/coregrind/vg_preloaded.c
+--- valgrind-3.13.0/coregrind/vg_preloaded.c 2017-05-31 08:14:39.000000000 -0700
++++ /huge-ssd/aosp-arm64/external/valgrind/coregrind/vg_preloaded.c 2017-06-21 14:21:53.515782606 -0700
+@@ -58,10 +58,11 @@
void VG_NOTIFY_ON_LOAD(freeres)(Vg_FreeresToRun to_run)
{
- # if !defined(__UCLIBC__) \
+ # if !defined(__UCLIBC__) && !defined(MUSL_LIBC) \
+ && !defined(VGPV_amd64_linux_android) \
&& !defined(VGPV_arm_linux_android) \
&& !defined(VGPV_x86_linux_android) \
&& !defined(VGPV_mips32_linux_android) \
-diff '--exclude=.git' -ru ./include/pub_tool_libcsetjmp.h /huge-ssd/aosp-arm64/external/valgrind/include/pub_tool_libcsetjmp.h
---- ./include/pub_tool_libcsetjmp.h 2016-10-21 03:37:39.000000000 -0700
-+++ /huge-ssd/aosp-arm64/external/valgrind/include/pub_tool_libcsetjmp.h 2017-04-18 17:15:06.932302961 -0700
-@@ -120,6 +120,14 @@
+- && !defined(VGPV_arm64_linux_android)
++ && !defined(VGPV_arm64_linux_android) \
+
+ /* g++ mangled __gnu_cxx::__freeres yields -> _ZN9__gnu_cxx9__freeresEv */
+ extern void _ZN9__gnu_cxx9__freeresEv(void) __attribute__((weak));
+diff '--exclude=.git' -ru valgrind-3.13.0/include/pub_tool_libcsetjmp.h /huge-ssd/aosp-arm64/external/valgrind/include/pub_tool_libcsetjmp.h
+--- valgrind-3.13.0/include/pub_tool_libcsetjmp.h 2017-05-31 08:14:14.000000000 -0700
++++ /huge-ssd/aosp-arm64/external/valgrind/include/pub_tool_libcsetjmp.h 2017-06-21 14:27:04.766932185 -0700
+@@ -128,6 +128,14 @@
__attribute__((noreturn))
void VG_MINIMAL_LONGJMP(VG_MINIMAL_JMP_BUF(_env));
@@ -196,8 +152,6 @@
#else
/* The default implementation. */
-Only in /huge-ssd/aosp-arm64/external/valgrind/: MODULE_LICENSE_GPL
-Only in /huge-ssd/aosp-arm64/external/valgrind/: NOTICE
Only in /huge-ssd/aosp-arm64/external/valgrind/: runtests-arm64.sh
Only in /huge-ssd/aosp-arm64/external/valgrind/: runtests-arm.sh
Only in /huge-ssd/aosp-arm64/external/valgrind/: runtest.sh
diff --git a/Android.mk b/Android.mk
index a192c2e..ea29261 100644
--- a/Android.mk
+++ b/Android.mk
@@ -193,6 +193,8 @@
coregrind/m_vkiscnums.c \
coregrind/m_wordfm.c \
coregrind/m_xarray.c \
+ coregrind/m_xtmemory.c \
+ coregrind/m_xtree.c \
coregrind/m_aspacehl.c \
coregrind/m_aspacemgr/aspacemgr-common.c \
coregrind/m_aspacemgr/aspacemgr-linux.c \
@@ -218,6 +220,7 @@
coregrind/m_demangle/d-demangle.c \
coregrind/m_demangle/demangle.c \
coregrind/m_demangle/dyn-string.c \
+ coregrind/m_demangle/rust-demangle.c \
coregrind/m_demangle/safe-ctype.c \
coregrind/m_dispatch/dispatch-x86-linux.S \
coregrind/m_dispatch/dispatch-amd64-linux.S \
diff --git a/FAQ.txt b/FAQ.txt
index 2ffc052..63b199f 100644
--- a/FAQ.txt
+++ b/FAQ.txt
@@ -1,8 +1,8 @@
Valgrind FAQ
-Release 3.12.0 20 October 2016
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Release 3.13.0 15 June 2017
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
Table of Contents
1. Background
diff --git a/Makefile.all.am b/Makefile.all.am
index 02059a3..1859a51 100644
--- a/Makefile.all.am
+++ b/Makefile.all.am
@@ -150,6 +150,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -160,6 +161,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -239,9 +241,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
-
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -299,7 +298,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
diff --git a/Makefile.am b/Makefile.am
index c43b570..fdce3cf 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -62,7 +62,7 @@
pkgconfigdir = $(libdir)/pkgconfig
pkgconfig_DATA = valgrind.pc
-BUILT_SOURCES = default.supp valgrind.pc
+BUILT_SOURCES = default.supp include/vgversion.h valgrind.pc
CLEANFILES = default.supp
default.supp: $(DEFAULT_SUPP_FILES)
@@ -116,16 +116,26 @@
valgrind.spec \
autogen.sh
+dist-hook: include/vgversion.h
+ cp -p include/vgversion.h $(distdir)/include/vgversion_dist.h
+
dist_noinst_SCRIPTS = \
vg-in-place
-all-local: default.supp
+all-local: default.supp include/vgversion.h
mkdir -p $(inplacedir)
rm -f $(inplacedir)/default.supp
ln -s ../default.supp $(inplacedir)
clean-local:
- rm -rf $(inplacedir)
+ rm -rf $(inplacedir) include/vgversion.h
# Need config.h in the installed tree, since some files depend on it
pkginclude_HEADERS = config.h
+
+# vgversion.h defines accurate versions to report with -v --version
+include/vgversion.h:
+ $(top_srcdir)/auxprogs/make_or_upd_vgversion_h $(top_srcdir)
+
+.PHONY: include/vgversion.h
+
diff --git a/Makefile.in b/Makefile.in
index dae8b1f..be1d460 100644
--- a/Makefile.in
+++ b/Makefile.in
@@ -214,7 +214,7 @@
$(srcdir)/valgrind.spec.in $(top_srcdir)/Makefile.all.am \
$(top_srcdir)/drd/scripts/download-and-build-splash2.in \
AUTHORS COPYING NEWS README compile config.guess config.sub \
- install-sh missing
+ depcomp install-sh missing
DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
distdir = $(PACKAGE)-$(VERSION)
top_distdir = $(distdir)
@@ -301,6 +301,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -472,6 +473,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -482,6 +484,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -556,8 +559,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -602,7 +603,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
TOOLS = memcheck \
@@ -663,7 +663,7 @@
vglib_DATA = default.supp
pkgconfigdir = $(libdir)/pkgconfig
pkgconfig_DATA = valgrind.pc
-BUILT_SOURCES = default.supp valgrind.pc
+BUILT_SOURCES = default.supp include/vgversion.h valgrind.pc
CLEANFILES = default.supp
# Nb: no need to include any Makefile.am files here, or files included from
@@ -982,6 +982,9 @@
|| exit 1; \
fi; \
done
+ $(MAKE) $(AM_MAKEFLAGS) \
+ top_distdir="$(top_distdir)" distdir="$(distdir)" \
+ dist-hook
-test -n "$(am__skip_mode_fix)" \
|| find "$(distdir)" -type d ! -perm -755 \
-exec chmod u+rwx,go+rx {} \; -o \
@@ -990,7 +993,7 @@
! -type d ! -perm -444 -exec $(install_sh) -c -m a+r {} {} \; \
|| chmod -R a+r "$(distdir)"
dist-gzip: distdir
- tardir=$(distdir) && $(am__tar) | GZIP=$(GZIP_ENV) gzip -c >$(distdir).tar.gz
+ tardir=$(distdir) && $(am__tar) | eval GZIP= gzip $(GZIP_ENV) -c >$(distdir).tar.gz
$(am__post_remove_distdir)
dist-bzip2: distdir
tardir=$(distdir) && $(am__tar) | BZIP2=$${BZIP2--9} bzip2 -c >$(distdir).tar.bz2
@@ -1015,7 +1018,7 @@
@echo WARNING: "Support for shar distribution archives is" \
"deprecated." >&2
@echo WARNING: "It will be removed altogether in Automake 2.0" >&2
- shar $(distdir) | GZIP=$(GZIP_ENV) gzip -c >$(distdir).shar.gz
+ shar $(distdir) | eval GZIP= gzip $(GZIP_ENV) -c >$(distdir).shar.gz
$(am__post_remove_distdir)
dist-zip: distdir
@@ -1033,7 +1036,7 @@
distcheck: dist
case '$(DIST_ARCHIVES)' in \
*.tar.gz*) \
- GZIP=$(GZIP_ENV) gzip -dc $(distdir).tar.gz | $(am__untar) ;;\
+ eval GZIP= gzip $(GZIP_ENV) -dc $(distdir).tar.gz | $(am__untar) ;;\
*.tar.bz2*) \
bzip2 -dc $(distdir).tar.bz2 | $(am__untar) ;;\
*.tar.lz*) \
@@ -1043,7 +1046,7 @@
*.tar.Z*) \
uncompress -c $(distdir).tar.Z | $(am__untar) ;;\
*.shar.gz*) \
- GZIP=$(GZIP_ENV) gzip -dc $(distdir).shar.gz | unshar ;;\
+ eval GZIP= gzip $(GZIP_ENV) -dc $(distdir).shar.gz | unshar ;;\
*.zip*) \
unzip $(distdir).zip ;;\
esac
@@ -1231,20 +1234,21 @@
.PHONY: $(am__recursive_targets) CTAGS GTAGS TAGS all all-am all-local \
am--refresh check check-am clean clean-cscope clean-generic \
clean-local cscope cscopelist-am ctags ctags-am dist dist-all \
- dist-bzip2 dist-gzip dist-lzip dist-shar dist-tarZ dist-xz \
- dist-zip distcheck distclean distclean-generic distclean-hdr \
- distclean-tags distcleancheck distdir distuninstallcheck dvi \
- dvi-am html html-am info info-am install install-am \
- install-data install-data-am install-dvi install-dvi-am \
- install-exec install-exec-am install-html install-html-am \
- install-info install-info-am install-man install-pdf \
- install-pdf-am install-pkgconfigDATA install-pkgincludeHEADERS \
- install-ps install-ps-am install-strip install-vglibDATA \
- installcheck installcheck-am installdirs installdirs-am \
- maintainer-clean maintainer-clean-generic mostlyclean \
- mostlyclean-generic pdf pdf-am ps ps-am tags tags-am uninstall \
- uninstall-am uninstall-pkgconfigDATA \
- uninstall-pkgincludeHEADERS uninstall-vglibDATA
+ dist-bzip2 dist-gzip dist-hook dist-lzip dist-shar dist-tarZ \
+ dist-xz dist-zip distcheck distclean distclean-generic \
+ distclean-hdr distclean-tags distcleancheck distdir \
+ distuninstallcheck dvi dvi-am html html-am info info-am \
+ install install-am install-data install-data-am install-dvi \
+ install-dvi-am install-exec install-exec-am install-html \
+ install-html-am install-info install-info-am install-man \
+ install-pdf install-pdf-am install-pkgconfigDATA \
+ install-pkgincludeHEADERS install-ps install-ps-am \
+ install-strip install-vglibDATA installcheck installcheck-am \
+ installdirs installdirs-am maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-generic pdf \
+ pdf-am ps ps-am tags tags-am uninstall uninstall-am \
+ uninstall-pkgconfigDATA uninstall-pkgincludeHEADERS \
+ uninstall-vglibDATA
.PRECIOUS: Makefile
@@ -1354,13 +1358,22 @@
perf: check
@PERL@ perf/vg_perf perf
-all-local: default.supp
+dist-hook: include/vgversion.h
+ cp -p include/vgversion.h $(distdir)/include/vgversion_dist.h
+
+all-local: default.supp include/vgversion.h
mkdir -p $(inplacedir)
rm -f $(inplacedir)/default.supp
ln -s ../default.supp $(inplacedir)
clean-local:
- rm -rf $(inplacedir)
+ rm -rf $(inplacedir) include/vgversion.h
+
+# vgversion.h defines accurate versions to report with -v --version
+include/vgversion.h:
+ $(top_srcdir)/auxprogs/make_or_upd_vgversion_h $(top_srcdir)
+
+.PHONY: include/vgversion.h
# Tell versions [3.59,3.63) of GNU make to not export all variables.
# Otherwise a system limit (for SysV at least) may be exceeded.
diff --git a/Makefile.tool-tests.am b/Makefile.tool-tests.am
index 59c3b42..b27724f 100644
--- a/Makefile.tool-tests.am
+++ b/Makefile.tool-tests.am
@@ -28,7 +28,7 @@
if VGCONF_OS_IS_SOLARIS
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
AM_CFLAGS += -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
endif
diff --git a/Makefile.tool.am b/Makefile.tool.am
index 5af3023..677571f 100644
--- a/Makefile.tool.am
+++ b/Makefile.tool.am
@@ -79,9 +79,6 @@
-static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \
@FLAG_M64@
-TOOL_LDFLAGS_TILEGX_LINUX = \
- $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-
TOOL_LDFLAGS_X86_SOLARIS = \
$(TOOL_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
@@ -144,9 +141,6 @@
LIBREPLACEMALLOC_MIPS64_LINUX = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a
-LIBREPLACEMALLOC_TILEGX_LINUX = \
- $(top_builddir)/coregrind/libreplacemalloc_toolpreload-tilegx-linux.a
-
LIBREPLACEMALLOC_X86_SOLARIS = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-solaris.a
@@ -209,11 +203,6 @@
$(LIBREPLACEMALLOC_MIPS64_LINUX) \
-Wl,--no-whole-archive
-LIBREPLACEMALLOC_LDFLAGS_TILEGX_LINUX = \
- -Wl,--whole-archive \
- $(LIBREPLACEMALLOC_TILEGX_LINUX) \
- -Wl,--no-whole-archive
-
LIBREPLACEMALLOC_LDFLAGS_X86_SOLARIS = \
-Wl,--whole-archive \
$(LIBREPLACEMALLOC_X86_SOLARIS) \
diff --git a/Makefile.vex.am b/Makefile.vex.am
index 8e1ec3c..9b9b9b5 100644
--- a/Makefile.vex.am
+++ b/Makefile.vex.am
@@ -26,7 +26,6 @@
pub/libvex_guest_s390x.h \
pub/libvex_guest_mips32.h \
pub/libvex_guest_mips64.h \
- pub/libvex_guest_tilegx.h \
pub/libvex_s390x_common.h \
pub/libvex_ir.h \
pub/libvex_trc_values.h
@@ -45,7 +44,6 @@
priv/guest_arm64_defs.h \
priv/guest_s390_defs.h \
priv/guest_mips_defs.h \
- priv/guest_tilegx_defs.h \
priv/host_generic_regs.h \
priv/host_generic_simd64.h \
priv/host_generic_simd128.h \
@@ -57,11 +55,9 @@
priv/host_arm_defs.h \
priv/host_arm64_defs.h \
priv/host_s390_defs.h \
- priv/host_tilegx_defs.h \
priv/s390_disasm.h \
priv/s390_defs.h \
- priv/host_mips_defs.h \
- priv/tilegx_disasm.h
+ priv/host_mips_defs.h
BUILT_SOURCES = pub/libvex_guest_offsets.h
CLEANFILES = pub/libvex_guest_offsets.h
@@ -86,8 +82,7 @@
pub/libvex_guest_arm64.h \
pub/libvex_guest_s390x.h \
pub/libvex_guest_mips32.h \
- pub/libvex_guest_mips64.h \
- pub/libvex_guest_tilegx.h
+ pub/libvex_guest_mips64.h
rm -f auxprogs/genoffsets.s
$(mkdir_p) auxprogs pub
$(CC) $(CFLAGS_FOR_GENOFFSETS) \
@@ -142,8 +137,6 @@
priv/guest_s390_toIR.c \
priv/guest_mips_helpers.c \
priv/guest_mips_toIR.c \
- priv/guest_tilegx_helpers.c \
- priv/guest_tilegx_toIR.c \
priv/host_generic_regs.c \
priv/host_generic_simd64.c \
priv/host_generic_simd128.c \
@@ -164,10 +157,7 @@
priv/host_s390_isel.c \
priv/s390_disasm.c \
priv/host_mips_defs.c \
- priv/host_mips_isel.c \
- priv/host_tilegx_defs.c \
- priv/host_tilegx_isel.c \
- priv/tilegx_disasm.c
+ priv/host_mips_isel.c
LIBVEXMULTIARCH_SOURCES = priv/multiarch_main_main.c
diff --git a/Makefile.vex.in b/Makefile.vex.in
index ab9bc2f..b348da6 100644
--- a/Makefile.vex.in
+++ b/Makefile.vex.in
@@ -182,8 +182,6 @@
priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_s390_toIR.$(OBJEXT) \
priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_mips_helpers.$(OBJEXT) \
priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_mips_toIR.$(OBJEXT) \
- priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_tilegx_helpers.$(OBJEXT) \
- priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_tilegx_toIR.$(OBJEXT) \
priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_regs.$(OBJEXT) \
priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd64.$(OBJEXT) \
priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.$(OBJEXT) \
@@ -204,10 +202,7 @@
priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_s390_isel.$(OBJEXT) \
priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-s390_disasm.$(OBJEXT) \
priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_mips_defs.$(OBJEXT) \
- priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_mips_isel.$(OBJEXT) \
- priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_tilegx_defs.$(OBJEXT) \
- priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_tilegx_isel.$(OBJEXT) \
- priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-tilegx_disasm.$(OBJEXT)
+ priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_mips_isel.$(OBJEXT)
am_libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_OBJECTS = $(am__objects_1)
libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_OBJECTS = \
$(am_libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_OBJECTS)
@@ -224,7 +219,6 @@
priv/guest_arm64_helpers.c priv/guest_arm64_toIR.c \
priv/guest_s390_helpers.c priv/guest_s390_toIR.c \
priv/guest_mips_helpers.c priv/guest_mips_toIR.c \
- priv/guest_tilegx_helpers.c priv/guest_tilegx_toIR.c \
priv/host_generic_regs.c priv/host_generic_simd64.c \
priv/host_generic_simd128.c priv/host_generic_simd256.c \
priv/host_generic_maddf.c priv/host_generic_reg_alloc2.c \
@@ -234,8 +228,7 @@
priv/host_arm_isel.c priv/host_arm64_defs.c \
priv/host_arm64_isel.c priv/host_s390_defs.c \
priv/host_s390_isel.c priv/s390_disasm.c priv/host_mips_defs.c \
- priv/host_mips_isel.c priv/host_tilegx_defs.c \
- priv/host_tilegx_isel.c priv/tilegx_disasm.c
+ priv/host_mips_isel.c
am__objects_2 = priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main_globals.$(OBJEXT) \
priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main_main.$(OBJEXT) \
priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main_util.$(OBJEXT) \
@@ -259,8 +252,6 @@
priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_s390_toIR.$(OBJEXT) \
priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_mips_helpers.$(OBJEXT) \
priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_mips_toIR.$(OBJEXT) \
- priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_tilegx_helpers.$(OBJEXT) \
- priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_tilegx_toIR.$(OBJEXT) \
priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_regs.$(OBJEXT) \
priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd64.$(OBJEXT) \
priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.$(OBJEXT) \
@@ -281,10 +272,7 @@
priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_s390_isel.$(OBJEXT) \
priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-s390_disasm.$(OBJEXT) \
priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_mips_defs.$(OBJEXT) \
- priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_mips_isel.$(OBJEXT) \
- priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_tilegx_defs.$(OBJEXT) \
- priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_tilegx_isel.$(OBJEXT) \
- priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-tilegx_disasm.$(OBJEXT)
+ priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_mips_isel.$(OBJEXT)
@VGCONF_HAVE_PLATFORM_SEC_TRUE@am_libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_OBJECTS = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(am__objects_2)
libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_OBJECTS = \
@@ -417,6 +405,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -587,6 +576,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -597,6 +587,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -671,8 +662,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -717,7 +706,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
@@ -744,7 +732,6 @@
pub/libvex_guest_s390x.h \
pub/libvex_guest_mips32.h \
pub/libvex_guest_mips64.h \
- pub/libvex_guest_tilegx.h \
pub/libvex_s390x_common.h \
pub/libvex_ir.h \
pub/libvex_trc_values.h
@@ -763,7 +750,6 @@
priv/guest_arm64_defs.h \
priv/guest_s390_defs.h \
priv/guest_mips_defs.h \
- priv/guest_tilegx_defs.h \
priv/host_generic_regs.h \
priv/host_generic_simd64.h \
priv/host_generic_simd128.h \
@@ -775,11 +761,9 @@
priv/host_arm_defs.h \
priv/host_arm64_defs.h \
priv/host_s390_defs.h \
- priv/host_tilegx_defs.h \
priv/s390_disasm.h \
priv/s390_defs.h \
- priv/host_mips_defs.h \
- priv/tilegx_disasm.h
+ priv/host_mips_defs.h
BUILT_SOURCES = pub/libvex_guest_offsets.h
CLEANFILES = pub/libvex_guest_offsets.h
@@ -820,8 +804,6 @@
priv/guest_s390_toIR.c \
priv/guest_mips_helpers.c \
priv/guest_mips_toIR.c \
- priv/guest_tilegx_helpers.c \
- priv/guest_tilegx_toIR.c \
priv/host_generic_regs.c \
priv/host_generic_simd64.c \
priv/host_generic_simd128.c \
@@ -842,10 +824,7 @@
priv/host_s390_isel.c \
priv/s390_disasm.c \
priv/host_mips_defs.c \
- priv/host_mips_isel.c \
- priv/host_tilegx_defs.c \
- priv/host_tilegx_isel.c \
- priv/tilegx_disasm.c
+ priv/host_mips_isel.c
LIBVEXMULTIARCH_SOURCES = priv/multiarch_main_main.c
LIBVEX_CFLAGS = \
@@ -1002,10 +981,6 @@
priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp)
priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_mips_toIR.$(OBJEXT): \
priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp)
-priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_tilegx_helpers.$(OBJEXT): \
- priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp)
-priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_tilegx_toIR.$(OBJEXT): \
- priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp)
priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_regs.$(OBJEXT): \
priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp)
priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd64.$(OBJEXT): \
@@ -1048,12 +1023,6 @@
priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp)
priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_mips_isel.$(OBJEXT): \
priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp)
-priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_tilegx_defs.$(OBJEXT): \
- priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp)
-priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_tilegx_isel.$(OBJEXT): \
- priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp)
-priv/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-tilegx_disasm.$(OBJEXT): \
- priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp)
libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a: $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_OBJECTS) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_DEPENDENCIES) $(EXTRA_libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_DEPENDENCIES)
$(AM_V_at)-rm -f libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
@@ -1105,10 +1074,6 @@
priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp)
priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_mips_toIR.$(OBJEXT): \
priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp)
-priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_tilegx_helpers.$(OBJEXT): \
- priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp)
-priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_tilegx_toIR.$(OBJEXT): \
- priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp)
priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_regs.$(OBJEXT): \
priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp)
priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd64.$(OBJEXT): \
@@ -1151,12 +1116,6 @@
priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp)
priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_mips_isel.$(OBJEXT): \
priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp)
-priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_tilegx_defs.$(OBJEXT): \
- priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp)
-priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_tilegx_isel.$(OBJEXT): \
- priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp)
-priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-tilegx_disasm.$(OBJEXT): \
- priv/$(am__dirstamp) priv/$(DEPDIR)/$(am__dirstamp)
libvex-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a: $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_OBJECTS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_DEPENDENCIES) $(EXTRA_libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_DEPENDENCIES)
$(AM_V_at)-rm -f libvex-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a
@@ -1198,8 +1157,6 @@
@AMDEP_TRUE@@am__include@ @am__quote@priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_ppc_toIR.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_s390_helpers.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_s390_toIR.Po@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_tilegx_helpers.Po@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_tilegx_toIR.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_x86_helpers.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_x86_toIR.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_amd64_defs.Po@am__quote@
@@ -1220,8 +1177,6 @@
@AMDEP_TRUE@@am__include@ @am__quote@priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_ppc_isel.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_s390_defs.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_s390_isel.Po@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_tilegx_defs.Po@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_tilegx_isel.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_x86_defs.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_x86_isel.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-ir_defs.Po@am__quote@
@@ -1232,7 +1187,6 @@
@AMDEP_TRUE@@am__include@ @am__quote@priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-main_main.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-main_util.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@priv/$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-s390_disasm.Po@am__quote@
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-
-priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_tilegx_isel.o: priv/host_tilegx_isel.c
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-
-priv/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_tilegx_isel.obj: priv/host_tilegx_isel.c
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-
priv/libvexmultiarch_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-multiarch_main_main.o: priv/multiarch_main_main.c
@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvexmultiarch_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvexmultiarch_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT priv/libvexmultiarch_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-multiarch_main_main.o -MD -MP -MF priv/$(DEPDIR)/libvexmultiarch_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-multiarch_main_main.Tpo -c -o priv/libvexmultiarch_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-multiarch_main_main.o `test -f 'priv/multiarch_main_main.c' || echo '$(srcdir)/'`priv/multiarch_main_main.c
@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) priv/$(DEPDIR)/libvexmultiarch_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-multiarch_main_main.Tpo priv/$(DEPDIR)/libvexmultiarch_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-multiarch_main_main.Po
@@ -3029,8 +2838,7 @@
pub/libvex_guest_arm64.h \
pub/libvex_guest_s390x.h \
pub/libvex_guest_mips32.h \
- pub/libvex_guest_mips64.h \
- pub/libvex_guest_tilegx.h
+ pub/libvex_guest_mips64.h
rm -f auxprogs/genoffsets.s
$(mkdir_p) auxprogs pub
$(CC) $(CFLAGS_FOR_GENOFFSETS) \
diff --git a/NEWS b/NEWS
index e0ce235..7f6befa 100644
--- a/NEWS
+++ b/NEWS
@@ -1,3 +1,262 @@
+Release 3.13.0 (15 June 2017)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+3.13.0 is a feature release with many improvements and the usual collection of
+bug fixes.
+
+This release supports X86/Linux, AMD64/Linux, ARM32/Linux, ARM64/Linux,
+PPC32/Linux, PPC64BE/Linux, PPC64LE/Linux, S390X/Linux, MIPS32/Linux,
+MIPS64/Linux, ARM/Android, ARM64/Android, MIPS32/Android, X86/Android,
+X86/Solaris, AMD64/Solaris and AMD64/MacOSX 10.12.
+
+* ==================== CORE CHANGES ===================
+
+* The translation cache size has been increased to keep up with the demands of
+ large applications. The maximum number of sectors has increased from 24 to
+ 48. The default number of sectors has increased from 16 to 32 on all
+ targets except Android, where the increase is from 6 to 12.
+
+* The amount of memory that Valgrind can use has been increased from 64GB to
+ 128GB. In particular this means your application can allocate up to about
+ 60GB when running on Memcheck.
+
+* Valgrind's default load address has been changed from 0x3800'0000 to
+ 0x5800'0000, so as to make it possible to load larger executables. This
+ should make it possible to load executables of size at least 1200MB.
+
+* A massive spaceleak caused by reading compressed debuginfo files has been
+ fixed. Valgrind should now be entirely usable with gcc-7.0 "-gz" created
+ debuginfo.
+
+* The C++ demangler has been updated.
+
+* Support for demangling Rust symbols has been added.
+
+* A new representation of stack traces, the "XTree", has been added. An XTree
+ is a tree of stacktraces with data associated with the stacktraces. This is
+ used by various tools (Memcheck, Helgrind, Massif) to report on the heap
+ consumption of your program. Reporting is controlled by the new options
+ --xtree-memory=none|allocs|full and --xtree-memory-file=<file>.
+
+ A report can also be produced on demand using the gdbserver monitor command
+ 'xtmemory [<filename>]>'. The XTree can be output in 2 formats: 'callgrind
+ format' and 'massif format. The existing visualisers for these formats (e.g.
+ callgrind_annotate, KCachegrind, ms_print) can be used to visualise and
+ analyse these reports.
+
+ Memcheck can also produce XTree leak reports using the Callgrind file
+ format. For more details, see the user manual.
+
+* ================== PLATFORM CHANGES =================
+
+* ppc64: support for ISA 3.0B and various fixes for existing 3.0 support
+
+* amd64: fixes for JIT failure problems on long AVX2 code blocks
+
+* amd64 and x86: support for CET prefixes has been added
+
+* arm32: a few missing ARMv8 instructions have been implemented
+
+* arm64, mips64, mips32: an alternative implementation of Load-Linked and
+ Store-Conditional instructions has been added. This is to deal with
+ processor implementations that implement the LL/SC specifications strictly
+ and as a result cause Valgrind to hang in certain situations. The
+ alternative implementation is automatically enabled at startup, as required.
+ You can use the option --sim-hints=fallback-llsc to force-enable it if you
+ want.
+
+* Support for OSX 10.12 has been improved.
+
+* On Linux, clone handling has been improved to honour CLONE_VFORK that
+ involves a child stack. Note however that CLONE_VFORK | CLONE_VM is handled
+ like CLONE_VFORK (by removing CLONE_VM), so applications that depend on
+ CLONE_VM exact semantics will (still) not work.
+
+* The TileGX/Linux port has been removed because it appears to be both unused
+ and unsupported.
+
+* ==================== TOOL CHANGES ====================
+
+* Memcheck:
+
+ - Memcheck should give fewer false positives when running optimised
+ Clang/LLVM generated code.
+
+ - Support for --xtree-memory and 'xtmemory [<filename>]>'.
+
+ - New command line options --xtree-leak=no|yes and --xtree-leak-file=<file>
+ to produce the end of execution leak report in a xtree callgrind format
+ file.
+
+ - New option 'xtleak' in the memcheck leak_check monitor command, to produce
+ the leak report in an xtree file.
+
+* Massif:
+
+ - Support for --xtree-memory and 'xtmemory [<filename>]>'.
+
+ - For some workloads (typically, for big applications), Massif memory
+ consumption and CPU consumption has decreased significantly.
+
+* Helgrind:
+
+ - Support for --xtree-memory and 'xtmemory [<filename>]>'.
+
+ - addition of client request VALGRIND_HG_GNAT_DEPENDENT_MASTER_JOIN, useful
+ for Ada gnat compiled applications.
+
+* ==================== OTHER CHANGES ====================
+
+* For Valgrind developers: in an outer/inner setup, the outer Valgrind will
+ append the inner guest stacktrace to the inner host stacktrace. This helps
+ to investigate the errors reported by the outer, when they are caused by the
+ inner guest program (such as an inner regtest). See README_DEVELOPERS for
+ more info.
+
+* To allow fast detection of callgrind files by desktop environments and file
+ managers, the format was extended to have an optional first line that
+ uniquely identifies the format ("# callgrind format"). Callgrind creates
+ this line now, as does the new xtree functionality.
+
+* File name template arguments (such as --log-file, --xtree-memory-file, ...)
+ have a new %n format letter that is replaced by a sequence number.
+
+* "--version -v" now shows the SVN revision numbers from which Valgrind was
+ built.
+
+* ==================== FIXED BUGS ====================
+
+The following bugs have been fixed or resolved. Note that "n-i-bz"
+stands for "not in bugzilla" -- that is, a bug that was reported to us
+but never got a bugzilla entry. We encourage you to file bugs in
+bugzilla (https://bugs.kde.org/enter_bug.cgi?product=valgrind) rather
+than mailing the developers (or mailing lists) directly -- bugs that
+are not entered into bugzilla tend to get forgotten about or ignored.
+
+To see details of a given bug, visit
+ https://bugs.kde.org/show_bug.cgi?id=XXXXXX
+where XXXXXX is the bug number as listed below.
+
+162848 --log-file output isn't split when a program forks
+340777 Illegal instruction on mips (ar71xx)
+341481 MIPS64: Iop_CmpNE32 triggers false warning on MIPS64 platforms
+342040 Valgrind mishandles clone with CLONE_VFORK | CLONE_VM that clones
+ to a different stack.
+344139 x86 stack-seg overrides, needed by the Wine people
+344524 store conditional of guest applications always fail - observed on
+ Octeon3(MIPS)
+348616 Wine/valgrind: noted but unhandled ioctl 0x5390 [..] (DVD_READ_STRUCT)
+352395 Please provide SVN revision info in --version -v
+352767 Wine/valgrind: noted but unhandled ioctl 0x5307 [..] (CDROMSTOP)
+356374 Assertion 'DRD_(g_threadinfo)[tid].pt_threadid !=
+ INVALID_POSIX_THREADID' failed
+358213 helgrind/drd bar_bad testcase hangs or crashes with new glibc pthread
+ barrier implementation
+358697 valgrind.h: Some code remains even when defining NVALGRIND
+359202 Add musl libc configure/compile
+360415 amd64 instructions ADCX and ADOX are not implemented in VEX
+ == 372828 (vex amd64->IR: 0x66 0xF 0x3A 0x62 0x4A 0x10)
+360429 unhandled ioctl 0x530d with no size/direction hints (CDROMREADMODE1)
+362223 assertion failed when .valgrindrc is a directory instead of a file
+367543 bt/btc/btr/bts x86/x86_64 instructions are poorly-handled wrt flags
+367942 Segfault vgPlain_do_sys_sigaction (m_signals.c:1138)
+368507 can't malloc chunks larger than about 34GB
+368529 Android arm target link error, missing atexit and pthread_atfork
+368863 WARNING: unhandled arm64-linux syscall: 100 (get_robust_list)
+368865 WARNING: unhandled arm64-linux syscall: 272 (kcmp)
+368868 disInstr(arm64): unhandled instruction 0xD53BE000 = cntfrq_el0 (ARMv8)
+368917 WARNING: unhandled arm64-linux syscall: 218 (request_key)
+368918 WARNING: unhandled arm64-linux syscall: 127 (sched_rr_get_interval)
+368922 WARNING: unhandled arm64-linux syscall: 161 (sethostname)
+368924 WARNING: unhandled arm64-linux syscall: 84 (sync_file_range)
+368925 WARNING: unhandled arm64-linux syscall: 130 (tkill)
+368926 WARNING: unhandled arm64-linux syscall: 97 (unshare)
+369459 valgrind on arm64 violates the ARMv8 spec (ldxr/stxr)
+370028 Reduce the number of compiler warnings on MIPS platforms
+370635 arm64 missing syscall getcpu
+371225 Fix order of timer_{gettime,getoverrun,settime} syscalls on arm64
+371227 Clean AArch64 syscall table
+371412 Rename wrap_sys_shmat to sys_shmat like other wrappers
+371471 Valgrind complains about non legit memory leaks on placement new (C++)
+371491 handleAddrOverrides() is [incorrect] when ASO prefix is used
+371503 disInstr(arm64): unhandled instruction 0xF89F0000
+371869 support '%' in symbol Z-encoding
+371916 execution tree xtree concept
+372120 c++ demangler demangles symbols which are not c++
+372185 Support of valgrind on ARMv8 with 32 bit executable
+372188 vex amd64->IR: 0x66 0xF 0x3A 0x62 0x4A 0x10 0x10 0x48 (PCMPxSTRx $0x10)
+372195 Power PC, xxsel instruction is not always recognized.
+372504 Hanging on exit_group
+372600 process loops forever when fatal signals are arriving quickly
+372794 LibVEX (arm32 front end): 'Assertion szBlg2 <= 3' failed
+373046 Stacks registered by core are never deregistered
+373069 memcheck/tests/leak_cpp_interior fails with GCC 5.1+
+373086 Implement additional Xen hypercalls
+373192 Calling posix_spawn in glibc 2.24 completely broken
+373488 Support for fanotify API on ARM64 architecture
+ == 368864 WARNING: unhandled arm64-linux syscall: 262 (fanotify_init)
+373555 Rename BBPTR to GSPTR as it denotes guest state pointer only
+373938 const IRExpr arguments for matchIRExpr()
+374719 some spelling fixes
+374963 increase valgrind's load address to prevent mmap failure
+375514 valgrind_get_tls_addr() does not work in case of static TLS
+375772 +1 error in get_elf_symbol_info() when computing value of 'hi' address
+ for ML_(find_rx_mapping)()
+375806 Test helgrind/tests/tc22_exit_w_lock fails with glibc 2.24
+375839 Temporary storage exhausted, with long sequence of vfmadd231ps insns
+ == 377159 "vex: the `impossible' happened" still present
+ == 375150 Assertion 'tres.status == VexTransOK' failed
+ == 378068 valgrind crashes on AVX2 function in FFmpeg
+376142 Segfaults on MIPS Cavium Octeon boards
+376279 disInstr(arm64): unhandled instruction 0xD50320FF
+376455 Solaris: unhandled syscall lgrpsys(180)
+376518 Solaris: unhandled fast trap getlgrp(6)
+376611 ppc64 and arm64 don't know about prlimit64 syscall
+376729 PPC64, remove R2 from the clobber list
+ == 371668
+376956 syswrap of SNDDRV and DRM_IOCTL_VERSION causing some addresses
+ to be wrongly marked as addressable
+377066 Some Valgrind unit tests fail to compile on Ubuntu 16.10 with
+ PIE enabled by default
+377376 memcheck/tests/linux/getregset fails with glibc2.24
+377427 PPC64, lxv instruction failing on odd destination register
+377478 PPC64: ISA 3.0 setup fixes
+377698 Missing memory check for futex() uaddr arg for FUTEX_WAKE
+ and FUTEX_WAKE_BITSET, check only 4 args for FUTEX_WAKE_BITSET,
+ and 2 args for FUTEX_TRYLOCK_PI
+377717 Fix massive space leak when reading compressed debuginfo sections
+377891 Update Xen 4.6 domctl wrappers
+377930 fcntl syscall wrapper is missing flock structure check
+378524 libvexmultiarch_test regression on s390x and ppc64
+378535 Valgrind reports INTERNAL ERROR in execve syscall wrapper
+378673 Update libiberty demangler
+378931 Add ISA 3.0B additional isnstructions, add OV32, CA32 setting support
+379039 syscall wrapper for prctl(PR_SET_NAME) must not check more than 16 bytes
+379094 Valgrind reports INTERNAL ERROR in rt_sigsuspend syscall wrapper
+379371 UNKNOWN task message [id 3444, to mach_task_self(), reply 0x603]
+ (task_register_dyld_image_infos)
+379372 UNKNOWN task message [id 3447, to mach_task_self(), reply 0x603]
+ (task_register_dyld_shared_cache_image_info)
+379390 unhandled syscall: mach:70 (host_create_mach_voucher_trap)
+379473 MIPS: add support for rdhwr cycle counter register
+379504 remove TileGX/Linux port
+379525 Support more x86 nop opcodes
+379838 disAMode(x86): not an addr!
+379703 PC ISA 3.0 fixes: stxvx, stxv, xscmpexpdp instructions
+379890 arm: unhandled instruction: 0xEBAD 0x1B05 (sub.w fp, sp, r5, lsl #4)
+379895 clock_gettime does not execute POST syscall wrapper
+379925 PPC64, mtffs does not set the FPCC and C bits in the FPSCR correctly
+379966 WARNING: unhandled amd64-linux syscall: 313 (finit_module)
+380200 xtree generated callgrind files refer to files without directory name
+380202 Assertion failure for cache line size (cls == 64) on aarch64.
+380397 s390x: __GI_strcspn() replacement needed
+n-i-bz Fix pub_tool_basics.h build issue with g++ 4.4.7.
+
+(3.13.0.RC1: 2 June 2017, vex r3386, valgrind r16434)
+(3.13.0.RC2: 9 June 2017, vex r3389, valgrind r16443)
+(3.13.0: 14 June 2017, vex r3396, valgrind r16446)
+
+
Release 3.12.0 (20 October 2016)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -119,6 +378,7 @@
303877 valgrind doesn't support compressed debuginfo sections.
345307 Warning about "still reachable" memory when using libstdc++ from gcc 5
348345 Assertion fails for negative lineno
+348924 MIPS: Load doubles through memory so the code compiles with the FPXX ABI
351282 V 3.10.1 MIPS softfloat build broken with GCC 4.9.3 / binutils 2.25.1
351692 Dumps created by valgrind are not readable by gdb (mips32 specific)
351804 Crash on generating suppressions for "printf" call on OS X 10.10
@@ -246,6 +506,8 @@
369468 Remove quadratic metapool algorithm using VG_(HT_remove_at_Iter)
370265 ISA 3.0 HW cap stuff needs updating
371128 BCD add and subtract instructions on Power BE in 32-bit mode do not work
+372195 Power PC, xxsel instruction is not always recognized
+
n-i-bz Fix incorrect (or infinite loop) unwind on RHEL7 x86 and amd64
n-i-bz massif --pages-as-heap=yes does not report peak caused by mmap+munmap
n-i-bz false positive leaks due to aspacemgr merging heap & non heap segments
diff --git a/README.solaris b/README.solaris
index 330756e..b9b122d 100644
--- a/README.solaris
+++ b/README.solaris
@@ -11,12 +11,14 @@
- A working combination of autotools is required: aclocal, autoheader,
automake and autoconf have to be found in the PATH. You should be able to
install pkg:/developer/build/automake and pkg:/developer/build/autoconf
- packages to fullfil this requirement.
+ packages to fulfil this requirement.
- System header files are required. On Solaris, these can be installed with:
# pkg install system/header
- GNU make is also required. On Solaris, this can be quickly achieved with:
$ PATH=/usr/gnu/bin:$PATH; export PATH
- For remote debugging support, working GDB is required (see below).
+- For running regression tests, GNU sed, grep, awk, diff are required.
+ This can be quickly achieved on Solaris by prepending /usr/gnu/bin to PATH.
Compilation
@@ -123,7 +125,6 @@
- Provide better error reporting for various subsyscalls.
- Implement storing of extra register state in signal frame.
- Performance comparison against other platforms.
-
- Prevent SIGPIPE when writing to a socket (coregrind/m_libcfile.c).
- Implement ticket locking for fair scheduling (--fair-sched=yes).
- Implement support in DRD and Helgrind tools for thr_join() with thread == 0.
@@ -137,6 +138,8 @@
to see this in effect. Would require awareness of syscall parameter semantics.
- Correctly print arguments of DW_CFA_ORCL_arg_loc in show_CF_instruction() when
it is implemented in libdwarf.
+- Handle a situation when guest program sets SC_CANCEL_FLG in schedctl and
+ Valgrind needs to invoke a syscall on its own.
Contacts
diff --git a/README_DEVELOPERS b/README_DEVELOPERS
index fdd70b5..ab0cf66 100644
--- a/README_DEVELOPERS
+++ b/README_DEVELOPERS
@@ -233,6 +233,45 @@
The file tests/outer_inner.supp contains suppressions for
the irrelevant or benign errors found in the inner.
+An regression test running in the inner (e.g. memcheck/tests/badrw) will
+cause the inner to report an error, which is expected and checked
+as usual when running the regtests in an outer/inner setup.
+However, the outer will often also observe an error, e.g. a jump
+using uninitialised data, or a read/write outside the bounds of a heap
+block. When the outer reports such an error, it will output the
+inner host stacktrace. To this stacktrace, it will append the
+stacktrace of the inner guest program. For example, this is an error
+reported by the outer when the inner runs the badrw regtest:
+ ==8119== Invalid read of size 2
+ ==8119== at 0x7F2EFD7AF: ???
+ ==8119== by 0x7F2C82EAF: ???
+ ==8119== by 0x7F180867F: ???
+ ==8119== by 0x40051D: main (badrw.c:5)
+ ==8119== by 0x7F180867F: ???
+ ==8119== by 0x1BFF: ???
+ ==8119== by 0x3803B7F0: _______VVVVVVVV_appended_inner_guest_stack_VVVVVVVV_______ (m_execontext.c:332)
+ ==8119== by 0x40055C: main (badrw.c:22)
+ ==8119== Address 0x55cd03c is 4 bytes before a block of size 16 alloc'd
+ ==8119== at 0x2804E26D: vgPlain_arena_malloc (m_mallocfree.c:1914)
+ ==8119== by 0x2800BAB4: vgMemCheck_new_block (mc_malloc_wrappers.c:368)
+ ==8119== by 0x2800BC87: vgMemCheck_malloc (mc_malloc_wrappers.c:403)
+ ==8119== by 0x28097EAE: do_client_request (scheduler.c:1861)
+ ==8119== by 0x28097EAE: vgPlain_scheduler (scheduler.c:1425)
+ ==8119== by 0x280A7237: thread_wrapper (syswrap-linux.c:103)
+ ==8119== by 0x280A7237: run_a_thread_NORETURN (syswrap-linux.c:156)
+ ==8119== by 0x3803B7F0: _______VVVVVVVV_appended_inner_guest_stack_VVVVVVVV_______ (m_execontext.c:332)
+ ==8119== by 0x4C294C4: malloc (vg_replace_malloc.c:298)
+ ==8119== by 0x40051D: main (badrw.c:5)
+In the above, the first stacktrace starts with the inner host stacktrace,
+which in this case is some JITted code. Such code sometimes contains IPs
+that points in the inner guest code (0x40051D: main (badrw.c:5)).
+After the separator, we have the inner guest stacktrace.
+The second stacktrace gives the stacktrace where the heap block that was
+overrun was allocated. We see it was allocated by the inner valgrind
+in the client arena (first part of the stacktrace). The second part is
+the guest stacktrace that did the allocation.
+
+
(C) Performance tests in an outer/inner setup:
To run all the performance tests with an outer cachegrind, do :
diff --git a/README_MISSING_SYSCALL_OR_IOCTL b/README_MISSING_SYSCALL_OR_IOCTL
index ab78902..24af45b 100644
--- a/README_MISSING_SYSCALL_OR_IOCTL
+++ b/README_MISSING_SYSCALL_OR_IOCTL
@@ -140,7 +140,7 @@
LINX_, LINXY, PLAX_, PLAXY.
GEN* for generic syscalls (in syswrap-generic.c), LIN* for linux
specific ones (in syswrap-linux.c) and PLA* for the platform
- dependant ones (in syswrap-$(PLATFORM)-linux.c).
+ dependent ones (in syswrap-$(PLATFORM)-linux.c).
The *XY variant if it requires a PRE() and POST() function, and
the *X_ variant if it only requires a PRE()
function.
diff --git a/VEX/auxprogs/genoffsets.c b/VEX/auxprogs/genoffsets.c
index 70f6491..1f680e4 100644
--- a/VEX/auxprogs/genoffsets.c
+++ b/VEX/auxprogs/genoffsets.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -55,7 +55,6 @@
#include "../pub/libvex_guest_s390x.h"
#include "../pub/libvex_guest_mips32.h"
#include "../pub/libvex_guest_mips64.h"
-#include "../pub/libvex_guest_tilegx.h"
#define VG_STRINGIFZ(__str) #__str
#define VG_STRINGIFY(__str) VG_STRINGIFZ(__str)
@@ -264,68 +263,6 @@
GENOFFSET(MIPS64,mips64,PC);
GENOFFSET(MIPS64,mips64,HI);
GENOFFSET(MIPS64,mips64,LO);
-
- // Tilegx
- GENOFFSET(TILEGX,tilegx,r0);
- GENOFFSET(TILEGX,tilegx,r1);
- GENOFFSET(TILEGX,tilegx,r2);
- GENOFFSET(TILEGX,tilegx,r3);
- GENOFFSET(TILEGX,tilegx,r4);
- GENOFFSET(TILEGX,tilegx,r5);
- GENOFFSET(TILEGX,tilegx,r6);
- GENOFFSET(TILEGX,tilegx,r7);
- GENOFFSET(TILEGX,tilegx,r8);
- GENOFFSET(TILEGX,tilegx,r9);
- GENOFFSET(TILEGX,tilegx,r10);
- GENOFFSET(TILEGX,tilegx,r11);
- GENOFFSET(TILEGX,tilegx,r12);
- GENOFFSET(TILEGX,tilegx,r13);
- GENOFFSET(TILEGX,tilegx,r14);
- GENOFFSET(TILEGX,tilegx,r15);
- GENOFFSET(TILEGX,tilegx,r16);
- GENOFFSET(TILEGX,tilegx,r17);
- GENOFFSET(TILEGX,tilegx,r18);
- GENOFFSET(TILEGX,tilegx,r19);
- GENOFFSET(TILEGX,tilegx,r20);
- GENOFFSET(TILEGX,tilegx,r21);
- GENOFFSET(TILEGX,tilegx,r22);
- GENOFFSET(TILEGX,tilegx,r23);
- GENOFFSET(TILEGX,tilegx,r24);
- GENOFFSET(TILEGX,tilegx,r25);
- GENOFFSET(TILEGX,tilegx,r26);
- GENOFFSET(TILEGX,tilegx,r27);
- GENOFFSET(TILEGX,tilegx,r28);
- GENOFFSET(TILEGX,tilegx,r29);
- GENOFFSET(TILEGX,tilegx,r30);
- GENOFFSET(TILEGX,tilegx,r31);
- GENOFFSET(TILEGX,tilegx,r32);
- GENOFFSET(TILEGX,tilegx,r33);
- GENOFFSET(TILEGX,tilegx,r34);
- GENOFFSET(TILEGX,tilegx,r35);
- GENOFFSET(TILEGX,tilegx,r36);
- GENOFFSET(TILEGX,tilegx,r37);
- GENOFFSET(TILEGX,tilegx,r38);
- GENOFFSET(TILEGX,tilegx,r39);
- GENOFFSET(TILEGX,tilegx,r40);
- GENOFFSET(TILEGX,tilegx,r41);
- GENOFFSET(TILEGX,tilegx,r42);
- GENOFFSET(TILEGX,tilegx,r43);
- GENOFFSET(TILEGX,tilegx,r44);
- GENOFFSET(TILEGX,tilegx,r45);
- GENOFFSET(TILEGX,tilegx,r46);
- GENOFFSET(TILEGX,tilegx,r47);
- GENOFFSET(TILEGX,tilegx,r48);
- GENOFFSET(TILEGX,tilegx,r49);
- GENOFFSET(TILEGX,tilegx,r50);
- GENOFFSET(TILEGX,tilegx,r51);
- GENOFFSET(TILEGX,tilegx,r52);
- GENOFFSET(TILEGX,tilegx,r53);
- GENOFFSET(TILEGX,tilegx,r54);
- GENOFFSET(TILEGX,tilegx,r55);
- GENOFFSET(TILEGX,tilegx,pc);
- GENOFFSET(TILEGX,tilegx,EMNOTE);
- GENOFFSET(TILEGX,tilegx,CMSTART);
- GENOFFSET(TILEGX,tilegx,NRADDR);
}
/*--------------------------------------------------------------------*/
diff --git a/VEX/priv/guest_amd64_defs.h b/VEX/priv/guest_amd64_defs.h
index ec30015..88593e6 100644
--- a/VEX/priv/guest_amd64_defs.h
+++ b/VEX/priv/guest_amd64_defs.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -48,7 +48,7 @@
/*---------------------------------------------------------*/
/* Convert one amd64 insn to IR. See the type DisOneInstrFn in
- bb_to_IR.h. */
+ guest_generic_bb_to_IR.h. */
extern
DisResult disInstr_AMD64 ( IRSB* irbb,
Bool (*resteerOkFn) ( void*, Addr ),
@@ -541,6 +541,12 @@
AMD64G_CC_OP_BLSR32, /* 59 */
AMD64G_CC_OP_BLSR64, /* 60 DEP1 = res, DEP2 = arg, NDEP = unused */
+ AMD64G_CC_OP_ADCX32, /* 61 DEP1 = argL, DEP2 = argR ^ oldCarry, .. */
+ AMD64G_CC_OP_ADCX64, /* 62 .. NDEP = old flags */
+
+ AMD64G_CC_OP_ADOX32, /* 63 DEP1 = argL, DEP2 = argR ^ oldOverflow, .. */
+ AMD64G_CC_OP_ADOX64, /* 64 .. NDEP = old flags */
+
AMD64G_CC_OP_NUMBER
};
diff --git a/VEX/priv/guest_amd64_helpers.c b/VEX/priv/guest_amd64_helpers.c
index 3a0a4c6..d69d110 100644
--- a/VEX/priv/guest_amd64_helpers.c
+++ b/VEX/priv/guest_amd64_helpers.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -560,6 +560,26 @@
/*-------------------------------------------------------------*/
+#define ACTIONS_ADX(DATA_BITS,DATA_UTYPE,FLAGNAME) \
+{ \
+ PREAMBLE(DATA_BITS); \
+ { ULong ocf; /* o or c */ \
+ ULong argL, argR, oldOC, res; \
+ oldOC = (CC_NDEP >> AMD64G_CC_SHIFT_##FLAGNAME) & 1; \
+ argL = CC_DEP1; \
+ argR = CC_DEP2 ^ oldOC; \
+ res = (argL + argR) + oldOC; \
+ if (oldOC) \
+ ocf = (DATA_UTYPE)res <= (DATA_UTYPE)argL; \
+ else \
+ ocf = (DATA_UTYPE)res < (DATA_UTYPE)argL; \
+ return (CC_NDEP & ~AMD64G_CC_MASK_##FLAGNAME) \
+ | (ocf << AMD64G_CC_SHIFT_##FLAGNAME); \
+ } \
+}
+
+/*-------------------------------------------------------------*/
+
#if PROFILE_RFLAGS
@@ -735,6 +755,12 @@
case AMD64G_CC_OP_BLSR32: ACTIONS_BLSR( 32, UInt );
case AMD64G_CC_OP_BLSR64: ACTIONS_BLSR( 64, ULong );
+ case AMD64G_CC_OP_ADCX32: ACTIONS_ADX( 32, UInt, C );
+ case AMD64G_CC_OP_ADCX64: ACTIONS_ADX( 64, ULong, C );
+
+ case AMD64G_CC_OP_ADOX32: ACTIONS_ADX( 32, UInt, O );
+ case AMD64G_CC_OP_ADOX64: ACTIONS_ADX( 64, ULong, O );
+
default:
/* shouldn't really make these calls from generated code */
vex_printf("amd64g_calculate_rflags_all_WRK(AMD64)"
@@ -1353,6 +1379,34 @@
binop(Iop_Shl64, cc_dep2, mkU8(48))));
}
+ /* 8, 9 */
+ if (isU64(cc_op, AMD64G_CC_OP_SUBW) && isU64(cond, AMD64CondS)
+ && isU64(cc_dep2, 0)) {
+ /* word sub/cmp of zero, then S --> test (dst-0 <s 0)
+ --> test dst <s 0
+ --> (ULong)dst[15]
+ This is yet another scheme by which clang figures out if the
+ top bit of a word is 1 or 0. See also LOGICB/CondS below. */
+ /* Note: isU64(cc_dep2, 0) is correct, even though this is
+ for an 16-bit comparison, since the args to the helper
+ function are always U64s. */
+ return binop(Iop_And64,
+ binop(Iop_Shr64,cc_dep1,mkU8(15)),
+ mkU64(1));
+ }
+ if (isU64(cc_op, AMD64G_CC_OP_SUBW) && isU64(cond, AMD64CondNS)
+ && isU64(cc_dep2, 0)) {
+ /* word sub/cmp of zero, then NS --> test !(dst-0 <s 0)
+ --> test !(dst <s 0)
+ --> (ULong) !dst[15]
+ */
+ return binop(Iop_Xor64,
+ binop(Iop_And64,
+ binop(Iop_Shr64,cc_dep1,mkU8(15)),
+ mkU64(1)),
+ mkU64(1));
+ }
+
/* 14, */
if (isU64(cc_op, AMD64G_CC_OP_SUBW) && isU64(cond, AMD64CondLE)) {
/* word sub/cmp, then LE (signed less than or equal)
@@ -1604,6 +1658,19 @@
mkU64(0)));
}
+ /*---------------- SHRQ ----------------*/
+
+ if (isU64(cc_op, AMD64G_CC_OP_SHRQ) && isU64(cond, AMD64CondZ)) {
+ /* SHRQ, then Z --> test dep1 == 0 */
+ return unop(Iop_1Uto64,
+ binop(Iop_CmpEQ64, cc_dep1, mkU64(0)));
+ }
+ if (isU64(cc_op, AMD64G_CC_OP_SHRQ) && isU64(cond, AMD64CondNZ)) {
+ /* SHRQ, then NZ --> test dep1 != 0 */
+ return unop(Iop_1Uto64,
+ binop(Iop_CmpNE64, cc_dep1, mkU64(0)));
+ }
+
/*---------------- SHRL ----------------*/
if (isU64(cc_op, AMD64G_CC_OP_SHRL) && isU64(cond, AMD64CondZ)) {
@@ -1612,6 +1679,12 @@
binop(Iop_CmpEQ32, unop(Iop_64to32, cc_dep1),
mkU32(0)));
}
+ if (isU64(cc_op, AMD64G_CC_OP_SHRL) && isU64(cond, AMD64CondNZ)) {
+ /* SHRL, then NZ --> test dep1 != 0 */
+ return unop(Iop_1Uto64,
+ binop(Iop_CmpNE32, unop(Iop_64to32, cc_dep1),
+ mkU32(0)));
+ }
/*---------------- COPY ----------------*/
/* This can happen, as a result of amd64 FP compares: "comisd ... ;
@@ -1732,6 +1805,20 @@
binop(Iop_And64,cc_dep1,mkU64(0xFF)),
binop(Iop_And64,cc_dep2,mkU64(0xFF))));
}
+ if (isU64(cc_op, AMD64G_CC_OP_ADDQ)) {
+ /* C after add denotes sum <u either arg */
+ return unop(Iop_1Uto64,
+ binop(Iop_CmpLT64U,
+ binop(Iop_Add64, cc_dep1, cc_dep2),
+ cc_dep1));
+ }
+ if (isU64(cc_op, AMD64G_CC_OP_ADDL)) {
+ /* C after add denotes sum <u either arg */
+ return unop(Iop_1Uto64,
+ binop(Iop_CmpLT32U,
+ unop(Iop_64to32, binop(Iop_Add64, cc_dep1, cc_dep2)),
+ unop(Iop_64to32, cc_dep1)));
+ }
if (isU64(cc_op, AMD64G_CC_OP_LOGICQ)
|| isU64(cc_op, AMD64G_CC_OP_LOGICL)
|| isU64(cc_op, AMD64G_CC_OP_LOGICW)
@@ -1852,18 +1939,17 @@
themselves are not transferred into the guest state. */
static
VexEmNote do_put_x87 ( Bool moveRegs,
- /*IN*/UChar* x87_state,
+ /*IN*/Fpu_State* x87_state,
/*OUT*/VexGuestAMD64State* vex_state )
{
Int stno, preg;
UInt tag;
ULong* vexRegs = (ULong*)(&vex_state->guest_FPREG[0]);
UChar* vexTags = (UChar*)(&vex_state->guest_FPTAG[0]);
- Fpu_State* x87 = (Fpu_State*)x87_state;
- UInt ftop = (x87->env[FP_ENV_STAT] >> 11) & 7;
- UInt tagw = x87->env[FP_ENV_TAG];
- UInt fpucw = x87->env[FP_ENV_CTRL];
- UInt c3210 = x87->env[FP_ENV_STAT] & 0x4700;
+ UInt ftop = (x87_state->env[FP_ENV_STAT] >> 11) & 7;
+ UInt tagw = x87_state->env[FP_ENV_TAG];
+ UInt fpucw = x87_state->env[FP_ENV_CTRL];
+ UInt c3210 = x87_state->env[FP_ENV_STAT] & 0x4700;
VexEmNote ew;
UInt fpround;
ULong pair;
@@ -1884,7 +1970,7 @@
} else {
/* register is non-empty */
if (moveRegs)
- convert_f80le_to_f64le( &x87->reg[10*stno],
+ convert_f80le_to_f64le( &x87_state->reg[10*stno],
(UChar*)&vexRegs[preg] );
vexTags[preg] = 1;
}
@@ -1913,23 +1999,23 @@
we can approximate it. */
static
void do_get_x87 ( /*IN*/VexGuestAMD64State* vex_state,
- /*OUT*/UChar* x87_state )
+ /*OUT*/Fpu_State* x87_state )
{
Int i, stno, preg;
UInt tagw;
ULong* vexRegs = (ULong*)(&vex_state->guest_FPREG[0]);
UChar* vexTags = (UChar*)(&vex_state->guest_FPTAG[0]);
- Fpu_State* x87 = (Fpu_State*)x87_state;
UInt ftop = vex_state->guest_FTOP;
UInt c3210 = vex_state->guest_FC3210;
for (i = 0; i < 14; i++)
- x87->env[i] = 0;
+ x87_state->env[i] = 0;
- x87->env[1] = x87->env[3] = x87->env[5] = x87->env[13] = 0xFFFF;
- x87->env[FP_ENV_STAT]
+ x87_state->env[1] = x87_state->env[3] = x87_state->env[5]
+ = x87_state->env[13] = 0xFFFF;
+ x87_state->env[FP_ENV_STAT]
= toUShort(((ftop & 7) << 11) | (c3210 & 0x4700));
- x87->env[FP_ENV_CTRL]
+ x87_state->env[FP_ENV_CTRL]
= toUShort(amd64g_create_fpucw( vex_state->guest_FPROUND ));
/* Dump the register stack in ST order. */
@@ -1940,15 +2026,15 @@
/* register is empty */
tagw |= (3 << (2*preg));
convert_f64le_to_f80le( (UChar*)&vexRegs[preg],
- &x87->reg[10*stno] );
+ &x87_state->reg[10*stno] );
} else {
/* register is full. */
tagw |= (0 << (2*preg));
convert_f64le_to_f80le( (UChar*)&vexRegs[preg],
- &x87->reg[10*stno] );
+ &x87_state->reg[10*stno] );
}
}
- x87->env[FP_ENV_TAG] = toUShort(tagw);
+ x87_state->env[FP_ENV_TAG] = toUShort(tagw);
}
@@ -1980,7 +2066,7 @@
Int r, stno;
UShort *srcS, *dstS;
- do_get_x87( gst, (UChar*)&tmp );
+ do_get_x87( gst, &tmp );
/* Now build the proper fxsave x87 image from the fsave x87 image
we just made. */
@@ -2149,7 +2235,7 @@
tmp.env[FP_ENV_TAG] = fp_tags;
/* Now write 'tmp' into the guest state. */
- VexEmNote warnX87 = do_put_x87( True/*moveRegs*/, (UChar*)&tmp, gst );
+ VexEmNote warnX87 = do_put_x87( True/*moveRegs*/, &tmp, gst );
return warnX87;
}
@@ -2353,7 +2439,7 @@
VexEmNote amd64g_dirtyhelper_FLDENV ( /*OUT*/VexGuestAMD64State* vex_state,
/*IN*/HWord x87_state)
{
- return do_put_x87( False, (UChar*)x87_state, vex_state );
+ return do_put_x87( False, (Fpu_State*)x87_state, vex_state );
}
@@ -2405,7 +2491,7 @@
void amd64g_dirtyhelper_FNSAVE ( /*IN*/VexGuestAMD64State* vex_state,
/*OUT*/HWord x87_state)
{
- do_get_x87( vex_state, (UChar*)x87_state );
+ do_get_x87( vex_state, (Fpu_State*)x87_state );
}
@@ -2459,7 +2545,7 @@
VexEmNote amd64g_dirtyhelper_FRSTOR ( /*OUT*/VexGuestAMD64State* vex_state,
/*IN*/HWord x87_state)
{
- return do_put_x87( True, (UChar*)x87_state, vex_state );
+ return do_put_x87( True, (Fpu_State*)x87_state, vex_state );
}
diff --git a/VEX/priv/guest_amd64_toIR.c b/VEX/priv/guest_amd64_toIR.c
index 2080dc0..9073e1d 100644
--- a/VEX/priv/guest_amd64_toIR.c
+++ b/VEX/priv/guest_amd64_toIR.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -1533,11 +1533,21 @@
return IRExpr_Get( ymmGuestRegLane128offset(ymmreg,laneno), Ity_V128 );
}
+static IRExpr* getYMMRegLane64F ( UInt ymmreg, Int laneno )
+{
+ return IRExpr_Get( ymmGuestRegLane64offset(ymmreg,laneno), Ity_F64 );
+}
+
static IRExpr* getYMMRegLane64 ( UInt ymmreg, Int laneno )
{
return IRExpr_Get( ymmGuestRegLane64offset(ymmreg,laneno), Ity_I64 );
}
+static IRExpr* getYMMRegLane32F ( UInt ymmreg, Int laneno )
+{
+ return IRExpr_Get( ymmGuestRegLane32offset(ymmreg,laneno), Ity_F32 );
+}
+
static IRExpr* getYMMRegLane32 ( UInt ymmreg, Int laneno )
{
return IRExpr_Get( ymmGuestRegLane32offset(ymmreg,laneno), Ity_I32 );
@@ -2111,6 +2121,54 @@
}
+/* Given ta1, ta2 and tres, compute tres = ADCX(ta1,ta2) or tres = ADOX(ta1,ta2)
+ and set flags appropriately.
+*/
+static void helper_ADCX_ADOX ( Bool isADCX, Int sz,
+ IRTemp tres, IRTemp ta1, IRTemp ta2 )
+{
+ UInt thunkOp;
+ IRType ty = szToITy(sz);
+ IRTemp oldflags = newTemp(Ity_I64);
+ IRTemp oldOC = newTemp(Ity_I64); // old O or C flag
+ IRTemp oldOCn = newTemp(ty); // old O or C flag, narrowed
+ IROp plus = mkSizedOp(ty, Iop_Add8);
+ IROp xor = mkSizedOp(ty, Iop_Xor8);
+
+ vassert(typeOfIRTemp(irsb->tyenv, tres) == ty);
+
+ switch (sz) {
+ case 8: thunkOp = isADCX ? AMD64G_CC_OP_ADCX64
+ : AMD64G_CC_OP_ADOX64; break;
+ case 4: thunkOp = isADCX ? AMD64G_CC_OP_ADCX32
+ : AMD64G_CC_OP_ADOX32; break;
+ default: vassert(0);
+ }
+
+ assign( oldflags, mk_amd64g_calculate_rflags_all() );
+
+ /* oldOC = old overflow/carry flag, 0 or 1 */
+ assign( oldOC, binop(Iop_And64,
+ binop(Iop_Shr64,
+ mkexpr(oldflags),
+ mkU8(isADCX ? AMD64G_CC_SHIFT_C
+ : AMD64G_CC_SHIFT_O)),
+ mkU64(1)) );
+
+ assign( oldOCn, narrowTo(ty, mkexpr(oldOC)) );
+
+ assign( tres, binop(plus,
+ binop(plus,mkexpr(ta1),mkexpr(ta2)),
+ mkexpr(oldOCn)) );
+
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU64(thunkOp) ) );
+ stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto64(mkexpr(ta1)) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP2, widenUto64(binop(xor, mkexpr(ta2),
+ mkexpr(oldOCn)) )) );
+ stmt( IRStmt_Put( OFFB_CC_NDEP, mkexpr(oldflags) ) );
+}
+
+
/* -------------- Helpers for disassembly printing. -------------- */
static const HChar* nameGrp1 ( Int opc_aux )
@@ -2330,6 +2388,10 @@
IRExpr* handleAddrOverrides ( const VexAbiInfo* vbi,
Prefix pfx, IRExpr* virtual )
{
+ /* --- address size override --- */
+ if (haveASO(pfx))
+ virtual = unop(Iop_32Uto64, unop(Iop_64to32, virtual));
+
/* Note that the below are hacks that relies on the assumption
that %fs or %gs are constant.
Typically, %fs is always 0x63 on linux (in the main thread, it
@@ -2357,10 +2419,6 @@
/* cs, ds, es and ss are simply ignored in 64-bit mode. */
- /* --- address size override --- */
- if (haveASO(pfx))
- virtual = unop(Iop_32Uto64, unop(Iop_64to32, virtual));
-
return virtual;
}
@@ -2884,6 +2942,10 @@
/*--- Disassembling common idioms ---*/
/*------------------------------------------------------------*/
+typedef
+ enum { WithFlagNone=2, WithFlagCarry, WithFlagCarryX, WithFlagOverX }
+ WithFlag;
+
/* Handle binary integer instructions of the form
op E, G meaning
op reg-or-mem, reg
@@ -2914,8 +2976,8 @@
static
ULong dis_op2_E_G ( const VexAbiInfo* vbi,
Prefix pfx,
- Bool addSubCarry,
- IROp op8,
+ IROp op8,
+ WithFlag flag,
Bool keep,
Int size,
Long delta0,
@@ -2930,37 +2992,63 @@
UChar rm = getUChar(delta0);
IRTemp addr = IRTemp_INVALID;
- /* addSubCarry == True indicates the intended operation is
- add-with-carry or subtract-with-borrow. */
- if (addSubCarry) {
- vassert(op8 == Iop_Add8 || op8 == Iop_Sub8);
- vassert(keep);
+ /* Stay sane -- check for valid (op8, flag, keep) combinations. */
+ switch (op8) {
+ case Iop_Add8:
+ switch (flag) {
+ case WithFlagNone: case WithFlagCarry:
+ case WithFlagCarryX: case WithFlagOverX:
+ vassert(keep);
+ break;
+ default:
+ vassert(0);
+ }
+ break;
+ case Iop_Sub8:
+ vassert(flag == WithFlagNone || flag == WithFlagCarry);
+ if (flag == WithFlagCarry) vassert(keep);
+ break;
+ case Iop_And8:
+ vassert(flag == WithFlagNone);
+ break;
+ case Iop_Or8: case Iop_Xor8:
+ vassert(flag == WithFlagNone);
+ vassert(keep);
+ break;
+ default:
+ vassert(0);
}
if (epartIsReg(rm)) {
/* Specially handle XOR reg,reg, because that doesn't really
depend on reg, and doing the obvious thing potentially
generates a spurious value check failure due to the bogus
- dependency. */
- if ((op8 == Iop_Xor8 || (op8 == Iop_Sub8 && addSubCarry))
+ dependency. Ditto SUB/SBB reg,reg. */
+ if ((op8 == Iop_Xor8 || ((op8 == Iop_Sub8) && keep))
&& offsetIRegG(size,pfx,rm) == offsetIRegE(size,pfx,rm)) {
- if (False && op8 == Iop_Sub8)
- vex_printf("vex amd64->IR: sbb %%r,%%r optimisation(1)\n");
putIRegG(size,pfx,rm, mkU(ty,0));
}
assign( dst0, getIRegG(size,pfx,rm) );
assign( src, getIRegE(size,pfx,rm) );
- if (addSubCarry && op8 == Iop_Add8) {
+ if (op8 == Iop_Add8 && flag == WithFlagCarry) {
helper_ADC( size, dst1, dst0, src,
/*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 );
putIRegG(size, pfx, rm, mkexpr(dst1));
} else
- if (addSubCarry && op8 == Iop_Sub8) {
+ if (op8 == Iop_Sub8 && flag == WithFlagCarry) {
helper_SBB( size, dst1, dst0, src,
/*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 );
putIRegG(size, pfx, rm, mkexpr(dst1));
+ } else
+ if (op8 == Iop_Add8 && flag == WithFlagCarryX) {
+ helper_ADCX_ADOX( True/*isADCX*/, size, dst1, dst0, src );
+ putIRegG(size, pfx, rm, mkexpr(dst1));
+ } else
+ if (op8 == Iop_Add8 && flag == WithFlagOverX) {
+ helper_ADCX_ADOX( False/*!isADCX*/, size, dst1, dst0, src );
+ putIRegG(size, pfx, rm, mkexpr(dst1));
} else {
assign( dst1, binop(mkSizedOp(ty,op8), mkexpr(dst0), mkexpr(src)) );
if (isAddSub(op8))
@@ -2981,15 +3069,23 @@
assign( dst0, getIRegG(size,pfx,rm) );
assign( src, loadLE(szToITy(size), mkexpr(addr)) );
- if (addSubCarry && op8 == Iop_Add8) {
+ if (op8 == Iop_Add8 && flag == WithFlagCarry) {
helper_ADC( size, dst1, dst0, src,
/*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 );
putIRegG(size, pfx, rm, mkexpr(dst1));
} else
- if (addSubCarry && op8 == Iop_Sub8) {
+ if (op8 == Iop_Sub8 && flag == WithFlagCarry) {
helper_SBB( size, dst1, dst0, src,
/*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 );
putIRegG(size, pfx, rm, mkexpr(dst1));
+ } else
+ if (op8 == Iop_Add8 && flag == WithFlagCarryX) {
+ /* normal store */
+ helper_ADCX_ADOX( True/*isADCX*/, size, dst1, dst0, src );
+ } else
+ if (op8 == Iop_Add8 && flag == WithFlagOverX) {
+ /* normal store */
+ helper_ADCX_ADOX( False/*!isADCX*/, size, dst1, dst0, src );
} else {
assign( dst1, binop(mkSizedOp(ty,op8), mkexpr(dst0), mkexpr(src)) );
if (isAddSub(op8))
@@ -3030,10 +3126,10 @@
static
ULong dis_op2_G_E ( const VexAbiInfo* vbi,
Prefix pfx,
- Bool addSubCarry,
- IROp op8,
+ IROp op8,
+ WithFlag flag,
Bool keep,
- Int size,
+ Int size,
Long delta0,
const HChar* t_amd64opc )
{
@@ -3046,19 +3142,33 @@
UChar rm = getUChar(delta0);
IRTemp addr = IRTemp_INVALID;
- /* addSubCarry == True indicates the intended operation is
- add-with-carry or subtract-with-borrow. */
- if (addSubCarry) {
- vassert(op8 == Iop_Add8 || op8 == Iop_Sub8);
- vassert(keep);
+ /* Stay sane -- check for valid (op8, flag, keep) combinations. */
+ switch (op8) {
+ case Iop_Add8:
+ vassert(flag == WithFlagNone || flag == WithFlagCarry);
+ vassert(keep);
+ break;
+ case Iop_Sub8:
+ vassert(flag == WithFlagNone || flag == WithFlagCarry);
+ if (flag == WithFlagCarry) vassert(keep);
+ break;
+ case Iop_And8: case Iop_Or8: case Iop_Xor8:
+ vassert(flag == WithFlagNone);
+ vassert(keep);
+ break;
+ default:
+ vassert(0);
}
+ /* flag != WithFlagNone is only allowed for Add and Sub and indicates the
+ intended operation is add-with-carry or subtract-with-borrow. */
+
if (epartIsReg(rm)) {
/* Specially handle XOR reg,reg, because that doesn't really
depend on reg, and doing the obvious thing potentially
generates a spurious value check failure due to the bogus
- dependency. Ditto SBB reg,reg. */
- if ((op8 == Iop_Xor8 || (op8 == Iop_Sub8 && addSubCarry))
+ dependency. Ditto SUB/SBB reg,reg. */
+ if ((op8 == Iop_Xor8 || ((op8 == Iop_Sub8) && keep))
&& offsetIRegG(size,pfx,rm) == offsetIRegE(size,pfx,rm)) {
putIRegE(size,pfx,rm, mkU(ty,0));
}
@@ -3066,12 +3176,12 @@
assign(dst0, getIRegE(size,pfx,rm));
assign(src, getIRegG(size,pfx,rm));
- if (addSubCarry && op8 == Iop_Add8) {
+ if (op8 == Iop_Add8 && flag == WithFlagCarry) {
helper_ADC( size, dst1, dst0, src,
/*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 );
putIRegE(size, pfx, rm, mkexpr(dst1));
} else
- if (addSubCarry && op8 == Iop_Sub8) {
+ if (op8 == Iop_Sub8 && flag == WithFlagCarry) {
helper_SBB( size, dst1, dst0, src,
/*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 );
putIRegE(size, pfx, rm, mkexpr(dst1));
@@ -3097,7 +3207,7 @@
assign(dst0, loadLE(ty,mkexpr(addr)));
assign(src, getIRegG(size,pfx,rm));
- if (addSubCarry && op8 == Iop_Add8) {
+ if (op8 == Iop_Add8 && flag == WithFlagCarry) {
if (haveLOCK(pfx)) {
/* cas-style store */
helper_ADC( size, dst1, dst0, src,
@@ -3108,7 +3218,7 @@
/*store*/addr, IRTemp_INVALID, 0 );
}
} else
- if (addSubCarry && op8 == Iop_Sub8) {
+ if (op8 == Iop_Sub8 && flag == WithFlagCarry) {
if (haveLOCK(pfx)) {
/* cas-style store */
helper_SBB( size, dst1, dst0, src,
@@ -5214,7 +5324,7 @@
0/*regparms*/,
"amd64g_dirtyhelper_FINIT",
&amd64g_dirtyhelper_FINIT,
- mkIRExprVec_1( IRExpr_BBPTR() )
+ mkIRExprVec_1( IRExpr_GSPTR() )
);
/* declare we're writing guest state */
@@ -5584,7 +5694,7 @@
0/*regparms*/,
"amd64g_dirtyhelper_FLDENV",
&amd64g_dirtyhelper_FLDENV,
- mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) )
+ mkIRExprVec_2( IRExpr_GSPTR(), mkexpr(addr) )
);
d->tmp = w64;
/* declare we're reading memory */
@@ -5681,7 +5791,7 @@
0/*regparms*/,
"amd64g_dirtyhelper_FSTENV",
&amd64g_dirtyhelper_FSTENV,
- mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) )
+ mkIRExprVec_2( IRExpr_GSPTR(), mkexpr(addr) )
);
/* declare we're writing memory */
d->mFx = Ifx_Write;
@@ -6551,7 +6661,7 @@
0/*regparms*/,
"amd64g_dirtyhelper_FRSTOR",
&amd64g_dirtyhelper_FRSTOR,
- mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) )
+ mkIRExprVec_2( IRExpr_GSPTR(), mkexpr(addr) )
);
d->mSize = 108;
}
@@ -6632,7 +6742,7 @@
0/*regparms*/,
"amd64g_dirtyhelper_FNSAVE",
&amd64g_dirtyhelper_FNSAVE,
- mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) )
+ mkIRExprVec_2( IRExpr_GSPTR(), mkexpr(addr) )
);
d->mSize = 108;
}
@@ -8105,18 +8215,31 @@
}
}
- /* Side effect done; now get selected bit into Carry flag */
- /* Flags: C=selected bit, O,S,Z,A,P undefined, so are set to zero. */
+ /* Side effect done; now get selected bit into Carry flag. The Intel docs
+ (as of 2015, at least) say that C holds the result, Z is unchanged, and
+ O,S,A and P are undefined. However, on Skylake it appears that O,S,A,P
+ are also unchanged, so let's do that. */
+ const ULong maskC = AMD64G_CC_MASK_C;
+ const ULong maskOSZAP = AMD64G_CC_MASK_O | AMD64G_CC_MASK_S
+ | AMD64G_CC_MASK_Z | AMD64G_CC_MASK_A
+ | AMD64G_CC_MASK_P;
+
+ IRTemp old_rflags = newTemp(Ity_I64);
+ assign(old_rflags, mk_amd64g_calculate_rflags_all());
+
+ IRTemp new_rflags = newTemp(Ity_I64);
+ assign(new_rflags,
+ binop(Iop_Or64,
+ binop(Iop_And64, mkexpr(old_rflags), mkU64(maskOSZAP)),
+ binop(Iop_And64,
+ binop(Iop_Shr64,
+ unop(Iop_8Uto64, mkexpr(t_fetched)),
+ mkexpr(t_bitno2)),
+ mkU64(maskC))));
+
stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) ));
stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
- stmt( IRStmt_Put(
- OFFB_CC_DEP1,
- binop(Iop_And64,
- binop(Iop_Shr64,
- unop(Iop_8Uto64, mkexpr(t_fetched)),
- mkexpr(t_bitno2)),
- mkU64(1)))
- );
+ stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(new_rflags) ));
/* Set NDEP even though it isn't used. This makes redundant-PUT
elimination of previous stores to this field work better. */
stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) ));
@@ -11598,7 +11721,7 @@
0/*regparms*/,
"amd64g_dirtyhelper_XSAVE_COMPONENT_0",
&amd64g_dirtyhelper_XSAVE_COMPONENT_0,
- mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) )
+ mkIRExprVec_2( IRExpr_GSPTR(), mkexpr(addr) )
);
d0->guard = binop(Iop_CmpEQ64, binop(Iop_And64, mkexpr(rfbm), mkU64(1)),
mkU64(1));
@@ -11658,7 +11781,7 @@
0/*regparms*/,
"amd64g_dirtyhelper_XSAVE_COMPONENT_1_EXCLUDING_XMMREGS",
&amd64g_dirtyhelper_XSAVE_COMPONENT_1_EXCLUDING_XMMREGS,
- mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) )
+ mkIRExprVec_2( IRExpr_GSPTR(), mkexpr(addr) )
);
d1->guard = guard_1or2;
@@ -11821,7 +11944,7 @@
0/*regparms*/,
"amd64g_dirtyhelper_XRSTOR_COMPONENT_0",
&amd64g_dirtyhelper_XRSTOR_COMPONENT_0,
- mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) )
+ mkIRExprVec_2( IRExpr_GSPTR(), mkexpr(addr) )
);
d0->guard = binop(Iop_CmpNE64, mkexpr(restore_0), mkU64(0));
@@ -11902,7 +12025,7 @@
0/*regparms*/,
"amd64g_dirtyhelper_XRSTOR_COMPONENT_1_EXCLUDING_XMMREGS",
&amd64g_dirtyhelper_XRSTOR_COMPONENT_1_EXCLUDING_XMMREGS,
- mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) )
+ mkIRExprVec_2( IRExpr_GSPTR(), mkexpr(addr) )
) ;
d1->guard = restore_1or2e;
@@ -17681,7 +17804,7 @@
IRExpr* gstOffLe = mkU64(gstOffL);
IRExpr* gstOffRe = mkU64(gstOffR);
IRExpr** args
- = mkIRExprVec_5( IRExpr_BBPTR(), opc4, gstOffDe, gstOffLe, gstOffRe );
+ = mkIRExprVec_5( IRExpr_GSPTR(), opc4, gstOffDe, gstOffLe, gstOffRe );
IRDirty* d = unsafeIRDirty_0_N( 0/*regparms*/, nm, fn, args );
/* It's not really a dirty call, but we can't use the clean helper
@@ -17771,7 +17894,7 @@
IRExpr* gstOffLe = mkU64(gstOffL);
IRExpr* gstOffRe = mkU64(gstOffR);
IRExpr** args
- = mkIRExprVec_4( IRExpr_BBPTR(), imme, gstOffLe, gstOffRe );
+ = mkIRExprVec_4( IRExpr_GSPTR(), imme, gstOffLe, gstOffRe );
IRDirty* d = unsafeIRDirty_0_N( 0/*regparms*/, nm, fn, args );
/* It's not really a dirty call, but we can't use the clean helper
@@ -18673,7 +18796,7 @@
switch (imm) {
case 0x00: case 0x02:
case 0x08: case 0x0A: case 0x0C: case 0x0E:
- case 0x12: case 0x14:
+ case 0x10: case 0x12: case 0x14:
case 0x18: case 0x1A:
case 0x30: case 0x34:
case 0x38: case 0x3A:
@@ -18711,7 +18834,7 @@
IRExpr* edxIN = isISTRx ? mkU64(0) : getIRegRDX(8);
IRExpr* eaxIN = isISTRx ? mkU64(0) : getIRegRAX(8);
IRExpr** args
- = mkIRExprVec_6( IRExpr_BBPTR(),
+ = mkIRExprVec_6( IRExpr_GSPTR(),
opc4_and_imm, gstOffLe, gstOffRe, edxIN, eaxIN );
IRTemp resT = newTemp(Ity_I64);
@@ -19866,20 +19989,20 @@
case 0x00: /* ADD Gb,Eb */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Add8, True, 1, delta, "add" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Add8, WithFlagNone, True, 1, delta, "add" );
return delta;
case 0x01: /* ADD Gv,Ev */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Add8, True, sz, delta, "add" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Add8, WithFlagNone, True, sz, delta, "add" );
return delta;
case 0x02: /* ADD Eb,Gb */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Add8, True, 1, delta, "add" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Add8, WithFlagNone, True, 1, delta, "add" );
return delta;
case 0x03: /* ADD Ev,Gv */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Add8, True, sz, delta, "add" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Add8, WithFlagNone, True, sz, delta, "add" );
return delta;
case 0x04: /* ADD Ib, AL */
@@ -19893,20 +20016,20 @@
case 0x08: /* OR Gb,Eb */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Or8, True, 1, delta, "or" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Or8, WithFlagNone, True, 1, delta, "or" );
return delta;
case 0x09: /* OR Gv,Ev */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Or8, True, sz, delta, "or" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Or8, WithFlagNone, True, sz, delta, "or" );
return delta;
case 0x0A: /* OR Eb,Gb */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Or8, True, 1, delta, "or" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Or8, WithFlagNone, True, 1, delta, "or" );
return delta;
case 0x0B: /* OR Ev,Gv */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Or8, True, sz, delta, "or" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Or8, WithFlagNone, True, sz, delta, "or" );
return delta;
case 0x0C: /* OR Ib, AL */
@@ -19920,20 +20043,20 @@
case 0x10: /* ADC Gb,Eb */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, True, Iop_Add8, True, 1, delta, "adc" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Add8, WithFlagCarry, True, 1, delta, "adc" );
return delta;
case 0x11: /* ADC Gv,Ev */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, True, Iop_Add8, True, sz, delta, "adc" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Add8, WithFlagCarry, True, sz, delta, "adc" );
return delta;
case 0x12: /* ADC Eb,Gb */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, True, Iop_Add8, True, 1, delta, "adc" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Add8, WithFlagCarry, True, 1, delta, "adc" );
return delta;
case 0x13: /* ADC Ev,Gv */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, True, Iop_Add8, True, sz, delta, "adc" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Add8, WithFlagCarry, True, sz, delta, "adc" );
return delta;
case 0x14: /* ADC Ib, AL */
@@ -19947,20 +20070,20 @@
case 0x18: /* SBB Gb,Eb */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, True, Iop_Sub8, True, 1, delta, "sbb" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Sub8, WithFlagCarry, True, 1, delta, "sbb" );
return delta;
case 0x19: /* SBB Gv,Ev */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, True, Iop_Sub8, True, sz, delta, "sbb" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Sub8, WithFlagCarry, True, sz, delta, "sbb" );
return delta;
case 0x1A: /* SBB Eb,Gb */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, True, Iop_Sub8, True, 1, delta, "sbb" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Sub8, WithFlagCarry, True, 1, delta, "sbb" );
return delta;
case 0x1B: /* SBB Ev,Gv */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, True, Iop_Sub8, True, sz, delta, "sbb" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Sub8, WithFlagCarry, True, sz, delta, "sbb" );
return delta;
case 0x1C: /* SBB Ib, AL */
@@ -19974,20 +20097,20 @@
case 0x20: /* AND Gb,Eb */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_And8, True, 1, delta, "and" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_And8, WithFlagNone, True, 1, delta, "and" );
return delta;
case 0x21: /* AND Gv,Ev */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_And8, True, sz, delta, "and" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_And8, WithFlagNone, True, sz, delta, "and" );
return delta;
case 0x22: /* AND Eb,Gb */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_And8, True, 1, delta, "and" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_And8, WithFlagNone, True, 1, delta, "and" );
return delta;
case 0x23: /* AND Ev,Gv */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_And8, True, sz, delta, "and" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_And8, WithFlagNone, True, sz, delta, "and" );
return delta;
case 0x24: /* AND Ib, AL */
@@ -20001,20 +20124,20 @@
case 0x28: /* SUB Gb,Eb */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Sub8, True, 1, delta, "sub" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Sub8, WithFlagNone, True, 1, delta, "sub" );
return delta;
case 0x29: /* SUB Gv,Ev */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Sub8, True, sz, delta, "sub" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Sub8, WithFlagNone, True, sz, delta, "sub" );
return delta;
case 0x2A: /* SUB Eb,Gb */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Sub8, True, 1, delta, "sub" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Sub8, WithFlagNone, True, 1, delta, "sub" );
return delta;
case 0x2B: /* SUB Ev,Gv */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Sub8, True, sz, delta, "sub" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Sub8, WithFlagNone, True, sz, delta, "sub" );
return delta;
case 0x2C: /* SUB Ib, AL */
@@ -20028,20 +20151,20 @@
case 0x30: /* XOR Gb,Eb */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Xor8, True, 1, delta, "xor" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Xor8, WithFlagNone, True, 1, delta, "xor" );
return delta;
case 0x31: /* XOR Gv,Ev */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Xor8, True, sz, delta, "xor" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Xor8, WithFlagNone, True, sz, delta, "xor" );
return delta;
case 0x32: /* XOR Eb,Gb */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Xor8, True, 1, delta, "xor" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Xor8, WithFlagNone, True, 1, delta, "xor" );
return delta;
case 0x33: /* XOR Ev,Gv */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Xor8, True, sz, delta, "xor" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Xor8, WithFlagNone, True, sz, delta, "xor" );
return delta;
case 0x34: /* XOR Ib, AL */
@@ -20055,20 +20178,20 @@
case 0x38: /* CMP Gb,Eb */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Sub8, False, 1, delta, "cmp" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Sub8, WithFlagNone, False, 1, delta, "cmp" );
return delta;
case 0x39: /* CMP Gv,Ev */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Sub8, False, sz, delta, "cmp" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Sub8, WithFlagNone, False, sz, delta, "cmp" );
return delta;
case 0x3A: /* CMP Eb,Gb */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Sub8, False, 1, delta, "cmp" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Sub8, WithFlagNone, False, 1, delta, "cmp" );
return delta;
case 0x3B: /* CMP Ev,Gv */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Sub8, False, sz, delta, "cmp" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Sub8, WithFlagNone, False, sz, delta, "cmp" );
return delta;
case 0x3C: /* CMP Ib, AL */
@@ -20313,12 +20436,14 @@
case 0x84: /* TEST Eb,Gb */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_And8, False, 1, delta, "test" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_And8, WithFlagNone, False,
+ 1, delta, "test" );
return delta;
case 0x85: /* TEST Ev,Gv */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_And8, False, sz, delta, "test" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_And8, WithFlagNone, False,
+ sz, delta, "test" );
return delta;
/* XCHG reg,mem automatically asserts LOCK# even without a LOCK
@@ -21645,7 +21770,7 @@
void* fAddr = &amd64g_dirtyhelper_RDTSCP;
IRDirty* d
= unsafeIRDirty_0_N ( 0/*regparms*/,
- fName, fAddr, mkIRExprVec_1(IRExpr_BBPTR()) );
+ fName, fAddr, mkIRExprVec_1(IRExpr_GSPTR()) );
/* declare guest state effects */
d->nFxState = 3;
vex_bzero(&d->fxState, sizeof(d->fxState));
@@ -21705,13 +21830,22 @@
}
return delta;
+ case 0x19:
+ case 0x1C:
+ case 0x1D:
+ case 0x1E:
case 0x1F:
- if (haveF2orF3(pfx)) goto decode_failure;
+ // Intel CET instructions can have any prefixes before NOPs
+ // and can use any ModRM, SIB and disp
modrm = getUChar(delta);
- if (epartIsReg(modrm)) goto decode_failure;
- addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
- delta += alen;
- DIP("nop%c %s\n", nameISize(sz), dis_buf);
+ if (epartIsReg(modrm)) {
+ delta += 1;
+ DIP("nop%c\n", nameISize(sz));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ DIP("nop%c %s\n", nameISize(sz), dis_buf);
+ }
return delta;
case 0x31: { /* RDTSC */
@@ -21966,7 +22100,7 @@
vassert(fName); vassert(fAddr);
d = unsafeIRDirty_0_N ( 0/*regparms*/,
- fName, fAddr, mkIRExprVec_1(IRExpr_BBPTR()) );
+ fName, fAddr, mkIRExprVec_1(IRExpr_GSPTR()) );
/* declare guest state effects */
d->nFxState = 4;
vex_bzero(&d->fxState, sizeof(d->fxState));
@@ -22537,7 +22671,6 @@
default:
break;
-
}
/* =-=-=-=-=-=-=-=-= SSSE3ery =-=-=-=-=-=-=-=-= */
@@ -22560,6 +22693,40 @@
return delta;
}
+ /* Ignore previous decode attempts and restart from the beginning of
+ the instruction. */
+ delta = deltaIN;
+ opc = getUChar(delta);
+ delta++;
+
+ switch (opc) {
+
+ case 0xF6: {
+ /* 66 0F 38 F6 = ADCX r32/64(G), m32/64(E) */
+ /* F3 0F 38 F6 = ADOX r32/64(G), m32/64(E) */
+ /* These were introduced in Broadwell. Gate them on AVX so as to at
+ least reject them on earlier guests. Has no host requirements. */
+ if (have66noF2noF3(pfx) && (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX)) {
+ if (sz == 2) {
+ sz = 4; /* 66 prefix but operand size is 4/8 */
+ }
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Add8, WithFlagCarryX, True,
+ sz, delta, "adcx" );
+ return delta;
+ }
+ if (haveF3no66noF2(pfx) && (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX)) {
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Add8, WithFlagOverX, True,
+ sz, delta, "adox" );
+ return delta;
+ }
+ /* else fall through */
+ break;
+ }
+
+ default:
+ break;
+ }
+
/*decode_failure:*/
return deltaIN; /* fail */
}
@@ -27545,11 +27712,7 @@
UInt rV = getVexNvvvv(pfx);
Bool scalar = (opc & 0xF) > 7 && (opc & 1);
IRType ty = getRexW(pfx) ? Ity_F64 : Ity_F32;
- IRType vty = scalar ? ty : getVexL(pfx) ? Ity_V256 : Ity_V128;
- IRTemp vX = newTemp(vty);
- IRTemp vY = newTemp(vty);
- IRTemp vZ = newTemp(vty);
- IRExpr *x[8], *y[8], *z[8];
+ IRType vty = scalar ? ty : (getVexL(pfx) ? Ity_V256 : Ity_V128);
IRTemp addr = IRTemp_INVALID;
HChar dis_buf[50];
Int alen = 0;
@@ -27559,76 +27722,60 @@
Bool negateRes = False;
Bool negateZeven = False;
Bool negateZodd = False;
- Int i, j;
- Int count;
- static IROp ops[] = { Iop_V256to64_0, Iop_V256to64_1,
- Iop_V256to64_2, Iop_V256to64_3,
- Iop_V128to64, Iop_V128HIto64 };
+ UInt count = 0;
switch (opc & 0xF) {
- case 0x6:
- name = "addsub";
- negateZeven = True;
- break;
- case 0x7:
- name = "subadd";
- negateZodd = True;
- break;
- case 0x8:
- case 0x9:
- name = "add";
- break;
- case 0xA:
- case 0xB:
- name = "sub";
- negateZeven = True;
- negateZodd = True;
- break;
- case 0xC:
- case 0xD:
- name = "add";
- negateRes = True;
- negateZeven = True;
- negateZodd = True;
- break;
- case 0xE:
- case 0xF:
- name = "sub";
- negateRes = True;
- break;
- default:
- vpanic("dis_FMA(amd64)");
- break;
+ case 0x6: name = "addsub"; negateZeven = True; break;
+ case 0x7: name = "subadd"; negateZodd = True; break;
+ case 0x8:
+ case 0x9: name = "add"; break;
+ case 0xA:
+ case 0xB: name = "sub"; negateZeven = True; negateZodd = True;
+ break;
+ case 0xC:
+ case 0xD: name = "add"; negateRes = True; negateZeven = True;
+ negateZodd = True; break;
+ case 0xE:
+ case 0xF: name = "sub"; negateRes = True; break;
+ default: vpanic("dis_FMA(amd64)"); break;
}
switch (opc & 0xF0) {
- case 0x90: order = "132"; break;
- case 0xA0: order = "213"; break;
- case 0xB0: order = "231"; break;
- default: vpanic("dis_FMA(amd64)"); break;
+ case 0x90: order = "132"; break;
+ case 0xA0: order = "213"; break;
+ case 0xB0: order = "231"; break;
+ default: vpanic("dis_FMA(amd64)"); break;
}
- if (scalar)
- suffix = ty == Ity_F64 ? "sd" : "ss";
- else
- suffix = ty == Ity_F64 ? "pd" : "ps";
-
if (scalar) {
- assign( vX, ty == Ity_F64
- ? getXMMRegLane64F(rG, 0) : getXMMRegLane32F(rG, 0) );
- assign( vZ, ty == Ity_F64
- ? getXMMRegLane64F(rV, 0) : getXMMRegLane32F(rV, 0) );
+ suffix = ty == Ity_F64 ? "sd" : "ss";
} else {
- assign( vX, vty == Ity_V256 ? getYMMReg(rG) : getXMMReg(rG) );
- assign( vZ, vty == Ity_V256 ? getYMMReg(rV) : getXMMReg(rV) );
+ suffix = ty == Ity_F64 ? "pd" : "ps";
+ }
+
+ // Figure out |count| (the number of elements) by considering |vty| and |ty|.
+ count = sizeofIRType(vty) / sizeofIRType(ty);
+ vassert(count == 1 || count == 2 || count == 4 || count == 8);
+
+ // Fetch operands into the first |count| elements of |sX|, |sY| and |sZ|.
+ UInt i;
+ IRExpr *sX[8], *sY[8], *sZ[8], *res[8];
+ for (i = 0; i < 8; i++) sX[i] = sY[i] = sZ[i] = res[i] = NULL;
+
+ IRExpr* (*getYMMRegLane)(UInt,Int)
+ = ty == Ity_F32 ? getYMMRegLane32F : getYMMRegLane64F;
+ void (*putYMMRegLane)(UInt,Int,IRExpr*)
+ = ty == Ity_F32 ? putYMMRegLane32F : putYMMRegLane64F;
+
+ for (i = 0; i < count; i++) {
+ sX[i] = getYMMRegLane(rG, i);
+ sZ[i] = getYMMRegLane(rV, i);
}
if (epartIsReg(modrm)) {
UInt rE = eregOfRexRM(pfx, modrm);
delta += 1;
- if (scalar)
- assign( vY, ty == Ity_F64
- ? getXMMRegLane64F(rE, 0) : getXMMRegLane32F(rE, 0) );
- else
- assign( vY, vty == Ity_V256 ? getYMMReg(rE) : getXMMReg(rE) );
+ for (i = 0; i < count; i++) {
+ sY[i] = getYMMRegLane(rE, i);
+ }
if (vty == Ity_V256) {
DIP("vf%sm%s%s%s %s,%s,%s\n", negateRes ? "n" : "",
name, order, suffix, nameYMMReg(rE), nameYMMReg(rV),
@@ -27641,7 +27788,10 @@
} else {
addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
delta += alen;
- assign(vY, loadLE(vty, mkexpr(addr)));
+ for (i = 0; i < count; i++) {
+ sY[i] = loadLE(ty, binop(Iop_Add64, mkexpr(addr),
+ mkU64(i * sizeofIRType(ty))));
+ }
if (vty == Ity_V256) {
DIP("vf%sm%s%s%s %s,%s,%s\n", negateRes ? "n" : "",
name, order, suffix, dis_buf, nameYMMReg(rV),
@@ -27653,73 +27803,50 @@
}
}
- /* vX/vY/vZ now in 132 order. If it is different order, swap the
- arguments. */
+ /* vX/vY/vZ are now in 132 order. If the instruction requires a different
+ order, swap them around. */
+
+# define COPY_ARR(_dst, _src) \
+ do { for (int j = 0; j < 8; j++) { _dst[j] = _src[j]; } } while (0)
+
if ((opc & 0xF0) != 0x90) {
- IRTemp tem = vX;
+ IRExpr* temp[8];
+ COPY_ARR(temp, sX);
if ((opc & 0xF0) == 0xA0) {
- vX = vZ;
- vZ = vY;
- vY = tem;
+ COPY_ARR(sX, sZ);
+ COPY_ARR(sZ, sY);
+ COPY_ARR(sY, temp);
} else {
- vX = vZ;
- vZ = tem;
+ COPY_ARR(sX, sZ);
+ COPY_ARR(sZ, temp);
}
}
- if (scalar) {
- count = 1;
- x[0] = mkexpr(vX);
- y[0] = mkexpr(vY);
- z[0] = mkexpr(vZ);
- } else if (ty == Ity_F32) {
- count = vty == Ity_V256 ? 8 : 4;
- j = vty == Ity_V256 ? 0 : 4;
- for (i = 0; i < count; i += 2) {
- IRTemp tem = newTemp(Ity_I64);
- assign(tem, unop(ops[i / 2 + j], mkexpr(vX)));
- x[i] = unop(Iop_64to32, mkexpr(tem));
- x[i + 1] = unop(Iop_64HIto32, mkexpr(tem));
- tem = newTemp(Ity_I64);
- assign(tem, unop(ops[i / 2 + j], mkexpr(vY)));
- y[i] = unop(Iop_64to32, mkexpr(tem));
- y[i + 1] = unop(Iop_64HIto32, mkexpr(tem));
- tem = newTemp(Ity_I64);
- assign(tem, unop(ops[i / 2 + j], mkexpr(vZ)));
- z[i] = unop(Iop_64to32, mkexpr(tem));
- z[i + 1] = unop(Iop_64HIto32, mkexpr(tem));
- }
- } else {
- count = vty == Ity_V256 ? 4 : 2;
- j = vty == Ity_V256 ? 0 : 4;
- for (i = 0; i < count; i++) {
- x[i] = unop(ops[i + j], mkexpr(vX));
- y[i] = unop(ops[i + j], mkexpr(vY));
- z[i] = unop(ops[i + j], mkexpr(vZ));
- }
- }
- if (!scalar)
- for (i = 0; i < count; i++) {
- IROp op = ty == Ity_F64
- ? Iop_ReinterpI64asF64 : Iop_ReinterpI32asF32;
- x[i] = unop(op, x[i]);
- y[i] = unop(op, y[i]);
- z[i] = unop(op, z[i]);
- }
+# undef COPY_ARR
+
for (i = 0; i < count; i++) {
- if ((i & 1) ? negateZodd : negateZeven)
- z[i] = unop(ty == Ity_F64 ? Iop_NegF64 : Iop_NegF32, z[i]);
- x[i] = IRExpr_Qop(ty == Ity_F64 ? Iop_MAddF64 : Iop_MAddF32,
- get_FAKE_roundingmode(), x[i], y[i], z[i]);
- if (negateRes)
- x[i] = unop(ty == Ity_F64 ? Iop_NegF64 : Iop_NegF32, x[i]);
- if (ty == Ity_F64)
- putYMMRegLane64F( rG, i, x[i] );
- else
- putYMMRegLane32F( rG, i, x[i] );
+ IROp opNEG = ty == Ity_F64 ? Iop_NegF64 : Iop_NegF32;
+ if ((i & 1) ? negateZodd : negateZeven) {
+ sZ[i] = unop(opNEG, sZ[i]);
+ }
+ res[i] = IRExpr_Qop(ty == Ity_F64 ? Iop_MAddF64 : Iop_MAddF32,
+ get_FAKE_roundingmode(), sX[i], sY[i], sZ[i]);
+ if (negateRes) {
+ res[i] = unop(opNEG, res[i]);
+ }
}
- if (vty != Ity_V256)
- putYMMRegLane128( rG, 1, mkV128(0) );
+
+ for (i = 0; i < count; i++) {
+ putYMMRegLane(rG, i, res[i]);
+ }
+
+ switch (vty) {
+ case Ity_F32: putYMMRegLane32(rG, 1, mkU32(0)); /*fallthru*/
+ case Ity_F64: putYMMRegLane64(rG, 1, mkU64(0)); /*fallthru*/
+ case Ity_V128: putYMMRegLane128(rG, 1, mkV128(0)); /*fallthru*/
+ case Ity_V256: break;
+ default: vassert(0);
+ }
return delta;
}
@@ -28182,6 +28309,7 @@
)
);
*uses_vvvv = True;
+ dres->hint = Dis_HintVerbose;
goto decode_success;
}
break;
@@ -29646,6 +29774,7 @@
if (have66noF2noF3(pfx)) {
delta = dis_FMA( vbi, pfx, delta, opc );
*uses_vvvv = True;
+ dres->hint = Dis_HintVerbose;
goto decode_success;
}
break;
@@ -31774,13 +31903,18 @@
/* else fall though; dis_PCMPxSTRx failed to decode it */
}
break;
+
case 0x5C ... 0x5F:
case 0x68 ... 0x6F:
case 0x78 ... 0x7F:
+ /* FIXME: list the instructions decoded here */
if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
Long delta0 = delta;
delta = dis_FMA4( pfx, delta, opc, uses_vvvv, vbi );
- if (delta > delta0) goto decode_success;
+ if (delta > delta0) {
+ dres->hint = Dis_HintVerbose;
+ goto decode_success;
+ }
/* else fall though; dis_FMA4 failed to decode it */
}
break;
@@ -31893,6 +32027,7 @@
dres.len = 0;
dres.continueAt = 0;
dres.jk_StopHere = Ijk_INVALID;
+ dres.hint = Dis_HintNone;
*expect_CAS = False;
vassert(guest_RIP_next_assumed == 0);
diff --git a/VEX/priv/guest_arm64_defs.h b/VEX/priv/guest_arm64_defs.h
index ad1ab96..b28f326 100644
--- a/VEX/priv/guest_arm64_defs.h
+++ b/VEX/priv/guest_arm64_defs.h
@@ -6,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2013-2015 OpenWorks
+ Copyright (C) 2013-2017 OpenWorks
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -38,7 +38,7 @@
/*---------------------------------------------------------*/
/* Convert one ARM64 insn to IR. See the type DisOneInstrFn in
- bb_to_IR.h. */
+ guest_generic_bb_to_IR.h. */
extern
DisResult disInstr_ARM64 ( IRSB* irbb,
Bool (*resteerOkFn) ( void*, Addr ),
@@ -124,6 +124,8 @@
extern ULong arm64g_dirtyhelper_MRS_CNTVCT_EL0 ( void );
+extern ULong arm64g_dirtyhelper_MRS_CNTFRQ_EL0 ( void );
+
extern void arm64g_dirtyhelper_PMULLQ ( /*OUT*/V128* res,
ULong arg1, ULong arg2 );
diff --git a/VEX/priv/guest_arm64_helpers.c b/VEX/priv/guest_arm64_helpers.c
index 5edeef1..10065d5 100644
--- a/VEX/priv/guest_arm64_helpers.c
+++ b/VEX/priv/guest_arm64_helpers.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2013-2015 OpenWorks
+ Copyright (C) 2013-2017 OpenWorks
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -774,6 +774,21 @@
}
+/* CALLED FROM GENERATED CODE */
+/* DIRTY HELPER (non-referentially-transparent) */
+/* Horrible hack. On non-arm64 platforms, return 0. */
+ULong arm64g_dirtyhelper_MRS_CNTFRQ_EL0 ( void )
+{
+# if defined(__aarch64__) && !defined(__arm__)
+ ULong w = 0x5555555555555555ULL; /* overwritten */
+ __asm__ __volatile__("mrs %0, cntfrq_el0" : "=r"(w));
+ return w;
+# else
+ return 0ULL;
+# endif
+}
+
+
void arm64g_dirtyhelper_PMULLQ ( /*OUT*/V128* res, ULong arg1, ULong arg2 )
{
/* This doesn't need to be a dirty helper, except for the fact that
diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c
index e527447..e5af388 100644
--- a/VEX/priv/guest_arm64_toIR.c
+++ b/VEX/priv/guest_arm64_toIR.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2013-2015 OpenWorks
+ Copyright (C) 2013-2017 OpenWorks
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -1147,6 +1147,10 @@
#define OFFB_CMSTART offsetof(VexGuestARM64State,guest_CMSTART)
#define OFFB_CMLEN offsetof(VexGuestARM64State,guest_CMLEN)
+#define OFFB_LLSC_SIZE offsetof(VexGuestARM64State,guest_LLSC_SIZE)
+#define OFFB_LLSC_ADDR offsetof(VexGuestARM64State,guest_LLSC_ADDR)
+#define OFFB_LLSC_DATA offsetof(VexGuestARM64State,guest_LLSC_DATA)
+
/* ---------------- Integer registers ---------------- */
@@ -4702,7 +4706,9 @@
static
-Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn)
+Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn,
+ const VexAbiInfo* abiinfo
+)
{
# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
@@ -6457,6 +6463,32 @@
sz 001000 000 s 0 11111 n t STX{R,RH,RB} Ws, Rt, [Xn|SP]
sz 001000 000 s 1 11111 n t STLX{R,RH,RB} Ws, Rt, [Xn|SP]
*/
+ /* For the "standard" implementation we pass through the LL and SC to
+ the host. For the "fallback" implementation, for details see
+ https://bugs.kde.org/show_bug.cgi?id=344524 and
+ https://bugs.kde.org/show_bug.cgi?id=369459,
+ but in short:
+
+ LoadLinked(addr)
+ gs.LLsize = load_size // 1, 2, 4 or 8
+ gs.LLaddr = addr
+ gs.LLdata = zeroExtend(*addr)
+
+ StoreCond(addr, data)
+ tmp_LLsize = gs.LLsize
+ gs.LLsize = 0 // "no transaction"
+ if tmp_LLsize != store_size -> fail
+ if addr != gs.LLaddr -> fail
+ if zeroExtend(*addr) != gs.LLdata -> fail
+ cas_ok = CAS(store_size, addr, gs.LLdata -> data)
+ if !cas_ok -> fail
+ succeed
+
+ When thread scheduled
+ gs.LLsize = 0 // "no transaction"
+ (coregrind/m_scheduler/scheduler.c, run_thread_for_a_while()
+ has to do this bit)
+ */
if (INSN(29,23) == BITS7(0,0,1,0,0,0,0)
&& (INSN(23,21) & BITS3(1,0,1)) == BITS3(0,0,0)
&& INSN(14,10) == BITS5(1,1,1,1,1)) {
@@ -6478,29 +6510,99 @@
if (isLD && ss == BITS5(1,1,1,1,1)) {
IRTemp res = newTemp(ty);
- stmt(IRStmt_LLSC(Iend_LE, res, mkexpr(ea), NULL/*LL*/));
- putIReg64orZR(tt, widenUto64(ty, mkexpr(res)));
+ if (abiinfo->guest__use_fallback_LLSC) {
+ // Do the load first so we don't update any guest state
+ // if it faults.
+ IRTemp loaded_data64 = newTemp(Ity_I64);
+ assign(loaded_data64, widenUto64(ty, loadLE(ty, mkexpr(ea))));
+ stmt( IRStmt_Put( OFFB_LLSC_DATA, mkexpr(loaded_data64) ));
+ stmt( IRStmt_Put( OFFB_LLSC_ADDR, mkexpr(ea) ));
+ stmt( IRStmt_Put( OFFB_LLSC_SIZE, mkU64(szB) ));
+ putIReg64orZR(tt, mkexpr(loaded_data64));
+ } else {
+ stmt(IRStmt_LLSC(Iend_LE, res, mkexpr(ea), NULL/*LL*/));
+ putIReg64orZR(tt, widenUto64(ty, mkexpr(res)));
+ }
if (isAcqOrRel) {
stmt(IRStmt_MBE(Imbe_Fence));
}
- DIP("ld%sx%s %s, [%s]\n", isAcqOrRel ? "a" : "", suffix[szBlg2],
- nameIRegOrZR(szB == 8, tt), nameIReg64orSP(nn));
+ DIP("ld%sx%s %s, [%s] %s\n", isAcqOrRel ? "a" : "", suffix[szBlg2],
+ nameIRegOrZR(szB == 8, tt), nameIReg64orSP(nn),
+ abiinfo->guest__use_fallback_LLSC
+ ? "(fallback implementation)" : "");
return True;
}
if (!isLD) {
if (isAcqOrRel) {
stmt(IRStmt_MBE(Imbe_Fence));
}
- IRTemp res = newTemp(Ity_I1);
IRExpr* data = narrowFrom64(ty, getIReg64orZR(tt));
- stmt(IRStmt_LLSC(Iend_LE, res, mkexpr(ea), data));
- /* IR semantics: res is 1 if store succeeds, 0 if it fails.
- Need to set rS to 1 on failure, 0 on success. */
- putIReg64orZR(ss, binop(Iop_Xor64, unop(Iop_1Uto64, mkexpr(res)),
- mkU64(1)));
- DIP("st%sx%s %s, %s, [%s]\n", isAcqOrRel ? "a" : "", suffix[szBlg2],
+ if (abiinfo->guest__use_fallback_LLSC) {
+ // This is really ugly, since we don't have any way to do
+ // proper if-then-else. First, set up as if the SC failed,
+ // and jump forwards if it really has failed.
+
+ // Continuation address
+ IRConst* nia = IRConst_U64(guest_PC_curr_instr + 4);
+
+ // "the SC failed". Any non-zero value means failure.
+ putIReg64orZR(ss, mkU64(1));
+
+ IRTemp tmp_LLsize = newTemp(Ity_I64);
+ assign(tmp_LLsize, IRExpr_Get(OFFB_LLSC_SIZE, Ity_I64));
+ stmt( IRStmt_Put( OFFB_LLSC_SIZE, mkU64(0) // "no transaction"
+ ));
+ // Fail if no or wrong-size transaction
+ vassert(szB == 8 || szB == 4 || szB == 2 || szB == 1);
+ stmt( IRStmt_Exit(
+ binop(Iop_CmpNE64, mkexpr(tmp_LLsize), mkU64(szB)),
+ Ijk_Boring, nia, OFFB_PC
+ ));
+ // Fail if the address doesn't match the LL address
+ stmt( IRStmt_Exit(
+ binop(Iop_CmpNE64, mkexpr(ea),
+ IRExpr_Get(OFFB_LLSC_ADDR, Ity_I64)),
+ Ijk_Boring, nia, OFFB_PC
+ ));
+ // Fail if the data doesn't match the LL data
+ IRTemp llsc_data64 = newTemp(Ity_I64);
+ assign(llsc_data64, IRExpr_Get(OFFB_LLSC_DATA, Ity_I64));
+ stmt( IRStmt_Exit(
+ binop(Iop_CmpNE64, widenUto64(ty, loadLE(ty, mkexpr(ea))),
+ mkexpr(llsc_data64)),
+ Ijk_Boring, nia, OFFB_PC
+ ));
+ // Try to CAS the new value in.
+ IRTemp old = newTemp(ty);
+ IRTemp expd = newTemp(ty);
+ assign(expd, narrowFrom64(ty, mkexpr(llsc_data64)));
+ stmt( IRStmt_CAS(mkIRCAS(/*oldHi*/IRTemp_INVALID, old,
+ Iend_LE, mkexpr(ea),
+ /*expdHi*/NULL, mkexpr(expd),
+ /*dataHi*/NULL, data
+ )));
+ // Fail if the CAS failed (viz, old != expd)
+ stmt( IRStmt_Exit(
+ binop(Iop_CmpNE64,
+ widenUto64(ty, mkexpr(old)),
+ widenUto64(ty, mkexpr(expd))),
+ Ijk_Boring, nia, OFFB_PC
+ ));
+ // Otherwise we succeeded (!)
+ putIReg64orZR(ss, mkU64(0));
+ } else {
+ IRTemp res = newTemp(Ity_I1);
+ stmt(IRStmt_LLSC(Iend_LE, res, mkexpr(ea), data));
+ /* IR semantics: res is 1 if store succeeds, 0 if it fails.
+ Need to set rS to 1 on failure, 0 on success. */
+ putIReg64orZR(ss, binop(Iop_Xor64, unop(Iop_1Uto64, mkexpr(res)),
+ mkU64(1)));
+ }
+ DIP("st%sx%s %s, %s, [%s] %s\n", isAcqOrRel ? "a" : "", suffix[szBlg2],
nameIRegOrZR(False, ss),
- nameIRegOrZR(szB == 8, tt), nameIReg64orSP(nn));
+ nameIRegOrZR(szB == 8, tt), nameIReg64orSP(nn),
+ abiinfo->guest__use_fallback_LLSC
+ ? "(fallback implementation)" : "");
return True;
}
/* else fall through */
@@ -6545,6 +6647,9 @@
return True;
}
+ /* The PRFM cases that follow are possibly allow Rt values (the
+ prefetch operation) which are not allowed by the documentation.
+ This should be looked into. */
/* ------------------ PRFM (immediate) ------------------ */
/* 31 21 9 4
11 111 00110 imm12 n t PRFM pfrop=Rt, [Xn|SP, #pimm]
@@ -6577,6 +6682,23 @@
}
}
+ /* ------------------ PRFM (unscaled offset) ------------------ */
+ /* 31 29 22 20 11 9 4
+ 11 1110001 00 imm9 00 Rn Rt PRFM pfrop=Rt, [Xn|SP, #simm]
+ */
+ if (INSN(31,21) == BITS11(1,1, 1,1,1,0,0,0,1, 0,0)
+ && INSN(11,10) == BITS2(0,0)) {
+ ULong imm9 = INSN(20,12);
+ UInt nn = INSN(9,5);
+ UInt tt = INSN(4,0);
+ ULong offset = sx_to_64(imm9, 9);
+ IRTemp ea = newTemp(Ity_I64);
+ assign(ea, binop(Iop_Add64, getIReg64orSP(nn), mkU64(offset)));
+ /* No actual code to generate. */
+ DIP("prfum prfop=%u, [%s, #0x%llx]\n", tt, nameIReg64orSP(nn), offset);
+ return True;
+ }
+
vex_printf("ARM64 front end: load_store\n");
return False;
# undef INSN
@@ -6589,7 +6711,8 @@
static
Bool dis_ARM64_branch_etc(/*MB_OUT*/DisResult* dres, UInt insn,
- const VexArchInfo* archinfo)
+ const VexArchInfo* archinfo,
+ const VexAbiInfo* abiinfo)
{
# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
@@ -6905,6 +7028,27 @@
DIP("mrs %s, cntvct_el0\n", nameIReg64orZR(tt));
return True;
}
+ /* ---- Cases for CNTFRQ_EL0 ----
+ This is always RO at EL0, so it's safe to pass through to the host.
+ D5 3B E0 000 Rt MRS Xt, cntfrq_el0
+ */
+ if ((INSN(31,0) & 0xFFFFFFE0) == 0xD53BE000) {
+ UInt tt = INSN(4,0);
+ IRTemp val = newTemp(Ity_I64);
+ IRExpr** args = mkIRExprVec_0();
+ IRDirty* d = unsafeIRDirty_1_N (
+ val,
+ 0/*regparms*/,
+ "arm64g_dirtyhelper_MRS_CNTFRQ_EL0",
+ &arm64g_dirtyhelper_MRS_CNTFRQ_EL0,
+ args
+ );
+ /* execute the dirty call, dumping the result in val. */
+ stmt( IRStmt_Dirty(d) );
+ putIReg64orZR(tt, mkexpr(val));
+ DIP("mrs %s, cntfrq_el0\n", nameIReg64orZR(tt));
+ return True;
+ }
/* ------------------ IC_IVAU ------------------ */
/* D5 0B 75 001 Rt ic ivau, rT
@@ -7022,6 +7166,22 @@
return True;
}
+ /* -------------------- HINT ------------------- */
+ /* 31 23 15 11 4 3
+ 1101 0101 0000 0011 0010 imm7 1 1111
+ Catch otherwise unhandled HINT instructions - any
+ like YIELD which are explicitly handled should go
+ above this case.
+ */
+ if (INSN(31,24) == BITS8(1,1,0,1,0,1,0,1)
+ && INSN(23,16) == BITS8(0,0,0,0,0,0,1,1)
+ && INSN(15,12) == BITS4(0,0,1,0)
+ && INSN(4,0) == BITS5(1,1,1,1,1)) {
+ UInt imm7 = INSN(11,5);
+ DIP("hint #%u\n", imm7);
+ return True;
+ }
+
/* ------------------- CLREX ------------------ */
/* 31 23 15 11 7
1101 0101 0000 0011 0011 m 0101 1111 CLREX CRm
@@ -7032,7 +7192,11 @@
/* AFAICS, this simply cancels a (all?) reservations made by a
(any?) preceding LDREX(es). Arrange to hand it through to
the back end. */
- stmt( IRStmt_MBE(Imbe_CancelReservation) );
+ if (abiinfo->guest__use_fallback_LLSC) {
+ stmt( IRStmt_Put( OFFB_LLSC_SIZE, mkU64(0) )); // "no transaction"
+ } else {
+ stmt( IRStmt_MBE(Imbe_CancelReservation) );
+ }
DIP("clrex #%u\n", mm);
return True;
}
@@ -14289,6 +14453,7 @@
dres->len = 4;
dres->continueAt = 0;
dres->jk_StopHere = Ijk_INVALID;
+ dres->hint = Dis_HintNone;
/* At least this is simple on ARM64: insns are all 4 bytes long, and
4-aligned. So just fish the whole thing out of memory right now
@@ -14394,12 +14559,12 @@
break;
case BITS4(1,0,1,0): case BITS4(1,0,1,1):
// Branch, exception generation and system instructions
- ok = dis_ARM64_branch_etc(dres, insn, archinfo);
+ ok = dis_ARM64_branch_etc(dres, insn, archinfo, abiinfo);
break;
case BITS4(0,1,0,0): case BITS4(0,1,1,0):
case BITS4(1,1,0,0): case BITS4(1,1,1,0):
// Loads and stores
- ok = dis_ARM64_load_store(dres, insn);
+ ok = dis_ARM64_load_store(dres, insn, abiinfo);
break;
case BITS4(0,1,0,1): case BITS4(1,1,0,1):
// Data processing - register
diff --git a/VEX/priv/guest_arm_defs.h b/VEX/priv/guest_arm_defs.h
index a8a278c..2ccbe43 100644
--- a/VEX/priv/guest_arm_defs.h
+++ b/VEX/priv/guest_arm_defs.h
@@ -6,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -40,7 +40,7 @@
/*---------------------------------------------------------*/
/* Convert one ARM insn to IR. See the type DisOneInstrFn in
- bb_to_IR.h. */
+ geust_generic_ bb_to_IR.h. */
extern
DisResult disInstr_ARM ( IRSB* irbb,
Bool (*resteerOkFn) ( void*, Addr ),
diff --git a/VEX/priv/guest_arm_helpers.c b/VEX/priv/guest_arm_helpers.c
index 9002a76..0ef26b6 100644
--- a/VEX/priv/guest_arm_helpers.c
+++ b/VEX/priv/guest_arm_helpers.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c
index ef5a79b..b26393a 100644
--- a/VEX/priv/guest_arm_toIR.c
+++ b/VEX/priv/guest_arm_toIR.c
@@ -7,11 +7,11 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
NEON support is
- Copyright (C) 2010-2015 Samsung Electronics
+ Copyright (C) 2010-2017 Samsung Electronics
contributed by Dmitry Zhurikhin <zhur@ispras.ru>
and Kirill Batuzov <batuzovk@ispras.ru>
@@ -855,7 +855,10 @@
for endianness. Actually this is completely bogus and needs
careful thought. */
Int off;
- vassert(fregNo < 32);
+ /* NB! Limit is 64, not 32, because we might be pulling F32 bits
+ out of SIMD registers, and there are 16 SIMD registers each of
+ 128 bits (4 x F32). */
+ vassert(fregNo < 64);
off = doubleGuestRegOffset(fregNo >> 1);
if (host_endness == VexEndnessLE) {
if (fregNo & 1)
@@ -873,6 +876,12 @@
return IRExpr_Get( floatGuestRegOffset(fregNo), Ity_F32 );
}
+static IRExpr* llGetFReg_up_to_64 ( UInt fregNo )
+{
+ vassert(fregNo < 64);
+ return IRExpr_Get( floatGuestRegOffset(fregNo), Ity_F32 );
+}
+
/* Architected read from a VFP Freg. */
static IRExpr* getFReg ( UInt fregNo ) {
return llGetFReg( fregNo );
@@ -886,6 +895,13 @@
stmt( IRStmt_Put(floatGuestRegOffset(fregNo), e) );
}
+static void llPutFReg_up_to_64 ( UInt fregNo, IRExpr* e )
+{
+ vassert(fregNo < 64);
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_F32);
+ stmt( IRStmt_Put(floatGuestRegOffset(fregNo), e) );
+}
+
/* Architected write to a VFP Freg. Handles conditional writes to the
register: if guardT == IRTemp_INVALID then the write is
unconditional. */
@@ -3392,6 +3408,8 @@
reg_t, dreg, reg_t, nreg, reg_t, mreg);
break;
}
+ default:
+ vassert(0);
}
} else {
switch(C) {
@@ -3489,6 +3507,8 @@
Q ? 'q' : 'd', dreg,
Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
break;
+ default:
+ vassert(0);
}
}
}
@@ -4611,6 +4631,8 @@
DIP("vpadd.i%d %c%u, %c%u, %c%u\n",
8 << size, Q ? 'q' : 'd',
dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+ } else {
+ return False;
}
}
break;
@@ -4768,6 +4790,8 @@
DIP("vacg%c.f32 %c%u, %c%u, %c%u\n", op_bit ? 't' : 'e',
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg,
Q ? 'q' : 'd', mreg);
+ } else {
+ return False;
}
}
break;
@@ -4827,6 +4851,8 @@
DIP("vrsqrts.f32 %c%u, %c%u, %c%u\n", Q ? 'q' : 'd', dreg,
Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
}
+ } else {
+ return False;
}
}
break;
@@ -13348,12 +13374,14 @@
}
else /*NOTREACHED*/vassert(0);
}
- // Paranoia ..
- vassert(szBlg2 <= 3);
- if (szBlg2 < 3) { vassert(tt2 == 16/*invalid*/); }
- else { vassert(tt2 <= 14); }
- if (isLoad) { vassert(dd == 16/*invalid*/); }
- else { vassert(dd <= 14); }
+ if (gate) {
+ // Paranoia ..
+ vassert(szBlg2 <= 3);
+ if (szBlg2 < 3) { vassert(tt2 == 16/*invalid*/); }
+ else { vassert(tt2 <= 14); }
+ if (isLoad) { vassert(dd == 16/*invalid*/); }
+ else { vassert(dd <= 14); }
+ }
// If we're still good even after all that, generate the IR.
if (gate) {
/* First, go unconditional. Staying in-line is too complex. */
@@ -13460,6 +13488,551 @@
/* else fall through */
}
+ /* ----------- VSEL<c>.F64 d_d_d, VSEL<c>.F32 s_s_s ----------- */
+ /* 31 27 22 21 19 15 11 8 7 6 5 4 3
+ T1/A1: 1111 11100 D cc n d 101 1 N 0 M 0 m VSEL<c>.F64 Dd, Dn, Dm
+ T1/A1: 1111 11100 D cc n d 101 0 N 0 M 0 m VSEL<c>.F32 Sd, Sn, Sm
+
+ ARM encoding is in NV space.
+ In Thumb mode, we must not be in an IT block.
+ */
+ if (INSN(31,23) == BITS9(1,1,1,1,1,1,1,0,0) && INSN(11,9) == BITS3(1,0,1)
+ && INSN(6,6) == 0 && INSN(4,4) == 0) {
+ UInt bit_D = INSN(22,22);
+ UInt fld_cc = INSN(21,20);
+ UInt fld_n = INSN(19,16);
+ UInt fld_d = INSN(15,12);
+ Bool isF64 = INSN(8,8) == 1;
+ UInt bit_N = INSN(7,7);
+ UInt bit_M = INSN(5,5);
+ UInt fld_m = INSN(3,0);
+
+ UInt dd = isF64 ? ((bit_D << 4) | fld_d) : ((fld_d << 1) | bit_D);
+ UInt nn = isF64 ? ((bit_N << 4) | fld_n) : ((fld_n << 1) | bit_N);
+ UInt mm = isF64 ? ((bit_M << 4) | fld_m) : ((fld_m << 1) | bit_M);
+
+ UInt cc_1 = (fld_cc >> 1) & 1;
+ UInt cc_0 = (fld_cc >> 0) & 1;
+ UInt cond = (fld_cc << 2) | ((cc_1 ^ cc_0) << 1) | 0;
+
+ if (isT) {
+ gen_SIGILL_T_if_in_ITBlock(old_itstate, new_itstate);
+ }
+ /* In ARM mode, this is statically unconditional. In Thumb mode,
+ this must be dynamically unconditional, and we've SIGILLd if not.
+ In either case we can create unconditional IR. */
+
+ IRTemp guard = newTemp(Ity_I32);
+ assign(guard, mk_armg_calculate_condition(cond));
+ IRExpr* srcN = (isF64 ? llGetDReg : llGetFReg)(nn);
+ IRExpr* srcM = (isF64 ? llGetDReg : llGetFReg)(mm);
+ IRExpr* res = IRExpr_ITE(unop(Iop_32to1, mkexpr(guard)), srcN, srcM);
+ (isF64 ? llPutDReg : llPutFReg)(dd, res);
+
+ UChar rch = isF64 ? 'd' : 'f';
+ DIP("vsel%s.%s %c%u, %c%u, %c%u\n",
+ nCC(cond), isF64 ? "f64" : "f32", rch, dd, rch, nn, rch, mm);
+ return True;
+ }
+
+ /* -------- VRINT{A,N,P,M}.F64 d_d, VRINT{A,N,P,M}.F32 s_s -------- */
+ /* 31 22 21 17 15 11 8 7 5 4 3
+ T1/A1: 111111101 D 1110 rm Vd 101 1 01 M 0 Vm VRINT{A,N,P,M}.F64 Dd, Dm
+ T1/A1: 111111101 D 1110 rm Vd 101 0 01 M 0 Vm VRINT{A,N,P,M}.F32 Sd, Sm
+
+ ARM encoding is in NV space.
+ In Thumb mode, we must not be in an IT block.
+ */
+ if (INSN(31,23) == BITS9(1,1,1,1,1,1,1,0,1)
+ && INSN(21,18) == BITS4(1,1,1,0) && INSN(11,9) == BITS3(1,0,1)
+ && INSN(7,6) == BITS2(0,1) && INSN(4,4) == 0) {
+ UInt bit_D = INSN(22,22);
+ UInt fld_rm = INSN(17,16);
+ UInt fld_d = INSN(15,12);
+ Bool isF64 = INSN(8,8) == 1;
+ UInt bit_M = INSN(5,5);
+ UInt fld_m = INSN(3,0);
+
+ UInt dd = isF64 ? ((bit_D << 4) | fld_d) : ((fld_d << 1) | bit_D);
+ UInt mm = isF64 ? ((bit_M << 4) | fld_m) : ((fld_m << 1) | bit_M);
+
+ if (isT) {
+ gen_SIGILL_T_if_in_ITBlock(old_itstate, new_itstate);
+ }
+ /* In ARM mode, this is statically unconditional. In Thumb mode,
+ this must be dynamically unconditional, and we've SIGILLd if not.
+ In either case we can create unconditional IR. */
+
+ UChar c = '?';
+ IRRoundingMode rm = Irrm_NEAREST;
+ switch (fld_rm) {
+ /* The use of NEAREST for both the 'a' and 'n' cases is a bit of a
+ kludge since it doesn't take into account the nearest-even vs
+ nearest-away semantics. */
+ case BITS2(0,0): c = 'a'; rm = Irrm_NEAREST; break;
+ case BITS2(0,1): c = 'n'; rm = Irrm_NEAREST; break;
+ case BITS2(1,0): c = 'p'; rm = Irrm_PosINF; break;
+ case BITS2(1,1): c = 'm'; rm = Irrm_NegINF; break;
+ default: vassert(0);
+ }
+
+ IRExpr* srcM = (isF64 ? llGetDReg : llGetFReg)(mm);
+ IRExpr* res = binop(isF64 ? Iop_RoundF64toInt : Iop_RoundF32toInt,
+ mkU32((UInt)rm), srcM);
+ (isF64 ? llPutDReg : llPutFReg)(dd, res);
+
+ UChar rch = isF64 ? 'd' : 'f';
+ DIP("vrint%c.%s.%s %c%u, %c%u\n",
+ c, isF64 ? "f64" : "f32", isF64 ? "f64" : "f32", rch, dd, rch, mm);
+ return True;
+ }
+
+ /* -------- VRINT{Z,R}.F64.F64 d_d, VRINT{Z,R}.F32.F32 s_s -------- */
+ /* 31 27 22 21 15 11 7 6 5 4 3
+ T1: 1110 11101 D 110110 Vd 1011 op 1 M 0 Vm VRINT<r><c>.F64.F64 Dd, Dm
+ A1: cond 11101 D 110110 Vd 1011 op 1 M 0 Vm
+
+ T1: 1110 11101 D 110110 Vd 1010 op 1 M 0 Vm VRINT<r><c>.F32.F32 Sd, Sm
+ A1: cond 11101 D 110110 Vd 1010 op 1 M 0 Vm
+
+ In contrast to the VRINT variants just above, this can be conditional.
+ */
+ if ((isT ? (INSN(31,28) == BITS4(1,1,1,0)) : True)
+ && INSN(27,23) == BITS5(1,1,1,0,1) && INSN(21,16) == BITS6(1,1,0,1,1,0)
+ && INSN(11,9) == BITS3(1,0,1) && INSN(6,6) == 1 && INSN(4,4) == 0) {
+ UInt bit_D = INSN(22,22);
+ UInt fld_Vd = INSN(15,12);
+ Bool isF64 = INSN(8,8) == 1;
+ Bool rToZero = INSN(7,7) == 1;
+ UInt bit_M = INSN(5,5);
+ UInt fld_Vm = INSN(3,0);
+ UInt dd = isF64 ? ((bit_D << 4) | fld_Vd) : ((fld_Vd << 1) | bit_D);
+ UInt mm = isF64 ? ((bit_M << 4) | fld_Vm) : ((fld_Vm << 1) | bit_M);
+
+ if (isT) vassert(condT != IRTemp_INVALID);
+ IRType ty = isF64 ? Ity_F64 : Ity_F32;
+ IRTemp src = newTemp(ty);
+ IRTemp res = newTemp(ty);
+ assign(src, (isF64 ? getDReg : getFReg)(mm));
+
+ IRTemp rm = newTemp(Ity_I32);
+ assign(rm, rToZero ? mkU32(Irrm_ZERO)
+ : mkexpr(mk_get_IR_rounding_mode()));
+ assign(res, binop(isF64 ? Iop_RoundF64toInt : Iop_RoundF32toInt,
+ mkexpr(rm), mkexpr(src)));
+ (isF64 ? putDReg : putFReg)(dd, mkexpr(res), condT);
+
+ UChar rch = isF64 ? 'd' : 'f';
+ DIP("vrint%c.%s.%s %c%u, %c%u\n",
+ rToZero ? 'z' : 'r',
+ isF64 ? "f64" : "f32", isF64 ? "f64" : "f32", rch, dd, rch, mm);
+ return True;
+ }
+
+ /* ----------- VCVT{A,N,P,M}{.S32,.U32}{.F64,.F32} ----------- */
+ /* 31 27 22 21 17 15 11 8 7 6 5 4 3
+ T1/A1: 1111 11101 D 1111 rm Vd 101 sz op 1 M 0 Vm
+ VCVT{A,N,P,M}{.S32,.U32}.F64 Sd, Dm
+ VCVT{A,N,P,M}{.S32,.U32}.F32 Sd, Sm
+
+ ARM encoding is in NV space.
+ In Thumb mode, we must not be in an IT block.
+ */
+ if (INSN(31,23) == BITS9(1,1,1,1,1,1,1,0,1) && INSN(21,18) == BITS4(1,1,1,1)
+ && INSN(11,9) == BITS3(1,0,1) && INSN(6,6) == 1 && INSN(4,4) == 0) {
+ UInt bit_D = INSN(22,22);
+ UInt fld_rm = INSN(17,16);
+ UInt fld_Vd = INSN(15,12);
+ Bool isF64 = INSN(8,8) == 1;
+ Bool isU = INSN(7,7) == 0;
+ UInt bit_M = INSN(5,5);
+ UInt fld_Vm = INSN(3,0);
+
+ UInt dd = (fld_Vd << 1) | bit_D;
+ UInt mm = isF64 ? ((bit_M << 4) | fld_Vm) : ((fld_Vm << 1) | bit_M);
+
+ if (isT) {
+ gen_SIGILL_T_if_in_ITBlock(old_itstate, new_itstate);
+ }
+ /* In ARM mode, this is statically unconditional. In Thumb mode,
+ this must be dynamically unconditional, and we've SIGILLd if not.
+ In either case we can create unconditional IR. */
+
+ UChar c = '?';
+ IRRoundingMode rm = Irrm_NEAREST;
+ switch (fld_rm) {
+ /* The use of NEAREST for both the 'a' and 'n' cases is a bit of a
+ kludge since it doesn't take into account the nearest-even vs
+ nearest-away semantics. */
+ case BITS2(0,0): c = 'a'; rm = Irrm_NEAREST; break;
+ case BITS2(0,1): c = 'n'; rm = Irrm_NEAREST; break;
+ case BITS2(1,0): c = 'p'; rm = Irrm_PosINF; break;
+ case BITS2(1,1): c = 'm'; rm = Irrm_NegINF; break;
+ default: vassert(0);
+ }
+
+ IRExpr* srcM = (isF64 ? llGetDReg : llGetFReg)(mm);
+ IRTemp res = newTemp(Ity_I32);
+
+ /* The arm back end doesn't support use of Iop_F32toI32U or
+ Iop_F32toI32S, so for those cases we widen the F32 to F64
+ and then follow the F64 route. */
+ if (!isF64) {
+ srcM = unop(Iop_F32toF64, srcM);
+ }
+ assign(res, binop(isU ? Iop_F64toI32U : Iop_F64toI32S,
+ mkU32((UInt)rm), srcM));
+
+ llPutFReg(dd, unop(Iop_ReinterpI32asF32, mkexpr(res)));
+
+ UChar rch = isF64 ? 'd' : 'f';
+ DIP("vcvt%c.%s.%s %c%u, %c%u\n",
+ c, isU ? "u32" : "s32", isF64 ? "f64" : "f32", 's', dd, rch, mm);
+ return True;
+ }
+
+ /* ----------- V{MAX,MIN}NM{.F64 d_d_d, .F32 s_s_s} ----------- */
+ /* 31 27 22 21 19 15 11 8 7 6 5 4 3
+ 1111 11101 D 00 Vn Vd 101 1 N op M 0 Vm V{MIN,MAX}NM.F64 Dd, Dn, Dm
+ 1111 11101 D 00 Vn Vd 101 0 N op M 0 Vm V{MIN,MAX}NM.F32 Sd, Sn, Sm
+
+ ARM encoding is in NV space.
+ In Thumb mode, we must not be in an IT block.
+ */
+ if (INSN(31,23) == BITS9(1,1,1,1,1,1,1,0,1) && INSN(21,20) == BITS2(0,0)
+ && INSN(11,9) == BITS3(1,0,1) && INSN(4,4) == 0) {
+ UInt bit_D = INSN(22,22);
+ UInt fld_Vn = INSN(19,16);
+ UInt fld_Vd = INSN(15,12);
+ Bool isF64 = INSN(8,8) == 1;
+ UInt bit_N = INSN(7,7);
+ Bool isMAX = INSN(6,6) == 0;
+ UInt bit_M = INSN(5,5);
+ UInt fld_Vm = INSN(3,0);
+
+ UInt dd = isF64 ? ((bit_D << 4) | fld_Vd) : ((fld_Vd << 1) | bit_D);
+ UInt nn = isF64 ? ((bit_N << 4) | fld_Vn) : ((fld_Vn << 1) | bit_N);
+ UInt mm = isF64 ? ((bit_M << 4) | fld_Vm) : ((fld_Vm << 1) | bit_M);
+
+ if (isT) {
+ gen_SIGILL_T_if_in_ITBlock(old_itstate, new_itstate);
+ }
+ /* In ARM mode, this is statically unconditional. In Thumb mode,
+ this must be dynamically unconditional, and we've SIGILLd if not.
+ In either case we can create unconditional IR. */
+
+ IROp op = isF64 ? (isMAX ? Iop_MaxNumF64 : Iop_MinNumF64)
+ : (isMAX ? Iop_MaxNumF32 : Iop_MinNumF32);
+ IRExpr* srcN = (isF64 ? llGetDReg : llGetFReg)(nn);
+ IRExpr* srcM = (isF64 ? llGetDReg : llGetFReg)(mm);
+ IRExpr* res = binop(op, srcN, srcM);
+ (isF64 ? llPutDReg : llPutFReg)(dd, res);
+
+ UChar rch = isF64 ? 'd' : 'f';
+ DIP("v%snm.%s %c%u, %c%u, %c%u\n",
+ isMAX ? "max" : "min", isF64 ? "f64" : "f32",
+ rch, dd, rch, nn, rch, mm);
+ return True;
+ }
+
+ /* ----------- VRINTX.F64.F64 d_d, VRINTX.F32.F32 s_s ----------- */
+ /* 31 27 22 21 15 11 8 7 5 4 3
+ T1: 1110 11101 D 110111 Vd 101 1 01 M 0 Vm VRINTX<c>.F64.F64 Dd, Dm
+ A1: cond 11101 D 110111 Vd 101 1 01 M 0 Vm
+
+ T1: 1110 11101 D 110111 Vd 101 0 01 M 0 Vm VRINTX<c>.F32.F32 Dd, Dm
+ A1: cond 11101 D 110111 Vd 101 0 01 M 0 Vm
+
+ Like VRINT{Z,R}{.F64.F64, .F32.F32} just above, this can be conditional.
+ This produces the same code as the VRINTR case since we ignore the
+ requirement to signal inexactness.
+ */
+ if ((isT ? (INSN(31,28) == BITS4(1,1,1,0)) : True)
+ && INSN(27,23) == BITS5(1,1,1,0,1) && INSN(21,16) == BITS6(1,1,0,1,1,1)
+ && INSN(11,9) == BITS3(1,0,1) && INSN(7,6) == BITS2(0,1)
+ && INSN(4,4) == 0) {
+ UInt bit_D = INSN(22,22);
+ UInt fld_Vd = INSN(15,12);
+ Bool isF64 = INSN(8,8) == 1;
+ UInt bit_M = INSN(5,5);
+ UInt fld_Vm = INSN(3,0);
+ UInt dd = isF64 ? ((bit_D << 4) | fld_Vd) : ((fld_Vd << 1) | bit_D);
+ UInt mm = isF64 ? ((bit_M << 4) | fld_Vm) : ((fld_Vm << 1) | bit_M);
+
+ if (isT) vassert(condT != IRTemp_INVALID);
+ IRType ty = isF64 ? Ity_F64 : Ity_F32;
+ IRTemp src = newTemp(ty);
+ IRTemp res = newTemp(ty);
+ assign(src, (isF64 ? getDReg : getFReg)(mm));
+
+ IRTemp rm = newTemp(Ity_I32);
+ assign(rm, mkexpr(mk_get_IR_rounding_mode()));
+ assign(res, binop(isF64 ? Iop_RoundF64toInt : Iop_RoundF32toInt,
+ mkexpr(rm), mkexpr(src)));
+ (isF64 ? putDReg : putFReg)(dd, mkexpr(res), condT);
+
+ UChar rch = isF64 ? 'd' : 'f';
+ DIP("vrint%c.%s.%s %c%u, %c%u\n",
+ 'x',
+ isF64 ? "f64" : "f32", isF64 ? "f64" : "f32", rch, dd, rch, mm);
+ return True;
+ }
+
+ /* ----------- V{MAX,MIN}NM{.F32 d_d_d, .F32 q_q_q} ----------- */
+ /* 31 27 22 21 20 19 15 11 7 6 5 4 3
+ T1: 1111 11110 D op 0 Vn Vd 1111 N 1 M 1 Vm V{MIN,MAX}NM.F32 Qd,Qn,Qm
+ A1: 1111 00110 D op 0 Vn Vd 1111 N 1 M 1 Vm
+
+ T1: 1111 11110 D op 0 Vn Vd 1111 N 0 M 1 Vm V{MIN,MAX}NM.F32 Dd,Dn,Dm
+ A1: 1111 00110 D op 0 Vn Vd 1111 N 0 M 1 Vm
+
+ ARM encoding is in NV space.
+ In Thumb mode, we must not be in an IT block.
+ */
+ if (INSN(31,23) == (isT ? BITS9(1,1,1,1,1,1,1,1,0)
+ : BITS9(1,1,1,1,0,0,1,1,0))
+ && INSN(20,20) == 0 && INSN(11,8) == BITS4(1,1,1,1) && INSN(4,4) == 1) {
+ UInt bit_D = INSN(22,22);
+ Bool isMax = INSN(21,21) == 0;
+ UInt fld_Vn = INSN(19,16);
+ UInt fld_Vd = INSN(15,12);
+ UInt bit_N = INSN(7,7);
+ Bool isQ = INSN(6,6) == 1;
+ UInt bit_M = INSN(5,5);
+ UInt fld_Vm = INSN(3,0);
+
+ /* dd, nn, mm are D-register numbers. */
+ UInt dd = (bit_D << 4) | fld_Vd;
+ UInt nn = (bit_N << 4) | fld_Vn;
+ UInt mm = (bit_M << 4) | fld_Vm;
+
+ if (! (isQ && ((dd & 1) == 1 || (nn & 1) == 1 || (mm & 1) == 1))) {
+ /* Do this piecewise on f regs. This is a bit tricky
+ though because we are dealing with the full 16 x Q == 32 x D
+ register set, so the implied F reg numbers are 0 to 63. But
+ ll{Get,Put}FReg only allow the 0 .. 31 as those are the only
+ architected F regs. */
+ UInt ddF = dd << 1;
+ UInt nnF = nn << 1;
+ UInt mmF = mm << 1;
+
+ if (isT) {
+ gen_SIGILL_T_if_in_ITBlock(old_itstate, new_itstate);
+ }
+ /* In ARM mode, this is statically unconditional. In Thumb mode,
+ this must be dynamically unconditional, and we've SIGILLd if not.
+ In either case we can create unconditional IR. */
+
+ IROp op = isMax ? Iop_MaxNumF32 : Iop_MinNumF32;
+
+ IRTemp r0 = newTemp(Ity_F32);
+ IRTemp r1 = newTemp(Ity_F32);
+ IRTemp r2 = isQ ? newTemp(Ity_F32) : IRTemp_INVALID;
+ IRTemp r3 = isQ ? newTemp(Ity_F32) : IRTemp_INVALID;
+
+ assign(r0, binop(op, llGetFReg_up_to_64(nnF+0),
+ llGetFReg_up_to_64(mmF+0)));
+ assign(r1, binop(op, llGetFReg_up_to_64(nnF+1),
+ llGetFReg_up_to_64(mmF+1)));
+ if (isQ) {
+ assign(r2, binop(op, llGetFReg_up_to_64(nnF+2),
+ llGetFReg_up_to_64(mmF+2)));
+ assign(r3, binop(op, llGetFReg_up_to_64(nnF+3),
+ llGetFReg_up_to_64(mmF+3)));
+ }
+ llPutFReg_up_to_64(ddF+0, mkexpr(r0));
+ llPutFReg_up_to_64(ddF+1, mkexpr(r1));
+ if (isQ) {
+ llPutFReg_up_to_64(ddF+2, mkexpr(r2));
+ llPutFReg_up_to_64(ddF+3, mkexpr(r3));
+ }
+
+ HChar rch = isQ ? 'q' : 'd';
+ UInt sh = isQ ? 1 : 0;
+ DIP("v%snm.f32 %c%u, %c%u, %c%u\n",
+ isMax ? "max" : "min", rch,
+ dd >> sh, rch, nn >> sh, rch, mm >> sh);
+ return True;
+ }
+ /* else fall through */
+ }
+
+ /* ----------- VCVT{A,N,P,M}{.F32 d_d, .F32 q_q} ----------- */
+ /* 31 27 22 21 15 11 9 7 6 5 4 3
+ T1: 1111 11111 D 111011 Vd 00 rm op Q M 0 Vm
+ A1: 1111 00111 D 111011 Vd 00 rm op Q M 0 Vm
+
+ ARM encoding is in NV space.
+ In Thumb mode, we must not be in an IT block.
+ */
+ if (INSN(31,23) == (isT ? BITS9(1,1,1,1,1,1,1,1,1)
+ : BITS9(1,1,1,1,0,0,1,1,1))
+ && INSN(21,16) == BITS6(1,1,1,0,1,1) && INSN(11,10) == BITS2(0,0)
+ && INSN(4,4) == 0) {
+ UInt bit_D = INSN(22,22);
+ UInt fld_Vd = INSN(15,12);
+ UInt fld_rm = INSN(9,8);
+ Bool isU = INSN(7,7) == 1;
+ Bool isQ = INSN(6,6) == 1;
+ UInt bit_M = INSN(5,5);
+ UInt fld_Vm = INSN(3,0);
+
+ /* dd, nn, mm are D-register numbers. */
+ UInt dd = (bit_D << 4) | fld_Vd;
+ UInt mm = (bit_M << 4) | fld_Vm;
+
+ if (! (isQ && ((dd & 1) == 1 || (mm & 1) == 1))) {
+ /* Do this piecewise on f regs. */
+ UInt ddF = dd << 1;
+ UInt mmF = mm << 1;
+
+ if (isT) {
+ gen_SIGILL_T_if_in_ITBlock(old_itstate, new_itstate);
+ }
+ /* In ARM mode, this is statically unconditional. In Thumb mode,
+ this must be dynamically unconditional, and we've SIGILLd if not.
+ In either case we can create unconditional IR. */
+
+ UChar cvtc = '?';
+ IRRoundingMode rm = Irrm_NEAREST;
+ switch (fld_rm) {
+ /* The use of NEAREST for both the 'a' and 'n' cases is a bit of a
+ kludge since it doesn't take into account the nearest-even vs
+ nearest-away semantics. */
+ case BITS2(0,0): cvtc = 'a'; rm = Irrm_NEAREST; break;
+ case BITS2(0,1): cvtc = 'n'; rm = Irrm_NEAREST; break;
+ case BITS2(1,0): cvtc = 'p'; rm = Irrm_PosINF; break;
+ case BITS2(1,1): cvtc = 'm'; rm = Irrm_NegINF; break;
+ default: vassert(0);
+ }
+
+ IROp cvt = isU ? Iop_F64toI32U : Iop_F64toI32S;
+
+ IRTemp r0 = newTemp(Ity_F32);
+ IRTemp r1 = newTemp(Ity_F32);
+ IRTemp r2 = isQ ? newTemp(Ity_F32) : IRTemp_INVALID;
+ IRTemp r3 = isQ ? newTemp(Ity_F32) : IRTemp_INVALID;
+
+ IRExpr* rmE = mkU32((UInt)rm);
+
+ assign(r0, unop(Iop_ReinterpI32asF32,
+ binop(cvt, rmE, unop(Iop_F32toF64,
+ llGetFReg_up_to_64(mmF+0)))));
+ assign(r1, unop(Iop_ReinterpI32asF32,
+ binop(cvt, rmE, unop(Iop_F32toF64,
+ llGetFReg_up_to_64(mmF+1)))));
+ if (isQ) {
+ assign(r2, unop(Iop_ReinterpI32asF32,
+ binop(cvt, rmE, unop(Iop_F32toF64,
+ llGetFReg_up_to_64(mmF+2)))));
+ assign(r3, unop(Iop_ReinterpI32asF32,
+ binop(cvt, rmE, unop(Iop_F32toF64,
+ llGetFReg_up_to_64(mmF+3)))));
+ }
+
+ llPutFReg_up_to_64(ddF+0, mkexpr(r0));
+ llPutFReg_up_to_64(ddF+1, mkexpr(r1));
+ if (isQ) {
+ llPutFReg_up_to_64(ddF+2, mkexpr(r2));
+ llPutFReg_up_to_64(ddF+3, mkexpr(r3));
+ }
+
+ HChar rch = isQ ? 'q' : 'd';
+ UInt sh = isQ ? 1 : 0;
+ DIP("vcvt%c.%c32.f32 %c%u, %c%u\n",
+ cvtc, isU ? 'u' : 's', rch, dd >> sh, rch, mm >> sh);
+ return True;
+ }
+ /* else fall through */
+ }
+
+ /* ----------- VRINT{A,N,P,M,X,Z}{.F32 d_d, .F32 q_q} ----------- */
+ /* 31 27 22 21 15 11 9 6 5 4 3
+ T1: 1111 11111 D 111010 Vd 01 op Q M 0 Vm
+ A1: 1111 00111 D 111010 Vd 01 op Q M 0 Vm
+
+ ARM encoding is in NV space.
+ In Thumb mode, we must not be in an IT block.
+ */
+ if (INSN(31,23) == (isT ? BITS9(1,1,1,1,1,1,1,1,1)
+ : BITS9(1,1,1,1,0,0,1,1,1))
+ && INSN(21,16) == BITS6(1,1,1,0,1,0) && INSN(11,10) == BITS2(0,1)
+ && INSN(4,4) == 0) {
+ UInt bit_D = INSN(22,22);
+ UInt fld_Vd = INSN(15,12);
+ UInt fld_op = INSN(9,7);
+ Bool isQ = INSN(6,6) == 1;
+ UInt bit_M = INSN(5,5);
+ UInt fld_Vm = INSN(3,0);
+
+ /* dd, nn, mm are D-register numbers. */
+ UInt dd = (bit_D << 4) | fld_Vd;
+ UInt mm = (bit_M << 4) | fld_Vm;
+
+ if (! (fld_op == BITS3(1,0,0) || fld_op == BITS3(1,1,0))
+ && ! (isQ && ((dd & 1) == 1 || (mm & 1) == 1))) {
+ /* Do this piecewise on f regs. */
+ UInt ddF = dd << 1;
+ UInt mmF = mm << 1;
+
+ if (isT) {
+ gen_SIGILL_T_if_in_ITBlock(old_itstate, new_itstate);
+ }
+ /* In ARM mode, this is statically unconditional. In Thumb mode,
+ this must be dynamically unconditional, and we've SIGILLd if not.
+ In either case we can create unconditional IR. */
+
+ UChar cvtc = '?';
+ IRRoundingMode rm = Irrm_NEAREST;
+ switch (fld_op) {
+ /* Various kludges:
+ - The use of NEAREST for both the 'a' and 'n' cases,
+ since it doesn't take into account the nearest-even vs
+ nearest-away semantics.
+ - For the 'x' case, we don't signal inexactness.
+ */
+ case BITS3(0,1,0): cvtc = 'a'; rm = Irrm_NEAREST; break;
+ case BITS3(0,0,0): cvtc = 'n'; rm = Irrm_NEAREST; break;
+ case BITS3(1,1,1): cvtc = 'p'; rm = Irrm_PosINF; break;
+ case BITS3(1,0,1): cvtc = 'm'; rm = Irrm_NegINF; break;
+ case BITS3(0,1,1): cvtc = 'z'; rm = Irrm_ZERO; break;
+ case BITS3(0,0,1): cvtc = 'x'; rm = Irrm_NEAREST; break;
+ case BITS3(1,0,0):
+ case BITS3(1,1,0):
+ default: vassert(0);
+ }
+
+ IRTemp r0 = newTemp(Ity_F32);
+ IRTemp r1 = newTemp(Ity_F32);
+ IRTemp r2 = isQ ? newTemp(Ity_F32) : IRTemp_INVALID;
+ IRTemp r3 = isQ ? newTemp(Ity_F32) : IRTemp_INVALID;
+
+ IRExpr* rmE = mkU32((UInt)rm);
+ IROp rnd = Iop_RoundF32toInt;
+
+ assign(r0, binop(rnd, rmE, llGetFReg_up_to_64(mmF+0)));
+ assign(r1, binop(rnd, rmE, llGetFReg_up_to_64(mmF+1)));
+ if (isQ) {
+ assign(r2, binop(rnd, rmE, llGetFReg_up_to_64(mmF+2)));
+ assign(r3, binop(rnd, rmE, llGetFReg_up_to_64(mmF+3)));
+ }
+
+ llPutFReg_up_to_64(ddF+0, mkexpr(r0));
+ llPutFReg_up_to_64(ddF+1, mkexpr(r1));
+ if (isQ) {
+ llPutFReg_up_to_64(ddF+2, mkexpr(r2));
+ llPutFReg_up_to_64(ddF+3, mkexpr(r3));
+ }
+
+ HChar rch = isQ ? 'q' : 'd';
+ UInt sh = isQ ? 1 : 0;
+ DIP("vrint%c.f32.f32 %c%u, %c%u\n",
+ cvtc, rch, dd >> sh, rch, mm >> sh);
+ return True;
+ }
+ /* else fall through */
+ }
+
/* ---------- Doesn't match anything. ---------- */
return False;
@@ -15526,6 +16099,7 @@
dres.len = 4;
dres.continueAt = 0;
dres.jk_StopHere = Ijk_INVALID;
+ dres.hint = Dis_HintNone;
/* Set default actions for post-insn handling of writes to r15, if
required. */
@@ -18413,6 +18987,7 @@
dres.len = 2;
dres.continueAt = 0;
dres.jk_StopHere = Ijk_INVALID;
+ dres.hint = Dis_HintNone;
/* Set default actions for post-insn handling of writes to r15, if
required. */
@@ -20578,10 +21153,10 @@
&& rD != 15 && rN == 13 && imm5 <= 31 && how == 0) {
valid = True;
}
- /* also allow "sub.w reg, sp, reg lsl #N for N=0,1,2 or 3
+ /* also allow "sub.w reg, sp, reg lsl #N for N=0 .. 5
(T1) "SUB (SP minus register) */
if (!valid && INSN0(8,5) == BITS4(1,1,0,1) // sub
- && rD != 15 && rN == 13 && imm5 <= 3 && how == 0) {
+ && rD != 15 && rN == 13 && imm5 <= 5 && how == 0) {
valid = True;
}
if (valid) {
diff --git a/VEX/priv/guest_generic_bb_to_IR.c b/VEX/priv/guest_generic_bb_to_IR.c
index 779f8ae..6df594d 100644
--- a/VEX/priv/guest_generic_bb_to_IR.c
+++ b/VEX/priv/guest_generic_bb_to_IR.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -237,6 +237,13 @@
vassert((offB_GUEST_IP % 8) == 0);
}
+ /* Although we will try to disassemble up to vex_control.guest_max_insns
+ insns into the block, the individual insn assemblers may hint to us that a
+ disassembled instruction is verbose. In that case we will lower the limit
+ so as to ensure that the JIT doesn't run out of space. See bug 375839 for
+ the motivating example. */
+ Int guest_max_insns_really = vex_control.guest_max_insns;
+
/* Start a new, empty extent. */
vge->n_used = 1;
vge->base[0] = guest_IP_bbstart;
@@ -284,7 +291,7 @@
/* Process instructions. */
while (True) {
- vassert(n_instrs < vex_control.guest_max_insns);
+ vassert(n_instrs < guest_max_insns_really);
/* Regardless of what chase_into_ok says, is chasing permissible
at all right now? Set resteerOKfn accordingly. */
@@ -383,6 +390,23 @@
if (n_cond_resteers_allowed == 0)
vassert(dres.whatNext != Dis_ResteerC);
+ /* If the disassembly function passed us a hint, take note of it. */
+ if (LIKELY(dres.hint == Dis_HintNone)) {
+ /* Do nothing */
+ } else {
+ vassert(dres.hint == Dis_HintVerbose);
+ /* The current insn is known to be verbose. Lower the max insns limit
+ if necessary so as to avoid running the JIT out of space in the
+ event that we've encountered the start of a long sequence of them.
+ This is expected to be a very rare event. In any case the remaining
+ limit (30 insns) is still so high that most blocks will terminate
+ anyway before then. So this is very unlikely to give a perf hit in
+ practice. See bug 375839 for the motivating example. */
+ if (guest_max_insns_really > 30) {
+ guest_max_insns_really = 30;
+ }
+ }
+
/* Fill in the insn-mark length field. */
vassert(first_stmt_idx >= 0 && first_stmt_idx < irsb->stmts_used);
imark = irsb->stmts[first_stmt_idx];
@@ -435,7 +459,7 @@
case Dis_Continue:
vassert(dres.continueAt == 0);
vassert(dres.jk_StopHere == Ijk_INVALID);
- if (n_instrs < vex_control.guest_max_insns) {
+ if (n_instrs < guest_max_insns_really) {
/* keep going */
} else {
/* We have to stop. See comment above re irsb field
diff --git a/VEX/priv/guest_generic_bb_to_IR.h b/VEX/priv/guest_generic_bb_to_IR.h
index 78a5a87..ac87510 100644
--- a/VEX/priv/guest_generic_bb_to_IR.h
+++ b/VEX/priv/guest_generic_bb_to_IR.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -76,10 +76,16 @@
Dis_ResteerC: (speculatively, of course) followed a
conditional branch; continue at 'continueAt'
*/
- enum { Dis_StopHere, Dis_Continue,
+ enum { Dis_StopHere=0x10, Dis_Continue,
Dis_ResteerU, Dis_ResteerC } whatNext;
- /* For Dis_StopHere, we need to end the block and create a
+ /* Any other hints that we should feed back to the disassembler?
+ Dis_HintNone: no hint
+ Dis_HintVerbose: this insn potentially generates a lot of code
+ */
+ enum { Dis_HintNone=0x20, Dis_HintVerbose } hint;
+
+ /* For whatNext==Dis_StopHere, we need to end the block and create a
transfer to whatever the NIA is. That will have presumably
been set by the IR generated for this insn. So we need to
know the jump kind to use. Should Ijk_INVALID in other Dis_
@@ -89,7 +95,6 @@
/* For Dis_Resteer, this is the guest address we should continue
at. Otherwise ignored (should be zero). */
Addr continueAt;
-
}
DisResult;
diff --git a/VEX/priv/guest_generic_x87.c b/VEX/priv/guest_generic_x87.c
index 9f08352..d1979ef 100644
--- a/VEX/priv/guest_generic_x87.c
+++ b/VEX/priv/guest_generic_x87.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -797,7 +797,7 @@
switch (imm8) {
case 0x00: case 0x02:
case 0x08: case 0x0A: case 0x0C: case 0x0E:
- case 0x12: case 0x14:
+ case 0x10: case 0x12: case 0x14:
case 0x18: case 0x1A:
case 0x30: case 0x34:
case 0x38: case 0x3A:
diff --git a/VEX/priv/guest_generic_x87.h b/VEX/priv/guest_generic_x87.h
index 5a520ea..8183e35 100644
--- a/VEX/priv/guest_generic_x87.h
+++ b/VEX/priv/guest_generic_x87.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/VEX/priv/guest_mips_defs.h b/VEX/priv/guest_mips_defs.h
index 60db3b5..5ea213d 100644
--- a/VEX/priv/guest_mips_defs.h
+++ b/VEX/priv/guest_mips_defs.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 RT-RK
+ Copyright (C) 2010-2017 RT-RK
mips-valgrind@rt-rk.com
This program is free software; you can redistribute it and/or
@@ -40,7 +40,8 @@
/*--- mips to IR conversion ---*/
/*---------------------------------------------------------*/
-/* Convert one MIPS insn to IR. See the type DisOneInstrFn in bb_to_IR.h. */
+/* Convert one MIPS insn to IR. See the type DisOneInstrFn in
+ guest_generic_bb_to_IR.h. */
extern DisResult disInstr_MIPS ( IRSB* irbb,
Bool (*resteerOkFn) (void *, Addr),
Bool resteerCisOk,
@@ -93,11 +94,14 @@
SUBS, SUBD, DIVS
} flt_op;
-#if defined(__mips__) && ((defined(__mips_isa_rev) && __mips_isa_rev >= 2))
-extern UInt mips32_dirtyhelper_rdhwr ( UInt rt, UInt rd );
-extern ULong mips64_dirtyhelper_rdhwr ( ULong rt, ULong rd );
+#if defined (_MIPSEL)
+ #define MIPS_IEND Iend_LE
+#else
+ #define MIPS_IEND Iend_BE
#endif
+extern HWord mips_dirtyhelper_rdhwr ( UInt rd );
+
/* Calculate FCSR in fp32 mode. */
extern UInt mips_dirtyhelper_calculate_FCSR_fp32 ( void* guest_state, UInt fs,
UInt ft, flt_op op );
diff --git a/VEX/priv/guest_mips_helpers.c b/VEX/priv/guest_mips_helpers.c
index 07dccec..00a92c3 100644
--- a/VEX/priv/guest_mips_helpers.c
+++ b/VEX/priv/guest_mips_helpers.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 RT-RK
+ Copyright (C) 2010-2017 RT-RK
mips-valgrind@rt-rk.com
This program is free software; you can redistribute it and/or
@@ -167,6 +167,9 @@
vex_state->guest_CP0_status = 0;
+ vex_state->guest_LLaddr = 0xFFFFFFFF;
+ vex_state->guest_LLdata = 0;
+
/* MIPS32 DSP ASE(r2) specific registers */
vex_state->guest_DSPControl = 0; /* DSPControl register */
vex_state->guest_ac0 = 0; /* Accumulator 0 */
@@ -276,6 +279,9 @@
vex_state->guest_COND = 0;
vex_state->guest_CP0_status = MIPS_CP0_STATUS_FR;
+
+ vex_state->guest_LLaddr = 0xFFFFFFFFFFFFFFFFULL;
+ vex_state->guest_LLdata = 0;
}
/*-----------------------------------------------------------*/
@@ -418,17 +424,35 @@
}
};
-#if defined(__mips__) && ((defined(__mips_isa_rev) && __mips_isa_rev >= 2))
-UInt mips32_dirtyhelper_rdhwr ( UInt rt, UInt rd )
+#define ASM_VOLATILE_RDHWR(opcode) \
+ __asm__ __volatile__(".word 0x7C02003B | "#opcode" << 11 \n\t" \
+ : "+r" (x) : : \
+ )
+
+HWord mips_dirtyhelper_rdhwr ( UInt rd )
{
- UInt x = 0;
+#if defined(__mips__)
+ register HWord x __asm__("v0") = 0;
+
switch (rd) {
- case 1: /* x = SYNCI_StepSize() */
- __asm__ __volatile__("rdhwr %0, $1\n\t" : "=r" (x) );
+ case 0: /* x = CPUNum() */
+ ASM_VOLATILE_RDHWR(0); /* rdhwr v0, $0 */
+ break;
+
+ case 1: /* x = SYNCI_Step() */
+ ASM_VOLATILE_RDHWR(1); /* rdhwr v0, $1 */
+ break;
+
+ case 2: /* x = CC() */
+ ASM_VOLATILE_RDHWR(2); /* rdhwr v0, $2 */
+ break;
+
+ case 3: /* x = CCRes() */
+ ASM_VOLATILE_RDHWR(3); /* rdhwr v0, $3 */
break;
case 31: /* x = CVMX_get_cycles() */
- __asm__ __volatile__("rdhwr %0, $31\n\t" : "=r" (x) );
+ ASM_VOLATILE_RDHWR(31); /* rdhwr v0, $31 */
break;
default:
@@ -436,27 +460,10 @@
break;
}
return x;
-}
-
-ULong mips64_dirtyhelper_rdhwr ( ULong rt, ULong rd )
-{
- ULong x = 0;
- switch (rd) {
- case 1: /* x = SYNCI_StepSize() */
- __asm__ __volatile__("rdhwr %0, $1\n\t" : "=r" (x) );
- break;
-
- case 31: /* x = CVMX_get_cycles() */
- __asm__ __volatile__("rdhwr %0, $31\n\t" : "=r" (x) );
- break;
-
- default:
- vassert(0);
- break;
- }
- return x;
-}
+#else
+ return 0;
#endif
+}
#define ASM_VOLATILE_UNARY32(inst) \
__asm__ volatile(".set push" "\n\t" \
@@ -491,6 +498,7 @@
#define ASM_VOLATILE_UNARY64(inst) \
__asm__ volatile(".set push" "\n\t" \
".set hardfloat" "\n\t" \
+ ".set fp=64" "\n\t" \
"cfc1 $t0, $31" "\n\t" \
"ctc1 %2, $31" "\n\t" \
"ldc1 $f24, 0(%1)" "\n\t" \
@@ -619,45 +627,6 @@
case ROUNDWS:
ASM_VOLATILE_UNARY32(round.w.s)
break;
-#if ((__mips == 32) && defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) \
- || (__mips == 64)
- case CEILLS:
- ASM_VOLATILE_UNARY32(ceil.l.s)
- break;
- case CEILLD:
- ASM_VOLATILE_UNARY32_DOUBLE(ceil.l.d)
- break;
- case CVTDL:
- ASM_VOLATILE_UNARY32_DOUBLE(cvt.d.l)
- break;
- case CVTLS:
- ASM_VOLATILE_UNARY32(cvt.l.s)
- break;
- case CVTLD:
- ASM_VOLATILE_UNARY32_DOUBLE(cvt.l.d)
- break;
- case CVTSL:
- ASM_VOLATILE_UNARY32_DOUBLE(cvt.s.l)
- break;
- case FLOORLS:
- ASM_VOLATILE_UNARY32(floor.l.s)
- break;
- case FLOORLD:
- ASM_VOLATILE_UNARY32_DOUBLE(floor.l.d)
- break;
- case ROUNDLS:
- ASM_VOLATILE_UNARY32(round.l.s)
- break;
- case ROUNDLD:
- ASM_VOLATILE_UNARY32_DOUBLE(round.l.d)
- break;
- case TRUNCLS:
- ASM_VOLATILE_UNARY32(trunc.l.s)
- break;
- case TRUNCLD:
- ASM_VOLATILE_UNARY32_DOUBLE(trunc.l.d)
- break;
-#endif
case ADDS:
ASM_VOLATILE_BINARY32(add.s)
break;
@@ -687,7 +656,8 @@
flt_op inst )
{
UInt ret = 0;
-#if defined(__mips__)
+#if defined(__mips__) && ((__mips == 64) || \
+ (defined(__mips_isa_rev) && (__mips_isa_rev >= 2)))
#if defined(VGA_mips32)
VexGuestMIPS32State* guest_state = (VexGuestMIPS32State*)gs;
#else
@@ -738,8 +708,6 @@
case ROUNDWS:
ASM_VOLATILE_UNARY64(round.w.s)
break;
-#if ((__mips == 32) && defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) \
- || (__mips == 64)
case CEILLS:
ASM_VOLATILE_UNARY64(ceil.l.s)
break;
@@ -776,7 +744,6 @@
case TRUNCLD:
ASM_VOLATILE_UNARY64(trunc.l.d)
break;
-#endif
case ADDS:
ASM_VOLATILE_BINARY64(add.s)
break;
diff --git a/VEX/priv/guest_mips_toIR.c b/VEX/priv/guest_mips_toIR.c
index 776e6c5..a73b5dc 100644
--- a/VEX/priv/guest_mips_toIR.c
+++ b/VEX/priv/guest_mips_toIR.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 RT-RK
+ Copyright (C) 2010-2017 RT-RK
mips-valgrind@rt-rk.com
This program is free software; you can redistribute it and/or
@@ -549,6 +549,9 @@
dres.jk_StopHere = Ijk_SigILL; \
dres.whatNext = Dis_StopHere;
+#define LLADDR_INVALID \
+ (mode64 ? mkU64(0xFFFFFFFFFFFFFFFFULL) : mkU32(0xFFFFFFFF))
+
/*------------------------------------------------------------*/
/*--- Field helpers ---*/
/*------------------------------------------------------------*/
@@ -1087,6 +1090,22 @@
return IRExpr_Get(offsetof(VexGuestMIPS32State, guest_FCSR), Ity_I32);
}
+static IRExpr *getLLaddr(void)
+{
+ if (mode64)
+ return IRExpr_Get(offsetof(VexGuestMIPS64State, guest_LLaddr), Ity_I64);
+ else
+ return IRExpr_Get(offsetof(VexGuestMIPS32State, guest_LLaddr), Ity_I32);
+}
+
+static IRExpr *getLLdata(void)
+{
+ if (mode64)
+ return IRExpr_Get(offsetof(VexGuestMIPS64State, guest_LLdata), Ity_I64);
+ else
+ return IRExpr_Get(offsetof(VexGuestMIPS32State, guest_LLdata), Ity_I32);
+}
+
/* Get byte from register reg, byte pos from 0 to 3 (or 7 for MIPS64) . */
static IRExpr *getByteFromReg(UInt reg, UInt byte_pos)
{
@@ -1109,6 +1128,22 @@
stmt(IRStmt_Put(offsetof(VexGuestMIPS32State, guest_FCSR), e));
}
+static void putLLaddr(IRExpr * e)
+{
+ if (mode64)
+ stmt(IRStmt_Put(offsetof(VexGuestMIPS64State, guest_LLaddr), e));
+ else
+ stmt(IRStmt_Put(offsetof(VexGuestMIPS32State, guest_LLaddr), e));
+}
+
+static void putLLdata(IRExpr * e)
+{
+ if (mode64)
+ stmt(IRStmt_Put(offsetof(VexGuestMIPS64State, guest_LLdata), e));
+ else
+ stmt(IRStmt_Put(offsetof(VexGuestMIPS32State, guest_LLdata), e));
+}
+
/* fs - fpu source register number.
inst - fpu instruction that needs to be executed.
sz32 - size of source register.
@@ -1119,12 +1154,12 @@
{
IRDirty *d;
IRTemp fcsr = newTemp(Ity_I32);
- /* IRExpr_BBPTR() => Need to pass pointer to guest state to helper. */
+ /* IRExpr_GSPTR() => Need to pass pointer to guest state to helper. */
if (fp_mode64)
d = unsafeIRDirty_1_N(fcsr, 0,
"mips_dirtyhelper_calculate_FCSR_fp64",
&mips_dirtyhelper_calculate_FCSR_fp64,
- mkIRExprVec_4(IRExpr_BBPTR(),
+ mkIRExprVec_4(IRExpr_GSPTR(),
mkU32(fs),
mkU32(ft),
mkU32(inst)));
@@ -1132,7 +1167,7 @@
d = unsafeIRDirty_1_N(fcsr, 0,
"mips_dirtyhelper_calculate_FCSR_fp32",
&mips_dirtyhelper_calculate_FCSR_fp32,
- mkIRExprVec_4(IRExpr_BBPTR(),
+ mkIRExprVec_4(IRExpr_GSPTR(),
mkU32(fs),
mkU32(ft),
mkU32(inst)));
@@ -1339,6 +1374,16 @@
return src;
}
+/* Convenience function to move to next instruction on condition. */
+static void mips_next_insn_if(IRExpr *condition) {
+ vassert(typeOfIRExpr(irsb->tyenv, condition) == Ity_I1);
+
+ stmt(IRStmt_Exit(condition, Ijk_Boring,
+ mode64 ? IRConst_U64(guest_PC_curr_instr + 4) :
+ IRConst_U32(guest_PC_curr_instr + 4),
+ OFFB_PC));
+}
+
static IRExpr *dis_branch_likely(IRExpr * guard, UInt imm)
{
ULong branch_offset;
@@ -2187,17 +2232,19 @@
}
/* Based on s390_irgen_load_and_add32. */
-static void mips_irgen_load_and_add32(IRTemp op1addr, IRTemp new_val,
- UChar rd, Bool putIntoRd)
+static void mips_load_store32(IRTemp op1addr, IRTemp new_val,
+ IRTemp expd, UChar rd, Bool putIntoRd)
{
IRCAS *cas;
IRTemp old_mem = newTemp(Ity_I32);
- IRTemp expd = newTemp(Ity_I32);
-
- assign(expd, load(Ity_I32, mkexpr(op1addr)));
+ IRType ty = mode64 ? Ity_I64 : Ity_I32;
cas = mkIRCAS(IRTemp_INVALID, old_mem,
+#if defined (_MIPSEL)
Iend_LE, mkexpr(op1addr),
+#else /* _MIPSEB */
+ Iend_BE, mkexpr(op1addr),
+#endif
NULL, mkexpr(expd), /* expected value */
NULL, mkexpr(new_val) /* new value */);
stmt(IRStmt_CAS(cas));
@@ -2206,21 +2253,22 @@
Otherwise, it did not */
jump_back(binop(Iop_CmpNE32, mkexpr(old_mem), mkexpr(expd)));
if (putIntoRd)
- putIReg(rd, mkWidenFrom32(Ity_I64, mkexpr(old_mem), True));
+ putIReg(rd, mkWidenFrom32(ty, mkexpr(old_mem), True));
}
/* Based on s390_irgen_load_and_add64. */
-static void mips_irgen_load_and_add64(IRTemp op1addr, IRTemp new_val,
- UChar rd, Bool putIntoRd)
+static void mips_load_store64(IRTemp op1addr, IRTemp new_val,
+ IRTemp expd, UChar rd, Bool putIntoRd)
{
IRCAS *cas;
IRTemp old_mem = newTemp(Ity_I64);
- IRTemp expd = newTemp(Ity_I64);
-
- assign(expd, load(Ity_I64, mkexpr(op1addr)));
-
+ vassert(mode64);
cas = mkIRCAS(IRTemp_INVALID, old_mem,
+#if defined (_MIPSEL)
Iend_LE, mkexpr(op1addr),
+#else /* _MIPSEB */
+ Iend_BE, mkexpr(op1addr),
+#endif
NULL, mkexpr(expd), /* expected value */
NULL, mkexpr(new_val) /* new value */);
stmt(IRStmt_CAS(cas));
@@ -2267,12 +2315,14 @@
case 0x18: { /* Store Atomic Add Word - SAA; Cavium OCTEON */
DIP("saa r%u, (r%u)", regRt, regRs);
IRTemp addr = newTemp(Ity_I64);
- IRTemp new = newTemp(Ity_I32);
- assign (addr, getIReg(regRs));
- assign(new, binop(Iop_Add32,
- load(Ity_I32, mkexpr(addr)),
- mkNarrowTo32(ty, getIReg(regRt))));
- mips_irgen_load_and_add32(addr, new, 0, False);
+ IRTemp new_val = newTemp(Ity_I32);
+ IRTemp old = newTemp(Ity_I32);
+ assign(addr, getIReg(regRs));
+ assign(old, load(Ity_I32, mkexpr(addr)));
+ assign(new_val, binop(Iop_Add32,
+ mkexpr(old),
+ mkNarrowTo32(ty, getIReg(regRt))));
+ mips_load_store32(addr, new_val, old, 0, False);
break;
}
@@ -2280,12 +2330,14 @@
case 0x19: {
DIP( "saad r%u, (r%u)", regRt, regRs);
IRTemp addr = newTemp(Ity_I64);
- IRTemp new = newTemp(Ity_I64);
- assign (addr, getIReg(regRs));
- assign(new, binop(Iop_Add64,
- load(Ity_I64, mkexpr(addr)),
- getIReg(regRt)));
- mips_irgen_load_and_add64(addr, new, 0, False);
+ IRTemp new_val = newTemp(Ity_I64);
+ IRTemp old = newTemp(Ity_I64);
+ assign(addr, getIReg(regRs));
+ assign(old, load(Ity_I64, mkexpr(addr)));
+ assign(new_val, binop(Iop_Add64,
+ mkexpr(old),
+ getIReg(regRt)));
+ mips_load_store64(addr, new_val, old, 0, False);
break;
}
@@ -2298,121 +2350,145 @@
/* Load Atomic Increment Word - LAI; Cavium OCTEON2 */
case 0x02: {
DIP("lai r%u,(r%u)\n", regRd, regRs);
- IRTemp new = newTemp(Ity_I32);
+ IRTemp new_val = newTemp(Ity_I32);
+ IRTemp old = newTemp(Ity_I32);
assign(addr, getIReg(regRs));
- assign(new, binop(Iop_Add32,
- load(Ity_I32, mkexpr(addr)),
- mkU32(1)));
- mips_irgen_load_and_add32(addr, new, regRd, True);
+ assign(old, load(Ity_I32, mkexpr(addr)));
+ assign(new_val, binop(Iop_Add32,
+ mkexpr(old),
+ mkU32(1)));
+ mips_load_store32(addr, new_val, old, regRd, True);
break;
}
/* Load Atomic Increment Doubleword - LAID; Cavium OCTEON2 */
case 0x03: {
DIP("laid r%u,(r%u)\n", regRd, regRs);
- IRTemp new = newTemp(Ity_I64);
+ IRTemp new_val = newTemp(Ity_I64);
+ IRTemp old = newTemp(Ity_I64);
assign(addr, getIReg(regRs));
- assign(new, binop(Iop_Add64,
- load(Ity_I64, mkexpr(addr)),
- mkU64(1)));
- mips_irgen_load_and_add64(addr, new, regRd, True);
+ assign(old, load(Ity_I64, mkexpr(addr)));
+ assign(new_val, binop(Iop_Add64,
+ mkexpr(old),
+ mkU64(1)));
+ mips_load_store64(addr, new_val, old, regRd, True);
break;
}
/* Load Atomic Decrement Word - LAD; Cavium OCTEON2 */
case 0x06: {
DIP("lad r%u,(r%u)\n", regRd, regRs);
- IRTemp new = newTemp(Ity_I32);
+ IRTemp new_val = newTemp(Ity_I32);
+ IRTemp old = newTemp(Ity_I32);
assign(addr, getIReg(regRs));
- assign(new, binop(Iop_Sub32,
- load(Ity_I32, mkexpr(addr)),
- mkU32(1)));
- mips_irgen_load_and_add32(addr, new, regRd, True);
+ assign(old, load(Ity_I32, mkexpr(addr)));
+ assign(new_val, binop(Iop_Sub32,
+ mkexpr(old),
+ mkU32(1)));
+ mips_load_store32(addr, new_val, old, regRd, True);
break;
}
/* Load Atomic Decrement Doubleword - LADD; Cavium OCTEON2 */
case 0x07: {
DIP("ladd r%u,(r%u)\n", regRd, regRs);
- IRTemp new = newTemp(Ity_I64);
- assign (addr, getIReg(regRs));
- assign(new, binop(Iop_Sub64,
- load(Ity_I64, mkexpr(addr)),
- mkU64(1)));
- mips_irgen_load_and_add64(addr, new, regRd, True);
+ IRTemp new_val = newTemp(Ity_I64);
+ IRTemp old = newTemp(Ity_I64);
+ assign(addr, getIReg(regRs));
+ assign(old, load(Ity_I64, mkexpr(addr)));
+ assign(new_val, binop(Iop_Sub64,
+ mkexpr(old),
+ mkU64(1)));
+ mips_load_store64(addr, new_val, old, regRd, True);
break;
}
/* Load Atomic Set Word - LAS; Cavium OCTEON2 */
case 0x0a: {
DIP("las r%u,(r%u)\n", regRd, regRs);
- IRTemp new = newTemp(Ity_I32);
+ IRTemp new_val = newTemp(Ity_I32);
+ IRTemp old = newTemp(Ity_I32);
assign(addr, getIReg(regRs));
- assign(new, mkU32(0xffffffff));
- mips_irgen_load_and_add32(addr, new, regRd, True);
+ assign(new_val, mkU32(0xffffffff));
+ assign(old, load(Ity_I32, mkexpr(addr)));
+ mips_load_store32(addr, new_val, old, regRd, True);
break;
}
/* Load Atomic Set Doubleword - LASD; Cavium OCTEON2 */
case 0x0b: {
DIP("lasd r%u,(r%u)\n", regRd, regRs);
- IRTemp new = newTemp(Ity_I64);
- assign (addr, getIReg(regRs));
- assign(new, mkU64(0xffffffffffffffffULL));
- mips_irgen_load_and_add64(addr, new, regRd, True);
+ IRTemp new_val = newTemp(Ity_I64);
+ IRTemp old = newTemp(Ity_I64);
+ assign(addr, getIReg(regRs));
+ assign(new_val, mkU64(0xffffffffffffffffULL));
+ assign(old, load(Ity_I64, mkexpr(addr)));
+ mips_load_store64(addr, new_val, old, regRd, True);
break;
}
/* Load Atomic Clear Word - LAC; Cavium OCTEON2 */
case 0x0e: {
DIP("lac r%u,(r%u)\n", regRd, regRs);
- IRTemp new = newTemp(Ity_I32);
- assign (addr, getIReg(regRs));
- assign(new, mkU32(0));
- mips_irgen_load_and_add32(addr, new, regRd, True);
+ IRTemp new_val = newTemp(Ity_I32);
+ IRTemp old = newTemp(Ity_I32);
+ assign(addr, getIReg(regRs));
+ assign(new_val, mkU32(0));
+ assign(old, load(Ity_I32, mkexpr(addr)));
+ mips_load_store32(addr, new_val, old, regRd, True);
break;
}
/* Load Atomic Clear Doubleword - LACD; Cavium OCTEON2 */
case 0x0f: {
DIP("lacd r%u,(r%u)\n", regRd, regRs);
- IRTemp new = newTemp(Ity_I64);
+ IRTemp new_val = newTemp(Ity_I64);
+ IRTemp old = newTemp(Ity_I64);
assign(addr, getIReg(regRs));
- assign(new, mkU64(0));
- mips_irgen_load_and_add64(addr, new, regRd, True);
+ assign(new_val, mkU64(0));
+ assign(old, load(Ity_I64, mkexpr(addr)));
+ mips_load_store64(addr, new_val, old, regRd, True);
break;
}
/* Load Atomic Add Word - LAA; Cavium OCTEON2 */
case 0x12: {
DIP("laa r%u,(r%u),r%u\n", regRd, regRs, regRt);
- IRTemp new = newTemp(Ity_I32);
+ IRTemp new_val = newTemp(Ity_I32);
+ IRTemp old = newTemp(Ity_I32);
assign(addr, getIReg(regRs));
- assign(new, binop(Iop_Add32,
- load(Ity_I32, mkexpr(addr)),
- mkNarrowTo32(ty, getIReg(regRt))));
- mips_irgen_load_and_add32(addr, new, regRd, True);
+ assign(old, load(Ity_I32, mkexpr(addr)));
+ assign(new_val, binop(Iop_Add32,
+ mkexpr(old),
+ mkNarrowTo32(ty, getIReg(regRt))));
+ mips_load_store32(addr, new_val, old, regRd, True);
break;
}
/* Load Atomic Add Doubleword - LAAD; Cavium OCTEON2 */
case 0x13: {
DIP("laad r%u,(r%u),r%u\n", regRd, regRs, regRt);
- IRTemp new = newTemp(Ity_I64);
- assign (addr, getIReg(regRs));
- assign(new, binop(Iop_Add64,
- load(Ity_I64, mkexpr(addr)),
- getIReg(regRt)));
- mips_irgen_load_and_add64(addr, new, regRd, True);
+ IRTemp new_val = newTemp(Ity_I64);
+ IRTemp old = newTemp(Ity_I64);
+ assign(addr, getIReg(regRs));
+ assign(old, load(Ity_I64, mkexpr(addr)));
+ assign(new_val, binop(Iop_Add64,
+ load(Ity_I64, mkexpr(addr)),
+ getIReg(regRt)));
+ mips_load_store64(addr, new_val, old, regRd, True);
break;
}
/* Load Atomic Swap Word - LAW; Cavium OCTEON2 */
case 0x16: {
DIP("law r%u,(r%u)\n", regRd, regRs);
- IRTemp new = newTemp(Ity_I32);
+ IRTemp new_val = newTemp(Ity_I32);
+ IRTemp old = newTemp(Ity_I32);
assign(addr, getIReg(regRs));
- assign(new, mkNarrowTo32(ty, getIReg(regRt)));
- mips_irgen_load_and_add32(addr, new, regRd, True);
+ assign(new_val, mkNarrowTo32(ty, getIReg(regRt)));
+ assign(old, load(Ity_I32, mkexpr(addr)));
+ mips_load_store32(addr, new_val, old, regRd, True);
break;
}
/* Load Atomic Swap Doubleword - LAWD; Cavium OCTEON2 */
case 0x17: {
DIP("lawd r%u,(r%u)\n", regRd, regRs);
- IRTemp new = newTemp(Ity_I64);
+ IRTemp new_val = newTemp(Ity_I64);
+ IRTemp old = newTemp(Ity_I64);
assign(addr, getIReg(regRs));
- assign(new, getIReg(regRt));
- mips_irgen_load_and_add64(addr, new, regRd, True);
+ assign(new_val, getIReg(regRt));
+ assign(old, load(Ity_I64, mkexpr(addr)));
+ mips_load_store64(addr, new_val, old, regRd, True);
break;
}
default:
@@ -12056,6 +12132,7 @@
dres.len = 0;
dres.continueAt = 0;
dres.jk_StopHere = Ijk_INVALID;
+ dres.hint = Dis_HintNone;
delay_slot_branch = likely_delay_slot = delay_slot_jump = False;
@@ -13013,12 +13090,16 @@
case 0x15: /* L */
DIP("cvt.s.l %u, %u", fd, fs);
- calculateFCSR(fs, 0, CVTSL, False, 1);
- t0 = newTemp(Ity_I64);
- assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs)));
+ if (fp_mode64) {
+ calculateFCSR(fs, 0, CVTSL, False, 1);
+ t0 = newTemp(Ity_I64);
+ assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs)));
- putFReg(fd, mkWidenFromF32(tyF, binop(Iop_I64StoF32,
- get_IR_roundingmode(), mkexpr(t0))));
+ putFReg(fd, mkWidenFromF32(tyF, binop(Iop_I64StoF32,
+ get_IR_roundingmode(), mkexpr(t0))));
+ } else {
+ ILLEGAL_INSTRUCTON;
+ }
break;
default:
@@ -15010,41 +15091,31 @@
goto decode_failure;;
}
break;
- case 0x3B: { /* RDHWR */
+ case 0x3B: /* RDHWR */
DIP("rdhwr r%u, r%u", rt, rd);
+ if (VEX_MIPS_CPU_HAS_MIPS32R2(archinfo->hwcaps) ||
+ (VEX_MIPS_COMP_ID(archinfo->hwcaps) == VEX_PRID_COMP_BROADCOM)) {
if (rd == 29) {
putIReg(rt, getULR());
-#if defined(__mips__) && ((defined(__mips_isa_rev) && __mips_isa_rev >= 2))
- } else if (rd == 1
+ } else if (rd <= 3
|| (rd == 31
&& VEX_MIPS_COMP_ID(archinfo->hwcaps)
== VEX_PRID_COMP_CAVIUM)) {
- if (mode64) {
- IRTemp val = newTemp(Ity_I64);
- IRExpr** args = mkIRExprVec_2 (mkU64(rt), mkU64(rd));
- IRDirty *d = unsafeIRDirty_1_N(val,
- 0,
- "mips64_dirtyhelper_rdhwr",
- &mips64_dirtyhelper_rdhwr,
- args);
- stmt(IRStmt_Dirty(d));
- putIReg(rt, mkexpr(val));
- } else {
- IRTemp val = newTemp(Ity_I32);
- IRExpr** args = mkIRExprVec_2 (mkU32(rt), mkU32(rd));
- IRDirty *d = unsafeIRDirty_1_N(val,
- 0,
- "mips32_dirtyhelper_rdhwr",
- &mips32_dirtyhelper_rdhwr,
- args);
- stmt(IRStmt_Dirty(d));
- putIReg(rt, mkexpr(val));
- }
-#endif
+ IRExpr** arg = mkIRExprVec_1(mkU32(rd));
+ IRTemp val = newTemp(ty);
+ IRDirty *d = unsafeIRDirty_1_N(val,
+ 0,
+ "mips_dirtyhelper_rdhwr",
+ &mips_dirtyhelper_rdhwr,
+ arg);
+ stmt(IRStmt_Dirty(d));
+ putIReg(rt, mkexpr(val));
} else
goto decode_failure;
- break;
+ } else {
+ ILLEGAL_INSTRUCTON;
}
+ break;
case 0x04: /* INS */
msb = get_msb(cins);
lsb = get_lsb(cins);
@@ -16904,64 +16975,106 @@
putIReg(rt, mkWidenFrom32(ty, load(Ity_I32, mkexpr(t1)), False));
break;
- case 0x30: /* LL / LWC0 */
+ case 0x30: /* LL */
DIP("ll r%u, %u(r%u)", rt, imm, rs);
LOAD_STORE_PATTERN;
-
- t2 = newTemp(Ity_I32);
-#if defined (_MIPSEL)
- stmt(IRStmt_LLSC(Iend_LE, t2, mkexpr(t1), NULL /* this is a load */ ));
-#elif defined (_MIPSEB)
- stmt(IRStmt_LLSC(Iend_BE, t2, mkexpr(t1), NULL /* this is a load */ ));
-#endif
- if (mode64)
- putIReg(rt, unop(Iop_32Sto64, mkexpr(t2)));
- else
+ if (abiinfo->guest__use_fallback_LLSC) {
+ t2 = newTemp(ty);
+ assign(t2, mkWidenFrom32(ty, load(Ity_I32, mkexpr(t1)), True));
+ putLLaddr(mkexpr(t1));
+ putLLdata(mkexpr(t2));
putIReg(rt, mkexpr(t2));
+ } else {
+ t2 = newTemp(Ity_I32);
+ stmt(IRStmt_LLSC(MIPS_IEND, t2, mkexpr(t1), NULL));
+ putIReg(rt, mkWidenFrom32(ty, mkexpr(t2), True));
+ }
break;
case 0x34: /* Load Linked Doubleword - LLD; MIPS64 */
DIP("lld r%u, %u(r%u)", rt, imm, rs);
- LOAD_STORE_PATTERN;
-
- t2 = newTemp(Ity_I64);
-#if defined (_MIPSEL)
- stmt(IRStmt_LLSC
- (Iend_LE, t2, mkexpr(t1), NULL /* this is a load */ ));
-#elif defined (_MIPSEB)
- stmt(IRStmt_LLSC
- (Iend_BE, t2, mkexpr(t1), NULL /* this is a load */ ));
-#endif
-
- putIReg(rt, mkexpr(t2));
+ if (mode64) {
+ LOAD_STORE_PATTERN;
+ t2 = newTemp(Ity_I64);
+ if (abiinfo->guest__use_fallback_LLSC) {
+ assign(t2, load(Ity_I64, mkexpr(t1)));
+ putLLaddr(mkexpr(t1));
+ putLLdata(mkexpr(t2));
+ } else {
+ stmt(IRStmt_LLSC(MIPS_IEND, t2, mkexpr(t1), NULL));
+ }
+ putIReg(rt, mkexpr(t2));
+ } else {
+ ILLEGAL_INSTRUCTON;
+ }
break;
- case 0x38: /* SC / SWC0 */
+ case 0x38: /* SC */
DIP("sc r%u, %u(r%u)", rt, imm, rs);
- LOAD_STORE_PATTERN;
-
t2 = newTemp(Ity_I1);
-#if defined (_MIPSEL)
- stmt(IRStmt_LLSC(Iend_LE, t2, mkexpr(t1), mkNarrowTo32(ty, getIReg(rt))));
-#elif defined (_MIPSEB)
- stmt(IRStmt_LLSC(Iend_BE, t2, mkexpr(t1), mkNarrowTo32(ty, getIReg(rt))));
-#endif
+ LOAD_STORE_PATTERN;
+ if (abiinfo->guest__use_fallback_LLSC) {
+ t3 = newTemp(Ity_I32);
+ assign(t2, binop(mode64 ? Iop_CmpNE64 : Iop_CmpNE32,
+ mkexpr(t1), getLLaddr()));
+ assign(t3, mkNarrowTo32(ty, getIReg(rt)));
+ putLLaddr(LLADDR_INVALID);
+ putIReg(rt, getIReg(0));
- putIReg(rt, unop(mode64 ? Iop_1Uto64 : Iop_1Uto32, mkexpr(t2)));
+ mips_next_insn_if(mkexpr(t2));
+
+ t4 = newTemp(Ity_I32);
+ t5 = newTemp(Ity_I32);
+
+ assign(t5, mkNarrowTo32(ty, getLLdata()));
+
+ stmt(IRStmt_CAS(mkIRCAS(IRTemp_INVALID, t4, /* old_mem */
+ MIPS_IEND, mkexpr(t1), /* addr */
+ NULL, mkexpr(t5), /* expected value */
+ NULL, mkexpr(t3) /* new value */)));
+
+ putIReg(rt, unop(mode64 ? Iop_1Uto64 : Iop_1Uto32,
+ binop(Iop_CmpEQ32, mkexpr(t4), mkexpr(t5))));
+ } else {
+ stmt(IRStmt_LLSC(MIPS_IEND, t2, mkexpr(t1),
+ mkNarrowTo32(ty, getIReg(rt))));
+ putIReg(rt, unop(mode64 ? Iop_1Uto64 : Iop_1Uto32, mkexpr(t2)));
+ }
break;
case 0x3C: /* Store Conditional Doubleword - SCD; MIPS64 */
- DIP("sdc r%u, %u(r%u)", rt, imm, rs);
- LOAD_STORE_PATTERN;
+ DIP("scd r%u, %u(r%u)", rt, imm, rs);
+ if (mode64) {
+ t2 = newTemp(Ity_I1);
+ LOAD_STORE_PATTERN;
+ if (abiinfo->guest__use_fallback_LLSC) {
+ t3 = newTemp(Ity_I64);
+ assign(t2, binop(Iop_CmpNE64, mkexpr(t1), getLLaddr()));
+ assign(t3, getIReg(rt));
+ putLLaddr(LLADDR_INVALID);
+ putIReg(rt, getIReg(0));
- t2 = newTemp(Ity_I1);
-#if defined (_MIPSEL)
- stmt(IRStmt_LLSC(Iend_LE, t2, mkexpr(t1), getIReg(rt)));
-#elif defined (_MIPSEB)
- stmt(IRStmt_LLSC(Iend_BE, t2, mkexpr(t1), getIReg(rt)));
-#endif
+ mips_next_insn_if(mkexpr(t2));
- putIReg(rt, unop(Iop_1Uto64, mkexpr(t2)));
+ t4 = newTemp(Ity_I64);
+ t5 = newTemp(Ity_I64);
+
+ assign(t5, getLLdata());
+
+ stmt(IRStmt_CAS(mkIRCAS(IRTemp_INVALID, t4, /* old_mem */
+ MIPS_IEND, mkexpr(t1), /* addr */
+ NULL, mkexpr(t5), /* expected value */
+ NULL, mkexpr(t3) /* new value */)));
+
+ putIReg(rt, unop(Iop_1Uto64,
+ binop(Iop_CmpEQ64, mkexpr(t4), mkexpr(t5))));
+ } else {
+ stmt(IRStmt_LLSC(MIPS_IEND, t2, mkexpr(t1), getIReg(rt)));
+ putIReg(rt, unop(Iop_1Uto64, mkexpr(t2)));
+ }
+ } else {
+ ILLEGAL_INSTRUCTON;
+ }
break;
case 0x37: /* Load Doubleword - LD; MIPS64 */
@@ -17130,7 +17243,10 @@
break;
case Dis_ResteerU:
case Dis_ResteerC:
- putPC(mkU32(dres.continueAt));
+ if (mode64)
+ putPC(mkU64(dres.continueAt));
+ else
+ putPC(mkU32(dres.continueAt));
break;
case Dis_StopHere:
break;
@@ -17185,6 +17301,8 @@
mode64 = guest_arch != VexArchMIPS32;
fp_mode64 = abiinfo->guest_mips_fp_mode64;
+ vassert(VEX_MIPS_HOST_FP_MODE(archinfo->hwcaps) >= fp_mode64);
+
guest_code = guest_code_IN;
irsb = irsb_IN;
host_endness = host_endness_IN;
diff --git a/VEX/priv/guest_ppc_defs.h b/VEX/priv/guest_ppc_defs.h
index 008418d..fe411f7 100644
--- a/VEX/priv/guest_ppc_defs.h
+++ b/VEX/priv/guest_ppc_defs.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -49,7 +49,7 @@
/*---------------------------------------------------------*/
/* Convert one ppc insn to IR. See the type DisOneInstrFn in
- bb_to_IR.h. */
+ guest_generic_bb_to_IR.h. */
extern
DisResult disInstr_PPC ( IRSB* irbb,
Bool (*resteerOkFn) ( void*, Addr ),
diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c
index 0a4a31c..8230d65 100644
--- a/VEX/priv/guest_ppc_helpers.c
+++ b/VEX/priv/guest_ppc_helpers.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -537,6 +537,8 @@
w |= ( (((UInt)vex_state->guest_XER_SO) & 0x1) << 31 );
w |= ( (((UInt)vex_state->guest_XER_OV) & 0x1) << 30 );
w |= ( (((UInt)vex_state->guest_XER_CA) & 0x1) << 29 );
+ w |= ( (((UInt)vex_state->guest_XER_OV32) & 0x1) << 19 );
+ w |= ( (((UInt)vex_state->guest_XER_CA32) & 0x1) << 18 );
return w;
}
@@ -550,6 +552,8 @@
w |= ( (((UInt)vex_state->guest_XER_SO) & 0x1) << 31 );
w |= ( (((UInt)vex_state->guest_XER_OV) & 0x1) << 30 );
w |= ( (((UInt)vex_state->guest_XER_CA) & 0x1) << 29 );
+ w |= ( (((UInt)vex_state->guest_XER_OV32) & 0x1) << 19 );
+ w |= ( (((UInt)vex_state->guest_XER_CA32) & 0x1) << 18 );
return w;
}
@@ -562,6 +566,8 @@
vex_state->guest_XER_SO = toUChar((xer_native >> 31) & 0x1);
vex_state->guest_XER_OV = toUChar((xer_native >> 30) & 0x1);
vex_state->guest_XER_CA = toUChar((xer_native >> 29) & 0x1);
+ vex_state->guest_XER_OV32 = toUChar((xer_native >> 19) & 0x1);
+ vex_state->guest_XER_CA32 = toUChar((xer_native >> 18) & 0x1);
}
/* VISIBLE TO LIBVEX CLIENT */
@@ -573,6 +579,8 @@
vex_state->guest_XER_SO = toUChar((xer_native >> 31) & 0x1);
vex_state->guest_XER_OV = toUChar((xer_native >> 30) & 0x1);
vex_state->guest_XER_CA = toUChar((xer_native >> 29) & 0x1);
+ vex_state->guest_XER_OV32 = toUChar((xer_native >> 19) & 0x1);
+ vex_state->guest_XER_CA32 = toUChar((xer_native >> 18) & 0x1);
}
/* VISIBLE TO LIBVEX CLIENT */
@@ -696,6 +704,9 @@
vex_state->guest_XER_CA = 0;
vex_state->guest_XER_BC = 0;
+ vex_state->guest_XER_OV32 = 0;
+ vex_state->guest_XER_CA32 = 0;
+
vex_state->guest_CR0_321 = 0;
vex_state->guest_CR0_0 = 0;
vex_state->guest_CR1_321 = 0;
@@ -740,7 +751,7 @@
vex_state->guest_PSPB = 0x100; // an arbitrary non-zero value to start with
vex_state->padding1 = 0;
- vex_state->padding2 = 0;
+ /* vex_state->padding2 = 0; currently not used */
}
diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index c393740..e16e837 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -239,6 +239,9 @@
}
}
+/* The OV32 and CA32 bits were added with ISA3.0 */
+static Bool OV32_CA32_supported = False;
+
#define SIGN_BIT 0x8000000000000000ULL
#define SIGN_MASK 0x7fffffffffffffffULL
#define SIGN_BIT32 0x80000000
@@ -273,7 +276,9 @@
#define OFFB_CTR offsetofPPCGuestState(guest_CTR)
#define OFFB_XER_SO offsetofPPCGuestState(guest_XER_SO)
#define OFFB_XER_OV offsetofPPCGuestState(guest_XER_OV)
+#define OFFB_XER_OV32 offsetofPPCGuestState(guest_XER_OV32)
#define OFFB_XER_CA offsetofPPCGuestState(guest_XER_CA)
+#define OFFB_XER_CA32 offsetofPPCGuestState(guest_XER_CA32)
#define OFFB_XER_BC offsetofPPCGuestState(guest_XER_BC)
#define OFFB_FPROUND offsetofPPCGuestState(guest_FPROUND)
#define OFFB_DFPROUND offsetofPPCGuestState(guest_DFPROUND)
@@ -2201,20 +2206,48 @@
static void putXER_OV ( IRExpr* e )
{
+ /* Interface to write XER[OV] */
IRExpr* ov;
vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I8);
ov = binop(Iop_And8, e, mkU8(1));
stmt( IRStmt_Put( OFFB_XER_OV, ov ) );
}
+static void putXER_OV32 ( IRExpr* e )
+{
+ /*Interface to write XER[OV32] */
+ IRExpr* ov;
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I8);
+ ov = binop(Iop_And8, e, mkU8(1));
+
+ /* The OV32 bit was added to XER in ISA 3.0. Do not write unless we
+ * ISA 3.0 or beyond is supported. */
+ if( OV32_CA32_supported )
+ stmt( IRStmt_Put( OFFB_XER_OV32, ov ) );
+}
+
static void putXER_CA ( IRExpr* e )
{
+ /* Interface to write XER[CA] */
IRExpr* ca;
vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I8);
ca = binop(Iop_And8, e, mkU8(1));
stmt( IRStmt_Put( OFFB_XER_CA, ca ) );
}
+static void putXER_CA32 ( IRExpr* e )
+{
+ /* Interface to write XER[CA32] */
+ IRExpr* ca;
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I8);
+ ca = binop(Iop_And8, e, mkU8(1));
+
+ /* The CA32 bit was added to XER in ISA 3.0. Do not write unless we
+ * ISA 3.0 or beyond is supported. */
+ if( OV32_CA32_supported )
+ stmt( IRStmt_Put( OFFB_XER_CA32, ca ) );
+}
+
static void putXER_BC ( IRExpr* e )
{
IRExpr* bc;
@@ -2228,7 +2261,7 @@
return IRExpr_Get( OFFB_XER_SO, Ity_I8 );
}
-static IRExpr* /* :: Ity_I32 */ getXER_SO32 ( void )
+static IRExpr* /* :: Ity_I32 */ getXER_SO_32 ( void )
{
return binop( Iop_And32, unop(Iop_8Uto32, getXER_SO()), mkU32(1) );
}
@@ -2238,23 +2271,43 @@
return IRExpr_Get( OFFB_XER_OV, Ity_I8 );
}
-static IRExpr* /* :: Ity_I32 */ getXER_OV32 ( void )
+static IRExpr* /* :: Ity_I8 */ getXER_OV32 ( void )
{
+ return IRExpr_Get( OFFB_XER_OV32, Ity_I8 );
+}
+
+static IRExpr* /* :: Ity_I32 */ getXER_OV_32 ( void )
+{
+ /* get XER[OV], 32-bit interface */
return binop( Iop_And32, unop(Iop_8Uto32, getXER_OV()), mkU32(1) );
}
-static IRExpr* /* :: Ity_I32 */ getXER_CA32 ( void )
+static IRExpr* /* :: Ity_I32 */ getXER_OV32_32 ( void )
{
+ /* get XER[OV32], 32-bit interface */
+ return binop( Iop_And32, unop(Iop_8Uto32, getXER_OV32()), mkU32(1) );
+}
+
+static IRExpr* /* :: Ity_I32 */ getXER_CA_32 ( void )
+{
+ /* get XER[CA], 32-bit interface */
IRExpr* ca = IRExpr_Get( OFFB_XER_CA, Ity_I8 );
return binop( Iop_And32, unop(Iop_8Uto32, ca ), mkU32(1) );
}
+static IRExpr* /* :: Ity_I32 */ getXER_CA32_32 ( void )
+{
+ /* get XER[CA32], 32-bit interface */
+ IRExpr* ca = IRExpr_Get( OFFB_XER_CA32, Ity_I8 );
+ return binop( Iop_And32, unop(Iop_8Uto32, ca ), mkU32(1) );
+}
+
static IRExpr* /* :: Ity_I8 */ getXER_BC ( void )
{
return IRExpr_Get( OFFB_XER_BC, Ity_I8 );
}
-static IRExpr* /* :: Ity_I32 */ getXER_BC32 ( void )
+static IRExpr* /* :: Ity_I32 */ getXER_BC_32 ( void )
{
IRExpr* bc = IRExpr_Get( OFFB_XER_BC, Ity_I8 );
return binop( Iop_And32, unop(Iop_8Uto32, bc), mkU32(0x7F) );
@@ -2264,15 +2317,11 @@
/* RES is the result of doing OP on ARGL and ARGR. Set %XER.OV and
%XER.SO accordingly. */
-static void set_XER_OV_32( UInt op, IRExpr* res,
- IRExpr* argL, IRExpr* argR )
+static IRExpr* calculate_XER_OV_32( UInt op, IRExpr* res,
+ IRExpr* argL, IRExpr* argR )
{
IRTemp t64;
IRExpr* xer_ov;
- vassert(op < PPCG_FLAG_OP_NUMBER);
- vassert(typeOfIRExpr(irsb->tyenv,res) == Ity_I32);
- vassert(typeOfIRExpr(irsb->tyenv,argL) == Ity_I32);
- vassert(typeOfIRExpr(irsb->tyenv,argR) == Ity_I32);
# define INT32_MIN 0x80000000
@@ -2381,15 +2430,11 @@
default:
- vex_printf("set_XER_OV: op = %u\n", op);
- vpanic("set_XER_OV(ppc)");
+ vex_printf("calculate_XER_OV_32: op = %u\n", op);
+ vpanic("calculate_XER_OV_32(ppc)");
}
-
- /* xer_ov MUST denote either 0 or 1, no other value allowed */
- putXER_OV( unop(Iop_32to8, xer_ov) );
- /* Update the summary overflow */
- putXER_SO( binop(Iop_Or8, getXER_SO(), getXER_OV()) );
+ return xer_ov;
# undef INT32_MIN
# undef AND3
@@ -2398,14 +2443,27 @@
# undef NOT
}
-static void set_XER_OV_64( UInt op, IRExpr* res,
- IRExpr* argL, IRExpr* argR )
+static void set_XER_OV_OV32_32( UInt op, IRExpr* res,
+ IRExpr* argL, IRExpr* argR )
{
IRExpr* xer_ov;
+
vassert(op < PPCG_FLAG_OP_NUMBER);
- vassert(typeOfIRExpr(irsb->tyenv,res) == Ity_I64);
- vassert(typeOfIRExpr(irsb->tyenv,argL) == Ity_I64);
- vassert(typeOfIRExpr(irsb->tyenv,argR) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,res) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv,argL) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv,argR) == Ity_I32);
+
+ xer_ov = calculate_XER_OV_32( op, res, argL, argR );
+
+ /* xer_ov MUST denote either 0 or 1, no other value allowed */
+ putXER_OV( unop(Iop_32to8, xer_ov) );
+ putXER_OV32( unop(Iop_32to8, xer_ov) );
+}
+
+static IRExpr* calculate_XER_OV_64( UInt op, IRExpr* res,
+ IRExpr* argL, IRExpr* argR )
+{
+ IRExpr* xer_ov;
# define INT64_MIN 0x8000000000000000ULL
@@ -2485,7 +2543,7 @@
= unop(Iop_64to1, binop(Iop_Shr64, xer_ov, mkU8(63)));
break;
- case PPCG_FLAG_OP_DIVDE:
+ case /* 14 */ PPCG_FLAG_OP_DIVDE:
/* If argR == 0, we must set the OV bit. But there's another condition
* where we can get overflow set for divde . . . when the
@@ -2499,7 +2557,7 @@
binop( Iop_CmpNE64, argR, mkU64( 0 ) ) ) ) );
break;
- case PPCG_FLAG_OP_DIVDEU:
+ case /* 17 */ PPCG_FLAG_OP_DIVDEU:
/* If argR == 0 or if argL >= argR, set OV. */
xer_ov = mkOR1( binop( Iop_CmpEQ64, argR, mkU64( 0 ) ),
binop( Iop_CmpLE64U, argR, argL ) );
@@ -2522,15 +2580,11 @@
}
default:
- vex_printf("set_XER_OV: op = %u\n", op);
- vpanic("set_XER_OV(ppc64)");
+ vex_printf("calculate_XER_OV_64: op = %u\n", op);
+ vpanic("calculate_XER_OV_64(ppc64)");
}
-
- /* xer_ov MUST denote either 0 or 1, no other value allowed */
- putXER_OV( unop(Iop_1Uto8, xer_ov) );
- /* Update the summary overflow */
- putXER_SO( binop(Iop_Or8, getXER_SO(), getXER_OV()) );
+ return xer_ov;
# undef INT64_MIN
# undef AND3
@@ -2539,13 +2593,62 @@
# undef NOT
}
-static void set_XER_OV ( IRType ty, UInt op, IRExpr* res,
- IRExpr* argL, IRExpr* argR )
+static void set_XER_OV_64( UInt op, IRExpr* res,
+ IRExpr* argL, IRExpr* argR )
{
- if (ty == Ity_I32)
- set_XER_OV_32( op, res, argL, argR );
- else
+ IRExpr* xer_ov;
+ vassert(op < PPCG_FLAG_OP_NUMBER);
+ vassert(typeOfIRExpr(irsb->tyenv,res) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,argL) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,argR) == Ity_I64);
+
+ /* xer_ov MUST denote either 0 or 1, no other value allowed */
+ xer_ov = calculate_XER_OV_64( op, res, argL, argR);
+ putXER_OV( unop(Iop_1Uto8, xer_ov) );
+
+ /* Update the summary overflow */
+ putXER_SO( binop(Iop_Or8, getXER_SO(), getXER_OV()) );
+}
+
+static void update_SO( void ) {
+ /* Update the summary overflow bit */
+ putXER_SO( binop(Iop_Or8, getXER_SO(), getXER_OV()) );
+}
+
+static void copy_OV_to_OV32( void ) {
+ /* Update the OV32 to match OV */
+ putXER_OV32( getXER_OV() );
+}
+
+static void set_XER_OV_OV32 ( IRType ty, UInt op, IRExpr* res,
+ IRExpr* argL, IRExpr* argR )
+{
+ if (ty == Ity_I32) {
+ set_XER_OV_OV32_32( op, res, argL, argR );
+ } else {
+ IRExpr* xer_ov_32;
set_XER_OV_64( op, res, argL, argR );
+ xer_ov_32 = calculate_XER_OV_32( op, unop(Iop_64to32, res),
+ unop(Iop_64to32, argL),
+ unop(Iop_64to32, argR));
+ putXER_OV32( unop(Iop_32to8, xer_ov_32) );
+ }
+}
+
+static void set_XER_OV_OV32_SO ( IRType ty, UInt op, IRExpr* res,
+ IRExpr* argL, IRExpr* argR )
+{
+ if (ty == Ity_I32) {
+ set_XER_OV_OV32_32( op, res, argL, argR );
+ } else {
+ IRExpr* xer_ov_32;
+ set_XER_OV_64( op, res, argL, argR );
+ xer_ov_32 = calculate_XER_OV_32( op, unop(Iop_64to32, res),
+ unop(Iop_64to32, argL),
+ unop(Iop_64to32, argR));
+ putXER_OV32( unop(Iop_32to8, xer_ov_32) );
+ }
+ update_SO();
}
@@ -2553,21 +2656,10 @@
/* RES is the result of doing OP on ARGL and ARGR with the old %XER.CA
value being OLDCA. Set %XER.CA accordingly. */
-static void set_XER_CA_32 ( UInt op, IRExpr* res,
- IRExpr* argL, IRExpr* argR, IRExpr* oldca )
+static IRExpr* calculate_XER_CA_32 ( UInt op, IRExpr* res,
+ IRExpr* argL, IRExpr* argR, IRExpr* oldca )
{
IRExpr* xer_ca;
- vassert(op < PPCG_FLAG_OP_NUMBER);
- vassert(typeOfIRExpr(irsb->tyenv,res) == Ity_I32);
- vassert(typeOfIRExpr(irsb->tyenv,argL) == Ity_I32);
- vassert(typeOfIRExpr(irsb->tyenv,argR) == Ity_I32);
- vassert(typeOfIRExpr(irsb->tyenv,oldca) == Ity_I32);
-
- /* Incoming oldca is assumed to hold the values 0 or 1 only. This
- seems reasonable given that it's always generated by
- getXER_CA32(), which masks it accordingly. In any case it being
- 0 or 1 is an invariant of the ppc guest state representation;
- if it has any other value, that invariant has been violated. */
switch (op) {
case /* 0 */ PPCG_FLAG_OP_ADD:
@@ -2667,26 +2759,36 @@
vpanic("set_XER_CA(ppc)");
}
- /* xer_ca MUST denote either 0 or 1, no other value allowed */
- putXER_CA( unop(Iop_32to8, xer_ca) );
+ return xer_ca;
}
-static void set_XER_CA_64 ( UInt op, IRExpr* res,
+static void set_XER_CA_32 ( UInt op, IRExpr* res,
IRExpr* argL, IRExpr* argR, IRExpr* oldca )
{
IRExpr* xer_ca;
vassert(op < PPCG_FLAG_OP_NUMBER);
- vassert(typeOfIRExpr(irsb->tyenv,res) == Ity_I64);
- vassert(typeOfIRExpr(irsb->tyenv,argL) == Ity_I64);
- vassert(typeOfIRExpr(irsb->tyenv,argR) == Ity_I64);
- vassert(typeOfIRExpr(irsb->tyenv,oldca) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,res) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv,argL) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv,argR) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv,oldca) == Ity_I32);
/* Incoming oldca is assumed to hold the values 0 or 1 only. This
seems reasonable given that it's always generated by
- getXER_CA32(), which masks it accordingly. In any case it being
+ getXER_CA_32(), which masks it accordingly. In any case it being
0 or 1 is an invariant of the ppc guest state representation;
if it has any other value, that invariant has been violated. */
+ xer_ca = calculate_XER_CA_32( op, res, argL, argR, oldca);
+
+ /* xer_ca MUST denote either 0 or 1, no other value allowed */
+ putXER_CA( unop(Iop_32to8, xer_ca) );
+}
+
+static IRExpr* calculate_XER_CA_64 ( UInt op, IRExpr* res,
+ IRExpr* argL, IRExpr* argR, IRExpr* oldca )
+{
+ IRExpr* xer_ca;
+
switch (op) {
case /* 0 */ PPCG_FLAG_OP_ADD:
/* res <u argL */
@@ -2843,17 +2945,39 @@
vpanic("set_XER_CA(ppc64)");
}
+ return xer_ca;
+}
+
+static void set_XER_CA_64 ( UInt op, IRExpr* res,
+ IRExpr* argL, IRExpr* argR, IRExpr* oldca )
+{
+ IRExpr* xer_ca;
+ vassert(op < PPCG_FLAG_OP_NUMBER);
+ vassert(typeOfIRExpr(irsb->tyenv,res) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,argL) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,argR) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,oldca) == Ity_I64);
+
+ /* Incoming oldca is assumed to hold the values 0 or 1 only. This
+ seems reasonable given that it's always generated by
+ getXER_CA_32(), which masks it accordingly. In any case it being
+ 0 or 1 is an invariant of the ppc guest state representation;
+ if it has any other value, that invariant has been violated. */
+
+ xer_ca = calculate_XER_CA_64( op, res, argL, argR, oldca );
+
/* xer_ca MUST denote either 0 or 1, no other value allowed */
putXER_CA( unop(Iop_32to8, xer_ca) );
}
-static void set_XER_CA ( IRType ty, UInt op, IRExpr* res,
- IRExpr* argL, IRExpr* argR, IRExpr* oldca )
+static void set_XER_CA_CA32 ( IRType ty, UInt op, IRExpr* res,
+ IRExpr* argL, IRExpr* argR, IRExpr* oldca )
{
- if (ty == Ity_I32)
+ if (ty == Ity_I32) {
set_XER_CA_32( op, res, argL, argR, oldca );
- else
+ } else {
set_XER_CA_64( op, res, argL, argR, oldca );
+ }
}
@@ -2913,11 +3037,15 @@
case PPC_GST_XER:
return binop(Iop_Or32,
binop(Iop_Or32,
- binop( Iop_Shl32, getXER_SO32(), mkU8(31)),
- binop( Iop_Shl32, getXER_OV32(), mkU8(30))),
+ binop(Iop_Or32,
+ binop( Iop_Shl32, getXER_SO_32(), mkU8(31)),
+ binop( Iop_Shl32, getXER_OV_32(), mkU8(30))),
+ binop(Iop_Or32,
+ binop( Iop_Shl32, getXER_CA_32(), mkU8(29)),
+ getXER_BC_32())),
binop(Iop_Or32,
- binop( Iop_Shl32, getXER_CA32(), mkU8(29)),
- getXER_BC32()));
+ binop( Iop_Shl32, getXER_OV32_32(), mkU8(19)),
+ binop( Iop_Shl32, getXER_CA32_32(), mkU8(18))));
case PPC_GST_TFHAR:
return IRExpr_Get( OFFB_TFHAR, ty );
@@ -2963,8 +3091,13 @@
* floating point rounding mode and Floating-point Condition code, so
* if the mask isn't asking for either of these, just return 0x0.
*/
- if ( mask & MASK_FPSCR_RN ) {
- assign( val, unop( Iop_8Uto32, IRExpr_Get( OFFB_FPROUND, Ity_I8 ) ) );
+ if ( mask & ( MASK_FPSCR_C_FPCC | MASK_FPSCR_RN ) ) {
+ assign( val, binop( Iop_Or32,
+ unop( Iop_8Uto32, IRExpr_Get( OFFB_FPROUND, Ity_I8 ) ),
+ binop( Iop_Shl32,
+ unop( Iop_8Uto32,
+ IRExpr_Get( OFFB_C_FPCC, Ity_I8 ) ),
+ mkU8( 12 ) ) ) );
} else {
assign( val, mkU32(0x0) );
}
@@ -3032,9 +3165,9 @@
vassert(fld ==7);
return binop(Iop_Or32,
binop(Iop_Or32,
- binop(Iop_Shl32, getXER_SO32(), mkU8(3)),
- binop(Iop_Shl32, getXER_OV32(), mkU8(2))),
- binop( Iop_Shl32, getXER_CA32(), mkU8(1)));
+ binop(Iop_Shl32, getXER_SO_32(), mkU8(3)),
+ binop(Iop_Shl32, getXER_OV_32(), mkU8(2))),
+ binop( Iop_Shl32, getXER_CA_32(), mkU8(1)));
break;
default:
@@ -3084,6 +3217,8 @@
putXER_SO( unop(Iop_32to8, binop(Iop_Shr32, src, mkU8(31))) );
putXER_OV( unop(Iop_32to8, binop(Iop_Shr32, src, mkU8(30))) );
putXER_CA( unop(Iop_32to8, binop(Iop_Shr32, src, mkU8(29))) );
+ putXER_OV32( unop(Iop_32to8, binop(Iop_Shr32, src, mkU8(19))) );
+ putXER_CA32( unop(Iop_32to8, binop(Iop_Shr32, src, mkU8(18))) );
putXER_BC( unop(Iop_32to8, src) );
break;
@@ -3256,27 +3391,27 @@
}
if (mask & MASK_FPSCR_C_FPCC) {
+ /* FPCC bits are in [47:51] */
stmt(
IRStmt_Put(
OFFB_C_FPCC,
unop(
- Iop_32to8,
- binop(
- Iop_Or32,
- binop(
- Iop_And32,
- unop(Iop_64to32, src),
- mkU32(MASK_FPSCR_C_FPCC & mask)
- ),
- binop(
- Iop_And32,
- unop(Iop_8Uto32, IRExpr_Get(OFFB_C_FPCC,Ity_I8)),
- mkU32(MASK_FPSCR_C_FPCC & ~mask)
- )
- )
- )
- )
- );
+ Iop_32to8,
+ binop(Iop_Shr32,
+ binop(
+ Iop_Or32,
+ binop(
+ Iop_And32,
+ unop(Iop_64to32, src),
+ mkU32(MASK_FPSCR_C_FPCC & mask) ),
+ binop(
+ Iop_And32,
+ unop(Iop_8Uto32,
+ IRExpr_Get(OFFB_C_FPCC,Ity_I8)),
+ mkU32(MASK_FPSCR_C_FPCC & ~mask)
+ ) ),
+ mkU8( 12 ) )
+ ) ) );
}
/* Similarly, update FPSCR.DRN if any bits of |mask|
@@ -4858,18 +4993,18 @@
DIP("addic r%u,r%u,%d\n", rD_addr, rA_addr, (Int)simm16);
assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA),
mkSzExtendS16(ty, uimm16) ) );
- set_XER_CA( ty, PPCG_FLAG_OP_ADD,
- mkexpr(rD), mkexpr(rA), mkSzExtendS16(ty, uimm16),
- mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_ADD,
+ mkexpr(rD), mkexpr(rA), mkSzExtendS16(ty, uimm16),
+ mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ );
break;
case 0x0D: // addic. (Add Immediate Carrying and Record, PPC32 p352)
DIP("addic. r%u,r%u,%d\n", rD_addr, rA_addr, (Int)simm16);
assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA),
mkSzExtendS16(ty, uimm16) ) );
- set_XER_CA( ty, PPCG_FLAG_OP_ADD,
- mkexpr(rD), mkexpr(rA), mkSzExtendS16(ty, uimm16),
- mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_ADD,
+ mkexpr(rD), mkexpr(rA), mkSzExtendS16(ty, uimm16),
+ mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ );
do_rc = True; // Always record to CR
flag_rC = 1;
break;
@@ -4917,9 +5052,9 @@
assign( rD, binop( mkSzOp(ty, Iop_Sub8),
mkSzExtendS16(ty, uimm16),
mkexpr(rA)) );
- set_XER_CA( ty, PPCG_FLAG_OP_SUBFI,
- mkexpr(rD), mkexpr(rA), mkSzExtendS16(ty, uimm16),
- mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_SUBFI,
+ mkexpr(rD), mkexpr(rA), mkSzExtendS16(ty, uimm16),
+ mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ );
break;
/* XO-Form */
@@ -4934,8 +5069,8 @@
assign( rD, binop( mkSzOp(ty, Iop_Add8),
mkexpr(rA), mkexpr(rB) ) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_ADD,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_ADD,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
}
break;
@@ -4945,12 +5080,12 @@
rD_addr, rA_addr, rB_addr);
assign( rD, binop( mkSzOp(ty, Iop_Add8),
mkexpr(rA), mkexpr(rB)) );
- set_XER_CA( ty, PPCG_FLAG_OP_ADD,
- mkexpr(rD), mkexpr(rA), mkexpr(rB),
- mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_ADD,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB),
+ mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_ADD,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_ADD,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
}
break;
@@ -4960,16 +5095,35 @@
flag_OE ? "o" : "", flag_rC ? ".":"",
rD_addr, rA_addr, rB_addr);
// rD = rA + rB + XER[CA]
- assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA32(), False) );
+ assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA_32(), False) );
assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA),
binop( mkSzOp(ty, Iop_Add8),
mkexpr(rB), mkexpr(old_xer_ca))) );
- set_XER_CA( ty, PPCG_FLAG_OP_ADDE,
- mkexpr(rD), mkexpr(rA), mkexpr(rB),
- mkexpr(old_xer_ca) );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_ADDE,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB),
+ mkexpr(old_xer_ca) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_ADDE,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_ADDE,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ }
+ break;
+ }
+
+ case 0xAA: {// addex (Add Extended alternate carry bit Z23-form)
+ DIP("addex r%u,r%u,r%u,%d\n", rD_addr, rA_addr, rB_addr, (Int)flag_OE);
+ assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA),
+ binop( mkSzOp(ty, Iop_Add8), mkexpr(rB),
+ mkWidenFrom8( ty, getXER_OV(), False ) ) ) );
+
+ /* CY bit is same as OE bit */
+ if (flag_OE == 0) {
+ /* Exception, do not set SO bit */
+ set_XER_OV_OV32( ty, PPCG_FLAG_OP_ADDE,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ } else {
+ /* CY=1, 2 and 3 (AKA flag_OE) are reserved */
+ vex_printf("addex instruction, CY = %d is reserved.\n", flag_OE);
+ vpanic("addex instruction\n");
}
break;
}
@@ -4986,17 +5140,17 @@
rD_addr, rA_addr, rB_addr);
// rD = rA + (-1) + XER[CA]
// => Just another form of adde
- assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA32(), False) );
+ assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA_32(), False) );
min_one = mkSzImm(ty, (Long)-1);
assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA),
binop( mkSzOp(ty, Iop_Add8),
min_one, mkexpr(old_xer_ca)) ));
- set_XER_CA( ty, PPCG_FLAG_OP_ADDE,
- mkexpr(rD), mkexpr(rA), min_one,
- mkexpr(old_xer_ca) );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_ADDE,
+ mkexpr(rD), mkexpr(rA), min_one,
+ mkexpr(old_xer_ca) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_ADDE,
- mkexpr(rD), mkexpr(rA), min_one );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_ADDE,
+ mkexpr(rD), mkexpr(rA), min_one );
}
break;
}
@@ -5012,15 +5166,15 @@
rD_addr, rA_addr, rB_addr);
// rD = rA + (0) + XER[CA]
// => Just another form of adde
- assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA32(), False) );
+ assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA_32(), False) );
assign( rD, binop( mkSzOp(ty, Iop_Add8),
mkexpr(rA), mkexpr(old_xer_ca)) );
- set_XER_CA( ty, PPCG_FLAG_OP_ADDE,
- mkexpr(rD), mkexpr(rA), mkSzImm(ty, 0),
- mkexpr(old_xer_ca) );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_ADDE,
+ mkexpr(rD), mkexpr(rA), mkSzImm(ty, 0),
+ mkexpr(old_xer_ca) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_ADDE,
- mkexpr(rD), mkexpr(rA), mkSzImm(ty, 0) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_ADDE,
+ mkexpr(rD), mkexpr(rA), mkSzImm(ty, 0) );
}
break;
}
@@ -5042,14 +5196,14 @@
assign( rD, mk64lo32Uto64( binop(Iop_DivS64, dividend,
divisor) ) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_DIVW,
- mkexpr(rD), dividend, divisor );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_DIVW,
+ mkexpr(rD), dividend, divisor );
}
} else {
assign( rD, binop(Iop_DivS32, mkexpr(rA), mkexpr(rB)) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_DIVW,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_DIVW,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
}
}
/* Note:
@@ -5073,14 +5227,14 @@
assign( rD, mk64lo32Uto64( binop(Iop_DivU64, dividend,
divisor) ) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_DIVWU,
- mkexpr(rD), dividend, divisor );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_DIVWU,
+ mkexpr(rD), dividend, divisor );
}
} else {
assign( rD, binop(Iop_DivU32, mkexpr(rA), mkexpr(rB)) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_DIVWU,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_DIVWU,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
}
}
/* Note: ditto comment divw, for (x / 0) */
@@ -5141,17 +5295,17 @@
IRExpr *b = unop(Iop_64to32, mkexpr(rB) );
assign( rD, binop(Iop_MullS32, a, b) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_MULLW,
- mkexpr(rD),
- unop(Iop_32Uto64, a), unop(Iop_32Uto64, b) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_MULLW,
+ mkexpr(rD),
+ unop(Iop_32Uto64, a), unop(Iop_32Uto64, b) );
}
} else {
assign( rD, unop(Iop_64to32,
binop(Iop_MullU32,
mkexpr(rA), mkexpr(rB))) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_MULLW,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_MULLW,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
}
}
break;
@@ -5169,8 +5323,8 @@
unop( mkSzOp(ty, Iop_Not8), mkexpr(rA) ),
mkSzImm(ty, 1)) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_NEG,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_NEG,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
}
break;
@@ -5182,8 +5336,8 @@
assign( rD, binop( mkSzOp(ty, Iop_Sub8),
mkexpr(rB), mkexpr(rA)) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_SUBF,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_SUBF,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
}
break;
@@ -5194,12 +5348,12 @@
// rD = rB - rA
assign( rD, binop( mkSzOp(ty, Iop_Sub8),
mkexpr(rB), mkexpr(rA)) );
- set_XER_CA( ty, PPCG_FLAG_OP_SUBFC,
- mkexpr(rD), mkexpr(rA), mkexpr(rB),
- mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_SUBFC,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB),
+ mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_SUBFC,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_SUBFC,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
}
break;
@@ -5209,17 +5363,17 @@
flag_OE ? "o" : "", flag_rC ? ".":"",
rD_addr, rA_addr, rB_addr);
// rD = (log not)rA + rB + XER[CA]
- assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA32(), False) );
+ assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA_32(), False) );
assign( rD, binop( mkSzOp(ty, Iop_Add8),
unop( mkSzOp(ty, Iop_Not8), mkexpr(rA)),
binop( mkSzOp(ty, Iop_Add8),
mkexpr(rB), mkexpr(old_xer_ca))) );
- set_XER_CA( ty, PPCG_FLAG_OP_SUBFE,
- mkexpr(rD), mkexpr(rA), mkexpr(rB),
- mkexpr(old_xer_ca) );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_SUBFE,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB),
+ mkexpr(old_xer_ca) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_SUBFE,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_SUBFE,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
}
break;
}
@@ -5236,18 +5390,18 @@
rD_addr, rA_addr);
// rD = (log not)rA + (-1) + XER[CA]
// => Just another form of subfe
- assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA32(), False) );
+ assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA_32(), False) );
min_one = mkSzImm(ty, (Long)-1);
assign( rD, binop( mkSzOp(ty, Iop_Add8),
unop( mkSzOp(ty, Iop_Not8), mkexpr(rA)),
binop( mkSzOp(ty, Iop_Add8),
min_one, mkexpr(old_xer_ca))) );
- set_XER_CA( ty, PPCG_FLAG_OP_SUBFE,
- mkexpr(rD), mkexpr(rA), min_one,
- mkexpr(old_xer_ca) );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_SUBFE,
+ mkexpr(rD), mkexpr(rA), min_one,
+ mkexpr(old_xer_ca) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_SUBFE,
- mkexpr(rD), mkexpr(rA), min_one );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_SUBFE,
+ mkexpr(rD), mkexpr(rA), min_one );
}
break;
}
@@ -5263,16 +5417,16 @@
rD_addr, rA_addr);
// rD = (log not)rA + (0) + XER[CA]
// => Just another form of subfe
- assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA32(), False) );
+ assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA_32(), False) );
assign( rD, binop( mkSzOp(ty, Iop_Add8),
unop( mkSzOp(ty, Iop_Not8),
mkexpr(rA)), mkexpr(old_xer_ca)) );
- set_XER_CA( ty, PPCG_FLAG_OP_SUBFE,
- mkexpr(rD), mkexpr(rA), mkSzImm(ty, 0),
- mkexpr(old_xer_ca) );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_SUBFE,
+ mkexpr(rD), mkexpr(rA), mkSzImm(ty, 0),
+ mkexpr(old_xer_ca) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_SUBFE,
- mkexpr(rD), mkexpr(rA), mkSzImm(ty, 0) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_SUBFE,
+ mkexpr(rD), mkexpr(rA), mkSzImm(ty, 0) );
}
break;
}
@@ -5310,8 +5464,14 @@
rD_addr, rA_addr, rB_addr);
assign( rD, binop(Iop_Mul64, mkexpr(rA), mkexpr(rB)) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_MULLD,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_64( PPCG_FLAG_OP_MULLD,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ /* OV is set to 1 if product isn't representable.
+ * In this case also need to set OV32 and SO to 1,
+ * i.e. copy OV to OV32 and SO.
+ */
+ copy_OV_to_OV32();
+ update_SO();
}
break;
@@ -5321,8 +5481,8 @@
rD_addr, rA_addr, rB_addr);
assign( rD, binop(Iop_DivS64, mkexpr(rA), mkexpr(rB)) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_DIVW,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_DIVW,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
}
break;
/* Note:
@@ -5336,8 +5496,8 @@
rD_addr, rA_addr, rB_addr);
assign( rD, binop(Iop_DivU64, mkexpr(rA), mkexpr(rB)) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_DIVWU,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_DIVWU,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
}
break;
/* Note: ditto comment divd, for (x / 0) */
@@ -5369,8 +5529,9 @@
}
if (flag_OE) {
- set_XER_OV_32( PPCG_FLAG_OP_DIVWEU,
- mkexpr(res), dividend, divisor );
+ set_XER_OV_OV32_32( PPCG_FLAG_OP_DIVWEU,
+ mkexpr(res), dividend, divisor );
+ update_SO( );
}
break;
}
@@ -5404,8 +5565,9 @@
}
if (flag_OE) {
- set_XER_OV_32( PPCG_FLAG_OP_DIVWE,
- mkexpr(res), dividend, divisor );
+ set_XER_OV_OV32_32( PPCG_FLAG_OP_DIVWE,
+ mkexpr(res), dividend, divisor );
+ update_SO( );
}
break;
}
@@ -5427,6 +5589,8 @@
if (flag_OE) {
set_XER_OV_64( PPCG_FLAG_OP_DIVDE, mkexpr( rD ),
mkexpr( rA ), mkexpr( rB ) );
+ copy_OV_to_OV32();
+ update_SO();
}
break;
@@ -5439,6 +5603,8 @@
if (flag_OE) {
set_XER_OV_64( PPCG_FLAG_OP_DIVDEU, mkexpr( rD ),
mkexpr( rA ), mkexpr( rB ) );
+ copy_OV_to_OV32();
+ update_SO();
}
break;
@@ -8862,11 +9028,11 @@
mkexpr(sh_amt)) ) );
assign( rA, mkWidenFrom32(ty, e_tmp, /* Signed */True) );
- set_XER_CA( ty, PPCG_FLAG_OP_SRAW,
- mkexpr(rA),
- mkWidenFrom32(ty, mkexpr(rS_lo32), True),
- mkWidenFrom32(ty, mkexpr(sh_amt), True ),
- mkWidenFrom32(ty, getXER_CA32(), True) );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_SRAW,
+ mkexpr(rA),
+ mkWidenFrom32(ty, mkexpr(rS_lo32), True),
+ mkWidenFrom32(ty, mkexpr(sh_amt), True ),
+ mkWidenFrom32(ty, getXER_CA_32(), True) );
break;
}
@@ -8884,11 +9050,11 @@
mkU8(sh_imm)) );
}
- set_XER_CA( ty, PPCG_FLAG_OP_SRAWI,
- mkexpr(rA),
- mkWidenFrom32(ty, mkexpr(rS_lo32), /* Syned */True),
- mkSzImm(ty, sh_imm),
- mkWidenFrom32(ty, getXER_CA32(), /* Syned */False) );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_SRAWI,
+ mkexpr(rA),
+ mkWidenFrom32(ty, mkexpr(rS_lo32), /* Syned */True),
+ mkSzImm(ty, sh_imm),
+ mkWidenFrom32(ty, getXER_CA_32(), /* Syned */False) );
break;
case 0x218: // srw (Shift Right Word, PPC32 p508)
@@ -8959,9 +9125,9 @@
mkU64(63),
mkexpr(sh_amt)) ))
);
- set_XER_CA( ty, PPCG_FLAG_OP_SRAD,
- mkexpr(rA), mkexpr(rS), mkexpr(sh_amt),
- mkWidenFrom32(ty, getXER_CA32(), /* Syned */False) );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_SRAD,
+ mkexpr(rA), mkexpr(rS), mkexpr(sh_amt),
+ mkWidenFrom32(ty, getXER_CA_32(), /* Syned */False) );
break;
}
@@ -8972,11 +9138,11 @@
flag_rC ? ".":"", rA_addr, rS_addr, sh_imm);
assign( rA, binop(Iop_Sar64, getIReg(rS_addr), mkU8(sh_imm)) );
- set_XER_CA( ty, PPCG_FLAG_OP_SRADI,
- mkexpr(rA),
- getIReg(rS_addr),
- mkU64(sh_imm),
- mkWidenFrom32(ty, getXER_CA32(), /* Syned */False) );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_SRADI,
+ mkexpr(rA),
+ getIReg(rS_addr),
+ mkU64(sh_imm),
+ mkWidenFrom32(ty, getXER_CA_32(), /* Syned */False) );
break;
case 0x21B: // srd (Shift Right DWord, PPC64 p574)
@@ -11310,13 +11476,16 @@
UChar b0 = ifieldBIT0(theInstr);
Bool is_load = 0;
- if ((frT_hi_addr %2) != 0) {
- vex_printf("dis_fp_pair(ppc) : odd frT register\n");
- return False;
- }
-
switch (opc1) {
case 0x1F: // register offset
+ /* These instructions work on a pair of registers. The specified
+ * register must be even.
+ */
+ if ((frT_hi_addr %2) != 0) {
+ vex_printf("dis_fp_pair(ppc) ldpx or stdpx: odd frT register\n");
+ return False;
+ }
+
switch(opc2) {
case 0x317: // lfdpx (FP Load Double Pair X-form, ISA 2.05 p125)
DIP("ldpx fr%u,r%u,r%u\n", frT_hi_addr, rA_addr, rB_addr);
@@ -11346,6 +11515,14 @@
switch(opc2) {
case 0x0: // lfdp (FP Load Double Pair DS-form, ISA 2.05 p125)
+ /* This instruction works on a pair of registers. The specified
+ * register must be even.
+ */
+ if ((frT_hi_addr %2) != 0) {
+ vex_printf("dis_fp_pair(ppc) lfdp : odd frT register\n");
+ return False;
+ }
+
DIP("lfdp fr%u,%d(r%u)\n", frT_hi_addr, simm16, rA_addr);
assign( EA_hi, ea_rAor0_simm( rA_addr, simm16 ) );
is_load = 1;
@@ -11390,6 +11567,14 @@
switch(opc2) {
case 0x0:
// stfdp (FP Store Double Pair DS-form, ISA 2.05 p125)
+ /* This instruction works on a pair of registers. The specified
+ * register must be even.
+ */
+ if ((frT_hi_addr %2) != 0) {
+ vex_printf("dis_fp_pair(ppc) stfdp : odd frT register\n");
+ return False;
+ }
+
DIP("stfdp fr%u,%d(r%u)\n", frT_hi_addr, simm16, rA_addr);
assign( EA_hi, ea_rAor0_simm( rA_addr, simm16 ) );
break;
@@ -11404,7 +11589,7 @@
word[0] = newTemp(Ity_I64);
word[1] = newTemp(Ity_I64);
- DS = IFIELD( theInstr, 4, 11); // DQ in the instruction definition
+ DS = IFIELD( theInstr, 4, 12); // DQ in the instruction definition
assign( EA, ea_rAor0_simm( rA_addr, DS<<4 ) );
if ( IFIELD( theInstr, 0, 3) == 1) {
@@ -11463,6 +11648,13 @@
store( mkexpr(EA), unop( Iop_V128HIto64,
getVSReg( vRS+32 ) ) );
+ /* HW is clearing vector element 1. Don't see that in the ISA but
+ * matching the HW.
+ */
+ putVSReg( vRS+32, binop( Iop_64HLtoV128,
+ unop( Iop_V128HIto64,
+ getVSReg( vRS+32 ) ),
+ mkU64( 0 ) ) );
return True;
case 0x3:
@@ -11748,7 +11940,13 @@
case 0x247: { // mffs (Move from FPSCR, PPC32 p468)
UChar frD_addr = ifieldRegDS(theInstr);
- UInt b11to20 = IFIELD(theInstr, 11, 10);
+ UChar frB_addr = ifieldRegB(theInstr);
+ IRTemp frB = newTemp(Ity_F64);
+ UInt b11to12 = IFIELD(theInstr, 19, 2);
+ UInt b13to15 = IFIELD(theInstr, 16, 3);
+ UInt RN = IFIELD(theInstr, 11, 2);
+ UInt DRN = IFIELD(theInstr, 11, 3);
+
/* The FPSCR_DRN, FPSCR_RN and FPSCR_FPCC are all stored in
* their own 8-bit entries with distinct offsets. The FPSCR
* register is handled as two 32-bit values. We need to
@@ -11756,7 +11954,7 @@
*/
IRExpr* fpscr_lower
= binop( Iop_Or32,
- getGST_masked( PPC_GST_FPSCR, MASK_FPSCR_RN),
+ getGST_masked( PPC_GST_FPSCR, (MASK_FPSCR_RN | MASK_FPSCR_C_FPCC) ),
binop( Iop_Or32,
binop( Iop_Shl32,
getC(),
@@ -11764,17 +11962,117 @@
binop( Iop_Shl32,
getFPCC(),
mkU8(63-51) ) ) );
- IRExpr* fpscr_upper = getGST_masked_upper( PPC_GST_FPSCR,
- MASK_FPSCR_DRN );
+ IRExpr* fpscr_upper = getGST_masked_upper( PPC_GST_FPSCR, MASK_FPSCR_DRN );
- if (b11to20 != 0) {
- vex_printf("dis_fp_scr(ppc)(instr,mffs)\n");
+ if ((b11to12 == 0) && (b13to15 == 0)) {
+ DIP("mffs%s fr%u\n", flag_rC ? ".":"", frD_addr);
+ putFReg( frD_addr,
+ unop( Iop_ReinterpI64asF64,
+ binop( Iop_32HLto64, fpscr_upper, fpscr_lower ) ) );
+
+ } else if ((b11to12 == 0) && (b13to15 == 1)) {
+ DIP("mffsce fr%u\n", frD_addr);
+ /* Technically as of 4/5/2017 we are not tracking VE, OE, UE, ZE,
+ or XE but in case that changes in the future, do the masking. */
+ putFReg( frD_addr,
+ unop( Iop_ReinterpI64asF64,
+ binop( Iop_32HLto64, fpscr_upper,
+ binop( Iop_And32, fpscr_lower,
+ mkU32( 0xFFFFFF07 ) ) ) ) );
+
+ } else if ((b11to12 == 2) && (b13to15 == 4)) {
+ IRTemp frB_int = newTemp(Ity_I64);
+
+ DIP("mffscdrn fr%u,fr%u\n", frD_addr, frB_addr);
+
+ assign( frB, getFReg(frB_addr));
+ assign( frB_int, unop( Iop_ReinterpF64asI64, mkexpr( frB ) ) );
+
+ /* Clear all of the FPSCR bits except for the DRN field, VE,
+ OE, UE, ZE and XE bits and write the result to the frD
+ register. Note, currently the exception bits are not tracked but
+ will mask anyway in case that changes in the future. */
+ putFReg( frD_addr,
+ unop( Iop_ReinterpI64asF64,
+ binop( Iop_32HLto64,
+ binop( Iop_And32, mkU32(0x7), fpscr_upper ),
+ binop( Iop_And32, mkU32(0xFF), fpscr_lower ) ) ) );
+
+ /* Put new_DRN bits into the FPSCR register */
+ putGST_masked( PPC_GST_FPSCR, mkexpr( frB_int ), MASK_FPSCR_DRN );
+
+ } else if ((b11to12 == 2) && (b13to15 == 5)) {
+ DIP("mffscdrni fr%u,%d\n", frD_addr, DRN);
+
+ /* Clear all of the FPSCR bits except for the DRN field, VE,
+ OE, UE, ZE and XE bits and write the result to the frD
+ register. Note, currently the exception bits are not tracked but
+ will mask anyway in case that changes in the future. */
+ putFReg( frD_addr,
+ unop( Iop_ReinterpI64asF64,
+ binop( Iop_32HLto64,
+ binop( Iop_And32, mkU32(0x7), fpscr_upper ),
+ binop( Iop_And32, mkU32(0xFF), fpscr_lower ) ) ) );
+
+ /* Put new_DRN bits into the FPSCR register */
+ putGST_masked( PPC_GST_FPSCR, binop( Iop_32HLto64, mkU32( DRN ),
+ mkU32( 0 ) ), MASK_FPSCR_DRN );
+
+ } else if ((b11to12 == 2) && (b13to15 == 6)) {
+ IRTemp frB_int = newTemp(Ity_I64);
+
+ DIP("mffscrn fr%u,fr%u\n", frD_addr,frB_addr);
+
+ assign( frB, getFReg(frB_addr));
+ assign( frB_int, unop( Iop_ReinterpF64asI64, mkexpr( frB ) ) );
+
+ /* Clear all of the FPSCR bits except for the DRN field, VE,
+ OE, UE, ZE and XE bits and write the result to the frD
+ register. Note, currently the exception bits are not tracked but
+ will mask anyway in case that changes in the future. */
+ putFReg( frD_addr,
+ unop( Iop_ReinterpI64asF64,
+ binop( Iop_32HLto64,
+ binop( Iop_And32, mkU32(0x7), fpscr_upper ),
+ binop( Iop_And32, mkU32(0xFF), fpscr_lower ) ) ) );
+
+ /* Put new_CRN bits into the FPSCR register */
+ putGST_masked( PPC_GST_FPSCR, mkexpr( frB_int ), MASK_FPSCR_RN );
+
+ } else if ((b11to12 == 2) && (b13to15 == 7)) {
+ DIP("mffscrni fr%u,%u\n", frD_addr, RN);
+
+ /* Clear all of the FPSCR bits except for the DRN field, VE,
+ OE, UE, ZE and XE bits and write the result to the frD
+ register. Note, currently the exception bits are not tracked but
+ will mask anyway in case that changes in the future. */
+ putFReg( frD_addr,
+ unop( Iop_ReinterpI64asF64,
+ binop( Iop_32HLto64,
+ binop( Iop_And32, mkU32(0x7), fpscr_upper ),
+ binop( Iop_And32, mkU32(0xFF), fpscr_lower ) ) ) );
+
+ /* Put new_RN bits into the FPSCR register */
+ putGST_masked( PPC_GST_FPSCR, binop( Iop_32HLto64, mkU32( 0 ),
+ mkU32( RN ) ), MASK_FPSCR_RN );
+
+ } else if ((b11to12 == 3) && (b13to15 == 0)) {
+ DIP("mffsl fr%u\n", frD_addr);
+ /* Technically as of 4/5/2017 we are not tracking VE, OE, UE, ZE,
+ XE, FR, FI, C, FL, FG, FE, FU. Also only track DRN in the upper
+ bits but in case that changes in the future we will do the
+ masking. */
+ putFReg( frD_addr,
+ unop( Iop_ReinterpI64asF64,
+ binop( Iop_32HLto64,
+ binop( Iop_And32, fpscr_upper,
+ mkU32( 0x7 ) ),
+ binop( Iop_And32, fpscr_lower,
+ mkU32( 0x7F0FF ) ) ) ) );
+ } else {
+ vex_printf("dis_fp_scr(ppc)(mff**) Unrecognized instruction.\n");
return False;
}
- DIP("mffs%s fr%u\n", flag_rC ? ".":"", frD_addr);
- putFReg( frD_addr,
- unop( Iop_ReinterpI64asF64,
- binop( Iop_32HLto64, fpscr_upper, fpscr_lower ) ) );
break;
}
@@ -11803,11 +12101,11 @@
/* new 64 bit move variant for power 6. If L field (bit 25) is
* a one do a full 64 bit move. Note, the FPSCR is not really
* properly modeled. This instruciton only changes the value of
- * the rounding mode. The HW exception bits do not get set in
- * the simulator. 1/12/09
+ * the rounding mode bit fields RN, FPCC and DRN. The HW exception bits
+ * do not get set in the simulator. 1/12/09
*/
DIP("mtfsf%s %d,fr%u (L=1)\n", flag_rC ? ".":"", FM, frB_addr);
- mask = 0xFF;
+ mask = 0x1F0001F003;
} else {
DIP("mtfsf%s %d,fr%u\n", flag_rC ? ".":"", FM, frB_addr);
@@ -18146,7 +18444,7 @@
assign( vB, getVSReg( XB ) );
switch (opc2) {
- case 0x18C: case 0x38C: // xvcmpeqdp[.] (VSX Vector Compare Equal To Double-Precision [ & Record ])
+ case 0x18C: // xvcmpeqdp[.] (VSX Vector Compare Equal To Double-Precision [ & Record ])
{
DIP("xvcmpeqdp%s crf%d,fr%u,fr%u\n", (flag_rC ? ".":""),
XT, XA, XB);
@@ -18154,7 +18452,7 @@
break;
}
- case 0x1CC: case 0x3CC: // xvcmpgedp[.] (VSX Vector Compare Greater Than or Equal To Double-Precision [ & Record ])
+ case 0x1CC: // xvcmpgedp[.] (VSX Vector Compare Greater Than or Equal To Double-Precision [ & Record ])
{
DIP("xvcmpgedp%s crf%d,fr%u,fr%u\n", (flag_rC ? ".":""),
XT, XA, XB);
@@ -18162,7 +18460,7 @@
break;
}
- case 0x1AC: case 0x3AC: // xvcmpgtdp[.] (VSX Vector Compare Greater Than Double-Precision [ & Record ])
+ case 0x1AC: // xvcmpgtdp[.] (VSX Vector Compare Greater Than Double-Precision [ & Record ])
{
DIP("xvcmpgtdp%s crf%d,fr%u,fr%u\n", (flag_rC ? ".":""),
XT, XA, XB);
@@ -18170,7 +18468,7 @@
break;
}
- case 0x10C: case 0x30C: // xvcmpeqsp[.] (VSX Vector Compare Equal To Single-Precision [ & Record ])
+ case 0x10C: // xvcmpeqsp[.] (VSX Vector Compare Equal To Single-Precision [ & Record ])
{
IRTemp vD = newTemp(Ity_V128);
@@ -18184,7 +18482,7 @@
break;
}
- case 0x14C: case 0x34C: // xvcmpgesp[.] (VSX Vector Compare Greater Than or Equal To Single-Precision [ & Record ])
+ case 0x14C: // xvcmpgesp[.] (VSX Vector Compare Greater Than or Equal To Single-Precision [ & Record ])
{
IRTemp vD = newTemp(Ity_V128);
@@ -18198,7 +18496,7 @@
break;
}
- case 0x12C: case 0x32C: //xvcmpgtsp[.] (VSX Vector Compare Greater Than Single-Precision [ & Record ])
+ case 0x12C: //xvcmpgtsp[.] (VSX Vector Compare Greater Than Single-Precision [ & Record ])
{
IRTemp vD = newTemp(Ity_V128);
@@ -18267,16 +18565,19 @@
switch ( opc2 ) {
case 0x0ec: // xscmpexpdp (VSX Scalar Compare Exponents Double-Precision)
{
+ /* Compare 64-bit data, 128-bit layout:
+ src1[0:63] is double word, src1[64:127] is unused
+ src2[0:63] is double word, src2[64:127] is unused
+ */
IRExpr *bit4, *bit5, *bit6, *bit7;
UInt BF = IFIELD( theInstr, 23, 3 );
IRTemp eq_lt_gt = newTemp( Ity_I32 );
IRTemp CC = newTemp( Ity_I32 );
IRTemp vA_hi = newTemp( Ity_I64 );
IRTemp vB_hi = newTemp( Ity_I64 );
- UChar rA_addr = ifieldRegA(theInstr);
- UChar rB_addr = ifieldRegB(theInstr);
+ IRExpr *mask = mkU64( 0x7FF0000000000000 );
- DIP("xscmpexpdp %d,v%d,v%d\n", BF, rA_addr, rB_addr);
+ DIP("xscmpexpdp %d,v%d,v%d\n", BF, XA, XB);
assign( vA_hi, unop( Iop_V128HIto64, mkexpr( vA ) ) );
assign( vB_hi, unop( Iop_V128HIto64, mkexpr( vB ) ) );
@@ -18284,31 +18585,31 @@
/* A exp < B exp */
bit4 = binop( Iop_CmpLT64U,
binop( Iop_And64,
- mkexpr( vA_hi ),
- mkU64( 0x7FFF0000000000 ) ),
+ mkexpr( vA_hi ),
+ mask ),
binop( Iop_And64,
mkexpr( vB_hi ),
- mkU64( 0x7FFF0000000000 ) ) );
+ mask ) );
/* A exp > B exp */
bit5 = binop( Iop_CmpLT64U,
binop( Iop_And64,
mkexpr( vB_hi ),
- mkU64( 0x7FFF00000000000 ) ),
+ mask ),
binop( Iop_And64,
mkexpr( vA_hi ),
- mkU64( 0x7FFF00000000000 ) ) );
+ mask ) );
/* test equal */
bit6 = binop( Iop_CmpEQ64,
binop( Iop_And64,
mkexpr( vA_hi ),
- mkU64( 0x7FFF00000000000 ) ),
+ mask ),
binop( Iop_And64,
- mkexpr( vB_hi ),
- mkU64( 0x7FFF00000000000 ) ) );
+ mkexpr( vB_hi ),
+ mask ) );
/* exp A or exp B is NaN */
- bit7 = mkOR1( is_NaN( Ity_V128, vA ),
- is_NaN( Ity_V128, vB ) );
+ bit7 = mkOR1( is_NaN( Ity_I64, vA_hi ),
+ is_NaN( Ity_I64, vB_hi ) );
assign( eq_lt_gt, binop( Iop_Or32,
binop( Iop_Shl32,
@@ -18322,7 +18623,9 @@
unop( Iop_1Uto32, bit6 ),
mkU8( 1 ) ) ) ) );
assign(CC, binop( Iop_Or32,
- mkexpr( eq_lt_gt ) ,
+ binop( Iop_And32,
+ mkexpr( eq_lt_gt ) ,
+ unop( Iop_Not32, unop( Iop_1Sto32, bit7 ) ) ),
unop( Iop_1Uto32, bit7 ) ) );
putGST_field( PPC_GST_CR, mkexpr( CC ), BF );
@@ -20341,24 +20644,45 @@
unop( Iop_V128to64, mkexpr( vS ) ),
mkU64( 0xFFFFFFFF ) ) );
- store( mkexpr( EA ), unop( Iop_64to32, mkexpr( word0 ) ) );
+ if (host_endness == VexEndnessBE) {
+ store( mkexpr( EA ), unop( Iop_64to32, mkexpr( word0 ) ) );
- ea_off += 4;
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- store( irx_addr, unop( Iop_64to32, mkexpr( word1 ) ) );
+ store( irx_addr, unop( Iop_64to32, mkexpr( word1 ) ) );
- ea_off += 4;
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- store( irx_addr, unop( Iop_64to32, mkexpr( word2 ) ) );
- ea_off += 4;
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ store( irx_addr, unop( Iop_64to32, mkexpr( word2 ) ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- store( irx_addr, unop( Iop_64to32, mkexpr( word3 ) ) );
+ store( irx_addr, unop( Iop_64to32, mkexpr( word3 ) ) );
+ } else {
+ store( mkexpr( EA ), unop( Iop_64to32, mkexpr( word3 ) ) );
+
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ store( irx_addr, unop( Iop_64to32, mkexpr( word2 ) ) );
+
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ store( irx_addr, unop( Iop_64to32, mkexpr( word1 ) ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ store( irx_addr, unop( Iop_64to32, mkexpr( word0 ) ) );
+ }
break;
}
@@ -22247,14 +22571,14 @@
IRDirty* d;
UInt vD_off = vectorGuestRegOffset(vD_addr);
IRExpr** args_be = mkIRExprVec_5(
- IRExpr_BBPTR(),
+ IRExpr_GSPTR(),
mkU32(vD_off),
binop(Iop_And32, mkNarrowTo32(ty, mkexpr(EA)),
mkU32(0xF)),
mkU32(0)/*left*/,
mkU32(1)/*Big Endian*/);
IRExpr** args_le = mkIRExprVec_5(
- IRExpr_BBPTR(),
+ IRExpr_GSPTR(),
mkU32(vD_off),
binop(Iop_And32, mkNarrowTo32(ty, mkexpr(EA)),
mkU32(0xF)),
@@ -22296,14 +22620,14 @@
IRDirty* d;
UInt vD_off = vectorGuestRegOffset(vD_addr);
IRExpr** args_be = mkIRExprVec_5(
- IRExpr_BBPTR(),
+ IRExpr_GSPTR(),
mkU32(vD_off),
binop(Iop_And32, mkNarrowTo32(ty, mkexpr(EA)),
mkU32(0xF)),
mkU32(1)/*right*/,
mkU32(1)/*Big Endian*/);
IRExpr** args_le = mkIRExprVec_5(
- IRExpr_BBPTR(),
+ IRExpr_GSPTR(),
mkU32(vD_off),
binop(Iop_And32, mkNarrowTo32(ty, mkexpr(EA)),
mkU32(0xF)),
@@ -23396,6 +23720,85 @@
break;
}
+ case 0x23: { // vmsumudm
+ DIP("vmsumudm v%d,v%d,v%d,v%d\n",
+ vD_addr, vA_addr, vB_addr, vC_addr);
+ /* This instruction takes input vectors VA, VB consisting of 2 usigned
+ 64-bit integer elements and a 128 bit unsigned input U128_C. The
+ instruction performs the following operation:
+
+ VA[0] * VB[0] -> U128_mul_result0;
+ VA[1] * VB[1] -> U128_mul_result1;
+ U128_C + U128_mul_result0 + U128_mul_result1 -> U128_partial_sum;
+ carry out and overflow is discarded.
+ */
+
+ /* The Iop_MulI128low assumes the upper 64-bits in the two input operands
+ are zero. */
+ IRTemp mul_result0 = newTemp( Ity_I128 );
+ IRTemp mul_result1 = newTemp( Ity_I128 );
+ IRTemp partial_sum_hi = newTemp( Ity_I64 );
+ IRTemp partial_sum_low = newTemp( Ity_I64 );
+ IRTemp result_hi = newTemp( Ity_I64 );
+ IRTemp result_low = newTemp( Ity_I64 );
+ IRExpr *ca_sum, *ca_result;
+
+
+ /* Do multiplications */
+ assign ( mul_result0, binop( Iop_MullU64,
+ unop( Iop_V128to64, mkexpr( vA ) ),
+ unop( Iop_V128to64, mkexpr( vB) ) ) );
+
+ assign ( mul_result1, binop( Iop_MullU64,
+ unop( Iop_V128HIto64, mkexpr( vA ) ),
+ unop( Iop_V128HIto64, mkexpr( vB) ) ) );
+
+ /* Add the two 128-bit results using 64-bit unsigned adds, calculate carry
+ from low 64-bits add into sum of upper 64-bits. Throw away carry out
+ of the upper 64-bit sum. */
+ assign ( partial_sum_low, binop( Iop_Add64,
+ unop( Iop_128to64, mkexpr( mul_result0 ) ),
+ unop( Iop_128to64, mkexpr( mul_result1 ) )
+ ) );
+
+ /* ca_sum is type U32 */
+ ca_sum = calculate_XER_CA_64 ( PPCG_FLAG_OP_ADD,
+ mkexpr(partial_sum_low ),
+ unop( Iop_128to64, mkexpr( mul_result0 ) ),
+ unop( Iop_128to64, mkexpr( mul_result1 ) ),
+ mkU64( 0 ) );
+
+ assign ( partial_sum_hi,
+ binop( Iop_Add64,
+ binop( Iop_Add64,
+ unop( Iop_128HIto64, mkexpr( mul_result0 ) ),
+ unop( Iop_128HIto64, mkexpr( mul_result1 ) ) ),
+ binop( Iop_32HLto64, mkU32( 0 ), ca_sum ) ) );
+
+ /* Now add in the value of C */
+ assign ( result_low, binop( Iop_Add64,
+ mkexpr( partial_sum_low ),
+ unop( Iop_V128to64, mkexpr( vC ) ) ) );
+
+ /* ca_result is type U32 */
+ ca_result = calculate_XER_CA_64( PPCG_FLAG_OP_ADD,
+ mkexpr( result_low ),
+ mkexpr( partial_sum_low ),
+ unop( Iop_V128to64,
+ mkexpr( vC ) ),
+ mkU64( 0 ) );
+
+ assign ( result_hi,
+ binop( Iop_Add64,
+ binop( Iop_Add64,
+ mkexpr( partial_sum_hi ),
+ unop( Iop_V128HIto64, mkexpr( vC ) ) ),
+ binop( Iop_32HLto64, mkU32( 0 ), ca_result ) ) );
+
+ putVReg( vD_addr, binop( Iop_64HLtoV128,
+ mkexpr( result_hi ), mkexpr ( result_low ) ) );
+ break;
+ }
/* Multiply-Sum */
case 0x24: { // vmsumubm (Multiply Sum Unsigned B Modulo, AV p204)
@@ -27043,17 +27446,93 @@
};
// ATTENTION: Keep this array sorted on the opcocde!!!
-static struct vsx_insn vsx_all[] = {
- { 0x0, "xsaddsp" },
- { 0x4, "xsmaddasp" },
- { 0x8, "xxsldwi" },
+static struct vsx_insn vsx_xx2[] = {
{ 0x14, "xsrsqrtesp" },
{ 0x16, "xssqrtsp" },
{ 0x18, "xxsel" },
+ { 0x34, "xsresp" },
+ { 0x90, "xscvdpuxws" },
+ { 0x92, "xsrdpi" },
+ { 0x94, "xsrsqrtedp" },
+ { 0x96, "xssqrtdp" },
+ { 0xb0, "xscvdpsxws" },
+ { 0xb2, "xsrdpiz" },
+ { 0xb4, "xsredp" },
+ { 0xd2, "xsrdpip" },
+ { 0xd4, "xstsqrtdp" },
+ { 0xd6, "xsrdpic" },
+ { 0xf2, "xsrdpim" },
+ { 0x112, "xvrspi" },
+ { 0x116, "xvsqrtsp" },
+ { 0x130, "xvcvspsxws" },
+ { 0x132, "xvrspiz" },
+ { 0x134, "xvresp" },
+ { 0x148, "xxspltw" },
+ { 0x14A, "xxextractuw" },
+ { 0x150, "xvcvuxwsp" },
+ { 0x152, "xvrspip" },
+ { 0x154, "xvtsqrtsp" },
+ { 0x156, "xvrspic" },
+ { 0x16A, "xxinsertw" },
+ { 0x170, "xvcvsxwsp" },
+ { 0x172, "xvrspim" },
+ { 0x190, "xvcvdpuxws" },
+ { 0x192, "xvrdpi" },
+ { 0x194, "xvrsqrtedp" },
+ { 0x196, "xvsqrtdp" },
+ { 0x1b0, "xvcvdpsxws" },
+ { 0x1b2, "xvrdpiz" },
+ { 0x1b4, "xvredp" },
+ { 0x1d0, "xvcvuxwdp" },
+ { 0x1d2, "xvrdpip" },
+ { 0x1d4, "xvtsqrtdp" },
+ { 0x1d6, "xvrdpic" },
+ { 0x1f0, "xvcvsxwdp" },
+ { 0x1f2, "xvrdpim" },
+ { 0x212, "xscvdpsp" },
+ { 0x216, "xscvdpspn" },
+ { 0x232, "xxrsp" },
+ { 0x250, "xscvuxdsp" },
+ { 0x254, "xststdcsp" },
+ { 0x270, "xscvsxdsp" },
+ { 0x290, "xscvdpuxds" },
+ { 0x292, "xscvspdp" },
+ { 0x296, "xscvspdpn" },
+ { 0x2b0, "xscvdpsxds" },
+ { 0x2b2, "xsabsdp" },
+ { 0x2b6, "xsxexpdp_xsxigdp" },
+ { 0x2d0, "xscvuxddp" },
+ { 0x2d2, "xsnabsdp" },
+ { 0x2d4, "xststdcdp" },
+ { 0x2e4, "xsnmsubmdp" },
+ { 0x2f0, "xscvsxddp" },
+ { 0x2f2, "xsnegdp" },
+ { 0x310, "xvcvspuxds" },
+ { 0x312, "xvcvdpsp" },
+ { 0x330, "xvcvspsxds" },
+ { 0x332, "xvabssp" },
+ { 0x350, "xvcvuxdsp" },
+ { 0x352, "xvnabssp" },
+ { 0x370, "xvcvsxdsp" },
+ { 0x372, "xvnegsp" },
+ { 0x390, "xvcvdpuxds" },
+ { 0x392, "xvcvspdp" },
+ { 0x3b0, "xvcvdpsxds" },
+ { 0x3b2, "xvabsdp" },
+ { 0x3b6, "xxbr[h|w|d|q]|xvxexpdp|xvxexpsp|xvxsigdp|xvxsigsp|xvcvhpsp|xvcvsphp|xscvdphp|xscvhpdp" },
+ { 0x3d0, "xvcvuxddp" },
+ { 0x3d2, "xvnabsdp" },
+ { 0x3f2, "xvnegdp" }
+};
+#define VSX_XX2_LEN (sizeof vsx_xx2 / sizeof *vsx_xx2)
+
+// ATTENTION: Keep this array sorted on the opcocde!!!
+static struct vsx_insn vsx_xx3[] = {
+ { 0x0, "xsaddsp" },
+ { 0x4, "xsmaddasp" },
+ { 0x9, "xsmaddmsp" },
{ 0x20, "xssubsp" },
{ 0x24, "xsmaddmsp" },
- { 0x28, "xxpermdi" },
- { 0x34, "xsresp" },
{ 0x3A, "xxpermr" },
{ 0x40, "xsmulsp" },
{ 0x44, "xsmsubasp" },
@@ -27064,174 +27543,114 @@
{ 0x80, "xsadddp" },
{ 0x84, "xsmaddadp" },
{ 0x8c, "xscmpudp" },
- { 0x90, "xscvdpuxws" },
- { 0x92, "xsrdpi" },
- { 0x94, "xsrsqrtedp" },
- { 0x96, "xssqrtdp" },
{ 0xa0, "xssubdp" },
{ 0xa4, "xsmaddmdp" },
{ 0xac, "xscmpodp" },
- { 0xb0, "xscvdpsxws" },
- { 0xb2, "xsrdpiz" },
- { 0xb4, "xsredp" },
{ 0xc0, "xsmuldp" },
{ 0xc4, "xsmsubadp" },
{ 0xc8, "xxmrglw" },
- { 0xd2, "xsrdpip" },
{ 0xd4, "xstsqrtdp" },
- { 0xd6, "xsrdpic" },
{ 0xe0, "xsdivdp" },
{ 0xe4, "xsmsubmdp" },
{ 0xe8, "xxpermr" },
{ 0xeC, "xscmpexpdp" },
- { 0xf2, "xsrdpim" },
{ 0xf4, "xstdivdp" },
{ 0x100, "xvaddsp" },
{ 0x104, "xvmaddasp" },
- { 0x10c, "xvcmpeqsp" },
+ { 0x10C, "xvcmpeqsp" },
{ 0x110, "xvcvspuxws" },
- { 0x112, "xvrspi" },
{ 0x114, "xvrsqrtesp" },
- { 0x116, "xvsqrtsp" },
{ 0x120, "xvsubsp" },
{ 0x124, "xvmaddmsp" },
- { 0x12c, "xvcmpgtsp" },
{ 0x130, "xvcvspsxws" },
- { 0x132, "xvrspiz" },
- { 0x134, "xvresp" },
{ 0x140, "xvmulsp" },
{ 0x144, "xvmsubasp" },
- { 0x148, "xxspltw" },
- { 0x14A, "xxextractuw" },
- { 0x14c, "xvcmpgesp" },
- { 0x150, "xvcvuxwsp" },
- { 0x152, "xvrspip" },
- { 0x154, "xvtsqrtsp" },
- { 0x156, "xvrspic" },
+ { 0x14C, "xvcmpgesp", },
{ 0x160, "xvdivsp" },
{ 0x164, "xvmsubmsp" },
- { 0x16A, "xxinsertw" },
- { 0x170, "xvcvsxwsp" },
- { 0x172, "xvrspim" },
{ 0x174, "xvtdivsp" },
{ 0x180, "xvadddp" },
{ 0x184, "xvmaddadp" },
- { 0x18c, "xvcmpeqdp" },
- { 0x190, "xvcvdpuxws" },
- { 0x192, "xvrdpi" },
- { 0x194, "xvrsqrtedp" },
- { 0x196, "xvsqrtdp" },
+ { 0x18C, "xvcmpeqdp" },
{ 0x1a0, "xvsubdp" },
{ 0x1a4, "xvmaddmdp" },
- { 0x1ac, "xvcmpgtdp" },
- { 0x1b0, "xvcvdpsxws" },
- { 0x1b2, "xvrdpiz" },
- { 0x1b4, "xvredp" },
+ { 0x1aC, "xvcmpgtdp" },
{ 0x1c0, "xvmuldp" },
{ 0x1c4, "xvmsubadp" },
{ 0x1cc, "xvcmpgedp" },
- { 0x1d0, "xvcvuxwdp" },
- { 0x1d2, "xvrdpip" },
- { 0x1d4, "xvtsqrtdp" },
- { 0x1d6, "xvrdpic" },
{ 0x1e0, "xvdivdp" },
{ 0x1e4, "xvmsubmdp" },
- { 0x1f0, "xvcvsxwdp" },
- { 0x1f2, "xvrdpim" },
{ 0x1f4, "xvtdivdp" },
{ 0x204, "xsnmaddasp" },
{ 0x208, "xxland" },
- { 0x212, "xscvdpsp" },
- { 0x216, "xscvdpspn" },
{ 0x224, "xsnmaddmsp" },
{ 0x228, "xxlandc" },
- { 0x232, "xxrsp" },
{ 0x244, "xsnmsubasp" },
{ 0x248, "xxlor" },
- { 0x250, "xscvuxdsp" },
- { 0x254, "xststdcsp" },
{ 0x264, "xsnmsubmsp" },
{ 0x268, "xxlxor" },
- { 0x270, "xscvsxdsp" },
{ 0x280, "xsmaxdp" },
{ 0x284, "xsnmaddadp" },
{ 0x288, "xxlnor" },
- { 0x290, "xscvdpuxds" },
- { 0x292, "xscvspdp" },
- { 0x296, "xscvspdpn" },
{ 0x2a0, "xsmindp" },
{ 0x2a4, "xsnmaddmdp" },
{ 0x2a8, "xxlorc" },
- { 0x2b0, "xscvdpsxds" },
- { 0x2b2, "xsabsdp" },
- { 0x2b6, "xsxexpdp_xsxigdp" },
{ 0x2c0, "xscpsgndp" },
{ 0x2c4, "xsnmsubadp" },
{ 0x2c8, "xxlnand" },
- { 0x2d0, "xscvuxddp" },
- { 0x2d2, "xsnabsdp" },
- { 0x2d4, "xststdcdp" },
{ 0x2e4, "xsnmsubmdp" },
{ 0x2e8, "xxleqv" },
- { 0x2f0, "xscvsxddp" },
- { 0x2f2, "xsnegdp" },
{ 0x300, "xvmaxsp" },
{ 0x304, "xvnmaddasp" },
- { 0x30c, "xvcmpeqsp." },
- { 0x310, "xvcvspuxds" },
- { 0x312, "xvcvdpsp" },
{ 0x320, "xvminsp" },
{ 0x324, "xvnmaddmsp" },
- { 0x32c, "xvcmpgtsp." },
- { 0x330, "xvcvspsxds" },
- { 0x332, "xvabssp" },
{ 0x340, "xvcpsgnsp" },
{ 0x344, "xvnmsubasp" },
- { 0x34c, "xvcmpgesp." },
- { 0x350, "xvcvuxdsp" },
- { 0x352, "xvnabssp" },
- { 0x354, "xvtstdcsp" },
{ 0x360, "xviexpsp" },
{ 0x364, "xvnmsubmsp" },
- { 0x370, "xvcvsxdsp" },
- { 0x372, "xvnegsp" },
{ 0x380, "xvmaxdp" },
{ 0x384, "xvnmaddadp" },
- { 0x38c, "xvcmpeqdp." },
- { 0x390, "xvcvdpuxds" },
- { 0x392, "xvcvspdp" },
- { 0x396, "xsiexpdp" },
{ 0x3a0, "xvmindp" },
{ 0x3a4, "xvnmaddmdp" },
- { 0x3ac, "xvcmpgtdp." },
- { 0x3b0, "xvcvdpsxds" },
- { 0x3b2, "xvabsdp" },
- { 0x3b6, "xxbr[h|w|d|q]|xvxexpdp|xvxexpsp|xvxsigdp|xvxsigsp|xvcvhpsp|xvcvsphp|xscvdphp|xscvhpdp" },
{ 0x3c0, "xvcpsgndp" },
{ 0x3c4, "xvnmsubadp" },
- { 0x3cc, "xvcmpgedp." },
- { 0x3d0, "xvcvuxddp" },
- { 0x3d2, "xvnabsdp" },
- { 0x3d4, "xvtstdcdp" },
{ 0x3e0, "xviexpdp" },
{ 0x3e4, "xvnmsubmdp" },
{ 0x3f0, "xvcvsxddp" },
- { 0x3f2, "xvnegdp" }
};
-#define VSX_ALL_LEN (sizeof vsx_all / sizeof *vsx_all)
+#define VSX_XX3_LEN (sizeof vsx_xx3 / sizeof *vsx_xx3)
-// ATTENTION: This search function assumes vsx_all array is sorted.
-static Int findVSXextOpCode(UInt opcode)
+/* ATTENTION: These search functions assumes vsx_xx2 and vsx_xx3 arrays
+ * are sorted.
+ */
+static Int findVSXextOpCode_xx2(UInt opcode)
{
Int low, mid, high;
low = 0;
- high = VSX_ALL_LEN - 1;
+ high = VSX_XX2_LEN - 1;
while (low <= high) {
mid = (low + high)/2;
- if (opcode < vsx_all[mid].opcode)
+ if (opcode < vsx_xx2[mid].opcode)
high = mid - 1;
- else if (opcode > vsx_all[mid].opcode)
+ else if (opcode > vsx_xx2[mid].opcode)
+ low = mid + 1;
+ else
+ return mid;
+ }
+ return -1;
+}
+
+static Int findVSXextOpCode_xx3(UInt opcode)
+{
+ Int low, mid, high;
+ low = 0;
+ high = VSX_XX3_LEN - 1;
+ while (low <= high) {
+ mid = (low + high)/2;
+ if (opcode < vsx_xx3[mid].opcode)
+ high = mid - 1;
+ else if (opcode > vsx_xx3[mid].opcode)
low = mid + 1;
else
return mid;
@@ -27244,31 +27663,68 @@
* passed, and we then try to match it up with one of the VSX forms
* below.
*/
-static UInt get_VSX60_opc2(UInt opc2_full)
+static UInt get_VSX60_opc2(UInt opc2_full, UInt theInstr)
{
-#define XX2_MASK 0x000003FE
+#define XX2_1_MASK 0x000003FF // xsiexpdp specific
+#define XX2_2_MASK 0x000003FE
#define XX3_1_MASK 0x000003FC
#define XX3_2_MASK 0x000001FC
-#define XX3_3_MASK 0x0000007C
-#define XX4_MASK 0x00000018
-#define VDCMX_MASK 0x000003B8
+#define XX3_4_MASK 0x0000027C
+#define XX3_5_MASK 0x000003DC
+#define XX4_MASK 0x00000018
+
Int ret;
UInt vsxExtOpcode = 0;
- if (( ret = findVSXextOpCode(opc2_full & XX2_MASK)) >= 0)
- vsxExtOpcode = vsx_all[ret].opcode;
- else if (( ret = findVSXextOpCode(opc2_full & XX3_1_MASK)) >= 0)
- vsxExtOpcode = vsx_all[ret].opcode;
- else if (( ret = findVSXextOpCode(opc2_full & VDCMX_MASK)) >= 0)
- vsxExtOpcode = vsx_all[ret].opcode;
- else if (( ret = findVSXextOpCode(opc2_full & XX3_2_MASK)) >= 0)
- vsxExtOpcode = vsx_all[ret].opcode;
- else if (( ret = findVSXextOpCode(opc2_full & XX3_3_MASK)) >= 0)
- vsxExtOpcode = vsx_all[ret].opcode;
- else if (( ret = findVSXextOpCode(opc2_full & XX4_MASK)) >= 0)
- vsxExtOpcode = vsx_all[ret].opcode;
+ if (( ret = findVSXextOpCode_xx2(opc2_full & XX2_2_MASK)) >= 0)
+ return vsx_xx2[ret].opcode;
+ else if ((opc2_full & XX2_1_MASK) == 0x396 ) // xsiexpdp
+ return 0x396;
+ else if (( ret = findVSXextOpCode_xx3(opc2_full & XX3_1_MASK)) >= 0)
+ return vsx_xx3[ret].opcode;
+ else {
- return vsxExtOpcode;
+ /* There are only a few codes in each of these cases it is
+ * probably faster to check for the codes then do the array lookups.
+ */
+ vsxExtOpcode = opc2_full & XX3_2_MASK;
+
+ switch (vsxExtOpcode) {
+ case 0x10C: return vsxExtOpcode; // xvcmpeqsp
+ case 0x12C: return vsxExtOpcode; // xvcmpgtsp, xvcmpgtsp.
+ case 0x14C: return vsxExtOpcode; // xvcmpgesp, xvcmpgesp.
+ case 0x18C: return vsxExtOpcode; // xvcmpeqdp, xvcmpeqdp.
+ case 0x1AC: return vsxExtOpcode; // xvcmpgtdp, xvcmpgtdp.
+ case 0x1CC: return vsxExtOpcode; // xvcmpgedp, xvcmpgedp.
+ default: break;
+ }
+
+ vsxExtOpcode = opc2_full & XX3_4_MASK;
+
+ switch (vsxExtOpcode) {
+ case 0x8: return vsxExtOpcode; // xxsldwi
+ case 0x28: return vsxExtOpcode; // xxpermdi
+ default: break;
+ }
+
+ vsxExtOpcode = opc2_full & XX3_5_MASK;
+
+ switch (vsxExtOpcode) {
+ case 0x354: return vsxExtOpcode; // xvtstdcsp
+ case 0x3D4: return vsxExtOpcode; // xvtstdcdp
+ default: break;
+ }
+
+ if (( opc2_full & XX4_MASK ) == XX4_MASK ) { // xxsel
+ vsxExtOpcode = 0x18;
+ return vsxExtOpcode;
+ }
+ }
+
+ vex_printf( "Error: undefined opcode 0x %x, the instruction = 0x %x\n",
+ opc2_full, theInstr );
+ vpanic( "ERROR: get_VSX60_opc2()\n" );
+ return 0;
}
/*------------------------------------------------------------*/
@@ -27294,6 +27750,8 @@
DisResult dres;
UInt theInstr;
IRType ty = mode64 ? Ity_I64 : Ity_I32;
+ UInt hwcaps = archinfo->hwcaps;
+ Long delta;
Bool allow_F = False;
Bool allow_V = False;
Bool allow_FX = False;
@@ -27302,8 +27760,6 @@
Bool allow_DFP = False;
Bool allow_isa_2_07 = False;
Bool allow_isa_3_0 = False;
- UInt hwcaps = archinfo->hwcaps;
- Long delta;
/* What insn variants are we supporting today? */
if (mode64) {
@@ -27326,6 +27782,9 @@
allow_isa_3_0 = (0 != (hwcaps & VEX_HWCAPS_PPC32_ISA3_0));
}
+ /* Enable writting the OV32 and CA32 bits added with ISA3.0 */
+ OV32_CA32_supported = allow_isa_3_0;
+
/* The running delta */
delta = (Long)mkSzAddr(ty, (ULong)delta64);
@@ -27334,6 +27793,7 @@
dres.len = 0;
dres.continueAt = 0;
dres.jk_StopHere = Ijk_INVALID;
+ dres.hint = Dis_HintNone;
/* At least this is simple on PPC32: insns are all 4 bytes long, and
4-aligned. So just fish the whole thing out of memory right now
@@ -27718,7 +28178,7 @@
opc2 = ifieldOPClo10(theInstr);
UInt opc2hi = IFIELD(theInstr, 7, 4);
UInt opc2lo = IFIELD(theInstr, 3, 3);
- UInt vsxOpc2 = get_VSX60_opc2(opc2);
+ UInt vsxOpc2;
if (( opc2hi == 13 ) && ( opc2lo == 5)) { //xvtstdcsp
if (dis_vxs_misc(theInstr, 0x354, allow_isa_3_0))
@@ -27747,6 +28207,8 @@
goto decode_failure;
}
+ vsxOpc2 = get_VSX60_opc2(opc2, theInstr);
+
switch (vsxOpc2) {
case 0x8: case 0x28: case 0x48: case 0xc8: // xxsldwi, xxpermdi, xxmrghw, xxmrglw
case 0x068: case 0xE8: // xxperm, xxpermr
@@ -27851,12 +28313,12 @@
if (dis_vx_conv(theInstr, vsxOpc2)) goto decode_success;
goto decode_failure;
- case 0x18C: case 0x38C: // xvcmpeqdp[.]
- case 0x10C: case 0x30C: // xvcmpeqsp[.]
- case 0x14C: case 0x34C: // xvcmpgesp[.]
- case 0x12C: case 0x32C: // xvcmpgtsp[.]
- case 0x1CC: case 0x3CC: // xvcmpgedp[.]
- case 0x1AC: case 0x3AC: // xvcmpgtdp[.]
+ case 0x18C: // xvcmpeqdp[.]
+ case 0x10C: // xvcmpeqsp[.]
+ case 0x14C: // xvcmpgesp[.]
+ case 0x12C: // xvcmpgtsp[.]
+ case 0x1CC: // xvcmpgedp[.]
+ case 0x1AC: // xvcmpgtdp[.]
if (dis_vvec_cmp(theInstr, vsxOpc2)) goto decode_success;
goto decode_failure;
@@ -28041,7 +28503,8 @@
case 0x040: // mcrfs
case 0x046: // mtfsb0
case 0x086: // mtfsfi
- case 0x247: // mffs
+ case 0x247: // mffs, mmfs., mffsce, mffscdrn, mffscdrni,
+ // mffscrn, mffscrn, mffscri, mffsl
case 0x2C7: // mtfsf
// Some of the above instructions need to know more about the
// ISA level supported by the host.
@@ -28186,6 +28649,7 @@
switch (opc2) {
/* Integer Arithmetic Instructions */
case 0x10A: case 0x00A: case 0x08A: // add, addc, adde
+ case 0x0AA: // addex
case 0x0EA: case 0x0CA: case 0x1EB: // addme, addze, divw
case 0x1CB: case 0x04B: case 0x00B: // divwu, mulhw, mulhwu
case 0x0EB: case 0x068: case 0x028: // mullw, neg, subf
@@ -28568,6 +29032,7 @@
switch (opc2) {
/* AV Mult-Add, Mult-Sum */
case 0x20: case 0x21: case 0x22: // vmhaddshs, vmhraddshs, vmladduhm
+ case 0x23: // vmsumudm
case 0x24: case 0x25: case 0x26: // vmsumubm, vmsummbm, vmsumuhm
case 0x27: case 0x28: case 0x29: // vmsumuhs, vmsumshm, vmsumshs
if (!allow_V) goto decode_noV;
@@ -29038,6 +29503,7 @@
dres.whatNext = Dis_StopHere;
dres.jk_StopHere = Ijk_NoDecode;
dres.continueAt = 0;
+ dres.hint = Dis_HintNone;
return dres;
}
@@ -29048,7 +29514,7 @@
mask64 = VEX_HWCAPS_PPC64_V | VEX_HWCAPS_PPC64_FX
| VEX_HWCAPS_PPC64_GX | VEX_HWCAPS_PPC64_VX | VEX_HWCAPS_PPC64_DFP
- | VEX_HWCAPS_PPC64_ISA2_07;
+ | VEX_HWCAPS_PPC64_ISA2_07 | VEX_HWCAPS_PPC64_ISA3_0;
if (mode64) {
vassert((hwcaps_guest & mask32) == 0);
diff --git a/VEX/priv/guest_s390_defs.h b/VEX/priv/guest_s390_defs.h
index cfe5f2f..8ba6d94 100644
--- a/VEX/priv/guest_s390_defs.h
+++ b/VEX/priv/guest_s390_defs.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2015
+ Copyright IBM Corp. 2010-2017
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -39,7 +39,7 @@
/* Convert one s390 insn to IR. See the type DisOneInstrFn in
- bb_to_IR.h. */
+ guest_generic_bb_to_IR.h. */
DisResult disInstr_S390 ( IRSB* irbb,
Bool (*resteerOkFn) ( void*, Addr ),
Bool resteerCisOk,
diff --git a/VEX/priv/guest_s390_helpers.c b/VEX/priv/guest_s390_helpers.c
index f484f8e..4cccdec 100644
--- a/VEX/priv/guest_s390_helpers.c
+++ b/VEX/priv/guest_s390_helpers.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2015
+ Copyright IBM Corp. 2010-2017
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c
index 59cddfd..14c8950 100644
--- a/VEX/priv/guest_s390_toIR.c
+++ b/VEX/priv/guest_s390_toIR.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2016
+ Copyright IBM Corp. 2010-2017
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -13172,10 +13172,10 @@
IRDirty *d;
IRTemp cc = newTemp(Ity_I64);
- /* IRExpr_BBPTR() => Need to pass pointer to guest state to helper */
+ /* IRExpr_GSPTR() => Need to pass pointer to guest state to helper */
d = unsafeIRDirty_1_N(cc, 0, "s390x_dirtyhelper_STFLE",
&s390x_dirtyhelper_STFLE,
- mkIRExprVec_2(IRExpr_BBPTR(), mkexpr(op2addr)));
+ mkIRExprVec_2(IRExpr_GSPTR(), mkexpr(op2addr)));
d->nFxState = 1;
vex_bzero(&d->fxState, sizeof(d->fxState));
@@ -16832,6 +16832,7 @@
dres.len = insn_length;
dres.continueAt = 0;
dres.jk_StopHere = Ijk_INVALID;
+ dres.hint = Dis_HintNone;
/* fixs390: consider chasing of conditional jumps */
diff --git a/VEX/priv/guest_tilegx_defs.h b/VEX/priv/guest_tilegx_defs.h
deleted file mode 100644
index 9910890..0000000
--- a/VEX/priv/guest_tilegx_defs.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*---------------------------------------------------------------*/
-/*--- begin guest_tilegx_defs.h ---*/
-/*---------------------------------------------------------------*/
-
-/*
- This file is part of Valgrind, a dynamic binary instrumentation
- framework.
-
- Copyright (C) 2010-2015 Tilera Corp.
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of the
- License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful, but
- WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
- 02111-1307, USA.
-
- The GNU General Public License is contained in the file COPYING.
-*/
-
- /* Contributed by Zhi-Gang Liu <zliu at tilera dot com> */
-
-#ifndef __VEX_GUEST_TILEGX_DEFS_H
-#define __VEX_GUEST_TILEGX_DEFS_H
-
-#ifdef __tilegx__
-#include "tilegx_disasm.h"
-#endif
-
-/*---------------------------------------------------------*/
-/*--- tilegx to IR conversion ---*/
-/*---------------------------------------------------------*/
-
-/* Convert one TILEGX insn to IR. See the type DisOneInstrFn in
- bb_to_IR.h. */
-extern DisResult disInstr_TILEGX ( IRSB* irbb,
- Bool (*resteerOkFn) ( void *, Addr ),
- Bool resteerCisOk,
- void* callback_opaque,
- const UChar* guest_code,
- Long delta,
- Addr guest_IP,
- VexArch guest_arch,
- const VexArchInfo* archinfo,
- const VexAbiInfo* abiinfo,
- VexEndness host_endness_IN,
- Bool sigill_diag_IN );
-
-/* Used by the optimiser to specialise calls to helpers. */
-extern IRExpr *guest_tilegx_spechelper ( const HChar * function_name,
- IRExpr ** args,
- IRStmt ** precedingStmts,
- Int n_precedingStmts );
-
-/* Describes to the optimser which part of the guest state require
- precise memory exceptions. This is logically part of the guest
- state description. */
-extern Bool guest_tilegx_state_requires_precise_mem_exns (
- Int, Int, VexRegisterUpdates );
-
-extern VexGuestLayout tilegxGuest_layout;
-
-/*---------------------------------------------------------*/
-/*--- tilegx guest helpers ---*/
-/*---------------------------------------------------------*/
-
-extern ULong tilegx_dirtyhelper_gen ( ULong opc,
- ULong rd0,
- ULong rd1,
- ULong rd2,
- ULong rd3 );
-
-/*---------------------------------------------------------*/
-/*--- Condition code stuff ---*/
-/*---------------------------------------------------------*/
-
-/* Defines conditions which we can ask for TILEGX */
-
-typedef enum {
- TILEGXCondEQ = 0, /* equal : Z=1 */
- TILEGXCondNE = 1, /* not equal : Z=0 */
- TILEGXCondHS = 2, /* >=u (higher or same) : C=1 */
- TILEGXCondLO = 3, /* <u (lower) : C=0 */
- TILEGXCondMI = 4, /* minus (negative) : N=1 */
- TILEGXCondPL = 5, /* plus (zero or +ve) : N=0 */
- TILEGXCondVS = 6, /* overflow : V=1 */
- TILEGXCondVC = 7, /* no overflow : V=0 */
- TILEGXCondHI = 8, /* >u (higher) : C=1 && Z=0 */
- TILEGXCondLS = 9, /* <=u (lower or same) : C=0 || Z=1 */
- TILEGXCondGE = 10, /* >=s (signed greater or equal) : N=V */
- TILEGXCondLT = 11, /* <s (signed less than) : N!=V */
- TILEGXCondGT = 12, /* >s (signed greater) : Z=0 && N=V */
- TILEGXCondLE = 13, /* <=s (signed less or equal) : Z=1 || N!=V */
- TILEGXCondAL = 14, /* always (unconditional) : 1 */
- TILEGXCondNV = 15 /* never (unconditional): : 0 */
-} TILEGXCondcode;
-
-#endif /* __VEX_GUEST_TILEGX_DEFS_H */
-
-/*---------------------------------------------------------------*/
-/*--- end guest_tilegx_defs.h ---*/
-/*---------------------------------------------------------------*/
diff --git a/VEX/priv/guest_tilegx_helpers.c b/VEX/priv/guest_tilegx_helpers.c
deleted file mode 100644
index b26c06d..0000000
--- a/VEX/priv/guest_tilegx_helpers.c
+++ /dev/null
@@ -1,1103 +0,0 @@
-/*---------------------------------------------------------------*/
-/*--- begin guest_tilegx_helpers.c ---*/
-/*---------------------------------------------------------------*/
-
-/*
- This file is part of Valgrind, a dynamic binary instrumentation
- framework.
-
- Copyright (C) 2010-2015 Tilera Corp.
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of the
- License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful, but
- WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
- 02111-1307, USA.
-
- The GNU General Public License is contained in the file COPYING.
-*/
-
-/* Contributed by Zhi-Gang Liu <zliu at tilera dot com> */
-
-#include "libvex_basictypes.h"
-#include "libvex_emnote.h"
-#include "libvex_guest_tilegx.h"
-#include "libvex_ir.h"
-#include "libvex.h"
-
-#include "main_util.h"
-#include "guest_generic_bb_to_IR.h"
-#include "guest_tilegx_defs.h"
-
-/* This file contains helper functions for tilegx guest code. Calls to
- these functions are generated by the back end.
-*/
-
-#define ALWAYSDEFD(field) \
- { offsetof(VexGuestTILEGXState, field), \
- (sizeof ((VexGuestTILEGXState*)0)->field) }
-
-IRExpr *guest_tilegx_spechelper ( const HChar * function_name, IRExpr ** args,
- IRStmt ** precedingStmts, Int n_precedingStmts)
-{
- return NULL;
-}
-
-/* VISIBLE TO LIBVEX CLIENT */
-void LibVEX_GuestTILEGX_initialise ( VexGuestTILEGXState * vex_state )
-{
- vex_state->guest_r0 = 0;
- vex_state->guest_r1 = 0;
- vex_state->guest_r2 = 0;
- vex_state->guest_r3 = 0;
- vex_state->guest_r4 = 0;
- vex_state->guest_r5 = 0;
- vex_state->guest_r6 = 0;
- vex_state->guest_r7 = 0;
- vex_state->guest_r8 = 0;
- vex_state->guest_r9 = 0;
- vex_state->guest_r10 = 0;
- vex_state->guest_r11 = 0;
- vex_state->guest_r12 = 0;
- vex_state->guest_r13 = 0;
- vex_state->guest_r14 = 0;
- vex_state->guest_r15 = 0;
- vex_state->guest_r16 = 0;
- vex_state->guest_r17 = 0;
- vex_state->guest_r18 = 0;
- vex_state->guest_r19 = 0;
- vex_state->guest_r20 = 0;
- vex_state->guest_r21 = 0;
- vex_state->guest_r22 = 0;
- vex_state->guest_r23 = 0;
- vex_state->guest_r24 = 0;
- vex_state->guest_r25 = 0;
- vex_state->guest_r26 = 0;
- vex_state->guest_r27 = 0;
- vex_state->guest_r28 = 0;
- vex_state->guest_r29 = 0;
- vex_state->guest_r30 = 0;
- vex_state->guest_r31 = 0;
- vex_state->guest_r32 = 0;
- vex_state->guest_r33 = 0;
- vex_state->guest_r34 = 0;
- vex_state->guest_r35 = 0;
- vex_state->guest_r36 = 0;
- vex_state->guest_r37 = 0;
- vex_state->guest_r38 = 0;
- vex_state->guest_r39 = 0;
- vex_state->guest_r40 = 0;
- vex_state->guest_r41 = 0;
- vex_state->guest_r42 = 0;
- vex_state->guest_r43 = 0;
- vex_state->guest_r44 = 0;
- vex_state->guest_r45 = 0;
- vex_state->guest_r46 = 0;
- vex_state->guest_r47 = 0;
- vex_state->guest_r48 = 0;
- vex_state->guest_r49 = 0;
- vex_state->guest_r50 = 0;
- vex_state->guest_r51 = 0;
- vex_state->guest_r52 = 0;
- vex_state->guest_r53 = 0;
- vex_state->guest_r54 = 0;
- vex_state->guest_r55 = 0;
-
- vex_state->guest_pc = 0; /* Program counter */
-
- vex_state->guest_EMNOTE = 0;
- vex_state->guest_CMSTART = 0;
-
- /* For clflush: record start and length of area to invalidate */
- vex_state->guest_CMSTART = 0;
- vex_state->guest_CMLEN = 0;
-
- /* Used to record the unredirected guest address at the start of
- a translation whose start has been redirected. By reading
- this pseudo-register shortly afterwards, the translation can
- find out what the corresponding no-redirection address was.
- Note, this is only set for wrap-style redirects, not for
- replace-style ones. */
- vex_state->guest_NRADDR = 0;
-}
-
-/*-----------------------------------------------------------*/
-/*--- Describing the tilegx guest state, for the benefit ---*/
-/*--- of iropt and instrumenters. ---*/
-/*-----------------------------------------------------------*/
-
-/* Figure out if any part of the guest state contained in minoff
- .. maxoff requires precise memory exceptions. If in doubt return
- True (but this is generates significantly slower code).
-
- We enforce precise exns for guest SP, PC.
-*/
-Bool guest_tilegx_state_requires_precise_mem_exns (
- Int minoff, Int maxoff,
- VexRegisterUpdates pxControl)
-{
- Int sp_min = offsetof(VexGuestTILEGXState, guest_r54);
- Int sp_max = sp_min + 8 - 1;
- Int pc_min = offsetof(VexGuestTILEGXState, guest_pc);
- Int pc_max = pc_min + 8 - 1;
-
- if (maxoff < sp_min || minoff > sp_max) {
- /* no overlap with sp */
- if (pxControl == VexRegUpdSpAtMemAccess)
- return False; /* We only need to check stack pointer. */
- } else {
- return True;
- }
-
- if (maxoff < pc_min || minoff > pc_max) {
- /* no overlap with pc */
- } else {
- return True;
- }
-
- /* We appear to need precise updates of R52 in order to get proper
- stacktraces from non-optimised code. */
- Int fp_min = offsetof(VexGuestTILEGXState, guest_r52);
- Int fp_max = fp_min + 8 - 1;
-
- if (maxoff < fp_min || minoff > fp_max) {
- /* no overlap with fp */
- } else {
- return True;
- }
-
- return False;
-}
-
-VexGuestLayout tilegxGuest_layout = {
- /* Total size of the guest state, in bytes. */
- .total_sizeB = sizeof(VexGuestTILEGXState),
- /* Describe the stack pointer. */
- .offset_SP = offsetof(VexGuestTILEGXState, guest_r54),
- .sizeof_SP = 8,
- /* Describe the frame pointer. */
- .offset_FP = offsetof(VexGuestTILEGXState, guest_r52),
- .sizeof_FP = 8,
- /* Describe the instruction pointer. */
- .offset_IP = offsetof(VexGuestTILEGXState, guest_pc),
- .sizeof_IP = 8,
- /* Describe any sections to be regarded by Memcheck as
- 'always-defined'. */
- .n_alwaysDefd = 8,
- /* ? :( */
- .alwaysDefd = {
- /* 0 */ ALWAYSDEFD(guest_r0),
- /* 1 */ ALWAYSDEFD(guest_r1),
- /* 2 */ ALWAYSDEFD(guest_EMNOTE),
- /* 3 */ ALWAYSDEFD(guest_CMSTART),
- /* 4 */ ALWAYSDEFD(guest_CMLEN),
- /* 5 */ ALWAYSDEFD(guest_r52),
- /* 6 */ ALWAYSDEFD(guest_r55),
- /* 7 */ ALWAYSDEFD(guest_pc),
- }
-};
-
-#ifdef __tilegx__
-ULong tilegx_dirtyhelper_gen ( ULong opc,
- ULong rd0, ULong rd1,
- ULong rd2, ULong rd3)
-{
- switch (opc)
- {
- case 0:
- {
- /* break point */
- switch (rd0) {
- case 0x286a44ae90048fffULL:
- asm (" bpt ");
- break;
- default:
- vex_printf("unhandled \"bpt\": cins=%016llx\n", rd0);
-
- vassert(0);
- return 0;
- }
- }
- break;
- case 28:
- {
- return __insn_addxsc(rd1, rd2);
- }
- break;
-
- case 150:
- {
- __insn_mf();
- return 0;
- }
- break;
-
- case 152: /* mm rd, ra, imm0, imm1 */
- {
- ULong mask;
-
- if( rd2 <= rd3)
- mask = (-1ULL << rd2) ^ ((-1ULL << rd3) << 1);
- else
- mask = (-1ULL << rd2) | (-1ULL >> (63 - rd3));
-
- return (rd0 & mask) | (rd1 & (-1ULL ^ mask));
- }
- break;
- case 154: /* mtspr imm, ra */
- {
- switch(rd0)
- {
- case 0x2785:
- __insn_mtspr(0x2785, rd1);
- break;
- case 0x2780:
- __insn_mtspr(0x2780, rd1);
- break;
- case 0x2708:
- __insn_mtspr(0x2708, rd1);
- break;
- case 0x2580:
- __insn_mtspr(0x2580, rd1);
- break;
- case 0x2581:
- __insn_mtspr(0x2581, rd1);
- break;
- case 0x2709: // PASS
- __insn_mtspr(0x2709, rd1);
- break;
- case 0x2707: // FAIL
- __insn_mtspr(0x2707, rd1);
- break;
- case 0x2705: // DONE
- __insn_mtspr(0x2705, rd1);
- break;
-
- case 0x2870: //
-
- default:
- vex_printf("opc=%d rd0=%llx rd1=%llx\n",
- (int)opc, rd0, rd1);
- vassert(0);
- }
- }
- break;
-
- case 151: /* mfspr rd, imm */
- {
- switch(rd1)
- {
- case 0x2785: // SIM_CTRL
- return __insn_mfspr(0x2785);
- break;
-
- case 0x2708: // ICS
- return __insn_mfspr(0x2708);
- break;
-
- case 0x2780: // CMPEXCH_VALUE
- return __insn_mfspr(0x2780);
- break;
-
- case 0x2781: // CYCLE
- return __insn_mfspr(0x2781);
- break;
-
- case 0x2709: // PASS
- return __insn_mfspr(0x2709);
- break;
-
- case 0x2707: // FAIL
- return __insn_mfspr(0x2707);
- break;
-
- case 0x2705: // DONE
- return __insn_mfspr(0x2705);
- break;
-
- case 0x2580: // EX_CONTEXT_0
- return __insn_mfspr(0x2580);
- break;
-
- case 0x2581: // EX_CONTEXT_1
- return __insn_mfspr(0x2581);
- break;
-
- default:
- vex_printf("opc=%d rd0=%llx rd1=%llx\n",
- (int)opc, rd0, rd1);
- vassert(0);
- }
- }
- break;
- case 183:
- {
- return __insn_pcnt(rd1);
- }
- break;
- case 184:
- {
- return __insn_revbits(rd1);
- }
- break;
- case 185: /* revbytes rd, ra */
- {
- return __insn_revbytes(rd1);
- }
- break;
-
- case 102:
- return __insn_fsingle_add1(rd1, rd2);
- break;
-
- case 103:
- return __insn_fsingle_addsub2(rd0, rd1, rd2);
- break;
-
- case 104:
- return __insn_fsingle_mul1(rd1, rd2);
- break;
-
- case 105:
- return __insn_fsingle_mul2(rd1, rd2);
- break;
-
- case 106:
- return __insn_fsingle_pack1(rd1);
- break;
-
- case 107:
- return __insn_fsingle_pack2(rd1, rd2);
- break;
-
- case 108:
- return __insn_fsingle_sub1(rd1, rd2);
- break;
-
- case 21:
- switch (rd0) {
- case 0x286a44ae90048fffULL:
- asm ("{ moveli zero, 72 ; raise }");
- break;
- default:
- vex_printf("unhandled \"raise\": cins=%016llx\n", rd0);
- __insn_ill();
- return 0;
- }
- break;
-
- case 64:
- {
- return __insn_cmul(rd1, rd2);
- }
- break;
- case 65:
- {
- return __insn_cmula(rd0, rd1, rd2);
- }
- break;
- case 66:
- {
- return __insn_cmulaf(rd0, rd1, rd2);
- }
- break;
- case 67:
- {
- return __insn_cmulf(rd1, rd2);
- }
- break;
- case 68:
- {
- return __insn_cmulfr(rd1, rd2);
- }
- break;
- case 69:
- {
- return __insn_cmulh(rd1, rd2);
- }
- break;
- case 70:
- {
- return __insn_cmulhr(rd1, rd2);
- }
- break;
- case 71:
- {
- return __insn_crc32_32(rd1, rd2);
- }
- break;
- case 72:
- {
- return __insn_crc32_8(rd1, rd2);
- }
- break;
- case 75:
- {
- return __insn_dblalign2(rd1, rd2);
- }
- break;
- case 76:
- {
- return __insn_dblalign4(rd1, rd2);
- }
- break;
- case 77:
- {
- return __insn_dblalign6(rd1, rd2);
- }
- break;
- case 78:
- {
- __insn_drain();
- return 0;
- }
- break;
- case 79:
- {
- __insn_dtlbpr(rd0);
- return 0;
- }
- break;
- case 82:
- {
- return __insn_fdouble_add_flags(rd1, rd2);
- }
- break;
- case 83:
- {
- return __insn_fdouble_addsub(rd0, rd1, rd2);
- }
- break;
- case 84:
- {
- return __insn_fdouble_mul_flags(rd1, rd2);
- }
- break;
- case 85:
- {
- return __insn_fdouble_pack1(rd1, rd2);
- }
- break;
- case 86:
- {
- return __insn_fdouble_pack2(rd0, rd1, rd2);
- }
- break;
- case 87:
- {
- return __insn_fdouble_sub_flags(rd1, rd2);
- }
- break;
- case 88:
- {
- return __insn_fdouble_unpack_max(rd1, rd2);
- }
- break;
- case 89:
- {
- return __insn_fdouble_unpack_min(rd1, rd2);
- }
- break;
-
- case 98:
- {
- __insn_finv(rd0);
- return 0;
- }
- break;
- case 99:
- {
- __insn_flush(rd0);
- return 0;
- }
- break;
- case 100:
- {
- __insn_flushwb();
- return 0;
- }
- break;
-
- case 109:
- {
- __insn_icoh((ULong *)rd0);
- return 0;
- }
- break;
- case 110:
- {
- __insn_ill();
- }
- break;
- case 111:
- {
- __insn_inv((ULong *)rd0);
- return 0;
- }
- break;
-
- case 169:
- {
- return __insn_mula_hu_hu(rd0, rd1, rd2);
- }
- break;
- case 170:
- {
- return __insn_mula_hu_ls(rd0, rd1, rd2);
- }
- break;
- case 205:
- {
- return __insn_shufflebytes(rd0, rd1, rd2);
- }
- break;
- case 224:
- {
- return __insn_subxsc(rd1, rd2);
- }
- break;
- case 229:
- {
- return __insn_tblidxb0(rd0, rd1);
- }
- break;
- case 230:
- {
- return __insn_tblidxb1(rd0, rd1);
- }
- break;
- case 231:
- {
- return __insn_tblidxb2(rd0, rd1);
- }
- break;
- case 232:
- {
- return __insn_tblidxb3(rd0, rd1);
- }
- break;
- case 233:
- {
- return __insn_v1add(rd1, rd2);
- }
- break;
- case 234:
- {
- return __insn_v1add(rd1, rd2);
- }
- break;
- case 235:
- {
- return __insn_v1adduc(rd1, rd2);
- }
- break;
- case 236:
- {
- return __insn_v1adiffu(rd1, rd2);
- }
- break;
- case 237:
- {
- return __insn_v1avgu(rd1, rd2);
- }
- break;
-
- case 238:
- {
- return __insn_v1cmpeq(rd1, rd2);
- }
- break;
- case 239:
- {
- return __insn_v1cmpeq(rd1, rd2);
- }
- break;
- case 240:
- {
- return __insn_v1cmples(rd1, rd2);
- }
- break;
- case 241:
- {
- return __insn_v1cmpleu(rd1, rd2);
- }
- break;
- case 242:
- {
- return __insn_v1cmplts(rd1, rd2);
- }
- break;
- case 243:
- {
- return __insn_v1cmplts(rd1, rd2);
- }
- break;
- case 244:
- {
- return __insn_v1cmpltu(rd1, rd2);
- }
- break;
- case 245:
- {
- return __insn_v1cmpltu(rd1, rd2);
- }
- break;
- case 246:
- {
- return __insn_v1cmpne(rd1, rd2);
- }
- break;
- case 247:
- {
- return __insn_v1ddotpu(rd1, rd2);
- }
- break;
- case 248:
- {
- return __insn_v1ddotpua(rd0, rd1, rd2);
- }
- break;
- case 249:
- {
- return __insn_v1ddotpus(rd1, rd2);
- }
- break;
- case 250:
- {
- return __insn_v1ddotpusa(rd0, rd1, rd2);
- }
- break;
- case 251:
- {
- return __insn_v1dotp(rd1, rd2);
- }
- break;
- case 252:
- {
- return __insn_v1dotpa(rd0, rd1, rd2);
- }
- break;
- case 253:
- {
- return __insn_v1dotpu(rd1, rd2);
- }
- break;
- case 254:
- {
- return __insn_v1dotpua(rd0, rd1, rd2);
- }
- break;
- case 255:
- {
- return __insn_v1dotpus(rd1, rd2);
- }
- break;
- case 256:
- {
- return __insn_v1dotpusa(rd0, rd1, rd2);
- }
- break;
- case 257:
- {
- return __insn_v1int_h(rd1, rd2);
- }
- break;
- case 258:
- {
- return __insn_v1int_l(rd1, rd2);
- }
- break;
- case 259:
- {
- return __insn_v1maxu(rd1, rd2);
- }
- break;
- case 260:
- {
- return __insn_v1maxu(rd1, rd2);
- }
- break;
- case 261:
- {
- return __insn_v1minu(rd1, rd2);
- }
- break;
- case 262:
- {
- return __insn_v1minu(rd1, rd2);
- }
- break;
- case 263:
- {
- return __insn_v1mnz(rd1, rd2);
- }
- break;
- case 264:
- {
- return __insn_v1multu(rd1, rd2);
- }
- break;
- case 265:
- {
- return __insn_v1mulu(rd1, rd2);
- }
- break;
- case 266:
- {
- return __insn_v1mulus(rd1, rd2);
- }
- break;
- case 267:
- {
- return __insn_v1mz(rd1, rd2);
- }
- break;
- case 268:
- {
- return __insn_v1sadau(rd0, rd1, rd2);
- }
- break;
- case 269:
- {
- return __insn_v1sadu(rd1, rd2);
- }
- break;
- case 270:
- {
- return __insn_v1shl(rd1, rd2);
- }
- break;
- case 271:
- {
- return __insn_v1shl(rd1, rd2);
- }
- break;
- case 272:
- {
- return __insn_v1shrs(rd1, rd2);
- }
- break;
- case 273:
- {
- return __insn_v1shrs(rd1, rd2);
- }
- break;
- case 274:
- {
- return __insn_v1shru(rd1, rd2);
- }
- break;
- case 275:
- {
- return __insn_v1shrui(rd1, rd2);
- }
- break;
- case 276:
- {
- return __insn_v1sub(rd1, rd2);
- }
- break;
- case 277:
- {
- return __insn_v1subuc(rd1, rd2);
- }
- break;
- case 278:
- {
- return __insn_v2add(rd1, rd2);
- }
- break;
- case 279:
- {
- return __insn_v2add(rd1, rd2);
- }
- break;
- case 280:
- {
- return __insn_v2addsc(rd1, rd2);
- }
- break;
- case 281:
- {
- return __insn_v2adiffs(rd1, rd2);
- }
- break;
- case 282:
- {
- return __insn_v2avgs(rd1, rd2);
- }
- break;
- case 283:
- {
- return __insn_v2cmpeq(rd1, rd2);
- }
- break;
- case 284:
- {
- return __insn_v2cmpeq(rd1, rd2);
- }
- break;
- case 285:
- {
- return __insn_v2cmples(rd1, rd2);
- }
- break;
- case 286:
- {
- return __insn_v2cmpleu(rd1, rd2);
- }
- break;
- case 287:
- {
- return __insn_v2cmplts(rd1, rd2);
- }
- break;
- case 288:
- {
- return __insn_v2cmplts(rd1, rd2);
- }
- break;
- case 289:
- {
- return __insn_v2cmpltu(rd1, rd2);
- }
- break;
- case 290:
- {
- return __insn_v2cmpltu(rd1, rd2);
- }
- break;
- case 291:
- {
- return __insn_v2cmpne(rd1, rd2);
- }
- break;
- case 292:
- {
- return __insn_v2dotp(rd1, rd2);
- }
- break;
- case 293:
- {
- return __insn_v2dotpa(rd0, rd1, rd2);
- }
- break;
- case 294:
- {
- return __insn_v2int_h(rd1, rd2);
- }
- break;
- case 295:
- {
- return __insn_v2int_l(rd1, rd2);
- }
- break;
- case 296:
- {
- return __insn_v2maxs(rd1, rd2);
- }
- break;
- case 297:
- {
- return __insn_v2maxs(rd1, rd2);
- }
- break;
- case 298:
- {
- return __insn_v2mins(rd1, rd2);
- }
- break;
- case 299:
- {
- return __insn_v2mins(rd1, rd2);
- }
- break;
- case 300:
- {
- return __insn_v2mnz(rd1, rd2);
- }
- break;
- case 301:
- {
- return __insn_v2mulfsc(rd1, rd2);
- }
- break;
- case 302:
- {
- return __insn_v2muls(rd1, rd2);
- }
- break;
- case 303:
- {
- return __insn_v2mults(rd1, rd2);
- }
- break;
- case 304:
- {
- return __insn_v2mz(rd1, rd2);
- }
- break;
- case 305:
- {
- return __insn_v2packh(rd1, rd2);
- }
- break;
- case 306:
- {
- return __insn_v2packl(rd1, rd2);
- }
- break;
- case 307:
- {
- return __insn_v2packuc(rd1, rd2);
- }
- break;
- case 308:
- {
- return __insn_v2sadas(rd0, rd1, rd2);
- }
- break;
- case 309:
- {
- return __insn_v2sadau(rd0, rd1, rd2);
- }
- break;
- case 310:
- {
- return __insn_v2sads(rd1, rd2);
- }
- break;
- case 311:
- {
- return __insn_v2sadu(rd1, rd2);
- }
- break;
- case 312:
- {
- return __insn_v2shl(rd1, rd2);
- }
- break;
- case 313:
- {
- return __insn_v2shl(rd1, rd2);
- }
- break;
- case 314:
- {
- return __insn_v2shlsc(rd1, rd2);
- }
- break;
- case 315:
- {
- return __insn_v2shrs(rd1, rd2);
- }
- break;
- case 316:
- {
- return __insn_v2shrs(rd1, rd2);
- }
- break;
- case 317:
- {
- return __insn_v2shru(rd1, rd2);
- }
- break;
- case 318:
- {
- return __insn_v2shru(rd1, rd2);
- }
- break;
- case 319:
- {
- return __insn_v2sub(rd1, rd2);
- }
- break;
- case 320:
- {
- return __insn_v2subsc(rd1, rd2);
- }
- break;
- case 321:
- {
- return __insn_v4add(rd1, rd2);
- }
- break;
- case 322:
- {
- return __insn_v4addsc(rd1, rd2);
- }
- break;
- case 323:
- {
- return __insn_v4int_h(rd1, rd2);
- }
- break;
- case 324:
- {
- return __insn_v4int_l(rd1, rd2);
- }
- break;
- case 325:
- {
- return __insn_v4packsc(rd1, rd2);
- }
- break;
- case 326:
- {
- return __insn_v4shl(rd1, rd2);
- }
- break;
- case 327:
- {
- return __insn_v4shlsc(rd1, rd2);
- }
- break;
- case 328:
- {
- return __insn_v4shrs(rd1, rd2);
- }
- break;
- case 329:
- {
- return __insn_v4shru(rd1, rd2);
- }
- break;
- case 330:
- {
- return __insn_v4sub(rd1, rd2);
- }
- break;
- case 331:
- {
- return __insn_v4subsc(rd1, rd2);
- }
- break;
-
- default:
- vex_printf("opc=%d rd0=%llx rd1=%llx\n",
- (int)opc, rd0, rd1);
- vassert(0);
- }
-}
-#else
-ULong tilegx_dirtyhelper_gen ( ULong opc,
- ULong rd0, ULong rd1,
- ULong rd2, ULong rd3 )
-{
- vex_printf("NOT a TILEGX platform");
- return 0;
-}
-#endif /* __tilegx__ */
-
-/*---------------------------------------------------------------*/
-/*--- end guest_tilegx_helpers.c ---*/
-/*---------------------------------------------------------------*/
diff --git a/VEX/priv/guest_tilegx_toIR.c b/VEX/priv/guest_tilegx_toIR.c
deleted file mode 100644
index f13c7ad..0000000
--- a/VEX/priv/guest_tilegx_toIR.c
+++ /dev/null
@@ -1,2577 +0,0 @@
-
-/*--------------------------------------------------------------------*/
-/*--- begin guest_tilegx_toIR.c ---*/
-/*--------------------------------------------------------------------*/
-
-/*
- This file is part of Valgrind, a dynamic binary instrumentation
- framework.
-
- Copyright (C) 2010-2015 Tilera Corp.
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of the
- License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful, but
- WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
- 02111-1307, USA.
-
- The GNU General Public License is contained in the file COPYING.
-*/
-
-/* Contributed by Zhi-Gang Liu <zliu at tilera dot com> */
-
-/* Translates TILEGX code to IR. */
-
-#include "libvex_basictypes.h"
-#include "libvex_ir.h"
-#include "libvex.h"
-#include "libvex_guest_tilegx.h"
-
-#include "main_util.h"
-#include "main_globals.h"
-#include "guest_generic_bb_to_IR.h"
-#include "guest_tilegx_defs.h"
-#include "tilegx_disasm.h"
-
-/*------------------------------------------------------------*/
-/*--- Globals ---*/
-/*------------------------------------------------------------*/
-
-/* These are set at the start of the translation of a instruction, so
- that we don't have to pass them around endlessly. CONST means does
- not change during translation of the instruction.
-*/
-
-/* CONST: is the host bigendian? This has to do with float vs double
- register accesses on VFP, but it's complex and not properly thought
- out. */
-static VexEndness host_endness;
-
-/* Pointer to the guest code area. */
-static UChar *guest_code;
-
-/* The guest address corresponding to guest_code[0]. */
-static Addr64 guest_PC_bbstart;
-
-/* CONST: The guest address for the instruction currently being
- translated. */
-static Addr64 guest_PC_curr_instr;
-
-/* MOD: The IRSB* into which we're generating code. */
-static IRSB *irsb;
-
-/*------------------------------------------------------------*/
-/*--- Debugging output ---*/
-/*------------------------------------------------------------*/
-
-#define DIP(format, args...) \
- if (vex_traceflags & VEX_TRACE_FE) \
- vex_printf(format, ## args)
-
-/*------------------------------------------------------------*/
-/*--- Helper bits and pieces for deconstructing the ---*/
-/*--- tilegx insn stream. ---*/
-/*------------------------------------------------------------*/
-
-static Int integerGuestRegOffset ( UInt iregNo )
-{
- return 8 * (iregNo);
-}
-
-/*------------------------------------------------------------*/
-/*--- Field helpers ---*/
-/*------------------------------------------------------------*/
-
-/*------------------------------------------------------------*/
-/*--- Helper bits and pieces for creating IR fragments. ---*/
-/*------------------------------------------------------------*/
-
-static IRExpr *mkU8 ( UInt i )
-{
- return IRExpr_Const(IRConst_U8((UChar) i));
-}
-
-/* Create an expression node for a 32-bit integer constant */
-static IRExpr *mkU32 ( UInt i )
-{
- return IRExpr_Const(IRConst_U32(i));
-}
-
-/* Create an expression node for a 64-bit integer constant */
-static IRExpr *mkU64 ( ULong i )
-{
- return IRExpr_Const(IRConst_U64(i));
-}
-
-static IRExpr *mkexpr ( IRTemp tmp )
-{
- return IRExpr_RdTmp(tmp);
-}
-
-static IRExpr *unop ( IROp op, IRExpr * a )
-{
- return IRExpr_Unop(op, a);
-}
-
-static IRExpr *binop ( IROp op, IRExpr * a1, IRExpr * a2 )
-{
- return IRExpr_Binop(op, a1, a2);
-}
-
-static IRExpr *load ( IRType ty, IRExpr * addr )
-{
- IRExpr *load1 = NULL;
-
- load1 = IRExpr_Load(Iend_LE, ty, addr);
- return load1;
-}
-
-/* Add a statement to the list held by "irsb". */
-static void stmt ( IRStmt * st )
-{
- addStmtToIRSB(irsb, st);
-}
-
-#define OFFB_PC offsetof(VexGuestTILEGXState, guest_pc)
-
-static void putPC ( IRExpr * e )
-{
- stmt(IRStmt_Put(OFFB_PC, e));
-}
-
-static void assign ( IRTemp dst, IRExpr * e )
-{
- stmt(IRStmt_WrTmp(dst, e));
-}
-
-static void store ( IRExpr * addr, IRExpr * data )
-{
- stmt(IRStmt_Store(Iend_LE, addr, data));
-}
-
-/* Generate a new temporary of the given type. */
-static IRTemp newTemp ( IRType ty )
-{
- vassert(isPlausibleIRType(ty));
- return newIRTemp(irsb->tyenv, ty);
-}
-
-static ULong extend_s_16to64 ( UInt x )
-{
- return (ULong) ((((Long) x) << 48) >> 48);
-}
-
-static ULong extend_s_8to64 ( UInt x )
-{
- return (ULong) ((((Long) x) << 56) >> 56);
-}
-
-static IRExpr *getIReg ( UInt iregNo )
-{
- IRType ty = Ity_I64;
- if(!(iregNo < 56 || iregNo == 63 ||
- (iregNo >= 70 && iregNo <= 73))) {
- vex_printf("iregNo=%u\n", iregNo);
- vassert(0);
- }
- return IRExpr_Get(integerGuestRegOffset(iregNo), ty);
-}
-
-static void putIReg ( UInt archreg, IRExpr * e )
-{
- IRType ty = Ity_I64;
- if(!(archreg < 56 || archreg == 63 || archreg == 70 ||
- archreg == 72 || archreg == 73)) {
- vex_printf("archreg=%u\n", archreg);
- vassert(0);
- }
- vassert(typeOfIRExpr(irsb->tyenv, e) == ty);
- if (archreg != 63)
- stmt(IRStmt_Put(integerGuestRegOffset(archreg), e));
-}
-
-/* Narrow 8/16/32 bit int expr to 8/16/32. Clearly only some
- of these combinations make sense. */
-static IRExpr *narrowTo ( IRType dst_ty, IRExpr * e )
-{
- IRType src_ty = typeOfIRExpr(irsb->tyenv, e);
- if (src_ty == dst_ty)
- return e;
- if (src_ty == Ity_I32 && dst_ty == Ity_I16)
- return unop(Iop_32to16, e);
- if (src_ty == Ity_I32 && dst_ty == Ity_I8)
- return unop(Iop_32to8, e);
-
- if (src_ty == Ity_I64 && dst_ty == Ity_I8) {
- return unop(Iop_64to8, e);
- }
- if (src_ty == Ity_I64 && dst_ty == Ity_I16) {
- return unop(Iop_64to16, e);
- }
- if (src_ty == Ity_I64 && dst_ty == Ity_I32) {
- return unop(Iop_64to32, e);
- }
-
- if (vex_traceflags & VEX_TRACE_FE) {
- vex_printf("\nsrc, dst tys are: ");
- ppIRType(src_ty);
- vex_printf(", ");
- ppIRType(dst_ty);
- vex_printf("\n");
- }
- vpanic("narrowTo(tilegx)");
- return e;
-}
-
-#define signExtend(_e, _n) \
- ((_n == 32) ? \
- unop(Iop_32Sto64, _e) : \
- ((_n == 16) ? \
- unop(Iop_16Sto64, _e) : \
- (binop(Iop_Sar64, binop(Iop_Shl64, _e, mkU8(63 - (_n))), mkU8(63 - (_n))))))
-
-static IRStmt* dis_branch ( IRExpr* guard, ULong imm )
-{
- IRTemp t0;
-
- t0 = newTemp(Ity_I1);
- assign(t0, guard);
- return IRStmt_Exit(mkexpr(t0), Ijk_Boring,
- IRConst_U64(imm), OFFB_PC);
-}
-
-#define MARK_REG_WB(_rd, _td) \
- do { \
- vassert(rd_wb_index < 6); \
- rd_wb_temp[rd_wb_index] = _td; \
- rd_wb_reg[rd_wb_index] = _rd; \
- rd_wb_index++; \
- } while(0)
-
-
-/* Expand/repeat byte _X 8 times to a 64-bit value */
-#define V1EXP(_X) \
- ({ \
- _X = ((((UChar)(_X)) << 8) | ((UChar)(_X))); \
- _X = (((_X) << 16) | (_X)); \
- (((_X) << 32) | (_X)); \
- })
-
-/* Expand/repeat byte _X 4 times to a 64-bit value */
-#define V2EXP(_X) \
- ({ \
- _X = ((((UChar)(_X)) << 16) | ((UChar)(_X))); \
- (((_X) << 32) | (_X)); \
- })
-
-/*------------------------------------------------------------*/
-/*--- Disassemble a single instruction ---*/
-/*------------------------------------------------------------*/
-
-/* Disassemble a single instruction bundle into IR. The bundle is
- located in host memory at guest_instr, and has guest IP of
- guest_PC_curr_instr, which will have been set before the call
- here. */
-static DisResult disInstr_TILEGX_WRK ( Bool(*resteerOkFn) (void *, Addr),
- Bool resteerCisOk,
- void *callback_opaque,
- Long delta64,
- const VexArchInfo * archinfo,
- const VexAbiInfo * abiinfo,
- Bool sigill_diag )
-{
- struct tilegx_decoded_instruction
- decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE];
- ULong cins, opcode = -1, rd, ra, rb, imm = 0;
- ULong opd[4];
- ULong opd_src_map, opd_dst_map, opd_imm_map;
- Int use_dirty_helper;
- IRTemp t0, t1, t2, t3, t4;
- IRTemp tb[4];
- IRTemp rd_wb_temp[6];
- ULong rd_wb_reg[6];
- /* Tilegx is a VLIW processor, we have to commit register write after read.*/
- Int rd_wb_index;
- Int n = 0, nr_insn;
- DisResult dres;
-
- /* The running delta */
- Long delta = delta64;
-
- /* Holds pc at the start of the insn, so that we can print
- consistent error messages for unimplemented insns. */
- //Long delta_start = delta;
-
- UChar *code = (UChar *) (guest_code + delta);
-
- IRStmt *bstmt = NULL; /* Branch statement. */
- IRExpr *next = NULL; /* Next bundle expr. */
- ULong jumpkind = Ijk_Boring;
- ULong steering_pc;
-
- /* Set result defaults. */
- dres.whatNext = Dis_Continue;
- dres.len = 0;
- dres.continueAt = 0;
- dres.jk_StopHere = Ijk_INVALID;
-
- /* Verify the code addr is 8-byte aligned. */
- vassert((((Addr)code) & 7) == 0);
-
- /* Get the instruction bundle. */
- cins = *((ULong *)(Addr) code);
-
- /* "Special" instructions. */
- /* Spot the 16-byte preamble: ****tilegx****
- 0:02b3c7ff91234fff { moveli zero, 4660 ; moveli zero, 22136 }
- 8:0091a7ff95678fff { moveli zero, 22136 ; moveli zero, 4660 }
- */
-#define CL_W0 0x02b3c7ff91234fffULL
-#define CL_W1 0x0091a7ff95678fffULL
-
- if (*((ULong*)(Addr)(code)) == CL_W0 &&
- *((ULong*)(Addr)(code + 8)) == CL_W1) {
- /* Got a "Special" instruction preamble. Which one is it? */
- if (*((ULong*)(Addr)(code + 16)) ==
- 0x283a69a6d1483000ULL /* or r13, r13, r13 */ ) {
- /* r0 = client_request ( r12 ) */
- DIP("r0 = client_request ( r12 )\n");
-
- putPC(mkU64(guest_PC_curr_instr + 24));
-
- dres.jk_StopHere = Ijk_ClientReq;
- dres.whatNext = Dis_StopHere;
- dres.len = 24;
- goto decode_success;
-
- } else if (*((ULong*)(Addr)(code + 16)) ==
- 0x283a71c751483000ULL /* or r14, r14, r14 */ ) {
- /* r11 = guest_NRADDR */
- DIP("r11 = guest_NRADDR\n");
- dres.len = 24;
- putIReg(11, IRExpr_Get(offsetof(VexGuestTILEGXState, guest_NRADDR),
- Ity_I64));
- putPC(mkU64(guest_PC_curr_instr + 8));
- goto decode_success;
-
- } else if (*((ULong*)(Addr)(code + 16)) ==
- 0x283a79e7d1483000ULL /* or r15, r15, r15 */ ) {
- /* branch-and-link-to-noredir r12 */
- DIP("branch-and-link-to-noredir r12\n");
- dres.len = 24;
- putIReg(55, mkU64(guest_PC_curr_instr + 24));
-
- putPC(getIReg(12));
-
- dres.jk_StopHere = Ijk_NoRedir;
- dres.whatNext = Dis_StopHere;
- goto decode_success;
-
- } else if (*((ULong*)(Addr)(code + 16)) ==
- 0x283a5965d1483000ULL /* or r11, r11, r11 */ ) {
- /* vex-inject-ir */
- DIP("vex-inject-ir\n");
- dres.len = 24;
-
- vex_inject_ir(irsb, Iend_LE);
-
- stmt(IRStmt_Put(offsetof(VexGuestTILEGXState, guest_CMSTART),
- mkU64(guest_PC_curr_instr)));
- stmt(IRStmt_Put(offsetof(VexGuestTILEGXState, guest_CMLEN),
- mkU64(24)));
-
- /* 2 + 1 = 3 bundles. 24 bytes. */
- putPC(mkU64(guest_PC_curr_instr + 24));
-
- dres.jk_StopHere = Ijk_InvalICache;
- dres.whatNext = Dis_StopHere;
- goto decode_success;
- }
-
- /* We don't expect this. */
- vex_printf("%s: unexpect special bundles at %lx\n",
- __func__, (Addr)guest_PC_curr_instr);
- delta += 16;
- goto decode_failure;
- /*NOTREACHED*/
- }
-
- /* To decode the given instruction bundle. */
- nr_insn = parse_insn_tilegx((tilegx_bundle_bits)cins,
- (ULong)(Addr)code,
- decoded);
-
- if (vex_traceflags & VEX_TRACE_FE)
- decode_and_display(&cins, 1, (ULong)(Addr)code);
-
- /* Init. rb_wb_index */
- rd_wb_index = 0;
-
- steering_pc = -1ULL;
-
- for (n = 0; n < nr_insn; n++) {
- opcode = decoded[n].opcode->mnemonic;
- Int opi;
-
- rd = ra = rb = -1;
- opd[0] = opd[1] = opd[2] = opd[3] = -1;
- opd_dst_map = 0;
- opd_src_map = 0;
- opd_imm_map = 0;
-
- for (opi = 0; opi < decoded[n].opcode->num_operands; opi++) {
- const struct tilegx_operand *op = decoded[n].operands[opi];
- opd[opi] = decoded[n].operand_values[opi];
-
- /* Set the operands. rd, ra, rb and imm. */
- if (opi < 3) {
- if (op->is_dest_reg) {
- if (rd == -1)
- rd = decoded[n].operand_values[opi];
- else if (ra == -1)
- ra = decoded[n].operand_values[opi];
- } else if (op->is_src_reg) {
- if (ra == -1) {
- ra = decoded[n].operand_values[opi];
- } else if(rb == -1) {
- rb = decoded[n].operand_values[opi];
- } else {
- vassert(0);
- }
- } else {
- imm = decoded[n].operand_values[opi];
- }
- }
-
- /* Build bit maps of used dest, source registers
- and immediate. */
- if (op->is_dest_reg) {
- opd_dst_map |= 1ULL << opi;
- if(op->is_src_reg)
- opd_src_map |= 1ULL << opi;
- } else if(op->is_src_reg) {
- opd_src_map |= 1ULL << opi;
- } else {
- opd_imm_map |= 1ULL << opi;
- }
- }
-
- use_dirty_helper = 0;
-
- switch (opcode) {
- case 0: /* "bpt" */ /* "raise" */
- /* "bpt" pseudo instruction is an illegal instruction */
- opd_imm_map |= (1 << 0);
- opd[0] = cins;
- use_dirty_helper = 1;
- break;
- case 1: /* "info" */ /* Ignore this instruction. */
- break;
- case 2: /* "infol" */ /* Ignore this instruction. */
- break;
- case 3: /* "ld4s_tls" */ /* Ignore this instruction. */
- break;
- case 4: /* "ld_tls" */ /* Ignore this instruction. */
- break;
- case 5: /* "move" */
- t2 = newTemp(Ity_I64);
- assign(t2, getIReg(ra));
- MARK_REG_WB(rd, t2);
- break;
- case 6: /* "movei" */
- t2 = newTemp(Ity_I64);
- assign(t2, mkU64(extend_s_8to64(imm)));
- MARK_REG_WB(rd, t2);
- break;
- case 7: /* "moveli" */
- t2 = newTemp(Ity_I64);
- assign(t2, mkU64(extend_s_16to64(imm)));
- MARK_REG_WB(rd, t2);
- break;
- case 8: /* "prefetch" */ /* Ignore. */
- break;
- case 9: /* "prefetch_add_l1" */ /* Ignore. */
- break;
- case 10: /* "prefetch_add_l1_fault" */ /* Ignore. */
- break;
- case 11: /* "prefetch_add_l2" */ /* Ignore. */
- break;
- case 12: /* "prefetch_add_l2_fault" */ /* Ignore. */
- break;
- case 13: /* "prefetch_add_l3" */ /* Ignore. */
- break;
- case 14: /* "prefetch_add_l3_fault" */ /* Ignore. */
- break;
- case 15: /* "prefetch_l1" */ /* Ignore. */
- break;
- case 16: /* "prefetch_l1_fault" */ /* Ignore. */
- break;
- case 17: /* "prefetch_l2" */ /* Ignore. */
- break;
- case 18: /* "prefetch_l2_fault" */ /* Ignore. */
- break;
- case 19: /* "prefetch_l3" */ /* Ignore. */
- break;
- case 20: /* "prefetch_l3_fault" */ /* Ignore. */
- break;
- case 21: /* "raise" */
- /* "raise" pseudo instruction is an illegal instruction plusing
- a "moveli zero, <sig>", so we need save whole bundle in the
- opd[0], which will be used in the dirty helper. */
- opd_imm_map |= (1 << 0);
- opd[0] = cins;
- use_dirty_helper = 1;
- break;
- case 22: /* "add" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_Add64, getIReg(ra), getIReg(rb)));
- MARK_REG_WB(rd, t2);
- break;
- case 23: /* "addi" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_Add64, getIReg(ra),
- mkU64(extend_s_8to64(imm))));
- MARK_REG_WB(rd, t2);
- break;
- case 24: /* "addli" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_Add64, getIReg(ra),
- mkU64(extend_s_16to64(imm))));
- MARK_REG_WB(rd, t2);
- break;
- case 25: /* "addx" */
- t2 = newTemp(Ity_I64);
- assign(t2, signExtend(binop(Iop_Add32,
- narrowTo(Ity_I32, getIReg(ra)),
- narrowTo(Ity_I32, getIReg(rb))),
- 32));
- MARK_REG_WB(rd, t2);
- break;
- case 26: /* "addxi" */
- t2 = newTemp(Ity_I64);
- assign(t2, signExtend(binop(Iop_Add32,
- narrowTo(Ity_I32, getIReg(ra)),
- mkU32(imm)), 32));
- MARK_REG_WB(rd, t2);
- break;
- case 27: /* "addxli" */
- t2 = newTemp(Ity_I64);
- assign(t2, signExtend(binop(Iop_Add32,
- narrowTo(Ity_I32, getIReg(ra)),
- mkU32(imm)), 32));
-
- MARK_REG_WB(rd, t2);
- break;
- case 28: /* "addxsc" */
- use_dirty_helper = 1;
- break;
- case 29: /* "and" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_And64, getIReg(ra), getIReg(rb)));
- MARK_REG_WB(rd, t2);
- break;
- case 30: /* "andi" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_And64, getIReg(ra),
- mkU64(extend_s_8to64(imm))));
- MARK_REG_WB(rd, t2);
- break;
- case 31: /* "beqz" */
- /* Fall-through */
- case 32:
- /* "beqzt" */
- bstmt = dis_branch(binop(Iop_CmpEQ64, getIReg(ra), mkU64(0)),
- imm);
- break;
- case 33: /* "bfexts" */
- {
- ULong imm0 = decoded[n].operand_values[3];
- ULong mask = ((-1ULL) ^ ((-1ULL << ((imm0 - imm) & 63)) << 1));
- t0 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- assign(t0, binop(Iop_Xor64,
- binop(Iop_Sub64,
- binop(Iop_And64,
- binop(Iop_Shr64,
- getIReg(ra),
- mkU8(imm0)),
- mkU64(1)),
- mkU64(1)),
- mkU64(-1ULL)));
- assign(t2,
- binop(Iop_Or64,
- binop(Iop_And64,
- binop(Iop_Or64,
- binop(Iop_Shr64,
- getIReg(ra),
- mkU8(imm)),
- binop(Iop_Shl64,
- getIReg(ra),
- mkU8(64 - imm))),
- mkU64(mask)),
- binop(Iop_And64,
- mkexpr(t0),
- mkU64(~mask))));
-
- MARK_REG_WB(rd, t2);
- }
- break;
- case 34: /* "bfextu" */
- {
- ULong imm0 = decoded[n].operand_values[3];
- ULong mask = 0;
- t2 = newTemp(Ity_I64);
- mask = ((-1ULL) ^ ((-1ULL << ((imm0 - imm) & 63)) << 1));
-
- assign(t2,
- binop(Iop_And64,
- binop(Iop_Or64,
- binop(Iop_Shr64,
- getIReg(ra),
- mkU8(imm)),
- binop(Iop_Shl64,
- getIReg(ra),
- mkU8(64 - imm))),
- mkU64(mask)));
- MARK_REG_WB(rd, t2);
- }
- break;
- case 35: /* "bfins" */
- {
- ULong mask;
- ULong imm0 = decoded[n].operand_values[3];
- t0 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- if (imm <= imm0)
- {
- mask = ((-1ULL << imm) ^ ((-1ULL << imm0) << 1));
- }
- else
- {
- mask = ((-1ULL << imm) | (-1ULL >> (63 - imm0)));
- }
-
- assign(t0, binop(Iop_Or64,
- binop(Iop_Shl64,
- getIReg(ra),
- mkU8(imm)),
- binop(Iop_Shr64,
- getIReg(ra),
- mkU8(64 - imm))));
-
- assign(t2, binop(Iop_Or64,
- binop(Iop_And64,
- mkexpr(t0),
- mkU64(mask)),
- binop(Iop_And64,
- getIReg(rd),
- mkU64(~mask))));
-
- MARK_REG_WB(rd, t2);
- }
- break;
- case 36: /* "bgez" */
- /* Fall-through */
- case 37: /* "bgezt" */
- bstmt = dis_branch(binop(Iop_CmpEQ64,
- binop(Iop_And64,
- getIReg(ra),
- mkU64(0x8000000000000000ULL)),
- mkU64(0x0)),
- imm);
- break;
- case 38: /* "bgtz" */
- /* Fall-through */
- case 39:
- /* "bgtzt" */
- bstmt = dis_branch(unop(Iop_Not1,
- binop(Iop_CmpLE64S,
- getIReg(ra),
- mkU64(0))),
- imm);
- break;
- case 40: /* "blbc" */
- /* Fall-through */
- case 41: /* "blbct" */
- bstmt = dis_branch(unop(Iop_64to1,
- unop(Iop_Not64, getIReg(ra))),
- imm);
-
- break;
- case 42: /* "blbs" */
- /* Fall-through */
- case 43:
- /* "blbst" */
- bstmt = dis_branch(unop(Iop_64to1,
- getIReg(ra)),
- imm);
- break;
- case 44: /* "blez" */
- bstmt = dis_branch(binop(Iop_CmpLE64S, getIReg(ra),
- mkU64(0)),
- imm);
- break;
- case 45: /* "blezt" */
- bstmt = dis_branch(binop(Iop_CmpLE64S, getIReg(ra),
- mkU64(0)),
- imm);
- break;
- case 46: /* "bltz" */
- bstmt = dis_branch(binop(Iop_CmpLT64S, getIReg(ra),
- mkU64(0)),
- imm);
- break;
- case 47: /* "bltzt" */
- bstmt = dis_branch(binop(Iop_CmpLT64S, getIReg(ra),
- mkU64(0)),
- imm);
- break;
- case 48: /* "bnez" */
- /* Fall-through */
- case 49:
- /* "bnezt" */
- bstmt = dis_branch(binop(Iop_CmpNE64, getIReg(ra),
- mkU64(0)),
- imm);
- break;
- case 50: /* "clz" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_Clz64, getIReg(ra)));
-
- MARK_REG_WB(rd, t2);
- break;
- case 51: /* "cmoveqz rd, ra, rb" */
- t2 = newTemp(Ity_I64);
- assign(t2, IRExpr_ITE(binop(Iop_CmpEQ64, getIReg(ra), mkU64(0)),
- getIReg(rb), getIReg(rd)));
- MARK_REG_WB(rd, t2);
- break;
- case 52: /* "cmovnez" */
- t2 = newTemp(Ity_I64);
- assign(t2, IRExpr_ITE(binop(Iop_CmpEQ64, getIReg(ra), mkU64(0)),
- getIReg(rd), getIReg(rb)));
- MARK_REG_WB(rd, t2);
- break;
- case 53: /* "cmpeq" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_1Uto64, binop(Iop_CmpEQ64,
- getIReg(ra), getIReg(rb))));
- MARK_REG_WB(rd, t2);
- break;
-
- case 54: /* "cmpeqi" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_1Uto64, binop(Iop_CmpEQ64,
- getIReg(ra),
- mkU64(extend_s_8to64(imm)))));
- MARK_REG_WB(rd, t2);
- break;
- case 55: /* "cmpexch" */
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
-
- assign(t1, getIReg(rb));
- stmt( IRStmt_CAS(mkIRCAS(IRTemp_INVALID, t2, Iend_LE,
- getIReg(ra),
- NULL, binop(Iop_Add64,
- getIReg(70),
- getIReg(71)),
- NULL, mkexpr(t1))));
- MARK_REG_WB(rd, t2);
- break;
- case 56: /* "cmpexch4" */
- t1 = newTemp(Ity_I32);
- t2 = newTemp(Ity_I64);
- t3 = newTemp(Ity_I32);
-
- assign(t1, narrowTo(Ity_I32, getIReg(rb)));
- stmt( IRStmt_CAS(mkIRCAS(IRTemp_INVALID, t3, Iend_LE,
- getIReg(ra),
- NULL,
- narrowTo(Ity_I32, binop(Iop_Add64,
- getIReg(70),
- getIReg(71))),
- NULL,
- mkexpr(t1))));
- assign(t2, unop(Iop_32Uto64, mkexpr(t3)));
- MARK_REG_WB(rd, t2);
- break;
- case 57: /* "cmples" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_1Uto64,
- binop(Iop_CmpLE64S, getIReg(ra), getIReg(rb))));
- MARK_REG_WB(rd, t2);
- break;
- case 58: /* "cmpleu" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_1Uto64,
- binop(Iop_CmpLE64U, getIReg(ra), getIReg(rb))));
- MARK_REG_WB(rd, t2);
- break;
- case 59: /* "cmplts" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_1Uto64,
- binop(Iop_CmpLT64S, getIReg(ra), getIReg(rb))));
- MARK_REG_WB(rd, t2);
- break;
- case 60: /* "cmpltsi" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_1Uto64,
- binop(Iop_CmpLT64S,
- getIReg(ra),
- mkU64(extend_s_8to64(imm)))));
- MARK_REG_WB(rd, t2);
- break;
- case 61:
-
- /* "cmpltu" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_1Uto64,
- binop(Iop_CmpLT64U, getIReg(ra), getIReg(rb))));
- MARK_REG_WB(rd, t2);
-
-
- break;
- case 62: /* "cmpltui" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_1Uto64,
- binop(Iop_CmpLT64U,
- getIReg(ra),
- mkU64(imm))));
- MARK_REG_WB(rd, t2);
-
-
- break;
- case 63: /* "cmpne" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_1Uto64,
- binop(Iop_CmpNE64, getIReg(ra), getIReg(rb))));
- MARK_REG_WB(rd, t2);
-
-
- break;
- case 64:
- /* Fall-through */
- case 65:
- /* Fall-through */
- case 66:
- /* Fall-through */
- case 67:
- /* Fall-through */
- case 68:
- /* Fall-through */
- case 69:
- /* Fall-through */
- case 70:
- /* Fall-through */
- case 71:
- /* Fall-through */
- case 72:
- use_dirty_helper = 1;
- break;
- case 73: /* "ctz" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_Ctz64, getIReg(ra)));
-
- MARK_REG_WB(rd, t2);
-
-
- break;
- case 74: /* "dblalign" */
- t0 = newTemp(Ity_I64);
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
-
- /* t0 is the bit shift amount */
- assign(t0, binop(Iop_Shl64,
- binop(Iop_And64,
- getIReg(rb),
- mkU64(7)),
- mkU8(3)));
- assign(t1, binop(Iop_Sub64,
- mkU64(64),
- mkexpr(t0)));
-
- assign(t2, binop(Iop_Or64,
- binop(Iop_Shl64,
- getIReg(ra),
- unop(Iop_64to8, mkexpr(t1))),
- binop(Iop_Shr64,
- getIReg(rd),
- unop(Iop_64to8, mkexpr(t0)))));
-
- MARK_REG_WB(rd, t2);
- break;
- case 75:
- /* Fall-through */
- case 76:
- /* Fall-through */
- case 77:
- /* Fall-through */
- case 78:
- /* Fall-through */
- case 79:
- use_dirty_helper = 1;
- break;
- case 80: /* "exch" */
- t2 = newTemp(Ity_I64);
- stmt( IRStmt_CAS(
- mkIRCAS(IRTemp_INVALID,
- t2,
- Iend_LE,
- getIReg(ra),
- NULL,
- mkU64(0x0),
- NULL,
- getIReg(rb))));
- MARK_REG_WB(rd, t2);
- break;
- case 81: /* "exch4 rd, ra, rb" */
- t0 = newTemp(Ity_I32);
- t2 = newTemp(Ity_I64);
- stmt( IRStmt_CAS(
- mkIRCAS(IRTemp_INVALID,
- t0,
- Iend_LE,
- getIReg(ra),
- NULL,
- mkU32(0x0),
- NULL,
- narrowTo(Ity_I32,
- getIReg(rb)))));
- assign(t2, unop(Iop_32Sto64, mkexpr(t0)));
- MARK_REG_WB(rd, t2);
- break;
- case 82:
- /* Fall-through */
- case 83:
- /* Fall-through */
- case 84:
- /* Fall-through */
- case 85:
- /* Fall-through */
- case 86:
- /* Fall-through */
- case 87:
- /* Fall-through */
- case 88:
- /* Fall-through */
- case 89:
- use_dirty_helper = 1;
- break;
- case 90: /* "fetchadd" */
- t2 = newTemp(Ity_I64);
- stmt( IRStmt_CAS(
- mkIRCAS(IRTemp_INVALID,
- t2,
- Iend_LE,
- getIReg(ra),
- NULL,
- // fetchadd=3
- mkU64(0x3),
- NULL,
- getIReg(rb))));
- MARK_REG_WB(rd, t2);
- break;
- case 91: /* "fetchadd4" */
- t0 = newTemp(Ity_I32);
- t2 = newTemp(Ity_I64);
- stmt( IRStmt_CAS(
- mkIRCAS(IRTemp_INVALID,
- t0,
- Iend_LE,
- getIReg(ra),
- NULL,
- // fetchadd=3
- mkU32(0x3),
- NULL,
- narrowTo(Ity_I32,
- getIReg(rb)))));
- assign(t2, unop(Iop_32Sto64, mkexpr(t0)));
- MARK_REG_WB(rd, t2);
-
- break;
- case 92: /* "fetchaddgez" */
- t2 = newTemp(Ity_I64);
- stmt( IRStmt_CAS(
- mkIRCAS(IRTemp_INVALID,
- t2,
- Iend_LE,
- getIReg(ra),
- NULL,
- // fetchaddgez=5
- mkU64(0x5),
- NULL,
- getIReg(rb))));
- MARK_REG_WB(rd, t2);
- break;
- case 93: /* "fetchaddgez4" */
- t0 = newTemp(Ity_I32);
- t2 = newTemp(Ity_I64);
- stmt( IRStmt_CAS(
- mkIRCAS(IRTemp_INVALID,
- t0,
- Iend_LE,
- getIReg(ra),
- NULL,
- // fetchaddgez=5
- mkU32(0x5),
- NULL,
- narrowTo(Ity_I32,
- getIReg(rb)))));
- assign(t2, unop(Iop_32Sto64, mkexpr(t0)));
- MARK_REG_WB(rd, t2);
- break;
- case 94: /* "fetchand\n") */
- t2 = newTemp(Ity_I64);
- stmt( IRStmt_CAS(
- mkIRCAS(IRTemp_INVALID,
- t2,
- Iend_LE,
- getIReg(ra),
- NULL,
- mkU64(0x2),
- NULL,
- getIReg(rb))));
- MARK_REG_WB(rd, t2);
- break;
- case 95:
- /* mkIRCAS.
- 0: xch### 1: cmpexch###,
- 2: fetchand## 3: fetchadd##
- 4: fetchor## 5: fetchaddgez
- */
- /* "fetchand4" */
- t0 = newTemp(Ity_I32);
- t2 = newTemp(Ity_I64);
- stmt( IRStmt_CAS(
- mkIRCAS(IRTemp_INVALID,
- t0,
- Iend_LE,
- getIReg(ra),
- NULL,
- mkU32(0x2),
- NULL,
- narrowTo(Ity_I32,
- getIReg(rb)))));
- assign(t2, unop(Iop_32Sto64, mkexpr(t0)));
- MARK_REG_WB(rd, t2);
- break;
- case 96: /* "fetchor" */
- t2 = newTemp(Ity_I64);
- stmt( IRStmt_CAS(
- mkIRCAS(IRTemp_INVALID,
- t2,
- Iend_LE,
- getIReg(ra),
- NULL,
- mkU64(0x4),
- NULL,
- getIReg(rb))));
- MARK_REG_WB(rd, t2);
- break;
- case 97: /* "fetchor4" */
- t0 = newTemp(Ity_I32);
- t2 = newTemp(Ity_I64);
- stmt( IRStmt_CAS(
- mkIRCAS(IRTemp_INVALID,
- t0,
- Iend_LE,
- getIReg(ra),
- NULL,
- mkU32(0x4),
- NULL,
- narrowTo(Ity_I32,
- getIReg(rb)))));
- assign(t2, unop(Iop_32Sto64, mkexpr(t0)));
- MARK_REG_WB(rd, t2);
- break;
- case 98:
- /* Fall-through */
- case 99:
- /* Fall-through */
- case 100:
- use_dirty_helper = 1;
- break;
- case 101: /* "fnop" Ignore */
- break;
- case 102:
- /* Fall-through */
- case 103:
- /* Fall-through */
- case 104:
- /* Fall-through */
- case 105:
- /* Fall-through */
- case 106:
- /* Fall-through */
- case 107:
- /* Fall-through */
- case 108:
- use_dirty_helper = 1;
- break;
- case 109:
- /* Fall-through */
- case 110:
- /* Fall-through */
- case 111:
- use_dirty_helper = 1;
- break;
- case 112: /* "iret" */
- next = mkU64(guest_PC_curr_instr + 8);
- jumpkind = Ijk_Ret;
- break;
- case 113: /* "j" */
- next = mkU64(imm);
- /* set steering address. */
- steering_pc = imm;
- jumpkind = Ijk_Boring;
- break;
- case 114:
- t2 = newTemp(Ity_I64);
- assign(t2, mkU64(guest_PC_curr_instr + 8));
- /* set steering address. */
- steering_pc = imm;
- next = mkU64(imm);
- jumpkind = Ijk_Call;
- MARK_REG_WB(55, t2);
- break;
- case 115: /* "jalr" */
- /* Fall-through */
- case 116: /* "jalrp" */
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- assign(t1, getIReg(ra));
- assign(t2, mkU64(guest_PC_curr_instr + 8));
- next = mkexpr(t1);
- jumpkind = Ijk_Call;
- MARK_REG_WB(55, t2);
- break;
- case 117: /* "jr" */
- /* Fall-through */
- case 118: /* "jrp" */
- next = getIReg(ra);
- jumpkind = Ijk_Boring;
- break;
- case 119: /* "ld" */
- t2 = newTemp(Ity_I64);
- assign(t2, load(Ity_I64, (getIReg(ra))));
- MARK_REG_WB(rd, t2);
- break;
- case 120: /* "ld1s" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_8Sto64,
- load(Ity_I8, (getIReg(ra)))));
- MARK_REG_WB(rd, t2);
- break;
- case 121: /* "ld1s_add" */
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm)));
- assign(t2, unop(Iop_8Sto64,
- load(Ity_I8, (getIReg(ra)))));
- MARK_REG_WB(ra, t1);
- MARK_REG_WB(rd, t2);
- break;
- case 122: /* "ld1u" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_8Uto64,
- load(Ity_I8, (getIReg(ra)))));
- MARK_REG_WB(rd, t2);
-
- break;
- case 123: /* "ld1u_add" */
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm)));
- assign(t2, unop(Iop_8Uto64,
- load(Ity_I8, (getIReg(ra)))));
- MARK_REG_WB(ra, t1);
- MARK_REG_WB(rd, t2);
- break;
- case 124: /* "ld2s" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_16Sto64,
- load(Ity_I16, getIReg(ra))));
- MARK_REG_WB(rd, t2);
- break;
- case 125: /* "ld2s_add" */
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm)));
- assign(t2, unop(Iop_16Sto64,
- load(Ity_I16, getIReg(ra))));
- MARK_REG_WB(rd, t2);
- MARK_REG_WB(ra, t1);
- break;
- case 126: /* "ld2u" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_16Uto64,
- load(Ity_I16, getIReg(ra))));
- MARK_REG_WB(rd, t2);
- break;
- case 127: /* "ld2u_add" */
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm)));
- assign(t2, unop(Iop_16Uto64,
- load(Ity_I16, getIReg(ra))));
- MARK_REG_WB(rd, t2);
- MARK_REG_WB(ra, t1);
- break;
- case 128: /* "ld4s" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_32Sto64,
- load(Ity_I32, (getIReg(ra)))));
- MARK_REG_WB(rd, t2);
- break;
- case 129: /* "ld4s_add" */
- t2 = newTemp(Ity_I64);
- t1 = newTemp(Ity_I64);
- assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm)));
- assign(t2, unop(Iop_32Sto64,
- load(Ity_I32, (getIReg(ra)))));
- MARK_REG_WB(rd, t2);
- MARK_REG_WB(ra, t1);
- break;
- case 130: /* "ld4u" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_32Uto64,
- load(Ity_I32, getIReg(ra))));
- MARK_REG_WB(rd, t2);
- break;
- case 131: /* "ld4u_add" */
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm)));
- assign(t2, unop(Iop_32Uto64,
- load(Ity_I32, getIReg(ra))));
- MARK_REG_WB(ra, t1);
- MARK_REG_WB(rd, t2);
- break;
- case 132: /* "ld_add" */
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- assign(t1, load(Ity_I64, getIReg(ra)));
- assign(t2, binop(Iop_Add64, getIReg(ra), mkU64(imm)));
- MARK_REG_WB(ra, t2);
- MARK_REG_WB(rd, t1);
- break;
- case 133: /* "ldna" */
- t2 = newTemp(Ity_I64);
- assign(t2, load(Ity_I64,
- binop(Iop_And64,
- getIReg(ra),
- unop(Iop_Not64,
- mkU64(7)))));
- MARK_REG_WB(rd, t2);
- break;
- case 134: /* "ldna_add" */
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
-
- assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm)));
- assign(t2, load(Ity_I64,
- binop(Iop_And64,
- getIReg(ra),
- unop(Iop_Not64,
- mkU64(7)))));
- MARK_REG_WB(ra, t1);
- MARK_REG_WB(rd, t2);
- break;
- case 135: /* "ldnt" */
- /* Valgrind IR has no Non-Temp load. Use normal load. */
- t2 = newTemp(Ity_I64);
- assign(t2, load(Ity_I64, (getIReg(ra))));
- MARK_REG_WB(rd, t2);
- break;
- case 136: /* "ldnt1s" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_8Sto64,
- load(Ity_I8, (getIReg(ra)))));
- MARK_REG_WB(rd, t2);
- break;
- case 137: /* "ldnt1s_add" */
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_8Sto64,
- load(Ity_I8, (getIReg(ra)))));
- assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm)));
- MARK_REG_WB(ra, t1);
- MARK_REG_WB(rd, t2);
- break;
- case 138: /* "ldnt1u" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_8Uto64,
- load(Ity_I8, (getIReg(ra)))));
- MARK_REG_WB(rd, t2);
- break;
- case 139: /* "ldnt1u_add" */
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
-
- assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm)));
- assign(t2, unop(Iop_8Uto64,
- load(Ity_I8, (getIReg(ra)))));
-
- MARK_REG_WB(ra, t1);
- MARK_REG_WB(rd, t2);
- break;
- case 140: /* "ldnt2s" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_16Sto64,
- load(Ity_I16, getIReg(ra))));
- MARK_REG_WB(rd, t2);
- break;
- case 141: /* "ldnt2s_add" */
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_16Sto64,
- load(Ity_I16, getIReg(ra))));
- assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm)));
- MARK_REG_WB(ra, t1);
- MARK_REG_WB(rd, t2);
- break;
- case 142: /* "ldnt2u" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_16Uto64,
- load(Ity_I16, getIReg(ra))));
- MARK_REG_WB(rd, t2);
- break;
- case 143: /* "ldnt2u_add" */
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_16Uto64,
- load(Ity_I16, getIReg(ra))));
- assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm)));
- MARK_REG_WB(ra, t1);
- MARK_REG_WB(rd, t2);
- break;
- case 144: /* "ldnt4s" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_32Sto64,
- load(Ity_I32, (getIReg(ra)))));
- MARK_REG_WB(rd, t2);
- break;
- case 145: /* "ldnt4s_add" */
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_32Sto64,
- load(Ity_I32, (getIReg(ra)))));
- assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm)));
- MARK_REG_WB(rd, t2);
- MARK_REG_WB(ra, t1);
- break;
- case 146: /* "ldnt4u" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_32Uto64,
- load(Ity_I32, getIReg(ra))));
- MARK_REG_WB(rd, t2);
- break;
- case 147: /* "ldnt4u_add" */
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_32Uto64,
- load(Ity_I32, getIReg(ra))));
- assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm)));
- MARK_REG_WB(rd, t2);
- MARK_REG_WB(ra, t1);
- break;
- case 148: /* "ldnt_add" */
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- assign(t1, load(Ity_I64, getIReg(ra)));
- assign(t2, binop(Iop_Add64, getIReg(ra), mkU64(imm)));
- MARK_REG_WB(rd, t1);
- MARK_REG_WB(ra, t2);
- break;
- case 149: /* "lnk" */
- t2 = newTemp(Ity_I64);
- assign(t2, mkU64(guest_PC_curr_instr + 8));
- MARK_REG_WB(rd, t2);
- break;
- case 150: /* "mf" */
- use_dirty_helper = 1;
- break;
- case 151: /* "mfspr" */
- t2 = newTemp(Ity_I64);
- if (imm == 0x2780) { // Get Cmpexch value
- assign(t2, getIReg(70));
- MARK_REG_WB(rd, t2);
- } else if (imm == 0x2580) { // Get EX_CONTEXT_0_0
- assign(t2, getIReg(576 / 8));
- MARK_REG_WB(rd, t2);
- } else if (imm == 0x2581) { // Get EX_CONTEXT_0_1
- assign(t2, getIReg(584 / 8));
- MARK_REG_WB(rd, t2);
- } else
- use_dirty_helper = 1;
- break;
- case 152: /* "mm" */
- use_dirty_helper = 1;
- break;
- case 153: /* "mnz" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_And64,
- unop(Iop_1Sto64, binop(Iop_CmpNE64,
- getIReg(ra),
- mkU64(0))),
- getIReg(rb)));
- MARK_REG_WB(rd, t2);
- break;
- case 154: /* "mtspr imm, ra" */
- if (imm == 0x2780) // Set Cmpexch value
- putIReg(70, getIReg(ra));
- else if (imm == 0x2580) // set EX_CONTEXT_0_0
- putIReg(576/8, getIReg(ra));
- else if (imm == 0x2581) // set EX_CONTEXT_0_1
- putIReg(584/8, getIReg(ra));
- else
- use_dirty_helper = 1;
- break;
- case 155: /* "mul_hs_hs" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_MullS32,
- unop(Iop_64to32,
- binop(Iop_Shr64,
- getIReg(ra),
- mkU8(32))),
- unop(Iop_64to32,
- binop(Iop_Shr64,
- getIReg(rb),
- mkU8(32)))));
- MARK_REG_WB(rd, t2);
- break;
- case 156: /* "mul_hs_hu" */
- t0 = newTemp(Ity_I64);
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- t3 = newTemp(Ity_I64);
-
- assign(t0, unop(Iop_32Sto64,
- unop(Iop_64to32,
- binop(Iop_Shr64, getIReg(ra), mkU8(32)))));
- assign(t1, binop(Iop_MullU32,
- unop(Iop_64to32, mkexpr(t0)),
- unop(Iop_64to32, binop(Iop_Shr64, getIReg(rb), mkU8(32)))));
- assign(t3, binop(Iop_MullU32,
- unop(Iop_64to32, binop(Iop_Shr64,
- mkexpr(t0),
- mkU8(32))),
- unop(Iop_64to32, binop(Iop_Shr64, getIReg(rb), mkU8(32)))));
- assign(t2, binop(Iop_Add64,
- mkexpr(t1),
- binop(Iop_Shl64,
- mkexpr(t3),
- mkU8(32))));
- MARK_REG_WB(rd, t2);
- break;
- case 157: /* "mul_hs_ls" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_MullS32,
- unop(Iop_64to32,
- binop(Iop_Shr64,
- getIReg(ra),
- mkU8(32))),
- unop(Iop_64to32,
- getIReg(rb))));
- MARK_REG_WB(rd, t2);
- break;
- case 158: /* "mul_hs_lu" */
- t0 = newTemp(Ity_I64);
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- t3 = newTemp(Ity_I64);
-
- assign(t0, unop(Iop_32Sto64,
- unop(Iop_64to32,
- binop(Iop_Shr64, getIReg(ra), mkU8(32)))));
- assign(t1, binop(Iop_MullU32,
- unop(Iop_64to32, mkexpr(t0)),
- unop(Iop_64to32, getIReg(rb))));
- assign(t3, binop(Iop_MullU32,
- unop(Iop_64to32, binop(Iop_Shr64,
- mkexpr(t0),
- mkU8(32))),
- unop(Iop_64to32, getIReg(rb))));
- assign(t2, binop(Iop_Add64,
- mkexpr(t1),
- binop(Iop_Shl64,
- mkexpr(t3),
- mkU8(32))));
- MARK_REG_WB(rd, t2);
- break;
- case 159: /* "mul_hu_hu" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_MullU32,
- unop(Iop_64to32,
- binop(Iop_Shr64,
- getIReg(ra),
- mkU8(32))),
- unop(Iop_64to32,
- binop(Iop_Shr64,
- getIReg(rb),
- mkU8(32)))));
- MARK_REG_WB(rd, t2);
- break;
- case 160: /* "mul_hu_ls" */
- t0 = newTemp(Ity_I64);
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- t3 = newTemp(Ity_I64);
-
- assign(t0, unop(Iop_32Sto64,
- unop(Iop_64to32,
- getIReg(ra))));
-
- assign(t1, binop(Iop_MullU32,
- unop(Iop_64to32, mkexpr(t0)),
- unop(Iop_64to32, binop(Iop_Shr64, getIReg(rb), mkU8(32)))));
- assign(t3, binop(Iop_MullU32,
- unop(Iop_64to32, binop(Iop_Shr64,
- mkexpr(t0),
- mkU8(32))),
- unop(Iop_64to32, binop(Iop_Shr64, getIReg(rb), mkU8(32)))));
- assign(t2, binop(Iop_Add64,
- mkexpr(t1),
- binop(Iop_Shl64,
- mkexpr(t3),
- mkU8(32))));
- MARK_REG_WB(rd, t2);
- break;
- case 161: /* "mul_hu_lu" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_MullU32,
- unop(Iop_64to32,
- binop(Iop_Shr64,
- getIReg(ra),
- mkU8(32))),
- unop(Iop_64to32,
- getIReg(rb))));
- MARK_REG_WB(rd, t2);
- break;
- case 162: /* "mul_ls_ls" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_MullS32,
- unop(Iop_64to32, getIReg(ra)),
- unop(Iop_64to32, getIReg(rb))));
- MARK_REG_WB(rd, t2);
- break;
- case 163: /* "mul_ls_lu" */
- t0 = newTemp(Ity_I64);
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- t3 = newTemp(Ity_I64);
-
- assign(t0, unop(Iop_32Sto64,
- unop(Iop_64to32, getIReg(ra))));
- assign(t1, binop(Iop_MullU32,
- unop(Iop_64to32, mkexpr(t0)),
- unop(Iop_64to32, getIReg(rb))));
- assign(t3, binop(Iop_MullU32,
- unop(Iop_64to32, binop(Iop_Shr64,
- mkexpr(t0),
- mkU8(32))),
- unop(Iop_64to32, getIReg(rb))));
- assign(t2, binop(Iop_Add64,
- mkexpr(t1),
- binop(Iop_Shl64,
- mkexpr(t3),
- mkU8(32))));
- MARK_REG_WB(rd, t2);
- break;
- case 164: /* "mul_lu_lu" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_MullU32,
- unop(Iop_64to32, getIReg(ra)),
- unop(Iop_64to32, getIReg(rb))));
- MARK_REG_WB(rd, t2);
- break;
- case 165: /* "mula_hs_hs" */
- t0 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
-
- assign(t0, binop(Iop_MullS32,
- unop(Iop_64to32, binop(Iop_Shr64,
- getIReg(ra), mkU8(32))),
- unop(Iop_64to32, binop(Iop_Shr64,
- getIReg(rb), mkU8(32)))));
- assign(t2, binop(Iop_Add64, getIReg(rd), mkexpr(t0)));
- MARK_REG_WB(rd, t2);
- break;
- case 166: /* "mula_hs_hu" */
- t0 = newTemp(Ity_I64);
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- t3 = newTemp(Ity_I64);
- t4 = newTemp(Ity_I64);
- assign(t0, unop(Iop_32Sto64,
- unop(Iop_64to32,
- binop(Iop_Shr64, getIReg(ra), mkU8(32)))));
- assign(t1, binop(Iop_MullU32,
- unop(Iop_64to32, mkexpr(t0)),
- unop(Iop_64to32, binop(Iop_Shr64,
- getIReg(rb), mkU8(32)))));
- assign(t3, binop(Iop_MullU32,
- unop(Iop_64to32, binop(Iop_Shr64,
- mkexpr(t0),
- mkU8(32))),
- unop(Iop_64to32, binop(Iop_Shr64,
- getIReg(rb), mkU8(32)))));
- assign(t2, binop(Iop_Add64,
- mkexpr(t1),
- binop(Iop_Shl64,
- mkexpr(t3),
- mkU8(32))));
- assign(t4, binop(Iop_Add64, getIReg(rd), mkexpr(t2)));
- MARK_REG_WB(rd, t4);
- break;
- case 167: /* "mula_hs_ls" */
- t2 = newTemp(Ity_I64);
- t4 = newTemp(Ity_I64);
- assign(t2, binop(Iop_MullS32,
- unop(Iop_64to32,
- binop(Iop_Shr64,
- getIReg(ra),
- mkU8(32))),
- unop(Iop_64to32,
- getIReg(rb))));
- assign(t4, binop(Iop_Add64, getIReg(rd), mkexpr(t2)));
- MARK_REG_WB(rd, t4);
- break;
- case 168: /* "mula_hs_lu" */
- t0 = newTemp(Ity_I64);
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- t3 = newTemp(Ity_I64);
- t4 = newTemp(Ity_I64);
- assign(t0, unop(Iop_32Sto64,
- unop(Iop_64to32,
- binop(Iop_Shr64, getIReg(ra), mkU8(32)))));
- assign(t1, binop(Iop_MullU32,
- unop(Iop_64to32, mkexpr(t0)),
- unop(Iop_64to32, getIReg(rb))));
- assign(t3, binop(Iop_MullU32,
- unop(Iop_64to32, binop(Iop_Shr64,
- mkexpr(t0),
- mkU8(32))),
- unop(Iop_64to32, getIReg(rb))));
- assign(t2, binop(Iop_Add64,
- mkexpr(t1),
- binop(Iop_Shl64,
- mkexpr(t3),
- mkU8(32))));
- assign(t4, binop(Iop_Add64, getIReg(rd), mkexpr(t2)));
- MARK_REG_WB(rd, t4);
- break;
- case 169: /* "mula_hu_hu" */
- use_dirty_helper = 1;
- break;
- case 170: /* "mula_hu_ls" */
- use_dirty_helper = 1;
- break;
- case 171: /* "mula_hu_lu" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_Add64,
- binop(Iop_MullU32,
- unop(Iop_64to32,
- binop(Iop_Shr64,
- getIReg(ra),
- mkU8(32))),
- unop(Iop_64to32,
- getIReg(rb))),
- getIReg(rd)));
- MARK_REG_WB(rd, t2);
- break;
- case 172: /* "mula_ls_ls" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_Add64,
- getIReg(rd),
- binop(Iop_MullS32,
- unop(Iop_64to32, getIReg(ra)),
- unop(Iop_64to32, getIReg(rb)))));
- MARK_REG_WB(rd, t2);
- break;
- case 173: /* "mula_ls_lu" */
- t0 = newTemp(Ity_I64);
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- t3 = newTemp(Ity_I64);
-
- assign(t0, unop(Iop_32Sto64,
- unop(Iop_64to32, getIReg(ra))));
- assign(t1, binop(Iop_MullU32,
- unop(Iop_64to32, mkexpr(t0)),
- unop(Iop_64to32, getIReg(rb))));
- assign(t3, binop(Iop_MullU32,
- unop(Iop_64to32, binop(Iop_Shr64,
- mkexpr(t0),
- mkU8(32))),
- unop(Iop_64to32, getIReg(rb))));
- assign(t2, binop(Iop_Add64,
- getIReg(rd),
- binop(Iop_Add64,
- mkexpr(t1),
- binop(Iop_Shl64,
- mkexpr(t3),
- mkU8(32)))));
- MARK_REG_WB(rd, t2);
- break;
- case 174: /* "mula_lu_lu" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_Add64,
- binop(Iop_MullU32,
- unop(Iop_64to32,
- getIReg(ra)),
- unop(Iop_64to32,
- getIReg(rb))),
- getIReg(rd)));
- MARK_REG_WB(rd, t2);
- break;
- case 175: /* "mulax" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_32Sto64,
- unop(Iop_64to32,
- binop(Iop_Add64,
- getIReg(rd),
- binop(Iop_MullU32,
- narrowTo(Ity_I32, getIReg(ra)),
- narrowTo(Ity_I32, getIReg(rb)))))));
- MARK_REG_WB(rd, t2);
- break;
- case 176: /* "mulx" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_32Sto64,
- unop(Iop_64to32,
- binop(Iop_MullU32,
- narrowTo(Ity_I32, getIReg(ra)),
- narrowTo(Ity_I32, getIReg(rb))))));
- MARK_REG_WB(rd, t2);
- break;
- case 177: /* "mz" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_And64,
- unop(Iop_1Sto64, binop(Iop_CmpEQ64,
- getIReg(ra),
- mkU64(0))),
- getIReg(rb)));
- MARK_REG_WB(rd, t2);
- break;
- case 178: /* "nap" */
- break;
- case 179: /* "nop" */
- break;
- case 180: /* "nor" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_Not64,
- binop(Iop_Or64,
- getIReg(ra),
- getIReg(rb))));
- MARK_REG_WB(rd, t2);
- break;
- case 181: /* "or" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_Or64,
- getIReg(ra),
- getIReg(rb)));
- MARK_REG_WB(rd, t2);
- break;
- case 182: /* "ori" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_Or64,
- getIReg(ra),
- mkU64(imm)));
- MARK_REG_WB(rd, t2);
- break;
- case 183:
- /* Fall-through */
- case 184:
- /* Fall-through */
- case 185:
- use_dirty_helper = 1;
- break;
- case 186: /* "rotl" */
- t0 = newTemp(Ity_I64);
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- assign(t0, binop(Iop_Shl64,
- getIReg(ra),
- unop(Iop_64to8, getIReg(rb))));
- assign(t1, binop(Iop_Shr64,
- getIReg(ra),
- unop(Iop_64to8, binop(Iop_Sub64,
- mkU64(0),
- getIReg(rb)))));
- assign(t2, binop(Iop_Or64, mkexpr(t0), mkexpr(t1)));
- MARK_REG_WB(rd, t2);
- break;
- case 187: /* "rotli" */
- t0 = newTemp(Ity_I64);
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- assign(t0, binop(Iop_Shl64,
- getIReg(ra),
- mkU8(imm)));
- assign(t1, binop(Iop_Shr64,
- getIReg(ra),
- mkU8(0 - imm)));
- assign(t2, binop(Iop_Or64, mkexpr(t0), mkexpr(t1)));
- MARK_REG_WB(rd, t2);
- break;
- case 188: /* "shl" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_Shl64,
- getIReg(ra),
- unop(Iop_64to8, getIReg(rb))));
- MARK_REG_WB(rd, t2);
-
- break;
- case 189: /* "shl16insli" */
- t2 = newTemp(Ity_I64);
- t3 = newTemp(Ity_I64);
- assign(t3, binop(Iop_Shl64, getIReg(ra), mkU8(16)));
- imm &= 0xFFFFULL;
- if (imm & 0x8000)
- {
- t4 = newTemp(Ity_I64);
- assign(t4, mkU64(imm));
- assign(t2, binop(Iop_Add64, mkexpr(t3), mkexpr(t4)));
- }
- else
- {
- assign(t2, binop(Iop_Add64, mkexpr(t3), mkU64(imm)));
- }
- MARK_REG_WB(rd, t2);
-
- break;
- case 190: /* "shl1add" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_Add64,
- binop(Iop_Shl64,
- getIReg(ra), mkU8(1)),
- getIReg(rb)));
-
- MARK_REG_WB(rd, t2);
- break;
- case 191: /* "shl1addx" */
- t2 = newTemp(Ity_I64);
- assign(t2,
- unop(Iop_32Sto64,
- unop(Iop_64to32,
- binop(Iop_Add64,
- binop(Iop_Shl64,
- getIReg(ra), mkU8(1)),
- getIReg(rb)))));
- MARK_REG_WB(rd, t2);
- break;
- case 192: /* "shl2add" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_Add64,
- binop(Iop_Shl64,
- getIReg(ra), mkU8(2)),
- getIReg(rb)));
-
- MARK_REG_WB(rd, t2);
-
- break;
- case 193: /* "shl2addx" */
- t2 = newTemp(Ity_I64);
- assign(t2,
- unop(Iop_32Sto64,
- unop(Iop_64to32,
- binop(Iop_Add64,
- binop(Iop_Shl64,
- getIReg(ra), mkU8(2)),
- getIReg(rb)))));
- MARK_REG_WB(rd, t2);
-
- break;
- case 194: /* "shl3add" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_Add64,
- binop(Iop_Shl64,
- getIReg(ra), mkU8(3)),
- getIReg(rb)));
-
- MARK_REG_WB(rd, t2);
- break;
- case 195: /* "shl3addx" */
- t2 = newTemp(Ity_I64);
- assign(t2,
- unop(Iop_32Sto64,
- unop(Iop_64to32,
- binop(Iop_Add64,
- binop(Iop_Shl64,
- getIReg(ra), mkU8(3)),
- getIReg(rb)))));
- MARK_REG_WB(rd, t2);
- break;
- case 196: /* "shli" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_Shl64, getIReg(ra),
- mkU8(imm)));
- MARK_REG_WB(rd, t2);
- break;
- case 197: /* "shlx" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_32Sto64,
- binop(Iop_Shl32,
- narrowTo(Ity_I32, getIReg(ra)),
- narrowTo(Ity_I8, getIReg(rb)))));
- MARK_REG_WB(rd, t2);
- break;
- case 198: /* "shlxi" */
- t2 = newTemp(Ity_I64);
- assign(t2, signExtend(binop(Iop_Shl32,
- narrowTo(Ity_I32, getIReg(ra)),
- mkU8(imm)),
- 32));
- MARK_REG_WB(rd, t2);
- break;
- case 199: /* "shrs" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_Sar64, getIReg(ra),
- narrowTo(Ity_I8, getIReg(rb))));
-
- MARK_REG_WB(rd, t2);
- break;
- case 200: /* "shrsi" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_Sar64, getIReg(ra),
- mkU8(imm)));
-
- MARK_REG_WB(rd, t2);
- break;
- case 201: /* "shru" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_Shr64,
- getIReg(ra),
- narrowTo(Ity_I8, (getIReg(rb)))));
-
- MARK_REG_WB(rd, t2);
- break;
- case 202: /* "shrui" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_Shr64, getIReg(ra), mkU8(imm)));
-
- MARK_REG_WB(rd, t2);
- break;
- case 203: /* "shrux" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_32Sto64,
- (binop(Iop_Shr32,
- narrowTo(Ity_I32, getIReg(ra)),
- narrowTo(Ity_I8, getIReg(rb))))));
- MARK_REG_WB(rd, t2);
- break;
- case 204: /* "shruxi" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_32Sto64,
- (binop(Iop_Shr32,
- narrowTo(Ity_I32, getIReg(ra)),
- mkU8(imm)))));
- MARK_REG_WB(rd, t2);
- break;
- case 205: /* "shufflebytes" */
- use_dirty_helper = 1;
- break;
- case 206: /* "st" */
- store(getIReg(ra), getIReg(rb));
- break;
- case 207: /* "st1" */
- store(getIReg(ra), narrowTo(Ity_I8, getIReg(rb)));
- break;
- case 208: /* "st1_add" */
- t2 = newTemp(Ity_I64);
- store(getIReg(opd[0]), narrowTo(Ity_I8, getIReg(opd[1])));
- assign(t2, binop(Iop_Add64, getIReg(opd[0]), mkU64(opd[2])));
- MARK_REG_WB(opd[0], t2);
- break;
- case 209: /* "st2" */
- store(getIReg(ra), narrowTo(Ity_I16, getIReg(rb)));
- break;
- case 210: /* "st2_add" */
- t2 = newTemp(Ity_I64);
- store(getIReg(opd[0]), narrowTo(Ity_I16, getIReg(opd[1])));
- assign(t2, binop(Iop_Add64, getIReg(opd[0]), mkU64(opd[2])));
- MARK_REG_WB(opd[0], t2);
- break;
- case 211: /* "st4" */
- store(getIReg(ra), narrowTo(Ity_I32, getIReg(rb)));
- break;
- case 212: /* "st4_add" */
- t2 = newTemp(Ity_I64);
- store(getIReg(opd[0]), narrowTo(Ity_I32, getIReg(opd[1])));
- assign(t2, binop(Iop_Add64, getIReg(opd[0]), mkU64(opd[2])));
- MARK_REG_WB(opd[0], t2);
- break;
- case 213: /* "st_add" */
- t2 = newTemp(Ity_I64);
- store(getIReg(opd[0]), getIReg(opd[1]));
- assign(t2, binop(Iop_Add64, getIReg(opd[0]), mkU64(opd[2])));
- MARK_REG_WB(opd[0], t2);
- break;
- case 214: /* "stnt" */
- store(getIReg(ra), getIReg(rb));
- break;
- case 215: /* "stnt1" */
- store(getIReg(ra), narrowTo(Ity_I8, getIReg(rb)));
- break;
- case 216: /* "stnt1_add" */
- t2 = newTemp(Ity_I64);
- store(getIReg(opd[0]), narrowTo(Ity_I8, getIReg(opd[1])));
- assign(t2, binop(Iop_Add64, getIReg(opd[0]), mkU64(opd[2])));
- MARK_REG_WB(opd[0], t2);
- break;
- case 217: /* "stnt2" */
- store(getIReg(ra), narrowTo(Ity_I16, getIReg(rb)));
- break;
- case 218: /* "stnt2_add" */
- t2 = newTemp(Ity_I64);
- store(getIReg(opd[0]), narrowTo(Ity_I16, getIReg(opd[1])));
- assign(t2, binop(Iop_Add64, getIReg(opd[0]), mkU64(opd[2])));
- MARK_REG_WB(opd[0], t2);
- break;
- case 219: /* "stnt4" */
- store(getIReg(ra), narrowTo(Ity_I32, getIReg(rb)));
- break;
- case 220: /* "stnt4_add" */
- t2 = newTemp(Ity_I64);
- store(getIReg(opd[0]), narrowTo(Ity_I32, getIReg(opd[1])));
- assign(t2, binop(Iop_Add64, getIReg(opd[0]), mkU64(opd[2])));
- MARK_REG_WB(opd[0], t2);
- break;
- case 221: /* "stnt_add" */
- t2 = newTemp(Ity_I64);
- store(getIReg(opd[0]), getIReg(opd[1]));
- assign(t2, binop(Iop_Add64, getIReg(opd[0]), mkU64(opd[2])));
- MARK_REG_WB(opd[0], t2);
- break;
- case 222: /* "sub" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_Sub64, getIReg(ra),
- getIReg(rb)));
- MARK_REG_WB(rd, t2);
- break;
- case 223: /* "subx" */
- t2 = newTemp(Ity_I64);
- assign(t2, unop(Iop_32Sto64,
- binop(Iop_Sub32,
- narrowTo(Ity_I32, getIReg(ra)),
- narrowTo(Ity_I32, getIReg(rb)))));
- MARK_REG_WB(rd, t2);
- break;
- case 224: /* "subxsc" */
- use_dirty_helper = 1;
- break;
- case 225: /* "swint0" */
- vex_printf( "\n *** swint0 ***\n");
- vassert(0);
- break;
- case 226: /* "swint1" */
- next = mkU64(guest_PC_curr_instr + 8);
- jumpkind = Ijk_Sys_syscall;
- break;
- case 227: /* "swint2" */
- vex_printf( "\n *** swint2 ***\n");
- vassert(0);
- break;
- case 228: /* "swint3" */
- vex_printf( "\n *** swint3 ***\n");
- vassert(0);
- break;
- case 229:
- /* Fall-through */
- case 230:
- /* Fall-through */
- case 231:
- /* Fall-through */
- case 232:
- /* Fall-through */
- case 233:
- use_dirty_helper = 1;
- break;
- case 234:
- opd[3] = V1EXP(opd[3]);
- use_dirty_helper = 1;
- break;
- case 235:
- /* Fall-through */
- case 236:
- /* Fall-through */
- case 237:
- use_dirty_helper = 1;
- break;
- case 238: /* "v1cmpeq" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_CmpEQ8x8, getIReg(ra),
- getIReg(rb)));
- MARK_REG_WB(rd, t2);
- break;
- case 239: /* "v1cmpeqi" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_CmpEQ8x8, getIReg(ra),
- mkU64(imm)));
-
- MARK_REG_WB(rd, t2);
- break;
- case 240:
- /* Fall-through */
- case 241:
- /* Fall-through */
- case 242:
- use_dirty_helper = 1;
- break;
- case 243:
- opd[3] = V1EXP(opd[3]);
- use_dirty_helper = 1;
- break;
- /* Fall-through */
- case 244:
- use_dirty_helper = 1;
- break;
- case 245:
- opd[3] = V1EXP(opd[3]);
- use_dirty_helper = 1;
- break;
- case 246: /* "v1cmpne" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_CmpEQ8x8,
- binop(Iop_CmpEQ8x8, getIReg(ra),
- getIReg(rb)),
- getIReg(63)));
- MARK_REG_WB(rd, t2);
- break;
- case 247:
- /* Fall-through */
- case 248:
- /* Fall-through */
- case 249:
- /* Fall-through */
- case 250:
- /* Fall-through */
- case 251:
- /* Fall-through */
- case 252:
- /* Fall-through */
- case 253:
- /* Fall-through */
- case 254:
- /* Fall-through */
- case 255:
- /* Fall-through */
- case 256:
- /* Fall-through */
- case 257:
- /* Fall-through */
- case 258:
- /* Fall-through */
- case 259:
- use_dirty_helper = 1;
- break;
- case 260:
- opd[3] = V1EXP(opd[3]);
- use_dirty_helper = 1;
- break;
- case 261:
- use_dirty_helper = 1;
- break;
- case 262:
- opd[3] = V1EXP(opd[3]);
- use_dirty_helper = 1;
- break;
- case 263:
- /* Fall-through */
- case 264:
- /* Fall-through */
- case 265:
- /* Fall-through */
- case 266:
- /* Fall-through */
- case 267:
- /* Fall-through */
- case 268:
- /* Fall-through */
- case 269:
- /* Fall-through */
- case 270:
- use_dirty_helper = 1;
- break;
- case 271:
- opd[3] = V1EXP(opd[3]);
- use_dirty_helper = 1;
- break;
- case 272:
- use_dirty_helper = 1;
- break;
- case 273:
- opd[3] = V1EXP(opd[3]);
- use_dirty_helper = 1;
- break;
- case 274:
- use_dirty_helper = 1;
- break;
- case 275: /* "v1shrui" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_Shr8x8,
- getIReg(ra),
- mkU64(imm)));
- MARK_REG_WB(rd, t2);
- break;
- case 276:
- /* Fall-through */
- case 277:
- /* Fall-through */
- case 278:
- use_dirty_helper = 1;
- break;
- case 279:
- opd[3] = V2EXP(opd[3]);
- use_dirty_helper = 1;
- break;
- case 280:
- /* Fall-through */
- case 281:
- /* Fall-through */
- case 282:
- /* Fall-through */
- case 283:
- use_dirty_helper = 1;
- break;
- case 284:
- opd[3] = V2EXP(opd[3]);
- use_dirty_helper = 1;
- break;
- case 285:
- /* Fall-through */
- case 286:
- /* Fall-through */
- case 287:
- use_dirty_helper = 1;
- break;
- case 288:
- opd[3] = V2EXP(opd[3]);
- use_dirty_helper = 1;
- break;
- case 289:
- use_dirty_helper = 1;
- break;
- case 290:
- opd[3] = V2EXP(opd[3]);
- use_dirty_helper = 1;
- break;
- case 291:
- /* Fall-through */
- case 292:
- /* Fall-through */
- case 293:
- /* Fall-through */
- case 294:
- /* Fall-through */
- case 295:
- /* Fall-through */
- case 296:
- use_dirty_helper = 1;
- break;
- case 297:
- opd[3] = V2EXP(opd[3]);
- use_dirty_helper = 1;
- break;
- case 298:
- use_dirty_helper = 1;
- break;
- case 299:
- opd[3] = V2EXP(opd[3]);
- use_dirty_helper = 1;
- break;
- case 300:
- /* Fall-through */
- case 301:
- /* Fall-through */
- case 302:
- /* Fall-through */
- case 303:
- /* Fall-through */
- case 304:
- /* Fall-through */
- case 305:
- /* Fall-through */
- case 306:
- /* Fall-through */
- case 307:
- /* Fall-through */
- case 308:
- /* Fall-through */
- case 309:
- /* Fall-through */
- case 310:
- /* Fall-through */
- case 311:
- /* Fall-through */
- case 312:
- use_dirty_helper = 1;
- break;
- case 313:
- opd[3] = V2EXP(opd[3]);
- use_dirty_helper = 1;
- break;
- case 314:
- /* Fall-through */
- case 315:
- use_dirty_helper = 1;
- break;
- case 316:
- opd[3] = V2EXP(opd[3]);
- use_dirty_helper = 1;
- break;
- case 317:
- use_dirty_helper = 1;
- break;
- case 318:
- opd[3] = V2EXP(opd[3]);
- use_dirty_helper = 1;
- break;
- case 319:
- /* Fall-through */
- case 320:
- /* Fall-through */
- case 321:
- /* Fall-through */
- case 322:
- /* Fall-through */
- case 323:
- use_dirty_helper = 1;
- break;
- case 324: /* "v4int_l" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_Or64,
- binop(Iop_Shl64,
- getIReg(ra),
- mkU8(32)),
- binop(Iop_And64,
- getIReg(rb),
- mkU64(0xFFFFFFFF))));
- MARK_REG_WB(rd, t2);
- break;
- case 325:
- /* Fall-through */
- case 326:
- /* Fall-through */
- case 327:
- /* Fall-through */
- case 328:
- /* Fall-through */
- case 329:
- /* Fall-through */
- case 330:
- /* Fall-through */
- case 331:
- use_dirty_helper = 1;
- break;
- case 332: /* "wh64" */ /* Ignore store hint */
- break;
- case 333: /* "xor" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_Xor64,
- getIReg(ra),
- getIReg(rb)));
- MARK_REG_WB(rd, t2);
- break;
- case 334: /* "xori" */
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_Xor64,
- getIReg(ra),
- mkU64(imm)));
- MARK_REG_WB(rd, t2);
- break;
- case 335: /* "(null)" */ /* ignore */
- break;
- default:
-
- decode_failure:
- vex_printf("error: %d\n", (Int)opcode);
-
- /* All decode failures end up here. */
- vex_printf("vex tilegx->IR: unhandled instruction: "
- "%s 0x%llx 0x%llx 0x%llx 0x%llx\n",
- decoded[n].opcode->name,
- opd[0], opd[1], opd[2], opd[3]);
-
- /* Tell the dispatcher that this insn cannot be decoded, and so has
- not been executed, and (is currently) the next to be executed. */
- stmt(IRStmt_Put(offsetof(VexGuestTILEGXState, guest_pc),
- mkU64(guest_PC_curr_instr)));
- dres.whatNext = Dis_StopHere;
- dres.len = 0;
- return dres;
- }
-
- /* Hook the dirty helper for rare instruxtions. */
- if (use_dirty_helper)
- {
- Int i = 0;
- Int wbc = 0;
- IRExpr *opc_oprand[5];
-
- opc_oprand[0] = mkU64(opcode);
-
- /* Get the operand registers or immediate. */
- for (i = 0 ; i < 4; i++)
- {
- opc_oprand[i + 1] = NULL;
-
- if (opd_dst_map & (1ULL << i))
- {
- tb[wbc] = newTemp(Ity_I64);
- wbc++;
- opc_oprand[i + 1] = getIReg(opd[i]);
- }
- else if (opd_imm_map & (1ULL << i))
- opc_oprand[i + 1] = mkU64(opd[i]);
- else if (opd_src_map & (1ULL << i))
- opc_oprand[i + 1] = getIReg(opd[i]);
- else
- opc_oprand[i + 1] = mkU64(0xfeee);
- }
-
- IRExpr **args = mkIRExprVec_5(opc_oprand[0], opc_oprand[1],
- opc_oprand[2], opc_oprand[3],
- opc_oprand[4]);
- IRDirty *genIR = NULL;
-
- switch (wbc) {
- case 0:
- {
- genIR = unsafeIRDirty_0_N (0/*regparms*/,
- "tilegx_dirtyhelper_gen",
- &tilegx_dirtyhelper_gen,
- args);
- }
- break;
- case 1:
- {
- genIR = unsafeIRDirty_1_N (tb[0],
- 0/*regparms*/,
- "tilegx_dirtyhelper_gen",
- &tilegx_dirtyhelper_gen,
- args);
- }
- break;
- default:
- vex_printf("opc = %d\n", (Int)opcode);
- vassert(0);
- }
-
- stmt(IRStmt_Dirty(genIR));
-
- wbc = 0;
- for (i = 0 ; i < 4; i++)
- {
- if(opd_dst_map & (1 << i))
- {
- /* Queue the writeback destination registers. */
- MARK_REG_WB(opd[i], tb[wbc]);
- wbc++;
- }
- }
- }
- }
-
- /* Write back registers for a bundle. Note have to get all source registers
- for all instructions in a bundle before write the destinations b/c this is
- an VLIW processor. */
- for (n = 0; n < rd_wb_index; n++)
- putIReg(rd_wb_reg[n], mkexpr(rd_wb_temp[n]));
-
- /* Add branch IR if apply finally, only upto one branch per bundle. */
- if (bstmt) {
- stmt(bstmt);
- dres.whatNext = Dis_StopHere;
-
- dres.jk_StopHere = jumpkind;
- stmt(IRStmt_Put(offsetof(VexGuestTILEGXState, guest_pc),
- mkU64(guest_PC_curr_instr + 8)));
- } else if (next) {
- if (steering_pc != -1ULL) {
- if (resteerOkFn(callback_opaque, steering_pc)) {
- dres.whatNext = Dis_ResteerU;
- dres.continueAt = steering_pc;
- stmt(IRStmt_Put(offsetof(VexGuestTILEGXState, guest_pc),
- mkU64(steering_pc)));
- } else {
- dres.whatNext = Dis_StopHere;
- dres.jk_StopHere = jumpkind;
- stmt(IRStmt_Put(offsetof(VexGuestTILEGXState, guest_pc),
- mkU64(steering_pc)));
- }
- } else {
- dres.whatNext = Dis_StopHere;
- dres.jk_StopHere = jumpkind;
- stmt(IRStmt_Put(offsetof(VexGuestTILEGXState, guest_pc), next));
- }
- } else {
- /* As dafault dres.whatNext = Dis_Continue. */
- stmt(IRStmt_Put(offsetof(VexGuestTILEGXState, guest_pc),
- mkU64(guest_PC_curr_instr + 8)));
- }
-
- irsb->jumpkind = Ijk_Boring;
- irsb->next = NULL;
- dres.len = 8;
-
- decode_success:
-
- return dres;
-}
-
-/*------------------------------------------------------------*/
-/*--- Top-level fn ---*/
-/*------------------------------------------------------------*/
-
-/* Disassemble a single instruction into IR. The instruction
- is located in host memory at &guest_code[delta]. */
-
-DisResult
-disInstr_TILEGX ( IRSB* irsb_IN,
- Bool (*resteerOkFn) (void *, Addr),
- Bool resteerCisOk,
- void* callback_opaque,
- const UChar* guest_code_IN,
- Long delta,
- Addr guest_IP,
- VexArch guest_arch,
- const VexArchInfo* archinfo,
- const VexAbiInfo* abiinfo,
- VexEndness host_endness_IN,
- Bool sigill_diag_IN )
-{
- DisResult dres;
-
- /* Set globals (see top of this file) */
- vassert(guest_arch == VexArchTILEGX);
-
- guest_code = (UChar*)(Addr)guest_code_IN;
- irsb = irsb_IN;
- host_endness = host_endness_IN;
- guest_PC_curr_instr = (Addr64) guest_IP;
- guest_PC_bbstart = (Addr64) toUInt(guest_IP - delta);
-
- dres = disInstr_TILEGX_WRK(resteerOkFn, resteerCisOk,
- callback_opaque,
- delta, archinfo, abiinfo, sigill_diag_IN);
-
- return dres;
-}
-
-/*--------------------------------------------------------------------*/
-/*--- end guest_tilegx_toIR.c ---*/
-/*--------------------------------------------------------------------*/
diff --git a/VEX/priv/guest_x86_defs.h b/VEX/priv/guest_x86_defs.h
index 65f4a08..3f7a710 100644
--- a/VEX/priv/guest_x86_defs.h
+++ b/VEX/priv/guest_x86_defs.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -48,7 +48,7 @@
/*---------------------------------------------------------*/
/* Convert one x86 insn to IR. See the type DisOneInstrFn in
- bb_to_IR.h. */
+ guest_generic_bb_to_IR.h. */
extern
DisResult disInstr_X86 ( IRSB* irbb,
Bool (*resteerOkFn) ( void*, Addr ),
diff --git a/VEX/priv/guest_x86_helpers.c b/VEX/priv/guest_x86_helpers.c
index bc5a29e..250b1db 100644
--- a/VEX/priv/guest_x86_helpers.c
+++ b/VEX/priv/guest_x86_helpers.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -1599,18 +1599,17 @@
themselves are not transferred into the guest state. */
static
VexEmNote do_put_x87 ( Bool moveRegs,
- /*IN*/UChar* x87_state,
+ /*IN*/Fpu_State* x87_state,
/*OUT*/VexGuestX86State* vex_state )
{
Int stno, preg;
UInt tag;
ULong* vexRegs = (ULong*)(&vex_state->guest_FPREG[0]);
UChar* vexTags = (UChar*)(&vex_state->guest_FPTAG[0]);
- Fpu_State* x87 = (Fpu_State*)x87_state;
- UInt ftop = (x87->env[FP_ENV_STAT] >> 11) & 7;
- UInt tagw = x87->env[FP_ENV_TAG];
- UInt fpucw = x87->env[FP_ENV_CTRL];
- UInt c3210 = x87->env[FP_ENV_STAT] & 0x4700;
+ UInt ftop = (x87_state->env[FP_ENV_STAT] >> 11) & 7;
+ UInt tagw = x87_state->env[FP_ENV_TAG];
+ UInt fpucw = x87_state->env[FP_ENV_CTRL];
+ UInt c3210 = x87_state->env[FP_ENV_STAT] & 0x4700;
VexEmNote ew;
UInt fpround;
ULong pair;
@@ -1631,7 +1630,7 @@
} else {
/* register is non-empty */
if (moveRegs)
- convert_f80le_to_f64le( &x87->reg[10*stno],
+ convert_f80le_to_f64le( &x87_state->reg[10*stno],
(UChar*)&vexRegs[preg] );
vexTags[preg] = 1;
}
@@ -1660,23 +1659,23 @@
we can approximate it. */
static
void do_get_x87 ( /*IN*/VexGuestX86State* vex_state,
- /*OUT*/UChar* x87_state )
+ /*OUT*/Fpu_State* x87_state )
{
Int i, stno, preg;
UInt tagw;
ULong* vexRegs = (ULong*)(&vex_state->guest_FPREG[0]);
UChar* vexTags = (UChar*)(&vex_state->guest_FPTAG[0]);
- Fpu_State* x87 = (Fpu_State*)x87_state;
UInt ftop = vex_state->guest_FTOP;
UInt c3210 = vex_state->guest_FC3210;
for (i = 0; i < 14; i++)
- x87->env[i] = 0;
+ x87_state->env[i] = 0;
- x87->env[1] = x87->env[3] = x87->env[5] = x87->env[13] = 0xFFFF;
- x87->env[FP_ENV_STAT]
+ x87_state->env[1] = x87_state->env[3] = x87_state->env[5]
+ = x87_state->env[13] = 0xFFFF;
+ x87_state->env[FP_ENV_STAT]
= toUShort(((ftop & 7) << 11) | (c3210 & 0x4700));
- x87->env[FP_ENV_CTRL]
+ x87_state->env[FP_ENV_CTRL]
= toUShort(x86g_create_fpucw( vex_state->guest_FPROUND ));
/* Dump the register stack in ST order. */
@@ -1687,15 +1686,15 @@
/* register is empty */
tagw |= (3 << (2*preg));
convert_f64le_to_f80le( (UChar*)&vexRegs[preg],
- &x87->reg[10*stno] );
+ &x87_state->reg[10*stno] );
} else {
/* register is full. */
tagw |= (0 << (2*preg));
convert_f64le_to_f80le( (UChar*)&vexRegs[preg],
- &x87->reg[10*stno] );
+ &x87_state->reg[10*stno] );
}
}
- x87->env[FP_ENV_TAG] = toUShort(tagw);
+ x87_state->env[FP_ENV_TAG] = toUShort(tagw);
}
@@ -1714,7 +1713,7 @@
Int r, stno;
UShort *srcS, *dstS;
- do_get_x87( gst, (UChar*)&tmp );
+ do_get_x87( gst, &tmp );
mxcsr = x86g_create_mxcsr( gst->guest_SSEROUND );
/* Now build the proper fxsave image from the x87 image we just
@@ -1865,7 +1864,7 @@
tmp.env[FP_ENV_TAG] = fp_tags;
/* Now write 'tmp' into the guest state. */
- warnX87 = do_put_x87( True/*moveRegs*/, (UChar*)&tmp, gst );
+ warnX87 = do_put_x87( True/*moveRegs*/, &tmp, gst );
{ UInt w32 = (((UInt)addrS[12]) & 0xFFFF)
| ((((UInt)addrS[13]) & 0xFFFF) << 16);
@@ -1888,14 +1887,14 @@
/* DIRTY HELPER (reads guest state, writes guest mem) */
void x86g_dirtyhelper_FSAVE ( VexGuestX86State* gst, HWord addr )
{
- do_get_x87( gst, (UChar*)addr );
+ do_get_x87( gst, (Fpu_State*)addr );
}
/* CALLED FROM GENERATED CODE */
/* DIRTY HELPER (writes guest state, reads guest mem) */
VexEmNote x86g_dirtyhelper_FRSTOR ( VexGuestX86State* gst, HWord addr )
{
- return do_put_x87( True/*regs too*/, (UChar*)addr, gst );
+ return do_put_x87( True/*regs too*/, (Fpu_State*)addr, gst );
}
/* CALLED FROM GENERATED CODE */
@@ -1906,7 +1905,7 @@
Int i;
UShort* addrP = (UShort*)addr;
Fpu_State tmp;
- do_get_x87( gst, (UChar*)&tmp );
+ do_get_x87( gst, &tmp );
for (i = 0; i < 14; i++)
addrP[i] = tmp.env[i];
}
@@ -1915,7 +1914,7 @@
/* DIRTY HELPER (writes guest state, reads guest mem) */
VexEmNote x86g_dirtyhelper_FLDENV ( VexGuestX86State* gst, HWord addr )
{
- return do_put_x87( False/*don't move regs*/, (UChar*)addr, gst);
+ return do_put_x87( False/*don't move regs*/, (Fpu_State*)addr, gst);
}
/* VISIBLE TO LIBVEX CLIENT */
@@ -1925,7 +1924,7 @@
void LibVEX_GuestX86_get_x87 ( /*IN*/VexGuestX86State* vex_state,
/*OUT*/UChar* x87_state )
{
- do_get_x87 ( vex_state, x87_state );
+ do_get_x87 ( vex_state, (Fpu_State*)x87_state );
}
/* VISIBLE TO LIBVEX CLIENT */
@@ -1934,7 +1933,7 @@
VexEmNote LibVEX_GuestX86_put_x87 ( /*IN*/UChar* x87_state,
/*MOD*/VexGuestX86State* vex_state )
{
- return do_put_x87 ( True/*moveRegs*/, x87_state, vex_state );
+ return do_put_x87 ( True/*moveRegs*/, (Fpu_State*)x87_state, vex_state );
}
/* VISIBLE TO LIBVEX CLIENT */
@@ -2879,6 +2878,8 @@
vex_state->guest_IP_AT_SYSCALL = 0;
vex_state->padding1 = 0;
+ vex_state->padding2 = 0;
+ vex_state->padding3 = 0;
}
diff --git a/VEX/priv/guest_x86_toIR.c b/VEX/priv/guest_x86_toIR.c
index 24f9848..9f6a41a 100644
--- a/VEX/priv/guest_x86_toIR.c
+++ b/VEX/priv/guest_x86_toIR.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -1409,6 +1409,7 @@
case 0x26: return "%es:";
case 0x64: return "%fs:";
case 0x65: return "%gs:";
+ case 0x36: return "%ss:";
default: vpanic("sorbTxt(x86,guest)");
}
}
@@ -1433,6 +1434,7 @@
case 0x26: sreg = R_ES; break;
case 0x64: sreg = R_FS; break;
case 0x65: sreg = R_GS; break;
+ case 0x36: sreg = R_SS; break;
default: vpanic("handleSegOverride(x86,guest)");
}
@@ -3170,7 +3172,7 @@
/* Code shared by all the string ops */
static
-void dis_string_op_increment(Int sz, Int t_inc)
+void dis_string_op_increment(Int sz, IRTemp t_inc)
{
if (sz == 4 || sz == 2) {
assign( t_inc,
@@ -4030,7 +4032,7 @@
0/*regparms*/,
"x86g_dirtyhelper_FLDENV",
&x86g_dirtyhelper_FLDENV,
- mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) )
+ mkIRExprVec_2( IRExpr_GSPTR(), mkexpr(addr) )
);
d->tmp = ew;
/* declare we're reading memory */
@@ -4126,7 +4128,7 @@
0/*regparms*/,
"x86g_dirtyhelper_FSTENV",
&x86g_dirtyhelper_FSTENV,
- mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) )
+ mkIRExprVec_2( IRExpr_GSPTR(), mkexpr(addr) )
);
/* declare we're writing memory */
d->mFx = Ifx_Write;
@@ -4842,7 +4844,7 @@
0/*regparms*/,
"x86g_dirtyhelper_FINIT",
&x86g_dirtyhelper_FINIT,
- mkIRExprVec_1(IRExpr_BBPTR())
+ mkIRExprVec_1(IRExpr_GSPTR())
);
/* declare we're writing guest state */
@@ -5041,7 +5043,7 @@
0/*regparms*/,
"x86g_dirtyhelper_FRSTOR",
&x86g_dirtyhelper_FRSTOR,
- mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) )
+ mkIRExprVec_2( IRExpr_GSPTR(), mkexpr(addr) )
);
d->tmp = ew;
/* declare we're reading memory */
@@ -5100,7 +5102,7 @@
0/*regparms*/,
"x86g_dirtyhelper_FSAVE",
&x86g_dirtyhelper_FSAVE,
- mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) )
+ mkIRExprVec_2( IRExpr_GSPTR(), mkexpr(addr) )
);
/* declare we're writing memory */
d->mFx = Ifx_Write;
@@ -8101,7 +8103,7 @@
Int sz = 4;
/* sorb holds the segment-override-prefix byte, if any. Zero if no
- prefix has been seen, else one of {0x26, 0x3E, 0x64, 0x65}
+ prefix has been seen, else one of {0x26, 0x36, 0x3E, 0x64, 0x65}
indicating the prefix. */
UChar sorb = 0;
@@ -8112,6 +8114,7 @@
dres.whatNext = Dis_Continue;
dres.len = 0;
dres.continueAt = 0;
+ dres.hint = Dis_HintNone;
dres.jk_StopHere = Ijk_INVALID;
*expect_CAS = False;
@@ -8228,8 +8231,58 @@
goto decode_success;
}
}
- }
+ // Intel CET requires the following opcodes to be treated as NOPs
+ // with any prefix and ModRM, SIB and disp combination:
+ // "0F 19", "0F 1C", "0F 1D", "0F 1E", "0F 1F"
+ UInt opcode_index = 0;
+ // Skip any prefix combination
+ UInt addr_override = 0;
+ UInt temp_sz = 4;
+ Bool is_prefix = True;
+ while (is_prefix) {
+ switch (code[opcode_index]) {
+ case 0x66:
+ temp_sz = 2;
+ opcode_index++;
+ break;
+ case 0x67:
+ addr_override = 1;
+ opcode_index++;
+ break;
+ case 0x26: case 0x3E: // if we set segment override here,
+ case 0x64: case 0x65: // disAMode segfaults
+ case 0x2E: case 0x36:
+ case 0xF0: case 0xF2: case 0xF3:
+ opcode_index++;
+ break;
+ default:
+ is_prefix = False;
+ }
+ }
+ // Check the opcode
+ if (code[opcode_index] == 0x0F) {
+ switch (code[opcode_index+1]) {
+ case 0x19:
+ case 0x1C: case 0x1D:
+ case 0x1E: case 0x1F:
+ delta += opcode_index+2;
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ delta += 1;
+ DIP("nop%c\n", nameISize(temp_sz));
+ }
+ else {
+ addr = disAMode(&alen, 0/*"no sorb"*/, delta, dis_buf);
+ delta += alen - addr_override;
+ DIP("nop%c %s\n", nameISize(temp_sz), dis_buf);
+ }
+ goto decode_success;
+ default:
+ break;
+ }
+ }
+ }
/* Normal instruction handling starts here. */
/* Deal with some but not all prefixes:
@@ -8255,6 +8308,7 @@
case 0x26: /* %ES: */
case 0x64: /* %FS: */
case 0x65: /* %GS: */
+ case 0x36: /* %SS: */
if (sorb != 0)
goto decode_failure; /* only one seg override allowed */
sorb = pre;
@@ -8274,9 +8328,6 @@
}
break;
}
- case 0x36: /* %SS: */
- /* SS override cases are not handled */
- goto decode_failure;
default:
goto not_a_prefix;
}
@@ -8337,7 +8388,7 @@
0/*regparms*/,
"x86g_dirtyhelper_FXSAVE",
&x86g_dirtyhelper_FXSAVE,
- mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) )
+ mkIRExprVec_2( IRExpr_GSPTR(), mkexpr(addr) )
);
/* declare we're writing memory */
@@ -8411,7 +8462,7 @@
0/*regparms*/,
"x86g_dirtyhelper_FXRSTOR",
&x86g_dirtyhelper_FXRSTOR,
- mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) )
+ mkIRExprVec_2( IRExpr_GSPTR(), mkexpr(addr) )
);
/* declare we're reading memory */
@@ -14874,7 +14925,7 @@
vassert(fName); vassert(fAddr);
d = unsafeIRDirty_0_N ( 0/*regparms*/,
- fName, fAddr, mkIRExprVec_1(IRExpr_BBPTR()) );
+ fName, fAddr, mkIRExprVec_1(IRExpr_GSPTR()) );
/* declare guest state effects */
d->nFxState = 4;
vex_bzero(&d->fxState, sizeof(d->fxState));
@@ -15318,11 +15369,11 @@
see it (pass-through semantics). I can't see any way to
construct a faked-up value, so don't bother to try. */
modrm = getUChar(delta);
- addr = disAMode ( &alen, sorb, delta, dis_buf );
- delta += alen;
if (epartIsReg(modrm)) goto decode_failure;
if (gregOfRM(modrm) != 0 && gregOfRM(modrm) != 1)
goto decode_failure;
+ addr = disAMode ( &alen, sorb, delta, dis_buf );
+ delta += alen;
switch (gregOfRM(modrm)) {
case 0: DIP("sgdt %s\n", dis_buf); break;
case 1: DIP("sidt %s\n", dis_buf); break;
diff --git a/VEX/priv/host_amd64_defs.c b/VEX/priv/host_amd64_defs.c
index 9dec78c..5e0600a 100644
--- a/VEX/priv/host_amd64_defs.c
+++ b/VEX/priv/host_amd64_defs.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -1995,6 +1995,43 @@
}
}
+AMD64Instr* directReload_AMD64( AMD64Instr* i, HReg vreg, Short spill_off )
+{
+ vassert(spill_off >= 0 && spill_off < 10000); /* let's say */
+
+ /* Deal with form: src=RMI_Reg, dst=Reg where src == vreg
+ Convert to: src=RMI_Mem, dst=Reg
+ */
+ if (i->tag == Ain_Alu64R
+ && (i->Ain.Alu64R.op == Aalu_MOV || i->Ain.Alu64R.op == Aalu_OR
+ || i->Ain.Alu64R.op == Aalu_XOR)
+ && i->Ain.Alu64R.src->tag == Armi_Reg
+ && sameHReg(i->Ain.Alu64R.src->Armi.Reg.reg, vreg)) {
+ vassert(! sameHReg(i->Ain.Alu64R.dst, vreg));
+ return AMD64Instr_Alu64R(
+ i->Ain.Alu64R.op,
+ AMD64RMI_Mem( AMD64AMode_IR( spill_off, hregAMD64_RBP())),
+ i->Ain.Alu64R.dst
+ );
+ }
+
+ /* Deal with form: src=RMI_Imm, dst=Reg where dst == vreg
+ Convert to: src=RI_Imm, dst=Mem
+ */
+ if (i->tag == Ain_Alu64R
+ && (i->Ain.Alu64R.op == Aalu_CMP)
+ && i->Ain.Alu64R.src->tag == Armi_Imm
+ && sameHReg(i->Ain.Alu64R.dst, vreg)) {
+ return AMD64Instr_Alu64M(
+ i->Ain.Alu64R.op,
+ AMD64RI_Imm( i->Ain.Alu64R.src->Armi.Imm.imm32 ),
+ AMD64AMode_IR( spill_off, hregAMD64_RBP())
+ );
+ }
+
+ return NULL;
+}
+
/* --------- The amd64 assembler (bleh.) --------- */
@@ -2607,6 +2644,39 @@
goto bad;
}
}
+ /* ADD/SUB/ADC/SBB/AND/OR/XOR/CMP. MUL is not
+ allowed here. (This is derived from the x86 version of same). */
+ opc = subopc_imm = opc_imma = 0;
+ switch (i->Ain.Alu64M.op) {
+ case Aalu_CMP: opc = 0x39; subopc_imm = 7; break;
+ default: goto bad;
+ }
+ switch (i->Ain.Alu64M.src->tag) {
+ /*
+ case Xri_Reg:
+ *p++ = toUChar(opc);
+ p = doAMode_M(p, i->Xin.Alu32M.src->Xri.Reg.reg,
+ i->Xin.Alu32M.dst);
+ goto done;
+ */
+ case Ari_Imm:
+ if (fits8bits(i->Ain.Alu64M.src->Ari.Imm.imm32)) {
+ *p++ = rexAMode_M_enc(subopc_imm, i->Ain.Alu64M.dst);
+ *p++ = 0x83;
+ p = doAMode_M_enc(p, subopc_imm, i->Ain.Alu64M.dst);
+ *p++ = toUChar(0xFF & i->Ain.Alu64M.src->Ari.Imm.imm32);
+ goto done;
+ } else {
+ *p++ = rexAMode_M_enc(subopc_imm, i->Ain.Alu64M.dst);
+ *p++ = 0x81;
+ p = doAMode_M_enc(p, subopc_imm, i->Ain.Alu64M.dst);
+ p = emit32(p, i->Ain.Alu64M.src->Ari.Imm.imm32);
+ goto done;
+ }
+ default:
+ goto bad;
+ }
+
break;
case Ain_Sh64:
diff --git a/VEX/priv/host_amd64_defs.h b/VEX/priv/host_amd64_defs.h
index fe999f2..39682ef 100644
--- a/VEX/priv/host_amd64_defs.h
+++ b/VEX/priv/host_amd64_defs.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -802,6 +802,9 @@
extern void genReload_AMD64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
HReg rreg, Int offset, Bool );
+extern AMD64Instr* directReload_AMD64 ( AMD64Instr* i,
+ HReg vreg, Short spill_off );
+
extern const RRegUniverse* getRRegUniverse_AMD64 ( void );
extern HInstrArray* iselSB_AMD64 ( const IRSB*,
diff --git a/VEX/priv/host_amd64_isel.c b/VEX/priv/host_amd64_isel.c
index a08c980..ecd57e7 100644
--- a/VEX/priv/host_amd64_isel.c
+++ b/VEX/priv/host_amd64_isel.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -216,42 +216,42 @@
checks that all returned registers are virtual. You should not
call the _wrk version directly.
*/
-static AMD64RMI* iselIntExpr_RMI_wrk ( ISelEnv* env, IRExpr* e );
-static AMD64RMI* iselIntExpr_RMI ( ISelEnv* env, IRExpr* e );
+static AMD64RMI* iselIntExpr_RMI_wrk ( ISelEnv* env, const IRExpr* e );
+static AMD64RMI* iselIntExpr_RMI ( ISelEnv* env, const IRExpr* e );
-static AMD64RI* iselIntExpr_RI_wrk ( ISelEnv* env, IRExpr* e );
-static AMD64RI* iselIntExpr_RI ( ISelEnv* env, IRExpr* e );
+static AMD64RI* iselIntExpr_RI_wrk ( ISelEnv* env, const IRExpr* e );
+static AMD64RI* iselIntExpr_RI ( ISelEnv* env, const IRExpr* e );
-static AMD64RM* iselIntExpr_RM_wrk ( ISelEnv* env, IRExpr* e );
-static AMD64RM* iselIntExpr_RM ( ISelEnv* env, IRExpr* e );
+static AMD64RM* iselIntExpr_RM_wrk ( ISelEnv* env, const IRExpr* e );
+static AMD64RM* iselIntExpr_RM ( ISelEnv* env, const IRExpr* e );
-static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e );
-static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e );
+static HReg iselIntExpr_R_wrk ( ISelEnv* env, const IRExpr* e );
+static HReg iselIntExpr_R ( ISelEnv* env, const IRExpr* e );
-static AMD64AMode* iselIntExpr_AMode_wrk ( ISelEnv* env, IRExpr* e );
-static AMD64AMode* iselIntExpr_AMode ( ISelEnv* env, IRExpr* e );
+static AMD64AMode* iselIntExpr_AMode_wrk ( ISelEnv* env, const IRExpr* e );
+static AMD64AMode* iselIntExpr_AMode ( ISelEnv* env, const IRExpr* e );
static void iselInt128Expr_wrk ( /*OUT*/HReg* rHi, HReg* rLo,
- ISelEnv* env, IRExpr* e );
+ ISelEnv* env, const IRExpr* e );
static void iselInt128Expr ( /*OUT*/HReg* rHi, HReg* rLo,
- ISelEnv* env, IRExpr* e );
+ ISelEnv* env, const IRExpr* e );
-static AMD64CondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e );
-static AMD64CondCode iselCondCode ( ISelEnv* env, IRExpr* e );
+static AMD64CondCode iselCondCode_wrk ( ISelEnv* env, const IRExpr* e );
+static AMD64CondCode iselCondCode ( ISelEnv* env, const IRExpr* e );
-static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e );
-static HReg iselDblExpr ( ISelEnv* env, IRExpr* e );
+static HReg iselDblExpr_wrk ( ISelEnv* env, const IRExpr* e );
+static HReg iselDblExpr ( ISelEnv* env, const IRExpr* e );
-static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e );
-static HReg iselFltExpr ( ISelEnv* env, IRExpr* e );
+static HReg iselFltExpr_wrk ( ISelEnv* env, const IRExpr* e );
+static HReg iselFltExpr ( ISelEnv* env, const IRExpr* e );
-static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e );
-static HReg iselVecExpr ( ISelEnv* env, IRExpr* e );
+static HReg iselVecExpr_wrk ( ISelEnv* env, const IRExpr* e );
+static HReg iselVecExpr ( ISelEnv* env, const IRExpr* e );
static void iselDVecExpr_wrk ( /*OUT*/HReg* rHi, HReg* rLo,
- ISelEnv* env, IRExpr* e );
+ ISelEnv* env, const IRExpr* e );
static void iselDVecExpr ( /*OUT*/HReg* rHi, HReg* rLo,
- ISelEnv* env, IRExpr* e );
+ ISelEnv* env, const IRExpr* e );
/*---------------------------------------------------------*/
@@ -370,7 +370,7 @@
vassert(e->tag != Iex_VECRET);
/* In this case we give out a copy of the BaseBlock pointer. */
- if (UNLIKELY(e->tag == Iex_BBPTR)) {
+ if (UNLIKELY(e->tag == Iex_GSPTR)) {
return mk_iMOVsd_RR( hregAMD64_RBP(), dst );
}
@@ -442,9 +442,9 @@
*retloc = mk_RetLoc_INVALID();
/* These are used for cross-checking that IR-level constraints on
- the use of IRExpr_VECRET() and IRExpr_BBPTR() are observed. */
+ the use of IRExpr_VECRET() and IRExpr_GSPTR() are observed. */
UInt nVECRETs = 0;
- UInt nBBPTRs = 0;
+ UInt nGSPTRs = 0;
/* Marshal args for a call and do the call.
@@ -462,7 +462,7 @@
stack, it is enough to preallocate the return space before
marshalling any arguments, in this case.
- |args| may also contain IRExpr_BBPTR(), in which case the
+ |args| may also contain IRExpr_GSPTR(), in which case the
value in %rbp is passed as the corresponding argument.
Generating code which is both efficient and correct when
@@ -556,7 +556,7 @@
/* FAST SCHEME */
/* In this loop, we process args that can be computed into the
destination (real) register with a single instruction, without
- using any fixed regs. That also includes IRExpr_BBPTR(), but
+ using any fixed regs. That also includes IRExpr_GSPTR(), but
not IRExpr_VECRET(). Indeed, if the IR is well-formed, we can
never see IRExpr_VECRET() at this point, since the return-type
check above should ensure all those cases use the slow scheme
@@ -564,7 +564,7 @@
vassert(n_args >= 0 && n_args <= 6);
for (i = 0; i < n_args; i++) {
IRExpr* arg = args[i];
- if (LIKELY(!is_IRExpr_VECRET_or_BBPTR(arg))) {
+ if (LIKELY(!is_IRExpr_VECRET_or_GSPTR(arg))) {
vassert(typeOfIRExpr(env->type_env, args[i]) == Ity_I64);
}
fastinstrs[i]
@@ -610,10 +610,10 @@
vassert(n_args >= 0 && n_args <= 6);
for (i = 0; i < n_args; i++) {
IRExpr* arg = args[i];
- if (UNLIKELY(arg->tag == Iex_BBPTR)) {
+ if (UNLIKELY(arg->tag == Iex_GSPTR)) {
tmpregs[i] = newVRegI(env);
addInstr(env, mk_iMOVsd_RR( hregAMD64_RBP(), tmpregs[i]));
- nBBPTRs++;
+ nGSPTRs++;
}
else if (UNLIKELY(arg->tag == Iex_VECRET)) {
/* We stashed the address of the return slot earlier, so just
@@ -661,7 +661,7 @@
vassert(nVECRETs == 0);
}
- vassert(nBBPTRs == 0 || nBBPTRs == 1);
+ vassert(nGSPTRs == 0 || nGSPTRs == 1);
vassert(*stackAdjustAfterCall == 0);
vassert(is_RetLoc_INVALID(*retloc));
@@ -896,7 +896,7 @@
mask or sign extend partial values if necessary.
*/
-static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e )
+static HReg iselIntExpr_R ( ISelEnv* env, const IRExpr* e )
{
HReg r = iselIntExpr_R_wrk(env, e);
/* sanity checks ... */
@@ -909,7 +909,7 @@
}
/* DO NOT CALL THIS DIRECTLY ! */
-static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
+static HReg iselIntExpr_R_wrk ( ISelEnv* env, const IRExpr* e )
{
/* Used for unary/binary SIMD64 ops. */
HWord fn = 0;
@@ -1379,7 +1379,7 @@
DEFINE_PATTERN( p_1Uto8_64to1,
unop(Iop_1Uto8, unop(Iop_64to1, bind(0))) );
if (matchIRExpr(&mi,p_1Uto8_64to1,e)) {
- IRExpr* expr64 = mi.bindee[0];
+ const IRExpr* expr64 = mi.bindee[0];
HReg dst = newVRegI(env);
HReg src = iselIntExpr_R(env, expr64);
addInstr(env, mk_iMOVsd_RR(src,dst) );
@@ -1934,7 +1934,7 @@
result. The expression may only be a 32-bit one.
*/
-static AMD64AMode* iselIntExpr_AMode ( ISelEnv* env, IRExpr* e )
+static AMD64AMode* iselIntExpr_AMode ( ISelEnv* env, const IRExpr* e )
{
AMD64AMode* am = iselIntExpr_AMode_wrk(env, e);
vassert(sane_AMode(am));
@@ -1942,7 +1942,7 @@
}
/* DO NOT CALL THIS DIRECTLY ! */
-static AMD64AMode* iselIntExpr_AMode_wrk ( ISelEnv* env, IRExpr* e )
+static AMD64AMode* iselIntExpr_AMode_wrk ( ISelEnv* env, const IRExpr* e )
{
MatchInfo mi;
DECLARE_PATTERN(p_complex);
@@ -1961,10 +1961,10 @@
)
);
if (matchIRExpr(&mi, p_complex, e)) {
- IRExpr* expr1 = mi.bindee[0];
- IRExpr* expr2 = mi.bindee[1];
- IRExpr* imm8 = mi.bindee[2];
- IRExpr* simm32 = mi.bindee[3];
+ const IRExpr* expr1 = mi.bindee[0];
+ const IRExpr* expr2 = mi.bindee[1];
+ const IRExpr* imm8 = mi.bindee[2];
+ const IRExpr* simm32 = mi.bindee[3];
if (imm8->tag == Iex_Const
&& imm8->Iex.Const.con->tag == Ico_U8
&& imm8->Iex.Const.con->Ico.U8 < 4
@@ -2023,7 +2023,7 @@
/* Similarly, calculate an expression into an X86RMI operand. As with
iselIntExpr_R, the expression can have type 32, 16 or 8 bits. */
-static AMD64RMI* iselIntExpr_RMI ( ISelEnv* env, IRExpr* e )
+static AMD64RMI* iselIntExpr_RMI ( ISelEnv* env, const IRExpr* e )
{
AMD64RMI* rmi = iselIntExpr_RMI_wrk(env, e);
/* sanity checks ... */
@@ -2043,7 +2043,7 @@
}
/* DO NOT CALL THIS DIRECTLY ! */
-static AMD64RMI* iselIntExpr_RMI_wrk ( ISelEnv* env, IRExpr* e )
+static AMD64RMI* iselIntExpr_RMI_wrk ( ISelEnv* env, const IRExpr* e )
{
IRType ty = typeOfIRExpr(env->type_env,e);
vassert(ty == Ity_I64 || ty == Ity_I32
@@ -2095,7 +2095,7 @@
iselIntExpr_R, the expression can have type 64, 32, 16 or 8
bits. */
-static AMD64RI* iselIntExpr_RI ( ISelEnv* env, IRExpr* e )
+static AMD64RI* iselIntExpr_RI ( ISelEnv* env, const IRExpr* e )
{
AMD64RI* ri = iselIntExpr_RI_wrk(env, e);
/* sanity checks ... */
@@ -2112,7 +2112,7 @@
}
/* DO NOT CALL THIS DIRECTLY ! */
-static AMD64RI* iselIntExpr_RI_wrk ( ISelEnv* env, IRExpr* e )
+static AMD64RI* iselIntExpr_RI_wrk ( ISelEnv* env, const IRExpr* e )
{
IRType ty = typeOfIRExpr(env->type_env,e);
vassert(ty == Ity_I64 || ty == Ity_I32
@@ -2151,7 +2151,7 @@
with iselIntExpr_R, the expression can have type 64, 32, 16 or 8
bits. */
-static AMD64RM* iselIntExpr_RM ( ISelEnv* env, IRExpr* e )
+static AMD64RM* iselIntExpr_RM ( ISelEnv* env, const IRExpr* e )
{
AMD64RM* rm = iselIntExpr_RM_wrk(env, e);
/* sanity checks ... */
@@ -2169,7 +2169,7 @@
}
/* DO NOT CALL THIS DIRECTLY ! */
-static AMD64RM* iselIntExpr_RM_wrk ( ISelEnv* env, IRExpr* e )
+static AMD64RM* iselIntExpr_RM_wrk ( ISelEnv* env, const IRExpr* e )
{
IRType ty = typeOfIRExpr(env->type_env,e);
vassert(ty == Ity_I64 || ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8);
@@ -2196,14 +2196,14 @@
condition code which would correspond when the expression would
notionally have returned 1. */
-static AMD64CondCode iselCondCode ( ISelEnv* env, IRExpr* e )
+static AMD64CondCode iselCondCode ( ISelEnv* env, const IRExpr* e )
{
/* Uh, there's nothing we can sanity check here, unfortunately. */
return iselCondCode_wrk(env,e);
}
/* DO NOT CALL THIS DIRECTLY ! */
-static AMD64CondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e )
+static AMD64CondCode iselCondCode_wrk ( ISelEnv* env, const IRExpr* e )
{
MatchInfo mi;
@@ -2457,7 +2457,7 @@
by subsequent code emitted by the caller. */
static void iselInt128Expr ( HReg* rHi, HReg* rLo,
- ISelEnv* env, IRExpr* e )
+ ISelEnv* env, const IRExpr* e )
{
iselInt128Expr_wrk(rHi, rLo, env, e);
# if 0
@@ -2471,7 +2471,7 @@
/* DO NOT CALL THIS DIRECTLY ! */
static void iselInt128Expr_wrk ( HReg* rHi, HReg* rLo,
- ISelEnv* env, IRExpr* e )
+ ISelEnv* env, const IRExpr* e )
{
vassert(e);
vassert(typeOfIRExpr(env->type_env,e) == Ity_I128);
@@ -2550,7 +2550,7 @@
/* Nothing interesting here; really just wrappers for
64-bit stuff. */
-static HReg iselFltExpr ( ISelEnv* env, IRExpr* e )
+static HReg iselFltExpr ( ISelEnv* env, const IRExpr* e )
{
HReg r = iselFltExpr_wrk( env, e );
# if 0
@@ -2562,7 +2562,7 @@
}
/* DO NOT CALL THIS DIRECTLY */
-static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e )
+static HReg iselFltExpr_wrk ( ISelEnv* env, const IRExpr* e )
{
IRType ty = typeOfIRExpr(env->type_env,e);
vassert(ty == Ity_F32);
@@ -2737,7 +2737,7 @@
positive zero 0 0 .000000---0
*/
-static HReg iselDblExpr ( ISelEnv* env, IRExpr* e )
+static HReg iselDblExpr ( ISelEnv* env, const IRExpr* e )
{
HReg r = iselDblExpr_wrk( env, e );
# if 0
@@ -2749,7 +2749,7 @@
}
/* DO NOT CALL THIS DIRECTLY */
-static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e )
+static HReg iselDblExpr_wrk ( ISelEnv* env, const IRExpr* e )
{
IRType ty = typeOfIRExpr(env->type_env,e);
vassert(e);
@@ -3104,7 +3104,7 @@
/*--- ISEL: SIMD (Vector) expressions, 128 bit. ---*/
/*---------------------------------------------------------*/
-static HReg iselVecExpr ( ISelEnv* env, IRExpr* e )
+static HReg iselVecExpr ( ISelEnv* env, const IRExpr* e )
{
HReg r = iselVecExpr_wrk( env, e );
# if 0
@@ -3117,7 +3117,7 @@
/* DO NOT CALL THIS DIRECTLY */
-static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
+static HReg iselVecExpr_wrk ( ISelEnv* env, const IRExpr* e )
{
HWord fn = 0; /* address of helper fn, if required */
Bool arg1isEReg = False;
@@ -3719,7 +3719,7 @@
/*---------------------------------------------------------*/
static void iselDVecExpr ( /*OUT*/HReg* rHi, /*OUT*/HReg* rLo,
- ISelEnv* env, IRExpr* e )
+ ISelEnv* env, const IRExpr* e )
{
iselDVecExpr_wrk( rHi, rLo, env, e );
# if 0
@@ -3734,7 +3734,7 @@
/* DO NOT CALL THIS DIRECTLY */
static void iselDVecExpr_wrk ( /*OUT*/HReg* rHi, /*OUT*/HReg* rLo,
- ISelEnv* env, IRExpr* e )
+ ISelEnv* env, const IRExpr* e )
{
HWord fn = 0; /* address of helper fn, if required */
vassert(e);
diff --git a/VEX/priv/host_arm64_defs.c b/VEX/priv/host_arm64_defs.c
index cc7c832..380a24d 100644
--- a/VEX/priv/host_arm64_defs.c
+++ b/VEX/priv/host_arm64_defs.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2013-2015 OpenWorks
+ Copyright (C) 2013-2017 OpenWorks
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -1005,6 +1005,13 @@
vassert(szB == 8 || szB == 4 || szB == 2 || szB == 1);
return i;
}
+ARM64Instr* ARM64Instr_CAS ( Int szB ) {
+ ARM64Instr* i = LibVEX_Alloc_inline(sizeof(ARM64Instr));
+ i->tag = ARM64in_CAS;
+ i->ARM64in.CAS.szB = szB;
+ vassert(szB == 8 || szB == 4 || szB == 2 || szB == 1);
+ return i;
+}
ARM64Instr* ARM64Instr_MFence ( void ) {
ARM64Instr* i = LibVEX_Alloc_inline(sizeof(ARM64Instr));
i->tag = ARM64in_MFence;
@@ -1569,6 +1576,10 @@
sz, i->ARM64in.StrEX.szB == 8 ? 'x' : 'w');
return;
}
+ case ARM64in_CAS: {
+ vex_printf("x1 = cas(%dbit)(x3, x5 -> x7)", 8 * i->ARM64in.CAS.szB);
+ return;
+ }
case ARM64in_MFence:
vex_printf("(mfence) dsb sy; dmb sy; isb");
return;
@@ -2064,6 +2075,14 @@
addHRegUse(u, HRmWrite, hregARM64_X0());
addHRegUse(u, HRmRead, hregARM64_X2());
return;
+ case ARM64in_CAS:
+ addHRegUse(u, HRmRead, hregARM64_X3());
+ addHRegUse(u, HRmRead, hregARM64_X5());
+ addHRegUse(u, HRmRead, hregARM64_X7());
+ addHRegUse(u, HRmWrite, hregARM64_X1());
+ /* Pointless to state this since X8 is not available to RA. */
+ addHRegUse(u, HRmWrite, hregARM64_X8());
+ break;
case ARM64in_MFence:
return;
case ARM64in_ClrEX:
@@ -2326,6 +2345,8 @@
return;
case ARM64in_StrEX:
return;
+ case ARM64in_CAS:
+ return;
case ARM64in_MFence:
return;
case ARM64in_ClrEX:
@@ -3803,6 +3824,61 @@
}
goto bad;
}
+ case ARM64in_CAS: {
+ /* This isn't simple. For an explanation see the comment in
+ host_arm64_defs.h on the the definition of ARM64Instr case
+ CAS. */
+ /* Generate:
+ -- one of:
+ mov x8, x5 // AA0503E8
+ and x8, x5, #0xFFFFFFFF // 92407CA8
+ and x8, x5, #0xFFFF // 92403CA8
+ and x8, x5, #0xFF // 92401CA8
+
+ -- one of:
+ ldxr x1, [x3] // C85F7C61
+ ldxr w1, [x3] // 885F7C61
+ ldxrh w1, [x3] // 485F7C61
+ ldxrb w1, [x3] // 085F7C61
+
+ -- always:
+ cmp x1, x8 // EB08003F
+ bne out // 54000061
+
+ -- one of:
+ stxr w1, x7, [x3] // C8017C67
+ stxr w1, w7, [x3] // 88017C67
+ stxrh w1, w7, [x3] // 48017C67
+ stxrb w1, w7, [x3] // 08017C67
+
+ -- always:
+ eor x1, x5, x1 // CA0100A1
+ out:
+ */
+ switch (i->ARM64in.CAS.szB) {
+ case 8: *p++ = 0xAA0503E8; break;
+ case 4: *p++ = 0x92407CA8; break;
+ case 2: *p++ = 0x92403CA8; break;
+ case 1: *p++ = 0x92401CA8; break;
+ default: vassert(0);
+ }
+ switch (i->ARM64in.CAS.szB) {
+ case 8: *p++ = 0xC85F7C61; break;
+ case 4: *p++ = 0x885F7C61; break;
+ case 2: *p++ = 0x485F7C61; break;
+ case 1: *p++ = 0x085F7C61; break;
+ }
+ *p++ = 0xEB08003F;
+ *p++ = 0x54000061;
+ switch (i->ARM64in.CAS.szB) {
+ case 8: *p++ = 0xC8017C67; break;
+ case 4: *p++ = 0x88017C67; break;
+ case 2: *p++ = 0x48017C67; break;
+ case 1: *p++ = 0x08017C67; break;
+ }
+ *p++ = 0xCA0100A1;
+ goto done;
+ }
case ARM64in_MFence: {
*p++ = 0xD5033F9F; /* DSB sy */
*p++ = 0xD5033FBF; /* DMB sy */
diff --git a/VEX/priv/host_arm64_defs.h b/VEX/priv/host_arm64_defs.h
index 62b25fd..14b2de6 100644
--- a/VEX/priv/host_arm64_defs.h
+++ b/VEX/priv/host_arm64_defs.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2013-2015 OpenWorks
+ Copyright (C) 2013-2017 OpenWorks
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -481,6 +481,7 @@
ARM64in_Mul,
ARM64in_LdrEX,
ARM64in_StrEX,
+ ARM64in_CAS,
ARM64in_MFence,
ARM64in_ClrEX,
/* ARM64in_V*: scalar ops involving vector registers */
@@ -668,6 +669,32 @@
struct {
Int szB; /* 1, 2, 4 or 8 */
} StrEX;
+ /* x1 = CAS(x3(addr), x5(expected) -> x7(new)),
+ where x1[8*szB-1 : 0] == x5[8*szB-1 : 0] indicates success,
+ x1[8*szB-1 : 0] != x5[8*szB-1 : 0] indicates failure.
+ Uses x8 as scratch (but that's not allocatable).
+ Hence: RD x3, x5, x7; WR x1
+
+ (szB=8) mov x8, x5
+ (szB=4) and x8, x5, #0xFFFFFFFF
+ (szB=2) and x8, x5, #0xFFFF
+ (szB=1) and x8, x5, #0xFF
+ -- x8 is correctly zero-extended expected value
+ ldxr x1, [x3]
+ -- x1 is correctly zero-extended actual value
+ cmp x1, x8
+ bne after
+ -- if branch taken, failure; x1[[8*szB-1 : 0] holds old value
+ -- attempt to store
+ stxr w1, x7, [x3]
+ -- if store successful, x1==0, so the eor is "x1 := x5"
+ -- if store failed, x1==1, so the eor makes x1 != x5
+ eor x1, x5, x1
+ after:
+ */
+ struct {
+ Int szB; /* 1, 2, 4 or 8 */
+ } CAS;
/* Mem fence. An insn which fences all loads and stores as
much as possible before continuing. On ARM64 we emit the
sequence "dsb sy ; dmb sy ; isb sy", which is probably
@@ -912,6 +939,7 @@
ARM64MulOp op );
extern ARM64Instr* ARM64Instr_LdrEX ( Int szB );
extern ARM64Instr* ARM64Instr_StrEX ( Int szB );
+extern ARM64Instr* ARM64Instr_CAS ( Int szB );
extern ARM64Instr* ARM64Instr_MFence ( void );
extern ARM64Instr* ARM64Instr_ClrEX ( void );
extern ARM64Instr* ARM64Instr_VLdStH ( Bool isLoad, HReg sD, HReg rN,
diff --git a/VEX/priv/host_arm64_isel.c b/VEX/priv/host_arm64_isel.c
index 9aadcce..50f9205 100644
--- a/VEX/priv/host_arm64_isel.c
+++ b/VEX/priv/host_arm64_isel.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2013-2015 OpenWorks
+ Copyright (C) 2013-2017 OpenWorks
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -298,10 +298,9 @@
a new register, and return the new register. */
static HReg widen_z_16_to_64 ( ISelEnv* env, HReg src )
{
- HReg dst = newVRegI(env);
- ARM64RI6* n48 = ARM64RI6_I6(48);
- addInstr(env, ARM64Instr_Shift(dst, src, n48, ARM64sh_SHL));
- addInstr(env, ARM64Instr_Shift(dst, dst, n48, ARM64sh_SHR));
+ HReg dst = newVRegI(env);
+ ARM64RIL* mask = ARM64RIL_I13(1, 0, 15); /* encodes 0xFFFF */
+ addInstr(env, ARM64Instr_Logic(dst, src, mask, ARM64lo_AND));
return dst;
}
@@ -329,10 +328,9 @@
static HReg widen_z_8_to_64 ( ISelEnv* env, HReg src )
{
- HReg dst = newVRegI(env);
- ARM64RI6* n56 = ARM64RI6_I6(56);
- addInstr(env, ARM64Instr_Shift(dst, src, n56, ARM64sh_SHL));
- addInstr(env, ARM64Instr_Shift(dst, dst, n56, ARM64sh_SHR));
+ HReg dst = newVRegI(env);
+ ARM64RIL* mask = ARM64RIL_I13(1, 0, 7); /* encodes 0xFF */
+ addInstr(env, ARM64Instr_Logic(dst, src, mask, ARM64lo_AND));
return dst;
}
@@ -449,7 +447,7 @@
static
Bool mightRequireFixedRegs ( IRExpr* e )
{
- if (UNLIKELY(is_IRExpr_VECRET_or_BBPTR(e))) {
+ if (UNLIKELY(is_IRExpr_VECRET_or_GSPTR(e))) {
// These are always "safe" -- either a copy of SP in some
// arbitrary vreg, or a copy of x21, respectively.
return False;
@@ -493,9 +491,9 @@
*retloc = mk_RetLoc_INVALID();
/* These are used for cross-checking that IR-level constraints on
- the use of IRExpr_VECRET() and IRExpr_BBPTR() are observed. */
+ the use of IRExpr_VECRET() and IRExpr_GSPTR() are observed. */
UInt nVECRETs = 0;
- UInt nBBPTRs = 0;
+ UInt nGSPTRs = 0;
/* Marshal args for a call and do the call.
@@ -513,7 +511,7 @@
preallocate the return space before marshalling any arguments,
in this case.
- |args| may also contain IRExpr_BBPTR(), in which case the
+ |args| may also contain IRExpr_GSPTR(), in which case the
value in x21 is passed as the corresponding argument.
Generating code which is both efficient and correct when
@@ -560,14 +558,14 @@
IRExpr* arg = args[i];
if (UNLIKELY(arg->tag == Iex_VECRET)) {
nVECRETs++;
- } else if (UNLIKELY(arg->tag == Iex_BBPTR)) {
- nBBPTRs++;
+ } else if (UNLIKELY(arg->tag == Iex_GSPTR)) {
+ nGSPTRs++;
}
n_args++;
}
/* If this fails, the IR is ill-formed */
- vassert(nBBPTRs == 0 || nBBPTRs == 1);
+ vassert(nGSPTRs == 0 || nGSPTRs == 1);
/* If we have a VECRET, allocate space on the stack for the return
value, and record the stack pointer after that. */
@@ -640,7 +638,7 @@
IRExpr* arg = args[i];
IRType aTy = Ity_INVALID;
- if (LIKELY(!is_IRExpr_VECRET_or_BBPTR(arg)))
+ if (LIKELY(!is_IRExpr_VECRET_or_GSPTR(arg)))
aTy = typeOfIRExpr(env->type_env, args[i]);
if (nextArgReg >= ARM64_N_ARGREGS)
@@ -651,7 +649,7 @@
iselIntExpr_R(env, args[i]) ));
nextArgReg++;
}
- else if (arg->tag == Iex_BBPTR) {
+ else if (arg->tag == Iex_GSPTR) {
vassert(0); //ATC
addInstr(env, ARM64Instr_MovI( argregs[nextArgReg],
hregARM64_X21() ));
@@ -679,7 +677,7 @@
IRExpr* arg = args[i];
IRType aTy = Ity_INVALID;
- if (LIKELY(!is_IRExpr_VECRET_or_BBPTR(arg)))
+ if (LIKELY(!is_IRExpr_VECRET_or_GSPTR(arg)))
aTy = typeOfIRExpr(env->type_env, args[i]);
if (nextArgReg >= ARM64_N_ARGREGS)
@@ -689,7 +687,7 @@
tmpregs[nextArgReg] = iselIntExpr_R(env, args[i]);
nextArgReg++;
}
- else if (arg->tag == Iex_BBPTR) {
+ else if (arg->tag == Iex_GSPTR) {
vassert(0); //ATC
tmpregs[nextArgReg] = hregARM64_X21();
nextArgReg++;
@@ -733,8 +731,8 @@
/* Do final checks, set the return values, and generate the call
instruction proper. */
- vassert(nBBPTRs == 0 || nBBPTRs == 1);
- vassert(nVECRETs == (retTy == Ity_V128 || retTy == Ity_V256) ? 1 : 0);
+ vassert(nGSPTRs == 0 || nGSPTRs == 1);
+ vassert(nVECRETs == ((retTy == Ity_V128 || retTy == Ity_V256) ? 1 : 0));
vassert(*stackAdjustAfterCall == 0);
vassert(is_RetLoc_INVALID(*retloc));
switch (retTy) {
@@ -1383,12 +1381,13 @@
|| e->Iex.Binop.op == Iop_CmpLT64S
|| e->Iex.Binop.op == Iop_CmpLT64U
|| e->Iex.Binop.op == Iop_CmpLE64S
- || e->Iex.Binop.op == Iop_CmpLE64U)) {
+ || e->Iex.Binop.op == Iop_CmpLE64U
+ || e->Iex.Binop.op == Iop_CasCmpEQ64)) {
HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
ARM64RIA* argR = iselIntExpr_RIA(env, e->Iex.Binop.arg2);
addInstr(env, ARM64Instr_Cmp(argL, argR, True/*is64*/));
switch (e->Iex.Binop.op) {
- case Iop_CmpEQ64: return ARM64cc_EQ;
+ case Iop_CmpEQ64: case Iop_CasCmpEQ64: return ARM64cc_EQ;
case Iop_CmpNE64: return ARM64cc_NE;
case Iop_CmpLT64S: return ARM64cc_LT;
case Iop_CmpLT64U: return ARM64cc_CC;
@@ -1405,12 +1404,13 @@
|| e->Iex.Binop.op == Iop_CmpLT32S
|| e->Iex.Binop.op == Iop_CmpLT32U
|| e->Iex.Binop.op == Iop_CmpLE32S
- || e->Iex.Binop.op == Iop_CmpLE32U)) {
+ || e->Iex.Binop.op == Iop_CmpLE32U
+ || e->Iex.Binop.op == Iop_CasCmpEQ32)) {
HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
ARM64RIA* argR = iselIntExpr_RIA(env, e->Iex.Binop.arg2);
addInstr(env, ARM64Instr_Cmp(argL, argR, False/*!is64*/));
switch (e->Iex.Binop.op) {
- case Iop_CmpEQ32: return ARM64cc_EQ;
+ case Iop_CmpEQ32: case Iop_CasCmpEQ32: return ARM64cc_EQ;
case Iop_CmpNE32: return ARM64cc_NE;
case Iop_CmpLT32S: return ARM64cc_LT;
case Iop_CmpLT32U: return ARM64cc_CC;
@@ -1420,6 +1420,34 @@
}
}
+ /* --- Cmp*16*(x,y) --- */
+ if (e->tag == Iex_Binop
+ && (e->Iex.Binop.op == Iop_CasCmpEQ16)) {
+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
+ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
+ HReg argL2 = widen_z_16_to_64(env, argL);
+ HReg argR2 = widen_z_16_to_64(env, argR);
+ addInstr(env, ARM64Instr_Cmp(argL2, ARM64RIA_R(argR2), True/*is64*/));
+ switch (e->Iex.Binop.op) {
+ case Iop_CasCmpEQ16: return ARM64cc_EQ;
+ default: vpanic("iselCondCode(arm64): CmpXX16");
+ }
+ }
+
+ /* --- Cmp*8*(x,y) --- */
+ if (e->tag == Iex_Binop
+ && (e->Iex.Binop.op == Iop_CasCmpEQ8)) {
+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
+ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
+ HReg argL2 = widen_z_8_to_64(env, argL);
+ HReg argR2 = widen_z_8_to_64(env, argR);
+ addInstr(env, ARM64Instr_Cmp(argL2, ARM64RIA_R(argR2), True/*is64*/));
+ switch (e->Iex.Binop.op) {
+ case Iop_CasCmpEQ8: return ARM64cc_EQ;
+ default: vpanic("iselCondCode(arm64): CmpXX8");
+ }
+ }
+
ppIRExpr(e);
vpanic("iselCondCode");
}
@@ -3833,6 +3861,57 @@
break;
}
+ /* --------- ACAS --------- */
+ case Ist_CAS: {
+ if (stmt->Ist.CAS.details->oldHi == IRTemp_INVALID) {
+ /* "normal" singleton CAS */
+ UChar sz;
+ IRCAS* cas = stmt->Ist.CAS.details;
+ IRType ty = typeOfIRExpr(env->type_env, cas->dataLo);
+ switch (ty) {
+ case Ity_I64: sz = 8; break;
+ case Ity_I32: sz = 4; break;
+ case Ity_I16: sz = 2; break;
+ case Ity_I8: sz = 1; break;
+ default: goto unhandled_cas;
+ }
+ HReg rAddr = iselIntExpr_R(env, cas->addr);
+ HReg rExpd = iselIntExpr_R(env, cas->expdLo);
+ HReg rData = iselIntExpr_R(env, cas->dataLo);
+ vassert(cas->expdHi == NULL);
+ vassert(cas->dataHi == NULL);
+ addInstr(env, ARM64Instr_MovI(hregARM64_X3(), rAddr));
+ addInstr(env, ARM64Instr_MovI(hregARM64_X5(), rExpd));
+ addInstr(env, ARM64Instr_MovI(hregARM64_X7(), rData));
+ addInstr(env, ARM64Instr_CAS(sz));
+ /* Now we have the lowest szB bytes of x1 are either equal to
+ the lowest szB bytes of x5, indicating success, or they
+ aren't, indicating failure. The IR semantics actually
+ require us to return the old value at the location,
+ regardless of success or failure, but in the case of
+ failure it's not clear how to do this, since
+ ARM64Instr_CAS can't provide that. Instead we'll just
+ return the relevant bit of x1, since that's at least
+ guaranteed to be different from the lowest bits of x5 on
+ failure. */
+ HReg rResult = hregARM64_X1();
+ switch (sz) {
+ case 8: break;
+ case 4: rResult = widen_z_32_to_64(env, rResult); break;
+ case 2: rResult = widen_z_16_to_64(env, rResult); break;
+ case 1: rResult = widen_z_8_to_64(env, rResult); break;
+ default: vassert(0);
+ }
+ // "old" in this case is interpreted somewhat liberally, per
+ // the previous comment.
+ HReg rOld = lookupIRTemp(env, cas->oldLo);
+ addInstr(env, ARM64Instr_MovI(rOld, rResult));
+ return;
+ }
+ unhandled_cas:
+ break;
+ }
+
/* --------- MEM FENCE --------- */
case Ist_MBE:
switch (stmt->Ist.MBE.event) {
diff --git a/VEX/priv/host_arm_defs.c b/VEX/priv/host_arm_defs.c
index 2b18714..a986f37 100644
--- a/VEX/priv/host_arm_defs.c
+++ b/VEX/priv/host_arm_defs.c
@@ -7,11 +7,11 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
NEON support is
- Copyright (C) 2010-2015 Samsung Electronics
+ Copyright (C) 2010-2017 Samsung Electronics
contributed by Dmitry Zhurikhin <zhur@ispras.ru>
and Kirill Batuzov <batuzovk@ispras.ru>
@@ -1365,6 +1365,27 @@
i->ARMin.VCvtID.src = src;
return i;
}
+ARMInstr* ARMInstr_VRIntR ( Bool isF64, HReg dst, HReg src )
+{
+ ARMInstr* i = LibVEX_Alloc_inline(sizeof(ARMInstr));
+ i->tag = ARMin_VRIntR;
+ i->ARMin.VRIntR.isF64 = isF64;
+ i->ARMin.VRIntR.dst = dst ;
+ i->ARMin.VRIntR.src = src;
+ return i;
+}
+ARMInstr* ARMInstr_VMinMaxNum ( Bool isF64, Bool isMax,
+ HReg dst, HReg srcL, HReg srcR )
+{
+ ARMInstr* i = LibVEX_Alloc_inline(sizeof(ARMInstr));
+ i->tag = ARMin_VMinMaxNum;
+ i->ARMin.VMinMaxNum.isF64 = isF64;
+ i->ARMin.VMinMaxNum.isMax = isMax;
+ i->ARMin.VMinMaxNum.dst = dst ;
+ i->ARMin.VMinMaxNum.srcL = srcL;
+ i->ARMin.VMinMaxNum.srcR = srcR;
+ return i;
+}
ARMInstr* ARMInstr_FPSCR ( Bool toFPSCR, HReg iReg ) {
ARMInstr* i = LibVEX_Alloc_inline(sizeof(ARMInstr));
i->tag = ARMin_FPSCR;
@@ -1873,6 +1894,25 @@
ppHRegARM(i->ARMin.VCvtID.src);
return;
}
+ case ARMin_VRIntR: {
+ const HChar* sz = i->ARMin.VRIntR.isF64 ? "f64" : "f32";
+ vex_printf("vrintr.%s.%s ", sz, sz);
+ ppHRegARM(i->ARMin.VRIntR.dst);
+ vex_printf(", ");
+ ppHRegARM(i->ARMin.VRIntR.src);
+ return;
+ }
+ case ARMin_VMinMaxNum: {
+ const HChar* sz = i->ARMin.VMinMaxNum.isF64 ? "f64" : "f32";
+ const HChar* nm = i->ARMin.VMinMaxNum.isMax ? "vmaxnm" : "vminnm";
+ vex_printf("%s.%s ", nm, sz);
+ ppHRegARM(i->ARMin.VMinMaxNum.dst);
+ vex_printf(", ");
+ ppHRegARM(i->ARMin.VMinMaxNum.srcL);
+ vex_printf(", ");
+ ppHRegARM(i->ARMin.VMinMaxNum.srcR);
+ return;
+ }
case ARMin_FPSCR:
if (i->ARMin.FPSCR.toFPSCR) {
vex_printf("fmxr fpscr, ");
@@ -2268,6 +2308,15 @@
addHRegUse(u, HRmWrite, i->ARMin.VCvtID.dst);
addHRegUse(u, HRmRead, i->ARMin.VCvtID.src);
return;
+ case ARMin_VRIntR:
+ addHRegUse(u, HRmWrite, i->ARMin.VRIntR.dst);
+ addHRegUse(u, HRmRead, i->ARMin.VRIntR.src);
+ return;
+ case ARMin_VMinMaxNum:
+ addHRegUse(u, HRmWrite, i->ARMin.VMinMaxNum.dst);
+ addHRegUse(u, HRmRead, i->ARMin.VMinMaxNum.srcL);
+ addHRegUse(u, HRmRead, i->ARMin.VMinMaxNum.srcR);
+ return;
case ARMin_FPSCR:
if (i->ARMin.FPSCR.toFPSCR)
addHRegUse(u, HRmRead, i->ARMin.FPSCR.iReg);
@@ -2483,6 +2532,18 @@
i->ARMin.VCvtID.dst = lookupHRegRemap(m, i->ARMin.VCvtID.dst);
i->ARMin.VCvtID.src = lookupHRegRemap(m, i->ARMin.VCvtID.src);
return;
+ case ARMin_VRIntR:
+ i->ARMin.VRIntR.dst = lookupHRegRemap(m, i->ARMin.VRIntR.dst);
+ i->ARMin.VRIntR.src = lookupHRegRemap(m, i->ARMin.VRIntR.src);
+ return;
+ case ARMin_VMinMaxNum:
+ i->ARMin.VMinMaxNum.dst
+ = lookupHRegRemap(m, i->ARMin.VMinMaxNum.dst);
+ i->ARMin.VMinMaxNum.srcL
+ = lookupHRegRemap(m, i->ARMin.VMinMaxNum.srcL);
+ i->ARMin.VMinMaxNum.srcR
+ = lookupHRegRemap(m, i->ARMin.VMinMaxNum.srcR);
+ return;
case ARMin_FPSCR:
i->ARMin.FPSCR.iReg = lookupHRegRemap(m, i->ARMin.FPSCR.iReg);
return;
@@ -3852,6 +3913,61 @@
/*UNREACHED*/
vassert(0);
}
+ case ARMin_VRIntR: { /* NB: ARM v8 and above only */
+ Bool isF64 = i->ARMin.VRIntR.isF64;
+ UInt rDst = (isF64 ? dregEnc : fregEnc)(i->ARMin.VRIntR.dst);
+ UInt rSrc = (isF64 ? dregEnc : fregEnc)(i->ARMin.VRIntR.src);
+ /* The encoding of registers here differs strangely for the
+ F32 and F64 cases. */
+ UInt D, Vd, M, Vm;
+ if (isF64) {
+ D = (rDst >> 4) & 1;
+ Vd = rDst & 0xF;
+ M = (rSrc >> 4) & 1;
+ Vm = rSrc & 0xF;
+ } else {
+ Vd = (rDst >> 1) & 0xF;
+ D = rDst & 1;
+ Vm = (rSrc >> 1) & 0xF;
+ M = rSrc & 1;
+ }
+ vassert(D <= 1 && Vd <= 15 && M <= 1 && Vm <= 15);
+ *p++ = XXXXXXXX(0xE, X1110, X1011 | (D << 2), X0110, Vd,
+ isF64 ? X1011 : X1010, X0100 | (M << 1), Vm);
+ goto done;
+ }
+ case ARMin_VMinMaxNum: {
+ Bool isF64 = i->ARMin.VMinMaxNum.isF64;
+ Bool isMax = i->ARMin.VMinMaxNum.isMax;
+ UInt rDst = (isF64 ? dregEnc : fregEnc)(i->ARMin.VMinMaxNum.dst);
+ UInt rSrcL = (isF64 ? dregEnc : fregEnc)(i->ARMin.VMinMaxNum.srcL);
+ UInt rSrcR = (isF64 ? dregEnc : fregEnc)(i->ARMin.VMinMaxNum.srcR);
+ /* The encoding of registers here differs strangely for the
+ F32 and F64 cases. */
+ UInt D, Vd, N, Vn, M, Vm;
+ if (isF64) {
+ D = (rDst >> 4) & 1;
+ Vd = rDst & 0xF;
+ N = (rSrcL >> 4) & 1;
+ Vn = rSrcL & 0xF;
+ M = (rSrcR >> 4) & 1;
+ Vm = rSrcR & 0xF;
+ } else {
+ Vd = (rDst >> 1) & 0xF;
+ D = rDst & 1;
+ Vn = (rSrcL >> 1) & 0xF;
+ N = rSrcL & 1;
+ Vm = (rSrcR >> 1) & 0xF;
+ M = rSrcR & 1;
+ }
+ vassert(D <= 1 && Vd <= 15 && M <= 1 && Vm <= 15 && N <= 1
+ && Vn <= 15);
+ *p++ = XXXXXXXX(X1111,X1110, X1000 | (D << 2), Vn, Vd,
+ X1010 | (isF64 ? 1 : 0),
+ (N << 3) | ((isMax ? 0 : 1) << 2) | (M << 1) | 0,
+ Vm);
+ goto done;
+ }
case ARMin_FPSCR: {
Bool toFPSCR = i->ARMin.FPSCR.toFPSCR;
UInt iReg = iregEnc(i->ARMin.FPSCR.iReg);
diff --git a/VEX/priv/host_arm_defs.h b/VEX/priv/host_arm_defs.h
index cd20512..e8a2eb7 100644
--- a/VEX/priv/host_arm_defs.h
+++ b/VEX/priv/host_arm_defs.h
@@ -6,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -595,6 +595,8 @@
ARMin_VXferD,
ARMin_VXferS,
ARMin_VCvtID,
+ ARMin_VRIntR,
+ ARMin_VMinMaxNum,
ARMin_FPSCR,
ARMin_MFence,
ARMin_CLREX,
@@ -853,6 +855,22 @@
HReg dst;
HReg src;
} VCvtID;
+ /* Round a F32 or F64 value to the nearest integral value,
+ according to the FPSCR.RM. For ARM >= V8 hosts only. */
+ struct {
+ Bool isF64;
+ HReg dst;
+ HReg src;
+ } VRIntR;
+ /* Do Min/Max of F32 or F64 values, propagating the numerical arg
+ if the other is a qNaN. For ARM >= V8 hosts only. */
+ struct {
+ Bool isF64;
+ Bool isMax;
+ HReg dst;
+ HReg srcL;
+ HReg srcR;
+ } VMinMaxNum;
/* Move a 32-bit value to/from the FPSCR (FMXR, FMRX) */
struct {
Bool toFPSCR;
@@ -1007,6 +1025,9 @@
extern ARMInstr* ARMInstr_VXferS ( Bool toS, HReg fD, HReg rLo );
extern ARMInstr* ARMInstr_VCvtID ( Bool iToD, Bool syned,
HReg dst, HReg src );
+extern ARMInstr* ARMInstr_VRIntR ( Bool isF64, HReg dst, HReg src );
+extern ARMInstr* ARMInstr_VMinMaxNum ( Bool isF64, Bool isMax,
+ HReg dst, HReg srcL, HReg srcR );
extern ARMInstr* ARMInstr_FPSCR ( Bool toFPSCR, HReg iReg );
extern ARMInstr* ARMInstr_MFence ( void );
extern ARMInstr* ARMInstr_CLREX ( void );
diff --git a/VEX/priv/host_arm_isel.c b/VEX/priv/host_arm_isel.c
index 426f85d..3db44f4 100644
--- a/VEX/priv/host_arm_isel.c
+++ b/VEX/priv/host_arm_isel.c
@@ -7,11 +7,11 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
NEON support is
- Copyright (C) 2010-2015 Samsung Electronics
+ Copyright (C) 2010-2017 Samsung Electronics
contributed by Dmitry Zhurikhin <zhur@ispras.ru>
and Kirill Batuzov <batuzovk@ispras.ru>
@@ -233,9 +233,9 @@
static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e );
static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo,
- ISelEnv* env, IRExpr* e );
+ ISelEnv* env, const IRExpr* e );
static void iselInt64Expr ( HReg* rHi, HReg* rLo,
- ISelEnv* env, IRExpr* e );
+ ISelEnv* env, const IRExpr* e );
static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e );
static HReg iselDblExpr ( ISelEnv* env, IRExpr* e );
@@ -243,11 +243,11 @@
static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e );
static HReg iselFltExpr ( ISelEnv* env, IRExpr* e );
-static HReg iselNeon64Expr_wrk ( ISelEnv* env, IRExpr* e );
-static HReg iselNeon64Expr ( ISelEnv* env, IRExpr* e );
+static HReg iselNeon64Expr_wrk ( ISelEnv* env, const IRExpr* e );
+static HReg iselNeon64Expr ( ISelEnv* env, const IRExpr* e );
-static HReg iselNeonExpr_wrk ( ISelEnv* env, IRExpr* e );
-static HReg iselNeonExpr ( ISelEnv* env, IRExpr* e );
+static HReg iselNeonExpr_wrk ( ISelEnv* env, const IRExpr* e );
+static HReg iselNeonExpr ( ISelEnv* env, const IRExpr* e );
/*---------------------------------------------------------*/
/*--- ISEL: Misc helpers ---*/
@@ -353,7 +353,7 @@
static
Bool mightRequireFixedRegs ( IRExpr* e )
{
- if (UNLIKELY(is_IRExpr_VECRET_or_BBPTR(e))) {
+ if (UNLIKELY(is_IRExpr_VECRET_or_GSPTR(e))) {
// These are always "safe" -- either a copy of r13(sp) in some
// arbitrary vreg, or a copy of r8, respectively.
return False;
@@ -387,7 +387,7 @@
UInt n_real_args = 0;
for (i = 1; args[i]; i++) {
IRExpr* arg = args[i];
- if (UNLIKELY(is_IRExpr_VECRET_or_BBPTR(arg)))
+ if (UNLIKELY(is_IRExpr_VECRET_or_GSPTR(arg)))
goto no_match;
IRType argTy = typeOfIRExpr(env->type_env, arg);
if (UNLIKELY(argTy != Ity_I32))
@@ -525,9 +525,9 @@
*retloc = mk_RetLoc_INVALID();
/* These are used for cross-checking that IR-level constraints on
- the use of IRExpr_VECRET() and IRExpr_BBPTR() are observed. */
+ the use of IRExpr_VECRET() and IRExpr_GSPTR() are observed. */
UInt nVECRETs = 0;
- UInt nBBPTRs = 0;
+ UInt nGSPTRs = 0;
/* Marshal args for a call and do the call.
@@ -545,7 +545,7 @@
preallocate the return space before marshalling any arguments,
in this case.
- |args| may also contain IRExpr_BBPTR(), in which case the
+ |args| may also contain IRExpr_GSPTR(), in which case the
value in r8 is passed as the corresponding argument.
Generating code which is both efficient and correct when
@@ -592,8 +592,8 @@
IRExpr* arg = args[i];
if (UNLIKELY(arg->tag == Iex_VECRET)) {
nVECRETs++;
- } else if (UNLIKELY(arg->tag == Iex_BBPTR)) {
- nBBPTRs++;
+ } else if (UNLIKELY(arg->tag == Iex_GSPTR)) {
+ nGSPTRs++;
}
n_args++;
}
@@ -665,7 +665,7 @@
IRExpr* arg = args[i];
IRType aTy = Ity_INVALID;
- if (LIKELY(!is_IRExpr_VECRET_or_BBPTR(arg)))
+ if (LIKELY(!is_IRExpr_VECRET_or_GSPTR(arg)))
aTy = typeOfIRExpr(env->type_env, arg);
if (nextArgReg >= ARM_N_ARGREGS)
@@ -696,7 +696,7 @@
addInstr(env, mk_iMOVds_RR( argregs[nextArgReg], raHi ));
nextArgReg++;
}
- else if (arg->tag == Iex_BBPTR) {
+ else if (arg->tag == Iex_GSPTR) {
vassert(0); //ATC
addInstr(env, mk_iMOVds_RR( argregs[nextArgReg],
hregARM_R8() ));
@@ -722,7 +722,7 @@
IRExpr* arg = args[i];
IRType aTy = Ity_INVALID;
- if (LIKELY(!is_IRExpr_VECRET_or_BBPTR(arg)))
+ if (LIKELY(!is_IRExpr_VECRET_or_GSPTR(arg)))
aTy = typeOfIRExpr(env->type_env, arg);
if (nextArgReg >= ARM_N_ARGREGS)
@@ -745,7 +745,7 @@
tmpregs[nextArgReg] = raHi;
nextArgReg++;
}
- else if (arg->tag == Iex_BBPTR) {
+ else if (arg->tag == Iex_GSPTR) {
vassert(0); //ATC
tmpregs[nextArgReg] = hregARM_R8();
nextArgReg++;
@@ -791,8 +791,8 @@
/* Do final checks, set the return values, and generate the call
instruction proper. */
- vassert(nBBPTRs == 0 || nBBPTRs == 1);
- vassert(nVECRETs == (retTy == Ity_V128 || retTy == Ity_V256) ? 1 : 0);
+ vassert(nGSPTRs == 0 || nGSPTRs == 1);
+ vassert(nVECRETs == ((retTy == Ity_V128 || retTy == Ity_V256) ? 1 : 0));
vassert(*stackAdjustAfterCall == 0);
vassert(is_RetLoc_INVALID(*retloc));
switch (retTy) {
@@ -1655,7 +1655,7 @@
//zz DEFINE_PATTERN(p_32to1_then_1Uto8,
//zz unop(Iop_1Uto8,unop(Iop_32to1,bind(0))));
//zz if (matchIRExpr(&mi,p_32to1_then_1Uto8,e)) {
-//zz IRExpr* expr32 = mi.bindee[0];
+//zz const IRExpr* expr32 = mi.bindee[0];
//zz HReg dst = newVRegI(env);
//zz HReg src = iselIntExpr_R(env, expr32);
//zz addInstr(env, mk_iMOVsd_RR(src,dst) );
@@ -2053,7 +2053,8 @@
either real or virtual regs; in any case they must not be changed
by subsequent code emitted by the caller. */
-static void iselInt64Expr ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e )
+static void iselInt64Expr ( HReg* rHi, HReg* rLo, ISelEnv* env,
+ const IRExpr* e )
{
iselInt64Expr_wrk(rHi, rLo, env, e);
# if 0
@@ -2066,7 +2067,8 @@
}
/* DO NOT CALL THIS DIRECTLY ! */
-static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e )
+static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env,
+ const IRExpr* e )
{
vassert(e);
vassert(typeOfIRExpr(env->type_env,e) == Ity_I64);
@@ -2317,7 +2319,7 @@
/*--- ISEL: Vector (NEON) expressions (64 or 128 bit) ---*/
/*---------------------------------------------------------*/
-static HReg iselNeon64Expr ( ISelEnv* env, IRExpr* e )
+static HReg iselNeon64Expr ( ISelEnv* env, const IRExpr* e )
{
HReg r;
vassert(env->hwcaps & VEX_HWCAPS_ARM_NEON);
@@ -2328,7 +2330,7 @@
}
/* DO NOT CALL THIS DIRECTLY */
-static HReg iselNeon64Expr_wrk ( ISelEnv* env, IRExpr* e )
+static HReg iselNeon64Expr_wrk ( ISelEnv* env, const IRExpr* e )
{
IRType ty = typeOfIRExpr(env->type_env, e);
MatchInfo mi;
@@ -3938,7 +3940,7 @@
}
-static HReg iselNeonExpr ( ISelEnv* env, IRExpr* e )
+static HReg iselNeonExpr ( ISelEnv* env, const IRExpr* e )
{
HReg r;
vassert(env->hwcaps & VEX_HWCAPS_ARM_NEON);
@@ -3949,7 +3951,7 @@
}
/* DO NOT CALL THIS DIRECTLY */
-static HReg iselNeonExpr_wrk ( ISelEnv* env, IRExpr* e )
+static HReg iselNeonExpr_wrk ( ISelEnv* env, const IRExpr* e )
{
IRType ty = typeOfIRExpr(env->type_env, e);
MatchInfo mi;
@@ -5601,6 +5603,36 @@
addInstr(env, ARMInstr_VUnaryD(ARMvfpu_SQRT, dst, src));
return dst;
}
+ case Iop_RoundF64toInt: {
+ /* We can only generate this on a >= V8 capable target. But
+ that's OK since we should only be asked to generate for V8
+ capable guests, and we assume here that host == guest. */
+ if (VEX_ARM_ARCHLEVEL(env->hwcaps) >= 8) {
+ HReg src = iselDblExpr(env, e->Iex.Binop.arg2);
+ HReg dst = newVRegD(env);
+ set_VFP_rounding_mode(env, e->Iex.Binop.arg1);
+ addInstr(env, ARMInstr_VRIntR(True/*isF64*/, dst, src));
+ set_VFP_rounding_default(env);
+ return dst;
+ }
+ /* not a V8 target, so we can't select insns for this. */
+ break;
+ }
+ case Iop_MaxNumF64:
+ case Iop_MinNumF64: {
+ /* Same comments regarding V8 support as for Iop_RoundF64toInt. */
+ if (VEX_ARM_ARCHLEVEL(env->hwcaps) >= 8) {
+ HReg srcL = iselDblExpr(env, e->Iex.Binop.arg1);
+ HReg srcR = iselDblExpr(env, e->Iex.Binop.arg2);
+ HReg dst = newVRegD(env);
+ Bool isMax = e->Iex.Binop.op == Iop_MaxNumF64;
+ addInstr(env, ARMInstr_VMinMaxNum(
+ True/*isF64*/, isMax, dst, srcL, srcR));
+ return dst;
+ }
+ /* not a V8 target, so we can't select insns for this. */
+ break;
+ }
default:
break;
}
@@ -5743,6 +5775,36 @@
set_VFP_rounding_default(env);
return valS;
}
+ case Iop_RoundF32toInt: {
+ /* We can only generate this on a >= V8 capable target. But
+ that's OK since we should only be asked to generate for V8
+ capable guests, and we assume here that host == guest. */
+ if (VEX_ARM_ARCHLEVEL(env->hwcaps) >= 8) {
+ HReg src = iselFltExpr(env, e->Iex.Binop.arg2);
+ HReg dst = newVRegF(env);
+ set_VFP_rounding_mode(env, e->Iex.Binop.arg1);
+ addInstr(env, ARMInstr_VRIntR(False/*!isF64*/, dst, src));
+ set_VFP_rounding_default(env);
+ return dst;
+ }
+ /* not a V8 target, so we can't select insns for this. */
+ break;
+ }
+ case Iop_MaxNumF32:
+ case Iop_MinNumF32: {
+ /* Same comments regarding V8 support as for Iop_RoundF32toInt. */
+ if (VEX_ARM_ARCHLEVEL(env->hwcaps) >= 8) {
+ HReg srcL = iselFltExpr(env, e->Iex.Binop.arg1);
+ HReg srcR = iselFltExpr(env, e->Iex.Binop.arg2);
+ HReg dst = newVRegF(env);
+ Bool isMax = e->Iex.Binop.op == Iop_MaxNumF32;
+ addInstr(env, ARMInstr_VMinMaxNum(
+ False/*!isF64*/, isMax, dst, srcL, srcR));
+ return dst;
+ }
+ /* not a V8 target, so we can't select insns for this. */
+ break;
+ }
default:
break;
}
diff --git a/VEX/priv/host_generic_maddf.c b/VEX/priv/host_generic_maddf.c
index fe44974..7855068 100644
--- a/VEX/priv/host_generic_maddf.c
+++ b/VEX/priv/host_generic_maddf.c
@@ -5,7 +5,7 @@
/*
Compute x * y + z as ternary operation.
- Copyright (C) 2010-2015 Free Software Foundation, Inc.
+ Copyright (C) 2010-2017 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Jakub Jelinek <jakub@redhat.com>, 2010.
diff --git a/VEX/priv/host_generic_maddf.h b/VEX/priv/host_generic_maddf.h
index 7282d97..9fc0d1c 100644
--- a/VEX/priv/host_generic_maddf.h
+++ b/VEX/priv/host_generic_maddf.h
@@ -5,7 +5,7 @@
/*
Compute x * y + z as ternary operation.
- Copyright (C) 2010-2015 Free Software Foundation, Inc.
+ Copyright (C) 2010-2017 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Jakub Jelinek <jakub@redhat.com>, 2010.
diff --git a/VEX/priv/host_generic_reg_alloc2.c b/VEX/priv/host_generic_reg_alloc2.c
index 3c0b8db..ada2396 100644
--- a/VEX/priv/host_generic_reg_alloc2.c
+++ b/VEX/priv/host_generic_reg_alloc2.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/VEX/priv/host_generic_regs.c b/VEX/priv/host_generic_regs.c
index 33fc7a3..8710b2b 100644
--- a/VEX/priv/host_generic_regs.c
+++ b/VEX/priv/host_generic_regs.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/VEX/priv/host_generic_regs.h b/VEX/priv/host_generic_regs.h
index 5c4804e..670114d 100644
--- a/VEX/priv/host_generic_regs.h
+++ b/VEX/priv/host_generic_regs.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/VEX/priv/host_generic_simd128.c b/VEX/priv/host_generic_simd128.c
index 77a3183..62cb88e 100644
--- a/VEX/priv/host_generic_simd128.c
+++ b/VEX/priv/host_generic_simd128.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 OpenWorks GbR
+ Copyright (C) 2010-2017 OpenWorks GbR
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/VEX/priv/host_generic_simd128.h b/VEX/priv/host_generic_simd128.h
index c547666..0b63ab3 100644
--- a/VEX/priv/host_generic_simd128.h
+++ b/VEX/priv/host_generic_simd128.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 OpenWorks GbR
+ Copyright (C) 2010-2017 OpenWorks GbR
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/VEX/priv/host_generic_simd256.c b/VEX/priv/host_generic_simd256.c
index 045ee8d..6bfdf7b 100644
--- a/VEX/priv/host_generic_simd256.c
+++ b/VEX/priv/host_generic_simd256.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2012-2015 OpenWorks GbR
+ Copyright (C) 2012-2017 OpenWorks GbR
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/VEX/priv/host_generic_simd256.h b/VEX/priv/host_generic_simd256.h
index ffb55f4..12a16bb 100644
--- a/VEX/priv/host_generic_simd256.h
+++ b/VEX/priv/host_generic_simd256.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2012-2015 OpenWorks GbR
+ Copyright (C) 2012-2017 OpenWorks GbR
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/VEX/priv/host_generic_simd64.c b/VEX/priv/host_generic_simd64.c
index be70f5d..48a55bd 100644
--- a/VEX/priv/host_generic_simd64.c
+++ b/VEX/priv/host_generic_simd64.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/VEX/priv/host_generic_simd64.h b/VEX/priv/host_generic_simd64.h
index c01e3c9..a0f1ed8 100644
--- a/VEX/priv/host_generic_simd64.h
+++ b/VEX/priv/host_generic_simd64.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/VEX/priv/host_mips_defs.c b/VEX/priv/host_mips_defs.c
index 7d73ecc..d6a3219 100644
--- a/VEX/priv/host_mips_defs.c
+++ b/VEX/priv/host_mips_defs.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 RT-RK
+ Copyright (C) 2010-2017 RT-RK
mips-valgrind@rt-rk.com
This program is free software; you can redistribute it and/or
@@ -36,9 +36,6 @@
#include "host_generic_regs.h"
#include "host_mips_defs.h"
-/* guest_COND offset. */
-#define COND_OFFSET(__mode64) (__mode64 ? 612 : 448)
-
/* Register number for guest state pointer in host code. */
#define GuestSP 23
@@ -1514,7 +1511,7 @@
return;
}
case Min_MfFCSR: {
- vex_printf("ctc1 ");
+ vex_printf("cfc1 ");
ppHRegMIPS(i->Min.MfFCSR.dst, mode64);
vex_printf(", $31");
return;
diff --git a/VEX/priv/host_mips_defs.h b/VEX/priv/host_mips_defs.h
index 8504498..481a487 100644
--- a/VEX/priv/host_mips_defs.h
+++ b/VEX/priv/host_mips_defs.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 RT-RK
+ Copyright (C) 2010-2017 RT-RK
mips-valgrind@rt-rk.com
This program is free software; you can redistribute it and/or
@@ -123,6 +123,9 @@
#define StackFramePointer(_mode64) hregMIPS_GPR30(_mode64)
#define StackPointer(_mode64) hregMIPS_GPR29(_mode64)
+/* guest_COND offset */
+#define COND_OFFSET(_mode64) ((_mode64) ? 588 : 448)
+
/* Num registers used for function calls */
#if defined(VGP_mips32_linux)
/* a0, a1, a2, a3 */
diff --git a/VEX/priv/host_mips_isel.c b/VEX/priv/host_mips_isel.c
index 848234a..0c51c07 100644
--- a/VEX/priv/host_mips_isel.c
+++ b/VEX/priv/host_mips_isel.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 RT-RK
+ Copyright (C) 2010-2017 RT-RK
mips-valgrind@rt-rk.com
This program is free software; you can redistribute it and/or
@@ -61,9 +61,6 @@
/* FPR register class for mips32/64 */
#define HRcFPR(_mode64) ((_mode64) ? HRcFlt64 : HRcFlt32)
-/* guest_COND offset */
-#define COND_OFFSET(_mode64) ((_mode64) ? 612 : 448)
-
/*---------------------------------------------------------*/
/*--- ISelEnv ---*/
/*---------------------------------------------------------*/
@@ -132,14 +129,12 @@
static HReg lookupIRTemp(ISelEnv * env, IRTemp tmp)
{
- vassert(tmp >= 0);
vassert(tmp < env->n_vregmap);
return env->vregmap[tmp];
}
static void lookupIRTemp64(HReg * vrHI, HReg * vrLO, ISelEnv * env, IRTemp tmp)
{
- vassert(tmp >= 0);
vassert(tmp < env->n_vregmap);
vassert(! hregIsInvalid(env->vregmapHI[tmp]));
*vrLO = env->vregmap[tmp];
@@ -150,7 +145,6 @@
lookupIRTempPair(HReg * vrHI, HReg * vrLO, ISelEnv * env, IRTemp tmp)
{
vassert(env->mode64);
- vassert(tmp >= 0);
vassert(tmp < env->n_vregmap);
vassert(! hregIsInvalid(env->vregmapHI[tmp]));
*vrLO = env->vregmap[tmp];
@@ -290,7 +284,7 @@
addInstr(env, MIPSInstr_Shft(Mshft_SLL, True, tmp, irrm,
MIPSRH_Imm(False, 1)));
addInstr(env, MIPSInstr_Alu(Malu_XOR, tmp, irrm, MIPSRH_Reg(tmp)));
- addInstr(env, MIPSInstr_Alu(Malu_AND, irrm, tmp, MIPSRH_Imm(False, 3)));
+ addInstr(env, MIPSInstr_Alu(Malu_AND, tmp, tmp, MIPSRH_Imm(False, 3)));
/* save old value of FCSR */
addInstr(env, MIPSInstr_MfFCSR(fcsr_old));
sub_from_sp(env, 8); /* Move SP down 8 bytes */
@@ -300,7 +294,7 @@
addInstr(env, MIPSInstr_Store(4, am_addr, fcsr_old, mode64));
/* set new value of FCSR */
- addInstr(env, MIPSInstr_MtFCSR(irrm));
+ addInstr(env, MIPSInstr_MtFCSR(tmp));
}
static void set_MIPS_rounding_default(ISelEnv * env)
@@ -398,8 +392,8 @@
IRCallee* cee, IRType retTy, IRExpr** args )
{
MIPSCondCode cc;
- HReg argregs[MIPS_N_REGPARMS];
- HReg tmpregs[MIPS_N_REGPARMS];
+ HReg argregs[8];
+ HReg tmpregs[8];
Bool go_fast;
Int n_args, i, argreg;
UInt argiregs;
@@ -410,9 +404,9 @@
*retloc = mk_RetLoc_INVALID();
/* These are used for cross-checking that IR-level constraints on
- the use of IRExpr_VECRET() and IRExpr_BBPTR() are observed. */
+ the use of IRExpr_VECRET() and IRExpr_GSPTR() are observed. */
UInt nVECRETs = 0;
- UInt nBBPTRs = 0;
+ UInt nGSPTRs = 0;
/* MIPS O32 calling convention: up to four registers ($a0 ... $a3)
are allowed to be used for passing integer arguments. They correspond
@@ -434,7 +428,7 @@
stack, it is enough to preallocate the return space before
marshalling any arguments, in this case.
- |args| may also contain IRExpr_BBPTR(), in which case the value
+ |args| may also contain IRExpr_GSPTR(), in which case the value
in the guest state pointer register is passed as the
corresponding argument. */
@@ -443,8 +437,8 @@
IRExpr* arg = args[i];
if (UNLIKELY(arg->tag == Iex_VECRET)) {
nVECRETs++;
- } else if (UNLIKELY(arg->tag == Iex_BBPTR)) {
- nBBPTRs++;
+ } else if (UNLIKELY(arg->tag == Iex_GSPTR)) {
+ nGSPTRs++;
}
n_args++;
}
@@ -515,7 +509,7 @@
vassert(argreg < MIPS_N_REGPARMS);
IRType aTy = Ity_INVALID;
- if (LIKELY(!is_IRExpr_VECRET_or_BBPTR(arg)))
+ if (LIKELY(!is_IRExpr_VECRET_or_GSPTR(arg)))
aTy = typeOfIRExpr(env->type_env, arg);
if (aTy == Ity_I32 || mode64) {
@@ -535,7 +529,7 @@
argiregs |= (1 << (argreg + 4));
addInstr(env, mk_iMOVds_RR( argregs[argreg], rLo));
argreg++;
- } else if (arg->tag == Iex_BBPTR) {
+ } else if (arg->tag == Iex_GSPTR) {
vassert(0); // ATC
addInstr(env, mk_iMOVds_RR(argregs[argreg],
GuestStatePointer(mode64)));
@@ -556,10 +550,10 @@
IRExpr* arg = args[i];
IRType aTy = Ity_INVALID;
- if (LIKELY(!is_IRExpr_VECRET_or_BBPTR(arg)))
+ if (LIKELY(!is_IRExpr_VECRET_or_GSPTR(arg)))
aTy = typeOfIRExpr(env->type_env, arg);
- if (aTy == Ity_I32 || (mode64 && arg->tag != Iex_BBPTR)) {
+ if (aTy == Ity_I32 || (mode64 && arg->tag != Iex_GSPTR)) {
tmpregs[argreg] = iselWordExpr_R(env, arg);
argreg++;
} else if (aTy == Ity_I64) { /* Ity_I64 */
@@ -573,7 +567,7 @@
argreg++;
tmpregs[argreg] = raHi;
argreg++;
- } else if (arg->tag == Iex_BBPTR) {
+ } else if (arg->tag == Iex_GSPTR) {
tmpregs[argreg] = GuestStatePointer(mode64);
argreg++;
}
@@ -610,8 +604,8 @@
/* Do final checks, set the return values, and generate the call
instruction proper. */
- vassert(nBBPTRs == 0 || nBBPTRs == 1);
- vassert(nVECRETs == (retTy == Ity_V128 || retTy == Ity_V256) ? 1 : 0);
+ vassert(nGSPTRs == 0 || nGSPTRs == 1);
+ vassert(nVECRETs == ((retTy == Ity_V128 || retTy == Ity_V256) ? 1 : 0));
vassert(*stackAdjustAfterCall == 0);
vassert(is_RetLoc_INVALID(*retloc));
switch (retTy) {
@@ -1003,7 +997,7 @@
break;
case Iop_CmpNE64:
cc = MIPScc_NE;
- size32 = True;
+ size32 = False;
break;
case Iop_CmpLT32S:
cc = MIPScc_LT;
@@ -2083,7 +2077,7 @@
break;
case Iop_CmpNE64:
cc = MIPScc_NE;
- size32 = True;
+ size32 = False;
break;
case Iop_CmpLT32S:
cc = MIPScc_LT;
@@ -2951,6 +2945,19 @@
return;
}
+ case Iop_Not64: {
+ HReg tLo = newVRegI(env);
+ HReg tHi = newVRegI(env);
+ iselInt64Expr(&tHi, &tLo, env, e->Iex.Unop.arg);
+ addInstr(env, MIPSInstr_Alu(Malu_NOR, tLo, tLo, MIPSRH_Reg(tLo)));
+ addInstr(env, MIPSInstr_Alu(Malu_NOR, tHi, tHi, MIPSRH_Reg(tHi)));
+
+ *rHi = tHi;
+ *rLo = tLo;
+
+ return;
+ }
+
default:
vex_printf("UNARY: No such op: ");
ppIROp(e->Iex.Unop.op);
@@ -3391,18 +3398,17 @@
/* --------- ITE --------- */
if (e->tag == Iex_ITE) {
- if (ty == Ity_F64
- && typeOfIRExpr(env->type_env, e->Iex.ITE.cond) == Ity_I1) {
- vassert(mode64);
- HReg r0 = iselFltExpr(env, e->Iex.ITE.iffalse);
- HReg r1 = iselFltExpr(env, e->Iex.ITE.iftrue);
- HReg r_cond = iselWordExpr_R(env, e->Iex.ITE.cond);
- HReg r_dst = newVRegF(env);
- addInstr(env, MIPSInstr_FpUnary(Mfp_MOVD, r_dst, r0));
- addInstr(env, MIPSInstr_MoveCond(MFpMoveCond_movnd, r_dst, r1,
- r_cond));
- return r_dst;
- }
+ vassert(typeOfIRExpr(env->type_env, e->Iex.ITE.cond) == Ity_I1);
+ HReg r0 = iselFltExpr(env, e->Iex.ITE.iffalse);
+ HReg r1 = iselFltExpr(env, e->Iex.ITE.iftrue);
+ HReg r_cond = iselWordExpr_R(env, e->Iex.ITE.cond);
+ HReg r_dst = newVRegF(env);
+ addInstr(env, MIPSInstr_FpUnary((ty == Ity_F64) ? Mfp_MOVD : Mfp_MOVS,
+ r_dst, r0));
+ addInstr(env, MIPSInstr_MoveCond((ty == Ity_F64) ? MFpMoveCond_movnd :
+ MFpMoveCond_movns,
+ r_dst, r1, r_cond));
+ return r_dst;
}
vex_printf("iselFltExpr(mips): No such tag(0x%x)\n", e->tag);
@@ -3846,7 +3852,9 @@
/* The returned value is in $v0. Park it in the register
associated with tmp. */
HReg r_dst = lookupIRTemp(env, d->tmp);
- addInstr(env, mk_iMOVds_RR(r_dst, hregMIPS_GPR2(mode64)));
+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, True, r_dst,
+ hregMIPS_GPR2(mode64),
+ MIPSRH_Imm(False, 0)));
vassert(rloc.pri == RLPri_Int);
vassert(addToSp == 0);
return;
diff --git a/VEX/priv/host_ppc_defs.c b/VEX/priv/host_ppc_defs.c
index dc70f24..6f7c009 100644
--- a/VEX/priv/host_ppc_defs.c
+++ b/VEX/priv/host_ppc_defs.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/VEX/priv/host_ppc_defs.h b/VEX/priv/host_ppc_defs.h
index 59a016b..62c15ae 100644
--- a/VEX/priv/host_ppc_defs.h
+++ b/VEX/priv/host_ppc_defs.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c
index d2c4cb1..6bdb5f7 100644
--- a/VEX/priv/host_ppc_isel.c
+++ b/VEX/priv/host_ppc_isel.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -379,9 +379,9 @@
*/
/* 32-bit mode: compute an I8/I16/I32 into a GPR.
64-bit mode: compute an I8/I16/I32/I64 into a GPR. */
-static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e,
+static HReg iselWordExpr_R_wrk ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
-static HReg iselWordExpr_R ( ISelEnv* env, IRExpr* e,
+static HReg iselWordExpr_R ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
/* 32-bit mode: Compute an I8/I16/I32 into a RH
@@ -394,33 +394,33 @@
return can have their sign inverted if need be.
*/
static PPCRH* iselWordExpr_RH_wrk ( ISelEnv* env,
- Bool syned, IRExpr* e,
+ Bool syned, const IRExpr* e,
IREndness IEndianess );
static PPCRH* iselWordExpr_RH ( ISelEnv* env,
- Bool syned, IRExpr* e,
+ Bool syned, const IRExpr* e,
IREndness IEndianess );
/* 32-bit mode: compute an I32 into a RI (reg or 32-bit immediate).
64-bit mode: compute an I64 into a RI (reg or 64-bit immediate). */
-static PPCRI* iselWordExpr_RI_wrk ( ISelEnv* env, IRExpr* e,
+static PPCRI* iselWordExpr_RI_wrk ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
-static PPCRI* iselWordExpr_RI ( ISelEnv* env, IRExpr* e,
+static PPCRI* iselWordExpr_RI ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
/* In 32 bit mode ONLY, compute an I8 into a
reg-or-5-bit-unsigned-immediate, the latter being an immediate in
the range 1 .. 31 inclusive. Used for doing shift amounts. */
-static PPCRH* iselWordExpr_RH5u_wrk ( ISelEnv* env, IRExpr* e,
+static PPCRH* iselWordExpr_RH5u_wrk ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
-static PPCRH* iselWordExpr_RH5u ( ISelEnv* env, IRExpr* e,
+static PPCRH* iselWordExpr_RH5u ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
/* In 64-bit mode ONLY, compute an I8 into a
reg-or-6-bit-unsigned-immediate, the latter being an immediate in
the range 1 .. 63 inclusive. Used for doing shift amounts. */
-static PPCRH* iselWordExpr_RH6u_wrk ( ISelEnv* env, IRExpr* e,
+static PPCRH* iselWordExpr_RH6u_wrk ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
-static PPCRH* iselWordExpr_RH6u ( ISelEnv* env, IRExpr* e,
+static PPCRH* iselWordExpr_RH6u ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
/* 32-bit mode: compute an I32 into an AMode.
@@ -434,77 +434,79 @@
Since there are no such restrictions on 32-bit insns, xferTy is
ignored for 32-bit code generation. */
-static PPCAMode* iselWordExpr_AMode_wrk ( ISelEnv* env, IRExpr* e,
+static PPCAMode* iselWordExpr_AMode_wrk ( ISelEnv* env, const IRExpr* e,
IRType xferTy,
IREndness IEndianess );
-static PPCAMode* iselWordExpr_AMode ( ISelEnv* env, IRExpr* e,
+static PPCAMode* iselWordExpr_AMode ( ISelEnv* env, const IRExpr* e,
IRType xferTy,
IREndness IEndianess );
static void iselInt128Expr_to_32x4_wrk ( HReg* rHi, HReg* rMedHi,
HReg* rMedLo, HReg* rLo,
- ISelEnv* env, IRExpr* e,
+ ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
static void iselInt128Expr_to_32x4 ( HReg* rHi, HReg* rMedHi,
HReg* rMedLo, HReg* rLo,
- ISelEnv* env, IRExpr* e,
+ ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
/* 32-bit mode ONLY: compute an I64 into a GPR pair. */
static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo,
- ISelEnv* env, IRExpr* e,
+ ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
static void iselInt64Expr ( HReg* rHi, HReg* rLo,
- ISelEnv* env, IRExpr* e,
+ ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
/* 64-bit mode ONLY: compute an I128 into a GPR64 pair. */
static void iselInt128Expr_wrk ( HReg* rHi, HReg* rLo,
- ISelEnv* env, IRExpr* e,
+ ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
static void iselInt128Expr ( HReg* rHi, HReg* rLo,
- ISelEnv* env, IRExpr* e,
+ ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
-static PPCCondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e,
+static PPCCondCode iselCondCode_wrk ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
-static PPCCondCode iselCondCode ( ISelEnv* env, IRExpr* e,
+static PPCCondCode iselCondCode ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
-static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e,
+static HReg iselDblExpr_wrk ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
-static HReg iselDblExpr ( ISelEnv* env, IRExpr* e,
+static HReg iselDblExpr ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
-static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e,
+static HReg iselFltExpr_wrk ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
-static HReg iselFltExpr ( ISelEnv* env, IRExpr* e,
+static HReg iselFltExpr ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
-static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e,
+static HReg iselVecExpr_wrk ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
-static HReg iselVecExpr ( ISelEnv* env, IRExpr* e,
+static HReg iselVecExpr ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
/* 64-bit mode ONLY. */
-static HReg iselDfp32Expr_wrk ( ISelEnv* env, IRExpr* e,
+static HReg iselDfp32Expr_wrk ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
-static HReg iselDfp32Expr ( ISelEnv* env, IRExpr* e,
+static HReg iselDfp32Expr ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
-static HReg iselDfp64Expr_wrk ( ISelEnv* env, IRExpr* e,
+static HReg iselDfp64Expr_wrk ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
-static HReg iselDfp64Expr ( ISelEnv* env, IRExpr* e,
+static HReg iselDfp64Expr ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess );
-static HReg iselFp128Expr_wrk ( ISelEnv* env, IRExpr* e, IREndness IEndianess);
-static HReg iselFp128Expr ( ISelEnv* env, IRExpr* e, IREndness IEndianess);
+static HReg iselFp128Expr_wrk ( ISelEnv* env, const IRExpr* e,
+ IREndness IEndianess);
+static HReg iselFp128Expr ( ISelEnv* env, const IRExpr* e,
+ IREndness IEndianess);
/* 64-bit mode ONLY: compute an D128 into a GPR64 pair. */
static void iselDfp128Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env,
- IRExpr* e, IREndness IEndianess );
+ const IRExpr* e, IREndness IEndianess );
static void iselDfp128Expr ( HReg* rHi, HReg* rLo, ISelEnv* env,
- IRExpr* e, IREndness IEndianess );
+ const IRExpr* e, IREndness IEndianess );
/*---------------------------------------------------------*/
/*--- ISEL: Misc helpers ---*/
@@ -736,9 +738,9 @@
*retloc = mk_RetLoc_INVALID();
/* These are used for cross-checking that IR-level constraints on
- the use of IRExpr_VECRET() and IRExpr_BBPTR() are observed. */
+ the use of IRExpr_VECRET() and IRExpr_GSPTR() are observed. */
UInt nVECRETs = 0;
- UInt nBBPTRs = 0;
+ UInt nGSPTRs = 0;
/* Marshal args for a call and do the call.
@@ -756,7 +758,7 @@
stack, it is enough to preallocate the return space before
marshalling any arguments, in this case.
- |args| may also contain IRExpr_BBPTR(), in which case the value
+ |args| may also contain IRExpr_GSPTR(), in which case the value
in the guest state pointer register is passed as the
corresponding argument.
@@ -852,7 +854,7 @@
if (go_fast) {
for (i = 0; i < n_args; i++) {
IRExpr* arg = args[i];
- if (UNLIKELY(arg->tag == Iex_BBPTR)) {
+ if (UNLIKELY(arg->tag == Iex_GSPTR)) {
/* that's OK */
}
else if (UNLIKELY(arg->tag == Iex_VECRET)) {
@@ -880,7 +882,7 @@
IRExpr* arg = args[i];
vassert(argreg < PPC_N_REGPARMS);
- if (arg->tag == Iex_BBPTR) {
+ if (arg->tag == Iex_GSPTR) {
argiregs |= (1 << (argreg+3));
addInstr(env, mk_iMOVds_RR( argregs[argreg],
GuestStatePtr(mode64) ));
@@ -954,11 +956,11 @@
for (i = 0; i < n_args; i++) {
IRExpr* arg = args[i];
vassert(argreg < PPC_N_REGPARMS);
- if (UNLIKELY(arg->tag == Iex_BBPTR)) {
+ if (UNLIKELY(arg->tag == Iex_GSPTR)) {
tmpregs[argreg] = newVRegI(env);
addInstr(env, mk_iMOVds_RR( tmpregs[argreg],
GuestStatePtr(mode64) ));
- nBBPTRs++;
+ nGSPTRs++;
}
else if (UNLIKELY(arg->tag == Iex_VECRET)) {
/* We stashed the address of the return slot earlier, so just
@@ -1025,7 +1027,7 @@
vassert(nVECRETs == 0);
}
- vassert(nBBPTRs == 0 || nBBPTRs == 1);
+ vassert(nGSPTRs == 0 || nGSPTRs == 1);
vassert(*stackAdjustAfterCall == 0);
vassert(is_RetLoc_INVALID(*retloc));
@@ -1396,7 +1398,8 @@
if necessary.
*/
-static HReg iselWordExpr_R ( ISelEnv* env, IRExpr* e, IREndness IEndianess )
+static HReg iselWordExpr_R ( ISelEnv* env, const IRExpr* e,
+ IREndness IEndianess )
{
HReg r = iselWordExpr_R_wrk(env, e, IEndianess);
/* sanity checks ... */
@@ -1410,7 +1413,7 @@
}
/* DO NOT CALL THIS DIRECTLY ! */
-static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e,
+static HReg iselWordExpr_R_wrk ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess )
{
Bool mode64 = env->mode64;
@@ -1871,7 +1874,7 @@
DEFINE_PATTERN(p_32to1_then_1Uto8,
unop(Iop_1Uto8,unop(Iop_32to1,bind(0))));
if (matchIRExpr(&mi,p_32to1_then_1Uto8,e)) {
- IRExpr* expr32 = mi.bindee[0];
+ const IRExpr* expr32 = mi.bindee[0];
HReg r_dst = newVRegI(env);
HReg r_src = iselWordExpr_R(env, expr32, IEndianess);
addInstr(env, PPCInstr_Alu(Palu_AND, r_dst,
@@ -2604,7 +2607,7 @@
}
static
-PPCAMode* iselWordExpr_AMode ( ISelEnv* env, IRExpr* e, IRType xferTy,
+PPCAMode* iselWordExpr_AMode ( ISelEnv* env, const IRExpr* e, IRType xferTy,
IREndness IEndianess )
{
PPCAMode* am = iselWordExpr_AMode_wrk(env, e, xferTy, IEndianess);
@@ -2613,7 +2616,7 @@
}
/* DO NOT CALL THIS DIRECTLY ! */
-static PPCAMode* iselWordExpr_AMode_wrk ( ISelEnv* env, IRExpr* e,
+static PPCAMode* iselWordExpr_AMode_wrk ( ISelEnv* env, const IRExpr* e,
IRType xferTy, IREndness IEndianess )
{
IRType ty = typeOfIRExpr(env->type_env,e);
@@ -2695,7 +2698,7 @@
signed immediates that are return can have their sign inverted if
need be. */
-static PPCRH* iselWordExpr_RH ( ISelEnv* env, Bool syned, IRExpr* e,
+static PPCRH* iselWordExpr_RH ( ISelEnv* env, Bool syned, const IRExpr* e,
IREndness IEndianess )
{
PPCRH* ri = iselWordExpr_RH_wrk(env, syned, e, IEndianess);
@@ -2716,7 +2719,7 @@
}
/* DO NOT CALL THIS DIRECTLY ! */
-static PPCRH* iselWordExpr_RH_wrk ( ISelEnv* env, Bool syned, IRExpr* e,
+static PPCRH* iselWordExpr_RH_wrk ( ISelEnv* env, Bool syned, const IRExpr* e,
IREndness IEndianess )
{
ULong u;
@@ -2760,7 +2763,8 @@
iselIntExpr_R, the expression can have type 32, 16 or 8 bits, or,
in 64-bit mode, 64 bits. */
-static PPCRI* iselWordExpr_RI ( ISelEnv* env, IRExpr* e, IREndness IEndianess )
+static PPCRI* iselWordExpr_RI ( ISelEnv* env, const IRExpr* e,
+ IREndness IEndianess )
{
PPCRI* ri = iselWordExpr_RI_wrk(env, e, IEndianess);
/* sanity checks ... */
@@ -2777,7 +2781,7 @@
}
/* DO NOT CALL THIS DIRECTLY ! */
-static PPCRI* iselWordExpr_RI_wrk ( ISelEnv* env, IRExpr* e,
+static PPCRI* iselWordExpr_RI_wrk ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess )
{
Long l;
@@ -2810,7 +2814,7 @@
being an immediate in the range 1 .. 31 inclusive. Used for doing
shift amounts. Only used in 32-bit mode. */
-static PPCRH* iselWordExpr_RH5u ( ISelEnv* env, IRExpr* e,
+static PPCRH* iselWordExpr_RH5u ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess )
{
PPCRH* ri;
@@ -2832,7 +2836,7 @@
}
/* DO NOT CALL THIS DIRECTLY ! */
-static PPCRH* iselWordExpr_RH5u_wrk ( ISelEnv* env, IRExpr* e,
+static PPCRH* iselWordExpr_RH5u_wrk ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess )
{
IRType ty = typeOfIRExpr(env->type_env,e);
@@ -2857,7 +2861,7 @@
being an immediate in the range 1 .. 63 inclusive. Used for doing
shift amounts. Only used in 64-bit mode. */
-static PPCRH* iselWordExpr_RH6u ( ISelEnv* env, IRExpr* e,
+static PPCRH* iselWordExpr_RH6u ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess )
{
PPCRH* ri;
@@ -2879,7 +2883,7 @@
}
/* DO NOT CALL THIS DIRECTLY ! */
-static PPCRH* iselWordExpr_RH6u_wrk ( ISelEnv* env, IRExpr* e,
+static PPCRH* iselWordExpr_RH6u_wrk ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess )
{
IRType ty = typeOfIRExpr(env->type_env,e);
@@ -2904,7 +2908,7 @@
condition code which would correspond when the expression would
notionally have returned 1. */
-static PPCCondCode iselCondCode ( ISelEnv* env, IRExpr* e,
+static PPCCondCode iselCondCode ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess )
{
/* Uh, there's nothing we can sanity check here, unfortunately. */
@@ -2912,7 +2916,7 @@
}
/* DO NOT CALL THIS DIRECTLY ! */
-static PPCCondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e,
+static PPCCondCode iselCondCode_wrk ( ISelEnv* env, const IRExpr* e,
IREndness IEndianess )
{
vassert(e);
@@ -3100,8 +3104,8 @@
case they must not be changed by subsequent code emitted by the
caller. */
-static void iselInt128Expr ( HReg* rHi, HReg* rLo,
- ISelEnv* env, IRExpr* e, IREndness IEndianess )
+static void iselInt128Expr ( HReg* rHi, HReg* rLo, ISelEnv* env,
+ const IRExpr* e, IREndness IEndianess )
{
vassert(env->mode64);
iselInt128Expr_wrk(rHi, rLo, env, e, IEndianess);
@@ -3115,8 +3119,8 @@
}
/* DO NOT CALL THIS DIRECTLY ! */
-static void iselInt128Expr_wrk ( HReg* rHi, HReg* rLo,
- ISelEnv* env, IRExpr* e, IREndness IEndianess )
+static void iselInt128Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env,
+ const IRExpr* e, IREndness IEndianess )
{
Bool mode64 = env->mode64;
@@ -3197,7 +3201,7 @@
/* 32-bit mode ONLY: compute a 128-bit value into a register quad */
static void iselInt128Expr_to_32x4 ( HReg* rHi, HReg* rMedHi, HReg* rMedLo,
- HReg* rLo, ISelEnv* env, IRExpr* e,
+ HReg* rLo, ISelEnv* env, const IRExpr* e,
IREndness IEndianess )
{
vassert(!env->mode64);
@@ -3217,7 +3221,7 @@
static void iselInt128Expr_to_32x4_wrk ( HReg* rHi, HReg* rMedHi,
HReg* rMedLo, HReg* rLo,
- ISelEnv* env, IRExpr* e,
+ ISelEnv* env, const IRExpr* e,
IREndness IEndianess )
{
vassert(e);
@@ -3255,7 +3259,7 @@
caller. */
static void iselInt64Expr ( HReg* rHi, HReg* rLo,
- ISelEnv* env, IRExpr* e,
+ ISelEnv* env, const IRExpr* e,
IREndness IEndianess )
{
vassert(!env->mode64);
@@ -3271,7 +3275,7 @@
/* DO NOT CALL THIS DIRECTLY ! */
static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo,
- ISelEnv* env, IRExpr* e,
+ ISelEnv* env, const IRExpr* e,
IREndness IEndianess )
{
vassert(e);
@@ -3893,7 +3897,7 @@
/* Nothing interesting here; really just wrappers for
64-bit stuff. */
-static HReg iselFltExpr ( ISelEnv* env, IRExpr* e, IREndness IEndianess )
+static HReg iselFltExpr ( ISelEnv* env, const IRExpr* e, IREndness IEndianess )
{
HReg r = iselFltExpr_wrk( env, e, IEndianess );
# if 0
@@ -3905,7 +3909,8 @@
}
/* DO NOT CALL THIS DIRECTLY */
-static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e, IREndness IEndianess )
+static HReg iselFltExpr_wrk ( ISelEnv* env, const IRExpr* e,
+ IREndness IEndianess )
{
Bool mode64 = env->mode64;
@@ -4065,7 +4070,7 @@
positive zero 0 0 .000000---0
*/
-static HReg iselDblExpr ( ISelEnv* env, IRExpr* e, IREndness IEndianess )
+static HReg iselDblExpr ( ISelEnv* env, const IRExpr* e, IREndness IEndianess )
{
HReg r = iselDblExpr_wrk( env, e, IEndianess );
# if 0
@@ -4077,7 +4082,8 @@
}
/* DO NOT CALL THIS DIRECTLY */
-static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e, IREndness IEndianess )
+static HReg iselDblExpr_wrk ( ISelEnv* env, const IRExpr* e,
+ IREndness IEndianess )
{
Bool mode64 = env->mode64;
IRType ty = typeOfIRExpr(env->type_env,e);
@@ -4431,7 +4437,7 @@
vpanic("iselDblExpr_wrk(ppc)");
}
-static HReg iselDfp32Expr(ISelEnv* env, IRExpr* e, IREndness IEndianess)
+static HReg iselDfp32Expr(ISelEnv* env, const IRExpr* e, IREndness IEndianess)
{
HReg r = iselDfp32Expr_wrk( env, e, IEndianess );
vassert(hregClass(r) == HRcFlt64);
@@ -4440,7 +4446,8 @@
}
/* DO NOT CALL THIS DIRECTLY */
-static HReg iselDfp32Expr_wrk(ISelEnv* env, IRExpr* e, IREndness IEndianess)
+static HReg iselDfp32Expr_wrk(ISelEnv* env, const IRExpr* e,
+ IREndness IEndianess)
{
Bool mode64 = env->mode64;
IRType ty = typeOfIRExpr( env->type_env, e );
@@ -4483,7 +4490,7 @@
vpanic( "iselDfp32Expr_wrk(ppc)" );
}
-static HReg iselFp128Expr( ISelEnv* env, IRExpr* e, IREndness IEndianess )
+static HReg iselFp128Expr( ISelEnv* env, const IRExpr* e, IREndness IEndianess )
{
HReg r = iselFp128Expr_wrk( env, e, IEndianess );
vassert(hregClass(r) == HRcVec128);
@@ -4492,7 +4499,8 @@
}
/* DO NOT CALL THIS DIRECTLY */
-static HReg iselFp128Expr_wrk( ISelEnv* env, IRExpr* e, IREndness IEndianess)
+static HReg iselFp128Expr_wrk( ISelEnv* env, const IRExpr* e,
+ IREndness IEndianess)
{
Bool mode64 = env->mode64;
PPCFpOp fpop = Pfp_INVALID;
@@ -4799,7 +4807,7 @@
vpanic( "iselFp128Expr(ppc64)" );
}
-static HReg iselDfp64Expr(ISelEnv* env, IRExpr* e, IREndness IEndianess)
+static HReg iselDfp64Expr(ISelEnv* env, const IRExpr* e, IREndness IEndianess)
{
HReg r = iselDfp64Expr_wrk( env, e, IEndianess );
vassert(hregClass(r) == HRcFlt64);
@@ -4808,7 +4816,8 @@
}
/* DO NOT CALL THIS DIRECTLY */
-static HReg iselDfp64Expr_wrk(ISelEnv* env, IRExpr* e, IREndness IEndianess)
+static HReg iselDfp64Expr_wrk(ISelEnv* env, const IRExpr* e,
+ IREndness IEndianess)
{
Bool mode64 = env->mode64;
IRType ty = typeOfIRExpr( env->type_env, e );
@@ -5082,7 +5091,7 @@
vpanic( "iselDfp64Expr_wrk(ppc)" );
}
-static void iselDfp128Expr(HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e,
+static void iselDfp128Expr(HReg* rHi, HReg* rLo, ISelEnv* env, const IRExpr* e,
IREndness IEndianess)
{
iselDfp128Expr_wrk( rHi, rLo, env, e, IEndianess );
@@ -5091,8 +5100,8 @@
}
/* DO NOT CALL THIS DIRECTLY */
-static void iselDfp128Expr_wrk(HReg* rHi, HReg *rLo, ISelEnv* env, IRExpr* e,
- IREndness IEndianess)
+static void iselDfp128Expr_wrk(HReg* rHi, HReg *rLo, ISelEnv* env,
+ const IRExpr* e, IREndness IEndianess)
{
vassert( e );
vassert( typeOfIRExpr(env->type_env,e) == Ity_D128 );
@@ -5359,7 +5368,7 @@
/*--- ISEL: SIMD (Vector) expressions, 128 bit. ---*/
/*---------------------------------------------------------*/
-static HReg iselVecExpr ( ISelEnv* env, IRExpr* e, IREndness IEndianess )
+static HReg iselVecExpr ( ISelEnv* env, const IRExpr* e, IREndness IEndianess )
{
HReg r = iselVecExpr_wrk( env, e, IEndianess );
# if 0
@@ -5371,7 +5380,8 @@
}
/* DO NOT CALL THIS DIRECTLY */
-static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e, IREndness IEndianess )
+static HReg iselVecExpr_wrk ( ISelEnv* env, const IRExpr* e,
+ IREndness IEndianess )
{
Bool mode64 = env->mode64;
PPCAvOp op = Pav_INVALID;
diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c
index 9885d47..91f08e5 100644
--- a/VEX/priv/host_s390_defs.c
+++ b/VEX/priv/host_s390_defs.c
@@ -8,8 +8,8 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2015
- Copyright (C) 2012-2015 Florian Krohm (britzel@acm.org)
+ Copyright IBM Corp. 2010-2017
+ Copyright (C) 2012-2017 Florian Krohm (britzel@acm.org)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/VEX/priv/host_s390_defs.h b/VEX/priv/host_s390_defs.h
index a7c4b1e..2026900 100644
--- a/VEX/priv/host_s390_defs.h
+++ b/VEX/priv/host_s390_defs.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2015
+ Copyright IBM Corp. 2010-2017
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/VEX/priv/host_s390_isel.c b/VEX/priv/host_s390_isel.c
index 02f399d..9322a05 100644
--- a/VEX/priv/host_s390_isel.c
+++ b/VEX/priv/host_s390_isel.c
@@ -8,8 +8,8 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2015
- Copyright (C) 2012-2015 Florian Krohm (britzel@acm.org)
+ Copyright IBM Corp. 2010-2017
+ Copyright (C) 2012-2017 Florian Krohm (britzel@acm.org)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -527,14 +527,14 @@
special node IRExpr_VECRET(). For s390, however, V128 and V256 return
values do not occur as we generally do not support vector types.
- |args| may also contain IRExpr_BBPTR(), in which case the value
+ |args| may also contain IRExpr_GSPTR(), in which case the value
in the guest state pointer register is passed as the
corresponding argument.
These are used for cross-checking that IR-level constraints on
- the use of IRExpr_VECRET() and IRExpr_BBPTR() are observed. */
+ the use of IRExpr_VECRET() and IRExpr_GSPTR() are observed. */
UInt nVECRETs = 0;
- UInt nBBPTRs = 0;
+ UInt nGSPTRs = 0;
n_args = 0;
for (i = 0; args[i]; i++)
@@ -553,8 +553,8 @@
for (i = 0; i < n_args; ++i) {
if (UNLIKELY(args[i]->tag == Iex_VECRET)) {
nVECRETs++;
- } else if (UNLIKELY(args[i]->tag == Iex_BBPTR)) {
- nBBPTRs++;
+ } else if (UNLIKELY(args[i]->tag == Iex_GSPTR)) {
+ nGSPTRs++;
} else {
IRType type = typeOfIRExpr(env->type_env, args[i]);
if (type != Ity_I64) {
@@ -570,7 +570,7 @@
vpanic("cannot continue due to errors in argument passing");
/* If these fail, the IR is ill-formed */
- vassert(nBBPTRs == 0 || nBBPTRs == 1);
+ vassert(nGSPTRs == 0 || nGSPTRs == 1);
vassert(nVECRETs == 0);
argreg = 0;
@@ -578,7 +578,7 @@
/* Compute the function arguments into a temporary register each */
for (i = 0; i < n_args; i++) {
IRExpr *arg = args[i];
- if (UNLIKELY(arg->tag == Iex_BBPTR)) {
+ if (UNLIKELY(arg->tag == Iex_GSPTR)) {
/* If we need the guest state pointer put it in a temporary arg reg */
tmpregs[argreg] = newVRegI(env);
addInstr(env, s390_insn_move(sizeof(ULong), tmpregs[argreg],
diff --git a/VEX/priv/host_tilegx_defs.c b/VEX/priv/host_tilegx_defs.c
deleted file mode 100644
index fc259e9..0000000
--- a/VEX/priv/host_tilegx_defs.c
+++ /dev/null
@@ -1,2628 +0,0 @@
-
-/*---------------------------------------------------------------*/
-/*--- begin host_tilegx_defs.c ---*/
-/*---------------------------------------------------------------*/
-
-/*
- This file is part of Valgrind, a dynamic binary instrumentation
- framework.
-
- Copyright (C) 2010-2015 Tilera Corp.
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of the
- License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful, but
- WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
- 02111-1307, USA.
-
- The GNU General Public License is contained in the file COPYING.
-*/
-
-/* Contributed by Zhi-Gang Liu <zliu at tilera dot com> */
-
-#include "libvex_basictypes.h"
-#include "libvex.h"
-#include "libvex_trc_values.h"
-
-#include "main_util.h"
-#include "host_generic_regs.h"
-#include "host_tilegx_defs.h"
-#include "tilegx_disasm.h"
-
-/* Contributed by Zhi-Gang Liu <zliu at tilera dot com> */
-
-/* Register number for guest state pointer in host code, r50 */
-#define GuestSP ( 50)
-/* CONTEXT_EX0 offset */
-#define OFFSET_EX0 (576)
-/* CONTEXT_EX1 offset */
-#define OFFSET_EX1 (584)
-/* COND offset */
-#define OFFSET_COND (608)
-/* PC offset */
-#define OFFSET_PC (512)
-
-/* guest_COND offset. */
-#define COND_OFFSET() OFFSET_COND
-
-/*---------------- Registers ----------------*/
-
-void ppHRegTILEGX ( HReg reg )
-{
- Int r;
- static const HChar *ireg_names[64] = {
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
- "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
- "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29",
- "r30", "r31", "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
- "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", "r48", "r49",
- "r50", "r51", "r52", "r53", "r54", "r55",
- "sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn3", "zero"
- };
-
- /* Be generic for all virtual regs. */
- if (hregIsVirtual(reg)) {
- ppHReg(reg);
- return;
- }
-
- /* But specific for real regs. */
- vassert(hregClass(reg) == HRcInt32 || hregClass(reg) == HRcInt64 ||
- hregClass(reg) == HRcFlt32 || hregClass(reg) == HRcFlt64);
-
- /* But specific for real regs. */
- switch (hregClass(reg)) {
- case HRcInt32:
- case HRcInt64:
- r = hregEncoding(reg);
- vassert(r >= 0 && r < 64);
- vex_printf("%s", ireg_names[r]);
- return;
- case HRcFlt32:
- r = hregEncoding(reg);
- vassert(r >= 0 && r < 64);
- vex_printf("%s", ireg_names[r]);
- return;
- case HRcFlt64:
- r = hregEncoding(reg);
- vassert(r >= 0 && r < 64);
- vex_printf("%s", ireg_names[r]);
- return;
- default:
- vpanic("ppHRegTILEGX");
- }
-
- return;
-}
-
-static const HChar* tilegxUnaryOp [] =
- {
- "clz ",
- "ctz ",
- "nop "
- };
-
-static const HChar* tilegxAluOp [] =
- { "Alu_invalid",
- "Add ",
- "Sub ",
- "And ",
- "Or ",
- "Nor ",
- "Xor "
- };
-
-static const HChar* tilegxShftOp [] =
- {
- "Shft_invalid",
- "Sll ",
- "Srl ",
- "Sra ",
- "Sll8x8 ",
- "Srl8x8 ",
- };
-
-static const HChar* tilegxBfOp [] =
- {
- "BfExts ",
- "BfEtxu ",
- "BfIns "
- };
-
-
-static const HChar* tilegxAcasOp [] =
- {
- "CmpExch ",
- "Exch ",
- "FetchAnd ",
- "FetchAdd ",
- "FetchAddgez",
- "FetchOr "
- };
-
-static const HChar* tilegxInstrTag [] =
- {
- "Imm ",
- "ALU ",
- "Shift ",
- "Unary ",
- "Cmp ",
- "CmpI ",
- "Mul ",
- "Call ",
- "XDirect ",
- "XIndir ",
- "XAssisted",
- "EvCheck ",
- "ProfInc ",
- "RdWrLR ",
- "Load ",
- "Store ",
- "MovCond ",
- "BitField ",
- "ACAS "
- };
-
-/* -------- Pretty Print instructions ------------- */
-static void ppLoadImm ( HReg dst, ULong imm )
-{
- vex_printf("li ");
- ppHRegTILEGX(dst);
- vex_printf(",0x%016lx", (unsigned long)imm);
-}
-
-void ppTILEGXInstr ( const TILEGXInstr * instr )
-{
- vex_printf("%s ", tilegxInstrTag[instr->tag]);
- switch (instr->tag) {
- case GXin_LI: {
- ppHRegTILEGX(instr->GXin.LI.dst);
- vex_printf(",0x%016llx", instr->GXin.LI.imm);
- }
- break;
-
- case GXin_Alu: {
- HReg r_srcL = instr->GXin.Alu.srcL;
- TILEGXRH *rh_srcR = instr->GXin.Alu.srcR;
- /* generic */
- vex_printf("%s ", tilegxAluOp[instr->GXin.Alu.op]);
- ppHRegTILEGX(instr->GXin.Alu.dst);
- vex_printf(",");
- ppHRegTILEGX(r_srcL);
- vex_printf(",");
- ppTILEGXRH(rh_srcR);
- }
- break;
-
- case GXin_Shft: {
- HReg r_srcL = instr->GXin.Shft.srcL;
- TILEGXRH *rh_srcR = instr->GXin.Shft.srcR;
- vex_printf("%s ", tilegxShftOp[instr->GXin.Shft.op]);
- ppHRegTILEGX(instr->GXin.Shft.dst);
- vex_printf(",");
- ppHRegTILEGX(r_srcL);
- vex_printf(",");
- ppTILEGXRH(rh_srcR);
- }
- break;
-
- case GXin_Unary: {
- vex_printf("%s ", tilegxUnaryOp[instr->GXin.Unary.op]);
- ppHRegTILEGX(instr->GXin.Unary.dst);
- vex_printf(",");
- ppHRegTILEGX(instr->GXin.Unary.src);
- }
- break;
-
- case GXin_Cmp: {
- ppHRegTILEGX(instr->GXin.Cmp.dst);
- vex_printf(" = %s ( ", showTILEGXCondCode(instr->GXin.Cmp.cond));
- ppHRegTILEGX(instr->GXin.Cmp.srcL);
- vex_printf(", ");
- ppHRegTILEGX(instr->GXin.Cmp.srcR);
- vex_printf(" )");
- }
- break;
-
- case GXin_CmpI: {
- ppHRegTILEGX(instr->GXin.CmpI.dst);
- vex_printf(" = %s ( ", showTILEGXCondCode(instr->GXin.CmpI.cond));
- ppHRegTILEGX(instr->GXin.CmpI.srcL);
- vex_printf(", ");
- ppTILEGXRH(instr->GXin.CmpI.srcR);
- vex_printf(" )");
- }
- break;
-
- case GXin_Mul: {
- if (instr->GXin.Mul.widening == False) {
- vex_printf("mul ");
- ppHRegTILEGX(instr->GXin.Mul.dst);
- vex_printf(", ");
- ppHRegTILEGX(instr->GXin.Mul.srcL);
- vex_printf(", ");
- ppHRegTILEGX(instr->GXin.Mul.srcR);
-
- } else {
- vex_printf("%s ", instr->GXin.Mul.syned ? "mull32s" : "mull32u");
- ppHRegTILEGX(instr->GXin.Mul.dst);
- vex_printf(", ");
- ppHRegTILEGX(instr->GXin.Mul.srcL);
- vex_printf(", ");
- ppHRegTILEGX(instr->GXin.Mul.srcR);
- }
- }
- break;
-
- case GXin_Call: {
- Int n;
- if (instr->GXin.Call.cond != TILEGXcc_AL) {
- vex_printf("if (%s (", showTILEGXCondCode(instr->GXin.Call.cond));
- ppHRegTILEGX(instr->GXin.Call.src);
- vex_printf(",zero))");
- }
- else
- vex_printf("(always) ");
-
- vex_printf("{ ");
- ppLoadImm(hregTILEGX_R11(), instr->GXin.Call.target);
-
- vex_printf(" ; [");
- for (n = 0; n < 56; n++) {
- if (instr->GXin.Call.argiregs & (1ULL << n)) {
- vex_printf("r%d", n);
- if ((instr->GXin.Call.argiregs >> n) > 1)
- vex_printf(",");
- }
- }
- vex_printf("] }");
- }
- break;
-
- case GXin_XDirect:
- vex_printf("(xDirect) ");
- vex_printf("if (guest_COND.%s) { ",
- showTILEGXCondCode(instr->GXin.XDirect.cond));
- vex_printf("move r11, 0x%x,", (UInt)instr->GXin.XDirect.dstGA);
- vex_printf("; st r11, ");
- ppTILEGXAMode(instr->GXin.XDirect.amPC);
- vex_printf("; move r11, $disp_cp_chain_me_to_%sEP; jalr r11; nop}",
- instr->GXin.XDirect.toFastEP ? "fast" : "slow");
- return;
- case GXin_XIndir:
- vex_printf("(xIndir) ");
- vex_printf("if (guest_COND.%s) { st ",
- showTILEGXCondCode(instr->GXin.XIndir.cond));
- ppHRegTILEGX(instr->GXin.XIndir.dstGA);
- vex_printf(", ");
- ppTILEGXAMode(instr->GXin.XIndir.amPC);
- vex_printf("; move r11, $disp_indir; jalr r11; nop}");
- return;
- case GXin_XAssisted:
- vex_printf("(xAssisted) ");
- vex_printf("if (guest_COND.%s) { ",
- showTILEGXCondCode(instr->GXin.XAssisted.cond));
- vex_printf("st ");
- ppHRegTILEGX(instr->GXin.XAssisted.dstGA);
- vex_printf(", ");
- ppTILEGXAMode(instr->GXin.XAssisted.amPC);
- vex_printf("; move r50, $IRJumpKind_to_TRCVAL(%d)",
- (Int)instr->GXin.XAssisted.jk);
- vex_printf("; move r11, $disp_assisted; jalr r11; nop; }");
- return;
-
- case GXin_EvCheck:
- vex_printf("(evCheck) ld r11, ");
- ppTILEGXAMode(instr->GXin.EvCheck.amCounter);
- vex_printf("; addli r11, r11, -1");
- vex_printf("; st r11, ");
- ppTILEGXAMode(instr->GXin.EvCheck.amCounter);
- vex_printf("; bgez r11, nofail; jalr *");
- ppTILEGXAMode(instr->GXin.EvCheck.amFailAddr);
- vex_printf("; nofail:");
- return;
- case GXin_ProfInc:
- vex_printf("(profInc) move r11, ($NotKnownYet); "
- "ld r8, r11; "
- "addi r8, r8, 1; "
- "st r11, r8; " );
- return;
- case GXin_Load: {
- UChar sz = instr->GXin.Load.sz;
- UChar c_sz = sz == 1 ? '1' : sz == 2 ? '2' : sz == 4 ? '4' : '8';
- vex_printf("ld%c ", c_sz);
- ppHRegTILEGX(instr->GXin.Load.dst);
- vex_printf(",");
- ppTILEGXAMode(instr->GXin.Load.src);
- }
- break;
-
- case GXin_Store: {
- UChar sz = instr->GXin.Store.sz;
- UChar c_sz = sz == 1 ? '1' : sz == 2 ? '2' : sz == 4 ? '4' : '8';
- vex_printf("st%c ", c_sz);
- ppTILEGXAMode(instr->GXin.Store.dst);
- vex_printf(",");
- ppHRegTILEGX(instr->GXin.Store.src);
- }
- break;
-
- case GXin_MovCond: {
- ppHRegTILEGX(instr->GXin.MovCond.dst);
- vex_printf("=");
- showTILEGXCondCode(instr->GXin.MovCond.cond);
- vex_printf("?");
- ppHRegTILEGX(instr->GXin.MovCond.srcL);
- vex_printf(":");
- ppTILEGXRH(instr->GXin.MovCond.srcR);
- }
- break;
-
- case GXin_Acas: {
- vex_printf("%s ", tilegxAcasOp[instr->GXin.Acas.op]);
- ppHRegTILEGX(instr->GXin.Acas.old);
- vex_printf(",");
- if (instr->GXin.Acas.op == GXacas_CMPEXCH) {
- ppHRegTILEGX(instr->GXin.Acas.exp);
- vex_printf(",");
- }
- ppHRegTILEGX(instr->GXin.Acas.new);
- }
- break;
-
- case GXin_Bf: {
- vex_printf("%s ", tilegxBfOp[instr->GXin.Bf.op]);
- ppHRegTILEGX(instr->GXin.Bf.dst);
- vex_printf(",");
- ppHRegTILEGX(instr->GXin.Bf.src);
- vex_printf(",");
- vex_printf("%d,%d", (Int)instr->GXin.Bf.Start, (Int)instr->GXin.Bf.End);
- }
- break;
-
- default:
- vassert(0);
- }
-}
-
-
-const RRegUniverse* getRRegUniverse_TILEGX ( void )
-{
- /* The 'universe' is constant and BIG, do it statically. */
- static RRegUniverse rRegUniverse_TILEGX;
- static UInt rRegUniverse_TILEGX_initted = False;
-
- /* Get a pointer of the 'universe' */
- RRegUniverse* ru = &rRegUniverse_TILEGX;
-
- if (LIKELY(rRegUniverse_TILEGX_initted))
- return ru;
-
- RRegUniverse__init(ru);
-
- /* Callee saves ones are listed first, since we prefer them
- if they're available */
-
- ru->regs[ru->size++] = hregTILEGX_R30();
- ru->regs[ru->size++] = hregTILEGX_R31();
- ru->regs[ru->size++] = hregTILEGX_R32();
- ru->regs[ru->size++] = hregTILEGX_R33();
- ru->regs[ru->size++] = hregTILEGX_R34();
- ru->regs[ru->size++] = hregTILEGX_R35();
- ru->regs[ru->size++] = hregTILEGX_R36();
- ru->regs[ru->size++] = hregTILEGX_R37();
- ru->regs[ru->size++] = hregTILEGX_R38();
- ru->regs[ru->size++] = hregTILEGX_R39();
-
- ru->regs[ru->size++] = hregTILEGX_R40();
- ru->regs[ru->size++] = hregTILEGX_R41();
- ru->regs[ru->size++] = hregTILEGX_R42();
- ru->regs[ru->size++] = hregTILEGX_R43();
- ru->regs[ru->size++] = hregTILEGX_R44();
- ru->regs[ru->size++] = hregTILEGX_R45();
- ru->regs[ru->size++] = hregTILEGX_R46();
- ru->regs[ru->size++] = hregTILEGX_R47();
- ru->regs[ru->size++] = hregTILEGX_R48();
- ru->regs[ru->size++] = hregTILEGX_R49();
-
- /* GPR 50 is reserved as Guest state */
- /* GPR 51 is reserved register, mainly used to do memory
- load and store since TileGx has no pre-displacement
- addressing mode */
-
- ru->regs[ru->size++] = hregTILEGX_R10();
-
- /* GPR 11 is reserved as next guest address */
-
- ru->regs[ru->size++] = hregTILEGX_R13();
- ru->regs[ru->size++] = hregTILEGX_R14();
- ru->regs[ru->size++] = hregTILEGX_R15();
- ru->regs[ru->size++] = hregTILEGX_R16();
- ru->regs[ru->size++] = hregTILEGX_R17();
- ru->regs[ru->size++] = hregTILEGX_R18();
- ru->regs[ru->size++] = hregTILEGX_R19();
- ru->regs[ru->size++] = hregTILEGX_R20();
- ru->regs[ru->size++] = hregTILEGX_R21();
- ru->regs[ru->size++] = hregTILEGX_R22();
- ru->regs[ru->size++] = hregTILEGX_R23();
- ru->regs[ru->size++] = hregTILEGX_R24();
- ru->regs[ru->size++] = hregTILEGX_R25();
- ru->regs[ru->size++] = hregTILEGX_R26();
- ru->regs[ru->size++] = hregTILEGX_R27();
- ru->regs[ru->size++] = hregTILEGX_R28();
- ru->regs[ru->size++] = hregTILEGX_R29();
-
- ru->allocable = ru->size;
-
- /* And other unallocable registers. */
- ru->regs[ru->size++] = hregTILEGX_R0();
- ru->regs[ru->size++] = hregTILEGX_R1();
- ru->regs[ru->size++] = hregTILEGX_R2();
- ru->regs[ru->size++] = hregTILEGX_R3();
- ru->regs[ru->size++] = hregTILEGX_R4();
- ru->regs[ru->size++] = hregTILEGX_R5();
- ru->regs[ru->size++] = hregTILEGX_R6();
- ru->regs[ru->size++] = hregTILEGX_R7();
- ru->regs[ru->size++] = hregTILEGX_R8();
- ru->regs[ru->size++] = hregTILEGX_R9();
- ru->regs[ru->size++] = hregTILEGX_R11();
- ru->regs[ru->size++] = hregTILEGX_R12();
- ru->regs[ru->size++] = hregTILEGX_R50();
- ru->regs[ru->size++] = hregTILEGX_R51();
- ru->regs[ru->size++] = hregTILEGX_R52();
- ru->regs[ru->size++] = hregTILEGX_R53();
- ru->regs[ru->size++] = hregTILEGX_R54();
- ru->regs[ru->size++] = hregTILEGX_R55();
- ru->regs[ru->size++] = hregTILEGX_R63();
-
- rRegUniverse_TILEGX_initted = True;
-
- RRegUniverse__check_is_sane(ru);
-
- return ru;
-}
-
-/*----------------- Condition Codes ----------------------*/
-
-const HChar *showTILEGXCondCode ( TILEGXCondCode cond )
-{
- switch (cond) {
- case TILEGXcc_EQ:
- return "e"; /* equal */
- case TILEGXcc_EQ8x8:
- return "e8x8"; /* equal */
-
- case TILEGXcc_NE:
- return "ne"; /* not equal */
- case TILEGXcc_NE8x8:
- return "ne8x8"; /* not equal */
-
- case TILEGXcc_HS:
- return "hs"; /* >=u (higher or same) */
- case TILEGXcc_LO:
- return "lo"; /* <u (lower) */
-
- case TILEGXcc_MI:
- return "mi"; /* minus (negative) */
- case TILEGXcc_PL:
- return "pl"; /* plus (zero or +ve) */
-
- case TILEGXcc_VS:
- return "vs"; /* overflow */
- case TILEGXcc_VC:
- return "vc"; /* no overflow */
-
- case TILEGXcc_HI:
- return "hi"; /* >u (higher) */
- case TILEGXcc_LS:
- return "ls"; /* <=u (lower or same) */
-
- case TILEGXcc_GE:
- return "ge"; /* >=s (signed greater or equal) */
- case TILEGXcc_LT:
- return "lt"; /* <s (signed less than) */
-
- case TILEGXcc_GT:
- return "gt"; /* >s (signed greater) */
- case TILEGXcc_LE:
- return "le"; /* <=s (signed less or equal) */
-
- case TILEGXcc_AL:
- return "al"; /* always (unconditional) */
- case TILEGXcc_NV:
- return "nv"; /* never (unconditional): */
- case TILEGXcc_EZ:
- return "ez"; /* equal 0 */
- case TILEGXcc_NZ:
- return "nz"; /* not equal 0 */
-
- default:
- vpanic("showTILEGXCondCode");
- }
-}
-
-
-/* --------- TILEGXAMode: memory address expressions. --------- */
-
-TILEGXAMode *TILEGXAMode_IR ( Int idx, HReg base )
-{
- TILEGXAMode *am = LibVEX_Alloc(sizeof(TILEGXAMode));
- am->tag = GXam_IR;
- am->GXam.IR.base = base;
- am->GXam.IR.index = idx;
-
- return am;
-}
-
-TILEGXAMode *nextTILEGXAModeInt ( TILEGXAMode * am )
-{
- if (am->tag == GXam_IR)
- return TILEGXAMode_IR(am->GXam.IR.index + 4, am->GXam.IR.base);
-
- vpanic("dopyTILEGXAMode");
-}
-
-void ppTILEGXAMode ( const TILEGXAMode * am )
-{
- if (am->tag == GXam_IR)
- {
- if (am->GXam.IR.index == 0)
- vex_printf("(");
- else
- vex_printf("%d(", (Int) am->GXam.IR.index);
- ppHRegTILEGX(am->GXam.IR.base);
- vex_printf(")");
- return;
- }
- vpanic("ppTILEGXAMode");
-}
-
-static void addRegUsage_TILEGXAMode ( HRegUsage * u, TILEGXAMode * am )
-{
- if (am->tag == GXam_IR)
- {
- addHRegUse(u, HRmRead, am->GXam.IR.base);
- return;
- }
-
- vpanic("addRegUsage_TILEGXAMode");
-}
-
-static void mapRegs_TILEGXAMode ( HRegRemap * m, TILEGXAMode * am )
-{
- if (am->tag == GXam_IR)
- {
- am->GXam.IR.base = lookupHRegRemap(m, am->GXam.IR.base);
- return;
- }
-
- vpanic("mapRegs_TILEGXAMode");
-}
-
-/* --------- Operand, which can be a reg or a u16/s16. --------- */
-
-TILEGXRH *TILEGXRH_Imm ( Bool syned, UShort imm16 )
-{
- TILEGXRH *op = LibVEX_Alloc(sizeof(TILEGXRH));
- op->tag = GXrh_Imm;
- op->GXrh.Imm.syned = syned;
- op->GXrh.Imm.imm16 = imm16;
- /* If this is a signed value, ensure it's not -32768, so that we
- are guaranteed always to be able to negate if needed. */
- if (syned)
- vassert(imm16 != 0x8000);
- vassert(syned == True || syned == False);
- return op;
-}
-
-TILEGXRH *TILEGXRH_Reg ( HReg reg )
-{
- TILEGXRH *op = LibVEX_Alloc(sizeof(TILEGXRH));
- op->tag = GXrh_Reg;
- op->GXrh.Reg.reg = reg;
- return op;
-}
-
-void ppTILEGXRH ( const TILEGXRH * op )
-{
- TILEGXRHTag tag = op->tag;
- switch (tag) {
- case GXrh_Imm:
- if (op->GXrh.Imm.syned)
- vex_printf("%d", (Int) (Short) op->GXrh.Imm.imm16);
- else
- vex_printf("%u", (UInt) (UShort) op->GXrh.Imm.imm16);
- return;
- case GXrh_Reg:
- ppHRegTILEGX(op->GXrh.Reg.reg);
- return;
- default:
- vpanic("ppTILEGXRH");
- }
-}
-
-/* An TILEGXRH can only be used in a "read" context (what would it mean
- to write or modify a literal?) and so we enumerate its registers
- accordingly. */
-static void addRegUsage_TILEGXRH ( HRegUsage * u, TILEGXRH * op )
-{
- switch (op->tag) {
- case GXrh_Imm:
- return;
- case GXrh_Reg:
- addHRegUse(u, HRmRead, op->GXrh.Reg.reg);
- return;
- default:
- vpanic("addRegUsage_TILEGXRH");
- }
-}
-
-static void mapRegs_TILEGXRH ( HRegRemap * m, TILEGXRH * op )
-{
- switch (op->tag) {
- case GXrh_Imm:
- return;
- case GXrh_Reg:
- op->GXrh.Reg.reg = lookupHRegRemap(m, op->GXrh.Reg.reg);
- return;
- default:
- vpanic("mapRegs_TILEGXRH");
- }
-}
-
-TILEGXInstr *TILEGXInstr_LI ( HReg dst, ULong imm )
-{
- TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr));
- i->tag = GXin_LI;
- i->GXin.LI.dst = dst;
- i->GXin.LI.imm = imm;
- return i;
-}
-
-TILEGXInstr *TILEGXInstr_Alu ( TILEGXAluOp op, HReg dst, HReg srcL,
- TILEGXRH * srcR )
-{
- TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr));
- i->tag = GXin_Alu;
- i->GXin.Alu.op = op;
- i->GXin.Alu.dst = dst;
- i->GXin.Alu.srcL = srcL;
- i->GXin.Alu.srcR = srcR;
- return i;
-}
-
-TILEGXInstr *TILEGXInstr_Shft ( TILEGXShftOp op, Bool sz32, HReg dst, HReg srcL,
- TILEGXRH * srcR )
-{
- TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr));
- i->tag = GXin_Shft;
- i->GXin.Shft.op = op;
- i->GXin.Shft.sz32 = sz32;
- i->GXin.Shft.dst = dst;
- i->GXin.Shft.srcL = srcL;
- i->GXin.Shft.srcR = srcR;
- return i;
-}
-
-TILEGXInstr *TILEGXInstr_Unary ( TILEGXUnaryOp op, HReg dst, HReg src )
-{
- TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr));
- i->tag = GXin_Unary;
- i->GXin.Unary.op = op;
- i->GXin.Unary.dst = dst;
- i->GXin.Unary.src = src;
- return i;
-}
-
-TILEGXInstr *TILEGXInstr_Cmp ( Bool syned, Bool sz32, HReg dst,
- HReg srcL, HReg srcR, TILEGXCondCode cond )
-{
- TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr));
- i->tag = GXin_Cmp;
- i->GXin.Cmp.syned = syned;
- i->GXin.Cmp.sz32 = sz32;
- i->GXin.Cmp.dst = dst;
- i->GXin.Cmp.srcL = srcL;
- i->GXin.Cmp.srcR = srcR;
- i->GXin.Cmp.cond = cond;
- return i;
-}
-
-TILEGXInstr *TILEGXInstr_CmpI ( Bool syned, Bool sz32, HReg dst,
- HReg srcL, TILEGXRH * srcR,
- TILEGXCondCode cond )
-{
- TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr));
- i->tag = GXin_CmpI;
- i->GXin.CmpI.syned = syned;
- i->GXin.CmpI.sz32 = sz32;
- i->GXin.CmpI.dst = dst;
- i->GXin.CmpI.srcL = srcL;
- i->GXin.CmpI.srcR = srcR;
- i->GXin.CmpI.cond = cond;
- return i;
-}
-
-TILEGXInstr *TILEGXInstr_Bf ( TILEGXBfOp op, HReg dst, HReg src,
- UInt Start, UInt End )
-{
- TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr));
- i->tag = GXin_Bf;
- i->GXin.Bf.op = op;
- i->GXin.Bf.dst = dst;
- i->GXin.Bf.src = src;
- i->GXin.Bf.Start = Start;
- i->GXin.Bf.End = End;
- return i;
-}
-
-TILEGXInstr *TILEGXInstr_Acas ( TILEGXAcasOp op, HReg old,
- HReg addr, HReg exp, HReg new, UInt sz )
-{
- TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr));
- i->tag = GXin_Acas;
- i->GXin.Acas.op = op;
- i->GXin.Acas.old = old;
- i->GXin.Acas.addr = addr;
- i->GXin.Acas.exp = exp;
- i->GXin.Acas.new = new;
- i->GXin.Acas.sz = sz;
- return i;
-}
-
-/* multiply */
-TILEGXInstr *TILEGXInstr_Mul ( Bool syned, Bool wid, Bool sz32,
- HReg dst, HReg srcL,
- HReg srcR )
-{
- TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr));
- i->tag = GXin_Mul;
- i->GXin.Mul.syned = syned;
- i->GXin.Mul.widening = wid; /* widen=True else False */
- i->GXin.Mul.sz32 = sz32; /* True = 32 bits */
- i->GXin.Mul.dst = dst;
- i->GXin.Mul.srcL = srcL;
- i->GXin.Mul.srcR = srcR;
- return i;
-}
-
-TILEGXInstr *TILEGXInstr_Call ( TILEGXCondCode cond, Addr64 target,
- ULong argiregs,
- HReg src )
-{
- ULong mask;
- TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr));
- i->tag = GXin_Call;
- i->GXin.Call.cond = cond;
- i->GXin.Call.target = target;
- i->GXin.Call.argiregs = argiregs;
- i->GXin.Call.src = src;
-
- /* Only r0 .. r9 inclusive may be used as arg regs. Hence: */
- mask = (1ULL << 10) - 1;
- vassert(0 == (argiregs & ~mask));
- return i;
-}
-
-TILEGXInstr *TILEGXInstr_CallAlways ( TILEGXCondCode cond, Addr64 target,
- ULong argiregs )
-{
- ULong mask;
- TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr));
- i->tag = GXin_Call;
- i->GXin.Call.cond = cond;
- i->GXin.Call.target = target;
- i->GXin.Call.argiregs = argiregs;
-
- /* Only r0 .. r9 inclusive may be used as arg regs. Hence: */
- mask = (1ULL << 10) - 1;
- vassert(0 == (argiregs & ~mask));
- return i;
-}
-
-TILEGXInstr *TILEGXInstr_XDirect ( Addr64 dstGA, TILEGXAMode* amPC,
- TILEGXCondCode cond, Bool toFastEP )
-{
- TILEGXInstr* i = LibVEX_Alloc(sizeof(TILEGXInstr));
- i->tag = GXin_XDirect;
- i->GXin.XDirect.dstGA = dstGA;
- i->GXin.XDirect.amPC = amPC;
- i->GXin.XDirect.cond = cond;
- i->GXin.XDirect.toFastEP = toFastEP;
- return i;
-}
-
-TILEGXInstr *TILEGXInstr_XIndir ( HReg dstGA, TILEGXAMode* amPC,
- TILEGXCondCode cond )
-{
- TILEGXInstr* i = LibVEX_Alloc(sizeof(TILEGXInstr));
- i->tag = GXin_XIndir;
- i->GXin.XIndir.dstGA = dstGA;
- i->GXin.XIndir.amPC = amPC;
- i->GXin.XIndir.cond = cond;
- return i;
-}
-
-TILEGXInstr *TILEGXInstr_XAssisted ( HReg dstGA, TILEGXAMode* amPC,
- TILEGXCondCode cond, IRJumpKind jk )
-{
- TILEGXInstr* i = LibVEX_Alloc(sizeof(TILEGXInstr));
- i->tag = GXin_XAssisted;
- i->GXin.XAssisted.dstGA = dstGA;
- i->GXin.XAssisted.amPC = amPC;
- i->GXin.XAssisted.cond = cond;
- i->GXin.XAssisted.jk = jk;
- return i;
-}
-
-TILEGXInstr *TILEGXInstr_EvCheck ( TILEGXAMode* amCounter,
- TILEGXAMode* amFailAddr ) {
- TILEGXInstr* i = LibVEX_Alloc(sizeof(TILEGXInstr));
- i->tag = GXin_EvCheck;
- i->GXin.EvCheck.amCounter = amCounter;
- i->GXin.EvCheck.amFailAddr = amFailAddr;
- return i;
-}
-
-TILEGXInstr* TILEGXInstr_ProfInc ( void ) {
- TILEGXInstr* i = LibVEX_Alloc(sizeof(TILEGXInstr));
- i->tag = GXin_ProfInc;
- return i;
-}
-
-TILEGXInstr *TILEGXInstr_Load ( UChar sz, HReg dst, TILEGXAMode * src )
-{
- TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr));
- i->tag = GXin_Load;
- i->GXin.Load.sz = sz;
- i->GXin.Load.src = src;
- i->GXin.Load.dst = dst;
- vassert(sz == 1 || sz == 2 || sz == 4 || sz == 8);
- return i;
-}
-
-TILEGXInstr *TILEGXInstr_Store(UChar sz, TILEGXAMode * dst, HReg src)
-{
- TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr));
- i->tag = GXin_Store;
- i->GXin.Store.sz = sz;
- i->GXin.Store.src = src;
- i->GXin.Store.dst = dst;
- vassert(sz == 1 || sz == 2 || sz == 4 || sz == 8);
- return i;
-}
-
-/* Read/Write Link Register */
-TILEGXInstr *TILEGXInstr_RdWrLR ( Bool wrLR, HReg gpr )
-{
- TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr));
- i->tag = GXin_RdWrLR;
- i->GXin.RdWrLR.wrLR = wrLR;
- i->GXin.RdWrLR.gpr = gpr;
- return i;
-}
-
-TILEGXInstr *TILEGXInstr_MovCond ( HReg dst, HReg argL, TILEGXRH * argR,
- HReg condR, TILEGXCondCode cond )
-{
- TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr));
- i->tag = GXin_MovCond;
- i->GXin.MovCond.dst = dst;
- i->GXin.MovCond.srcL = argL;
- i->GXin.MovCond.srcR = argR;
- i->GXin.MovCond.condR = condR;
- i->GXin.MovCond.cond = cond;
- return i;
-}
-
-/* --------- Helpers for register allocation. --------- */
-
-void getRegUsage_TILEGXInstr ( HRegUsage * u, TILEGXInstr * i )
-{
- initHRegUsage(u);
- switch (i->tag) {
- case GXin_LI:
- addHRegUse(u, HRmWrite, i->GXin.LI.dst);
- break;
- case GXin_Alu:
- addHRegUse(u, HRmRead, i->GXin.Alu.srcL);
- addRegUsage_TILEGXRH(u, i->GXin.Alu.srcR);
- addHRegUse(u, HRmWrite, i->GXin.Alu.dst);
- return;
- case GXin_CmpI:
- addHRegUse(u, HRmRead, i->GXin.CmpI.srcL);
- addRegUsage_TILEGXRH(u, i->GXin.CmpI.srcR);
- addHRegUse(u, HRmWrite, i->GXin.CmpI.dst);
- return;
- case GXin_Shft:
- addHRegUse(u, HRmRead, i->GXin.Shft.srcL);
- addRegUsage_TILEGXRH(u, i->GXin.Shft.srcR);
- addHRegUse(u, HRmWrite, i->GXin.Shft.dst);
- return;
- case GXin_Cmp:
- addHRegUse(u, HRmRead, i->GXin.Cmp.srcL);
- addHRegUse(u, HRmRead, i->GXin.Cmp.srcR);
- addHRegUse(u, HRmWrite, i->GXin.Cmp.dst);
- return;
- case GXin_Bf:
- addHRegUse(u, HRmRead, i->GXin.Bf.src);
- addHRegUse(u, HRmWrite, i->GXin.Bf.dst);
- return;
- case GXin_Acas:
- addHRegUse(u, HRmRead, i->GXin.Acas.addr);
- addHRegUse(u, HRmRead, i->GXin.Acas.new);
- if (i->GXin.Acas.op == GXacas_CMPEXCH)
- addHRegUse(u, HRmRead, i->GXin.Acas.exp);
- addHRegUse(u, HRmWrite, i->GXin.Acas.old);
- return;
- case GXin_Unary:
- addHRegUse(u, HRmRead, i->GXin.Unary.src);
- addHRegUse(u, HRmWrite, i->GXin.Unary.dst);
- return;
- case GXin_Mul:
- addHRegUse(u, HRmWrite, i->GXin.Mul.dst);
- addHRegUse(u, HRmRead, i->GXin.Mul.srcL);
- addHRegUse(u, HRmRead, i->GXin.Mul.srcR);
- return;
- case GXin_Call: {
- if (i->GXin.Call.cond != TILEGXcc_AL)
- addHRegUse(u, HRmRead, i->GXin.Call.src);
- ULong argir;
-
- // Only need save r10-r29, and r0-r9 is not allocable.
- addHRegUse(u, HRmWrite, hregTILEGX_R10());
- addHRegUse(u, HRmWrite, hregTILEGX_R11());
- addHRegUse(u, HRmWrite, hregTILEGX_R12());
- addHRegUse(u, HRmWrite, hregTILEGX_R13());
- addHRegUse(u, HRmWrite, hregTILEGX_R14());
- addHRegUse(u, HRmWrite, hregTILEGX_R15());
-
- addHRegUse(u, HRmWrite, hregTILEGX_R16());
- addHRegUse(u, HRmWrite, hregTILEGX_R17());
- addHRegUse(u, HRmWrite, hregTILEGX_R18());
- addHRegUse(u, HRmWrite, hregTILEGX_R19());
- addHRegUse(u, HRmWrite, hregTILEGX_R20());
- addHRegUse(u, HRmWrite, hregTILEGX_R21());
- addHRegUse(u, HRmWrite, hregTILEGX_R22());
- addHRegUse(u, HRmWrite, hregTILEGX_R23());
-
- addHRegUse(u, HRmWrite, hregTILEGX_R24());
- addHRegUse(u, HRmWrite, hregTILEGX_R25());
- addHRegUse(u, HRmWrite, hregTILEGX_R26());
- addHRegUse(u, HRmWrite, hregTILEGX_R27());
-
- addHRegUse(u, HRmWrite, hregTILEGX_R28());
- addHRegUse(u, HRmWrite, hregTILEGX_R29());
-
- /* Now we have to state any parameter-carrying registers
- which might be read. This depends on the argiregs field. */
- argir = i->GXin.Call.argiregs;
- if (argir & (1 << 9))
- addHRegUse(u, HRmRead, hregTILEGX_R9());
- if (argir & (1 << 8))
- addHRegUse(u, HRmRead, hregTILEGX_R8());
- if (argir & (1 << 7))
- addHRegUse(u, HRmRead, hregTILEGX_R7());
- if (argir & (1 << 6))
- addHRegUse(u, HRmRead, hregTILEGX_R6());
- if (argir & (1 << 5))
- addHRegUse(u, HRmRead, hregTILEGX_R5());
- if (argir & (1 << 4))
- addHRegUse(u, HRmRead, hregTILEGX_R4());
- if (argir & (1 << 3))
- addHRegUse(u, HRmRead, hregTILEGX_R3());
- if (argir & (1 << 2))
- addHRegUse(u, HRmRead, hregTILEGX_R2());
- if (argir & (1 << 1))
- addHRegUse(u, HRmRead, hregTILEGX_R1());
- if (argir & (1 << 0))
- addHRegUse(u, HRmRead, hregTILEGX_R0());
-
- vassert(0 == (argir & ~((1ULL << 10) - 1)));
- return;
- }
- case GXin_XDirect:
- addRegUsage_TILEGXAMode(u, i->GXin.XDirect.amPC);
- return;
- case GXin_XIndir:
- addHRegUse(u, HRmRead, i->GXin.XIndir.dstGA);
- addRegUsage_TILEGXAMode(u, i->GXin.XIndir.amPC);
- return;
- case GXin_XAssisted:
- addHRegUse(u, HRmRead, i->GXin.XAssisted.dstGA);
- addRegUsage_TILEGXAMode(u, i->GXin.XAssisted.amPC);
- return;
-
- case GXin_EvCheck:
- addRegUsage_TILEGXAMode(u, i->GXin.EvCheck.amCounter);
- addRegUsage_TILEGXAMode(u, i->GXin.EvCheck.amFailAddr);
- return;
- case GXin_ProfInc:
- return;
- case GXin_Load:
- addRegUsage_TILEGXAMode(u, i->GXin.Load.src);
- addHRegUse(u, HRmWrite, i->GXin.Load.dst);
- return;
- case GXin_Store:
- addHRegUse(u, HRmRead, i->GXin.Store.src);
- addRegUsage_TILEGXAMode(u, i->GXin.Store.dst);
- return;
- case GXin_RdWrLR:
- addHRegUse(u, (i->GXin.RdWrLR.wrLR ? HRmRead : HRmWrite),
- i->GXin.RdWrLR.gpr);
- return;
- case GXin_MovCond:
- if (i->GXin.MovCond.srcR->tag == GXrh_Reg) {
- addHRegUse(u, HRmRead, i->GXin.MovCond.srcR->GXrh.Reg.reg);
- }
- addHRegUse(u, HRmRead, i->GXin.MovCond.srcL);
- addHRegUse(u, HRmRead, i->GXin.MovCond.condR);
- addHRegUse(u, HRmWrite, i->GXin.MovCond.dst);
- return;
- default:
- vpanic("getRegUsage_TILEGXInstr");
- }
-}
-
-/* local helper */
-static void mapReg ( HRegRemap * m, HReg * r )
-{
- *r = lookupHRegRemap(m, *r);
-}
-
-void mapRegs_TILEGXInstr ( HRegRemap * m, TILEGXInstr * i )
-{
- switch (i->tag) {
- case GXin_LI:
- mapReg(m, &i->GXin.LI.dst);
- break;
- case GXin_Alu:
- mapReg(m, &i->GXin.Alu.srcL);
- mapRegs_TILEGXRH(m, i->GXin.Alu.srcR);
- mapReg(m, &i->GXin.Alu.dst);
- return;
- case GXin_CmpI:
- mapReg(m, &i->GXin.CmpI.srcL);
- mapRegs_TILEGXRH(m, i->GXin.CmpI.srcR);
- mapReg(m, &i->GXin.CmpI.dst);
- return;
- case GXin_Shft:
- mapReg(m, &i->GXin.Shft.srcL);
- mapRegs_TILEGXRH(m, i->GXin.Shft.srcR);
- mapReg(m, &i->GXin.Shft.dst);
- return;
- case GXin_Cmp:
- mapReg(m, &i->GXin.Cmp.srcL);
- mapReg(m, &i->GXin.Cmp.srcR);
- mapReg(m, &i->GXin.Cmp.dst);
- return;
- case GXin_Acas:
- mapReg(m, &i->GXin.Acas.old);
- mapReg(m, &i->GXin.Acas.addr);
- mapReg(m, &i->GXin.Acas.new);
- if (i->GXin.Acas.op == GXacas_CMPEXCH)
- mapReg(m, &i->GXin.Acas.exp);
- return;
- case GXin_Bf:
- mapReg(m, &i->GXin.Bf.src);
- mapReg(m, &i->GXin.Bf.dst);
- return;
- case GXin_Unary:
- mapReg(m, &i->GXin.Unary.src);
- mapReg(m, &i->GXin.Unary.dst);
- return;
- case GXin_Mul:
- mapReg(m, &i->GXin.Mul.dst);
- mapReg(m, &i->GXin.Mul.srcL);
- mapReg(m, &i->GXin.Mul.srcR);
- return;
- case GXin_Call:
- {
- if (i->GXin.Call.cond != TILEGXcc_AL)
- mapReg(m, &i->GXin.Call.src);
- return;
- }
- case GXin_XDirect:
- mapRegs_TILEGXAMode(m, i->GXin.XDirect.amPC);
- return;
- case GXin_XIndir:
- mapReg(m, &i->GXin.XIndir.dstGA);
- mapRegs_TILEGXAMode(m, i->GXin.XIndir.amPC);
- return;
- case GXin_XAssisted:
- mapReg(m, &i->GXin.XAssisted.dstGA);
- mapRegs_TILEGXAMode(m, i->GXin.XAssisted.amPC);
- return;
- case GXin_EvCheck:
- mapRegs_TILEGXAMode(m, i->GXin.EvCheck.amCounter);
- mapRegs_TILEGXAMode(m, i->GXin.EvCheck.amFailAddr);
- return;
- case GXin_ProfInc:
- return;
- case GXin_Load:
- mapRegs_TILEGXAMode(m, i->GXin.Load.src);
- mapReg(m, &i->GXin.Load.dst);
- return;
- case GXin_Store:
- mapReg(m, &i->GXin.Store.src);
- mapRegs_TILEGXAMode(m, i->GXin.Store.dst);
- return;
- case GXin_RdWrLR:
- mapReg(m, &i->GXin.RdWrLR.gpr);
- return;
- case GXin_MovCond:
- if (i->GXin.MovCond.srcR->tag == GXrh_Reg) {
- mapReg(m, &(i->GXin.MovCond.srcR->GXrh.Reg.reg));
- }
- mapReg(m, &i->GXin.MovCond.srcL);
- mapReg(m, &i->GXin.MovCond.condR);
- mapReg(m, &i->GXin.MovCond.dst);
-
- return;
- default:
- vpanic("mapRegs_TILEGXInstr");
- }
-}
-
-/* Figure out if i represents a reg-reg move, and if so assign the
- source and destination to *src and *dst. If in doubt say No. Used
- by the register allocator to do move coalescing.
-*/
-Bool isMove_TILEGXInstr ( TILEGXInstr * i, HReg * src, HReg * dst )
-{
- /* Moves between integer regs */
- if (i->tag == GXin_Alu) {
- // or Rd,Rs,Rs == mov Rd, Rs
- if (i->GXin.Alu.op != GXalu_OR)
- return False;
- if (i->GXin.Alu.srcR->tag != GXrh_Reg)
- return False;
- if (!sameHReg(i->GXin.Alu.srcR->GXrh.Reg.reg, i->GXin.Alu.srcL))
- return False;
- *src = i->GXin.Alu.srcL;
- *dst = i->GXin.Alu.dst;
- return True;
- }
- return False;
-}
-
-/* Generate tilegx spill/reload instructions under the direction of the
- register allocator.
-*/
-void genSpill_TILEGX ( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, HReg rreg,
- Int offsetB )
-{
- TILEGXAMode *am;
- vassert(offsetB >= 0);
- vassert(!hregIsVirtual(rreg));
- *i1 = *i2 = NULL;
- am = TILEGXAMode_IR(offsetB, TILEGXGuestStatePointer());
-
- switch (hregClass(rreg)) {
- case HRcInt64:
- *i1 = TILEGXInstr_Store(8, am, rreg);
- break;
- case HRcInt32:
- *i1 = TILEGXInstr_Store(4, am, rreg);
- break;
- default:
- ppHRegClass(hregClass(rreg));
- vpanic("genSpill_TILEGX: unimplemented regclass");
- }
-}
-
-void genReload_TILEGX ( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, HReg rreg,
- Int offsetB )
-{
- TILEGXAMode *am;
- vassert(!hregIsVirtual(rreg));
- am = TILEGXAMode_IR(offsetB, TILEGXGuestStatePointer());
-
- switch (hregClass(rreg)) {
- case HRcInt64:
- *i1 = TILEGXInstr_Load(8, rreg, am);
- break;
- case HRcInt32:
- *i1 = TILEGXInstr_Load(4, rreg, am);
- break;
- default:
- ppHRegClass(hregClass(rreg));
- vpanic("genReload_TILEGX: unimplemented regclass");
- break;
- }
-}
-
-/* --------- The tilegx assembler --------- */
-
-static UChar *mkInsnBin ( UChar * p, ULong insn )
-{
- vassert(insn != (ULong)(-1));
- if (((Addr)p) & 7) {
- vex_printf("p=%p\n", p);
- vassert((((Addr)p) & 7) == 0);
- }
- *((ULong *)(Addr)p) = insn;
- p += 8;
- return p;
-}
-
-static Int display_insn ( struct tilegx_decoded_instruction
- decoded[1] )
-{
- Int i;
- for (i = 0;
- decoded[i].opcode && (i < 1);
- i++) {
- Int n;
- vex_printf("%s ", decoded[i].opcode->name);
-
- for (n = 0; n < decoded[i].opcode->num_operands; n++) {
- const struct tilegx_operand *op = decoded[i].operands[n];
-
- if (op->type == TILEGX_OP_TYPE_REGISTER)
- vex_printf("r%d", (Int) decoded[i].operand_values[n]);
- else
- vex_printf("%llu", (ULong)decoded[i].operand_values[n]);
-
- if (n != (decoded[i].opcode->num_operands - 1))
- vex_printf(", ");
- }
- vex_printf(" ");
- }
- return i;
-}
-
-
-Int decode_and_display ( tilegx_bundle_bits *p, Int count, ULong pc )
-{
- struct tilegx_decoded_instruction
- decode[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE];
- Int i;
-
-#ifdef TILEGX_DEBUG
- vex_printf("Insn@0x%lx\n", (ULong)p);
-#endif
-
- if (count > 0x1000) {
- vex_printf("insn count: %d", count);
- vassert(0);
- }
-
- for (i = 0 ; i < count ; i++) {
- if (pc) {
- vex_printf("%012llx %016llx ", pc, (ULong)p[i]);
- pc += 8;
- }
- parse_insn_tilegx(p[i], 0, decode);
-
- Int n, k, bundled = 0;
-
- for(k = 0; (k < TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE) && decode[k].opcode;
- k++) {
- if (decode[k].opcode->mnemonic != TILEGX_OPC_FNOP)
- bundled++;
- }
-
- /* Print "{", ";" and "}" only if multiple instructions are bundled. */
- if (bundled > 1)
- vex_printf("{ ");
-
- n = bundled;
- for(k = 0; (k < TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE) && decode[k].opcode;
- k++) {
- if (decode[k].opcode->mnemonic == TILEGX_OPC_FNOP)
- continue;
-
- display_insn(&decode[k]);
-
- if (--n > 0)
- vex_printf("; ");
- }
-
- if (bundled > 1)
- vex_printf(" }");
-
- vex_printf("\n");
- }
- return count;
-}
-
-static UInt iregNo ( HReg r )
-{
- UInt n;
- vassert(hregClass(r) == HRcInt64);
- vassert(!hregIsVirtual(r));
- n = hregEncoding(r);
- vassert(n <= 63);
- return n;
-}
-
-static UChar *doAMode_IR ( UChar * p, UInt opc1, UInt rSD, TILEGXAMode * am )
-{
- UInt rA;
- vassert(am->tag == GXam_IR);
-
- rA = iregNo(am->GXam.IR.base);
-
- if (opc1 == TILEGX_OPC_ST1 || opc1 == TILEGX_OPC_ST2 ||
- opc1 == TILEGX_OPC_ST4 || opc1 == TILEGX_OPC_ST) {
- if ( am->GXam.IR.index ) {
- /* r51 is reserved scratch registers. */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3,
- 51, rA, am->GXam.IR.index));
- /* store rSD to address in r51 */
- p = mkInsnBin(p, mkTileGxInsn(opc1, 2, 51, rSD));
- } else {
- /* store rSD to address in rA */
- p = mkInsnBin(p, mkTileGxInsn(opc1, 2, rA, rSD));
- }
- } else {
- if ( am->GXam.IR.index ) {
- /* r51 is reserved scratch registers. */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3,
- 51, rA, am->GXam.IR.index));
- /* load from address in r51 to rSD. */
- p = mkInsnBin(p, mkTileGxInsn(opc1, 2, rSD, 51));
- } else {
- /* load from address in rA to rSD. */
- p = mkInsnBin(p, mkTileGxInsn(opc1, 2, rSD, rA));
- }
- }
- return p;
-}
-
-/* Generate a machine-word sized load or store using exact 2 bundles.
- Simplified version of the GXin_Load and GXin_Store cases below. */
-static UChar* do_load_or_store_machine_word ( UChar* p, Bool isLoad, UInt reg,
- TILEGXAMode* am )
-{
- UInt rA = iregNo(am->GXam.IR.base);
-
- if (am->tag != GXam_IR)
- vpanic(__func__);
-
- if (isLoad) /* load */ {
- /* r51 is reserved scratch registers. */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3,
- 51, rA, am->GXam.IR.index));
- /* load from address in r51 to rSD. */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_LD, 2, reg, 51));
- } else /* store */ {
- /* r51 is reserved scratch registers. */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3,
- 51, rA, am->GXam.IR.index));
- /* store rSD to address in r51 */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ST, 2, 51, reg));
- }
- return p;
-}
-
-/* Load imm to r_dst */
-static UChar *mkLoadImm ( UChar * p, UInt r_dst, ULong imm )
-{
- vassert(r_dst < 0x40);
-
- if (imm == 0)
- {
- /* A special case, use r63 - zero register. */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_MOVE, 2, r_dst, 63));
- }
- else if (imm >= 0xFFFFFFFFFFFF8000ULL || imm < 0x8000)
- {
- /* only need one 16-bit sign-extendable movli instructon. */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_MOVELI, 2,
- r_dst, imm & 0xFFFF));
-
- }
- else if (imm >= 0xFFFFFFFF80000000ULL || imm < 0x80000000ULL)
- {
- /* Sign-extendable moveli and a shl16insli */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_MOVELI, 2,
- r_dst,
- (imm >> 16) & 0xFFFF));
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHL16INSLI, 3,
- r_dst, r_dst,
- (imm & 0xFFFF)));
-
- }
- else
- {
- /* A general slower and rare case, use 4 instructions/bundles:
- moveli r_dst, imm[63:48]
- shl16insli r_dst, imm[47:32]
- shl16insli r_dst, imm[31:16]
- shl16insli r_dst, imm[15: 0]
- */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_MOVELI, 2,
- r_dst,
- (imm >> 48) & 0xFFFF));
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHL16INSLI, 3,
- r_dst, r_dst,
- (imm >> 32) & 0xFFFF));
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHL16INSLI, 3,
- r_dst, r_dst,
- (imm >> 16) & 0xFFFF));
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHL16INSLI, 3,
- r_dst, r_dst,
- imm & 0xFFFF));
- }
- return p;
-}
-
-/* Load imm to r_dst using exact 4 bundles. A special case of above
- mkLoadImm(...). */
-static UChar *mkLoadImm_EXACTLY4 ( UChar * p, UInt r_dst, ULong imm )
-{
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_MOVELI, 2,
- r_dst,
- (imm >> 48) & 0xFFFF));
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHL16INSLI, 3,
- r_dst, r_dst,
- (imm >> 32) & 0xFFFF));
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHL16INSLI, 3,
- r_dst, r_dst,
- (imm >> 16) & 0xFFFF));
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHL16INSLI, 3,
- r_dst, r_dst,
- (imm) & 0xFFFF));
- return p;
-}
-
-/* Move r_dst to r_src */
-static UChar *mkMoveReg ( UChar * p, UInt r_dst, UInt r_src )
-{
- vassert(r_dst < 0x40);
- vassert(r_src < 0x40);
-
- if (r_dst != r_src) {
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_MOVE, 2,
- r_dst, r_src));
- }
- return p;
-}
-
-/* Emit an instruction into buf and return the number of bytes used.
- Note that buf is not the insn's final place, and therefore it is
- imperative to emit position-independent code. */
-Int emit_TILEGXInstr ( Bool* is_profInc,
- UChar* buf,
- Int nbuf,
- TILEGXInstr* i,
- Bool mode64,
- VexEndness endness_host,
- void* disp_cp_chain_me_to_slowEP,
- void* disp_cp_chain_me_to_fastEP,
- void* disp_cp_xindir,
- void* disp_cp_xassisted )
-{
- Int instr_bytes = 0;
- UChar *p = &buf[0];
- UChar *ptmp = p;
- vassert(nbuf >= 32);
- vassert(!((Addr)p & 0x7));
- vassert (mode64);
-
- switch (i->tag) {
- case GXin_MovCond: {
-
- TILEGXRH *srcR = i->GXin.MovCond.srcR;
- UInt condR = iregNo(i->GXin.MovCond.condR);
- UInt dst = iregNo(i->GXin.MovCond.dst);
-
- UInt srcL = iregNo(i->GXin.MovCond.srcL);
-
- if (i->GXin.MovCond.cond == TILEGXcc_EZ) {
- if (srcR->tag == GXrh_Reg) {
- p = mkMoveReg(p, dst, iregNo(srcR->GXrh.Reg.reg));
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CMOVEQZ, 3,
- dst, condR, srcL));
- } else {
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_MOVELI, 2,
- dst, srcR->GXrh.Imm.imm16));
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CMOVEQZ, 3,
- dst, condR, srcL));
- }
- } else {
- vassert(0);
- }
-
- goto done;
- }
- case GXin_LI:
-
- // Tilegx, load literal
- p = mkLoadImm(p, iregNo(i->GXin.LI.dst), i->GXin.LI.imm);
- goto done;
-
- case GXin_Alu: {
- TILEGXRH *srcR = i->GXin.Alu.srcR;
- Bool immR = toBool(srcR->tag == GXrh_Imm);
- UInt r_dst = iregNo(i->GXin.Alu.dst);
- UInt r_srcL = iregNo(i->GXin.Alu.srcL);
- UInt r_srcR = immR ? (-1) /*bogus */ : iregNo(srcR->GXrh.Reg.reg);
-
- switch (i->GXin.Alu.op) {
- /*GXalu_ADD, GXalu_SUB, GXalu_AND, GXalu_OR, GXalu_NOR, GXalu_XOR */
- case GXalu_ADD:
- if (immR) {
- vassert(srcR->GXrh.Imm.imm16 != 0x8000);
- if (srcR->GXrh.Imm.syned)
- /* addi */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3,
- r_dst, r_srcL,
- srcR->GXrh.Imm.imm16));
- else
- /* addiu, use shil16insli for tilegx */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHL16INSLI, 3,
- r_dst, 63,
- srcR->GXrh.Imm.imm16));
- } else {
- /* addu */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADD, 3,
- r_dst, r_srcL,
- r_srcR));
- }
- break;
- case GXalu_SUB:
- if (immR) {
- /* addi , but with negated imm */
- vassert(srcR->GXrh.Imm.syned);
- vassert(srcR->GXrh.Imm.imm16 != 0x8000);
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3,
- r_dst, r_srcL,
- -srcR->GXrh.Imm.imm16));
- } else {
- /* subu */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SUB, 3,
- r_dst, r_srcL,
- r_srcR));
- }
- break;
- case GXalu_AND:
- if (immR) {
- /* andi */
- vassert((srcR->GXrh.Imm.imm16 >> 8 == 0) ||
- (srcR->GXrh.Imm.imm16 >> 8 == 0xFF));
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ANDI, 3,
- r_dst, r_srcL,
- srcR->GXrh.Imm.imm16));
-
- } else {
- /* and */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_AND, 3,
- r_dst, r_srcL,
- r_srcR));
- }
- break;
- case GXalu_OR:
- if (immR) {
- /* ori */
- vassert((srcR->GXrh.Imm.imm16 >> 8 == 0) ||
- (srcR->GXrh.Imm.imm16 >> 8 == 0xFF));
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ORI, 3,
- r_dst, r_srcL,
- srcR->GXrh.Imm.imm16));
- } else {
- /* or */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_OR, 3,
- r_dst, r_srcL,
- r_srcR));
- }
- break;
- case GXalu_NOR:
- /* nor */
- vassert(!immR);
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_NOR, 3,
- r_dst, r_srcL,
- r_srcR));
- break;
- case GXalu_XOR:
- if (immR) {
- /* xori */
- vassert(srcR->GXrh.Imm.syned);
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_XORI, 3,
- r_dst, r_srcL,
- srcR->GXrh.Imm.imm16));
- } else {
- /* xor */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_XOR, 3,
- r_dst, r_srcL,
- r_srcR));
- }
- break;
-
- default:
- goto bad;
- }
- goto done;
- }
-
- case GXin_Shft: {
- TILEGXRH *srcR = i->GXin.Shft.srcR;
- Bool sz32 = i->GXin.Shft.sz32;
- Bool immR = toBool(srcR->tag == GXrh_Imm);
- UInt r_dst = iregNo(i->GXin.Shft.dst);
- UInt r_srcL = iregNo(i->GXin.Shft.srcL);
- UInt r_srcR = immR ? (-1) /*bogus */ : iregNo(srcR->GXrh.Reg.reg);
-
- switch (i->GXin.Shft.op) {
- case GXshft_SLL:
- if (sz32) {
- if (immR) {
- UInt n = srcR->GXrh.Imm.imm16;
- vassert(n >= 0 && n < 64);
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHLXI, 3,
- r_dst, r_srcL,
- srcR->GXrh.Imm.imm16));
- } else {
- /* shift variable */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHLX, 3,
- r_dst, r_srcL,
- r_srcR));
- }
- } else {
- if (immR) {
- UInt n = srcR->GXrh.Imm.imm16;
- vassert(n >= 0 && n < 64);
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHLI, 3,
- r_dst, r_srcL,
- srcR->GXrh.Imm.imm16));
- } else {
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHL, 3,
- r_dst, r_srcL,
- r_srcR));
- }
- }
- break;
-
- case GXshft_SLL8x8:
- if (immR) {
- UInt n = srcR->GXrh.Imm.imm16;
- vassert(n >= 0 && n < 64);
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_V1SHLI, 3,
- r_dst, r_srcL,
- srcR->GXrh.Imm.imm16));
- } else {
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_V1SHL, 3,
- r_dst, r_srcL,
- r_srcR));
- }
- break;
-
- case GXshft_SRL8x8:
- if (immR) {
- UInt n = srcR->GXrh.Imm.imm16;
- vassert(n >= 0 && n < 64);
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_V1SHRUI, 3,
- r_dst, r_srcL,
- srcR->GXrh.Imm.imm16));
- } else {
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_V1SHRU, 3,
- r_dst, r_srcL,
- r_srcR));
- }
- break;
-
- case GXshft_SRL:
- if (sz32) {
- // SRL, SRLV
- if (immR) {
- UInt n = srcR->GXrh.Imm.imm16;
- vassert(n >= 0 && n < 32);
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHRUXI, 3,
- r_dst, r_srcL,
- srcR->GXrh.Imm.imm16));
- } else {
- /* shift variable */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHRUX, 3,
- r_dst, r_srcL,
- r_srcR));
- }
- } else {
- // DSRL, DSRL32, DSRLV
- if (immR) {
- UInt n = srcR->GXrh.Imm.imm16;
- vassert((n >= 0 && n < 64));
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHRUI, 3,
- r_dst, r_srcL,
- srcR->GXrh.Imm.imm16));
- } else {
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHRU, 3,
- r_dst, r_srcL,
- r_srcR));
- }
- }
- break;
-
- case GXshft_SRA:
- if (sz32) {
- // SRA, SRAV
- if (immR) {
- UInt n = srcR->GXrh.Imm.imm16;
- vassert(n >= 0 && n < 64);
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHRSI, 3,
- r_dst, r_srcL,
- srcR->GXrh.Imm.imm16));
-
- } else {
- /* shift variable */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHRS, 3,
- r_dst, r_srcL,
- r_srcR));
- }
- } else {
- // DSRA, DSRA32, DSRAV
- if (immR) {
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHRSI, 3,
- r_dst, r_srcL,
- srcR->GXrh.Imm.imm16));
- } else {
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHRS, 3,
- r_dst, r_srcL,
- r_srcR));
- }
- }
- break;
-
- default:
- goto bad;
- }
-
- goto done;
- }
-
- case GXin_Unary: {
- UInt r_dst = iregNo(i->GXin.Unary.dst);
- UInt r_src = iregNo(i->GXin.Unary.src);
-
- switch (i->GXin.Unary.op) {
- /* GXun_CLZ, GXun_NOP */
- case GXun_CLZ: //clz
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CLZ, 2,
- r_dst, r_src));
- break;
- case GXun_CTZ: //ctz
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CTZ, 2,
- r_dst, r_src));
- break;
-
- case GXun_NOP:
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_NOP, 0));
- break;
- }
- goto done;
- }
-
- case GXin_Cmp: {
-
- Bool syned = i->GXin.Cmp.syned;
- UInt r_srcL = iregNo(i->GXin.Cmp.srcL);
- UInt r_srcR = iregNo(i->GXin.Cmp.srcR);
- UInt r_dst = iregNo(i->GXin.Cmp.dst);
-
- switch (i->GXin.Cmp.cond) {
- case TILEGXcc_EQ:
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CMPEQ, 3,
- r_dst, r_srcL,
- r_srcR));
-
- break;
-
- case TILEGXcc_NE:
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CMPNE, 3,
- r_dst, r_srcL,
- r_srcR));
-
- break;
- case TILEGXcc_LT:
- /* slt r_dst, r_srcL, r_srcR */
-
- if (syned)
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CMPLTS, 3,
- r_dst, r_srcL,
- r_srcR));
- else
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CMPLTU, 3,
- r_dst, r_srcL,
- r_srcR));
-
- break;
- case TILEGXcc_LO:
- /* sltu r_dst, r_srcL, r_srcR */
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CMPLTU, 3,
- r_dst, r_srcL,
- r_srcR));
-
- break;
- case TILEGXcc_LE:
- if (syned)
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CMPLES, 3,
- r_dst, r_srcL,
- r_srcR));
- else
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CMPLEU, 3,
- r_dst, r_srcL,
- r_srcR));
- break;
- case TILEGXcc_LS:
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CMPLTU, 3,
- r_dst, r_srcL,
- r_srcR));
- break;
- default:
- goto bad;
- }
- goto done;
- }
-
- case GXin_CmpI: {
-
- TILEGXRH *srcR = i->GXin.CmpI.srcR;
- Bool immR = toBool(srcR->tag == GXrh_Imm);
- UInt r_dst = iregNo(i->GXin.CmpI.dst);
- UInt r_srcL = iregNo(i->GXin.CmpI.srcL);
- UInt r_srcR = immR ? (-1) /*bogus */ : iregNo(srcR->GXrh.Reg.reg);
-
- switch (i->GXin.CmpI.cond) {
- case TILEGXcc_EQ8x8:
- if (immR) {
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_V1CMPEQI, 3,
- r_dst, r_srcL,
- srcR->GXrh.Imm.imm16));
- } else {
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_V1CMPEQ, 3,
- r_dst, r_srcL,
- r_srcR));
- }
- break;
-
- case TILEGXcc_NE8x8:
- if (immR) {
- vassert(0);
- } else {
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_V1CMPNE, 3,
- r_dst, r_srcR,
- r_srcL));
- }
- break;
- default:
- vassert(0);
- }
- goto done;
- break;
- }
-
- case GXin_Bf: {
-
- /* Bit Field */
- UInt r_dst = iregNo(i->GXin.Bf.dst);
- UInt r_src = iregNo(i->GXin.Bf.src);
- UInt Start = i->GXin.Bf.Start;
- UInt End = i->GXin.Bf.End;
-
- switch (i->GXin.Bf.op) {
- case GXbf_EXTS:
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_BFEXTS, 4,
- r_dst, r_src,
- Start, End));
-
- break;
- case GXbf_EXTU:
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_BFEXTU, 4,
- r_dst, r_src,
- Start, End));
-
- break;
- case GXbf_INS:
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_BFINS, 4,
- r_dst, r_src,
- Start, End));
-
- break;
- default:
- vassert(0);
- }
- goto done;
- break;
- }
-
- case GXin_Acas: {
-
- /* Atomic */
- UInt sz = i->GXin.Acas.sz;
- UInt old = iregNo(i->GXin.Acas.old);
- UInt addr= iregNo(i->GXin.Acas.addr);
- UInt new = iregNo(i->GXin.Acas.new);
-
- switch (i->GXin.Acas.op) {
- case GXacas_CMPEXCH:
- {
- UInt exp = iregNo(i->GXin.Acas.exp);
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_MTSPR, 2,
- 0x2780, exp));
- if (sz == 8)
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CMPEXCH, 3,
- old, addr, new));
- else
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CMPEXCH4, 3,
- old, addr, new));
- }
- break;
-
- case GXacas_EXCH:
- if (sz == 8)
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_EXCH, 3,
- old, addr, new));
- else
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_EXCH4, 3,
- old, addr, new));
- break;
-
- case GXacas_FetchAnd:
- if (sz == 8)
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_FETCHAND, 3,
- old, addr, new));
- else
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_FETCHAND4, 3,
- old, addr, new));
- break;
-
- case GXacas_FetchAdd:
- if (sz == 8)
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_FETCHADD, 3,
- old, addr, new));
- else
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_FETCHADD4, 3,
- old, addr, new));
- break;
-
- case GXacas_FetchAddgez:
- if (sz == 8)
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_FETCHADDGEZ, 3,
- old, addr, new));
- else
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_FETCHADDGEZ4, 3,
- old, addr, new));
- break;
-
- case GXacas_FetchOr:
- if (sz == 8)
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_FETCHOR, 3,
- old, addr, new));
- else
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_FETCHOR4, 3,
- old, addr, new));
- break;
-
- default: vassert(0);
- }
- goto done;
- break;
- }
-
- case GXin_Mul: {
-
- /* Multiplication */
- Bool syned = i->GXin.Mul.syned;
- Bool widening = i->GXin.Mul.widening;
- Bool sz32 = i->GXin.Mul.sz32;
- UInt r_srcL = iregNo(i->GXin.Mul.srcL);
- UInt r_srcR = iregNo(i->GXin.Mul.srcR);
- UInt r_dst = iregNo(i->GXin.Mul.dst);
-
- vassert(widening); // always widen.
- vassert(!sz32); // always be 64 bits.
-
- if (syned) {
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_MUL_LS_LS, 3,
- r_dst, r_srcL, r_srcR));
- } else {
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_MUL_LU_LU, 3,
- r_dst, r_srcL, r_srcR));
- }
- goto done;
- }
-
- case GXin_Call: {
-
- /* Function Call. */
- TILEGXCondCode cond = i->GXin.Call.cond;
- UInt r_dst = 11; /* using r11 as address temporary */
-
- /* jump over the following insns if conditional. */
- if (cond != TILEGXcc_AL) {
- /* jmp fwds if !condition */
- /* don't know how many bytes to jump over yet...
- make space for a jump instruction + nop!!! and fill in later. */
- ptmp = p; /* fill in this bit later */
- p += 8;
- }
-
- /* load target to r_dst */
- p = mkLoadImm(p, r_dst, i->GXin.Call.target);
-
- /* jalr %r_dst */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_JALRP, 1,
- r_dst));
-
- /* Fix up the conditional jump, if there was one. */
- if (cond != TILEGXcc_AL) {
- UInt r_src = iregNo(i->GXin.Call.src);
- Int delta = p - ptmp;
-
- vassert(cond == TILEGXcc_EQ);
-
- ptmp = mkInsnBin(ptmp, mkTileGxInsn(TILEGX_OPC_BEQZ, 2,
- r_src, delta / 8));
- }
- goto done;
- }
-
- case GXin_XDirect: {
- /* NB: what goes on here has to be very closely coordinated
- with the chainXDirect_TILEGX and unchainXDirect_TILEGX below. */
- /* We're generating chain-me requests here, so we need to be
- sure this is actually allowed -- no-redir translations
- can't use chain-me's. Hence: */
- vassert(disp_cp_chain_me_to_slowEP != NULL);
- vassert(disp_cp_chain_me_to_fastEP != NULL);
-
- /* Use ptmp for backpatching conditional jumps. */
- ptmp = NULL;
-
- /* First, if this is conditional, create a conditional
- jump over the rest of it. Or at least, leave a space for
- it that we will shortly fill in. */
- if (i->GXin.XDirect.cond != TILEGXcc_AL) {
- vassert(i->GXin.XDirect.cond != TILEGXcc_NV);
- ptmp = p;
- p += 24;
- }
-
- /* Update the guest PC. */
- /* move r11, dstGA */
- /* st amPC, r11 */
- p = mkLoadImm_EXACTLY4(p, /*r*/ 11, (ULong)i->GXin.XDirect.dstGA);
-
- p = do_load_or_store_machine_word(p, False /*!isLoad*/ , /*r*/ 11,
- i->GXin.XDirect.amPC);
-
- /* --- FIRST PATCHABLE BYTE follows --- */
- /* VG_(disp_cp_chain_me_to_{slowEP,fastEP}) (where we're
- calling to) backs up the return address, so as to find the
- address of the first patchable byte. So: don't change the
- number of instructions (3) below. */
- /* move r9, VG_(disp_cp_chain_me_to_{slowEP,fastEP}) */
- /* jr r11 */
- void* disp_cp_chain_me
- = i->GXin.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP
- : disp_cp_chain_me_to_slowEP;
- p = mkLoadImm_EXACTLY4(p, /*r*/ 11,
- (Addr)disp_cp_chain_me);
- /* jalr r11 */
- /* nop */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_JALR, 1, 11));
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_NOP, 0));
-
- /* --- END of PATCHABLE BYTES --- */
-
- /* Fix up the conditional jump, if there was one. */
- if (i->GXin.XDirect.cond != TILEGXcc_AL) {
- Int delta = p - ptmp;
- delta = delta / 8 - 3;
-
- /* ld r11, COND_OFFSET(GuestSP=r50)
- beqz r11, delta
- */
- ptmp = mkInsnBin(ptmp, mkTileGxInsn(TILEGX_OPC_ADDLI, 3,
- 11, 50, COND_OFFSET()));
- ptmp = mkInsnBin(ptmp, mkTileGxInsn(TILEGX_OPC_LD, 2,
- 11, 11));
-
- ptmp = mkInsnBin(ptmp, mkTileGxInsn(TILEGX_OPC_BEQZ, 2,
- 11, delta));
-
- }
- goto done;
- }
-
- case GXin_XIndir: {
- /* We're generating transfers that could lead indirectly to a
- chain-me, so we need to be sure this is actually allowed --
- no-redir translations are not allowed to reach normal
- translations without going through the scheduler. That means
- no XDirects or XIndirs out from no-redir translations.
- Hence: */
- vassert(disp_cp_xindir != NULL);
-
- /* Use ptmp for backpatching conditional jumps. */
- ptmp = NULL;
-
- /* First off, if this is conditional, create a conditional
- jump over the rest of it. */
- if (i->GXin.XIndir.cond != TILEGXcc_AL) {
- vassert(i->GXin.XIndir.cond != TILEGXcc_NV);
- ptmp = p;
- p += 24;
- }
-
- /* Update the guest PC. */
- /* st amPC, dstGA */
- p = do_load_or_store_machine_word(p, False /*!isLoad*/ ,
- iregNo(i->GXin.XIndir.dstGA),
- i->GXin.XIndir.amPC);
-
- /* move r11, VG_(disp_cp_xindir), 4 bundles. */
- /* jalr r11 */
- /* nop */
- p = mkLoadImm_EXACTLY4(p, /*r*/ 11,
- (Addr)disp_cp_xindir);
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_JALR, 1, 11));
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_NOP, 0));
-
- /* Fix up the conditional jump, if there was one. */
- if (i->GXin.XIndir.cond != TILEGXcc_AL) {
- Int delta = p - ptmp;
- delta = delta / 8 - 3;
- vassert(delta > 0 && delta < 40);
-
- /* ld r11, COND_OFFSET($GuestSP)
- beqz r11, delta */
-
- ptmp = mkInsnBin(ptmp, mkTileGxInsn(TILEGX_OPC_ADDLI, 3,
- 11, 50, COND_OFFSET()));
- ptmp = mkInsnBin(ptmp, mkTileGxInsn(TILEGX_OPC_LD, 2,
- 11, 11));
- ptmp = mkInsnBin(ptmp, mkTileGxInsn(TILEGX_OPC_BEQZ, 2,
- 11, delta));
- }
- goto done;
- }
-
- case GXin_XAssisted: {
- /* First off, if this is conditional, create a conditional jump
- over the rest of it. Or at least, leave a space for it that
- we will shortly fill in. */
- ptmp = NULL;
- if (i->GXin.XAssisted.cond != TILEGXcc_AL) {
- vassert(i->GXin.XAssisted.cond != TILEGXcc_NV);
- ptmp = p;
- p += 24;
- }
-
- /* Update the guest PC. */
- /* st amPC, dstGA */
- p = do_load_or_store_machine_word(p, False /*!isLoad*/ ,
- iregNo(i->GXin.XIndir.dstGA),
- i->GXin.XIndir.amPC);
-
- UInt trcval = 0;
- switch (i->GXin.XAssisted.jk) {
- case Ijk_ClientReq: trcval = VEX_TRC_JMP_CLIENTREQ; break;
- case Ijk_Sys_syscall: trcval = VEX_TRC_JMP_SYS_SYSCALL; break;
- case Ijk_Yield: trcval = VEX_TRC_JMP_YIELD; break;
- case Ijk_EmWarn: trcval = VEX_TRC_JMP_EMWARN; break;
- case Ijk_EmFail: trcval = VEX_TRC_JMP_EMFAIL; break;
- case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break;
- case Ijk_InvalICache: trcval = VEX_TRC_JMP_INVALICACHE; break;
- case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break;
- case Ijk_SigILL: trcval = VEX_TRC_JMP_SIGILL; break;
- case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break;
- case Ijk_SigBUS: trcval = VEX_TRC_JMP_SIGBUS; break;
- case Ijk_SigFPE_IntDiv: trcval = VEX_TRC_JMP_SIGFPE_INTDIV; break;
- case Ijk_SigFPE_IntOvf: trcval = VEX_TRC_JMP_SIGFPE_INTOVF; break;
- case Ijk_Boring: trcval = VEX_TRC_JMP_BORING; break;
- case Ijk_Ret:
- {
- /* Tilegx "iret" instruction. */
- trcval = VEX_TRC_JMP_BORING;
- /* Interrupt return "iret", setup the jump address into EX_CONTRXT_0_0.
- Read context_0_1 from guest_state */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3,
- 51, 50, OFFSET_EX1));
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_LD, 2,
- 11, 51));
- /* Write into host cpu's context_0_1 spr. */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_MTSPR, 2,
- 0x2581, 11));
- /* Read context_0_0 from guest_state */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3,
- 51, 50, OFFSET_EX0));
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_LD, 2,
- 11, 51));
- /* Write into host cpu's context_0_0 spr */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_MTSPR, 2,
- 0x2580, 11));
- /* Update the guest PC so branch to the iret target address
- in EX_CONTEXT_0. */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3,
- 51, 50, 512));
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ST, 2,
- 51, 11));
- }
- break;
- /* We don't expect to see the following being assisted.
- case Ijk_Call:
- fallthrough */
- default:
- ppIRJumpKind(i->GXin.XAssisted.jk);
- vpanic("emit_TILEGXInstr.GXin_XAssisted: unexpected jump kind");
- }
- vassert(trcval != 0);
-
- /* moveli r50, trcval */
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3, 50, 63, trcval));
-
- /* move r11, VG_(disp_cp_xassisted) */
-
- p = mkLoadImm_EXACTLY4(p, /*r*/ 11,
- (Addr)disp_cp_xassisted);
- /* jalr r11
- nop */
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_JALR, 1, 11));
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_NOP, 0));
-
- /* Fix up the conditional jump, if there was one. */
- if (i->GXin.XAssisted.cond != TILEGXcc_AL) {
- Int delta = p - ptmp;
- delta = delta / 8 - 3;
- vassert(delta > 0 && delta < 40);
-
- /* ld r11, COND_OFFSET($GuestSP)
- beqz r11, delta
- nop */
-
- ptmp = mkInsnBin(ptmp, mkTileGxInsn(TILEGX_OPC_ADDLI, 3,
- 11, 50, COND_OFFSET()));
- ptmp = mkInsnBin(ptmp, mkTileGxInsn(TILEGX_OPC_LD, 2,
- 11, 11));
- ptmp = mkInsnBin(ptmp, mkTileGxInsn(TILEGX_OPC_BEQZ, 2,
- 11, delta));
- }
- goto done;
- }
-
- case GXin_EvCheck: {
- /* We generate:
- ld r11, amCounter
- addi r11, r11, -1
- st amCounter, r11
- bgez r11, nofail
- ld r11, amFailAddr
- jalr r11
- nop
- nofail:
- */
- UChar* p0 = p;
- /* ld r11, amCounter */
- p = do_load_or_store_machine_word(p, True /*isLoad*/ , /*r*/ 11,
- i->GXin.EvCheck.amCounter);
-
- /* addi r11,r11,-1 */
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDI, 3,
- 11, 11, -1));
-
- /* st amCounter, 11 */
- p = do_load_or_store_machine_word(p, False /*!isLoad*/ , /*r*/ 11,
- i->GXin.EvCheck.amCounter);
-
- /* Reserve a bundle, fill it after the do_load_or_store_machine_word.
- since we are not sure how many bundles it takes. */
- UChar* p1 = p;
- p += 8;
- /* bgez t9, nofail */
-
- /* lw/ld r9, amFailAddr */
- p = do_load_or_store_machine_word(p, True /*isLoad*/ , /*r*/ 11,
- i->GXin.EvCheck.amFailAddr);
-
- mkInsnBin(p1, mkTileGxInsn(TILEGX_OPC_BGEZ, 2,
- 11, 2 + (p - p1) / 8));
-
- /* jalr r11 */
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_JALR, 1, 11));
-
- /* nop */
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_NOP, 0));
-
- /* nofail: */
-
- /* Crosscheck */
- vassert(evCheckSzB_TILEGX() == (UChar*)p - (UChar*)p0);
- goto done;
- }
-
- case GXin_ProfInc: {
- /* Generate a code template to increment a memory location whose
- address will be known later as an immediate value. This code
- template will be patched once the memory location is known.
- For now we do this with address == 0x65556555. */
- /* 64-bit:
- move r11, 0x6555655565556555ULL
- ld r51, r11
- addi r51, r51, 1
- st r11, r51
- */
-
- /* move r11, 0x6555655565556555ULL */
- p = mkLoadImm_EXACTLY4(p, /*r*/ 11, 0x6555655565556555ULL);
-
- /* ld r51, r11 */
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_LD, 2, 51, 11));
-
- /* addi r51, r51, 1 */
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDI, 3, 51, 51, 1));
-
- /* st r11, r51 */
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ST, 2, 11, 51));
-
- /* Tell the caller .. */
- vassert(!(*is_profInc));
- *is_profInc = True;
- goto done;
- }
-
- case GXin_Load: {
- TILEGXAMode *am_addr = i->GXin.Load.src;
- if (am_addr->tag == GXam_IR) {
- UInt r_dst = iregNo(i->GXin.Load.dst);
- UInt opc, sz = i->GXin.Load.sz;
- if ((sz == 4 || sz == 8)) {
- /* should be guaranteed to us by iselWordExpr_AMode */
- vassert(0 == (am_addr->GXam.IR.index & 3));
- }
-
- // Note: Valgrind memory load has no sign-extend. We extend explicitly.
- switch (sz) {
- case 1:
- opc = TILEGX_OPC_LD1U;
- break;
- case 2:
- opc = TILEGX_OPC_LD2U;
- break;
- case 4:
- opc = TILEGX_OPC_LD4U;
- break;
- case 8:
- opc = TILEGX_OPC_LD;
- break;
- default:
- goto bad;
- }
-
- p = doAMode_IR(p, opc, r_dst, am_addr);
- goto done;
-
- }
- }
-
- case GXin_Store: {
- TILEGXAMode *am_addr = i->GXin.Store.dst;
- if (am_addr->tag == GXam_IR) {
- UInt r_src = iregNo(i->GXin.Store.src);
- UInt opc, sz = i->GXin.Store.sz;
- switch (sz) {
- case 1:
- opc = TILEGX_OPC_ST1;
- break;
- case 2:
- opc = TILEGX_OPC_ST2;
- break;
- case 4:
- opc = TILEGX_OPC_ST4;
- break;
- case 8:
- opc = TILEGX_OPC_ST;
- break;
- default:
- goto bad;
- }
-
- p = doAMode_IR(p, opc, r_src, am_addr);
- goto done;
- } else {
- vassert(0);
- }
- }
-
- case GXin_RdWrLR: {
- UInt reg = iregNo(i->GXin.RdWrLR.gpr);
- Bool wrLR = i->GXin.RdWrLR.wrLR;
- if (wrLR)
- p = mkMoveReg(p, 55, reg);
- else
- p = mkMoveReg(p, reg, 55);
- goto done;
- }
-
- default:
- goto bad;
- }
-
- bad:
- vex_printf("\n=> ");
- vpanic("emit_TILEGXInstr");
- /*NOTREACHED*/
-
- done:
- instr_bytes = p - &buf[0];
- /* Instr byte count must be modular of 8. */
- vassert(0 == (instr_bytes & 0x7));
-
- if ( 0) {
- Int k;
- for (k = 0; k < instr_bytes; k += 8)
- decode_and_display((ULong *)(Addr)&buf[k], 1, 0);
- }
-
- /* Limit the JIT size. */
- vassert(instr_bytes <= 256);
- return instr_bytes;
-}
-
-
-Int evCheckSzB_TILEGX ( void )
-{
- UInt kInstrSize = 8;
- return 10*kInstrSize;
-}
-
-VexInvalRange chainXDirect_TILEGX ( VexEndness endness_host,
- void* place_to_chain,
- const void* disp_cp_chain_me_EXPECTED,
- const void* place_to_jump_to,
- Bool mode64 )
-{
- vassert(mode64);
- vassert(endness_host == VexEndnessLE);
- /* What we're expecting to see is:
- move r11, disp_cp_chain_me_to_EXPECTED
- jalr r11
- nop
- viz
- <32 bytes generated by mkLoadImm_EXACTLY4>
- jalr r11
- nop
- */
- UChar* p = (UChar*)place_to_chain;
- vassert(0 == (7 & (HWord)p));
-
-#ifdef TILEGX_DEBUG
- vex_printf("chainXDirect_TILEGX: disp_cp_chain_me_EXPECTED=%p\n",
- disp_cp_chain_me_EXPECTED);
- decode_and_display(p, 6, p);
-
- vex_printf("chainXDirect_TILEGX: place_to_jump_to=%p\n",
- place_to_jump_to);
-#endif
-
- /* And what we want to change it to is either:
- move r11, place_to_jump_to
- jalr r11
- nop
- viz
- <32 bytes generated by mkLoadImm_EXACTLY4>
- jalr r11
- nop
-
- The replacement has the same length as the original.
- */
-
- p = mkLoadImm_EXACTLY4(p, /*r*/ 11,
- (Addr)place_to_jump_to);
-
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_JALR, 1, 11));
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_NOP, 0));
-
-#ifdef TILEGX_DEBUG
- decode_and_display((UChar*)place_to_chain, 8, place_to_chain);
-#endif
-
- Int len = p - (UChar*)place_to_chain;
- vassert(len == 48); /* stay sane */
- VexInvalRange vir = {(HWord)place_to_chain, len};
- return vir;
-}
-
-VexInvalRange unchainXDirect_TILEGX ( VexEndness endness_host,
- void* place_to_unchain,
- const void* place_to_jump_to_EXPECTED,
- const void* disp_cp_chain_me,
- Bool mode64 )
-{
- vassert(mode64);
- vassert(endness_host == VexEndnessLE);
- /* What we're expecting to see is:
- move r11, place_to_jump_to_EXPECTED
- jalr r11
- nop
- viz
- <32 bytes generated by mkLoadImm_EXACTLY4>
- jalr r11
- nop
- */
- UChar* p = (UChar*)place_to_unchain;
- vassert(0 == (7 & (HWord)p));
-
- /* And what we want to change it to is:
- move r11, disp_cp_chain_me
- jalr r11
- nop
- viz
- <32 bytes generated by mkLoadImm_EXACTLY4>
- jalr r11
- nop
- The replacement has the same length as the original.
- */
- p = mkLoadImm_EXACTLY4(p, /*r*/ 11,
- (Addr)disp_cp_chain_me);
-
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_JALR, 1, 11));
-
- p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_NOP, 0));
-
- Int len = p - (UChar*)place_to_unchain;
- vassert(len == 48); /* stay sane */
- VexInvalRange vir = {(HWord)place_to_unchain, len};
- return vir;
-}
-
-/* Patch the counter address into a profile inc point, as previously
- created by the GXin_ProfInc case for emit_TILEGXInstr. */
-VexInvalRange patchProfInc_TILEGX ( VexEndness endness_host,
- void* place_to_patch,
- const ULong* location_of_counter,
- Bool mode64 )
-{
- vassert(mode64);
- vassert(endness_host == VexEndnessLE);
- UChar* p = (UChar*)place_to_patch;
- vassert(0 == (7 & (HWord)p));
-
- p = mkLoadImm_EXACTLY4(p, /*r*/ 11,
- (Addr)location_of_counter);
-
- VexInvalRange vir = {(HWord)p, 32};
- return vir;
-}
-
-/*---------------------------------------------------------------*/
-/*--- end host_tilegx_defs.c ---*/
-/*---------------------------------------------------------------*/
diff --git a/VEX/priv/host_tilegx_defs.h b/VEX/priv/host_tilegx_defs.h
deleted file mode 100644
index 344a440..0000000
--- a/VEX/priv/host_tilegx_defs.h
+++ /dev/null
@@ -1,562 +0,0 @@
-
-/*---------------------------------------------------------------*/
-/*--- begin host_tilegx_defs.h ---*/
-/*---------------------------------------------------------------*/
-
-/*
- This file is part of Valgrind, a dynamic binary instrumentation
- framework.
-
- Copyright (C) 2010-2015 Tilera Corp.
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of the
- License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful, but
- WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
- 02111-1307, USA.
-
- The GNU General Public License is contained in the file COPYING.
-*/
-
- /* Contributed by Zhi-Gang Liu <zliu at tilera dot com> */
-
-#ifndef __VEX_HOST_TILEGX_DEFS_H
-#define __VEX_HOST_TILEGX_DEFS_H
-
-#include "tilegx_disasm.h"
-
-/* Num registers used for function calls */
-#define TILEGX_N_REGPARMS 10
-
-/* --------- Registers. --------- */
-
-/* The usual HReg abstraction.
- There are 56 general purpose regs.
-*/
-
-#define ST_IN static inline
-
-ST_IN HReg hregTILEGX_R30 ( void ) { return mkHReg(False, HRcInt64, 30, 0); }
-ST_IN HReg hregTILEGX_R31 ( void ) { return mkHReg(False, HRcInt64, 31, 1); }
-ST_IN HReg hregTILEGX_R32 ( void ) { return mkHReg(False, HRcInt64, 32, 2); }
-ST_IN HReg hregTILEGX_R33 ( void ) { return mkHReg(False, HRcInt64, 33, 3); }
-ST_IN HReg hregTILEGX_R34 ( void ) { return mkHReg(False, HRcInt64, 34, 4); }
-ST_IN HReg hregTILEGX_R35 ( void ) { return mkHReg(False, HRcInt64, 35, 5); }
-ST_IN HReg hregTILEGX_R36 ( void ) { return mkHReg(False, HRcInt64, 36, 6); }
-ST_IN HReg hregTILEGX_R37 ( void ) { return mkHReg(False, HRcInt64, 37, 7); }
-ST_IN HReg hregTILEGX_R38 ( void ) { return mkHReg(False, HRcInt64, 38, 8); }
-ST_IN HReg hregTILEGX_R39 ( void ) { return mkHReg(False, HRcInt64, 39, 9); }
-
-ST_IN HReg hregTILEGX_R40 ( void ) { return mkHReg(False, HRcInt64, 40, 10); }
-ST_IN HReg hregTILEGX_R41 ( void ) { return mkHReg(False, HRcInt64, 41, 11); }
-ST_IN HReg hregTILEGX_R42 ( void ) { return mkHReg(False, HRcInt64, 42, 12); }
-ST_IN HReg hregTILEGX_R43 ( void ) { return mkHReg(False, HRcInt64, 43, 13); }
-ST_IN HReg hregTILEGX_R44 ( void ) { return mkHReg(False, HRcInt64, 44, 14); }
-ST_IN HReg hregTILEGX_R45 ( void ) { return mkHReg(False, HRcInt64, 45, 15); }
-ST_IN HReg hregTILEGX_R46 ( void ) { return mkHReg(False, HRcInt64, 46, 16); }
-ST_IN HReg hregTILEGX_R47 ( void ) { return mkHReg(False, HRcInt64, 47, 17); }
-ST_IN HReg hregTILEGX_R48 ( void ) { return mkHReg(False, HRcInt64, 48, 18); }
-ST_IN HReg hregTILEGX_R49 ( void ) { return mkHReg(False, HRcInt64, 49, 19); }
-
-ST_IN HReg hregTILEGX_R10 ( void ) { return mkHReg(False, HRcInt64, 10, 20); }
-ST_IN HReg hregTILEGX_R13 ( void ) { return mkHReg(False, HRcInt64, 13, 21); }
-ST_IN HReg hregTILEGX_R14 ( void ) { return mkHReg(False, HRcInt64, 14, 22); }
-ST_IN HReg hregTILEGX_R15 ( void ) { return mkHReg(False, HRcInt64, 15, 23); }
-ST_IN HReg hregTILEGX_R16 ( void ) { return mkHReg(False, HRcInt64, 16, 24); }
-ST_IN HReg hregTILEGX_R17 ( void ) { return mkHReg(False, HRcInt64, 17, 25); }
-ST_IN HReg hregTILEGX_R18 ( void ) { return mkHReg(False, HRcInt64, 18, 26); }
-ST_IN HReg hregTILEGX_R19 ( void ) { return mkHReg(False, HRcInt64, 19, 27); }
-ST_IN HReg hregTILEGX_R20 ( void ) { return mkHReg(False, HRcInt64, 20, 28); }
-
-ST_IN HReg hregTILEGX_R21 ( void ) { return mkHReg(False, HRcInt64, 21, 29); }
-ST_IN HReg hregTILEGX_R22 ( void ) { return mkHReg(False, HRcInt64, 22, 30); }
-ST_IN HReg hregTILEGX_R23 ( void ) { return mkHReg(False, HRcInt64, 23, 31); }
-ST_IN HReg hregTILEGX_R24 ( void ) { return mkHReg(False, HRcInt64, 24, 32); }
-ST_IN HReg hregTILEGX_R25 ( void ) { return mkHReg(False, HRcInt64, 25, 33); }
-ST_IN HReg hregTILEGX_R26 ( void ) { return mkHReg(False, HRcInt64, 26, 34); }
-ST_IN HReg hregTILEGX_R27 ( void ) { return mkHReg(False, HRcInt64, 27, 35); }
-ST_IN HReg hregTILEGX_R28 ( void ) { return mkHReg(False, HRcInt64, 28, 36); }
-ST_IN HReg hregTILEGX_R29 ( void ) { return mkHReg(False, HRcInt64, 29, 37); }
-
-ST_IN HReg hregTILEGX_R0 ( void ) { return mkHReg(False, HRcInt64, 0, 38); }
-ST_IN HReg hregTILEGX_R1 ( void ) { return mkHReg(False, HRcInt64, 1, 39); }
-ST_IN HReg hregTILEGX_R2 ( void ) { return mkHReg(False, HRcInt64, 2, 40); }
-ST_IN HReg hregTILEGX_R3 ( void ) { return mkHReg(False, HRcInt64, 3, 41); }
-ST_IN HReg hregTILEGX_R4 ( void ) { return mkHReg(False, HRcInt64, 4, 42); }
-ST_IN HReg hregTILEGX_R5 ( void ) { return mkHReg(False, HRcInt64, 5, 43); }
-ST_IN HReg hregTILEGX_R6 ( void ) { return mkHReg(False, HRcInt64, 6, 44); }
-ST_IN HReg hregTILEGX_R7 ( void ) { return mkHReg(False, HRcInt64, 7, 45); }
-ST_IN HReg hregTILEGX_R8 ( void ) { return mkHReg(False, HRcInt64, 8, 46); }
-ST_IN HReg hregTILEGX_R9 ( void ) { return mkHReg(False, HRcInt64, 9, 47); }
-
-ST_IN HReg hregTILEGX_R11 ( void ) { return mkHReg(False, HRcInt64, 11, 48); }
-ST_IN HReg hregTILEGX_R12 ( void ) { return mkHReg(False, HRcInt64, 12, 49); }
-ST_IN HReg hregTILEGX_R50 ( void ) { return mkHReg(False, HRcInt64, 50, 50); }
-ST_IN HReg hregTILEGX_R51 ( void ) { return mkHReg(False, HRcInt64, 51, 51); }
-ST_IN HReg hregTILEGX_R52 ( void ) { return mkHReg(False, HRcInt64, 52, 52); }
-ST_IN HReg hregTILEGX_R53 ( void ) { return mkHReg(False, HRcInt64, 53, 53); }
-ST_IN HReg hregTILEGX_R54 ( void ) { return mkHReg(False, HRcInt64, 54, 54); }
-ST_IN HReg hregTILEGX_R55 ( void ) { return mkHReg(False, HRcInt64, 55, 55); }
-ST_IN HReg hregTILEGX_R63 ( void ) { return mkHReg(False, HRcInt64, 63, 56); }
-
-extern void ppHRegTILEGX ( HReg );
-
-#define TILEGXGuestStatePointer() hregTILEGX_R50()
-#define TILEGXStackFramePointer() hregTILEGX_R52()
-#define TILEGXLinkRegister() hregTILEGX_R55()
-#define TILEGXStackPointer() hregTILEGX_R54()
-
-/* r0, r1, r2, r3 ... r9 */
-#define TILEGX_N_ARGREGS 10
-
-/* --------- Condition codes, Tilegx encoding. --------- */
-typedef enum {
- TILEGXcc_EQ = 0, /* equal */
- TILEGXcc_NE = 1, /* not equal */
- TILEGXcc_HS = 2, /* >=u (higher or same) */
- TILEGXcc_LO = 3, /* <u (lower) */
- TILEGXcc_MI = 4, /* minus (negative) */
- TILEGXcc_PL = 5, /* plus (zero or +ve) */
- TILEGXcc_VS = 6, /* overflow */
- TILEGXcc_VC = 7, /* no overflow */
- TILEGXcc_HI = 8, /* >u (higher) */
- TILEGXcc_LS = 9, /* <=u (lower or same) */
- TILEGXcc_GE = 10, /* >=s (signed greater or equal) */
- TILEGXcc_LT = 11, /* <s (signed less than) */
- TILEGXcc_GT = 12, /* >s (signed greater) */
- TILEGXcc_LE = 13, /* <=s (signed less or equal) */
- TILEGXcc_AL = 14, /* always (unconditional) */
- TILEGXcc_NV = 15, /* never (unconditional): */
- TILEGXcc_EQ8x8 = 16,/* V1 equal */
- TILEGXcc_NE8x8 = 17,/* V1 not equal */
- TILEGXcc_EZ = 18, /* equal 0 */
- TILEGXcc_NZ = 19, /* not equal */
-
-} TILEGXCondCode;
-
-/* --------- Memory address expressions (amodes). --------- */
-typedef enum {
- GXam_IR, /* Immediate (signed 16-bit) + Reg */
-} TILEGXAModeTag;
-
-typedef struct {
- TILEGXAModeTag tag;
- union {
- struct {
- HReg base;
- Int index;
- } IR;
- struct {
- HReg base;
- HReg index;
- } RR;
- } GXam;
-} TILEGXAMode;
-
-extern TILEGXAMode *TILEGXAMode_IR ( Int, HReg );
-extern TILEGXAMode *TILEGXAMode_RR ( HReg, HReg );
-extern TILEGXAMode *dopyTILEGXAMode ( TILEGXAMode * );
-extern TILEGXAMode *nextTILEGXAModeFloat ( TILEGXAMode * );
-extern TILEGXAMode *nextTILEGXAModeInt ( TILEGXAMode * );
-extern void ppTILEGXAMode ( const TILEGXAMode * );
-
-/* --------- Operand, which can be a reg or a u16/s16. --------- */
-/* ("RH" == "Register or Halfword immediate") */
-typedef enum {
- GXrh_Imm,
- GXrh_Reg
-} TILEGXRHTag;
-
-typedef struct {
- TILEGXRHTag tag;
- union {
- struct {
- Bool syned;
- UShort imm16;
- } Imm;
- struct {
- HReg reg;
- } Reg;
- } GXrh;
-} TILEGXRH;
-
-extern void ppTILEGXRH ( const TILEGXRH * );
-extern TILEGXRH *TILEGXRH_Imm ( Bool, UShort );
-extern TILEGXRH *TILEGXRH_Reg ( HReg );
-
-/* --------- Reg or imm5 operands --------- */
-typedef enum {
- TILEGXri5_I5 = 7, /* imm5, 1 .. 31 only (no zero!) */
- TILEGXri5_R /* reg */
-} TILEGXRI5Tag;
-
-typedef struct {
- TILEGXRI5Tag tag;
- union {
- struct {
- UInt imm5;
- } I5;
- struct {
- HReg reg;
- } R;
- } TILEGXri5;
-} TILEGXRI5;
-
-extern TILEGXRI5 *TILEGXRI5_I5 ( UInt imm5 );
-extern TILEGXRI5 *TILEGXRI5_R ( HReg );
-
-extern void ppTILEGXRI5 ( const TILEGXRI5 * );
-
-/* --------- Instructions. --------- */
-
-/*Tags for operations*/
-
-/* --------- */
-typedef enum {
- GXun_CLZ,
- GXun_CTZ,
- GXun_NOP,
-} TILEGXUnaryOp;
-
-/* --------- */
-
-typedef enum {
- GXalu_INVALID,
- GXalu_ADD,
- GXalu_SUB,
- GXalu_AND,
- GXalu_OR,
- GXalu_NOR,
- GXalu_XOR,
-} TILEGXAluOp;
-
-/* --------- */
-
-typedef enum {
- GXshft_INVALID,
- GXshft_SLL,
- GXshft_SRL,
- GXshft_SRA,
- GXshft_SLL8x8,
- GXshft_SRL8x8,
-
-} TILEGXShftOp;
-
-
-/* --------- */
-typedef enum {
- GXbf_EXTS,
- GXbf_EXTU,
- GXbf_INS
-} TILEGXBfOp;
-
-/* --------- */
-
-
-/* --------- */
-typedef enum {
- GXacas_CMPEXCH,
- GXacas_EXCH,
- GXacas_FetchAnd,
- GXacas_FetchAdd,
- GXacas_FetchAddgez,
- GXacas_FetchOr,
-} TILEGXAcasOp;
-
-/* --------- */
-
-/* ----- Instruction tags ----- */
-typedef enum {
- GXin_LI, /* load word (32/64-bit) immediate (fake insn) */
- GXin_Alu, /* word add/sub/and/or/xor/nor/others? */
- GXin_Shft, /* word sll/srl/sra */
- GXin_Unary, /* clo, clz, nop, neg */
-
- GXin_Cmp, /* word compare (fake insn) */
- GXin_CmpI,
-
- GXin_Mul, /* widening/non-widening multiply */
-
- GXin_Call, /* call to address in register */
-
- GXin_XDirect, /* direct transfer to GA */
- GXin_XIndir, /* indirect transfer to GA */
- GXin_XAssisted, /* assisted transfer to GA */
- GXin_EvCheck, /* Event check */
- GXin_ProfInc, /* 64-bit profile counter increment */
-
- GXin_RdWrLR, /* Read/Write Link Register */
-
- GXin_Load, /* zero-extending load a 8|16|32|64 bit value from mem */
- GXin_Store, /* store a 8|16|32|64 bit value to mem */
-
- GXin_MovCond,
- GXin_Bf, /* Bitfield operations */
- GXin_Acas, /* Atomic Campare and swap. */
-
-} TILEGXInstrTag;
-
-/*--------- Structure for instructions ----------*/
-/* Destinations are on the LEFT (first operand) */
-
-typedef struct {
- TILEGXInstrTag tag;
- union {
- /* Get a 32/64-bit literal into a register.
- May turn into a number of real insns. */
- struct {
- HReg dst;
- ULong imm;
- } LI;
- /* Integer add/sub/and/or/xor. Limitations:
- - For add, the immediate, if it exists, is a signed 16.
- - For sub, the immediate, if it exists, is a signed 16
- which may not be -32768, since no such instruction
- exists, and so we have to emit addi with +32768, but
- that is not possible.
- - For and/or/xor, the immediate, if it exists,
- is an unsigned 16.
- */
- struct {
- TILEGXAluOp op;
- HReg dst;
- HReg srcL;
- TILEGXRH *srcR;
- } Alu;
-
- struct {
- TILEGXBfOp op;
- HReg dst;
- HReg src;
- UInt Start;
- UInt End;
- } Bf;
-
- struct {
- TILEGXAcasOp op;
- HReg addr;
- HReg exp;
- HReg new;
- HReg old;
- UInt sz;
- } Acas;
-
- /* Integer shl/shr/sar.
- Limitations: the immediate, if it exists,
- is a signed 5-bit value between 1 and 31 inclusive.
- */
- struct {
- TILEGXShftOp op;
- Bool sz32;
- HReg dst;
- HReg srcL;
- TILEGXRH *srcR;
- } Shft;
- /* Clz, Ctz, Clo, nop */
- struct {
- TILEGXUnaryOp op;
- HReg dst;
- HReg src;
- } Unary;
- /* Word compare. Fake instruction, used for basic block ending */
- struct {
- Bool syned;
- Bool sz32;
- HReg dst;
- HReg srcL;
- HReg srcR;
- TILEGXCondCode cond;
- } Cmp;
- struct {
- Bool syned;
- Bool sz32;
- HReg dst;
- HReg srcL;
- TILEGXRH *srcR;
- TILEGXCondCode cond;
- } CmpI;
- struct {
- Bool widening; //True => widening, False => non-widening
- Bool syned; //signed/unsigned - meaningless if widenind = False
- Bool sz32;
- HReg dst;
- HReg srcL;
- HReg srcR;
- } Mul;
- /* Pseudo-insn. Call target (an absolute address), on given
- condition (which could be Mcc_ALWAYS). argiregs indicates
- which of r0 .. r9
- carries argument values for this call,
- using a bit mask (1<<N is set if rN holds an arg, for N in
- 0 .. 9 inclusive).
- If cond is != Mcc_ALWAYS, src is checked.
- Otherwise, unconditional call */
- struct {
- TILEGXCondCode cond;
- Addr64 target;
- ULong argiregs;
- HReg src;
- RetLoc rloc; /* where the return value saved. */
- } Call;
-
- /* Update the guest IP value, then exit requesting to chain
- to it. May be conditional. Urr, use of Addr32 implicitly
- assumes that wordsize(guest) == wordsize(host). */
- struct {
- Addr64 dstGA; /* next guest address */
- TILEGXAMode* amPC; /* amode in guest state for PC */
- TILEGXCondCode cond; /* can be TILEGXcc_AL */
- Bool toFastEP; /* chain to the slow or fast point? */
- } XDirect;
-
- /* Boring transfer to a guest address not known at JIT time.
- Not chainable. May be conditional. */
- struct {
- HReg dstGA;
- TILEGXAMode* amPC;
- TILEGXCondCode cond; /* can be TILEGXcc_AL */
- } XIndir;
-
- /* Assisted transfer to a guest address, most general case.
- Not chainable. May be conditional. */
- struct {
- HReg dstGA;
- TILEGXAMode* amPC;
- TILEGXCondCode cond; /* can be TILEGXcc_AL */
- IRJumpKind jk;
- } XAssisted;
-
- struct {
- TILEGXAMode* amCounter;
- TILEGXAMode* amFailAddr;
- } EvCheck;
-
- struct {
- /* No fields. The address of the counter to inc is
- installed later, post-translation, by patching it in,
- as it is not known at translation time. */
- } ProfInc;
- /* Zero extending loads. Dst size is host word size */
- struct {
- UChar sz; /* 1|2|4|8 */
- HReg dst;
- TILEGXAMode *src;
- } Load;
- /* 64/32/16/8 bit stores */
- struct {
- UChar sz; /* 1|2|4|8 */
- TILEGXAMode *dst;
- HReg src;
- } Store;
- /* Read/Write Link Register */
- struct {
- Bool wrLR;
- HReg gpr;
- } RdWrLR;
- struct {
- HReg dst;
- HReg srcL;
- TILEGXRH *srcR;
- HReg condR;
- TILEGXCondCode cond;
- } MovCond;
- } GXin;
-} TILEGXInstr;
-extern TILEGXInstr *TILEGXInstr_LI ( HReg, ULong );
-extern TILEGXInstr *TILEGXInstr_Alu ( TILEGXAluOp, HReg, HReg, TILEGXRH * );
-extern TILEGXInstr *TILEGXInstr_Shft ( TILEGXShftOp, Bool sz32, HReg, HReg,
- TILEGXRH * );
-extern TILEGXInstr *TILEGXInstr_Unary ( TILEGXUnaryOp op, HReg dst, HReg src );
-extern TILEGXInstr *TILEGXInstr_Cmp ( Bool, Bool, HReg, HReg, HReg,
- TILEGXCondCode );
-extern TILEGXInstr *TILEGXInstr_CmpI ( Bool, Bool, HReg, HReg, TILEGXRH *,
- TILEGXCondCode );
-extern TILEGXInstr *TILEGXInstr_Bf ( TILEGXBfOp op, HReg dst, HReg src,
- UInt Start, UInt End );
-extern TILEGXInstr *TILEGXInstr_Acas ( TILEGXAcasOp op, HReg old, HReg addr,
- HReg exp, HReg new, UInt sz );
-extern TILEGXInstr *TILEGXInstr_Mul ( Bool syned, Bool hi32, Bool sz32, HReg,
- HReg, HReg );
-extern TILEGXInstr *TILEGXInstr_Div ( Bool syned, Bool sz32, HReg, HReg );
-extern TILEGXInstr *TILEGXInstr_Madd ( Bool, HReg, HReg );
-extern TILEGXInstr *TILEGXInstr_Msub ( Bool, HReg, HReg );
-
-extern TILEGXInstr *TILEGXInstr_Load ( UChar sz, HReg dst, TILEGXAMode * src );
-
-extern TILEGXInstr *TILEGXInstr_Store ( UChar sz, TILEGXAMode * dst, HReg src );
-
-extern TILEGXInstr *TILEGXInstr_LoadL ( UChar sz, HReg dst, TILEGXAMode * src );
-
-extern TILEGXInstr *TILEGXInstr_StoreC ( UChar sz, TILEGXAMode * dst, HReg src );
-
-extern TILEGXInstr *TILEGXInstr_Call ( TILEGXCondCode, Addr64, ULong, HReg );
-extern TILEGXInstr *TILEGXInstr_CallAlways ( TILEGXCondCode, Addr64, ULong );
-extern TILEGXInstr *TILEGXInstr_XDirect ( Addr64 dstGA, TILEGXAMode* amPC,
- TILEGXCondCode cond, Bool toFastEP );
-extern TILEGXInstr *TILEGXInstr_XIndir ( HReg dstGA, TILEGXAMode* amPC,
- TILEGXCondCode cond );
-extern TILEGXInstr *TILEGXInstr_XAssisted ( HReg dstGA, TILEGXAMode* amPC,
- TILEGXCondCode cond, IRJumpKind jk );
-extern TILEGXInstr *TILEGXInstr_EvCheck ( TILEGXAMode* amCounter,
- TILEGXAMode* amFailAddr );
-extern TILEGXInstr* TILEGXInstr_ProfInc (void);
-
-extern TILEGXInstr *TILEGXInstr_Goto ( IRJumpKind, TILEGXCondCode,
- TILEGXRH * dst, HReg );
-extern TILEGXInstr *TILEGXInstr_GotoAlways ( IRJumpKind, TILEGXRH * );
-extern TILEGXInstr *TILEGXInstr_RdWrLR ( Bool wrLR, HReg gpr );
-extern TILEGXInstr *TILEGXInstr_MovCond ( HReg dst, HReg srcL, TILEGXRH * src,
- HReg condR, TILEGXCondCode cond );
-extern void ppTILEGXInstr ( const TILEGXInstr * );
-
-/* Some functions that insulate the register allocator from details
- of the underlying instruction set. */
-extern void getRegUsage_TILEGXInstr ( HRegUsage *, TILEGXInstr *);
-extern void mapRegs_TILEGXInstr ( HRegRemap *, TILEGXInstr *);
-extern Bool isMove_TILEGXInstr ( TILEGXInstr *, HReg *, HReg * );
-extern Int emit_TILEGXInstr ( Bool*, UChar*, Int, TILEGXInstr*, Bool, VexEndness,
- void*, void*, void*, void* );
-extern void genSpill_TILEGX ( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2,
- HReg rreg, Int offset );
-extern void genReload_TILEGX ( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2,
- HReg rreg, Int offset );
-
-extern const RRegUniverse* getRRegUniverse_TILEGX ( void );
-
-extern HInstrArray *iselSB_TILEGX ( const IRSB*, VexArch,
- const VexArchInfo*,
- const VexAbiInfo*,
- Int, Int, Bool, Bool, Addr);
-extern const HChar *showTILEGXCondCode ( TILEGXCondCode cond );
-extern Int evCheckSzB_TILEGX (void);
-extern VexInvalRange chainXDirect_TILEGX ( VexEndness endness_host,
- void* place_to_chain,
- const void* disp_cp_chain_me_EXPECTED,
- const void* place_to_jump_to,
- Bool mode64 );
-extern VexInvalRange unchainXDirect_TILEGX ( VexEndness endness_host,
- void* place_to_unchain,
- const void* place_to_jump_to_EXPECTED,
- const void* disp_cp_chain_me,
- Bool mode64 );
-extern VexInvalRange patchProfInc_TILEGX ( VexEndness endness_host,
- void* place_to_patch,
- const ULong* location_of_counter,
- Bool mode64 );
-
-extern Int decode_and_display ( tilegx_bundle_bits *p, Int count, ULong pc );
-
-#endif /* __LIBVEX_HOST_TILEGX_HDEFS_H */
-
-/*---------------------------------------------------------------*/
-/*--- end host-tilegx_defs.h ---*/
-/*---------------------------------------------------------------*/
diff --git a/VEX/priv/host_tilegx_isel.c b/VEX/priv/host_tilegx_isel.c
deleted file mode 100644
index 0c9ea65..0000000
--- a/VEX/priv/host_tilegx_isel.c
+++ /dev/null
@@ -1,1864 +0,0 @@
-
-/*---------------------------------------------------------------*/
-/*--- begin host_tilegx_isel.c ---*/
-/*---------------------------------------------------------------*/
-
-/*
- This file is part of Valgrind, a dynamic binary instrumentation
- framework.
-
- Copyright (C) 2010-2015 Tilera Corp.
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of the
- License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful, but
- WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- 02110-1301, USA.
-
- The GNU General Public License is contained in the file COPYING.
-*/
-
- /* Contributed by Zhi-Gang Liu <zliu at tilera dot com> */
-
-#include "libvex_basictypes.h"
-#include "libvex_ir.h"
-#include "libvex.h"
-
-#include "main_util.h"
-#include "main_globals.h"
-#include "host_generic_regs.h"
-#include "host_tilegx_defs.h"
-#include "tilegx_disasm.h"
-
-/*---------------------------------------------------------*/
-/*--- Register Usage Conventions ---*/
-/*---------------------------------------------------------*/
-
-/* GPR register class for tilegx */
-#define HRcGPR() HRcInt64
-
-/* guest_COND offset. */
-#define COND_OFFSET() (608)
-
-/*---------------------------------------------------------*/
-/*--- ISelEnv ---*/
-/*---------------------------------------------------------*/
-
-/* This carries around:
-
- - A mapping from IRTemp to IRType, giving the type of any IRTemp we
- might encounter. This is computed before insn selection starts,
- and does not change.
-
- - A mapping from IRTemp to HReg. This tells the insn selector
- which virtual register(s) are associated with each IRTemp
- temporary. This is computed before insn selection starts, and
- does not change. We expect this mapping to map precisely the
- same set of IRTemps as the type mapping does.
-
- - vregmap holds the primary register for the IRTemp.
- - vregmapHI holds the secondary register for the IRTemp,
- if any is needed. That's only for Ity_I64 temps
- in 32 bit mode or Ity_I128 temps in 64-bit mode.
-
- - The name of the vreg in which we stash a copy of the link reg,
- so helper functions don't kill it.
-
- - The code array, that is, the insns selected so far.
-
- - A counter, for generating new virtual registers.
-
- - The host subarchitecture we are selecting insns for.
- This is set at the start and does not change.
-
- - A Bool to tell us if the host is 32 or 64bit.
- This is set at the start and does not change.
-
- - An IRExpr*, which may be NULL, holding the IR expression (an
- IRRoundingMode-encoded value) to which the FPU's rounding mode
- was most recently set. Setting to NULL is always safe. Used to
- avoid redundant settings of the FPU's rounding mode, as
- described in set_FPU_rounding_mode below.
-
- - A VexMiscInfo*, needed for knowing how to generate
- function calls for this target
-*/
-typedef struct {
- IRTypeEnv *type_env;
-
- HReg *vregmap;
-
- Int n_vregmap;
-
- HInstrArray *code;
-
- Int vreg_ctr;
-
- UInt hwcaps;
-
- Bool mode64;
-
- Bool chainingAllowed;
-
- Addr64 max_ga;
-
- IRExpr *previous_rm;
-
- VexAbiInfo *vbi;
-} ISelEnv;
-
-static HReg lookupIRTemp ( ISelEnv * env, IRTemp tmp )
-{
- vassert(tmp >= 0);
- vassert(tmp < env->n_vregmap);
- return env->vregmap[tmp];
-}
-
-static void addInstr ( ISelEnv * env, TILEGXInstr * instr )
-{
- addHInstr(env->code, instr);
- if (vex_traceflags & VEX_TRACE_VCODE) {
- ppTILEGXInstr(instr);
- vex_printf("\n");
- }
-}
-
-static HReg newVRegI ( ISelEnv * env )
-{
- HReg reg = mkHReg(True /*virtual R*/, HRcGPR(), 0, env->vreg_ctr);
- env->vreg_ctr++;
- return reg;
-}
-
-/*---------------------------------------------------------*/
-/*--- ISEL: Forward declarations ---*/
-/*---------------------------------------------------------*/
-
-/* These are organised as iselXXX and iselXXX_wrk pairs. The
- iselXXX_wrk do the real work, but are not to be called directly.
- For each XXX, iselXXX calls its iselXXX_wrk counterpart, then
- checks that all returned registers are virtual. You should not
- call the _wrk version directly.
-*/
-/* Compute an I8/I16/I32/I64 into a RH (reg-or-halfword-immediate).
- It's important to specify whether the immediate is to be regarded
- as signed or not. If yes, this will never return -32768 as an
- immediate; this guaranteed that all signed immediates that are
- return can have their sign inverted if need be.
-*/
-static TILEGXRH *iselWordExpr_RH_wrk ( ISelEnv * env, Bool syned, IRExpr * e );
-static TILEGXRH *iselWordExpr_RH ( ISelEnv * env, Bool syned, IRExpr * e );
-
-static TILEGXRH *iselWordExpr_RH6u_wrk ( ISelEnv * env, IRExpr * e );
-static TILEGXRH *iselWordExpr_RH6u ( ISelEnv * env, IRExpr * e );
-
-/* compute an I8/I16/I32/I64 into a GPR*/
-static HReg iselWordExpr_R_wrk ( ISelEnv * env, IRExpr * e );
-static HReg iselWordExpr_R ( ISelEnv * env, IRExpr * e );
-
-/* compute an I64 into an AMode. */
-static TILEGXAMode *iselWordExpr_AMode_wrk ( ISelEnv * env, IRExpr * e,
- IRType xferTy );
-static TILEGXAMode *iselWordExpr_AMode ( ISelEnv * env, IRExpr * e,
- IRType xferTy );
-
-static TILEGXCondCode iselCondCode_wrk ( ISelEnv * env, IRExpr * e );
-static TILEGXCondCode iselCondCode ( ISelEnv * env, IRExpr * e );
-
-/*---------------------------------------------------------*/
-/*--- ISEL: Misc helpers ---*/
-/*---------------------------------------------------------*/
-
-/* Make an int reg-reg move. */
-static TILEGXInstr *mk_iMOVds_RR ( HReg r_dst, HReg r_src )
-{
- vassert(hregClass(r_dst) == hregClass(r_src));
- vassert(hregClass(r_src) == HRcInt32 || hregClass(r_src) == HRcInt64);
- return TILEGXInstr_Alu(GXalu_OR, r_dst, r_src, TILEGXRH_Reg(r_src));
-}
-
-/*---------------------------------------------------------*/
-/*--- ISEL: Function call helpers ---*/
-/*---------------------------------------------------------*/
-
-/* Used only in doHelperCall. See big comment in doHelperCall
- handling of register-parameter args. This function figures out
- whether evaluation of an expression might require use of a fixed
- register.
-*/
-static Bool mightRequireFixedRegs ( IRExpr * e )
-{
- switch (e->tag) {
- case Iex_RdTmp:
- case Iex_Const:
- case Iex_Get:
- return False;
- default:
- return True;
- }
-}
-
-/* Do a complete function call. guard is a Ity_Bit expression
- indicating whether or not the call happens. If guard==NULL, the
- call is unconditional. */
-
-static void doHelperCall ( ISelEnv * env, IRExpr * guard, IRCallee * cee,
- IRExpr ** args, IRType retTy )
-{
- TILEGXCondCode cc;
- HReg argregs[TILEGX_N_REGPARMS];
- HReg tmpregs[TILEGX_N_REGPARMS];
- Bool go_fast;
- Long n_args, i, argreg;
- ULong argiregs;
- ULong target;
- HReg src = INVALID_HREG;
-
-
- UInt nVECRETs = 0;
- UInt nBBPTRs = 0;
-
- /* TILEGX calling convention: up to 10 registers (r0 ... r9)
- are allowed to be used for passing integer arguments. They correspond
- to regs GPR0 ... GPR9. */
-
- /* Note that the cee->regparms field is meaningless on ARM64 hosts
- (since there is only one calling convention) and so we always
- ignore it. */
-
- n_args = 0;
- for (i = 0; args[i]; i++) {
- n_args++;
- IRExpr* arg = args[i];
- if (UNLIKELY(arg->tag == Iex_VECRET)) {
- nVECRETs++;
- } else if (UNLIKELY(arg->tag == Iex_BBPTR)) {
- nBBPTRs++;
- }
- }
-
- if (nVECRETs || nBBPTRs)
- vex_printf("nVECRETs=%u, nBBPTRs=%u\n",
- nVECRETs, nBBPTRs);
-
- if (TILEGX_N_REGPARMS < n_args) {
- vpanic("doHelperCall(TILEGX): cannot currently handle > 10 args");
- }
- argregs[0] = hregTILEGX_R0();
- argregs[1] = hregTILEGX_R1();
- argregs[2] = hregTILEGX_R2();
- argregs[3] = hregTILEGX_R3();
- argregs[4] = hregTILEGX_R4();
- argregs[5] = hregTILEGX_R5();
- argregs[6] = hregTILEGX_R6();
- argregs[7] = hregTILEGX_R7();
- argregs[8] = hregTILEGX_R8();
- argregs[9] = hregTILEGX_R9();
- argiregs = 0;
-
- for (i = 0; i < TILEGX_N_REGPARMS; i++)
- tmpregs[i] = INVALID_HREG;
-
- /* First decide which scheme (slow or fast) is to be used. First
- assume the fast scheme, and select slow if any contraindications
- (wow) appear. */
-
- go_fast = True;
-
- if (guard) {
- if (guard->tag == Iex_Const && guard->Iex.Const.con->tag == Ico_U1
- && guard->Iex.Const.con->Ico.U1 == True) {
- /* unconditional */
- } else {
- /* Not manifestly unconditional -- be conservative. */
- go_fast = False;
- }
- }
-
- if (go_fast) {
- for (i = 0; i < n_args; i++) {
- if (mightRequireFixedRegs(args[i])) {
- go_fast = False;
- break;
- }
- }
- }
-
- /* At this point the scheme to use has been established. Generate
- code to get the arg values into the argument rregs. */
- if (go_fast) {
- /* FAST SCHEME */
- argreg = 0;
-
- for (i = 0; i < n_args; i++) {
- vassert(argreg < TILEGX_N_REGPARMS);
- vassert(typeOfIRExpr(env->type_env, args[i]) == Ity_I32 ||
- typeOfIRExpr(env->type_env, args[i]) == Ity_I64);
-
- argiregs |= (1 << (argreg));
- addInstr(env, mk_iMOVds_RR(argregs[argreg],
- iselWordExpr_R(env,
- args[i])));
- argreg++;
- }
- /* Fast scheme only applies for unconditional calls. Hence: */
- cc = TILEGXcc_AL;
- } else {
- /* SLOW SCHEME; move via temporaries */
- argreg = 0;
-
- for (i = 0; i < n_args; i++) {
- vassert(argreg < TILEGX_N_REGPARMS);
- vassert(typeOfIRExpr(env->type_env, args[i]) == Ity_I32
- || typeOfIRExpr(env->type_env, args[i]) == Ity_I64);
- tmpregs[argreg] = iselWordExpr_R(env, args[i]);
- argreg++;
- }
-
- /* Now we can compute the condition. We can't do it earlier
- because the argument computations could trash the condition
- codes. Be a bit clever to handle the common case where the
- guard is 1:Bit. */
- cc = TILEGXcc_AL;
- if (guard) {
- if (guard->tag == Iex_Const && guard->Iex.Const.con->tag == Ico_U1
- && guard->Iex.Const.con->Ico.U1 == True) {
- /* unconditional -- do nothing */
- } else {
- cc = iselCondCode(env, guard);
- src = iselWordExpr_R(env, guard);
- }
- }
- /* Move the args to their final destinations. */
- for (i = 0; i < argreg; i++) {
- if (hregIsInvalid(tmpregs[i])) // Skip invalid regs
- continue;
- /* None of these insns, including any spill code that might
- be generated, may alter the condition codes. */
- argiregs |= (1 << (i));
- addInstr(env, mk_iMOVds_RR(argregs[i], tmpregs[i]));
- }
- }
-
- target = (Addr)(cee->addr);
-
- /* Finally, the call itself. */
- if (cc == TILEGXcc_AL)
- addInstr(env, TILEGXInstr_CallAlways(cc, target, argiregs));
- else
- addInstr(env, TILEGXInstr_Call(cc, target, argiregs, src));
-}
-
-/*---------------------------------------------------------*/
-/*--- ISEL: Integer expression auxiliaries ---*/
-/*---------------------------------------------------------*/
-
-/* --------------------- AMODEs --------------------- */
-
-/* Return an AMode which computes the value of the specified
- expression, possibly also adding insns to the code list as a
- result. The expression may only be a word-size one.
-*/
-
-static Bool uInt_fits_in_16_bits ( UInt u )
-{
- UInt v = u & 0xFFFF;
-
- v = (Int)(v << 16) >> 16; /* sign extend */
-
- return u == v;
-}
-
-static Bool sane_AMode ( ISelEnv * env, TILEGXAMode * am )
-{
- if (am->tag == GXam_IR)
- return toBool(hregClass(am->GXam.IR.base) == HRcGPR() &&
- hregIsVirtual(am->GXam.IR.base) &&
- uInt_fits_in_16_bits(am->GXam.IR.index));
-
- vpanic("sane_AMode: unknown tilegx amode tag");
-}
-
-static TILEGXAMode *iselWordExpr_AMode ( ISelEnv * env, IRExpr * e,
- IRType xferTy )
-{
- TILEGXAMode *am = iselWordExpr_AMode_wrk(env, e, xferTy);
- vassert(sane_AMode(env, am));
- return am;
-}
-
-/* DO NOT CALL THIS DIRECTLY ! */
-static TILEGXAMode *iselWordExpr_AMode_wrk ( ISelEnv * env, IRExpr * e,
- IRType xferTy )
-{
- IRType ty = typeOfIRExpr(env->type_env, e);
-
- vassert(ty == Ity_I64);
- /* Add64(expr,i), where i == sign-extend of (i & 0xFFFF) */
- if (e->tag == Iex_Binop
- && e->Iex.Binop.op == Iop_Add64
- && e->Iex.Binop.arg2->tag == Iex_Const
- && e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U64
- && uInt_fits_in_16_bits(e->Iex.Binop.arg2->Iex.Const.con->Ico.U64)) {
-
- return TILEGXAMode_IR((Long) e->Iex.Binop.arg2->Iex.Const.con->Ico.U64,
- iselWordExpr_R(env, e->Iex.Binop.arg1));
- }
-
- /* Doesn't match anything in particular. Generate it into
- a register and use that. */
- return TILEGXAMode_IR(0, iselWordExpr_R(env, e));
-}
-
-
-
-
-
-/*---------------------------------------------------------*/
-/*--- ISEL: Integer expressions (64/32/16/8 bit) ---*/
-/*---------------------------------------------------------*/
-
-/* Select insns for an integer-typed expression, and add them to the
- code list. Return a reg holding the result. This reg will be a
- virtual register. THE RETURNED REG MUST NOT BE MODIFIED. If you
- want to modify it, ask for a new vreg, copy it in there, and modify
- the copy. The register allocator will do its best to map both
- add vregs to the same real register, so the copies will often disappear
- later in the game.
-
- This should handle expressions of 64, 32, 16 and 8-bit type.
- All results are returned in a 64bit register.
-*/
-static HReg iselWordExpr_R ( ISelEnv * env, IRExpr * e )
-{
- HReg r = iselWordExpr_R_wrk(env, e);
- /* sanity checks ... */
-
- vassert(hregClass(r) == HRcGPR());
- vassert(hregIsVirtual(r));
- return r;
-}
-
-/* DO NOT CALL THIS DIRECTLY ! */
-static HReg iselWordExpr_R_wrk ( ISelEnv * env, IRExpr * e )
-{
- IRType ty = typeOfIRExpr(env->type_env, e);
- vassert(ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 ||
- ty == Ity_I1 || ty == Ity_I64);
-
- switch (e->tag) {
- /* --------- TEMP --------- */
- case Iex_RdTmp:
- return lookupIRTemp(env, e->Iex.RdTmp.tmp);
-
- /* --------- LOAD --------- */
- case Iex_Load: {
- HReg r_dst = newVRegI(env);
- TILEGXAMode *am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, ty);
-
- if (e->Iex.Load.end != Iend_LE
- && e->Iex.Load.end != Iend_BE)
- goto irreducible;
-
- addInstr(env, TILEGXInstr_Load(toUChar(sizeofIRType(ty)),
- r_dst, am_addr));
- return r_dst;
- break;
- }
- /* --------- BINARY OP --------- */
- case Iex_Binop: {
- TILEGXAluOp aluOp;
- TILEGXShftOp shftOp;
-
- switch (e->Iex.Binop.op) {
-
- case Iop_Add8:
- case Iop_Add16:
- case Iop_Add32:
- case Iop_Add64:
- aluOp = GXalu_ADD;
- break;
-
- case Iop_Sub8:
- case Iop_Sub16:
- case Iop_Sub32:
- case Iop_Sub64:
- aluOp = GXalu_SUB;
- break;
-
- case Iop_And8:
- case Iop_And16:
- case Iop_And32:
- case Iop_And64:
- aluOp = GXalu_AND;
- break;
-
- case Iop_Or8:
- case Iop_Or16:
- case Iop_Or32:
- case Iop_Or64:
- aluOp = GXalu_OR;
- break;
-
- case Iop_Xor8:
- case Iop_Xor16:
- case Iop_Xor32:
- case Iop_Xor64:
- aluOp = GXalu_XOR;
- break;
-
- default:
- aluOp = GXalu_INVALID;
- break;
- }
-
- /* For commutative ops we assume any literal
- values are on the second operand. */
- if (aluOp != GXalu_INVALID) {
- HReg r_dst = newVRegI(env);
- HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
- TILEGXRH *ri_srcR = NULL;
- /* get right arg into an RH, in the appropriate way */
- switch (aluOp) {
- case GXalu_ADD:
- case GXalu_SUB:
- ri_srcR = iselWordExpr_RH(env, True /*signed */ ,
- e->Iex.Binop.arg2);
- break;
- case GXalu_AND:
- case GXalu_OR:
- case GXalu_XOR:
- ri_srcR = iselWordExpr_RH(env, True /*signed */,
- e->Iex.Binop.arg2);
- break;
- default:
- vpanic("iselWordExpr_R_wrk-aluOp-arg2");
- }
- addInstr(env, TILEGXInstr_Alu(aluOp, r_dst, r_srcL, ri_srcR));
- return r_dst;
- }
-
- /* a shift? */
- switch (e->Iex.Binop.op) {
- case Iop_Shl32:
- case Iop_Shl64:
- shftOp = GXshft_SLL;
- break;
- case Iop_Shr32:
- case Iop_Shr64:
- shftOp = GXshft_SRL;
- break;
- case Iop_Sar64:
- shftOp = GXshft_SRA;
- break;
- case Iop_Shl8x8:
- shftOp = GXshft_SLL8x8;
- break;
- case Iop_Shr8x8:
- shftOp = GXshft_SRL8x8;
- break;
- default:
- shftOp = GXshft_INVALID;
- break;
- }
-
- /* we assume any literal values are on the second operand. */
- if (shftOp != GXshft_INVALID) {
- HReg r_dst = newVRegI(env);
- HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
- TILEGXRH *ri_srcR = NULL;
- /* get right arg into an RH, in the appropriate way */
- switch (shftOp) {
- case GXshft_SLL:
- case GXshft_SRL:
- case GXshft_SRA:
- //ri_srcR = iselWordExpr_RH6u(env, e->Iex.Binop.arg2);
- //break;
- case GXshft_SLL8x8:
- case GXshft_SRL8x8:
- //if (e->Iex.Binop.arg2->tag == GXrh_Imm)
- //{
- // ri_srcR = iselWordExpr_RH6u(env, e->Iex.Binop.arg2);
- // break;
- //}
- ri_srcR = iselWordExpr_RH6u(env, e->Iex.Binop.arg2);
- break;
- default:
- vpanic("iselIntExpr_R_wrk-shftOp-arg2");
- }
- /* widen the left arg if needed */
- /*TODO do we need this? */
- if (ty == Ity_I8 || ty == Ity_I16)
- goto irreducible;
- if (ty == Ity_I64) {
- addInstr(env, TILEGXInstr_Shft(shftOp, False/*64bit shift */,
- r_dst, r_srcL, ri_srcR));
- } else {
- addInstr(env, TILEGXInstr_Shft(shftOp, True /*32bit shift */,
- r_dst, r_srcL, ri_srcR));
- }
- return r_dst;
- }
-
- /* Cmp*32*(x,y) ? */
- if (e->Iex.Binop.op == Iop_CasCmpEQ32
- || e->Iex.Binop.op == Iop_CmpEQ32
- || e->Iex.Binop.op == Iop_CasCmpNE32
- || e->Iex.Binop.op == Iop_CmpNE32
- || e->Iex.Binop.op == Iop_CmpNE64
- || e->Iex.Binop.op == Iop_CmpLT32S
- || e->Iex.Binop.op == Iop_CmpLT32U
- || e->Iex.Binop.op == Iop_CmpLT64U
- || e->Iex.Binop.op == Iop_CmpLE32S
- || e->Iex.Binop.op == Iop_CmpLE64S
- || e->Iex.Binop.op == Iop_CmpLE64U
- || e->Iex.Binop.op == Iop_CmpLT64S
- || e->Iex.Binop.op == Iop_CmpEQ64
- || e->Iex.Binop.op == Iop_CasCmpEQ64
- || e->Iex.Binop.op == Iop_CasCmpNE64) {
-
- Bool syned = (e->Iex.Binop.op == Iop_CmpLT32S
- || e->Iex.Binop.op == Iop_CmpLE32S
- || e->Iex.Binop.op == Iop_CmpLT64S
- || e->Iex.Binop.op == Iop_CmpLE64S);
- Bool size32;
- HReg dst = newVRegI(env);
- HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1);
- HReg r2 = iselWordExpr_R(env, e->Iex.Binop.arg2);
- TILEGXCondCode cc;
-
- switch (e->Iex.Binop.op) {
- case Iop_CasCmpEQ32:
- case Iop_CmpEQ32:
- cc = TILEGXcc_EQ;
- size32 = True;
- break;
- case Iop_CasCmpNE32:
- case Iop_CmpNE32:
- cc = TILEGXcc_NE;
- size32 = True;
- break;
- case Iop_CasCmpNE64:
- case Iop_CmpNE64:
- cc = TILEGXcc_NE;
- size32 = True;
- break;
- case Iop_CmpLT32S:
- cc = TILEGXcc_LT;
- size32 = True;
- break;
- case Iop_CmpLT32U:
- cc = TILEGXcc_LO;
- size32 = True;
- break;
- case Iop_CmpLT64U:
- cc = TILEGXcc_LT;
- size32 = False;
- break;
- case Iop_CmpLE32S:
- cc = TILEGXcc_LE;
- size32 = True;
- break;
- case Iop_CmpLE64S:
- cc = TILEGXcc_LE;
- size32 = False;
- break;
- case Iop_CmpLE64U:
- cc = TILEGXcc_LE;
- size32 = False;
- break;
- case Iop_CmpLT64S:
- cc = TILEGXcc_LT;
- size32 = False;
- break;
- case Iop_CasCmpEQ64:
- case Iop_CmpEQ64:
- cc = TILEGXcc_EQ;
- size32 = False;
- break;
- default:
- vpanic
- ("iselCondCode(tilegx): CmpXX32 or CmpXX64");
- }
-
- addInstr(env, TILEGXInstr_Cmp(syned, size32, dst, r1, r2, cc));
- return dst;
-
- break;
-
- }
-
- if (e->Iex.Binop.op == Iop_CmpEQ8x8) {
-
- Bool syned = False;
-
- Bool size32;
- HReg dst = newVRegI(env);
- HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1);
- TILEGXRH *r2 = iselWordExpr_RH(env, True, e->Iex.Binop.arg2);
- TILEGXCondCode cc;
-
- switch (e->Iex.Binop.op) {
- case Iop_CmpEQ8x8:
- cc = TILEGXcc_EQ8x8;
- size32 = False;
- break;
-
- default:
- vassert(0);
- }
-
- addInstr(env, TILEGXInstr_CmpI(syned, size32, dst, r1, r2, cc));
- return dst;
-
- break;
- }
-
- if (e->Iex.Binop.op == Iop_Max32U) {
- /*
- tmp = argL - argR;
- tmp &= (1<<31)
- dst = (tmp) ? (argL) ? (argR)
- */
- HReg argL = iselWordExpr_R(env, e->Iex.Binop.arg1);
- TILEGXRH *argR = iselWordExpr_RH(env, False /*signed */ ,
- e->Iex.Binop.arg2);
- HReg dst = newVRegI(env);
- HReg tmp = newVRegI(env);
- // temp = argL - argR
- addInstr(env, TILEGXInstr_Alu(GXalu_SUB, tmp, argL, argR));
- // tmp &= bit31
- addInstr(env, TILEGXInstr_Bf(GXbf_EXTU, tmp, tmp , 31, 31));
- // (tmp == 0) ? (argL) : (argR)
- addInstr(env, TILEGXInstr_MovCond(dst, argL, argR, tmp, TILEGXcc_EZ));
- return dst;
- }
-
- if (e->Iex.Binop.op == Iop_MullS32 || e->Iex.Binop.op == Iop_MullU32) {
- Bool syned = (e->Iex.Binop.op == Iop_MullS32);
- Bool sz32 = (e->Iex.Binop.op == Iop_Mul32);
- HReg r_dst = newVRegI(env);
- HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
- HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
- addInstr(env, TILEGXInstr_Mul(syned /*Unsigned or Signed */ ,
- True /*widen */ ,
- sz32 /*32bit or 64bit */,
- r_dst, r_srcL, r_srcR));
- return r_dst;
- }
-
- if (e->Iex.Binop.op == Iop_32HLto64) {
- HReg tHi = iselWordExpr_R(env, e->Iex.Binop.arg1);
- HReg tLo = iselWordExpr_R(env, e->Iex.Binop.arg2);
- HReg tLo_1 = newVRegI(env);
- HReg tHi_1 = newVRegI(env);
- HReg r_dst = newVRegI(env);
- HReg mask = newVRegI(env);
-
- addInstr(env, TILEGXInstr_Shft(GXshft_SLL, False, tHi_1, tHi,
- TILEGXRH_Imm(False, 32)));
-
- addInstr(env, TILEGXInstr_LI(mask, 0xffffffff));
- addInstr(env, TILEGXInstr_Alu(GXalu_AND, tLo_1, tLo,
- TILEGXRH_Reg(mask)));
- addInstr(env, TILEGXInstr_Alu(GXalu_OR, r_dst, tHi_1,
- TILEGXRH_Reg(tLo_1)));
-
- return r_dst;
- }
-
- /* Anything reached here !*/
- goto irreducible;
- }
-
- /* --------- UNARY OP --------- */
- case Iex_Unop: {
-
- IROp op_unop = e->Iex.Unop.op;
-
- switch (op_unop) {
- case Iop_Not1: {
- HReg r_dst = newVRegI(env);
- HReg r_srcL = iselWordExpr_R(env, e->Iex.Unop.arg);
- TILEGXRH *r_srcR = TILEGXRH_Reg(r_srcL);
-
- addInstr(env, TILEGXInstr_LI(r_dst, 0x1));
- addInstr(env, TILEGXInstr_Alu(GXalu_SUB, r_dst, r_dst, r_srcR));
- return r_dst;
- }
-
- case Iop_Not8:
- case Iop_Not16:
- case Iop_Not32:
- case Iop_Not64: {
- /* not x = nor x, x */
- HReg r_dst = newVRegI(env);
- HReg r_srcL = iselWordExpr_R(env, e->Iex.Unop.arg);
- TILEGXRH *r_srcR = TILEGXRH_Reg(r_srcL);
-
- addInstr(env, TILEGXInstr_Alu(GXalu_NOR, r_dst, r_srcL, r_srcR));
- return r_dst;
- }
-
- case Iop_CmpNEZ8x8: {
-
- Bool syned = False;
- Bool size32;
- HReg dst = newVRegI(env);
- HReg r1;
- TILEGXCondCode cc = TILEGXcc_NE8x8;
- size32 = False;
- r1 = iselWordExpr_R(env, e->Iex.Unop.arg);
- addInstr(env, TILEGXInstr_CmpI(syned, size32, dst, hregTILEGX_R63(),
- TILEGXRH_Reg(r1), cc));
-
- return dst;
- break;
- }
-
- case Iop_16to8:
- case Iop_32to8:
- case Iop_64to8:
- case Iop_32to16:
- case Iop_64to16:
- case Iop_64to32:
- case Iop_128to64:
-
- return iselWordExpr_R(env, e->Iex.Unop.arg);
-
- case Iop_1Uto64:
- case Iop_1Uto32:
- case Iop_1Uto8: {
- HReg dst = newVRegI(env);
- HReg src = iselWordExpr_R(env, e->Iex.Unop.arg);
- addInstr(env, TILEGXInstr_Alu(GXalu_AND, dst, src, TILEGXRH_Imm(False, 1)));
- return dst;
- }
- case Iop_8Uto16:
- case Iop_8Uto32:
- case Iop_8Uto64:
- case Iop_16Uto32:
- case Iop_16Uto64: {
-
- HReg dst = newVRegI(env);
- HReg src = iselWordExpr_R(env, e->Iex.Unop.arg);
- Bool srcIs16 = toBool( e->Iex.Unop.op==Iop_16Uto32
- || e->Iex.Unop.op==Iop_16Uto64 );
-
- addInstr(env, TILEGXInstr_Bf(GXbf_EXTU, dst, src,
- 0,
- srcIs16 ? 15 : 7));
-
- return dst;
- }
-
- case Iop_32to1:
- case Iop_64to1:
- {
- HReg r_dst = newVRegI(env);
- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
-
- addInstr(env, TILEGXInstr_Bf(GXbf_EXTU, r_dst, r_src, 0, 0));
- return r_dst;
- }
- case Iop_1Sto32:
- case Iop_1Sto64:
- {
- HReg r_dst = newVRegI(env);
- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
-
- addInstr(env, TILEGXInstr_Bf(GXbf_EXTS, r_dst, r_src, 0, 0));
- return r_dst;
- }
- case Iop_8Sto16:
- case Iop_8Sto32:
- case Iop_8Sto64:
- {
- HReg r_dst = newVRegI(env);
- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
-
- addInstr(env, TILEGXInstr_Bf(GXbf_EXTS, r_dst, r_src, 0, 7));
- return r_dst;
- }
- case Iop_16Sto32:
- case Iop_16Sto64:
- {
- HReg r_dst = newVRegI(env);
- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
-
- addInstr(env, TILEGXInstr_Bf(GXbf_EXTS, r_dst, r_src, 0, 15));
- return r_dst;
- }
- case Iop_32Uto64:
- {
- HReg r_dst = newVRegI(env);
- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
-
- addInstr(env, TILEGXInstr_Bf(GXbf_EXTU, r_dst, r_src, 0, 31));
- return r_dst;
- }
- case Iop_32Sto64:
- {
- HReg r_dst = newVRegI(env);
- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
-
- addInstr(env, TILEGXInstr_Bf(GXbf_EXTS, r_dst, r_src, 0, 31));
- return r_dst;
- }
-
- case Iop_CmpNEZ8: {
- HReg r_dst = newVRegI(env);
- HReg tmp = newVRegI(env);
- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
-
- TILEGXCondCode cc;
-
- cc = TILEGXcc_NE;
- addInstr(env, TILEGXInstr_Alu(GXalu_AND, tmp, r_src,
- TILEGXRH_Imm(False, 0xFF)));
- addInstr(env, TILEGXInstr_Cmp(False, True, r_dst, tmp,
- hregTILEGX_R63(), cc));
- return r_dst;
- }
-
- case Iop_CmpNEZ32: {
- HReg r_dst = newVRegI(env);
- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
-
- TILEGXCondCode cc;
-
- cc = TILEGXcc_NE;
-
- addInstr(env, TILEGXInstr_Cmp(False, True, r_dst, r_src,
- hregTILEGX_R63(), cc));
- return r_dst;
- }
-
- case Iop_CmpwNEZ32: {
- HReg r_dst = newVRegI(env);
- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
-
- addInstr(env, TILEGXInstr_Alu(GXalu_SUB, r_dst, hregTILEGX_R63(),
- TILEGXRH_Reg(r_src)));
-
- addInstr(env, TILEGXInstr_Alu(GXalu_OR, r_dst, r_dst,
- TILEGXRH_Reg(r_src)));
- addInstr(env, TILEGXInstr_Shft(GXshft_SRA, True, r_dst, r_dst,
- TILEGXRH_Imm(False, 31)));
- return r_dst;
- }
-
- case Iop_Left8:
- case Iop_Left16:
- case Iop_Left32:
- case Iop_Left64: {
-
- HReg r_dst = newVRegI(env);
- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
- addInstr(env, TILEGXInstr_Alu(GXalu_SUB, r_dst, hregTILEGX_R63(),
- TILEGXRH_Reg(r_src)));
- addInstr(env, TILEGXInstr_Alu(GXalu_OR, r_dst, r_dst,
- TILEGXRH_Reg(r_src)));
- return r_dst;
- }
-
- case Iop_Ctz64:
- case Iop_Clz64: {
- HReg r_dst = newVRegI(env);
- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
- if (op_unop == Iop_Clz64)
- addInstr(env, TILEGXInstr_Unary(GXun_CLZ, r_dst, r_src));
- else
- addInstr(env, TILEGXInstr_Unary(GXun_CTZ, r_dst, r_src));
- return r_dst;
- }
-
- case Iop_CmpNEZ64: {
-
- HReg r_dst = newVRegI(env);
- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
-
- TILEGXCondCode cc;
-
- cc = TILEGXcc_NE;
-
- addInstr(env, TILEGXInstr_Cmp(False, False, r_dst, r_src,
- hregTILEGX_R63(), cc));
- return r_dst;
- }
-
- case Iop_CmpwNEZ64: {
- HReg tmp1;
- HReg tmp2 = newVRegI(env);
-
- tmp1 = iselWordExpr_R(env, e->Iex.Unop.arg);
-
- addInstr(env, TILEGXInstr_Alu(GXalu_SUB, tmp2, hregTILEGX_R63(),
- TILEGXRH_Reg(tmp1)));
-
- addInstr(env, TILEGXInstr_Alu(GXalu_OR, tmp2, tmp2, TILEGXRH_Reg(tmp1)));
- addInstr(env, TILEGXInstr_Shft(GXshft_SRA, False, tmp2, tmp2,
- TILEGXRH_Imm (False, 63)));
- return tmp2;
- }
-
- default:
- goto irreducible;
- break;
- }
- break;
- }
-
- /* --------- GET --------- */
- case Iex_Get: {
- if (ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32
- || ((ty == Ity_I64))) {
- HReg r_dst;
- TILEGXAMode *am_addr;
- r_dst = newVRegI(env);
- am_addr = TILEGXAMode_IR(e->Iex.Get.offset,
- TILEGXGuestStatePointer());
- addInstr(env, TILEGXInstr_Load(toUChar(sizeofIRType(ty)),
- r_dst, am_addr));
- return r_dst;
- }
- }
-
- /* --------- ITE --------- */
- case Iex_ITE: {
- if ((ty == Ity_I8 || ty == Ity_I16 ||
- ty == Ity_I32 || ((ty == Ity_I64))) &&
- typeOfIRExpr(env->type_env, e->Iex.ITE.cond) == Ity_I1) {
-
- HReg r0 = iselWordExpr_R(env, e->Iex.ITE.iffalse);
- HReg r1 = iselWordExpr_R(env, e->Iex.ITE.iftrue);
- HReg r_cond = iselWordExpr_R(env, e->Iex.ITE.cond);
- HReg r_dst = newVRegI(env);
-
- /* r_dst = (r_cond) ? r1 : r0 */
-
- addInstr(env, TILEGXInstr_MovCond(r_dst, r0, TILEGXRH_Reg(r1),
- r_cond, TILEGXcc_EZ));
-
- return r_dst;
- }
- }
-
- /* --------- LITERAL --------- */
- /* 32/16/8-bit literals */
- case Iex_Const: {
- Long l;
- HReg r_dst = newVRegI(env);
- IRConst *con = e->Iex.Const.con;
- switch (con->tag) {
- case Ico_U64:
-
- l = (Long) con->Ico.U64;
- break;
- case Ico_U32:
- l = (Long) (Int) con->Ico.U32;
- break;
- case Ico_U16:
- l = (Long) (Int) (Short) con->Ico.U16;
- break;
- case Ico_U8:
- l = (Long) (Int) (Char) con->Ico.U8;
- break;
- default:
- vpanic("iselIntExpr_R.const(tilegx)");
- }
- addInstr(env, TILEGXInstr_LI(r_dst, (ULong) l));
- return r_dst;
- }
-
- /* --------- CCALL --------- */
- case Iex_CCall: {
- HReg r_dst = newVRegI(env);
- vassert(ty == e->Iex.CCall.retty);
-
- /* Marshal args, do the call, clear stack. */
- doHelperCall(env, NULL, e->Iex.CCall.cee, e->Iex.CCall.args,
- e->Iex.CCall.retty);
-
- /* r0 is the return value. */
- addInstr(env, mk_iMOVds_RR(r_dst, hregTILEGX_R0()));
-
- return r_dst;
- }
-
- default:
- goto irreducible;
- break;
- } /* end switch(e->tag) */
-
- /* We get here if no pattern matched. */
- irreducible:
- vex_printf("--------------->\n");
- if (e->tag == Iex_RdTmp)
- vex_printf("Iex_RdTmp \n");
- ppIRExpr(e);
-
- vpanic("iselWordExpr_R(tilegx): cannot reduce tree");
-}
-
-/* --------------------- RH --------------------- */
-
-/* Compute an I8/I16/I32/I64 into a RH
- (reg-or-halfword-immediate). It's important to specify whether the
- immediate is to be regarded as signed or not. If yes, this will
- never return -32768 as an immediate; this guaranteed that all
- signed immediates that are return can have their sign inverted if
- need be. */
-
-static TILEGXRH *iselWordExpr_RH ( ISelEnv * env, Bool syned, IRExpr * e )
-{
- TILEGXRH *ri = iselWordExpr_RH_wrk(env, syned, e);
- /* sanity checks ... */
- switch (ri->tag) {
- case GXrh_Imm:
- vassert(ri->GXrh.Imm.syned == syned);
- if (syned)
- vassert(ri->GXrh.Imm.imm16 != 0x8000);
- return ri;
- case GXrh_Reg:
- vassert(hregClass(ri->GXrh.Reg.reg) == HRcGPR());
- vassert(hregIsVirtual(ri->GXrh.Reg.reg));
- return ri;
- default:
- vpanic("iselIntExpr_RH: unknown tilegx RH tag");
- }
-}
-
-/* DO NOT CALL THIS DIRECTLY ! */
-static TILEGXRH *iselWordExpr_RH_wrk ( ISelEnv * env, Bool syned, IRExpr * e )
-{
- ULong u;
- Long l;
- IRType ty = typeOfIRExpr(env->type_env, e);
- vassert(ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 ||
- ((ty == Ity_I64)));
-
- /* special case: immediate */
- if (e->tag == Iex_Const) {
- IRConst *con = e->Iex.Const.con;
- /* What value are we aiming to generate? */
- switch (con->tag) {
- /* Note: Not sign-extending - we carry 'syned' around */
- case Ico_U64:
- u = con->Ico.U64;
- break;
- case Ico_U32:
- u = 0xFFFFFFFF & con->Ico.U32;
- break;
- case Ico_U16:
- u = 0x0000FFFF & con->Ico.U16;
- break;
- case Ico_U8:
- u = 0x000000FF & con->Ico.U8;
- break;
- default:
- vpanic("iselIntExpr_RH.Iex_Const(tilegx)");
- }
- l = (Long) u;
- /* Now figure out if it's representable. */
- if (!syned && u <= 255) {
- return TILEGXRH_Imm(False /*unsigned */ , toUShort(u & 0xFFFF));
- }
- if (syned && l >= -127 && l <= 127) {
- return TILEGXRH_Imm(True /*signed */ , toUShort(u & 0xFFFF));
- }
- /* no luck; use the Slow Way. */
- }
- /* default case: calculate into a register and return that */
- return TILEGXRH_Reg(iselWordExpr_R(env, e));
-}
-
-/* --------------------- RH6u --------------------- */
-
-/* Compute an I8 into a reg-or-6-bit-unsigned-immediate, the latter
- being an immediate in the range 0 .. 63 inclusive. Used for doing
- shift amounts. */
-
-static TILEGXRH *iselWordExpr_RH6u ( ISelEnv * env, IRExpr * e )
-{
- TILEGXRH *ri;
- ri = iselWordExpr_RH6u_wrk(env, e);
- /* sanity checks ... */
- switch (ri->tag) {
- case GXrh_Imm:
- vassert(ri->GXrh.Imm.imm16 >= 1 && ri->GXrh.Imm.imm16 <= 63);
- vassert(!ri->GXrh.Imm.syned);
- return ri;
- case GXrh_Reg:
- vassert(hregClass(ri->GXrh.Reg.reg) == HRcInt64);
- vassert(hregIsVirtual(ri->GXrh.Reg.reg));
- return ri;
- default:
- vpanic("iselIntExpr_RH6u: unknown tilegx RH tag");
- }
-}
-
-/* DO NOT CALL THIS DIRECTLY ! */
-static TILEGXRH *iselWordExpr_RH6u_wrk ( ISelEnv * env, IRExpr * e )
-{
- IRType ty = typeOfIRExpr(env->type_env, e);
-
- /* special case: immediate */
- if (e->tag == Iex_Const)
- {
- if (ty == Ity_I8)
- {
- if(e->Iex.Const.con->tag == Ico_U8
- && e->Iex.Const.con->Ico.U8 >= 1 && e->Iex.Const.con->Ico.U8 <= 63)
- return TILEGXRH_Imm(False /*unsigned */ , e->Iex.Const.con->Ico.U8);
- }
- else if (ty == Ity_I64)
- {
- if(e->Iex.Const.con->tag == Ico_U64
- && e->Iex.Const.con->Ico.U64 >= 1
- && e->Iex.Const.con->Ico.U64 <= 63)
- return TILEGXRH_Imm(False /*unsigned */, e->Iex.Const.con->Ico.U64);
- }
- }
-
- /* default case: calculate into a register and return that */
- return TILEGXRH_Reg(iselWordExpr_R(env, e));
-}
-
-/* --------------------- CONDCODE --------------------- */
-
-/* Generate code to evaluated a bit-typed expression, returning the
- condition code which would correspond when the expression would
- notionally have returned 1. */
-
-static TILEGXCondCode iselCondCode(ISelEnv * env, IRExpr * e)
-{
- TILEGXCondCode cc = iselCondCode_wrk(env,e);
- vassert(cc != TILEGXcc_NV);
- return cc;
-}
-
-/* DO NOT CALL THIS DIRECTLY ! */
-static TILEGXCondCode iselCondCode_wrk ( ISelEnv * env, IRExpr * e )
-{
- vassert(e);
- vassert(typeOfIRExpr(env->type_env, e) == Ity_I1);
-
- /* Cmp*(x,y) ? */
- if (e->Iex.Binop.op == Iop_CmpEQ32
- || e->Iex.Binop.op == Iop_CmpNE32
- || e->Iex.Binop.op == Iop_CmpNE64
- || e->Iex.Binop.op == Iop_CmpLT32S
- || e->Iex.Binop.op == Iop_CmpLT32U
- || e->Iex.Binop.op == Iop_CmpLT64U
- || e->Iex.Binop.op == Iop_CmpLE32S
- || e->Iex.Binop.op == Iop_CmpLE64S
- || e->Iex.Binop.op == Iop_CmpLT64S
- || e->Iex.Binop.op == Iop_CmpEQ64
- || e->Iex.Binop.op == Iop_CasCmpEQ32
- || e->Iex.Binop.op == Iop_CasCmpEQ64) {
-
- Bool syned = (e->Iex.Binop.op == Iop_CmpLT32S
- || e->Iex.Binop.op == Iop_CmpLE32S
- || e->Iex.Binop.op == Iop_CmpLT64S
- || e->Iex.Binop.op == Iop_CmpLE64S);
- Bool size32;
- HReg dst = newVRegI(env);
- HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1);
- HReg r2 = iselWordExpr_R(env, e->Iex.Binop.arg2);
-
- TILEGXCondCode cc;
-
- switch (e->Iex.Binop.op) {
- case Iop_CmpEQ32:
- case Iop_CasCmpEQ32:
- cc = TILEGXcc_EQ;
- size32 = True;
- break;
- case Iop_CmpNE32:
- cc = TILEGXcc_NE;
- size32 = True;
- break;
- case Iop_CmpNE64:
- cc = TILEGXcc_NE;
- size32 = True;
- break;
- case Iop_CmpLT32S:
- cc = TILEGXcc_LT;
- size32 = True;
- break;
- case Iop_CmpLT32U:
- cc = TILEGXcc_LO;
- size32 = True;
- break;
- case Iop_CmpLT64U:
- cc = TILEGXcc_LO;
- size32 = False;
- break;
- case Iop_CmpLE32S:
- cc = TILEGXcc_LE;
- size32 = True;
- break;
- case Iop_CmpLE64S:
- cc = TILEGXcc_LE;
- size32 = False;
- break;
- case Iop_CmpLT64S:
- cc = TILEGXcc_LT;
- size32 = False;
- break;
- case Iop_CmpEQ64:
- case Iop_CasCmpEQ64:
- cc = TILEGXcc_EQ;
- size32 = False;
- break;
- default:
- vpanic("iselCondCode(tilegx): CmpXX32 or CmpXX64");
- break;
- }
-
- addInstr(env, TILEGXInstr_Cmp(syned, size32, dst, r1, r2, cc));
- /* Store result to guest_COND */
- TILEGXAMode *am_addr = TILEGXAMode_IR(0, TILEGXGuestStatePointer());
-
- addInstr(env, TILEGXInstr_Store(8,
- TILEGXAMode_IR(am_addr->GXam.IR.index +
- COND_OFFSET(),
- am_addr->GXam.IR.base),
- dst));
- return cc;
- }
-
- if (e->Iex.Binop.op == Iop_Not1) {
- HReg r_dst = newVRegI(env);
- HReg r_srcL = iselWordExpr_R(env, e->Iex.Unop.arg);
- TILEGXRH *r_srcR = TILEGXRH_Reg(r_srcL);
-
- addInstr(env, TILEGXInstr_LI(r_dst, 0x1));
- addInstr(env, TILEGXInstr_Alu(GXalu_SUB, r_dst, r_dst, r_srcR));
-
- /* Store result to guest_COND */
- TILEGXAMode *am_addr = TILEGXAMode_IR(0, TILEGXGuestStatePointer());
-
- addInstr(env, TILEGXInstr_Store(8,
- TILEGXAMode_IR(am_addr->GXam.IR.index +
- COND_OFFSET(),
- am_addr->GXam.IR.base),
- r_dst));
- return TILEGXcc_NE;
- }
-
- if (e->tag == Iex_RdTmp || e->tag == Iex_Unop) {
- HReg r_dst = iselWordExpr_R_wrk(env, e);
- /* Store result to guest_COND */
- TILEGXAMode *am_addr = TILEGXAMode_IR(0, TILEGXGuestStatePointer());
-
- addInstr(env, TILEGXInstr_Store(8,
- TILEGXAMode_IR(am_addr->GXam.IR.index +
- COND_OFFSET(),
- am_addr->GXam.IR.base),
- r_dst));
- return TILEGXcc_EQ;
- }
-
- vex_printf("iselCondCode(tilegx): No such tag(%u)\n", e->tag);
- ppIRExpr(e);
- vpanic("iselCondCode(tilegx)");
-
- /* Constant 1:Bit */
- if (e->tag == Iex_Const && e->Iex.Const.con->Ico.U1 == True)
- return TILEGXcc_AL;
-
- if (e->tag == Iex_RdTmp)
- return TILEGXcc_EQ;
-
- if (e->tag == Iex_Binop)
- return TILEGXcc_EQ;
-
- if (e->tag == Iex_Unop)
- return TILEGXcc_EQ;
-
- vex_printf("iselCondCode(tilegx): No such tag(%u)\n", e->tag);
- ppIRExpr(e);
- vpanic("iselCondCode(tilegx)");
-}
-
-/*---------------------------------------------------------*/
-/*--- ISEL: Statements ---*/
-/*---------------------------------------------------------*/
-
-static void iselStmt ( ISelEnv * env, IRStmt * stmt )
-{
- if (vex_traceflags & VEX_TRACE_VCODE) {
- vex_printf("\n-- ");
- ppIRStmt(stmt);
- vex_printf("\n");
- }
-
- switch (stmt->tag) {
- /* --------- STORE --------- */
- case Ist_Store: {
- TILEGXAMode *am_addr;
- IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Store.data);
-
- /*constructs addressing mode from address provided */
- am_addr = iselWordExpr_AMode(env, stmt->Ist.Store.addr, tyd);
-
- if (tyd == Ity_I8 || tyd == Ity_I16 || tyd == Ity_I32 ||
- (tyd == Ity_I64)) {
- HReg r_src = iselWordExpr_R(env, stmt->Ist.Store.data);
- addInstr(env, TILEGXInstr_Store(toUChar(sizeofIRType(tyd)),
- am_addr, r_src));
- return;
- }
- break;
- }
-
- /* --------- PUT --------- */
- case Ist_Put: {
- IRType ty = typeOfIRExpr(env->type_env, stmt->Ist.Put.data);
-
- if (ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 ||
- (ty == Ity_I64)) {
- HReg r_src = iselWordExpr_R(env, stmt->Ist.Put.data);
- TILEGXAMode *am_addr = TILEGXAMode_IR(stmt->Ist.Put.offset,
- TILEGXGuestStatePointer());
- addInstr(env, TILEGXInstr_Store(toUChar(sizeofIRType(ty)),
- am_addr, r_src));
- return;
- }
- break;
- }
-
- /* --------- TMP --------- */
- case Ist_WrTmp: {
- IRTemp tmp = stmt->Ist.WrTmp.tmp;
- IRType ty = typeOfIRTemp(env->type_env, tmp);
- HReg r_dst = lookupIRTemp(env, tmp);
- HReg r_src = iselWordExpr_R(env, stmt->Ist.WrTmp.data);
- IRType dty = typeOfIRExpr(env->type_env, stmt->Ist.WrTmp.data);
-
- if (ty == Ity_I64 || ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8 ||
- (ty == dty))
- {
- addInstr(env, mk_iMOVds_RR(r_dst, r_src));
- return;
- }
- else if (ty == Ity_I1) {
- switch (dty)
- {
- case Ity_I32:
- addInstr(env, TILEGXInstr_Bf(GXbf_EXTU, r_src, r_src, 0, 31));
- break;
- case Ity_I16:
- addInstr(env, TILEGXInstr_Bf(GXbf_EXTU, r_src, r_src, 0, 15));
- break;
- case Ity_I8:
- addInstr(env, TILEGXInstr_Bf(GXbf_EXTU, r_src, r_src, 0, 7));
- break;
- default:
- vassert(0);
- }
-
- addInstr(env, TILEGXInstr_MovCond(r_dst,
- hregTILEGX_R63(),
- TILEGXRH_Imm(False, 1),
- r_src,
- TILEGXcc_EZ));
- return;
- }
- break;
- }
-
- /* --------- Call to DIRTY helper --------- */
- case Ist_Dirty: {
- IRType retty;
- IRDirty *d = stmt->Ist.Dirty.details;
-
- /* Marshal args, do the call, clear stack. */
- doHelperCall(env, d->guard, d->cee, d->args, -1);
-
- /* Now figure out what to do with the returned value, if any. */
- if (d->tmp == IRTemp_INVALID)
- /* No return value. Nothing to do. */
- return;
-
- retty = typeOfIRTemp(env->type_env, d->tmp);
-
- if (retty == Ity_I8 || retty == Ity_I16 || retty == Ity_I32
- || (retty == Ity_I64)) {
- /* The returned value is in r0. Park it in the register
- associated with tmp. */
- HReg r_dst = lookupIRTemp(env, d->tmp);
- addInstr(env, mk_iMOVds_RR(r_dst, hregTILEGX_R0()));
- return;
- }
- break;
- }
-
-
- /* --------- ACAS --------- */
- case Ist_CAS:
- {
- UChar sz;
- IRCAS* cas = stmt->Ist.CAS.details;
- IRType ty = typeOfIRExpr(env->type_env, cas->dataLo);
-
- TILEGXAMode *r_addr = iselWordExpr_AMode(env, cas->addr, Ity_I64);
- HReg r_new = iselWordExpr_R(env, cas->dataLo);
- HReg r_old = lookupIRTemp(env, cas->oldLo);
- HReg r_exp = INVALID_HREG;
-
- vassert(cas->expdHi == NULL);
- vassert(cas->dataHi == NULL);
- vassert(r_addr->tag == GXam_IR);
- vassert(r_addr->GXam.IR.index == 0);
-
- switch (ty)
- {
- case Ity_I64: sz = 8; break;
- case Ity_I32: sz = 4; break;
- default: vassert(0);
- }
-
- if (cas->expdLo->tag != Iex_Const)
- {
- r_exp = iselWordExpr_R(env, cas->expdLo);
- addInstr(env, TILEGXInstr_Acas(GXacas_CMPEXCH, r_old,
- r_addr->GXam.IR.base, r_exp,
- r_new, sz));
- }
- else
- {
- if((sz == 8 && cas->expdLo->Iex.Const.con->Ico.U64 == 0) ||
- (sz == 4 && cas->expdLo->Iex.Const.con->Ico.U32 == 0))
- {
- addInstr(env, TILEGXInstr_Acas(GXacas_EXCH, r_old,
- r_addr->GXam.IR.base,
- r_exp, r_new, sz));
- }
- else if((sz == 8 && cas->expdLo->Iex.Const.con->Ico.U64 == 2) ||
- (sz == 4 && cas->expdLo->Iex.Const.con->Ico.U32 == 2))
- {
- addInstr(env, TILEGXInstr_Acas(GXacas_FetchAnd, r_old,
- r_addr->GXam.IR.base, r_exp,
- r_new, sz));
- }
- else if((sz == 8 && cas->expdLo->Iex.Const.con->Ico.U64 == 3) ||
- (sz == 4 && cas->expdLo->Iex.Const.con->Ico.U32 == 3))
- {
- addInstr(env, TILEGXInstr_Acas(GXacas_FetchAdd, r_old,
- r_addr->GXam.IR.base,
- r_exp, r_new, sz));
- }
- else if((sz == 8 && cas->expdLo->Iex.Const.con->Ico.U64 == 4) ||
- (sz == 4 && cas->expdLo->Iex.Const.con->Ico.U32 == 4))
- {
- addInstr(env, TILEGXInstr_Acas(GXacas_FetchOr, r_old,
- r_addr->GXam.IR.base, r_exp,
- r_new, sz));
- }
- else if((sz == 8 && cas->expdLo->Iex.Const.con->Ico.U64 == 5) ||
- (sz == 4 && cas->expdLo->Iex.Const.con->Ico.U32 == 5))
- {
- addInstr(env, TILEGXInstr_Acas(GXacas_FetchAddgez, r_old,
- r_addr->GXam.IR.base, r_exp,
- r_new, sz));
- }
- else
- {
- vassert(0);
- }
- }
- return;
- }
-
- /* --------- INSTR MARK --------- */
- /* Doesn't generate any executable code ... */
- case Ist_IMark:
- return;
-
- /* --------- ABI HINT --------- */
- /* These have no meaning (denotation in the IR) and so we ignore
- them ... if any actually made it this far. */
- case Ist_AbiHint:
- return;
-
- /* --------- NO-OP --------- */
- /* Fairly self-explanatory, wouldn't you say? */
- case Ist_NoOp:
- return;
-
- /* --------- EXIT --------- */
- case Ist_Exit: {
-
- TILEGXCondCode cc = iselCondCode(env, stmt->Ist.Exit.guard);
- TILEGXAMode* amPC = TILEGXAMode_IR(stmt->Ist.Exit.offsIP,
- TILEGXGuestStatePointer());
-
- /* Case: boring transfer to known address */
- if (stmt->Ist.Exit.jk == Ijk_Boring
- || stmt->Ist.Exit.jk == Ijk_Call
- /* || stmt->Ist.Exit.jk == Ijk_Ret */) {
- if (env->chainingAllowed) {
- /* .. almost always true .. */
- /* Skip the event check at the dst if this is a forwards
- edge. */
- Bool toFastEP =
- ((Addr64)stmt->Ist.Exit.dst->Ico.U64) > ((Addr64)env->max_ga);
-
- if (0) vex_printf("%s", toFastEP ? "Y" : ",");
- addInstr(env, TILEGXInstr_XDirect(
- (Addr64)stmt->Ist.Exit.dst->Ico.U64,
- amPC, cc, toFastEP));
- } else {
- /* .. very occasionally .. */
- /* We can't use chaining, so ask for an assisted transfer,
- as that's the only alternative that is allowable. */
- HReg r = iselWordExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
- addInstr(env, TILEGXInstr_XAssisted(r, amPC, cc, Ijk_Boring));
- }
- return;
- }
-
- /* Case: assisted transfer to arbitrary address */
- switch (stmt->Ist.Exit.jk) {
- /* Keep this list in sync with that in iselNext below */
- case Ijk_ClientReq:
- case Ijk_EmFail:
- case Ijk_EmWarn:
- case Ijk_NoDecode:
- case Ijk_NoRedir:
- case Ijk_SigBUS:
- case Ijk_Yield:
- case Ijk_SigTRAP:
- case Ijk_SigFPE_IntDiv:
- case Ijk_SigFPE_IntOvf:
- case Ijk_Sys_syscall:
- case Ijk_InvalICache:
- case Ijk_Ret:
- {
- HReg r = iselWordExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
- addInstr(env, TILEGXInstr_XAssisted(r, amPC, cc,
- stmt->Ist.Exit.jk));
- return;
- }
- default:
- break;
- }
-
- /* Do we ever expect to see any other kind? */
- goto stmt_fail;
- }
-
- default:
- break;
- }
-
- stmt_fail:
- vex_printf("stmt_fail tag: 0x%x\n", stmt->tag);
- ppIRStmt(stmt);
- vpanic("iselStmt:\n");
-}
-
-/*---------------------------------------------------------*/
-/*--- ISEL: Basic block terminators (Nexts) ---*/
-/*---------------------------------------------------------*/
-
-static void iselNext ( ISelEnv * env, IRExpr * next, IRJumpKind jk,
- Int offsIP )
-{
-
- if (vex_traceflags & VEX_TRACE_VCODE) {
- vex_printf("\n-- PUT(%d) = ", offsIP);
- ppIRExpr(next);
- vex_printf( "; exit-");
- ppIRJumpKind(jk);
- vex_printf( "\n");
- }
-
- /* Case: boring transfer to known address */
- if (next->tag == Iex_Const) {
- IRConst* cdst = next->Iex.Const.con;
- if (jk == Ijk_Boring || jk == Ijk_Call) {
- /* Boring transfer to known address */
- TILEGXAMode* amPC = TILEGXAMode_IR(offsIP, TILEGXGuestStatePointer());
- if (env->chainingAllowed) {
- /* .. almost always true .. */
- /* Skip the event check at the dst if this is a forwards
- edge. */
- Bool toFastEP = ((Addr64)cdst->Ico.U64) > ((Addr64)env->max_ga);
-
- if (0) vex_printf("%s", toFastEP ? "X" : ".");
- addInstr(env, TILEGXInstr_XDirect((Addr64)cdst->Ico.U64,
- amPC, TILEGXcc_AL, toFastEP));
- } else {
- /* .. very occasionally .. */
- /* We can't use chaining, so ask for an assisted transfer,
- as that's the only alternative that is allowable. */
- HReg r = iselWordExpr_R(env, next);
- addInstr(env, TILEGXInstr_XAssisted(r, amPC, TILEGXcc_AL,
- Ijk_Boring));
- }
- return;
- }
- }
-
- /* Case: call/return (==boring) transfer to any address */
- switch (jk) {
- case Ijk_Boring: case Ijk_Call: {
- HReg r = iselWordExpr_R(env, next);
- TILEGXAMode* amPC = TILEGXAMode_IR(offsIP,
- TILEGXGuestStatePointer());
- if (env->chainingAllowed)
- addInstr(env, TILEGXInstr_XIndir(r, amPC, TILEGXcc_AL));
- else
- addInstr(env, TILEGXInstr_XAssisted(r, amPC, TILEGXcc_AL,
- Ijk_Boring));
- return;
- }
- default:
- break;
- }
-
- /* Case: assisted transfer to arbitrary address */
- switch (jk) {
- /* Keep this list in sync with that for Ist_Exit above */
- case Ijk_ClientReq:
- case Ijk_EmFail:
- case Ijk_EmWarn:
- case Ijk_NoDecode:
- case Ijk_NoRedir:
- case Ijk_SigBUS:
- case Ijk_SigILL:
- case Ijk_SigTRAP:
- case Ijk_SigFPE_IntDiv:
- case Ijk_SigFPE_IntOvf:
- case Ijk_Sys_syscall:
- case Ijk_InvalICache:
- case Ijk_Ret: {
- HReg r = iselWordExpr_R(env, next);
- TILEGXAMode* amPC = TILEGXAMode_IR(offsIP, TILEGXGuestStatePointer());
- addInstr(env, TILEGXInstr_XAssisted(r, amPC, TILEGXcc_AL, jk));
- return;
- }
- default:
- break;
- }
-
- vex_printf("\n-- PUT(%d) = ", offsIP);
- ppIRExpr(next );
- vex_printf("; exit-");
- ppIRJumpKind(jk);
- vex_printf("\n");
- vassert(0); /* are we expecting any other kind? */
-}
-
-/*---------------------------------------------------------*/
-/*--- Insn selector top-level ---*/
-/*---------------------------------------------------------*/
-
-/* Translate an entire BB to tilegx code. */
-HInstrArray *iselSB_TILEGX ( const IRSB* bb,
- VexArch arch_host,
- const VexArchInfo* archinfo_host,
- const VexAbiInfo* vbi,
- Int offs_Host_EvC_Counter,
- Int offs_Host_EvC_FailAddr,
- Bool chainingAllowed,
- Bool addProfInc,
- Addr max_ga )
-{
- Int i, j;
- HReg hreg;
- ISelEnv *env;
- UInt hwcaps_host = archinfo_host->hwcaps;
- TILEGXAMode *amCounter, *amFailAddr;
-
- /* sanity ... */
- vassert(arch_host == VexArchTILEGX);
-
- /* Make up an initial environment to use. */
- env = LibVEX_Alloc(sizeof(ISelEnv));
- env->vreg_ctr = 0;
- env->mode64 = True;
-
- /* Set up output code array. */
- env->code = newHInstrArray();
-
- /* Copy BB's type env. */
- env->type_env = bb->tyenv;
-
- /* Make up an IRTemp -> virtual HReg mapping. This doesn't
- change as we go along. */
- env->n_vregmap = bb->tyenv->types_used;
- env->vregmap = LibVEX_Alloc(env->n_vregmap * sizeof(HReg));
-
- /* and finally ... */
- env->hwcaps = hwcaps_host;
- env->chainingAllowed = chainingAllowed;
- env->hwcaps = hwcaps_host;
- env->max_ga = max_ga;
-
- /* For each IR temporary, allocate a suitably-kinded virtual
- register. */
- j = 0;
-
- for (i = 0; i < env->n_vregmap; i++) {
- hreg = INVALID_HREG;
- switch (bb->tyenv->types[i]) {
- case Ity_I1:
- case Ity_I8:
- case Ity_I16:
- case Ity_I32:
- hreg = mkHReg(True, HRcInt64, 0, j++);
- break;
- case Ity_I64:
- hreg = mkHReg(True, HRcInt64, 0, j++);
- break;
- default:
- ppIRType(bb->tyenv->types[i]);
- vpanic("iselBB(tilegx): IRTemp type");
- }
- env->vregmap[i] = hreg;
- }
- env->vreg_ctr = j;
-
- /* The very first instruction must be an event check. */
- amCounter = TILEGXAMode_IR(offs_Host_EvC_Counter,
- TILEGXGuestStatePointer());
- amFailAddr = TILEGXAMode_IR(offs_Host_EvC_FailAddr,
- TILEGXGuestStatePointer());
- addInstr(env, TILEGXInstr_EvCheck(amCounter, amFailAddr));
-
- /* Possibly a block counter increment (for profiling). At this
- point we don't know the address of the counter, so just pretend
- it is zero. It will have to be patched later, but before this
- translation is used, by a call to LibVEX_patchProfCtr. */
- if (addProfInc) {
- addInstr(env, TILEGXInstr_ProfInc());
- }
-
- /* Ok, finally we can iterate over the statements. */
- for (i = 0; i < bb->stmts_used; i++)
- iselStmt(env, bb->stmts[i]);
-
- iselNext(env, bb->next, bb->jumpkind, bb->offsIP);
-
- /* record the number of vregs we used. */
- env->code->n_vregs = env->vreg_ctr;
- return env->code;
-}
-
-/*---------------------------------------------------------------*/
-/*--- end host_tilegx_isel.c ---*/
-/*---------------------------------------------------------------*/
diff --git a/VEX/priv/host_x86_defs.c b/VEX/priv/host_x86_defs.c
index 6321a3e..956e323 100644
--- a/VEX/priv/host_x86_defs.c
+++ b/VEX/priv/host_x86_defs.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/VEX/priv/host_x86_defs.h b/VEX/priv/host_x86_defs.h
index 3eacad7..0a3ed75 100644
--- a/VEX/priv/host_x86_defs.h
+++ b/VEX/priv/host_x86_defs.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/VEX/priv/host_x86_isel.c b/VEX/priv/host_x86_isel.c
index 56171bf..45aafeb 100644
--- a/VEX/priv/host_x86_isel.c
+++ b/VEX/priv/host_x86_isel.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -247,37 +247,37 @@
checks that all returned registers are virtual. You should not
call the _wrk version directly.
*/
-static X86RMI* iselIntExpr_RMI_wrk ( ISelEnv* env, IRExpr* e );
-static X86RMI* iselIntExpr_RMI ( ISelEnv* env, IRExpr* e );
+static X86RMI* iselIntExpr_RMI_wrk ( ISelEnv* env, const IRExpr* e );
+static X86RMI* iselIntExpr_RMI ( ISelEnv* env, const IRExpr* e );
-static X86RI* iselIntExpr_RI_wrk ( ISelEnv* env, IRExpr* e );
-static X86RI* iselIntExpr_RI ( ISelEnv* env, IRExpr* e );
+static X86RI* iselIntExpr_RI_wrk ( ISelEnv* env, const IRExpr* e );
+static X86RI* iselIntExpr_RI ( ISelEnv* env, const IRExpr* e );
-static X86RM* iselIntExpr_RM_wrk ( ISelEnv* env, IRExpr* e );
-static X86RM* iselIntExpr_RM ( ISelEnv* env, IRExpr* e );
+static X86RM* iselIntExpr_RM_wrk ( ISelEnv* env, const IRExpr* e );
+static X86RM* iselIntExpr_RM ( ISelEnv* env, const IRExpr* e );
-static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e );
-static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e );
+static HReg iselIntExpr_R_wrk ( ISelEnv* env, const IRExpr* e );
+static HReg iselIntExpr_R ( ISelEnv* env, const IRExpr* e );
-static X86AMode* iselIntExpr_AMode_wrk ( ISelEnv* env, IRExpr* e );
-static X86AMode* iselIntExpr_AMode ( ISelEnv* env, IRExpr* e );
+static X86AMode* iselIntExpr_AMode_wrk ( ISelEnv* env, const IRExpr* e );
+static X86AMode* iselIntExpr_AMode ( ISelEnv* env, const IRExpr* e );
static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo,
- ISelEnv* env, IRExpr* e );
+ ISelEnv* env, const IRExpr* e );
static void iselInt64Expr ( HReg* rHi, HReg* rLo,
- ISelEnv* env, IRExpr* e );
+ ISelEnv* env, const IRExpr* e );
-static X86CondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e );
-static X86CondCode iselCondCode ( ISelEnv* env, IRExpr* e );
+static X86CondCode iselCondCode_wrk ( ISelEnv* env, const IRExpr* e );
+static X86CondCode iselCondCode ( ISelEnv* env, const IRExpr* e );
-static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e );
-static HReg iselDblExpr ( ISelEnv* env, IRExpr* e );
+static HReg iselDblExpr_wrk ( ISelEnv* env, const IRExpr* e );
+static HReg iselDblExpr ( ISelEnv* env, const IRExpr* e );
-static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e );
-static HReg iselFltExpr ( ISelEnv* env, IRExpr* e );
+static HReg iselFltExpr_wrk ( ISelEnv* env, const IRExpr* e );
+static HReg iselFltExpr ( ISelEnv* env, const IRExpr* e );
-static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e );
-static HReg iselVecExpr ( ISelEnv* env, IRExpr* e );
+static HReg iselVecExpr_wrk ( ISelEnv* env, const IRExpr* e );
+static HReg iselVecExpr ( ISelEnv* env, const IRExpr* e );
/*---------------------------------------------------------*/
@@ -352,7 +352,7 @@
addInstr(env, X86Instr_Push(X86RMI_Reg(r_vecRetAddr)));
return 1;
}
- if (UNLIKELY(arg->tag == Iex_BBPTR)) {
+ if (UNLIKELY(arg->tag == Iex_GSPTR)) {
addInstr(env, X86Instr_Push(X86RMI_Reg(hregX86_EBP())));
return 1;
}
@@ -402,7 +402,7 @@
static
Bool mightRequireFixedRegs ( IRExpr* e )
{
- if (UNLIKELY(is_IRExpr_VECRET_or_BBPTR(e))) {
+ if (UNLIKELY(is_IRExpr_VECRET_or_GSPTR(e))) {
// These are always "safe" -- either a copy of %esp in some
// arbitrary vreg, or a copy of %ebp, respectively.
return False;
@@ -443,9 +443,9 @@
*retloc = mk_RetLoc_INVALID();
/* These are used for cross-checking that IR-level constraints on
- the use of Iex_VECRET and Iex_BBPTR are observed. */
+ the use of Iex_VECRET and Iex_GSPTR are observed. */
UInt nVECRETs = 0;
- UInt nBBPTRs = 0;
+ UInt nGSPTRs = 0;
/* Marshal args for a call, do the call, and clear the stack.
Complexities to consider:
@@ -458,7 +458,7 @@
is enough to preallocate the return space before marshalling
any arguments, in this case.
- |args| may also contain IRExpr_BBPTR(), in which case the
+ |args| may also contain IRExpr_GSPTR(), in which case the
value in %ebp is passed as the corresponding argument.
* If the callee claims regparmness of 1, 2 or 3, we must pass the
@@ -510,13 +510,13 @@
n_args++;
if (UNLIKELY(arg->tag == Iex_VECRET)) {
nVECRETs++;
- } else if (UNLIKELY(arg->tag == Iex_BBPTR)) {
- nBBPTRs++;
+ } else if (UNLIKELY(arg->tag == Iex_GSPTR)) {
+ nGSPTRs++;
}
}
/* If this fails, the IR is ill-formed */
- vassert(nBBPTRs == 0 || nBBPTRs == 1);
+ vassert(nGSPTRs == 0 || nGSPTRs == 1);
/* If we have a VECRET, allocate space on the stack for the return
value, and record the stack pointer after that. */
@@ -588,7 +588,7 @@
if (UNLIKELY(arg->tag == Iex_VECRET)) {
vassert(0); //ATC
}
- else if (UNLIKELY(arg->tag == Iex_BBPTR)) {
+ else if (UNLIKELY(arg->tag == Iex_GSPTR)) {
vassert(0); //ATC
} else {
vassert(typeOfIRExpr(env->type_env, arg) == Ity_I32);
@@ -615,7 +615,7 @@
X86RMI_Reg(r_vecRetAddr),
argregs[argreg]));
}
- else if (UNLIKELY(arg->tag == Iex_BBPTR)) {
+ else if (UNLIKELY(arg->tag == Iex_GSPTR)) {
vassert(0); //ATC
} else {
vassert(typeOfIRExpr(env->type_env, arg) == Ity_I32);
@@ -835,7 +835,7 @@
or sign extend partial values if necessary.
*/
-static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e )
+static HReg iselIntExpr_R ( ISelEnv* env, const IRExpr* e )
{
HReg r = iselIntExpr_R_wrk(env, e);
/* sanity checks ... */
@@ -848,7 +848,7 @@
}
/* DO NOT CALL THIS DIRECTLY ! */
-static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
+static HReg iselIntExpr_R_wrk ( ISelEnv* env, const IRExpr* e )
{
MatchInfo mi;
@@ -1161,7 +1161,7 @@
DEFINE_PATTERN(p_32to1_then_1Uto8,
unop(Iop_1Uto8,unop(Iop_32to1,bind(0))));
if (matchIRExpr(&mi,p_32to1_then_1Uto8,e)) {
- IRExpr* expr32 = mi.bindee[0];
+ const IRExpr* expr32 = mi.bindee[0];
HReg dst = newVRegI(env);
HReg src = iselIntExpr_R(env, expr32);
addInstr(env, mk_iMOVsd_RR(src,dst) );
@@ -1546,7 +1546,7 @@
}
}
-static X86AMode* iselIntExpr_AMode ( ISelEnv* env, IRExpr* e )
+static X86AMode* iselIntExpr_AMode ( ISelEnv* env, const IRExpr* e )
{
X86AMode* am = iselIntExpr_AMode_wrk(env, e);
vassert(sane_AMode(am));
@@ -1554,7 +1554,7 @@
}
/* DO NOT CALL THIS DIRECTLY ! */
-static X86AMode* iselIntExpr_AMode_wrk ( ISelEnv* env, IRExpr* e )
+static X86AMode* iselIntExpr_AMode_wrk ( ISelEnv* env, const IRExpr* e )
{
IRType ty = typeOfIRExpr(env->type_env,e);
vassert(ty == Ity_I32);
@@ -1621,7 +1621,7 @@
/* Similarly, calculate an expression into an X86RMI operand. As with
iselIntExpr_R, the expression can have type 32, 16 or 8 bits. */
-static X86RMI* iselIntExpr_RMI ( ISelEnv* env, IRExpr* e )
+static X86RMI* iselIntExpr_RMI ( ISelEnv* env, const IRExpr* e )
{
X86RMI* rmi = iselIntExpr_RMI_wrk(env, e);
/* sanity checks ... */
@@ -1641,7 +1641,7 @@
}
/* DO NOT CALL THIS DIRECTLY ! */
-static X86RMI* iselIntExpr_RMI_wrk ( ISelEnv* env, IRExpr* e )
+static X86RMI* iselIntExpr_RMI_wrk ( ISelEnv* env, const IRExpr* e )
{
IRType ty = typeOfIRExpr(env->type_env,e);
vassert(ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8);
@@ -1684,7 +1684,7 @@
/* Calculate an expression into an X86RI operand. As with
iselIntExpr_R, the expression can have type 32, 16 or 8 bits. */
-static X86RI* iselIntExpr_RI ( ISelEnv* env, IRExpr* e )
+static X86RI* iselIntExpr_RI ( ISelEnv* env, const IRExpr* e )
{
X86RI* ri = iselIntExpr_RI_wrk(env, e);
/* sanity checks ... */
@@ -1701,7 +1701,7 @@
}
/* DO NOT CALL THIS DIRECTLY ! */
-static X86RI* iselIntExpr_RI_wrk ( ISelEnv* env, IRExpr* e )
+static X86RI* iselIntExpr_RI_wrk ( ISelEnv* env, const IRExpr* e )
{
IRType ty = typeOfIRExpr(env->type_env,e);
vassert(ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8);
@@ -1731,7 +1731,7 @@
/* Similarly, calculate an expression into an X86RM operand. As with
iselIntExpr_R, the expression can have type 32, 16 or 8 bits. */
-static X86RM* iselIntExpr_RM ( ISelEnv* env, IRExpr* e )
+static X86RM* iselIntExpr_RM ( ISelEnv* env, const IRExpr* e )
{
X86RM* rm = iselIntExpr_RM_wrk(env, e);
/* sanity checks ... */
@@ -1749,7 +1749,7 @@
}
/* DO NOT CALL THIS DIRECTLY ! */
-static X86RM* iselIntExpr_RM_wrk ( ISelEnv* env, IRExpr* e )
+static X86RM* iselIntExpr_RM_wrk ( ISelEnv* env, const IRExpr* e )
{
IRType ty = typeOfIRExpr(env->type_env,e);
vassert(ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8);
@@ -1776,14 +1776,14 @@
condition code which would correspond when the expression would
notionally have returned 1. */
-static X86CondCode iselCondCode ( ISelEnv* env, IRExpr* e )
+static X86CondCode iselCondCode ( ISelEnv* env, const IRExpr* e )
{
/* Uh, there's nothing we can sanity check here, unfortunately. */
return iselCondCode_wrk(env,e);
}
/* DO NOT CALL THIS DIRECTLY ! */
-static X86CondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e )
+static X86CondCode iselCondCode_wrk ( ISelEnv* env, const IRExpr* e )
{
MatchInfo mi;
@@ -2069,7 +2069,8 @@
either real or virtual regs; in any case they must not be changed
by subsequent code emitted by the caller. */
-static void iselInt64Expr ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e )
+static void iselInt64Expr ( HReg* rHi, HReg* rLo, ISelEnv* env,
+ const IRExpr* e )
{
iselInt64Expr_wrk(rHi, rLo, env, e);
# if 0
@@ -2082,7 +2083,8 @@
}
/* DO NOT CALL THIS DIRECTLY ! */
-static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e )
+static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env,
+ const IRExpr* e )
{
MatchInfo mi;
HWord fn = 0; /* helper fn for most SIMD64 stuff */
@@ -2871,7 +2873,7 @@
/* Nothing interesting here; really just wrappers for
64-bit stuff. */
-static HReg iselFltExpr ( ISelEnv* env, IRExpr* e )
+static HReg iselFltExpr ( ISelEnv* env, const IRExpr* e )
{
HReg r = iselFltExpr_wrk( env, e );
# if 0
@@ -2883,7 +2885,7 @@
}
/* DO NOT CALL THIS DIRECTLY */
-static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e )
+static HReg iselFltExpr_wrk ( ISelEnv* env, const IRExpr* e )
{
IRType ty = typeOfIRExpr(env->type_env,e);
vassert(ty == Ity_F32);
@@ -2988,7 +2990,7 @@
positive zero 0 0 .000000---0
*/
-static HReg iselDblExpr ( ISelEnv* env, IRExpr* e )
+static HReg iselDblExpr ( ISelEnv* env, const IRExpr* e )
{
HReg r = iselDblExpr_wrk( env, e );
# if 0
@@ -3000,7 +3002,7 @@
}
/* DO NOT CALL THIS DIRECTLY */
-static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e )
+static HReg iselDblExpr_wrk ( ISelEnv* env, const IRExpr* e )
{
IRType ty = typeOfIRExpr(env->type_env,e);
vassert(e);
@@ -3239,7 +3241,7 @@
/*--- ISEL: SIMD (Vector) expressions, 128 bit. ---*/
/*---------------------------------------------------------*/
-static HReg iselVecExpr ( ISelEnv* env, IRExpr* e )
+static HReg iselVecExpr ( ISelEnv* env, const IRExpr* e )
{
HReg r = iselVecExpr_wrk( env, e );
# if 0
@@ -3252,7 +3254,7 @@
/* DO NOT CALL THIS DIRECTLY */
-static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
+static HReg iselVecExpr_wrk ( ISelEnv* env, const IRExpr* e )
{
# define REQUIRE_SSE1 \
diff --git a/VEX/priv/ir_defs.c b/VEX/priv/ir_defs.c
index 4940ffe..a853c2e 100644
--- a/VEX/priv/ir_defs.c
+++ b/VEX/priv/ir_defs.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -354,6 +354,11 @@
case Iop_RecpExpF64: vex_printf("RecpExpF64"); return;
case Iop_RecpExpF32: vex_printf("RecpExpF32"); return;
+ case Iop_MaxNumF64: vex_printf("MaxNumF64"); return;
+ case Iop_MinNumF64: vex_printf("MinNumF64"); return;
+ case Iop_MaxNumF32: vex_printf("MaxNumF32"); return;
+ case Iop_MinNumF32: vex_printf("MinNumF32"); return;
+
case Iop_F16toF64: vex_printf("F16toF64"); return;
case Iop_F64toF16: vex_printf("F64toF16"); return;
case Iop_F16toF32: vex_printf("F16toF32"); return;
@@ -1382,8 +1387,8 @@
case Iex_VECRET:
vex_printf("VECRET");
break;
- case Iex_BBPTR:
- vex_printf("BBPTR");
+ case Iex_GSPTR:
+ vex_printf("GSPTR");
break;
default:
vpanic("ppIRExpr");
@@ -1909,9 +1914,9 @@
e->tag = Iex_VECRET;
return e;
}
-IRExpr* IRExpr_BBPTR ( void ) {
+IRExpr* IRExpr_GSPTR ( void ) {
IRExpr* e = LibVEX_Alloc_inline(sizeof(IRExpr));
- e->tag = Iex_BBPTR;
+ e->tag = Iex_GSPTR;
return e;
}
@@ -2386,8 +2391,8 @@
case Iex_VECRET:
return IRExpr_VECRET();
- case Iex_BBPTR:
- return IRExpr_BBPTR();
+ case Iex_GSPTR:
+ return IRExpr_GSPTR();
case Iex_Binder:
return IRExpr_Binder(e->Iex.Binder.binder);
@@ -2838,7 +2843,13 @@
case Iop_RecpExpF32:
BINARY(ity_RMode,Ity_F32, Ity_F32);
- case Iop_CmpF32:
+ case Iop_MaxNumF64: case Iop_MinNumF64:
+ BINARY(Ity_F64,Ity_F64, Ity_F64);
+
+ case Iop_MaxNumF32: case Iop_MinNumF32:
+ BINARY(Ity_F32,Ity_F32, Ity_F32);
+
+ case Iop_CmpF32:
BINARY(Ity_F32,Ity_F32, Ity_I32);
case Iop_CmpF64:
@@ -3670,8 +3681,8 @@
vpanic("typeOfIRExpr: Binder is not a valid expression");
case Iex_VECRET:
vpanic("typeOfIRExpr: VECRET is not a valid expression");
- case Iex_BBPTR:
- vpanic("typeOfIRExpr: BBPTR is not a valid expression");
+ case Iex_GSPTR:
+ vpanic("typeOfIRExpr: GSPTR is not a valid expression");
default:
ppIRExpr(e);
vpanic("typeOfIRExpr");
@@ -3709,13 +3720,13 @@
}
*/
-static inline Bool isIRAtom_or_VECRET_or_BBPTR ( const IRExpr* e )
+static inline Bool isIRAtom_or_VECRET_or_GSPTR ( const IRExpr* e )
{
if (isIRAtom(e)) {
return True;
}
- return UNLIKELY(is_IRExpr_VECRET_or_BBPTR(e));
+ return UNLIKELY(is_IRExpr_VECRET_or_GSPTR(e));
}
Bool isFlatIRStmt ( const IRStmt* st )
@@ -3805,7 +3816,7 @@
if (!isIRAtom(di->guard))
return False;
for (i = 0; di->args[i]; i++)
- if (!isIRAtom_or_VECRET_or_BBPTR(di->args[i]))
+ if (!isIRAtom_or_VECRET_or_GSPTR(di->args[i]))
return False;
if (di->mAddr && !isIRAtom(di->mAddr))
return False;
@@ -3907,6 +3918,22 @@
}
static
+void assignedOnce_Temp(const IRSB *bb, const IRStmt *stmt, IRTemp tmp,
+ Int *def_counts, UInt n_def_counts,
+ const HChar *err_msg_out_of_range,
+ const HChar *err_msg_assigned_more_than_once)
+{
+ if (tmp < 0 || tmp >= n_def_counts) {
+ sanityCheckFail(bb, stmt, err_msg_out_of_range);
+ }
+
+ def_counts[tmp]++;
+ if (def_counts[tmp] > 1) {
+ sanityCheckFail(bb, stmt, err_msg_assigned_more_than_once);
+ }
+}
+
+static
void useBeforeDef_Expr ( const IRSB* bb, const IRStmt* stmt,
const IRExpr* expr, Int* def_counts )
{
@@ -3950,7 +3977,7 @@
case Iex_CCall:
for (i = 0; expr->Iex.CCall.args[i]; i++) {
const IRExpr* arg = expr->Iex.CCall.args[i];
- if (UNLIKELY(is_IRExpr_VECRET_or_BBPTR(arg))) {
+ if (UNLIKELY(is_IRExpr_VECRET_or_GSPTR(arg))) {
/* These aren't allowed in CCall lists. Let's detect
and throw them out here, though, rather than
segfaulting a bit later on. */
@@ -4032,7 +4059,7 @@
d = stmt->Ist.Dirty.details;
for (i = 0; d->args[i] != NULL; i++) {
IRExpr* arg = d->args[i];
- if (UNLIKELY(is_IRExpr_VECRET_or_BBPTR(arg))) {
+ if (UNLIKELY(is_IRExpr_VECRET_or_GSPTR(arg))) {
/* This is ensured by isFlatIRStmt */
;
} else {
@@ -4054,6 +4081,58 @@
}
static
+void assignedOnce_Stmt(const IRSB *bb, const IRStmt *stmt,
+ Int *def_counts, UInt n_def_counts)
+{
+ switch (stmt->tag) {
+ case Ist_WrTmp:
+ assignedOnce_Temp(
+ bb, stmt, stmt->Ist.WrTmp.tmp, def_counts, n_def_counts,
+ "IRStmt.Tmp: destination tmp is out of range",
+ "IRStmt.Tmp: destination tmp is assigned more than once");
+ break;
+ case Ist_LoadG:
+ assignedOnce_Temp(
+ bb, stmt, stmt->Ist.LoadG.details->dst, def_counts, n_def_counts,
+ "IRStmt.LoadG: destination tmp is out of range",
+ "IRStmt.LoadG: destination tmp is assigned more than once");
+ break;
+ case Ist_Dirty:
+ if (stmt->Ist.Dirty.details->tmp != IRTemp_INVALID) {
+ assignedOnce_Temp(
+ bb, stmt, stmt->Ist.Dirty.details->tmp, def_counts, n_def_counts,
+ "IRStmt.Dirty: destination tmp is out of range",
+ "IRStmt.Dirty: destination tmp is assigned more than once");
+ }
+ break;
+ case Ist_CAS:
+ if (stmt->Ist.CAS.details->oldHi != IRTemp_INVALID) {
+ assignedOnce_Temp(
+ bb, stmt, stmt->Ist.CAS.details->oldHi, def_counts, n_def_counts,
+ "IRStmt.CAS: destination tmpHi is out of range",
+ "IRStmt.CAS: destination tmpHi is assigned more than once");
+ }
+ assignedOnce_Temp(
+ bb, stmt, stmt->Ist.CAS.details->oldLo, def_counts, n_def_counts,
+ "IRStmt.CAS: destination tmpLo is out of range",
+ "IRStmt.CAS: destination tmpLo is assigned more than once");
+ break;
+ case Ist_LLSC:
+ assignedOnce_Temp(
+ bb, stmt, stmt->Ist.LLSC.result, def_counts, n_def_counts,
+ "IRStmt.LLSC: destination tmp is out of range",
+ "IRStmt.LLSC: destination tmp is assigned more than once");
+ break;
+ // Ignore all other cases
+ case Ist_NoOp: case Ist_IMark: case Ist_AbiHint: case Ist_Put: case Ist_PutI:
+ case Ist_Store: case Ist_StoreG: case Ist_MBE: case Ist_Exit:
+ break;
+ default:
+ vassert(0);
+ }
+}
+
+static
void tcExpr ( const IRSB* bb, const IRStmt* stmt, const IRExpr* expr,
IRType gWordTy )
{
@@ -4232,8 +4311,8 @@
if (i >= 32)
sanityCheckFail(bb,stmt,"Iex.CCall: > 32 args");
IRExpr* arg = expr->Iex.CCall.args[i];
- if (UNLIKELY(is_IRExpr_VECRET_or_BBPTR(arg)))
- sanityCheckFail(bb,stmt,"Iex.CCall.args: is VECRET/BBPTR");
+ if (UNLIKELY(is_IRExpr_VECRET_or_GSPTR(arg)))
+ sanityCheckFail(bb,stmt,"Iex.CCall.args: is VECRET/GSPTR");
tcExpr(bb,stmt, arg, gWordTy);
}
if (expr->Iex.CCall.retty == Ity_I1)
@@ -4351,7 +4430,7 @@
":: guest word type");
if (typeOfIRExpr(tyenv, lg->alt) != typeOfIRTemp(tyenv, lg->dst))
sanityCheckFail(bb,stmt,"IRStmt.LoadG: dst/alt type mismatch");
- IRTemp cvtRes = Ity_INVALID, cvtArg = Ity_INVALID;
+ IRType cvtRes = Ity_INVALID, cvtArg = Ity_INVALID;
typeOfIRLoadGOp(lg->cvt, &cvtRes, &cvtArg);
if (cvtRes != typeOfIRTemp(tyenv, lg->dst))
sanityCheckFail(bb,stmt,"IRStmt.LoadG: dst/loaded type mismatch");
@@ -4472,21 +4551,21 @@
if (retTy == Ity_I1)
sanityCheckFail(bb,stmt,"IRStmt.Dirty.dst :: Ity_I1");
}
- UInt nVECRETs = 0, nBBPTRs = 0;
+ UInt nVECRETs = 0, nGSPTRs = 0;
for (i = 0; d->args[i] != NULL; i++) {
if (i >= 32)
sanityCheckFail(bb,stmt,"IRStmt.Dirty: > 32 args");
const IRExpr* arg = d->args[i];
if (UNLIKELY(arg->tag == Iex_VECRET)) {
nVECRETs++;
- } else if (UNLIKELY(arg->tag == Iex_BBPTR)) {
- nBBPTRs++;
+ } else if (UNLIKELY(arg->tag == Iex_GSPTR)) {
+ nGSPTRs++;
} else {
if (typeOfIRExpr(tyenv, arg) == Ity_I1)
sanityCheckFail(bb,stmt,"IRStmt.Dirty.arg[i] :: Ity_I1");
}
- if (nBBPTRs > 1) {
- sanityCheckFail(bb,stmt,"IRStmt.Dirty.args: > 1 BBPTR arg");
+ if (nGSPTRs > 1) {
+ sanityCheckFail(bb,stmt,"IRStmt.Dirty.args: > 1 GSPTR arg");
}
if (nVECRETs == 1) {
/* Fn must return V128 or V256. */
@@ -4505,15 +4584,15 @@
"IRStmt.Dirty.args: > 1 VECRET present");
}
}
- if (nBBPTRs > 1) {
+ if (nGSPTRs > 1) {
sanityCheckFail(bb,stmt,
- "IRStmt.Dirty.args: > 1 BBPTR present");
+ "IRStmt.Dirty.args: > 1 GSPTR present");
}
/* If you ask for the baseblock pointer, you have to make
some declaration about access to the guest state too. */
- if (d->nFxState == 0 && nBBPTRs != 0) {
+ if (d->nFxState == 0 && nGSPTRs != 0) {
sanityCheckFail(bb,stmt,
- "IRStmt.Dirty.args: BBPTR requested, "
+ "IRStmt.Dirty.args: GSPTR requested, "
"but no fxState declared");
}
break;
@@ -4603,79 +4682,12 @@
useBeforeDef_Stmt(bb,stmt,def_counts);
/* Now make note of any temps defd by this statement. */
- switch (stmt->tag) {
- case Ist_WrTmp:
- if (stmt->Ist.WrTmp.tmp < 0 || stmt->Ist.WrTmp.tmp >= n_temps)
- sanityCheckFail(bb, stmt,
- "IRStmt.Tmp: destination tmp is out of range");
- def_counts[stmt->Ist.WrTmp.tmp]++;
- if (def_counts[stmt->Ist.WrTmp.tmp] > 1)
- sanityCheckFail(bb, stmt,
- "IRStmt.Tmp: destination tmp is assigned more than once");
- break;
- case Ist_LoadG: {
- const IRLoadG* lg = stmt->Ist.LoadG.details;
- if (lg->dst < 0 || lg->dst >= n_temps)
- sanityCheckFail(bb, stmt,
- "IRStmt.LoadG: destination tmp is out of range");
- def_counts[lg->dst]++;
- if (def_counts[lg->dst] > 1)
- sanityCheckFail(bb, stmt,
- "IRStmt.LoadG: destination tmp is assigned more than once");
- break;
- }
- case Ist_Dirty: {
- const IRDirty* d = stmt->Ist.Dirty.details;
- if (d->tmp != IRTemp_INVALID) {
- if (d->tmp < 0 || d->tmp >= n_temps)
- sanityCheckFail(bb, stmt,
- "IRStmt.Dirty: destination tmp is out of range");
- def_counts[d->tmp]++;
- if (def_counts[d->tmp] > 1)
- sanityCheckFail(bb, stmt,
- "IRStmt.Dirty: destination tmp is assigned more than once");
- }
- break;
- }
- case Ist_CAS: {
- const IRCAS* cas = stmt->Ist.CAS.details;
- if (cas->oldHi != IRTemp_INVALID) {
- if (cas->oldHi < 0 || cas->oldHi >= n_temps)
- sanityCheckFail(bb, stmt,
- "IRStmt.CAS: destination tmpHi is out of range");
- def_counts[cas->oldHi]++;
- if (def_counts[cas->oldHi] > 1)
- sanityCheckFail(bb, stmt,
- "IRStmt.CAS: destination tmpHi is assigned more than once");
- }
- if (cas->oldLo < 0 || cas->oldLo >= n_temps)
- sanityCheckFail(bb, stmt,
- "IRStmt.CAS: destination tmpLo is out of range");
- def_counts[cas->oldLo]++;
- if (def_counts[cas->oldLo] > 1)
- sanityCheckFail(bb, stmt,
- "IRStmt.CAS: destination tmpLo is assigned more than once");
- break;
- }
- case Ist_LLSC:
- if (stmt->Ist.LLSC.result < 0 || stmt->Ist.LLSC.result >= n_temps)
- sanityCheckFail(bb, stmt,
- "IRStmt.LLSC: destination tmp is out of range");
- def_counts[stmt->Ist.LLSC.result]++;
- if (def_counts[stmt->Ist.LLSC.result] > 1)
- sanityCheckFail(bb, stmt,
- "IRStmt.LLSC: destination tmp is assigned more than once");
- break;
- default:
- /* explicitly handle the rest, so as to keep gcc quiet */
- break;
- }
+ assignedOnce_Stmt(bb, stmt, def_counts, n_temps);
}
/* Typecheck everything. */
for (i = 0; i < bb->stmts_used; i++)
- if (bb->stmts[i])
- tcStmt( bb, bb->stmts[i], guest_word_size );
+ tcStmt(bb, bb->stmts[i], guest_word_size);
if (typeOfIRExpr(bb->tyenv,bb->next) != guest_word_size)
sanityCheckFail(bb, NULL, "bb->next field has wrong type");
/* because it would intersect with host_EvC_* */
diff --git a/VEX/priv/ir_inject.c b/VEX/priv/ir_inject.c
index 94b0fdf..c127aca 100644
--- a/VEX/priv/ir_inject.c
+++ b/VEX/priv/ir_inject.c
@@ -9,7 +9,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2012-2015 Florian Krohm (britzel@acm.org)
+ Copyright (C) 2012-2017 Florian Krohm (britzel@acm.org)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/VEX/priv/ir_match.c b/VEX/priv/ir_match.c
index 40fd46f..b88a66a 100644
--- a/VEX/priv/ir_match.c
+++ b/VEX/priv/ir_match.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -42,7 +42,7 @@
/* Assign a value to a binder. Checks for obvious stupidities. */
static
-void setBindee ( MatchInfo* mi, Int n, IRExpr* bindee )
+void setBindee ( MatchInfo* mi, Int n, const IRExpr* bindee )
{
if (n < 0 || n >= N_IRMATCH_BINDERS)
vpanic("setBindee: out of range index");
@@ -57,7 +57,8 @@
found into 'mi'. */
static
-Bool matchWrk ( MatchInfo* mi, IRExpr* p/*attern*/, IRExpr* e/*xpr*/ )
+Bool matchWrk ( MatchInfo* mi, const IRExpr* p/*attern*/,
+ const IRExpr* e/*xpr*/ )
{
switch (p->tag) {
case Iex_Binder: /* aha, what we were looking for. */
@@ -96,7 +97,8 @@
/* Top level entry point to the matcher. */
-Bool matchIRExpr ( MatchInfo* mi, IRExpr* p/*attern*/, IRExpr* e/*xpr*/ )
+Bool matchIRExpr ( MatchInfo* mi, const IRExpr* p/*attern*/,
+ const IRExpr* e/*xpr*/ )
{
Int i;
for (i = 0; i < N_IRMATCH_BINDERS; i++)
diff --git a/VEX/priv/ir_match.h b/VEX/priv/ir_match.h
index f339426..4691bd0 100644
--- a/VEX/priv/ir_match.h
+++ b/VEX/priv/ir_match.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -68,7 +68,7 @@
typedef
struct {
- IRExpr* bindee[N_IRMATCH_BINDERS];
+ const IRExpr* bindee[N_IRMATCH_BINDERS];
}
MatchInfo;
@@ -78,7 +78,8 @@
succeeded. */
extern
-Bool matchIRExpr ( MatchInfo* mi, IRExpr* p/*attern*/, IRExpr* e/*xpr*/ );
+Bool matchIRExpr ( MatchInfo* mi, const IRExpr* p/*attern*/,
+ const IRExpr* e/*xpr*/ );
#endif /* ndef __VEX_IR_MATCH_H */
diff --git a/VEX/priv/ir_opt.c b/VEX/priv/ir_opt.c
index 4266823..f40870b 100644
--- a/VEX/priv/ir_opt.c
+++ b/VEX/priv/ir_opt.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -488,7 +488,7 @@
d2->guard = flatten_Expr(bb, d2->guard);
for (i = 0; d2->args[i]; i++) {
IRExpr* arg = d2->args[i];
- if (LIKELY(!is_IRExpr_VECRET_or_BBPTR(arg)))
+ if (LIKELY(!is_IRExpr_VECRET_or_GSPTR(arg)))
d2->args[i] = flatten_Expr(bb, arg);
}
addStmtToIRSB(bb, IRStmt_Dirty(d2));
@@ -2702,7 +2702,7 @@
d2->guard = fold_Expr(env, subst_Expr(env, d2->guard));
for (i = 0; d2->args[i]; i++) {
IRExpr* arg = d2->args[i];
- if (LIKELY(!is_IRExpr_VECRET_or_BBPTR(arg))) {
+ if (LIKELY(!is_IRExpr_VECRET_or_GSPTR(arg))) {
vassert(isIRAtom(arg));
d2->args[i] = fold_Expr(env, subst_Expr(env, arg));
}
@@ -3045,7 +3045,7 @@
addUses_Expr(set, d->guard);
for (i = 0; d->args[i] != NULL; i++) {
IRExpr* arg = d->args[i];
- if (LIKELY(!is_IRExpr_VECRET_or_BBPTR(arg)))
+ if (LIKELY(!is_IRExpr_VECRET_or_GSPTR(arg)))
addUses_Expr(set, arg);
}
return;
@@ -4670,7 +4670,7 @@
deltaIRExpr(d->guard, delta);
for (i = 0; d->args[i]; i++) {
IRExpr* arg = d->args[i];
- if (LIKELY(!is_IRExpr_VECRET_or_BBPTR(arg)))
+ if (LIKELY(!is_IRExpr_VECRET_or_GSPTR(arg)))
deltaIRExpr(arg, delta);
}
if (d->tmp != IRTemp_INVALID)
@@ -5207,7 +5207,7 @@
aoccCount_Expr(uses, d->guard);
for (i = 0; d->args[i]; i++) {
IRExpr* arg = d->args[i];
- if (LIKELY(!is_IRExpr_VECRET_or_BBPTR(arg)))
+ if (LIKELY(!is_IRExpr_VECRET_or_GSPTR(arg)))
aoccCount_Expr(uses, arg);
}
return;
@@ -5598,7 +5598,7 @@
d2->guard = atbSubst_Expr(env, d2->guard);
for (i = 0; d2->args[i]; i++) {
IRExpr* arg = d2->args[i];
- if (LIKELY(!is_IRExpr_VECRET_or_BBPTR(arg)))
+ if (LIKELY(!is_IRExpr_VECRET_or_GSPTR(arg)))
d2->args[i] = atbSubst_Expr(env, arg);
}
return IRStmt_Dirty(d2);
@@ -5629,7 +5629,7 @@
guest state under the covers. It's not allowed, but let's be
extra conservative and assume the worst. */
for (i = 0; d->args[i]; i++) {
- if (UNLIKELY(d->args[i]->tag == Iex_BBPTR)) {
+ if (UNLIKELY(d->args[i]->tag == Iex_GSPTR)) {
*requiresPreciseMemExns = True;
/* Assume all guest state is written. */
interval.present = True;
@@ -6007,7 +6007,7 @@
case Iex_RdTmp:
ppIRTemp(e->Iex.RdTmp.tmp);
vex_printf("=");
- print_flat_expr(env, chase(env, e));
+ print_flat_expr(env, chase1(env, e));
break;
case Iex_Const:
case Iex_CCall:
@@ -6328,7 +6328,7 @@
vassert(isIRAtom(d->guard));
for (Int j = 0; d->args[j]; j++) {
IRExpr* arg = d->args[j];
- if (LIKELY(!is_IRExpr_VECRET_or_BBPTR(arg))) {
+ if (LIKELY(!is_IRExpr_VECRET_or_GSPTR(arg))) {
vassert(isIRAtom(arg));
}
}
@@ -6537,7 +6537,7 @@
vassert(isIRAtom(d->guard));
for (j = 0; d->args[j]; j++) {
IRExpr* arg = d->args[j];
- if (LIKELY(!is_IRExpr_VECRET_or_BBPTR(arg)))
+ if (LIKELY(!is_IRExpr_VECRET_or_GSPTR(arg)))
vassert(isIRAtom(arg));
}
if (d->mFx != Ifx_None)
diff --git a/VEX/priv/ir_opt.h b/VEX/priv/ir_opt.h
index f012962..f67ed00 100644
--- a/VEX/priv/ir_opt.h
+++ b/VEX/priv/ir_opt.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/VEX/priv/main_globals.c b/VEX/priv/main_globals.c
index 8f3a394..97a161e 100644
--- a/VEX/priv/main_globals.c
+++ b/VEX/priv/main_globals.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/VEX/priv/main_globals.h b/VEX/priv/main_globals.h
index af13e75..cab88b6 100644
--- a/VEX/priv/main_globals.h
+++ b/VEX/priv/main_globals.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c
index e263754..7c125ce 100644
--- a/VEX/priv/main_main.c
+++ b/VEX/priv/main_main.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -45,7 +45,6 @@
#include "libvex_guest_s390x.h"
#include "libvex_guest_mips32.h"
#include "libvex_guest_mips64.h"
-#include "libvex_guest_tilegx.h"
#include "main_globals.h"
#include "main_util.h"
@@ -59,7 +58,6 @@
#include "host_arm64_defs.h"
#include "host_s390_defs.h"
#include "host_mips_defs.h"
-#include "host_tilegx_defs.h"
#include "guest_generic_bb_to_IR.h"
#include "guest_x86_defs.h"
@@ -69,7 +67,6 @@
#include "guest_ppc_defs.h"
#include "guest_s390_defs.h"
#include "guest_mips_defs.h"
-#include "guest_tilegx_defs.h"
#include "host_generic_simd128.h"
@@ -158,14 +155,6 @@
#define MIPS64ST(f) vassert(0)
#endif
-#if defined(VGA_tilegx) || defined(VEXMULTIARCH)
-#define TILEGXFN(f) f
-#define TILEGXST(f) f
-#else
-#define TILEGXFN(f) NULL
-#define TILEGXST(f) vassert(0)
-#endif
-
/* This file contains the top level interface to the library. */
@@ -173,7 +162,7 @@
static void check_hwcaps ( VexArch arch, UInt hwcaps );
static const HChar* show_hwcaps ( VexArch arch, UInt hwcaps );
-
+static IRType arch_word_size ( VexArch arch );
/* --------- helpers --------- */
@@ -306,6 +295,7 @@
/* --------- Make a translation. --------- */
+
/* KLUDGE: S390 need to know the hwcaps of the host when generating
code. But that info is not passed to emit_S390Instr. Only mode64 is
being passed. So, ideally, we want this passed as an argument, too.
@@ -318,72 +308,31 @@
/* Exported to library client. */
-VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta )
+IRSB* LibVEX_FrontEnd ( /*MOD*/ VexTranslateArgs* vta,
+ /*OUT*/ VexTranslateResult* res,
+ /*OUT*/ VexRegisterUpdates* pxControl)
{
- /* This the bundle of functions we need to do the back-end stuff
- (insn selection, reg-alloc, assembly) whilst being insulated
- from the target instruction set. */
- Bool (*isMove) ( const HInstr*, HReg*, HReg* );
- void (*getRegUsage) ( HRegUsage*, const HInstr*, Bool );
- void (*mapRegs) ( HRegRemap*, HInstr*, Bool );
- void (*genSpill) ( HInstr**, HInstr**, HReg, Int, Bool );
- void (*genReload) ( HInstr**, HInstr**, HReg, Int, Bool );
- HInstr* (*directReload) ( HInstr*, HReg, Short );
- void (*ppInstr) ( const HInstr*, Bool );
- void (*ppReg) ( HReg );
- HInstrArray* (*iselSB) ( const IRSB*, VexArch, const VexArchInfo*,
- const VexAbiInfo*, Int, Int, Bool, Bool,
- Addr );
- Int (*emit) ( /*MB_MOD*/Bool*,
- UChar*, Int, const HInstr*, Bool, VexEndness,
- const void*, const void*, const void*,
- const void* );
IRExpr* (*specHelper) ( const HChar*, IRExpr**, IRStmt**, Int );
- Bool (*preciseMemExnsFn) ( Int, Int, VexRegisterUpdates );
-
- const RRegUniverse* rRegUniv = NULL;
-
+ Bool (*preciseMemExnsFn) ( Int, Int, VexRegisterUpdates );
DisOneInstrFn disInstrFn;
VexGuestLayout* guest_layout;
IRSB* irsb;
- HInstrArray* vcode;
- HInstrArray* rcode;
- Int i, j, k, out_used, guest_sizeB;
+ Int i;
Int offB_CMSTART, offB_CMLEN, offB_GUEST_IP, szB_GUEST_IP;
- Int offB_HOST_EvC_COUNTER, offB_HOST_EvC_FAILADDR;
- UChar insn_bytes[128];
IRType guest_word_type;
IRType host_word_type;
- Bool mode64, chainingAllowed;
- Addr max_ga;
- guest_layout = NULL;
- isMove = NULL;
- getRegUsage = NULL;
- mapRegs = NULL;
- genSpill = NULL;
- genReload = NULL;
- directReload = NULL;
- ppInstr = NULL;
- ppReg = NULL;
- iselSB = NULL;
- emit = NULL;
- specHelper = NULL;
- preciseMemExnsFn = NULL;
- disInstrFn = NULL;
- guest_word_type = Ity_INVALID;
- host_word_type = Ity_INVALID;
- offB_CMSTART = 0;
- offB_CMLEN = 0;
- offB_GUEST_IP = 0;
- szB_GUEST_IP = 0;
- offB_HOST_EvC_COUNTER = 0;
- offB_HOST_EvC_FAILADDR = 0;
- mode64 = False;
- chainingAllowed = False;
-
- vex_traceflags = vta->traceflags;
+ guest_layout = NULL;
+ specHelper = NULL;
+ disInstrFn = NULL;
+ preciseMemExnsFn = NULL;
+ guest_word_type = arch_word_size(vta->arch_guest);
+ host_word_type = arch_word_size(vta->arch_host);
+ offB_CMSTART = 0;
+ offB_CMLEN = 0;
+ offB_GUEST_IP = 0;
+ szB_GUEST_IP = 0;
vassert(vex_initdone);
vassert(vta->needs_self_check != NULL);
@@ -392,7 +341,6 @@
if (vta->disp_cp_chain_me_to_slowEP != NULL) {
vassert(vta->disp_cp_chain_me_to_fastEP != NULL);
vassert(vta->disp_cp_xindir != NULL);
- chainingAllowed = True;
} else {
vassert(vta->disp_cp_chain_me_to_fastEP == NULL);
vassert(vta->disp_cp_xindir == NULL);
@@ -401,212 +349,28 @@
vexSetAllocModeTEMP_and_clear();
vexAllocSanityCheck();
- /* First off, check that the guest and host insn sets
- are supported. */
+ vex_traceflags = vta->traceflags;
- switch (vta->arch_host) {
-
- case VexArchX86:
- mode64 = False;
- rRegUniv = X86FN(getRRegUniverse_X86());
- isMove = (__typeof__(isMove)) X86FN(isMove_X86Instr);
- getRegUsage
- = (__typeof__(getRegUsage)) X86FN(getRegUsage_X86Instr);
- mapRegs = (__typeof__(mapRegs)) X86FN(mapRegs_X86Instr);
- genSpill = (__typeof__(genSpill)) X86FN(genSpill_X86);
- genReload = (__typeof__(genReload)) X86FN(genReload_X86);
- directReload = (__typeof__(directReload)) X86FN(directReload_X86);
- ppInstr = (__typeof__(ppInstr)) X86FN(ppX86Instr);
- ppReg = (__typeof__(ppReg)) X86FN(ppHRegX86);
- iselSB = X86FN(iselSB_X86);
- emit = (__typeof__(emit)) X86FN(emit_X86Instr);
- host_word_type = Ity_I32;
- vassert(vta->archinfo_host.endness == VexEndnessLE);
- break;
-
- case VexArchAMD64:
- mode64 = True;
- rRegUniv = AMD64FN(getRRegUniverse_AMD64());
- isMove = (__typeof__(isMove)) AMD64FN(isMove_AMD64Instr);
- getRegUsage
- = (__typeof__(getRegUsage)) AMD64FN(getRegUsage_AMD64Instr);
- mapRegs = (__typeof__(mapRegs)) AMD64FN(mapRegs_AMD64Instr);
- genSpill = (__typeof__(genSpill)) AMD64FN(genSpill_AMD64);
- genReload = (__typeof__(genReload)) AMD64FN(genReload_AMD64);
- ppInstr = (__typeof__(ppInstr)) AMD64FN(ppAMD64Instr);
- ppReg = (__typeof__(ppReg)) AMD64FN(ppHRegAMD64);
- iselSB = AMD64FN(iselSB_AMD64);
- emit = (__typeof__(emit)) AMD64FN(emit_AMD64Instr);
- host_word_type = Ity_I64;
- vassert(vta->archinfo_host.endness == VexEndnessLE);
- break;
-
- case VexArchPPC32:
- mode64 = False;
- rRegUniv = PPC32FN(getRRegUniverse_PPC(mode64));
- isMove = (__typeof__(isMove)) PPC32FN(isMove_PPCInstr);
- getRegUsage
- = (__typeof__(getRegUsage)) PPC32FN(getRegUsage_PPCInstr);
- mapRegs = (__typeof__(mapRegs)) PPC32FN(mapRegs_PPCInstr);
- genSpill = (__typeof__(genSpill)) PPC32FN(genSpill_PPC);
- genReload = (__typeof__(genReload)) PPC32FN(genReload_PPC);
- ppInstr = (__typeof__(ppInstr)) PPC32FN(ppPPCInstr);
- ppReg = (__typeof__(ppReg)) PPC32FN(ppHRegPPC);
- iselSB = PPC32FN(iselSB_PPC);
- emit = (__typeof__(emit)) PPC32FN(emit_PPCInstr);
- host_word_type = Ity_I32;
- vassert(vta->archinfo_host.endness == VexEndnessBE);
- break;
-
- case VexArchPPC64:
- mode64 = True;
- rRegUniv = PPC64FN(getRRegUniverse_PPC(mode64));
- isMove = (__typeof__(isMove)) PPC64FN(isMove_PPCInstr);
- getRegUsage
- = (__typeof__(getRegUsage)) PPC64FN(getRegUsage_PPCInstr);
- mapRegs = (__typeof__(mapRegs)) PPC64FN(mapRegs_PPCInstr);
- genSpill = (__typeof__(genSpill)) PPC64FN(genSpill_PPC);
- genReload = (__typeof__(genReload)) PPC64FN(genReload_PPC);
- ppInstr = (__typeof__(ppInstr)) PPC64FN(ppPPCInstr);
- ppReg = (__typeof__(ppReg)) PPC64FN(ppHRegPPC);
- iselSB = PPC64FN(iselSB_PPC);
- emit = (__typeof__(emit)) PPC64FN(emit_PPCInstr);
- host_word_type = Ity_I64;
- vassert(vta->archinfo_host.endness == VexEndnessBE ||
- vta->archinfo_host.endness == VexEndnessLE );
- break;
-
- case VexArchS390X:
- mode64 = True;
- /* KLUDGE: export hwcaps. */
- s390_host_hwcaps = vta->archinfo_host.hwcaps;
- rRegUniv = S390FN(getRRegUniverse_S390());
- isMove = (__typeof__(isMove)) S390FN(isMove_S390Instr);
- getRegUsage
- = (__typeof__(getRegUsage)) S390FN(getRegUsage_S390Instr);
- mapRegs = (__typeof__(mapRegs)) S390FN(mapRegs_S390Instr);
- genSpill = (__typeof__(genSpill)) S390FN(genSpill_S390);
- genReload = (__typeof__(genReload)) S390FN(genReload_S390);
- // fixs390: consider implementing directReload_S390
- ppInstr = (__typeof__(ppInstr)) S390FN(ppS390Instr);
- ppReg = (__typeof__(ppReg)) S390FN(ppHRegS390);
- iselSB = S390FN(iselSB_S390);
- emit = (__typeof__(emit)) S390FN(emit_S390Instr);
- host_word_type = Ity_I64;
- vassert(vta->archinfo_host.endness == VexEndnessBE);
- break;
-
- case VexArchARM:
- mode64 = False;
- rRegUniv = ARMFN(getRRegUniverse_ARM());
- isMove = (__typeof__(isMove)) ARMFN(isMove_ARMInstr);
- getRegUsage
- = (__typeof__(getRegUsage)) ARMFN(getRegUsage_ARMInstr);
- mapRegs = (__typeof__(mapRegs)) ARMFN(mapRegs_ARMInstr);
- genSpill = (__typeof__(genSpill)) ARMFN(genSpill_ARM);
- genReload = (__typeof__(genReload)) ARMFN(genReload_ARM);
- ppInstr = (__typeof__(ppInstr)) ARMFN(ppARMInstr);
- ppReg = (__typeof__(ppReg)) ARMFN(ppHRegARM);
- iselSB = ARMFN(iselSB_ARM);
- emit = (__typeof__(emit)) ARMFN(emit_ARMInstr);
- host_word_type = Ity_I32;
- vassert(vta->archinfo_host.endness == VexEndnessLE);
- break;
-
- case VexArchARM64:
- mode64 = True;
- rRegUniv = ARM64FN(getRRegUniverse_ARM64());
- isMove = (__typeof__(isMove)) ARM64FN(isMove_ARM64Instr);
- getRegUsage
- = (__typeof__(getRegUsage)) ARM64FN(getRegUsage_ARM64Instr);
- mapRegs = (__typeof__(mapRegs)) ARM64FN(mapRegs_ARM64Instr);
- genSpill = (__typeof__(genSpill)) ARM64FN(genSpill_ARM64);
- genReload = (__typeof__(genReload)) ARM64FN(genReload_ARM64);
- ppInstr = (__typeof__(ppInstr)) ARM64FN(ppARM64Instr);
- ppReg = (__typeof__(ppReg)) ARM64FN(ppHRegARM64);
- iselSB = ARM64FN(iselSB_ARM64);
- emit = (__typeof__(emit)) ARM64FN(emit_ARM64Instr);
- host_word_type = Ity_I64;
- vassert(vta->archinfo_host.endness == VexEndnessLE);
- break;
-
- case VexArchMIPS32:
- mode64 = False;
- rRegUniv = MIPS32FN(getRRegUniverse_MIPS(mode64));
- isMove = (__typeof__(isMove)) MIPS32FN(isMove_MIPSInstr);
- getRegUsage
- = (__typeof__(getRegUsage)) MIPS32FN(getRegUsage_MIPSInstr);
- mapRegs = (__typeof__(mapRegs)) MIPS32FN(mapRegs_MIPSInstr);
- genSpill = (__typeof__(genSpill)) MIPS32FN(genSpill_MIPS);
- genReload = (__typeof__(genReload)) MIPS32FN(genReload_MIPS);
- ppInstr = (__typeof__(ppInstr)) MIPS32FN(ppMIPSInstr);
- ppReg = (__typeof__(ppReg)) MIPS32FN(ppHRegMIPS);
- iselSB = MIPS32FN(iselSB_MIPS);
- emit = (__typeof__(emit)) MIPS32FN(emit_MIPSInstr);
- host_word_type = Ity_I32;
- vassert(vta->archinfo_host.endness == VexEndnessLE
- || vta->archinfo_host.endness == VexEndnessBE);
- break;
-
- case VexArchMIPS64:
- mode64 = True;
- rRegUniv = MIPS64FN(getRRegUniverse_MIPS(mode64));
- isMove = (__typeof__(isMove)) MIPS64FN(isMove_MIPSInstr);
- getRegUsage
- = (__typeof__(getRegUsage)) MIPS64FN(getRegUsage_MIPSInstr);
- mapRegs = (__typeof__(mapRegs)) MIPS64FN(mapRegs_MIPSInstr);
- genSpill = (__typeof__(genSpill)) MIPS64FN(genSpill_MIPS);
- genReload = (__typeof__(genReload)) MIPS64FN(genReload_MIPS);
- ppInstr = (__typeof__(ppInstr)) MIPS64FN(ppMIPSInstr);
- ppReg = (__typeof__(ppReg)) MIPS64FN(ppHRegMIPS);
- iselSB = MIPS64FN(iselSB_MIPS);
- emit = (__typeof__(emit)) MIPS64FN(emit_MIPSInstr);
- host_word_type = Ity_I64;
- vassert(vta->archinfo_host.endness == VexEndnessLE
- || vta->archinfo_host.endness == VexEndnessBE);
- break;
-
- case VexArchTILEGX:
- mode64 = True;
- rRegUniv = TILEGXFN(getRRegUniverse_TILEGX());
- isMove = (__typeof__(isMove)) TILEGXFN(isMove_TILEGXInstr);
- getRegUsage =
- (__typeof__(getRegUsage)) TILEGXFN(getRegUsage_TILEGXInstr);
- mapRegs = (__typeof__(mapRegs)) TILEGXFN(mapRegs_TILEGXInstr);
- genSpill = (__typeof__(genSpill)) TILEGXFN(genSpill_TILEGX);
- genReload = (__typeof__(genReload)) TILEGXFN(genReload_TILEGX);
- ppInstr = (__typeof__(ppInstr)) TILEGXFN(ppTILEGXInstr);
- ppReg = (__typeof__(ppReg)) TILEGXFN(ppHRegTILEGX);
- iselSB = TILEGXFN(iselSB_TILEGX);
- emit = (__typeof__(emit)) TILEGXFN(emit_TILEGXInstr);
- host_word_type = Ity_I64;
- vassert(vta->archinfo_host.endness == VexEndnessLE);
- break;
-
- default:
- vpanic("LibVEX_Translate: unsupported host insn set");
+ /* KLUDGE: export hwcaps. */
+ if (vta->arch_host == VexArchS390X) {
+ s390_host_hwcaps = vta->archinfo_host.hwcaps;
}
- // Are the host's hardware capabilities feasible. The function will
- // not return if hwcaps are infeasible in some sense.
- check_hwcaps(vta->arch_host, vta->archinfo_host.hwcaps);
+ /* First off, check that the guest and host insn sets
+ are supported. */
switch (vta->arch_guest) {
case VexArchX86:
preciseMemExnsFn
= X86FN(guest_x86_state_requires_precise_mem_exns);
- disInstrFn = X86FN(disInstr_X86);
- specHelper = X86FN(guest_x86_spechelper);
- guest_sizeB = sizeof(VexGuestX86State);
- guest_word_type = Ity_I32;
- guest_layout = X86FN(&x86guest_layout);
- offB_CMSTART = offsetof(VexGuestX86State,guest_CMSTART);
- offB_CMLEN = offsetof(VexGuestX86State,guest_CMLEN);
- offB_GUEST_IP = offsetof(VexGuestX86State,guest_EIP);
- szB_GUEST_IP = sizeof( ((VexGuestX86State*)0)->guest_EIP );
- offB_HOST_EvC_COUNTER = offsetof(VexGuestX86State,host_EvC_COUNTER);
- offB_HOST_EvC_FAILADDR = offsetof(VexGuestX86State,host_EvC_FAILADDR);
+ disInstrFn = X86FN(disInstr_X86);
+ specHelper = X86FN(guest_x86_spechelper);
+ guest_layout = X86FN(&x86guest_layout);
+ offB_CMSTART = offsetof(VexGuestX86State,guest_CMSTART);
+ offB_CMLEN = offsetof(VexGuestX86State,guest_CMLEN);
+ offB_GUEST_IP = offsetof(VexGuestX86State,guest_EIP);
+ szB_GUEST_IP = sizeof( ((VexGuestX86State*)0)->guest_EIP );
vassert(vta->archinfo_guest.endness == VexEndnessLE);
vassert(0 == sizeof(VexGuestX86State) % LibVEX_GUEST_STATE_ALIGN);
vassert(sizeof( ((VexGuestX86State*)0)->guest_CMSTART) == 4);
@@ -617,17 +381,13 @@
case VexArchAMD64:
preciseMemExnsFn
= AMD64FN(guest_amd64_state_requires_precise_mem_exns);
- disInstrFn = AMD64FN(disInstr_AMD64);
- specHelper = AMD64FN(guest_amd64_spechelper);
- guest_sizeB = sizeof(VexGuestAMD64State);
- guest_word_type = Ity_I64;
- guest_layout = AMD64FN(&amd64guest_layout);
- offB_CMSTART = offsetof(VexGuestAMD64State,guest_CMSTART);
- offB_CMLEN = offsetof(VexGuestAMD64State,guest_CMLEN);
- offB_GUEST_IP = offsetof(VexGuestAMD64State,guest_RIP);
- szB_GUEST_IP = sizeof( ((VexGuestAMD64State*)0)->guest_RIP );
- offB_HOST_EvC_COUNTER = offsetof(VexGuestAMD64State,host_EvC_COUNTER);
- offB_HOST_EvC_FAILADDR = offsetof(VexGuestAMD64State,host_EvC_FAILADDR);
+ disInstrFn = AMD64FN(disInstr_AMD64);
+ specHelper = AMD64FN(guest_amd64_spechelper);
+ guest_layout = AMD64FN(&amd64guest_layout);
+ offB_CMSTART = offsetof(VexGuestAMD64State,guest_CMSTART);
+ offB_CMLEN = offsetof(VexGuestAMD64State,guest_CMLEN);
+ offB_GUEST_IP = offsetof(VexGuestAMD64State,guest_RIP);
+ szB_GUEST_IP = sizeof( ((VexGuestAMD64State*)0)->guest_RIP );
vassert(vta->archinfo_guest.endness == VexEndnessLE);
vassert(0 == sizeof(VexGuestAMD64State) % LibVEX_GUEST_STATE_ALIGN);
vassert(sizeof( ((VexGuestAMD64State*)0)->guest_CMSTART ) == 8);
@@ -638,17 +398,13 @@
case VexArchPPC32:
preciseMemExnsFn
= PPC32FN(guest_ppc32_state_requires_precise_mem_exns);
- disInstrFn = PPC32FN(disInstr_PPC);
- specHelper = PPC32FN(guest_ppc32_spechelper);
- guest_sizeB = sizeof(VexGuestPPC32State);
- guest_word_type = Ity_I32;
- guest_layout = PPC32FN(&ppc32Guest_layout);
- offB_CMSTART = offsetof(VexGuestPPC32State,guest_CMSTART);
- offB_CMLEN = offsetof(VexGuestPPC32State,guest_CMLEN);
- offB_GUEST_IP = offsetof(VexGuestPPC32State,guest_CIA);
- szB_GUEST_IP = sizeof( ((VexGuestPPC32State*)0)->guest_CIA );
- offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC32State,host_EvC_COUNTER);
- offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC32State,host_EvC_FAILADDR);
+ disInstrFn = PPC32FN(disInstr_PPC);
+ specHelper = PPC32FN(guest_ppc32_spechelper);
+ guest_layout = PPC32FN(&ppc32Guest_layout);
+ offB_CMSTART = offsetof(VexGuestPPC32State,guest_CMSTART);
+ offB_CMLEN = offsetof(VexGuestPPC32State,guest_CMLEN);
+ offB_GUEST_IP = offsetof(VexGuestPPC32State,guest_CIA);
+ szB_GUEST_IP = sizeof( ((VexGuestPPC32State*)0)->guest_CIA );
vassert(vta->archinfo_guest.endness == VexEndnessBE);
vassert(0 == sizeof(VexGuestPPC32State) % LibVEX_GUEST_STATE_ALIGN);
vassert(sizeof( ((VexGuestPPC32State*)0)->guest_CMSTART ) == 4);
@@ -659,17 +415,13 @@
case VexArchPPC64:
preciseMemExnsFn
= PPC64FN(guest_ppc64_state_requires_precise_mem_exns);
- disInstrFn = PPC64FN(disInstr_PPC);
- specHelper = PPC64FN(guest_ppc64_spechelper);
- guest_sizeB = sizeof(VexGuestPPC64State);
- guest_word_type = Ity_I64;
- guest_layout = PPC64FN(&ppc64Guest_layout);
- offB_CMSTART = offsetof(VexGuestPPC64State,guest_CMSTART);
- offB_CMLEN = offsetof(VexGuestPPC64State,guest_CMLEN);
- offB_GUEST_IP = offsetof(VexGuestPPC64State,guest_CIA);
- szB_GUEST_IP = sizeof( ((VexGuestPPC64State*)0)->guest_CIA );
- offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC64State,host_EvC_COUNTER);
- offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC64State,host_EvC_FAILADDR);
+ disInstrFn = PPC64FN(disInstr_PPC);
+ specHelper = PPC64FN(guest_ppc64_spechelper);
+ guest_layout = PPC64FN(&ppc64Guest_layout);
+ offB_CMSTART = offsetof(VexGuestPPC64State,guest_CMSTART);
+ offB_CMLEN = offsetof(VexGuestPPC64State,guest_CMLEN);
+ offB_GUEST_IP = offsetof(VexGuestPPC64State,guest_CIA);
+ szB_GUEST_IP = sizeof( ((VexGuestPPC64State*)0)->guest_CIA );
vassert(vta->archinfo_guest.endness == VexEndnessBE ||
vta->archinfo_guest.endness == VexEndnessLE );
vassert(0 == sizeof(VexGuestPPC64State) % LibVEX_GUEST_STATE_ALIGN);
@@ -682,17 +434,13 @@
case VexArchS390X:
preciseMemExnsFn
= S390FN(guest_s390x_state_requires_precise_mem_exns);
- disInstrFn = S390FN(disInstr_S390);
- specHelper = S390FN(guest_s390x_spechelper);
- guest_sizeB = sizeof(VexGuestS390XState);
- guest_word_type = Ity_I64;
- guest_layout = S390FN(&s390xGuest_layout);
- offB_CMSTART = offsetof(VexGuestS390XState,guest_CMSTART);
- offB_CMLEN = offsetof(VexGuestS390XState,guest_CMLEN);
- offB_GUEST_IP = offsetof(VexGuestS390XState,guest_IA);
- szB_GUEST_IP = sizeof( ((VexGuestS390XState*)0)->guest_IA);
- offB_HOST_EvC_COUNTER = offsetof(VexGuestS390XState,host_EvC_COUNTER);
- offB_HOST_EvC_FAILADDR = offsetof(VexGuestS390XState,host_EvC_FAILADDR);
+ disInstrFn = S390FN(disInstr_S390);
+ specHelper = S390FN(guest_s390x_spechelper);
+ guest_layout = S390FN(&s390xGuest_layout);
+ offB_CMSTART = offsetof(VexGuestS390XState,guest_CMSTART);
+ offB_CMLEN = offsetof(VexGuestS390XState,guest_CMLEN);
+ offB_GUEST_IP = offsetof(VexGuestS390XState,guest_IA);
+ szB_GUEST_IP = sizeof( ((VexGuestS390XState*)0)->guest_IA);
vassert(vta->archinfo_guest.endness == VexEndnessBE);
vassert(0 == sizeof(VexGuestS390XState) % LibVEX_GUEST_STATE_ALIGN);
vassert(sizeof( ((VexGuestS390XState*)0)->guest_CMSTART ) == 8);
@@ -703,17 +451,13 @@
case VexArchARM:
preciseMemExnsFn
= ARMFN(guest_arm_state_requires_precise_mem_exns);
- disInstrFn = ARMFN(disInstr_ARM);
- specHelper = ARMFN(guest_arm_spechelper);
- guest_sizeB = sizeof(VexGuestARMState);
- guest_word_type = Ity_I32;
- guest_layout = ARMFN(&armGuest_layout);
- offB_CMSTART = offsetof(VexGuestARMState,guest_CMSTART);
- offB_CMLEN = offsetof(VexGuestARMState,guest_CMLEN);
- offB_GUEST_IP = offsetof(VexGuestARMState,guest_R15T);
- szB_GUEST_IP = sizeof( ((VexGuestARMState*)0)->guest_R15T );
- offB_HOST_EvC_COUNTER = offsetof(VexGuestARMState,host_EvC_COUNTER);
- offB_HOST_EvC_FAILADDR = offsetof(VexGuestARMState,host_EvC_FAILADDR);
+ disInstrFn = ARMFN(disInstr_ARM);
+ specHelper = ARMFN(guest_arm_spechelper);
+ guest_layout = ARMFN(&armGuest_layout);
+ offB_CMSTART = offsetof(VexGuestARMState,guest_CMSTART);
+ offB_CMLEN = offsetof(VexGuestARMState,guest_CMLEN);
+ offB_GUEST_IP = offsetof(VexGuestARMState,guest_R15T);
+ szB_GUEST_IP = sizeof( ((VexGuestARMState*)0)->guest_R15T );
vassert(vta->archinfo_guest.endness == VexEndnessLE);
vassert(0 == sizeof(VexGuestARMState) % LibVEX_GUEST_STATE_ALIGN);
vassert(sizeof( ((VexGuestARMState*)0)->guest_CMSTART) == 4);
@@ -724,17 +468,13 @@
case VexArchARM64:
preciseMemExnsFn
= ARM64FN(guest_arm64_state_requires_precise_mem_exns);
- disInstrFn = ARM64FN(disInstr_ARM64);
- specHelper = ARM64FN(guest_arm64_spechelper);
- guest_sizeB = sizeof(VexGuestARM64State);
- guest_word_type = Ity_I64;
- guest_layout = ARM64FN(&arm64Guest_layout);
- offB_CMSTART = offsetof(VexGuestARM64State,guest_CMSTART);
- offB_CMLEN = offsetof(VexGuestARM64State,guest_CMLEN);
- offB_GUEST_IP = offsetof(VexGuestARM64State,guest_PC);
- szB_GUEST_IP = sizeof( ((VexGuestARM64State*)0)->guest_PC );
- offB_HOST_EvC_COUNTER = offsetof(VexGuestARM64State,host_EvC_COUNTER);
- offB_HOST_EvC_FAILADDR = offsetof(VexGuestARM64State,host_EvC_FAILADDR);
+ disInstrFn = ARM64FN(disInstr_ARM64);
+ specHelper = ARM64FN(guest_arm64_spechelper);
+ guest_layout = ARM64FN(&arm64Guest_layout);
+ offB_CMSTART = offsetof(VexGuestARM64State,guest_CMSTART);
+ offB_CMLEN = offsetof(VexGuestARM64State,guest_CMLEN);
+ offB_GUEST_IP = offsetof(VexGuestARM64State,guest_PC);
+ szB_GUEST_IP = sizeof( ((VexGuestARM64State*)0)->guest_PC );
vassert(vta->archinfo_guest.endness == VexEndnessLE);
vassert(0 == sizeof(VexGuestARM64State) % LibVEX_GUEST_STATE_ALIGN);
vassert(sizeof( ((VexGuestARM64State*)0)->guest_CMSTART) == 8);
@@ -745,17 +485,13 @@
case VexArchMIPS32:
preciseMemExnsFn
= MIPS32FN(guest_mips32_state_requires_precise_mem_exns);
- disInstrFn = MIPS32FN(disInstr_MIPS);
- specHelper = MIPS32FN(guest_mips32_spechelper);
- guest_sizeB = sizeof(VexGuestMIPS32State);
- guest_word_type = Ity_I32;
- guest_layout = MIPS32FN(&mips32Guest_layout);
- offB_CMSTART = offsetof(VexGuestMIPS32State,guest_CMSTART);
- offB_CMLEN = offsetof(VexGuestMIPS32State,guest_CMLEN);
- offB_GUEST_IP = offsetof(VexGuestMIPS32State,guest_PC);
- szB_GUEST_IP = sizeof( ((VexGuestMIPS32State*)0)->guest_PC );
- offB_HOST_EvC_COUNTER = offsetof(VexGuestMIPS32State,host_EvC_COUNTER);
- offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS32State,host_EvC_FAILADDR);
+ disInstrFn = MIPS32FN(disInstr_MIPS);
+ specHelper = MIPS32FN(guest_mips32_spechelper);
+ guest_layout = MIPS32FN(&mips32Guest_layout);
+ offB_CMSTART = offsetof(VexGuestMIPS32State,guest_CMSTART);
+ offB_CMLEN = offsetof(VexGuestMIPS32State,guest_CMLEN);
+ offB_GUEST_IP = offsetof(VexGuestMIPS32State,guest_PC);
+ szB_GUEST_IP = sizeof( ((VexGuestMIPS32State*)0)->guest_PC );
vassert(vta->archinfo_guest.endness == VexEndnessLE
|| vta->archinfo_guest.endness == VexEndnessBE);
vassert(0 == sizeof(VexGuestMIPS32State) % LibVEX_GUEST_STATE_ALIGN);
@@ -767,17 +503,13 @@
case VexArchMIPS64:
preciseMemExnsFn
= MIPS64FN(guest_mips64_state_requires_precise_mem_exns);
- disInstrFn = MIPS64FN(disInstr_MIPS);
- specHelper = MIPS64FN(guest_mips64_spechelper);
- guest_sizeB = sizeof(VexGuestMIPS64State);
- guest_word_type = Ity_I64;
- guest_layout = MIPS64FN(&mips64Guest_layout);
- offB_CMSTART = offsetof(VexGuestMIPS64State,guest_CMSTART);
- offB_CMLEN = offsetof(VexGuestMIPS64State,guest_CMLEN);
- offB_GUEST_IP = offsetof(VexGuestMIPS64State,guest_PC);
- szB_GUEST_IP = sizeof( ((VexGuestMIPS64State*)0)->guest_PC );
- offB_HOST_EvC_COUNTER = offsetof(VexGuestMIPS64State,host_EvC_COUNTER);
- offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS64State,host_EvC_FAILADDR);
+ disInstrFn = MIPS64FN(disInstr_MIPS);
+ specHelper = MIPS64FN(guest_mips64_spechelper);
+ guest_layout = MIPS64FN(&mips64Guest_layout);
+ offB_CMSTART = offsetof(VexGuestMIPS64State,guest_CMSTART);
+ offB_CMLEN = offsetof(VexGuestMIPS64State,guest_CMLEN);
+ offB_GUEST_IP = offsetof(VexGuestMIPS64State,guest_PC);
+ szB_GUEST_IP = sizeof( ((VexGuestMIPS64State*)0)->guest_PC );
vassert(vta->archinfo_guest.endness == VexEndnessLE
|| vta->archinfo_guest.endness == VexEndnessBE);
vassert(0 == sizeof(VexGuestMIPS64State) % LibVEX_GUEST_STATE_ALIGN);
@@ -786,28 +518,6 @@
vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_NRADDR ) == 8);
break;
- case VexArchTILEGX:
- preciseMemExnsFn =
- TILEGXFN(guest_tilegx_state_requires_precise_mem_exns);
- disInstrFn = TILEGXFN(disInstr_TILEGX);
- specHelper = TILEGXFN(guest_tilegx_spechelper);
- guest_sizeB = sizeof(VexGuestTILEGXState);
- guest_word_type = Ity_I64;
- guest_layout = TILEGXFN(&tilegxGuest_layout);
- offB_CMSTART = offsetof(VexGuestTILEGXState,guest_CMSTART);
- offB_CMLEN = offsetof(VexGuestTILEGXState,guest_CMLEN);
- offB_GUEST_IP = offsetof(VexGuestTILEGXState,guest_pc);
- szB_GUEST_IP = sizeof( ((VexGuestTILEGXState*)0)->guest_pc );
- offB_HOST_EvC_COUNTER = offsetof(VexGuestTILEGXState,host_EvC_COUNTER);
- offB_HOST_EvC_FAILADDR = offsetof(VexGuestTILEGXState,host_EvC_FAILADDR);
- vassert(vta->archinfo_guest.endness == VexEndnessLE);
- vassert(0 ==
- sizeof(VexGuestTILEGXState) % LibVEX_GUEST_STATE_ALIGN);
- vassert(sizeof( ((VexGuestTILEGXState*)0)->guest_CMSTART ) == 8);
- vassert(sizeof( ((VexGuestTILEGXState*)0)->guest_CMLEN ) == 8);
- vassert(sizeof( ((VexGuestTILEGXState*)0)->guest_NRADDR ) == 8);
- break;
-
default:
vpanic("LibVEX_Translate: unsupported guest insn set");
}
@@ -817,13 +527,12 @@
// FIXME: how can we know the guest's hardware capabilities?
check_hwcaps(vta->arch_guest, vta->archinfo_guest.hwcaps);
- /* Set up result struct. */
- VexTranslateResult res;
- res.status = VexTransOK;
- res.n_sc_extents = 0;
- res.offs_profInc = -1;
- res.n_guest_instrs = 0;
+ res->status = VexTransOK;
+ res->n_sc_extents = 0;
+ res->offs_profInc = -1;
+ res->n_guest_instrs = 0;
+#ifndef VEXMULTIARCH
/* yet more sanity checks ... */
if (vta->arch_guest == vta->arch_host) {
/* doesn't necessarily have to be true, but if it isn't it means
@@ -833,6 +542,7 @@
/* ditto */
vassert(vta->archinfo_guest.endness == vta->archinfo_host.endness);
}
+#endif
vexAllocSanityCheck();
@@ -841,14 +551,14 @@
" Front end "
"------------------------\n\n");
- VexRegisterUpdates pxControl = vex_control.iropt_register_updates_default;
- vassert(pxControl >= VexRegUpdSpAtMemAccess
- && pxControl <= VexRegUpdAllregsAtEachInsn);
+ *pxControl = vex_control.iropt_register_updates_default;
+ vassert(*pxControl >= VexRegUpdSpAtMemAccess
+ && *pxControl <= VexRegUpdAllregsAtEachInsn);
irsb = bb_to_IR ( vta->guest_extents,
- &res.n_sc_extents,
- &res.n_guest_instrs,
- &pxControl,
+ &res->n_sc_extents,
+ &res->n_guest_instrs,
+ pxControl,
vta->callback_opaque,
disInstrFn,
vta->guest_bytes,
@@ -872,8 +582,7 @@
if (irsb == NULL) {
/* Access failure. */
vexSetAllocModeTEMP_and_clear();
- vex_traceflags = 0;
- res.status = VexTransAccessFail; return res;
+ return NULL;
}
vassert(vta->guest_extents->n_used >= 1 && vta->guest_extents->n_used <= 3);
@@ -883,8 +592,8 @@
}
/* bb_to_IR() could have caused pxControl to change. */
- vassert(pxControl >= VexRegUpdSpAtMemAccess
- && pxControl <= VexRegUpdAllregsAtEachInsn);
+ vassert(*pxControl >= VexRegUpdSpAtMemAccess
+ && *pxControl <= VexRegUpdAllregsAtEachInsn);
/* If debugging, show the raw guest bytes for this bb. */
if (0 || (vex_traceflags & VEX_TRACE_FE)) {
@@ -913,7 +622,7 @@
vexAllocSanityCheck();
/* Clean it up, hopefully a lot. */
- irsb = do_iropt_BB ( irsb, specHelper, preciseMemExnsFn, pxControl,
+ irsb = do_iropt_BB ( irsb, specHelper, preciseMemExnsFn, *pxControl,
vta->guest_bytes_addr,
vta->arch_guest );
@@ -984,6 +693,322 @@
vex_printf("\n");
}
+ return irsb;
+}
+
+
+/* Back end of the compilation pipeline. Is not exported. */
+
+static void libvex_BackEnd ( const VexTranslateArgs *vta,
+ /*MOD*/ VexTranslateResult* res,
+ /*MOD*/ IRSB* irsb,
+ VexRegisterUpdates pxControl )
+{
+ /* This the bundle of functions we need to do the back-end stuff
+ (insn selection, reg-alloc, assembly) whilst being insulated
+ from the target instruction set. */
+ Bool (*isMove) ( const HInstr*, HReg*, HReg* );
+ void (*getRegUsage) ( HRegUsage*, const HInstr*, Bool );
+ void (*mapRegs) ( HRegRemap*, HInstr*, Bool );
+ void (*genSpill) ( HInstr**, HInstr**, HReg, Int, Bool );
+ void (*genReload) ( HInstr**, HInstr**, HReg, Int, Bool );
+ HInstr* (*directReload) ( HInstr*, HReg, Short );
+ void (*ppInstr) ( const HInstr*, Bool );
+ void (*ppReg) ( HReg );
+ HInstrArray* (*iselSB) ( const IRSB*, VexArch, const VexArchInfo*,
+ const VexAbiInfo*, Int, Int, Bool, Bool,
+ Addr );
+ Int (*emit) ( /*MB_MOD*/Bool*,
+ UChar*, Int, const HInstr*, Bool, VexEndness,
+ const void*, const void*, const void*,
+ const void* );
+ Bool (*preciseMemExnsFn) ( Int, Int, VexRegisterUpdates );
+
+ const RRegUniverse* rRegUniv = NULL;
+
+ Bool mode64, chainingAllowed;
+ Int i, j, k, out_used;
+ Int guest_sizeB;
+ Int offB_HOST_EvC_COUNTER;
+ Int offB_HOST_EvC_FAILADDR;
+ Addr max_ga;
+ UChar insn_bytes[128];
+ HInstrArray* vcode;
+ HInstrArray* rcode;
+
+ isMove = NULL;
+ getRegUsage = NULL;
+ mapRegs = NULL;
+ genSpill = NULL;
+ genReload = NULL;
+ directReload = NULL;
+ ppInstr = NULL;
+ ppReg = NULL;
+ iselSB = NULL;
+ emit = NULL;
+
+ mode64 = False;
+ chainingAllowed = False;
+ guest_sizeB = 0;
+ offB_HOST_EvC_COUNTER = 0;
+ offB_HOST_EvC_FAILADDR = 0;
+ preciseMemExnsFn = NULL;
+
+ vassert(vex_initdone);
+ vassert(vta->disp_cp_xassisted != NULL);
+
+ vex_traceflags = vta->traceflags;
+
+ /* Both the chainers and the indir are either NULL or non-NULL. */
+ if (vta->disp_cp_chain_me_to_slowEP != NULL) {
+ vassert(vta->disp_cp_chain_me_to_fastEP != NULL);
+ vassert(vta->disp_cp_xindir != NULL);
+ chainingAllowed = True;
+ } else {
+ vassert(vta->disp_cp_chain_me_to_fastEP == NULL);
+ vassert(vta->disp_cp_xindir == NULL);
+ }
+
+ switch (vta->arch_guest) {
+
+ case VexArchX86:
+ preciseMemExnsFn
+ = X86FN(guest_x86_state_requires_precise_mem_exns);
+ guest_sizeB = sizeof(VexGuestX86State);
+ offB_HOST_EvC_COUNTER = offsetof(VexGuestX86State,host_EvC_COUNTER);
+ offB_HOST_EvC_FAILADDR = offsetof(VexGuestX86State,host_EvC_FAILADDR);
+ break;
+
+ case VexArchAMD64:
+ preciseMemExnsFn
+ = AMD64FN(guest_amd64_state_requires_precise_mem_exns);
+ guest_sizeB = sizeof(VexGuestAMD64State);
+ offB_HOST_EvC_COUNTER = offsetof(VexGuestAMD64State,host_EvC_COUNTER);
+ offB_HOST_EvC_FAILADDR = offsetof(VexGuestAMD64State,host_EvC_FAILADDR);
+ break;
+
+ case VexArchPPC32:
+ preciseMemExnsFn
+ = PPC32FN(guest_ppc32_state_requires_precise_mem_exns);
+ guest_sizeB = sizeof(VexGuestPPC32State);
+ offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC32State,host_EvC_COUNTER);
+ offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC32State,host_EvC_FAILADDR);
+ break;
+
+ case VexArchPPC64:
+ preciseMemExnsFn
+ = PPC64FN(guest_ppc64_state_requires_precise_mem_exns);
+ guest_sizeB = sizeof(VexGuestPPC64State);
+ offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC64State,host_EvC_COUNTER);
+ offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC64State,host_EvC_FAILADDR);
+ break;
+
+ case VexArchS390X:
+ preciseMemExnsFn
+ = S390FN(guest_s390x_state_requires_precise_mem_exns);
+ guest_sizeB = sizeof(VexGuestS390XState);
+ offB_HOST_EvC_COUNTER = offsetof(VexGuestS390XState,host_EvC_COUNTER);
+ offB_HOST_EvC_FAILADDR = offsetof(VexGuestS390XState,host_EvC_FAILADDR);
+ break;
+
+ case VexArchARM:
+ preciseMemExnsFn
+ = ARMFN(guest_arm_state_requires_precise_mem_exns);
+ guest_sizeB = sizeof(VexGuestARMState);
+ offB_HOST_EvC_COUNTER = offsetof(VexGuestARMState,host_EvC_COUNTER);
+ offB_HOST_EvC_FAILADDR = offsetof(VexGuestARMState,host_EvC_FAILADDR);
+ break;
+
+ case VexArchARM64:
+ preciseMemExnsFn
+ = ARM64FN(guest_arm64_state_requires_precise_mem_exns);
+ guest_sizeB = sizeof(VexGuestARM64State);
+ offB_HOST_EvC_COUNTER = offsetof(VexGuestARM64State,host_EvC_COUNTER);
+ offB_HOST_EvC_FAILADDR = offsetof(VexGuestARM64State,host_EvC_FAILADDR);
+ break;
+
+ case VexArchMIPS32:
+ preciseMemExnsFn
+ = MIPS32FN(guest_mips32_state_requires_precise_mem_exns);
+ guest_sizeB = sizeof(VexGuestMIPS32State);
+ offB_HOST_EvC_COUNTER = offsetof(VexGuestMIPS32State,host_EvC_COUNTER);
+ offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS32State,host_EvC_FAILADDR);
+ break;
+
+ case VexArchMIPS64:
+ preciseMemExnsFn
+ = MIPS64FN(guest_mips64_state_requires_precise_mem_exns);
+ guest_sizeB = sizeof(VexGuestMIPS64State);
+ offB_HOST_EvC_COUNTER = offsetof(VexGuestMIPS64State,host_EvC_COUNTER);
+ offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS64State,host_EvC_FAILADDR);
+ break;
+
+ default:
+ vpanic("LibVEX_Codegen: unsupported guest insn set");
+ }
+
+
+ switch (vta->arch_host) {
+
+ case VexArchX86:
+ mode64 = False;
+ rRegUniv = X86FN(getRRegUniverse_X86());
+ isMove = CAST_TO_TYPEOF(isMove) X86FN(isMove_X86Instr);
+ getRegUsage
+ = CAST_TO_TYPEOF(getRegUsage) X86FN(getRegUsage_X86Instr);
+ mapRegs = CAST_TO_TYPEOF(mapRegs) X86FN(mapRegs_X86Instr);
+ genSpill = CAST_TO_TYPEOF(genSpill) X86FN(genSpill_X86);
+ genReload = CAST_TO_TYPEOF(genReload) X86FN(genReload_X86);
+ directReload = CAST_TO_TYPEOF(directReload) X86FN(directReload_X86);
+ ppInstr = CAST_TO_TYPEOF(ppInstr) X86FN(ppX86Instr);
+ ppReg = CAST_TO_TYPEOF(ppReg) X86FN(ppHRegX86);
+ iselSB = X86FN(iselSB_X86);
+ emit = CAST_TO_TYPEOF(emit) X86FN(emit_X86Instr);
+ vassert(vta->archinfo_host.endness == VexEndnessLE);
+ break;
+
+ case VexArchAMD64:
+ mode64 = True;
+ rRegUniv = AMD64FN(getRRegUniverse_AMD64());
+ isMove = CAST_TO_TYPEOF(isMove) AMD64FN(isMove_AMD64Instr);
+ getRegUsage
+ = CAST_TO_TYPEOF(getRegUsage) AMD64FN(getRegUsage_AMD64Instr);
+ mapRegs = CAST_TO_TYPEOF(mapRegs) AMD64FN(mapRegs_AMD64Instr);
+ genSpill = CAST_TO_TYPEOF(genSpill) AMD64FN(genSpill_AMD64);
+ genReload = CAST_TO_TYPEOF(genReload) AMD64FN(genReload_AMD64);
+ directReload = CAST_TO_TYPEOF(directReload) AMD64FN(directReload_AMD64);
+ ppInstr = CAST_TO_TYPEOF(ppInstr) AMD64FN(ppAMD64Instr);
+ ppReg = CAST_TO_TYPEOF(ppReg) AMD64FN(ppHRegAMD64);
+ iselSB = AMD64FN(iselSB_AMD64);
+ emit = CAST_TO_TYPEOF(emit) AMD64FN(emit_AMD64Instr);
+ vassert(vta->archinfo_host.endness == VexEndnessLE);
+ break;
+
+ case VexArchPPC32:
+ mode64 = False;
+ rRegUniv = PPC32FN(getRRegUniverse_PPC(mode64));
+ isMove = CAST_TO_TYPEOF(isMove) PPC32FN(isMove_PPCInstr);
+ getRegUsage
+ = CAST_TO_TYPEOF(getRegUsage) PPC32FN(getRegUsage_PPCInstr);
+ mapRegs = CAST_TO_TYPEOF(mapRegs) PPC32FN(mapRegs_PPCInstr);
+ genSpill = CAST_TO_TYPEOF(genSpill) PPC32FN(genSpill_PPC);
+ genReload = CAST_TO_TYPEOF(genReload) PPC32FN(genReload_PPC);
+ ppInstr = CAST_TO_TYPEOF(ppInstr) PPC32FN(ppPPCInstr);
+ ppReg = CAST_TO_TYPEOF(ppReg) PPC32FN(ppHRegPPC);
+ iselSB = PPC32FN(iselSB_PPC);
+ emit = CAST_TO_TYPEOF(emit) PPC32FN(emit_PPCInstr);
+ vassert(vta->archinfo_host.endness == VexEndnessBE);
+ break;
+
+ case VexArchPPC64:
+ mode64 = True;
+ rRegUniv = PPC64FN(getRRegUniverse_PPC(mode64));
+ isMove = CAST_TO_TYPEOF(isMove) PPC64FN(isMove_PPCInstr);
+ getRegUsage
+ = CAST_TO_TYPEOF(getRegUsage) PPC64FN(getRegUsage_PPCInstr);
+ mapRegs = CAST_TO_TYPEOF(mapRegs) PPC64FN(mapRegs_PPCInstr);
+ genSpill = CAST_TO_TYPEOF(genSpill) PPC64FN(genSpill_PPC);
+ genReload = CAST_TO_TYPEOF(genReload) PPC64FN(genReload_PPC);
+ ppInstr = CAST_TO_TYPEOF(ppInstr) PPC64FN(ppPPCInstr);
+ ppReg = CAST_TO_TYPEOF(ppReg) PPC64FN(ppHRegPPC);
+ iselSB = PPC64FN(iselSB_PPC);
+ emit = CAST_TO_TYPEOF(emit) PPC64FN(emit_PPCInstr);
+ vassert(vta->archinfo_host.endness == VexEndnessBE ||
+ vta->archinfo_host.endness == VexEndnessLE );
+ break;
+
+ case VexArchS390X:
+ mode64 = True;
+ rRegUniv = S390FN(getRRegUniverse_S390());
+ isMove = CAST_TO_TYPEOF(isMove) S390FN(isMove_S390Instr);
+ getRegUsage
+ = CAST_TO_TYPEOF(getRegUsage) S390FN(getRegUsage_S390Instr);
+ mapRegs = CAST_TO_TYPEOF(mapRegs) S390FN(mapRegs_S390Instr);
+ genSpill = CAST_TO_TYPEOF(genSpill) S390FN(genSpill_S390);
+ genReload = CAST_TO_TYPEOF(genReload) S390FN(genReload_S390);
+ // fixs390: consider implementing directReload_S390
+ ppInstr = CAST_TO_TYPEOF(ppInstr) S390FN(ppS390Instr);
+ ppReg = CAST_TO_TYPEOF(ppReg) S390FN(ppHRegS390);
+ iselSB = S390FN(iselSB_S390);
+ emit = CAST_TO_TYPEOF(emit) S390FN(emit_S390Instr);
+ vassert(vta->archinfo_host.endness == VexEndnessBE);
+ break;
+
+ case VexArchARM:
+ mode64 = False;
+ rRegUniv = ARMFN(getRRegUniverse_ARM());
+ isMove = CAST_TO_TYPEOF(isMove) ARMFN(isMove_ARMInstr);
+ getRegUsage
+ = CAST_TO_TYPEOF(getRegUsage) ARMFN(getRegUsage_ARMInstr);
+ mapRegs = CAST_TO_TYPEOF(mapRegs) ARMFN(mapRegs_ARMInstr);
+ genSpill = CAST_TO_TYPEOF(genSpill) ARMFN(genSpill_ARM);
+ genReload = CAST_TO_TYPEOF(genReload) ARMFN(genReload_ARM);
+ ppInstr = CAST_TO_TYPEOF(ppInstr) ARMFN(ppARMInstr);
+ ppReg = CAST_TO_TYPEOF(ppReg) ARMFN(ppHRegARM);
+ iselSB = ARMFN(iselSB_ARM);
+ emit = CAST_TO_TYPEOF(emit) ARMFN(emit_ARMInstr);
+ vassert(vta->archinfo_host.endness == VexEndnessLE);
+ break;
+
+ case VexArchARM64:
+ mode64 = True;
+ rRegUniv = ARM64FN(getRRegUniverse_ARM64());
+ isMove = CAST_TO_TYPEOF(isMove) ARM64FN(isMove_ARM64Instr);
+ getRegUsage
+ = CAST_TO_TYPEOF(getRegUsage) ARM64FN(getRegUsage_ARM64Instr);
+ mapRegs = CAST_TO_TYPEOF(mapRegs) ARM64FN(mapRegs_ARM64Instr);
+ genSpill = CAST_TO_TYPEOF(genSpill) ARM64FN(genSpill_ARM64);
+ genReload = CAST_TO_TYPEOF(genReload) ARM64FN(genReload_ARM64);
+ ppInstr = CAST_TO_TYPEOF(ppInstr) ARM64FN(ppARM64Instr);
+ ppReg = CAST_TO_TYPEOF(ppReg) ARM64FN(ppHRegARM64);
+ iselSB = ARM64FN(iselSB_ARM64);
+ emit = CAST_TO_TYPEOF(emit) ARM64FN(emit_ARM64Instr);
+ vassert(vta->archinfo_host.endness == VexEndnessLE);
+ break;
+
+ case VexArchMIPS32:
+ mode64 = False;
+ rRegUniv = MIPS32FN(getRRegUniverse_MIPS(mode64));
+ isMove = CAST_TO_TYPEOF(isMove) MIPS32FN(isMove_MIPSInstr);
+ getRegUsage
+ = CAST_TO_TYPEOF(getRegUsage) MIPS32FN(getRegUsage_MIPSInstr);
+ mapRegs = CAST_TO_TYPEOF(mapRegs) MIPS32FN(mapRegs_MIPSInstr);
+ genSpill = CAST_TO_TYPEOF(genSpill) MIPS32FN(genSpill_MIPS);
+ genReload = CAST_TO_TYPEOF(genReload) MIPS32FN(genReload_MIPS);
+ ppInstr = CAST_TO_TYPEOF(ppInstr) MIPS32FN(ppMIPSInstr);
+ ppReg = CAST_TO_TYPEOF(ppReg) MIPS32FN(ppHRegMIPS);
+ iselSB = MIPS32FN(iselSB_MIPS);
+ emit = CAST_TO_TYPEOF(emit) MIPS32FN(emit_MIPSInstr);
+ vassert(vta->archinfo_host.endness == VexEndnessLE
+ || vta->archinfo_host.endness == VexEndnessBE);
+ break;
+
+ case VexArchMIPS64:
+ mode64 = True;
+ rRegUniv = MIPS64FN(getRRegUniverse_MIPS(mode64));
+ isMove = CAST_TO_TYPEOF(isMove) MIPS64FN(isMove_MIPSInstr);
+ getRegUsage
+ = CAST_TO_TYPEOF(getRegUsage) MIPS64FN(getRegUsage_MIPSInstr);
+ mapRegs = CAST_TO_TYPEOF(mapRegs) MIPS64FN(mapRegs_MIPSInstr);
+ genSpill = CAST_TO_TYPEOF(genSpill) MIPS64FN(genSpill_MIPS);
+ genReload = CAST_TO_TYPEOF(genReload) MIPS64FN(genReload_MIPS);
+ ppInstr = CAST_TO_TYPEOF(ppInstr) MIPS64FN(ppMIPSInstr);
+ ppReg = CAST_TO_TYPEOF(ppReg) MIPS64FN(ppHRegMIPS);
+ iselSB = MIPS64FN(iselSB_MIPS);
+ emit = CAST_TO_TYPEOF(emit) MIPS64FN(emit_MIPSInstr);
+ vassert(vta->archinfo_host.endness == VexEndnessLE
+ || vta->archinfo_host.endness == VexEndnessBE);
+ break;
+
+ default:
+ vpanic("LibVEX_Translate: unsupported host insn set");
+ }
+
+ // Are the host's hardware capabilities feasible. The function will
+ // not return if hwcaps are infeasible in some sense.
+ check_hwcaps(vta->arch_host, vta->archinfo_host.hwcaps);
+
+
/* Turn it into virtual-registerised code. Build trees -- this
also throws away any dead bindings. */
max_ga = ado_treebuild_BB( irsb, preciseMemExnsFn, pxControl );
@@ -1005,7 +1030,7 @@
/* HACK */
if (0) {
*(vta->host_bytes_used) = 0;
- res.status = VexTransOK; return res;
+ res->status = VexTransOK; return;
}
/* end HACK */
@@ -1066,7 +1091,7 @@
/* HACK */
if (0) {
*(vta->host_bytes_used) = 0;
- res.status = VexTransOK; return res;
+ res->status = VexTransOK; return;
}
/* end HACK */
@@ -1100,14 +1125,14 @@
if (UNLIKELY(out_used + j > vta->host_bytes_size)) {
vexSetAllocModeTEMP_and_clear();
vex_traceflags = 0;
- res.status = VexTransOutputFull;
- return res;
+ res->status = VexTransOutputFull;
+ return;
}
if (UNLIKELY(hi_isProfInc)) {
vassert(vta->addProfInc); /* else where did it come from? */
- vassert(res.offs_profInc == -1); /* there can be only one (tm) */
+ vassert(res->offs_profInc == -1); /* there can be only one (tm) */
vassert(out_used >= 0);
- res.offs_profInc = out_used;
+ res->offs_profInc = out_used;
}
{ UChar* dst = &vta->host_bytes[out_used];
for (k = 0; k < j; k++) {
@@ -1133,7 +1158,20 @@
}
vex_traceflags = 0;
- res.status = VexTransOK;
+ res->status = VexTransOK;
+ return;
+}
+
+
+/* Exported to library client. */
+
+VexTranslateResult LibVEX_Translate ( /*MOD*/ VexTranslateArgs* vta )
+{
+ VexTranslateResult res = { 0 };
+ VexRegisterUpdates pxControl = VexRegUpd_INVALID;
+
+ IRSB* irsb = LibVEX_FrontEnd(vta, &res, &pxControl);
+ libvex_BackEnd(vta, &res, irsb, pxControl);
return res;
}
@@ -1192,12 +1230,6 @@
place_to_chain,
disp_cp_chain_me_EXPECTED,
place_to_jump_to, True/*!mode64*/));
-
- case VexArchTILEGX:
- TILEGXST(return chainXDirect_TILEGX(endness_host,
- place_to_chain,
- disp_cp_chain_me_EXPECTED,
- place_to_jump_to, True/*!mode64*/));
default:
vassert(0);
}
@@ -1255,13 +1287,6 @@
place_to_unchain,
place_to_jump_to_EXPECTED,
disp_cp_chain_me, True/*!mode64*/));
-
- case VexArchTILEGX:
- TILEGXST(return unchainXDirect_TILEGX(endness_host,
- place_to_unchain,
- place_to_jump_to_EXPECTED,
- disp_cp_chain_me, True/*!mode64*/));
-
default:
vassert(0);
}
@@ -1290,8 +1315,6 @@
MIPS32ST(cached = evCheckSzB_MIPS()); break;
case VexArchMIPS64:
MIPS64ST(cached = evCheckSzB_MIPS()); break;
- case VexArchTILEGX:
- TILEGXST(cached = evCheckSzB_TILEGX()); break;
default:
vassert(0);
}
@@ -1332,10 +1355,6 @@
case VexArchMIPS64:
MIPS64ST(return patchProfInc_MIPS(endness_host, place_to_patch,
location_of_counter, True/*!mode64*/));
- case VexArchTILEGX:
- TILEGXST(return patchProfInc_TILEGX(endness_host, place_to_patch,
- location_of_counter,
- True/*!mode64*/));
default:
vassert(0);
}
@@ -1415,7 +1434,6 @@
case VexArchS390X: return "S390X";
case VexArchMIPS32: return "MIPS32";
case VexArchMIPS64: return "MIPS64";
- case VexArchTILEGX: return "TILEGX";
default: return "VexArch???";
}
}
@@ -1450,6 +1468,7 @@
vai->ppc_dcbzl_szB = 0;
vai->arm64_dMinLine_lg2_szB = 0;
vai->arm64_iMinLine_lg2_szB = 0;
+ vai->arm64_requires_fallback_LLSC = False;
vai->hwcache_info.num_levels = 0;
vai->hwcache_info.num_caches = 0;
vai->hwcache_info.caches = NULL;
@@ -1465,10 +1484,33 @@
vbi->guest_amd64_assume_gs_is_const = False;
vbi->guest_ppc_zap_RZ_at_blr = False;
vbi->guest_ppc_zap_RZ_at_bl = NULL;
+ vbi->guest__use_fallback_LLSC = False;
vbi->host_ppc_calls_use_fndescrs = False;
}
+static IRType arch_word_size (VexArch arch) {
+ switch (arch) {
+ case VexArchX86:
+ case VexArchARM:
+ case VexArchMIPS32:
+ case VexArchPPC32:
+ return Ity_I32;
+
+ case VexArchAMD64:
+ case VexArchARM64:
+ case VexArchMIPS64:
+ case VexArchPPC64:
+ case VexArchS390X:
+ return Ity_I64;
+
+ default:
+ vex_printf("Fatal: unknown arch in arch_word_size\n");
+ vassert(0);
+ }
+}
+
+
/* Convenience macro to be used in show_hwcaps_ARCH functions */
#define NUM_HWCAPS (sizeof hwcaps_list / sizeof hwcaps_list[0])
@@ -1756,11 +1798,6 @@
return "Unsupported baseline";
}
-static const HChar* show_hwcaps_tilegx ( UInt hwcaps )
-{
- return "tilegx-baseline";
-}
-
#undef NUM_HWCAPS
/* Thie function must not return NULL. */
@@ -1777,7 +1814,6 @@
case VexArchS390X: return show_hwcaps_s390x(hwcaps);
case VexArchMIPS32: return show_hwcaps_mips32(hwcaps);
case VexArchMIPS64: return show_hwcaps_mips64(hwcaps);
- case VexArchTILEGX: return show_hwcaps_tilegx(hwcaps);
default: return NULL;
}
}
@@ -2001,9 +2037,6 @@
invalid_hwcaps(arch, hwcaps, "Unsupported baseline\n");
}
- case VexArchTILEGX:
- return;
-
default:
vpanic("unknown architecture");
}
diff --git a/VEX/priv/main_util.c b/VEX/priv/main_util.c
index 028d353..4e0494b 100644
--- a/VEX/priv/main_util.c
+++ b/VEX/priv/main_util.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/VEX/priv/main_util.h b/VEX/priv/main_util.h
index 57f45ed..8627d1f 100644
--- a/VEX/priv/main_util.h
+++ b/VEX/priv/main_util.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -43,8 +43,15 @@
#define NULL ((void*)0)
-#define LIKELY(x) __builtin_expect(!!(x), 1)
-#define UNLIKELY(x) __builtin_expect(!!(x), 0)
+#if defined(_MSC_VER) // building with MSVC
+# define LIKELY(x) (x)
+# define UNLIKELY(x) (x)
+# define CAST_TO_TYPEOF(x) /**/
+#else
+# define LIKELY(x) __builtin_expect(!!(x), 1)
+# define UNLIKELY(x) __builtin_expect(!!(x), 0)
+# define CAST_TO_TYPEOF(x) (__typeof__(x))
+#endif // defined(_MSC_VER)
#if !defined(offsetof)
# define offsetof(type,memb) ((SizeT)(HWord)&((type*)0)->memb)
diff --git a/VEX/priv/multiarch_main_main.c b/VEX/priv/multiarch_main_main.c
index c7500bc..bd0fa79 100644
--- a/VEX/priv/multiarch_main_main.c
+++ b/VEX/priv/multiarch_main_main.c
@@ -6,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2015 Philippe Waroquiers
+ Copyright (C) 2015-2017 Philippe Waroquiers
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/VEX/priv/s390_defs.h b/VEX/priv/s390_defs.h
index 6751d80..4c2de40 100644
--- a/VEX/priv/s390_defs.h
+++ b/VEX/priv/s390_defs.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2015
+ Copyright IBM Corp. 2010-2017
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/VEX/priv/s390_disasm.c b/VEX/priv/s390_disasm.c
index fa18ca5..94bb90a 100644
--- a/VEX/priv/s390_disasm.c
+++ b/VEX/priv/s390_disasm.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2015
+ Copyright IBM Corp. 2010-2017
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/VEX/priv/s390_disasm.h b/VEX/priv/s390_disasm.h
index 2334f01..696e52d 100644
--- a/VEX/priv/s390_disasm.h
+++ b/VEX/priv/s390_disasm.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2015
+ Copyright IBM Corp. 2010-2017
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/VEX/priv/tilegx_disasm.c b/VEX/priv/tilegx_disasm.c
deleted file mode 100644
index bbbfa27..0000000
--- a/VEX/priv/tilegx_disasm.c
+++ /dev/null
@@ -1,7694 +0,0 @@
-
-/*---------------------------------------------------------------*/
-/*--- begin Tilegx disassembler tilegx-disasm.c ---*/
-/*---------------------------------------------------------------*/
-
-/*
- This file is part of Valgrind, a dynamic binary instrumentation
- framework.
-
- Copyright Tilera Corp. 2010-2013
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of the
- License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful, but
- WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- 02110-1301, USA.
-
- The GNU General Public License is contained in the file COPYING.
-*/
-
- /* Contributed by Zhi-Gang Liu <zliu at tilera dot com> */
-
-#include "tilegx_disasm.h"
-#include <stdarg.h>
-
-/* This define is BFD_RELOC_##x for real bfd, or -1 for everyone else. */
-#define BFD_RELOC(x) -1
-
-/* Special registers. */
-#define TREG_LR 55
-#define TREG_SN 56
-#define TREG_ZERO 63
-
-#ifndef NULL
-#define NULL 0
-#endif
-
-const struct tilegx_opcode tilegx_opcodes[336] =
-{
- { "bpt", TILEGX_OPC_BPT, 0x2, 0, TREG_ZERO, 0,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xffffffff80000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286a44ae00000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "info", TILEGX_OPC_INFO, 0xf, 1, TREG_ZERO, 1,
- { { 0 }, { 1 }, { 2 }, { 3 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ff00fffULL,
- 0xfff807ff80000000ULL,
- 0x0000000078000fffULL,
- 0x3c0007ff80000000ULL,
- 0ULL
- },
- {
- 0x0000000040300fffULL,
- 0x181807ff80000000ULL,
- 0x0000000010000fffULL,
- 0x0c0007ff80000000ULL,
- -1ULL
- }
-#endif
- },
- { "infol", TILEGX_OPC_INFOL, 0x3, 1, TREG_ZERO, 1,
- { { 4 }, { 5 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc000000070000fffULL,
- 0xf80007ff80000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000070000fffULL,
- 0x380007ff80000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ld4s_tls", TILEGX_OPC_LD4S_TLS, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1858000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ld_tls", TILEGX_OPC_LD_TLS, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x18a0000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "move", TILEGX_OPC_MOVE, 0xf, 2, TREG_ZERO, 1,
- { { 8, 9 }, { 6, 7 }, { 10, 11 }, { 12, 13 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffff000ULL,
- 0xfffff80000000000ULL,
- 0x00000000780ff000ULL,
- 0x3c07f80000000000ULL,
- 0ULL
- },
- {
- 0x000000005107f000ULL,
- 0x283bf80000000000ULL,
- 0x00000000500bf000ULL,
- 0x2c05f80000000000ULL,
- -1ULL
- }
-#endif
- },
- { "movei", TILEGX_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1,
- { { 8, 0 }, { 6, 1 }, { 10, 2 }, { 12, 3 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ff00fc0ULL,
- 0xfff807e000000000ULL,
- 0x0000000078000fc0ULL,
- 0x3c0007e000000000ULL,
- 0ULL
- },
- {
- 0x0000000040100fc0ULL,
- 0x180807e000000000ULL,
- 0x0000000000000fc0ULL,
- 0x040007e000000000ULL,
- -1ULL
- }
-#endif
- },
- { "moveli", TILEGX_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1,
- { { 8, 4 }, { 6, 5 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc000000070000fc0ULL,
- 0xf80007e000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000010000fc0ULL,
- 0x000007e000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "prefetch", TILEGX_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1,
- { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff81f80000000ULL,
- 0ULL,
- 0ULL,
- 0xc3f8000004000000ULL
- },
- {
- -1ULL,
- 0x286a801f80000000ULL,
- -1ULL,
- -1ULL,
- 0x41f8000004000000ULL
- }
-#endif
- },
- { "prefetch_add_l1", TILEGX_OPC_PREFETCH_ADD_L1, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8001f80000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1840001f80000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "prefetch_add_l1_fault", TILEGX_OPC_PREFETCH_ADD_L1_FAULT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8001f80000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1838001f80000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "prefetch_add_l2", TILEGX_OPC_PREFETCH_ADD_L2, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8001f80000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1850001f80000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "prefetch_add_l2_fault", TILEGX_OPC_PREFETCH_ADD_L2_FAULT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8001f80000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1848001f80000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "prefetch_add_l3", TILEGX_OPC_PREFETCH_ADD_L3, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8001f80000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1860001f80000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "prefetch_add_l3_fault", TILEGX_OPC_PREFETCH_ADD_L3_FAULT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8001f80000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1858001f80000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "prefetch_l1", TILEGX_OPC_PREFETCH_L1, 0x12, 1, TREG_ZERO, 1,
- { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff81f80000000ULL,
- 0ULL,
- 0ULL,
- 0xc3f8000004000000ULL
- },
- {
- -1ULL,
- 0x286a801f80000000ULL,
- -1ULL,
- -1ULL,
- 0x41f8000004000000ULL
- }
-#endif
- },
- { "prefetch_l1_fault", TILEGX_OPC_PREFETCH_L1_FAULT, 0x12, 1, TREG_ZERO, 1,
- { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff81f80000000ULL,
- 0ULL,
- 0ULL,
- 0xc3f8000004000000ULL
- },
- {
- -1ULL,
- 0x286a781f80000000ULL,
- -1ULL,
- -1ULL,
- 0x41f8000000000000ULL
- }
-#endif
- },
- { "prefetch_l2", TILEGX_OPC_PREFETCH_L2, 0x12, 1, TREG_ZERO, 1,
- { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff81f80000000ULL,
- 0ULL,
- 0ULL,
- 0xc3f8000004000000ULL
- },
- {
- -1ULL,
- 0x286a901f80000000ULL,
- -1ULL,
- -1ULL,
- 0x43f8000004000000ULL
- }
-#endif
- },
- { "prefetch_l2_fault", TILEGX_OPC_PREFETCH_L2_FAULT, 0x12, 1, TREG_ZERO, 1,
- { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff81f80000000ULL,
- 0ULL,
- 0ULL,
- 0xc3f8000004000000ULL
- },
- {
- -1ULL,
- 0x286a881f80000000ULL,
- -1ULL,
- -1ULL,
- 0x43f8000000000000ULL
- }
-#endif
- },
- { "prefetch_l3", TILEGX_OPC_PREFETCH_L3, 0x12, 1, TREG_ZERO, 1,
- { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff81f80000000ULL,
- 0ULL,
- 0ULL,
- 0xc3f8000004000000ULL
- },
- {
- -1ULL,
- 0x286aa01f80000000ULL,
- -1ULL,
- -1ULL,
- 0x83f8000000000000ULL
- }
-#endif
- },
- { "prefetch_l3_fault", TILEGX_OPC_PREFETCH_L3_FAULT, 0x12, 1, TREG_ZERO, 1,
- { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff81f80000000ULL,
- 0ULL,
- 0ULL,
- 0xc3f8000004000000ULL
- },
- {
- -1ULL,
- 0x286a981f80000000ULL,
- -1ULL,
- -1ULL,
- 0x81f8000004000000ULL
- }
-#endif
- },
- { "raise", TILEGX_OPC_RAISE, 0x2, 0, TREG_ZERO, 1,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xffffffff80000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286a44ae80000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "add", TILEGX_OPC_ADD, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x00000000500c0000ULL,
- 0x2806000000000000ULL,
- 0x0000000028040000ULL,
- 0x1802000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "addi", TILEGX_OPC_ADDI, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ff00000ULL,
- 0xfff8000000000000ULL,
- 0x0000000078000000ULL,
- 0x3c00000000000000ULL,
- 0ULL
- },
- {
- 0x0000000040100000ULL,
- 0x1808000000000000ULL,
- 0ULL,
- 0x0400000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "addli", TILEGX_OPC_ADDLI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 4 }, { 6, 7, 5 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc000000070000000ULL,
- 0xf800000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000010000000ULL,
- 0ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "addx", TILEGX_OPC_ADDX, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x0000000050080000ULL,
- 0x2804000000000000ULL,
- 0x0000000028000000ULL,
- 0x1800000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "addxi", TILEGX_OPC_ADDXI, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ff00000ULL,
- 0xfff8000000000000ULL,
- 0x0000000078000000ULL,
- 0x3c00000000000000ULL,
- 0ULL
- },
- {
- 0x0000000040200000ULL,
- 0x1810000000000000ULL,
- 0x0000000008000000ULL,
- 0x0800000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "addxli", TILEGX_OPC_ADDXLI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 4 }, { 6, 7, 5 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc000000070000000ULL,
- 0xf800000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000020000000ULL,
- 0x0800000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "addxsc", TILEGX_OPC_ADDXSC, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050040000ULL,
- 0x2802000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "and", TILEGX_OPC_AND, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x0000000050100000ULL,
- 0x2808000000000000ULL,
- 0x0000000050000000ULL,
- 0x2c00000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "andi", TILEGX_OPC_ANDI, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ff00000ULL,
- 0xfff8000000000000ULL,
- 0x0000000078000000ULL,
- 0x3c00000000000000ULL,
- 0ULL
- },
- {
- 0x0000000040300000ULL,
- 0x1818000000000000ULL,
- 0x0000000010000000ULL,
- 0x0c00000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "beqz", TILEGX_OPC_BEQZ, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xffc0000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1440000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "beqzt", TILEGX_OPC_BEQZT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xffc0000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1400000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "bfexts", TILEGX_OPC_BFEXTS, 0x1, 4, TREG_ZERO, 1,
- { { 8, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007f000000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000034000000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "bfextu", TILEGX_OPC_BFEXTU, 0x1, 4, TREG_ZERO, 1,
- { { 8, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007f000000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000035000000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "bfins", TILEGX_OPC_BFINS, 0x1, 4, TREG_ZERO, 1,
- { { 23, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007f000000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000036000000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "bgez", TILEGX_OPC_BGEZ, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xffc0000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x14c0000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "bgezt", TILEGX_OPC_BGEZT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xffc0000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1480000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "bgtz", TILEGX_OPC_BGTZ, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xffc0000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1540000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "bgtzt", TILEGX_OPC_BGTZT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xffc0000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1500000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "blbc", TILEGX_OPC_BLBC, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xffc0000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x15c0000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "blbct", TILEGX_OPC_BLBCT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xffc0000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1580000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "blbs", TILEGX_OPC_BLBS, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xffc0000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1640000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "blbst", TILEGX_OPC_BLBST, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xffc0000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1600000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "blez", TILEGX_OPC_BLEZ, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xffc0000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x16c0000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "blezt", TILEGX_OPC_BLEZT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xffc0000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1680000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "bltz", TILEGX_OPC_BLTZ, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xffc0000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1740000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "bltzt", TILEGX_OPC_BLTZT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xffc0000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1700000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "bnez", TILEGX_OPC_BNEZ, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xffc0000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x17c0000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "bnezt", TILEGX_OPC_BNEZT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xffc0000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1780000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "clz", TILEGX_OPC_CLZ, 0x5, 2, TREG_ZERO, 1,
- { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffff000ULL,
- 0ULL,
- 0x00000000780ff000ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051481000ULL,
- -1ULL,
- 0x00000000300c1000ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "cmoveqz", TILEGX_OPC_CMOVEQZ, 0x5, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0x00000000780c0000ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050140000ULL,
- -1ULL,
- 0x0000000048000000ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "cmovnez", TILEGX_OPC_CMOVNEZ, 0x5, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0x00000000780c0000ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050180000ULL,
- -1ULL,
- 0x0000000048040000ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "cmpeq", TILEGX_OPC_CMPEQ, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x00000000501c0000ULL,
- 0x280a000000000000ULL,
- 0x0000000040000000ULL,
- 0x2404000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "cmpeqi", TILEGX_OPC_CMPEQI, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ff00000ULL,
- 0xfff8000000000000ULL,
- 0x0000000078000000ULL,
- 0x3c00000000000000ULL,
- 0ULL
- },
- {
- 0x0000000040400000ULL,
- 0x1820000000000000ULL,
- 0x0000000018000000ULL,
- 0x1000000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "cmpexch", TILEGX_OPC_CMPEXCH, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x280e000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "cmpexch4", TILEGX_OPC_CMPEXCH4, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x280c000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "cmples", TILEGX_OPC_CMPLES, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x0000000050200000ULL,
- 0x2810000000000000ULL,
- 0x0000000038000000ULL,
- 0x2000000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "cmpleu", TILEGX_OPC_CMPLEU, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x0000000050240000ULL,
- 0x2812000000000000ULL,
- 0x0000000038040000ULL,
- 0x2002000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "cmplts", TILEGX_OPC_CMPLTS, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x0000000050280000ULL,
- 0x2814000000000000ULL,
- 0x0000000038080000ULL,
- 0x2004000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "cmpltsi", TILEGX_OPC_CMPLTSI, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ff00000ULL,
- 0xfff8000000000000ULL,
- 0x0000000078000000ULL,
- 0x3c00000000000000ULL,
- 0ULL
- },
- {
- 0x0000000040500000ULL,
- 0x1828000000000000ULL,
- 0x0000000020000000ULL,
- 0x1400000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "cmpltu", TILEGX_OPC_CMPLTU, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x00000000502c0000ULL,
- 0x2816000000000000ULL,
- 0x00000000380c0000ULL,
- 0x2006000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "cmpltui", TILEGX_OPC_CMPLTUI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ff00000ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000040600000ULL,
- 0x1830000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "cmpne", TILEGX_OPC_CMPNE, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x0000000050300000ULL,
- 0x2818000000000000ULL,
- 0x0000000040040000ULL,
- 0x2406000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "cmul", TILEGX_OPC_CMUL, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000504c0000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "cmula", TILEGX_OPC_CMULA, 0x1, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050380000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "cmulaf", TILEGX_OPC_CMULAF, 0x1, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050340000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "cmulf", TILEGX_OPC_CMULF, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050400000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "cmulfr", TILEGX_OPC_CMULFR, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000503c0000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "cmulh", TILEGX_OPC_CMULH, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050480000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "cmulhr", TILEGX_OPC_CMULHR, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050440000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "crc32_32", TILEGX_OPC_CRC32_32, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050500000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "crc32_8", TILEGX_OPC_CRC32_8, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050540000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ctz", TILEGX_OPC_CTZ, 0x5, 2, TREG_ZERO, 1,
- { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffff000ULL,
- 0ULL,
- 0x00000000780ff000ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051482000ULL,
- -1ULL,
- 0x00000000300c2000ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "dblalign", TILEGX_OPC_DBLALIGN, 0x1, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050640000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "dblalign2", TILEGX_OPC_DBLALIGN2, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050580000ULL,
- 0x281a000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "dblalign4", TILEGX_OPC_DBLALIGN4, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000505c0000ULL,
- 0x281c000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "dblalign6", TILEGX_OPC_DBLALIGN6, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050600000ULL,
- 0x281e000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "drain", TILEGX_OPC_DRAIN, 0x2, 0, TREG_ZERO, 0,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286a080000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "dtlbpr", TILEGX_OPC_DTLBPR, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286a100000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "exch", TILEGX_OPC_EXCH, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x2822000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "exch4", TILEGX_OPC_EXCH4, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x2820000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "fdouble_add_flags", TILEGX_OPC_FDOUBLE_ADD_FLAGS, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000506c0000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "fdouble_addsub", TILEGX_OPC_FDOUBLE_ADDSUB, 0x1, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050680000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "fdouble_mul_flags", TILEGX_OPC_FDOUBLE_MUL_FLAGS, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050700000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "fdouble_pack1", TILEGX_OPC_FDOUBLE_PACK1, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050740000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "fdouble_pack2", TILEGX_OPC_FDOUBLE_PACK2, 0x1, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050780000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "fdouble_sub_flags", TILEGX_OPC_FDOUBLE_SUB_FLAGS, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000507c0000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "fdouble_unpack_max", TILEGX_OPC_FDOUBLE_UNPACK_MAX, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050800000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "fdouble_unpack_min", TILEGX_OPC_FDOUBLE_UNPACK_MIN, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050840000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "fetchadd", TILEGX_OPC_FETCHADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x282a000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "fetchadd4", TILEGX_OPC_FETCHADD4, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x2824000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "fetchaddgez", TILEGX_OPC_FETCHADDGEZ, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x2828000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "fetchaddgez4", TILEGX_OPC_FETCHADDGEZ4, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x2826000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "fetchand", TILEGX_OPC_FETCHAND, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x282e000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "fetchand4", TILEGX_OPC_FETCHAND4, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x282c000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "fetchor", TILEGX_OPC_FETCHOR, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x2832000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "fetchor4", TILEGX_OPC_FETCHOR4, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x2830000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "finv", TILEGX_OPC_FINV, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286a180000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "flush", TILEGX_OPC_FLUSH, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286a280000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "flushwb", TILEGX_OPC_FLUSHWB, 0x2, 0, TREG_ZERO, 1,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286a200000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "fnop", TILEGX_OPC_FNOP, 0xf, 0, TREG_ZERO, 1,
- { { }, { }, { }, { }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffff000ULL,
- 0xfffff80000000000ULL,
- 0x00000000780ff000ULL,
- 0x3c07f80000000000ULL,
- 0ULL
- },
- {
- 0x0000000051483000ULL,
- 0x286a300000000000ULL,
- 0x00000000300c3000ULL,
- 0x1c06400000000000ULL,
- -1ULL
- }
-#endif
- },
- { "fsingle_add1", TILEGX_OPC_FSINGLE_ADD1, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050880000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "fsingle_addsub2", TILEGX_OPC_FSINGLE_ADDSUB2, 0x1, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000508c0000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "fsingle_mul1", TILEGX_OPC_FSINGLE_MUL1, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050900000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "fsingle_mul2", TILEGX_OPC_FSINGLE_MUL2, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050940000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "fsingle_pack1", TILEGX_OPC_FSINGLE_PACK1, 0x5, 2, TREG_ZERO, 1,
- { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffff000ULL,
- 0ULL,
- 0x00000000780ff000ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051484000ULL,
- -1ULL,
- 0x00000000300c4000ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "fsingle_pack2", TILEGX_OPC_FSINGLE_PACK2, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050980000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "fsingle_sub1", TILEGX_OPC_FSINGLE_SUB1, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000509c0000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "icoh", TILEGX_OPC_ICOH, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286a380000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ill", TILEGX_OPC_ILL, 0xa, 0, TREG_ZERO, 1,
- { { 0, }, { }, { 0, }, { }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0x3c07f80000000000ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286a400000000000ULL,
- -1ULL,
- 0x1c06480000000000ULL,
- -1ULL
- }
-#endif
- },
- { "inv", TILEGX_OPC_INV, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286a480000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "iret", TILEGX_OPC_IRET, 0x2, 0, TREG_ZERO, 1,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286a500000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "j", TILEGX_OPC_J, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 25 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfc00000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x2400000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "jal", TILEGX_OPC_JAL, 0x2, 1, TREG_LR, 1,
- { { 0, }, { 25 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfc00000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x2000000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "jalr", TILEGX_OPC_JALR, 0xa, 1, TREG_LR, 1,
- { { 0, }, { 7 }, { 0, }, { 13 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0x3c07f80000000000ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286a600000000000ULL,
- -1ULL,
- 0x1c06580000000000ULL,
- -1ULL
- }
-#endif
- },
- { "jalrp", TILEGX_OPC_JALRP, 0xa, 1, TREG_LR, 1,
- { { 0, }, { 7 }, { 0, }, { 13 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0x3c07f80000000000ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286a580000000000ULL,
- -1ULL,
- 0x1c06500000000000ULL,
- -1ULL
- }
-#endif
- },
- { "jr", TILEGX_OPC_JR, 0xa, 1, TREG_ZERO, 1,
- { { 0, }, { 7 }, { 0, }, { 13 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0x3c07f80000000000ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286a700000000000ULL,
- -1ULL,
- 0x1c06680000000000ULL,
- -1ULL
- }
-#endif
- },
- { "jrp", TILEGX_OPC_JRP, 0xa, 1, TREG_ZERO, 1,
- { { 0, }, { 7 }, { 0, }, { 13 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0x3c07f80000000000ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286a680000000000ULL,
- -1ULL,
- 0x1c06600000000000ULL,
- -1ULL
- }
-#endif
- },
- { "ld", TILEGX_OPC_LD, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0xc200000004000000ULL
- },
- {
- -1ULL,
- 0x286ae80000000000ULL,
- -1ULL,
- -1ULL,
- 0x8200000004000000ULL
- }
-#endif
- },
- { "ld1s", TILEGX_OPC_LD1S, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0xc200000004000000ULL
- },
- {
- -1ULL,
- 0x286a780000000000ULL,
- -1ULL,
- -1ULL,
- 0x4000000000000000ULL
- }
-#endif
- },
- { "ld1s_add", TILEGX_OPC_LD1S_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1838000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ld1u", TILEGX_OPC_LD1U, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0xc200000004000000ULL
- },
- {
- -1ULL,
- 0x286a800000000000ULL,
- -1ULL,
- -1ULL,
- 0x4000000004000000ULL
- }
-#endif
- },
- { "ld1u_add", TILEGX_OPC_LD1U_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1840000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ld2s", TILEGX_OPC_LD2S, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0xc200000004000000ULL
- },
- {
- -1ULL,
- 0x286a880000000000ULL,
- -1ULL,
- -1ULL,
- 0x4200000000000000ULL
- }
-#endif
- },
- { "ld2s_add", TILEGX_OPC_LD2S_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1848000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ld2u", TILEGX_OPC_LD2U, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0xc200000004000000ULL
- },
- {
- -1ULL,
- 0x286a900000000000ULL,
- -1ULL,
- -1ULL,
- 0x4200000004000000ULL
- }
-#endif
- },
- { "ld2u_add", TILEGX_OPC_LD2U_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1850000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ld4s", TILEGX_OPC_LD4S, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0xc200000004000000ULL
- },
- {
- -1ULL,
- 0x286a980000000000ULL,
- -1ULL,
- -1ULL,
- 0x8000000004000000ULL
- }
-#endif
- },
- { "ld4s_add", TILEGX_OPC_LD4S_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1858000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ld4u", TILEGX_OPC_LD4U, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0xc200000004000000ULL
- },
- {
- -1ULL,
- 0x286aa00000000000ULL,
- -1ULL,
- -1ULL,
- 0x8200000000000000ULL
- }
-#endif
- },
- { "ld4u_add", TILEGX_OPC_LD4U_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1860000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ld_add", TILEGX_OPC_LD_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x18a0000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ldna", TILEGX_OPC_LDNA, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286aa80000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ldna_add", TILEGX_OPC_LDNA_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x18a8000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ldnt", TILEGX_OPC_LDNT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286ae00000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ldnt1s", TILEGX_OPC_LDNT1S, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286ab00000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ldnt1s_add", TILEGX_OPC_LDNT1S_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1868000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ldnt1u", TILEGX_OPC_LDNT1U, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286ab80000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ldnt1u_add", TILEGX_OPC_LDNT1U_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1870000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ldnt2s", TILEGX_OPC_LDNT2S, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286ac00000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ldnt2s_add", TILEGX_OPC_LDNT2S_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1878000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ldnt2u", TILEGX_OPC_LDNT2U, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286ac80000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ldnt2u_add", TILEGX_OPC_LDNT2U_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1880000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ldnt4s", TILEGX_OPC_LDNT4S, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286ad00000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ldnt4s_add", TILEGX_OPC_LDNT4S_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1888000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ldnt4u", TILEGX_OPC_LDNT4U, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286ad80000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ldnt4u_add", TILEGX_OPC_LDNT4U_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1890000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "ldnt_add", TILEGX_OPC_LDNT_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1898000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "lnk", TILEGX_OPC_LNK, 0xa, 1, TREG_ZERO, 1,
- { { 0, }, { 6 }, { 0, }, { 12 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0x3c07f80000000000ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286af00000000000ULL,
- -1ULL,
- 0x1c06700000000000ULL,
- -1ULL
- }
-#endif
- },
- { "mf", TILEGX_OPC_MF, 0x2, 0, TREG_ZERO, 1,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286af80000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mfspr", TILEGX_OPC_MFSPR, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 6, 27 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x18b0000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mm", TILEGX_OPC_MM, 0x1, 4, TREG_ZERO, 1,
- { { 23, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007f000000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000037000000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mnz", TILEGX_OPC_MNZ, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x0000000050a00000ULL,
- 0x2834000000000000ULL,
- 0x0000000048080000ULL,
- 0x2804000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "mtspr", TILEGX_OPC_MTSPR, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 28, 7 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x18b8000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mul_hs_hs", TILEGX_OPC_MUL_HS_HS, 0x5, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0x00000000780c0000ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050d40000ULL,
- -1ULL,
- 0x0000000068000000ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mul_hs_hu", TILEGX_OPC_MUL_HS_HU, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050d80000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mul_hs_ls", TILEGX_OPC_MUL_HS_LS, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050dc0000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mul_hs_lu", TILEGX_OPC_MUL_HS_LU, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050e00000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mul_hu_hu", TILEGX_OPC_MUL_HU_HU, 0x5, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0x00000000780c0000ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050e40000ULL,
- -1ULL,
- 0x0000000068040000ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mul_hu_ls", TILEGX_OPC_MUL_HU_LS, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050e80000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mul_hu_lu", TILEGX_OPC_MUL_HU_LU, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050ec0000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mul_ls_ls", TILEGX_OPC_MUL_LS_LS, 0x5, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0x00000000780c0000ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050f00000ULL,
- -1ULL,
- 0x0000000068080000ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mul_ls_lu", TILEGX_OPC_MUL_LS_LU, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050f40000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mul_lu_lu", TILEGX_OPC_MUL_LU_LU, 0x5, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0x00000000780c0000ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050f80000ULL,
- -1ULL,
- 0x00000000680c0000ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mula_hs_hs", TILEGX_OPC_MULA_HS_HS, 0x5, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0x00000000780c0000ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050a80000ULL,
- -1ULL,
- 0x0000000070000000ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mula_hs_hu", TILEGX_OPC_MULA_HS_HU, 0x1, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050ac0000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mula_hs_ls", TILEGX_OPC_MULA_HS_LS, 0x1, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050b00000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mula_hs_lu", TILEGX_OPC_MULA_HS_LU, 0x1, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050b40000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mula_hu_hu", TILEGX_OPC_MULA_HU_HU, 0x5, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0x00000000780c0000ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050b80000ULL,
- -1ULL,
- 0x0000000070040000ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mula_hu_ls", TILEGX_OPC_MULA_HU_LS, 0x1, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050bc0000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mula_hu_lu", TILEGX_OPC_MULA_HU_LU, 0x1, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050c00000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mula_ls_ls", TILEGX_OPC_MULA_LS_LS, 0x5, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0x00000000780c0000ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050c40000ULL,
- -1ULL,
- 0x0000000070080000ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mula_ls_lu", TILEGX_OPC_MULA_LS_LU, 0x1, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050c80000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mula_lu_lu", TILEGX_OPC_MULA_LU_LU, 0x5, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0x00000000780c0000ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050cc0000ULL,
- -1ULL,
- 0x00000000700c0000ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mulax", TILEGX_OPC_MULAX, 0x5, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0x00000000780c0000ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050a40000ULL,
- -1ULL,
- 0x0000000040080000ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mulx", TILEGX_OPC_MULX, 0x5, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0x00000000780c0000ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000050d00000ULL,
- -1ULL,
- 0x00000000400c0000ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "mz", TILEGX_OPC_MZ, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x0000000050fc0000ULL,
- 0x2836000000000000ULL,
- 0x00000000480c0000ULL,
- 0x2806000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "nap", TILEGX_OPC_NAP, 0x2, 0, TREG_ZERO, 0,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286b000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "nop", TILEGX_OPC_NOP, 0xf, 0, TREG_ZERO, 1,
- { { }, { }, { }, { }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffff000ULL,
- 0xfffff80000000000ULL,
- 0x00000000780ff000ULL,
- 0x3c07f80000000000ULL,
- 0ULL
- },
- {
- 0x0000000051485000ULL,
- 0x286b080000000000ULL,
- 0x00000000300c5000ULL,
- 0x1c06780000000000ULL,
- -1ULL
- }
-#endif
- },
- { "nor", TILEGX_OPC_NOR, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x0000000051000000ULL,
- 0x2838000000000000ULL,
- 0x0000000050040000ULL,
- 0x2c02000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "or", TILEGX_OPC_OR, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x0000000051040000ULL,
- 0x283a000000000000ULL,
- 0x0000000050080000ULL,
- 0x2c04000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "ori", TILEGX_OPC_ORI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ff00000ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000040700000ULL,
- 0x18c0000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "pcnt", TILEGX_OPC_PCNT, 0x5, 2, TREG_ZERO, 1,
- { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffff000ULL,
- 0ULL,
- 0x00000000780ff000ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051486000ULL,
- -1ULL,
- 0x00000000300c6000ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "revbits", TILEGX_OPC_REVBITS, 0x5, 2, TREG_ZERO, 1,
- { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffff000ULL,
- 0ULL,
- 0x00000000780ff000ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051487000ULL,
- -1ULL,
- 0x00000000300c7000ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "revbytes", TILEGX_OPC_REVBYTES, 0x5, 2, TREG_ZERO, 1,
- { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffff000ULL,
- 0ULL,
- 0x00000000780ff000ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051488000ULL,
- -1ULL,
- 0x00000000300c8000ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "rotl", TILEGX_OPC_ROTL, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x0000000051080000ULL,
- 0x283c000000000000ULL,
- 0x0000000058000000ULL,
- 0x3000000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "rotli", TILEGX_OPC_ROTLI, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 29 }, { 6, 7, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x0000000060040000ULL,
- 0x3002000000000000ULL,
- 0x0000000078000000ULL,
- 0x3800000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "shl", TILEGX_OPC_SHL, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x0000000051280000ULL,
- 0x284c000000000000ULL,
- 0x0000000058040000ULL,
- 0x3002000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "shl16insli", TILEGX_OPC_SHL16INSLI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 4 }, { 6, 7, 5 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc000000070000000ULL,
- 0xf800000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000070000000ULL,
- 0x3800000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "shl1add", TILEGX_OPC_SHL1ADD, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x0000000051100000ULL,
- 0x2840000000000000ULL,
- 0x0000000030000000ULL,
- 0x1c00000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "shl1addx", TILEGX_OPC_SHL1ADDX, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x00000000510c0000ULL,
- 0x283e000000000000ULL,
- 0x0000000060040000ULL,
- 0x3402000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "shl2add", TILEGX_OPC_SHL2ADD, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x0000000051180000ULL,
- 0x2844000000000000ULL,
- 0x0000000030040000ULL,
- 0x1c02000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "shl2addx", TILEGX_OPC_SHL2ADDX, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x0000000051140000ULL,
- 0x2842000000000000ULL,
- 0x0000000060080000ULL,
- 0x3404000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "shl3add", TILEGX_OPC_SHL3ADD, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x0000000051200000ULL,
- 0x2848000000000000ULL,
- 0x0000000030080000ULL,
- 0x1c04000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "shl3addx", TILEGX_OPC_SHL3ADDX, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x00000000511c0000ULL,
- 0x2846000000000000ULL,
- 0x00000000600c0000ULL,
- 0x3406000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "shli", TILEGX_OPC_SHLI, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 29 }, { 6, 7, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x0000000060080000ULL,
- 0x3004000000000000ULL,
- 0x0000000078040000ULL,
- 0x3802000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "shlx", TILEGX_OPC_SHLX, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051240000ULL,
- 0x284a000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "shlxi", TILEGX_OPC_SHLXI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000600c0000ULL,
- 0x3006000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "shrs", TILEGX_OPC_SHRS, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x00000000512c0000ULL,
- 0x284e000000000000ULL,
- 0x0000000058080000ULL,
- 0x3004000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "shrsi", TILEGX_OPC_SHRSI, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 29 }, { 6, 7, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x0000000060100000ULL,
- 0x3008000000000000ULL,
- 0x0000000078080000ULL,
- 0x3804000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "shru", TILEGX_OPC_SHRU, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x0000000051340000ULL,
- 0x2852000000000000ULL,
- 0x00000000580c0000ULL,
- 0x3006000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "shrui", TILEGX_OPC_SHRUI, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 29 }, { 6, 7, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x0000000060140000ULL,
- 0x300a000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3806000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "shrux", TILEGX_OPC_SHRUX, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051300000ULL,
- 0x2850000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "shruxi", TILEGX_OPC_SHRUXI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000060180000ULL,
- 0x300c000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "shufflebytes", TILEGX_OPC_SHUFFLEBYTES, 0x1, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051380000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "st", TILEGX_OPC_ST, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 14, 33 } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0xc200000004000000ULL
- },
- {
- -1ULL,
- 0x2862000000000000ULL,
- -1ULL,
- -1ULL,
- 0xc200000004000000ULL
- }
-#endif
- },
- { "st1", TILEGX_OPC_ST1, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 14, 33 } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0xc200000004000000ULL
- },
- {
- -1ULL,
- 0x2854000000000000ULL,
- -1ULL,
- -1ULL,
- 0xc000000000000000ULL
- }
-#endif
- },
- { "st1_add", TILEGX_OPC_ST1_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x18c8000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "st2", TILEGX_OPC_ST2, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 14, 33 } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0xc200000004000000ULL
- },
- {
- -1ULL,
- 0x2856000000000000ULL,
- -1ULL,
- -1ULL,
- 0xc000000004000000ULL
- }
-#endif
- },
- { "st2_add", TILEGX_OPC_ST2_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x18d0000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "st4", TILEGX_OPC_ST4, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 14, 33 } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0xc200000004000000ULL
- },
- {
- -1ULL,
- 0x2858000000000000ULL,
- -1ULL,
- -1ULL,
- 0xc200000000000000ULL
- }
-#endif
- },
- { "st4_add", TILEGX_OPC_ST4_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x18d8000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "st_add", TILEGX_OPC_ST_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x1900000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "stnt", TILEGX_OPC_STNT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x2860000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "stnt1", TILEGX_OPC_STNT1, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x285a000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "stnt1_add", TILEGX_OPC_STNT1_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x18e0000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "stnt2", TILEGX_OPC_STNT2, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x285c000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "stnt2_add", TILEGX_OPC_STNT2_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x18e8000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "stnt4", TILEGX_OPC_STNT4, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x285e000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "stnt4_add", TILEGX_OPC_STNT4_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x18f0000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "stnt_add", TILEGX_OPC_STNT_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x18f8000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "sub", TILEGX_OPC_SUB, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x0000000051440000ULL,
- 0x2868000000000000ULL,
- 0x00000000280c0000ULL,
- 0x1806000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "subx", TILEGX_OPC_SUBX, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x0000000051400000ULL,
- 0x2866000000000000ULL,
- 0x0000000028080000ULL,
- 0x1804000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "subxsc", TILEGX_OPC_SUBXSC, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000513c0000ULL,
- 0x2864000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "swint0", TILEGX_OPC_SWINT0, 0x2, 0, TREG_ZERO, 0,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286b100000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "swint1", TILEGX_OPC_SWINT1, 0x2, 0, TREG_ZERO, 0,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286b180000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "swint2", TILEGX_OPC_SWINT2, 0x2, 0, TREG_ZERO, 0,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286b200000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "swint3", TILEGX_OPC_SWINT3, 0x2, 0, TREG_ZERO, 0,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286b280000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "tblidxb0", TILEGX_OPC_TBLIDXB0, 0x5, 2, TREG_ZERO, 1,
- { { 23, 9 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffff000ULL,
- 0ULL,
- 0x00000000780ff000ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051489000ULL,
- -1ULL,
- 0x00000000300c9000ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "tblidxb1", TILEGX_OPC_TBLIDXB1, 0x5, 2, TREG_ZERO, 1,
- { { 23, 9 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffff000ULL,
- 0ULL,
- 0x00000000780ff000ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x000000005148a000ULL,
- -1ULL,
- 0x00000000300ca000ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "tblidxb2", TILEGX_OPC_TBLIDXB2, 0x5, 2, TREG_ZERO, 1,
- { { 23, 9 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffff000ULL,
- 0ULL,
- 0x00000000780ff000ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x000000005148b000ULL,
- -1ULL,
- 0x00000000300cb000ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "tblidxb3", TILEGX_OPC_TBLIDXB3, 0x5, 2, TREG_ZERO, 1,
- { { 23, 9 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffff000ULL,
- 0ULL,
- 0x00000000780ff000ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x000000005148c000ULL,
- -1ULL,
- 0x00000000300cc000ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1add", TILEGX_OPC_V1ADD, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051500000ULL,
- 0x286e000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1addi", TILEGX_OPC_V1ADDI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ff00000ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000040800000ULL,
- 0x1908000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1adduc", TILEGX_OPC_V1ADDUC, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000514c0000ULL,
- 0x286c000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1adiffu", TILEGX_OPC_V1ADIFFU, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051540000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1avgu", TILEGX_OPC_V1AVGU, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051580000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1cmpeq", TILEGX_OPC_V1CMPEQ, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000515c0000ULL,
- 0x2870000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1cmpeqi", TILEGX_OPC_V1CMPEQI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ff00000ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000040900000ULL,
- 0x1910000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1cmples", TILEGX_OPC_V1CMPLES, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051600000ULL,
- 0x2872000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1cmpleu", TILEGX_OPC_V1CMPLEU, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051640000ULL,
- 0x2874000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1cmplts", TILEGX_OPC_V1CMPLTS, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051680000ULL,
- 0x2876000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1cmpltsi", TILEGX_OPC_V1CMPLTSI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ff00000ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000040a00000ULL,
- 0x1918000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1cmpltu", TILEGX_OPC_V1CMPLTU, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000516c0000ULL,
- 0x2878000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1cmpltui", TILEGX_OPC_V1CMPLTUI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ff00000ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000040b00000ULL,
- 0x1920000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1cmpne", TILEGX_OPC_V1CMPNE, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051700000ULL,
- 0x287a000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1ddotpu", TILEGX_OPC_V1DDOTPU, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052880000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1ddotpua", TILEGX_OPC_V1DDOTPUA, 0x1, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052840000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1ddotpus", TILEGX_OPC_V1DDOTPUS, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051780000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1ddotpusa", TILEGX_OPC_V1DDOTPUSA, 0x1, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051740000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1dotp", TILEGX_OPC_V1DOTP, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051880000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1dotpa", TILEGX_OPC_V1DOTPA, 0x1, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000517c0000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1dotpu", TILEGX_OPC_V1DOTPU, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052900000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1dotpua", TILEGX_OPC_V1DOTPUA, 0x1, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000528c0000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1dotpus", TILEGX_OPC_V1DOTPUS, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051840000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1dotpusa", TILEGX_OPC_V1DOTPUSA, 0x1, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051800000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1int_h", TILEGX_OPC_V1INT_H, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000518c0000ULL,
- 0x287c000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1int_l", TILEGX_OPC_V1INT_L, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051900000ULL,
- 0x287e000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1maxu", TILEGX_OPC_V1MAXU, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051940000ULL,
- 0x2880000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1maxui", TILEGX_OPC_V1MAXUI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ff00000ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000040c00000ULL,
- 0x1928000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1minu", TILEGX_OPC_V1MINU, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051980000ULL,
- 0x2882000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1minui", TILEGX_OPC_V1MINUI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ff00000ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000040d00000ULL,
- 0x1930000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1mnz", TILEGX_OPC_V1MNZ, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000519c0000ULL,
- 0x2884000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1multu", TILEGX_OPC_V1MULTU, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051a00000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1mulu", TILEGX_OPC_V1MULU, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051a80000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1mulus", TILEGX_OPC_V1MULUS, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051a40000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1mz", TILEGX_OPC_V1MZ, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051ac0000ULL,
- 0x2886000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1sadau", TILEGX_OPC_V1SADAU, 0x1, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051b00000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1sadu", TILEGX_OPC_V1SADU, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051b40000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1shl", TILEGX_OPC_V1SHL, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051b80000ULL,
- 0x2888000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1shli", TILEGX_OPC_V1SHLI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000601c0000ULL,
- 0x300e000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1shrs", TILEGX_OPC_V1SHRS, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051bc0000ULL,
- 0x288a000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1shrsi", TILEGX_OPC_V1SHRSI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000060200000ULL,
- 0x3010000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1shru", TILEGX_OPC_V1SHRU, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051c00000ULL,
- 0x288c000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1shrui", TILEGX_OPC_V1SHRUI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000060240000ULL,
- 0x3012000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1sub", TILEGX_OPC_V1SUB, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051c80000ULL,
- 0x2890000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v1subuc", TILEGX_OPC_V1SUBUC, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051c40000ULL,
- 0x288e000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2add", TILEGX_OPC_V2ADD, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051d00000ULL,
- 0x2894000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2addi", TILEGX_OPC_V2ADDI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ff00000ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000040e00000ULL,
- 0x1938000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2addsc", TILEGX_OPC_V2ADDSC, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051cc0000ULL,
- 0x2892000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2adiffs", TILEGX_OPC_V2ADIFFS, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051d40000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2avgs", TILEGX_OPC_V2AVGS, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051d80000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2cmpeq", TILEGX_OPC_V2CMPEQ, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051dc0000ULL,
- 0x2896000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2cmpeqi", TILEGX_OPC_V2CMPEQI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ff00000ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000040f00000ULL,
- 0x1940000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2cmples", TILEGX_OPC_V2CMPLES, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051e00000ULL,
- 0x2898000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2cmpleu", TILEGX_OPC_V2CMPLEU, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051e40000ULL,
- 0x289a000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2cmplts", TILEGX_OPC_V2CMPLTS, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051e80000ULL,
- 0x289c000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2cmpltsi", TILEGX_OPC_V2CMPLTSI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ff00000ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000041000000ULL,
- 0x1948000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2cmpltu", TILEGX_OPC_V2CMPLTU, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051ec0000ULL,
- 0x289e000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2cmpltui", TILEGX_OPC_V2CMPLTUI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ff00000ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000041100000ULL,
- 0x1950000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2cmpne", TILEGX_OPC_V2CMPNE, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051f00000ULL,
- 0x28a0000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2dotp", TILEGX_OPC_V2DOTP, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051f80000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2dotpa", TILEGX_OPC_V2DOTPA, 0x1, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051f40000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2int_h", TILEGX_OPC_V2INT_H, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000051fc0000ULL,
- 0x28a2000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2int_l", TILEGX_OPC_V2INT_L, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052000000ULL,
- 0x28a4000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2maxs", TILEGX_OPC_V2MAXS, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052040000ULL,
- 0x28a6000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2maxsi", TILEGX_OPC_V2MAXSI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ff00000ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000041200000ULL,
- 0x1958000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2mins", TILEGX_OPC_V2MINS, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052080000ULL,
- 0x28a8000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2minsi", TILEGX_OPC_V2MINSI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ff00000ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000041300000ULL,
- 0x1960000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2mnz", TILEGX_OPC_V2MNZ, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000520c0000ULL,
- 0x28aa000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2mulfsc", TILEGX_OPC_V2MULFSC, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052100000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2muls", TILEGX_OPC_V2MULS, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052140000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2mults", TILEGX_OPC_V2MULTS, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052180000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2mz", TILEGX_OPC_V2MZ, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000521c0000ULL,
- 0x28ac000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2packh", TILEGX_OPC_V2PACKH, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052200000ULL,
- 0x28ae000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2packl", TILEGX_OPC_V2PACKL, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052240000ULL,
- 0x28b0000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2packuc", TILEGX_OPC_V2PACKUC, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052280000ULL,
- 0x28b2000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2sadas", TILEGX_OPC_V2SADAS, 0x1, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000522c0000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2sadau", TILEGX_OPC_V2SADAU, 0x1, 3, TREG_ZERO, 1,
- { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052300000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2sads", TILEGX_OPC_V2SADS, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052340000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2sadu", TILEGX_OPC_V2SADU, 0x1, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052380000ULL,
- -1ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2shl", TILEGX_OPC_V2SHL, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052400000ULL,
- 0x28b6000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2shli", TILEGX_OPC_V2SHLI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000060280000ULL,
- 0x3014000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2shlsc", TILEGX_OPC_V2SHLSC, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000523c0000ULL,
- 0x28b4000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2shrs", TILEGX_OPC_V2SHRS, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052440000ULL,
- 0x28b8000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2shrsi", TILEGX_OPC_V2SHRSI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000602c0000ULL,
- 0x3016000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2shru", TILEGX_OPC_V2SHRU, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052480000ULL,
- 0x28ba000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2shrui", TILEGX_OPC_V2SHRUI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000060300000ULL,
- 0x3018000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2sub", TILEGX_OPC_V2SUB, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052500000ULL,
- 0x28be000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v2subsc", TILEGX_OPC_V2SUBSC, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000524c0000ULL,
- 0x28bc000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v4add", TILEGX_OPC_V4ADD, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052580000ULL,
- 0x28c2000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v4addsc", TILEGX_OPC_V4ADDSC, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052540000ULL,
- 0x28c0000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v4int_h", TILEGX_OPC_V4INT_H, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000525c0000ULL,
- 0x28c4000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v4int_l", TILEGX_OPC_V4INT_L, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052600000ULL,
- 0x28c6000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v4packsc", TILEGX_OPC_V4PACKSC, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052640000ULL,
- 0x28c8000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v4shl", TILEGX_OPC_V4SHL, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000526c0000ULL,
- 0x28cc000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v4shlsc", TILEGX_OPC_V4SHLSC, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052680000ULL,
- 0x28ca000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v4shrs", TILEGX_OPC_V4SHRS, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052700000ULL,
- 0x28ce000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v4shru", TILEGX_OPC_V4SHRU, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052740000ULL,
- 0x28d0000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v4sub", TILEGX_OPC_V4SUB, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x00000000527c0000ULL,
- 0x28d4000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "v4subsc", TILEGX_OPC_V4SUBSC, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000052780000ULL,
- 0x28d2000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "wh64", TILEGX_OPC_WH64, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0ULL,
- 0xfffff80000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- -1ULL,
- 0x286b300000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { "xor", TILEGX_OPC_XOR, 0xf, 3, TREG_ZERO, 1,
- { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ffc0000ULL,
- 0xfffe000000000000ULL,
- 0x00000000780c0000ULL,
- 0x3c06000000000000ULL,
- 0ULL
- },
- {
- 0x0000000052800000ULL,
- 0x28d6000000000000ULL,
- 0x00000000500c0000ULL,
- 0x2c06000000000000ULL,
- -1ULL
- }
-#endif
- },
- { "xori", TILEGX_OPC_XORI, 0x3, 3, TREG_ZERO, 1,
- { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
-#ifndef DISASM_ONLY
- {
- 0xc00000007ff00000ULL,
- 0xfff8000000000000ULL,
- 0ULL,
- 0ULL,
- 0ULL
- },
- {
- 0x0000000041400000ULL,
- 0x1968000000000000ULL,
- -1ULL,
- -1ULL,
- -1ULL
- }
-#endif
- },
- { NULL, TILEGX_OPC_NONE, 0, 0, TREG_ZERO, 0, { { 0, } },
-#ifndef DISASM_ONLY
- { 0, }, { 0, }
-#endif
- }
-};
-#define BITFIELD(start, size) ((start) | (((1 << (size)) - 1) << 6))
-#define CHILD(array_index) (TILEGX_OPC_NONE + (array_index))
-
-static const UShort decode_X0_fsm[936] =
-{
- BITFIELD(22, 9) /* index 0 */,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_BFEXTS,
- TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTU,
- TILEGX_OPC_BFEXTU, TILEGX_OPC_BFEXTU, TILEGX_OPC_BFEXTU, TILEGX_OPC_BFINS,
- TILEGX_OPC_BFINS, TILEGX_OPC_BFINS, TILEGX_OPC_BFINS, TILEGX_OPC_MM,
- TILEGX_OPC_MM, TILEGX_OPC_MM, TILEGX_OPC_MM, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(528), CHILD(578),
- CHILD(583), CHILD(588), CHILD(593), CHILD(598), TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, CHILD(603), CHILD(620), CHILD(637), CHILD(654), CHILD(671),
- CHILD(703), CHILD(797), CHILD(814), CHILD(831), CHILD(848), CHILD(865),
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, CHILD(889), TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
- CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
- CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
- CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
- CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
- CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
- CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
- CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
- CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
- CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
- CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
- BITFIELD(6, 2) /* index 513 */,
- TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(518),
- BITFIELD(8, 2) /* index 518 */,
- TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(523),
- BITFIELD(10, 2) /* index 523 */,
- TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_MOVELI,
- BITFIELD(20, 2) /* index 528 */,
- TILEGX_OPC_NONE, CHILD(533), TILEGX_OPC_ADDXI, CHILD(548),
- BITFIELD(6, 2) /* index 533 */,
- TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(538),
- BITFIELD(8, 2) /* index 538 */,
- TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(543),
- BITFIELD(10, 2) /* index 543 */,
- TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
- BITFIELD(0, 2) /* index 548 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(553),
- BITFIELD(2, 2) /* index 553 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(558),
- BITFIELD(4, 2) /* index 558 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(563),
- BITFIELD(6, 2) /* index 563 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(568),
- BITFIELD(8, 2) /* index 568 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(573),
- BITFIELD(10, 2) /* index 573 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
- BITFIELD(20, 2) /* index 578 */,
- TILEGX_OPC_CMPEQI, TILEGX_OPC_CMPLTSI, TILEGX_OPC_CMPLTUI, TILEGX_OPC_ORI,
- BITFIELD(20, 2) /* index 583 */,
- TILEGX_OPC_V1ADDI, TILEGX_OPC_V1CMPEQI, TILEGX_OPC_V1CMPLTSI,
- TILEGX_OPC_V1CMPLTUI,
- BITFIELD(20, 2) /* index 588 */,
- TILEGX_OPC_V1MAXUI, TILEGX_OPC_V1MINUI, TILEGX_OPC_V2ADDI,
- TILEGX_OPC_V2CMPEQI,
- BITFIELD(20, 2) /* index 593 */,
- TILEGX_OPC_V2CMPLTSI, TILEGX_OPC_V2CMPLTUI, TILEGX_OPC_V2MAXSI,
- TILEGX_OPC_V2MINSI,
- BITFIELD(20, 2) /* index 598 */,
- TILEGX_OPC_XORI, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(18, 4) /* index 603 */,
- TILEGX_OPC_NONE, TILEGX_OPC_ADDXSC, TILEGX_OPC_ADDX, TILEGX_OPC_ADD,
- TILEGX_OPC_AND, TILEGX_OPC_CMOVEQZ, TILEGX_OPC_CMOVNEZ, TILEGX_OPC_CMPEQ,
- TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
- TILEGX_OPC_CMPNE, TILEGX_OPC_CMULAF, TILEGX_OPC_CMULA, TILEGX_OPC_CMULFR,
- BITFIELD(18, 4) /* index 620 */,
- TILEGX_OPC_CMULF, TILEGX_OPC_CMULHR, TILEGX_OPC_CMULH, TILEGX_OPC_CMUL,
- TILEGX_OPC_CRC32_32, TILEGX_OPC_CRC32_8, TILEGX_OPC_DBLALIGN2,
- TILEGX_OPC_DBLALIGN4, TILEGX_OPC_DBLALIGN6, TILEGX_OPC_DBLALIGN,
- TILEGX_OPC_FDOUBLE_ADDSUB, TILEGX_OPC_FDOUBLE_ADD_FLAGS,
- TILEGX_OPC_FDOUBLE_MUL_FLAGS, TILEGX_OPC_FDOUBLE_PACK1,
- TILEGX_OPC_FDOUBLE_PACK2, TILEGX_OPC_FDOUBLE_SUB_FLAGS,
- BITFIELD(18, 4) /* index 637 */,
- TILEGX_OPC_FDOUBLE_UNPACK_MAX, TILEGX_OPC_FDOUBLE_UNPACK_MIN,
- TILEGX_OPC_FSINGLE_ADD1, TILEGX_OPC_FSINGLE_ADDSUB2,
- TILEGX_OPC_FSINGLE_MUL1, TILEGX_OPC_FSINGLE_MUL2, TILEGX_OPC_FSINGLE_PACK2,
- TILEGX_OPC_FSINGLE_SUB1, TILEGX_OPC_MNZ, TILEGX_OPC_MULAX,
- TILEGX_OPC_MULA_HS_HS, TILEGX_OPC_MULA_HS_HU, TILEGX_OPC_MULA_HS_LS,
- TILEGX_OPC_MULA_HS_LU, TILEGX_OPC_MULA_HU_HU, TILEGX_OPC_MULA_HU_LS,
- BITFIELD(18, 4) /* index 654 */,
- TILEGX_OPC_MULA_HU_LU, TILEGX_OPC_MULA_LS_LS, TILEGX_OPC_MULA_LS_LU,
- TILEGX_OPC_MULA_LU_LU, TILEGX_OPC_MULX, TILEGX_OPC_MUL_HS_HS,
- TILEGX_OPC_MUL_HS_HU, TILEGX_OPC_MUL_HS_LS, TILEGX_OPC_MUL_HS_LU,
- TILEGX_OPC_MUL_HU_HU, TILEGX_OPC_MUL_HU_LS, TILEGX_OPC_MUL_HU_LU,
- TILEGX_OPC_MUL_LS_LS, TILEGX_OPC_MUL_LS_LU, TILEGX_OPC_MUL_LU_LU,
- TILEGX_OPC_MZ,
- BITFIELD(18, 4) /* index 671 */,
- TILEGX_OPC_NOR, CHILD(688), TILEGX_OPC_ROTL, TILEGX_OPC_SHL1ADDX,
- TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADDX, TILEGX_OPC_SHL2ADD,
- TILEGX_OPC_SHL3ADDX, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHLX, TILEGX_OPC_SHL,
- TILEGX_OPC_SHRS, TILEGX_OPC_SHRUX, TILEGX_OPC_SHRU, TILEGX_OPC_SHUFFLEBYTES,
- TILEGX_OPC_SUBXSC,
- BITFIELD(12, 2) /* index 688 */,
- TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(693),
- BITFIELD(14, 2) /* index 693 */,
- TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(698),
- BITFIELD(16, 2) /* index 698 */,
- TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
- BITFIELD(18, 4) /* index 703 */,
- TILEGX_OPC_SUBX, TILEGX_OPC_SUB, CHILD(720), TILEGX_OPC_V1ADDUC,
- TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADIFFU, TILEGX_OPC_V1AVGU,
- TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLEU,
- TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPNE,
- TILEGX_OPC_V1DDOTPUSA, TILEGX_OPC_V1DDOTPUS, TILEGX_OPC_V1DOTPA,
- BITFIELD(12, 4) /* index 720 */,
- TILEGX_OPC_NONE, CHILD(737), CHILD(742), CHILD(747), CHILD(752), CHILD(757),
- CHILD(762), CHILD(767), CHILD(772), CHILD(777), CHILD(782), CHILD(787),
- CHILD(792), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(16, 2) /* index 737 */,
- TILEGX_OPC_CLZ, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(16, 2) /* index 742 */,
- TILEGX_OPC_CTZ, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(16, 2) /* index 747 */,
- TILEGX_OPC_FNOP, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(16, 2) /* index 752 */,
- TILEGX_OPC_FSINGLE_PACK1, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(16, 2) /* index 757 */,
- TILEGX_OPC_NOP, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(16, 2) /* index 762 */,
- TILEGX_OPC_PCNT, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(16, 2) /* index 767 */,
- TILEGX_OPC_REVBITS, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(16, 2) /* index 772 */,
- TILEGX_OPC_REVBYTES, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(16, 2) /* index 777 */,
- TILEGX_OPC_TBLIDXB0, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(16, 2) /* index 782 */,
- TILEGX_OPC_TBLIDXB1, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(16, 2) /* index 787 */,
- TILEGX_OPC_TBLIDXB2, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(16, 2) /* index 792 */,
- TILEGX_OPC_TBLIDXB3, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(18, 4) /* index 797 */,
- TILEGX_OPC_V1DOTPUSA, TILEGX_OPC_V1DOTPUS, TILEGX_OPC_V1DOTP,
- TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1MAXU,
- TILEGX_OPC_V1MINU, TILEGX_OPC_V1MNZ, TILEGX_OPC_V1MULTU, TILEGX_OPC_V1MULUS,
- TILEGX_OPC_V1MULU, TILEGX_OPC_V1MZ, TILEGX_OPC_V1SADAU, TILEGX_OPC_V1SADU,
- TILEGX_OPC_V1SHL, TILEGX_OPC_V1SHRS,
- BITFIELD(18, 4) /* index 814 */,
- TILEGX_OPC_V1SHRU, TILEGX_OPC_V1SUBUC, TILEGX_OPC_V1SUB, TILEGX_OPC_V2ADDSC,
- TILEGX_OPC_V2ADD, TILEGX_OPC_V2ADIFFS, TILEGX_OPC_V2AVGS,
- TILEGX_OPC_V2CMPEQ, TILEGX_OPC_V2CMPLES, TILEGX_OPC_V2CMPLEU,
- TILEGX_OPC_V2CMPLTS, TILEGX_OPC_V2CMPLTU, TILEGX_OPC_V2CMPNE,
- TILEGX_OPC_V2DOTPA, TILEGX_OPC_V2DOTP, TILEGX_OPC_V2INT_H,
- BITFIELD(18, 4) /* index 831 */,
- TILEGX_OPC_V2INT_L, TILEGX_OPC_V2MAXS, TILEGX_OPC_V2MINS, TILEGX_OPC_V2MNZ,
- TILEGX_OPC_V2MULFSC, TILEGX_OPC_V2MULS, TILEGX_OPC_V2MULTS, TILEGX_OPC_V2MZ,
- TILEGX_OPC_V2PACKH, TILEGX_OPC_V2PACKL, TILEGX_OPC_V2PACKUC,
- TILEGX_OPC_V2SADAS, TILEGX_OPC_V2SADAU, TILEGX_OPC_V2SADS,
- TILEGX_OPC_V2SADU, TILEGX_OPC_V2SHLSC,
- BITFIELD(18, 4) /* index 848 */,
- TILEGX_OPC_V2SHL, TILEGX_OPC_V2SHRS, TILEGX_OPC_V2SHRU, TILEGX_OPC_V2SUBSC,
- TILEGX_OPC_V2SUB, TILEGX_OPC_V4ADDSC, TILEGX_OPC_V4ADD, TILEGX_OPC_V4INT_H,
- TILEGX_OPC_V4INT_L, TILEGX_OPC_V4PACKSC, TILEGX_OPC_V4SHLSC,
- TILEGX_OPC_V4SHL, TILEGX_OPC_V4SHRS, TILEGX_OPC_V4SHRU, TILEGX_OPC_V4SUBSC,
- TILEGX_OPC_V4SUB,
- BITFIELD(18, 3) /* index 865 */,
- CHILD(874), CHILD(877), CHILD(880), CHILD(883), CHILD(886), TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(21, 1) /* index 874 */,
- TILEGX_OPC_XOR, TILEGX_OPC_NONE,
- BITFIELD(21, 1) /* index 877 */,
- TILEGX_OPC_V1DDOTPUA, TILEGX_OPC_NONE,
- BITFIELD(21, 1) /* index 880 */,
- TILEGX_OPC_V1DDOTPU, TILEGX_OPC_NONE,
- BITFIELD(21, 1) /* index 883 */,
- TILEGX_OPC_V1DOTPUA, TILEGX_OPC_NONE,
- BITFIELD(21, 1) /* index 886 */,
- TILEGX_OPC_V1DOTPU, TILEGX_OPC_NONE,
- BITFIELD(18, 4) /* index 889 */,
- TILEGX_OPC_NONE, TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHLXI,
- TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, TILEGX_OPC_SHRUXI, TILEGX_OPC_V1SHLI,
- TILEGX_OPC_V1SHRSI, TILEGX_OPC_V1SHRUI, TILEGX_OPC_V2SHLI,
- TILEGX_OPC_V2SHRSI, TILEGX_OPC_V2SHRUI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE,
- BITFIELD(0, 2) /* index 906 */,
- TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
- CHILD(911),
- BITFIELD(2, 2) /* index 911 */,
- TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
- CHILD(916),
- BITFIELD(4, 2) /* index 916 */,
- TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
- CHILD(921),
- BITFIELD(6, 2) /* index 921 */,
- TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
- CHILD(926),
- BITFIELD(8, 2) /* index 926 */,
- TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
- CHILD(931),
- BITFIELD(10, 2) /* index 931 */,
- TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
- TILEGX_OPC_INFOL,
-};
-
-static const UShort decode_X1_fsm[1266] =
-{
- BITFIELD(53, 9) /* index 0 */,
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_BEQZT,
- TILEGX_OPC_BEQZT, TILEGX_OPC_BEQZ, TILEGX_OPC_BEQZ, TILEGX_OPC_BGEZT,
- TILEGX_OPC_BGEZT, TILEGX_OPC_BGEZ, TILEGX_OPC_BGEZ, TILEGX_OPC_BGTZT,
- TILEGX_OPC_BGTZT, TILEGX_OPC_BGTZ, TILEGX_OPC_BGTZ, TILEGX_OPC_BLBCT,
- TILEGX_OPC_BLBCT, TILEGX_OPC_BLBC, TILEGX_OPC_BLBC, TILEGX_OPC_BLBST,
- TILEGX_OPC_BLBST, TILEGX_OPC_BLBS, TILEGX_OPC_BLBS, TILEGX_OPC_BLEZT,
- TILEGX_OPC_BLEZT, TILEGX_OPC_BLEZ, TILEGX_OPC_BLEZ, TILEGX_OPC_BLTZT,
- TILEGX_OPC_BLTZT, TILEGX_OPC_BLTZ, TILEGX_OPC_BLTZ, TILEGX_OPC_BNEZT,
- TILEGX_OPC_BNEZT, TILEGX_OPC_BNEZ, TILEGX_OPC_BNEZ, CHILD(528), CHILD(578),
- CHILD(598), CHILD(703), CHILD(723), CHILD(728), CHILD(753), CHILD(758),
- CHILD(763), CHILD(768), CHILD(773), CHILD(778), TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_JAL,
- TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
- TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
- TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
- TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
- TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
- TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
- TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
- TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_J, TILEGX_OPC_J,
- TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
- TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
- TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
- TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
- TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
- TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
- CHILD(783), CHILD(800), CHILD(832), CHILD(849), CHILD(1168), CHILD(1185),
- CHILD(1202), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(1219), TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(1236), CHILD(1236), CHILD(1236),
- CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
- CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
- CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
- CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
- CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
- CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
- CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
- CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
- CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
- CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
- CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
- CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236),
- CHILD(1236),
- BITFIELD(37, 2) /* index 513 */,
- TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(518),
- BITFIELD(39, 2) /* index 518 */,
- TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(523),
- BITFIELD(41, 2) /* index 523 */,
- TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_MOVELI,
- BITFIELD(51, 2) /* index 528 */,
- TILEGX_OPC_NONE, CHILD(533), TILEGX_OPC_ADDXI, CHILD(548),
- BITFIELD(37, 2) /* index 533 */,
- TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(538),
- BITFIELD(39, 2) /* index 538 */,
- TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(543),
- BITFIELD(41, 2) /* index 543 */,
- TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
- BITFIELD(31, 2) /* index 548 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(553),
- BITFIELD(33, 2) /* index 553 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(558),
- BITFIELD(35, 2) /* index 558 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(563),
- BITFIELD(37, 2) /* index 563 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(568),
- BITFIELD(39, 2) /* index 568 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(573),
- BITFIELD(41, 2) /* index 573 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
- BITFIELD(51, 2) /* index 578 */,
- TILEGX_OPC_CMPEQI, TILEGX_OPC_CMPLTSI, TILEGX_OPC_CMPLTUI, CHILD(583),
- BITFIELD(31, 2) /* index 583 */,
- TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, CHILD(588),
- BITFIELD(33, 2) /* index 588 */,
- TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, CHILD(593),
- BITFIELD(35, 2) /* index 593 */,
- TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD,
- TILEGX_OPC_PREFETCH_ADD_L1_FAULT,
- BITFIELD(51, 2) /* index 598 */,
- CHILD(603), CHILD(618), CHILD(633), CHILD(648),
- BITFIELD(31, 2) /* index 603 */,
- TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, CHILD(608),
- BITFIELD(33, 2) /* index 608 */,
- TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, CHILD(613),
- BITFIELD(35, 2) /* index 613 */,
- TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD,
- TILEGX_OPC_PREFETCH_ADD_L1,
- BITFIELD(31, 2) /* index 618 */,
- TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, CHILD(623),
- BITFIELD(33, 2) /* index 623 */,
- TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, CHILD(628),
- BITFIELD(35, 2) /* index 628 */,
- TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD,
- TILEGX_OPC_PREFETCH_ADD_L2_FAULT,
- BITFIELD(31, 2) /* index 633 */,
- TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, CHILD(638),
- BITFIELD(33, 2) /* index 638 */,
- TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, CHILD(643),
- BITFIELD(35, 2) /* index 643 */,
- TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD,
- TILEGX_OPC_PREFETCH_ADD_L2,
- BITFIELD(31, 2) /* index 648 */,
- CHILD(653), CHILD(653), CHILD(653), CHILD(673),
- BITFIELD(43, 2) /* index 653 */,
- CHILD(658), TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD,
- BITFIELD(45, 2) /* index 658 */,
- CHILD(663), TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD,
- BITFIELD(47, 2) /* index 663 */,
- CHILD(668), TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD,
- BITFIELD(49, 2) /* index 668 */,
- TILEGX_OPC_LD4S_TLS, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD,
- TILEGX_OPC_LD4S_ADD,
- BITFIELD(33, 2) /* index 673 */,
- CHILD(653), CHILD(653), CHILD(653), CHILD(678),
- BITFIELD(35, 2) /* index 678 */,
- CHILD(653), CHILD(653), CHILD(653), CHILD(683),
- BITFIELD(43, 2) /* index 683 */,
- CHILD(688), TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
- TILEGX_OPC_PREFETCH_ADD_L3_FAULT, TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
- BITFIELD(45, 2) /* index 688 */,
- CHILD(693), TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
- TILEGX_OPC_PREFETCH_ADD_L3_FAULT, TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
- BITFIELD(47, 2) /* index 693 */,
- CHILD(698), TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
- TILEGX_OPC_PREFETCH_ADD_L3_FAULT, TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
- BITFIELD(49, 2) /* index 698 */,
- TILEGX_OPC_LD4S_TLS, TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
- TILEGX_OPC_PREFETCH_ADD_L3_FAULT, TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
- BITFIELD(51, 2) /* index 703 */,
- CHILD(708), TILEGX_OPC_LDNT1S_ADD, TILEGX_OPC_LDNT1U_ADD,
- TILEGX_OPC_LDNT2S_ADD,
- BITFIELD(31, 2) /* index 708 */,
- TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, CHILD(713),
- BITFIELD(33, 2) /* index 713 */,
- TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, CHILD(718),
- BITFIELD(35, 2) /* index 718 */,
- TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD,
- TILEGX_OPC_PREFETCH_ADD_L3,
- BITFIELD(51, 2) /* index 723 */,
- TILEGX_OPC_LDNT2U_ADD, TILEGX_OPC_LDNT4S_ADD, TILEGX_OPC_LDNT4U_ADD,
- TILEGX_OPC_LDNT_ADD,
- BITFIELD(51, 2) /* index 728 */,
- CHILD(733), TILEGX_OPC_LDNA_ADD, TILEGX_OPC_MFSPR, TILEGX_OPC_MTSPR,
- BITFIELD(43, 2) /* index 733 */,
- CHILD(738), TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD,
- BITFIELD(45, 2) /* index 738 */,
- CHILD(743), TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD,
- BITFIELD(47, 2) /* index 743 */,
- CHILD(748), TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD,
- BITFIELD(49, 2) /* index 748 */,
- TILEGX_OPC_LD_TLS, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD,
- BITFIELD(51, 2) /* index 753 */,
- TILEGX_OPC_ORI, TILEGX_OPC_ST1_ADD, TILEGX_OPC_ST2_ADD, TILEGX_OPC_ST4_ADD,
- BITFIELD(51, 2) /* index 758 */,
- TILEGX_OPC_STNT1_ADD, TILEGX_OPC_STNT2_ADD, TILEGX_OPC_STNT4_ADD,
- TILEGX_OPC_STNT_ADD,
- BITFIELD(51, 2) /* index 763 */,
- TILEGX_OPC_ST_ADD, TILEGX_OPC_V1ADDI, TILEGX_OPC_V1CMPEQI,
- TILEGX_OPC_V1CMPLTSI,
- BITFIELD(51, 2) /* index 768 */,
- TILEGX_OPC_V1CMPLTUI, TILEGX_OPC_V1MAXUI, TILEGX_OPC_V1MINUI,
- TILEGX_OPC_V2ADDI,
- BITFIELD(51, 2) /* index 773 */,
- TILEGX_OPC_V2CMPEQI, TILEGX_OPC_V2CMPLTSI, TILEGX_OPC_V2CMPLTUI,
- TILEGX_OPC_V2MAXSI,
- BITFIELD(51, 2) /* index 778 */,
- TILEGX_OPC_V2MINSI, TILEGX_OPC_XORI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(49, 4) /* index 783 */,
- TILEGX_OPC_NONE, TILEGX_OPC_ADDXSC, TILEGX_OPC_ADDX, TILEGX_OPC_ADD,
- TILEGX_OPC_AND, TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPEXCH4, TILEGX_OPC_CMPEXCH,
- TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
- TILEGX_OPC_CMPNE, TILEGX_OPC_DBLALIGN2, TILEGX_OPC_DBLALIGN4,
- TILEGX_OPC_DBLALIGN6,
- BITFIELD(49, 4) /* index 800 */,
- TILEGX_OPC_EXCH4, TILEGX_OPC_EXCH, TILEGX_OPC_FETCHADD4,
- TILEGX_OPC_FETCHADDGEZ4, TILEGX_OPC_FETCHADDGEZ, TILEGX_OPC_FETCHADD,
- TILEGX_OPC_FETCHAND4, TILEGX_OPC_FETCHAND, TILEGX_OPC_FETCHOR4,
- TILEGX_OPC_FETCHOR, TILEGX_OPC_MNZ, TILEGX_OPC_MZ, TILEGX_OPC_NOR,
- CHILD(817), TILEGX_OPC_ROTL, TILEGX_OPC_SHL1ADDX,
- BITFIELD(43, 2) /* index 817 */,
- TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(822),
- BITFIELD(45, 2) /* index 822 */,
- TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(827),
- BITFIELD(47, 2) /* index 827 */,
- TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
- BITFIELD(49, 4) /* index 832 */,
- TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADDX, TILEGX_OPC_SHL2ADD,
- TILEGX_OPC_SHL3ADDX, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHLX, TILEGX_OPC_SHL,
- TILEGX_OPC_SHRS, TILEGX_OPC_SHRUX, TILEGX_OPC_SHRU, TILEGX_OPC_ST1,
- TILEGX_OPC_ST2, TILEGX_OPC_ST4, TILEGX_OPC_STNT1, TILEGX_OPC_STNT2,
- TILEGX_OPC_STNT4,
- BITFIELD(46, 7) /* index 849 */,
- TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT,
- TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT,
- TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST,
- TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_SUBXSC,
- TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC,
- TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBX,
- TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX,
- TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUB,
- TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB,
- TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, CHILD(978), CHILD(987),
- CHILD(1066), CHILD(1150), CHILD(1159), TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC,
- TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC,
- TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD,
- TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD,
- TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ,
- TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ,
- TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ,
- TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES,
- TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES,
- TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLEU,
- TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU,
- TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU,
- TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS,
- TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS,
- TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS,
- TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU,
- TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU,
- TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPNE,
- TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE,
- TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE,
- TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
- TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
- TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
- TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
- TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
- TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
- BITFIELD(43, 3) /* index 978 */,
- TILEGX_OPC_NONE, TILEGX_OPC_DRAIN, TILEGX_OPC_DTLBPR, TILEGX_OPC_FINV,
- TILEGX_OPC_FLUSHWB, TILEGX_OPC_FLUSH, TILEGX_OPC_FNOP, TILEGX_OPC_ICOH,
- BITFIELD(43, 3) /* index 987 */,
- CHILD(996), TILEGX_OPC_INV, TILEGX_OPC_IRET, TILEGX_OPC_JALRP,
- TILEGX_OPC_JALR, TILEGX_OPC_JRP, TILEGX_OPC_JR, CHILD(1051),
- BITFIELD(31, 2) /* index 996 */,
- CHILD(1001), CHILD(1026), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
- BITFIELD(33, 2) /* index 1001 */,
- TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_ILL, CHILD(1006),
- BITFIELD(35, 2) /* index 1006 */,
- TILEGX_OPC_ILL, CHILD(1011), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
- BITFIELD(37, 2) /* index 1011 */,
- TILEGX_OPC_ILL, CHILD(1016), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
- BITFIELD(39, 2) /* index 1016 */,
- TILEGX_OPC_ILL, CHILD(1021), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
- BITFIELD(41, 2) /* index 1021 */,
- TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_BPT, TILEGX_OPC_ILL,
- BITFIELD(33, 2) /* index 1026 */,
- TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_ILL, CHILD(1031),
- BITFIELD(35, 2) /* index 1031 */,
- TILEGX_OPC_ILL, CHILD(1036), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
- BITFIELD(37, 2) /* index 1036 */,
- TILEGX_OPC_ILL, CHILD(1041), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
- BITFIELD(39, 2) /* index 1041 */,
- TILEGX_OPC_ILL, CHILD(1046), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
- BITFIELD(41, 2) /* index 1046 */,
- TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_RAISE, TILEGX_OPC_ILL,
- BITFIELD(31, 2) /* index 1051 */,
- TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(1056),
- BITFIELD(33, 2) /* index 1056 */,
- TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(1061),
- BITFIELD(35, 2) /* index 1061 */,
- TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S,
- TILEGX_OPC_PREFETCH_L1_FAULT,
- BITFIELD(43, 3) /* index 1066 */,
- CHILD(1075), CHILD(1090), CHILD(1105), CHILD(1120), CHILD(1135),
- TILEGX_OPC_LDNA, TILEGX_OPC_LDNT1S, TILEGX_OPC_LDNT1U,
- BITFIELD(31, 2) /* index 1075 */,
- TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(1080),
- BITFIELD(33, 2) /* index 1080 */,
- TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(1085),
- BITFIELD(35, 2) /* index 1085 */,
- TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_PREFETCH,
- BITFIELD(31, 2) /* index 1090 */,
- TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(1095),
- BITFIELD(33, 2) /* index 1095 */,
- TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(1100),
- BITFIELD(35, 2) /* index 1100 */,
- TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S,
- TILEGX_OPC_PREFETCH_L2_FAULT,
- BITFIELD(31, 2) /* index 1105 */,
- TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(1110),
- BITFIELD(33, 2) /* index 1110 */,
- TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(1115),
- BITFIELD(35, 2) /* index 1115 */,
- TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_PREFETCH_L2,
- BITFIELD(31, 2) /* index 1120 */,
- TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(1125),
- BITFIELD(33, 2) /* index 1125 */,
- TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(1130),
- BITFIELD(35, 2) /* index 1130 */,
- TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S,
- TILEGX_OPC_PREFETCH_L3_FAULT,
- BITFIELD(31, 2) /* index 1135 */,
- TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(1140),
- BITFIELD(33, 2) /* index 1140 */,
- TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(1145),
- BITFIELD(35, 2) /* index 1145 */,
- TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_PREFETCH_L3,
- BITFIELD(43, 3) /* index 1150 */,
- TILEGX_OPC_LDNT2S, TILEGX_OPC_LDNT2U, TILEGX_OPC_LDNT4S, TILEGX_OPC_LDNT4U,
- TILEGX_OPC_LDNT, TILEGX_OPC_LD, TILEGX_OPC_LNK, TILEGX_OPC_MF,
- BITFIELD(43, 3) /* index 1159 */,
- TILEGX_OPC_NAP, TILEGX_OPC_NOP, TILEGX_OPC_SWINT0, TILEGX_OPC_SWINT1,
- TILEGX_OPC_SWINT2, TILEGX_OPC_SWINT3, TILEGX_OPC_WH64, TILEGX_OPC_NONE,
- BITFIELD(49, 4) /* index 1168 */,
- TILEGX_OPC_V1MAXU, TILEGX_OPC_V1MINU, TILEGX_OPC_V1MNZ, TILEGX_OPC_V1MZ,
- TILEGX_OPC_V1SHL, TILEGX_OPC_V1SHRS, TILEGX_OPC_V1SHRU, TILEGX_OPC_V1SUBUC,
- TILEGX_OPC_V1SUB, TILEGX_OPC_V2ADDSC, TILEGX_OPC_V2ADD, TILEGX_OPC_V2CMPEQ,
- TILEGX_OPC_V2CMPLES, TILEGX_OPC_V2CMPLEU, TILEGX_OPC_V2CMPLTS,
- TILEGX_OPC_V2CMPLTU,
- BITFIELD(49, 4) /* index 1185 */,
- TILEGX_OPC_V2CMPNE, TILEGX_OPC_V2INT_H, TILEGX_OPC_V2INT_L,
- TILEGX_OPC_V2MAXS, TILEGX_OPC_V2MINS, TILEGX_OPC_V2MNZ, TILEGX_OPC_V2MZ,
- TILEGX_OPC_V2PACKH, TILEGX_OPC_V2PACKL, TILEGX_OPC_V2PACKUC,
- TILEGX_OPC_V2SHLSC, TILEGX_OPC_V2SHL, TILEGX_OPC_V2SHRS, TILEGX_OPC_V2SHRU,
- TILEGX_OPC_V2SUBSC, TILEGX_OPC_V2SUB,
- BITFIELD(49, 4) /* index 1202 */,
- TILEGX_OPC_V4ADDSC, TILEGX_OPC_V4ADD, TILEGX_OPC_V4INT_H,
- TILEGX_OPC_V4INT_L, TILEGX_OPC_V4PACKSC, TILEGX_OPC_V4SHLSC,
- TILEGX_OPC_V4SHL, TILEGX_OPC_V4SHRS, TILEGX_OPC_V4SHRU, TILEGX_OPC_V4SUBSC,
- TILEGX_OPC_V4SUB, TILEGX_OPC_XOR, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(49, 4) /* index 1219 */,
- TILEGX_OPC_NONE, TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHLXI,
- TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, TILEGX_OPC_SHRUXI, TILEGX_OPC_V1SHLI,
- TILEGX_OPC_V1SHRSI, TILEGX_OPC_V1SHRUI, TILEGX_OPC_V2SHLI,
- TILEGX_OPC_V2SHRSI, TILEGX_OPC_V2SHRUI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE,
- BITFIELD(31, 2) /* index 1236 */,
- TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
- CHILD(1241),
- BITFIELD(33, 2) /* index 1241 */,
- TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
- CHILD(1246),
- BITFIELD(35, 2) /* index 1246 */,
- TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
- CHILD(1251),
- BITFIELD(37, 2) /* index 1251 */,
- TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
- CHILD(1256),
- BITFIELD(39, 2) /* index 1256 */,
- TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
- CHILD(1261),
- BITFIELD(41, 2) /* index 1261 */,
- TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
- TILEGX_OPC_INFOL,
-};
-
-static const UShort decode_Y0_fsm[178] =
-{
- BITFIELD(27, 4) /* index 0 */,
- CHILD(17), TILEGX_OPC_ADDXI, CHILD(32), TILEGX_OPC_CMPEQI,
- TILEGX_OPC_CMPLTSI, CHILD(62), CHILD(67), CHILD(118), CHILD(123),
- CHILD(128), CHILD(133), CHILD(153), CHILD(158), CHILD(163), CHILD(168),
- CHILD(173),
- BITFIELD(6, 2) /* index 17 */,
- TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(22),
- BITFIELD(8, 2) /* index 22 */,
- TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(27),
- BITFIELD(10, 2) /* index 27 */,
- TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
- BITFIELD(0, 2) /* index 32 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(37),
- BITFIELD(2, 2) /* index 37 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(42),
- BITFIELD(4, 2) /* index 42 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(47),
- BITFIELD(6, 2) /* index 47 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(52),
- BITFIELD(8, 2) /* index 52 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(57),
- BITFIELD(10, 2) /* index 57 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
- BITFIELD(18, 2) /* index 62 */,
- TILEGX_OPC_ADDX, TILEGX_OPC_ADD, TILEGX_OPC_SUBX, TILEGX_OPC_SUB,
- BITFIELD(15, 5) /* index 67 */,
- TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD,
- TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD,
- TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADD,
- TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD,
- TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD,
- TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD,
- TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD,
- TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, CHILD(100),
- CHILD(109), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(12, 3) /* index 100 */,
- TILEGX_OPC_NONE, TILEGX_OPC_CLZ, TILEGX_OPC_CTZ, TILEGX_OPC_FNOP,
- TILEGX_OPC_FSINGLE_PACK1, TILEGX_OPC_NOP, TILEGX_OPC_PCNT,
- TILEGX_OPC_REVBITS,
- BITFIELD(12, 3) /* index 109 */,
- TILEGX_OPC_REVBYTES, TILEGX_OPC_TBLIDXB0, TILEGX_OPC_TBLIDXB1,
- TILEGX_OPC_TBLIDXB2, TILEGX_OPC_TBLIDXB3, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE,
- BITFIELD(18, 2) /* index 118 */,
- TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
- BITFIELD(18, 2) /* index 123 */,
- TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPNE, TILEGX_OPC_MULAX, TILEGX_OPC_MULX,
- BITFIELD(18, 2) /* index 128 */,
- TILEGX_OPC_CMOVEQZ, TILEGX_OPC_CMOVNEZ, TILEGX_OPC_MNZ, TILEGX_OPC_MZ,
- BITFIELD(18, 2) /* index 133 */,
- TILEGX_OPC_AND, TILEGX_OPC_NOR, CHILD(138), TILEGX_OPC_XOR,
- BITFIELD(12, 2) /* index 138 */,
- TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(143),
- BITFIELD(14, 2) /* index 143 */,
- TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(148),
- BITFIELD(16, 2) /* index 148 */,
- TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
- BITFIELD(18, 2) /* index 153 */,
- TILEGX_OPC_ROTL, TILEGX_OPC_SHL, TILEGX_OPC_SHRS, TILEGX_OPC_SHRU,
- BITFIELD(18, 2) /* index 158 */,
- TILEGX_OPC_NONE, TILEGX_OPC_SHL1ADDX, TILEGX_OPC_SHL2ADDX,
- TILEGX_OPC_SHL3ADDX,
- BITFIELD(18, 2) /* index 163 */,
- TILEGX_OPC_MUL_HS_HS, TILEGX_OPC_MUL_HU_HU, TILEGX_OPC_MUL_LS_LS,
- TILEGX_OPC_MUL_LU_LU,
- BITFIELD(18, 2) /* index 168 */,
- TILEGX_OPC_MULA_HS_HS, TILEGX_OPC_MULA_HU_HU, TILEGX_OPC_MULA_LS_LS,
- TILEGX_OPC_MULA_LU_LU,
- BITFIELD(18, 2) /* index 173 */,
- TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI,
-};
-
-static const UShort decode_Y1_fsm[167] =
-{
- BITFIELD(58, 4) /* index 0 */,
- TILEGX_OPC_NONE, CHILD(17), TILEGX_OPC_ADDXI, CHILD(32), TILEGX_OPC_CMPEQI,
- TILEGX_OPC_CMPLTSI, CHILD(62), CHILD(67), CHILD(117), CHILD(122),
- CHILD(127), CHILD(132), CHILD(152), CHILD(157), CHILD(162), TILEGX_OPC_NONE,
- BITFIELD(37, 2) /* index 17 */,
- TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(22),
- BITFIELD(39, 2) /* index 22 */,
- TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(27),
- BITFIELD(41, 2) /* index 27 */,
- TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
- BITFIELD(31, 2) /* index 32 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(37),
- BITFIELD(33, 2) /* index 37 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(42),
- BITFIELD(35, 2) /* index 42 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(47),
- BITFIELD(37, 2) /* index 47 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(52),
- BITFIELD(39, 2) /* index 52 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(57),
- BITFIELD(41, 2) /* index 57 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
- BITFIELD(49, 2) /* index 62 */,
- TILEGX_OPC_ADDX, TILEGX_OPC_ADD, TILEGX_OPC_SUBX, TILEGX_OPC_SUB,
- BITFIELD(47, 4) /* index 67 */,
- TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD,
- TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD,
- TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL3ADD,
- TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, CHILD(84),
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(43, 3) /* index 84 */,
- CHILD(93), CHILD(96), CHILD(99), CHILD(102), CHILD(105), CHILD(108),
- CHILD(111), CHILD(114),
- BITFIELD(46, 1) /* index 93 */,
- TILEGX_OPC_NONE, TILEGX_OPC_FNOP,
- BITFIELD(46, 1) /* index 96 */,
- TILEGX_OPC_NONE, TILEGX_OPC_ILL,
- BITFIELD(46, 1) /* index 99 */,
- TILEGX_OPC_NONE, TILEGX_OPC_JALRP,
- BITFIELD(46, 1) /* index 102 */,
- TILEGX_OPC_NONE, TILEGX_OPC_JALR,
- BITFIELD(46, 1) /* index 105 */,
- TILEGX_OPC_NONE, TILEGX_OPC_JRP,
- BITFIELD(46, 1) /* index 108 */,
- TILEGX_OPC_NONE, TILEGX_OPC_JR,
- BITFIELD(46, 1) /* index 111 */,
- TILEGX_OPC_NONE, TILEGX_OPC_LNK,
- BITFIELD(46, 1) /* index 114 */,
- TILEGX_OPC_NONE, TILEGX_OPC_NOP,
- BITFIELD(49, 2) /* index 117 */,
- TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
- BITFIELD(49, 2) /* index 122 */,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPNE,
- BITFIELD(49, 2) /* index 127 */,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_MNZ, TILEGX_OPC_MZ,
- BITFIELD(49, 2) /* index 132 */,
- TILEGX_OPC_AND, TILEGX_OPC_NOR, CHILD(137), TILEGX_OPC_XOR,
- BITFIELD(43, 2) /* index 137 */,
- TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(142),
- BITFIELD(45, 2) /* index 142 */,
- TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(147),
- BITFIELD(47, 2) /* index 147 */,
- TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
- BITFIELD(49, 2) /* index 152 */,
- TILEGX_OPC_ROTL, TILEGX_OPC_SHL, TILEGX_OPC_SHRS, TILEGX_OPC_SHRU,
- BITFIELD(49, 2) /* index 157 */,
- TILEGX_OPC_NONE, TILEGX_OPC_SHL1ADDX, TILEGX_OPC_SHL2ADDX,
- TILEGX_OPC_SHL3ADDX,
- BITFIELD(49, 2) /* index 162 */,
- TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI,
-};
-
-static const UShort decode_Y2_fsm[118] =
-{
- BITFIELD(62, 2) /* index 0 */,
- TILEGX_OPC_NONE, CHILD(5), CHILD(66), CHILD(109),
- BITFIELD(55, 3) /* index 5 */,
- CHILD(14), CHILD(14), CHILD(14), CHILD(17), CHILD(40), CHILD(40), CHILD(40),
- CHILD(43),
- BITFIELD(26, 1) /* index 14 */,
- TILEGX_OPC_LD1S, TILEGX_OPC_LD1U,
- BITFIELD(26, 1) /* index 17 */,
- CHILD(20), CHILD(30),
- BITFIELD(51, 2) /* index 20 */,
- TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(25),
- BITFIELD(53, 2) /* index 25 */,
- TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S,
- TILEGX_OPC_PREFETCH_L1_FAULT,
- BITFIELD(51, 2) /* index 30 */,
- TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(35),
- BITFIELD(53, 2) /* index 35 */,
- TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_PREFETCH,
- BITFIELD(26, 1) /* index 40 */,
- TILEGX_OPC_LD2S, TILEGX_OPC_LD2U,
- BITFIELD(26, 1) /* index 43 */,
- CHILD(46), CHILD(56),
- BITFIELD(51, 2) /* index 46 */,
- TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(51),
- BITFIELD(53, 2) /* index 51 */,
- TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S,
- TILEGX_OPC_PREFETCH_L2_FAULT,
- BITFIELD(51, 2) /* index 56 */,
- TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(61),
- BITFIELD(53, 2) /* index 61 */,
- TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_PREFETCH_L2,
- BITFIELD(56, 2) /* index 66 */,
- CHILD(71), CHILD(74), CHILD(90), CHILD(93),
- BITFIELD(26, 1) /* index 71 */,
- TILEGX_OPC_NONE, TILEGX_OPC_LD4S,
- BITFIELD(26, 1) /* index 74 */,
- TILEGX_OPC_NONE, CHILD(77),
- BITFIELD(51, 2) /* index 77 */,
- TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(82),
- BITFIELD(53, 2) /* index 82 */,
- TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(87),
- BITFIELD(55, 1) /* index 87 */,
- TILEGX_OPC_LD4S, TILEGX_OPC_PREFETCH_L3_FAULT,
- BITFIELD(26, 1) /* index 90 */,
- TILEGX_OPC_LD4U, TILEGX_OPC_LD,
- BITFIELD(26, 1) /* index 93 */,
- CHILD(96), TILEGX_OPC_LD,
- BITFIELD(51, 2) /* index 96 */,
- TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(101),
- BITFIELD(53, 2) /* index 101 */,
- TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(106),
- BITFIELD(55, 1) /* index 106 */,
- TILEGX_OPC_LD4U, TILEGX_OPC_PREFETCH_L3,
- BITFIELD(26, 1) /* index 109 */,
- CHILD(112), CHILD(115),
- BITFIELD(57, 1) /* index 112 */,
- TILEGX_OPC_ST1, TILEGX_OPC_ST4,
- BITFIELD(57, 1) /* index 115 */,
- TILEGX_OPC_ST2, TILEGX_OPC_ST,
-};
-
-#undef BITFIELD
-#undef CHILD
-const UShort * const
-tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS] =
-{
- decode_X0_fsm,
- decode_X1_fsm,
- decode_Y0_fsm,
- decode_Y1_fsm,
- decode_Y2_fsm
-};
-const struct tilegx_operand tilegx_operands[35] =
-{
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_X0),
- 8, 1, 0, 0, 0, 0,
- create_Imm8_X0, get_Imm8_X0
- },
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_X1),
- 8, 1, 0, 0, 0, 0,
- create_Imm8_X1, get_Imm8_X1
- },
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_Y0),
- 8, 1, 0, 0, 0, 0,
- create_Imm8_Y0, get_Imm8_Y0
- },
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_Y1),
- 8, 1, 0, 0, 0, 0,
- create_Imm8_Y1, get_Imm8_Y1
- },
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM16_X0_HW0_LAST),
- 16, 1, 0, 0, 0, 0,
- create_Imm16_X0, get_Imm16_X0
- },
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM16_X1_HW0_LAST),
- 16, 1, 0, 0, 0, 0,
- create_Imm16_X1, get_Imm16_X1
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 0, 1, 0, 0,
- create_Dest_X1, get_Dest_X1
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcA_X1, get_SrcA_X1
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 0, 1, 0, 0,
- create_Dest_X0, get_Dest_X0
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcA_X0, get_SrcA_X0
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 0, 1, 0, 0,
- create_Dest_Y0, get_Dest_Y0
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcA_Y0, get_SrcA_Y0
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 0, 1, 0, 0,
- create_Dest_Y1, get_Dest_Y1
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcA_Y1, get_SrcA_Y1
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcA_Y2, get_SrcA_Y2
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 1, 0, 0,
- create_SrcA_X1, get_SrcA_X1
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcB_X0, get_SrcB_X0
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcB_X1, get_SrcB_X1
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcB_Y0, get_SrcB_Y0
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcB_Y1, get_SrcB_Y1
- },
- {
- TILEGX_OP_TYPE_ADDRESS, BFD_RELOC(TILEGX_BROFF_X1),
- 17, 1, 0, 0, 1, TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES,
- create_BrOff_X1, get_BrOff_X1
- },
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_MMSTART_X0),
- 6, 0, 0, 0, 0, 0,
- create_BFStart_X0, get_BFStart_X0
- },
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_MMEND_X0),
- 6, 0, 0, 0, 0, 0,
- create_BFEnd_X0, get_BFEnd_X0
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 1, 0, 0,
- create_Dest_X0, get_Dest_X0
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 1, 0, 0,
- create_Dest_Y0, get_Dest_Y0
- },
- {
- TILEGX_OP_TYPE_ADDRESS, BFD_RELOC(TILEGX_JUMPOFF_X1),
- 27, 1, 0, 0, 1, TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES,
- create_JumpOff_X1, get_JumpOff_X1
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 0, 1, 0, 0,
- create_SrcBDest_Y2, get_SrcBDest_Y2
- },
- {
- TILEGX_OP_TYPE_SPR, BFD_RELOC(TILEGX_MF_IMM14_X1),
- 14, 0, 0, 0, 0, 0,
- create_MF_Imm14_X1, get_MF_Imm14_X1
- },
- {
- TILEGX_OP_TYPE_SPR, BFD_RELOC(TILEGX_MT_IMM14_X1),
- 14, 0, 0, 0, 0, 0,
- create_MT_Imm14_X1, get_MT_Imm14_X1
- },
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_X0),
- 6, 0, 0, 0, 0, 0,
- create_ShAmt_X0, get_ShAmt_X0
- },
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_X1),
- 6, 0, 0, 0, 0, 0,
- create_ShAmt_X1, get_ShAmt_X1
- },
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_Y0),
- 6, 0, 0, 0, 0, 0,
- create_ShAmt_Y0, get_ShAmt_Y0
- },
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_Y1),
- 6, 0, 0, 0, 0, 0,
- create_ShAmt_Y1, get_ShAmt_Y1
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcBDest_Y2, get_SrcBDest_Y2
- },
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_DEST_IMM8_X1),
- 8, 1, 0, 0, 0, 0,
- create_Dest_Imm8_X1, get_Dest_Imm8_X1
- }
-};
-
-
-/* Given a set of bundle bits and a specific pipe, returns which
- * instruction the bundle contains in that pipe.
- */
-const struct tilegx_opcode *
-find_opcode ( tilegx_bundle_bits bits, tilegx_pipeline pipe )
-{
- const UShort *table = tilegx_bundle_decoder_fsms[pipe];
- Int index = 0;
-
- while (1)
- {
- UShort bitspec = table[index];
- UInt bitfield =
- ((UInt)(bits >> (bitspec & 63))) & (bitspec >> 6);
-
- UShort next = table[index + 1 + bitfield];
- if (next <= TILEGX_OPC_NONE)
- return &tilegx_opcodes[next];
-
- index = next - TILEGX_OPC_NONE;
- }
-}
-
-
-int
-parse_insn_tilegx ( tilegx_bundle_bits bits,
- ULong pc,
- struct tilegx_decoded_instruction
- decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE] )
-{
- Int num_instructions = 0;
- Int pipe;
-
- Int min_pipe, max_pipe;
- if ((bits & TILEGX_BUNDLE_MODE_MASK) == 0)
- {
- min_pipe = TILEGX_PIPELINE_X0;
- max_pipe = TILEGX_PIPELINE_X1;
- }
- else
- {
- min_pipe = TILEGX_PIPELINE_Y0;
- max_pipe = TILEGX_PIPELINE_Y2;
- }
-
- /* For each pipe, find an instruction that fits. */
- for (pipe = min_pipe; pipe <= max_pipe; pipe++)
- {
- const struct tilegx_opcode *opc;
- struct tilegx_decoded_instruction *d;
- Int i;
-
- d = &decoded[num_instructions++];
- opc = find_opcode (bits, (tilegx_pipeline)pipe);
- d->opcode = opc;
-
- /* Decode each operand, sign extending, etc. as appropriate. */
- for (i = 0; i < opc->num_operands; i++)
- {
- const struct tilegx_operand *op =
- &tilegx_operands[opc->operands[pipe][i]];
- Int raw_opval = op->extract (bits);
- Long opval;
-
- if (op->is_signed)
- {
- /* Sign-extend the operand. */
- Int shift = (int)((sizeof(int) * 8) - op->num_bits);
- raw_opval = (raw_opval << shift) >> shift;
- }
-
- /* Adjust PC-relative scaled branch offsets. */
- if (op->type == TILEGX_OP_TYPE_ADDRESS)
- opval = (raw_opval * TILEGX_BUNDLE_SIZE_IN_BYTES) + pc;
- else
- opval = raw_opval;
-
- /* Record the final value. */
- d->operands[i] = op;
- d->operand_values[i] = opval;
- }
- }
- decoded[num_instructions].opcode = NULL;
- return num_instructions;
-}
-
-tilegx_bundle_bits mkTileGxInsn ( Int opc, Int argc, ... )
-{
- struct tilegx_decoded_instruction decoded;
- decoded.opcode = &tilegx_opcodes[opc];
- Int i;
- va_list argv;
-
- if (decoded.opcode->num_operands != argc)
- return -1;
-
- if (opc > TILEGX_OPC_NONE) return 0;
-
- if (decoded.opcode->num_operands > 4)
- return -1;
-
- va_start(argv, argc);
- for (i = 0 ; i < decoded.opcode->num_operands; i++)
- {
- decoded.operands[i] = 0;
- decoded.operand_values[i] = va_arg(argv, ULong);
- }
- va_end(argv);
-
- return encode_insn_tilegx(decoded);
-}
-
-tilegx_bundle_bits
-encode_insn_tilegx ( struct tilegx_decoded_instruction decoded )
-{
- const struct tilegx_opcode *opc =
- decoded.opcode;
-
- tilegx_bundle_bits insn = 0;
- Int pipeX01 = (opc->pipes & 0x01) ? 0 : 1;
- Int op_num = opc->num_operands;
-
- /* Assume either X0 or X1. */
- if ((opc->pipes & 3) == 0)
- return -1;
-
- /* Insert fnop in other pipe. */
- insn = tilegx_opcodes[TILEGX_OPC_FNOP].
- fixed_bit_values[pipeX01 ? 0 : 1];
-
- insn |= opc->fixed_bit_values[pipeX01];
-
- Int i;
- /* loop for each operand. */
- for (i = 0 ; i < op_num; i++)
- {
- const struct tilegx_operand *opd =
- &tilegx_operands[opc->operands[pipeX01][i]];
- Long op = decoded.operand_values[i];
- decoded.operands[i] = opd;
- ULong x = opd->insert(op);
- insn |= x;
- }
-
- return insn;
-}
-
-/*---------------------------------------------------------------*/
-/*--- end tilegx_disasm.c ---*/
-/*---------------------------------------------------------------*/
diff --git a/VEX/priv/tilegx_disasm.h b/VEX/priv/tilegx_disasm.h
deleted file mode 100644
index 701e3c5..0000000
--- a/VEX/priv/tilegx_disasm.h
+++ /dev/null
@@ -1,1306 +0,0 @@
-
-/*---------------------------------------------------------------*/
-/*--- begin Tilegx disassembler tilegx-disasm.h ---*/
-/*---------------------------------------------------------------*/
-
-/*
- This file is part of Valgrind, a dynamic binary instrumentation
- framework.
-
- Copyright Tilera Corp. 2010-2013
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of the
- License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful, but
- WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- 02110-1301, USA.
-
- The GNU General Public License is contained in the file COPYING.
-*/
-
- /* Contributed by Zhi-Gang Liu <zliu at tilera dot com> */
-
-#ifndef __TILEGX_DISASM_H
-#define __TILEGX_DISASM_H
-
-#include "libvex_basictypes.h"
-
-typedef ULong tilegx_bundle_bits;
-
-/* These are the bits that determine if a bundle is in the X encoding. */
-#define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 << 62)
-
-enum
-{
- /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
- TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
-
- /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
- TILEGX_NUM_PIPELINE_ENCODINGS = 5,
-
- /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */
- TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
-
- /* Instructions take this many bytes. */
- TILEGX_BUNDLE_SIZE_IN_BYTES = 1 << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES,
-
- /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */
- TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
-
- /* Bundles should be aligned modulo this number of bytes. */
- TILEGX_BUNDLE_ALIGNMENT_IN_BYTES =
- (1 << TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
-
- /* Number of registers (some are magic, such as network I/O). */
- TILEGX_NUM_REGISTERS = 64,
-};
-
-/* Make a few "tile_" variables to simplify common code between
- architectures. */
-
-typedef tilegx_bundle_bits tile_bundle_bits;
-#define TILE_BUNDLE_SIZE_IN_BYTES TILEGX_BUNDLE_SIZE_IN_BYTES
-#define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES
-#define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \
- TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES
-
-/* 64-bit pattern for a { bpt ; nop } bundle. */
-#define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL
-
-static __inline UInt
-get_BFEnd_X0(tilegx_bundle_bits num)
-{
- const UInt n = (UInt)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline UInt
-get_BFOpcodeExtension_X0(tilegx_bundle_bits num)
-{
- const UInt n = (UInt)num;
- return (((n >> 24)) & 0xf);
-}
-
-static __inline UInt
-get_BFStart_X0(tilegx_bundle_bits num)
-{
- const UInt n = (UInt)num;
- return (((n >> 18)) & 0x3f);
-}
-
-static __inline UInt
-get_BrOff_X1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 31)) & 0x0000003f) |
- (((UInt)(n >> 37)) & 0x0001ffc0);
-}
-
-static __inline UInt
-get_BrType_X1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 54)) & 0x1f);
-}
-
-static __inline UInt
-get_Dest_Imm8_X1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 31)) & 0x0000003f) |
- (((UInt)(n >> 43)) & 0x000000c0);
-}
-
-static __inline UInt
-get_Dest_X0(tilegx_bundle_bits num)
-{
- const UInt n = (UInt)num;
- return (((n >> 0)) & 0x3f);
-}
-
-static __inline UInt
-get_Dest_X1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 31)) & 0x3f);
-}
-
-static __inline UInt
-get_Dest_Y0(tilegx_bundle_bits num)
-{
- const UInt n = (UInt)num;
- return (((n >> 0)) & 0x3f);
-}
-
-static __inline UInt
-get_Dest_Y1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 31)) & 0x3f);
-}
-
-static __inline UInt
-get_Imm16_X0(tilegx_bundle_bits num)
-{
- const UInt n = (UInt)num;
- return (((n >> 12)) & 0xffff);
-}
-
-static __inline UInt
-get_Imm16_X1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 43)) & 0xffff);
-}
-
-static __inline UInt
-get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)
-{
- const UInt n = (UInt)num;
- return (((n >> 20)) & 0xff);
-}
-
-static __inline UInt
-get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 51)) & 0xff);
-}
-
-static __inline UInt
-get_Imm8_X0(tilegx_bundle_bits num)
-{
- const UInt n = (UInt)num;
- return (((n >> 12)) & 0xff);
-}
-
-static __inline UInt
-get_Imm8_X1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 43)) & 0xff);
-}
-
-static __inline UInt
-get_Imm8_Y0(tilegx_bundle_bits num)
-{
- const UInt n = (UInt)num;
- return (((n >> 12)) & 0xff);
-}
-
-static __inline UInt
-get_Imm8_Y1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 43)) & 0xff);
-}
-
-static __inline UInt
-get_JumpOff_X1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 31)) & 0x7ffffff);
-}
-
-static __inline UInt
-get_JumpOpcodeExtension_X1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 58)) & 0x1);
-}
-
-static __inline UInt
-get_MF_Imm14_X1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 37)) & 0x3fff);
-}
-
-static __inline UInt
-get_MT_Imm14_X1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 31)) & 0x0000003f) |
- (((UInt)(n >> 37)) & 0x00003fc0);
-}
-
-static __inline UInt
-get_Mode(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 62)) & 0x3);
-}
-
-static __inline UInt
-get_Opcode_X0(tilegx_bundle_bits num)
-{
- const UInt n = (UInt)num;
- return (((n >> 28)) & 0x7);
-}
-
-static __inline UInt
-get_Opcode_X1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 59)) & 0x7);
-}
-
-static __inline UInt
-get_Opcode_Y0(tilegx_bundle_bits num)
-{
- const UInt n = (UInt)num;
- return (((n >> 27)) & 0xf);
-}
-
-static __inline UInt
-get_Opcode_Y1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 58)) & 0xf);
-}
-
-static __inline UInt
-get_Opcode_Y2(tilegx_bundle_bits n)
-{
- return (((n >> 26)) & 0x00000001) |
- (((UInt)(n >> 56)) & 0x00000002);
-}
-
-static __inline UInt
-get_RRROpcodeExtension_X0(tilegx_bundle_bits num)
-{
- const UInt n = (UInt)num;
- return (((n >> 18)) & 0x3ff);
-}
-
-static __inline UInt
-get_RRROpcodeExtension_X1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 49)) & 0x3ff);
-}
-
-static __inline UInt
-get_RRROpcodeExtension_Y0(tilegx_bundle_bits num)
-{
- const UInt n = (UInt)num;
- return (((n >> 18)) & 0x3);
-}
-
-static __inline UInt
-get_RRROpcodeExtension_Y1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 49)) & 0x3);
-}
-
-static __inline UInt
-get_ShAmt_X0(tilegx_bundle_bits num)
-{
- const UInt n = (UInt)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline UInt
-get_ShAmt_X1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 43)) & 0x3f);
-}
-
-static __inline UInt
-get_ShAmt_Y0(tilegx_bundle_bits num)
-{
- const UInt n = (UInt)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline UInt
-get_ShAmt_Y1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 43)) & 0x3f);
-}
-
-static __inline UInt
-get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num)
-{
- const UInt n = (UInt)num;
- return (((n >> 18)) & 0x3ff);
-}
-
-static __inline UInt
-get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 49)) & 0x3ff);
-}
-
-static __inline UInt
-get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num)
-{
- const UInt n = (UInt)num;
- return (((n >> 18)) & 0x3);
-}
-
-static __inline UInt
-get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 49)) & 0x3);
-}
-
-static __inline UInt
-get_SrcA_X0(tilegx_bundle_bits num)
-{
- const UInt n = (UInt)num;
- return (((n >> 6)) & 0x3f);
-}
-
-static __inline UInt
-get_SrcA_X1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 37)) & 0x3f);
-}
-
-static __inline UInt
-get_SrcA_Y0(tilegx_bundle_bits num)
-{
- const UInt n = (UInt)num;
- return (((n >> 6)) & 0x3f);
-}
-
-static __inline UInt
-get_SrcA_Y1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 37)) & 0x3f);
-}
-
-static __inline UInt
-get_SrcA_Y2(tilegx_bundle_bits num)
-{
- const UInt n = (UInt)num;
- return (((n >> 20)) & 0x3f);
-}
-
-static __inline UInt
-get_SrcBDest_Y2(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 51)) & 0x3f);
-}
-
-static __inline UInt
-get_SrcB_X0(tilegx_bundle_bits num)
-{
- const UInt n = (UInt)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline UInt
-get_SrcB_X1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 43)) & 0x3f);
-}
-
-static __inline UInt
-get_SrcB_Y0(tilegx_bundle_bits num)
-{
- const UInt n = (UInt)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline UInt
-get_SrcB_Y1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 43)) & 0x3f);
-}
-
-static __inline UInt
-get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num)
-{
- const UInt n = (UInt)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline UInt
-get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 43)) & 0x3f);
-}
-
-static __inline UInt
-get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num)
-{
- const UInt n = (UInt)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline UInt
-get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n)
-{
- return (((UInt)(n >> 43)) & 0x3f);
-}
-
-
-static __inline int
-sign_extend(int n, int num_bits)
-{
- int shift = (int)(sizeof(int) * 8 - num_bits);
- return (n << shift) >> shift;
-}
-
-
-
-static __inline tilegx_bundle_bits
-create_BFEnd_X0(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_BFOpcodeExtension_X0(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0xf) << 24);
-}
-
-static __inline tilegx_bundle_bits
-create_BFStart_X0(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0x3f) << 18);
-}
-
-static __inline tilegx_bundle_bits
-create_BrOff_X1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
- (((tilegx_bundle_bits)(n & 0x0001ffc0)) << 37);
-}
-
-static __inline tilegx_bundle_bits
-create_BrType_X1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0x1f)) << 54);
-}
-
-static __inline tilegx_bundle_bits
-create_Dest_Imm8_X1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
- (((tilegx_bundle_bits)(n & 0x000000c0)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_Dest_X0(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0x3f) << 0);
-}
-
-static __inline tilegx_bundle_bits
-create_Dest_X1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
-}
-
-static __inline tilegx_bundle_bits
-create_Dest_Y0(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0x3f) << 0);
-}
-
-static __inline tilegx_bundle_bits
-create_Dest_Y1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
-}
-
-static __inline tilegx_bundle_bits
-create_Imm16_X0(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0xffff) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_Imm16_X1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0xffff)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_Imm8OpcodeExtension_X0(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0xff) << 20);
-}
-
-static __inline tilegx_bundle_bits
-create_Imm8OpcodeExtension_X1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0xff)) << 51);
-}
-
-static __inline tilegx_bundle_bits
-create_Imm8_X0(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0xff) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_Imm8_X1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0xff)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_Imm8_Y0(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0xff) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_Imm8_Y1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0xff)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_JumpOff_X1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0x7ffffff)) << 31);
-}
-
-static __inline tilegx_bundle_bits
-create_JumpOpcodeExtension_X1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0x1)) << 58);
-}
-
-static __inline tilegx_bundle_bits
-create_MF_Imm14_X1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0x3fff)) << 37);
-}
-
-static __inline tilegx_bundle_bits
-create_MT_Imm14_X1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
- (((tilegx_bundle_bits)(n & 0x00003fc0)) << 37);
-}
-
-static __inline tilegx_bundle_bits
-create_Mode(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0x3)) << 62);
-}
-
-static __inline tilegx_bundle_bits
-create_Opcode_X0(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0x7) << 28);
-}
-
-static __inline tilegx_bundle_bits
-create_Opcode_X1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0x7)) << 59);
-}
-
-static __inline tilegx_bundle_bits
-create_Opcode_Y0(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0xf) << 27);
-}
-
-static __inline tilegx_bundle_bits
-create_Opcode_Y1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0xf)) << 58);
-}
-
-static __inline tilegx_bundle_bits
-create_Opcode_Y2(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0x00000001) << 26) |
- (((tilegx_bundle_bits)(n & 0x00000002)) << 56);
-}
-
-static __inline tilegx_bundle_bits
-create_RRROpcodeExtension_X0(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0x3ff) << 18);
-}
-
-static __inline tilegx_bundle_bits
-create_RRROpcodeExtension_X1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
-}
-
-static __inline tilegx_bundle_bits
-create_RRROpcodeExtension_Y0(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0x3) << 18);
-}
-
-static __inline tilegx_bundle_bits
-create_RRROpcodeExtension_Y1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0x3)) << 49);
-}
-
-static __inline tilegx_bundle_bits
-create_ShAmt_X0(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_ShAmt_X1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_ShAmt_Y0(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_ShAmt_Y1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_ShiftOpcodeExtension_X0(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0x3ff) << 18);
-}
-
-static __inline tilegx_bundle_bits
-create_ShiftOpcodeExtension_X1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
-}
-
-static __inline tilegx_bundle_bits
-create_ShiftOpcodeExtension_Y0(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0x3) << 18);
-}
-
-static __inline tilegx_bundle_bits
-create_ShiftOpcodeExtension_Y1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0x3)) << 49);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcA_X0(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0x3f) << 6);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcA_X1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcA_Y0(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0x3f) << 6);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcA_Y1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcA_Y2(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0x3f) << 20);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcBDest_Y2(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 51);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcB_X0(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcB_X1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcB_Y0(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcB_Y1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_UnaryOpcodeExtension_X0(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_UnaryOpcodeExtension_X1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_UnaryOpcodeExtension_Y0(int num)
-{
- const UInt n = (UInt)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_UnaryOpcodeExtension_Y1(int num)
-{
- const UInt n = (UInt)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
-}
-
-enum
-{
- TILEGX_MAX_OPERANDS = 4 /* bfexts */
-};
-
-typedef enum
-{
- TILEGX_OPC_BPT,
- TILEGX_OPC_INFO,
- TILEGX_OPC_INFOL,
- TILEGX_OPC_LD4S_TLS,
- TILEGX_OPC_LD_TLS,
- TILEGX_OPC_MOVE,
- TILEGX_OPC_MOVEI,
- TILEGX_OPC_MOVELI,
- TILEGX_OPC_PREFETCH,
- TILEGX_OPC_PREFETCH_ADD_L1,
- TILEGX_OPC_PREFETCH_ADD_L1_FAULT,
- TILEGX_OPC_PREFETCH_ADD_L2,
- TILEGX_OPC_PREFETCH_ADD_L2_FAULT,
- TILEGX_OPC_PREFETCH_ADD_L3,
- TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
- TILEGX_OPC_PREFETCH_L1,
- TILEGX_OPC_PREFETCH_L1_FAULT,
- TILEGX_OPC_PREFETCH_L2,
- TILEGX_OPC_PREFETCH_L2_FAULT,
- TILEGX_OPC_PREFETCH_L3,
- TILEGX_OPC_PREFETCH_L3_FAULT,
- TILEGX_OPC_RAISE,
- TILEGX_OPC_ADD,
- TILEGX_OPC_ADDI,
- TILEGX_OPC_ADDLI,
- TILEGX_OPC_ADDX,
- TILEGX_OPC_ADDXI,
- TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXSC,
- TILEGX_OPC_AND,
- TILEGX_OPC_ANDI,
- TILEGX_OPC_BEQZ,
- TILEGX_OPC_BEQZT,
- TILEGX_OPC_BFEXTS,
- TILEGX_OPC_BFEXTU,
- TILEGX_OPC_BFINS,
- TILEGX_OPC_BGEZ,
- TILEGX_OPC_BGEZT,
- TILEGX_OPC_BGTZ,
- TILEGX_OPC_BGTZT,
- TILEGX_OPC_BLBC,
- TILEGX_OPC_BLBCT,
- TILEGX_OPC_BLBS,
- TILEGX_OPC_BLBST,
- TILEGX_OPC_BLEZ,
- TILEGX_OPC_BLEZT,
- TILEGX_OPC_BLTZ,
- TILEGX_OPC_BLTZT,
- TILEGX_OPC_BNEZ,
- TILEGX_OPC_BNEZT,
- TILEGX_OPC_CLZ,
- TILEGX_OPC_CMOVEQZ,
- TILEGX_OPC_CMOVNEZ,
- TILEGX_OPC_CMPEQ,
- TILEGX_OPC_CMPEQI,
- TILEGX_OPC_CMPEXCH,
- TILEGX_OPC_CMPEXCH4,
- TILEGX_OPC_CMPLES,
- TILEGX_OPC_CMPLEU,
- TILEGX_OPC_CMPLTS,
- TILEGX_OPC_CMPLTSI,
- TILEGX_OPC_CMPLTU,
- TILEGX_OPC_CMPLTUI,
- TILEGX_OPC_CMPNE,
- TILEGX_OPC_CMUL,
- TILEGX_OPC_CMULA,
- TILEGX_OPC_CMULAF,
- TILEGX_OPC_CMULF,
- TILEGX_OPC_CMULFR,
- TILEGX_OPC_CMULH,
- TILEGX_OPC_CMULHR,
- TILEGX_OPC_CRC32_32,
- TILEGX_OPC_CRC32_8,
- TILEGX_OPC_CTZ,
- TILEGX_OPC_DBLALIGN,
- TILEGX_OPC_DBLALIGN2,
- TILEGX_OPC_DBLALIGN4,
- TILEGX_OPC_DBLALIGN6,
- TILEGX_OPC_DRAIN,
- TILEGX_OPC_DTLBPR,
- TILEGX_OPC_EXCH,
- TILEGX_OPC_EXCH4,
- TILEGX_OPC_FDOUBLE_ADD_FLAGS,
- TILEGX_OPC_FDOUBLE_ADDSUB,
- TILEGX_OPC_FDOUBLE_MUL_FLAGS,
- TILEGX_OPC_FDOUBLE_PACK1,
- TILEGX_OPC_FDOUBLE_PACK2,
- TILEGX_OPC_FDOUBLE_SUB_FLAGS,
- TILEGX_OPC_FDOUBLE_UNPACK_MAX,
- TILEGX_OPC_FDOUBLE_UNPACK_MIN,
- TILEGX_OPC_FETCHADD,
- TILEGX_OPC_FETCHADD4,
- TILEGX_OPC_FETCHADDGEZ,
- TILEGX_OPC_FETCHADDGEZ4,
- TILEGX_OPC_FETCHAND,
- TILEGX_OPC_FETCHAND4,
- TILEGX_OPC_FETCHOR,
- TILEGX_OPC_FETCHOR4,
- TILEGX_OPC_FINV,
- TILEGX_OPC_FLUSH,
- TILEGX_OPC_FLUSHWB,
- TILEGX_OPC_FNOP,
- TILEGX_OPC_FSINGLE_ADD1,
- TILEGX_OPC_FSINGLE_ADDSUB2,
- TILEGX_OPC_FSINGLE_MUL1,
- TILEGX_OPC_FSINGLE_MUL2,
- TILEGX_OPC_FSINGLE_PACK1,
- TILEGX_OPC_FSINGLE_PACK2,
- TILEGX_OPC_FSINGLE_SUB1,
- TILEGX_OPC_ICOH,
- TILEGX_OPC_ILL,
- TILEGX_OPC_INV,
- TILEGX_OPC_IRET,
- TILEGX_OPC_J,
- TILEGX_OPC_JAL,
- TILEGX_OPC_JALR,
- TILEGX_OPC_JALRP,
- TILEGX_OPC_JR,
- TILEGX_OPC_JRP,
- TILEGX_OPC_LD,
- TILEGX_OPC_LD1S,
- TILEGX_OPC_LD1S_ADD,
- TILEGX_OPC_LD1U,
- TILEGX_OPC_LD1U_ADD,
- TILEGX_OPC_LD2S,
- TILEGX_OPC_LD2S_ADD,
- TILEGX_OPC_LD2U,
- TILEGX_OPC_LD2U_ADD,
- TILEGX_OPC_LD4S,
- TILEGX_OPC_LD4S_ADD,
- TILEGX_OPC_LD4U,
- TILEGX_OPC_LD4U_ADD,
- TILEGX_OPC_LD_ADD,
- TILEGX_OPC_LDNA,
- TILEGX_OPC_LDNA_ADD,
- TILEGX_OPC_LDNT,
- TILEGX_OPC_LDNT1S,
- TILEGX_OPC_LDNT1S_ADD,
- TILEGX_OPC_LDNT1U,
- TILEGX_OPC_LDNT1U_ADD,
- TILEGX_OPC_LDNT2S,
- TILEGX_OPC_LDNT2S_ADD,
- TILEGX_OPC_LDNT2U,
- TILEGX_OPC_LDNT2U_ADD,
- TILEGX_OPC_LDNT4S,
- TILEGX_OPC_LDNT4S_ADD,
- TILEGX_OPC_LDNT4U,
- TILEGX_OPC_LDNT4U_ADD,
- TILEGX_OPC_LDNT_ADD,
- TILEGX_OPC_LNK,
- TILEGX_OPC_MF,
- TILEGX_OPC_MFSPR,
- TILEGX_OPC_MM,
- TILEGX_OPC_MNZ,
- TILEGX_OPC_MTSPR,
- TILEGX_OPC_MUL_HS_HS,
- TILEGX_OPC_MUL_HS_HU,
- TILEGX_OPC_MUL_HS_LS,
- TILEGX_OPC_MUL_HS_LU,
- TILEGX_OPC_MUL_HU_HU,
- TILEGX_OPC_MUL_HU_LS,
- TILEGX_OPC_MUL_HU_LU,
- TILEGX_OPC_MUL_LS_LS,
- TILEGX_OPC_MUL_LS_LU,
- TILEGX_OPC_MUL_LU_LU,
- TILEGX_OPC_MULA_HS_HS,
- TILEGX_OPC_MULA_HS_HU,
- TILEGX_OPC_MULA_HS_LS,
- TILEGX_OPC_MULA_HS_LU,
- TILEGX_OPC_MULA_HU_HU,
- TILEGX_OPC_MULA_HU_LS,
- TILEGX_OPC_MULA_HU_LU,
- TILEGX_OPC_MULA_LS_LS,
- TILEGX_OPC_MULA_LS_LU,
- TILEGX_OPC_MULA_LU_LU,
- TILEGX_OPC_MULAX,
- TILEGX_OPC_MULX,
- TILEGX_OPC_MZ,
- TILEGX_OPC_NAP,
- TILEGX_OPC_NOP,
- TILEGX_OPC_NOR,
- TILEGX_OPC_OR,
- TILEGX_OPC_ORI,
- TILEGX_OPC_PCNT,
- TILEGX_OPC_REVBITS,
- TILEGX_OPC_REVBYTES,
- TILEGX_OPC_ROTL,
- TILEGX_OPC_ROTLI,
- TILEGX_OPC_SHL,
- TILEGX_OPC_SHL16INSLI,
- TILEGX_OPC_SHL1ADD,
- TILEGX_OPC_SHL1ADDX,
- TILEGX_OPC_SHL2ADD,
- TILEGX_OPC_SHL2ADDX,
- TILEGX_OPC_SHL3ADD,
- TILEGX_OPC_SHL3ADDX,
- TILEGX_OPC_SHLI,
- TILEGX_OPC_SHLX,
- TILEGX_OPC_SHLXI,
- TILEGX_OPC_SHRS,
- TILEGX_OPC_SHRSI,
- TILEGX_OPC_SHRU,
- TILEGX_OPC_SHRUI,
- TILEGX_OPC_SHRUX,
- TILEGX_OPC_SHRUXI,
- TILEGX_OPC_SHUFFLEBYTES,
- TILEGX_OPC_ST,
- TILEGX_OPC_ST1,
- TILEGX_OPC_ST1_ADD,
- TILEGX_OPC_ST2,
- TILEGX_OPC_ST2_ADD,
- TILEGX_OPC_ST4,
- TILEGX_OPC_ST4_ADD,
- TILEGX_OPC_ST_ADD,
- TILEGX_OPC_STNT,
- TILEGX_OPC_STNT1,
- TILEGX_OPC_STNT1_ADD,
- TILEGX_OPC_STNT2,
- TILEGX_OPC_STNT2_ADD,
- TILEGX_OPC_STNT4,
- TILEGX_OPC_STNT4_ADD,
- TILEGX_OPC_STNT_ADD,
- TILEGX_OPC_SUB,
- TILEGX_OPC_SUBX,
- TILEGX_OPC_SUBXSC,
- TILEGX_OPC_SWINT0,
- TILEGX_OPC_SWINT1,
- TILEGX_OPC_SWINT2,
- TILEGX_OPC_SWINT3,
- TILEGX_OPC_TBLIDXB0,
- TILEGX_OPC_TBLIDXB1,
- TILEGX_OPC_TBLIDXB2,
- TILEGX_OPC_TBLIDXB3,
- TILEGX_OPC_V1ADD,
- TILEGX_OPC_V1ADDI,
- TILEGX_OPC_V1ADDUC,
- TILEGX_OPC_V1ADIFFU,
- TILEGX_OPC_V1AVGU,
- TILEGX_OPC_V1CMPEQ,
- TILEGX_OPC_V1CMPEQI,
- TILEGX_OPC_V1CMPLES,
- TILEGX_OPC_V1CMPLEU,
- TILEGX_OPC_V1CMPLTS,
- TILEGX_OPC_V1CMPLTSI,
- TILEGX_OPC_V1CMPLTU,
- TILEGX_OPC_V1CMPLTUI,
- TILEGX_OPC_V1CMPNE,
- TILEGX_OPC_V1DDOTPU,
- TILEGX_OPC_V1DDOTPUA,
- TILEGX_OPC_V1DDOTPUS,
- TILEGX_OPC_V1DDOTPUSA,
- TILEGX_OPC_V1DOTP,
- TILEGX_OPC_V1DOTPA,
- TILEGX_OPC_V1DOTPU,
- TILEGX_OPC_V1DOTPUA,
- TILEGX_OPC_V1DOTPUS,
- TILEGX_OPC_V1DOTPUSA,
- TILEGX_OPC_V1INT_H,
- TILEGX_OPC_V1INT_L,
- TILEGX_OPC_V1MAXU,
- TILEGX_OPC_V1MAXUI,
- TILEGX_OPC_V1MINU,
- TILEGX_OPC_V1MINUI,
- TILEGX_OPC_V1MNZ,
- TILEGX_OPC_V1MULTU,
- TILEGX_OPC_V1MULU,
- TILEGX_OPC_V1MULUS,
- TILEGX_OPC_V1MZ,
- TILEGX_OPC_V1SADAU,
- TILEGX_OPC_V1SADU,
- TILEGX_OPC_V1SHL,
- TILEGX_OPC_V1SHLI,
- TILEGX_OPC_V1SHRS,
- TILEGX_OPC_V1SHRSI,
- TILEGX_OPC_V1SHRU,
- TILEGX_OPC_V1SHRUI,
- TILEGX_OPC_V1SUB,
- TILEGX_OPC_V1SUBUC,
- TILEGX_OPC_V2ADD,
- TILEGX_OPC_V2ADDI,
- TILEGX_OPC_V2ADDSC,
- TILEGX_OPC_V2ADIFFS,
- TILEGX_OPC_V2AVGS,
- TILEGX_OPC_V2CMPEQ,
- TILEGX_OPC_V2CMPEQI,
- TILEGX_OPC_V2CMPLES,
- TILEGX_OPC_V2CMPLEU,
- TILEGX_OPC_V2CMPLTS,
- TILEGX_OPC_V2CMPLTSI,
- TILEGX_OPC_V2CMPLTU,
- TILEGX_OPC_V2CMPLTUI,
- TILEGX_OPC_V2CMPNE,
- TILEGX_OPC_V2DOTP,
- TILEGX_OPC_V2DOTPA,
- TILEGX_OPC_V2INT_H,
- TILEGX_OPC_V2INT_L,
- TILEGX_OPC_V2MAXS,
- TILEGX_OPC_V2MAXSI,
- TILEGX_OPC_V2MINS,
- TILEGX_OPC_V2MINSI,
- TILEGX_OPC_V2MNZ,
- TILEGX_OPC_V2MULFSC,
- TILEGX_OPC_V2MULS,
- TILEGX_OPC_V2MULTS,
- TILEGX_OPC_V2MZ,
- TILEGX_OPC_V2PACKH,
- TILEGX_OPC_V2PACKL,
- TILEGX_OPC_V2PACKUC,
- TILEGX_OPC_V2SADAS,
- TILEGX_OPC_V2SADAU,
- TILEGX_OPC_V2SADS,
- TILEGX_OPC_V2SADU,
- TILEGX_OPC_V2SHL,
- TILEGX_OPC_V2SHLI,
- TILEGX_OPC_V2SHLSC,
- TILEGX_OPC_V2SHRS,
- TILEGX_OPC_V2SHRSI,
- TILEGX_OPC_V2SHRU,
- TILEGX_OPC_V2SHRUI,
- TILEGX_OPC_V2SUB,
- TILEGX_OPC_V2SUBSC,
- TILEGX_OPC_V4ADD,
- TILEGX_OPC_V4ADDSC,
- TILEGX_OPC_V4INT_H,
- TILEGX_OPC_V4INT_L,
- TILEGX_OPC_V4PACKSC,
- TILEGX_OPC_V4SHL,
- TILEGX_OPC_V4SHLSC,
- TILEGX_OPC_V4SHRS,
- TILEGX_OPC_V4SHRU,
- TILEGX_OPC_V4SUB,
- TILEGX_OPC_V4SUBSC,
- TILEGX_OPC_WH64,
- TILEGX_OPC_XOR,
- TILEGX_OPC_XORI,
- TILEGX_OPC_NONE
-} tilegx_mnemonic;
-
-
-
-typedef enum
-{
- TILEGX_PIPELINE_X0,
- TILEGX_PIPELINE_X1,
- TILEGX_PIPELINE_Y0,
- TILEGX_PIPELINE_Y1,
- TILEGX_PIPELINE_Y2,
-} tilegx_pipeline;
-
-#define tilegx_is_x_pipeline(p) ((Int)(p) <= (Int)TILEGX_PIPELINE_X1)
-
-typedef enum
-{
- TILEGX_OP_TYPE_REGISTER,
- TILEGX_OP_TYPE_IMMEDIATE,
- TILEGX_OP_TYPE_ADDRESS,
- TILEGX_OP_TYPE_SPR
-} tilegx_operand_type;
-
-struct tilegx_operand
-{
- /* Is this operand a register, immediate or address? */
- tilegx_operand_type type;
-
- /* The default relocation type for this operand. */
- Int default_reloc : 16;
-
- /* How many bits is this value? (used for range checking) */
- UInt num_bits : 5;
-
- /* Is the value signed? (used for range checking) */
- UInt is_signed : 1;
-
- /* Is this operand a source register? */
- UInt is_src_reg : 1;
-
- /* Is this operand written? (i.e. is it a destination register) */
- UInt is_dest_reg : 1;
-
- /* Is this operand PC-relative? */
- UInt is_pc_relative : 1;
-
- /* By how many bits do we right shift the value before inserting? */
- UInt rightshift : 2;
-
- /* Return the bits for this operand to be ORed into an existing bundle. */
- tilegx_bundle_bits (*insert) (int op);
-
- /* Extract this operand and return it. */
- UInt (*extract) (tilegx_bundle_bits bundle);
-};
-
-
-extern const struct tilegx_operand tilegx_operands[];
-
-/* One finite-state machine per pipe for rapid instruction decoding. */
-extern const unsigned short * const
-tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS];
-
-
-struct tilegx_opcode
-{
- /* The opcode mnemonic, e.g. "add" */
- const char *name;
-
- /* The enum value for this mnemonic. */
- tilegx_mnemonic mnemonic;
-
- /* A bit mask of which of the five pipes this instruction
- is compatible with:
- X0 0x01
- X1 0x02
- Y0 0x04
- Y1 0x08
- Y2 0x10 */
- unsigned char pipes;
-
- /* How many operands are there? */
- unsigned char num_operands;
-
- /* Which register does this write implicitly, or TREG_ZERO if none? */
- unsigned char implicitly_written_register;
-
- /* Can this be bundled with other instructions (almost always true). */
- unsigned char can_bundle;
-
- /* The description of the operands. Each of these is an
- * index into the tilegx_operands[] table. */
- unsigned char operands[TILEGX_NUM_PIPELINE_ENCODINGS][TILEGX_MAX_OPERANDS];
-
- /* A mask of which bits have predefined values for each pipeline.
- * This is useful for disassembly. */
- tilegx_bundle_bits fixed_bit_masks[TILEGX_NUM_PIPELINE_ENCODINGS];
-
- /* For each bit set in fixed_bit_masks, what the value is for this
- * instruction. */
- tilegx_bundle_bits fixed_bit_values[TILEGX_NUM_PIPELINE_ENCODINGS];
-};
-
-extern const struct tilegx_opcode tilegx_opcodes[];
-
-/* Used for non-textual disassembly into structs. */
-struct tilegx_decoded_instruction
-{
- const struct tilegx_opcode *opcode;
- const struct tilegx_operand *operands[TILEGX_MAX_OPERANDS];
- Long operand_values[TILEGX_MAX_OPERANDS];
-};
-
-
-/* Disassemble a bundle into a struct for machine processing. */
-extern Int parse_insn_tilegx ( tilegx_bundle_bits bits,
- ULong pc,
- struct tilegx_decoded_instruction
- decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE] );
-
-extern Int decode_and_display ( tilegx_bundle_bits *p, Int count, ULong pc );
-
-extern tilegx_bundle_bits
-encode_insn_tilegx ( struct tilegx_decoded_instruction decoded );
-
-
-extern tilegx_bundle_bits
-mkTileGxInsn ( Int opc, Int argc, ... );
-
-/* Given a set of bundle bits and a specific pipe, returns which
- * instruction the bundle contains in that pipe.
- */
-extern const struct tilegx_opcode *
-find_opcode ( tilegx_bundle_bits bits, tilegx_pipeline pipe );
-
-
-#endif /* __TILEGX_DISASM_H */
-
-/*---------------------------------------------------------------*/
-/*--- end tilegx-disasm.h ---*/
-/*---------------------------------------------------------------*/
diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h
index 855bc64..d75919d 100644
--- a/VEX/pub/libvex.h
+++ b/VEX/pub/libvex.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -60,8 +60,7 @@
VexArchPPC64,
VexArchS390X,
VexArchMIPS32,
- VexArchMIPS64,
- VexArchTILEGX
+ VexArchMIPS64
}
VexArch;
@@ -177,9 +176,6 @@
#define VEX_HWCAPS_S390X(x) ((x) & ~VEX_S390X_MODEL_MASK)
#define VEX_S390X_MODEL(x) ((x) & VEX_S390X_MODEL_MASK)
-/* Tilegx: baseline capability is TILEGX36 */
-#define VEX_HWCAPS_TILEGX_BASE (1<<16) /* TILEGX Baseline */
-
/* arm: baseline capability is ARMv4 */
/* Bits 5:0 - architecture level (e.g. 5 for v5, 6 for v6 etc) */
#define VEX_HWCAPS_ARM_VFP (1<<6) /* VFP extension */
@@ -327,6 +323,9 @@
line size of 64 bytes would be encoded here as 6. */
UInt arm64_dMinLine_lg2_szB;
UInt arm64_iMinLine_lg2_szB;
+ /* ARM64: does the host require us to use the fallback LLSC
+ implementation? */
+ Bool arm64_requires_fallback_LLSC;
}
VexArchInfo;
@@ -369,6 +368,11 @@
guest is ppc32-linux ==> const False
guest is other ==> inapplicable
+ guest__use_fallback_LLSC
+ guest is mips32 ==> applicable, default True
+ guest is mips64 ==> applicable, default True
+ guest is arm64 ==> applicable, default False
+
host_ppc_calls_use_fndescrs:
host is ppc32-linux ==> False
host is ppc64-linux ==> True
@@ -401,11 +405,17 @@
is assumed equivalent to a fn which always returns False. */
Bool (*guest_ppc_zap_RZ_at_bl)(Addr);
+ /* Potentially for all guests that use LL/SC: use the fallback
+ (synthesised) implementation rather than passing LL/SC on to
+ the host? */
+ Bool guest__use_fallback_LLSC;
+
/* PPC32/PPC64 HOSTS only: does '&f' give us a pointer to a
function descriptor on the host, or to the function code
itself? True => descriptor, False => code. */
Bool host_ppc_calls_use_fndescrs;
+ /* ??? Description ??? */
Bool guest_mips_fp_mode64;
}
VexAbiInfo;
@@ -475,7 +485,7 @@
Default=120. A setting of zero disables unrolling. */
Int iropt_unroll_thresh;
/* What's the maximum basic block length the front end(s) allow?
- BBs longer than this are split up. Default=50 (guest
+ BBs longer than this are split up. Default=60 (guest
insns). */
Int guest_max_insns;
/* How aggressive should front ends be in following
@@ -776,8 +786,17 @@
VexTranslateArgs;
+/* Runs the entire compilation pipeline. */
extern
-VexTranslateResult LibVEX_Translate ( VexTranslateArgs* );
+VexTranslateResult LibVEX_Translate ( /*MOD*/ VexTranslateArgs* );
+
+/* Runs the first half of the compilation pipeline: lifts guest code to IR,
+ optimises, instruments and optimises it some more. */
+extern
+IRSB* LibVEX_FrontEnd ( /*MOD*/ VexTranslateArgs*,
+ /*OUT*/ VexTranslateResult* res,
+ /*OUT*/ VexRegisterUpdates* pxControl );
+
/* A subtlety re interaction between self-checking translations and
bb-chasing. The supplied chase_into_ok function should say NO
diff --git a/VEX/pub/libvex_basictypes.h b/VEX/pub/libvex_basictypes.h
index b1d0f6c..86df444 100644
--- a/VEX/pub/libvex_basictypes.h
+++ b/VEX/pub/libvex_basictypes.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -183,10 +183,6 @@
# define VEX_HOST_WORDSIZE 4
# define VEX_REGPARM(_n) /* */
-#elif defined(__tilegx__)
-# define VEX_HOST_WORDSIZE 8
-# define VEX_REGPARM(_n) /* */
-
#else
# error "Vex: Fatal: Can't establish the host architecture"
#endif
diff --git a/VEX/pub/libvex_emnote.h b/VEX/pub/libvex_emnote.h
index 9435130..e597790 100644
--- a/VEX/pub/libvex_emnote.h
+++ b/VEX/pub/libvex_emnote.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/VEX/pub/libvex_guest_amd64.h b/VEX/pub/libvex_guest_amd64.h
index fd104ab..7db7cbc 100644
--- a/VEX/pub/libvex_guest_amd64.h
+++ b/VEX/pub/libvex_guest_amd64.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/VEX/pub/libvex_guest_arm.h b/VEX/pub/libvex_guest_arm.h
index f446262..029441f 100644
--- a/VEX/pub/libvex_guest_arm.h
+++ b/VEX/pub/libvex_guest_arm.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/VEX/pub/libvex_guest_arm64.h b/VEX/pub/libvex_guest_arm64.h
index c438c1e..bf1573d 100644
--- a/VEX/pub/libvex_guest_arm64.h
+++ b/VEX/pub/libvex_guest_arm64.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2013-2015 OpenWorks
+ Copyright (C) 2013-2017 OpenWorks
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -159,9 +159,14 @@
note of bits 23 and 22. */
UInt guest_FPCR;
+ /* Fallback LL/SC support. See bugs 344524 and 369459. */
+ ULong guest_LLSC_SIZE; // 0==no current transaction, else 1,2,4 or 8.
+ ULong guest_LLSC_ADDR; // Address of transaction.
+ ULong guest_LLSC_DATA; // Original value at _ADDR, zero-extended.
+
/* Padding to make it have an 16-aligned size */
/* UInt pad_end_0; */
- /* ULong pad_end_1; */
+ ULong pad_end_1;
}
VexGuestARM64State;
diff --git a/VEX/pub/libvex_guest_mips32.h b/VEX/pub/libvex_guest_mips32.h
index 8351f0e..0ac8d30 100644
--- a/VEX/pub/libvex_guest_mips32.h
+++ b/VEX/pub/libvex_guest_mips32.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 RT-RK
+ Copyright (C) 2010-2017 RT-RK
mips-valgrind@rt-rk.com
This program is free software; you can redistribute it and/or
@@ -40,82 +40,86 @@
typedef
struct {
+ /* 0 */ UInt host_EvC_FAILADDR;
+ /* 4 */ UInt host_EvC_COUNTER;
+
/* CPU Registers */
- /* 0 */ UInt guest_r0; /* Hardwired to 0 */
- /* 4 */ UInt guest_r1; /* Assembler temporary */
- /* 8 */ UInt guest_r2; /* Values for function returns ...*/
- /* 12 */ UInt guest_r3; /* ...and expression evaluation */
- /* 16 */ UInt guest_r4; /* Function arguments */
- /* 20 */ UInt guest_r5;
- /* 24 */ UInt guest_r6;
- /* 28 */ UInt guest_r7;
- /* 32 */ UInt guest_r8; /* Temporaries */
- /* 36 */ UInt guest_r9;
- /* 40 */ UInt guest_r10;
- /* 44 */ UInt guest_r11;
- /* 48 */ UInt guest_r12;
- /* 52 */ UInt guest_r13;
- /* 56 */ UInt guest_r14;
- /* 60 */ UInt guest_r15;
- /* 64 */ UInt guest_r16; /* Saved temporaries */
- /* 68 */ UInt guest_r17;
- /* 72 */ UInt guest_r18;
- /* 76 */ UInt guest_r19;
- /* 80 */ UInt guest_r20;
- /* 84 */ UInt guest_r21;
- /* 88 */ UInt guest_r22;
- /* 92 */ UInt guest_r23;
- /* 96 */ UInt guest_r24; /* Temporaries */
- /* 100 */ UInt guest_r25;
- /* 104 */ UInt guest_r26; /* Reserved for OS kernel */
- /* 108 */ UInt guest_r27;
- /* 112 */ UInt guest_r28; /* Global pointer */
- /* 116 */ UInt guest_r29; /* Stack pointer */
- /* 120 */ UInt guest_r30; /* Frame pointer */
- /* 124 */ UInt guest_r31; /* Return address */
- /* 128 */ UInt guest_PC; /* Program counter */
- /* 132 */ UInt guest_HI; /* Multiply and divide register higher result */
- /* 136 */ UInt guest_LO; /* Multiply and divide register lower result */
+ /* 8 */ UInt guest_r0; /* Hardwired to 0. */
+ /* 12 */ UInt guest_r1; /* Assembler temporary */
+ /* 16 */ UInt guest_r2; /* Values for function returns ...*/
+ /* 20 */ UInt guest_r3; /* ... and expression evaluation */
+ /* 24 */ UInt guest_r4; /* Function arguments */
+ /* 28 */ UInt guest_r5;
+ /* 32 */ UInt guest_r6;
+ /* 36 */ UInt guest_r7;
+ /* 40 */ UInt guest_r8; /* Temporaries */
+ /* 44 */ UInt guest_r9;
+ /* 48 */ UInt guest_r10;
+ /* 52 */ UInt guest_r11;
+ /* 56 */ UInt guest_r12;
+ /* 60 */ UInt guest_r13;
+ /* 64 */ UInt guest_r14;
+ /* 68 */ UInt guest_r15;
+ /* 72 */ UInt guest_r16; /* Saved temporaries */
+ /* 76 */ UInt guest_r17;
+ /* 80 */ UInt guest_r18;
+ /* 84 */ UInt guest_r19;
+ /* 88 */ UInt guest_r20;
+ /* 92 */ UInt guest_r21;
+ /* 96 */ UInt guest_r22;
+ /* 100 */ UInt guest_r23;
+ /* 104 */ UInt guest_r24; /* Temporaries */
+ /* 108 */ UInt guest_r25;
+ /* 112 */ UInt guest_r26; /* Reserved for OS kernel */
+ /* 116 */ UInt guest_r27;
+ /* 120 */ UInt guest_r28; /* Global pointer */
+ /* 124 */ UInt guest_r29; /* Stack pointer */
+ /* 128 */ UInt guest_r30; /* Frame pointer */
+ /* 132 */ UInt guest_r31; /* Return address */
+ /* 136 */ UInt guest_PC; /* Program counter */
+ /* 140 */ UInt guest_HI; /* Multiply and divide reg higher result */
+ /* 144 */ UInt guest_LO; /* Multiply and divide reg lower result */
+ /* 148 */ UInt _padding1;
/* FPU Registers */
- /* 144 */ ULong guest_f0; /* Floating point general purpose registers */
- /* 152 */ ULong guest_f1;
- /* 160 */ ULong guest_f2;
- /* 168 */ ULong guest_f3;
- /* 176 */ ULong guest_f4;
- /* 184 */ ULong guest_f5;
- /* 192 */ ULong guest_f6;
- /* 200 */ ULong guest_f7;
- /* 208 */ ULong guest_f8;
- /* 216 */ ULong guest_f9;
- /* 224 */ ULong guest_f10;
- /* 232 */ ULong guest_f11;
- /* 240 */ ULong guest_f12;
- /* 248 */ ULong guest_f13;
- /* 256 */ ULong guest_f14;
- /* 264 */ ULong guest_f15;
- /* 272 */ ULong guest_f16;
- /* 280 */ ULong guest_f17;
- /* 288 */ ULong guest_f18;
- /* 296 */ ULong guest_f19;
- /* 304 */ ULong guest_f20;
- /* 312 */ ULong guest_f21;
- /* 320 */ ULong guest_f22;
- /* 328 */ ULong guest_f23;
- /* 336 */ ULong guest_f24;
- /* 344 */ ULong guest_f25;
- /* 352 */ ULong guest_f26;
- /* 360 */ ULong guest_f27;
- /* 368 */ ULong guest_f28;
- /* 376 */ ULong guest_f29;
- /* 384 */ ULong guest_f30;
- /* 392 */ ULong guest_f31;
+ /* 152 */ ULong guest_f0; /* Floating point general purpose registers */
+ /* 160 */ ULong guest_f1;
+ /* 168 */ ULong guest_f2;
+ /* 176 */ ULong guest_f3;
+ /* 184 */ ULong guest_f4;
+ /* 192 */ ULong guest_f5;
+ /* 200 */ ULong guest_f6;
+ /* 208 */ ULong guest_f7;
+ /* 216 */ ULong guest_f8;
+ /* 224 */ ULong guest_f9;
+ /* 232 */ ULong guest_f10;
+ /* 240 */ ULong guest_f11;
+ /* 248 */ ULong guest_f12;
+ /* 256 */ ULong guest_f13;
+ /* 264 */ ULong guest_f14;
+ /* 272 */ ULong guest_f15;
+ /* 280 */ ULong guest_f16;
+ /* 288 */ ULong guest_f17;
+ /* 296 */ ULong guest_f18;
+ /* 304 */ ULong guest_f19;
+ /* 312 */ ULong guest_f20;
+ /* 320 */ ULong guest_f21;
+ /* 328 */ ULong guest_f22;
+ /* 336 */ ULong guest_f23;
+ /* 344 */ ULong guest_f24;
+ /* 352 */ ULong guest_f25;
+ /* 360 */ ULong guest_f26;
+ /* 368 */ ULong guest_f27;
+ /* 376 */ ULong guest_f28;
+ /* 384 */ ULong guest_f29;
+ /* 392 */ ULong guest_f30;
+ /* 400 */ ULong guest_f31;
- /* 400 */ UInt guest_FIR;
- /* 404 */ UInt guest_FCCR;
- /* 408 */ UInt guest_FEXR;
- /* 412 */ UInt guest_FENR;
- /* 416 */ UInt guest_FCSR;
+ /* 408 */ UInt guest_FIR;
+ /* 412 */ UInt guest_FCCR;
+ /* 416 */ UInt guest_FEXR;
+ /* 420 */ UInt guest_FENR;
+ /* 424 */ UInt guest_FCSR;
/* TLS pointer for the thread. It's read-only in user space.
On Linux it is set in user space by various thread-related
@@ -126,36 +130,37 @@
environments, the UserLocal register is a pointer to a
thread-specific storage block.
*/
- /* 420 */ UInt guest_ULR;
+ /* 428 */ UInt guest_ULR;
/* Emulation notes */
- /* 424 */ UInt guest_EMNOTE;
+ /* 432 */ UInt guest_EMNOTE;
- /* For clflush: record start and length of area to invalidate */
- /* 428 */ UInt guest_CMSTART;
- /* 432 */ UInt guest_CMLEN;
- /* 436 */ UInt guest_NRADDR;
+ /* For clflush: record start and length of area to invalidate. */
+ /* 436 */ UInt guest_CMSTART;
+ /* 440 */ UInt guest_CMLEN;
+ /* 444 */ UInt guest_NRADDR;
- /* 440 */ UInt host_EvC_FAILADDR;
- /* 444 */ UInt host_EvC_COUNTER;
- /* 448 */ UInt guest_COND;
+ /* 448 */ UInt guest_COND;
/* MIPS32 DSP ASE(r2) specific registers. */
- /* 452 */ UInt guest_DSPControl;
- /* 456 */ ULong guest_ac0;
- /* 464 */ ULong guest_ac1;
- /* 472 */ ULong guest_ac2;
- /* 480 */ ULong guest_ac3;
+ /* 452 */ UInt guest_DSPControl;
+ /* 456 */ ULong guest_ac0;
+ /* 464 */ ULong guest_ac1;
+ /* 472 */ ULong guest_ac2;
+ /* 480 */ ULong guest_ac3;
- /* 488 */ UInt guest_CP0_status;
+ /* 488 */ UInt guest_CP0_status;
- /* 492 */ UInt padding;
+ /* 492 */ UInt guest_LLaddr;
+ /* 496 */ UInt guest_LLdata;
+
+ /* 500 */ UInt _padding2[3];
} VexGuestMIPS32State;
/*---------------------------------------------------------------*/
/*--- Utility functions for MIPS32 guest stuff. ---*/
/*---------------------------------------------------------------*/
-/* ALL THE FOLLOWING ARE VISIBLE TO LIBRARY CLIENT */
+/* ALL THE FOLLOWING ARE VISIBLE TO LIBRARY CLIENT. */
/* Initialise all guest MIPS32 state. */
diff --git a/VEX/pub/libvex_guest_mips64.h b/VEX/pub/libvex_guest_mips64.h
index 88d1f7f..792803e 100644
--- a/VEX/pub/libvex_guest_mips64.h
+++ b/VEX/pub/libvex_guest_mips64.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 RT-RK
+ Copyright (C) 2010-2017 RT-RK
mips-valgrind@rt-rk.com
This program is free software; you can redistribute it and/or
@@ -46,84 +46,87 @@
typedef
struct {
+ /* 0 */ ULong host_EvC_FAILADDR;
+ /* 8 */ UInt host_EvC_COUNTER;
+ /* 12 */ UInt _padding1;
+
/* CPU Registers */
- /* 0 */ ULong guest_r0; /* Hardwired to 0 */
- /* 8 */ ULong guest_r1; /* Assembler temporary */
- /* 16 */ ULong guest_r2; /* Values for function returns ...*/
- /* 24 */ ULong guest_r3; /* ...and expression evaluation */
- /* 32 */ ULong guest_r4; /* Function arguments */
- /* 40 */ ULong guest_r5;
- /* 48 */ ULong guest_r6;
- /* 56 */ ULong guest_r7;
- /* 64 */ ULong guest_r8;
- /* 72 */ ULong guest_r9;
- /* 80 */ ULong guest_r10;
- /* 88 */ ULong guest_r11;
- /* 96 */ ULong guest_r12; /* Temporaries */
- /* 104 */ ULong guest_r13;
- /* 112 */ ULong guest_r14;
- /* 120 */ ULong guest_r15;
- /* 128 */ ULong guest_r16; /* Saved temporaries */
- /* 136 */ ULong guest_r17;
- /* 144 */ ULong guest_r18;
- /* 152 */ ULong guest_r19;
- /* 160 */ ULong guest_r20;
- /* 168 */ ULong guest_r21;
- /* 176 */ ULong guest_r22;
- /* 184 */ ULong guest_r23;
- /* 192 */ ULong guest_r24; /* Temporaries */
- /* 200 */ ULong guest_r25;
- /* 208 */ ULong guest_r26; /* Reserved for OS kernel */
- /* 216 */ ULong guest_r27;
- /* 224 */ ULong guest_r28; /* Global pointer */
- /* 232 */ ULong guest_r29; /* Stack pointer */
- /* 240 */ ULong guest_r30; /* Frame pointer */
- /* 248 */ ULong guest_r31; /* Return address */
- /* 256 */ ULong guest_PC; /* Program counter */
- /* 264 */ ULong guest_HI; /* Multiply and divide reg higher result */
- /* 272 */ ULong guest_LO; /* Multiply and divide reg lower result */
+ /* 16 */ ULong guest_r0; /* Hardwired to 0. */
+ /* 24 */ ULong guest_r1; /* Assembler temporary */
+ /* 32 */ ULong guest_r2; /* Values for function returns ...*/
+ /* 40 */ ULong guest_r3; /* ... and expression evaluation */
+ /* 48 */ ULong guest_r4; /* Function arguments */
+ /* 56 */ ULong guest_r5;
+ /* 64 */ ULong guest_r6;
+ /* 72 */ ULong guest_r7;
+ /* 80 */ ULong guest_r8;
+ /* 88 */ ULong guest_r9;
+ /* 96 */ ULong guest_r10;
+ /* 104 */ ULong guest_r11;
+ /* 112 */ ULong guest_r12; /* Temporaries */
+ /* 120 */ ULong guest_r13;
+ /* 128 */ ULong guest_r14;
+ /* 136 */ ULong guest_r15;
+ /* 144 */ ULong guest_r16; /* Saved temporaries */
+ /* 152 */ ULong guest_r17;
+ /* 160 */ ULong guest_r18;
+ /* 168 */ ULong guest_r19;
+ /* 176 */ ULong guest_r20;
+ /* 184 */ ULong guest_r21;
+ /* 192 */ ULong guest_r22;
+ /* 200 */ ULong guest_r23;
+ /* 208 */ ULong guest_r24; /* Temporaries */
+ /* 216 */ ULong guest_r25;
+ /* 224 */ ULong guest_r26; /* Reserved for OS kernel */
+ /* 232 */ ULong guest_r27;
+ /* 240 */ ULong guest_r28; /* Global pointer */
+ /* 248 */ ULong guest_r29; /* Stack pointer */
+ /* 256 */ ULong guest_r30; /* Frame pointer */
+ /* 264 */ ULong guest_r31; /* Return address */
+ /* 272 */ ULong guest_PC; /* Program counter */
+ /* 280 */ ULong guest_HI; /* Multiply and divide reg higher result */
+ /* 288 */ ULong guest_LO; /* Multiply and divide reg lower result */
/* FPU Registers */
- /* 280 */ ULong guest_f0; /* Floting point gen purpose registers */
- /* 288 */ ULong guest_f1;
- /* 296 */ ULong guest_f2;
- /* 304 */ ULong guest_f3;
- /* 312 */ ULong guest_f4;
- /* 320 */ ULong guest_f5;
- /* 328 */ ULong guest_f6;
- /* 336 */ ULong guest_f7;
- /* 344 */ ULong guest_f8;
- /* 352 */ ULong guest_f9;
- /* 360 */ ULong guest_f10;
- /* 368 */ ULong guest_f11;
- /* 376 */ ULong guest_f12;
- /* 384 */ ULong guest_f13;
- /* 392 */ ULong guest_f14;
- /* 400 */ ULong guest_f15;
- /* 408 */ ULong guest_f16;
- /* 416 */ ULong guest_f17;
- /* 424 */ ULong guest_f18;
- /* 432 */ ULong guest_f19;
- /* 440 */ ULong guest_f20;
- /* 448 */ ULong guest_f21;
- /* 456 */ ULong guest_f22;
- /* 464 */ ULong guest_f23;
- /* 472 */ ULong guest_f24;
- /* 480 */ ULong guest_f25;
- /* 488 */ ULong guest_f26;
- /* 496 */ ULong guest_f27;
- /* 504 */ ULong guest_f28;
- /* 512 */ ULong guest_f29;
- /* 520 */ ULong guest_f30;
- /* 528 */ ULong guest_f31;
+ /* 296 */ ULong guest_f0; /* Floating point gen. purpose registers */
+ /* 304 */ ULong guest_f1;
+ /* 312 */ ULong guest_f2;
+ /* 320 */ ULong guest_f3;
+ /* 328 */ ULong guest_f4;
+ /* 336 */ ULong guest_f5;
+ /* 344 */ ULong guest_f6;
+ /* 352 */ ULong guest_f7;
+ /* 360 */ ULong guest_f8;
+ /* 368 */ ULong guest_f9;
+ /* 376 */ ULong guest_f10;
+ /* 384 */ ULong guest_f11;
+ /* 392 */ ULong guest_f12;
+ /* 400 */ ULong guest_f13;
+ /* 408 */ ULong guest_f14;
+ /* 416 */ ULong guest_f15;
+ /* 424 */ ULong guest_f16;
+ /* 432 */ ULong guest_f17;
+ /* 440 */ ULong guest_f18;
+ /* 448 */ ULong guest_f19;
+ /* 456 */ ULong guest_f20;
+ /* 464 */ ULong guest_f21;
+ /* 472 */ ULong guest_f22;
+ /* 480 */ ULong guest_f23;
+ /* 488 */ ULong guest_f24;
+ /* 496 */ ULong guest_f25;
+ /* 504 */ ULong guest_f26;
+ /* 512 */ ULong guest_f27;
+ /* 520 */ ULong guest_f28;
+ /* 528 */ ULong guest_f29;
+ /* 536 */ ULong guest_f30;
+ /* 544 */ ULong guest_f31;
- /* 536 */ UInt guest_FIR;
- /* 540 */ UInt guest_FCCR;
- /* 544 */ UInt guest_FEXR;
- /* 548 */ UInt guest_FENR;
- /* 552 */ UInt guest_FCSR;
-
- /* 556 */ UInt guest_CP0_status;
+ /* 552 */ UInt guest_FIR;
+ /* 556 */ UInt guest_FCCR;
+ /* 560 */ UInt guest_FEXR;
+ /* 564 */ UInt guest_FENR;
+ /* 568 */ UInt guest_FCSR;
+ /* 572 */ UInt guest_CP0_status;
/* TLS pointer for the thread. It's read-only in user space. On Linux it
is set in user space by various thread-related syscalls.
@@ -132,29 +135,30 @@
UserLocal register, if it is implemented. In some operating
environments, the UserLocal register is a pointer to a thread-specific
storage block.
- */
- ULong guest_ULR; /* 560 */
+ */
+ /* 576 */ ULong guest_ULR;
/* Emulation notes */
- UInt guest_EMNOTE; /* 568 */
+ /* 584 */ UInt guest_EMNOTE;
+ /* 588 */ UInt guest_COND;
/* For clflush: record start and length of area to invalidate */
- ULong guest_CMSTART; /* 576 */
- ULong guest_CMLEN; /* 584 */
+ /* 592 */ ULong guest_CMSTART;
+ /* 600 */ ULong guest_CMLEN;
- ULong guest_NRADDR; /* 592 */
+ /* 608 */ ULong guest_NRADDR;
- ULong host_EvC_FAILADDR; /* 600 */
- UInt host_EvC_COUNTER; /* 608 */
- UInt guest_COND; /* 612 */
- UInt padding[2];
+ /* 616 */ ULong guest_LLaddr;
+ /* 624 */ ULong guest_LLdata;
+
+ /* 632 */ ULong _padding2;
} VexGuestMIPS64State;
/*---------------------------------------------------------------*/
/*--- Utility functions for MIPS64 guest stuff. ---*/
/*---------------------------------------------------------------*/
-/* ALL THE FOLLOWING ARE VISIBLE TO LIBRARY CLIENT */
+/* ALL THE FOLLOWING ARE VISIBLE TO LIBRARY CLIENT. */
/* Initialise all guest MIPS64 state. */
diff --git a/VEX/pub/libvex_guest_offsets.h b/VEX/pub/libvex_guest_offsets.h
index 6834fbb..7dfcd12 100644
--- a/VEX/pub/libvex_guest_offsets.h
+++ b/VEX/pub/libvex_guest_offsets.h
@@ -42,7 +42,7 @@
#define OFFSET_ppc32_GPR9 52
#define OFFSET_ppc32_GPR10 56
#define OFFSET_ppc32_CIA 1168
-#define OFFSET_ppc32_CR0_0 1185
+#define OFFSET_ppc32_CR0_0 1187
#define OFFSET_ppc64_GPR0 16
#define OFFSET_ppc64_GPR1 24
#define OFFSET_ppc64_GPR2 32
@@ -55,7 +55,7 @@
#define OFFSET_ppc64_GPR9 88
#define OFFSET_ppc64_GPR10 96
#define OFFSET_ppc64_CIA 1296
-#define OFFSET_ppc64_CR0_0 1325
+#define OFFSET_ppc64_CR0_0 1327
#define OFFSET_arm_R0 8
#define OFFSET_arm_R1 12
#define OFFSET_arm_R2 16
@@ -92,133 +92,73 @@
#define OFFSET_s390x_CC_DEP1 360
#define OFFSET_s390x_CC_DEP2 368
#define OFFSET_s390x_CC_NDEP 376
-#define OFFSET_mips32_r0 0
-#define OFFSET_mips32_r1 4
-#define OFFSET_mips32_r2 8
-#define OFFSET_mips32_r3 12
-#define OFFSET_mips32_r4 16
-#define OFFSET_mips32_r5 20
-#define OFFSET_mips32_r6 24
-#define OFFSET_mips32_r7 28
-#define OFFSET_mips32_r8 32
-#define OFFSET_mips32_r9 36
-#define OFFSET_mips32_r10 40
-#define OFFSET_mips32_r11 44
-#define OFFSET_mips32_r12 48
-#define OFFSET_mips32_r13 52
-#define OFFSET_mips32_r14 56
-#define OFFSET_mips32_r15 60
-#define OFFSET_mips32_r15 60
-#define OFFSET_mips32_r17 68
-#define OFFSET_mips32_r18 72
-#define OFFSET_mips32_r19 76
-#define OFFSET_mips32_r20 80
-#define OFFSET_mips32_r21 84
-#define OFFSET_mips32_r22 88
-#define OFFSET_mips32_r23 92
-#define OFFSET_mips32_r24 96
-#define OFFSET_mips32_r25 100
-#define OFFSET_mips32_r26 104
-#define OFFSET_mips32_r27 108
-#define OFFSET_mips32_r28 112
-#define OFFSET_mips32_r29 116
-#define OFFSET_mips32_r30 120
-#define OFFSET_mips32_r31 124
-#define OFFSET_mips32_PC 128
-#define OFFSET_mips32_HI 132
-#define OFFSET_mips32_LO 136
-#define OFFSET_mips64_r0 0
-#define OFFSET_mips64_r1 8
-#define OFFSET_mips64_r2 16
-#define OFFSET_mips64_r3 24
-#define OFFSET_mips64_r4 32
-#define OFFSET_mips64_r5 40
-#define OFFSET_mips64_r6 48
-#define OFFSET_mips64_r7 56
-#define OFFSET_mips64_r8 64
-#define OFFSET_mips64_r9 72
-#define OFFSET_mips64_r10 80
-#define OFFSET_mips64_r11 88
-#define OFFSET_mips64_r12 96
-#define OFFSET_mips64_r13 104
-#define OFFSET_mips64_r14 112
-#define OFFSET_mips64_r15 120
-#define OFFSET_mips64_r15 120
-#define OFFSET_mips64_r17 136
-#define OFFSET_mips64_r18 144
-#define OFFSET_mips64_r19 152
-#define OFFSET_mips64_r20 160
-#define OFFSET_mips64_r21 168
-#define OFFSET_mips64_r22 176
-#define OFFSET_mips64_r23 184
-#define OFFSET_mips64_r24 192
-#define OFFSET_mips64_r25 200
-#define OFFSET_mips64_r26 208
-#define OFFSET_mips64_r27 216
-#define OFFSET_mips64_r28 224
-#define OFFSET_mips64_r29 232
-#define OFFSET_mips64_r30 240
-#define OFFSET_mips64_r31 248
-#define OFFSET_mips64_PC 256
-#define OFFSET_mips64_HI 264
-#define OFFSET_mips64_LO 272
-#define OFFSET_tilegx_r0 0
-#define OFFSET_tilegx_r1 8
-#define OFFSET_tilegx_r2 16
-#define OFFSET_tilegx_r3 24
-#define OFFSET_tilegx_r4 32
-#define OFFSET_tilegx_r5 40
-#define OFFSET_tilegx_r6 48
-#define OFFSET_tilegx_r7 56
-#define OFFSET_tilegx_r8 64
-#define OFFSET_tilegx_r9 72
-#define OFFSET_tilegx_r10 80
-#define OFFSET_tilegx_r11 88
-#define OFFSET_tilegx_r12 96
-#define OFFSET_tilegx_r13 104
-#define OFFSET_tilegx_r14 112
-#define OFFSET_tilegx_r15 120
-#define OFFSET_tilegx_r16 128
-#define OFFSET_tilegx_r17 136
-#define OFFSET_tilegx_r18 144
-#define OFFSET_tilegx_r19 152
-#define OFFSET_tilegx_r20 160
-#define OFFSET_tilegx_r21 168
-#define OFFSET_tilegx_r22 176
-#define OFFSET_tilegx_r23 184
-#define OFFSET_tilegx_r24 192
-#define OFFSET_tilegx_r25 200
-#define OFFSET_tilegx_r26 208
-#define OFFSET_tilegx_r27 216
-#define OFFSET_tilegx_r28 224
-#define OFFSET_tilegx_r29 232
-#define OFFSET_tilegx_r30 240
-#define OFFSET_tilegx_r31 248
-#define OFFSET_tilegx_r32 256
-#define OFFSET_tilegx_r33 264
-#define OFFSET_tilegx_r34 272
-#define OFFSET_tilegx_r35 280
-#define OFFSET_tilegx_r36 288
-#define OFFSET_tilegx_r37 296
-#define OFFSET_tilegx_r38 304
-#define OFFSET_tilegx_r39 312
-#define OFFSET_tilegx_r40 320
-#define OFFSET_tilegx_r41 328
-#define OFFSET_tilegx_r42 336
-#define OFFSET_tilegx_r43 344
-#define OFFSET_tilegx_r44 352
-#define OFFSET_tilegx_r45 360
-#define OFFSET_tilegx_r46 368
-#define OFFSET_tilegx_r47 376
-#define OFFSET_tilegx_r48 384
-#define OFFSET_tilegx_r49 392
-#define OFFSET_tilegx_r50 400
-#define OFFSET_tilegx_r51 408
-#define OFFSET_tilegx_r52 416
-#define OFFSET_tilegx_r53 424
-#define OFFSET_tilegx_r54 432
-#define OFFSET_tilegx_r55 440
-#define OFFSET_tilegx_pc 512
-#define OFFSET_tilegx_EMNOTE 528
-#define OFFSET_tilegx_CMSTART 536
-#define OFFSET_tilegx_NRADDR 552
+#define OFFSET_mips32_r0 8
+#define OFFSET_mips32_r1 12
+#define OFFSET_mips32_r2 16
+#define OFFSET_mips32_r3 20
+#define OFFSET_mips32_r4 24
+#define OFFSET_mips32_r5 28
+#define OFFSET_mips32_r6 32
+#define OFFSET_mips32_r7 36
+#define OFFSET_mips32_r8 40
+#define OFFSET_mips32_r9 44
+#define OFFSET_mips32_r10 48
+#define OFFSET_mips32_r11 52
+#define OFFSET_mips32_r12 56
+#define OFFSET_mips32_r13 60
+#define OFFSET_mips32_r14 64
+#define OFFSET_mips32_r15 68
+#define OFFSET_mips32_r15 68
+#define OFFSET_mips32_r17 76
+#define OFFSET_mips32_r18 80
+#define OFFSET_mips32_r19 84
+#define OFFSET_mips32_r20 88
+#define OFFSET_mips32_r21 92
+#define OFFSET_mips32_r22 96
+#define OFFSET_mips32_r23 100
+#define OFFSET_mips32_r24 104
+#define OFFSET_mips32_r25 108
+#define OFFSET_mips32_r26 112
+#define OFFSET_mips32_r27 116
+#define OFFSET_mips32_r28 120
+#define OFFSET_mips32_r29 124
+#define OFFSET_mips32_r30 128
+#define OFFSET_mips32_r31 132
+#define OFFSET_mips32_PC 136
+#define OFFSET_mips32_HI 140
+#define OFFSET_mips32_LO 144
+#define OFFSET_mips64_r0 16
+#define OFFSET_mips64_r1 24
+#define OFFSET_mips64_r2 32
+#define OFFSET_mips64_r3 40
+#define OFFSET_mips64_r4 48
+#define OFFSET_mips64_r5 56
+#define OFFSET_mips64_r6 64
+#define OFFSET_mips64_r7 72
+#define OFFSET_mips64_r8 80
+#define OFFSET_mips64_r9 88
+#define OFFSET_mips64_r10 96
+#define OFFSET_mips64_r11 104
+#define OFFSET_mips64_r12 112
+#define OFFSET_mips64_r13 120
+#define OFFSET_mips64_r14 128
+#define OFFSET_mips64_r15 136
+#define OFFSET_mips64_r15 136
+#define OFFSET_mips64_r17 152
+#define OFFSET_mips64_r18 160
+#define OFFSET_mips64_r19 168
+#define OFFSET_mips64_r20 176
+#define OFFSET_mips64_r21 184
+#define OFFSET_mips64_r22 192
+#define OFFSET_mips64_r23 200
+#define OFFSET_mips64_r24 208
+#define OFFSET_mips64_r25 216
+#define OFFSET_mips64_r26 224
+#define OFFSET_mips64_r27 232
+#define OFFSET_mips64_r28 240
+#define OFFSET_mips64_r29 248
+#define OFFSET_mips64_r30 256
+#define OFFSET_mips64_r31 264
+#define OFFSET_mips64_PC 272
+#define OFFSET_mips64_HI 280
+#define OFFSET_mips64_LO 288
diff --git a/VEX/pub/libvex_guest_ppc32.h b/VEX/pub/libvex_guest_ppc32.h
index 842032a..816ef5a 100644
--- a/VEX/pub/libvex_guest_ppc32.h
+++ b/VEX/pub/libvex_guest_ppc32.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -173,49 +173,53 @@
/* XER pieces */
/* 1164 */ UChar guest_XER_SO; /* in lsb */
/* 1165 */ UChar guest_XER_OV; /* in lsb */
- /* 1166 */ UChar guest_XER_CA; /* in lsb */
- /* 1167 */ UChar guest_XER_BC; /* all bits */
+ /* 1166 */ UChar guest_XER_OV32; /* in lsb */
+ /* 1167 */ UChar guest_XER_CA; /* in lsb */
+ /* 1168 */ UChar guest_XER_CA32; /* in lsb */
+ /* 1169 */ UChar guest_XER_BC; /* all bits */
/* CR pieces */
- /* 1168 */ UChar guest_CR0_321; /* in [3:1] */
- /* 1169 */ UChar guest_CR0_0; /* in lsb */
- /* 1170 */ UChar guest_CR1_321; /* in [3:1] */
- /* 1171 */ UChar guest_CR1_0; /* in lsb */
- /* 1172 */ UChar guest_CR2_321; /* in [3:1] */
- /* 1173 */ UChar guest_CR2_0; /* in lsb */
- /* 1174 */ UChar guest_CR3_321; /* in [3:1] */
- /* 1175 */ UChar guest_CR3_0; /* in lsb */
- /* 1176 */ UChar guest_CR4_321; /* in [3:1] */
- /* 1177 */ UChar guest_CR4_0; /* in lsb */
- /* 1178 */ UChar guest_CR5_321; /* in [3:1] */
- /* 1179 */ UChar guest_CR5_0; /* in lsb */
- /* 1180 */ UChar guest_CR6_321; /* in [3:1] */
- /* 1181 */ UChar guest_CR6_0; /* in lsb */
- /* 1182 */ UChar guest_CR7_321; /* in [3:1] */
- /* 1183 */ UChar guest_CR7_0; /* in lsb */
+ /* 1170 */ UChar guest_CR0_321; /* in [3:1] */
+ /* 1171 */ UChar guest_CR0_0; /* in lsb */
+ /* 1172 */ UChar guest_CR1_321; /* in [3:1] */
+ /* 1173 */ UChar guest_CR1_0; /* in lsb */
+ /* 1174 */ UChar guest_CR2_321; /* in [3:1] */
+ /* 1175 */ UChar guest_CR2_0; /* in lsb */
+ /* 1176 */ UChar guest_CR3_321; /* in [3:1] */
+ /* 1177 */ UChar guest_CR3_0; /* in lsb */
+ /* 1178 */ UChar guest_CR4_321; /* in [3:1] */
+ /* 1179 */ UChar guest_CR4_0; /* in lsb */
+ /* 1180 */ UChar guest_CR5_321; /* in [3:1] */
+ /* 1181 */ UChar guest_CR5_0; /* in lsb */
+ /* 1182 */ UChar guest_CR6_321; /* in [3:1] */
+ /* 1183 */ UChar guest_CR6_0; /* in lsb */
+ /* 1184 */ UChar guest_CR7_321; /* in [3:1] */
+ /* 1185 */ UChar guest_CR7_0; /* in lsb */
/* FP Status and Control Register fields. Only rounding mode fields
* and Floating-point Condition Code (FPCC) fields in the FPSCR are
* supported.
*/
- /* 1184 */ UChar guest_FPROUND; // Binary Floating Point Rounding Mode
- /* 1185 */ UChar guest_DFPROUND; // Decimal Floating Point Rounding Mode
- /* 1186 */ UChar guest_C_FPCC; // Floating-Point Result Class Descriptor
+ /* 1186 */ UChar guest_FPROUND; // Binary Floating Point Rounding Mode
+ /* 1187 */ UChar guest_DFPROUND; // Decimal Floating Point Rounding Mode
+ /* 1188 */ UChar guest_C_FPCC; // Floating-Point Result Class Descriptor
// and Floating-point Condition Code
- /* 1187 */ UChar pad2;
+ /* 1189 */ UChar pad0;
+ /* 1190 */ UChar pad1;
+ /* 1191 */ UChar pad2;
/* Vector Save/Restore Register */
- /* 1188 */ UInt guest_VRSAVE;
+ /* 1192 */ UInt guest_VRSAVE;
/* Vector Status and Control Register */
- /* 1192 */ UInt guest_VSCR;
+ /* 1196 */ UInt guest_VSCR;
/* Emulation notes */
- /* 1196 */ UInt guest_EMNOTE;
+ /* 1200 */ UInt guest_EMNOTE;
/* For icbi: record start and length of area to invalidate */
- /* 1200 */ UInt guest_CMSTART;
- /* 1204 */ UInt guest_CMLEN;
+ /* 1204 */ UInt guest_CMSTART;
+ /* 1208 */ UInt guest_CMLEN;
/* Used to record the unredirected guest address at the start of
a translation whose start has been redirected. By reading
@@ -223,34 +227,35 @@
find out what the corresponding no-redirection address was.
Note, this is only set for wrap-style redirects, not for
replace-style ones. */
- /* 1208 */ UInt guest_NRADDR;
- /* 1212 */ UInt guest_NRADDR_GPR2; /* needed by aix */
+ /* 1212 */ UInt guest_NRADDR;
+ /* 1216 */ UInt guest_NRADDR_GPR2; /* needed by aix */
/* A grows-upwards stack for hidden saves/restores of LR and R2
needed for function interception and wrapping on ppc32-aix5.
A horrible hack. REDIR_SP points to the highest live entry,
and so starts at -1. */
- /* 1216 */ UInt guest_REDIR_SP;
- /* 1220 */ UInt guest_REDIR_STACK[VEX_GUEST_PPC32_REDIR_STACK_SIZE];
+ /* 1220 */ UInt guest_REDIR_SP;
+ /* 1224 */ UInt guest_REDIR_STACK[VEX_GUEST_PPC32_REDIR_STACK_SIZE];
/* Needed for Darwin (but mandated for all guest architectures):
CIA at the last SC insn. Used when backing up to restart a
syscall that has been interrupted by a signal. */
- /* 1348 */ UInt guest_IP_AT_SYSCALL;
+ /* 134C */ UInt guest_IP_AT_SYSCALL;
/* SPRG3, which AIUI is readonly in user space. Needed for
threading on AIX. */
- /* 1352 */ UInt guest_SPRG3_RO;
- /* 1356 */ UInt padding1;
- /* 1360 */ ULong guest_TFHAR; // Transaction Failure Handler Address Register
- /* 1368 */ ULong guest_TEXASR; // Transaction EXception And Summary Register
- /* 1376 */ ULong guest_TFIAR; // Transaction Failure Instruction Address Register
- /* 1384 */ ULong guest_PPR; // Program Priority register
- /* 1392 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
- /* 1396 */ UInt guest_PSPB; // Problem State Priority Boost register
+ /* 1356 */ UInt guest_SPRG3_RO;
+ /* 1360 */ UInt padding1;
+ /* 1364 */ ULong guest_TFHAR; // Transaction Failure Handler Address Register
+ /* 1372 */ ULong guest_TEXASR; // Transaction EXception And Summary Register
+ /* 1380 */ ULong guest_TFIAR; // Transaction Failure Instruction Address Register
+ /* 1388 */ ULong guest_PPR; // Program Priority register
+ /* 1396 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
+ /* 1400 */ UInt guest_PSPB; // Problem State Priority Boost register
/* Padding to make it have an 16-aligned size */
- /* 1400 */ UInt padding2;
- /* 1404 */ UInt padding3;
+ /* 1404 */ UInt padding2;
+ /* 1408 */ UInt padding3;
+ /* 1412 */ UInt padding4;
}
VexGuestPPC32State;
diff --git a/VEX/pub/libvex_guest_ppc64.h b/VEX/pub/libvex_guest_ppc64.h
index 927b227..02c4020 100644
--- a/VEX/pub/libvex_guest_ppc64.h
+++ b/VEX/pub/libvex_guest_ppc64.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -211,52 +211,56 @@
/* XER pieces */
/* 1304 */ UChar guest_XER_SO; /* in lsb */
/* 1305 */ UChar guest_XER_OV; /* in lsb */
- /* 1306 */ UChar guest_XER_CA; /* in lsb */
- /* 1307 */ UChar guest_XER_BC; /* all bits */
+ /* 1306 */ UChar guest_XER_OV32; /* in lsb */
+ /* 1307 */ UChar guest_XER_CA; /* in lsb */
+ /* 1308 */ UChar guest_XER_CA32; /* in lsb */
+ /* 1309 */ UChar guest_XER_BC; /* all bits */
/* CR pieces */
- /* 1308 */ UChar guest_CR0_321; /* in [3:1] */
- /* 1309 */ UChar guest_CR0_0; /* in lsb */
- /* 1310 */ UChar guest_CR1_321; /* in [3:1] */
- /* 1311 */ UChar guest_CR1_0; /* in lsb */
- /* 1312 */ UChar guest_CR2_321; /* in [3:1] */
- /* 1313 */ UChar guest_CR2_0; /* in lsb */
- /* 1314 */ UChar guest_CR3_321; /* in [3:1] */
- /* 1315 */ UChar guest_CR3_0; /* in lsb */
- /* 1316 */ UChar guest_CR4_321; /* in [3:1] */
- /* 1317 */ UChar guest_CR4_0; /* in lsb */
- /* 1318 */ UChar guest_CR5_321; /* in [3:1] */
- /* 1319 */ UChar guest_CR5_0; /* in lsb */
- /* 1320 */ UChar guest_CR6_321; /* in [3:1] */
- /* 1321 */ UChar guest_CR6_0; /* in lsb */
- /* 1322 */ UChar guest_CR7_321; /* in [3:1] */
- /* 1323 */ UChar guest_CR7_0; /* in lsb */
+ /* 1310 */ UChar guest_CR0_321; /* in [3:1] */
+ /* 1311 */ UChar guest_CR0_0; /* in lsb */
+ /* 1312 */ UChar guest_CR1_321; /* in [3:1] */
+ /* 1313 */ UChar guest_CR1_0; /* in lsb */
+ /* 1314 */ UChar guest_CR2_321; /* in [3:1] */
+ /* 1315 */ UChar guest_CR2_0; /* in lsb */
+ /* 1316 */ UChar guest_CR3_321; /* in [3:1] */
+ /* 1317 */ UChar guest_CR3_0; /* in lsb */
+ /* 1318 */ UChar guest_CR4_321; /* in [3:1] */
+ /* 1319 */ UChar guest_CR4_0; /* in lsb */
+ /* 1320 */ UChar guest_CR5_321; /* in [3:1] */
+ /* 1321 */ UChar guest_CR5_0; /* in lsb */
+ /* 1322 */ UChar guest_CR6_321; /* in [3:1] */
+ /* 1323 */ UChar guest_CR6_0; /* in lsb */
+ /* 1324 */ UChar guest_CR7_321; /* in [3:1] */
+ /* 1325 */ UChar guest_CR7_0; /* in lsb */
/* FP Status and Control Register fields. Only rounding mode fields
* and Floating-point Condition Code (FPCC) fields are supported.
*/
- /* 1324 */ UChar guest_FPROUND; // Binary Floating Point Rounding Mode
- /* 1325 */ UChar guest_DFPROUND; // Decimal Floating Point Rounding Mode
- /* 1326 */ UChar guest_C_FPCC; // Floating-point Condition Code
+ /* 1326 */ UChar guest_FPROUND; // Binary Floating Point Rounding Mode
+ /* 1327 */ UChar guest_DFPROUND; // Decimal Floating Point Rounding Mode
+ /* 1328 */ UChar guest_C_FPCC; // Floating-point Condition Code
// and Floating-point Condition Code
- /* 1327 */ UChar pad2;
+ /* 1329 */ UChar pad2;
+ /* 1330 */ UChar pad3;
+ /* 1331 */ UChar pad4;
/* Vector Save/Restore Register */
- /* 1328 */ UInt guest_VRSAVE;
+ /* 1332 */ UInt guest_VRSAVE;
/* Vector Status and Control Register */
- /* 1332 */ UInt guest_VSCR;
+ /* 1336 */ UInt guest_VSCR;
/* Emulation notes */
- /* 1336 */ UInt guest_EMNOTE;
+ /* 1340 */ UInt guest_EMNOTE;
/* gcc adds 4 bytes padding here: pre-empt it. */
- /* 1340 */ UInt padding;
+ /* 1344 */ UInt padding;
/* For icbi: record start and length of area to invalidate */
- /* 1344 */ ULong guest_CMSTART;
- /* 1352 */ ULong guest_CMLEN;
+ /* 1348 */ ULong guest_CMSTART;
+ /* 1356 */ ULong guest_CMLEN;
/* Used to record the unredirected guest address at the start of
a translation whose start has been redirected. By reading
@@ -264,35 +268,35 @@
find out what the corresponding no-redirection address was.
Note, this is only set for wrap-style redirects, not for
replace-style ones. */
- /* 1360 */ ULong guest_NRADDR;
- /* 1368 */ ULong guest_NRADDR_GPR2;
+ /* 1364 */ ULong guest_NRADDR;
+ /* 1372 */ ULong guest_NRADDR_GPR2;
/* A grows-upwards stack for hidden saves/restores of LR and R2
needed for function interception and wrapping on ppc64-linux.
A horrible hack. REDIR_SP points to the highest live entry,
and so starts at -1. */
- /* 1376 */ ULong guest_REDIR_SP;
- /* 1384 */ ULong guest_REDIR_STACK[VEX_GUEST_PPC64_REDIR_STACK_SIZE];
+ /* 1380 */ ULong guest_REDIR_SP;
+ /* 1388 */ ULong guest_REDIR_STACK[VEX_GUEST_PPC64_REDIR_STACK_SIZE];
/* Needed for Darwin: CIA at the last SC insn. Used when backing up
to restart a syscall that has been interrupted by a signal. */
- /* 1640 */ ULong guest_IP_AT_SYSCALL;
+ /* 1646 */ ULong guest_IP_AT_SYSCALL;
/* SPRG3, which AIUI is readonly in user space. Needed for
threading on AIX. */
- /* 1648 */ ULong guest_SPRG3_RO;
+ /* 1654 */ ULong guest_SPRG3_RO;
- /* 1656 */ ULong guest_TFHAR; // Transaction Failure Handler Address Register
- /* 1664 */ ULong guest_TEXASR; // Transaction EXception And Summary Register
- /* 1672 */ ULong guest_TFIAR; // Transaction Failure Instruction Address Register
- /* 1680 */ ULong guest_PPR; // Program Priority register
- /* 1688 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
- /* 1692 */ UInt guest_PSPB; // Problem State Priority Boost register
+ /* 1662 */ ULong guest_TFHAR; // Transaction Failure Handler Address Register
+ /* 1670 */ ULong guest_TEXASR; // Transaction EXception And Summary Register
+ /* 1678 */ ULong guest_TFIAR; // Transaction Failure Instruction Address Register
+ /* 1686 */ ULong guest_PPR; // Program Priority register
+ /* 1694 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
+ /* 1698 */ UInt guest_PSPB; // Problem State Priority Boost register
/* Padding to make it have an 16-aligned size */
- /* 1696 UInt padding1; currently not needed */
- /* 1700 UInt padding2; currently not needed */
- /* 1708 UInt padding3; currently not needed */
+ /* 1698 */ UInt padding1;
+ /* 1702 UInt padding2; */
+ /* 1706 UInt padding3; */
}
VexGuestPPC64State;
diff --git a/VEX/pub/libvex_guest_s390x.h b/VEX/pub/libvex_guest_s390x.h
index 99d5947..8cf0919 100644
--- a/VEX/pub/libvex_guest_s390x.h
+++ b/VEX/pub/libvex_guest_s390x.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2015
+ Copyright IBM Corp. 2010-2017
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/VEX/pub/libvex_guest_tilegx.h b/VEX/pub/libvex_guest_tilegx.h
deleted file mode 100644
index d3c7062..0000000
--- a/VEX/pub/libvex_guest_tilegx.h
+++ /dev/null
@@ -1,149 +0,0 @@
-
-/*---------------------------------------------------------------*/
-/*--- begin libvex_guest_tilegx.h ---*/
-/*---------------------------------------------------------------*/
-
-/*
- This file is part of Valgrind, a dynamic binary instrumentation
- framework.
-
- Copyright (C) 2010-2015 Tilera Corp.
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of the
- License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful, but
- WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
- 02111-1307, USA.
-
- The GNU General Public License is contained in the file COPYING.
-*/
-
-/* Contributed by Zhi-Gang Liu <zliu at tilera dot com> */
-
-#ifndef __LIBVEX_PUB_GUEST_TILEGX_H
-#define __LIBVEX_PUB_GUEST_TILEGX_H
-
-#include "libvex_basictypes.h"
-#include "libvex_emnote.h"
-
-#undef TILEGX_DEBUG
-
-/*---------------------------------------------------------------*/
-/*--- Vex's representation of the tilegx CPU state. ---*/
-/*---------------------------------------------------------------*/
-
-typedef ULong ULONG;
-
-typedef
-struct {
- /* CPU Registers */
- /* 0 */ ULONG guest_r0;
- /* 8 */ ULONG guest_r1;
- /* 16 */ ULONG guest_r2;
- /* 24 */ ULONG guest_r3;
- /* 32 */ ULONG guest_r4;
- /* 40 */ ULONG guest_r5;
- /* 48 */ ULONG guest_r6;
- /* 56 */ ULONG guest_r7;
- /* 64 */ ULONG guest_r8;
- /* 72 */ ULONG guest_r9;
- /* 80 */ ULONG guest_r10;
- /* 88 */ ULONG guest_r11;
- /* 96 */ ULONG guest_r12;
- /* 104 */ ULONG guest_r13;
- /* 112 */ ULONG guest_r14;
- /* 120 */ ULONG guest_r15;
- /* 128 */ ULONG guest_r16;
- /* 136 */ ULONG guest_r17;
- /* 144 */ ULONG guest_r18;
- /* 152 */ ULONG guest_r19;
- /* 160 */ ULONG guest_r20;
- /* 168 */ ULONG guest_r21;
- /* 176 */ ULONG guest_r22;
- /* 184 */ ULONG guest_r23;
- /* 192 */ ULONG guest_r24;
- /* 200 */ ULONG guest_r25;
- /* 208 */ ULONG guest_r26;
- /* 216 */ ULONG guest_r27;
- /* 224 */ ULONG guest_r28;
- /* 232 */ ULONG guest_r29;
- /* 240 */ ULONG guest_r30;
- /* 248 */ ULONG guest_r31;
- /* 256 */ ULONG guest_r32;
- /* 264 */ ULONG guest_r33;
- /* 272 */ ULONG guest_r34;
- /* 280 */ ULONG guest_r35;
- /* 288 */ ULONG guest_r36;
- /* 296 */ ULONG guest_r37;
- /* 304 */ ULONG guest_r38;
- /* 312 */ ULONG guest_r39;
- /* 320 */ ULONG guest_r40;
- /* 328 */ ULONG guest_r41;
- /* 336 */ ULONG guest_r42;
- /* 344 */ ULONG guest_r43;
- /* 352 */ ULONG guest_r44;
- /* 360 */ ULONG guest_r45;
- /* 368 */ ULONG guest_r46;
- /* 376 */ ULONG guest_r47;
- /* 384 */ ULONG guest_r48;
- /* 392 */ ULONG guest_r49;
- /* 400 */ ULONG guest_r50;
- /* 408 */ ULONG guest_r51;
- /* 416 */ ULONG guest_r52; /* FP */
- /* 424 */ ULONG guest_r53;
- /* 432 */ ULONG guest_r54; /* SP */
- /* 440 */ ULONG guest_r55; /* LR */
- /* 448 */ ULONG guest_r56; /* zero */
- /* 456 */ ULONG guest_r57; /* Reserved */
- /* 464 */ ULONG guest_r58; /* Reserved */
- /* 472 */ ULONG guest_r59; /* Reserved */
- /* 480 */ ULONG guest_r60; /* Reserved */
- /* 488 */ ULONG guest_r61; /* Reserved */
- /* 496 */ ULONG guest_r62; /* Reserved */
- /* 504 */ ULONG guest_r63; /* Reserved */
- /* 512 */ ULONG guest_pc;
- /* 520 */ ULONG guest_spare; /* Reserved */
- /* 528 */ ULONG guest_EMNOTE;
- /* 536 */ ULONG guest_CMSTART;
- /* 544 */ ULONG guest_CMLEN;
- /* 552 */ ULONG guest_NRADDR;
- /* 560 */ ULong guest_cmpexch;
- /* 568 */ ULong guest_zero;
- /* 576 */ ULong guest_ex_context_0;
- /* 584 */ ULong guest_ex_context_1;
- /* 592 */ ULong host_EvC_FAILADDR;
- /* 600 */ ULong host_EvC_COUNTER;
- /* 608 */ ULong guest_COND;
- /* 616 */ ULong PAD;
-
-} VexGuestTILEGXState;
-
-#define OFFSET_tilegx_r(_N) (8 * (_N))
-
-/*---------------------------------------------------------------*/
-/*--- Utility functions for TILEGX guest stuff. ---*/
-/*---------------------------------------------------------------*/
-
-/* ALL THE FOLLOWING ARE VISIBLE TO LIBRARY CLIENT */
-
-/* Initialise all guest TILEGX state. */
-
-extern
-void LibVEX_GuestTILEGX_initialise ( /*OUT*/VexGuestTILEGXState* vex_state );
-
-
-#endif /* __LIBVEX_PUB_GUEST_TILEGX_H */
-
-
-/*---------------------------------------------------------------*/
-/*--- libvex_guest_tilegx.h ---*/
-/*---------------------------------------------------------------*/
diff --git a/VEX/pub/libvex_guest_x86.h b/VEX/pub/libvex_guest_x86.h
index 5c77569..3ec8af5 100644
--- a/VEX/pub/libvex_guest_x86.h
+++ b/VEX/pub/libvex_guest_x86.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -194,8 +194,8 @@
UShort guest_GS;
UShort guest_SS;
/* LDT/GDT stuff. */
- HWord guest_LDT; /* host addr, a VexGuestX86SegDescr* */
- HWord guest_GDT; /* host addr, a VexGuestX86SegDescr* */
+ ULong guest_LDT; /* host addr, a VexGuestX86SegDescr* */
+ ULong guest_GDT; /* host addr, a VexGuestX86SegDescr* */
/* Emulation notes */
UInt guest_EMNOTE;
@@ -223,6 +223,8 @@
/* Padding to make it have an 16-aligned size */
UInt padding1;
+ UInt padding2;
+ UInt padding3;
}
VexGuestX86State;
diff --git a/VEX/pub/libvex_ir.h b/VEX/pub/libvex_ir.h
index 5efcd5c..fcac043 100644
--- a/VEX/pub/libvex_ir.h
+++ b/VEX/pub/libvex_ir.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -776,6 +776,13 @@
Iop_RecpExpF64, /* FRECPX d :: IRRoundingMode(I32) x F64 -> F64 */
Iop_RecpExpF32, /* FRECPX s :: IRRoundingMode(I32) x F32 -> F32 */
+ /* --------- Possibly required by IEEE 754-2008. --------- */
+
+ Iop_MaxNumF64, /* max, F64, numerical operand if other is a qNaN */
+ Iop_MinNumF64, /* min, F64, ditto */
+ Iop_MaxNumF32, /* max, F32, ditto */
+ Iop_MinNumF32, /* min, F32, ditto */
+
/* ------------------ 16-bit scalar FP ------------------ */
Iop_F16toF64, /* F16 -> F64 */
@@ -1957,7 +1964,7 @@
Iex_ITE,
Iex_CCall,
Iex_VECRET,
- Iex_BBPTR
+ Iex_GSPTR
}
IRExprTag;
@@ -2132,7 +2139,7 @@
quite poor code to be generated. Try to avoid it.
In principle it would be allowable to have the arg vector
- contain an IRExpr_VECRET(), although not IRExpr_BBPTR(). However,
+ contain an IRExpr_VECRET(), although not IRExpr_GSPTR(). However,
at the moment there is no requirement for clean helper calls to
be able to return V128 or V256 values. Hence this is not allowed.
@@ -2196,8 +2203,8 @@
only appear at most once in an argument list, and it may not appear
at all in argument lists for clean helper calls. */
-static inline Bool is_IRExpr_VECRET_or_BBPTR ( const IRExpr* e ) {
- return e->tag == Iex_VECRET || e->tag == Iex_BBPTR;
+static inline Bool is_IRExpr_VECRET_or_GSPTR ( const IRExpr* e ) {
+ return e->tag == Iex_VECRET || e->tag == Iex_GSPTR;
}
@@ -2217,7 +2224,7 @@
extern IRExpr* IRExpr_CCall ( IRCallee* cee, IRType retty, IRExpr** args );
extern IRExpr* IRExpr_ITE ( IRExpr* cond, IRExpr* iftrue, IRExpr* iffalse );
extern IRExpr* IRExpr_VECRET ( void );
-extern IRExpr* IRExpr_BBPTR ( void );
+extern IRExpr* IRExpr_GSPTR ( void );
/* Deep-copy an IRExpr. */
extern IRExpr* deepCopyIRExpr ( const IRExpr* );
@@ -2376,10 +2383,10 @@
number of times at a fixed interval, if required.
Normally, code is generated to pass just the args to the helper.
- However, if IRExpr_BBPTR() is present in the argument list (at most
- one instance is allowed), then the baseblock pointer is passed for
+ However, if IRExpr_GSPTR() is present in the argument list (at most
+ one instance is allowed), then the guest state pointer is passed for
that arg, so that the callee can access the guest state. It is
- invalid for .nFxState to be zero but IRExpr_BBPTR() to be present,
+ invalid for .nFxState to be zero but IRExpr_GSPTR() to be present,
since .nFxState==0 is a claim that the call does not access guest
state.
@@ -2416,7 +2423,7 @@
allowed. */
IRCallee* cee; /* where to call */
IRExpr* guard; /* :: Ity_Bit. Controls whether call happens */
- /* The args vector may contain IRExpr_BBPTR() and/or
+ /* The args vector may contain IRExpr_GSPTR() and/or
IRExpr_VECRET(), in both cases, at most once. */
IRExpr** args; /* arg vector, ends in NULL. */
IRTemp tmp; /* to assign result to, or IRTemp_INVALID if none */
diff --git a/VEX/pub/libvex_s390x_common.h b/VEX/pub/libvex_s390x_common.h
index ecdc11b..5b21b34 100644
--- a/VEX/pub/libvex_s390x_common.h
+++ b/VEX/pub/libvex_s390x_common.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2015
+ Copyright IBM Corp. 2010-2017
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/VEX/pub/libvex_trc_values.h b/VEX/pub/libvex_trc_values.h
index 38ff2e1..e46e0fb 100644
--- a/VEX/pub/libvex_trc_values.h
+++ b/VEX/pub/libvex_trc_values.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 OpenWorks LLP
+ Copyright (C) 2004-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/auxprogs/Makefile.am b/auxprogs/Makefile.am
index f5654c1..c13f07a 100644
--- a/auxprogs/Makefile.am
+++ b/auxprogs/Makefile.am
@@ -6,6 +6,7 @@
gen-mdg \
gsl16test \
gsl19test \
+ make_or_upd_vgversion_h \
nightly-build-summary \
update-demangler \
posixtestsuite-1.5.1-diff-results
diff --git a/auxprogs/Makefile.in b/auxprogs/Makefile.in
index a5277d4..b7868a4 100644
--- a/auxprogs/Makefile.in
+++ b/auxprogs/Makefile.in
@@ -278,6 +278,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -448,6 +449,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -458,6 +460,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -532,8 +535,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -578,7 +579,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
dist_noinst_SCRIPTS = \
@@ -587,6 +587,7 @@
gen-mdg \
gsl16test \
gsl19test \
+ make_or_upd_vgversion_h \
nightly-build-summary \
update-demangler \
posixtestsuite-1.5.1-diff-results
diff --git a/auxprogs/change-copyright-year b/auxprogs/change-copyright-year
index bd8fdc5..4e7f5c7 100755
--- a/auxprogs/change-copyright-year
+++ b/auxprogs/change-copyright-year
@@ -3,7 +3,7 @@
# Script updates the copyright year in every file in Valgrind that contains
# a copyright notice. Assumes they're all in the same format:
#
-# "Copyright (C) 20xy-2012"
+# "Copyright (C) 20xy-2017"
#
# where x can be 0 or 1 and y can be anything.
# To use:
@@ -19,11 +19,11 @@
for i in `find . -name '*.[chS]' -o -name '*.in' -type f -not -path '*.svn\/*'` ; do
echo $i
if [ -L $i ]; then continue; fi # skip symbolic links
- perl -p -e 's/Copyright \(C\) 20([0-1])([0-9])-2013/Copyright (C) 20$1$2-2015/' < $i > tmp.$$
+ perl -p -e 's/Copyright \(C\) 20([0-1])([0-9])-2015/Copyright (C) 20$1$2-2017/' < $i > tmp.$$
mv tmp.$$ $i
# Copyright IBM Corp. 2010-2011
- perl -p -e 's/Copyright IBM Corp. 20([0-1])([0-9])-2013/Copyright IBM Corp. 20$1$2-2015/' < $i > tmp.$$
+ perl -p -e 's/Copyright IBM Corp. 20([0-1])([0-9])-2015/Copyright IBM Corp. 20$1$2-2017/' < $i > tmp.$$
mv tmp.$$ $i
done
diff --git a/auxprogs/getoff.c b/auxprogs/getoff.c
index 6e94b9a..d3392a7 100644
--- a/auxprogs/getoff.c
+++ b/auxprogs/getoff.c
@@ -2,7 +2,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2014-2015 Philippe Waroquiers
+ Copyright (C) 2014-2017 Philippe Waroquiers
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/auxprogs/make_or_upd_vgversion_h b/auxprogs/make_or_upd_vgversion_h
new file mode 100755
index 0000000..9a3bee3
--- /dev/null
+++ b/auxprogs/make_or_upd_vgversion_h
@@ -0,0 +1,47 @@
+#!/bin/sh
+
+extract_svn_version()
+{
+ if [ -d "$1"/.svn ]
+ then
+ svnversion -n "$1"
+ elif [ -d "$1"/.git/svn ]
+ then
+ cd "$1" || exit 1
+ git svn info . | grep '^Revision' | cut -d ' ' -f2 | tr -d '\n'
+ else
+ echo "unknown"
+ fi
+}
+
+srcdir="${1:-.}"
+
+if [ -e "$srcdir"/include/vgversion_dist.h ]
+then
+ cp "$srcdir"/include/vgversion_dist.h include/vgversion.h.tmp
+else
+ cat > include/vgversion.h.tmp <<EOF
+/* Do not edit: file generated by auxprogs/make_or_upd_vgversion_h.
+ This file defines VGSVN and VEXSVN, used to report SVN revision
+ when using command line options: -v --version
+*/
+#define VGSVN "$(extract_svn_version "$srcdir/.")"
+#define VEXSVN "$(extract_svn_version "$srcdir/VEX")"
+EOF
+fi
+
+if [ -f include/vgversion.h ]
+then
+ # There is already a vgversion.h.
+ # Update it only if we found a different and real svn version
+ if grep -q unknown include/vgversion.h.tmp ||
+ cmp -s include/vgversion.h include/vgversion.h.tmp
+ then
+ rm -f include/vgversion.h.tmp
+ else
+ mv include/vgversion.h.tmp include/vgversion.h
+ fi
+else
+ # There is no vgversion.h. Use the one just generated, whatever it is.
+ mv include/vgversion.h.tmp include/vgversion.h
+fi
diff --git a/auxprogs/update-demangler b/auxprogs/update-demangler
index 18189b3..8c1bbaa 100755
--- a/auxprogs/update-demangler
+++ b/auxprogs/update-demangler
@@ -17,8 +17,8 @@
#---------------------------------------------------------------------
# You need to modify these revision numbers for your update.
-old_gcc_revision=r212125 # the revision of the previous update
-new_gcc_revision=r240068 # the revision for this update
+old_gcc_revision=r240068 # the revision of the previous update
+new_gcc_revision=r246502 # the revision for this update
# Unless the organization of demangler related files has changed, no
# changes below this line should be necessary.
@@ -56,6 +56,7 @@
cp ../gcc-$old_gcc_revision/libiberty/cplus-dem.c .
cp ../gcc-$old_gcc_revision/libiberty/dyn-string.c .
cp ../gcc-$old_gcc_revision/libiberty/d-demangle.c .
+cp ../gcc-$old_gcc_revision/libiberty/rust-demangle.c .
cp ../gcc-$old_gcc_revision/libiberty/safe-ctype.c .
cd ..
@@ -83,6 +84,7 @@
cp ../gcc-$new_gcc_revision/libiberty/cplus-dem.c .
cp ../gcc-$new_gcc_revision/libiberty/dyn-string.c .
cp ../gcc-$new_gcc_revision/libiberty/d-demangle.c .
+cp ../gcc-$new_gcc_revision/libiberty/rust-demangle.c .
cp ../gcc-$new_gcc_revision/libiberty/safe-ctype.c .
cd ..
diff --git a/auxprogs/valgrind-di-server.c b/auxprogs/valgrind-di-server.c
index 1715a55..85963f5 100644
--- a/auxprogs/valgrind-di-server.c
+++ b/auxprogs/valgrind-di-server.c
@@ -17,7 +17,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2013-2015 Mozilla Foundation
+ Copyright (C) 2013-2017 Mozilla Foundation
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/auxprogs/valgrind-listener.c b/auxprogs/valgrind-listener.c
index d56c74e..b092536 100644
--- a/auxprogs/valgrind-listener.c
+++ b/auxprogs/valgrind-listener.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/cachegrind/Makefile.in b/cachegrind/Makefile.in
index d20883d..35d8182 100644
--- a/cachegrind/Makefile.in
+++ b/cachegrind/Makefile.in
@@ -333,6 +333,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -504,6 +505,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -514,6 +516,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -588,8 +591,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -634,7 +635,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
@@ -712,9 +712,6 @@
-static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \
@FLAG_M64@
-TOOL_LDFLAGS_TILEGX_LINUX = \
- $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-
TOOL_LDFLAGS_X86_SOLARIS = \
$(TOOL_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
@@ -769,9 +766,6 @@
LIBREPLACEMALLOC_MIPS64_LINUX = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a
-LIBREPLACEMALLOC_TILEGX_LINUX = \
- $(top_builddir)/coregrind/libreplacemalloc_toolpreload-tilegx-linux.a
-
LIBREPLACEMALLOC_X86_SOLARIS = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-solaris.a
@@ -834,11 +828,6 @@
$(LIBREPLACEMALLOC_MIPS64_LINUX) \
-Wl,--no-whole-archive
-LIBREPLACEMALLOC_LDFLAGS_TILEGX_LINUX = \
- -Wl,--whole-archive \
- $(LIBREPLACEMALLOC_TILEGX_LINUX) \
- -Wl,--no-whole-archive
-
LIBREPLACEMALLOC_LDFLAGS_X86_SOLARIS = \
-Wl,--whole-archive \
$(LIBREPLACEMALLOC_X86_SOLARIS) \
diff --git a/cachegrind/cg_annotate.in b/cachegrind/cg_annotate.in
index 69365e8..fa0468e 100644
--- a/cachegrind/cg_annotate.in
+++ b/cachegrind/cg_annotate.in
@@ -7,7 +7,7 @@
# This file is part of Cachegrind, a Valgrind tool for cache
# profiling programs.
#
-# Copyright (C) 2002-2015 Nicholas Nethercote
+# Copyright (C) 2002-2017 Nicholas Nethercote
# njn@valgrind.org
#
# This program is free software; you can redistribute it and/or
@@ -158,7 +158,7 @@
-I<d> --include=<d> add <d> to list of directories to search for
source files
- cg_annotate is Copyright (C) 2002-2015 Nicholas Nethercote.
+ cg_annotate is Copyright (C) 2002-2017 Nicholas Nethercote.
and licensed under the GNU General Public License, version 2.
Bug reports, feedback, admiration, abuse, etc, to: njn\@valgrind.org.
diff --git a/cachegrind/cg_arch.c b/cachegrind/cg_arch.c
index 08558be..bf98ab0 100644
--- a/cachegrind/cg_arch.c
+++ b/cachegrind/cg_arch.c
@@ -6,7 +6,7 @@
This file is part of Cachegrind, a Valgrind tool for cache
profiling programs.
- Copyright (C) 2011-2015 Nicholas Nethercote
+ Copyright (C) 2011-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -477,13 +477,6 @@
*D1c = (cache_t) { 65536, 2, 64 };
*LLc = (cache_t) { 262144, 8, 64 };
-#elif defined(VGA_tilegx)
-
- // Set caches to default for Tilegx.
- *I1c = (cache_t) { 0x8000, 2, 64 };
- *D1c = (cache_t) { 0x8000, 2, 64 };
- *LLc = (cache_t) { 0x40000, 8, 64 };
-
#else
#error "Unknown arch"
diff --git a/cachegrind/cg_arch.h b/cachegrind/cg_arch.h
index 910a9b1..b813bb7 100644
--- a/cachegrind/cg_arch.h
+++ b/cachegrind/cg_arch.h
@@ -7,7 +7,7 @@
This file is part of Cachegrind, a Valgrind tool for cache
profiling programs.
- Copyright (C) 2002-2015 Nicholas Nethercote
+ Copyright (C) 2002-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
diff --git a/cachegrind/cg_branchpred.c b/cachegrind/cg_branchpred.c
index a347345..24c8fb2 100644
--- a/cachegrind/cg_branchpred.c
+++ b/cachegrind/cg_branchpred.c
@@ -7,7 +7,7 @@
This file is part of Cachegrind, a Valgrind tool for cache
profiling programs.
- Copyright (C) 2002-2015 Nicholas Nethercote
+ Copyright (C) 2002-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -51,8 +51,6 @@
# define N_IADDR_LO_ZERO_BITS 0
#elif defined(VGA_s390x) || defined(VGA_arm)
# define N_IADDR_LO_ZERO_BITS 1
-#elif defined(VGA_tilegx)
-# define N_IADDR_LO_ZERO_BITS 3
#else
# error "Unsupported architecture"
#endif
diff --git a/cachegrind/cg_diff.in b/cachegrind/cg_diff.in
index 395460b..b093d6f 100755
--- a/cachegrind/cg_diff.in
+++ b/cachegrind/cg_diff.in
@@ -7,7 +7,7 @@
# This file is part of Cachegrind, a Valgrind tool for cache
# profiling programs.
#
-# Copyright (C) 2002-2015 Nicholas Nethercote
+# Copyright (C) 2002-2017 Nicholas Nethercote
# njn@valgrind.org
#
# This program is free software; you can redistribute it and/or
@@ -52,7 +52,7 @@
to filenames, eg. --mod-filename='s/prog[0-9]/projN/'
--mod-funcname=<expr> like --mod-filename, but applied to function names
- cg_diff is Copyright (C) 2002-2015 Nicholas Nethercote.
+ cg_diff is Copyright (C) 2002-2017 Nicholas Nethercote.
and licensed under the GNU General Public License, version 2.
Bug reports, feedback, admiration, abuse, etc, to: njn\@valgrind.org.
diff --git a/cachegrind/cg_main.c b/cachegrind/cg_main.c
index 8a21bf2..5d44667 100644
--- a/cachegrind/cg_main.c
+++ b/cachegrind/cg_main.c
@@ -8,7 +8,7 @@
This file is part of Cachegrind, a Valgrind tool for cache
profiling programs.
- Copyright (C) 2002-2015 Nicholas Nethercote
+ Copyright (C) 2002-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -294,7 +294,7 @@
* As this can be detected at instrumentation time, and results
* in faster simulation, special-casing is benefical.
*
- * Abbrevations used in var/function names:
+ * Abbreviations used in var/function names:
* IrNoX - instruction read does not cross cache lines
* IrGen - generic instruction read; not detected as IrNoX
* Ir - not known / not important whether it is an IrNoX
@@ -1783,7 +1783,7 @@
VG_(details_version) (NULL);
VG_(details_description) ("a cache and branch-prediction profiler");
VG_(details_copyright_author)(
- "Copyright (C) 2002-2015, and GNU GPL'd, by Nicholas Nethercote et al.");
+ "Copyright (C) 2002-2017, and GNU GPL'd, by Nicholas Nethercote et al.");
VG_(details_bug_reports_to) (VG_BUGS_TO);
VG_(details_avg_translation_sizeB) ( 500 );
diff --git a/cachegrind/cg_merge.c b/cachegrind/cg_merge.c
index b17b1ea..b53cbe4 100644
--- a/cachegrind/cg_merge.c
+++ b/cachegrind/cg_merge.c
@@ -8,11 +8,11 @@
This file is part of Cachegrind, a Valgrind tool for cache
profiling programs.
- Copyright (C) 2002-2015 Nicholas Nethercote
+ Copyright (C) 2002-2017 Nicholas Nethercote
njn@valgrind.org
AVL tree code derived from
- ANSI C Library for maintainance of AVL Balanced Trees
+ ANSI C Library for maintenance of AVL Balanced Trees
(C) 2000 Daniel Nagy, Budapest University of Technology and Economics
Released under GNU General Public License (GPL) version 2
@@ -1006,7 +1006,7 @@
/* forward */
static Bool avl_removeroot_wrk(AvlNode** t, Word(*kCmp)(Word,Word));
-/* Swing to the left. Warning: no balance maintainance. */
+/* Swing to the left. Warning: no balance maintenance. */
static void avl_swl ( AvlNode** root )
{
AvlNode* a = *root;
@@ -1016,7 +1016,7 @@
b->left = a;
}
-/* Swing to the right. Warning: no balance maintainance. */
+/* Swing to the right. Warning: no balance maintenance. */
static void avl_swr ( AvlNode** root )
{
AvlNode* a = *root;
@@ -1026,7 +1026,7 @@
b->right = a;
}
-/* Balance maintainance after especially nasty swings. */
+/* Balance maintenance after especially nasty swings. */
static void avl_nasty ( AvlNode* root )
{
switch (root->balance) {
diff --git a/cachegrind/cg_sim.c b/cachegrind/cg_sim.c
index 7edd18e..7a8b3bf 100644
--- a/cachegrind/cg_sim.c
+++ b/cachegrind/cg_sim.c
@@ -7,7 +7,7 @@
This file is part of Cachegrind, a Valgrind tool for cache
profiling programs.
- Copyright (C) 2002-2015 Nicholas Nethercote
+ Copyright (C) 2002-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
diff --git a/cachegrind/tests/Makefile.in b/cachegrind/tests/Makefile.in
index dcd4af4..936d46b 100644
--- a/cachegrind/tests/Makefile.in
+++ b/cachegrind/tests/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -295,6 +295,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -465,6 +466,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -475,6 +477,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -549,8 +552,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -595,7 +596,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/cachegrind/tests/x86/Makefile.in b/cachegrind/tests/x86/Makefile.in
index 44fe65b..3858924 100644
--- a/cachegrind/tests/x86/Makefile.in
+++ b/cachegrind/tests/x86/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -243,6 +243,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -413,6 +414,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -423,6 +425,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -497,8 +500,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -543,7 +544,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/callgrind/Makefile.in b/callgrind/Makefile.in
index ce86b54..c6f9bcc 100644
--- a/callgrind/Makefile.in
+++ b/callgrind/Makefile.in
@@ -345,6 +345,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -516,6 +517,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -526,6 +528,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -600,8 +603,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -646,7 +647,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
@@ -724,9 +724,6 @@
-static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \
@FLAG_M64@
-TOOL_LDFLAGS_TILEGX_LINUX = \
- $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-
TOOL_LDFLAGS_X86_SOLARIS = \
$(TOOL_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
@@ -781,9 +778,6 @@
LIBREPLACEMALLOC_MIPS64_LINUX = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a
-LIBREPLACEMALLOC_TILEGX_LINUX = \
- $(top_builddir)/coregrind/libreplacemalloc_toolpreload-tilegx-linux.a
-
LIBREPLACEMALLOC_X86_SOLARIS = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-solaris.a
@@ -846,11 +840,6 @@
$(LIBREPLACEMALLOC_MIPS64_LINUX) \
-Wl,--no-whole-archive
-LIBREPLACEMALLOC_LDFLAGS_TILEGX_LINUX = \
- -Wl,--whole-archive \
- $(LIBREPLACEMALLOC_TILEGX_LINUX) \
- -Wl,--no-whole-archive
-
LIBREPLACEMALLOC_LDFLAGS_X86_SOLARIS = \
-Wl,--whole-archive \
$(LIBREPLACEMALLOC_X86_SOLARIS) \
diff --git a/callgrind/bb.c b/callgrind/bb.c
index ceea5b9..b5459cf 100644
--- a/callgrind/bb.c
+++ b/callgrind/bb.c
@@ -6,7 +6,7 @@
/*
This file is part of Callgrind, a Valgrind tool for call tracing.
- Copyright (C) 2002-2015, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2017, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/callgrind/bbcc.c b/callgrind/bbcc.c
index e9426e5..5716b07 100644
--- a/callgrind/bbcc.c
+++ b/callgrind/bbcc.c
@@ -6,7 +6,7 @@
/*
This file is part of Callgrind, a Valgrind tool for call tracing.
- Copyright (C) 2002-2015, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2017, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/callgrind/callgrind.h b/callgrind/callgrind.h
index 33b0e29..f078cc8 100644
--- a/callgrind/callgrind.h
+++ b/callgrind/callgrind.h
@@ -13,7 +13,7 @@
This file is part of callgrind, a valgrind tool for cache simulation
and call tree tracing.
- Copyright (C) 2003-2015 Josef Weidendorfer. All rights reserved.
+ Copyright (C) 2003-2017 Josef Weidendorfer. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
@@ -109,7 +109,7 @@
/* Start full callgrind instrumentation if not already switched on.
When cache simulation is done, it will flush the simulated cache;
- this will lead to an artifical cache warmup phase afterwards with
+ this will lead to an artificial cache warmup phase afterwards with
cache misses which would not have happened in reality. */
#define CALLGRIND_START_INSTRUMENTATION \
VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__START_INSTRUMENTATION, \
diff --git a/callgrind/callgrind_annotate.in b/callgrind/callgrind_annotate.in
index 82f6f05..4f28129 100644
--- a/callgrind/callgrind_annotate.in
+++ b/callgrind/callgrind_annotate.in
@@ -8,11 +8,11 @@
# This file is part of Callgrind, a cache-simulator and call graph
# tracer built on Valgrind.
#
-# Copyright (C) 2003-2015 Josef Weidendorfer
+# Copyright (C) 2003-2017 Josef Weidendorfer
# Josef.Weidendorfer@gmx.de
#
# This file is based heavily on cg_annotate, part of Valgrind.
-# Copyright (C) 2002-2015 Nicholas Nethercote
+# Copyright (C) 2002-2017 Nicholas Nethercote
# njn@valgrind.org
#
# This program is free software; you can redistribute it and/or
@@ -429,6 +429,9 @@
$has_line = ($positions =~ /line/);
$has_addr = ($positions =~ /(addr|instr)/);
}
+ elsif (/^event:\s+.*$/) {
+ # ignore lines giving a long name to an event
+ }
elsif (/^events:\s+(.*)$/) {
$events = $1;
@@ -1216,9 +1219,17 @@
if ($did_annotations) {
my $percent_printed_CC;
foreach (my $i = 0; $i < @$summary_CC; $i++) {
- $percent_printed_CC->[$i] =
- sprintf("%.0f",
- $printed_totals_CC->[$i] / $summary_CC->[$i] * 100);
+ # Some files (in particular the files produced by --xtree-memory)
+ # have non additive self costs, so have a special case for these
+ # to print all functions and also to avoid a division by 0.
+ if ($summary_CC->[$i] == 0
+ || $printed_totals_CC->[$i] > $summary_CC->[$i]) {
+ $percent_printed_CC->[$i] = "100";
+ } else {
+ $percent_printed_CC->[$i] =
+ sprintf("%.0f",
+ $printed_totals_CC->[$i] / $summary_CC->[$i] * 100);
+ }
}
my $pp_CC_col_widths = compute_CC_col_widths($percent_printed_CC);
print($fancy);
diff --git a/callgrind/callgrind_control.in b/callgrind/callgrind_control.in
index 7660259..4c57ccf 100644
--- a/callgrind/callgrind_control.in
+++ b/callgrind/callgrind_control.in
@@ -7,7 +7,7 @@
# This file is part of Callgrind, a cache-simulator and call graph
# tracer built on Valgrind.
#
-# Copyright (C) 2003-2015 Josef Weidendorfer <Josef.Weidendorfer@gmx.de>
+# Copyright (C) 2003-2017 Josef Weidendorfer <Josef.Weidendorfer@gmx.de>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
diff --git a/callgrind/callstack.c b/callgrind/callstack.c
index abe5126..3b06db1 100644
--- a/callgrind/callstack.c
+++ b/callgrind/callstack.c
@@ -6,7 +6,7 @@
/*
This file is part of Callgrind, a Valgrind tool for call tracing.
- Copyright (C) 2002-2015, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2017, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/callgrind/clo.c b/callgrind/clo.c
index fa76f1e..b26ddd6 100644
--- a/callgrind/clo.c
+++ b/callgrind/clo.c
@@ -2,10 +2,10 @@
This file is part of Callgrind, a Valgrind tool for call graph
profiling programs.
- Copyright (C) 2002-2015, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2017, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This tool is derived from and contains lot of code from Cachegrind
- Copyright (C) 2002-2015 Nicholas Nethercote (njn@valgrind.org)
+ Copyright (C) 2002-2017 Nicholas Nethercote (njn@valgrind.org)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/callgrind/context.c b/callgrind/context.c
index 33f7386..a7532b6 100644
--- a/callgrind/context.c
+++ b/callgrind/context.c
@@ -6,7 +6,7 @@
/*
This file is part of Callgrind, a Valgrind tool for call tracing.
- Copyright (C) 2002-2015, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2017, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/callgrind/costs.c b/callgrind/costs.c
index 5071170..32d8d87 100644
--- a/callgrind/costs.c
+++ b/callgrind/costs.c
@@ -6,7 +6,7 @@
/*
This file is part of Callgrind, a Valgrind tool for call tracing.
- Copyright (C) 2002-2015, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2017, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/callgrind/costs.h b/callgrind/costs.h
index 25ad7c3..de88f5c 100644
--- a/callgrind/costs.h
+++ b/callgrind/costs.h
@@ -6,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 Josef Weidendorfer
+ Copyright (C) 2004-2017 Josef Weidendorfer
josef.weidendorfer@gmx.de
This program is free software; you can redistribute it and/or
diff --git a/callgrind/debug.c b/callgrind/debug.c
index 6e8215c..4a8b9b0 100644
--- a/callgrind/debug.c
+++ b/callgrind/debug.c
@@ -2,10 +2,10 @@
This file is part of Callgrind, a Valgrind tool for call graph
profiling programs.
- Copyright (C) 2002-2015, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2017, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This tool is derived from and contains lot of code from Cachegrind
- Copyright (C) 2002-2015 Nicholas Nethercote (njn@valgrind.org)
+ Copyright (C) 2002-2017 Nicholas Nethercote (njn@valgrind.org)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/callgrind/docs/cl-format.xml b/callgrind/docs/cl-format.xml
index 182b199..77fe5df 100644
--- a/callgrind/docs/cl-format.xml
+++ b/callgrind/docs/cl-format.xml
@@ -6,10 +6,7 @@
<chapter id="cl-format" xreflabel="Callgrind Format Specification">
<title>Callgrind Format Specification</title>
-<para>This chapter describes the Callgrind Profile Format, Version 1.</para>
-
-<para>A synonymous name is "Calltree Profile Format". These names actually mean
-the same since Callgrind was previously named Calltree.</para>
+<para>This chapter describes the Callgrind Format, Version 1.</para>
<para>The format description is meant for the user to be able to understand the
file contents; but more important, it is given for authors of measurement or
@@ -29,6 +26,10 @@
<sect2 id="cl-format.overview.basics" xreflabel="Basic Structure">
<title>Basic Structure</title>
+<para>To uniquely specify that a file is a callgrind profile, it
+should add "# callgrind format" as first line. This is optional but
+recommended for easy format detection.</para>
+
<para>Each file has a header part of an arbitrary number of lines of the
format "key: value". After the header, lines specifying profile costs
follow. Everywhere, comments on own lines starting with '#' are allowed.
@@ -58,7 +59,8 @@
However, any profiling tool could use the format described in this chapter.</para>
<para>
-<screen>events: Cycles Instructions Flops
+<screen># callgrind format
+events: Cycles Instructions Flops
fl=file.f
fn=main
15 90 14 2
@@ -130,7 +132,9 @@
<function>main</function> calls <function>func1</function> once and
<function>func2</function> 3 times. <function>func1</function> calls
<function>func2</function> 2 times.
-<screen>events: Instructions
+
+<screen># callgrind format
+events: Instructions
fl=file1.c
fn=main
@@ -186,8 +190,9 @@
mapping. There is a separate ID mapping for each position specification,
i.e. you can use ID 1 for both a file name and a symbol name.</para>
-<para>With string compression, the example from 1.4 looks like this:
-<screen>events: Instructions
+<para>With string compression, the example from above looks like this:
+<screen># callgrind format
+events: Instructions
fl=(1) file1.c
fn=(1) main
@@ -216,7 +221,8 @@
everywhere in the file without any negative consequence. Especially, you can
define name compression mappings directly after the header, and before any cost
lines. Thus, the above example can also be written as
-<screen>events: Instructions
+<screen># callgrind format
+events: Instructions
# define file ID mapping
fl=(1) file1.c
@@ -256,7 +262,8 @@
absolute and relative subposition specifications can be mixed freely.
Assume the following example (subpositions can always be specified
as hexadecimal numbers, beginning with "0x"):
-<screen>positions: instr line
+<screen># callgrind format
+positions: instr line
events: ticks
fn=func
@@ -265,7 +272,8 @@
0x80001238 91 6</screen></para>
<para>With subposition compression, this looks like
-<screen>positions: instr line
+<screen># callgrind format
+positions: instr line
events: ticks
fn=func
@@ -326,7 +334,8 @@
<title>Grammar</title>
<para>
-<screen>ProfileDataFile := FormatVersion? Creator? PartData*</screen>
+<screen>ProfileDataFile := FormatSpec? FormatVersion? Creator? PartData*</screen>
+<screen>FormatSpec := "# callgrind format\n"</screen>
<screen>FormatVersion := "version: 1\n"</screen>
<screen>Creator := "creator:" NoNewLineChar* "\n"</screen>
<screen>PartData := (HeaderLine "\n")+ (BodyLine "\n")+</screen>
@@ -379,7 +388,7 @@
</para>
<para>A profile data file ("ProfileDataFile") starts with basic information
- such as the version and creator information, and then has a list of parts, where
+ such as a format marker, the version and creator information, and then has a list of parts, where
each part has its own header and body. Parts typically are different threads
and/or time spans/phases within a profiled application run.</para>
@@ -396,11 +405,23 @@
<itemizedlist>
<listitem>
+ <para><computeroutput># callgrind format</computeroutput> [Callgrind]</para>
+ <para>This line specifies that the file is a callgrind profile,
+ and it has to be the first line. It was added late to the
+ format (with Valgrind 3.13) and is optional, as all readers also
+ should work with older callgrind profiles not including this line.
+ However, generation of this line is recommended to allow desktop
+ environments and file managers to uniquely detect the format.</para>
+ </listitem>
+
+ <listitem>
<para><computeroutput>version: number</computeroutput> [Callgrind]</para>
<para>This is used to distinguish future profile data formats. A
major version of 0 or 1 is supposed to be upwards compatible with
Cachegrind's format. It is optional; if not appearing, version 1
- is assumed. Otherwise, this has to be the first header line.</para>
+ is assumed. Otherwise, it has to follow directly after the format
+ specification (i.e. be the first line if the optional format
+ specification is skipped).</para>
</listitem>
<listitem>
diff --git a/callgrind/docs/cl-manual.xml b/callgrind/docs/cl-manual.xml
index 508094e..a5f8c4b 100644
--- a/callgrind/docs/cl-manual.xml
+++ b/callgrind/docs/cl-manual.xml
@@ -316,7 +316,7 @@
what is happening within a given function or starting from a given
program phase. To this end, you can disable event aggregation for
uninteresting program parts. While attribution of events to
- functions as well as producing seperate output per program phase
+ functions as well as producing separate output per program phase
can be done by other means (see previous section), there are two
benefits by disabling aggregation. First, this is very
fine-granular (e.g. just for a loop within a function). Second,
@@ -432,7 +432,7 @@
cycles, this does not hold true: callees of a function in a cycle include
the function itself. Therefore, KCachegrind does cycle detection
and skips visualization of any inclusive cost for calls inside
- of cycles. Further, all functions in a cycle are collapsed into artifical
+ of cycles. Further, all functions in a cycle are collapsed into artificial
functions called like <computeroutput>Cycle 1</computeroutput>.</para>
<para>Now, when a program exposes really big cycles (as is
@@ -1194,7 +1194,7 @@
<listitem>
<para>Start full Callgrind instrumentation if not already enabled.
When cache simulation is done, this will flush the simulated cache
- and lead to an artifical cache warmup phase afterwards with
+ and lead to an artificial cache warmup phase afterwards with
cache misses which would not have happened in reality. See also
option <option><xref linkend="opt.instr-atstart"/></option>.</para>
</listitem>
@@ -1257,6 +1257,8 @@
</term>
<listitem>
<para>Sort columns by events A,B,C [event column order].</para>
+ <para>Optionally, each event is followed by a : and a threshold,
+ to specify different thresholds depending on the event.</para>
</listitem>
</varlistentry>
diff --git a/callgrind/dump.c b/callgrind/dump.c
index 8907995..1997c71 100644
--- a/callgrind/dump.c
+++ b/callgrind/dump.c
@@ -6,7 +6,7 @@
/*
This file is part of Callgrind, a Valgrind tool for call tracing.
- Copyright (C) 2002-2015, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2017, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -1215,6 +1215,9 @@
if (!appending) {
+ /* callgrind format specification, has to be on 1st line */
+ VG_(fprintf)(fp, "# callgrind format\n");
+
/* version */
VG_(fprintf)(fp, "version: 1\n");
diff --git a/callgrind/events.c b/callgrind/events.c
index e7ca68e..a3925e9 100644
--- a/callgrind/events.c
+++ b/callgrind/events.c
@@ -6,7 +6,7 @@
/*
This file is part of Callgrind, a Valgrind tool for call tracing.
- Copyright (C) 2002-2015, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2017, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/callgrind/events.h b/callgrind/events.h
index b38b3c3..b45893f 100644
--- a/callgrind/events.h
+++ b/callgrind/events.h
@@ -6,7 +6,7 @@
/*
This file is part of Callgrind, a Valgrind tool for call tracing.
- Copyright (C) 2002-2015, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2017, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/callgrind/fn.c b/callgrind/fn.c
index 2434941..d4c7b24 100644
--- a/callgrind/fn.c
+++ b/callgrind/fn.c
@@ -6,7 +6,7 @@
/*
This file is part of Callgrind, a Valgrind tool for call tracing.
- Copyright (C) 2002-2015, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2017, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -110,7 +110,7 @@
/* _ld_runtime_resolve, located in ld.so, needs special handling:
* The jump at end into the resolved function should not be
* represented as a call (as usually done in callgrind with jumps),
- * but as a return + call. Otherwise, the repeated existance of
+ * but as a return + call. Otherwise, the repeated existence of
* _ld_runtime_resolve in call chains will lead to huge cycles,
* making the profile almost worthless.
*
diff --git a/callgrind/global.h b/callgrind/global.h
index bf511f7..7c5a59c 100644
--- a/callgrind/global.h
+++ b/callgrind/global.h
@@ -6,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2015 Josef Weidendorfer
+ Copyright (C) 2004-2017 Josef Weidendorfer
josef.weidendorfer@gmx.de
This program is free software; you can redistribute it and/or
@@ -347,7 +347,7 @@
* Basic Block Cost Center
*
* On demand, multiple BBCCs will be created for the same BB
- * dependend on command line options and:
+ * dependent on command line options and:
* - current function (it's possible that a BB is executed in the
* context of different functions, e.g. in manual assembler/PLT)
* - current thread ID
diff --git a/callgrind/jumps.c b/callgrind/jumps.c
index dbd4533..2cf30c4 100644
--- a/callgrind/jumps.c
+++ b/callgrind/jumps.c
@@ -6,7 +6,7 @@
/*
This file is part of Callgrind, a Valgrind tool for call tracing.
- Copyright (C) 2002-2015, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2017, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/callgrind/main.c b/callgrind/main.c
index 69b0ddb..ab49272 100644
--- a/callgrind/main.c
+++ b/callgrind/main.c
@@ -8,10 +8,10 @@
This file is part of Callgrind, a Valgrind tool for call graph
profiling programs.
- Copyright (C) 2002-2015, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2017, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This tool is derived from and contains code from Cachegrind
- Copyright (C) 2002-2015 Nicholas Nethercote (njn@valgrind.org)
+ Copyright (C) 2002-2017 Nicholas Nethercote (njn@valgrind.org)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -1975,6 +1975,16 @@
"sp-at-mem-access\n");
}
+ if (CLG_(clo).collect_systime) {
+ VG_(needs_syscall_wrapper)(CLG_(pre_syscalltime),
+ CLG_(post_syscalltime));
+ syscalltime = CLG_MALLOC("cl.main.pci.1",
+ VG_N_THREADS * sizeof syscalltime[0]);
+ for (UInt i = 0; i < VG_N_THREADS; ++i) {
+ syscalltime[i] = 0;
+ }
+ }
+
if (VG_(clo_px_file_backed) != VexRegUpdSpAtMemAccess) {
CLG_DEBUG(1, " Using user specified value for "
"--px-file-backed\n");
@@ -1988,13 +1998,13 @@
VG_(message)(Vg_UserMsg,
"callgrind only works with --vex-iropt-unroll-thresh=0\n"
"=> resetting it back to 0\n");
- VG_(clo_vex_control).iropt_unroll_thresh = 0; // cannot be overriden.
+ VG_(clo_vex_control).iropt_unroll_thresh = 0; // cannot be overridden.
}
if (VG_(clo_vex_control).guest_chase_thresh != 0) {
VG_(message)(Vg_UserMsg,
"callgrind only works with --vex-guest-chase-thresh=0\n"
"=> resetting it back to 0\n");
- VG_(clo_vex_control).guest_chase_thresh = 0; // cannot be overriden.
+ VG_(clo_vex_control).guest_chase_thresh = 0; // cannot be overridden.
}
CLG_DEBUG(1, " dump threads: %s\n", CLG_(clo).separate_threads ? "Yes":"No");
@@ -2038,7 +2048,7 @@
VG_(details_name) ("Callgrind");
VG_(details_version) (NULL);
VG_(details_description) ("a call-graph generating cache profiler");
- VG_(details_copyright_author)("Copyright (C) 2002-2015, and GNU GPL'd, "
+ VG_(details_copyright_author)("Copyright (C) 2002-2017, and GNU GPL'd, "
"by Josef Weidendorfer et al.");
VG_(details_bug_reports_to) (VG_BUGS_TO);
VG_(details_avg_translation_sizeB) ( 500 );
@@ -2047,8 +2057,8 @@
= VG_(clo_px_file_backed)
= VexRegUpdSpAtMemAccess; // overridable by the user.
- VG_(clo_vex_control).iropt_unroll_thresh = 0; // cannot be overriden.
- VG_(clo_vex_control).guest_chase_thresh = 0; // cannot be overriden.
+ VG_(clo_vex_control).iropt_unroll_thresh = 0; // cannot be overridden.
+ VG_(clo_vex_control).guest_chase_thresh = 0; // cannot be overridden.
VG_(basic_tool_funcs) (CLG_(post_clo_init),
CLG_(instrument),
@@ -2063,8 +2073,6 @@
VG_(needs_client_requests)(CLG_(handle_client_request));
VG_(needs_print_stats) (clg_print_stats);
- VG_(needs_syscall_wrapper)(CLG_(pre_syscalltime),
- CLG_(post_syscalltime));
VG_(track_start_client_code) ( & clg_start_client_code_callback );
VG_(track_pre_deliver_signal) ( & CLG_(pre_signal) );
@@ -2072,11 +2080,6 @@
CLG_(set_clo_defaults)();
- syscalltime = CLG_MALLOC("cl.main.pci.1",
- VG_N_THREADS * sizeof syscalltime[0]);
- for (UInt i = 0; i < VG_N_THREADS; ++i) {
- syscalltime[i] = 0;
- }
}
VG_DETERMINE_INTERFACE_VERSION(CLG_(pre_clo_init))
diff --git a/callgrind/sim.c b/callgrind/sim.c
index 8fedbea..28012c8 100644
--- a/callgrind/sim.c
+++ b/callgrind/sim.c
@@ -7,10 +7,10 @@
This file is part of Callgrind, a Valgrind tool for call graph
profiling programs.
- Copyright (C) 2003-2015, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2003-2017, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This tool is derived from and contains code from Cachegrind
- Copyright (C) 2002-2015 Nicholas Nethercote (njn@valgrind.org)
+ Copyright (C) 2002-2017 Nicholas Nethercote (njn@valgrind.org)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/callgrind/tests/Makefile.in b/callgrind/tests/Makefile.in
index 9ed6df1..a796786 100644
--- a/callgrind/tests/Makefile.in
+++ b/callgrind/tests/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -284,6 +284,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -454,6 +455,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -464,6 +466,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -538,8 +541,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -584,7 +585,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/callgrind/threads.c b/callgrind/threads.c
index 2a38fc1..2ada286 100644
--- a/callgrind/threads.c
+++ b/callgrind/threads.c
@@ -6,7 +6,7 @@
/*
This file is part of Callgrind, a Valgrind tool for call tracing.
- Copyright (C) 2002-2015, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2017, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/config.h b/config.h
index 68228cc..858b447 100644
--- a/config.h
+++ b/config.h
@@ -95,10 +95,10 @@
#endif
/* Define to 1 if the system has the type `Elf32_Chdr'. */
-/* #undef HAVE_ELF32_CHDR */
+//#define HAVE_ELF32_CHDR 1
/* Define to 1 if the system has the type `Elf64_Chdr'. */
-/* #undef HAVE_ELF64_CHDR */
+//#define HAVE_ELF64_CHDR 1
/* Define to 1 if you have the <endian.h> header file. */
#define HAVE_ENDIAN_H 1
@@ -281,6 +281,9 @@
/* Define to 1 if you have the <sys/klog.h> header file. */
#define HAVE_SYS_KLOG_H 1
+/* Define to 1 if you have the <sys/lgrp_user_impl.h> header file. */
+/* #undef HAVE_SYS_LGRP_USER_IMPL_H */
+
/* Define to 1 if you have the <sys/param.h> header file. */
#define HAVE_SYS_PARAM_H 1
@@ -326,6 +329,9 @@
/* Define to 1 if you have the `utimensat' function. */
#define HAVE_UTIMENSAT 1
+/* Define to 1 if you're using Musl libc */
+/* #undef MUSL_LIBC */
+
/* Name of package */
#define PACKAGE "valgrind"
@@ -336,7 +342,7 @@
#define PACKAGE_NAME "Valgrind"
/* Define to the full name and version of this package. */
-#define PACKAGE_STRING "Valgrind 3.12.0"
+#define PACKAGE_STRING "Valgrind 3.13.0"
/* Define to the one symbol short name of this package. */
#define PACKAGE_TARNAME "valgrind"
@@ -345,7 +351,7 @@
#define PACKAGE_URL ""
/* Define to the version of this package. */
-#define PACKAGE_VERSION "3.12.0"
+#define PACKAGE_VERSION "3.13.0"
/* Define to 1 if you have the `A_GETSTAT' and `A_SETSTAT' constants. */
/* #undef SOLARIS_AUDITON_STAT */
@@ -459,7 +465,7 @@
#define TIME_WITH_SYS_TIME 1
/* Version number of package */
-#define VERSION "3.12.0"
+#define VERSION "3.13.0"
/* Temporary files directory */
#ifdef __ANDROID__
diff --git a/config.h.in b/config.h.in
index 246fe80..8b04c06 100644
--- a/config.h.in
+++ b/config.h.in
@@ -268,6 +268,9 @@
/* Define to 1 if you have the <sys/klog.h> header file. */
#undef HAVE_SYS_KLOG_H
+/* Define to 1 if you have the <sys/lgrp_user_impl.h> header file. */
+#undef HAVE_SYS_LGRP_USER_IMPL_H
+
/* Define to 1 if you have the <sys/param.h> header file. */
#undef HAVE_SYS_PARAM_H
@@ -313,6 +316,9 @@
/* Define to 1 if you have the `utimensat' function. */
#undef HAVE_UTIMENSAT
+/* Define to 1 if you're using Musl libc */
+#undef MUSL_LIBC
+
/* Name of package */
#undef PACKAGE
diff --git a/configure b/configure
index 0f9e645..c2e319d 100755
--- a/configure
+++ b/configure
@@ -1,6 +1,6 @@
#! /bin/sh
# Guess values for system-dependent variables and create Makefiles.
-# Generated by GNU Autoconf 2.69 for Valgrind 3.12.0.
+# Generated by GNU Autoconf 2.69 for Valgrind 3.13.0.
#
# Report bugs to <valgrind-users@lists.sourceforge.net>.
#
@@ -580,8 +580,8 @@
# Identity of this package.
PACKAGE_NAME='Valgrind'
PACKAGE_TARNAME='valgrind'
-PACKAGE_VERSION='3.12.0'
-PACKAGE_STRING='Valgrind 3.12.0'
+PACKAGE_VERSION='3.13.0'
+PACKAGE_STRING='Valgrind 3.13.0'
PACKAGE_BUGREPORT='valgrind-users@lists.sourceforge.net'
PACKAGE_URL=''
@@ -726,6 +726,8 @@
BUILD_IFUNC_TESTS_TRUE
BUILD_MOVBE_TESTS_FALSE
BUILD_MOVBE_TESTS_TRUE
+BUILD_ADX_TESTS_FALSE
+BUILD_ADX_TESTS_TRUE
BUILD_MPX_TESTS_FALSE
BUILD_MPX_TESTS_TRUE
BUILD_FMA_TESTS_FALSE
@@ -758,6 +760,7 @@
BUILD_SSE3_TESTS_TRUE
FLAG_NO_BUILD_ID
FLAG_T_TEXT
+FLAG_NO_PIE
HAVE_ASM_CONSTRAINT_P_FALSE
HAVE_ASM_CONSTRAINT_P_TRUE
HAVE_NESTED_FUNCTIONS_FALSE
@@ -869,8 +872,6 @@
VGCONF_PLATFORMS_INCLUDE_AMD64_DARWIN_TRUE
VGCONF_PLATFORMS_INCLUDE_X86_DARWIN_FALSE
VGCONF_PLATFORMS_INCLUDE_X86_DARWIN_TRUE
-VGCONF_PLATFORMS_INCLUDE_TILEGX_LINUX_FALSE
-VGCONF_PLATFORMS_INCLUDE_TILEGX_LINUX_TRUE
VGCONF_PLATFORMS_INCLUDE_MIPS64_LINUX_FALSE
VGCONF_PLATFORMS_INCLUDE_MIPS64_LINUX_TRUE
VGCONF_PLATFORMS_INCLUDE_MIPS32_LINUX_FALSE
@@ -891,8 +892,6 @@
VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE
VGCONF_PLATFORMS_INCLUDE_X86_LINUX_FALSE
VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE
-VGCONF_ARCHS_INCLUDE_TILEGX_FALSE
-VGCONF_ARCHS_INCLUDE_TILEGX_TRUE
VGCONF_ARCHS_INCLUDE_MIPS64_FALSE
VGCONF_ARCHS_INCLUDE_MIPS64_TRUE
VGCONF_ARCHS_INCLUDE_MIPS32_FALSE
@@ -1601,7 +1600,7 @@
# Omit some internal or obsolete options to make the list less imposing.
# This message is too long to be a string in the A/UX 3.1 sh.
cat <<_ACEOF
-\`configure' configures Valgrind 3.12.0 to adapt to many kinds of systems.
+\`configure' configures Valgrind 3.13.0 to adapt to many kinds of systems.
Usage: $0 [OPTION]... [VAR=VALUE]...
@@ -1671,7 +1670,7 @@
if test -n "$ac_init_help"; then
case $ac_init_help in
- short | recursive ) echo "Configuration of Valgrind 3.12.0:";;
+ short | recursive ) echo "Configuration of Valgrind 3.13.0:";;
esac
cat <<\_ACEOF
@@ -1781,7 +1780,7 @@
test -n "$ac_init_help" && exit $ac_status
if $ac_init_version; then
cat <<\_ACEOF
-Valgrind configure 3.12.0
+Valgrind configure 3.13.0
generated by GNU Autoconf 2.69
Copyright (C) 2012 Free Software Foundation, Inc.
@@ -2345,7 +2344,7 @@
This file contains any messages produced by compilers while
running configure, to aid debugging if configure makes a mistake.
-It was created by Valgrind $as_me 3.12.0, which was
+It was created by Valgrind $as_me 3.13.0, which was
generated by GNU Autoconf 2.69. Invocation command line was
$ $0 $@
@@ -3214,7 +3213,7 @@
# Define the identity of the package.
PACKAGE='valgrind'
- VERSION='3.12.0'
+ VERSION='3.13.0'
cat >>confdefs.h <<_ACEOF
@@ -5580,10 +5579,10 @@
# Power PC returns powerpc for Big Endian. This was not changed when Little
# Endian support was added to the 64-bit architecture. The 64-bit Little
# Endian systems explicitly state le in the host_cpu. For clarity in the
-# Valgrind code, the ARCH_MAX name will state LE or BE for the endianess of
+# Valgrind code, the ARCH_MAX name will state LE or BE for the endianness of
# the 64-bit system. Big Endian is the only mode supported on 32-bit Power PC.
# The abreviation PPC or ppc refers to 32-bit and 64-bit systems with either
-# Endianess. The name PPC64 or ppc64 to 64-bit systems of either Endianess.
+# Endianness. The name PPC64 or ppc64 to 64-bit systems of either Endianness.
# The names ppc64be or PPC64BE refer to only 64-bit systems that are Big
# Endian. Similarly, ppc64le or PPC64LE refer to only 64-bit systems that are
# Little Endian.
@@ -5670,12 +5669,6 @@
ARCH_MAX="mips64"
;;
- tilegx)
- { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${host_cpu})" >&5
-$as_echo "ok (${host_cpu})" >&6; }
- ARCH_MAX="tilegx"
- ;;
-
*)
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: no (${host_cpu})" >&5
$as_echo "no (${host_cpu})" >&6; }
@@ -6021,8 +6014,8 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="X86_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
valt_load_address_sec_norml="0xUNSET"
valt_load_address_sec_inner="0xUNSET"
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
@@ -6036,24 +6029,24 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="AMD64_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
elif test x$vg_cv_only32bit = xyes; then
VGCONF_ARCH_PRI="x86"
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="X86_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
else
VGCONF_ARCH_PRI="amd64"
VGCONF_ARCH_SEC="x86"
VGCONF_PLATFORM_PRI_CAPS="AMD64_LINUX"
VGCONF_PLATFORM_SEC_CAPS="X86_LINUX"
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
- valt_load_address_sec_norml="0x38000000"
- valt_load_address_sec_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
+ valt_load_address_sec_norml="0x58000000"
+ valt_load_address_sec_inner="0x38000000"
fi
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
$as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
@@ -6063,8 +6056,8 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="PPC32_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
valt_load_address_sec_norml="0xUNSET"
valt_load_address_sec_inner="0xUNSET"
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
@@ -6078,24 +6071,24 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="PPC64BE_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
elif test x$vg_cv_only32bit = xyes; then
VGCONF_ARCH_PRI="ppc32"
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="PPC32_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
else
VGCONF_ARCH_PRI="ppc64be"
VGCONF_ARCH_SEC="ppc32"
VGCONF_PLATFORM_PRI_CAPS="PPC64BE_LINUX"
VGCONF_PLATFORM_SEC_CAPS="PPC32_LINUX"
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
- valt_load_address_sec_norml="0x38000000"
- valt_load_address_sec_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
+ valt_load_address_sec_norml="0x58000000"
+ valt_load_address_sec_inner="0x38000000"
fi
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
$as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
@@ -6108,8 +6101,8 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="PPC64LE_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
$as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
;;
@@ -6127,25 +6120,25 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="AMD64_DARWIN"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x138000000"
- valt_load_address_pri_inner="0x128000000"
+ valt_load_address_pri_norml="0x158000000"
+ valt_load_address_pri_inner="0x138000000"
elif test x$vg_cv_only32bit = xyes; then
VGCONF_ARCH_PRI="x86"
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="X86_DARWIN"
VGCONF_PLATFORM_SEC_CAPS=""
VGCONF_ARCH_PRI_CAPS="x86"
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
else
VGCONF_ARCH_PRI="amd64"
VGCONF_ARCH_SEC="x86"
VGCONF_PLATFORM_PRI_CAPS="AMD64_DARWIN"
VGCONF_PLATFORM_SEC_CAPS="X86_DARWIN"
- valt_load_address_pri_norml="0x138000000"
- valt_load_address_pri_inner="0x128000000"
- valt_load_address_sec_norml="0x38000000"
- valt_load_address_sec_inner="0x28000000"
+ valt_load_address_pri_norml="0x158000000"
+ valt_load_address_pri_inner="0x138000000"
+ valt_load_address_sec_norml="0x58000000"
+ valt_load_address_sec_inner="0x38000000"
fi
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
$as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
@@ -6154,8 +6147,8 @@
VGCONF_ARCH_PRI="arm"
VGCONF_PLATFORM_PRI_CAPS="ARM_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
valt_load_address_sec_norml="0xUNSET"
valt_load_address_sec_inner="0xUNSET"
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${host_cpu}-${host_os})" >&5
@@ -6169,24 +6162,24 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="ARM64_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
elif test x$vg_cv_only32bit = xyes; then
VGCONF_ARCH_PRI="arm"
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="ARM_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
else
VGCONF_ARCH_PRI="arm64"
VGCONF_ARCH_SEC="arm"
VGCONF_PLATFORM_PRI_CAPS="ARM64_LINUX"
VGCONF_PLATFORM_SEC_CAPS="ARM_LINUX"
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
- valt_load_address_sec_norml="0x38000000"
- valt_load_address_sec_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
+ valt_load_address_sec_norml="0x58000000"
+ valt_load_address_sec_inner="0x38000000"
fi
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
$as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
@@ -6209,8 +6202,8 @@
VGCONF_ARCH_PRI="mips32"
VGCONF_PLATFORM_PRI_CAPS="MIPS32_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
valt_load_address_sec_norml="0xUNSET"
valt_load_address_sec_inner="0xUNSET"
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
@@ -6220,20 +6213,8 @@
VGCONF_ARCH_PRI="mips64"
VGCONF_PLATFORM_PRI_CAPS="MIPS64_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
- valt_load_address_sec_norml="0xUNSET"
- valt_load_address_sec_inner="0xUNSET"
- { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
-$as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
- ;;
- tilegx-linux)
- VGCONF_ARCH_PRI="tilegx"
- VGCONF_ARCH_SEC=""
- VGCONF_PLATFORM_PRI_CAPS="TILEGX_LINUX"
- VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
valt_load_address_sec_norml="0xUNSET"
valt_load_address_sec_inner="0xUNSET"
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
@@ -6244,8 +6225,8 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="X86_SOLARIS"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
valt_load_address_sec_norml="0xUNSET"
valt_load_address_sec_inner="0xUNSET"
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
@@ -6259,24 +6240,24 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="AMD64_SOLARIS"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
elif test x$vg_cv_only32bit = xyes; then
VGCONF_ARCH_PRI="x86"
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="X86_SOLARIS"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
else
VGCONF_ARCH_PRI="amd64"
VGCONF_ARCH_SEC="x86"
VGCONF_PLATFORM_PRI_CAPS="AMD64_SOLARIS"
VGCONF_PLATFORM_SEC_CAPS="X86_SOLARIS"
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
- valt_load_address_sec_norml="0x38000000"
- valt_load_address_sec_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
+ valt_load_address_sec_norml="0x58000000"
+ valt_load_address_sec_inner="0x38000000"
fi
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
$as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
@@ -6382,14 +6363,6 @@
VGCONF_ARCHS_INCLUDE_MIPS64_FALSE=
fi
- if test x$VGCONF_PLATFORM_PRI_CAPS = xTILEGX_LINUX ; then
- VGCONF_ARCHS_INCLUDE_TILEGX_TRUE=
- VGCONF_ARCHS_INCLUDE_TILEGX_FALSE='#'
-else
- VGCONF_ARCHS_INCLUDE_TILEGX_TRUE='#'
- VGCONF_ARCHS_INCLUDE_TILEGX_FALSE=
-fi
-
# Set up VGCONF_PLATFORMS_INCLUDE_<platform>. Either one or two of these
# become defined.
@@ -6477,14 +6450,6 @@
VGCONF_PLATFORMS_INCLUDE_MIPS64_LINUX_FALSE=
fi
- if test x$VGCONF_PLATFORM_PRI_CAPS = xTILEGX_LINUX; then
- VGCONF_PLATFORMS_INCLUDE_TILEGX_LINUX_TRUE=
- VGCONF_PLATFORMS_INCLUDE_TILEGX_LINUX_FALSE='#'
-else
- VGCONF_PLATFORMS_INCLUDE_TILEGX_LINUX_TRUE='#'
- VGCONF_PLATFORMS_INCLUDE_TILEGX_LINUX_FALSE=
-fi
-
if test x$VGCONF_PLATFORM_PRI_CAPS = xX86_DARWIN \
-o x$VGCONF_PLATFORM_SEC_CAPS = xX86_DARWIN; then
VGCONF_PLATFORMS_INCLUDE_X86_DARWIN_TRUE=
@@ -6533,8 +6498,7 @@
-o x$VGCONF_PLATFORM_PRI_CAPS = xARM64_LINUX \
-o x$VGCONF_PLATFORM_PRI_CAPS = xS390X_LINUX \
-o x$VGCONF_PLATFORM_PRI_CAPS = xMIPS32_LINUX \
- -o x$VGCONF_PLATFORM_PRI_CAPS = xMIPS64_LINUX \
- -o x$VGCONF_PLATFORM_PRI_CAPS = xTILEGX_LINUX; then
+ -o x$VGCONF_PLATFORM_PRI_CAPS = xMIPS64_LINUX; then
VGCONF_OS_IS_LINUX_TRUE=
VGCONF_OS_IS_LINUX_FALSE='#'
else
@@ -6973,6 +6937,13 @@
GLIBC_VERSION="solaris"
fi
+# GLIBC_VERSION is empty if a musl libc is used, so use the toolchain tuple
+# in this case.
+if test x$GLIBC_VERSION = x; then
+ if $CC -dumpmachine | grep -q musl; then
+ GLIBC_VERSION=musl
+ fi
+fi
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking the glibc version" >&5
$as_echo_n "checking the glibc version... " >&6; }
@@ -7044,11 +7015,19 @@
# DEFAULT_SUPP set in host_os switch-case above.
# No other suppression file is used.
;;
+ musl)
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: Musl" >&5
+$as_echo "Musl" >&6; }
+
+$as_echo "#define MUSL_LIBC 1" >>confdefs.h
+
+ # no DEFAULT_SUPP file yet for musl libc.
+ ;;
2.0|2.1|*)
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported version ${GLIBC_VERSION}" >&5
$as_echo "unsupported version ${GLIBC_VERSION}" >&6; }
- as_fn_error $? "Valgrind requires glibc version 2.2 or later," "$LINENO" 5
- as_fn_error $? "Darwin libc, Bionic libc or Solaris libc" "$LINENO" 5
+ as_fn_error $? "Valgrind requires glibc version 2.2 or later, uClibc," "$LINENO" 5
+ as_fn_error $? "musl libc, Darwin libc, Bionic libc or Solaris libc" "$LINENO" 5
;;
esac
@@ -8122,7 +8101,7 @@
rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
if test x$ac_asm_have_isa_3_00 = xyes \
- -a x$HWCAP_HAS_ISA_3_00 = xyes]; then
+ -a x$HWCAP_HAS_ISA_3_00 = xyes; then
HAS_ISA_3_00_TRUE=
HAS_ISA_3_00_FALSE='#'
else
@@ -9859,6 +9838,49 @@
+# Does this compiler support -no-pie?
+# On Ubuntu 16.10+, gcc produces position independent executables (PIE) by
+# default. However this gets in the way with some tests, we use -no-pie
+# for these.
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking if gcc accepts -no-pie" >&5
+$as_echo_n "checking if gcc accepts -no-pie... " >&6; }
+
+safe_CFLAGS=$CFLAGS
+CFLAGS="-no-pie"
+
+cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+
+int
+main ()
+{
+
+ return 0;
+
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+
+FLAG_NO_PIE="-no-pie"
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
+$as_echo "yes" >&6; }
+
+else
+
+FLAG_NO_PIE=""
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+CFLAGS=$safe_CFLAGS
+
+
# We want to use use the -Ttext-segment option to the linker.
# GNU (bfd) ld supports this directly. Newer GNU gold linkers
# support it as an alias of -Ttext. Sadly GNU (bfd) ld's -Ttext
@@ -9905,7 +9927,7 @@
CFLAGS=$safe_CFLAGS
# If the linker only supports -Ttext (not -Ttext-segment) then we will
-# have to strip any build-id ELF NOTEs from the staticly linked tools.
+# have to strip any build-id ELF NOTEs from the statically linked tools.
# Otherwise the build-id NOTE might end up at the default load address.
# (Pedantically if the linker is gold then -Ttext is fine, but newer
# gold versions also support -Ttext-segment. So just assume that unless
@@ -10810,6 +10832,52 @@
+# does the amd64 assembler understand ADX instructions?
+# Note, this doesn't generate a C-level symbol. It generates a
+# automake-level symbol (BUILD_ADX_TESTS), used in test Makefile.am's
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking if amd64 assembler knows the ADX instructions" >&5
+$as_echo_n "checking if amd64 assembler knows the ADX instructions... " >&6; }
+
+cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+
+int
+main ()
+{
+
+ do {
+ asm ("adcxq %r14,%r8");
+ } while (0)
+
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+
+ac_have_as_adx=yes
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
+$as_echo "yes" >&6; }
+
+else
+
+ac_have_as_adx=no
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+
+ if test x$ac_have_as_adx = xyes; then
+ BUILD_ADX_TESTS_TRUE=
+ BUILD_ADX_TESTS_FALSE='#'
+else
+ BUILD_ADX_TESTS_TRUE='#'
+ BUILD_ADX_TESTS_FALSE=
+fi
+
+
+
# Does the C compiler support the "ifunc" attribute
# Note, this doesn't generate a C-level symbol. It generates a
# automake-level symbol (BUILD_IFUNC_TESTS), used in test Makefile.am's
@@ -11029,6 +11097,19 @@
#----------------------------------------------------------------------------
if test "$VGCONF_OS" = "solaris" ; then
+for ac_header in sys/lgrp_user_impl.h
+do :
+ ac_fn_c_check_header_mongrel "$LINENO" "sys/lgrp_user_impl.h" "ac_cv_header_sys_lgrp_user_impl_h" "$ac_includes_default"
+if test "x$ac_cv_header_sys_lgrp_user_impl_h" = xyes; then :
+ cat >>confdefs.h <<_ACEOF
+#define HAVE_SYS_LGRP_USER_IMPL_H 1
+_ACEOF
+
+fi
+
+done
+
+
# Solaris-specific check determining if the Sun Studio Assembler is used to
# build Valgrind. The test checks if the x86/amd64 assembler understands the
# cmovl.l instruction, if yes then it's Sun Assembler.
@@ -11076,10 +11157,10 @@
# Solaris-specific check determining if symbols __xpg4 and __xpg6
-# are present in linked elfs when gcc is invoked with -std=gnu99.
+# are present in linked shared libraries when gcc is invoked with -std=gnu99.
# See solaris/vgpreload-solaris.mapfile for details.
-# gcc on Solaris instructs linker to include these symbols,
-# gcc on illumos does not.
+# gcc on older Solaris instructs linker to include these symbols,
+# gcc on illumos and newer Solaris does not.
#
# C-level symbol: none
# Automake-level symbol: SOLARIS_XPG_SYMBOLS_PRESENT
@@ -11088,54 +11169,23 @@
CFLAGS="$CFLAGS -std=gnu99"
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking if xpg symbols are present with -std=gnu99 (Solaris-specific)" >&5
$as_echo_n "checking if xpg symbols are present with -std=gnu99 (Solaris-specific)... " >&6; }
-if test "$cross_compiling" = yes; then :
- { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
-$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
-as_fn_error $? "cannot run test program while cross compiling
-See \`config.log' for more details" "$LINENO" 5; }
-else
- cat confdefs.h - <<_ACEOF >conftest.$ac_ext
-/* end confdefs.h. */
-
-#include <limits.h>
+temp_dir=$( /usr/bin/mktemp -d )
+cat <<_ACEOF >${temp_dir}/mylib.c
#include <stdio.h>
-#include <stdlib.h>
-
-int main(int argc, const char *argv[]) {
- char command[PATH_MAX + 50];
- snprintf(command, sizeof(command), "nm %s | egrep '__xpg[4,6]'", argv[0]);
-
- FILE *output = popen(command, "r");
- if (output == NULL) return -1;
-
- char buf[100];
- if (fgets(buf, sizeof(buf), output) != NULL) {
- pclose(output);
- return 0;
- } else {
- pclose(output);
- return 1;
- }
-}
-
+int myfunc(void) { printf("LaPutyka\n"); }
_ACEOF
-if ac_fn_c_try_run "$LINENO"; then :
-
-solaris_xpg_symbols_present=yes
-{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
-$as_echo "yes" >&6; }
-
-else
-
-solaris_xpg_symbols_present=no
-{ $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+${CC} ${CFLAGS} -fpic -shared -o ${temp_dir}/mylib.so ${temp_dir}/mylib.c
+xpg_present=$( /usr/bin/nm ${temp_dir}/mylib.so | ${EGREP} '(__xpg4|__xpg6)' )
+if test "x${xpg_present}" = "x" ; then
+ solaris_xpg_symbols_present=no
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
$as_echo "no" >&6; }
-
+else
+ solaris_xpg_symbols_present=yes
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
+$as_echo "yes" >&6; }
fi
-rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \
- conftest.$ac_objext conftest.beam conftest.$ac_ext
-fi
-
+rm -rf ${temp_dir}
if test x$solaris_xpg_symbols_present = xyes; then
SOLARIS_XPG_SYMBOLS_PRESENT_TRUE=
SOLARIS_XPG_SYMBOLS_PRESENT_FALSE='#'
@@ -14841,7 +14891,7 @@
#----------------------------------------------------------------------------
# Nb: VEX/Makefile is generated from Makefile.vex.in.
-ac_config_files="$ac_config_files Makefile VEX/Makefile:Makefile.vex.in valgrind.spec valgrind.pc glibc-2.X.supp docs/Makefile tests/Makefile tests/vg_regtest perf/Makefile perf/vg_perf gdbserver_tests/Makefile gdbserver_tests/solaris/Makefile include/Makefile auxprogs/Makefile mpi/Makefile coregrind/Makefile memcheck/Makefile memcheck/tests/Makefile memcheck/tests/common/Makefile memcheck/tests/amd64/Makefile memcheck/tests/x86/Makefile memcheck/tests/linux/Makefile memcheck/tests/darwin/Makefile memcheck/tests/solaris/Makefile memcheck/tests/amd64-linux/Makefile memcheck/tests/arm64-linux/Makefile memcheck/tests/x86-linux/Makefile memcheck/tests/amd64-solaris/Makefile memcheck/tests/x86-solaris/Makefile memcheck/tests/ppc32/Makefile memcheck/tests/ppc64/Makefile memcheck/tests/s390x/Makefile memcheck/tests/vbit-test/Makefile cachegrind/Makefile cachegrind/tests/Makefile cachegrind/tests/x86/Makefile cachegrind/cg_annotate cachegrind/cg_diff callgrind/Makefile callgrind/callgrind_annotate callgrind/callgrind_control callgrind/tests/Makefile helgrind/Makefile helgrind/tests/Makefile massif/Makefile massif/tests/Makefile massif/ms_print lackey/Makefile lackey/tests/Makefile none/Makefile none/tests/Makefile none/tests/scripts/Makefile none/tests/amd64/Makefile none/tests/ppc32/Makefile none/tests/ppc64/Makefile none/tests/x86/Makefile none/tests/arm/Makefile none/tests/arm64/Makefile none/tests/s390x/Makefile none/tests/mips32/Makefile none/tests/mips64/Makefile none/tests/tilegx/Makefile none/tests/linux/Makefile none/tests/darwin/Makefile none/tests/solaris/Makefile none/tests/amd64-linux/Makefile none/tests/x86-linux/Makefile none/tests/amd64-darwin/Makefile none/tests/x86-darwin/Makefile none/tests/amd64-solaris/Makefile none/tests/x86-solaris/Makefile exp-sgcheck/Makefile exp-sgcheck/tests/Makefile drd/Makefile drd/scripts/download-and-build-splash2 drd/tests/Makefile exp-bbv/Makefile exp-bbv/tests/Makefile exp-bbv/tests/x86/Makefile exp-bbv/tests/x86-linux/Makefile exp-bbv/tests/amd64-linux/Makefile exp-bbv/tests/ppc32-linux/Makefile exp-bbv/tests/arm-linux/Makefile exp-dhat/Makefile exp-dhat/tests/Makefile shared/Makefile solaris/Makefile"
+ac_config_files="$ac_config_files Makefile VEX/Makefile:Makefile.vex.in valgrind.spec valgrind.pc glibc-2.X.supp docs/Makefile tests/Makefile tests/vg_regtest perf/Makefile perf/vg_perf gdbserver_tests/Makefile gdbserver_tests/solaris/Makefile include/Makefile auxprogs/Makefile mpi/Makefile coregrind/Makefile memcheck/Makefile memcheck/tests/Makefile memcheck/tests/common/Makefile memcheck/tests/amd64/Makefile memcheck/tests/x86/Makefile memcheck/tests/linux/Makefile memcheck/tests/darwin/Makefile memcheck/tests/solaris/Makefile memcheck/tests/amd64-linux/Makefile memcheck/tests/arm64-linux/Makefile memcheck/tests/x86-linux/Makefile memcheck/tests/amd64-solaris/Makefile memcheck/tests/x86-solaris/Makefile memcheck/tests/ppc32/Makefile memcheck/tests/ppc64/Makefile memcheck/tests/s390x/Makefile memcheck/tests/mips32/Makefile memcheck/tests/mips64/Makefile memcheck/tests/vbit-test/Makefile cachegrind/Makefile cachegrind/tests/Makefile cachegrind/tests/x86/Makefile cachegrind/cg_annotate cachegrind/cg_diff callgrind/Makefile callgrind/callgrind_annotate callgrind/callgrind_control callgrind/tests/Makefile helgrind/Makefile helgrind/tests/Makefile massif/Makefile massif/tests/Makefile massif/ms_print lackey/Makefile lackey/tests/Makefile none/Makefile none/tests/Makefile none/tests/scripts/Makefile none/tests/amd64/Makefile none/tests/ppc32/Makefile none/tests/ppc64/Makefile none/tests/x86/Makefile none/tests/arm/Makefile none/tests/arm64/Makefile none/tests/s390x/Makefile none/tests/mips32/Makefile none/tests/mips64/Makefile none/tests/linux/Makefile none/tests/darwin/Makefile none/tests/solaris/Makefile none/tests/amd64-linux/Makefile none/tests/x86-linux/Makefile none/tests/amd64-darwin/Makefile none/tests/x86-darwin/Makefile none/tests/amd64-solaris/Makefile none/tests/x86-solaris/Makefile exp-sgcheck/Makefile exp-sgcheck/tests/Makefile drd/Makefile drd/scripts/download-and-build-splash2 drd/tests/Makefile exp-bbv/Makefile exp-bbv/tests/Makefile exp-bbv/tests/x86/Makefile exp-bbv/tests/x86-linux/Makefile exp-bbv/tests/amd64-linux/Makefile exp-bbv/tests/ppc32-linux/Makefile exp-bbv/tests/arm-linux/Makefile exp-dhat/Makefile exp-dhat/tests/Makefile shared/Makefile solaris/Makefile"
ac_config_files="$ac_config_files coregrind/link_tool_exe_linux"
@@ -15038,10 +15088,6 @@
as_fn_error $? "conditional \"VGCONF_ARCHS_INCLUDE_MIPS64\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
fi
-if test -z "${VGCONF_ARCHS_INCLUDE_TILEGX_TRUE}" && test -z "${VGCONF_ARCHS_INCLUDE_TILEGX_FALSE}"; then
- as_fn_error $? "conditional \"VGCONF_ARCHS_INCLUDE_TILEGX\" was never defined.
-Usually this means the macro was only invoked conditionally." "$LINENO" 5
-fi
if test -z "${VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_X86_LINUX_FALSE}"; then
as_fn_error $? "conditional \"VGCONF_PLATFORMS_INCLUDE_X86_LINUX\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
@@ -15082,10 +15128,6 @@
as_fn_error $? "conditional \"VGCONF_PLATFORMS_INCLUDE_MIPS64_LINUX\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
fi
-if test -z "${VGCONF_PLATFORMS_INCLUDE_TILEGX_LINUX_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_TILEGX_LINUX_FALSE}"; then
- as_fn_error $? "conditional \"VGCONF_PLATFORMS_INCLUDE_TILEGX_LINUX\" was never defined.
-Usually this means the macro was only invoked conditionally." "$LINENO" 5
-fi
if test -z "${VGCONF_PLATFORMS_INCLUDE_X86_DARWIN_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_X86_DARWIN_FALSE}"; then
as_fn_error $? "conditional \"VGCONF_PLATFORMS_INCLUDE_X86_DARWIN\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
@@ -15266,6 +15308,10 @@
as_fn_error $? "conditional \"BUILD_MPX_TESTS\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
fi
+if test -z "${BUILD_ADX_TESTS_TRUE}" && test -z "${BUILD_ADX_TESTS_FALSE}"; then
+ as_fn_error $? "conditional \"BUILD_ADX_TESTS\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
if test -z "${BUILD_MOVBE_TESTS_TRUE}" && test -z "${BUILD_MOVBE_TESTS_FALSE}"; then
as_fn_error $? "conditional \"BUILD_MOVBE_TESTS\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
@@ -15963,7 +16009,7 @@
# report actual input values of CONFIG_FILES etc. instead of their
# values after options handling.
ac_log="
-This file was extended by Valgrind $as_me 3.12.0, which was
+This file was extended by Valgrind $as_me 3.13.0, which was
generated by GNU Autoconf 2.69. Invocation command line was
CONFIG_FILES = $CONFIG_FILES
@@ -16029,7 +16075,7 @@
cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
ac_cs_version="\\
-Valgrind config.status 3.12.0
+Valgrind config.status 3.13.0
configured by $0, generated by GNU Autoconf 2.69,
with options \\"\$ac_cs_config\\"
@@ -16192,6 +16238,8 @@
"memcheck/tests/ppc32/Makefile") CONFIG_FILES="$CONFIG_FILES memcheck/tests/ppc32/Makefile" ;;
"memcheck/tests/ppc64/Makefile") CONFIG_FILES="$CONFIG_FILES memcheck/tests/ppc64/Makefile" ;;
"memcheck/tests/s390x/Makefile") CONFIG_FILES="$CONFIG_FILES memcheck/tests/s390x/Makefile" ;;
+ "memcheck/tests/mips32/Makefile") CONFIG_FILES="$CONFIG_FILES memcheck/tests/mips32/Makefile" ;;
+ "memcheck/tests/mips64/Makefile") CONFIG_FILES="$CONFIG_FILES memcheck/tests/mips64/Makefile" ;;
"memcheck/tests/vbit-test/Makefile") CONFIG_FILES="$CONFIG_FILES memcheck/tests/vbit-test/Makefile" ;;
"cachegrind/Makefile") CONFIG_FILES="$CONFIG_FILES cachegrind/Makefile" ;;
"cachegrind/tests/Makefile") CONFIG_FILES="$CONFIG_FILES cachegrind/tests/Makefile" ;;
@@ -16221,7 +16269,6 @@
"none/tests/s390x/Makefile") CONFIG_FILES="$CONFIG_FILES none/tests/s390x/Makefile" ;;
"none/tests/mips32/Makefile") CONFIG_FILES="$CONFIG_FILES none/tests/mips32/Makefile" ;;
"none/tests/mips64/Makefile") CONFIG_FILES="$CONFIG_FILES none/tests/mips64/Makefile" ;;
- "none/tests/tilegx/Makefile") CONFIG_FILES="$CONFIG_FILES none/tests/tilegx/Makefile" ;;
"none/tests/linux/Makefile") CONFIG_FILES="$CONFIG_FILES none/tests/linux/Makefile" ;;
"none/tests/darwin/Makefile") CONFIG_FILES="$CONFIG_FILES none/tests/darwin/Makefile" ;;
"none/tests/solaris/Makefile") CONFIG_FILES="$CONFIG_FILES none/tests/solaris/Makefile" ;;
diff --git a/configure.ac b/configure.ac
index 372871b..3874296 100644
--- a/configure.ac
+++ b/configure.ac
@@ -8,7 +8,7 @@
##------------------------------------------------------------##
# Process this file with autoconf to produce a configure script.
-AC_INIT([Valgrind],[3.12.0],[valgrind-users@lists.sourceforge.net])
+AC_INIT([Valgrind],[3.13.0],[valgrind-users@lists.sourceforge.net])
AC_CONFIG_SRCDIR(coregrind/m_main.c)
AC_CONFIG_HEADERS([config.h])
AM_INIT_AUTOMAKE([foreign subdir-objects])
@@ -192,10 +192,10 @@
# Power PC returns powerpc for Big Endian. This was not changed when Little
# Endian support was added to the 64-bit architecture. The 64-bit Little
# Endian systems explicitly state le in the host_cpu. For clarity in the
-# Valgrind code, the ARCH_MAX name will state LE or BE for the endianess of
+# Valgrind code, the ARCH_MAX name will state LE or BE for the endianness of
# the 64-bit system. Big Endian is the only mode supported on 32-bit Power PC.
# The abreviation PPC or ppc refers to 32-bit and 64-bit systems with either
-# Endianess. The name PPC64 or ppc64 to 64-bit systems of either Endianess.
+# Endianness. The name PPC64 or ppc64 to 64-bit systems of either Endianness.
# The names ppc64be or PPC64BE refer to only 64-bit systems that are Big
# Endian. Similarly, ppc64le or PPC64LE refer to only 64-bit systems that are
# Little Endian.
@@ -269,11 +269,6 @@
ARCH_MAX="mips64"
;;
- tilegx)
- AC_MSG_RESULT([ok (${host_cpu})])
- ARCH_MAX="tilegx"
- ;;
-
*)
AC_MSG_RESULT([no (${host_cpu})])
AC_MSG_ERROR([Unsupported host architecture. Sorry])
@@ -527,8 +522,8 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="X86_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
valt_load_address_sec_norml="0xUNSET"
valt_load_address_sec_inner="0xUNSET"
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
@@ -541,24 +536,24 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="AMD64_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
elif test x$vg_cv_only32bit = xyes; then
VGCONF_ARCH_PRI="x86"
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="X86_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
else
VGCONF_ARCH_PRI="amd64"
VGCONF_ARCH_SEC="x86"
VGCONF_PLATFORM_PRI_CAPS="AMD64_LINUX"
VGCONF_PLATFORM_SEC_CAPS="X86_LINUX"
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
- valt_load_address_sec_norml="0x38000000"
- valt_load_address_sec_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
+ valt_load_address_sec_norml="0x58000000"
+ valt_load_address_sec_inner="0x38000000"
fi
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
;;
@@ -567,8 +562,8 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="PPC32_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
valt_load_address_sec_norml="0xUNSET"
valt_load_address_sec_inner="0xUNSET"
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
@@ -581,24 +576,24 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="PPC64BE_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
elif test x$vg_cv_only32bit = xyes; then
VGCONF_ARCH_PRI="ppc32"
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="PPC32_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
else
VGCONF_ARCH_PRI="ppc64be"
VGCONF_ARCH_SEC="ppc32"
VGCONF_PLATFORM_PRI_CAPS="PPC64BE_LINUX"
VGCONF_PLATFORM_SEC_CAPS="PPC32_LINUX"
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
- valt_load_address_sec_norml="0x38000000"
- valt_load_address_sec_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
+ valt_load_address_sec_norml="0x58000000"
+ valt_load_address_sec_inner="0x38000000"
fi
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
;;
@@ -610,8 +605,8 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="PPC64LE_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
;;
# Darwin gets identified as 32-bit even when it supports 64-bit.
@@ -628,25 +623,25 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="AMD64_DARWIN"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x138000000"
- valt_load_address_pri_inner="0x128000000"
+ valt_load_address_pri_norml="0x158000000"
+ valt_load_address_pri_inner="0x138000000"
elif test x$vg_cv_only32bit = xyes; then
VGCONF_ARCH_PRI="x86"
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="X86_DARWIN"
VGCONF_PLATFORM_SEC_CAPS=""
VGCONF_ARCH_PRI_CAPS="x86"
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
else
VGCONF_ARCH_PRI="amd64"
VGCONF_ARCH_SEC="x86"
VGCONF_PLATFORM_PRI_CAPS="AMD64_DARWIN"
VGCONF_PLATFORM_SEC_CAPS="X86_DARWIN"
- valt_load_address_pri_norml="0x138000000"
- valt_load_address_pri_inner="0x128000000"
- valt_load_address_sec_norml="0x38000000"
- valt_load_address_sec_inner="0x28000000"
+ valt_load_address_pri_norml="0x158000000"
+ valt_load_address_pri_inner="0x138000000"
+ valt_load_address_sec_norml="0x58000000"
+ valt_load_address_sec_inner="0x38000000"
fi
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
;;
@@ -654,8 +649,8 @@
VGCONF_ARCH_PRI="arm"
VGCONF_PLATFORM_PRI_CAPS="ARM_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
valt_load_address_sec_norml="0xUNSET"
valt_load_address_sec_inner="0xUNSET"
AC_MSG_RESULT([ok (${host_cpu}-${host_os})])
@@ -668,24 +663,24 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="ARM64_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
elif test x$vg_cv_only32bit = xyes; then
VGCONF_ARCH_PRI="arm"
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="ARM_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
else
VGCONF_ARCH_PRI="arm64"
VGCONF_ARCH_SEC="arm"
VGCONF_PLATFORM_PRI_CAPS="ARM64_LINUX"
VGCONF_PLATFORM_SEC_CAPS="ARM_LINUX"
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
- valt_load_address_sec_norml="0x38000000"
- valt_load_address_sec_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
+ valt_load_address_sec_norml="0x58000000"
+ valt_load_address_sec_inner="0x38000000"
fi
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
;;
@@ -706,8 +701,8 @@
VGCONF_ARCH_PRI="mips32"
VGCONF_PLATFORM_PRI_CAPS="MIPS32_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
valt_load_address_sec_norml="0xUNSET"
valt_load_address_sec_inner="0xUNSET"
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
@@ -716,19 +711,8 @@
VGCONF_ARCH_PRI="mips64"
VGCONF_PLATFORM_PRI_CAPS="MIPS64_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
- valt_load_address_sec_norml="0xUNSET"
- valt_load_address_sec_inner="0xUNSET"
- AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
- ;;
- tilegx-linux)
- VGCONF_ARCH_PRI="tilegx"
- VGCONF_ARCH_SEC=""
- VGCONF_PLATFORM_PRI_CAPS="TILEGX_LINUX"
- VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
valt_load_address_sec_norml="0xUNSET"
valt_load_address_sec_inner="0xUNSET"
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
@@ -738,8 +722,8 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="X86_SOLARIS"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
valt_load_address_sec_norml="0xUNSET"
valt_load_address_sec_inner="0xUNSET"
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
@@ -752,24 +736,24 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="AMD64_SOLARIS"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
elif test x$vg_cv_only32bit = xyes; then
VGCONF_ARCH_PRI="x86"
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="X86_SOLARIS"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
else
VGCONF_ARCH_PRI="amd64"
VGCONF_ARCH_SEC="x86"
VGCONF_PLATFORM_PRI_CAPS="AMD64_SOLARIS"
VGCONF_PLATFORM_SEC_CAPS="X86_SOLARIS"
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
- valt_load_address_sec_norml="0x38000000"
- valt_load_address_sec_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
+ valt_load_address_sec_norml="0x58000000"
+ valt_load_address_sec_inner="0x38000000"
fi
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
;;
@@ -819,8 +803,6 @@
test x$VGCONF_PLATFORM_PRI_CAPS = xMIPS32_LINUX )
AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_MIPS64,
test x$VGCONF_PLATFORM_PRI_CAPS = xMIPS64_LINUX )
-AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_TILEGX,
- test x$VGCONF_PLATFORM_PRI_CAPS = xTILEGX_LINUX )
# Set up VGCONF_PLATFORMS_INCLUDE_<platform>. Either one or two of these
# become defined.
@@ -848,8 +830,6 @@
test x$VGCONF_PLATFORM_PRI_CAPS = xMIPS32_LINUX)
AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_MIPS64_LINUX,
test x$VGCONF_PLATFORM_PRI_CAPS = xMIPS64_LINUX)
-AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_TILEGX_LINUX,
- test x$VGCONF_PLATFORM_PRI_CAPS = xTILEGX_LINUX)
AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_X86_DARWIN,
test x$VGCONF_PLATFORM_PRI_CAPS = xX86_DARWIN \
-o x$VGCONF_PLATFORM_SEC_CAPS = xX86_DARWIN)
@@ -875,8 +855,7 @@
-o x$VGCONF_PLATFORM_PRI_CAPS = xARM64_LINUX \
-o x$VGCONF_PLATFORM_PRI_CAPS = xS390X_LINUX \
-o x$VGCONF_PLATFORM_PRI_CAPS = xMIPS32_LINUX \
- -o x$VGCONF_PLATFORM_PRI_CAPS = xMIPS64_LINUX \
- -o x$VGCONF_PLATFORM_PRI_CAPS = xTILEGX_LINUX)
+ -o x$VGCONF_PLATFORM_PRI_CAPS = xMIPS64_LINUX)
AM_CONDITIONAL(VGCONF_OS_IS_DARWIN,
test x$VGCONF_PLATFORM_PRI_CAPS = xX86_DARWIN \
-o x$VGCONF_PLATFORM_PRI_CAPS = xAMD64_DARWIN)
@@ -990,6 +969,13 @@
GLIBC_VERSION="solaris"
fi
+# GLIBC_VERSION is empty if a musl libc is used, so use the toolchain tuple
+# in this case.
+if test x$GLIBC_VERSION = x; then
+ if $CC -dumpmachine | grep -q musl; then
+ GLIBC_VERSION=musl
+ fi
+fi
AC_MSG_CHECKING([the glibc version])
@@ -1045,10 +1031,15 @@
# DEFAULT_SUPP set in host_os switch-case above.
# No other suppression file is used.
;;
+ musl)
+ AC_MSG_RESULT(Musl)
+ AC_DEFINE([MUSL_LIBC], 1, [Define to 1 if you're using Musl libc])
+ # no DEFAULT_SUPP file yet for musl libc.
+ ;;
2.0|2.1|*)
AC_MSG_RESULT([unsupported version ${GLIBC_VERSION}])
- AC_MSG_ERROR([Valgrind requires glibc version 2.2 or later,])
- AC_MSG_ERROR([Darwin libc, Bionic libc or Solaris libc])
+ AC_MSG_ERROR([Valgrind requires glibc version 2.2 or later, uClibc,])
+ AC_MSG_ERROR([musl libc, Darwin libc, Bionic libc or Solaris libc])
;;
esac
@@ -1537,7 +1528,7 @@
AC_MSG_RESULT([no])
])
-AM_CONDITIONAL(HAS_ISA_3_00, test x$ac_asm_have_isa_3_00 = xyes \
+AM_CONDITIONAL(HAS_ISA_3_00, [test x$ac_asm_have_isa_3_00 = xyes \
-a x$HWCAP_HAS_ISA_3_00 = xyes])
# Check for pthread_create@GLIBC2.0
@@ -2186,6 +2177,28 @@
AM_CONDITIONAL([HAVE_ASM_CONSTRAINT_P], [test x$ac_have_asm_constraint_p = xyes])
+# Does this compiler support -no-pie?
+# On Ubuntu 16.10+, gcc produces position independent executables (PIE) by
+# default. However this gets in the way with some tests, we use -no-pie
+# for these.
+
+AC_MSG_CHECKING([if gcc accepts -no-pie])
+
+safe_CFLAGS=$CFLAGS
+CFLAGS="-no-pie"
+
+AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[ ]], [[
+ return 0;
+]])], [
+AC_SUBST([FLAG_NO_PIE], ["-no-pie"])
+AC_MSG_RESULT([yes])
+], [
+AC_SUBST([FLAG_NO_PIE], [""])
+AC_MSG_RESULT([no])
+])
+CFLAGS=$safe_CFLAGS
+
+
# We want to use use the -Ttext-segment option to the linker.
# GNU (bfd) ld supports this directly. Newer GNU gold linkers
# support it as an alias of -Ttext. Sadly GNU (bfd) ld's -Ttext
@@ -2219,7 +2232,7 @@
CFLAGS=$safe_CFLAGS
# If the linker only supports -Ttext (not -Ttext-segment) then we will
-# have to strip any build-id ELF NOTEs from the staticly linked tools.
+# have to strip any build-id ELF NOTEs from the statically linked tools.
# Otherwise the build-id NOTE might end up at the default load address.
# (Pedantically if the linker is gold then -Ttext is fine, but newer
# gold versions also support -Ttext-segment. So just assume that unless
@@ -2648,6 +2661,26 @@
AM_CONDITIONAL(BUILD_MPX_TESTS, test x$ac_have_as_mpx = xyes)
+# does the amd64 assembler understand ADX instructions?
+# Note, this doesn't generate a C-level symbol. It generates a
+# automake-level symbol (BUILD_ADX_TESTS), used in test Makefile.am's
+AC_MSG_CHECKING([if amd64 assembler knows the ADX instructions])
+
+AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[]], [[
+ do {
+ asm ("adcxq %r14,%r8");
+ } while (0)
+]])], [
+ac_have_as_adx=yes
+AC_MSG_RESULT([yes])
+], [
+ac_have_as_adx=no
+AC_MSG_RESULT([no])
+])
+
+AM_CONDITIONAL(BUILD_ADX_TESTS, test x$ac_have_as_adx = xyes)
+
+
# Does the C compiler support the "ifunc" attribute
# Note, this doesn't generate a C-level symbol. It generates a
# automake-level symbol (BUILD_IFUNC_TESTS), used in test Makefile.am's
@@ -2757,6 +2790,8 @@
#----------------------------------------------------------------------------
if test "$VGCONF_OS" = "solaris" ; then
+AC_CHECK_HEADERS([sys/lgrp_user_impl.h])
+
# Solaris-specific check determining if the Sun Studio Assembler is used to
# build Valgrind. The test checks if the x86/amd64 assembler understands the
# cmovl.l instruction, if yes then it's Sun Assembler.
@@ -2778,10 +2813,10 @@
AM_CONDITIONAL(SOLARIS_SUN_STUDIO_AS, test x$solaris_have_sun_studio_as = xyes)
# Solaris-specific check determining if symbols __xpg4 and __xpg6
-# are present in linked elfs when gcc is invoked with -std=gnu99.
+# are present in linked shared libraries when gcc is invoked with -std=gnu99.
# See solaris/vgpreload-solaris.mapfile for details.
-# gcc on Solaris instructs linker to include these symbols,
-# gcc on illumos does not.
+# gcc on older Solaris instructs linker to include these symbols,
+# gcc on illumos and newer Solaris does not.
#
# C-level symbol: none
# Automake-level symbol: SOLARIS_XPG_SYMBOLS_PRESENT
@@ -2789,34 +2824,21 @@
save_CFLAGS="$CFLAGS"
CFLAGS="$CFLAGS -std=gnu99"
AC_MSG_CHECKING([if xpg symbols are present with -std=gnu99 (Solaris-specific)])
-AC_RUN_IFELSE([AC_LANG_SOURCE([[
-#include <limits.h>
+temp_dir=$( /usr/bin/mktemp -d )
+cat <<_ACEOF >${temp_dir}/mylib.c
#include <stdio.h>
-#include <stdlib.h>
-
-int main(int argc, const char *argv[]) {
- char command[PATH_MAX + 50];
- snprintf(command, sizeof(command), "nm %s | egrep '__xpg[4,6]'", argv[0]);
-
- FILE *output = popen(command, "r");
- if (output == NULL) return -1;
-
- char buf[100];
- if (fgets(buf, sizeof(buf), output) != NULL) {
- pclose(output);
- return 0;
- } else {
- pclose(output);
- return 1;
- }
-}
-]])], [
-solaris_xpg_symbols_present=yes
-AC_MSG_RESULT([yes])
-], [
-solaris_xpg_symbols_present=no
-AC_MSG_RESULT([no])
-])
+int myfunc(void) { printf("LaPutyka\n"); }
+_ACEOF
+${CC} ${CFLAGS} -fpic -shared -o ${temp_dir}/mylib.so ${temp_dir}/mylib.c
+xpg_present=$( /usr/bin/nm ${temp_dir}/mylib.so | ${EGREP} '(__xpg4|__xpg6)' )
+if test "x${xpg_present}" = "x" ; then
+ solaris_xpg_symbols_present=no
+ AC_MSG_RESULT([no])
+else
+ solaris_xpg_symbols_present=yes
+ AC_MSG_RESULT([yes])
+fi
+rm -rf ${temp_dir}
AM_CONDITIONAL(SOLARIS_XPG_SYMBOLS_PRESENT, test x$solaris_xpg_symbols_present = xyes)
CFLAGS="$save_CFLAGS"
@@ -4369,6 +4391,8 @@
memcheck/tests/ppc32/Makefile
memcheck/tests/ppc64/Makefile
memcheck/tests/s390x/Makefile
+ memcheck/tests/mips32/Makefile
+ memcheck/tests/mips64/Makefile
memcheck/tests/vbit-test/Makefile
cachegrind/Makefile
cachegrind/tests/Makefile
@@ -4398,7 +4422,6 @@
none/tests/s390x/Makefile
none/tests/mips32/Makefile
none/tests/mips64/Makefile
- none/tests/tilegx/Makefile
none/tests/linux/Makefile
none/tests/darwin/Makefile
none/tests/solaris/Makefile
diff --git a/coregrind/Makefile.am b/coregrind/Makefile.am
index d798015..e55ab9a 100644
--- a/coregrind/Makefile.am
+++ b/coregrind/Makefile.am
@@ -234,6 +234,8 @@
pub_core_vkiscnums_asm.h\
pub_core_wordfm.h \
pub_core_xarray.h \
+ pub_core_xtree.h \
+ pub_core_xtmemory.h \
m_aspacemgr/priv_aspacemgr.h \
m_debuginfo/priv_misc.h \
m_debuginfo/priv_storage.h \
@@ -332,6 +334,8 @@
m_vkiscnums.c \
m_wordfm.c \
m_xarray.c \
+ m_xtree.c \
+ m_xtmemory.c \
m_aspacehl.c \
m_aspacemgr/aspacemgr-common.c \
m_aspacemgr/aspacemgr-linux.c \
@@ -358,6 +362,7 @@
m_demangle/demangle.c \
m_demangle/dyn-string.c \
m_demangle/d-demangle.c \
+ m_demangle/rust-demangle.c \
m_demangle/safe-ctype.c \
m_dispatch/dispatch-x86-linux.S \
m_dispatch/dispatch-amd64-linux.S \
@@ -369,7 +374,6 @@
m_dispatch/dispatch-s390x-linux.S \
m_dispatch/dispatch-mips32-linux.S \
m_dispatch/dispatch-mips64-linux.S \
- m_dispatch/dispatch-tilegx-linux.S \
m_dispatch/dispatch-x86-darwin.S \
m_dispatch/dispatch-amd64-darwin.S \
m_dispatch/dispatch-x86-solaris.S \
@@ -391,7 +395,6 @@
m_gdbserver/valgrind-low-s390x.c \
m_gdbserver/valgrind-low-mips32.c \
m_gdbserver/valgrind-low-mips64.c \
- m_gdbserver/valgrind-low-tilegx.c \
m_gdbserver/version.c \
m_initimg/initimg-linux.c \
m_initimg/initimg-darwin.c \
@@ -416,7 +419,6 @@
m_sigframe/sigframe-s390x-linux.c \
m_sigframe/sigframe-mips32-linux.c \
m_sigframe/sigframe-mips64-linux.c \
- m_sigframe/sigframe-tilegx-linux.c \
m_sigframe/sigframe-x86-darwin.c \
m_sigframe/sigframe-amd64-darwin.c \
m_sigframe/sigframe-solaris.c \
@@ -430,7 +432,6 @@
m_syswrap/syscall-s390x-linux.S \
m_syswrap/syscall-mips32-linux.S \
m_syswrap/syscall-mips64-linux.S \
- m_syswrap/syscall-tilegx-linux.S \
m_syswrap/syscall-x86-darwin.S \
m_syswrap/syscall-amd64-darwin.S \
m_syswrap/syscall-x86-solaris.S \
@@ -450,7 +451,6 @@
m_syswrap/syswrap-s390x-linux.c \
m_syswrap/syswrap-mips32-linux.c \
m_syswrap/syswrap-mips64-linux.c \
- m_syswrap/syswrap-tilegx-linux.c \
m_syswrap/syswrap-x86-darwin.c \
m_syswrap/syswrap-amd64-darwin.c \
m_syswrap/syswrap-xen.c \
diff --git a/coregrind/Makefile.in b/coregrind/Makefile.in
index 7079271..cbc9923 100644
--- a/coregrind/Makefile.in
+++ b/coregrind/Makefile.in
@@ -246,20 +246,21 @@
m_redir.c m_sbprofile.c m_seqmatch.c m_signals.c m_sparsewa.c \
m_stacks.c m_stacktrace.c m_syscall.c m_threadstate.c \
m_tooliface.c m_trampoline.S m_translate.c m_transtab.c \
- m_vki.c m_vkiscnums.c m_wordfm.c m_xarray.c m_aspacehl.c \
- m_aspacemgr/aspacemgr-common.c m_aspacemgr/aspacemgr-linux.c \
- m_aspacemgr/aspacemgr-segnames.c m_coredump/coredump-elf.c \
- m_coredump/coredump-macho.c m_coredump/coredump-solaris.c \
- m_debuginfo/misc.c m_debuginfo/d3basics.c \
- m_debuginfo/debuginfo.c m_debuginfo/image.c \
- m_debuginfo/minilzo-inl.c m_debuginfo/readdwarf.c \
- m_debuginfo/readdwarf3.c m_debuginfo/readelf.c \
- m_debuginfo/readexidx.c m_debuginfo/readmacho.c \
- m_debuginfo/readpdb.c m_debuginfo/storage.c \
- m_debuginfo/tinfl.c m_debuginfo/tytypes.c \
- m_demangle/cp-demangle.c m_demangle/cplus-dem.c \
- m_demangle/demangle.c m_demangle/dyn-string.c \
- m_demangle/d-demangle.c m_demangle/safe-ctype.c \
+ m_vki.c m_vkiscnums.c m_wordfm.c m_xarray.c m_xtree.c \
+ m_xtmemory.c m_aspacehl.c m_aspacemgr/aspacemgr-common.c \
+ m_aspacemgr/aspacemgr-linux.c m_aspacemgr/aspacemgr-segnames.c \
+ m_coredump/coredump-elf.c m_coredump/coredump-macho.c \
+ m_coredump/coredump-solaris.c m_debuginfo/misc.c \
+ m_debuginfo/d3basics.c m_debuginfo/debuginfo.c \
+ m_debuginfo/image.c m_debuginfo/minilzo-inl.c \
+ m_debuginfo/readdwarf.c m_debuginfo/readdwarf3.c \
+ m_debuginfo/readelf.c m_debuginfo/readexidx.c \
+ m_debuginfo/readmacho.c m_debuginfo/readpdb.c \
+ m_debuginfo/storage.c m_debuginfo/tinfl.c \
+ m_debuginfo/tytypes.c m_demangle/cp-demangle.c \
+ m_demangle/cplus-dem.c m_demangle/demangle.c \
+ m_demangle/dyn-string.c m_demangle/d-demangle.c \
+ m_demangle/rust-demangle.c m_demangle/safe-ctype.c \
m_dispatch/dispatch-x86-linux.S \
m_dispatch/dispatch-amd64-linux.S \
m_dispatch/dispatch-ppc32-linux.S \
@@ -270,7 +271,6 @@
m_dispatch/dispatch-s390x-linux.S \
m_dispatch/dispatch-mips32-linux.S \
m_dispatch/dispatch-mips64-linux.S \
- m_dispatch/dispatch-tilegx-linux.S \
m_dispatch/dispatch-x86-darwin.S \
m_dispatch/dispatch-amd64-darwin.S \
m_dispatch/dispatch-x86-solaris.S \
@@ -286,8 +286,7 @@
m_gdbserver/valgrind-low-ppc64.c \
m_gdbserver/valgrind-low-s390x.c \
m_gdbserver/valgrind-low-mips32.c \
- m_gdbserver/valgrind-low-mips64.c \
- m_gdbserver/valgrind-low-tilegx.c m_gdbserver/version.c \
+ m_gdbserver/valgrind-low-mips64.c m_gdbserver/version.c \
m_initimg/initimg-linux.c m_initimg/initimg-darwin.c \
m_initimg/initimg-solaris.c m_initimg/initimg-pathscan.c \
m_mach/mach_basics.c m_mach/mach_msg.c \
@@ -305,7 +304,6 @@
m_sigframe/sigframe-s390x-linux.c \
m_sigframe/sigframe-mips32-linux.c \
m_sigframe/sigframe-mips64-linux.c \
- m_sigframe/sigframe-tilegx-linux.c \
m_sigframe/sigframe-x86-darwin.c \
m_sigframe/sigframe-amd64-darwin.c \
m_sigframe/sigframe-solaris.c m_syswrap/syscall-x86-linux.S \
@@ -317,7 +315,6 @@
m_syswrap/syscall-s390x-linux.S \
m_syswrap/syscall-mips32-linux.S \
m_syswrap/syscall-mips64-linux.S \
- m_syswrap/syscall-tilegx-linux.S \
m_syswrap/syscall-x86-darwin.S \
m_syswrap/syscall-amd64-darwin.S \
m_syswrap/syscall-x86-solaris.S \
@@ -332,7 +329,6 @@
m_syswrap/syswrap-s390x-linux.c \
m_syswrap/syswrap-mips32-linux.c \
m_syswrap/syswrap-mips64-linux.c \
- m_syswrap/syswrap-tilegx-linux.c \
m_syswrap/syswrap-x86-darwin.c \
m_syswrap/syswrap-amd64-darwin.c m_syswrap/syswrap-xen.c \
m_syswrap/syswrap-x86-solaris.c \
@@ -381,6 +377,8 @@
libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vkiscnums.$(OBJEXT) \
libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_wordfm.$(OBJEXT) \
libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_xarray.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_xtree.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_xtmemory.$(OBJEXT) \
libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_aspacehl.$(OBJEXT) \
m_aspacemgr/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-common.$(OBJEXT) \
m_aspacemgr/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-linux.$(OBJEXT) \
@@ -407,6 +405,7 @@
m_demangle/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-demangle.$(OBJEXT) \
m_demangle/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dyn-string.$(OBJEXT) \
m_demangle/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-d-demangle.$(OBJEXT) \
+ m_demangle/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-rust-demangle.$(OBJEXT) \
m_demangle/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-safe-ctype.$(OBJEXT) \
m_dispatch/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-linux.$(OBJEXT) \
m_dispatch/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-linux.$(OBJEXT) \
@@ -418,7 +417,6 @@
m_dispatch/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-s390x-linux.$(OBJEXT) \
m_dispatch/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips32-linux.$(OBJEXT) \
m_dispatch/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips64-linux.$(OBJEXT) \
- m_dispatch/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-tilegx-linux.$(OBJEXT) \
m_dispatch/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-darwin.$(OBJEXT) \
m_dispatch/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-darwin.$(OBJEXT) \
m_dispatch/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-solaris.$(OBJEXT) \
@@ -440,7 +438,6 @@
m_gdbserver/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-s390x.$(OBJEXT) \
m_gdbserver/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips32.$(OBJEXT) \
m_gdbserver/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips64.$(OBJEXT) \
- m_gdbserver/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-tilegx.$(OBJEXT) \
m_gdbserver/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-version.$(OBJEXT) \
m_initimg/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-linux.$(OBJEXT) \
m_initimg/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-darwin.$(OBJEXT) \
@@ -465,7 +462,6 @@
m_sigframe/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-s390x-linux.$(OBJEXT) \
m_sigframe/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips32-linux.$(OBJEXT) \
m_sigframe/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips64-linux.$(OBJEXT) \
- m_sigframe/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-tilegx-linux.$(OBJEXT) \
m_sigframe/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-darwin.$(OBJEXT) \
m_sigframe/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-darwin.$(OBJEXT) \
m_sigframe/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-solaris.$(OBJEXT) \
@@ -479,7 +475,6 @@
m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-s390x-linux.$(OBJEXT) \
m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips32-linux.$(OBJEXT) \
m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips64-linux.$(OBJEXT) \
- m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-tilegx-linux.$(OBJEXT) \
m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-darwin.$(OBJEXT) \
m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-darwin.$(OBJEXT) \
m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-solaris.$(OBJEXT) \
@@ -499,7 +494,6 @@
m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-s390x-linux.$(OBJEXT) \
m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips32-linux.$(OBJEXT) \
m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips64-linux.$(OBJEXT) \
- m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-tilegx-linux.$(OBJEXT) \
m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-darwin.$(OBJEXT) \
m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-darwin.$(OBJEXT) \
m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-xen.$(OBJEXT) \
@@ -536,20 +530,21 @@
m_redir.c m_sbprofile.c m_seqmatch.c m_signals.c m_sparsewa.c \
m_stacks.c m_stacktrace.c m_syscall.c m_threadstate.c \
m_tooliface.c m_trampoline.S m_translate.c m_transtab.c \
- m_vki.c m_vkiscnums.c m_wordfm.c m_xarray.c m_aspacehl.c \
- m_aspacemgr/aspacemgr-common.c m_aspacemgr/aspacemgr-linux.c \
- m_aspacemgr/aspacemgr-segnames.c m_coredump/coredump-elf.c \
- m_coredump/coredump-macho.c m_coredump/coredump-solaris.c \
- m_debuginfo/misc.c m_debuginfo/d3basics.c \
- m_debuginfo/debuginfo.c m_debuginfo/image.c \
- m_debuginfo/minilzo-inl.c m_debuginfo/readdwarf.c \
- m_debuginfo/readdwarf3.c m_debuginfo/readelf.c \
- m_debuginfo/readexidx.c m_debuginfo/readmacho.c \
- m_debuginfo/readpdb.c m_debuginfo/storage.c \
- m_debuginfo/tinfl.c m_debuginfo/tytypes.c \
- m_demangle/cp-demangle.c m_demangle/cplus-dem.c \
- m_demangle/demangle.c m_demangle/dyn-string.c \
- m_demangle/d-demangle.c m_demangle/safe-ctype.c \
+ m_vki.c m_vkiscnums.c m_wordfm.c m_xarray.c m_xtree.c \
+ m_xtmemory.c m_aspacehl.c m_aspacemgr/aspacemgr-common.c \
+ m_aspacemgr/aspacemgr-linux.c m_aspacemgr/aspacemgr-segnames.c \
+ m_coredump/coredump-elf.c m_coredump/coredump-macho.c \
+ m_coredump/coredump-solaris.c m_debuginfo/misc.c \
+ m_debuginfo/d3basics.c m_debuginfo/debuginfo.c \
+ m_debuginfo/image.c m_debuginfo/minilzo-inl.c \
+ m_debuginfo/readdwarf.c m_debuginfo/readdwarf3.c \
+ m_debuginfo/readelf.c m_debuginfo/readexidx.c \
+ m_debuginfo/readmacho.c m_debuginfo/readpdb.c \
+ m_debuginfo/storage.c m_debuginfo/tinfl.c \
+ m_debuginfo/tytypes.c m_demangle/cp-demangle.c \
+ m_demangle/cplus-dem.c m_demangle/demangle.c \
+ m_demangle/dyn-string.c m_demangle/d-demangle.c \
+ m_demangle/rust-demangle.c m_demangle/safe-ctype.c \
m_dispatch/dispatch-x86-linux.S \
m_dispatch/dispatch-amd64-linux.S \
m_dispatch/dispatch-ppc32-linux.S \
@@ -560,7 +555,6 @@
m_dispatch/dispatch-s390x-linux.S \
m_dispatch/dispatch-mips32-linux.S \
m_dispatch/dispatch-mips64-linux.S \
- m_dispatch/dispatch-tilegx-linux.S \
m_dispatch/dispatch-x86-darwin.S \
m_dispatch/dispatch-amd64-darwin.S \
m_dispatch/dispatch-x86-solaris.S \
@@ -576,8 +570,7 @@
m_gdbserver/valgrind-low-ppc64.c \
m_gdbserver/valgrind-low-s390x.c \
m_gdbserver/valgrind-low-mips32.c \
- m_gdbserver/valgrind-low-mips64.c \
- m_gdbserver/valgrind-low-tilegx.c m_gdbserver/version.c \
+ m_gdbserver/valgrind-low-mips64.c m_gdbserver/version.c \
m_initimg/initimg-linux.c m_initimg/initimg-darwin.c \
m_initimg/initimg-solaris.c m_initimg/initimg-pathscan.c \
m_mach/mach_basics.c m_mach/mach_msg.c \
@@ -595,7 +588,6 @@
m_sigframe/sigframe-s390x-linux.c \
m_sigframe/sigframe-mips32-linux.c \
m_sigframe/sigframe-mips64-linux.c \
- m_sigframe/sigframe-tilegx-linux.c \
m_sigframe/sigframe-x86-darwin.c \
m_sigframe/sigframe-amd64-darwin.c \
m_sigframe/sigframe-solaris.c m_syswrap/syscall-x86-linux.S \
@@ -607,7 +599,6 @@
m_syswrap/syscall-s390x-linux.S \
m_syswrap/syscall-mips32-linux.S \
m_syswrap/syscall-mips64-linux.S \
- m_syswrap/syscall-tilegx-linux.S \
m_syswrap/syscall-x86-darwin.S \
m_syswrap/syscall-amd64-darwin.S \
m_syswrap/syscall-x86-solaris.S \
@@ -622,7 +613,6 @@
m_syswrap/syswrap-s390x-linux.c \
m_syswrap/syswrap-mips32-linux.c \
m_syswrap/syswrap-mips64-linux.c \
- m_syswrap/syswrap-tilegx-linux.c \
m_syswrap/syswrap-x86-darwin.c \
m_syswrap/syswrap-amd64-darwin.c m_syswrap/syswrap-xen.c \
m_syswrap/syswrap-x86-solaris.c \
@@ -670,6 +660,8 @@
libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vkiscnums.$(OBJEXT) \
libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_wordfm.$(OBJEXT) \
libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_xarray.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_xtree.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_xtmemory.$(OBJEXT) \
libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_aspacehl.$(OBJEXT) \
m_aspacemgr/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-common.$(OBJEXT) \
m_aspacemgr/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-linux.$(OBJEXT) \
@@ -696,6 +688,7 @@
m_demangle/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-demangle.$(OBJEXT) \
m_demangle/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dyn-string.$(OBJEXT) \
m_demangle/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-d-demangle.$(OBJEXT) \
+ m_demangle/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-rust-demangle.$(OBJEXT) \
m_demangle/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-safe-ctype.$(OBJEXT) \
m_dispatch/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-linux.$(OBJEXT) \
m_dispatch/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-linux.$(OBJEXT) \
@@ -707,7 +700,6 @@
m_dispatch/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-s390x-linux.$(OBJEXT) \
m_dispatch/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips32-linux.$(OBJEXT) \
m_dispatch/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips64-linux.$(OBJEXT) \
- m_dispatch/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-tilegx-linux.$(OBJEXT) \
m_dispatch/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-darwin.$(OBJEXT) \
m_dispatch/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-darwin.$(OBJEXT) \
m_dispatch/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-solaris.$(OBJEXT) \
@@ -729,7 +721,6 @@
m_gdbserver/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-s390x.$(OBJEXT) \
m_gdbserver/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips32.$(OBJEXT) \
m_gdbserver/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips64.$(OBJEXT) \
- m_gdbserver/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-tilegx.$(OBJEXT) \
m_gdbserver/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-version.$(OBJEXT) \
m_initimg/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-linux.$(OBJEXT) \
m_initimg/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-darwin.$(OBJEXT) \
@@ -754,7 +745,6 @@
m_sigframe/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-s390x-linux.$(OBJEXT) \
m_sigframe/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips32-linux.$(OBJEXT) \
m_sigframe/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips64-linux.$(OBJEXT) \
- m_sigframe/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-tilegx-linux.$(OBJEXT) \
m_sigframe/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-darwin.$(OBJEXT) \
m_sigframe/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-darwin.$(OBJEXT) \
m_sigframe/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-solaris.$(OBJEXT) \
@@ -768,7 +758,6 @@
m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-s390x-linux.$(OBJEXT) \
m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips32-linux.$(OBJEXT) \
m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips64-linux.$(OBJEXT) \
- m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-tilegx-linux.$(OBJEXT) \
m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-darwin.$(OBJEXT) \
m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-darwin.$(OBJEXT) \
m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-solaris.$(OBJEXT) \
@@ -788,7 +777,6 @@
m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-s390x-linux.$(OBJEXT) \
m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips32-linux.$(OBJEXT) \
m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips64-linux.$(OBJEXT) \
- m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-tilegx-linux.$(OBJEXT) \
m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.$(OBJEXT) \
m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-darwin.$(OBJEXT) \
m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-xen.$(OBJEXT) \
@@ -1003,6 +991,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -1175,15 +1164,17 @@
# Basics, flags
#----------------------------------------------------------------------------
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = -I$(top_srcdir) \
- -I$(top_srcdir)/include -I$(top_srcdir)/VEX/pub \
- -I$(top_builddir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
- -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -I$(top_srcdir)/include -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
-DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
-I$(top_srcdir)/coregrind -DVG_LIBDIR="\"$(pkglibdir)"\" \
-DVG_PLATFORM="\"@VGCONF_ARCH_PRI@-@VGCONF_OS@\""
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -1260,8 +1251,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -1306,7 +1295,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
@@ -1431,6 +1419,8 @@
pub_core_vkiscnums_asm.h\
pub_core_wordfm.h \
pub_core_xarray.h \
+ pub_core_xtree.h \
+ pub_core_xtmemory.h \
m_aspacemgr/priv_aspacemgr.h \
m_debuginfo/priv_misc.h \
m_debuginfo/priv_storage.h \
@@ -1532,6 +1522,8 @@
m_vkiscnums.c \
m_wordfm.c \
m_xarray.c \
+ m_xtree.c \
+ m_xtmemory.c \
m_aspacehl.c \
m_aspacemgr/aspacemgr-common.c \
m_aspacemgr/aspacemgr-linux.c \
@@ -1558,6 +1550,7 @@
m_demangle/demangle.c \
m_demangle/dyn-string.c \
m_demangle/d-demangle.c \
+ m_demangle/rust-demangle.c \
m_demangle/safe-ctype.c \
m_dispatch/dispatch-x86-linux.S \
m_dispatch/dispatch-amd64-linux.S \
@@ -1569,7 +1562,6 @@
m_dispatch/dispatch-s390x-linux.S \
m_dispatch/dispatch-mips32-linux.S \
m_dispatch/dispatch-mips64-linux.S \
- m_dispatch/dispatch-tilegx-linux.S \
m_dispatch/dispatch-x86-darwin.S \
m_dispatch/dispatch-amd64-darwin.S \
m_dispatch/dispatch-x86-solaris.S \
@@ -1591,7 +1583,6 @@
m_gdbserver/valgrind-low-s390x.c \
m_gdbserver/valgrind-low-mips32.c \
m_gdbserver/valgrind-low-mips64.c \
- m_gdbserver/valgrind-low-tilegx.c \
m_gdbserver/version.c \
m_initimg/initimg-linux.c \
m_initimg/initimg-darwin.c \
@@ -1616,7 +1607,6 @@
m_sigframe/sigframe-s390x-linux.c \
m_sigframe/sigframe-mips32-linux.c \
m_sigframe/sigframe-mips64-linux.c \
- m_sigframe/sigframe-tilegx-linux.c \
m_sigframe/sigframe-x86-darwin.c \
m_sigframe/sigframe-amd64-darwin.c \
m_sigframe/sigframe-solaris.c \
@@ -1630,7 +1620,6 @@
m_syswrap/syscall-s390x-linux.S \
m_syswrap/syscall-mips32-linux.S \
m_syswrap/syscall-mips64-linux.S \
- m_syswrap/syscall-tilegx-linux.S \
m_syswrap/syscall-x86-darwin.S \
m_syswrap/syscall-amd64-darwin.S \
m_syswrap/syscall-x86-solaris.S \
@@ -1650,7 +1639,6 @@
m_syswrap/syswrap-s390x-linux.c \
m_syswrap/syswrap-mips32-linux.c \
m_syswrap/syswrap-mips64-linux.c \
- m_syswrap/syswrap-tilegx-linux.c \
m_syswrap/syswrap-x86-darwin.c \
m_syswrap/syswrap-amd64-darwin.c \
m_syswrap/syswrap-xen.c \
@@ -2006,6 +1994,9 @@
m_demangle/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-d-demangle.$(OBJEXT): \
m_demangle/$(am__dirstamp) \
m_demangle/$(DEPDIR)/$(am__dirstamp)
+m_demangle/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-rust-demangle.$(OBJEXT): \
+ m_demangle/$(am__dirstamp) \
+ m_demangle/$(DEPDIR)/$(am__dirstamp)
m_demangle/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-safe-ctype.$(OBJEXT): \
m_demangle/$(am__dirstamp) \
m_demangle/$(DEPDIR)/$(am__dirstamp)
@@ -2045,9 +2036,6 @@
m_dispatch/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips64-linux.$(OBJEXT): \
m_dispatch/$(am__dirstamp) \
m_dispatch/$(DEPDIR)/$(am__dirstamp)
-m_dispatch/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-tilegx-linux.$(OBJEXT): \
- m_dispatch/$(am__dirstamp) \
- m_dispatch/$(DEPDIR)/$(am__dirstamp)
m_dispatch/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-darwin.$(OBJEXT): \
m_dispatch/$(am__dirstamp) \
m_dispatch/$(DEPDIR)/$(am__dirstamp)
@@ -2117,9 +2105,6 @@
m_gdbserver/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips64.$(OBJEXT): \
m_gdbserver/$(am__dirstamp) \
m_gdbserver/$(DEPDIR)/$(am__dirstamp)
-m_gdbserver/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-tilegx.$(OBJEXT): \
- m_gdbserver/$(am__dirstamp) \
- m_gdbserver/$(DEPDIR)/$(am__dirstamp)
m_gdbserver/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-version.$(OBJEXT): \
m_gdbserver/$(am__dirstamp) \
m_gdbserver/$(DEPDIR)/$(am__dirstamp)
@@ -2214,9 +2199,6 @@
m_sigframe/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips64-linux.$(OBJEXT): \
m_sigframe/$(am__dirstamp) \
m_sigframe/$(DEPDIR)/$(am__dirstamp)
-m_sigframe/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-tilegx-linux.$(OBJEXT): \
- m_sigframe/$(am__dirstamp) \
- m_sigframe/$(DEPDIR)/$(am__dirstamp)
m_sigframe/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-darwin.$(OBJEXT): \
m_sigframe/$(am__dirstamp) \
m_sigframe/$(DEPDIR)/$(am__dirstamp)
@@ -2252,8 +2234,6 @@
m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp)
m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips64-linux.$(OBJEXT): \
m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp)
-m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-tilegx-linux.$(OBJEXT): \
- m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp)
m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-darwin.$(OBJEXT): \
m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp)
m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-darwin.$(OBJEXT): \
@@ -2292,8 +2272,6 @@
m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp)
m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips64-linux.$(OBJEXT): \
m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp)
-m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-tilegx-linux.$(OBJEXT): \
- m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp)
m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-darwin.$(OBJEXT): \
m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp)
m_syswrap/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-darwin.$(OBJEXT): \
@@ -2409,6 +2387,9 @@
m_demangle/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-d-demangle.$(OBJEXT): \
m_demangle/$(am__dirstamp) \
m_demangle/$(DEPDIR)/$(am__dirstamp)
+m_demangle/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-rust-demangle.$(OBJEXT): \
+ m_demangle/$(am__dirstamp) \
+ m_demangle/$(DEPDIR)/$(am__dirstamp)
m_demangle/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-safe-ctype.$(OBJEXT): \
m_demangle/$(am__dirstamp) \
m_demangle/$(DEPDIR)/$(am__dirstamp)
@@ -2442,9 +2423,6 @@
m_dispatch/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips64-linux.$(OBJEXT): \
m_dispatch/$(am__dirstamp) \
m_dispatch/$(DEPDIR)/$(am__dirstamp)
-m_dispatch/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-tilegx-linux.$(OBJEXT): \
- m_dispatch/$(am__dirstamp) \
- m_dispatch/$(DEPDIR)/$(am__dirstamp)
m_dispatch/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-darwin.$(OBJEXT): \
m_dispatch/$(am__dirstamp) \
m_dispatch/$(DEPDIR)/$(am__dirstamp)
@@ -2508,9 +2486,6 @@
m_gdbserver/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips64.$(OBJEXT): \
m_gdbserver/$(am__dirstamp) \
m_gdbserver/$(DEPDIR)/$(am__dirstamp)
-m_gdbserver/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-tilegx.$(OBJEXT): \
- m_gdbserver/$(am__dirstamp) \
- m_gdbserver/$(DEPDIR)/$(am__dirstamp)
m_gdbserver/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-version.$(OBJEXT): \
m_gdbserver/$(am__dirstamp) \
m_gdbserver/$(DEPDIR)/$(am__dirstamp)
@@ -2575,9 +2550,6 @@
m_sigframe/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips64-linux.$(OBJEXT): \
m_sigframe/$(am__dirstamp) \
m_sigframe/$(DEPDIR)/$(am__dirstamp)
-m_sigframe/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-tilegx-linux.$(OBJEXT): \
- m_sigframe/$(am__dirstamp) \
- m_sigframe/$(DEPDIR)/$(am__dirstamp)
m_sigframe/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-darwin.$(OBJEXT): \
m_sigframe/$(am__dirstamp) \
m_sigframe/$(DEPDIR)/$(am__dirstamp)
@@ -2607,8 +2579,6 @@
m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp)
m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips64-linux.$(OBJEXT): \
m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp)
-m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-tilegx-linux.$(OBJEXT): \
- m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp)
m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-darwin.$(OBJEXT): \
m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp)
m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-darwin.$(OBJEXT): \
@@ -2647,8 +2617,6 @@
m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp)
m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips64-linux.$(OBJEXT): \
m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp)
-m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-tilegx-linux.$(OBJEXT): \
- m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp)
m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.$(OBJEXT): \
m_syswrap/$(am__dirstamp) m_syswrap/$(DEPDIR)/$(am__dirstamp)
m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-darwin.$(OBJEXT): \
@@ -2823,6 +2791,8 @@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vkiscnums.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_wordfm.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_xarray.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_xtmemory.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_xtree.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_addrinfo.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_aspacehl.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_cache.Po@am__quote@
@@ -2866,6 +2836,8 @@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_xarray.Po@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/valgrind-launcher-darwin.Po@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/valgrind-m_debuglog.Po@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@m_demangle/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dyn-string.Po@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@m_demangle/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dyn-string.Po@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@m_demangle/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-safe-ctype.Po@am__quote@
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m_gdbserver/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-version.o: m_gdbserver/version.c
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-@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='m_syswrap/syswrap-tilegx-linux.c' object='m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-tilegx-linux.o' libtool=no @AMDEPBACKSLASH@
-@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
-@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-tilegx-linux.o `test -f 'm_syswrap/syswrap-tilegx-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-tilegx-linux.c
-
-m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-tilegx-linux.obj: m_syswrap/syswrap-tilegx-linux.c
-@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-tilegx-linux.obj -MD -MP -MF m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-tilegx-linux.Tpo -c -o m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-tilegx-linux.obj `if test -f 'm_syswrap/syswrap-tilegx-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-tilegx-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-tilegx-linux.c'; fi`
-@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-tilegx-linux.Tpo m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-tilegx-linux.Po
-@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='m_syswrap/syswrap-tilegx-linux.c' object='m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-tilegx-linux.obj' libtool=no @AMDEPBACKSLASH@
-@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
-@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-tilegx-linux.obj `if test -f 'm_syswrap/syswrap-tilegx-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-tilegx-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-tilegx-linux.c'; fi`
-
m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.o: m_syswrap/syswrap-x86-darwin.c
@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.o -MD -MP -MF m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.Tpo -c -o m_syswrap/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.o `test -f 'm_syswrap/syswrap-x86-darwin.c' || echo '$(srcdir)/'`m_syswrap/syswrap-x86-darwin.c
@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.Tpo m_syswrap/$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.Po
diff --git a/coregrind/launcher-darwin.c b/coregrind/launcher-darwin.c
index 8d429e1..5097b58 100644
--- a/coregrind/launcher-darwin.c
+++ b/coregrind/launcher-darwin.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -357,7 +357,7 @@
/* Figure out the name of this executable (viz, the launcher), so
we can tell stage2. stage2 will use the name for recursive
- invokations of valgrind on child processes. */
+ invocations of valgrind on child processes. */
memset(launcher_name, 0, PATH_MAX+1);
for (i = 0; envp[i]; i++)
; /* executable path is after last envp item */
@@ -410,7 +410,7 @@
}
new_argv[new_argc++] = NULL;
- /* Build the stage2 invokation, and execve it. Bye! */
+ /* Build the stage2 invocation, and execve it. Bye! */
asprintf(&toolfile, "%s/%s-%s-darwin", valgrind_lib, toolname, arch);
if (access(toolfile, R_OK|X_OK) != 0) {
barf("tool '%s' not installed (%s) (%s)", toolname, toolfile, strerror(errno));
diff --git a/coregrind/launcher-linux.c b/coregrind/launcher-linux.c
index 4d018f2..8e7c734 100644
--- a/coregrind/launcher-linux.c
+++ b/coregrind/launcher-linux.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -65,10 +65,6 @@
#define EM_PPC64 21 // ditto
#endif
-#ifndef EM_TILEGX
-#define EM_TILEGX 191
-#endif
-
/* Report fatal errors */
__attribute__((noreturn))
static void barf ( const char *format, ... )
@@ -133,7 +129,11 @@
static const char *select_platform(const char *clientname)
{
int fd;
- char header[4096];
+ union {
+ char c[4096];
+ Elf32_Ehdr ehdr32;
+ Elf64_Ehdr ehdr64;
+ } header;
ssize_t n_bytes;
const char *platform = NULL;
@@ -150,7 +150,7 @@
VG_(debugLog)(2, "launcher", "opened '%s'\n", clientname);
- n_bytes = read(fd, header, sizeof(header));
+ n_bytes = read(fd, header.c, sizeof(header));
close(fd);
if (n_bytes < 2) {
return NULL;
@@ -159,25 +159,25 @@
VG_(debugLog)(2, "launcher", "read %ld bytes from '%s'\n",
(long int)n_bytes, clientname);
- if (header[0] == '#' && header[1] == '!') {
+ if (header.c[0] == '#' && header.c[1] == '!') {
int i = 2;
STATIC_ASSERT(VKI_BINPRM_BUF_SIZE < sizeof header);
if (n_bytes > VKI_BINPRM_BUF_SIZE)
n_bytes = VKI_BINPRM_BUF_SIZE - 1;
- header[n_bytes] = '\0';
- char *eol = strchr(header, '\n');
+ header.c[n_bytes] = '\0';
+ char *eol = strchr(header.c, '\n');
if (eol != NULL)
*eol = '\0';
// Skip whitespace.
- while (header[i] == ' '|| header[i] == '\t')
+ while (header.c[i] == ' '|| header.c[i] == '\t')
i++;
// Get the interpreter name.
- const char *interp = header + i;
+ const char *interp = header.c + i;
- if (header[i] == '\0') {
+ if (header.c[i] == '\0') {
// No interpreter was found; fall back to default shell
# if defined(VGPV_arm_linux_android) \
|| defined(VGPV_x86_linux_android) \
@@ -188,112 +188,106 @@
interp = "/bin/sh";
# endif
} else {
- while (header[i]) {
- if (header[i] == ' ' || header[i] == '\t') break;
+ while (header.c[i]) {
+ if (header.c[i] == ' ' || header.c[i] == '\t') break;
i++;
}
- header[i] = '\0';
+ header.c[i] = '\0';
}
platform = select_platform(interp);
- } else if (n_bytes >= SELFMAG && memcmp(header, ELFMAG, SELFMAG) == 0) {
+ } else if (n_bytes >= SELFMAG && memcmp(header.c, ELFMAG, SELFMAG) == 0) {
- if (n_bytes >= sizeof(Elf32_Ehdr) && header[EI_CLASS] == ELFCLASS32) {
- const Elf32_Ehdr *ehdr = (Elf32_Ehdr *)header;
+ if (n_bytes >= sizeof(Elf32_Ehdr) && header.c[EI_CLASS] == ELFCLASS32) {
- if (header[EI_DATA] == ELFDATA2LSB) {
+ if (header.c[EI_DATA] == ELFDATA2LSB) {
# if defined(VGO_solaris)
- if (ehdr->e_machine == EM_386 &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_SOLARIS)) {
+ if (header.ehdr32.e_machine == EM_386 &&
+ (header.ehdr32.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr32.e_ident[EI_OSABI] == ELFOSABI_SOLARIS)) {
platform = "x86-solaris";
}
else
# endif
- if (ehdr->e_machine == EM_386 &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ if (header.ehdr32.e_machine == EM_386 &&
+ (header.ehdr32.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr32.e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "x86-linux";
}
else
- if (ehdr->e_machine == EM_ARM &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ if (header.ehdr32.e_machine == EM_ARM &&
+ (header.ehdr32.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr32.e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "arm-linux";
}
else
- if (ehdr->e_machine == EM_MIPS &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ if (header.ehdr32.e_machine == EM_MIPS &&
+ (header.ehdr32.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr32.e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "mips32-linux";
}
}
- else if (header[EI_DATA] == ELFDATA2MSB) {
- if (ehdr->e_machine == EM_PPC &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ else if (header.c[EI_DATA] == ELFDATA2MSB) {
+ if (header.ehdr32.e_machine == EM_PPC &&
+ (header.ehdr32.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr32.e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "ppc32-linux";
}
else
- if (ehdr->e_machine == EM_MIPS &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ if (header.ehdr32.e_machine == EM_MIPS &&
+ (header.ehdr32.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr32.e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "mips32-linux";
}
}
- } else if (n_bytes >= sizeof(Elf64_Ehdr) && header[EI_CLASS] == ELFCLASS64) {
- const Elf64_Ehdr *ehdr = (Elf64_Ehdr *)header;
+ } else if (n_bytes >= sizeof(Elf64_Ehdr) && header.c[EI_CLASS] == ELFCLASS64) {
- if (header[EI_DATA] == ELFDATA2LSB) {
+ if (header.c[EI_DATA] == ELFDATA2LSB) {
# if defined(VGO_solaris)
- if (ehdr->e_machine == EM_X86_64 &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_SOLARIS)) {
+ if (header.ehdr64.e_machine == EM_X86_64 &&
+ (header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_SOLARIS)) {
platform = "amd64-solaris";
}
else
# endif
- if (ehdr->e_machine == EM_X86_64 &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ if (header.ehdr64.e_machine == EM_X86_64 &&
+ (header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "amd64-linux";
- } else if (ehdr->e_machine == EM_MIPS &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ } else if (header.ehdr64.e_machine == EM_MIPS &&
+ (header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "mips64-linux";
- } else if (ehdr->e_machine == EM_TILEGX &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
- platform = "tilegx-linux";
- } else if (ehdr->e_machine == EM_AARCH64 &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ } else if (header.ehdr64.e_machine == EM_AARCH64 &&
+ (header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "arm64-linux";
- } else if (ehdr->e_machine == EM_PPC64 &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ } else if (header.ehdr64.e_machine == EM_PPC64 &&
+ (header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "ppc64le-linux";
}
- } else if (header[EI_DATA] == ELFDATA2MSB) {
+ } else if (header.c[EI_DATA] == ELFDATA2MSB) {
# if !defined(VGPV_arm_linux_android) \
&& !defined(VGPV_x86_linux_android) \
&& !defined(VGPV_mips32_linux_android) \
&& !defined(VGPV_arm64_linux_android)
- if (ehdr->e_machine == EM_PPC64 &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ if (header.ehdr64.e_machine == EM_PPC64 &&
+ (header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "ppc64be-linux";
}
else
- if (ehdr->e_machine == EM_S390 &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ if (header.ehdr64.e_machine == EM_S390 &&
+ (header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "s390x-linux";
- } else if (ehdr->e_machine == EM_MIPS &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ } else if (header.ehdr64.e_machine == EM_MIPS &&
+ (header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "mips64-linux";
}
# endif
@@ -372,7 +366,6 @@
(0==strcmp(VG_PLATFORM,"arm-linux")) ||
(0==strcmp(VG_PLATFORM,"arm64-linux")) ||
(0==strcmp(VG_PLATFORM,"s390x-linux")) ||
- (0==strcmp(VG_PLATFORM,"tilegx-linux")) ||
(0==strcmp(VG_PLATFORM,"mips32-linux")) ||
(0==strcmp(VG_PLATFORM,"mips64-linux")))
default_platform = VG_PLATFORM;
diff --git a/coregrind/link_tool_exe_darwin.in b/coregrind/link_tool_exe_darwin.in
index d0e3c3e..2e00307 100644
--- a/coregrind/link_tool_exe_darwin.in
+++ b/coregrind/link_tool_exe_darwin.in
@@ -19,7 +19,7 @@
# first arg
# the alternative load address
# all the rest of the args
-# the gcc invokation to do the final link, that
+# the gcc invocation to do the final link, that
# the build system would have done, left to itself
#
# We just let the script 'die' if something is wrong, rather than do
@@ -30,7 +30,7 @@
#
# So: what we actually do is:
#
-# Look at the specified gcc invokation. Ignore all parts of it except
+# Look at the specified gcc invocation. Ignore all parts of it except
# the *.a, *.o and -o outfile parts. Wrap them up in a new command
# which looks (eg) as follows:
#
@@ -38,7 +38,7 @@
#
# /usr/bin/ld -static -arch x86_64 -macosx_version_min 10.6 \
# -o memcheck-amd64-darwin -u __start -e __start \
-# -image_base 0x138000000 -stack_addr 0x13c000000 \
+# -image_base 0x158000000 -stack_addr 0x13c000000 \
# -stack_size 0x800000 \
# memcheck_amd*.o \
# ../coregrind/libcoregrind-amd64-darwin.a \
@@ -48,7 +48,7 @@
#
# /usr/bin/ld -static -arch i386 -macosx_version_min 10.6 \
# -o memcheck-x86-darwin -u __start -e __start \
-# -image_base 0x38000000 -stack_addr 0x3c000000 \
+# -image_base 0x58000000 -stack_addr 0x3c000000 \
# -stack_size 0x800000 \
# memcheck_x86*.o \
# ../coregrind/libcoregrind-x86-darwin.a \
@@ -65,7 +65,7 @@
# executable for which we are linking. We need to know this because
# we must tell the linker that, by handing it either "-arch x86_64" or
# "-arch i386". Fortunately we can figure this out by scanning the
-# gcc invokation, which itself must contain either "-arch x86_64" or
+# gcc invocation, which itself must contain either "-arch x86_64" or
# "-arch i386".
use warnings;
diff --git a/coregrind/link_tool_exe_linux.in b/coregrind/link_tool_exe_linux.in
index 5214420..9d4c90f 100644
--- a/coregrind/link_tool_exe_linux.in
+++ b/coregrind/link_tool_exe_linux.in
@@ -19,7 +19,7 @@
# first arg
# the alternative load address
# all the rest of the args
-# the gcc invokation to do the final link, that
+# the gcc invocation to do the final link, that
# the build system would have done, left to itself
#
# We just let the script 'die' if something is wrong, rather than do
diff --git a/coregrind/link_tool_exe_solaris.in b/coregrind/link_tool_exe_solaris.in
index 795220f..f490e22 100644
--- a/coregrind/link_tool_exe_solaris.in
+++ b/coregrind/link_tool_exe_solaris.in
@@ -31,7 +31,7 @@
die "Bogus alt-load address"
if (length($ala) < 3 || index($ala, "0x") != 0);
-# the cc invokation to do the final link
+# the cc invocation to do the final link
my $cc = $ARGV[1];
# and the 'restargs' are argv[2 ..]
diff --git a/coregrind/m_addrinfo.c b/coregrind/m_addrinfo.c
index 7b1c4cf..c3edc13 100644
--- a/coregrind/m_addrinfo.c
+++ b/coregrind/m_addrinfo.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2015 OpenWorks Ltd
+ Copyright (C) 2008-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -222,7 +222,7 @@
ThreadId tid;
StackPos stackPos = StackPos_stacked;
// Default init to StackPos_stacked, to silence gcc warning.
- // We assert this value is overriden if a stack descr is produced.
+ // We assert this value is overridden if a stack descr is produced.
// First try to find a tid with stack containing a
tid = find_tid_with_stack_containing (a);
diff --git a/coregrind/m_aspacehl.c b/coregrind/m_aspacehl.c
index ea68bdf..982bd50 100644
--- a/coregrind/m_aspacehl.c
+++ b/coregrind/m_aspacehl.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2006-2015 Julian Seward
+ Copyright (C) 2006-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_aspacemgr/aspacemgr-common.c b/coregrind/m_aspacemgr/aspacemgr-common.c
index 205e052..bbfe19d 100644
--- a/coregrind/m_aspacemgr/aspacemgr-common.c
+++ b/coregrind/m_aspacemgr/aspacemgr-common.c
@@ -9,7 +9,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2006-2015 OpenWorks LLP
+ Copyright (C) 2006-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -158,8 +158,7 @@
# elif defined(VGP_amd64_linux) \
|| defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
|| defined(VGP_s390x_linux) || defined(VGP_mips32_linux) \
- || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) \
- || defined(VGP_tilegx_linux)
+ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux)
res = VG_(do_syscall6)(__NR_mmap, (UWord)start, length,
prot, flags, fd, offset);
# elif defined(VGP_x86_darwin)
@@ -258,9 +257,6 @@
/* ARM64 wants to use __NR_openat rather than __NR_open. */
SysRes res = VG_(do_syscall4)(__NR_openat,
VKI_AT_FDCWD, (UWord)pathname, flags, mode);
-# elif defined(VGP_tilegx_linux)
- SysRes res = VG_(do_syscall4)(__NR_openat, VKI_AT_FDCWD, (UWord)pathname,
- flags, mode);
# elif defined(VGO_linux) || defined(VGO_darwin)
SysRes res = VG_(do_syscall3)(__NR_open, (UWord)pathname, flags, mode);
# elif defined(VGO_solaris)
@@ -289,9 +285,6 @@
# if defined(VGP_arm64_linux)
res = VG_(do_syscall4)(__NR_readlinkat, VKI_AT_FDCWD,
(UWord)path, (UWord)buf, bufsiz);
-# elif defined(VGP_tilegx_linux)
- res = VG_(do_syscall4)(__NR_readlinkat, VKI_AT_FDCWD, (UWord)path,
- (UWord)buf, bufsiz);
# elif defined(VGO_linux) || defined(VGO_darwin)
res = VG_(do_syscall3)(__NR_readlink, (UWord)path, (UWord)buf, bufsiz);
# elif defined(VGO_solaris)
diff --git a/coregrind/m_aspacemgr/aspacemgr-linux.c b/coregrind/m_aspacemgr/aspacemgr-linux.c
index 907ceb7..32173c6 100644
--- a/coregrind/m_aspacemgr/aspacemgr-linux.c
+++ b/coregrind/m_aspacemgr/aspacemgr-linux.c
@@ -11,7 +11,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -260,7 +260,7 @@
Loss of pointercheck
~~~~~~~~~~~~~~~~~~~~
Up to and including Valgrind 2.4.1, x86 segmentation was used to
- enforce seperation of V and C, so that wild writes by C could not
+ enforce separation of V and C, so that wild writes by C could not
trash V. This got called "pointercheck". Unfortunately, the new
more flexible memory layout, plus the need to be portable across
different architectures, means doing this in hardware is no longer
@@ -1620,6 +1620,7 @@
aspacem_minAddr = VG_(clo_aspacem_minAddr);
+ // --- Darwin -------------------------------------------
#if defined(VGO_darwin)
# if VG_WORDSIZE == 4
@@ -1637,6 +1638,7 @@
suggested_clstack_end = -1; // ignored; Mach-O specifies its stack
+ // --- Solaris ------------------------------------------
#elif defined(VGO_solaris)
# if VG_WORDSIZE == 4
/*
@@ -1653,7 +1655,7 @@
| |
|--------------------------------|
| client stack |
- |--------------------------------| 0x38000000
+ |--------------------------------| 0x58000000
| V's text |
|--------------------------------|
| |
@@ -1686,13 +1688,13 @@
| |
|--------------------------------|
| client stack |
- |--------------------------------| 0x00000000_38000000
+ |--------------------------------| 0x00000000_58000000
| V's text |
|--------------------------------|
| |
|--------------------------------|
| dynamic shared objects |
- |--------------------------------| 0x0000000f_ffffffff
+ |--------------------------------| 0x0000001f_ffffffff
| |
| |
|--------------------------------|
@@ -1702,18 +1704,18 @@
*/
/* Kernel likes to place objects at the end of the address space.
- However accessing memory beyond 64GB makes memcheck slow
+ However accessing memory beyond 128GB makes memcheck slow
(see memcheck/mc_main.c, internal representation). Therefore:
- mmapobj() syscall is emulated so that libraries are subject to
Valgrind's aspacemgr control
- Kernel shared pages (such as schedctl and hrt) are left as they are
because kernel cannot be told where they should be put */
# ifdef ENABLE_INNER
- aspacem_maxAddr = (Addr) 0x00000007ffffffff; // 32GB
- aspacem_vStart = (Addr) 0x0000000400000000; // 16GB
-# else
aspacem_maxAddr = (Addr) 0x0000000fffffffff; // 64GB
aspacem_vStart = (Addr) 0x0000000800000000; // 32GB
+# else
+ aspacem_maxAddr = (Addr) 0x0000001fffffffff; // 128GB
+ aspacem_vStart = (Addr) 0x0000001000000000; // 64GB
# endif
# else
# error "Unknown word size"
@@ -1721,11 +1723,12 @@
aspacem_cStart = aspacem_minAddr;
# ifdef ENABLE_INNER
- suggested_clstack_end = (Addr) 0x27ff0000 - 1; // 64kB below V's text
-# else
suggested_clstack_end = (Addr) 0x37ff0000 - 1; // 64kB below V's text
+# else
+ suggested_clstack_end = (Addr) 0x57ff0000 - 1; // 64kB below V's text
# endif
+ // --- Linux --------------------------------------------
#else
/* Establish address limits and block out unusable parts
@@ -1736,7 +1739,7 @@
sp_at_startup );
# if VG_WORDSIZE == 8
- aspacem_maxAddr = (Addr)0x1000000000ULL - 1; // 64G
+ aspacem_maxAddr = (Addr)0x2000000000ULL - 1; // 128G
# ifdef ENABLE_INNER
{ Addr cse = VG_PGROUNDDN( sp_at_startup ) - 1;
if (aspacem_maxAddr > cse)
@@ -1751,13 +1754,14 @@
aspacem_vStart = VG_PGROUNDUP(aspacem_minAddr
+ (aspacem_maxAddr - aspacem_minAddr + 1) / 2);
# ifdef ENABLE_INNER
- aspacem_vStart -= 0x10000000; // 256M
+ aspacem_vStart -= 0x20000000; // 512M
# endif
suggested_clstack_end = aspacem_maxAddr - 16*1024*1024ULL
+ VKI_PAGE_SIZE;
#endif
+ // --- (end) --------------------------------------------
aspacem_assert(VG_IS_PAGE_ALIGNED(aspacem_minAddr));
aspacem_assert(VG_IS_PAGE_ALIGNED(aspacem_maxAddr + 1));
@@ -1861,7 +1865,7 @@
the outcome of the search and the kind of request made, decide
whether the request is allowable and what address to advise.
- The Default Policy is overriden by Policy Exception #1:
+ The Default Policy is overridden by Policy Exception #1:
If the request is for a fixed client map, we are prepared to
grant it providing all areas inside the request are either
@@ -1869,7 +1873,7 @@
other words we are prepared to let the client trash its own
mappings if it wants to.
- The Default Policy is overriden by Policy Exception #2:
+ The Default Policy is overridden by Policy Exception #2:
If the request is for a hinted client map, we are prepared to
grant it providing all areas inside the request are either
@@ -2773,6 +2777,9 @@
Bool d;
SysRes sres;
+ /* Be safe with this regardless of return path. */
+ *need_discard = False;
+
if (!VG_IS_PAGE_ALIGNED(start))
goto eINVAL;
diff --git a/coregrind/m_aspacemgr/aspacemgr-segnames.c b/coregrind/m_aspacemgr/aspacemgr-segnames.c
index 8e74356..99ea9bf 100644
--- a/coregrind/m_aspacemgr/aspacemgr-segnames.c
+++ b/coregrind/m_aspacemgr/aspacemgr-segnames.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2015-2015 Florian Krohm
+ Copyright (C) 2015-2017 Florian Krohm
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/m_aspacemgr/priv_aspacemgr.h b/coregrind/m_aspacemgr/priv_aspacemgr.h
index b5fd957..174678b 100644
--- a/coregrind/m_aspacemgr/priv_aspacemgr.h
+++ b/coregrind/m_aspacemgr/priv_aspacemgr.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2006-2015 OpenWorks LLP
+ Copyright (C) 2006-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_cache.c b/coregrind/m_cache.c
index 63a515f..974ca5d 100644
--- a/coregrind/m_cache.c
+++ b/coregrind/m_cache.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2002-2015 Nicholas Nethercote
+ Copyright (C) 2002-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -540,8 +540,7 @@
#elif defined(VGA_arm) || defined(VGA_ppc32) || \
defined(VGA_ppc64be) || defined(VGA_ppc64le) || \
- defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_arm64) || \
- defined(VGA_tilegx)
+ defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_arm64)
static Bool
get_cache_info(VexArchInfo *vai)
{
diff --git a/coregrind/m_clientstate.c b/coregrind/m_clientstate.c
index 296d658..cb3ba21 100644
--- a/coregrind/m_clientstate.c
+++ b/coregrind/m_clientstate.c
@@ -9,7 +9,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -31,6 +31,7 @@
*/
#include "pub_core_basics.h"
+#include "pub_core_threadstate.h"
#include "pub_core_vki.h"
#include "pub_core_xarray.h"
#include "pub_core_clientstate.h"
@@ -50,7 +51,7 @@
Addr VG_(clstk_start_base) = 0;
/* Initial highest address of the stack segment of the main thread. */
Addr VG_(clstk_end) = 0;
-UWord VG_(clstk_id) = 0;
+UWord VG_(clstk_id) = NULL_STK_ID;
/* Maximum size of the main thread's client stack. */
SizeT VG_(clstk_max_size) = 0;
diff --git a/coregrind/m_commandline.c b/coregrind/m_commandline.c
index e6209a5..d89b6ac 100644
--- a/coregrind/m_commandline.c
+++ b/coregrind/m_commandline.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -55,8 +55,6 @@
static HChar* read_dot_valgrindrc ( const HChar* dir )
{
- Int n;
- SysRes fd;
struct vg_stat stat_buf;
HChar* f_clo = NULL;
const HChar dot_valgrindrc[] = ".valgrindrc";
@@ -66,15 +64,18 @@
HChar filename[VG_(strlen)(dir) + 1 + VG_(strlen)(dot_valgrindrc) + 1];
VG_(sprintf)(filename, "%s/%s", dir, dot_valgrindrc);
- fd = VG_(open)(filename, 0, VKI_S_IRUSR);
+ SysRes fd = VG_(open)(filename, 0, VKI_S_IRUSR);
if ( !sr_isError(fd) ) {
Int res = VG_(fstat)( sr_Res(fd), &stat_buf );
- // Ignore if not owned by current user or world writeable (CVE-2008-4865)
- if (!res && stat_buf.uid == VG_(geteuid)()
- && (!(stat_buf.mode & VKI_S_IWOTH))) {
+ /* Ignore if not owned by the current user, or is not a regular file,
+ or is world writeable (CVE-2008-4865). */
+ if (res == 0
+ && stat_buf.uid == VG_(geteuid)()
+ && VKI_S_ISREG(stat_buf.mode)
+ && !(stat_buf.mode & VKI_S_IWOTH)) {
if ( stat_buf.size > 0 ) {
f_clo = VG_(malloc)("commandline.rdv.1", stat_buf.size+1);
- n = VG_(read)(sr_Res(fd), f_clo, stat_buf.size);
+ Int n = VG_(read)(sr_Res(fd), f_clo, stat_buf.size);
if (n == -1) n = 0;
vg_assert(n >= 0 && n <= stat_buf.size+1);
f_clo[n] = '\0';
@@ -82,8 +83,9 @@
}
else
VG_(message)(Vg_UserMsg,
- "%s was not read as it is either world writeable or not "
- "owned by the current user\n", filename);
+ "%s was not read as it is either not a regular file,\n"
+ " or is world writeable, or is not owned by the current user.\n",
+ filename);
VG_(close)(sr_Res(fd));
}
@@ -123,7 +125,7 @@
in the stated order.
VG_(args_for_valgrind_noexecpass) is set to be the number of items
- in the first three categories. They are not passed to child invokations
+ in the first three categories. They are not passed to child invocations
at exec, whereas the last group is.
If the last group contains --command-line-only=yes, then the
diff --git a/coregrind/m_compiler.c b/coregrind/m_compiler.c
index a6f5a32..8d0dc67 100644
--- a/coregrind/m_compiler.c
+++ b/coregrind/m_compiler.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2014-2015 Florian Krohm
+ Copyright (C) 2014-2017 Florian Krohm
florian@eich-krohm.de
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_coredump/coredump-elf.c b/coregrind/m_coredump/coredump-elf.c
index f36891f..913a0a5 100644
--- a/coregrind/m_coredump/coredump-elf.c
+++ b/coregrind/m_coredump/coredump-elf.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -418,17 +418,6 @@
regs[VKI_MIPS64_EF_HI] = arch->vex.guest_HI;
regs[VKI_MIPS64_EF_CP0_STATUS] = arch->vex.guest_CP0_status;
regs[VKI_MIPS64_EF_CP0_EPC] = arch->vex.guest_PC;
-#elif defined(VGP_tilegx_linux)
-# define DO(n) regs->regs[n] = arch->vex.guest_r##n
- DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7);
- DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15);
- DO(16); DO(17); DO(18); DO(19); DO(20); DO(21); DO(22); DO(23);
- DO(24); DO(25); DO(26); DO(27); DO(28); DO(29); DO(30); DO(31);
- DO(32); DO(33); DO(34); DO(35); DO(36); DO(37); DO(38); DO(39);
- DO(40); DO(41); DO(42); DO(43); DO(44); DO(45); DO(46); DO(47);
- DO(48); DO(49); DO(50); DO(51); DO(52); DO(53); DO(54); DO(55);
- regs->pc = arch->vex.guest_pc;
- regs->orig_r0 = arch->vex.guest_r0;
#else
# error Unknown ELF platform
#endif
@@ -501,7 +490,7 @@
DO(24); DO(25); DO(26); DO(27); DO(28); DO(29); DO(30); DO(31);
# undef DO
-#elif defined(VGP_arm_linux) || defined(VGP_tilegx_linux)
+#elif defined(VGP_arm_linux)
// umm ...
#elif defined(VGP_arm64_linux)
@@ -512,15 +501,8 @@
DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7);
DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15);
# undef DO
-#elif defined(VGP_mips32_linux)
-# define DO(n) (*fpu)[n] = *(double*)(&arch->vex.guest_f##n)
- DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7);
- DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15);
- DO(16); DO(17); DO(18); DO(19); DO(20); DO(21); DO(22); DO(23);
- DO(24); DO(25); DO(26); DO(27); DO(28); DO(29); DO(30); DO(31);
-# undef DO
#elif defined(VGP_mips32_linux) || defined(VGP_mips64_linux)
-# define DO(n) (*fpu)[n] = *(double*)(&arch->vex.guest_f##n)
+# define DO(n) (*fpu)[n] = *(const double*)(&arch->vex.guest_f##n)
DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7);
DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15);
DO(16); DO(17); DO(18); DO(19); DO(20); DO(21); DO(22); DO(23);
@@ -606,10 +588,10 @@
Addr *seg_starts;
Int n_seg_starts;
- if (VG_(clo_log_fname_expanded) != NULL) {
+ if (VG_(clo_log_fname_unexpanded) != NULL) {
coreext = ".core";
basename = VG_(expand_file_name)("--log-file",
- VG_(clo_log_fname_expanded));
+ VG_(clo_log_fname_unexpanded));
}
vg_assert(coreext);
diff --git a/coregrind/m_coredump/coredump-solaris.c b/coregrind/m_coredump/coredump-solaris.c
index 337edc6..0539a84 100644
--- a/coregrind/m_coredump/coredump-solaris.c
+++ b/coregrind/m_coredump/coredump-solaris.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2013-2015 Ivo Raisr
+ Copyright (C) 2013-2017 Ivo Raisr
ivosh@ivosh.net
This program is free software; you can redistribute it and/or
@@ -682,7 +682,7 @@
static vki_priv_impl_info_t *create_priv_info(SizeT *size)
{
- /* Size of the returned priv_impl_info_t is apriori unkown. */
+ /* Size of the returned priv_impl_info_t is apriori unknown. */
vki_priv_impl_info_t first_cut[100];
SysRes sres = VG_(do_syscall5)(SYS_privsys, VKI_PRIVSYS_GETIMPLINFO,
0, 0, (UWord) first_cut,
@@ -866,10 +866,10 @@
const HChar *coreext = "";
Int core_fd;
- if (VG_(clo_log_fname_expanded) != NULL) {
+ if (VG_(clo_log_fname_unexpanded) != NULL) {
coreext = ".core";
basename = VG_(expand_file_name)("--log-file",
- VG_(clo_log_fname_expanded));
+ VG_(clo_log_fname_unexpanded));
}
vg_assert(coreext != NULL);
diff --git a/coregrind/m_cpuid.S b/coregrind/m_cpuid.S
index 9ba75ec..ed1c0af 100644
--- a/coregrind/m_cpuid.S
+++ b/coregrind/m_cpuid.S
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_debuginfo/d3basics.c b/coregrind/m_debuginfo/d3basics.c
index 190ada1..088fa07 100644
--- a/coregrind/m_debuginfo/d3basics.c
+++ b/coregrind/m_debuginfo/d3basics.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2015 OpenWorks LLP
+ Copyright (C) 2008-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -426,9 +426,6 @@
if (regno == 30) { *a = regs->fp; return True; }
# elif defined(VGP_arm64_linux)
if (regno == 31) { *a = regs->sp; return True; }
-# elif defined(VGP_tilegx_linux)
- if (regno == 52) { *a = regs->fp; return True; }
- if (regno == 54) { *a = regs->sp; return True; }
# else
# error "Unknown platform"
# endif
diff --git a/coregrind/m_debuginfo/debuginfo.c b/coregrind/m_debuginfo/debuginfo.c
index b9c74a7..24814d8 100644
--- a/coregrind/m_debuginfo/debuginfo.c
+++ b/coregrind/m_debuginfo/debuginfo.c
@@ -9,7 +9,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -105,8 +105,7 @@
/*--- fwdses ---*/
/*------------------------------------------------------------*/
-static UInt debuginfo_generation = 0;
-static void cfsi_m_cache__invalidate ( void );
+static void caches__invalidate (void);
/*------------------------------------------------------------*/
@@ -586,8 +585,8 @@
less independently. */
vg_assert(debugInfo_list == NULL);
- /* flush the CFI fast query cache. */
- cfsi_m_cache__invalidate();
+ /* flush the debug info caches. */
+ caches__invalidate();
}
@@ -757,8 +756,8 @@
TRACE_SYMTAB("\n------ Canonicalising the "
"acquired info ------\n");
- /* invalidate the CFI unwind cache. */
- cfsi_m_cache__invalidate();
+ /* invalidate the debug info caches. */
+ caches__invalidate();
/* prepare read data for use */
ML_(canonicaliseTables)( di );
/* Check invariants listed in
@@ -954,9 +953,6 @@
# elif defined(VGP_s390x_linux)
is_rx_map = seg->hasR && seg->hasX && !seg->hasW;
is_rw_map = seg->hasR && seg->hasW;
-# elif defined(VGA_tilegx)
- is_rx_map = seg->hasR && seg->hasX; // && !seg->hasW;
- is_rw_map = seg->hasR && seg->hasW; // && !seg->hasX;
# else
# error "Unknown platform"
# endif
@@ -1082,7 +1078,7 @@
if (0) VG_(printf)("DISCARD %#lx %#lx\n", a, a+len);
anyFound = discard_syms_in_range(a, len);
if (anyFound)
- cfsi_m_cache__invalidate();
+ caches__invalidate();
}
@@ -1099,7 +1095,7 @@
if (0 && !exe_ok) {
Bool anyFound = discard_syms_in_range(a, len);
if (anyFound)
- cfsi_m_cache__invalidate();
+ caches__invalidate();
}
}
@@ -1394,9 +1390,9 @@
if (VG_(clo_verbosity) > 0)
VG_(message)(Vg_UserMsg, "LOAD_PDB_DEBUGINFO: pdbname: %s\n", pdbname);
- /* play safe; always invalidate the CFI cache. I don't know if
+ /* play safe; always invalidate the debug info caches. I don't know if
this is necessary, but anyway .. */
- cfsi_m_cache__invalidate();
+ caches__invalidate();
/* dump old info for this range, if any */
discard_syms_in_range( avma_obj, total_size );
@@ -1647,7 +1643,6 @@
*/
static void search_all_symtabs ( Addr ptr, /*OUT*/DebugInfo** pdi,
/*OUT*/Word* symno,
- Bool match_anywhere_in_sym,
Bool findText )
{
Word sno;
@@ -1691,8 +1686,7 @@
if (!inRange) continue;
- sno = ML_(search_one_symtab) (
- di, ptr, match_anywhere_in_sym, findText );
+ sno = ML_(search_one_symtab) ( di, ptr, findText );
if (sno == -1) goto not_found;
*symno = sno;
*pdi = di;
@@ -1728,6 +1722,40 @@
*pdi = NULL;
}
+/* Caching of queries to symbol names. */
+// Prime number, giving about 6Kbytes cache on 32 bits,
+// 12Kbytes cache on 64 bits.
+#define N_SYM_NAME_CACHE 509
+
+typedef
+ struct {
+ Addr sym_avma;
+ const HChar* sym_name;
+ PtrdiffT offset : (sizeof(PtrdiffT)*8)-1;
+ Bool isText : 1;
+ }
+ Sym_Name_CacheEnt;
+/* Sym_Name_CacheEnt associates a queried address to the sym name found.
+ By nature, if a sym name was found, it means the searched address
+ stored in the cache is an avma (see e.g. search_all_symtabs).
+ Note however that the caller is responsibe to work with 'avma'
+ addresses e.g. when calling VG_(get_fnname) : m_debuginfo.c has
+ no way to differentiate an 'svma a' from an 'avma a'. It is however
+ unlikely that svma would percolate outside of this module. */
+
+static Sym_Name_CacheEnt sym_name_cache[N_SYM_NAME_CACHE];
+
+static const HChar* no_sym_name = "<<<noname>>>";
+/* We need a special marker for the address 0 : a not used entry has
+ a zero sym_avma. So, if ever the 0 address is really queried, we need
+ to be able to detect there is no sym name for this address.
+ If on some platforms, 0 is associated to a symbol, the cache would
+ work properly. */
+
+static void sym_name_cache__invalidate ( void ) {
+ VG_(memset)(&sym_name_cache, 0, sizeof(sym_name_cache));
+ sym_name_cache[0].sym_name = no_sym_name;
+}
/* The whole point of this whole big deal: map a code address to a
plausible symbol name. Returns False if no idea; otherwise True.
@@ -1736,13 +1764,15 @@
call has come from VG_(get_fnname_raw)(). findText
indicates whether we're looking for a text symbol or a data symbol
-- caller must choose one kind or the other.
- Note: the string returned in *BUF is persistent as long as
+ NOTE: See IMPORTANT COMMENT above about persistence and ownership
+ in pub_tool_debuginfo.h
+ get_sym_name and the fact it calls the demangler is the main reason
+ for non persistence of the information returned by m_debuginfo.c
+ functions : the string returned in *BUF is persistent as long as
(1) the DebugInfo it belongs to is not discarded
- (2) the segment containing the address is not merged with another segment
- (3) the demangler is not invoked again
- In other words: if in doubt, save it away.
+ (2) the demangler is not invoked again
Also, the returned string is owned by "somebody else". Callers must
- not free it or modify it. */
+ not free it or modify it.*/
static
Bool get_sym_name ( Bool do_cxx_demangling, Bool do_z_demangling,
Bool do_below_main_renaming,
@@ -1750,34 +1780,48 @@
Bool match_anywhere_in_sym, Bool show_offset,
Bool findText, /*OUT*/PtrdiffT* offsetP )
{
- DebugInfo* di;
- Word sno;
- PtrdiffT offset;
+ UWord hash = a % N_SYM_NAME_CACHE;
+ Sym_Name_CacheEnt* se = &sym_name_cache[hash];
- search_all_symtabs ( a, &di, &sno, match_anywhere_in_sym, findText );
- if (di == NULL) {
+ if (UNLIKELY(se->sym_avma != a || se->isText != findText)) {
+ DebugInfo* di;
+ Word sno;
+
+ search_all_symtabs ( a, &di, &sno, findText );
+ se->sym_avma = a;
+ se->isText = findText;
+ if (di == NULL || a == 0)
+ se->sym_name = no_sym_name;
+ else {
+ vg_assert(di->symtab[sno].pri_name);
+ se->sym_name = di->symtab[sno].pri_name;
+ se->offset = a - di->symtab[sno].avmas.main;
+ }
+ }
+
+ if (se->sym_name == no_sym_name
+ || (!match_anywhere_in_sym && se->offset != 0)) {
*buf = "";
return False;
}
- vg_assert(di->symtab[sno].pri_name);
VG_(demangle) ( do_cxx_demangling, do_z_demangling,
- di->symtab[sno].pri_name, buf );
+ se->sym_name, buf );
/* Do the below-main hack */
// To reduce the endless nuisance of multiple different names
// for "the frame below main()" screwing up the testsuite, change all
// known incarnations of said into a single name, "(below main)", if
// --show-below-main=yes.
- if ( do_below_main_renaming && ! VG_(clo_show_below_main) &&
- Vg_FnNameBelowMain == VG_(get_fnname_kind)(*buf) )
+ if ( do_below_main_renaming && ! VG_(clo_show_below_main)
+ && Vg_FnNameBelowMain == VG_(get_fnname_kind)(*buf) )
{
*buf = "(below main)";
}
- offset = a - di->symtab[sno].avmas.main;
- if (offsetP) *offsetP = offset;
- if (show_offset && offset != 0) {
+ if (offsetP) *offsetP = se->offset;
+
+ if (show_offset && se->offset != 0) {
static HChar *bufwo; // buf with offset
static SizeT bufwo_szB;
SizeT need, len;
@@ -1791,8 +1835,8 @@
VG_(strcpy)(bufwo, *buf);
VG_(sprintf)(bufwo + len, "%c%ld",
- offset < 0 ? '-' : '+',
- offset < 0 ? -offset : offset);
+ se->offset < 0 ? '-' : '+',
+ (PtrdiffT) (se->offset < 0 ? -se->offset : se->offset));
*buf = bufwo;
}
@@ -1809,7 +1853,6 @@
Word sno;
search_all_symtabs ( guest_code_addr,
&si, &sno,
- True/*match_anywhere_in_fun*/,
True/*consider text symbols only*/ );
if (si == NULL)
return 0;
@@ -1822,8 +1865,8 @@
/* This is available to tools... always demangle C++ names,
match anywhere in function, but don't show offsets.
- NOTE: See important comment about the persistence and memory ownership
- of the return string at function get_sym_name */
+ NOTE: See IMPORTANT COMMENT above about persistence and ownership
+ in pub_tool_debuginfo.h */
Bool VG_(get_fnname) ( Addr a, const HChar** buf )
{
return get_sym_name ( /*C++-demangle*/True, /*Z-demangle*/True,
@@ -1831,14 +1874,14 @@
a, buf,
/*match_anywhere_in_fun*/True,
/*show offset?*/False,
- /*text syms only*/True,
+ /*text sym*/True,
/*offsetP*/NULL );
}
/* This is available to tools... always demangle C++ names,
match anywhere in function, and show offset if nonzero.
- NOTE: See important comment about the persistence and memory ownership
- of the return string at function get_sym_name */
+ NOTE: See IMPORTANT COMMENT above about persistence and ownership
+ in pub_tool_debuginfo.h */
Bool VG_(get_fnname_w_offset) ( Addr a, const HChar** buf )
{
return get_sym_name ( /*C++-demangle*/True, /*Z-demangle*/True,
@@ -1846,15 +1889,15 @@
a, buf,
/*match_anywhere_in_fun*/True,
/*show offset?*/True,
- /*text syms only*/True,
+ /*text sym*/True,
/*offsetP*/NULL );
}
/* This is available to tools... always demangle C++ names,
only succeed if 'a' matches first instruction of function,
and don't show offsets.
- NOTE: See important comment about the persistence and memory ownership
- of the return string at function get_sym_name */
+ NOTE: See IMPORTANT COMMENT above about persistence and ownership
+ in pub_tool_debuginfo.h */
Bool VG_(get_fnname_if_entry) ( Addr a, const HChar** buf )
{
const HChar *tmp;
@@ -1865,7 +1908,7 @@
a, &tmp,
/*match_anywhere_in_fun*/False,
/*show offset?*/False,
- /*text syms only*/True,
+ /*text sym*/True,
/*offsetP*/NULL );
if (res)
*buf = tmp;
@@ -1875,8 +1918,8 @@
/* This is only available to core... don't C++-demangle, don't Z-demangle,
don't rename below-main, match anywhere in function, and don't show
offsets.
- NOTE: See important comment about the persistence and memory ownership
- of the return string at function get_sym_name */
+ NOTE: See IMPORTANT COMMENT above about persistence and ownership
+ in pub_tool_debuginfo.h */
Bool VG_(get_fnname_raw) ( Addr a, const HChar** buf )
{
return get_sym_name ( /*C++-demangle*/False, /*Z-demangle*/False,
@@ -1884,15 +1927,15 @@
a, buf,
/*match_anywhere_in_fun*/True,
/*show offset?*/False,
- /*text syms only*/True,
+ /*text sym*/True,
/*offsetP*/NULL );
}
/* This is only available to core... don't demangle C++ names, but do
do Z-demangling and below-main-renaming, match anywhere in function, and
don't show offsets.
- NOTE: See important comment about the persistence and memory ownership
- of the return string at function get_sym_name */
+ NOTE: See IMPORTANT COMMENT above about persistence and ownership
+ in pub_tool_debuginfo.h */
Bool VG_(get_fnname_no_cxx_demangle) ( Addr a, const HChar** buf,
const InlIPCursor* iipc )
{
@@ -1903,7 +1946,7 @@
a, buf,
/*match_anywhere_in_fun*/True,
/*show offset?*/False,
- /*text syms only*/True,
+ /*text sym*/True,
/*offsetP*/NULL );
} else {
const DiInlLoc *next_inl = iipc && iipc->next_inltab >= 0
@@ -1928,7 +1971,7 @@
a, &fnname,
/*match_anywhere_in_sym*/True,
/*show offset?*/False,
- /*text syms only*/True,
+ /*text sym*/True,
offset );
}
@@ -1974,8 +2017,8 @@
/* Looks up data_addr in the collection of data symbols, and if found
puts a pointer to its name into dname. The name is zero terminated.
Also data_addr's offset from the symbol start is put into *offset.
- NOTE: See important comment about the persistence and memory ownership
- of the return string at function get_sym_name */
+ NOTE: See IMPORTANT COMMENT above about persistence and ownership
+ in pub_tool_debuginfo.h */
Bool VG_(get_datasym_and_offset)( Addr data_addr,
/*OUT*/const HChar** dname,
/*OUT*/PtrdiffT* offset )
@@ -1985,7 +2028,7 @@
data_addr, dname,
/*match_anywhere_in_sym*/True,
/*show offset?*/False,
- /*data syms only please*/False,
+ /*text sym*/False,
offset );
}
@@ -1995,7 +2038,7 @@
(1) the DebugInfo it belongs to is not discarded
(2) the segment containing the address is not merged with another segment
*/
-Bool VG_(get_objname) ( Addr a, const HChar** buf )
+Bool VG_(get_objname) ( Addr a, const HChar** objname )
{
DebugInfo* di;
const NSegment *seg;
@@ -2008,7 +2051,7 @@
&& di->text_size > 0
&& di->text_avma <= a
&& a < di->text_avma + di->text_size) {
- *buf = di->fsm.filename;
+ *objname = di->fsm.filename;
return True;
}
}
@@ -2019,7 +2062,7 @@
when running programs under wine. */
if ( (seg = VG_(am_find_nsegment)(a)) != NULL
&& (filename = VG_(am_get_filename)(seg)) != NULL ) {
- *buf = filename;
+ *objname = filename;
return True;
}
return False;
@@ -2497,11 +2540,6 @@
|| defined(VGA_ppc64le)
# elif defined(VGP_arm64_linux)
case Creg_ARM64_X30: return eec->uregs->x30;
-# elif defined(VGA_tilegx)
- case Creg_TILEGX_IP: return eec->uregs->pc;
- case Creg_TILEGX_SP: return eec->uregs->sp;
- case Creg_TILEGX_BP: return eec->uregs->fp;
- case Creg_TILEGX_LR: return eec->uregs->lr;
# else
# error "Unsupported arch"
# endif
@@ -2652,12 +2690,6 @@
static void cfsi_m_cache__invalidate ( void ) {
VG_(memset)(&cfsi_m_cache, 0, sizeof(cfsi_m_cache));
- debuginfo_generation++;
-}
-
-UInt VG_(debuginfo_generation) (void)
-{
- return debuginfo_generation;
}
static inline CFSI_m_CacheEnt* cfsi_m_cache__find ( Addr ip )
@@ -2760,16 +2792,6 @@
case CFIC_ARM64_X29REL:
cfa = cfsi_m->cfa_off + uregs->x29;
break;
-# elif defined(VGA_tilegx)
- case CFIC_IA_SPREL:
- cfa = cfsi_m->cfa_off + uregs->sp;
- break;
- case CFIR_SAME:
- cfa = uregs->fp;
- break;
- case CFIC_IA_BPREL:
- cfa = cfsi_m->cfa_off + uregs->fp;
- break;
# else
# error "Unsupported arch"
# endif
@@ -2824,7 +2846,7 @@
return compute_cfa(&uregs,
min_accessible, max_accessible, ce->di, ce->cfsi_m);
}
-#elif defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_tilegx)
+#elif defined(VGA_mips32) || defined(VGA_mips64)
{ D3UnwindRegs uregs;
uregs.pc = ip;
uregs.sp = sp;
@@ -2904,8 +2926,6 @@
# elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
# elif defined(VGP_arm64_linux)
ipHere = uregsHere->pc;
-# elif defined(VGA_tilegx)
- ipHere = uregsHere->pc;
# else
# error "Unknown arch"
# endif
@@ -2991,10 +3011,6 @@
COMPUTE(uregsPrev.sp, uregsHere->sp, cfsi_m->sp_how, cfsi_m->sp_off);
COMPUTE(uregsPrev.x30, uregsHere->x30, cfsi_m->x30_how, cfsi_m->x30_off);
COMPUTE(uregsPrev.x29, uregsHere->x29, cfsi_m->x29_how, cfsi_m->x29_off);
-# elif defined(VGA_tilegx)
- COMPUTE(uregsPrev.pc, uregsHere->pc, cfsi_m->ra_how, cfsi_m->ra_off);
- COMPUTE(uregsPrev.sp, uregsHere->sp, cfsi_m->sp_how, cfsi_m->sp_off);
- COMPUTE(uregsPrev.fp, uregsHere->fp, cfsi_m->fp_how, cfsi_m->fp_off);
# else
# error "Unknown arch"
# endif
@@ -4349,7 +4365,7 @@
in *name. The returned name, if any, should be saved away, if there is
a chance that a debug-info will be discarded and the name is being
used later on. */
-VgSectKind VG_(DebugInfo_sect_kind)( /*OUT*/const HChar** name, Addr a)
+VgSectKind VG_(DebugInfo_sect_kind)( /*OUT*/const HChar** objname, Addr a)
{
DebugInfo* di;
VgSectKind res = Vg_SectUnknown;
@@ -4426,11 +4442,11 @@
vg_assert( (di == NULL && res == Vg_SectUnknown)
|| (di != NULL && res != Vg_SectUnknown) );
- if (name) {
+ if (objname) {
if (di && di->fsm.filename) {
- *name = di->fsm.filename;
+ *objname = di->fsm.filename;
} else {
- *name = "???";
+ *objname = "???";
}
}
@@ -4438,6 +4454,19 @@
}
+static UInt debuginfo_generation = 0;
+
+UInt VG_(debuginfo_generation) (void)
+{
+ return debuginfo_generation;
+}
+
+static void caches__invalidate ( void ) {
+ cfsi_m_cache__invalidate();
+ sym_name_cache__invalidate();
+ debuginfo_generation++;
+}
+
/*--------------------------------------------------------------------*/
/*--- end ---*/
/*--------------------------------------------------------------------*/
diff --git a/coregrind/m_debuginfo/image.c b/coregrind/m_debuginfo/image.c
index b92f732..61e75f6 100644
--- a/coregrind/m_debuginfo/image.c
+++ b/coregrind/m_debuginfo/image.c
@@ -9,7 +9,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2013-2015 Mozilla Foundation
+ Copyright (C) 2013-2017 Mozilla Foundation
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -55,11 +55,12 @@
#define CACHE_ENTRY_SIZE (1 << CACHE_ENTRY_SIZE_BITS)
-#define COMMPRESSED_SLICE_ARRAY_GROW_SIZE 64
+#define COMPRESSED_SLICE_ARRAY_GROW_SIZE 64
/* An entry in the cache. */
typedef
struct {
+ Bool fromC; // True === contains decompressed data
DiOffT off; // file offset for data[0]
SizeT size; // sizeof(data)
SizeT used; // 1 .. sizeof(data), or 0 to denote not-in-use
@@ -117,6 +118,44 @@
UInt cslc_size;
};
+
+/* Sanity check code for CEnts. */
+static void pp_CEnt(const HChar* msg, CEnt* ce)
+{
+ VG_(printf)("%s: fromC %s, used %llu, size %llu, offset %llu\n",
+ msg, ce->fromC ? "True" : "False",
+ (ULong)ce->used, (ULong)ce->size, (ULong)ce->off);
+}
+
+static Bool is_sane_CEnt ( const HChar* who, const DiImage* img, UInt i )
+{
+ vg_assert(img);
+ vg_assert(i <= CACHE_N_ENTRIES);
+
+ CEnt* ce = img->ces[i];
+ if (!(ce->used <= ce->size)) goto fail;
+ if (ce->fromC) {
+ // ce->size can be anything, but ce->used must be either the
+ // same or zero, in the case that it hasn't been set yet.
+ // Similarly, ce->off must either be above the real_size
+ // threshold, or zero if it hasn't been set yet.
+ if (!(ce->off >= img->real_size || ce->off == 0)) goto fail;
+ if (!(ce->off + ce->used <= img->size)) goto fail;
+ if (!(ce->used == ce->size || ce->used == 0)) goto fail;
+ } else {
+ if (!(ce->size == CACHE_ENTRY_SIZE)) goto fail;
+ if (!(ce->off >= 0)) goto fail;
+ if (!(ce->off + ce->used <= img->real_size)) goto fail;
+ }
+ return True;
+
+ fail:
+ VG_(printf)("is_sane_CEnt[%u]: fail: %s\n", i, who);
+ pp_CEnt("failing CEnt", ce);
+ return False;
+}
+
+
/* A frame. The first 4 bytes of |data| give the kind of the frame,
and the rest of it is kind-specific data. */
typedef struct { UChar* data; SizeT n_data; } Frame;
@@ -452,23 +491,31 @@
}
/* Allocate a new CEnt, connect it to |img|, and return its index. */
-static UInt alloc_CEnt ( DiImage* img, SizeT szB )
+static UInt alloc_CEnt ( DiImage* img, SizeT szB, Bool fromC )
{
vg_assert(img != NULL);
vg_assert(img->ces_used < CACHE_N_ENTRIES);
- vg_assert(szB >= CACHE_ENTRY_SIZE);
+ if (fromC) {
+ // szB can be arbitrary
+ } else {
+ vg_assert(szB == CACHE_ENTRY_SIZE);
+ }
UInt entNo = img->ces_used;
img->ces_used++;
vg_assert(img->ces[entNo] == NULL);
img->ces[entNo] = ML_(dinfo_zalloc)("di.alloc_CEnt.1",
offsetof(CEnt, data) + szB);
img->ces[entNo]->size = szB;
+ img->ces[entNo]->fromC = fromC;
+ vg_assert(is_sane_CEnt("alloc_CEnt", img, entNo));
return entNo;
}
-static void realloc_CEnt ( DiImage* img, UInt entNo, SizeT szB ) {
+static void realloc_CEnt ( DiImage* img, UInt entNo, SizeT szB )
+{
vg_assert(img != NULL);
vg_assert(szB >= CACHE_ENTRY_SIZE);
+ vg_assert(is_sane_CEnt("realloc_CEnt-pre", img, entNo));
img->ces[entNo] = ML_(dinfo_realloc)("di.realloc_CEnt.1",
img->ces[entNo],
offsetof(CEnt, data) + szB);
@@ -594,7 +641,9 @@
ce->off = off;
ce->used = len;
- vg_assert(ce->used > 0 && ce->used <= ce->size);
+ ce->fromC = False;
+ vg_assert(ce == img->ces[entNo]);
+ vg_assert(is_sane_CEnt("set_CEnt", img, entNo));
}
__attribute__((noinline))
@@ -611,58 +660,144 @@
if (is_in_CEnt(img->ces[i], off))
break;
}
+ vg_assert(i >= 1);
+
+ if (LIKELY(i < img->ces_used)) {
+ // Found it. Move to the top and stop.
+ move_CEnt_to_top(img, i);
+ vg_assert(is_in_CEnt(img->ces[0], off));
+ return img->ces[0]->data[ off - img->ces[0]->off ];
+ }
+
vg_assert(i <= img->ces_used);
- if (i == img->ces_used) {
- /* It's not in any entry. Either allocate a new entry or
- recycle the LRU one. */
- CSlc* cslc = find_cslc(img, off);
- UChar* buf = NULL;
- if (cslc != NULL) {
- SizeT len = 0;
- buf = ML_(dinfo_zalloc)("di.image.get_slowcase.1", cslc->szC);
- // get compressed data
- while (len < cslc->szC)
- len += ML_(img_get_some)(buf + len, img, cslc->offC + len,
- cslc->szC - len);
- }
+ // It's not in any entry. Either allocate a new one or recycle the LRU
+ // one. This is where the presence of compressed sections makes things
+ // tricky. There are 4 cases to consider:
+ //
+ // (1) not from a compressed slice, we can allocate a new entry
+ // (2) not from a compressed slice, we have to recycle the LRU entry
+ // (3) from a compressed slice, we can allocate a new entry
+ // (4) from a compressed slice, we have to recycle the LRU entry
+ //
+ // Cases (3) and (4) are complex because we will have to call
+ // ML_(img_get_some) to get the compressed data. But this function is
+ // reachable from ML_(img_get_some), so we may re-enter get_slowcase a
+ // second time as a result. Given that the compressed data will be cause
+ // only cases (1) and (2) to happen, this guarantees no infinite recursion.
+ // It does however mean that we can't carry (in this function invokation)
+ // any local copies of the overall cache state across the ML_(img_get_some)
+ // call, since it may become invalidated by the recursive call to
+ // get_slowcase.
- if (img->ces_used == CACHE_N_ENTRIES) {
- /* All entries in use. Recycle the (ostensibly) LRU one. */
- i = CACHE_N_ENTRIES-1;
- if ((cslc != NULL) && (cslc->szD > img->ces[i]->size))
- realloc_CEnt(img, i, cslc->szD);
+ // First of all, see if it is in a compressed slice, and if so, pull the
+ // compressed data into an intermediate buffer. Given the preceding
+ // comment, this is a safe place to do it, since we are not carrying any
+ // cache state here apart from the knowledge that the requested offset is
+ // not in the cache at all, and the recursive call won't change that fact.
+
+ CSlc* cslc = find_cslc(img, off);
+ UChar* cbuf = NULL;
+ if (cslc != NULL) {
+ SizeT len = 0;
+ cbuf = ML_(dinfo_zalloc)("di.image.get_slowcase.cbuf-1", cslc->szC);
+ // get compressed data
+ while (len < cslc->szC)
+ len += ML_(img_get_some)(cbuf + len, img, cslc->offC + len,
+ cslc->szC - len);
+ }
+
+ // Now we can do what we like.
+ vg_assert((cslc == NULL && cbuf == NULL) || (cslc != NULL && cbuf != NULL));
+
+ // Note, we can't capture this earlier, for exactly the reasons detailed
+ // above.
+ UInt ces_used_at_entry = img->ces_used;
+
+ // This is the size of the CEnt that we want to have after allocation or
+ // recycling.
+ SizeT size = (cslc == NULL) ? CACHE_ENTRY_SIZE : cslc->szD;
+
+ // Cases (1) and (3)
+ if (img->ces_used < CACHE_N_ENTRIES) {
+ /* Allocate a new cache entry, and fill it in. */
+ i = alloc_CEnt(img, size, /*fromC?*/cslc != NULL);
+ if (cslc == NULL) {
+ set_CEnt(img, i, off);
+ img->ces[i]->fromC = False;
+ vg_assert(is_sane_CEnt("get_slowcase-case-1", img, i));
+ vg_assert(img->ces_used == ces_used_at_entry + 1);
} else {
- /* Allocate a new one, and fill it in. */
- SizeT size = CACHE_ENTRY_SIZE;
- if ((cslc != NULL) && (cslc->szD > CACHE_ENTRY_SIZE))
- size = cslc->szD;
- i = alloc_CEnt(img, size);
- }
-
- if (cslc != NULL) {
SizeT len = tinfl_decompress_mem_to_mem(
img->ces[i]->data, cslc->szD,
- buf, cslc->szC,
+ cbuf, cslc->szC,
TINFL_FLAG_USING_NON_WRAPPING_OUTPUT_BUF
| TINFL_FLAG_PARSE_ZLIB_HEADER);
- vg_assert(len == cslc->szD);
+ vg_assert(len == cslc->szD); // sanity check on data, FIXME
+ vg_assert(cslc->szD == size);
img->ces[i]->used = cslc->szD;
img->ces[i]->off = cslc->offD;
- ML_(dinfo_free)(buf);
- } else {
- set_CEnt(img, i, off);
+ img->ces[i]->fromC = True;
+ vg_assert(is_sane_CEnt("get_slowcase-case-3", img, i));
+ vg_assert(img->ces_used == ces_used_at_entry + 1);
}
-
- } else {
- /* We found it at position 'i'. */
- vg_assert(i > 0);
+ vg_assert(img->ces_used == ces_used_at_entry + 1);
+ if (i > 0) {
+ move_CEnt_to_top(img, i);
+ i = 0;
+ }
+ vg_assert(is_in_CEnt(img->ces[i], off));
+ if (cbuf != NULL) {
+ ML_(dinfo_free)(cbuf);
+ }
+ return img->ces[i]->data[ off - img->ces[i]->off ];
}
+
+ // Cases (2) and (4)
+ /* All entries in use. Recycle the (ostensibly) LRU one. But try to find
+ a non-fromC entry to recycle, though, since discarding and reloading
+ fromC entries is very expensive. The result is that -- unless all
+ CACHE_N_ENTRIES wind up being used by decompressed slices, which is
+ highly unlikely -- we'll wind up keeping all the decompressed data in
+ the cache for its entire remaining life. We could probably do better
+ but it would make the cache management even more complex. */
+ vg_assert(img->ces_used == CACHE_N_ENTRIES);
+
+ // Select entry to recycle.
+ for (i = CACHE_N_ENTRIES-1; i > 0; i--) {
+ if (!img->ces[i]->fromC)
+ break;
+ }
+ vg_assert(i >= 0 && i < CACHE_N_ENTRIES);
+
+ realloc_CEnt(img, i, size);
+ img->ces[i]->size = size;
+ img->ces[i]->used = 0;
+ if (cslc == NULL) {
+ set_CEnt(img, i, off);
+ img->ces[i]->fromC = False;
+ vg_assert(is_sane_CEnt("get_slowcase-case-2", img, i));
+ } else {
+ SizeT len = tinfl_decompress_mem_to_mem(
+ img->ces[i]->data, cslc->szD,
+ cbuf, cslc->szC,
+ TINFL_FLAG_USING_NON_WRAPPING_OUTPUT_BUF
+ | TINFL_FLAG_PARSE_ZLIB_HEADER);
+ vg_assert(len == size);
+ img->ces[i]->used = size;
+ img->ces[i]->off = cslc->offD;
+ img->ces[i]->fromC = True;
+ vg_assert(is_sane_CEnt("get_slowcase-case-4", img, i));
+ }
+ vg_assert(img->ces_used == ces_used_at_entry);
if (i > 0) {
move_CEnt_to_top(img, i);
i = 0;
}
vg_assert(is_in_CEnt(img->ces[i], off));
+ if (cbuf != NULL) {
+ ML_(dinfo_free)(cbuf);
+ }
return img->ces[i]->data[ off - img->ces[i]->off ];
}
@@ -724,7 +859,7 @@
loading it at this point forcing img->cent[0] to always be
non-empty, thereby saving us an is-it-empty check on the fast
path in get(). */
- UInt entNo = alloc_CEnt(img, CACHE_ENTRY_SIZE);
+ UInt entNo = alloc_CEnt(img, CACHE_ENTRY_SIZE, False/*!fromC*/);
vg_assert(entNo == 0);
set_CEnt(img, 0, 0);
@@ -815,7 +950,7 @@
/* See comment on equivalent bit in ML_(img_from_local_file) for
rationale. */
- UInt entNo = alloc_CEnt(img, CACHE_ENTRY_SIZE);
+ UInt entNo = alloc_CEnt(img, CACHE_ENTRY_SIZE, False/*!fromC*/);
vg_assert(entNo == 0);
set_CEnt(img, 0, 0);
@@ -849,7 +984,7 @@
vg_assert(offset + szC <= img->size);
if (img->cslc_used == img->cslc_size) {
- img->cslc_size += COMMPRESSED_SLICE_ARRAY_GROW_SIZE;
+ img->cslc_size += COMPRESSED_SLICE_ARRAY_GROW_SIZE;
img->cslc = ML_(dinfo_realloc)("di.image.ML_img_mark_compressed_part.1",
img->cslc, img->cslc_size * sizeof(CSlc));
}
diff --git a/coregrind/m_debuginfo/misc.c b/coregrind/m_debuginfo/misc.c
index 03cbf03..519a4f3 100644
--- a/coregrind/m_debuginfo/misc.c
+++ b/coregrind/m_debuginfo/misc.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2015 OpenWorks LLP
+ Copyright (C) 2008-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_debuginfo/priv_d3basics.h b/coregrind/m_debuginfo/priv_d3basics.h
index b7eec6f..94472ab 100644
--- a/coregrind/m_debuginfo/priv_d3basics.h
+++ b/coregrind/m_debuginfo/priv_d3basics.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2015 OpenWorks LLP and others; see below
+ Copyright (C) 2008-2017 OpenWorks LLP and others; see below
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_debuginfo/priv_image.h b/coregrind/m_debuginfo/priv_image.h
index c230026..965a4a9 100644
--- a/coregrind/m_debuginfo/priv_image.h
+++ b/coregrind/m_debuginfo/priv_image.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2013-2015 Mozilla Foundation
+ Copyright (C) 2013-2017 Mozilla Foundation
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/m_debuginfo/priv_misc.h b/coregrind/m_debuginfo/priv_misc.h
index d3adb7d..10591f9 100644
--- a/coregrind/m_debuginfo/priv_misc.h
+++ b/coregrind/m_debuginfo/priv_misc.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2015 OpenWorks LLP
+ Copyright (C) 2008-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_debuginfo/priv_readdwarf.h b/coregrind/m_debuginfo/priv_readdwarf.h
index 6cdf26e..eecdcd4 100644
--- a/coregrind/m_debuginfo/priv_readdwarf.h
+++ b/coregrind/m_debuginfo/priv_readdwarf.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_debuginfo/priv_readdwarf3.h b/coregrind/m_debuginfo/priv_readdwarf3.h
index 3cccc68..c7223d0 100644
--- a/coregrind/m_debuginfo/priv_readdwarf3.h
+++ b/coregrind/m_debuginfo/priv_readdwarf3.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2015 OpenWorks LLP
+ Copyright (C) 2008-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_debuginfo/priv_readelf.h b/coregrind/m_debuginfo/priv_readelf.h
index 17d3761..9b38742 100644
--- a/coregrind/m_debuginfo/priv_readelf.h
+++ b/coregrind/m_debuginfo/priv_readelf.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_debuginfo/priv_readexidx.h b/coregrind/m_debuginfo/priv_readexidx.h
index 49c1d1a..66ae483 100644
--- a/coregrind/m_debuginfo/priv_readexidx.h
+++ b/coregrind/m_debuginfo/priv_readexidx.h
@@ -9,7 +9,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2014-2015 Mozilla Foundation
+ Copyright (C) 2014-2017 Mozilla Foundation
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/m_debuginfo/priv_readpdb.h b/coregrind/m_debuginfo/priv_readpdb.h
index a423799..97407d9 100644
--- a/coregrind/m_debuginfo/priv_readpdb.h
+++ b/coregrind/m_debuginfo/priv_readpdb.h
@@ -11,7 +11,7 @@
derived from readelf.c and valgrind-20031012-wine/vg_symtab2.c
derived from wine-1.0/tools/winedump/pdb.c and msc.c
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_debuginfo/priv_storage.h b/coregrind/m_debuginfo/priv_storage.h
index a43720a..061ecf2 100644
--- a/coregrind/m_debuginfo/priv_storage.h
+++ b/coregrind/m_debuginfo/priv_storage.h
@@ -9,7 +9,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -337,19 +337,6 @@
Int fp_off;
}
DiCfSI_m;
-#elif defined(VGA_tilegx)
-typedef
- struct {
- UChar cfa_how; /* a CFIC_IA value */
- UChar ra_how; /* a CFIR_ value */
- UChar sp_how; /* a CFIR_ value */
- UChar fp_how; /* a CFIR_ value */
- Int cfa_off;
- Int ra_off;
- Int sp_off;
- Int fp_off;
- }
- DiCfSI_m;
#else
# error "Unknown arch"
#endif
@@ -403,11 +390,7 @@
Creg_S390_SP,
Creg_S390_FP,
Creg_S390_LR,
- Creg_MIPS_RA,
- Creg_TILEGX_IP,
- Creg_TILEGX_SP,
- Creg_TILEGX_BP,
- Creg_TILEGX_LR
+ Creg_MIPS_RA
}
CfiReg;
@@ -913,7 +896,7 @@
cfsi_m_ix as in many case, one byte is good enough. For big
objects, 2 bytes are needed. No object has yet been found where
4 bytes are needed (but the code is ready to handle this case).
- Not covered ranges ('cfi holes') are stored explicitely in
+ Not covered ranges ('cfi holes') are stored explicitly in
cfsi_base/cfsi_m_ix as this is more memory efficient than storing
a length for each covered range : on x86 or amd64, we typically have
a hole every 8 covered ranges. On arm64, we have very few holes
@@ -1108,7 +1091,6 @@
/* Find a symbol-table index containing the specified pointer, or -1
if not found. Binary search. */
extern Word ML_(search_one_symtab) ( const DebugInfo* di, Addr ptr,
- Bool match_anywhere_in_sym,
Bool findText );
/* Find a location-table index containing the specified pointer, or -1
diff --git a/coregrind/m_debuginfo/priv_tytypes.h b/coregrind/m_debuginfo/priv_tytypes.h
index eae3701..adc0226 100644
--- a/coregrind/m_debuginfo/priv_tytypes.h
+++ b/coregrind/m_debuginfo/priv_tytypes.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2015 OpenWorks LLP
+ Copyright (C) 2008-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_debuginfo/readdwarf.c b/coregrind/m_debuginfo/readdwarf.c
index c40c3b1..70ab16d 100644
--- a/coregrind/m_debuginfo/readdwarf.c
+++ b/coregrind/m_debuginfo/readdwarf.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -853,7 +853,7 @@
if ( acode != abcode ) {
/* This isn't illegal, but somewhat unlikely. Normally the
* first abbrev describes the first DIE, the compile_unit.
- * But maybe this abbrevation data is shared with another
+ * But maybe this abbreviation data is shared with another
* or it is a NULL entry used for padding. See para 7.5.3. */
abbrev_img = lookup_abbrev( ML_(cur_plus)(debugabbrev_img, atoffs),
acode );
@@ -1732,10 +1732,6 @@
# define FP_REG 30
# define SP_REG 29
# define RA_REG_DEFAULT 31
-#elif defined(VGP_tilegx_linux)
-# define FP_REG 52
-# define SP_REG 54
-# define RA_REG_DEFAULT 55
#else
# error "Unknown platform"
#endif
@@ -1748,7 +1744,7 @@
|| defined(VGP_ppc64le_linux) || defined(VGP_mips32_linux) \
|| defined(VGP_mips64_linux)
# define N_CFI_REGS 72
-#elif defined(VGP_arm_linux) || defined(VGP_tilegx_linux)
+#elif defined(VGP_arm_linux)
# define N_CFI_REGS 320
#elif defined(VGP_arm64_linux)
# define N_CFI_REGS 128
@@ -1899,7 +1895,7 @@
Int data_a_f;
Addr initloc;
Int ra_reg;
- /* The rest of these fields can be modifed by
+ /* The rest of these fields can be modified by
run_CF_instruction. */
/* The LOC entry */
Addr loc;
@@ -2058,8 +2054,7 @@
if (ctxs->cfa_is_regoff && ctxs->cfa_reg == SP_REG) {
si_m->cfa_off = ctxs->cfa_off;
# if defined(VGA_x86) || defined(VGA_amd64) || defined(VGA_s390x) \
- || defined(VGA_mips32) || defined(VGA_mips64) \
- || defined(VGA_tilegx)
+ || defined(VGA_mips32) || defined(VGA_mips64)
si_m->cfa_how = CFIC_IA_SPREL;
# elif defined(VGA_arm)
si_m->cfa_how = CFIC_ARM_R13REL;
@@ -2073,8 +2068,7 @@
if (ctxs->cfa_is_regoff && ctxs->cfa_reg == FP_REG) {
si_m->cfa_off = ctxs->cfa_off;
# if defined(VGA_x86) || defined(VGA_amd64) || defined(VGA_s390x) \
- || defined(VGA_mips32) || defined(VGA_mips64) \
- || defined(VGA_tilegx)
+ || defined(VGA_mips32) || defined(VGA_mips64)
si_m->cfa_how = CFIC_IA_BPREL;
# elif defined(VGA_arm)
si_m->cfa_how = CFIC_ARM_R12REL;
@@ -2363,48 +2357,6 @@
*len = (UInt)(ctx->loc - loc_start);
return True;
-# elif defined(VGA_tilegx)
-
- /* --- entire tail of this fn specialised for tilegx --- */
-
- SUMMARISE_HOW(si_m->ra_how, si_m->ra_off,
- ctxs->reg[ctx->ra_reg] );
- SUMMARISE_HOW(si_m->fp_how, si_m->fp_off,
- ctxs->reg[FP_REG] );
- SUMMARISE_HOW(si_m->sp_how, si_m->sp_off,
- ctxs->reg[SP_REG] );
- si_m->sp_how = CFIR_CFAREL;
- si_m->sp_off = 0;
-
- if (si_m->fp_how == CFIR_UNKNOWN)
- si_m->fp_how = CFIR_SAME;
- if (si_m->cfa_how == CFIR_UNKNOWN) {
- si_m->cfa_how = CFIC_IA_SPREL;
- si_m->cfa_off = 160;
- }
- if (si_m->ra_how == CFIR_UNKNOWN) {
- if (!debuginfo->cfsi_exprs)
- debuginfo->cfsi_exprs = VG_(newXA)( ML_(dinfo_zalloc),
- "di.ccCt.2a",
- ML_(dinfo_free),
- sizeof(CfiExpr) );
- si_m->ra_how = CFIR_EXPR;
- si_m->ra_off = ML_(CfiExpr_CfiReg)( debuginfo->cfsi_exprs,
- Creg_TILEGX_LR);
- }
-
- if (si_m->ra_how == CFIR_SAME)
- { why = 3; goto failed; }
-
- if (loc_start >= ctx->loc)
- { why = 4; goto failed; }
- if (ctx->loc - loc_start > 10000000 /* let's say */)
- { why = 5; goto failed; }
-
- *base = loc_start + ctx->initloc;
- *len = (UInt)(ctx->loc - loc_start);
-
- return True;
# elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
/* These don't use CFI based unwinding (is that really true?) */
@@ -2501,13 +2453,6 @@
I_die_here;
# elif defined(VGA_ppc32) || defined(VGA_ppc64be) \
|| defined(VGA_ppc64le)
-# elif defined(VGA_tilegx)
- if (dwreg == SP_REG)
- return ML_(CfiExpr_CfiReg)( dstxa, Creg_TILEGX_SP );
- if (dwreg == FP_REG)
- return ML_(CfiExpr_CfiReg)( dstxa, Creg_TILEGX_BP );
- if (dwreg == srcuc->ra_reg)
- return ML_(CfiExpr_CfiReg)( dstxa, Creg_TILEGX_IP );
# else
# error "Unknown arch"
# endif
diff --git a/coregrind/m_debuginfo/readdwarf3.c b/coregrind/m_debuginfo/readdwarf3.c
index cfc9e59..4d8f21b 100644
--- a/coregrind/m_debuginfo/readdwarf3.c
+++ b/coregrind/m_debuginfo/readdwarf3.c
@@ -9,7 +9,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2015 OpenWorks LLP
+ Copyright (C) 2008-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_debuginfo/readelf.c b/coregrind/m_debuginfo/readelf.c
index 81f94ee..3c8e62b 100644
--- a/coregrind/m_debuginfo/readelf.c
+++ b/coregrind/m_debuginfo/readelf.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -524,7 +524,7 @@
http://gcc.gnu.org/ml/gcc-patches/2004-08/msg00557.html
*/
# if defined(VGP_ppc64be_linux)
- /* Host and guest may have different Endianess, used by BE only */
+ /* Host and guest may have different Endianness, used by BE only */
is_in_opd = False;
# endif
@@ -692,15 +692,15 @@
in_rx = (ML_(find_rx_mapping)(
di,
(*sym_avmas_out).main,
- (*sym_avmas_out).main + *sym_size_out) != NULL);
+ (*sym_avmas_out).main + *sym_size_out - 1) != NULL);
if (in_text)
vg_assert(in_rx);
if (!in_rx) {
TRACE_SYMTAB(
"ignore -- %#lx .. %#lx outside .text svma range %#lx .. %#lx\n",
- (*sym_avmas_out).main, (*sym_avmas_out).main + *sym_size_out,
+ (*sym_avmas_out).main, (*sym_avmas_out).main + *sym_size_out - 1,
di->text_avma,
- di->text_avma + di->text_size);
+ di->text_avma + di->text_size - 1);
return False;
}
} else {
@@ -708,7 +708,7 @@
TRACE_SYMTAB(
"ignore -- %#lx .. %#lx outside .data / .sdata / .rodata "
"/ .bss / .sbss svma ranges\n",
- (*sym_avmas_out).main, (*sym_avmas_out).main + *sym_size_out);
+ (*sym_avmas_out).main, (*sym_avmas_out).main + *sym_size_out - 1);
return False;
}
}
@@ -2278,7 +2278,7 @@
# if defined(VGP_x86_linux) || defined(VGP_amd64_linux) \
|| defined(VGP_arm_linux) || defined (VGP_s390x_linux) \
|| defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \
- || defined(VGP_arm64_linux) || defined(VGP_tilegx_linux) \
+ || defined(VGP_arm64_linux) \
|| defined(VGP_x86_solaris) || defined(VGP_amd64_solaris)
/* Accept .plt where mapped as rx (code) */
if (0 == VG_(strcmp)(name, ".plt")) {
diff --git a/coregrind/m_debuginfo/readexidx.c b/coregrind/m_debuginfo/readexidx.c
index 06a9a5f..e79dc6f 100644
--- a/coregrind/m_debuginfo/readexidx.c
+++ b/coregrind/m_debuginfo/readexidx.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2014-2015 Mozilla Foundation
+ Copyright (C) 2014-2017 Mozilla Foundation
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/m_debuginfo/readmacho.c b/coregrind/m_debuginfo/readmacho.c
index 3f48b2b..1f6a61f 100644
--- a/coregrind/m_debuginfo/readmacho.c
+++ b/coregrind/m_debuginfo/readmacho.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Apple Inc.
+ Copyright (C) 2005-2017 Apple Inc.
Greg Parker gparker@apple.com
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_debuginfo/readpdb.c b/coregrind/m_debuginfo/readpdb.c
index 1ebf863..b01a8cb 100644
--- a/coregrind/m_debuginfo/readpdb.c
+++ b/coregrind/m_debuginfo/readpdb.c
@@ -11,7 +11,7 @@
derived from readelf.c and valgrind-20031012-wine/vg_symtab2.c
derived from wine-1.0/tools/winedump/pdb.c and msc.c
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
Copyright 2006 Eric Pouech (winedump/pdb.c and msc.c)
GNU Lesser General Public License version 2.1 or later applies.
diff --git a/coregrind/m_debuginfo/storage.c b/coregrind/m_debuginfo/storage.c
index c46f4bd..9d6a3fd 100644
--- a/coregrind/m_debuginfo/storage.c
+++ b/coregrind/m_debuginfo/storage.c
@@ -9,7 +9,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -216,11 +216,6 @@
SHOW_HOW(si_m->x30_how, si_m->x30_off);
VG_(printf)(" X29=");
SHOW_HOW(si_m->x29_how, si_m->x29_off);
-# elif defined(VGA_tilegx)
- VG_(printf)(" SP=");
- SHOW_HOW(si_m->sp_how, si_m->sp_off);
- VG_(printf)(" FP=");
- SHOW_HOW(si_m->fp_how, si_m->fp_off);
# else
# error "Unknown arch"
# endif
@@ -950,10 +945,6 @@
case Creg_S390_SP: VG_(printf)("SP"); break;
case Creg_S390_FP: VG_(printf)("FP"); break;
case Creg_S390_LR: VG_(printf)("LR"); break;
- case Creg_TILEGX_IP: VG_(printf)("PC"); break;
- case Creg_TILEGX_SP: VG_(printf)("SP"); break;
- case Creg_TILEGX_BP: VG_(printf)("BP"); break;
- case Creg_TILEGX_LR: VG_(printf)("R55"); break;
default: vg_assert(0);
}
}
@@ -1713,7 +1704,7 @@
di->symtab[r].sec_names = NULL;
}
/* Completely zap the entry -- paranoia to make it more
- likely we'll notice if we inadvertantly use it
+ likely we'll notice if we inadvertently use it
again. */
VG_(memset)(&di->symtab[r], 0, sizeof(DiSym));
} else {
@@ -2360,11 +2351,10 @@
if not found. Binary search. */
Word ML_(search_one_symtab) ( const DebugInfo* di, Addr ptr,
- Bool match_anywhere_in_sym,
Bool findText )
{
Addr a_mid_lo, a_mid_hi;
- Word mid, size,
+ Word mid,
lo = 0,
hi = di->symtab_used-1;
while (True) {
@@ -2372,10 +2362,7 @@
if (lo > hi) return -1; /* not found */
mid = (lo + hi) / 2;
a_mid_lo = di->symtab[mid].avmas.main;
- size = ( match_anywhere_in_sym
- ? di->symtab[mid].size
- : 1);
- a_mid_hi = ((Addr)di->symtab[mid].avmas.main) + size - 1;
+ a_mid_hi = ((Addr)di->symtab[mid].avmas.main) + di->symtab[mid].size - 1;
if (ptr < a_mid_lo) { hi = mid-1; continue; }
if (ptr > a_mid_hi) { lo = mid+1; continue; }
diff --git a/coregrind/m_debuginfo/tytypes.c b/coregrind/m_debuginfo/tytypes.c
index 839e546..9491dca 100644
--- a/coregrind/m_debuginfo/tytypes.c
+++ b/coregrind/m_debuginfo/tytypes.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2015 OpenWorks LLP
+ Copyright (C) 2008-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_debuglog.c b/coregrind/m_debuglog.c
index dc6e26d..bb9aa1b 100644
--- a/coregrind/m_debuglog.c
+++ b/coregrind/m_debuglog.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -215,7 +215,7 @@
:
: "b" (block)
: "cc","memory","cr0","ctr",
- "r0","r2","r3","r4","r5","r6","r7","r8","r9","r10","r11","r12"
+ "r0","r3","r4","r5","r6","r7","r8","r9","r10","r11","r12"
);
if (block[0] < 0)
block[0] = -1;
@@ -231,7 +231,7 @@
: "=&r" (__res)
: "i" (__NR_getpid)
: "cc","memory","cr0","ctr",
- "r0","r2","r4","r5","r6","r7","r8","r9","r10","r11","r12"
+ "r0","r4","r5","r6","r7","r8","r9","r10","r11","r12"
);
return (UInt)__res;
}
@@ -512,53 +512,6 @@
return (UInt)(__res);
}
-#elif defined(VGP_tilegx_linux)
-
-static UInt local_sys_write_stderr ( const HChar* buf, Int n )
-{
- volatile Long block[2];
- block[0] = (Long)buf;
- block[1] = n;
- Long __res = 0;
- __asm__ volatile (
- "movei r0, 2 \n\t" /* stderr */
- "move r1, %1 \n\t" /* buf */
- "move r2, %2 \n\t" /* n */
- "move r3, zero \n\t"
- "moveli r10, %3 \n\t" /* set r10 = __NR_write */
- "swint1 \n\t" /* write() */
- "nop \n\t"
- "move %0, r0 \n\t" /* save return into block[0] */
- : "=r"(__res)
- : "r" (block[0]), "r"(block[1]), "n" (__NR_write)
- : "r0", "r1", "r2", "r3", "r4", "r5");
- if (__res < 0)
- __res = -1;
- return (UInt)__res;
-}
-
-static UInt local_sys_getpid ( void )
-{
- UInt __res, __err;
- __res = 0;
- __err = 0;
- __asm__ volatile (
- "moveli r10, %2\n\t" /* set r10 = __NR_getpid */
- "swint1\n\t" /* getpid() */
- "nop\n\t"
- "move %0, r0\n"
- "move %1, r1\n"
- : "=r" (__res), "=r"(__err)
- : "n" (__NR_getpid)
- : "r0", "r1", "r2", "r3", "r4",
- "r5", "r6", "r7", "r8", "r9",
- "r10", "r11", "r12", "r13", "r14",
- "r15", "r16", "r17", "r18", "r19",
- "r20", "r21", "r22", "r23", "r24",
- "r25", "r26", "r27", "r28", "r29");
- return __res;
-}
-
#elif defined(VGP_x86_solaris)
static UInt local_sys_write_stderr ( const HChar* buf, Int n )
{
diff --git a/coregrind/m_deduppoolalloc.c b/coregrind/m_deduppoolalloc.c
index f7ebd27..597eaa7 100644
--- a/coregrind/m_deduppoolalloc.c
+++ b/coregrind/m_deduppoolalloc.c
@@ -6,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2014-2015 Philippe Waroquiers philippe.waroquiers@skynet.be
+ Copyright (C) 2014-2017 Philippe Waroquiers philippe.waroquiers@skynet.be
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -41,10 +41,11 @@
struct _DedupPoolAlloc {
SizeT poolSzB; /* Minimum size of a pool. */
SizeT fixedSzb; /* If using VG_(allocFixedEltDedupPA), size of elements */
+ Bool strPA; /* True if this is a string dedup pool */
SizeT eltAlign;
- void* (*alloc_fn)(const HChar*, SizeT); /* pool allocator */
+ Alloc_Fn_t alloc_fn; /* pool allocator */
const HChar* cc; /* pool allocator's cost centre */
- void (*free_fn)(void*); /* pool allocator's deallocation function */
+ Free_Fn_t free_fn; /* pool allocator's deallocation function */
/* XArray of void* (pointers to pools). The pools themselves.
Each element is a pointer to a block of size at least PoolSzB bytes.
The last block might be smaller due to a call to shrink_block. */
@@ -75,16 +76,17 @@
struct _ht_node {
struct _ht_node *next; // Read/Write by hashtable (pub_tool_hashtable.h)
UWord key; // Read by hashtable (pub_tool_hashtable.h)
- SizeT eltSzB;
+ SizeT eltSzBorStrNr; // for a normal pool, elt size
+ // for a string pool, the unique str number
const void *elt;
}
ht_node;
DedupPoolAlloc* VG_(newDedupPA) ( SizeT poolSzB,
SizeT eltAlign,
- void* (*alloc_fn)(const HChar*, SizeT),
+ Alloc_Fn_t alloc_fn,
const HChar* cc,
- void (*free_fn)(void*) )
+ Free_Fn_t free_fn )
{
DedupPoolAlloc* ddpa;
vg_assert(poolSzB >= eltAlign);
@@ -97,6 +99,7 @@
VG_(memset)(ddpa, 0, sizeof(*ddpa));
ddpa->poolSzB = poolSzB;
ddpa->fixedSzb = 0;
+ ddpa->strPA = False;
ddpa->eltAlign = eltAlign;
ddpa->alloc_fn = alloc_fn;
ddpa->cc = cc;
@@ -189,14 +192,24 @@
/* As this function is called by hashtable, that has already checked
for key equality, it is likely that it is the 'good' element.
So, we handle the equal case first. */
- if (hnode1->eltSzB == hnode2->eltSzB)
- return VG_(memcmp) (hnode1->elt, hnode2->elt, hnode1->eltSzB);
- else if (hnode1->eltSzB < hnode2->eltSzB)
+ if (hnode1->eltSzBorStrNr == hnode2->eltSzBorStrNr)
+ return VG_(memcmp) (hnode1->elt, hnode2->elt, hnode1->eltSzBorStrNr);
+ else if (hnode1->eltSzBorStrNr < hnode2->eltSzBorStrNr)
return -1;
else
return 1;
}
+/* String compare function for 'gen' hash table.
+ Similarly to cmp_pool_elt, no need to compare the key. */
+static Word cmp_pool_str (const void* node1, const void* node2 )
+{
+ const ht_node* hnode1 = node1;
+ const ht_node* hnode2 = node2;
+
+ return VG_(strcmp)(hnode1->elt, hnode2->elt);
+}
+
/* Print some stats. */
static void print_stats (DedupPoolAlloc *ddpa)
{
@@ -209,7 +222,10 @@
VG_(sizeXA)(ddpa->pools),
ddpa->curpool ?
(long int) (ddpa->curpool_limit - ddpa->curpool_free + 1) : 0);
- VG_(HT_print_stats) (ddpa->ht_elements, cmp_pool_elt);
+ if (ddpa->strPA)
+ VG_(HT_print_stats) (ddpa->ht_elements, cmp_pool_str);
+ else
+ VG_(HT_print_stats) (ddpa->ht_elements, cmp_pool_elt);
}
/* Dummy free, as the ht elements are allocated in a pool, and
@@ -247,8 +263,8 @@
return h;
}
-const void* VG_(allocEltDedupPA) (DedupPoolAlloc *ddpa, SizeT eltSzB,
- const void *elt)
+static ht_node* allocEltDedupPA (DedupPoolAlloc *ddpa, SizeT eltSzB,
+ const void *elt)
{
ht_node ht_elt;
void* elt_ins;
@@ -260,12 +276,16 @@
ht_elt.key = sdbm_hash (elt, eltSzB);
- ht_elt.eltSzB = eltSzB;
ht_elt.elt = elt;
- ht_ins = VG_(HT_gen_lookup) (ddpa->ht_elements, &ht_elt, cmp_pool_elt);
+ if (ddpa->strPA)
+ ht_ins = VG_(HT_gen_lookup) (ddpa->ht_elements, &ht_elt, cmp_pool_str);
+ else {
+ ht_elt.eltSzBorStrNr = eltSzB;
+ ht_ins = VG_(HT_gen_lookup) (ddpa->ht_elements, &ht_elt, cmp_pool_elt);
+ }
if (ht_ins)
- return ht_ins->elt;
+ return ht_ins;
/* Not found -> we need to allocate a new element from the pool
and insert it in the hash table of inserted elements. */
@@ -291,10 +311,37 @@
VG_(memcpy)(elt_ins, elt, eltSzB);
ht_ins = VG_(allocEltPA) (ddpa->ht_node_pa);
ht_ins->key = ht_elt.key;
- ht_ins->eltSzB = eltSzB;
+ if (ddpa->strPA)
+ ht_ins->eltSzBorStrNr = VG_(HT_count_nodes)(ddpa->ht_elements) + 1;
+ else
+ ht_ins->eltSzBorStrNr = eltSzB;
ht_ins->elt = elt_ins;
VG_(HT_add_node)(ddpa->ht_elements, ht_ins);
- return elt_ins;
+ return ht_ins;
+}
+
+const void* VG_(allocEltDedupPA) (DedupPoolAlloc *ddpa, SizeT eltSzB,
+ const void *elt)
+{
+ return allocEltDedupPA(ddpa, eltSzB, elt)->elt;
+}
+
+UInt VG_(allocStrDedupPA) (DedupPoolAlloc *ddpa,
+ const HChar* str,
+ Bool* newStr)
+{
+ if (!ddpa->strPA) {
+ // First insertion in this ddpa
+ vg_assert (ddpa->nr_alloc_calls == 0);
+ vg_assert (ddpa->fixedSzb == 0);
+ ddpa->strPA = True;
+ }
+
+ const UInt nr_str = VG_(HT_count_nodes)(ddpa->ht_elements);
+ const ht_node* ht_ins = allocEltDedupPA(ddpa, VG_(strlen)(str)+1, str);
+
+ *newStr = nr_str < VG_(HT_count_nodes)(ddpa->ht_elements);
+ return ht_ins->eltSzBorStrNr;
}
static __inline__
@@ -311,6 +358,7 @@
{
if (ddpa->fixedSzb == 0) {
// First insertion in this ddpa
+ vg_assert (!ddpa->strPA);
vg_assert (ddpa->nr_alloc_calls == 0);
vg_assert (eltSzB > 0);
ddpa->fixedSzb = eltSzB;
diff --git a/coregrind/m_demangle/ansidecl.h b/coregrind/m_demangle/ansidecl.h
index 6e4bfc2..3822be0 100644
--- a/coregrind/m_demangle/ansidecl.h
+++ b/coregrind/m_demangle/ansidecl.h
@@ -1,5 +1,5 @@
-/* ANSI and traditional C compatability macros
- Copyright (C) 1991-2015 Free Software Foundation, Inc.
+/* ANSI and traditional C compatibility macros
+ Copyright (C) 1991-2017 Free Software Foundation, Inc.
This file is part of the GNU C Library.
This program is free software; you can redistribute it and/or modify
@@ -313,13 +313,39 @@
#define ENUM_BITFIELD(TYPE) unsigned int
#endif
- /* This is used to mark a class or virtual function as final. */
-#if __cplusplus >= 201103L
-#define GCC_FINAL final
+/* C++11 adds the ability to add "override" after an implementation of a
+ virtual function in a subclass, to:
+ (A) document that this is an override of a virtual function
+ (B) allow the compiler to issue a warning if it isn't (e.g. a mismatch
+ of the type signature).
+
+ Similarly, it allows us to add a "final" to indicate that no subclass
+ may subsequently override the vfunc.
+
+ Provide OVERRIDE and FINAL as macros, allowing us to get these benefits
+ when compiling with C++11 support, but without requiring C++11.
+
+ For gcc, use "-std=c++11" to enable C++11 support; gcc 6 onwards enables
+ this by default (actually GNU++14). */
+
+#if __cplusplus >= 201103
+/* C++11 claims to be available: use it. final/override were only
+ implemented in 4.7, though. */
+# if GCC_VERSION < 4007
+# define OVERRIDE
+# define FINAL
+# else
+# define OVERRIDE override
+# define FINAL final
+# endif
#elif GCC_VERSION >= 4007
-#define GCC_FINAL __final
+/* G++ 4.7 supports __final in C++98. */
+# define OVERRIDE
+# define FINAL __final
#else
-#define GCC_FINAL
+/* No C++11 support; leave the macros empty: */
+# define OVERRIDE
+# define FINAL
#endif
#ifdef __cplusplus
diff --git a/coregrind/m_demangle/cp-demangle.c b/coregrind/m_demangle/cp-demangle.c
index a3f78ab..4a3fa5d 100644
--- a/coregrind/m_demangle/cp-demangle.c
+++ b/coregrind/m_demangle/cp-demangle.c
@@ -1,6 +1,5 @@
/* Demangler for g++ V3 ABI.
- Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2014
- Free Software Foundation, Inc.
+ Copyright (C) 2003-2017 Free Software Foundation, Inc.
Written by Ian Lance Taylor <ian@wasabisystems.com>.
This file is part of the libiberty library, which is part of GCC.
@@ -190,10 +189,10 @@
static struct demangle_component *d_type (struct d_info *);
#define cplus_demangle_print d_print
-static char *d_print (int, const struct demangle_component *, int, size_t *);
+static char *d_print (int, struct demangle_component *, int, size_t *);
#define cplus_demangle_print_callback d_print_callback
-static int d_print_callback (int, const struct demangle_component *,
+static int d_print_callback (int, struct demangle_component *,
demangle_callbackref, void *);
#define cplus_demangle_init_info d_init_info
@@ -282,7 +281,7 @@
in which they appeared in the mangled string. */
struct d_print_mod *next;
/* The modifier. */
- const struct demangle_component *mod;
+ struct demangle_component *mod;
/* Whether this modifier was printed. */
int printed;
/* The list of templates which applies to this modifier. */
@@ -360,6 +359,9 @@
struct d_print_mod *modifiers;
/* Set to 1 if we saw a demangling error. */
int demangle_failure;
+ /* Non-zero if we're printing a lambda argument. A template
+ parameter reference actually means 'auto'. */
+ int is_lambda_arg;
/* The current index into any template argument packs we are using
for printing, or -1 to print the whole pack. */
int pack_index;
@@ -453,6 +455,8 @@
static struct demangle_component *d_special_name (struct d_info *);
+static struct demangle_component *d_parmlist (struct d_info *);
+
static int d_call_offset (struct d_info *, int);
static struct demangle_component *d_ctor_dtor_name (struct d_info *);
@@ -543,7 +547,7 @@
static inline char d_last_char (struct d_print_info *);
static void
-d_print_comp (struct d_print_info *, int, const struct demangle_component *);
+d_print_comp (struct d_print_info *, int, struct demangle_component *);
static void
d_print_java_identifier (struct d_print_info *, const char *, int);
@@ -552,30 +556,56 @@
d_print_mod_list (struct d_print_info *, int, struct d_print_mod *, int);
static void
-d_print_mod (struct d_print_info *, int, const struct demangle_component *);
+d_print_mod (struct d_print_info *, int, struct demangle_component *);
static void
d_print_function_type (struct d_print_info *, int,
- const struct demangle_component *,
+ struct demangle_component *,
struct d_print_mod *);
static void
d_print_array_type (struct d_print_info *, int,
- const struct demangle_component *,
+ struct demangle_component *,
struct d_print_mod *);
static void
-d_print_expr_op (struct d_print_info *, int, const struct demangle_component *);
+d_print_expr_op (struct d_print_info *, int, struct demangle_component *);
static void d_print_cast (struct d_print_info *, int,
- const struct demangle_component *);
+ struct demangle_component *);
static void d_print_conversion (struct d_print_info *, int,
- const struct demangle_component *);
+ struct demangle_component *);
static int d_demangle_callback (const char *, int,
demangle_callbackref, void *);
static char *d_demangle (const char *, int, size_t *);
+/* True iff TYPE is a demangling component representing a
+ function-type-qualifier. */
+
+static int
+is_fnqual_component_type (enum demangle_component_type type)
+{
+ return (type == DEMANGLE_COMPONENT_RESTRICT_THIS
+ || type == DEMANGLE_COMPONENT_VOLATILE_THIS
+ || type == DEMANGLE_COMPONENT_CONST_THIS
+ || type == DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS
+ || type == DEMANGLE_COMPONENT_TRANSACTION_SAFE
+ || type == DEMANGLE_COMPONENT_NOEXCEPT
+ || type == DEMANGLE_COMPONENT_THROW_SPEC
+ || type == DEMANGLE_COMPONENT_REFERENCE_THIS);
+}
+
+#define FNQUAL_COMPONENT_CASE \
+ case DEMANGLE_COMPONENT_RESTRICT_THIS: \
+ case DEMANGLE_COMPONENT_VOLATILE_THIS: \
+ case DEMANGLE_COMPONENT_CONST_THIS: \
+ case DEMANGLE_COMPONENT_REFERENCE_THIS: \
+ case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS: \
+ case DEMANGLE_COMPONENT_TRANSACTION_SAFE: \
+ case DEMANGLE_COMPONENT_NOEXCEPT: \
+ case DEMANGLE_COMPONENT_THROW_SPEC
+
#ifdef CP_DEMANGLE_DEBUG
static void
@@ -841,6 +871,7 @@
{
if (p == NULL || s == NULL || len == 0)
return 0;
+ p->d_printing = 0;
p->type = DEMANGLE_COMPONENT_NAME;
p->u.s_name.s = s;
p->u.s_name.len = len;
@@ -856,6 +887,7 @@
{
if (p == NULL || args < 0 || name == NULL)
return 0;
+ p->d_printing = 0;
p->type = DEMANGLE_COMPONENT_EXTENDED_OPERATOR;
p->u.s_extended_operator.args = args;
p->u.s_extended_operator.name = name;
@@ -875,6 +907,7 @@
|| (int) kind < gnu_v3_complete_object_ctor
|| (int) kind > gnu_v3_object_ctor_group)
return 0;
+ p->d_printing = 0;
p->type = DEMANGLE_COMPONENT_CTOR;
p->u.s_ctor.kind = kind;
p->u.s_ctor.name = name;
@@ -894,6 +927,7 @@
|| (int) kind < gnu_v3_deleting_dtor
|| (int) kind > gnu_v3_object_dtor_group)
return 0;
+ p->d_printing = 0;
p->type = DEMANGLE_COMPONENT_DTOR;
p->u.s_dtor.kind = kind;
p->u.s_dtor.name = name;
@@ -910,6 +944,7 @@
if (di->next_comp >= di->num_comps)
return NULL;
p = &di->comps[di->next_comp];
+ p->d_printing = 0;
++di->next_comp;
return p;
}
@@ -1001,14 +1036,9 @@
case DEMANGLE_COMPONENT_RESTRICT:
case DEMANGLE_COMPONENT_VOLATILE:
case DEMANGLE_COMPONENT_CONST:
- case DEMANGLE_COMPONENT_RESTRICT_THIS:
- case DEMANGLE_COMPONENT_VOLATILE_THIS:
- case DEMANGLE_COMPONENT_CONST_THIS:
- case DEMANGLE_COMPONENT_TRANSACTION_SAFE:
- case DEMANGLE_COMPONENT_REFERENCE_THIS:
- case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:
case DEMANGLE_COMPONENT_ARGLIST:
case DEMANGLE_COMPONENT_TEMPLATE_ARGLIST:
+ FNQUAL_COMPONENT_CASE:
break;
/* Other types should not be seen here. */
@@ -1242,12 +1272,7 @@
return 0;
case DEMANGLE_COMPONENT_TEMPLATE:
return ! is_ctor_dtor_or_conversion (d_left (dc));
- case DEMANGLE_COMPONENT_RESTRICT_THIS:
- case DEMANGLE_COMPONENT_VOLATILE_THIS:
- case DEMANGLE_COMPONENT_CONST_THIS:
- case DEMANGLE_COMPONENT_REFERENCE_THIS:
- case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:
- case DEMANGLE_COMPONENT_TRANSACTION_SAFE:
+ FNQUAL_COMPONENT_CASE:
return has_return_type (d_left (dc));
}
}
@@ -1304,13 +1329,12 @@
while (dc->type == DEMANGLE_COMPONENT_RESTRICT_THIS
|| dc->type == DEMANGLE_COMPONENT_VOLATILE_THIS
|| dc->type == DEMANGLE_COMPONENT_CONST_THIS
- || dc->type == DEMANGLE_COMPONENT_TRANSACTION_SAFE
|| dc->type == DEMANGLE_COMPONENT_REFERENCE_THIS
|| dc->type == DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS)
dc = d_left (dc);
/* If the top level is a DEMANGLE_COMPONENT_LOCAL_NAME, then
- there may be CV-qualifiers on its right argument which
+ there may be function-qualifiers on its right argument which
really apply here; this happens when parsing a class
which is local to a function. */
if (dc->type == DEMANGLE_COMPONENT_LOCAL_NAME)
@@ -1318,12 +1342,7 @@
struct demangle_component *dcr;
dcr = d_right (dc);
- while (dcr->type == DEMANGLE_COMPONENT_RESTRICT_THIS
- || dcr->type == DEMANGLE_COMPONENT_VOLATILE_THIS
- || dcr->type == DEMANGLE_COMPONENT_CONST_THIS
- || dcr->type == DEMANGLE_COMPONENT_TRANSACTION_SAFE
- || dcr->type == DEMANGLE_COMPONENT_REFERENCE_THIS
- || dcr->type == DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS)
+ while (is_fnqual_component_type (dcr->type))
dcr = d_left (dcr);
dc->u.s_binary.right = dcr;
}
@@ -1597,6 +1616,8 @@
ret = d_source_name (di);
else if (IS_LOWER (peek))
{
+ if (peek == 'o' && d_peek_next_char (di) == 'n')
+ d_advance (di, 2);
ret = d_operator_name (di);
if (ret != NULL && ret->type == DEMANGLE_COMPONENT_OPERATOR)
{
@@ -2185,6 +2206,13 @@
case 'C':
{
enum gnu_v3_ctor_kinds kind;
+ int inheriting = 0;
+
+ if (d_peek_next_char (di) == 'I')
+ {
+ inheriting = 1;
+ d_advance (di, 1);
+ }
switch (d_peek_next_char (di))
{
@@ -2206,7 +2234,12 @@
default:
return NULL;
}
+
d_advance (di, 2);
+
+ if (inheriting)
+ cplus_demangle_type (di);
+
return d_make_ctor (di, kind, di->last_name);
}
@@ -2244,6 +2277,24 @@
}
}
+/* True iff we're looking at an order-insensitive type-qualifier, including
+ function-type-qualifiers. */
+
+static int
+next_is_type_qual (struct d_info *di)
+{
+ char peek = d_peek_char (di);
+ if (peek == 'r' || peek == 'V' || peek == 'K')
+ return 1;
+ if (peek == 'D')
+ {
+ peek = d_peek_next_char (di);
+ if (peek == 'x' || peek == 'o' || peek == 'O' || peek == 'w')
+ return 1;
+ }
+ return 0;
+}
+
/* <type> ::= <builtin-type>
::= <function-type>
::= <class-enum-type>
@@ -2329,9 +2380,7 @@
__vector, and it treats it as order-sensitive when mangling
names. */
- peek = d_peek_char (di);
- if (peek == 'r' || peek == 'V' || peek == 'K'
- || (peek == 'D' && d_peek_next_char (di) == 'x'))
+ if (next_is_type_qual (di))
{
struct demangle_component **pret;
@@ -2366,6 +2415,7 @@
can_subst = 1;
+ peek = d_peek_char (di);
switch (peek)
{
case 'a': case 'b': case 'c': case 'd': case 'e': case 'f': case 'g':
@@ -2566,7 +2616,11 @@
/* auto */
ret = d_make_name (di, "auto", 4);
break;
-
+ case 'c':
+ /* decltype(auto) */
+ ret = d_make_name (di, "decltype(auto)", 14);
+ break;
+
case 'f':
/* 32-bit decimal floating point */
ret = d_make_builtin_type (di, &cplus_demangle_builtin_types[26]);
@@ -2653,10 +2707,10 @@
pstart = pret;
peek = d_peek_char (di);
- while (peek == 'r' || peek == 'V' || peek == 'K'
- || (peek == 'D' && d_peek_next_char (di) == 'x'))
+ while (next_is_type_qual (di))
{
enum demangle_component_type t;
+ struct demangle_component *right = NULL;
d_advance (di, 1);
if (peek == 'r')
@@ -2682,12 +2736,41 @@
}
else
{
- t = DEMANGLE_COMPONENT_TRANSACTION_SAFE;
- di->expansion += sizeof "transaction_safe";
- d_advance (di, 1);
+ peek = d_next_char (di);
+ if (peek == 'x')
+ {
+ t = DEMANGLE_COMPONENT_TRANSACTION_SAFE;
+ di->expansion += sizeof "transaction_safe";
+ }
+ else if (peek == 'o'
+ || peek == 'O')
+ {
+ t = DEMANGLE_COMPONENT_NOEXCEPT;
+ di->expansion += sizeof "noexcept";
+ if (peek == 'O')
+ {
+ right = d_expression (di);
+ if (right == NULL)
+ return NULL;
+ if (! d_check_char (di, 'E'))
+ return NULL;
+ }
+ }
+ else if (peek == 'w')
+ {
+ t = DEMANGLE_COMPONENT_THROW_SPEC;
+ di->expansion += sizeof "throw";
+ right = d_parmlist (di);
+ if (right == NULL)
+ return NULL;
+ if (! d_check_char (di, 'E'))
+ return NULL;
+ }
+ else
+ return NULL;
}
- *pret = d_make_comp (di, t, NULL, NULL);
+ *pret = d_make_comp (di, t, NULL, right);
if (*pret == NULL)
return NULL;
pret = &d_left (*pret);
@@ -3362,6 +3445,8 @@
first = d_expression_1 (di);
second = d_expression_1 (di);
third = d_expression_1 (di);
+ if (third == NULL)
+ return NULL;
}
else if (code[0] == 'f')
{
@@ -3369,6 +3454,8 @@
first = d_operator_name (di);
second = d_expression_1 (di);
third = d_expression_1 (di);
+ if (third == NULL)
+ return NULL;
}
else if (code[0] == 'n')
{
@@ -3546,7 +3633,11 @@
}
}
-/* <discriminator> ::= _ <(non-negative) number>
+/* <discriminator> ::= _ <number> # when number < 10
+ ::= __ <number> _ # when number >= 10
+
+ <discriminator> ::= _ <number> # when number >=10
+ is also accepted to support gcc versions that wrongly mangled that way.
We demangle the discriminator, but we don't print it out. FIXME:
We should print it out in verbose mode. */
@@ -3554,14 +3645,28 @@
static int
d_discriminator (struct d_info *di)
{
- int discrim;
+ int discrim, num_underscores = 1;
if (d_peek_char (di) != '_')
return 1;
d_advance (di, 1);
+ if (d_peek_char (di) == '_')
+ {
+ ++num_underscores;
+ d_advance (di, 1);
+ }
+
discrim = d_number (di);
if (discrim < 0)
return 0;
+ if (num_underscores > 1 && discrim >= 10)
+ {
+ if (d_peek_char (di) == '_')
+ d_advance (di, 1);
+ else
+ return 0;
+ }
+
return 1;
}
@@ -3978,6 +4083,8 @@
case DEMANGLE_COMPONENT_REFERENCE_THIS:
case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:
case DEMANGLE_COMPONENT_TRANSACTION_SAFE:
+ case DEMANGLE_COMPONENT_NOEXCEPT:
+ case DEMANGLE_COMPONENT_THROW_SPEC:
case DEMANGLE_COMPONENT_VENDOR_TYPE_QUAL:
case DEMANGLE_COMPONENT_POINTER:
case DEMANGLE_COMPONENT_COMPLEX:
@@ -4067,6 +4174,7 @@
dpi->opaque = opaque;
dpi->demangle_failure = 0;
+ dpi->is_lambda_arg = 0;
dpi->component_stack = NULL;
@@ -4163,7 +4271,7 @@
CP_STATIC_IF_GLIBCPP_V3
int
cplus_demangle_print_callback (int options,
- const struct demangle_component *dc,
+ struct demangle_component *dc,
demangle_callbackref callback, void *opaque)
{
struct d_print_info dpi;
@@ -4222,7 +4330,7 @@
CP_STATIC_IF_GLIBCPP_V3
char *
-cplus_demangle_print (int options, const struct demangle_component *dc,
+cplus_demangle_print (int options, struct demangle_component *dc,
int estimate, size_t *palc)
{
struct d_growable_string dgs;
@@ -4382,7 +4490,7 @@
static void
d_print_subexpr (struct d_print_info *dpi, int options,
- const struct demangle_component *dc)
+ struct demangle_component *dc)
{
int simple = 0;
if (dc->type == DEMANGLE_COMPONENT_NAME
@@ -4458,9 +4566,9 @@
static int
d_maybe_print_fold_expression (struct d_print_info *dpi, int options,
- const struct demangle_component *dc)
+ struct demangle_component *dc)
{
- const struct demangle_component *ops, *operator_, *op1, *op2;
+ struct demangle_component *ops, *operator_, *op1, *op2;
int save_idx;
const char *fold_code = d_left (dc)->u.s_operator.op->code;
@@ -4521,11 +4629,11 @@
static void
d_print_comp_inner (struct d_print_info *dpi, int options,
- const struct demangle_component *dc)
+ struct demangle_component *dc)
{
/* Magic variable to let reference smashing skip over the next modifier
without needing to modify *dc. */
- const struct demangle_component *mod_inner = NULL;
+ struct demangle_component *mod_inner = NULL;
/* Variable used to store the current templates while a previously
captured scope is used. */
@@ -4608,12 +4716,7 @@
adpm[i].templates = dpi->templates;
++i;
- if (typed_name->type != DEMANGLE_COMPONENT_RESTRICT_THIS
- && typed_name->type != DEMANGLE_COMPONENT_VOLATILE_THIS
- && typed_name->type != DEMANGLE_COMPONENT_CONST_THIS
- && typed_name->type != DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS
- && typed_name->type != DEMANGLE_COMPONENT_TRANSACTION_SAFE
- && typed_name->type != DEMANGLE_COMPONENT_REFERENCE_THIS)
+ if (!is_fnqual_component_type (typed_name->type))
break;
typed_name = d_left (typed_name);
@@ -4650,13 +4753,7 @@
d_print_error (dpi);
return;
}
- while (local_name->type == DEMANGLE_COMPONENT_RESTRICT_THIS
- || local_name->type == DEMANGLE_COMPONENT_VOLATILE_THIS
- || local_name->type == DEMANGLE_COMPONENT_CONST_THIS
- || local_name->type == DEMANGLE_COMPONENT_REFERENCE_THIS
- || local_name->type == DEMANGLE_COMPONENT_TRANSACTION_SAFE
- || (local_name->type
- == DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS))
+ while (is_fnqual_component_type (local_name->type))
{
if (i >= sizeof adpm / sizeof adpm[0])
{
@@ -4751,33 +4848,41 @@
}
case DEMANGLE_COMPONENT_TEMPLATE_PARAM:
- {
- struct d_print_template *hold_dpt;
- struct demangle_component *a = d_lookup_template_argument (dpi, dc);
+ if (dpi->is_lambda_arg)
+ {
+ /* Show the template parm index, as that's how g++ displays
+ these, and future proofs us against potential
+ '[]<typename T> (T *a, T *b) {...}'. */
+ d_append_buffer (dpi, "auto:", 5);
+ d_append_num (dpi, dc->u.s_number.number + 1);
+ }
+ else
+ {
+ struct d_print_template *hold_dpt;
+ struct demangle_component *a = d_lookup_template_argument (dpi, dc);
- if (a && a->type == DEMANGLE_COMPONENT_TEMPLATE_ARGLIST)
- a = d_index_template_argument (a, dpi->pack_index);
+ if (a && a->type == DEMANGLE_COMPONENT_TEMPLATE_ARGLIST)
+ a = d_index_template_argument (a, dpi->pack_index);
- if (a == NULL)
- {
- d_print_error (dpi);
- return;
- }
+ if (a == NULL)
+ {
+ d_print_error (dpi);
+ return;
+ }
- /* While processing this parameter, we need to pop the list of
- templates. This is because the template parameter may
- itself be a reference to a parameter of an outer
- template. */
+ /* While processing this parameter, we need to pop the list
+ of templates. This is because the template parameter may
+ itself be a reference to a parameter of an outer
+ template. */
- hold_dpt = dpi->templates;
- dpi->templates = hold_dpt->next;
+ hold_dpt = dpi->templates;
+ dpi->templates = hold_dpt->next;
- d_print_comp (dpi, options, a);
+ d_print_comp (dpi, options, a);
- dpi->templates = hold_dpt;
-
- return;
- }
+ dpi->templates = hold_dpt;
+ }
+ return;
case DEMANGLE_COMPONENT_CTOR:
d_print_comp (dpi, options, dc->u.s_ctor.name);
@@ -4913,8 +5018,9 @@
case DEMANGLE_COMPONENT_RVALUE_REFERENCE:
{
/* Handle reference smashing: & + && = &. */
- const struct demangle_component *sub = d_left (dc);
- if (sub->type == DEMANGLE_COMPONENT_TEMPLATE_PARAM)
+ struct demangle_component *sub = d_left (dc);
+ if (!dpi->is_lambda_arg
+ && sub->type == DEMANGLE_COMPONENT_TEMPLATE_PARAM)
{
struct d_saved_scope *scope = d_get_saved_scope (dpi, sub);
struct demangle_component *a;
@@ -4981,16 +5087,11 @@
}
/* Fall through. */
- case DEMANGLE_COMPONENT_RESTRICT_THIS:
- case DEMANGLE_COMPONENT_VOLATILE_THIS:
- case DEMANGLE_COMPONENT_CONST_THIS:
- case DEMANGLE_COMPONENT_REFERENCE_THIS:
- case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:
case DEMANGLE_COMPONENT_VENDOR_TYPE_QUAL:
case DEMANGLE_COMPONENT_POINTER:
case DEMANGLE_COMPONENT_COMPLEX:
case DEMANGLE_COMPONENT_IMAGINARY:
- case DEMANGLE_COMPONENT_TRANSACTION_SAFE:
+ FNQUAL_COMPONENT_CASE:
modifier:
{
/* We keep a list of modifiers on the stack. */
@@ -5589,7 +5690,11 @@
case DEMANGLE_COMPONENT_LAMBDA:
d_append_string (dpi, "{lambda(");
+ /* Generic lambda auto parms are mangled as the template type
+ parm they are. */
+ dpi->is_lambda_arg++;
d_print_comp (dpi, options, dc->u.s_unary_num.sub);
+ dpi->is_lambda_arg--;
d_append_string (dpi, ")#");
d_append_num (dpi, dc->u.s_unary_num.num + 1);
d_append_char (dpi, '}');
@@ -5616,9 +5721,16 @@
static void
d_print_comp (struct d_print_info *dpi, int options,
- const struct demangle_component *dc)
+ struct demangle_component *dc)
{
struct d_component_stack self;
+ if (dc == NULL || dc->d_printing > 1)
+ {
+ d_print_error (dpi);
+ return;
+ }
+ else
+ dc->d_printing++;
self.dc = dc;
self.parent = dpi->component_stack;
@@ -5627,6 +5739,7 @@
d_print_comp_inner (dpi, options, dc);
dpi->component_stack = self.parent;
+ dc->d_printing--;
}
/* Print a Java dentifier. For Java we try to handle encoded extended
@@ -5695,13 +5808,7 @@
if (mods->printed
|| (! suffix
- && (mods->mod->type == DEMANGLE_COMPONENT_RESTRICT_THIS
- || mods->mod->type == DEMANGLE_COMPONENT_VOLATILE_THIS
- || mods->mod->type == DEMANGLE_COMPONENT_CONST_THIS
- || mods->mod->type == DEMANGLE_COMPONENT_REFERENCE_THIS
- || mods->mod->type == DEMANGLE_COMPONENT_TRANSACTION_SAFE
- || (mods->mod->type
- == DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS))))
+ && (is_fnqual_component_type (mods->mod->type))))
{
d_print_mod_list (dpi, options, mods->next, suffix);
return;
@@ -5754,12 +5861,7 @@
dc = dc->u.s_unary_num.sub;
}
- while (dc->type == DEMANGLE_COMPONENT_RESTRICT_THIS
- || dc->type == DEMANGLE_COMPONENT_VOLATILE_THIS
- || dc->type == DEMANGLE_COMPONENT_CONST_THIS
- || dc->type == DEMANGLE_COMPONENT_REFERENCE_THIS
- || dc->type == DEMANGLE_COMPONENT_TRANSACTION_SAFE
- || dc->type == DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS)
+ while (is_fnqual_component_type (dc->type))
dc = d_left (dc);
d_print_comp (dpi, options, dc);
@@ -5779,7 +5881,7 @@
static void
d_print_mod (struct d_print_info *dpi, int options,
- const struct demangle_component *mod)
+ struct demangle_component *mod)
{
switch (mod->type)
{
@@ -5798,6 +5900,24 @@
case DEMANGLE_COMPONENT_TRANSACTION_SAFE:
d_append_string (dpi, " transaction_safe");
return;
+ case DEMANGLE_COMPONENT_NOEXCEPT:
+ d_append_string (dpi, " noexcept");
+ if (d_right (mod))
+ {
+ d_append_char (dpi, '(');
+ d_print_comp (dpi, options, d_right (mod));
+ d_append_char (dpi, ')');
+ }
+ return;
+ case DEMANGLE_COMPONENT_THROW_SPEC:
+ d_append_string (dpi, " throw");
+ if (d_right (mod))
+ {
+ d_append_char (dpi, '(');
+ d_print_comp (dpi, options, d_right (mod));
+ d_append_char (dpi, ')');
+ }
+ return;
case DEMANGLE_COMPONENT_VENDOR_TYPE_QUAL:
d_append_char (dpi, ' ');
d_print_comp (dpi, options, d_right (mod));
@@ -5853,7 +5973,7 @@
static void
d_print_function_type (struct d_print_info *dpi, int options,
- const struct demangle_component *dc,
+ struct demangle_component *dc,
struct d_print_mod *mods)
{
int need_paren;
@@ -5885,12 +6005,7 @@
need_space = 1;
need_paren = 1;
break;
- case DEMANGLE_COMPONENT_RESTRICT_THIS:
- case DEMANGLE_COMPONENT_VOLATILE_THIS:
- case DEMANGLE_COMPONENT_CONST_THIS:
- case DEMANGLE_COMPONENT_REFERENCE_THIS:
- case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:
- case DEMANGLE_COMPONENT_TRANSACTION_SAFE:
+ FNQUAL_COMPONENT_CASE:
break;
default:
break;
@@ -5936,7 +6051,7 @@
static void
d_print_array_type (struct d_print_info *dpi, int options,
- const struct demangle_component *dc,
+ struct demangle_component *dc,
struct d_print_mod *mods)
{
int need_space;
@@ -5990,7 +6105,7 @@
static void
d_print_expr_op (struct d_print_info *dpi, int options,
- const struct demangle_component *dc)
+ struct demangle_component *dc)
{
if (dc->type == DEMANGLE_COMPONENT_OPERATOR)
d_append_buffer (dpi, dc->u.s_operator.op->name,
@@ -6003,7 +6118,7 @@
static void
d_print_cast (struct d_print_info *dpi, int options,
- const struct demangle_component *dc)
+ struct demangle_component *dc)
{
d_print_comp (dpi, options, d_left (dc));
}
@@ -6012,7 +6127,7 @@
static void
d_print_conversion (struct d_print_info *dpi, int options,
- const struct demangle_component *dc)
+ struct demangle_component *dc)
{
struct d_print_template dpt;
@@ -6451,7 +6566,6 @@
case DEMANGLE_COMPONENT_CONST_THIS:
case DEMANGLE_COMPONENT_REFERENCE_THIS:
case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:
- case DEMANGLE_COMPONENT_TRANSACTION_SAFE:
default:
dc = NULL;
break;
diff --git a/coregrind/m_demangle/cp-demangle.h b/coregrind/m_demangle/cp-demangle.h
index 197883e..a265775 100644
--- a/coregrind/m_demangle/cp-demangle.h
+++ b/coregrind/m_demangle/cp-demangle.h
@@ -1,6 +1,5 @@
/* Internal demangler interface for g++ V3 ABI.
- Copyright (C) 2003, 2004, 2005, 2006, 2007, 2010
- Free Software Foundation, Inc.
+ Copyright (C) 2003-2017 Free Software Foundation, Inc.
Written by Ian Lance Taylor <ian@wasabisystems.com>.
This file is part of the libiberty library, which is part of GCC.
diff --git a/coregrind/m_demangle/cplus-dem.c b/coregrind/m_demangle/cplus-dem.c
index d00f79f..cf16f38 100644
--- a/coregrind/m_demangle/cplus-dem.c
+++ b/coregrind/m_demangle/cplus-dem.c
@@ -1,6 +1,5 @@
/* Demangler for GNU C++
- Copyright 1989, 1991, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001, 2002, 2003, 2004, 2010 Free Software Foundation, Inc.
+ Copyright (C) 1989-2017 Free Software Foundation, Inc.
Written by James Clark (jjc@jclark.uucp)
Rewritten by Fred Fish (fnf@cygnus.com) for ARM and Lucid demangling
Modified by Satish Pai (pai@apollo.hp.com) for HP demangling
@@ -343,6 +342,12 @@
}
,
{
+ RUST_DEMANGLING_STYLE_STRING,
+ rust_demangling,
+ "Rust style demangling"
+ }
+ ,
+ {
NULL, unknown_demangling, NULL
}
};
@@ -893,10 +898,26 @@
work->options |= (int) current_demangling_style & DMGL_STYLE_MASK;
/* The V3 ABI demangling is implemented elsewhere. */
- if (GNU_V3_DEMANGLING || AUTO_DEMANGLING)
+ if (GNU_V3_DEMANGLING || RUST_DEMANGLING || AUTO_DEMANGLING)
{
ret = cplus_demangle_v3 (mangled, work->options);
- if (ret || GNU_V3_DEMANGLING)
+ if (GNU_V3_DEMANGLING)
+ return ret;
+
+ if (ret)
+ {
+ /* Rust symbols are GNU_V3 mangled plus some extra subtitutions.
+ The subtitutions are always smaller, so do in place changes. */
+ if (rust_is_mangled (ret))
+ rust_demangle_sym (ret);
+ else if (RUST_DEMANGLING)
+ {
+ free (ret);
+ ret = NULL;
+ }
+ }
+
+ if (ret || RUST_DEMANGLING)
return ret;
}
@@ -922,6 +943,27 @@
return (ret);
}
+char *
+rust_demangle (const char *mangled, int options)
+{
+ /* Rust symbols are GNU_V3 mangled plus some extra subtitutions. */
+ char *ret = cplus_demangle_v3 (mangled, options);
+
+ /* The Rust subtitutions are always smaller, so do in place changes. */
+ if (ret != NULL)
+ {
+ if (rust_is_mangled (ret))
+ rust_demangle_sym (ret);
+ else
+ {
+ free (ret);
+ ret = NULL;
+ }
+ }
+
+ return ret;
+}
+
/* Demangle ada names. The encoding is documented in gcc/ada/exp_dbug.ads. */
char *
@@ -930,7 +972,7 @@
int len0;
const char* p;
char *d;
- char *demangled;
+ char *demangled = NULL;
/* Discard leading _ada_, which is used for library level subprograms. */
if (strncmp (mangled, "_ada_", 5) == 0)
@@ -941,7 +983,7 @@
goto unknown;
/* Most of the demangling will trivially remove chars. Operator names
- may add one char but because they are always preceeded by '__' which is
+ may add one char but because they are always preceded by '__' which is
replaced by '.', they eventually never expand the size.
A few special names such as '___elabs' add a few chars (at most 7), but
they occur only once. */
@@ -1175,6 +1217,7 @@
return demangled;
unknown:
+ XDELETEVEC (demangled);
len0 = strlen (mangled);
demangled = XNEWVEC (char, len0 + 3);
@@ -1672,12 +1715,13 @@
0);
if (!(work->constructor & 1))
expect_return_type = 1;
- (*mangled)++;
+ if (!**mangled)
+ success = 0;
+ else
+ (*mangled)++;
break;
}
- else
- /* fall through */
- {;}
+ /* fall through */
default:
if (AUTO_DEMANGLING || GNU_DEMANGLING)
@@ -1960,7 +2004,7 @@
string_append (s, buf);
/* Numbers not otherwise delimited, might have an underscore
- appended as a delimeter, which we should skip.
+ appended as a delimiter, which we should skip.
??? This used to always remove a following underscore, which
is wrong. If other (arbitrary) cases are followed by an
@@ -2153,6 +2197,8 @@
{
int idx;
(*mangled)++;
+ if (**mangled == '\0')
+ return (0);
(*mangled)++;
idx = consume_count_with_underscores (mangled);
@@ -2997,7 +3043,7 @@
int success = 1;
const char *p;
- if ((*mangled)[0] == '_'
+ if ((*mangled)[0] == '_' && (*mangled)[1] != '\0'
&& strchr (cplus_markers, (*mangled)[1]) != NULL
&& (*mangled)[2] == '_')
{
@@ -3011,7 +3057,7 @@
&& (*mangled)[3] == 't'
&& (*mangled)[4] == '_')
|| ((*mangled)[1] == 'v'
- && (*mangled)[2] == 't'
+ && (*mangled)[2] == 't' && (*mangled)[3] != '\0'
&& strchr (cplus_markers, (*mangled)[3]) != NULL)))
{
/* Found a GNU style virtual table, get past "_vt<CPLUS_MARKER>"
@@ -3781,11 +3827,12 @@
break;
}
- if (*(*mangled)++ != 'F')
+ if (*(*mangled) != 'F')
{
success = 0;
break;
}
+ (*mangled)++;
}
if ((member && !demangle_nested_args (work, mangled, &decl))
|| **mangled != '_')
@@ -4042,6 +4089,7 @@
success = 0;
break;
}
+ /* fall through */
case 'I':
(*mangled)++;
if (**mangled == '_')
diff --git a/coregrind/m_demangle/d-demangle.c b/coregrind/m_demangle/d-demangle.c
index 129999c..f9a7f1d 100644
--- a/coregrind/m_demangle/d-demangle.c
+++ b/coregrind/m_demangle/d-demangle.c
@@ -1,5 +1,5 @@
/* Demangler for the D programming language
- Copyright 2014, 2015, 2016 Free Software Foundation, Inc.
+ Copyright (C) 2014-2017 Free Software Foundation, Inc.
Written by Iain Buclaw (ibuclaw@gdcproject.org)
This file is part of the libiberty library.
diff --git a/coregrind/m_demangle/demangle.c b/coregrind/m_demangle/demangle.c
index 78db073..00fa203 100644
--- a/coregrind/m_demangle/demangle.c
+++ b/coregrind/m_demangle/demangle.c
@@ -7,9 +7,13 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
+ Rust demangler components are
+ Copyright (C) 2016-2016 David Tolnay
+ dtolnay@gmail.com
+
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
published by the Free Software Foundation; either version 2 of the
@@ -39,12 +43,22 @@
#include "vg_libciface.h"
#include "demangle.h"
-/* The demangler's job is to take a raw symbol name and turn it into
- something a Human Bean can understand. There are two levels of
- mangling.
- 1. First, C++ names are mangled by the compiler. So we'll have to
- undo that.
+/*------------------------------------------------------------*/
+/*--- ---*/
+/*------------------------------------------------------------*/
+
+/* The demangler's job is to take a raw symbol name and turn it into
+ something a Human Bean can understand. Our mangling model
+ comprises a three stage pipeline. Mangling pushes names forward
+ through the pipeline (0, then 1, then 2) and demangling is
+ obviously the reverse. In practice it is highly unlikely that a
+ name would require all stages, but it is not impossible either.
+
+ 0. If we're working with Rust, Rust names are lightly mangled by
+ the Rust front end.
+
+ 1. Then the name is subject to standard C++ mangling.
2. Optionally, in relatively rare cases, the resulting name is then
itself encoded using Z-escaping (see pub_core_redir.h) so as to
@@ -52,20 +66,32 @@
Therefore, VG_(demangle) first tries to undo (2). If successful,
the soname part is discarded (humans don't want to see that).
- Then, it tries to undo (1) (using demangling code from GNU/FSF).
+ Then, it tries to undo (1) (using demangling code from GNU/FSF) and
+ finally it tries to undo (0).
- Finally, change the name of all symbols which are known to be
+ Finally, it changes the name of all symbols which are known to be
functions below main() to "(below main)". This helps reduce
variability of stack traces, something which has been a problem for
the testsuite for a long time.
--------
- If do_cxx_demangle == True, does all the above stages:
+ If do_cxx_demangle == True, it does all the above stages:
- undo (2) [Z-encoding]
- undo (1) [C++ mangling]
+ - if (1) succeeds, undo (0) [Rust mangling]
- do the below-main hack
- If do_cxx_demangle == False, the middle stage is skipped:
+ Rust demangling (0) is only done if C++ demangling (1) succeeds
+ because Rust demangling is performed in-place, and it is difficult
+ to prove that we "own" the storage -- hence, that the in-place
+ operation is safe -- unless it is clear that it has come from the
+ C++ demangler, which returns its output in a heap-allocated buffer
+ which we can be sure we own. In practice (Nov 2016) this does not
+ seem to be a problem, since the Rust compiler appears to apply C++
+ mangling after Rust mangling, so we never encounter symbols that
+ require Rust demangling but not C++ demangling.
+
+ If do_cxx_demangle == False, the C++ and Rust stags are skipped:
- undo (2) [Z-encoding]
- do the below-main hack
*/
@@ -89,7 +115,7 @@
that buffer is owned by VG_(demangle). That means two things:
(1) Users of VG_(demangle) must not free that buffer.
(2) If the demangled name needs to be stashed away for later use,
- the contents of the buffer needs to be copied. It is not sufficient
+ the contents of the buffer need to be copied. It is not sufficient
to just store the pointer as it will point to deallocated memory
after the next VG_(demangle) invocation. */
void VG_(demangle) ( Bool do_cxx_demangling, Bool do_z_demangling,
@@ -111,15 +137,37 @@
}
/* Possibly undo (1) */
- if (do_cxx_demangling && VG_(clo_demangle)) {
+ if (do_cxx_demangling && VG_(clo_demangle)
+ && orig != NULL && orig[0] == '_' && orig[1] == 'Z') {
+ /* !!! vvv STATIC vvv !!! */
static HChar* demangled = NULL;
+ /* !!! ^^^ STATIC ^^^ !!! */
/* Free up previously demangled name */
- if (demangled) VG_(arena_free) (VG_AR_DEMANGLE, demangled);
-
+ if (demangled) {
+ VG_(arena_free) (VG_AR_DEMANGLE, demangled);
+ demangled = NULL;
+ }
demangled = ML_(cplus_demangle) ( orig, DMGL_ANSI | DMGL_PARAMS );
*result = (demangled == NULL) ? orig : demangled;
+
+ if (demangled) {
+ /* Possibly undo (0). This is the only place where it is
+ safe, from a storage management perspective, to
+ Rust-demangle the symbol. That's because Rust demangling
+ happens in place, so we need to be sure that the storage
+ it is happening in is actually owned by us, and non-const.
+ In this case, the value returned by ML_(cplus_demangle)
+ does have that property. */
+ if (rust_is_mangled(demangled)) {
+ rust_demangle_sym(demangled);
+ }
+ *result = demangled;
+ } else {
+ *result = orig;
+ }
+
} else {
*result = orig;
}
@@ -281,6 +329,7 @@
case 'A': EMITSO('@'); break;
case 'D': EMITSO('$'); break;
case 'L': EMITSO('('); break;
+ case 'P': EMITSO('%'); break;
case 'R': EMITSO(')'); break;
case 'S': EMITSO('/'); break;
case 'Z': EMITSO('Z'); break;
@@ -331,7 +380,9 @@
case 'A': EMITFN('@'); break;
case 'D': EMITFN('$'); break;
case 'L': EMITFN('('); break;
+ case 'P': EMITFN('%'); break;
case 'R': EMITFN(')'); break;
+ case 'S': EMITFN('/'); break;
case 'Z': EMITFN('Z'); break;
default: error = True; goto out;
}
diff --git a/coregrind/m_demangle/demangle.h b/coregrind/m_demangle/demangle.h
index b3439d9..f5a2143 100644
--- a/coregrind/m_demangle/demangle.h
+++ b/coregrind/m_demangle/demangle.h
@@ -1,5 +1,5 @@
/* Defs for interface to demanglers.
- Copyright (C) 1992-2015 Free Software Foundation, Inc.
+ Copyright (C) 1992-2017 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public License
@@ -65,9 +65,10 @@
#define DMGL_GNU_V3 (1 << 14)
#define DMGL_GNAT (1 << 15)
#define DMGL_DLANG (1 << 16)
+#define DMGL_RUST (1 << 17) /* Rust wraps GNU_V3 style mangling. */
/* If none of these are set, use 'current_demangling_style' as the default. */
-#define DMGL_STYLE_MASK (DMGL_AUTO|DMGL_GNU|DMGL_LUCID|DMGL_ARM|DMGL_HP|DMGL_EDG|DMGL_GNU_V3|DMGL_JAVA|DMGL_GNAT|DMGL_DLANG)
+#define DMGL_STYLE_MASK (DMGL_AUTO|DMGL_GNU|DMGL_LUCID|DMGL_ARM|DMGL_HP|DMGL_EDG|DMGL_GNU_V3|DMGL_JAVA|DMGL_GNAT|DMGL_DLANG|DMGL_RUST)
/* Enumeration of possible demangling styles.
@@ -90,7 +91,8 @@
gnu_v3_demangling = DMGL_GNU_V3,
java_demangling = DMGL_JAVA,
gnat_demangling = DMGL_GNAT,
- dlang_demangling = DMGL_DLANG
+ dlang_demangling = DMGL_DLANG,
+ rust_demangling = DMGL_RUST
} current_demangling_style;
/* Define string names for the various demangling styles. */
@@ -106,6 +108,7 @@
#define JAVA_DEMANGLING_STYLE_STRING "java"
#define GNAT_DEMANGLING_STYLE_STRING "gnat"
#define DLANG_DEMANGLING_STYLE_STRING "dlang"
+#define RUST_DEMANGLING_STYLE_STRING "rust"
/* Some macros to test what demangling style is active. */
@@ -120,6 +123,7 @@
#define JAVA_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_JAVA)
#define GNAT_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_GNAT)
#define DLANG_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_DLANG)
+#define RUST_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_RUST)
/* Provide information about the available demangle styles. This code is
pulled from gdb into libiberty because it is useful to binutils also. */
@@ -177,6 +181,27 @@
extern char *
dlang_demangle (const char *mangled, int options);
+/* Returns non-zero iff MANGLED is a rust mangled symbol. MANGLED must
+ already have been demangled through cplus_demangle_v3. If this function
+ returns non-zero then MANGLED can be demangled (in-place) using
+ RUST_DEMANGLE_SYM. */
+extern int
+rust_is_mangled (const char *mangled);
+
+/* Demangles SYM (in-place) if RUST_IS_MANGLED returned non-zero for SYM.
+ If RUST_IS_MANGLED returned zero for SYM then RUST_DEMANGLE_SYM might
+ replace characters that cannot be demangled with '?' and might truncate
+ SYM. After calling RUST_DEMANGLE_SYM SYM might be shorter, but never
+ larger. */
+extern void
+rust_demangle_sym (char *sym);
+
+/* Demangles MANGLED if it was GNU_V3 and then RUST mangled, otherwise
+ returns NULL. Uses CPLUS_DEMANGLE_V3, RUST_IS_MANGLED and
+ RUST_DEMANGLE_SYM. Returns a new string that is owned by the caller. */
+extern char *
+rust_demangle (const char *mangled, int options);
+
enum gnu_v3_ctor_kinds {
gnu_v3_complete_object_ctor = 1,
gnu_v3_base_object_ctor,
@@ -451,7 +476,9 @@
/* A transaction-safe function type. */
DEMANGLE_COMPONENT_TRANSACTION_SAFE,
/* A cloned function. */
- DEMANGLE_COMPONENT_CLONE
+ DEMANGLE_COMPONENT_CLONE,
+ DEMANGLE_COMPONENT_NOEXCEPT,
+ DEMANGLE_COMPONENT_THROW_SPEC
};
/* Types which are only used internally. */
@@ -469,6 +496,11 @@
/* The type of this component. */
enum demangle_component_type type;
+ /* Guard against recursive component printing.
+ Initialize to zero. Private to d_print_comp.
+ All other fields are final after initialization. */
+ int d_printing;
+
union
{
/* For DEMANGLE_COMPONENT_NAME. */
@@ -663,7 +695,7 @@
extern char *
cplus_demangle_print (int options,
- const struct demangle_component *tree,
+ struct demangle_component *tree,
int estimated_length,
size_t *p_allocated_size);
@@ -683,7 +715,7 @@
extern int
cplus_demangle_print_callback (int options,
- const struct demangle_component *tree,
+ struct demangle_component *tree,
demangle_callbackref callback, void *opaque);
#ifdef __cplusplus
diff --git a/coregrind/m_demangle/dyn-string.c b/coregrind/m_demangle/dyn-string.c
index 0dbb3ac..9beba6e 100644
--- a/coregrind/m_demangle/dyn-string.c
+++ b/coregrind/m_demangle/dyn-string.c
@@ -1,5 +1,5 @@
/* An abstract string datatype.
- Copyright (C) 1998, 1999, 2000, 2002, 2004 Free Software Foundation, Inc.
+ Copyright (C) 1998-2017 Free Software Foundation, Inc.
Contributed by Mark Mitchell (mark@markmitchell.com).
This file is part of GNU CC.
diff --git a/coregrind/m_demangle/dyn-string.h b/coregrind/m_demangle/dyn-string.h
index 7c3684b..6c0accc 100644
--- a/coregrind/m_demangle/dyn-string.h
+++ b/coregrind/m_demangle/dyn-string.h
@@ -1,5 +1,5 @@
/* An abstract string datatype.
- Copyright (C) 1998-2015 Free Software Foundation, Inc.
+ Copyright (C) 1998-2017 Free Software Foundation, Inc.
Contributed by Mark Mitchell (mark@markmitchell.com).
This file is part of GCC.
diff --git a/coregrind/m_demangle/rust-demangle.c b/coregrind/m_demangle/rust-demangle.c
new file mode 100644
index 0000000..3bfde6d
--- /dev/null
+++ b/coregrind/m_demangle/rust-demangle.c
@@ -0,0 +1,363 @@
+/* Demangler for the Rust programming language
+ Copyright (C) 2016-2017 Free Software Foundation, Inc.
+ Written by David Tolnay (dtolnay@gmail.com).
+
+This file is part of the libiberty library.
+Libiberty is free software; you can redistribute it and/or
+modify it under the terms of the GNU Library General Public
+License as published by the Free Software Foundation; either
+version 2 of the License, or (at your option) any later version.
+
+In addition to the permissions in the GNU Library General Public
+License, the Free Software Foundation gives you unlimited permission
+to link the compiled version of this file into combinations with other
+programs, and to distribute those combinations without any restriction
+coming from the use of this file. (The Library Public License
+restrictions do apply in other respects; for example, they cover
+modification of the file, and distribution when not linked into a
+combined executable.)
+
+Libiberty is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+Library General Public License for more details.
+
+You should have received a copy of the GNU Library General Public
+License along with libiberty; see the file COPYING.LIB.
+If not, see <http://www.gnu.org/licenses/>. */
+
+
+#if 0 /* in valgrind */
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+#endif /* ! in valgrind */
+
+#if 0 /* in valgrind */
+#include "safe-ctype.h"
+#endif /* ! in valgrind */
+
+#if 0 /* in valgrind */
+#include <sys/types.h>
+#include <string.h>
+#include <stdio.h>
+#endif /* ! in valgrind */
+
+#if 0 /* in valgrind */
+#ifdef HAVE_STRING_H
+#include <string.h>
+#else
+extern size_t strlen(const char *s);
+extern int strncmp(const char *s1, const char *s2, size_t n);
+extern void *memset(void *s, int c, size_t n);
+#endif
+#endif /* ! in valgrind */
+
+#if 0 /* in valgrind */
+#include <demangle.h>
+#include "libiberty.h"
+#endif /* ! in valgrind */
+
+#include "vg_libciface.h"
+
+#include "ansidecl.h"
+#include "demangle.h"
+#include "safe-ctype.h"
+
+/* Mangled Rust symbols look like this:
+ _$LT$std..sys..fd..FileDesc$u20$as$u20$core..ops..Drop$GT$::drop::hc68340e1baa4987a
+
+ The original symbol is:
+ <std::sys::fd::FileDesc as core::ops::Drop>::drop
+
+ The last component of the path is a 64-bit hash in lowercase hex,
+ prefixed with "h". Rust does not have a global namespace between
+ crates, an illusion which Rust maintains by using the hash to
+ distinguish things that would otherwise have the same symbol.
+
+ Any path component not starting with a XID_Start character is
+ prefixed with "_".
+
+ The following escape sequences are used:
+
+ "," => $C$
+ "@" => $SP$
+ "*" => $BP$
+ "&" => $RF$
+ "<" => $LT$
+ ">" => $GT$
+ "(" => $LP$
+ ")" => $RP$
+ " " => $u20$
+ "\"" => $u22$
+ "'" => $u27$
+ "+" => $u2b$
+ ";" => $u3b$
+ "[" => $u5b$
+ "]" => $u5d$
+ "{" => $u7b$
+ "}" => $u7d$
+ "~" => $u7e$
+
+ A double ".." means "::" and a single "." means "-".
+
+ The only characters allowed in the mangled symbol are a-zA-Z0-9 and _.:$ */
+
+static const char *hash_prefix = "::h";
+static const size_t hash_prefix_len = 3;
+static const size_t hash_len = 16;
+
+static int is_prefixed_hash (const char *start);
+static int looks_like_rust (const char *sym, size_t len);
+static int unescape (const char **in, char **out, const char *seq, char value);
+
+/* INPUT: sym: symbol that has been through C++ (gnu v3) demangling
+
+ This function looks for the following indicators:
+
+ 1. The hash must consist of "h" followed by 16 lowercase hex digits.
+
+ 2. As a sanity check, the hash must use between 5 and 15 of the 16
+ possible hex digits. This is true of 99.9998% of hashes so once
+ in your life you may see a false negative. The point is to
+ notice path components that could be Rust hashes but are
+ probably not, like "haaaaaaaaaaaaaaaa". In this case a false
+ positive (non-Rust symbol has an important path component
+ removed because it looks like a Rust hash) is worse than a false
+ negative (the rare Rust symbol is not demangled) so this sets
+ the balance in favor of false negatives.
+
+ 3. There must be no characters other than a-zA-Z0-9 and _.:$
+
+ 4. There must be no unrecognized $-sign sequences.
+
+ 5. There must be no sequence of three or more dots in a row ("..."). */
+
+int
+rust_is_mangled (const char *sym)
+{
+ size_t len, len_without_hash;
+
+ if (!sym)
+ return 0;
+
+ len = strlen (sym);
+ if (len <= hash_prefix_len + hash_len)
+ /* Not long enough to contain "::h" + hash + something else */
+ return 0;
+
+ len_without_hash = len - (hash_prefix_len + hash_len);
+ if (!is_prefixed_hash (sym + len_without_hash))
+ return 0;
+
+ return looks_like_rust (sym, len_without_hash);
+}
+
+/* A hash is the prefix "::h" followed by 16 lowercase hex digits. The
+ hex digits must comprise between 5 and 15 (inclusive) distinct
+ digits. */
+
+static int
+is_prefixed_hash (const char *str)
+{
+ const char *end;
+ char seen[16];
+ size_t i;
+ int count;
+
+ if (strncmp (str, hash_prefix, hash_prefix_len))
+ return 0;
+ str += hash_prefix_len;
+
+ memset (seen, 0, sizeof(seen));
+ for (end = str + hash_len; str < end; str++)
+ if (*str >= '0' && *str <= '9')
+ seen[*str - '0'] = 1;
+ else if (*str >= 'a' && *str <= 'f')
+ seen[*str - 'a' + 10] = 1;
+ else
+ return 0;
+
+ /* Count how many distinct digits seen */
+ count = 0;
+ for (i = 0; i < 16; i++)
+ if (seen[i])
+ count++;
+
+ return count >= 5 && count <= 15;
+}
+
+static int
+looks_like_rust (const char *str, size_t len)
+{
+ const char *end = str + len;
+
+ while (str < end)
+ switch (*str)
+ {
+ case '$':
+ if (!strncmp (str, "$C$", 3))
+ str += 3;
+ else if (!strncmp (str, "$SP$", 4)
+ || !strncmp (str, "$BP$", 4)
+ || !strncmp (str, "$RF$", 4)
+ || !strncmp (str, "$LT$", 4)
+ || !strncmp (str, "$GT$", 4)
+ || !strncmp (str, "$LP$", 4)
+ || !strncmp (str, "$RP$", 4))
+ str += 4;
+ else if (!strncmp (str, "$u20$", 5)
+ || !strncmp (str, "$u22$", 5)
+ || !strncmp (str, "$u27$", 5)
+ || !strncmp (str, "$u2b$", 5)
+ || !strncmp (str, "$u3b$", 5)
+ || !strncmp (str, "$u5b$", 5)
+ || !strncmp (str, "$u5d$", 5)
+ || !strncmp (str, "$u7b$", 5)
+ || !strncmp (str, "$u7d$", 5)
+ || !strncmp (str, "$u7e$", 5))
+ str += 5;
+ else
+ return 0;
+ break;
+ case '.':
+ /* Do not allow three or more consecutive dots */
+ if (!strncmp (str, "...", 3))
+ return 0;
+ /* Fall through */
+ case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
+ case 'g': case 'h': case 'i': case 'j': case 'k': case 'l':
+ case 'm': case 'n': case 'o': case 'p': case 'q': case 'r':
+ case 's': case 't': case 'u': case 'v': case 'w': case 'x':
+ case 'y': case 'z':
+ case 'A': case 'B': case 'C': case 'D': case 'E': case 'F':
+ case 'G': case 'H': case 'I': case 'J': case 'K': case 'L':
+ case 'M': case 'N': case 'O': case 'P': case 'Q': case 'R':
+ case 'S': case 'T': case 'U': case 'V': case 'W': case 'X':
+ case 'Y': case 'Z':
+ case '0': case '1': case '2': case '3': case '4': case '5':
+ case '6': case '7': case '8': case '9':
+ case '_':
+ case ':':
+ str++;
+ break;
+ default:
+ return 0;
+ }
+
+ return 1;
+}
+
+/*
+ INPUT: sym: symbol for which rust_is_mangled(sym) returned 1.
+
+ The input is demangled in-place because the mangled name is always
+ longer than the demangled one. */
+
+void
+rust_demangle_sym (char *sym)
+{
+ const char *in;
+ char *out;
+ const char *end;
+
+ if (!sym)
+ return;
+
+ in = sym;
+ out = sym;
+ end = sym + strlen (sym) - (hash_prefix_len + hash_len);
+
+ while (in < end)
+ switch (*in)
+ {
+ case '$':
+ if (!(unescape (&in, &out, "$C$", ',')
+ || unescape (&in, &out, "$SP$", '@')
+ || unescape (&in, &out, "$BP$", '*')
+ || unescape (&in, &out, "$RF$", '&')
+ || unescape (&in, &out, "$LT$", '<')
+ || unescape (&in, &out, "$GT$", '>')
+ || unescape (&in, &out, "$LP$", '(')
+ || unescape (&in, &out, "$RP$", ')')
+ || unescape (&in, &out, "$u20$", ' ')
+ || unescape (&in, &out, "$u22$", '\"')
+ || unescape (&in, &out, "$u27$", '\'')
+ || unescape (&in, &out, "$u2b$", '+')
+ || unescape (&in, &out, "$u3b$", ';')
+ || unescape (&in, &out, "$u5b$", '[')
+ || unescape (&in, &out, "$u5d$", ']')
+ || unescape (&in, &out, "$u7b$", '{')
+ || unescape (&in, &out, "$u7d$", '}')
+ || unescape (&in, &out, "$u7e$", '~'))) {
+ /* unexpected escape sequence, not looks_like_rust. */
+ goto fail;
+ }
+ break;
+ case '_':
+ /* If this is the start of a path component and the next
+ character is an escape sequence, ignore the underscore. The
+ mangler inserts an underscore to make sure the path
+ component begins with a XID_Start character. */
+ if ((in == sym || in[-1] == ':') && in[1] == '$')
+ in++;
+ else
+ *out++ = *in++;
+ break;
+ case '.':
+ if (in[1] == '.')
+ {
+ /* ".." becomes "::" */
+ *out++ = ':';
+ *out++ = ':';
+ in += 2;
+ }
+ else
+ {
+ /* "." becomes "-" */
+ *out++ = '-';
+ in++;
+ }
+ break;
+ case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
+ case 'g': case 'h': case 'i': case 'j': case 'k': case 'l':
+ case 'm': case 'n': case 'o': case 'p': case 'q': case 'r':
+ case 's': case 't': case 'u': case 'v': case 'w': case 'x':
+ case 'y': case 'z':
+ case 'A': case 'B': case 'C': case 'D': case 'E': case 'F':
+ case 'G': case 'H': case 'I': case 'J': case 'K': case 'L':
+ case 'M': case 'N': case 'O': case 'P': case 'Q': case 'R':
+ case 'S': case 'T': case 'U': case 'V': case 'W': case 'X':
+ case 'Y': case 'Z':
+ case '0': case '1': case '2': case '3': case '4': case '5':
+ case '6': case '7': case '8': case '9':
+ case ':':
+ *out++ = *in++;
+ break;
+ default:
+ /* unexpected character in symbol, not looks_like_rust. */
+ goto fail;
+ }
+ goto done;
+
+fail:
+ *out++ = '?'; /* This is pretty lame, but it's hard to do better. */
+done:
+ *out = '\0';
+}
+
+static int
+unescape (const char **in, char **out, const char *seq, char value)
+{
+ size_t len = strlen (seq);
+
+ if (strncmp (*in, seq, len))
+ return 0;
+
+ **out = value;
+
+ *in += len;
+ *out += 1;
+
+ return 1;
+}
diff --git a/coregrind/m_demangle/safe-ctype.c b/coregrind/m_demangle/safe-ctype.c
index 7ac1c7a..d3247ed 100644
--- a/coregrind/m_demangle/safe-ctype.c
+++ b/coregrind/m_demangle/safe-ctype.c
@@ -1,7 +1,6 @@
/* <ctype.h> replacement macros.
- Copyright (C) 2000, 2001, 2002, 2003, 2004,
- 2005 Free Software Foundation, Inc.
+ Copyright (C) 2000-2017 Free Software Foundation, Inc.
Contributed by Zack Weinberg <zackw@stanford.edu>.
This file is part of the libiberty library.
diff --git a/coregrind/m_demangle/safe-ctype.h b/coregrind/m_demangle/safe-ctype.h
index 1f4465b..66c8fe9 100644
--- a/coregrind/m_demangle/safe-ctype.h
+++ b/coregrind/m_demangle/safe-ctype.h
@@ -1,6 +1,6 @@
/* <ctype.h> replacement macros.
- Copyright (C) 2000-2015 Free Software Foundation, Inc.
+ Copyright (C) 2000-2017 Free Software Foundation, Inc.
Contributed by Zack Weinberg <zackw@stanford.edu>.
This file is part of the libiberty library.
@@ -112,7 +112,7 @@
#define TOUPPER(c) _sch_toupper[(c) & 0xff]
#define TOLOWER(c) _sch_tolower[(c) & 0xff]
-/* Prevent the users of safe-ctype.h from accidently using the routines
+/* Prevent the users of safe-ctype.h from accidentally using the routines
from ctype.h. Initially, the approach was to produce an error when
detecting that ctype.h has been included. But this was causing
trouble as ctype.h might get indirectly included as a result of
diff --git a/coregrind/m_demangle/vg_libciface.h b/coregrind/m_demangle/vg_libciface.h
index dd57fca..762e63a 100644
--- a/coregrind/m_demangle/vg_libciface.h
+++ b/coregrind/m_demangle/vg_libciface.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_dispatch/dispatch-amd64-darwin.S b/coregrind/m_dispatch/dispatch-amd64-darwin.S
index dd7f117..d560306 100644
--- a/coregrind/m_dispatch/dispatch-amd64-darwin.S
+++ b/coregrind/m_dispatch/dispatch-amd64-darwin.S
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_dispatch/dispatch-amd64-linux.S b/coregrind/m_dispatch/dispatch-amd64-linux.S
index bb7a037..62717d3 100644
--- a/coregrind/m_dispatch/dispatch-amd64-linux.S
+++ b/coregrind/m_dispatch/dispatch-amd64-linux.S
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_dispatch/dispatch-amd64-solaris.S b/coregrind/m_dispatch/dispatch-amd64-solaris.S
index 3750693..79bb512 100644
--- a/coregrind/m_dispatch/dispatch-amd64-solaris.S
+++ b/coregrind/m_dispatch/dispatch-amd64-solaris.S
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_dispatch/dispatch-arm-linux.S b/coregrind/m_dispatch/dispatch-arm-linux.S
index c21e5e4..3731c2e 100644
--- a/coregrind/m_dispatch/dispatch-arm-linux.S
+++ b/coregrind/m_dispatch/dispatch-arm-linux.S
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2015 Evan Geller
+ Copyright (C) 2008-2017 Evan Geller
gaze@bea.ms
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_dispatch/dispatch-arm64-linux.S b/coregrind/m_dispatch/dispatch-arm64-linux.S
index 2e8e0cd..ee289fa 100644
--- a/coregrind/m_dispatch/dispatch-arm64-linux.S
+++ b/coregrind/m_dispatch/dispatch-arm64-linux.S
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2013-2015 OpenWorks
+ Copyright (C) 2013-2017 OpenWorks
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_dispatch/dispatch-mips32-linux.S b/coregrind/m_dispatch/dispatch-mips32-linux.S
index 0ff5f48..9918403 100644
--- a/coregrind/m_dispatch/dispatch-mips32-linux.S
+++ b/coregrind/m_dispatch/dispatch-mips32-linux.S
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 RT-RK
+ Copyright (C) 2000-2017 RT-RK
mips-valgrind@rt-rk.com
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_dispatch/dispatch-mips64-linux.S b/coregrind/m_dispatch/dispatch-mips64-linux.S
index 5eec8e5..dc2beee 100644
--- a/coregrind/m_dispatch/dispatch-mips64-linux.S
+++ b/coregrind/m_dispatch/dispatch-mips64-linux.S
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 RT-RK
+ Copyright (C) 2000-2017 RT-RK
mips-valgrind@rt-rk.com
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_dispatch/dispatch-ppc32-linux.S b/coregrind/m_dispatch/dispatch-ppc32-linux.S
index 2304b85..432306b 100644
--- a/coregrind/m_dispatch/dispatch-ppc32-linux.S
+++ b/coregrind/m_dispatch/dispatch-ppc32-linux.S
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Cerion Armour-Brown <cerion@open-works.co.uk>
+ Copyright (C) 2005-2017 Cerion Armour-Brown <cerion@open-works.co.uk>
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/m_dispatch/dispatch-ppc64be-linux.S b/coregrind/m_dispatch/dispatch-ppc64be-linux.S
index 64e192a..91bd3b2 100644
--- a/coregrind/m_dispatch/dispatch-ppc64be-linux.S
+++ b/coregrind/m_dispatch/dispatch-ppc64be-linux.S
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Cerion Armour-Brown <cerion@open-works.co.uk>
+ Copyright (C) 2005-2017 Cerion Armour-Brown <cerion@open-works.co.uk>
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/m_dispatch/dispatch-ppc64le-linux.S b/coregrind/m_dispatch/dispatch-ppc64le-linux.S
index 1772283..21e4358 100644
--- a/coregrind/m_dispatch/dispatch-ppc64le-linux.S
+++ b/coregrind/m_dispatch/dispatch-ppc64le-linux.S
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Cerion Armour-Brown <cerion@open-works.co.uk>
+ Copyright (C) 2005-2017 Cerion Armour-Brown <cerion@open-works.co.uk>
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/m_dispatch/dispatch-s390x-linux.S b/coregrind/m_dispatch/dispatch-s390x-linux.S
index aec65ba..83c2e2a 100644
--- a/coregrind/m_dispatch/dispatch-s390x-linux.S
+++ b/coregrind/m_dispatch/dispatch-s390x-linux.S
@@ -8,8 +8,8 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2015
- Copyright (C) 2011-2015, Florian Krohm (britzel@acm.org)
+ Copyright IBM Corp. 2010-2017
+ Copyright (C) 2011-2017, Florian Krohm (britzel@acm.org)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/m_dispatch/dispatch-tilegx-linux.S b/coregrind/m_dispatch/dispatch-tilegx-linux.S
deleted file mode 100644
index b3114ef..0000000
--- a/coregrind/m_dispatch/dispatch-tilegx-linux.S
+++ /dev/null
@@ -1,309 +0,0 @@
-
-/*--------------------------------------------------------------------*/
-/*--- begin dispatch-tilegx-linux.S ---*/
-/*--------------------------------------------------------------------*/
-
-/*
- This file is part of Valgrind, a dynamic binary instrumentation
- framework.
-
- Copyright (C) 2010-2015 Tilera Corp.
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of the
- License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful, but
- WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
- 02111-1307, USA.
-
- The GNU General Public License is contained in the file COPYING.
-*/
-
-/* Contributed by Zhi-Gang Liu <zliu at tilera dot com> */
-
-#include "pub_core_basics_asm.h"
-
-#if defined(VGP_tilegx_linux)
-#include "pub_core_dispatch_asm.h"
-#include "pub_core_transtab_asm.h"
-#include "libvex_guest_offsets.h" /* for OFFSET_tilegx_PC */
-
- /*------------------------------------------------------------*/
- /*--- ---*/
- /*--- The dispatch loop. VG_(run_innerloop) is used to ---*/
- /*--- run all translations except no-redir ones. ---*/
- /*--- ---*/
- /*------------------------------------------------------------*/
-
- /*----------------------------------------------------*/
- /*--- Preamble (set everything up) ---*/
- /*----------------------------------------------------*/
-
- /* signature:
- void VG_(disp_run_translations)(UWord* two_words,
- void* guest_state,
- Addr host_addr );
- UWord VG_(run_innerloop) ( void* guest_state, UWord do_profiling );
- */
-
- .text
- .globl VG_(disp_run_translations)
- VG_(disp_run_translations):
-
- /* r0 holds two_words
- r1 holds guest_state
- r2 holds host_addr */
-
- /* New stack frame */
- addli sp, sp, -256
- addi r29, sp, 8
- /*
- high memory of stack
- 216 lr
- 208 r53
- 200 r52
- 192 r51
- ...
- 48 r33
- 40 r32
- 32 r31
- 24 r30
- 16 r1 <---
- 8 r0
- 0 <-sp
- */
- st_add r29, r0, 8
- st_add r29, r1, 8
-
- /* ... and r30 - r53 */
- st_add r29, r30, 8
- st_add r29, r31, 8
- st_add r29, r32, 8
- st_add r29, r33, 8
- st_add r29, r34, 8
- st_add r29, r35, 8
- st_add r29, r36, 8
- st_add r29, r37, 8
- st_add r29, r38, 8
- st_add r29, r39, 8
- st_add r29, r40, 8
- st_add r29, r41, 8
- st_add r29, r42, 8
- st_add r29, r43, 8
- st_add r29, r44, 8
- st_add r29, r45, 8
- st_add r29, r46, 8
- st_add r29, r47, 8
- st_add r29, r48, 8
- st_add r29, r49, 8
- st_add r29, r50, 8
- st_add r29, r51, 8
- st_add r29, r52, 8
- st_add r29, r53, 8
- st r29, lr
-
- /* Load the address of guest state into guest state register r50. */
- move r50, r1
-
- //j postamble
-
- /* jump to the code cache. */
- jr r2
- /*NOTREACHED*/
-
-
- /*----------------------------------------------------*/
- /*--- Postamble and exit. ---*/
- /*----------------------------------------------------*/
-
-postamble:
- /* At this point, r12 and r13 contain two
- words to be returned to the caller. r12
- holds a TRC value, and r13 optionally may
- hold another word (for CHAIN_ME exits, the
- address of the place to patch.) */
-
- /* run_innerloop_exit_REALLY:
- r50 holds VG_TRC_* value to return
- Return to parent stack
- addli sp, sp, 256 */
-
- addi r29, sp, 8
-
- /* Restore r0 from stack; holding address of twp words */
- ld_add r0, r29, 16
- /* store r12 in two_words[0] */
- st_add r0, r12, 8
- /* store r13 in two_words[1] */
- st r0, r13
-
- /* Restore callee-saved registers... */
- ld_add r30, r29, 8
- ld_add r31, r29, 8
- ld_add r32, r29, 8
- ld_add r33, r29, 8
- ld_add r34, r29, 8
- ld_add r35, r29, 8
- ld_add r36, r29, 8
- ld_add r37, r29, 8
- ld_add r38, r29, 8
- ld_add r39, r29, 8
- ld_add r40, r29, 8
- ld_add r41, r29, 8
- ld_add r42, r29, 8
- ld_add r43, r29, 8
- ld_add r44, r29, 8
- ld_add r45, r29, 8
- ld_add r46, r29, 8
- ld_add r47, r29, 8
- ld_add r48, r29, 8
- ld_add r49, r29, 8
- ld_add r50, r29, 8
- ld_add r51, r29, 8
- ld_add r52, r29, 8
- ld_add r53, r29, 8
- ld lr, r29
- addli sp, sp, 256 /* stack_size */
- jr lr
- nop
-
-
- /*----------------------------------------------------*/
- /*--- Continuation points ---*/
- /*----------------------------------------------------*/
-
- /* ------ Chain me to slow entry point ------ */
- .global VG_(disp_cp_chain_me_to_slowEP)
- VG_(disp_cp_chain_me_to_slowEP):
- /* We got called. The return address indicates
- where the patching needs to happen. Collect
- the return address and, exit back to C land,
- handing the caller the pair (Chain_me_S, RA) */
- # if (VG_TRC_CHAIN_ME_TO_SLOW_EP > 128)
- # error ("VG_TRC_CHAIN_ME_TO_SLOW_EP is > 128");
- # endif
- moveli r12, VG_TRC_CHAIN_ME_TO_SLOW_EP
- move r13, lr
- /* 32 = mkLoadImm_EXACTLY4
- 8 = jalr r9
- 8 = nop */
- addi r13, r13, -40
- j postamble
-
- /* ------ Chain me to slow entry point ------ */
- .global VG_(disp_cp_chain_me_to_fastEP)
- VG_(disp_cp_chain_me_to_fastEP):
- /* We got called. The return address indicates
- where the patching needs to happen. Collect
- the return address and, exit back to C land,
- handing the caller the pair (Chain_me_S, RA) */
- # if (VG_TRC_CHAIN_ME_TO_FAST_EP > 128)
- # error ("VG_TRC_CHAIN_ME_TO_FAST_EP is > 128");
- # endif
- moveli r12, VG_TRC_CHAIN_ME_TO_FAST_EP
- move r13, lr
- /* 32 = mkLoadImm_EXACTLY4
- 8 = jalr r9
- 8 = nop */
- addi r13, r13, -40
- j postamble
-
- /* ------ Indirect but boring jump ------ */
- .global VG_(disp_cp_xindir)
- VG_(disp_cp_xindir):
- /* Where are we going? */
- addli r11, r50, OFFSET_tilegx_pc
- ld r11, r11
-
- moveli r7, hw2_last(VG_(stats__n_xindirs_32))
- shl16insli r7, r7, hw1(VG_(stats__n_xindirs_32))
- shl16insli r7, r7, hw0(VG_(stats__n_xindirs_32))
- ld4u r6, r7
- addi r6, r6, 1
- st4 r7, r6
-
- /* try a fast lookup in the translation cache */
- /* r14 = VG_TT_FAST_HASH(addr) * sizeof(ULong*)
- = (t8 >> 3 & VG_TT_FAST_MASK) << 3 */
-
- move r14, r11
- /* Assume VG_TT_FAST_MASK < 4G */
- moveli r12, hw1(VG_TT_FAST_MASK)
- shl16insli r12, r12, hw0(VG_TT_FAST_MASK)
- shrui r14, r14, 3
- and r14, r14, r12
- shli r14, r14, 4
- /* Note, each tt_fast hash entry has two pointers i.e. 16 Bytes. */
-
- /* r13 = (addr of VG_(tt_fast)) + r14 */
- moveli r13, hw2_last(VG_(tt_fast))
- shl16insli r13, r13, hw1(VG_(tt_fast))
- shl16insli r13, r13, hw0(VG_(tt_fast))
-
- add r13, r13, r14
-
- /* r12 = VG_(tt_fast)[hash] :: ULong* */
- ld_add r12, r13, 8
-
- {
- ld r25, r13
- sub r7, r12, r11
- }
-
- bnez r7, fast_lookup_failed
-
- /* Run the translation */
- jr r25
-
- .quad 0x0
-
-fast_lookup_failed:
- /* %PC is up to date */
- /* back out decrement of the dispatch counter */
- /* hold dispatch_ctr in t0 (r8) */
-
- moveli r7, hw2_last(VG_(stats__n_xindir_misses_32))
- shl16insli r7, r7, hw1(VG_(stats__n_xindir_misses_32))
- shl16insli r7, r7, hw0(VG_(stats__n_xindir_misses_32))
- ld4u r6, r7
- addi r6, r6, 1
- st4 r7, r6
- moveli r12, VG_TRC_INNER_FASTMISS
- movei r13, 0
- j postamble
-
- /* ------ Assisted jump ------ */
- .global VG_(disp_cp_xassisted)
- VG_(disp_cp_xassisted):
- /* guest-state-pointer contains the TRC. Put the value into the
- return register */
- move r12, r50
- movei r13, 0
- j postamble
-
- /* ------ Event check failed ------ */
- .global VG_(disp_cp_evcheck_fail)
- VG_(disp_cp_evcheck_fail):
- moveli r12, VG_TRC_INNER_COUNTERZERO
- movei r13, 0
- j postamble
-
- .size VG_(disp_run_translations), .-VG_(disp_run_translations)
-
-#endif /* defined(VGP_tilegx_linux) */
-
-/* Let the linker know we don't need an executable stack */
-MARK_STACK_NO_EXEC
-
-/*--------------------------------------------------------------------*/
-/*--- end ---*/
-/*--------------------------------------------------------------------*/
-
diff --git a/coregrind/m_dispatch/dispatch-x86-darwin.S b/coregrind/m_dispatch/dispatch-x86-darwin.S
index d5edbab..55188e9 100644
--- a/coregrind/m_dispatch/dispatch-x86-darwin.S
+++ b/coregrind/m_dispatch/dispatch-x86-darwin.S
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_dispatch/dispatch-x86-linux.S b/coregrind/m_dispatch/dispatch-x86-linux.S
index 6845911..d949f1f 100644
--- a/coregrind/m_dispatch/dispatch-x86-linux.S
+++ b/coregrind/m_dispatch/dispatch-x86-linux.S
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_dispatch/dispatch-x86-solaris.S b/coregrind/m_dispatch/dispatch-x86-solaris.S
index 88f796c..aec5b3a 100644
--- a/coregrind/m_dispatch/dispatch-x86-solaris.S
+++ b/coregrind/m_dispatch/dispatch-x86-solaris.S
@@ -8,8 +8,8 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2012 Julian Seward
- jseward@acm.org
+ Copyright (C) 2012-2017 Petr Pavlu
+ setup@dagobah.cz
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/m_errormgr.c b/coregrind/m_errormgr.c
index 8f63702..fd900ee 100644
--- a/coregrind/m_errormgr.c
+++ b/coregrind/m_errormgr.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_execontext.c b/coregrind/m_execontext.c
index c074f61..e655b09 100644
--- a/coregrind/m_execontext.c
+++ b/coregrind/m_execontext.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -186,7 +186,7 @@
" exectx: %'lu lists, %'llu contexts (avg %3.2f per list)"
" (avg %3.2f IP per context)\n",
ec_htab_size, ec_totstored, (Double)ec_totstored / (Double)ec_htab_size,
- (Double)total_n_ips / (Double)ec_htab_size
+ (Double)total_n_ips / (Double)ec_totstored
);
VG_(message)(Vg_DebugMsg,
" exectx: %'llu searches, %'llu full compares (%'llu per 1000)\n",
@@ -326,6 +326,12 @@
ec_htab_size_idx++;
}
+/* Used by the outer as a marker to separate the frames of the inner valgrind
+ from the frames of the inner guest frames. */
+static void _______VVVVVVVV_appended_inner_guest_stack_VVVVVVVV_______ (void)
+{
+}
+
/* Do the first part of getting a stack trace: actually unwind the
stack, and hand the results off to the duplicate-trace-finder
(_wrk2). */
@@ -350,6 +356,38 @@
NULL/*array to dump SP values in*/,
NULL/*array to dump FP values in*/,
first_ip_delta );
+ if (VG_(inner_threads) != NULL
+ && n_ips + 1 < VG_(clo_backtrace_size)) {
+ /* An inner V has informed us (the outer) of its thread array.
+ Append the inner guest stack trace, if we still have some
+ room in the ips array for the separator and (some) inner
+ guest IPs. */
+ UInt inner_tid;
+
+ for (inner_tid = 1; inner_tid < VG_N_THREADS; inner_tid++) {
+ if (VG_(threads)[tid].os_state.lwpid
+ == VG_(inner_threads)[inner_tid].os_state.lwpid) {
+ ThreadState* save_outer_vg_threads = VG_(threads);
+ UInt n_ips_inner_guest;
+
+ /* Append the separator + the inner guest stack trace. */
+ ips[n_ips] = (Addr)
+ _______VVVVVVVV_appended_inner_guest_stack_VVVVVVVV_______;
+ n_ips++;
+ VG_(threads) = VG_(inner_threads);
+ n_ips_inner_guest
+ = VG_(get_StackTrace)( inner_tid,
+ ips + n_ips,
+ VG_(clo_backtrace_size) - n_ips,
+ NULL/*array to dump SP values in*/,
+ NULL/*array to dump FP values in*/,
+ first_ip_delta );
+ n_ips += n_ips_inner_guest;
+ VG_(threads) = save_outer_vg_threads;
+ break;
+ }
+ }
+ }
}
return record_ExeContext_wrk2 ( ips, n_ips );
diff --git a/coregrind/m_gdbserver/README_DEVELOPERS b/coregrind/m_gdbserver/README_DEVELOPERS
index 8866ccb..03eb76a 100644
--- a/coregrind/m_gdbserver/README_DEVELOPERS
+++ b/coregrind/m_gdbserver/README_DEVELOPERS
@@ -32,7 +32,7 @@
The standard gdb distribution has a standalone gdbserver (a small
executable) which implements this protocol and the needed system calls
to allow gdb to remotely debug process running on a linux or MacOS or
-...
+Solaris...
Activation of gdbserver code inside valgrind
--------------------------------------------
@@ -113,7 +113,7 @@
before modifying the value. gdb checks that the value has not changed
and so "does not believe" the information that the write watchpoint
was triggered, and continues the execution. At the next watchpoint
-occurence, gdb sees the value has changed. But the watchpoints are all
+occurrence, gdb sees the value has changed. But the watchpoints are all
reported "off by one". To avoid this, Valgrind gdbserver must
terminate the current instruction before reporting the write watchpoint.
Terminating precisely the current instruction implies to have
@@ -206,6 +206,12 @@
Do not kill -9 vgdb while it has interrupted the valgrind process,
otherwise the valgrind process will very probably stay stopped or die.
+On Solaris, this forced invocation is implemented via agent thread.
+The process is first stopped (all the threads at once), and special agent
+thread is created which will force gbdserver invocation. After its
+work is done, the agent thread is destroyed and process resumed.
+Agent thread functionality is a Solaris OS feature, used also by debuggers.
+Therefore vgdb-invoker-solaris implementation is really small.
Implementation is based on the gdbserver code from gdb 6.6
----------------------------------------------------------
@@ -257,7 +263,7 @@
The main thing to do is to make a file valgrind-low-hal9000.c.
Start from an existing file (e.g. valgrind-low-x86.c).
The data structures 'struct reg regs'
-and 'const char *expedite_regs' are build from files
+and 'const char *expedite_regs' are built from files
in the gdb sources, e.g. for an new arch hal9000
cd gdb/regformats
sh ./regdat.sh reg-hal9000.dat hal9000
@@ -287,6 +293,9 @@
things are needed e.g. to attach to threads etc).
A courageous Mac aficionado is welcome on this aspect.
+For Solaris, only architecture specific functionality in vgdb-invoker-solaris.c
+needs to be implemented, similar to Linux above.
+
Optional:
To let gdb see the Valgrind shadow registers, xml description
files have to be provided + valgrind-low-hal9000.c has
diff --git a/coregrind/m_gdbserver/m_gdbserver.c b/coregrind/m_gdbserver/m_gdbserver.c
index 99122d2..87fbce2 100644
--- a/coregrind/m_gdbserver/m_gdbserver.c
+++ b/coregrind/m_gdbserver/m_gdbserver.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2015 Philippe Waroquiers
+ Copyright (C) 2011-2017 Philippe Waroquiers
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -811,7 +811,7 @@
/* When all threads are blocked in a system call, the Valgrind
scheduler cannot poll the shared memory for gdbserver activity. In
- such a case, vgdb will force the invokation of gdbserver using
+ such a case, vgdb will force the invocation of gdbserver using
ptrace. To do that, vgdb 'pushes' a call to invoke_gdbserver
on the stack using ptrace. invoke_gdbserver must not return.
Instead, it must call give_control_back_to_vgdb.
diff --git a/coregrind/m_gdbserver/server.c b/coregrind/m_gdbserver/server.c
index 2f26178..ca0d7bd 100644
--- a/coregrind/m_gdbserver/server.c
+++ b/coregrind/m_gdbserver/server.c
@@ -107,7 +107,7 @@
&& initial_valgrind_sink_saved) {
VG_(log_output_sink).fd = initial_valgrind_sink.fd;
VG_(umsg) ("Reset valgrind output to log (%s)\n",
- (info = NULL ? "" : info));
+ (info == NULL ? "" : info));
}
}
@@ -339,7 +339,7 @@
do not, suggest a 'likely somewhat working' address: */
const Addr tool_text_start
= tooldi ?
- VG_(DebugInfo_get_text_avma) (tooldi) : 0x38000000;
+ VG_(DebugInfo_get_text_avma) (tooldi) : 0x58000000;
const NSegment *toolseg
= tooldi ?
VG_(am_find_nsegment) (VG_(DebugInfo_get_text_avma) (tooldi))
diff --git a/coregrind/m_gdbserver/signals.c b/coregrind/m_gdbserver/signals.c
index a9128a6..ff5bfaf 100644
--- a/coregrind/m_gdbserver/signals.c
+++ b/coregrind/m_gdbserver/signals.c
@@ -486,7 +486,7 @@
}
/* Convert a OURSIG (an enum target_signal) to the form used by the
- target operating system (refered to as the ``host'') or zero if the
+ target operating system (referred to as the ``host'') or zero if the
equivalent host signal is not available. Set/clear OURSIG_OK
accordingly. */
diff --git a/coregrind/m_gdbserver/target.c b/coregrind/m_gdbserver/target.c
index 488730a..10e52fc 100644
--- a/coregrind/m_gdbserver/target.c
+++ b/coregrind/m_gdbserver/target.c
@@ -716,9 +716,48 @@
// Check we can access the dtv entry for modid
CHECK_DEREF(dtv + 2 * modid, sizeof(CORE_ADDR), "dtv[2*modid]");
- // And finally compute the address of the tls variable.
- *tls_addr = *(dtv + 2 * modid) + offset;
-
+ // Compute the base address of the tls block.
+ *tls_addr = *(dtv + 2 * modid);
+
+#if defined(VGA_mips32) || defined(VGA_mips64)
+ if (*tls_addr & 1) {
+ /* This means that computed address is not valid, most probably
+ because given module uses Static TLS.
+ However, the best we can is to try to compute address using
+ static TLS. This is what libthread_db does.
+ Ref. GLIBC/nptl_db/td_thr_tlsbase.c:td_thr_tlsbase().
+ */
+
+ CORE_ADDR tls_offset_addr;
+ PtrdiffT tls_offset;
+
+ dlog(1, "computing tls_addr using static TLS\n");
+
+ /* Assumes that tls_offset is placed right before tls_modid.
+ To check the assumption, start a gdb on none/tests/tls and do:
+ p &((struct link_map*)0x0)->l_tls_modid
+ p &((struct link_map*)0x0)->l_tls_offset */
+ tls_offset_addr = lm + lm_modid_offset - sizeof(PtrdiffT);
+
+ // Check we can read the tls_offset.
+ CHECK_DEREF(tls_offset_addr, sizeof(PtrdiffT), "link_map tls_offset");
+ tls_offset = *(PtrdiffT *)(tls_offset_addr);
+
+ /* Following two values represent platform dependent constants
+ NO_TLS_OFFSET and FORCED_DYNAMIC_TLS_OFFSET, respectively. */
+ if ((tls_offset == -1) || (tls_offset == -2)) {
+ dlog(2, "link_map tls_offset is not valid for static TLS\n");
+ return False;
+ }
+
+ // This calculation is also platform dependent.
+ *tls_addr = ((CORE_ADDR)dtv_loc + 2 * sizeof(CORE_ADDR) + tls_offset);
+ }
+#endif
+
+ // Finally, add tls variable offset to tls block base address.
+ *tls_addr += offset;
+
return True;
#undef CHECK_DEREF
@@ -842,8 +881,6 @@
mips32_init_architecture(&the_low_target);
#elif defined(VGA_mips64)
mips64_init_architecture(&the_low_target);
-#elif defined(VGA_tilegx)
- tilegx_init_architecture(&the_low_target);
#else
#error "architecture missing in target.c valgrind_initialize_target"
#endif
diff --git a/coregrind/m_gdbserver/valgrind-low-mips32.c b/coregrind/m_gdbserver/valgrind-low-mips32.c
index e44b635..300371d 100644
--- a/coregrind/m_gdbserver/valgrind-low-mips32.c
+++ b/coregrind/m_gdbserver/valgrind-low-mips32.c
@@ -356,9 +356,11 @@
static CORE_ADDR** target_get_dtv (ThreadState *tst)
{
VexGuestMIPS32State* mips32 = (VexGuestMIPS32State*)&tst->arch.vex;
- // mips32 dtv location similar to ppc64
- return (CORE_ADDR**)((CORE_ADDR)mips32->guest_ULR
- - 0x7000 - sizeof(CORE_ADDR));
+ // Top of MIPS tcbhead structure is located 0x7000 bytes before the value
+ // of ULR. Dtv is the first of two pointers in tcbhead structure.
+ // More details can be found in GLIBC/sysdeps/nptl/tls.h.
+ return (CORE_ADDR**)((CORE_ADDR)mips32->guest_ULR
+ - 0x7000 - 2 * sizeof(CORE_ADDR));
}
static struct valgrind_target_ops low_target = {
diff --git a/coregrind/m_gdbserver/valgrind-low-mips64.c b/coregrind/m_gdbserver/valgrind-low-mips64.c
index f02bef7..4aac574 100644
--- a/coregrind/m_gdbserver/valgrind-low-mips64.c
+++ b/coregrind/m_gdbserver/valgrind-low-mips64.c
@@ -357,9 +357,11 @@
static CORE_ADDR** target_get_dtv (ThreadState *tst)
{
VexGuestMIPS64State* mips64 = (VexGuestMIPS64State*)&tst->arch.vex;
- // mips64 dtv location similar to ppc64
- return (CORE_ADDR**)((CORE_ADDR)mips64->guest_ULR
- - 0x7000 - sizeof(CORE_ADDR));
+ // Top of MIPS tcbhead structure is located 0x7000 bytes before the value
+ // of ULR. Dtv is the first of two pointers in tcbhead structure.
+ // More details can be found in GLIBC/sysdeps/nptl/tls.h.
+ return (CORE_ADDR**)((CORE_ADDR)mips64->guest_ULR
+ - 0x7000 - 2 * sizeof(CORE_ADDR));
}
static struct valgrind_target_ops low_target = {
diff --git a/coregrind/m_gdbserver/valgrind-low-tilegx.c b/coregrind/m_gdbserver/valgrind-low-tilegx.c
deleted file mode 100644
index 5d58850..0000000
--- a/coregrind/m_gdbserver/valgrind-low-tilegx.c
+++ /dev/null
@@ -1,262 +0,0 @@
-/* Low level interface to valgrind, for the remote server for GDB integrated
- in valgrind.
- Copyright (C) 2012
- Free Software Foundation, Inc.
-
- This file is part of VALGRIND.
- It has been inspired from a file from gdbserver in gdb 6.6.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street, Fifth Floor,
- Boston, MA 02110-1301, USA. */
-
-#include "server.h"
-#include "target.h"
-#include "regdef.h"
-#include "regcache.h"
-
-#include "pub_core_aspacemgr.h"
-#include "pub_core_threadstate.h"
-#include "pub_core_transtab.h"
-#include "pub_core_gdbserver.h"
-
-#include "valgrind_low.h"
-
-#include "libvex_guest_tilegx.h"
-#define REG_ONE(_n) { "r"#_n, 64 * (_n), 64 }
-#define REG_ONE_NAME(_n, _name) { _name, 64 * (_n), 64 }
-
-static struct reg regs[] = {
- REG_ONE(0),
- REG_ONE(1),
- REG_ONE(2),
- REG_ONE(3),
- REG_ONE(4),
- REG_ONE(5),
- REG_ONE(6),
- REG_ONE(7),
- REG_ONE(8),
- REG_ONE(9),
-
- REG_ONE(10),
- REG_ONE(11),
- REG_ONE(12),
- REG_ONE(13),
- REG_ONE(14),
- REG_ONE(15),
- REG_ONE(16),
- REG_ONE(17),
- REG_ONE(18),
- REG_ONE(19),
-
- REG_ONE(20),
- REG_ONE(21),
- REG_ONE(22),
- REG_ONE(23),
- REG_ONE(24),
- REG_ONE(25),
- REG_ONE(26),
- REG_ONE(27),
- REG_ONE(28),
- REG_ONE(29),
-
- REG_ONE(30),
- REG_ONE(31),
- REG_ONE(32),
- REG_ONE(33),
- REG_ONE(34),
- REG_ONE(35),
- REG_ONE(36),
- REG_ONE(37),
- REG_ONE(38),
- REG_ONE(39),
-
- REG_ONE(40),
- REG_ONE(41),
- REG_ONE(42),
- REG_ONE(43),
- REG_ONE(44),
- REG_ONE(45),
- REG_ONE(46),
- REG_ONE(47),
- REG_ONE(48),
- REG_ONE(49),
-
- REG_ONE(50),
- REG_ONE(51),
- REG_ONE(52),
- REG_ONE(53),
-
- REG_ONE_NAME(54, "sp"),
- REG_ONE_NAME(55, "lr"),
- REG_ONE(56),
- REG_ONE(57),
- REG_ONE(58),
- REG_ONE(59),
-
- REG_ONE(60),
- REG_ONE(61),
- REG_ONE(62),
- REG_ONE_NAME(63, "zero"),
- REG_ONE_NAME(64, "pc"),
-};
-
-#define num_regs (sizeof (regs) / sizeof (regs[0]))
-
-static const char *expedite_regs[] = { "sp", "pc", 0 };
-
-static
-CORE_ADDR get_pc (void)
-{
- unsigned long pc;
-
- collect_register_by_name ("pc", &pc);
-
- dlog(1, "stop pc is %p\n", (void *) pc);
- return pc;
-}
-
-static
-void set_pc ( CORE_ADDR newpc )
-{
- Bool mod;
- supply_register_by_name ("pc", &newpc, &mod);
- if (mod)
- dlog(1, "set pc to %p\n", C2v (newpc));
- else
- dlog(1, "set pc not changed %p\n", C2v (newpc));
-}
-
-/* store registers in the guest state (gdbserver_to_valgrind)
- or fetch register from the guest state (valgrind_to_gdbserver). */
-static
-void transfer_register ( ThreadId tid, int abs_regno, void * buf,
- transfer_direction dir, int size, Bool *mod )
-{
- ThreadState* tst = VG_(get_ThreadState)(tid);
- int set = abs_regno / num_regs;
- int regno = abs_regno % num_regs;
- *mod = False;
-
- VexGuestTILEGXState* tilegx = (VexGuestTILEGXState*) get_arch (set, tst);
-
- switch (regno) {
- case 0: VG_(transfer) (&tilegx->guest_r0, buf, dir, size, mod); break;
- case 1: VG_(transfer) (&tilegx->guest_r1, buf, dir, size, mod); break;
- case 2: VG_(transfer) (&tilegx->guest_r2, buf, dir, size, mod); break;
- case 3: VG_(transfer) (&tilegx->guest_r3, buf, dir, size, mod); break;
- case 4: VG_(transfer) (&tilegx->guest_r4, buf, dir, size, mod); break;
- case 5: VG_(transfer) (&tilegx->guest_r5, buf, dir, size, mod); break;
- case 6: VG_(transfer) (&tilegx->guest_r6, buf, dir, size, mod); break;
- case 7: VG_(transfer) (&tilegx->guest_r7, buf, dir, size, mod); break;
- case 8: VG_(transfer) (&tilegx->guest_r8, buf, dir, size, mod); break;
- case 9: VG_(transfer) (&tilegx->guest_r9, buf, dir, size, mod); break;
- case 10: VG_(transfer) (&tilegx->guest_r10, buf, dir, size, mod); break;
- case 11: VG_(transfer) (&tilegx->guest_r11, buf, dir, size, mod); break;
- case 12: VG_(transfer) (&tilegx->guest_r12, buf, dir, size, mod); break;
- case 13: VG_(transfer) (&tilegx->guest_r13, buf, dir, size, mod); break;
- case 14: VG_(transfer) (&tilegx->guest_r14, buf, dir, size, mod); break;
- case 15: VG_(transfer) (&tilegx->guest_r15, buf, dir, size, mod); break;
- case 16: VG_(transfer) (&tilegx->guest_r16, buf, dir, size, mod); break;
- case 17: VG_(transfer) (&tilegx->guest_r17, buf, dir, size, mod); break;
- case 18: VG_(transfer) (&tilegx->guest_r18, buf, dir, size, mod); break;
- case 19: VG_(transfer) (&tilegx->guest_r19, buf, dir, size, mod); break;
- case 20: VG_(transfer) (&tilegx->guest_r20, buf, dir, size, mod); break;
- case 21: VG_(transfer) (&tilegx->guest_r21, buf, dir, size, mod); break;
- case 22: VG_(transfer) (&tilegx->guest_r22, buf, dir, size, mod); break;
- case 23: VG_(transfer) (&tilegx->guest_r23, buf, dir, size, mod); break;
- case 24: VG_(transfer) (&tilegx->guest_r24, buf, dir, size, mod); break;
- case 25: VG_(transfer) (&tilegx->guest_r25, buf, dir, size, mod); break;
- case 26: VG_(transfer) (&tilegx->guest_r26, buf, dir, size, mod); break;
- case 27: VG_(transfer) (&tilegx->guest_r27, buf, dir, size, mod); break;
- case 28: VG_(transfer) (&tilegx->guest_r28, buf, dir, size, mod); break;
- case 29: VG_(transfer) (&tilegx->guest_r29, buf, dir, size, mod); break;
- case 30: VG_(transfer) (&tilegx->guest_r30, buf, dir, size, mod); break;
- case 31: VG_(transfer) (&tilegx->guest_r31, buf, dir, size, mod); break;
- case 32: VG_(transfer) (&tilegx->guest_r32, buf, dir, size, mod); break;
- case 33: VG_(transfer) (&tilegx->guest_r33, buf, dir, size, mod); break;
- case 34: VG_(transfer) (&tilegx->guest_r34, buf, dir, size, mod); break;
- case 35: VG_(transfer) (&tilegx->guest_r35, buf, dir, size, mod); break;
- case 36: VG_(transfer) (&tilegx->guest_r36, buf, dir, size, mod); break;
- case 37: VG_(transfer) (&tilegx->guest_r37, buf, dir, size, mod); break;
- case 38: VG_(transfer) (&tilegx->guest_r38, buf, dir, size, mod); break;
- case 39: VG_(transfer) (&tilegx->guest_r39, buf, dir, size, mod); break;
- case 40: VG_(transfer) (&tilegx->guest_r40, buf, dir, size, mod); break;
- case 41: VG_(transfer) (&tilegx->guest_r41, buf, dir, size, mod); break;
- case 42: VG_(transfer) (&tilegx->guest_r42, buf, dir, size, mod); break;
- case 43: VG_(transfer) (&tilegx->guest_r43, buf, dir, size, mod); break;
- case 44: VG_(transfer) (&tilegx->guest_r44, buf, dir, size, mod); break;
- case 45: VG_(transfer) (&tilegx->guest_r45, buf, dir, size, mod); break;
- case 46: VG_(transfer) (&tilegx->guest_r46, buf, dir, size, mod); break;
- case 47: VG_(transfer) (&tilegx->guest_r47, buf, dir, size, mod); break;
- case 48: VG_(transfer) (&tilegx->guest_r48, buf, dir, size, mod); break;
- case 49: VG_(transfer) (&tilegx->guest_r49, buf, dir, size, mod); break;
- case 50: VG_(transfer) (&tilegx->guest_r50, buf, dir, size, mod); break;
- case 51: VG_(transfer) (&tilegx->guest_r51, buf, dir, size, mod); break;
- case 52: VG_(transfer) (&tilegx->guest_r52, buf, dir, size, mod); break;
- case 53: VG_(transfer) (&tilegx->guest_r53, buf, dir, size, mod); break;
- case 54: VG_(transfer) (&tilegx->guest_r54, buf, dir, size, mod); break;
- case 55: VG_(transfer) (&tilegx->guest_r55, buf, dir, size, mod); break;
- case 56: VG_(transfer) (&tilegx->guest_r56, buf, dir, size, mod); break;
- case 57: VG_(transfer) (&tilegx->guest_r57, buf, dir, size, mod); break;
- case 58: VG_(transfer) (&tilegx->guest_r58, buf, dir, size, mod); break;
- case 59: VG_(transfer) (&tilegx->guest_r59, buf, dir, size, mod); break;
- case 60: VG_(transfer) (&tilegx->guest_r60, buf, dir, size, mod); break;
- case 61: VG_(transfer) (&tilegx->guest_r61, buf, dir, size, mod); break;
- case 62: VG_(transfer) (&tilegx->guest_r62, buf, dir, size, mod); break;
- case 63: VG_(transfer) (&tilegx->guest_r63, buf, dir, size, mod); break;
- case 64: VG_(transfer) (&tilegx->guest_pc, buf, dir, size, mod); break;
-
- default: VG_(printf)("regno: %d\n", regno); vg_assert(0);
- }
-}
-
-static
-const char* target_xml ( Bool shadow_mode )
-{
- return NULL;
-#if 0
- if (shadow_mode)
- return "tilegx-linux-valgrind.xml";
- else
- return "tilegx-linux.xml";
-#endif
-}
-
-static CORE_ADDR** target_get_dtv (ThreadState *tst)
-{
- VexGuestTILEGXState* tilegx = (VexGuestTILEGXState*)&tst->arch.vex;
- // tilegx dtv location similar to mips
- return (CORE_ADDR**)((CORE_ADDR)tilegx->guest_r53
- - 0x7000 - sizeof(CORE_ADDR));
-}
-
-static struct valgrind_target_ops low_target = {
- num_regs,
- regs,
- 54, //sp = r54, which is register offset 54 in regs
- transfer_register,
- get_pc,
- set_pc,
- "tilegx",
- target_xml,
- target_get_dtv
-};
-
-void tilegx_init_architecture ( struct valgrind_target_ops *target )
-{
- *target = low_target;
- set_register_cache (regs, num_regs);
- gdbserver_expedite_regs = expedite_regs;
-}
diff --git a/coregrind/m_gdbserver/valgrind_low.h b/coregrind/m_gdbserver/valgrind_low.h
index 3a3228f..7b87856 100644
--- a/coregrind/m_gdbserver/valgrind_low.h
+++ b/coregrind/m_gdbserver/valgrind_low.h
@@ -107,6 +107,5 @@
extern void s390x_init_architecture (struct valgrind_target_ops *target);
extern void mips32_init_architecture (struct valgrind_target_ops *target);
extern void mips64_init_architecture (struct valgrind_target_ops *target);
-extern void tilegx_init_architecture (struct valgrind_target_ops *target);
#endif
diff --git a/coregrind/m_hashtable.c b/coregrind/m_hashtable.c
index 2091003..ef03298 100644
--- a/coregrind/m_hashtable.c
+++ b/coregrind/m_hashtable.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Nicholas Nethercote
+ Copyright (C) 2005-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_initimg/initimg-darwin.c b/coregrind/m_initimg/initimg-darwin.c
index 9ff1745..03402cd 100644
--- a/coregrind/m_initimg/initimg-darwin.c
+++ b/coregrind/m_initimg/initimg-darwin.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_initimg/initimg-linux.c b/coregrind/m_initimg/initimg-linux.c
index 2822f97..30e1f85 100644
--- a/coregrind/m_initimg/initimg-linux.c
+++ b/coregrind/m_initimg/initimg-linux.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -789,7 +789,8 @@
break;
# if !defined(VGP_ppc32_linux) && !defined(VGP_ppc64be_linux) \
- && !defined(VGP_ppc64le_linux)
+ && !defined(VGP_ppc64le_linux) \
+ && !defined(VGP_mips32_linux) && !defined(VGP_mips64_linux)
case AT_SYSINFO_EHDR: {
/* Trash this, because we don't reproduce it */
const NSegment* ehdrseg = VG_(am_find_nsegment)((Addr)auxv->u.a_ptr);
@@ -1198,20 +1199,6 @@
arch->vex.guest_PC = iifii.initial_client_IP;
arch->vex.guest_r31 = iifii.initial_client_SP;
-# elif defined(VGP_tilegx_linux)
- vg_assert(0 == sizeof(VexGuestTILEGXState) % LibVEX_GUEST_STATE_ALIGN);
-
- /* Zero out the initial state. */
- LibVEX_GuestTILEGX_initialise(&arch->vex);
-
- /* Zero out the shadow areas. */
- VG_(memset)(&arch->vex_shadow1, 0, sizeof(VexGuestTILEGXState));
- VG_(memset)(&arch->vex_shadow2, 0, sizeof(VexGuestTILEGXState));
-
- /* Put essential stuff into the new state. */
- arch->vex.guest_r54 = iifii.initial_client_SP;
- arch->vex.guest_pc = iifii.initial_client_IP;
-
# else
# error Unknown platform
# endif
diff --git a/coregrind/m_initimg/initimg-pathscan.c b/coregrind/m_initimg/initimg-pathscan.c
index 5b218fb..75c2292 100644
--- a/coregrind/m_initimg/initimg-pathscan.c
+++ b/coregrind/m_initimg/initimg-pathscan.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_initimg/initimg-solaris.c b/coregrind/m_initimg/initimg-solaris.c
index d3c6ebf..ce4779d 100644
--- a/coregrind/m_initimg/initimg-solaris.c
+++ b/coregrind/m_initimg/initimg-solaris.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2015 Petr Pavlu
+ Copyright (C) 2011-2017 Petr Pavlu
setup@dagobah.cz
This program is free software; you can redistribute it and/or
@@ -29,7 +29,7 @@
The GNU General Public License is contained in the file COPYING.
*/
-/* Copyright 2013-2015, Ivo Raisr <ivosh@ivosh.net>. */
+/* Copyright 2013-2017, Ivo Raisr <ivosh@ivosh.net>. */
#if defined(VGO_solaris)
diff --git a/coregrind/m_initimg/priv_initimg_pathscan.h b/coregrind/m_initimg/priv_initimg_pathscan.h
index e743836..9dd8fd9 100644
--- a/coregrind/m_initimg/priv_initimg_pathscan.h
+++ b/coregrind/m_initimg/priv_initimg_pathscan.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2006-2015 OpenWorks LLP
+ Copyright (C) 2006-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_libcassert.c b/coregrind/m_libcassert.c
index b5ce2d9..a6f3069 100644
--- a/coregrind/m_libcassert.c
+++ b/coregrind/m_libcassert.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -226,29 +226,6 @@
(srP)->misc.MIPS64.r31 = (ULong)ra; \
(srP)->misc.MIPS64.r28 = (ULong)gp; \
}
-#elif defined(VGP_tilegx_linux)
-# define GET_STARTREGS(srP) \
- { ULong pc, sp, fp, ra; \
- __asm__ __volatile__( \
- "move r8, lr \n" \
- "jal 0f \n" \
- "0:\n" \
- "move %0, lr \n" \
- "move lr, r8 \n" /* put old lr back*/ \
- "move %1, sp \n" \
- "move %2, r52 \n" \
- "move %3, lr \n" \
- : "=r" (pc), \
- "=r" (sp), \
- "=r" (fp), \
- "=r" (ra) \
- : /* reads none */ \
- : "%r8" /* trashed */ ); \
- (srP)->r_pc = (ULong)pc - 8; \
- (srP)->r_sp = (ULong)sp; \
- (srP)->misc.TILEGX.r52 = (ULong)fp; \
- (srP)->misc.TILEGX.r55 = (ULong)ra; \
- }
#else
# error Unknown platform
#endif
@@ -264,13 +241,14 @@
if (gdbserver_call_allowed && !exit_called) {
const ThreadId atid = 1; // Arbitrary tid used to call/terminate gdbsrv.
exit_called = True;
- if (status != 0 && VG_(gdbserver_stop_at) (VgdbStopAt_ValgrindAbExit)) {
+ if (status != 0
+ && VgdbStopAtiS(VgdbStopAt_ValgrindAbExit, VG_(clo_vgdb_stop_at))) {
if (VG_(gdbserver_init_done)()) {
VG_(umsg)("(action at valgrind abnormal exit) vgdb me ... \n");
VG_(gdbserver) (atid);
} else {
- VG_(umsg)("(action at valgrind abnormal exit) "
- "Early valgrind exit : vgdb not yet usable\n");
+ VG_(umsg)("(action at valgrind abnormal exit)\n"
+ "valgrind exit is too early => vgdb not yet usable\n");
}
}
if (VG_(gdbserver_init_done)()) {
@@ -317,6 +295,40 @@
exit_wrk (status, False);
}
+static void print_thread_state (Bool stack_usage,
+ const HChar* prefix, ThreadId i)
+{
+ VgStack *stack
+ = (VgStack*)VG_(threads)[i].os_state.valgrind_stack_base;
+
+ VG_(printf)("\n%sThread %d: status = %s (lwpid %d)\n", prefix, i,
+ VG_(name_of_ThreadStatus)(VG_(threads)[i].status),
+ VG_(threads)[i].os_state.lwpid);
+ if (VG_(threads)[i].status != VgTs_Empty)
+ VG_(get_and_pp_StackTrace)( i, BACKTRACE_DEPTH );
+ if (stack_usage && VG_(threads)[i].client_stack_highest_byte != 0 ) {
+ Addr start, end;
+
+ start = end = 0;
+ VG_(stack_limits)(VG_(get_SP)(i), &start, &end);
+ if (start != end)
+ VG_(printf)("%sclient stack range: [%p %p] client SP: %p\n",
+ prefix,
+ (void*)start, (void*)end, (void*)VG_(get_SP)(i));
+ else
+ VG_(printf)("%sclient stack range: ??????? client SP: %p\n",
+ prefix,
+ (void*)VG_(get_SP)(i));
+ }
+ if (stack_usage && stack != 0)
+ VG_(printf)
+ ("%svalgrind stack top usage: %lu of %lu\n",
+ prefix,
+ VG_(clo_valgrind_stacksize)
+ - VG_(am_get_VgStack_unused_szB) (stack,
+ VG_(clo_valgrind_stacksize)),
+ (SizeT) VG_(clo_valgrind_stacksize));
+}
// Print the scheduler status.
static void show_sched_status_wrk ( Bool host_stacktrace,
@@ -374,29 +386,24 @@
has exited, then valgrind_stack_base points to the stack base. */
if (VG_(threads)[i].status == VgTs_Empty
&& (!exited_threads || stack == 0)) continue;
- VG_(printf)("\nThread %d: status = %s (lwpid %d)\n", i,
- VG_(name_of_ThreadStatus)(VG_(threads)[i].status),
- VG_(threads)[i].os_state.lwpid);
- if (VG_(threads)[i].status != VgTs_Empty)
- VG_(get_and_pp_StackTrace)( i, BACKTRACE_DEPTH );
- if (stack_usage && VG_(threads)[i].client_stack_highest_byte != 0 ) {
- Addr start, end;
+ print_thread_state(stack_usage, "", i);
+ if (VG_(inner_threads) != NULL) {
+ /* An inner V has informed us (the outer) of its thread array.
+ Report the inner guest stack trace. */
+ UInt inner_tid;
- start = end = 0;
- VG_(stack_limits)(VG_(threads)[i].client_stack_highest_byte,
- &start, &end);
- if (start != end)
- VG_(printf)("client stack range: [%p %p] client SP: %p\n",
- (void*)start, (void*)end, (void*)VG_(get_SP)(i));
- else
- VG_(printf)("client stack range: ???????\n");
+ for (inner_tid = 1; inner_tid < VG_N_THREADS; inner_tid++) {
+ if (VG_(threads)[i].os_state.lwpid
+ == VG_(inner_threads)[inner_tid].os_state.lwpid) {
+ ThreadState* save_outer_vg_threads = VG_(threads);
+
+ VG_(threads) = VG_(inner_threads);
+ print_thread_state(stack_usage, "INNER ", inner_tid);
+ VG_(threads) = save_outer_vg_threads;
+ break;
+ }
+ }
}
- if (stack_usage && stack != 0)
- VG_(printf)("valgrind stack top usage: %lu of %lu\n",
- VG_(clo_valgrind_stacksize)
- - VG_(am_get_VgStack_unused_szB)
- (stack, VG_(clo_valgrind_stacksize)),
- (SizeT) VG_(clo_valgrind_stacksize));
}
}
VG_(printf)("\n");
diff --git a/coregrind/m_libcbase.c b/coregrind/m_libcbase.c
index 220247f..81ff2a4 100644
--- a/coregrind/m_libcbase.c
+++ b/coregrind/m_libcbase.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -266,6 +266,14 @@
return i;
}
+SizeT VG_(strnlen)(const HChar* str, SizeT n)
+{
+ SizeT i = 0;
+ while (i < n && str[i] != 0)
+ i++;
+ return i;
+}
+
HChar* VG_(strcat) ( HChar* dest, const HChar* src )
{
HChar* dest_orig = dest;
@@ -319,6 +327,29 @@
}
}
+/* Copies up to n-1 bytes from src to dst. Then nul-terminate dst if n > 0.
+ Returns strlen(src). Does not zero-fill the remainder of dst. */
+SizeT VG_(strlcpy)(HChar *dst, const HChar *src, SizeT n)
+{
+ const HChar *src_orig = src;
+ SizeT m = 0;
+
+ while (m < n - 1 && *src != '\0') {
+ m++;
+ *dst++ = *src++;
+ }
+
+ /* Nul-terminate dst. */ \
+ if (n > 0)
+ *dst = 0;
+
+ /* Finish counting strlen(src). */ \
+ while (*src != '\0')
+ src++;
+
+ return src - src_orig;
+}
+
Int VG_(strcmp) ( const HChar* s1, const HChar* s2 )
{
while (True) {
@@ -722,24 +753,26 @@
d++;
sz--;
}
+ UInt* d4 = ASSUME_ALIGNED(UInt*, d);
if (sz == 0)
return destV;
c4 = uc;
c4 |= (c4 << 8);
c4 |= (c4 << 16);
while (sz >= 16) {
- ((UInt*)d)[0] = c4;
- ((UInt*)d)[1] = c4;
- ((UInt*)d)[2] = c4;
- ((UInt*)d)[3] = c4;
- d += 16;
+ d4[0] = c4;
+ d4[1] = c4;
+ d4[2] = c4;
+ d4[3] = c4;
+ d4 += 4;
sz -= 16;
}
while (sz >= 4) {
- ((UInt*)d)[0] = c4;
- d += 4;
+ d4[0] = c4;
+ d4 += 1;
sz -= 4;
}
+ d = (UChar*) d4;
while (sz >= 1) {
d[0] = c;
d++;
@@ -793,7 +826,8 @@
#define BM_SWAP(a, b) \
swaptype != 0 \
? bm_swapfunc(a, b, es, swaptype) \
- : (void)BM_EXCH(*(Word*)(a), *(Word*)(b), t)
+ : (void)BM_EXCH(*ASSUME_ALIGNED(Word*, (a)), \
+ *ASSUME_ALIGNED(Word*, (b)), t)
#define BM_VECSWAP(a, b, n) \
if (n > 0) bm_swapfunc(a, b, n, swaptype)
@@ -802,7 +836,7 @@
if (swaptype != 0) \
pv = a, BM_SWAP(pv, pm); \
else \
- pv = (Char*)&v, v = *(Word*)pm
+ pv = (Char*)&v, v = *ASSUME_ALIGNED(Word*, pm)
static Char* bm_med3 ( Char* a, Char* b, Char* c,
Int (*cmp)(const void*, const void*) ) {
@@ -817,7 +851,7 @@
Word t;
for ( ; n > 0; a += sizeof(Word), b += sizeof(Word),
n -= sizeof(Word))
- BM_EXCH(*(Word*)a, *(Word*)b, t);
+ BM_EXCH(*ASSUME_ALIGNED(Word*, a), *ASSUME_ALIGNED(Word*, b), t);
} else {
Char t;
for ( ; n > 0; a += 1, b += 1, n -= 1)
diff --git a/coregrind/m_libcfile.c b/coregrind/m_libcfile.c
index 0d4cef2..c436821 100644
--- a/coregrind/m_libcfile.c
+++ b/coregrind/m_libcfile.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -138,7 +138,7 @@
SysRes VG_(mknod) ( const HChar* pathname, Int mode, UWord dev )
{
-# if defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
+# if defined(VGP_arm64_linux)
/* ARM64 wants to use __NR_mknodat rather than __NR_mknod. */
SysRes res = VG_(do_syscall4)(__NR_mknodat,
VKI_AT_FDCWD, (UWord)pathname, mode, dev);
@@ -156,7 +156,7 @@
SysRes VG_(open) ( const HChar* pathname, Int flags, Int mode )
{
-# if defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
+# if defined(VGP_arm64_linux)
/* ARM64 wants to use __NR_openat rather than __NR_open. */
SysRes res = VG_(do_syscall4)(__NR_openat,
VKI_AT_FDCWD, (UWord)pathname, flags, mode);
@@ -250,7 +250,7 @@
} else {
return -1;
}
-# elif defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
+# elif defined(VGP_arm64_linux)
SysRes res = VG_(do_syscall2)(__NR_pipe2, (UWord)fd, 0);
return sr_isError(res) ? -1 : 0;
# elif defined(VGO_linux)
@@ -360,7 +360,7 @@
# endif /* defined(__NR_stat64) */
/* This is the fallback ("vanilla version"). */
{ struct vki_stat buf;
-# if defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
+# if defined(VGP_arm64_linux)
res = VG_(do_syscall3)(__NR3264_fstatat, VKI_AT_FDCWD,
(UWord)file_name, (UWord)&buf);
# else
@@ -515,8 +515,7 @@
Int VG_(rename) ( const HChar* old_name, const HChar* new_name )
{
-# if defined(VGO_solaris) \
- || defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
+# if defined(VGO_solaris) || defined(VGP_arm64_linux)
SysRes res = VG_(do_syscall4)(__NR_renameat, VKI_AT_FDCWD, (UWord)old_name,
VKI_AT_FDCWD, (UWord)new_name);
# elif defined(VGO_linux) || defined(VGO_darwin)
@@ -529,7 +528,7 @@
Int VG_(unlink) ( const HChar* file_name )
{
-# if defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
+# if defined(VGP_arm64_linux)
SysRes res = VG_(do_syscall2)(__NR_unlinkat, VKI_AT_FDCWD,
(UWord)file_name);
# elif defined(VGO_linux) || defined(VGO_darwin)
@@ -604,7 +603,7 @@
SysRes VG_(poll) (struct vki_pollfd *fds, Int nfds, Int timeout)
{
SysRes res;
-# if defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
+# if defined(VGP_arm64_linux)
/* ARM64 wants to use __NR_ppoll rather than __NR_poll. */
struct vki_timespec timeout_ts;
if (timeout >= 0) {
@@ -647,7 +646,7 @@
{
SysRes res;
/* res = readlink( path, buf, bufsiz ); */
-# if defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
+# if defined(VGP_arm64_linux)
res = VG_(do_syscall4)(__NR_readlinkat, VKI_AT_FDCWD,
(UWord)path, (UWord)buf, bufsiz);
# elif defined(VGO_linux) || defined(VGO_darwin)
@@ -726,7 +725,7 @@
UWord w = (irusr ? VKI_R_OK : 0)
| (iwusr ? VKI_W_OK : 0)
| (ixusr ? VKI_X_OK : 0);
-# if defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
+# if defined(VGP_arm64_linux)
SysRes res = VG_(do_syscall3)(__NR_faccessat, VKI_AT_FDCWD, (UWord)path, w);
# elif defined(VGO_linux) || defined(VGO_darwin)
SysRes res = VG_(do_syscall2)(__NR_access, (UWord)path, w);
@@ -870,8 +869,7 @@
return res;
# elif defined(VGP_amd64_linux) || defined(VGP_s390x_linux) \
|| defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
- || defined(VGP_mips64_linux) \
- || defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
+ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux)
res = VG_(do_syscall4)(__NR_pread64, fd, (UWord)buf, count, offset);
return res;
# elif defined(VGP_amd64_darwin)
@@ -1126,7 +1124,7 @@
# elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \
|| defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \
- || defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
+ || defined(VGP_arm64_linux)
SysRes res;
res = VG_(do_syscall3)(__NR_socket, domain, type, protocol );
return sr_isError(res) ? -1 : sr_Res(res);
@@ -1181,7 +1179,7 @@
# elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \
|| defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \
- || defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
+ || defined(VGP_arm64_linux)
SysRes res;
res = VG_(do_syscall3)(__NR_connect, sockfd, (UWord)serv_addr, addrlen);
return sr_isError(res) ? -1 : sr_Res(res);
@@ -1228,7 +1226,7 @@
# elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \
|| defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \
- || defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
+ || defined(VGP_arm64_linux)
SysRes res;
res = VG_(do_syscall6)(__NR_sendto, sd, (UWord)msg,
count, VKI_MSG_NOSIGNAL, 0,0);
@@ -1264,8 +1262,7 @@
return sr_isError(res) ? -1 : sr_Res(res);
# elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \
- || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) \
- || defined(VGP_tilegx_linux)
+ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux)
SysRes res;
res = VG_(do_syscall3)( __NR_getsockname,
(UWord)sd, (UWord)name, (UWord)namelen );
@@ -1303,8 +1300,7 @@
return sr_isError(res) ? -1 : sr_Res(res);
# elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \
- || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) \
- || defined(VGP_tilegx_linux)
+ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux)
SysRes res;
res = VG_(do_syscall3)( __NR_getpeername,
(UWord)sd, (UWord)name, (UWord)namelen );
@@ -1345,7 +1341,7 @@
# elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \
|| defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \
- || defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
+ || defined(VGP_arm64_linux)
SysRes res;
res = VG_(do_syscall5)( __NR_getsockopt,
(UWord)sd, (UWord)level, (UWord)optname,
@@ -1389,7 +1385,7 @@
# elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \
|| defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \
- || defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
+ || defined(VGP_arm64_linux)
SysRes res;
res = VG_(do_syscall5)( __NR_setsockopt,
(UWord)sd, (UWord)level, (UWord)optname,
diff --git a/coregrind/m_libcprint.c b/coregrind/m_libcprint.c
index ce2c038..d66c67d 100644
--- a/coregrind/m_libcprint.c
+++ b/coregrind/m_libcprint.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -31,6 +31,7 @@
#include "pub_core_basics.h"
#include "pub_core_vki.h"
+#include "pub_core_vkiscnums.h"
#include "pub_core_debuglog.h"
#include "pub_core_gdbserver.h" // VG_(gdb_printf)
#include "pub_core_libcbase.h"
@@ -39,10 +40,276 @@
#include "pub_core_libcprint.h"
#include "pub_core_libcproc.h" // VG_(getpid)(), VG_(read_millisecond_timer()
#include "pub_core_mallocfree.h" // VG_(malloc)
+#include "pub_core_machine.h" // VG_(machine_get_VexArchInfo)
#include "pub_core_options.h"
#include "pub_core_clreq.h" // For RUNNING_ON_VALGRIND
+#include "pub_core_clientstate.h"
+#include "pub_core_syscall.h" // VG_(strerror)
+#include "pub_core_tooliface.h" // VG_(details)
+/*====================================================================*/
+/*=== Printing the preamble ===*/
+/*====================================================================*/
+
+// Print the argument, escaping any chars that require it.
+static void umsg_arg(const HChar *arg)
+{
+ SizeT len = VG_(strlen)(arg);
+ const HChar *special = " \\<>";
+ for (UInt i = 0; i < len; i++) {
+ if (VG_(strchr)(special, arg[i])) {
+ VG_(umsg)("\\"); // escape with a backslash if necessary
+ }
+ VG_(umsg)("%c", arg[i]);
+ }
+}
+
+// Send output to the XML-stream and escape any XML meta-characters.
+static void xml_arg(const HChar *arg)
+{
+ VG_(printf_xml)("%pS", arg);
+}
+
+// Write the name and value of log file qualifiers to the xml file.
+// We can safely assume here that the format string is well-formed.
+// It has been checked earlier in VG_(expand_file_name) when processing
+// command line options.
+static void print_file_vars(const HChar *format)
+{
+ UInt i = 0;
+
+ while (format[i]) {
+ if (format[i] == '%') {
+ // We saw a '%'. What's next...
+ i++;
+ if ('q' == format[i]) {
+ i++;
+ if ('{' == format[i]) {
+ // Get the env var name, print its contents.
+ UInt begin_qualname = ++i;
+ while (True) {
+ if ('}' == format[i]) {
+ UInt qualname_len = i - begin_qualname;
+ HChar qualname[qualname_len + 1];
+ VG_(strncpy)(qualname, format + begin_qualname,
+ qualname_len);
+ qualname[qualname_len] = '\0';
+ HChar *qual = VG_(getenv)(qualname);
+ i++;
+ VG_(printf_xml)("<logfilequalifier> <var>%pS</var> "
+ "<value>%pS</value> </logfilequalifier>\n",
+ qualname, qual);
+ break;
+ }
+ i++;
+ }
+ }
+ }
+ } else {
+ i++;
+ }
+ }
+}
+
+/* Ok, the logging sink is running now. Print a suitable preamble.
+ If logging to file or a socket, write details of parent PID and
+ command line args, to help people trying to interpret the
+ results of a run which encompasses multiple processes. */
+void VG_(print_preamble)(Bool logging_to_fd)
+{
+ const HChar *xpre = VG_(clo_xml) ? " <line>" : "";
+ const HChar *xpost = VG_(clo_xml) ? "</line>" : "";
+ UInt (*umsg_or_xml)( const HChar *, ... )
+ = VG_(clo_xml) ? VG_(printf_xml) : VG_(umsg);
+ void (*umsg_or_xml_arg)( const HChar *) = VG_(clo_xml) ? xml_arg : umsg_arg;
+
+ vg_assert( VG_(args_for_client) );
+ vg_assert( VG_(args_for_valgrind) );
+ vg_assert( VG_(clo_toolname) );
+
+ if (VG_(clo_xml)) {
+ VG_(printf_xml)("<?xml version=\"1.0\"?>\n");
+ VG_(printf_xml)("\n");
+ VG_(printf_xml)("<valgrindoutput>\n");
+ VG_(printf_xml)("\n");
+ VG_(printf_xml)("<protocolversion>4</protocolversion>\n");
+ VG_(printf_xml)("<protocoltool>%s</protocoltool>\n", VG_(clo_toolname));
+ VG_(printf_xml)("\n");
+ }
+
+ if (VG_(clo_xml) || VG_(clo_verbosity) > 0) {
+
+ if (VG_(clo_xml))
+ VG_(printf_xml)("<preamble>\n");
+
+ /* Tool details */
+ umsg_or_xml(VG_(clo_xml) ? "%s%pS%pS%pS, %pS%s\n" : "%s%s%s%s, %s%s\n",
+ xpre,
+ VG_(details).name,
+ NULL == VG_(details).version ? "" : "-",
+ NULL == VG_(details).version ? "" : VG_(details).version,
+ VG_(details).description,
+ xpost);
+
+ if (VG_(strlen)(VG_(clo_toolname)) >= 4 &&
+ VG_STREQN(4, VG_(clo_toolname), "exp-")) {
+ umsg_or_xml("%sNOTE: This is an Experimental-Class Valgrind Tool%s\n",
+ xpre, xpost);
+ }
+
+ umsg_or_xml(VG_(clo_xml) ? "%s%pS%s\n" : "%s%s%s\n",
+ xpre, VG_(details).copyright_author, xpost);
+
+ /* Core details */
+ umsg_or_xml(
+ "%sUsing Valgrind-%s and LibVEX; rerun with -h for copyright info%s\n",
+ xpre, VERSION, xpost);
+
+ // Print the command line. At one point we wrapped at 80 chars and
+ // printed a '\' as a line joiner, but that makes it hard to cut and
+ // paste the command line (because of the "==pid==" prefixes), so we now
+ // favour utility and simplicity over aesthetics.
+ umsg_or_xml("%sCommand: ", xpre);
+ umsg_or_xml_arg(VG_(args_the_exename));
+
+ for (UInt i = 0; i < VG_(sizeXA)( VG_(args_for_client)); i++) {
+ HChar *s = *(HChar **)VG_(indexXA)( VG_(args_for_client), i);
+ umsg_or_xml(" ");
+ umsg_or_xml_arg(s);
+ }
+ umsg_or_xml("%s\n", xpost);
+
+ if (VG_(clo_xml))
+ VG_(printf_xml)("</preamble>\n");
+ }
+
+ // Print the parent PID, and other stuff, if necessary.
+ if (!VG_(clo_xml) && VG_(clo_verbosity) > 0 && !logging_to_fd) {
+ VG_(umsg)("Parent PID: %d\n", VG_(getppid)());
+ } else if (VG_(clo_xml)) {
+ VG_(printf_xml)("\n");
+ VG_(printf_xml)("<pid>%d</pid>\n", VG_(getpid)());
+ VG_(printf_xml)("<ppid>%d</ppid>\n", VG_(getppid)());
+ VG_(printf_xml)("<tool>%pS</tool>\n", VG_(clo_toolname));
+ if (VG_(clo_xml_fname_unexpanded) != NULL)
+ print_file_vars(VG_(clo_xml_fname_unexpanded));
+ if (VG_(clo_xml_user_comment)) {
+ /* Note: the user comment itself is XML and is therefore to
+ be passed through verbatim (%s) rather than escaped (%pS). */
+ VG_(printf_xml)("<usercomment>%s</usercomment>\n",
+ VG_(clo_xml_user_comment));
+ }
+ VG_(printf_xml)("\n");
+ VG_(printf_xml)("<args>\n");
+
+ VG_(printf_xml)(" <vargv>\n");
+ if (VG_(name_of_launcher))
+ VG_(printf_xml)(" <exe>%pS</exe>\n", VG_(name_of_launcher));
+ else
+ VG_(printf_xml)(" <exe>%pS</exe>\n", "(launcher name unknown)");
+ for (UInt i = 0; i < VG_(sizeXA)( VG_(args_for_valgrind) ); i++) {
+ VG_(printf_xml)(
+ " <arg>%pS</arg>\n",
+ *(HChar **) VG_(indexXA)( VG_(args_for_valgrind), i));
+ }
+ VG_(printf_xml)(" </vargv>\n");
+
+ VG_(printf_xml)(" <argv>\n");
+ VG_(printf_xml)(" <exe>%pS</exe>\n", VG_(args_the_exename));
+ for (UInt i = 0; i < VG_(sizeXA)( VG_(args_for_client) ); i++) {
+ VG_(printf_xml)(
+ " <arg>%pS</arg>\n",
+ *(HChar **) VG_(indexXA)( VG_(args_for_client), i));
+ }
+ VG_(printf_xml)(" </argv>\n");
+
+ VG_(printf_xml)("</args>\n");
+ }
+
+ // Last thing in the preamble is a blank line.
+ if (VG_(clo_xml))
+ VG_(printf_xml)("\n");
+ else if (VG_(clo_verbosity) > 0)
+ VG_(umsg)("\n");
+
+ if (VG_(clo_verbosity) > 1) {
+# if defined(VGO_linux)
+ SysRes fd;
+# endif
+ VexArch vex_arch;
+ VexArchInfo vex_archinfo;
+ if (!logging_to_fd)
+ VG_(message)(Vg_DebugMsg, "\n");
+ VG_(message)(Vg_DebugMsg, "Valgrind options:\n");
+ for (UInt i = 0; i < VG_(sizeXA)( VG_(args_for_valgrind) ); i++) {
+ VG_(message)(Vg_DebugMsg,
+ " %s\n",
+ *(HChar **) VG_(indexXA)( VG_(args_for_valgrind), i));
+ }
+
+# if defined(VGO_linux)
+ VG_(message)(Vg_DebugMsg, "Contents of /proc/version:\n");
+ fd = VG_(open)("/proc/version", VKI_O_RDONLY, 0);
+ if (sr_isError(fd)) {
+ VG_(message)(Vg_DebugMsg, " can't open /proc/version\n");
+ } else {
+ const SizeT bufsiz = 255;
+ HChar version_buf[bufsiz+1];
+ VG_(message)(Vg_DebugMsg, " ");
+ Int n, fdno = sr_Res(fd);
+ do {
+ n = VG_(read)(fdno, version_buf, bufsiz);
+ if (n < 0) {
+ VG_(message)(Vg_DebugMsg, " error reading /proc/version\n");
+ break;
+ }
+ version_buf[n] = '\0';
+ VG_(message)(Vg_DebugMsg, "%s", version_buf);
+ } while (n == bufsiz);
+ VG_(message)(Vg_DebugMsg, "\n");
+ VG_(close)(fdno);
+ }
+# elif defined(VGO_darwin)
+ VG_(message)(Vg_DebugMsg, "Output from sysctl({CTL_KERN,KERN_VERSION}):\n");
+ /* Note: preferable to use sysctlbyname("kern.version", kernelVersion, &len, NULL, 0)
+ however that syscall is OS X 10.10+ only. */
+ Int mib[] = {CTL_KERN, KERN_VERSION};
+ SizeT len;
+ VG_(sysctl)(mib, sizeof(mib)/sizeof(Int), NULL, &len, NULL, 0);
+ HChar *kernelVersion = VG_(malloc)("main.pp.1", len);
+ VG_(sysctl)(mib, sizeof(mib)/sizeof(Int), kernelVersion, &len, NULL, 0);
+ VG_(message)(Vg_DebugMsg, " %s\n", kernelVersion);
+ VG_(free)( kernelVersion );
+# elif defined(VGO_solaris)
+ /* There is no /proc/version file on Solaris so we try to get some
+ system information using the uname(2) syscall. */
+ struct vki_utsname uts;
+ VG_(message)(Vg_DebugMsg, "System information:\n");
+ SysRes res = VG_(do_syscall1)(__NR_uname, (UWord)&uts);
+ if (sr_isError(res))
+ VG_(message)(Vg_DebugMsg, " uname() failed\n");
+ else
+ VG_(message)(Vg_DebugMsg, " %s %s %s %s\n",
+ uts.sysname, uts.release, uts.version, uts.machine);
+# endif
+
+ VG_(machine_get_VexArchInfo)(&vex_arch, &vex_archinfo);
+ VG_(message)(
+ Vg_DebugMsg,
+ "Arch and hwcaps: %s, %s, %s\n",
+ LibVEX_ppVexArch ( vex_arch ),
+ LibVEX_ppVexEndness ( vex_archinfo.endness ),
+ LibVEX_ppVexHwCaps ( vex_arch, vex_archinfo.hwcaps )
+ );
+ VG_(message)(Vg_DebugMsg,
+ "Page sizes: currently %u, max supported %u\n",
+ (UInt) VKI_PAGE_SIZE, (UInt) VKI_MAX_PAGE_SIZE);
+ VG_(message)(Vg_DebugMsg,
+ "Valgrind library directory: %s\n", VG_(libdir));
+ }
+}
+
/* ---------------------------------------------------------------------
Writing to file or a socket
------------------------------------------------------------------ */
@@ -54,19 +321,260 @@
After startup, the gdbserver monitor command might temporarily
set the fd of log_output_sink to -2 to indicate that output is
to be given to gdb rather than output to the startup fd */
-OutputSink VG_(log_output_sink) = { 2, False }; /* 2 = stderr */
-OutputSink VG_(xml_output_sink) = { -1, False }; /* disabled */
-
+OutputSink VG_(log_output_sink) = { 2, VgLogTo_Fd, NULL }; /* 2 = stderr */
+OutputSink VG_(xml_output_sink) = { -1, VgLogTo_Fd, NULL }; /* disabled */
+
+static void revert_sink_to_stderr ( OutputSink *sink )
+{
+ sink->fd = 2; /* stderr */
+ sink->type = VgLogTo_Fd;
+ VG_(free)(sink->fsname_expanded);
+ sink->fsname_expanded = NULL;
+}
+
+static Int prepare_sink_fd(const HChar *clo_fname_unexpanded, OutputSink *sink,
+ Bool is_xml)
+{
+ vg_assert(clo_fname_unexpanded != NULL);
+ vg_assert(VG_(strlen)(clo_fname_unexpanded) <= 900); /* paranoia */
+
+ // Nb: we overwrite an existing file of this name without asking
+ // any questions.
+ HChar *logfilename = VG_(expand_file_name)(
+ (is_xml) ? "--xml-file" : "--log-file",
+ clo_fname_unexpanded);
+ SysRes sres = VG_(open)(logfilename,
+ VKI_O_CREAT|VKI_O_WRONLY|VKI_O_TRUNC,
+ VKI_S_IRUSR|VKI_S_IWUSR|VKI_S_IRGRP|VKI_S_IROTH);
+ if (!sr_isError(sres)) {
+ Int fd = sr_Res(sres);
+ sink->fsname_expanded = logfilename;
+ sink->type = VgLogTo_File;
+ return fd;
+ } else {
+ VG_(fmsg)("Cannot create %s file '%s': %s\n",
+ (is_xml) ? "XML" : "log", logfilename,
+ VG_(strerror)(sr_Err(sres)));
+ VG_(exit)(1);
+ /*NOTREACHED*/
+ }
+}
+
+static Int prepare_sink_socket(const HChar *clo_fname_unexpanded,
+ OutputSink *sink, Bool is_xml)
+{
+ vg_assert(clo_fname_unexpanded != NULL);
+ vg_assert(VG_(strlen)(clo_fname_unexpanded) <= 900); /* paranoia */
+
+ Int fd = VG_(connect_via_socket)(clo_fname_unexpanded);
+ if (fd == -1) {
+ VG_(fmsg)("Invalid %s spec of '%s'\n",
+ (is_xml) ? "--xml-socket" : "--log-socket",
+ clo_fname_unexpanded);
+ VG_(exit)(1);
+ /*NOTREACHED*/
+ }
+ if (fd == -2) {
+ VG_(umsg)("Failed to connect to %slogging server '%s'.\n"
+ "%s will be sent to stderr instead.\n",
+ (is_xml) ? "XML " : "",
+ clo_fname_unexpanded,
+ (is_xml) ? "XML output" : "Logging messages");
+ /* We don't change anything here. */
+ vg_assert(sink->fd == 2);
+ vg_assert(sink->type == VgLogTo_Fd);
+ return 2;
+ } else {
+ vg_assert(fd > 0);
+ sink->type = VgLogTo_Socket;
+ return fd;
+ }
+}
+
+static void finalize_sink_fd(OutputSink *sink, Int new_fd, Bool is_xml)
+{
+ // Move new_fd into the safe range, so it doesn't conflict with any app fds.
+ Int safe_fd = VG_(fcntl)(new_fd, VKI_F_DUPFD, VG_(fd_hard_limit));
+ if (safe_fd < 0) {
+ VG_(message)(Vg_UserMsg, "Valgrind: failed to move %s file descriptor "
+ "into safe range, using stderr\n",
+ (is_xml) ? "XML" : "log");
+ revert_sink_to_stderr(sink);
+ } else {
+ VG_(fcntl)(safe_fd, VKI_F_SETFD, VKI_FD_CLOEXEC);
+ sink->fd = safe_fd;
+ }
+}
+
+/* Re-opens an output file sink when exanded file name differs from what we
+ have now. Returns 'True' if the sink was reopened */
+static Bool reopen_sink_if_needed(const HChar *clo_fname_unexpanded,
+ OutputSink *sink, Bool is_xml)
+{
+ if (sink->type == VgLogTo_File) {
+ /* Try to expand --log|xml-file again and see if it differs from what
+ we have now. */
+ HChar *logfilename = VG_(expand_file_name)(
+ (is_xml) ? "--xml-file" : "--log-file",
+ clo_fname_unexpanded);
+ if (VG_(strcmp)(logfilename, sink->fsname_expanded) != 0) {
+ Int fd = prepare_sink_fd(clo_fname_unexpanded, sink, is_xml);
+ finalize_sink_fd(sink, fd, is_xml);
+ return True;
+ }
+ VG_(free)(logfilename);
+ }
+
+ return False;
+}
+
+void VG_(logging_atfork_child)(ThreadId tid)
+{
+ /* If --child-silent-after-fork=yes was specified, set the output file
+ descriptors to 'impossible' values. This is noticed by
+ send_bytes_to_logging_sink(), which duly stops writing any further
+ output. */
+ if (VG_(clo_child_silent_after_fork)) {
+ if (VG_(log_output_sink).type != VgLogTo_Socket) {
+ VG_(log_output_sink).fd = -1;
+ VG_(log_output_sink).type = VgLogTo_Fd;
+ }
+ if (VG_(xml_output_sink).type != VgLogTo_Socket) {
+ VG_(xml_output_sink).fd = -1;
+ VG_(xml_output_sink).type = VgLogTo_Fd;
+ }
+ } else {
+ if (reopen_sink_if_needed(VG_(clo_log_fname_unexpanded),
+ &VG_(log_output_sink), False) ||
+ reopen_sink_if_needed(VG_(clo_xml_fname_unexpanded),
+ &VG_(xml_output_sink), True)) {
+ VG_(print_preamble)(VG_(log_output_sink).type != VgLogTo_File);
+ }
+ }
+}
+
+/* Initializes normal log and xml sinks (of type fd, file, or socket).
+ Any problem encountered is considered a hard error and causes V. to exit.
+
+ Comments on how the logging options are handled:
+
+ User can specify:
+ --log-fd= for a fd to write to (default setting, fd = 2)
+ --log-file= for a file name to write to
+ --log-socket= for a socket to write to
+
+ As a result of examining these and doing relevant socket/file
+ opening, a final fd is established. This is stored in
+ VG_(log_output_sink) in m_libcprint. Also, if --log-file=STR was
+ specified, then it is stored in VG_(clo_log_fname_unexpanded), in m_options.
+ And then STR, after expansion of %p and %q templates within
+ it, is stored in VG_(log_output_sink), just in case anybody wants to know
+ what it is.
+
+ When printing, VG_(log_output_sink) is consulted to find the
+ fd to send output to.
+
+ Exactly analogous actions are undertaken for the XML output
+ channel, with the one difference that the default fd is -1, meaning
+ the channel is disabled by default. */
+void VG_(init_log_xml_sinks)(VgLogTo log_to, VgLogTo xml_to,
+ Int /*initial*/log_fd, Int /*initial*/xml_fd)
+{
+ // VG_(clo_log_fd) is used by all the messaging. It starts as 2 (stderr)
+ // and we cannot change it until we know what we are changing it to is ok.
+
+ /* Start setting up logging now. After this is done, VG_(log_output_sink)
+ and (if relevant) VG_(xml_output_sink) should be connected to whatever
+ sink has been selected, and we indiscriminately chuck stuff into it
+ without worrying what the nature of it is.
+ Oh the wonder of Unix streams. */
+
+ vg_assert(VG_(log_output_sink).fd == 2 /* stderr */);
+ vg_assert(VG_(log_output_sink).type == VgLogTo_Fd);
+ vg_assert(VG_(log_output_sink).fsname_expanded == NULL);
+
+ vg_assert(VG_(xml_output_sink).fd == -1 /* disabled */);
+ vg_assert(VG_(xml_output_sink).type == VgLogTo_Fd);
+ vg_assert(VG_(xml_output_sink).fsname_expanded == NULL);
+
+ /* --- set up the normal text output channel --- */
+ switch (log_to) {
+ case VgLogTo_Fd:
+ vg_assert(VG_(clo_log_fname_unexpanded) == NULL);
+ break;
+
+ case VgLogTo_File:
+ log_fd = prepare_sink_fd(VG_(clo_log_fname_unexpanded),
+ &VG_(log_output_sink), False);
+ break;
+
+ case VgLogTo_Socket:
+ log_fd = prepare_sink_socket(VG_(clo_log_fname_unexpanded),
+ &VG_(log_output_sink), False);
+ break;
+ }
+
+ /* --- set up the XML output channel --- */
+ switch (xml_to) {
+ case VgLogTo_Fd:
+ vg_assert(VG_(clo_xml_fname_unexpanded) == NULL);
+ break;
+
+ case VgLogTo_File:
+ xml_fd = prepare_sink_fd(VG_(clo_xml_fname_unexpanded),
+ &VG_(xml_output_sink), True);
+ break;
+
+ case VgLogTo_Socket:
+ log_fd = prepare_sink_socket(VG_(clo_xml_fname_unexpanded),
+ &VG_(xml_output_sink), True);
+ break;
+ }
+
+ /* If we've got this far, and XML mode was requested, but no XML
+ output channel appears to have been specified, just stop. We
+ could continue, and XML output will simply vanish into nowhere,
+ but that is likely to confuse the hell out of users, which is
+ distinctly Ungood. */
+ if (VG_(clo_xml) && xml_fd == -1) {
+ VG_(fmsg_bad_option)(
+ "--xml=yes, but no XML destination specified",
+ "--xml=yes has been specified, but there is no XML output\n"
+ "destination. You must specify an XML output destination\n"
+ "using --xml-fd, --xml-file or --xml-socket.\n"
+ );
+ }
+
+ // Finalise the output fds: the log fd ..
+ if (log_fd >= 0) {
+ finalize_sink_fd(&VG_(log_output_sink), log_fd, False);
+ } else {
+ // If they said --log-fd=-1, don't print anything. Plausible for use in
+ // regression testing suites that use client requests to count errors.
+ VG_(log_output_sink).fd = -1;
+ VG_(log_output_sink).type = VgLogTo_Fd;
+ }
+
+ // Finalise the output fds: and the XML fd ..
+ if (xml_fd >= 0) {
+ finalize_sink_fd(&VG_(xml_output_sink), xml_fd, True);
+ } else {
+ // If they said --xml-fd=-1, don't print anything. Plausible for use in
+ // regression testing suites that use client requests to count errors.
+ VG_(xml_output_sink).fd = -1;
+ VG_(xml_output_sink).type = VgLogTo_Fd;
+ }
+}
+
/* Do the low-level send of a message to the logging sink. */
static
void send_bytes_to_logging_sink ( OutputSink* sink, const HChar* msg, Int nbytes )
{
- if (sink->is_socket) {
+ if (sink->type == VgLogTo_Socket) {
Int rc = VG_(write_socket)( sink->fd, msg, nbytes );
if (rc == -1) {
// For example, the listener process died. Switch back to stderr.
- sink->is_socket = False;
- sink->fd = 2;
+ revert_sink_to_stderr(sink);
VG_(write)( sink->fd, msg, nbytes );
}
} else {
@@ -557,8 +1065,7 @@
static void revert_to_stderr ( void )
{
- VG_(log_output_sink).fd = 2; /* stderr */
- VG_(log_output_sink).is_socket = False;
+ revert_sink_to_stderr(&VG_(log_output_sink));
}
/* VG_(message) variants with hardwired first argument. */
@@ -661,7 +1168,7 @@
return buf;
}
-#elif defined(VGO_darwin) || (VGO_solaris)
+#elif defined(VGO_darwin) || defined(VGO_solaris)
const HChar *VG_(sr_as_string) ( SysRes sr )
{
diff --git a/coregrind/m_libcproc.c b/coregrind/m_libcproc.c
index eb911be..afcc117 100644
--- a/coregrind/m_libcproc.c
+++ b/coregrind/m_libcproc.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -662,7 +662,7 @@
* the /proc/self link is pointing...
*/
-# if defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
+# if defined(VGP_arm64_linux)
res = VG_(do_syscall4)(__NR_readlinkat, VKI_AT_FDCWD,
(UWord)"/proc/self",
(UWord)pid, sizeof(pid));
@@ -787,7 +787,7 @@
if (size < 0) return -1;
# if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \
- || defined(VGP_mips64_linux) || defined(VGP_tilegx_linux)
+ || defined(VGP_mips64_linux)
Int i;
SysRes sres;
UShort list16[size];
@@ -845,7 +845,7 @@
Int VG_(fork) ( void )
{
-# if defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
+# if defined(VGP_arm64_linux)
SysRes res;
res = VG_(do_syscall5)(__NR_clone, VKI_SIGCHLD,
(UWord)NULL, (UWord)NULL, (UWord)NULL, (UWord)NULL);
@@ -951,7 +951,7 @@
if (! sr_isError(res)) return 0;
- /* Make sure, argument values are determinstic upon failure */
+ /* Make sure, argument values are deterministic upon failure */
if (tv) *tv = (struct vki_timeval){ .tv_sec = 0, .tv_usec = 0 };
if (tz) *tz = (struct vki_timezone){ .tz_minuteswest = 0, .tz_dsttime = 0 };
@@ -1186,25 +1186,6 @@
(UWord) nbytes, (UWord) 3);
vg_assert( !sr_isError(sres) );
-# elif defined(VGA_tilegx)
- const HChar *start, *end;
-
- /* L1 ICache is 32KB. cacheline size is 64 bytes. */
- if (nbytes > 0x8000) nbytes = 0x8000;
-
- start = (const HChar *)((unsigned long)ptr & -64ULL);
- end = (const HChar*)ptr + nbytes - 1;
-
- __insn_mf();
-
- do {
- const HChar* p;
- for (p = start; p <= end; p += 64)
- __insn_icoh(p);
- } while (0);
-
- __insn_drain();
-
# endif
}
@@ -1227,7 +1208,7 @@
cls = 4 * (1ULL << (0xF & (ctr_el0 >> 16)));
/* Stay sane .. */
- vg_assert(cls == 64);
+ vg_assert(cls == 64 || cls == 128);
startaddr &= ~(cls - 1);
for (addr = startaddr; addr < endaddr; addr += cls) {
diff --git a/coregrind/m_libcsetjmp.c b/coregrind/m_libcsetjmp.c
index 39d6415..68c101e 100644
--- a/coregrind/m_libcsetjmp.c
+++ b/coregrind/m_libcsetjmp.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 Mozilla Inc
+ Copyright (C) 2010-2017 Mozilla Inc
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -555,54 +555,141 @@
__asm__(
".text \n\t"
".globl VG_MINIMAL_SETJMP; \n\t"
-".align 2; \n\t"
-"VG_MINIMAL_SETJMP: \n\t" /* a0 = jmp_buf */
-" sw $s0, 0($a0) \n\t" /* Save registers s0-s7. */
-" sw $s1, 4($a0) \n\t"
-" sw $s2, 8($a0) \n\t"
-" sw $s3, 12($a0) \n\t"
-" sw $s4, 16($a0) \n\t"
-" sw $s5, 20($a0) \n\t"
-" sw $s6, 24($a0) \n\t"
-" sw $s7, 28($a0) \n\t"
-" sw $s8, 32($a0) \n\t" /* Frame pointer. */
-" sw $ra, 36($a0) \n\t" /* Return address. */
-" sw $gp, 40($a0) \n\t" /* Global data pointer. */
-" sw $sp, 44($a0) \n\t" /* Stack pointer. */
-
-" move $v0, $zero \n\t" /* Return zero. */
-" j $ra \n\t"
-" nop \n\t"
+".set push \n\t"
+".set noreorder \n\t"
+"VG_MINIMAL_SETJMP: \n\t"
+#if defined(__mips_hard_float)
+" sdc1 $f20, 56($a0) \n\t"
+" sdc1 $f22, 64($a0) \n\t"
+" sdc1 $f24, 72($a0) \n\t"
+" sdc1 $f26, 80($a0) \n\t"
+" sdc1 $f28, 88($a0) \n\t"
+" sdc1 $f30, 96($a0) \n\t"
+#endif
+" sw $gp, 44($a0) \n\t"
+" sw $s0, 8($a0) \n\t"
+" sw $s1, 12($a0) \n\t"
+" sw $s2, 16($a0) \n\t"
+" sw $s3, 20($a0) \n\t"
+" sw $s4, 24($a0) \n\t"
+" sw $s5, 28($a0) \n\t"
+" sw $s6, 32($a0) \n\t"
+" sw $s7, 36($a0) \n\t"
+" sw $ra, 0($a0) \n\t"
+" sw $sp, 4($a0) \n\t"
+" sw $fp, 40($a0) \n\t"
+" jr $ra \n\t"
+" move $v0, $zero \n\t"
+".set pop \n\t"
".previous \n\t"
" \n\t"
+".text \n\t"
".globl VG_MINIMAL_LONGJMP; \n\t"
-".align 2; \n\t"
-"VG_MINIMAL_LONGJMP: \n\t" /* a0 = jmp_buf */
-" lw $s0, 0($a0) \n\t" /* Restore registers s0-s7. */
-" lw $s1, 4($a0) \n\t"
-" lw $s2, 8($a0) \n\t"
-" lw $s3, 12($a0) \n\t"
-" lw $s4, 16($a0) \n\t"
-" lw $s5, 20($a0) \n\t"
-" lw $s6, 24($a0) \n\t"
-" lw $s7, 28($a0) \n\t"
-" lw $s8, 32($a0) \n\t" /* Frame pointer. */
-" lw $ra, 36($a0) \n\t" /* Return address. */
-" lw $gp, 40($a0) \n\t" /* Global data pointer. */
-" lw $sp, 44($a0) \n\t" /* Stack pointer. */
-
-/* Checking whether second argument is zero. */
-" bnez $a1, 1f \n\t"
-" nop \n\t"
-" addiu $a1, $a1, 1 \n\t" /* We must return 1 if val=0. */
+".set push \n\t"
+".set noreorder \n\t"
+"VG_MINIMAL_LONGJMP: \n\t"
+#if defined(__mips_hard_float)
+" ldc1 $f20, 56($a0) \n\t"
+" ldc1 $f22, 64($a0) \n\t"
+" ldc1 $f24, 72($a0) \n\t"
+" ldc1 $f26, 80($a0) \n\t"
+" ldc1 $f28, 88($a0) \n\t"
+" ldc1 $f30, 96($a0) \n\t"
+#endif
+" lw $gp, 44($a0) \n\t"
+" lw $s0, 8($a0) \n\t"
+" lw $s1, 12($a0) \n\t"
+" lw $s2, 16($a0) \n\t"
+" lw $s3, 20($a0) \n\t"
+" lw $s4, 24($a0) \n\t"
+" lw $s5, 28($a0) \n\t"
+" lw $s6, 32($a0) \n\t"
+" lw $s7, 36($a0) \n\t"
+" lw $ra, 0($a0) \n\t"
+" lw $sp, 4($a0) \n\t"
+" bnez $a1, 1f \n\t"
+" lw $fp, 40($a0) \n\t"
+" addiu $a1, $a1, 1 \n\t"
"1: \n\t"
-" move $v0, $a1 \n\t" /* Return value of second argument. */
-" j $ra \n\t"
-" nop \n\t"
+" jr $ra \n\t"
+" move $v0, $a1 \n\t"
+".set pop \n\t"
".previous \n\t"
);
#endif /* VGP_mips32_linux */
+#if defined(VGP_mips64_linux)
+
+__asm__(
+".text \n\t"
+".globl VG_MINIMAL_SETJMP; \n\t"
+".set push \n\t"
+".set noreorder \n\t"
+"VG_MINIMAL_SETJMP: \n\t"
+#if defined(__mips_hard_float)
+" sdc1 $f24, 104($a0) \n\t"
+" sdc1 $f25, 112($a0) \n\t"
+" sdc1 $f26, 120($a0) \n\t"
+" sdc1 $f27, 128($a0) \n\t"
+" sdc1 $f28, 136($a0) \n\t"
+" sdc1 $f29, 144($a0) \n\t"
+" sdc1 $f30, 152($a0) \n\t"
+" sdc1 $f31, 160($a0) \n\t"
+#endif
+" sd $gp, 88($a0) \n\t"
+" sd $s0, 16($a0) \n\t"
+" sd $s1, 24($a0) \n\t"
+" sd $s2, 32($a0) \n\t"
+" sd $s3, 40($a0) \n\t"
+" sd $s4, 48($a0) \n\t"
+" sd $s5, 56($a0) \n\t"
+" sd $s6, 64($a0) \n\t"
+" sd $s7, 72($a0) \n\t"
+" sd $ra, 0($a0) \n\t"
+" sd $sp, 8($a0) \n\t"
+" sd $fp, 80($a0) \n\t"
+" jr $ra \n\t"
+" move $v0, $zero \n\t"
+".set pop \n\t"
+".previous \n\t"
+" \n\t"
+".text \n\t"
+".globl VG_MINIMAL_LONGJMP; \n\t"
+".set push \n\t"
+".set noreorder \n\t"
+"VG_MINIMAL_LONGJMP: \n\t"
+#if defined(__mips_hard_float)
+" ldc1 $f24, 104($a0) \n\t"
+" ldc1 $f25, 112($a0) \n\t"
+" ldc1 $f26, 120($a0) \n\t"
+" ldc1 $f27, 128($a0) \n\t"
+" ldc1 $f28, 136($a0) \n\t"
+" ldc1 $f29, 144($a0) \n\t"
+" ldc1 $f30, 152($a0) \n\t"
+" ldc1 $f31, 160($a0) \n\t"
+#endif
+" ld $gp, 88($a0) \n\t"
+" ld $s0, 16($a0) \n\t"
+" ld $s1, 24($a0) \n\t"
+" ld $s2, 32($a0) \n\t"
+" ld $s3, 40($a0) \n\t"
+" ld $s4, 48($a0) \n\t"
+" ld $s5, 56($a0) \n\t"
+" ld $s6, 64($a0) \n\t"
+" ld $s7, 72($a0) \n\t"
+" ld $ra, 0($a0) \n\t"
+" ld $sp, 8($a0) \n\t"
+" bnez $a1, 1f \n\t"
+" ld $fp, 80($a0) \n\t"
+" daddiu $a1, $a1, 1 \n\t"
+"1: \n\t"
+" jr $ra \n\t"
+" move $v0, $a1 \n\t"
+".set pop \n\t"
+".previous \n\t"
+);
+#endif /* VGP_mips64_linux */
+
/*--------------------------------------------------------------------*/
/*--- end ---*/
/*--------------------------------------------------------------------*/
diff --git a/coregrind/m_libcsignal.c b/coregrind/m_libcsignal.c
index 557e219..d5e5f4f 100644
--- a/coregrind/m_libcsignal.c
+++ b/coregrind/m_libcsignal.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -275,7 +275,7 @@
whatever we were provided with. This is OK because all the
sigaction requests come from m_signals, and are not directly
what the client program requested, so there is no chance that we
- will inadvertantly ignore the sa_tramp field requested by the
+ will inadvertently ignore the sa_tramp field requested by the
client. (In fact m_signals does ignore it when building signal
frames for the client, but that's a completely different
matter).
diff --git a/coregrind/m_mach/mach_basics.c b/coregrind/m_mach/mach_basics.c
index 034511c..babcd65 100644
--- a/coregrind/m_mach/mach_basics.c
+++ b/coregrind/m_mach/mach_basics.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Apple Inc.
+ Copyright (C) 2005-2017 Apple Inc.
Greg Parker gparker@apple.com
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_mach/mach_traps-amd64-darwin.S b/coregrind/m_mach/mach_traps-amd64-darwin.S
index e5b393c..101e89c 100644
--- a/coregrind/m_mach/mach_traps-amd64-darwin.S
+++ b/coregrind/m_mach/mach_traps-amd64-darwin.S
@@ -6,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2007-2015 Apple Inc.
+ Copyright (C) 2007-2017 Apple Inc.
Greg Parker gparker@apple.com
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_mach/mach_traps-x86-darwin.S b/coregrind/m_mach/mach_traps-x86-darwin.S
index 5564060..b1567e2 100644
--- a/coregrind/m_mach/mach_traps-x86-darwin.S
+++ b/coregrind/m_mach/mach_traps-x86-darwin.S
@@ -6,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2006-2015 Apple Inc.
+ Copyright (C) 2006-2017 Apple Inc.
Greg Parker gparker@apple.com
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c
index 4fdfe93..893c32e 100644
--- a/coregrind/m_machine.c
+++ b/coregrind/m_machine.c
@@ -6,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -34,6 +34,7 @@
#include "pub_core_libcbase.h"
#include "pub_core_libcfile.h"
#include "pub_core_libcprint.h"
+#include "pub_core_libcproc.h"
#include "pub_core_mallocfree.h"
#include "pub_core_machine.h"
#include "pub_core_cpuid.h"
@@ -126,13 +127,6 @@
= VG_(threads)[tid].arch.vex.guest_r31;
regs->misc.MIPS64.r28
= VG_(threads)[tid].arch.vex.guest_r28;
-# elif defined(VGA_tilegx)
- regs->r_pc = VG_(threads)[tid].arch.vex.guest_pc;
- regs->r_sp = VG_(threads)[tid].arch.vex.guest_r54;
- regs->misc.TILEGX.r52
- = VG_(threads)[tid].arch.vex.guest_r52;
- regs->misc.TILEGX.r55
- = VG_(threads)[tid].arch.vex.guest_r55;
# else
# error "Unknown arch"
# endif
@@ -350,63 +344,6 @@
(*f)(tid, "x28", vex->guest_X28);
(*f)(tid, "x29", vex->guest_X29);
(*f)(tid, "x30", vex->guest_X30);
-#elif defined(VGA_tilegx)
- (*f)(tid, "r0", vex->guest_r0 );
- (*f)(tid, "r1", vex->guest_r1 );
- (*f)(tid, "r2", vex->guest_r2 );
- (*f)(tid, "r3", vex->guest_r3 );
- (*f)(tid, "r4", vex->guest_r4 );
- (*f)(tid, "r5", vex->guest_r5 );
- (*f)(tid, "r6", vex->guest_r6 );
- (*f)(tid, "r7", vex->guest_r7 );
- (*f)(tid, "r8", vex->guest_r8 );
- (*f)(tid, "r9", vex->guest_r9 );
- (*f)(tid, "r10", vex->guest_r10);
- (*f)(tid, "r11", vex->guest_r11);
- (*f)(tid, "r12", vex->guest_r12);
- (*f)(tid, "r13", vex->guest_r13);
- (*f)(tid, "r14", vex->guest_r14);
- (*f)(tid, "r15", vex->guest_r15);
- (*f)(tid, "r16", vex->guest_r16);
- (*f)(tid, "r17", vex->guest_r17);
- (*f)(tid, "r18", vex->guest_r18);
- (*f)(tid, "r19", vex->guest_r19);
- (*f)(tid, "r20", vex->guest_r20);
- (*f)(tid, "r21", vex->guest_r21);
- (*f)(tid, "r22", vex->guest_r22);
- (*f)(tid, "r23", vex->guest_r23);
- (*f)(tid, "r24", vex->guest_r24);
- (*f)(tid, "r25", vex->guest_r25);
- (*f)(tid, "r26", vex->guest_r26);
- (*f)(tid, "r27", vex->guest_r27);
- (*f)(tid, "r28", vex->guest_r28);
- (*f)(tid, "r29", vex->guest_r29);
- (*f)(tid, "r30", vex->guest_r30);
- (*f)(tid, "r31", vex->guest_r31);
- (*f)(tid, "r32", vex->guest_r32);
- (*f)(tid, "r33", vex->guest_r33);
- (*f)(tid, "r34", vex->guest_r34);
- (*f)(tid, "r35", vex->guest_r35);
- (*f)(tid, "r36", vex->guest_r36);
- (*f)(tid, "r37", vex->guest_r37);
- (*f)(tid, "r38", vex->guest_r38);
- (*f)(tid, "r39", vex->guest_r39);
- (*f)(tid, "r40", vex->guest_r40);
- (*f)(tid, "r41", vex->guest_r41);
- (*f)(tid, "r42", vex->guest_r42);
- (*f)(tid, "r43", vex->guest_r43);
- (*f)(tid, "r44", vex->guest_r44);
- (*f)(tid, "r45", vex->guest_r45);
- (*f)(tid, "r46", vex->guest_r46);
- (*f)(tid, "r47", vex->guest_r47);
- (*f)(tid, "r48", vex->guest_r48);
- (*f)(tid, "r49", vex->guest_r49);
- (*f)(tid, "r50", vex->guest_r50);
- (*f)(tid, "r51", vex->guest_r51);
- (*f)(tid, "r52", vex->guest_r52);
- (*f)(tid, "r53", vex->guest_r53);
- (*f)(tid, "r54", vex->guest_r54);
- (*f)(tid, "r55", vex->guest_r55);
#else
# error Unknown arch
#endif
@@ -697,7 +634,7 @@
return model;
}
-#endif /* VGA_s390x */
+#endif /* defined(VGA_s390x) */
#if defined(VGA_mips32) || defined(VGA_mips64)
@@ -789,6 +726,18 @@
vai.hwcaps |= VEX_MIPS_CPU_ISA_M64R2;
if (VG_(strstr) (isa, "mips64r6") != NULL)
vai.hwcaps |= VEX_MIPS_CPU_ISA_M64R6;
+
+ /*
+ * TODO(petarj): Remove this Cavium workaround once Linux kernel folks
+ * decide to change incorrect settings in
+ * mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h.
+ * The current settings show mips32r1, mips32r2 and mips64r1 as
+ * unsupported ISAs by Cavium MIPS CPUs.
+ */
+ if (VEX_MIPS_COMP_ID(vai.hwcaps) == VEX_PRID_COMP_CAVIUM) {
+ vai.hwcaps |= VEX_MIPS_CPU_ISA_M32R1 | VEX_MIPS_CPU_ISA_M32R2 |
+ VEX_MIPS_CPU_ISA_M64R1;
+ }
} else {
/*
* Kernel does not provide information about supported ISAs.
@@ -818,12 +767,65 @@
return True;
}
-#endif
+#endif /* defined(VGA_mips32) || defined(VGA_mips64) */
-/* Determine what insn set and insn set variant the host has, and
- record it. To be called once at system startup. Returns False if
- this a CPU incapable of running Valgrind.
- Also determine information about the caches on this host. */
+#if defined(VGP_arm64_linux)
+
+/* Check to see whether we are running on a Cavium core, and if so auto-enable
+ the fallback LLSC implementation. See #369459. */
+
+static Bool VG_(parse_cpuinfo)(void)
+{
+ const char *search_Cavium_str = "CPU implementer\t: 0x43";
+
+ Int n, fh;
+ SysRes fd;
+ SizeT num_bytes, file_buf_size;
+ HChar *file_buf;
+
+ /* Slurp contents of /proc/cpuinfo into FILE_BUF */
+ fd = VG_(open)( "/proc/cpuinfo", 0, VKI_S_IRUSR );
+ if ( sr_isError(fd) ) return False;
+
+ fh = sr_Res(fd);
+
+ /* Determine the size of /proc/cpuinfo.
+ Work around broken-ness in /proc file system implementation.
+ fstat returns a zero size for /proc/cpuinfo although it is
+ claimed to be a regular file. */
+ num_bytes = 0;
+ file_buf_size = 1000;
+ file_buf = VG_(malloc)("cpuinfo", file_buf_size + 1);
+ while (42) {
+ n = VG_(read)(fh, file_buf, file_buf_size);
+ if (n < 0) break;
+
+ num_bytes += n;
+ if (n < file_buf_size) break; /* reached EOF */
+ }
+
+ if (n < 0) num_bytes = 0; /* read error; ignore contents */
+
+ if (num_bytes > file_buf_size) {
+ VG_(free)( file_buf );
+ VG_(lseek)( fh, 0, VKI_SEEK_SET );
+ file_buf = VG_(malloc)( "cpuinfo", num_bytes + 1 );
+ n = VG_(read)( fh, file_buf, num_bytes );
+ if (n < 0) num_bytes = 0;
+ }
+
+ file_buf[num_bytes] = '\0';
+ VG_(close)(fh);
+
+ /* Parse file */
+ if (VG_(strstr)(file_buf, search_Cavium_str) != NULL)
+ vai.arm64_requires_fallback_LLSC = True;
+
+ VG_(free)(file_buf);
+ return True;
+}
+
+#endif /* defined(VGP_arm64_linux) */
Bool VG_(machine_get_hwcaps)( void )
{
@@ -1651,6 +1653,11 @@
VG_(machine_get_cache_info)(&vai);
+ /* Check whether we need to use the fallback LLSC implementation.
+ If the check fails, give up. */
+ if (! VG_(parse_cpuinfo)())
+ return False;
+
/* 0 denotes 'not set'. The range of legitimate values here,
after being set that is, is 2 though 17 inclusive. */
vg_assert(vai.arm64_dMinLine_lg2_szB == 0);
@@ -1663,6 +1670,8 @@
"ctr_el0.iMinLine_szB = %d\n",
1 << vai.arm64_dMinLine_lg2_szB,
1 << vai.arm64_iMinLine_lg2_szB);
+ VG_(debugLog)(1, "machine", "ARM64: requires_fallback_LLSC: %s\n",
+ vai.arm64_requires_fallback_LLSC ? "yes" : "no");
return True;
}
@@ -1739,7 +1748,7 @@
}
# if defined(VGP_mips32_linux)
- Int fpmode = VG_(prctl)(VKI_PR_GET_FP_MODE);
+ Int fpmode = VG_(prctl)(VKI_PR_GET_FP_MODE, 0, 0, 0, 0);
# else
Int fpmode = -1;
# endif
@@ -1802,17 +1811,6 @@
return True;
}
-#elif defined(VGA_tilegx)
- {
- va = VexArchTILEGX;
- vai.hwcaps = VEX_HWCAPS_TILEGX_BASE;
- vai.endness = VexEndnessLE;
-
- VG_(machine_get_cache_info)(&vai);
-
- return True;
- }
-
#else
# error "Unknown arch"
#endif
@@ -1946,9 +1944,6 @@
# elif defined(VGA_mips64)
return 8;
-# elif defined(VGA_tilegx)
- return 8;
-
# else
# error "Unknown arch"
# endif
@@ -1964,8 +1959,7 @@
|| defined(VGP_ppc32_linux) || defined(VGP_ppc64le_linux) \
|| defined(VGP_s390x_linux) || defined(VGP_mips32_linux) \
|| defined(VGP_mips64_linux) || defined(VGP_arm64_linux) \
- || defined(VGP_tilegx_linux) || defined(VGP_x86_solaris) \
- || defined(VGP_amd64_solaris)
+ || defined(VGP_x86_solaris) || defined(VGP_amd64_solaris)
return f;
# elif defined(VGP_ppc64be_linux)
/* ppc64-linux uses the AIX scheme, in which f is a pointer to a
diff --git a/coregrind/m_main.c b/coregrind/m_main.c
index 01c1a6d..87fbc8b 100644
--- a/coregrind/m_main.c
+++ b/coregrind/m_main.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -28,9 +28,9 @@
The GNU General Public License is contained in the file COPYING.
*/
+#include "vgversion.h"
#include "pub_core_basics.h"
#include "pub_core_vki.h"
-#include "pub_core_vkiscnums.h"
#include "pub_core_threadstate.h"
#include "pub_core_xarray.h"
#include "pub_core_clientstate.h"
@@ -50,7 +50,6 @@
#include "pub_core_libcproc.h"
#include "pub_core_libcsignal.h"
#include "pub_core_sbprofile.h"
-#include "pub_core_syscall.h" // VG_(strerror)
#include "pub_core_mach.h"
#include "pub_core_machine.h"
#include "pub_core_mallocfree.h"
@@ -145,6 +144,12 @@
" --alignment=<number> set minimum alignment of heap allocations [%s]\n"
" --redzone-size=<number> set minimum size of redzones added before/after\n"
" heap blocks (in bytes). [%s]\n"
+" --xtree-memory=none|allocs|full profile heap memory in an xtree [none]\n"
+" and produces a report at the end of the execution\n"
+" none: no profiling, allocs: current allocated\n"
+" size/blocks, full: profile current and cumulative\n"
+" allocated size/blocks and freed size/blocks.\n"
+" --xtree-memory-file=<file> xtree memory report file [xtmemory.kcg.%%p]\n"
"\n"
" uncommon user options for all Valgrind tools:\n"
" --fullpath-after= (with nothing after the '=')\n"
@@ -182,7 +187,7 @@
" --sim-hints=hint1,hint2,... activate unusual sim behaviours [none] \n"
" where hint is one of:\n"
" lax-ioctls lax-doors fuse-compatible enable-outer\n"
-" no-inner-prefix no-nptl-pthread-stackcache none\n"
+" no-inner-prefix no-nptl-pthread-stackcache fallback-llsc none\n"
" --fair-sched=no|yes|try schedule threads fairly on multicore systems [no]\n"
" --kernel-variant=variant1,variant2,...\n"
" handle non-standard kernel variants [none]\n"
@@ -288,6 +293,7 @@
"\n"
" debugging options for Valgrind tools that replace malloc:\n"
" --trace-malloc=no|yes show client malloc details? [no]\n"
+" --xtree-compress-strings=no|yes compress strings in xtree callgrind format [yes]\n"
"\n";
const HChar usage3[] =
@@ -295,8 +301,8 @@
" Extra options read from ~/.valgrindrc, $VALGRIND_OPTS, ./.valgrindrc\n"
"\n"
" %s is %s\n"
-" Valgrind is Copyright (C) 2000-2015, and GNU GPL'd, by Julian Seward et al.\n"
-" LibVEX is Copyright (C) 2004-2015, and GNU GPL'd, by OpenWorks LLP et al.\n"
+" Valgrind is Copyright (C) 2000-2017, and GNU GPL'd, by Julian Seward et al.\n"
+" LibVEX is Copyright (C) 2004-2017, and GNU GPL'd, by OpenWorks LLP et al.\n"
"\n"
" Bug reports, feedback, admiration, abuse, etc, to: %s.\n"
"\n";
@@ -306,7 +312,7 @@
// Ensure the message goes to stdout
VG_(log_output_sink).fd = 1;
- VG_(log_output_sink).is_socket = False;
+ VG_(log_output_sink).type = VgLogTo_Fd;
if (VG_(needs).malloc_replacement) {
VG_(sprintf)(default_alignment, "%d", VG_MIN_MALLOC_SZB);
@@ -355,7 +361,7 @@
- show the version string, if requested (-v)
- extract any request for help (--help, -h, --help-debug)
- - get the toolname (--tool=)
+ - set VG_(toolname) (--tool=)
- set VG_(clo_max_stackframe) (--max-stackframe=)
- set VG_(clo_main_stacksize) (--main-stacksize=)
- set VG_(clo_sim_hints) (--sim-hints=)
@@ -366,11 +372,11 @@
main_process_cmd_line_options has to handle but ignore the ones we
have handled here.
*/
-static void early_process_cmd_line_options ( /*OUT*/Int* need_help,
- /*OUT*/const HChar** tool )
+static void early_process_cmd_line_options ( /*OUT*/Int* need_help )
{
UInt i;
HChar* str;
+ Int need_version = 0;
vg_assert( VG_(args_for_valgrind) );
@@ -380,12 +386,13 @@
str = * (HChar**) VG_(indexXA)( VG_(args_for_valgrind), i );
vg_assert(str);
- // Nb: the version string goes to stdout.
- if VG_XACT_CLO(str, "--version", VG_(log_output_sink).fd, 1) {
- VG_(log_output_sink).is_socket = False;
- VG_(printf)("valgrind-" VERSION "\n");
- VG_(exit)(0);
- }
+ if VG_XACT_CLO(str, "--version", need_version, 1) {}
+ else if (VG_STREQ(str, "-v") ||
+ VG_STREQ(str, "--verbose"))
+ VG_(clo_verbosity)++;
+ else if (VG_STREQ(str, "-q") ||
+ VG_STREQ(str, "--quiet"))
+ VG_(clo_verbosity)--;
else if VG_XACT_CLO(str, "--help", *need_help, *need_help+1) {}
else if VG_XACT_CLO(str, "-h", *need_help, *need_help+1) {}
@@ -393,7 +400,7 @@
// The tool has already been determined, but we need to know the name
// here.
- else if VG_STR_CLO(str, "--tool", *tool) {}
+ else if VG_STR_CLO(str, "--tool", VG_(clo_toolname)) {}
// Set up VG_(clo_max_stackframe) and VG_(clo_main_stacksize).
// These are needed by VG_(ii_create_image), which happens
@@ -410,62 +417,33 @@
else if VG_USETX_CLO (str, "--sim-hints",
"lax-ioctls,lax-doors,fuse-compatible,"
"enable-outer,no-inner-prefix,"
- "no-nptl-pthread-stackcache",
+ "no-nptl-pthread-stackcache,fallback-llsc",
VG_(clo_sim_hints)) {}
}
+ if (need_version) {
+ // Nb: the version string goes to stdout.
+ VG_(log_output_sink).fd = 1;
+ VG_(log_output_sink).type = VgLogTo_Fd;
+ if (VG_(clo_verbosity) <= 1)
+ VG_(printf)("valgrind-" VERSION "\n");
+ else
+ VG_(printf)("valgrind-" VERSION "-" VGSVN "-vex-" VEXSVN "\n");
+ VG_(exit)(0);
+ }
+
/* For convenience */
VG_N_THREADS = VG_(clo_max_threads);
}
/* The main processing for command line options. See comments above
- on early_process_cmd_line_options.
-
- Comments on how the logging options are handled:
-
- User can specify:
- --log-fd= for a fd to write to (default setting, fd = 2)
- --log-file= for a file name to write to
- --log-socket= for a socket to write to
-
- As a result of examining these and doing relevant socket/file
- opening, a final fd is established. This is stored in
- VG_(log_output_sink) in m_libcprint. Also, if --log-file=STR was
- specified, then STR, after expansion of %p and %q templates within
- it, is stored in VG_(clo_log_fname_expanded), in m_options, just in
- case anybody wants to know what it is.
-
- When printing, VG_(log_output_sink) is consulted to find the
- fd to send output to.
-
- Exactly analogous actions are undertaken for the XML output
- channel, with the one difference that the default fd is -1, meaning
- the channel is disabled by default.
-*/
+ on early_process_cmd_line_options. */
static
-void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd,
- /*OUT*/const HChar** xml_fname_unexpanded,
- const HChar* toolname )
+void main_process_cmd_line_options( void )
{
- // VG_(clo_log_fd) is used by all the messaging. It starts as 2 (stderr)
- // and we cannot change it until we know what we are changing it to is
- // ok. So we have tmp_log_fd to hold the tmp fd prior to that point.
- SysRes sres;
- Int i, tmp_log_fd, tmp_xml_fd;
- Int toolname_len = VG_(strlen)(toolname);
+ Int i;
+ Int toolname_len = VG_(strlen)(VG_(clo_toolname));
const HChar* tmp_str; // Used in a couple of places.
- enum {
- VgLogTo_Fd,
- VgLogTo_File,
- VgLogTo_Socket
- } log_to = VgLogTo_Fd, // Where is logging output to be sent?
- xml_to = VgLogTo_Fd; // Where is XML output to be sent?
-
- /* Temporarily holds the string STR specified with
- --{log,xml}-{name,socket}=STR. 'fs' stands for
- file-or-socket. */
- const HChar* log_fsname_unexpanded = NULL;
- const HChar* xml_fsname_unexpanded = NULL;
/* Whether the user has explicitly provided --sigill-diagnostics.
If not explicitly given depends on general verbosity setting. */
@@ -473,9 +451,11 @@
/* Log to stderr by default, but usage message goes to stdout. XML
output is initially disabled. */
- tmp_log_fd = 2;
- tmp_xml_fd = -1;
-
+ VgLogTo log_to = VgLogTo_Fd; // Where is logging output to be sent?
+ VgLogTo xml_to = VgLogTo_Fd; // Where is XML output to be sent?
+ Int tmp_log_fd = 2;
+ Int tmp_xml_fd = -1;
+
/* Check for sane path in ./configure --prefix=... */
if (VG_LIBDIR[0] != '/')
VG_(err_config_error)("Please use absolute paths in "
@@ -515,7 +495,7 @@
// eg. "--memcheck:verbose".
if (*colon == ':') {
if (VG_STREQN(2, arg, "--") &&
- VG_STREQN(toolname_len, arg+2, toolname) &&
+ VG_STREQN(toolname_len, arg+2, VG_(clo_toolname)) &&
VG_STREQN(1, arg+2+toolname_len, ":"))
{
// Prefix matches, convert "--toolname:foo" to "--foo".
@@ -550,6 +530,10 @@
else if VG_STREQN(20, arg, "--command-line-only=") {}
else if VG_STREQ( arg, "--") {}
else if VG_STREQ( arg, "-d") {}
+ else if VG_STREQ( arg, "-q") {}
+ else if VG_STREQ( arg, "--quiet") {}
+ else if VG_STREQ( arg, "-v") {}
+ else if VG_STREQ( arg, "--verbose") {}
else if VG_STREQN(17, arg, "--max-stackframe=") {}
else if VG_STREQN(17, arg, "--main-stacksize=") {}
else if VG_STREQN(14, arg, "--max-threads=") {}
@@ -580,15 +564,8 @@
" (or --vex-iropt-register-updates=allregs-at-each-insn)\n");
}
- // These options are new.
- else if (VG_STREQ(arg, "-v") ||
- VG_STREQ(arg, "--verbose"))
- VG_(clo_verbosity)++;
-
- else if (VG_STREQ(arg, "-q") ||
- VG_STREQ(arg, "--quiet"))
- VG_(clo_verbosity)--;
-
+ /* These options are new, not yet handled by
+ early_process_cmd_line_options. */
else if VG_BOOL_CLO(arg, "--sigill-diagnostics", VG_(clo_sigill_diag))
sigill_diag_set = True;
@@ -762,24 +739,24 @@
else if VG_INT_CLO(arg, "--log-fd", tmp_log_fd) {
log_to = VgLogTo_Fd;
- log_fsname_unexpanded = NULL;
+ VG_(clo_log_fname_unexpanded) = NULL;
}
else if VG_INT_CLO(arg, "--xml-fd", tmp_xml_fd) {
xml_to = VgLogTo_Fd;
- xml_fsname_unexpanded = NULL;
+ VG_(clo_xml_fname_unexpanded) = NULL;
}
- else if VG_STR_CLO(arg, "--log-file", log_fsname_unexpanded) {
+ else if VG_STR_CLO(arg, "--log-file", VG_(clo_log_fname_unexpanded)) {
log_to = VgLogTo_File;
}
- else if VG_STR_CLO(arg, "--xml-file", xml_fsname_unexpanded) {
+ else if VG_STR_CLO(arg, "--xml-file", VG_(clo_xml_fname_unexpanded)) {
xml_to = VgLogTo_File;
}
- else if VG_STR_CLO(arg, "--log-socket", log_fsname_unexpanded) {
+ else if VG_STR_CLO(arg, "--log-socket", VG_(clo_log_fname_unexpanded)) {
log_to = VgLogTo_Socket;
}
- else if VG_STR_CLO(arg, "--xml-socket", xml_fsname_unexpanded) {
+ else if VG_STR_CLO(arg, "--xml-socket", VG_(clo_xml_fname_unexpanded)) {
xml_to = VgLogTo_Socket;
}
@@ -1013,197 +990,13 @@
have to generate any other command-line-related error messages.
(So far we should be still attached to stderr, so we can show on
the terminal any problems to do with processing command line
- opts.)
-
- So set up logging now. After this is done, VG_(log_output_sink)
- and (if relevant) VG_(xml_output_sink) should be connected to
- whatever sink has been selected, and we indiscriminately chuck
- stuff into it without worrying what the nature of it is. Oh the
- wonder of Unix streams. */
+ opts.) */
+ VG_(init_log_xml_sinks)(log_to, xml_to, tmp_log_fd, tmp_xml_fd);
- vg_assert(VG_(log_output_sink).fd == 2 /* stderr */);
- vg_assert(VG_(log_output_sink).is_socket == False);
- vg_assert(VG_(clo_log_fname_expanded) == NULL);
-
- vg_assert(VG_(xml_output_sink).fd == -1 /* disabled */);
- vg_assert(VG_(xml_output_sink).is_socket == False);
- vg_assert(VG_(clo_xml_fname_expanded) == NULL);
-
- /* --- set up the normal text output channel --- */
-
- switch (log_to) {
-
- case VgLogTo_Fd:
- vg_assert(log_fsname_unexpanded == NULL);
- break;
-
- case VgLogTo_File: {
- HChar* logfilename;
-
- vg_assert(log_fsname_unexpanded != NULL);
- vg_assert(VG_(strlen)(log_fsname_unexpanded) <= 900); /* paranoia */
-
- // Nb: we overwrite an existing file of this name without asking
- // any questions.
- logfilename = VG_(expand_file_name)("--log-file",
- log_fsname_unexpanded);
- sres = VG_(open)(logfilename,
- VKI_O_CREAT|VKI_O_WRONLY|VKI_O_TRUNC,
- VKI_S_IRUSR|VKI_S_IWUSR|VKI_S_IRGRP|VKI_S_IROTH);
- if (!sr_isError(sres)) {
- tmp_log_fd = sr_Res(sres);
- VG_(clo_log_fname_expanded) = logfilename;
- } else {
- VG_(fmsg)("can't create log file '%s': %s\n",
- logfilename, VG_(strerror)(sr_Err(sres)));
- VG_(exit)(1);
- /*NOTREACHED*/
- }
- break;
- }
-
- case VgLogTo_Socket: {
- vg_assert(log_fsname_unexpanded != NULL);
- vg_assert(VG_(strlen)(log_fsname_unexpanded) <= 900); /* paranoia */
- tmp_log_fd = VG_(connect_via_socket)( log_fsname_unexpanded );
- if (tmp_log_fd == -1) {
- VG_(fmsg)("Invalid --log-socket spec of '%s'\n",
- log_fsname_unexpanded);
- VG_(exit)(1);
- /*NOTREACHED*/
- }
- if (tmp_log_fd == -2) {
- VG_(umsg)("failed to connect to logging server '%s'.\n"
- "Log messages will sent to stderr instead.\n",
- log_fsname_unexpanded );
-
- /* We don't change anything here. */
- vg_assert(VG_(log_output_sink).fd == 2);
- tmp_log_fd = 2;
- } else {
- vg_assert(tmp_log_fd > 0);
- VG_(log_output_sink).is_socket = True;
- }
- break;
- }
- }
-
- /* --- set up the XML output channel --- */
-
- switch (xml_to) {
-
- case VgLogTo_Fd:
- vg_assert(xml_fsname_unexpanded == NULL);
- break;
-
- case VgLogTo_File: {
- HChar* xmlfilename;
-
- vg_assert(xml_fsname_unexpanded != NULL);
- vg_assert(VG_(strlen)(xml_fsname_unexpanded) <= 900); /* paranoia */
-
- // Nb: we overwrite an existing file of this name without asking
- // any questions.
- xmlfilename = VG_(expand_file_name)("--xml-file",
- xml_fsname_unexpanded);
- sres = VG_(open)(xmlfilename,
- VKI_O_CREAT|VKI_O_WRONLY|VKI_O_TRUNC,
- VKI_S_IRUSR|VKI_S_IWUSR|VKI_S_IRGRP|VKI_S_IROTH);
- if (!sr_isError(sres)) {
- tmp_xml_fd = sr_Res(sres);
- VG_(clo_xml_fname_expanded) = xmlfilename;
- *xml_fname_unexpanded = xml_fsname_unexpanded;
- } else {
- VG_(fmsg)("can't create XML file '%s': %s\n",
- xmlfilename, VG_(strerror)(sr_Err(sres)));
- VG_(exit)(1);
- /*NOTREACHED*/
- }
- break;
- }
-
- case VgLogTo_Socket: {
- vg_assert(xml_fsname_unexpanded != NULL);
- vg_assert(VG_(strlen)(xml_fsname_unexpanded) <= 900); /* paranoia */
- tmp_xml_fd = VG_(connect_via_socket)( xml_fsname_unexpanded );
- if (tmp_xml_fd == -1) {
- VG_(fmsg)("Invalid --xml-socket spec of '%s'\n",
- xml_fsname_unexpanded );
- VG_(exit)(1);
- /*NOTREACHED*/
- }
- if (tmp_xml_fd == -2) {
- VG_(umsg)("failed to connect to XML logging server '%s'.\n"
- "XML output will sent to stderr instead.\n",
- xml_fsname_unexpanded);
- /* We don't change anything here. */
- vg_assert(VG_(xml_output_sink).fd == 2);
- tmp_xml_fd = 2;
- } else {
- vg_assert(tmp_xml_fd > 0);
- VG_(xml_output_sink).is_socket = True;
- }
- break;
- }
- }
-
- /* If we've got this far, and XML mode was requested, but no XML
- output channel appears to have been specified, just stop. We
- could continue, and XML output will simply vanish into nowhere,
- but that is likely to confuse the hell out of users, which is
- distinctly Ungood. */
- if (VG_(clo_xml) && tmp_xml_fd == -1) {
- VG_(fmsg_bad_option)(
- "--xml=yes, but no XML destination specified",
- "--xml=yes has been specified, but there is no XML output\n"
- "destination. You must specify an XML output destination\n"
- "using --xml-fd, --xml-file or --xml-socket.\n"
- );
- }
-
- // Finalise the output fds: the log fd ..
-
- if (tmp_log_fd >= 0) {
- // Move log_fd into the safe range, so it doesn't conflict with
- // any app fds.
- tmp_log_fd = VG_(fcntl)(tmp_log_fd, VKI_F_DUPFD, VG_(fd_hard_limit));
- if (tmp_log_fd < 0) {
- VG_(message)(Vg_UserMsg, "valgrind: failed to move logfile fd "
- "into safe range, using stderr\n");
- VG_(log_output_sink).fd = 2; // stderr
- VG_(log_output_sink).is_socket = False;
- } else {
- VG_(log_output_sink).fd = tmp_log_fd;
- VG_(fcntl)(VG_(log_output_sink).fd, VKI_F_SETFD, VKI_FD_CLOEXEC);
- }
- } else {
- // If they said --log-fd=-1, don't print anything. Plausible for use in
- // regression testing suites that use client requests to count errors.
- VG_(log_output_sink).fd = -1;
- VG_(log_output_sink).is_socket = False;
- }
-
- // Finalise the output fds: and the XML fd ..
-
- if (tmp_xml_fd >= 0) {
- // Move xml_fd into the safe range, so it doesn't conflict with
- // any app fds.
- tmp_xml_fd = VG_(fcntl)(tmp_xml_fd, VKI_F_DUPFD, VG_(fd_hard_limit));
- if (tmp_xml_fd < 0) {
- VG_(message)(Vg_UserMsg, "valgrind: failed to move XML file fd "
- "into safe range, using stderr\n");
- VG_(xml_output_sink).fd = 2; // stderr
- VG_(xml_output_sink).is_socket = False;
- } else {
- VG_(xml_output_sink).fd = tmp_xml_fd;
- VG_(fcntl)(VG_(xml_output_sink).fd, VKI_F_SETFD, VKI_FD_CLOEXEC);
- }
- } else {
- // If they said --xml-fd=-1, don't print anything. Plausible for use in
- // regression testing suites that use client requests to count errors.
- VG_(xml_output_sink).fd = -1;
- VG_(xml_output_sink).is_socket = False;
- }
+ /* Register child at-fork handler which will take care of handling
+ --child-silent-after-fork clo and also reopening output sinks for forked
+ children, if requested via --log|xml-file= options. */
+ VG_(atfork)(NULL, NULL, VG_(logging_atfork_child));
// Suppressions related stuff
@@ -1217,294 +1010,6 @@
VG_(sprintf)(buf, "%s/%s", VG_(libdir), default_supp);
VG_(addToXA)(VG_(clo_suppressions), &buf);
}
-
- *logging_to_fd = log_to == VgLogTo_Fd || log_to == VgLogTo_Socket;
-}
-
-// Write the name and value of log file qualifiers to the xml file.
-// We can safely assume here that the format string is well-formed.
-// It has been checked earlier in VG_(expand_file_name) when processing
-// command line options.
-static void print_file_vars(const HChar* format)
-{
- Int i = 0;
-
- while (format[i]) {
- if (format[i] == '%') {
- // We saw a '%'. What's next...
- i++;
- if ('q' == format[i]) {
- i++;
- if ('{' == format[i]) {
- // Get the env var name, print its contents.
- HChar* qual;
- Int begin_qualname = ++i;
- while (True) {
- if ('}' == format[i]) {
- Int qualname_len = i - begin_qualname;
- HChar qualname[qualname_len + 1];
- VG_(strncpy)(qualname, format + begin_qualname,
- qualname_len);
- qualname[qualname_len] = '\0';
- qual = VG_(getenv)(qualname);
- i++;
- VG_(printf_xml)("<logfilequalifier> <var>%pS</var> "
- "<value>%pS</value> </logfilequalifier>\n",
- qualname, qual);
- break;
- }
- i++;
- }
- }
- }
- } else {
- i++;
- }
- }
-}
-
-
-/*====================================================================*/
-/*=== Printing the preamble ===*/
-/*====================================================================*/
-
-// Print the argument, escaping any chars that require it.
-static void umsg_arg(const HChar* arg)
-{
- SizeT len = VG_(strlen)(arg);
- const HChar* special = " \\<>";
- Int i;
- for (i = 0; i < len; i++) {
- if (VG_(strchr)(special, arg[i])) {
- VG_(umsg)("\\"); // escape with a backslash if necessary
- }
- VG_(umsg)("%c", arg[i]);
- }
-}
-
-// Send output to the XML-stream and escape any XML meta-characters.
-static void xml_arg(const HChar* arg)
-{
- VG_(printf_xml)("%pS", arg);
-}
-
-/* Ok, the logging sink is running now. Print a suitable preamble.
- If logging to file or a socket, write details of parent PID and
- command line args, to help people trying to interpret the
- results of a run which encompasses multiple processes. */
-static void print_preamble ( Bool logging_to_fd,
- const HChar* xml_fname_unexpanded,
- const HChar* toolname )
-{
- Int i;
- const HChar* xpre = VG_(clo_xml) ? " <line>" : "";
- const HChar* xpost = VG_(clo_xml) ? "</line>" : "";
- UInt (*umsg_or_xml)( const HChar*, ... )
- = VG_(clo_xml) ? VG_(printf_xml) : VG_(umsg);
-
- void (*umsg_or_xml_arg)( const HChar* )
- = VG_(clo_xml) ? xml_arg : umsg_arg;
-
- vg_assert( VG_(args_for_client) );
- vg_assert( VG_(args_for_valgrind) );
- vg_assert( toolname );
-
- if (VG_(clo_xml)) {
- VG_(printf_xml)("<?xml version=\"1.0\"?>\n");
- VG_(printf_xml)("\n");
- VG_(printf_xml)("<valgrindoutput>\n");
- VG_(printf_xml)("\n");
- VG_(printf_xml)("<protocolversion>4</protocolversion>\n");
- VG_(printf_xml)("<protocoltool>%s</protocoltool>\n", toolname);
- VG_(printf_xml)("\n");
- }
-
- if (VG_(clo_xml) || VG_(clo_verbosity) > 0) {
-
- if (VG_(clo_xml))
- VG_(printf_xml)("<preamble>\n");
-
- /* Tool details */
- umsg_or_xml( VG_(clo_xml) ? "%s%pS%pS%pS, %pS%s\n" : "%s%s%s%s, %s%s\n",
- xpre,
- VG_(details).name,
- NULL == VG_(details).version ? "" : "-",
- NULL == VG_(details).version
- ? "" : VG_(details).version,
- VG_(details).description,
- xpost );
-
- if (VG_(strlen)(toolname) >= 4 && VG_STREQN(4, toolname, "exp-")) {
- umsg_or_xml(
- "%sNOTE: This is an Experimental-Class Valgrind Tool%s\n",
- xpre, xpost
- );
- }
-
- umsg_or_xml( VG_(clo_xml) ? "%s%pS%s\n" : "%s%s%s\n",
- xpre, VG_(details).copyright_author, xpost );
-
- /* Core details */
- umsg_or_xml(
- "%sUsing Valgrind-%s and LibVEX; rerun with -h for copyright info%s\n",
- xpre, VERSION, xpost
- );
-
- // Print the command line. At one point we wrapped at 80 chars and
- // printed a '\' as a line joiner, but that makes it hard to cut and
- // paste the command line (because of the "==pid==" prefixes), so we now
- // favour utility and simplicity over aesthetics.
- umsg_or_xml("%sCommand: ", xpre);
- umsg_or_xml_arg(VG_(args_the_exename));
-
- for (i = 0; i < VG_(sizeXA)( VG_(args_for_client) ); i++) {
- HChar* s = *(HChar**)VG_(indexXA)( VG_(args_for_client), i );
- umsg_or_xml(" ");
- umsg_or_xml_arg(s);
- }
- umsg_or_xml("%s\n", xpost);
-
- if (VG_(clo_xml))
- VG_(printf_xml)("</preamble>\n");
- }
-
- // Print the parent PID, and other stuff, if necessary.
- if (!VG_(clo_xml) && VG_(clo_verbosity) > 0 && !logging_to_fd) {
- VG_(umsg)("Parent PID: %d\n", VG_(getppid)());
- }
- else
- if (VG_(clo_xml)) {
- VG_(printf_xml)("\n");
- VG_(printf_xml)("<pid>%d</pid>\n", VG_(getpid)());
- VG_(printf_xml)("<ppid>%d</ppid>\n", VG_(getppid)());
- VG_(printf_xml)("<tool>%pS</tool>\n", toolname);
- if (xml_fname_unexpanded)
- print_file_vars(xml_fname_unexpanded);
- if (VG_(clo_xml_user_comment)) {
- /* Note: the user comment itself is XML and is therefore to
- be passed through verbatim (%s) rather than escaped
- (%pS). */
- VG_(printf_xml)("<usercomment>%s</usercomment>\n",
- VG_(clo_xml_user_comment));
- }
- VG_(printf_xml)("\n");
- VG_(printf_xml)("<args>\n");
-
- VG_(printf_xml)(" <vargv>\n");
- if (VG_(name_of_launcher))
- VG_(printf_xml)(" <exe>%pS</exe>\n",
- VG_(name_of_launcher));
- else
- VG_(printf_xml)(" <exe>%pS</exe>\n",
- "(launcher name unknown)");
- for (i = 0; i < VG_(sizeXA)( VG_(args_for_valgrind) ); i++) {
- VG_(printf_xml)(
- " <arg>%pS</arg>\n",
- * (HChar**) VG_(indexXA)( VG_(args_for_valgrind), i )
- );
- }
- VG_(printf_xml)(" </vargv>\n");
-
- VG_(printf_xml)(" <argv>\n");
- VG_(printf_xml)(" <exe>%pS</exe>\n",
- VG_(args_the_exename));
- for (i = 0; i < VG_(sizeXA)( VG_(args_for_client) ); i++) {
- VG_(printf_xml)(
- " <arg>%pS</arg>\n",
- * (HChar**) VG_(indexXA)( VG_(args_for_client), i )
- );
- }
- VG_(printf_xml)(" </argv>\n");
-
- VG_(printf_xml)("</args>\n");
- }
-
- // Last thing in the preamble is a blank line.
- if (VG_(clo_xml))
- VG_(printf_xml)("\n");
- else if (VG_(clo_verbosity) > 0)
- VG_(umsg)("\n");
-
- if (VG_(clo_verbosity) > 1) {
-# if defined(VGO_linux)
- SysRes fd;
-# endif
- VexArch vex_arch;
- VexArchInfo vex_archinfo;
- if (!logging_to_fd)
- VG_(message)(Vg_DebugMsg, "\n");
- VG_(message)(Vg_DebugMsg, "Valgrind options:\n");
- for (i = 0; i < VG_(sizeXA)( VG_(args_for_valgrind) ); i++) {
- VG_(message)(Vg_DebugMsg,
- " %s\n",
- * (HChar**) VG_(indexXA)( VG_(args_for_valgrind), i ));
- }
-
-# if defined(VGO_linux)
- VG_(message)(Vg_DebugMsg, "Contents of /proc/version:\n");
- fd = VG_(open) ( "/proc/version", VKI_O_RDONLY, 0 );
- if (sr_isError(fd)) {
- VG_(message)(Vg_DebugMsg, " can't open /proc/version\n");
- } else {
- const SizeT bufsiz = 255;
- HChar version_buf[bufsiz+1];
- VG_(message)(Vg_DebugMsg, " ");
- Int n, fdno = sr_Res(fd);
- do {
- n = VG_(read)(fdno, version_buf, bufsiz);
- if (n < 0) {
- VG_(message)(Vg_DebugMsg, " error reading /proc/version\n");
- break;
- }
- version_buf[n] = '\0';
- VG_(message)(Vg_DebugMsg, "%s", version_buf);
- } while (n == bufsiz);
- VG_(message)(Vg_DebugMsg, "\n");
- VG_(close)(fdno);
- }
-# elif defined(VGO_darwin)
- VG_(message)(Vg_DebugMsg, "Output from sysctl({CTL_KERN,KERN_VERSION}):\n");
- /* Note: preferable to use sysctlbyname("kern.version", kernelVersion, &len, NULL, 0)
- however that syscall is OS X 10.10+ only. */
- Int mib[] = {CTL_KERN, KERN_VERSION};
- SizeT len;
- VG_(sysctl)(mib, sizeof(mib)/sizeof(Int), NULL, &len, NULL, 0);
- HChar *kernelVersion = VG_(malloc)("main.pp.1", len);
- VG_(sysctl)(mib, sizeof(mib)/sizeof(Int), kernelVersion, &len, NULL, 0);
- VG_(message)(Vg_DebugMsg, " %s\n", kernelVersion);
- VG_(free)( kernelVersion );
-# elif defined(VGO_solaris)
- /* There is no /proc/version file on Solaris so we try to get some
- system information using the uname(2) syscall. */
- {
- struct vki_utsname uts;
-
- VG_(message)(Vg_DebugMsg, "System information:\n");
- SysRes res = VG_(do_syscall1)(__NR_uname, (UWord)&uts);
- if (sr_isError(res))
- VG_(message)(Vg_DebugMsg, " uname() failed\n");
- else
- VG_(message)(Vg_DebugMsg, " %s %s %s %s\n",
- uts.sysname, uts.release, uts.version, uts.machine);
- }
-# endif
-
- VG_(machine_get_VexArchInfo)( &vex_arch, &vex_archinfo );
- VG_(message)(
- Vg_DebugMsg,
- "Arch and hwcaps: %s, %s, %s\n",
- LibVEX_ppVexArch ( vex_arch ),
- LibVEX_ppVexEndness ( vex_archinfo.endness ),
- LibVEX_ppVexHwCaps ( vex_arch, vex_archinfo.hwcaps )
- );
- VG_(message)(
- Vg_DebugMsg,
- "Page sizes: currently %d, max supported %d\n",
- (Int)VKI_PAGE_SIZE, (Int)VKI_MAX_PAGE_SIZE
- );
- VG_(message)(Vg_DebugMsg,
- "Valgrind library directory: %s\n", VG_(libdir));
- }
}
@@ -1625,11 +1130,8 @@
static
Int valgrind_main ( Int argc, HChar **argv, HChar **envp )
{
- const HChar* toolname = "memcheck"; // default to Memcheck
Int need_help = 0; // 0 = no, 1 = --help, 2 = --help-debug
ThreadId tid_main = VG_INVALID_THREADID;
- Bool logging_to_fd = False;
- const HChar* xml_fname_unexpanded = NULL;
Int loglevel, i;
XArray* addr2dihandle = NULL;
@@ -1836,6 +1338,7 @@
"AMD Athlon or above)\n");
VG_(printf)(" * AMD Athlon64/Opteron\n");
VG_(printf)(" * ARM (armv7)\n");
+ VG_(printf)(" * MIPS (mips32 and above; mips64 and above)\n");
VG_(printf)(" * PowerPC (most; ppc405 and above)\n");
VG_(printf)(" * System z (64bit only - s390x; z990 and above)\n");
VG_(printf)("\n");
@@ -1896,15 +1399,16 @@
//--------------------------------------------------------------
VG_(debugLog)(1, "main",
"(early_) Process Valgrind's command line options\n");
- early_process_cmd_line_options(&need_help, &toolname);
+ early_process_cmd_line_options(&need_help);
// BEGIN HACK
- vg_assert(toolname != NULL);
+ vg_assert(VG_(clo_toolname) != NULL);
vg_assert(VG_(clo_read_inline_info) == False);
# if !defined(VGO_darwin)
- if (0 == VG_(strcmp)(toolname, "memcheck")
- || 0 == VG_(strcmp)(toolname, "helgrind")
- || 0 == VG_(strcmp)(toolname, "drd")) {
+ if (0 == VG_(strcmp)(VG_(clo_toolname), "memcheck")
+ || 0 == VG_(strcmp)(VG_(clo_toolname), "helgrind")
+ || 0 == VG_(strcmp)(VG_(clo_toolname), "drd")
+ || 0 == VG_(strcmp)(VG_(clo_toolname), "exp-dhat")) {
/* Change the default setting. Later on (just below)
main_process_cmd_line_options should pick up any
user-supplied setting for it and will override the default
@@ -1926,7 +1430,7 @@
//
// Set up client's environment
// p: set-libdir [for VG_(libdir)]
- // p: early_process_cmd_line_options [for toolname]
+ // p: early_process_cmd_line_options [for VG_(clo_toolname)]
//
// Setup client stack, eip, and VG_(client_arg[cv])
// p: load_client() [for 'info']
@@ -1945,7 +1449,7 @@
# if defined(VGO_linux) || defined(VGO_darwin) || defined(VGO_solaris)
the_iicii.argv = argv;
the_iicii.envp = envp;
- the_iicii.toolname = toolname;
+ the_iicii.toolname = VG_(clo_toolname);
# else
# error "Unknown platform"
# endif
@@ -2102,8 +1606,7 @@
VG_(debugLog)(1, "main",
"(main_) Process Valgrind's command line options, "
"setup logging\n");
- main_process_cmd_line_options ( &logging_to_fd, &xml_fname_unexpanded,
- toolname );
+ main_process_cmd_line_options();
//--------------------------------------------------------------
// Zeroise the millisecond counter by doing a first read of it.
@@ -2115,11 +1618,10 @@
// Print the preamble
// p: tl_pre_clo_init [for 'VG_(details).name' and friends]
// p: main_process_cmd_line_options()
- // [for VG_(clo_verbosity), VG_(clo_xml),
- // logging_to_fd, xml_fname_unexpanded]
+ // [for VG_(clo_verbosity), VG_(clo_xml)]
//--------------------------------------------------------------
VG_(debugLog)(1, "main", "Print the preamble...\n");
- print_preamble(logging_to_fd, xml_fname_unexpanded, toolname);
+ VG_(print_preamble)(VG_(log_output_sink).type != VgLogTo_File);
VG_(debugLog)(1, "main", "...finished the preamble\n");
//--------------------------------------------------------------
@@ -2841,11 +2343,6 @@
VG_TRACK(post_reg_write, Vg_CoreClientReq, tid,
offsetof(VexGuestS390XState, guest_r2),
sizeof(VG_(threads)[tid].arch.vex.guest_r2));
-# elif defined(VGA_tilegx)
- VG_(threads)[tid].arch.vex.guest_r0 = to_run;
- VG_TRACK(post_reg_write, Vg_CoreClientReq, tid,
- offsetof(VexGuestTILEGXState, guest_r0),
- sizeof(VG_(threads)[tid].arch.vex.guest_r0));
#else
I_die_here : architecture missing in m_main.c
#endif
@@ -2926,6 +2423,7 @@
libgcc which boil down to an abort or raise, that's usually defined
in libc. Instead, define them here. */
#if defined(VGP_arm_linux)
+
void raise(void);
void raise(void){
VG_(printf)("Something called raise().\n");
@@ -2944,47 +2442,53 @@
vg_assert(0);
}
-#if defined(__ANDROID__) && defined(__clang__)
+#endif /* defined(VGP_arm_linux) */
+
+/* Some Android helpers. See bug 368529. */
+#if defined(__clang__) \
+ && (defined(VGPV_arm_linux_android) \
+ || defined(VGPV_x86_linux_android) \
+ || defined(VGPV_mips32_linux_android) \
+ || defined(VGPV_arm64_linux_android))
+
/* Replace __aeabi_memcpy* functions with vgPlain_memcpy. */
-void* __aeabi_memcpy(void *dest, const void *src, SizeT n);
-void* __aeabi_memcpy(void *dest, const void *src, SizeT n)
+void *__aeabi_memcpy(void *dest, const void *src, SizeT n);
+void *__aeabi_memcpy(void *dest, const void *src, SizeT n)
{
return VG_(memcpy)(dest, src, n);
}
-void* __aeabi_memcpy4(void *dest, const void *src, SizeT n);
-void* __aeabi_memcpy4(void *dest, const void *src, SizeT n)
+void *__aeabi_memcpy4(void *dest, const void *src, SizeT n);
+void *__aeabi_memcpy4(void *dest, const void *src, SizeT n)
{
return VG_(memcpy)(dest, src, n);
}
-void* __aeabi_memcpy8(void *dest, const void *src, SizeT n);
-void* __aeabi_memcpy8(void *dest, const void *src, SizeT n)
+void *__aeabi_memcpy8(void *dest, const void *src, SizeT n);
+void *__aeabi_memcpy8(void *dest, const void *src, SizeT n)
{
return VG_(memcpy)(dest, src, n);
}
/* Replace __aeabi_memclr* functions with vgPlain_memset. */
-void* __aeabi_memclr(void *dest, SizeT n);
-void* __aeabi_memclr(void *dest, SizeT n)
+void *__aeabi_memclr(void *dest, SizeT n);
+void *__aeabi_memclr(void *dest, SizeT n)
{
return VG_(memset)(dest, 0, n);
}
-void* __aeabi_memclr4(void *dest, SizeT n);
-void* __aeabi_memclr4(void *dest, SizeT n)
+void *__aeabi_memclr4(void *dest, SizeT n);
+void *__aeabi_memclr4(void *dest, SizeT n)
{
return VG_(memset)(dest, 0, n);
}
-void* __aeabi_memclr8(void *dest, SizeT n);
-void* __aeabi_memclr8(void *dest, SizeT n)
+void *__aeabi_memclr8(void *dest, SizeT n);
+void *__aeabi_memclr8(void *dest, SizeT n)
{
return VG_(memset)(dest, 0, n);
}
-#endif /* __ANDROID__ __clang__ */
-
-#endif
+#endif /* clang and android, basically */
/* ---------------- Requirement 2 ---------------- */
@@ -3343,45 +2847,6 @@
"\tnop\n"
".previous\n"
);
-#elif defined(VGP_tilegx_linux)
-asm("\n"
- ".text\n"
- "\t.align 8\n"
- "\t.globl _start\n"
- "\t.type _start,@function\n"
- "_start:\n"
-
- "\tjal 1f\n"
- "1:\n"
-
- /* --FIXME, bundle them :) */
- /* r19 <- Addr(interim_stack) */
- "\tmoveli r19, hw2_last(vgPlain_interim_stack)\n"
- "\tshl16insli r19, r19, hw1(vgPlain_interim_stack)\n"
- "\tshl16insli r19, r19, hw0(vgPlain_interim_stack)\n"
-
- "\tmoveli r20, hw1("VG_STRINGIFY(VG_STACK_GUARD_SZB)")\n"
- "\tshl16insli r20, r20, hw0("VG_STRINGIFY(VG_STACK_GUARD_SZB)")\n"
- "\tmoveli r21, hw1("VG_STRINGIFY(VG_DEFAULT_STACK_ACTIVE_SZB)")\n"
- "\tshl16insli r21, r21, hw0("VG_STRINGIFY(VG_DEFAULT_STACK_ACTIVE_SZB)")\n"
- "\tadd r19, r19, r20\n"
- "\tadd r19, r19, r21\n"
-
- "\tmovei r12, 0x0F\n"
- "\tnor r12, zero, r12\n"
-
- "\tand r19, r19, r12\n"
-
- /* now r19 = &vgPlain_interim_stack + VG_STACK_GUARD_SZB +
- VG_STACK_ACTIVE_SZB rounded down to the nearest 16-byte
- boundary. And $54 is the original SP. Set the SP to r0 and
- call _start_in_C, passing it the initial SP. */
-
- "\tmove r0, r54\n" // r0 <- $sp (_start_in_C first arg)
- "\tmove r54, r19\n" // $sp <- r19 (new sp)
-
- "\tjal _start_in_C_linux\n"
-);
#else
# error "Unknown linux platform"
#endif
@@ -3530,6 +2995,10 @@
// skip check
return VG_(memset)(s,c,n);
}
+void __bzero(void* s, UWord n);
+void __bzero(void* s, UWord n) {
+ (void)VG_(memset)(s,0,n);
+}
void bzero(void *s, SizeT n);
void bzero(void *s, SizeT n) {
VG_(memset)(s,0,n);
@@ -4099,19 +3568,6 @@
#endif
-#if defined(VGO_darwin) && DARWIN_VERS == DARWIN_10_10
-
-/* This might also be needed for > DARWIN_10_10, but I have no way
- to test for that. Hence '==' rather than '>=' in the version
- test above. */
-void __bzero ( void* s, UWord n );
-void __bzero ( void* s, UWord n )
-{
- (void) VG_(memset)( s, 0, n );
-}
-
-#endif
-
/*--------------------------------------------------------------------*/
/*--- end ---*/
diff --git a/coregrind/m_mallocfree.c b/coregrind/m_mallocfree.c
index c047d82..eb0bc12 100644
--- a/coregrind/m_mallocfree.c
+++ b/coregrind/m_mallocfree.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -148,13 +148,16 @@
}
Block;
+/* Ensure that Block payloads can be safely cast to various pointers below. */
+STATIC_ASSERT(VG_MIN_MALLOC_SZB % sizeof(void *) == 0);
+
// A superblock. 'padding' is never used, it just ensures that if the
// entire Superblock is aligned to VG_MIN_MALLOC_SZB, then payload_bytes[]
// will be too. It can add small amounts of padding unnecessarily -- eg.
// 8-bytes on 32-bit machines with an 8-byte VG_MIN_MALLOC_SZB -- because
// it's too hard to make a constant expression that works perfectly in all
// cases.
-// 'unsplittable' is set to NULL if superblock can be splitted, otherwise
+// 'unsplittable' is set to NULL if superblock can be split, otherwise
// it is set to the address of the superblock. An unsplittable superblock
// will contain only one allocated block. An unsplittable superblock will
// be unmapped when its (only) allocated block is freed.
@@ -198,7 +201,7 @@
SizeT min_unsplittable_sblock_szB;
// Minimum unsplittable superblock size in bytes. To be marked as
// unsplittable, a superblock must have a
- // size >= min_unsplittable_sblock_szB and cannot be splitted.
+ // size >= min_unsplittable_sblock_szB and cannot be split.
// So, to avoid big overhead, superblocks used to provide aligned
// blocks on big alignments are splittable.
// Unsplittable superblocks will be reclaimed when their (only)
@@ -296,8 +299,9 @@
SizeT get_bszB_as_is ( Block* b )
{
UByte* b2 = (UByte*)b;
- SizeT bszB_lo = *(SizeT*)&b2[0 + hp_overhead_szB()];
- SizeT bszB_hi = *(SizeT*)&b2[mk_plain_bszB(bszB_lo) - sizeof(SizeT)];
+ SizeT bszB_lo = *ASSUME_ALIGNED(SizeT*, &b2[0 + hp_overhead_szB()]);
+ SizeT bszB_hi = *ASSUME_ALIGNED(SizeT*,
+ &b2[mk_plain_bszB(bszB_lo) - sizeof(SizeT)]);
vg_assert2(bszB_lo == bszB_hi,
"Heap block lo/hi size mismatch: lo = %llu, hi = %llu.\n%s",
(ULong)bszB_lo, (ULong)bszB_hi, probably_your_fault);
@@ -316,8 +320,8 @@
void set_bszB ( Block* b, SizeT bszB )
{
UByte* b2 = (UByte*)b;
- *(SizeT*)&b2[0 + hp_overhead_szB()] = bszB;
- *(SizeT*)&b2[mk_plain_bszB(bszB) - sizeof(SizeT)] = bszB;
+ *ASSUME_ALIGNED(SizeT*, &b2[0 + hp_overhead_szB()]) = bszB;
+ *ASSUME_ALIGNED(SizeT*, &b2[mk_plain_bszB(bszB) - sizeof(SizeT)]) = bszB;
}
//---------------------------------------------------------------------------
@@ -408,25 +412,27 @@
void set_prev_b ( Block* b, Block* prev_p )
{
UByte* b2 = (UByte*)b;
- *(Block**)&b2[hp_overhead_szB() + sizeof(SizeT)] = prev_p;
+ *ASSUME_ALIGNED(Block**, &b2[hp_overhead_szB() + sizeof(SizeT)]) = prev_p;
}
static __inline__
void set_next_b ( Block* b, Block* next_p )
{
UByte* b2 = (UByte*)b;
- *(Block**)&b2[get_bszB(b) - sizeof(SizeT) - sizeof(void*)] = next_p;
+ *ASSUME_ALIGNED(Block**,
+ &b2[get_bszB(b) - sizeof(SizeT) - sizeof(void*)]) = next_p;
}
static __inline__
Block* get_prev_b ( Block* b )
{
UByte* b2 = (UByte*)b;
- return *(Block**)&b2[hp_overhead_szB() + sizeof(SizeT)];
+ return *ASSUME_ALIGNED(Block**, &b2[hp_overhead_szB() + sizeof(SizeT)]);
}
static __inline__
Block* get_next_b ( Block* b )
{
UByte* b2 = (UByte*)b;
- return *(Block**)&b2[get_bszB(b) - sizeof(SizeT) - sizeof(void*)];
+ return *ASSUME_ALIGNED(Block**,
+ &b2[get_bszB(b) - sizeof(SizeT) - sizeof(void*)]);
}
//---------------------------------------------------------------------------
@@ -437,14 +443,14 @@
{
UByte* b2 = (UByte*)b;
vg_assert( VG_(clo_profile_heap) );
- *(const HChar**)&b2[0] = cc;
+ *ASSUME_ALIGNED(const HChar**, &b2[0]) = cc;
}
static __inline__
const HChar* get_cc ( Block* b )
{
UByte* b2 = (UByte*)b;
vg_assert( VG_(clo_profile_heap) );
- return *(const HChar**)&b2[0];
+ return *ASSUME_ALIGNED(const HChar**, &b2[0]);
}
//---------------------------------------------------------------------------
@@ -454,7 +460,7 @@
Block* get_predecessor_block ( Block* b )
{
UByte* b2 = (UByte*)b;
- SizeT bszB = mk_plain_bszB( (*(SizeT*)&b2[-sizeof(SizeT)]) );
+ SizeT bszB = mk_plain_bszB(*ASSUME_ALIGNED(SizeT*, &b2[-sizeof(SizeT)]));
return (Block*)&b2[-bszB];
}
@@ -550,7 +556,7 @@
}
// Initialise an arena. rz_szB is the (default) minimum redzone size;
-// It might be overriden by VG_(clo_redzone_size) or VG_(clo_core_redzone_size).
+// It might be overridden by VG_(clo_redzone_size) or VG_(clo_core_redzone_size).
// it might be made bigger to ensure that VG_MIN_MALLOC_SZB is observed.
static
void arena_init ( ArenaId aid, const HChar* name, SizeT rz_szB,
@@ -1859,7 +1865,7 @@
vg_assert(b_bszB >= req_bszB);
// Could we split this block and still get a useful fragment?
- // A block in an unsplittable superblock can never be splitted.
+ // A block in an unsplittable superblock can never be split.
frag_bszB = b_bszB - req_bszB;
if (frag_bszB >= min_useful_bszB(a)
&& (NULL == new_sb || ! new_sb->unsplittable)) {
@@ -2002,7 +2008,7 @@
/* b must be a free block, of size b_bszB.
If b is followed by another free block, merge them.
- If b is preceeded by another free block, merge them.
+ If b is preceded by another free block, merge them.
If the merge results in the superblock being fully free,
deferred_reclaimSuperblock the superblock. */
static void mergeWithFreeNeighbours (Arena* a, Superblock* sb,
@@ -2248,7 +2254,7 @@
{
/* As we will split the block given back by VG_(arena_malloc),
we have to (temporarily) disable unsplittable for this arena,
- as unsplittable superblocks cannot be splitted. */
+ as unsplittable superblocks cannot be split. */
const SizeT save_min_unsplittable_sblock_szB
= a->min_unsplittable_sblock_szB;
a->min_unsplittable_sblock_szB = MAX_PSZB;
diff --git a/coregrind/m_options.c b/coregrind/m_options.c
index d5e07da..1bf2cc0 100644
--- a/coregrind/m_options.c
+++ b/coregrind/m_options.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Nicholas Nethercote
+ Copyright (C) 2000-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -45,6 +45,7 @@
/* Define, and set defaults. */
+const HChar *VG_(clo_toolname) = "memcheck"; // default to Memcheck
VexControl VG_(clo_vex_control);
VexRegisterUpdates VG_(clo_px_file_backed) = VexRegUpd_INVALID;
@@ -79,8 +80,8 @@
const HChar* VG_(clo_trace_children_skip) = NULL;
const HChar* VG_(clo_trace_children_skip_by_arg) = NULL;
Bool VG_(clo_child_silent_after_fork) = False;
-const HChar* VG_(clo_log_fname_expanded) = NULL;
-const HChar* VG_(clo_xml_fname_expanded) = NULL;
+const HChar *VG_(clo_log_fname_unexpanded) = NULL;
+const HChar *VG_(clo_xml_fname_unexpanded) = NULL;
Bool VG_(clo_time_stamp) = False;
Int VG_(clo_input_fd) = 0; /* stdin */
Bool VG_(clo_default_supp) = True;
@@ -112,6 +113,10 @@
// A value != -1 overrides the tool-specific value
// VG_(needs_malloc_replacement).tool_client_redzone_szB
Int VG_(clo_redzone_size) = -1;
+VgXTMemory VG_(clo_xtree_memory) = Vg_XTMemory_None;
+const HChar* VG_(clo_xtree_memory_file) = "xtmemory.kcg.%p";
+Bool VG_(clo_xtree_compress_strings) = True;
+
Int VG_(clo_dump_error) = 0;
Int VG_(clo_backtrace_size) = 12;
Int VG_(clo_merge_recursive_frames) = 0; // default value: no merge
@@ -143,8 +148,7 @@
VgSmc VG_(clo_smc_check) = Vg_SmcAllNonFile;
#elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \
|| defined(VGA_arm) || defined(VGA_arm64) \
- || defined(VGA_mips32) || defined(VGA_mips64) \
- || defined(VGA_tilegx)
+ || defined(VGA_mips32) || defined(VGA_mips64)
VgSmc VG_(clo_smc_check) = Vg_SmcStack;
#else
# error "Unknown arch"
@@ -221,6 +225,19 @@
j += VG_(sprintf)(&out[j], "%d", pid);
i++;
}
+ else if ('n' == format[i]) {
+ // Print a seq nr.
+ static Int last_pid;
+ static Int seq_nr;
+ Int pid = VG_(getpid)();
+ if (last_pid != pid)
+ seq_nr = 0;
+ last_pid = pid;
+ seq_nr++;
+ ENSURE_THIS_MUCH_SPACE(10);
+ j += VG_(sprintf)(&out[j], "%d", seq_nr);
+ i++;
+ }
else if ('q' == format[i]) {
i++;
if ('{' == format[i]) {
diff --git a/coregrind/m_oset.c b/coregrind/m_oset.c
index 3fd214f..5912134 100644
--- a/coregrind/m_oset.c
+++ b/coregrind/m_oset.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Nicholas Nethercote
+ Copyright (C) 2005-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -31,7 +31,7 @@
//----------------------------------------------------------------------
// This file is based on:
//
-// ANSI C Library for maintainance of AVL Balanced Trees
+// ANSI C Library for maintenance of AVL Balanced Trees
// (C) 2000 Daniel Nagy, Budapest University of Technology and Economics
// Released under GNU General Public License (GPL) version 2
//----------------------------------------------------------------------
@@ -112,9 +112,9 @@
struct _OSet {
SizeT keyOff; // key offset
OSetCmp_t cmp; // compare a key and an element, or NULL
- OSetAlloc_t alloc_fn; // allocator
+ Alloc_Fn_t alloc_fn; // allocator
const HChar* cc; // cost centre for allocator
- OSetFree_t free_fn; // deallocator
+ Free_Fn_t free_fn; // deallocator
PoolAlloc* node_pa; // (optional) pool allocator for nodes.
SizeT maxEltSize; // for node_pa, must be > 0. Otherwise unused.
UInt nElems; // number of elements in the tree
@@ -200,7 +200,7 @@
}
-// Swing to the left. Warning: no balance maintainance.
+// Swing to the left. Warning: no balance maintenance.
static void avl_swl ( AvlNode** root )
{
AvlNode* a = *root;
@@ -210,7 +210,7 @@
b->left = a;
}
-// Swing to the right. Warning: no balance maintainance.
+// Swing to the right. Warning: no balance maintenance.
static void avl_swr ( AvlNode** root )
{
AvlNode* a = *root;
@@ -220,7 +220,7 @@
b->right = a;
}
-// Balance maintainance after especially nasty swings.
+// Balance maintenance after especially nasty swings.
static void avl_nasty ( AvlNode* root )
{
switch (root->balance) {
@@ -286,8 +286,8 @@
// The underscores avoid GCC complaints about overshadowing global names.
AvlTree* VG_(OSetGen_Create)(PtrdiffT keyOff, OSetCmp_t cmp,
- OSetAlloc_t alloc_fn, const HChar* cc,
- OSetFree_t free_fn)
+ Alloc_Fn_t alloc_fn, const HChar* cc,
+ Free_Fn_t free_fn)
{
AvlTree* t;
@@ -315,8 +315,8 @@
}
AvlTree* VG_(OSetGen_Create_With_Pool)(PtrdiffT keyOff, OSetCmp_t cmp,
- OSetAlloc_t alloc_fn, const HChar* cc,
- OSetFree_t free_fn,
+ Alloc_Fn_t alloc_fn, const HChar* cc,
+ Free_Fn_t free_fn,
SizeT poolSize,
SizeT maxEltSize)
{
@@ -361,8 +361,8 @@
return t;
}
-AvlTree* VG_(OSetWord_Create)(OSetAlloc_t alloc_fn, const HChar* cc,
- OSetFree_t free_fn)
+AvlTree* VG_(OSetWord_Create)(Alloc_Fn_t alloc_fn, const HChar* cc,
+ Free_Fn_t free_fn)
{
return VG_(OSetGen_Create)(/*keyOff*/0, /*cmp*/NULL, alloc_fn, cc, free_fn);
}
diff --git a/coregrind/m_poolalloc.c b/coregrind/m_poolalloc.c
index ed203ce..ac4b563 100644
--- a/coregrind/m_poolalloc.c
+++ b/coregrind/m_poolalloc.c
@@ -5,7 +5,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2015 OpenWorks LLP info@open-works.co.uk,
+ Copyright (C) 2011-2017 OpenWorks LLP info@open-works.co.uk,
Philippe Waroquiers philippe.waroquiers@skynet.be
This program is free software; you can redistribute it and/or
@@ -36,9 +36,9 @@
UWord nrRef; /* nr reference to this pool allocator */
UWord elemSzB; /* element size */
UWord nPerPool; /* # elems per pool */
- void* (*alloc_fn)(const HChar*, SizeT); /* pool allocator */
- const HChar* cc; /* pool allocator's cost centre */
- void (*free_fn)(void*); /* pool allocator's free-er */
+ Alloc_Fn_t alloc_fn; /* pool allocator */
+ const HChar* cc; /* pool allocator's cost centre */
+ Free_Fn_t free_fn; /* pool allocator's free-er */
/* XArray of void* (pointers to pools). The pools themselves.
Each element is a pointer to a block of size (elemSzB *
nPerPool) bytes. */
@@ -50,9 +50,9 @@
PoolAlloc* VG_(newPA) ( UWord elemSzB,
UWord nPerPool,
- void* (*alloc_fn)(const HChar*, SizeT),
+ Alloc_Fn_t alloc_fn,
const HChar* cc,
- void (*free_fn)(void*) )
+ Free_Fn_t free_fn )
{
PoolAlloc* pa;
vg_assert(0 == (elemSzB % sizeof(UWord)));
diff --git a/coregrind/m_rangemap.c b/coregrind/m_rangemap.c
index b085d29..e1c1396 100644
--- a/coregrind/m_rangemap.c
+++ b/coregrind/m_rangemap.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2014-2015 Mozilla Foundation
+ Copyright (C) 2014-2017 Mozilla Foundation
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -48,9 +48,9 @@
struct _RangeMap {
- void* (*alloc_fn) ( const HChar*, SizeT ); /* alloc fn (nofail) */
+ Alloc_Fn_t alloc_fn; /* alloc fn (nofail) */
const HChar* cc; /* cost centre for alloc */
- void (*free_fn) ( void* ); /* free fn */
+ Free_Fn_t free_fn; /* free fn */
XArray* ranges;
};
@@ -62,9 +62,9 @@
static void show ( const RangeMap* rm );
-RangeMap* VG_(newRangeMap) ( void*(*alloc_fn)(const HChar*,SizeT),
+RangeMap* VG_(newRangeMap) ( Alloc_Fn_t alloc_fn,
const HChar* cc,
- void(*free_fn)(void*),
+ Free_Fn_t free_fn,
UWord initialVal )
{
/* check user-supplied info .. */
diff --git a/coregrind/m_redir.c b/coregrind/m_redir.c
index ff35009..b8cc022 100644
--- a/coregrind/m_redir.c
+++ b/coregrind/m_redir.c
@@ -7,9 +7,9 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
- Copyright (C) 2003-2015 Jeremy Fitzhardinge
+ Copyright (C) 2003-2017 Jeremy Fitzhardinge
jeremy@goop.org
This program is free software; you can redistribute it and/or
@@ -1567,10 +1567,23 @@
/* this is mandatory - can't sanely continue without it */
add_hardwired_spec(
- "ld.so.3", "strlen",
+ "ld.so.1", "strlen",
(Addr)&VG_(mips32_linux_REDIR_FOR_strlen),
complain_about_stripped_glibc_ldso
);
+ add_hardwired_spec(
+ "ld.so.1", "index",
+ (Addr)&VG_(mips32_linux_REDIR_FOR_index),
+ complain_about_stripped_glibc_ldso
+ );
+# if defined(VGPV_mips32_linux_android)
+ add_hardwired_spec(
+ "NONE", "__dl_strlen",
+ (Addr)&VG_(mips32_linux_REDIR_FOR_strlen),
+ NULL
+ );
+# endif
+
}
# elif defined(VGP_mips64_linux)
@@ -1578,18 +1591,14 @@
/* this is mandatory - can't sanely continue without it */
add_hardwired_spec(
- "ld.so.3", "strlen",
+ "ld.so.1", "strlen",
(Addr)&VG_(mips64_linux_REDIR_FOR_strlen),
complain_about_stripped_glibc_ldso
);
- }
-
-# elif defined(VGP_tilegx_linux)
- if (0==VG_(strcmp)("Memcheck", VG_(details).name)) {
-
add_hardwired_spec(
- "ld.so.1", "strlen",
- (Addr)&VG_(tilegx_linux_REDIR_FOR_strlen), NULL
+ "ld.so.1", "index",
+ (Addr)&VG_(mips64_linux_REDIR_FOR_index),
+ complain_about_stripped_glibc_ldso
);
}
diff --git a/coregrind/m_replacemalloc/replacemalloc_core.c b/coregrind/m_replacemalloc/replacemalloc_core.c
index c31add0..4ee787e 100644
--- a/coregrind/m_replacemalloc/replacemalloc_core.c
+++ b/coregrind/m_replacemalloc/replacemalloc_core.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -65,6 +65,16 @@
VG_MIN_MALLOC_SZB);
}
}
+ else if VG_XACT_CLO(arg, "--xtree-memory=none",
+ VG_(clo_xtree_memory), Vg_XTMemory_None) {}
+ else if VG_XACT_CLO(arg, "--xtree-memory=allocs",
+ VG_(clo_xtree_memory), Vg_XTMemory_Allocs) {}
+ else if VG_XACT_CLO(arg, "--xtree-memory=full",
+ VG_(clo_xtree_memory), Vg_XTMemory_Full) {}
+ else if VG_STR_CLO (arg, "--xtree-memory-file",
+ VG_(clo_xtree_memory_file)) {}
+ else if VG_BOOL_CLO(arg, "--xtree-compress-strings",
+ VG_(clo_xtree_compress_strings)) {}
else if VG_BOOL_CLO(arg, "--trace-malloc", VG_(clo_trace_malloc)) {}
else
diff --git a/coregrind/m_replacemalloc/vg_replace_malloc.c b/coregrind/m_replacemalloc/vg_replace_malloc.c
index 3c79c8a..9fb0069 100644
--- a/coregrind/m_replacemalloc/vg_replace_malloc.c
+++ b/coregrind/m_replacemalloc/vg_replace_malloc.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_sbprofile.c b/coregrind/m_sbprofile.c
index 25683f6..45c26d8 100644
--- a/coregrind/m_sbprofile.c
+++ b/coregrind/m_sbprofile.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2012-2015 Mozilla Foundation
+ Copyright (C) 2012-2017 Mozilla Foundation
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/m_scheduler/priv_sched-lock-impl.h b/coregrind/m_scheduler/priv_sched-lock-impl.h
index ae291b1..d68f9d6 100644
--- a/coregrind/m_scheduler/priv_sched-lock-impl.h
+++ b/coregrind/m_scheduler/priv_sched-lock-impl.h
@@ -9,7 +9,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2011-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/m_scheduler/priv_sched-lock.h b/coregrind/m_scheduler/priv_sched-lock.h
index aa2b78c..ed121b7 100644
--- a/coregrind/m_scheduler/priv_sched-lock.h
+++ b/coregrind/m_scheduler/priv_sched-lock.h
@@ -9,7 +9,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2011-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/m_scheduler/priv_sema.h b/coregrind/m_scheduler/priv_sema.h
index 49ea813..00a5f21 100644
--- a/coregrind/m_scheduler/priv_sema.h
+++ b/coregrind/m_scheduler/priv_sema.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_scheduler/sched-lock-generic.c b/coregrind/m_scheduler/sched-lock-generic.c
index e9de6f9..2b6ebcb 100644
--- a/coregrind/m_scheduler/sched-lock-generic.c
+++ b/coregrind/m_scheduler/sched-lock-generic.c
@@ -11,7 +11,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2011-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/m_scheduler/sched-lock.c b/coregrind/m_scheduler/sched-lock.c
index 0afdae0..692c277 100644
--- a/coregrind/m_scheduler/sched-lock.c
+++ b/coregrind/m_scheduler/sched-lock.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2011-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/m_scheduler/scheduler.c b/coregrind/m_scheduler/scheduler.c
index 727275c..39f10f8 100644
--- a/coregrind/m_scheduler/scheduler.c
+++ b/coregrind/m_scheduler/scheduler.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -488,6 +488,7 @@
{
tst->os_state.lwpid = 0;
tst->os_state.threadgroup = 0;
+ tst->os_state.stk_id = NULL_STK_ID;
# if defined(VGO_linux)
/* no other fields to clear */
# elif defined(VGO_darwin)
@@ -504,7 +505,6 @@
# if defined(VGP_x86_solaris)
tst->os_state.thrptr = 0;
# endif
- tst->os_state.stk_id = (UWord)-1;
tst->os_state.ustack = NULL;
tst->os_state.in_door_return = False;
tst->os_state.door_return_procedure = 0;
@@ -925,6 +925,14 @@
tst->arch.vex.host_EvC_FAILADDR
= (HWord)VG_(fnptr_to_fnentry)( &VG_(disp_cp_evcheck_fail) );
+ /* Invalidate any in-flight LL/SC transactions, in the case that we're
+ using the fallback LL/SC implementation. See bugs 344524 and 369459. */
+# if defined(VGP_mips32_linux) || defined(VGP_mips64_linux)
+ tst->arch.vex.guest_LLaddr = (HWord)(-1);
+# elif defined(VGP_arm64_linux)
+ tst->arch.vex.guest_LLSC_SIZE = 0;
+# endif
+
if (0) {
vki_sigset_t m;
Int i, err = VG_(sigprocmask)(VKI_SIG_SETMASK, NULL, &m);
@@ -1445,8 +1453,8 @@
before swapping to another. That means that short term
spins waiting for hardware to poke memory won't cause a
thread swap. */
- if (dispatch_ctr > 1000)
- dispatch_ctr = 1000;
+ if (dispatch_ctr > 300)
+ dispatch_ctr = 300;
break;
case VG_TRC_INNER_COUNTERZERO:
@@ -1700,9 +1708,6 @@
#elif defined(VGA_mips32) || defined(VGA_mips64)
# define VG_CLREQ_ARGS guest_r12
# define VG_CLREQ_RET guest_r11
-#elif defined(VGA_tilegx)
-# define VG_CLREQ_ARGS guest_r12
-# define VG_CLREQ_RET guest_r11
#else
# error Unknown arch
#endif
@@ -2007,6 +2012,15 @@
SET_CLREQ_RETVAL( tid, 0 ); /* return value is meaningless */
break;
+ case VG_USERREQ__INNER_THREADS:
+ if (VG_(clo_verbosity) > 2)
+ VG_(printf)( "client request: INNER_THREADS,"
+ " addr %p\n",
+ (void*)arg[1] );
+ VG_(inner_threads) = (ThreadState*)arg[1];
+ SET_CLREQ_RETVAL( tid, 0 ); /* return value is meaningless */
+ break;
+
case VG_USERREQ__COUNT_ERRORS:
SET_CLREQ_RETVAL( tid, VG_(get_n_errs_found)() );
break;
diff --git a/coregrind/m_scheduler/sema.c b/coregrind/m_scheduler/sema.c
index b563768..696fec0 100644
--- a/coregrind/m_scheduler/sema.c
+++ b/coregrind/m_scheduler/sema.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_scheduler/ticket-lock-linux.c b/coregrind/m_scheduler/ticket-lock-linux.c
index 4590481..a9705a0 100644
--- a/coregrind/m_scheduler/ticket-lock-linux.c
+++ b/coregrind/m_scheduler/ticket-lock-linux.c
@@ -14,7 +14,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2011-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/m_seqmatch.c b/coregrind/m_seqmatch.c
index 668e999..9e0f437 100644
--- a/coregrind/m_seqmatch.c
+++ b/coregrind/m_seqmatch.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2015 OpenWorks Ltd
+ Copyright (C) 2008-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_sigframe/priv_sigframe.h b/coregrind/m_sigframe/priv_sigframe.h
index 7435185..981ba90 100644
--- a/coregrind/m_sigframe/priv_sigframe.h
+++ b/coregrind/m_sigframe/priv_sigframe.h
@@ -9,7 +9,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2015-2015 Florian Krohm
+ Copyright (C) 2015-2017 Florian Krohm
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/m_sigframe/sigframe-amd64-darwin.c b/coregrind/m_sigframe/sigframe-amd64-darwin.c
index 281d719..8d32c80 100644
--- a/coregrind/m_sigframe/sigframe-amd64-darwin.c
+++ b/coregrind/m_sigframe/sigframe-amd64-darwin.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2006-2015 OpenWorks Ltd
+ Copyright (C) 2006-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_sigframe/sigframe-amd64-linux.c b/coregrind/m_sigframe/sigframe-amd64-linux.c
index fa34624..36803a6 100644
--- a/coregrind/m_sigframe/sigframe-amd64-linux.c
+++ b/coregrind/m_sigframe/sigframe-amd64-linux.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Nicholas Nethercote
+ Copyright (C) 2000-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_sigframe/sigframe-arm-linux.c b/coregrind/m_sigframe/sigframe-arm-linux.c
index 185367c..499023e 100644
--- a/coregrind/m_sigframe/sigframe-arm-linux.c
+++ b/coregrind/m_sigframe/sigframe-arm-linux.c
@@ -8,11 +8,11 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Nicholas Nethercote
+ Copyright (C) 2000-2017 Nicholas Nethercote
njn@valgrind.org
- Copyright (C) 2004-2015 Paul Mackerras
+ Copyright (C) 2004-2017 Paul Mackerras
paulus@samba.org
- Copyright (C) 2008-2015 Evan Geller
+ Copyright (C) 2008-2017 Evan Geller
gaze@bea.ms
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_sigframe/sigframe-arm64-linux.c b/coregrind/m_sigframe/sigframe-arm64-linux.c
index a0134e4..420c409 100644
--- a/coregrind/m_sigframe/sigframe-arm64-linux.c
+++ b/coregrind/m_sigframe/sigframe-arm64-linux.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2013-2015 OpenWorks
+ Copyright (C) 2013-2017 OpenWorks
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_sigframe/sigframe-common.c b/coregrind/m_sigframe/sigframe-common.c
index 8c513ff..9d243e6 100644
--- a/coregrind/m_sigframe/sigframe-common.c
+++ b/coregrind/m_sigframe/sigframe-common.c
@@ -10,9 +10,9 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Nicholas Nethercote
+ Copyright (C) 2000-2017 Nicholas Nethercote
njn@valgrind.org
- Copyright (C) 2006-2015 OpenWorks Ltd
+ Copyright (C) 2006-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_sigframe/sigframe-mips32-linux.c b/coregrind/m_sigframe/sigframe-mips32-linux.c
index a95a661..3157c32 100644
--- a/coregrind/m_sigframe/sigframe-mips32-linux.c
+++ b/coregrind/m_sigframe/sigframe-mips32-linux.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 RT-RK
+ Copyright (C) 2010-2017 RT-RK
mips-valgrind@rt-rk.com
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_sigframe/sigframe-mips64-linux.c b/coregrind/m_sigframe/sigframe-mips64-linux.c
index f21e2c7..c7ccd8f 100644
--- a/coregrind/m_sigframe/sigframe-mips64-linux.c
+++ b/coregrind/m_sigframe/sigframe-mips64-linux.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 RT-RK
+ Copyright (C) 2010-2017 RT-RK
mips-valgrind@rt-rk.com
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_sigframe/sigframe-ppc32-linux.c b/coregrind/m_sigframe/sigframe-ppc32-linux.c
index 2a496fe..1a3c0b4 100644
--- a/coregrind/m_sigframe/sigframe-ppc32-linux.c
+++ b/coregrind/m_sigframe/sigframe-ppc32-linux.c
@@ -8,9 +8,9 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Nicholas Nethercote
+ Copyright (C) 2000-2017 Nicholas Nethercote
njn@valgrind.org
- Copyright (C) 2004-2015 Paul Mackerras
+ Copyright (C) 2004-2017 Paul Mackerras
paulus@samba.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_sigframe/sigframe-ppc64-linux.c b/coregrind/m_sigframe/sigframe-ppc64-linux.c
index c5f5301..b16606c 100644
--- a/coregrind/m_sigframe/sigframe-ppc64-linux.c
+++ b/coregrind/m_sigframe/sigframe-ppc64-linux.c
@@ -8,9 +8,9 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Nicholas Nethercote
+ Copyright (C) 2000-2017 Nicholas Nethercote
njn@valgrind.org
- Copyright (C) 2004-2015 Paul Mackerras
+ Copyright (C) 2004-2017 Paul Mackerras
paulus@samba.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_sigframe/sigframe-s390x-linux.c b/coregrind/m_sigframe/sigframe-s390x-linux.c
index 3f106f9..dc71d5d 100644
--- a/coregrind/m_sigframe/sigframe-s390x-linux.c
+++ b/coregrind/m_sigframe/sigframe-s390x-linux.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2015
+ Copyright IBM Corp. 2010-2017
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/m_sigframe/sigframe-solaris.c b/coregrind/m_sigframe/sigframe-solaris.c
index c19fb1f..2ddb22e 100644
--- a/coregrind/m_sigframe/sigframe-solaris.c
+++ b/coregrind/m_sigframe/sigframe-solaris.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2015 Petr Pavlu
+ Copyright (C) 2011-2017 Petr Pavlu
setup@dagobah.cz
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_sigframe/sigframe-tilegx-linux.c b/coregrind/m_sigframe/sigframe-tilegx-linux.c
deleted file mode 100644
index 5820740..0000000
--- a/coregrind/m_sigframe/sigframe-tilegx-linux.c
+++ /dev/null
@@ -1,349 +0,0 @@
-
-/*--------------------------------------------------------------------*/
-/*--- Create/destroy signal delivery frames. ---*/
-/*--- sigframe-tilegx-linux.c ---*/
-/*--------------------------------------------------------------------*/
-
-/*
- This file is part of Valgrind, a dynamic binary instrumentation
- framework.
-
- Copyright (C) 2010-2015 Tilera Corp.
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of the
- License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful, but
- WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
- 02111-1307, USA.
-
- The GNU General Public License is contained in the file COPYING.
-*/
-
-/* Contributed by Zhi-Gang Liu <zliu at tilera dot com> */
-
-#if defined(VGP_tilegx_linux)
-
-#include "pub_core_basics.h"
-#include "pub_core_vki.h"
-#include "pub_core_vkiscnums.h"
-#include "pub_core_threadstate.h"
-#include "pub_core_aspacemgr.h"
-#include "pub_core_libcbase.h"
-#include "pub_core_libcassert.h"
-#include "pub_core_libcprint.h"
-#include "pub_core_machine.h"
-#include "pub_core_options.h"
-#include "pub_core_sigframe.h"
-#include "pub_core_signals.h"
-#include "pub_core_tooliface.h"
-#include "pub_core_trampoline.h"
-#include "priv_sigframe.h"
-
-struct vg_sig_private
-{
- UInt magicPI;
- UInt sigNo_private;
- VexGuestTILEGXState vex_shadow1;
- VexGuestTILEGXState vex_shadow2;
-};
-
-#ifndef C_ABI_SAVE_AREA_SIZE
-#define C_ABI_SAVE_AREA_SIZE 16
-#endif
-struct rt_sigframe {
- unsigned char save_area[C_ABI_SAVE_AREA_SIZE]; /* caller save area */
- vki_siginfo_t rs_info;
- struct vki_ucontext rs_uc;
- struct vg_sig_private priv;
-};
-
-
-static
-void setup_sigcontext2 ( ThreadState* tst, struct vki_sigcontext **sc1,
- const vki_siginfo_t *si )
-{
-
- struct vki_sigcontext *sc = *sc1;
-
- VG_TRACK( pre_mem_write, Vg_CoreSignal, tst->tid, "signal frame mcontext",
- (Addr)sc, sizeof(unsigned long long)*34 );
- sc->gregs[0] = tst->arch.vex.guest_r0;
- sc->gregs[1] = tst->arch.vex.guest_r1;
- sc->gregs[2] = tst->arch.vex.guest_r2;
- sc->gregs[3] = tst->arch.vex.guest_r3;
- sc->gregs[4] = tst->arch.vex.guest_r4;
- sc->gregs[5] = tst->arch.vex.guest_r5;
- sc->gregs[6] = tst->arch.vex.guest_r6;
- sc->gregs[7] = tst->arch.vex.guest_r7;
- sc->gregs[8] = tst->arch.vex.guest_r8;
- sc->gregs[9] = tst->arch.vex.guest_r9;
- sc->gregs[10] = tst->arch.vex.guest_r10;
- sc->gregs[11] = tst->arch.vex.guest_r11;
- sc->gregs[12] = tst->arch.vex.guest_r12;
- sc->gregs[13] = tst->arch.vex.guest_r13;
- sc->gregs[14] = tst->arch.vex.guest_r14;
- sc->gregs[15] = tst->arch.vex.guest_r15;
- sc->gregs[16] = tst->arch.vex.guest_r16;
- sc->gregs[17] = tst->arch.vex.guest_r17;
- sc->gregs[18] = tst->arch.vex.guest_r18;
- sc->gregs[19] = tst->arch.vex.guest_r19;
- sc->gregs[20] = tst->arch.vex.guest_r20;
- sc->gregs[21] = tst->arch.vex.guest_r21;
- sc->gregs[22] = tst->arch.vex.guest_r22;
- sc->gregs[23] = tst->arch.vex.guest_r23;
- sc->gregs[24] = tst->arch.vex.guest_r24;
- sc->gregs[25] = tst->arch.vex.guest_r25;
- sc->gregs[26] = tst->arch.vex.guest_r26;
- sc->gregs[27] = tst->arch.vex.guest_r27;
- sc->gregs[28] = tst->arch.vex.guest_r28;
- sc->gregs[29] = tst->arch.vex.guest_r29;
- sc->gregs[30] = tst->arch.vex.guest_r30;
- sc->gregs[31] = tst->arch.vex.guest_r31;
- sc->gregs[32] = tst->arch.vex.guest_r32;
- sc->gregs[33] = tst->arch.vex.guest_r33;
- sc->gregs[34] = tst->arch.vex.guest_r34;
- sc->gregs[35] = tst->arch.vex.guest_r35;
- sc->gregs[36] = tst->arch.vex.guest_r36;
- sc->gregs[37] = tst->arch.vex.guest_r37;
- sc->gregs[38] = tst->arch.vex.guest_r38;
- sc->gregs[39] = tst->arch.vex.guest_r39;
- sc->gregs[40] = tst->arch.vex.guest_r40;
- sc->gregs[41] = tst->arch.vex.guest_r41;
- sc->gregs[42] = tst->arch.vex.guest_r42;
- sc->gregs[43] = tst->arch.vex.guest_r43;
- sc->gregs[44] = tst->arch.vex.guest_r44;
- sc->gregs[45] = tst->arch.vex.guest_r45;
- sc->gregs[46] = tst->arch.vex.guest_r46;
- sc->gregs[47] = tst->arch.vex.guest_r47;
- sc->gregs[48] = tst->arch.vex.guest_r48;
- sc->gregs[49] = tst->arch.vex.guest_r49;
- sc->gregs[50] = tst->arch.vex.guest_r50;
- sc->gregs[51] = tst->arch.vex.guest_r51;
- sc->gregs[52] = tst->arch.vex.guest_r52;
- sc->tp = tst->arch.vex.guest_r53;
- sc->sp = tst->arch.vex.guest_r54;
- sc->lr = tst->arch.vex.guest_r55;
- sc->pc = tst->arch.vex.guest_pc;
-}
-
-/* EXPORTED */
-void VG_(sigframe_create)( ThreadId tid,
- Bool on_altstack,
- Addr sp_top_of_frame,
- const vki_siginfo_t *siginfo,
- const struct vki_ucontext *siguc,
- void *handler,
- UInt flags,
- const vki_sigset_t *mask,
- void *restorer )
-{
- Addr sp;
- ThreadState* tst;
- Addr faultaddr;
- Int sigNo = siginfo->si_signo;
- struct vg_sig_private *priv;
-
- /* Stack must be 8-byte aligned */
- sp_top_of_frame &= ~0x7ULL;
-
- sp = sp_top_of_frame - sizeof(struct rt_sigframe);
-
- tst = VG_(get_ThreadState)(tid);
- if (! ML_(sf_maybe_extend_stack)(tst, sp, sizeof(struct rt_sigframe), flags))
- return;
-
- vg_assert(VG_IS_8_ALIGNED(sp));
-
- /* SIGILL defines addr to be the faulting address */
-
- faultaddr = (Addr)siginfo->_sifields._sigfault._addr;
- if (sigNo == VKI_SIGILL && siginfo->si_code > 0)
- faultaddr = tst->arch.vex.guest_pc;
-
-
- struct rt_sigframe *frame = (struct rt_sigframe *) sp;
- struct vki_ucontext *ucp = &frame->rs_uc;
- if (VG_(clo_trace_signals))
- VG_(printf)("rt_sigframe\n");
- /* Create siginfo. */
- VG_TRACK( pre_mem_write, Vg_CoreSignal, tid, "signal frame siginfo",
- (Addr)&frame->rs_info, sizeof(frame->rs_info) );
-
- VG_(memcpy)(&frame->rs_info, siginfo, sizeof(*siginfo));
-
- VG_TRACK( post_mem_write, Vg_CoreSignal, tid,
- (Addr)&frame->rs_info, sizeof(frame->rs_info) );
-
- /* Create the ucontext. */
- VG_TRACK( pre_mem_write, Vg_CoreSignal, tid, "signal frame ucontext",
- (Addr)ucp, offsetof(struct vki_ucontext, uc_mcontext) );
-
- ucp->uc_flags = 0;
- ucp->uc_link = 0;
- ucp->uc_stack = tst->altstack;
-
- VG_TRACK( post_mem_write, Vg_CoreSignal, tid, (Addr)ucp,
- offsetof(struct vki_ucontext, uc_mcontext) );
-
- struct vki_sigcontext *scp = &(frame->rs_uc.uc_mcontext);
- setup_sigcontext2(tst, &(scp), siginfo);
-
- ucp->uc_sigmask = tst->sig_mask;
-
- priv = &frame->priv;
-
- /*
- * Arguments to signal handler:
- *
- * r0 = signal number
- * r1 = 0 (should be cause)
- * r2 = pointer to ucontext
- *
- * r54 points to the struct rt_sigframe.
- */
-
- tst->arch.vex.guest_r0 = siginfo->si_signo;
- tst->arch.vex.guest_r1 = (Addr) &frame->rs_info;
- tst->arch.vex.guest_r2 = (Addr) &frame->rs_uc;
- tst->arch.vex.guest_r54 = (Addr) frame;
-
- if (flags & VKI_SA_RESTORER)
- {
- tst->arch.vex.guest_r55 = (Addr) restorer;
- }
- else
- {
- tst->arch.vex.guest_r55 = (Addr)&VG_(tilegx_linux_SUBST_FOR_rt_sigreturn);
- }
-
- priv->magicPI = 0x31415927;
- priv->sigNo_private = sigNo;
- priv->vex_shadow1 = tst->arch.vex_shadow1;
- priv->vex_shadow2 = tst->arch.vex_shadow2;
- /* Set the thread so it will next run the handler. */
- /* tst->m_sp = sp; also notify the tool we've updated SP */
- VG_TRACK( post_reg_write, Vg_CoreSignal, tid, VG_O_STACK_PTR, sizeof(Addr));
- if (VG_(clo_trace_signals))
- VG_(printf)("handler = %p\n", handler);
- tst->arch.vex.guest_pc = (Addr) handler;
- /* This thread needs to be marked runnable, but we leave that the
- caller to do. */
-}
-
-/* EXPORTED */
-void VG_(sigframe_destroy)( ThreadId tid, Bool isRT )
-{
- ThreadState *tst;
- struct vg_sig_private *priv1;
- Addr sp;
- UInt frame_size;
- struct vki_sigcontext *mc;
- Int sigNo;
- Bool has_siginfo = isRT;
-
- vg_assert(VG_(is_valid_tid)(tid));
- tst = VG_(get_ThreadState)(tid);
- sp = tst->arch.vex.guest_r54 + 8;
- if (has_siginfo)
- {
- struct rt_sigframe *frame = (struct rt_sigframe *)sp;
- struct vki_ucontext *ucp = &frame->rs_uc;
-
- if (0)
- VG_(printf)("destroy signal frame; sp = %lx, "
- " %pc = %lx, status=%d\n",
- (Addr)frame, tst->arch.vex.guest_pc, (Int)tst->status);
-
- frame_size = sizeof(*frame);
- mc = &ucp->uc_mcontext;
- priv1 = &frame->priv;
- vg_assert(priv1->magicPI == 0x31415927);
- sigNo = priv1->sigNo_private;
- }
- else
- {
- vg_assert(0);
- }
-
- //restore regs
- tst->arch.vex.guest_r0 = mc->gregs[0];
- tst->arch.vex.guest_r1 = mc->gregs[1];
- tst->arch.vex.guest_r2 = mc->gregs[2];
- tst->arch.vex.guest_r3 = mc->gregs[3];
- tst->arch.vex.guest_r4 = mc->gregs[4];
- tst->arch.vex.guest_r5 = mc->gregs[5];
- tst->arch.vex.guest_r6 = mc->gregs[6];
- tst->arch.vex.guest_r7 = mc->gregs[7];
- tst->arch.vex.guest_r8 = mc->gregs[8];
- tst->arch.vex.guest_r9 = mc->gregs[9];
- tst->arch.vex.guest_r10 = mc->gregs[10];
- tst->arch.vex.guest_r11 = mc->gregs[11];
- tst->arch.vex.guest_r12 = mc->gregs[12];
- tst->arch.vex.guest_r13 = mc->gregs[13];
- tst->arch.vex.guest_r14 = mc->gregs[14];
- tst->arch.vex.guest_r15 = mc->gregs[15];
- tst->arch.vex.guest_r16 = mc->gregs[16];
- tst->arch.vex.guest_r17 = mc->gregs[17];
- tst->arch.vex.guest_r18 = mc->gregs[18];
- tst->arch.vex.guest_r19 = mc->gregs[19];
- tst->arch.vex.guest_r20 = mc->gregs[20];
- tst->arch.vex.guest_r21 = mc->gregs[21];
- tst->arch.vex.guest_r22 = mc->gregs[22];
- tst->arch.vex.guest_r23 = mc->gregs[23];
- tst->arch.vex.guest_r24 = mc->gregs[24];
- tst->arch.vex.guest_r25 = mc->gregs[25];
- tst->arch.vex.guest_r26 = mc->gregs[26];
- tst->arch.vex.guest_r27 = mc->gregs[27];
- tst->arch.vex.guest_r28 = mc->gregs[28];
- tst->arch.vex.guest_r29 = mc->gregs[29];
- tst->arch.vex.guest_r30 = mc->gregs[30];
- tst->arch.vex.guest_r31 = mc->gregs[31];
- tst->arch.vex.guest_r32 = mc->gregs[32];
- tst->arch.vex.guest_r33 = mc->gregs[33];
- tst->arch.vex.guest_r34 = mc->gregs[34];
- tst->arch.vex.guest_r35 = mc->gregs[35];
- tst->arch.vex.guest_r36 = mc->gregs[36];
- tst->arch.vex.guest_r37 = mc->gregs[37];
- tst->arch.vex.guest_r38 = mc->gregs[38];
- tst->arch.vex.guest_r39 = mc->gregs[39];
- tst->arch.vex.guest_r40 = mc->gregs[40];
- tst->arch.vex.guest_r41 = mc->gregs[41];
- tst->arch.vex.guest_r42 = mc->gregs[42];
- tst->arch.vex.guest_r43 = mc->gregs[43];
- tst->arch.vex.guest_r44 = mc->gregs[44];
- tst->arch.vex.guest_r45 = mc->gregs[45];
- tst->arch.vex.guest_r46 = mc->gregs[46];
- tst->arch.vex.guest_r47 = mc->gregs[47];
- tst->arch.vex.guest_r48 = mc->gregs[48];
- tst->arch.vex.guest_r49 = mc->gregs[49];
- tst->arch.vex.guest_r50 = mc->gregs[50];
- tst->arch.vex.guest_r51 = mc->gregs[51];
- tst->arch.vex.guest_r52 = mc->gregs[52];
- tst->arch.vex.guest_r53 = mc->tp;
- tst->arch.vex.guest_r54 = mc->sp;
- tst->arch.vex.guest_r55 = mc->lr;
- tst->arch.vex.guest_pc = mc->pc;
-
- VG_TRACK(die_mem_stack_signal, sp, frame_size);
- if (VG_(clo_trace_signals))
- VG_(message)( Vg_DebugMsg,
- "VG_(signal_return) (thread %u): isRT=%d valid magic; EIP=%#x\n",
- tid, isRT, tst->arch.vex.guest_pc);
- /* tell the tools */
- VG_TRACK( post_deliver_signal, tid, sigNo );
-}
-
-#endif // defined(VGP_tilegx_linux)
-
-/*--------------------------------------------------------------------*/
-/*--- end sigframe-tilegx-linux.c ---*/
-/*--------------------------------------------------------------------*/
diff --git a/coregrind/m_sigframe/sigframe-x86-darwin.c b/coregrind/m_sigframe/sigframe-x86-darwin.c
index 2e6492f..f55afb0 100644
--- a/coregrind/m_sigframe/sigframe-x86-darwin.c
+++ b/coregrind/m_sigframe/sigframe-x86-darwin.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2006-2015 OpenWorks Ltd
+ Copyright (C) 2006-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_sigframe/sigframe-x86-linux.c b/coregrind/m_sigframe/sigframe-x86-linux.c
index 3a46bfd..27ca4c2 100644
--- a/coregrind/m_sigframe/sigframe-x86-linux.c
+++ b/coregrind/m_sigframe/sigframe-x86-linux.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Nicholas Nethercote
+ Copyright (C) 2000-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_signals.c b/coregrind/m_signals.c
index 168b681..a1749e2 100644
--- a/coregrind/m_signals.c
+++ b/coregrind/m_signals.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -566,21 +566,6 @@
(srP)->misc.MIPS64.r28 = (uc)->uc_mcontext.sc_regs[28]; \
}
-#elif defined(VGP_tilegx_linux)
-# define VG_UCONTEXT_INSTR_PTR(uc) ((uc)->uc_mcontext.pc)
-# define VG_UCONTEXT_STACK_PTR(uc) ((uc)->uc_mcontext.sp)
-# define VG_UCONTEXT_FRAME_PTR(uc) ((uc)->uc_mcontext.gregs[52])
-# define VG_UCONTEXT_SYSCALL_NUM(uc) ((uc)->uc_mcontext.gregs[10])
-# define VG_UCONTEXT_SYSCALL_SYSRES(uc) \
- /* Convert the value in uc_mcontext.rax into a SysRes. */ \
- VG_(mk_SysRes_tilegx_linux)((uc)->uc_mcontext.gregs[0])
-# define VG_UCONTEXT_TO_UnwindStartRegs(srP, uc) \
- { (srP)->r_pc = (uc)->uc_mcontext.pc; \
- (srP)->r_sp = (uc)->uc_mcontext.sp; \
- (srP)->misc.TILEGX.r52 = (uc)->uc_mcontext.gregs[52]; \
- (srP)->misc.TILEGX.r55 = (uc)->uc_mcontext.lr; \
- }
-
#elif defined(VGP_x86_solaris)
# define VG_UCONTEXT_INSTR_PTR(uc) ((Addr)(uc)->uc_mcontext.gregs[VKI_EIP])
# define VG_UCONTEXT_STACK_PTR(uc) ((Addr)(uc)->uc_mcontext.gregs[VKI_UESP])
@@ -994,14 +979,6 @@
" syscall\n" \
".previous\n"
-#elif defined(VGP_tilegx_linux)
-# define _MY_SIGRETURN(name) \
- ".text\n" \
- "my_sigreturn:\n" \
- " moveli r10 ," #name "\n" \
- " swint1\n" \
- ".previous\n"
-
#elif defined(VGP_x86_solaris) || defined(VGP_amd64_solaris)
/* Not used on Solaris. */
# define _MY_SIGRETURN(name) \
@@ -1667,6 +1644,7 @@
Bool core = False; /* kills process w/ core */
struct vki_rlimit corelim;
Bool could_core;
+ ThreadState* tst = VG_(get_ThreadState)(tid);
vg_assert(VG_(is_running_thread)(tid));
@@ -1728,6 +1706,14 @@
if (!terminate)
return; /* nothing to do */
+#if defined(VGO_linux)
+ if (terminate && (tst->ptrace & VKI_PT_PTRACED)
+ && (sigNo != VKI_SIGKILL)) {
+ VG_(kill)(VG_(getpid)(), VKI_SIGSTOP);
+ return;
+ }
+#endif
+
could_core = core;
if (core) {
@@ -1746,7 +1732,6 @@
if (VG_(clo_xml)) {
VG_(printf_xml)("<fatal_signal>\n");
VG_(printf_xml)(" <tid>%d</tid>\n", tid);
- ThreadState* tst = VG_(get_ThreadState)(tid);
if (tst->thread_name) {
VG_(printf_xml)(" <threadname>%s</threadname>\n",
tst->thread_name);
@@ -2186,7 +2171,7 @@
info.si_signo = VKI_SIGFPE;
info.si_code = code;
- if (VG_(gdbserver_report_signal) (VKI_SIGFPE, tid)) {
+ if (VG_(gdbserver_report_signal) (&info, tid)) {
resume_scheduler(tid);
deliver_signal(tid, &info, &uc);
}
@@ -2430,8 +2415,14 @@
info->si_code = sanitize_si_code(info->si_code);
if (VG_(clo_trace_signals))
- VG_(dmsg)("async signal handler: signal=%d, tid=%u, si_code=%d\n",
- sigNo, tid, info->si_code);
+ VG_(dmsg)("async signal handler: signal=%d, tid=%u, si_code=%d, "
+ "exitreason %s\n",
+ sigNo, tid, info->si_code,
+ VG_(name_of_VgSchedReturnCode)(tst->exitreason));
+
+ /* */
+ if (tst->exitreason == VgSrc_FatalSig)
+ resume_scheduler(tid);
/* Update thread state properly. The signal can only have been
delivered whilst we were in
@@ -2479,8 +2470,16 @@
);
/* (2) */
- /* Set up the thread's state to deliver a signal */
- if (!is_sig_ign(info, tid))
+ /* Set up the thread's state to deliver a signal.
+ However, if exitreason is VgSrc_FatalSig, then thread tid was
+ taken out of a syscall by VG_(nuke_all_threads_except).
+ But after the emission of VKI_SIGKILL, another (fatal) async
+ signal might be sent. In such a case, we must not handle this
+ signal, as the thread is supposed to die first.
+ => resume the scheduler for such a thread, so that the scheduler
+ can let the thread die. */
+ if (tst->exitreason != VgSrc_FatalSig
+ && !is_sig_ign(info, tid))
deliver_signal(tid, info, uc);
/* It's crucial that (1) and (2) happen in the order (1) then (2)
@@ -2946,6 +2945,20 @@
ThreadState *tst = VG_(get_ThreadState)(tid);
vki_sigset_t saved_mask;
+ if (tst->exitreason == VgSrc_FatalSig) {
+ /* This task has been requested to die due to a fatal signal
+ received by the process. So, we cannot poll new signals,
+ as we are supposed to die asap. If we would poll and deliver
+ a new (maybe fatal) signal, this could cause a deadlock, as
+ this thread would believe it has to terminate the other threads
+ and wait for them to die, while we already have a thread doing
+ that. */
+ if (VG_(clo_trace_signals))
+ VG_(dmsg)("poll_signals: not polling as thread %u is exitreason %s\n",
+ tid, VG_(name_of_VgSchedReturnCode)(tst->exitreason));
+ return;
+ }
+
/* look for all the signals this thread isn't blocking */
/* pollset = ~tst->sig_mask */
VG_(sigcomplementset)( &pollset, &tst->sig_mask );
@@ -2961,15 +2974,18 @@
/* If there was nothing queued, ask the kernel for a pending signal */
if (sip == NULL && VG_(sigtimedwait_zero)(&pollset, &si) > 0) {
if (VG_(clo_trace_signals))
- VG_(dmsg)("poll_signals: got signal %d for thread %u\n",
- si.si_signo, tid);
+ VG_(dmsg)("poll_signals: got signal %d for thread %u exitreason %s\n",
+ si.si_signo, tid,
+ VG_(name_of_VgSchedReturnCode)(tst->exitreason));
sip = &si;
}
if (sip != NULL) {
/* OK, something to do; deliver it */
if (VG_(clo_trace_signals))
- VG_(dmsg)("Polling found signal %d for tid %u\n", sip->si_signo, tid);
+ VG_(dmsg)("Polling found signal %d for tid %u exitreason %s\n",
+ sip->si_signo, tid,
+ VG_(name_of_VgSchedReturnCode)(tst->exitreason));
if (!is_sig_ign(sip, tid))
deliver_signal(tid, sip, NULL);
else if (VG_(clo_trace_signals))
@@ -3073,7 +3089,8 @@
}
if (VG_(clo_trace_signals))
- VG_(dmsg)("Max kernel-supported signal is %d\n", VG_(max_signal));
+ VG_(dmsg)("Max kernel-supported signal is %d, VG_SIGVGKILL is %d\n",
+ VG_(max_signal), VG_SIGVGKILL);
/* Our private internal signals are treated as ignored */
scss.scss_per_sig[VG_SIGVGKILL].scss_handler = VKI_SIG_IGN;
diff --git a/coregrind/m_sparsewa.c b/coregrind/m_sparsewa.c
index a8a845d..8b3caab 100644
--- a/coregrind/m_sparsewa.c
+++ b/coregrind/m_sparsewa.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2015 OpenWorks Ltd
+ Copyright (C) 2008-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_stacks.c b/coregrind/m_stacks.c
index aac5ebf..560c756 100644
--- a/coregrind/m_stacks.c
+++ b/coregrind/m_stacks.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -37,6 +37,10 @@
#include "pub_core_options.h"
#include "pub_core_stacks.h"
#include "pub_core_tooliface.h"
+#include "pub_core_inner.h"
+#if defined(ENABLE_INNER_CLIENT_REQUEST)
+#include "pub_core_clreq.h"
+#endif
// For expensive debugging
#define EDEBUG(fmt, args...) //VG_(debugLog)(2, "stacks", fmt, ## args)
@@ -91,6 +95,8 @@
Addr start; // Lowest stack byte, included.
Addr end; // Highest stack byte, included.
struct _Stack *next;
+ UWord outer_id; /* For an inner valgrind, stack id registered in outer
+ valgrind. */
} Stack;
static Stack *stacks;
@@ -205,7 +211,7 @@
VG_(debugLog)(2, "stacks", "register [start-end] [%p-%p] as stack %lu\n",
(void*)start, (void*)end, i->id);
-
+ INNER_REQUEST(i->outer_id = VALGRIND_STACK_REGISTER(start, end));
return i->id;
}
@@ -231,6 +237,7 @@
} else {
prev->next = i->next;
}
+ INNER_REQUEST(VALGRIND_STACK_DEREGISTER(i->outer_id));
VG_(free)(i);
return;
}
@@ -257,6 +264,7 @@
/* FIXME : swap start/end like VG_(register_stack) ??? */
i->start = start;
i->end = end;
+ INNER_REQUEST(VALGRIND_STACK_CHANGE(i->outer_id, start, end));
return;
}
i = i->next;
diff --git a/coregrind/m_stacktrace.c b/coregrind/m_stacktrace.c
index ef4984c..41064af 100644
--- a/coregrind/m_stacktrace.c
+++ b/coregrind/m_stacktrace.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -1468,214 +1468,6 @@
#endif
-/* ------------------------ tilegx ------------------------- */
-#if defined(VGP_tilegx_linux)
-UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known,
- /*OUT*/Addr* ips, UInt max_n_ips,
- /*OUT*/Addr* sps, /*OUT*/Addr* fps,
- const UnwindStartRegs* startRegs,
- Addr fp_max_orig )
-{
- Bool debug = False;
- Int i;
- Addr fp_max;
- UInt n_found = 0;
- const Int cmrf = VG_(clo_merge_recursive_frames);
-
- vg_assert(sizeof(Addr) == sizeof(UWord));
- vg_assert(sizeof(Addr) == sizeof(void*));
-
- D3UnwindRegs uregs;
- uregs.pc = startRegs->r_pc;
- uregs.sp = startRegs->r_sp;
- Addr fp_min = uregs.sp - VG_STACK_REDZONE_SZB;
-
- uregs.fp = startRegs->misc.TILEGX.r52;
- uregs.lr = startRegs->misc.TILEGX.r55;
-
- fp_max = VG_PGROUNDUP(fp_max_orig);
- if (fp_max >= sizeof(Addr))
- fp_max -= sizeof(Addr);
-
- if (debug)
- VG_(printf)("max_n_ips=%u fp_min=0x%lx fp_max_orig=0x%lx, "
- "fp_max=0x%lx pc=0x%lx sp=0x%lx fp=0x%lx\n",
- max_n_ips, fp_min, fp_max_orig, fp_max,
- uregs.pc, uregs.sp, uregs.fp);
-
- if (sps) sps[0] = uregs.sp;
- if (fps) fps[0] = uregs.fp;
- ips[0] = uregs.pc;
- i = 1;
-
- /* Loop unwinding the stack. */
- while (True) {
- if (debug) {
- VG_(printf)("i: %d, pc: 0x%lx, sp: 0x%lx, lr: 0x%lx\n",
- i, uregs.pc, uregs.sp, uregs.lr);
- }
- if (i >= max_n_ips)
- break;
-
- D3UnwindRegs uregs_copy = uregs;
- if (VG_(use_CF_info)( &uregs, fp_min, fp_max )) {
- if (debug)
- VG_(printf)("USING CFI: pc: 0x%lx, sp: 0x%lx, fp: 0x%lx, lr: 0x%lx\n",
- uregs.pc, uregs.sp, uregs.fp, uregs.lr);
- if (0 != uregs.pc && 1 != uregs.pc &&
- (uregs.pc < fp_min || uregs.pc > fp_max)) {
- if (sps) sps[i] = uregs.sp;
- if (fps) fps[i] = uregs.fp;
- if (uregs.pc != uregs_copy.pc && uregs.sp != uregs_copy.sp)
- ips[i++] = uregs.pc - 8;
- uregs.pc = uregs.pc - 8;
- RECURSIVE_MERGE(cmrf,ips,i);
- continue;
- } else
- uregs = uregs_copy;
- }
-
- Long frame_offset = 0;
- PtrdiffT offset;
- if (VG_(get_inst_offset_in_function)(uregs.pc, &offset)) {
- Addr start_pc = uregs.pc;
- Addr limit_pc = uregs.pc - offset;
- Addr cur_pc;
- /* Try to find any stack adjustment from current instruction
- bundles downward. */
- for (cur_pc = start_pc; cur_pc > limit_pc; cur_pc -= 8) {
- ULong inst;
- Long off = 0;
- ULong* cur_inst;
- /* Fetch the instruction. */
- cur_inst = (ULong *)cur_pc;
- inst = *cur_inst;
- if(debug)
- VG_(printf)("cur_pc: 0x%lx, inst: 0x%lx\n", cur_pc, inst);
-
- if ((inst & 0xC000000000000000ULL) == 0) {
- /* Bundle is X type. */
- if ((inst & 0xC000000070000fffULL) ==
- (0x0000000010000db6ULL)) {
- /* addli at X0 */
- off = (short)(0xFFFF & (inst >> 12));
- } else if ((inst & 0xF80007ff80000000ULL) ==
- (0x000006db00000000ULL)) {
- /* addli at X1 addli*/
- off = (short)(0xFFFF & (inst >> 43));
- } else if ((inst & 0xC00000007FF00FFFULL) ==
- (0x0000000040100db6ULL)) {
- /* addi at X0 */
- off = (char)(0xFF & (inst >> 12));
- } else if ((inst & 0xFFF807ff80000000ULL) ==
- (0x180806db00000000ULL)) {
- /* addi at X1 */
- off = (char)(0xFF & (inst >> 43));
- }
- } else {
- /* Bundle is Y type. */
- if ((inst & 0x0000000078000FFFULL) ==
- (0x0000000000000db6ULL)) {
- /* addi at Y0 */
- off = (char)(0xFF & (inst >> 12));
- } else if ((inst & 0x3C0007FF80000000ULL) ==
- (0x040006db00000000ULL)) {
- /* addi at Y1 */
- off = (char)(0xFF & (inst >> 43));
- }
- }
-
- if(debug && off)
- VG_(printf)("offset: -0x%lx\n", -off);
-
- if (off < 0) {
- /* frame offset should be modular of 8 */
- vg_assert((off & 7) == 0);
- frame_offset += off;
- } else if (off > 0)
- /* Exit loop if a positive stack adjustment is found, which
- usually means that the stack cleanup code in the function
- epilogue is reached. */
- break;
- }
- }
-
- if (frame_offset < 0) {
- if (0 == uregs.pc || 1 == uregs.pc) break;
-
- /* Subtract the offset from the current stack. */
- uregs.sp = uregs.sp + (ULong)(-frame_offset);
-
- if (debug)
- VG_(printf)("offset: i: %d, pc: 0x%lx, sp: 0x%lx, lr: 0x%lx\n",
- i, uregs.pc, uregs.sp, uregs.lr);
-
- if (uregs.pc == uregs.lr - 8 ||
- uregs.lr - 8 >= fp_min && uregs.lr - 8 <= fp_max) {
- if (debug)
- VG_(printf)("new lr = 0x%lx\n", *(ULong*)uregs.sp);
- uregs.lr = *(ULong*)uregs.sp;
- }
-
- uregs.pc = uregs.lr - 8;
-
- if (uregs.lr != 0) {
- /* Avoid the invalid pc = 0xffff...ff8 */
- if (sps)
- sps[i] = uregs.sp;
-
- if (fps)
- fps[i] = fps[0];
-
- ips[i++] = uregs.pc;
-
- RECURSIVE_MERGE(cmrf,ips,i);
- }
- continue;
- }
-
- /* A special case for the 1st frame. Assume it was a bad jump.
- Use the link register "lr" and current stack and frame to
- try again. */
- if (i == 1) {
- if (sps) {
- sps[1] = sps[0];
- uregs.sp = sps[0];
- }
- if (fps) {
- fps[1] = fps[0];
- uregs.fp = fps[0];
- }
- if (0 == uregs.lr || 1 == uregs.lr)
- break;
-
- uregs.pc = uregs.lr - 8;
- ips[i++] = uregs.lr - 8;
- RECURSIVE_MERGE(cmrf,ips,i);
- continue;
- }
- /* No luck. We have to give up. */
- break;
- }
-
- if (debug) {
- /* Display the back trace. */
- Int ii ;
- for ( ii = 0; ii < i; ii++) {
- if (sps) {
- VG_(printf)("%d: pc=%lx ", ii, ips[ii]);
- VG_(printf)("sp=%lx\n", sps[ii]);
- } else {
- VG_(printf)("%d: pc=%lx\n", ii, ips[ii]);
- }
- }
- }
-
- n_found = i;
- return n_found;
-}
-#endif
-
/*------------------------------------------------------------*/
/*--- ---*/
/*--- END platform-dependent unwinder worker functions ---*/
@@ -1797,28 +1589,25 @@
StackTrace ips, UInt n_ips
)
{
- Bool main_done = False;
- Int i = 0;
+ Int i;
vg_assert(n_ips > 0);
- do {
- Addr ip = ips[i];
-
- // Stop after the first appearance of "main" or one of the other names
- // (the appearance of which is a pretty good sign that we've gone past
- // main without seeing it, for whatever reason)
- if ( ! VG_(clo_show_below_main) ) {
- Vg_FnNameKind kind = VG_(get_fnname_kind_from_IP)(ip);
- if (Vg_FnNameMain == kind || Vg_FnNameBelowMain == kind) {
- main_done = True;
- }
+ if ( ! VG_(clo_show_below_main) ) {
+ // Search (from the outer frame onwards) the appearance of "main"
+ // or the last appearance of a below main function.
+ // Then decrease n_ips so as to not call action for the below main
+ for (i = n_ips - 1; i >= 0; i--) {
+ Vg_FnNameKind kind = VG_(get_fnname_kind_from_IP)(ips[i]);
+ if (Vg_FnNameMain == kind || Vg_FnNameBelowMain == kind)
+ n_ips = i + 1;
+ if (Vg_FnNameMain == kind)
+ break;
}
+ }
+ for (i = 0; i < n_ips; i++)
// Act on the ip
- action(i, ip, opaque);
-
- i++;
- } while (i < n_ips && !main_done);
+ action(i, ips[i], opaque);
}
diff --git a/coregrind/m_syscall.c b/coregrind/m_syscall.c
index 308fcfe..3569948 100644
--- a/coregrind/m_syscall.c
+++ b/coregrind/m_syscall.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -131,17 +131,6 @@
return res;
}
-SysRes VG_(mk_SysRes_tilegx_linux) ( Long val ) {
- SysRes res;
- res._isError = val >= -4095 && val <= -1;
- if (res._isError) {
- res._val = (ULong)(-val);
- } else {
- res._val = (ULong)val;
- }
- return res;
-}
-
/* PPC uses the CR7.SO bit to flag an error (CR0 in IBM-speak) */
/* Note this must be in the bottom bit of the second arg */
SysRes VG_(mk_SysRes_ppc32_linux) ( UInt val, UInt cr0so ) {
@@ -790,65 +779,51 @@
int a4, int a5, int a6, int syscall_no, UWord *err,
UWord *valHi, UWord* valLo
);
-asm(
-".globl do_syscall_WRK\n"
-".ent do_syscall_WRK\n"
-".text\n"
-"do_syscall_WRK:\n"
-" lw $2, 24($29)\n"
-" syscall\n"
-" lw $8, 28($29)\n"
-" sw $7, ($8)\n"
-" lw $8, 32($29)\n"
-" sw $3, ($8)\n" // store valHi
-" lw $8, 36($29)\n"
-" sw $2, ($8)\n" // store valLo
-" jr $31\n"
-" nop\n"
-".previous\n"
-".end do_syscall_WRK\n"
+asm (
+ ".text \n\t"
+ ".globl do_syscall_WRK \n\t"
+ ".type do_syscall_WRK, @function \n\t"
+ ".set push \n\t"
+ ".set noreorder \n\t"
+ "do_syscall_WRK: \n\t"
+ " lw $2, 24($29) \n\t"
+ " syscall \n\t"
+ " lw $8, 28($29) \n\t"
+ " sw $7, ($8) \n\t"
+ " lw $8, 32($29) \n\t"
+ " sw $3, ($8) \n\t" /* store valHi */
+ " lw $8, 36($29) \n\t"
+ " jr $31 \n\t"
+ " sw $2, ($8) \n\t" /* store valLo */
+ ".size do_syscall_WRK, .-do_syscall_WRK \n\t"
+ ".set pop \n\t"
+ ".previous \n\t"
);
#elif defined(VGP_mips64_linux)
extern UWord do_syscall_WRK ( UWord a1, UWord a2, UWord a3, UWord a4, UWord a5,
- UWord a6, UWord syscall_no, ULong* V1_val );
+ UWord a6, UWord syscall_no, ULong* V1_A3_val );
asm (
-".text\n"
-".globl do_syscall_WRK\n"
-"do_syscall_WRK:\n"
-" daddiu $29, $29, -8\n"
-" sd $11, 0($29)\n"
-" move $2, $10\n"
-" syscall\n"
-" ld $11, 0($29)\n"
-" daddiu $29, $29, 8\n"
-" sd $3, 0($11)\n" /* store vale of v1 in last param */
-" sd $7, 8($11)\n" /* store vale of a3 in last param */
-" jr $31\n"
-".previous\n"
+ ".text \n\t"
+ ".globl do_syscall_WRK \n\t"
+ ".type do_syscall_WRK, @function \n\t"
+ ".set push \n\t"
+ ".set noreorder \n\t"
+ "do_syscall_WRK: \n\t"
+ " daddiu $29, $29, -8 \n\t"
+ " sd $11, 0($29) \n\t"
+ " move $2, $10 \n\t"
+ " syscall \n\t"
+ " ld $11, 0($29) \n\t"
+ " daddiu $29, $29, 8 \n\t"
+ " sd $3, 0($11) \n\t" /* store v1 in last param */
+ " jr $31 \n\t"
+ " sd $7, 8($11) \n\t" /* store a3 in last param */
+ ".size do_syscall_WRK, .-do_syscall_WRK \n\t"
+ ".set pop \n\t"
+ ".previous \n\t"
);
-#elif defined(VGP_tilegx_linux)
-extern UWord do_syscall_WRK (
- UWord syscall_no,
- UWord a1, UWord a2, UWord a3,
- UWord a4, UWord a5, UWord a6
- );
-asm(
- ".text\n"
- "do_syscall_WRK:\n"
- "move r10, r0\n"
- "move r0, r1\n"
- "move r1, r2\n"
- "move r2, r3\n"
- "move r3, r4\n"
- "move r4, r5\n"
- "move r5, r6\n"
- "swint1\n"
- "jrp lr\n"
- ".previous\n"
- );
-
#elif defined(VGP_x86_solaris)
extern ULong
@@ -1064,11 +1039,6 @@
ULong A3 = (ULong)v1_a3[1];
return VG_(mk_SysRes_mips64_linux)( V0, V1, A3 );
-# elif defined(VGP_tilegx_linux)
- UWord val = do_syscall_WRK(sysno,a1,a2,a3,a4,a5,a6);
-
- return VG_(mk_SysRes_tilegx_linux)( val );
-
# elif defined(VGP_x86_solaris)
UInt val, val2, err = False;
Bool restart;
diff --git a/coregrind/m_syswrap/priv_syswrap-darwin.h b/coregrind/m_syswrap/priv_syswrap-darwin.h
index 62784e9..4755e71 100644
--- a/coregrind/m_syswrap/priv_syswrap-darwin.h
+++ b/coregrind/m_syswrap/priv_syswrap-darwin.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Apple Inc.
+ Copyright (C) 2005-2017 Apple Inc.
Greg Parker gparker@apple.com
This program is free software; you can redistribute it and/or
@@ -234,8 +234,12 @@
// old getdents
// old gc_control
// NYI add_profil 176
-// 177
-// 178
+#if DARWIN_VERS >= DARWIN_10_12
+// NYI kdebug_typefilter // 177
+#endif /* DARWIN_VERS >= DARWIN_10_12 */
+#if DARWIN_VERS >= DARWIN_10_11
+// NYI kdebug_trace_string // 178
+#endif /* DARWIN_VERS >= DARWIN_10_11 */
// 179
DECL_TEMPLATE(darwin, kdebug_trace); // 180
// GEN setgid 181
@@ -463,7 +467,9 @@
DECL_TEMPLATE(darwin, __thread_selfid); // 372
#endif
// 373
-// 374
+#if DARWIN_VERS >= DARWIN_10_11
+// NYI kevent_qos // 374
+#endif /* DARWIN_VERS >= DARWIN_10_11 */
// 375
// 376
// 377
@@ -555,15 +561,19 @@
// NYI coalition_info // 459
DECL_TEMPLATE(darwin, necp_match_policy); // 460
DECL_TEMPLATE(darwin, getattrlistbulk); // 461
-// 462
+#endif /* DARWIN_VERS >= DARWIN_10_10 */
+#if DARWIN_VERS >= DARWIN_10_12
+// NYI clonefileat // 462
+#endif /* DARWIN_VERS >= DARWIN_10_12 */
+#if DARWIN_VERS >= DARWIN_10_10
// NYI openat // 463
// NYI openat_nocancel // 464
// NYI renameat // 465
-// NYI faccessat // 466
+DECL_TEMPLATE(darwin, faccessat); // 466
// NYI fchmodat // 467
// NYI fchownat // 468
// NYI fstatat // 469
-// NYI fstatat64 // 470
+DECL_TEMPLATE(darwin, fstatat64); // 470
// NYI linkat // 471
// NYI unlinkat // 472
DECL_TEMPLATE(darwin, readlinkat); // 473
@@ -576,14 +586,50 @@
// NYI recvmsg_x // 480
// NYI sendmsg_x // 481
// NYI thread_selfusage // 482
-// NYI csrctl // 483
+DECL_TEMPLATE(darwin, csrctl); // 483
DECL_TEMPLATE(darwin, guarded_open_dprotected_np); // 484
DECL_TEMPLATE(darwin, guarded_write_np); // 485
DECL_TEMPLATE(darwin, guarded_pwrite_np); // 486
DECL_TEMPLATE(darwin, guarded_writev_np); // 487
-// NYI rename_ext // 488
+// NYI renameatx_np // 488
// NYI mremap_encrypted // 489
#endif /* DARWIN_VERS >= DARWIN_10_10 */
+#if DARWIN_VERS >= DARWIN_10_11
+// NYI netagent_trigger // 490
+// NYI stack_snapshot_with_config // 491
+// NYI microstackshot // 492
+// NYI grab_pgo_data // 493
+// NYI persona // 494
+// 495
+// 496
+// 497
+// 498
+// NYI work_interval_ctl // 499
+#endif /* DARWIN_VERS >= DARWIN_10_11 */
+#if DARWIN_VERS >= DARWIN_10_12
+DECL_TEMPLATE(darwin, getentropy); // 500
+// NYI necp_open // 501
+// NYI necp_client_action // 502
+// 503
+// 504
+// 505
+// 506
+// 507
+// 508
+// 509
+// 510
+// 511
+// 512
+// 513
+// 514
+// NYI ulock_wait // 515
+DECL_TEMPLATE(darwin, ulock_wake); // 516
+// NYI fclonefileat // 517
+// NYI fs_snapshot // 518
+// 519
+// NYI terminate_with_payload // 520
+// NYI abort_with_payload // 521
+#endif /* DARWIN_VERS >= DARWIN_10_12 */
// Mach message helpers
DECL_TEMPLATE(darwin, mach_port_set_context);
@@ -699,6 +745,13 @@
DECL_TEMPLATE(darwin, semaphore_timedwait_signal);
DECL_TEMPLATE(darwin, task_for_pid);
DECL_TEMPLATE(darwin, pid_for_task);
+
+#if DARWIN_VERS >= DARWIN_10_12
+DECL_TEMPLATE(darwin, host_create_mach_voucher_trap);
+DECL_TEMPLATE(darwin, task_register_dyld_image_infos);
+DECL_TEMPLATE(darwin, task_register_dyld_shared_cache_image_info);
+#endif /* DARWIN_VERS >= DARWIN_10_12 */
+
DECL_TEMPLATE(darwin, mach_timebase_info);
DECL_TEMPLATE(darwin, mach_wait_until);
DECL_TEMPLATE(darwin, mk_timer_create);
diff --git a/coregrind/m_syswrap/priv_syswrap-generic.h b/coregrind/m_syswrap/priv_syswrap-generic.h
index 029260f..66c8c40 100644
--- a/coregrind/m_syswrap/priv_syswrap-generic.h
+++ b/coregrind/m_syswrap/priv_syswrap-generic.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_syswrap/priv_syswrap-linux-variants.h b/coregrind/m_syswrap/priv_syswrap-linux-variants.h
index 66cdaa6..5677245 100644
--- a/coregrind/m_syswrap/priv_syswrap-linux-variants.h
+++ b/coregrind/m_syswrap/priv_syswrap-linux-variants.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_syswrap/priv_syswrap-linux.h b/coregrind/m_syswrap/priv_syswrap-linux.h
index 162f8e5..5b5c8ef 100644
--- a/coregrind/m_syswrap/priv_syswrap-linux.h
+++ b/coregrind/m_syswrap/priv_syswrap-linux.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Nicholas Nethercote
+ Copyright (C) 2000-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -39,12 +39,10 @@
extern Addr ML_(allocstack) ( ThreadId tid );
extern void ML_(call_on_new_stack_0_1) ( Addr stack, Addr retaddr,
void (*f)(Word), Word arg1 );
-extern SysRes ML_(do_fork_clone) ( ThreadId tid, UInt flags,
- Int* parent_tidptr, Int* child_tidptr );
-
// Linux-specific (but non-arch-specific) syscalls
+DECL_TEMPLATE(linux, sys_clone)
DECL_TEMPLATE(linux, sys_mount);
DECL_TEMPLATE(linux, sys_oldumount);
DECL_TEMPLATE(linux, sys_umount);
@@ -61,6 +59,10 @@
DECL_TEMPLATE(linux, sys_readahead);
DECL_TEMPLATE(linux, sys_move_pages);
+// clone is similar enough between linux variants to have a generic
+// version, but which will call an extern defined in syswrap-<platform>-linux.c
+DECL_TEMPLATE(linux, sys_clone);
+
// POSIX, but various sub-cases differ between Linux and Darwin.
DECL_TEMPLATE(linux, sys_fcntl);
DECL_TEMPLATE(linux, sys_fcntl64);
@@ -271,6 +273,7 @@
// Linux specific (kernel modules)
DECL_TEMPLATE(linux, sys_init_module);
+DECL_TEMPLATE(linux, sys_finit_module);
DECL_TEMPLATE(linux, sys_delete_module);
// Linux-specific (oprofile-related)
@@ -316,6 +319,7 @@
// Linux-specific (but non-arch-specific) ptrace wrapper helpers
extern void ML_(linux_PRE_getregset) ( ThreadId, long, long );
extern void ML_(linux_PRE_setregset) ( ThreadId, long, long );
+extern void ML_(linux_POST_traceme) ( ThreadId );
extern void ML_(linux_POST_getregset)( ThreadId, long, long );
#undef TId
@@ -337,7 +341,7 @@
DECL_TEMPLATE(linux, sys_semctl);
DECL_TEMPLATE(linux, sys_semtimedop);
/* Shared memory */
-DECL_TEMPLATE(linux, wrap_sys_shmat);
+DECL_TEMPLATE(linux, sys_shmat);
DECL_TEMPLATE(linux, sys_shmget);
DECL_TEMPLATE(linux, sys_shmdt);
DECL_TEMPLATE(linux, sys_shmctl);
@@ -368,6 +372,75 @@
DECL_TEMPLATE(linux, sys_socketpair);
DECL_TEMPLATE(linux, sys_kcmp);
+// Some arch specific functions called from syswrap-linux.c
+extern Int do_syscall_clone_x86_linux ( Word (*fn)(void *),
+ void* stack,
+ Int flags,
+ void* arg,
+ Int* child_tid,
+ Int* parent_tid,
+ void* tls_ptr);
+extern SysRes ML_(x86_sys_set_thread_area) ( ThreadId tid,
+ vki_modify_ldt_t* info );
+extern void ML_(x86_setup_LDT_GDT) ( /*OUT*/ ThreadArchState *child,
+ /*IN*/ ThreadArchState *parent );
+
+extern Long do_syscall_clone_amd64_linux ( Word (*fn)(void *),
+ void* stack,
+ Long flags,
+ void* arg,
+ Int* child_tid,
+ Int* parent_tid,
+ void* tls_ptr);
+extern ULong do_syscall_clone_ppc32_linux ( Word (*fn)(void *),
+ void* stack,
+ Int flags,
+ void* arg,
+ Int* child_tid,
+ Int* parent_tid,
+ void* tls_ptr);
+extern ULong do_syscall_clone_ppc64_linux ( Word (*fn)(void *),
+ void* stack,
+ Int flags,
+ void* arg,
+ Int* child_tid,
+ Int* parent_tid,
+ void* tls_ptr );
+extern ULong do_syscall_clone_s390x_linux ( void *stack,
+ ULong flags,
+ Int *parent_tid,
+ Int *child_tid,
+ void* tls_ptr,
+ Word (*fn)(void *),
+ void *arg);
+extern Long do_syscall_clone_arm64_linux ( Word (*fn)(void *),
+ void* stack,
+ Long flags,
+ void* arg,
+ Int* child_tid,
+ Int* parent_tid,
+ void* tls_ptr );
+extern ULong do_syscall_clone_arm_linux ( Word (*fn)(void *),
+ void* stack,
+ Int flags,
+ void* arg,
+ Int* child_tid,
+ Int* parent_tid,
+ void* tls_ptr );
+extern ULong do_syscall_clone_mips64_linux ( Word (*fn) (void *), /* a0 - 4 */
+ void* stack, /* a1 - 5 */
+ Int flags, /* a2 - 6 */
+ void* arg, /* a3 - 7 */
+ Int* parent_tid, /* a4 - 8 */
+ void* tls_ptr, /* a5 - 9 */
+ Int* child_tid ); /* a6 - 10 */
+extern UInt do_syscall_clone_mips_linux ( Word (*fn) (void *), //a0 0 32
+ void* stack, //a1 4 36
+ Int flags, //a2 8 40
+ void* arg, //a3 12 44
+ Int* child_tid, //stack 16 48
+ Int* parent_tid, //stack 20 52
+ void* tls_ptr); //stack 24 56
#endif // __PRIV_SYSWRAP_LINUX_H
/*--------------------------------------------------------------------*/
diff --git a/coregrind/m_syswrap/priv_syswrap-main.h b/coregrind/m_syswrap/priv_syswrap-main.h
index 3164c81..13b7b5b 100644
--- a/coregrind/m_syswrap/priv_syswrap-main.h
+++ b/coregrind/m_syswrap/priv_syswrap-main.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Nicholas Nethercote
+ Copyright (C) 2000-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_syswrap/priv_syswrap-solaris.h b/coregrind/m_syswrap/priv_syswrap-solaris.h
index 3c30e49..76f6cf3 100644
--- a/coregrind/m_syswrap/priv_syswrap-solaris.h
+++ b/coregrind/m_syswrap/priv_syswrap-solaris.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2015 Petr Pavlu
+ Copyright (C) 2011-2017 Petr Pavlu
setup@dagobah.cz
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_syswrap/priv_syswrap-xen.h b/coregrind/m_syswrap/priv_syswrap-xen.h
index 696dda5..1234c8e 100644
--- a/coregrind/m_syswrap/priv_syswrap-xen.h
+++ b/coregrind/m_syswrap/priv_syswrap-xen.h
@@ -6,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2012-2015 Citrix Systems
+ Copyright (C) 2012-2017 Citrix Systems
ian.campbell@citrix.com
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_syswrap/priv_types_n_macros.h b/coregrind/m_syswrap/priv_types_n_macros.h
index 0eacfc7..62ad65a 100644
--- a/coregrind/m_syswrap/priv_types_n_macros.h
+++ b/coregrind/m_syswrap/priv_types_n_macros.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -93,8 +93,7 @@
|| defined(VGP_ppc32_linux) \
|| defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
|| defined(VGP_arm_linux) || defined(VGP_s390x_linux) \
- || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) \
- || defined(VGP_tilegx_linux)
+ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux)
Int o_arg1;
Int o_arg2;
Int o_arg3;
@@ -110,7 +109,7 @@
Int o_arg4;
Int s_arg5;
Int s_arg6;
- Int uu_arg7;
+ Int s_arg7;
Int uu_arg8;
# elif defined(VGP_x86_darwin) || defined(VGP_x86_solaris)
Int s_arg1;
@@ -181,16 +180,7 @@
fixed sized table exposed to the caller, but that's too inflexible;
hence now use a function which can do arbitrary messing around to
find the required entry. */
-#if defined(VGP_mips32_linux)
- /* Up to 6 parameters, 4 in registers 2 on stack. */
-# define PRA1(s,t,a) PRRAn(1,s,t,a)
-# define PRA2(s,t,a) PRRAn(2,s,t,a)
-# define PRA3(s,t,a) PRRAn(3,s,t,a)
-# define PRA4(s,t,a) PRRAn(4,s,t,a)
-# define PRA5(s,t,a) PSRAn(5,s,t,a)
-# define PRA6(s,t,a) PSRAn(6,s,t,a)
-#endif
#if defined(VGO_linux)
extern
SyscallTableEntry* ML_(get_linux_syscall_entry)( UInt sysno );
@@ -407,6 +397,7 @@
# define PRA4(s,t,a) PRRAn(4,s,t,a)
# define PRA5(s,t,a) PSRAn(5,s,t,a)
# define PRA6(s,t,a) PSRAn(6,s,t,a)
+# define PRA7(s,t,a) PSRAn(7,s,t,a)
#elif defined(VGO_linux) && !defined(VGP_mips32_linux)
/* Up to 6 parameters, all in registers. */
@@ -637,6 +628,19 @@
#define POST_FIELD_WRITE(zzfield) \
POST_MEM_WRITE((UWord)&zzfield, sizeof(zzfield))
+// Macros to support 64-bit syscall args split into two 32 bit values
+#define LOHI64(lo,hi) ( ((ULong)(lo)) | (((ULong)(hi)) << 32) )
+#if defined(VG_LITTLEENDIAN)
+#define MERGE64(lo,hi) ( ((ULong)(lo)) | (((ULong)(hi)) << 32) )
+#define MERGE64_FIRST(name) name##_low
+#define MERGE64_SECOND(name) name##_high
+#elif defined(VG_BIGENDIAN)
+#define MERGE64(hi,lo) ( ((ULong)(lo)) | (((ULong)(hi)) << 32) )
+#define MERGE64_FIRST(name) name##_high
+#define MERGE64_SECOND(name) name##_low
+#else
+#error Unknown endianness
+#endif
#endif // __PRIV_TYPES_N_MACROS_H
diff --git a/coregrind/m_syswrap/syscall-amd64-darwin.S b/coregrind/m_syswrap/syscall-amd64-darwin.S
index 6f1652b..3e0fd26 100644
--- a/coregrind/m_syswrap/syscall-amd64-darwin.S
+++ b/coregrind/m_syswrap/syscall-amd64-darwin.S
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_syswrap/syscall-amd64-linux.S b/coregrind/m_syswrap/syscall-amd64-linux.S
index 80cc75c..e2eb77f 100644
--- a/coregrind/m_syswrap/syscall-amd64-linux.S
+++ b/coregrind/m_syswrap/syscall-amd64-linux.S
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_syswrap/syscall-amd64-solaris.S b/coregrind/m_syswrap/syscall-amd64-solaris.S
index e04503e..391c48d 100644
--- a/coregrind/m_syswrap/syscall-amd64-solaris.S
+++ b/coregrind/m_syswrap/syscall-amd64-solaris.S
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2014-2015 Petr Pavlu
+ Copyright (C) 2014-2017 Petr Pavlu
setup@dagobah.cz
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_syswrap/syscall-arm-linux.S b/coregrind/m_syswrap/syscall-arm-linux.S
index 9e020f9..5d4f17b 100644
--- a/coregrind/m_syswrap/syscall-arm-linux.S
+++ b/coregrind/m_syswrap/syscall-arm-linux.S
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2015 Evan Geller (gaze@bea.ms)
+ Copyright (C) 2008-2017 Evan Geller (gaze@bea.ms)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/m_syswrap/syscall-arm64-linux.S b/coregrind/m_syswrap/syscall-arm64-linux.S
index 2306ade..0c91555 100644
--- a/coregrind/m_syswrap/syscall-arm64-linux.S
+++ b/coregrind/m_syswrap/syscall-arm64-linux.S
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2013-2015 OpenWorks
+ Copyright (C) 2013-2017 OpenWorks
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_syswrap/syscall-mips32-linux.S b/coregrind/m_syswrap/syscall-mips32-linux.S
index 8545976..0bbfb2b 100644
--- a/coregrind/m_syswrap/syscall-mips32-linux.S
+++ b/coregrind/m_syswrap/syscall-mips32-linux.S
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 RT-RK
+ Copyright (C) 2010-2017 RT-RK
mips-valgrind@rt-rk.com
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_syswrap/syscall-mips64-linux.S b/coregrind/m_syswrap/syscall-mips64-linux.S
index 6600878..8cc2ac0 100644
--- a/coregrind/m_syswrap/syscall-mips64-linux.S
+++ b/coregrind/m_syswrap/syscall-mips64-linux.S
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 RT-RK
+ Copyright (C) 2010-2017 RT-RK
mips-valgrind@rt-rk.com
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_syswrap/syscall-ppc32-linux.S b/coregrind/m_syswrap/syscall-ppc32-linux.S
index 6213922..a1ebe92 100644
--- a/coregrind/m_syswrap/syscall-ppc32-linux.S
+++ b/coregrind/m_syswrap/syscall-ppc32-linux.S
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Paul Mackerras (paulus@samba.org)
+ Copyright (C) 2005-2017 Paul Mackerras (paulus@samba.org)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/m_syswrap/syscall-ppc64be-linux.S b/coregrind/m_syswrap/syscall-ppc64be-linux.S
index 9c42f3e..16e9ced 100644
--- a/coregrind/m_syswrap/syscall-ppc64be-linux.S
+++ b/coregrind/m_syswrap/syscall-ppc64be-linux.S
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Paul Mackerras <paulus@samba.org>
+ Copyright (C) 2005-2017 Paul Mackerras <paulus@samba.org>
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/m_syswrap/syscall-ppc64le-linux.S b/coregrind/m_syswrap/syscall-ppc64le-linux.S
index b469cc4..6c7df6c 100644
--- a/coregrind/m_syswrap/syscall-ppc64le-linux.S
+++ b/coregrind/m_syswrap/syscall-ppc64le-linux.S
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Paul Mackerras <paulus@samba.org>
+ Copyright (C) 2005-2017 Paul Mackerras <paulus@samba.org>
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/m_syswrap/syscall-s390x-linux.S b/coregrind/m_syswrap/syscall-s390x-linux.S
index b8a9381..afe372c 100644
--- a/coregrind/m_syswrap/syscall-s390x-linux.S
+++ b/coregrind/m_syswrap/syscall-s390x-linux.S
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2015
+ Copyright IBM Corp. 2010-2017
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/m_syswrap/syscall-tilegx-linux.S b/coregrind/m_syswrap/syscall-tilegx-linux.S
deleted file mode 100644
index 7be2f6a..0000000
--- a/coregrind/m_syswrap/syscall-tilegx-linux.S
+++ /dev/null
@@ -1,193 +0,0 @@
-/*--------------------------------------------------------------------*/
-/*--- Support for doing system calls. syscall-tilegx-linux.S ---*/
-/*--------------------------------------------------------------------*/
-
-/*
- This file is part of Valgrind, a dynamic binary instrumentation
- framework.
-
- Copyright (C) 2010-2012 Tilera Corp.
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of the
- License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful, but
- WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
- 02111-1307, USA.
-
- The GNU General Public License is contained in the file COPYING.
-*/
-
-/* Contributed by Zhi-Gang Liu <zliu at tilera dot com> */
-
-#include "pub_core_basics_asm.h"
-
-#if defined(VGP_tilegx_linux)
-
-#include "pub_core_vkiscnums_asm.h"
-#include "libvex_guest_offsets.h"
-
-
-/*----------------------------------------------------------------*/
-/*
- Perform a syscall for the client. This will run a syscall
- with the client's specific per-thread signal mask.
-
- The structure of this function is such that, if the syscall is
- interrupted by a signal, we can determine exactly what
- execution state we were in with respect to the execution of
- the syscall by examining the value of IP in the signal
- handler. This means that we can always do the appropriate
- thing to precisely emulate the kernel's signal/syscall
- interactions.
-
- The syscall number is taken from the argument, even though it
- should also be in regs->v0. The syscall result is written
- back to regs->v0 on completion.
-
- Returns 0 if the syscall was successfully called (even if the
- syscall itself failed), or a nonzero error code in the lowest
- 8 bits if one of the sigprocmasks failed (there's no way to
- determine which one failed). And there's no obvious way to
- recover from that either, but nevertheless we want to know.
-
- VG_(fixup_guest_state_after_syscall_interrupted) does the
- thread state fixup in the case where we were interrupted by a
- signal.
-
- Prototype:
-
- UWord ML_(do_syscall_for_client_WRK)(
- Int syscallno, // r0
- void* guest_state, // r1
- const vki_sigset_t *sysmask, // r2
- const vki_sigset_t *postmask, // r3
- Int nsigwords) // r4
-*/
-/* from vki_arch.h */
-#define VKI_SIG_SETMASK 2
-
-.globl ML_(do_syscall_for_client_WRK)
-ML_(do_syscall_for_client_WRK):
-
- addli sp, sp, -64 // alloc 64B new stack space
- addli r29, sp, 56 // r29 points to offset 56 above sp
- st_add r29, r0, -8 // save r0
- // offset 48
- st_add r29, r1, -8 // save r1
- // offset 40
- st_add r29, r2, -8 // save r2
- // offset 32
- st_add r29, r3, -8 // save r3
- // offset 24
- st_add r29, r4, -8 // save r4
- // offset 16
- st r29, lr // save lr
-1:
- {
- moveli r10, __NR_rt_sigprocmask
- moveli r0, VKI_SIG_SETMASK
- }
- {
- move r1, r2
- move r2, r3
- }
- move r3, r4
- swint1
-
- // error, go 7f
- bnez r1, 7f
-
- /* Get registers from guest_state. */
- addli r29, sp, 56 // get syscallno
- ld r10, r29
- addli r29, sp, 48
- ld r29, r29 // r29 points to guest_state
- ld_add r0, r29, 8 // read r0
- ld_add r1, r29, 8 // read r1
- ld_add r2, r29, 8 // read r2
- ld_add r3, r29, 8 // read r3
- ld_add r4, r29, 8 // read r4
- ld_add r5, r29, 8 // read r5
-
-2: swint1 // syscall
-3:
- // Write register into guest_state
- addli r29, sp, 48
- ld r29, r29
- st_add r29, r0, 8
- st_add r29, r1, 8
- st_add r29, r2, 8
- st_add r29, r3, 8
- st_add r29, r4, 8
- st_add r29, r5, 8
- nop
-4:
- {
- moveli r10, __NR_rt_sigprocmask
- moveli r0, VKI_SIG_SETMASK
- }
- addli r29, sp, 32
- {
- ld r1, r29
- movei r2, 0
- }
- addli r29, sp, 24
- ld r3, r29
-
- swint1
- // error, go 7f
- bnez r1, 7f
- nop
-5: addli r29, sp, 16
- {
- ld lr, r29 // restore lr
- addli sp, sp, 64
- }
- jr lr
-
-7: addi r29, sp, 16
- {
- ld lr, r29 // restore lr
- addi sp, sp, 64
- }
- {
- // r0 = 0x8000
- shl16insli r0, zero, -0x8000
- jr lr
- }
-
- .section .rodata
- /* export the ranges so that
- VG_(fixup_guest_state_after_syscall_interrupted) can do the
- right thing */
-
- .globl ML_(blksys_setup)
- .globl ML_(blksys_restart)
- .globl ML_(blksys_complete)
- .globl ML_(blksys_committed)
- .globl ML_(blksys_finished)
- ML_(blksys_setup): .quad 1b
- ML_(blksys_restart): .quad 2b
- ML_(blksys_complete): .quad 3b
- ML_(blksys_committed): .quad 4b
- ML_(blksys_finished): .quad 5b
- .previous
-
-#endif /* defined(VGP_tilegx_linux) */
-
-/* Let the linker know we don't need an executable stack */
-MARK_STACK_NO_EXEC
-
-/*--------------------------------------------------------------------*/
-/*--- end ---*/
-/*--------------------------------------------------------------------*/
-
diff --git a/coregrind/m_syswrap/syscall-x86-darwin.S b/coregrind/m_syswrap/syscall-x86-darwin.S
index 823c9b4..7bdd3d5 100644
--- a/coregrind/m_syswrap/syscall-x86-darwin.S
+++ b/coregrind/m_syswrap/syscall-x86-darwin.S
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_syswrap/syscall-x86-linux.S b/coregrind/m_syswrap/syscall-x86-linux.S
index e4c6a0a..533fb0e 100644
--- a/coregrind/m_syswrap/syscall-x86-linux.S
+++ b/coregrind/m_syswrap/syscall-x86-linux.S
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_syswrap/syscall-x86-solaris.S b/coregrind/m_syswrap/syscall-x86-solaris.S
index c0df3d8..019401c 100644
--- a/coregrind/m_syswrap/syscall-x86-solaris.S
+++ b/coregrind/m_syswrap/syscall-x86-solaris.S
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2015 Petr Pavlu
+ Copyright (C) 2011-2017 Petr Pavlu
setup@dagobah.cz
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_syswrap/syswrap-amd64-darwin.c b/coregrind/m_syswrap/syswrap-amd64-darwin.c
index 375989f..c827bab 100644
--- a/coregrind/m_syswrap/syswrap-amd64-darwin.c
+++ b/coregrind/m_syswrap/syswrap-amd64-darwin.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Apple Inc.
+ Copyright (C) 2005-2017 Apple Inc.
Greg Parker gparker@apple.com
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_syswrap/syswrap-amd64-linux.c b/coregrind/m_syswrap/syswrap-amd64-linux.c
index a39148d..14ad649 100644
--- a/coregrind/m_syswrap/syswrap-amd64-linux.c
+++ b/coregrind/m_syswrap/syswrap-amd64-linux.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Nicholas Nethercote
+ Copyright (C) 2000-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -130,14 +130,7 @@
#define __NR_CLONE VG_STRINGIFY(__NR_clone)
#define __NR_EXIT VG_STRINGIFY(__NR_exit)
-extern
-Long do_syscall_clone_amd64_linux ( Word (*fn)(void *),
- void* stack,
- Long flags,
- void* arg,
- Long* child_tid,
- Long* parent_tid,
- vki_modify_ldt_t * );
+// See priv_syswrap-linux.h for arg profile.
asm(
".text\n"
".globl do_syscall_clone_amd64_linux\n"
@@ -183,126 +176,6 @@
#undef __NR_EXIT
-// forward declaration
-static void setup_child ( ThreadArchState*, ThreadArchState* );
-
-/*
- When a client clones, we need to keep track of the new thread. This means:
- 1. allocate a ThreadId+ThreadState+stack for the thread
-
- 2. initialize the thread's new VCPU state
-
- 3. create the thread using the same args as the client requested,
- but using the scheduler entrypoint for EIP, and a separate stack
- for ESP.
- */
-static SysRes do_clone ( ThreadId ptid,
- ULong flags, Addr rsp,
- Long* parent_tidptr,
- Long* child_tidptr,
- Addr tlsaddr )
-{
- static const Bool debug = False;
-
- ThreadId ctid = VG_(alloc_ThreadState)();
- ThreadState* ptst = VG_(get_ThreadState)(ptid);
- ThreadState* ctst = VG_(get_ThreadState)(ctid);
- UWord* stack;
- SysRes res;
- Long rax;
- vki_sigset_t blockall, savedmask;
-
- VG_(sigfillset)(&blockall);
-
- vg_assert(VG_(is_running_thread)(ptid));
- vg_assert(VG_(is_valid_tid)(ctid));
-
- stack = (UWord*)ML_(allocstack)(ctid);
- if (stack == NULL) {
- res = VG_(mk_SysRes_Error)( VKI_ENOMEM );
- goto out;
- }
-
- /* Copy register state
-
- Both parent and child return to the same place, and the code
- following the clone syscall works out which is which, so we
- don't need to worry about it.
-
- The parent gets the child's new tid returned from clone, but the
- child gets 0.
-
- If the clone call specifies a NULL rsp for the new thread, then
- it actually gets a copy of the parent's rsp.
- */
- setup_child( &ctst->arch, &ptst->arch );
-
- /* Make sys_clone appear to have returned Success(0) in the
- child. */
- ctst->arch.vex.guest_RAX = 0;
-
- if (rsp != 0)
- ctst->arch.vex.guest_RSP = rsp;
-
- ctst->os_state.parent = ptid;
-
- /* inherit signal mask */
- ctst->sig_mask = ptst->sig_mask;
- ctst->tmp_sig_mask = ptst->sig_mask;
-
- /* Start the child with its threadgroup being the same as the
- parent's. This is so that any exit_group calls that happen
- after the child is created but before it sets its
- os_state.threadgroup field for real (in thread_wrapper in
- syswrap-linux.c), really kill the new thread. a.k.a this avoids
- a race condition in which the thread is unkillable (via
- exit_group) because its threadgroup is not set. The race window
- is probably only a few hundred or a few thousand cycles long.
- See #226116. */
- ctst->os_state.threadgroup = ptst->os_state.threadgroup;
-
- ML_(guess_and_register_stack) (rsp, ctst);
-
- /* Assume the clone will succeed, and tell any tool that wants to
- know that this thread has come into existence. If the clone
- fails, we'll send out a ll_exit notification for it at the out:
- label below, to clean up. */
- vg_assert(VG_(owns_BigLock_LL)(ptid));
- VG_TRACK ( pre_thread_ll_create, ptid, ctid );
-
- if (flags & VKI_CLONE_SETTLS) {
- if (debug)
- VG_(printf)("clone child has SETTLS: tls at %#lx\n", tlsaddr);
- ctst->arch.vex.guest_FS_CONST = tlsaddr;
- }
-
- flags &= ~VKI_CLONE_SETTLS;
-
- /* start the thread with everything blocked */
- VG_(sigprocmask)(VKI_SIG_SETMASK, &blockall, &savedmask);
-
- /* Create the new thread */
- rax = do_syscall_clone_amd64_linux(
- ML_(start_thread_NORETURN), stack, flags, &VG_(threads)[ctid],
- child_tidptr, parent_tidptr, NULL
- );
- res = VG_(mk_SysRes_amd64_linux)( rax );
-
- VG_(sigprocmask)(VKI_SIG_SETMASK, &savedmask, NULL);
-
- out:
- if (sr_isError(res)) {
- /* clone failed */
- VG_(cleanup_thread)(&ctst->arch);
- ctst->status = VgTs_Empty;
- /* oops. Better tell the tool the thread exited in a hurry :-) */
- VG_TRACK( pre_thread_ll_exit, ctid );
- }
-
- return res;
-}
-
-
/* ---------------------------------------------------------------------
More thread stuff
------------------------------------------------------------------ */
@@ -311,16 +184,6 @@
{
}
-void setup_child ( /*OUT*/ ThreadArchState *child,
- /*IN*/ ThreadArchState *parent )
-{
- /* We inherit our parent's guest state. */
- child->vex = parent->vex;
- child->vex_shadow1 = parent->vex_shadow1;
- child->vex_shadow2 = parent->vex_shadow2;
-}
-
-
/* ---------------------------------------------------------------------
PRE/POST wrappers for AMD64/Linux-specific syscalls
------------------------------------------------------------------ */
@@ -333,7 +196,6 @@
the right thing to do is to make these wrappers 'static' since they
aren't visible outside this file, but that requires even more macro
magic. */
-DECL_TEMPLATE(amd64_linux, sys_clone);
DECL_TEMPLATE(amd64_linux, sys_rt_sigreturn);
DECL_TEMPLATE(amd64_linux, sys_arch_prctl);
DECL_TEMPLATE(amd64_linux, sys_ptrace);
@@ -342,108 +204,6 @@
DECL_TEMPLATE(amd64_linux, sys_syscall184);
-PRE(sys_clone)
-{
- ULong cloneflags;
-
- PRINT("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )",ARG1,ARG2,ARG3,ARG4,ARG5);
- PRE_REG_READ2(int, "clone",
- unsigned long, flags,
- void *, child_stack);
-
- if (ARG1 & VKI_CLONE_PARENT_SETTID) {
- if (VG_(tdict).track_pre_reg_read) {
- PRA3("clone", int *, parent_tidptr);
- }
- PRE_MEM_WRITE("clone(parent_tidptr)", ARG3, sizeof(Int));
- if (!VG_(am_is_valid_for_client)(ARG3, sizeof(Int), VKI_PROT_WRITE)) {
- SET_STATUS_Failure( VKI_EFAULT );
- return;
- }
- }
- if (ARG1 & VKI_CLONE_SETTLS) {
- if (VG_(tdict).track_pre_reg_read) {
- PRA4("clone", vki_modify_ldt_t *, tlsinfo);
- }
- PRE_MEM_READ("clone(tlsinfo)", ARG4, sizeof(vki_modify_ldt_t));
- if (!VG_(am_is_valid_for_client)(ARG4, sizeof(vki_modify_ldt_t),
- VKI_PROT_READ)) {
- SET_STATUS_Failure( VKI_EFAULT );
- return;
- }
- }
- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) {
- if (VG_(tdict).track_pre_reg_read) {
- PRA5("clone", int *, child_tidptr);
- }
- PRE_MEM_WRITE("clone(child_tidptr)", ARG4, sizeof(Int));
- if (!VG_(am_is_valid_for_client)(ARG4, sizeof(Int), VKI_PROT_WRITE)) {
- SET_STATUS_Failure( VKI_EFAULT );
- return;
- }
- }
-
- cloneflags = ARG1;
-
- if (!ML_(client_signal_OK)(ARG1 & VKI_CSIGNAL)) {
- SET_STATUS_Failure( VKI_EINVAL );
- return;
- }
-
- /* Only look at the flags we really care about */
- switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS
- | VKI_CLONE_FILES | VKI_CLONE_VFORK)) {
- case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES:
- /* thread creation */
- SET_STATUS_from_SysRes(
- do_clone(tid,
- ARG1, /* flags */
- (Addr)ARG2, /* child ESP */
- (Long *)ARG3, /* parent_tidptr */
- (Long *)ARG4, /* child_tidptr */
- (Addr)ARG5)); /* set_tls */
- break;
-
- case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */
- /* FALLTHROUGH - assume vfork == fork */
- cloneflags &= ~(VKI_CLONE_VFORK | VKI_CLONE_VM);
-
- case 0: /* plain fork */
- SET_STATUS_from_SysRes(
- ML_(do_fork_clone)(tid,
- cloneflags, /* flags */
- (Int *)ARG3, /* parent_tidptr */
- (Int *)ARG4)); /* child_tidptr */
- break;
-
- default:
- /* should we just ENOSYS? */
- VG_(message)(Vg_UserMsg,
- "Unsupported clone() flags: 0x%lx\n", ARG1);
- VG_(message)(Vg_UserMsg,
- "\n");
- VG_(message)(Vg_UserMsg,
- "The only supported clone() uses are:\n");
- VG_(message)(Vg_UserMsg,
- " - via a threads library (LinuxThreads or NPTL)\n");
- VG_(message)(Vg_UserMsg,
- " - via the implementation of fork or vfork\n");
- VG_(unimplemented)
- ("Valgrind does not support general clone().");
- }
-
- if (SUCCESS) {
- if (ARG1 & VKI_CLONE_PARENT_SETTID)
- POST_MEM_WRITE(ARG3, sizeof(Int));
- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID))
- POST_MEM_WRITE(ARG4, sizeof(Int));
-
- /* Thread creation was successful; let the child have the chance
- to run */
- *flags |= SfYieldAfter;
- }
-}
-
PRE(sys_rt_sigreturn)
{
/* This isn't really a syscall at all - it's a misuse of the
@@ -589,6 +349,9 @@
POST(sys_ptrace)
{
switch (ARG1) {
+ case VKI_PTRACE_TRACEME:
+ ML_(linux_POST_traceme)(tid);
+ break;
case VKI_PTRACE_PEEKTEXT:
case VKI_PTRACE_PEEKDATA:
case VKI_PTRACE_PEEKUSR:
@@ -730,7 +493,7 @@
GENX_(__NR_madvise, sys_madvise), // 28
LINX_(__NR_shmget, sys_shmget), // 29
- LINXY(__NR_shmat, wrap_sys_shmat), // 30
+ LINXY(__NR_shmat, sys_shmat), // 30
LINXY(__NR_shmctl, sys_shmctl), // 31
GENXY(__NR_dup, sys_dup), // 32
GENXY(__NR_dup2, sys_dup2), // 33
@@ -761,7 +524,7 @@
LINX_(__NR_setsockopt, sys_setsockopt), // 54
LINXY(__NR_getsockopt, sys_getsockopt), // 55
- PLAX_(__NR_clone, sys_clone), // 56
+ LINX_(__NR_clone, sys_clone), // 56
GENX_(__NR_fork, sys_fork), // 57
GENX_(__NR_vfork, sys_fork), // 58 treat as fork
GENX_(__NR_execve, sys_execve), // 59
@@ -1069,7 +832,7 @@
LINXY(__NR_process_vm_readv, sys_process_vm_readv), // 310
LINX_(__NR_process_vm_writev, sys_process_vm_writev),// 311
LINX_(__NR_kcmp, sys_kcmp), // 312
-// LIN__(__NR_finit_module, sys_ni_syscall), // 313
+ LINX_(__NR_finit_module, sys_finit_module), // 313
// LIN__(__NR_sched_setattr, sys_ni_syscall), // 314
// LIN__(__NR_sched_getattr, sys_ni_syscall), // 315
diff --git a/coregrind/m_syswrap/syswrap-amd64-solaris.c b/coregrind/m_syswrap/syswrap-amd64-solaris.c
index 4fd78ec..a6ddf53 100644
--- a/coregrind/m_syswrap/syswrap-amd64-solaris.c
+++ b/coregrind/m_syswrap/syswrap-amd64-solaris.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2014-2015 Petr Pavlu
+ Copyright (C) 2014-2017 Petr Pavlu
setup@dagobah.cz
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_syswrap/syswrap-arm-linux.c b/coregrind/m_syswrap/syswrap-arm-linux.c
index 445d5ac..4ae4e89 100644
--- a/coregrind/m_syswrap/syswrap-arm-linux.c
+++ b/coregrind/m_syswrap/syswrap-arm-linux.c
@@ -7,9 +7,9 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Nicholas Nethercote
+ Copyright (C) 2000-2017 Nicholas Nethercote
njn@valgrind.org
- Copyright (C) 2008-2015 Evan Geller
+ Copyright (C) 2008-2017 Evan Geller
gaze@bea.ms
This program is free software; you can redistribute it and/or
@@ -102,14 +102,7 @@
#define __NR_CLONE VG_STRINGIFY(__NR_clone)
#define __NR_EXIT VG_STRINGIFY(__NR_exit)
-extern
-ULong do_syscall_clone_arm_linux ( Word (*fn)(void *),
- void* stack,
- Int flags,
- void* arg,
- Int* child_tid,
- Int* parent_tid,
- void* tls );
+// See priv_syswrap-linux.h for arg profile.
asm(
".text\n"
".globl do_syscall_clone_arm_linux\n"
@@ -148,104 +141,8 @@
#undef __NR_EXIT
// forward declarations
-static void setup_child ( ThreadArchState*, ThreadArchState* );
-static void assign_guest_tls(ThreadId ctid, Addr tlsptr);
static SysRes sys_set_tls ( ThreadId tid, Addr tlsptr );
-/*
- When a client clones, we need to keep track of the new thread. This means:
- 1. allocate a ThreadId+ThreadState+stack for the thread
-
- 2. initialize the thread's new VCPU state
-
- 3. create the thread using the same args as the client requested,
- but using the scheduler entrypoint for IP, and a separate stack
- for SP.
- */
-static SysRes do_clone ( ThreadId ptid,
- UInt flags, Addr sp,
- Int *parent_tidptr,
- Int *child_tidptr,
- Addr child_tls)
-{
- ThreadId ctid = VG_(alloc_ThreadState)();
- ThreadState* ptst = VG_(get_ThreadState)(ptid);
- ThreadState* ctst = VG_(get_ThreadState)(ctid);
- UInt r0;
- UWord *stack;
- SysRes res;
- vki_sigset_t blockall, savedmask;
-
- VG_(sigfillset)(&blockall);
-
- vg_assert(VG_(is_running_thread)(ptid));
- vg_assert(VG_(is_valid_tid)(ctid));
-
- stack = (UWord*)ML_(allocstack)(ctid);
-
- if(stack == NULL) {
- res = VG_(mk_SysRes_Error)( VKI_ENOMEM );
- goto out;
- }
-
- setup_child( &ctst->arch, &ptst->arch );
-
- ctst->arch.vex.guest_R0 = 0;
- if(sp != 0)
- ctst->arch.vex.guest_R13 = sp;
-
- ctst->os_state.parent = ptid;
-
- ctst->sig_mask = ptst->sig_mask;
- ctst->tmp_sig_mask = ptst->sig_mask;
-
- /* Start the child with its threadgroup being the same as the
- parent's. This is so that any exit_group calls that happen
- after the child is created but before it sets its
- os_state.threadgroup field for real (in thread_wrapper in
- syswrap-linux.c), really kill the new thread. a.k.a this avoids
- a race condition in which the thread is unkillable (via
- exit_group) because its threadgroup is not set. The race window
- is probably only a few hundred or a few thousand cycles long.
- See #226116. */
- ctst->os_state.threadgroup = ptst->os_state.threadgroup;
-
- ML_(guess_and_register_stack) (sp, ctst);
-
- vg_assert(VG_(owns_BigLock_LL)(ptid));
- VG_TRACK ( pre_thread_ll_create, ptid, ctid );
-
- if (flags & VKI_CLONE_SETTLS) {
- /* Just assign the tls pointer in the guest TPIDRURO. */
- assign_guest_tls(ctid, child_tls);
- }
-
- flags &= ~VKI_CLONE_SETTLS;
-
- VG_(sigprocmask)(VKI_SIG_SETMASK, &blockall, &savedmask);
-
- r0 = do_syscall_clone_arm_linux(
- ML_(start_thread_NORETURN), stack, flags, &VG_(threads)[ctid],
- child_tidptr, parent_tidptr, NULL
- );
- //VG_(printf)("AFTER SYSCALL, %x and %x CHILD: %d PARENT: %d\n",child_tidptr, parent_tidptr,*child_tidptr,*parent_tidptr);
-
- res = VG_(mk_SysRes_arm_linux)( r0 );
-
- VG_(sigprocmask)(VKI_SIG_SETMASK, &savedmask, NULL);
-
-out:
- if (sr_isError(res)) {
- VG_(cleanup_thread)(&ctst->arch);
- ctst->status = VgTs_Empty;
- VG_TRACK( pre_thread_ll_exit, ctid );
- }
-
- return res;
-}
-
-
-
/* ---------------------------------------------------------------------
More thread stuff
------------------------------------------------------------------ */
@@ -256,26 +153,13 @@
{
}
-void setup_child ( /*OUT*/ ThreadArchState *child,
- /*IN*/ ThreadArchState *parent )
-{
- child->vex = parent->vex;
- child->vex_shadow1 = parent->vex_shadow1;
- child->vex_shadow2 = parent->vex_shadow2;
-}
-
-static void assign_guest_tls(ThreadId tid, Addr tlsptr)
-{
- VG_(threads)[tid].arch.vex.guest_TPIDRURO = tlsptr;
-}
-
/* Assigns tlsptr to the guest TPIDRURO.
If needed for the specific hardware, really executes
the set_tls syscall.
*/
static SysRes sys_set_tls ( ThreadId tid, Addr tlsptr )
{
- assign_guest_tls(tid, tlsptr);
+ VG_(threads)[tid].arch.vex.guest_TPIDRURO = tlsptr;
if (KernelVariantiS(KernelVariant_android_no_hw_tls,
VG_(clo_kernel_variant))) {
@@ -333,7 +217,6 @@
DECL_TEMPLATE(arm_linux, sys_lstat64);
DECL_TEMPLATE(arm_linux, sys_fstatat64);
DECL_TEMPLATE(arm_linux, sys_fstat64);
-DECL_TEMPLATE(arm_linux, sys_clone);
DECL_TEMPLATE(arm_linux, sys_sigreturn);
DECL_TEMPLATE(arm_linux, sys_rt_sigreturn);
DECL_TEMPLATE(arm_linux, sys_sigsuspend);
@@ -424,100 +307,6 @@
POST_MEM_WRITE( ARG2, sizeof(struct vki_stat64) );
}
-PRE(sys_clone)
-{
- UInt cloneflags;
-
- PRINT("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )",ARG1,ARG2,ARG3,ARG4,ARG5);
- PRE_REG_READ5(int, "clone",
- unsigned long, flags,
- void *, child_stack,
- int *, parent_tidptr,
- void *, child_tls,
- int *, child_tidptr);
-
- if (ARG1 & VKI_CLONE_PARENT_SETTID) {
- PRE_MEM_WRITE("clone(parent_tidptr)", ARG3, sizeof(Int));
- if (!VG_(am_is_valid_for_client)(ARG3, sizeof(Int),
- VKI_PROT_WRITE)) {
- SET_STATUS_Failure( VKI_EFAULT );
- return;
- }
- }
- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) {
- PRE_MEM_WRITE("clone(child_tidptr)", ARG5, sizeof(Int));
- if (!VG_(am_is_valid_for_client)(ARG5, sizeof(Int),
- VKI_PROT_WRITE)) {
- SET_STATUS_Failure( VKI_EFAULT );
- return;
- }
- }
- if (ARG1 & VKI_CLONE_SETTLS) {
- PRE_MEM_READ("clone(tls_user_desc)", ARG4, sizeof(vki_modify_ldt_t));
- if (!VG_(am_is_valid_for_client)(ARG4, sizeof(vki_modify_ldt_t),
- VKI_PROT_READ)) {
- SET_STATUS_Failure( VKI_EFAULT );
- return;
- }
- }
-
- cloneflags = ARG1;
-
- if (!ML_(client_signal_OK)(ARG1 & VKI_CSIGNAL)) {
- SET_STATUS_Failure( VKI_EINVAL );
- return;
- }
-
- /* Only look at the flags we really care about */
- switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS
- | VKI_CLONE_FILES | VKI_CLONE_VFORK)) {
- case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES:
- /* thread creation */
- SET_STATUS_from_SysRes(
- do_clone(tid,
- ARG1, /* flags */
- (Addr)ARG2, /* child ESP */
- (Int *)ARG3, /* parent_tidptr */
- (Int *)ARG5, /* child_tidptr */
- (Addr)ARG4)); /* set_tls */
- break;
-
- case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */
- /* FALLTHROUGH - assume vfork == fork */
- cloneflags &= ~(VKI_CLONE_VFORK | VKI_CLONE_VM);
-
- case 0: /* plain fork */
- SET_STATUS_from_SysRes(
- ML_(do_fork_clone)(tid,
- cloneflags, /* flags */
- (Int *)ARG3, /* parent_tidptr */
- (Int *)ARG5)); /* child_tidptr */
- break;
-
- default:
- /* should we just ENOSYS? */
- VG_(message)(Vg_UserMsg, "Unsupported clone() flags: 0x%lx\n", ARG1);
- VG_(message)(Vg_UserMsg, "\n");
- VG_(message)(Vg_UserMsg, "The only supported clone() uses are:\n");
- VG_(message)(Vg_UserMsg, " - via a threads library (LinuxThreads or NPTL)\n");
- VG_(message)(Vg_UserMsg, " - via the implementation of fork or vfork\n");
- VG_(message)(Vg_UserMsg, " - for the Quadrics Elan3 user-space driver\n");
- VG_(unimplemented)
- ("Valgrind does not support general clone().");
- }
-
- if (SUCCESS) {
- if (ARG1 & VKI_CLONE_PARENT_SETTID)
- POST_MEM_WRITE(ARG3, sizeof(Int));
- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID))
- POST_MEM_WRITE(ARG5, sizeof(Int));
-
- /* Thread creation was successful; let the child have the chance
- to run */
- *flags |= SfYieldAfter;
- }
-}
-
PRE(sys_sigreturn)
{
/* See comments on PRE(sys_rt_sigreturn) in syswrap-amd64-linux.c for
@@ -693,6 +482,9 @@
POST(sys_ptrace)
{
switch (ARG1) {
+ case VKI_PTRACE_TRACEME:
+ ML_(linux_POST_traceme)(tid);
+ break;
case VKI_PTRACE_PEEKTEXT:
case VKI_PTRACE_PEEKDATA:
case VKI_PTRACE_PEEKUSR:
@@ -901,7 +693,7 @@
GENX_(__NR_fsync, sys_fsync), // 118
PLAX_(__NR_sigreturn, sys_sigreturn), // 119 ?/Linux
- PLAX_(__NR_clone, sys_clone), // 120
+ LINX_(__NR_clone, sys_clone), // 120
//zz // (__NR_setdomainname, sys_setdomainname), // 121 */*(?)
GENXY(__NR_uname, sys_newuname), // 122
// PLAX_(__NR_modify_ldt, sys_modify_ldt), // 123
@@ -1152,7 +944,7 @@
LINX_(__NR_readlinkat, sys_readlinkat), //
LINX_(__NR_fchmodat, sys_fchmodat), //
LINX_(__NR_faccessat, sys_faccessat), //
- LINXY(__NR_shmat, wrap_sys_shmat), //305
+ LINXY(__NR_shmat, sys_shmat), //305
LINXY(__NR_shmdt, sys_shmdt), //306
LINX_(__NR_shmget, sys_shmget), //307
LINXY(__NR_shmctl, sys_shmctl), // 308
diff --git a/coregrind/m_syswrap/syswrap-arm64-linux.c b/coregrind/m_syswrap/syswrap-arm64-linux.c
index 00b0138..d244459 100644
--- a/coregrind/m_syswrap/syswrap-arm64-linux.c
+++ b/coregrind/m_syswrap/syswrap-arm64-linux.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2013-2015 OpenWorks
+ Copyright (C) 2013-2017 OpenWorks
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -138,14 +138,7 @@
#define __NR_CLONE VG_STRINGIFY(__NR_clone)
#define __NR_EXIT VG_STRINGIFY(__NR_exit)
-extern
-Long do_syscall_clone_arm64_linux ( Word (*fn)(void *),
- void* child_stack,
- Long flags,
- void* arg,
- Int* child_tid,
- Int* parent_tid,
- void* tls );
+// See priv_syswrap-linux.h for arg profile.
asm(
".text\n"
".globl do_syscall_clone_arm64_linux\n"
@@ -192,125 +185,8 @@
#undef __NR_EXIT
// forward declaration
-static void setup_child ( ThreadArchState*, ThreadArchState* );
-static void assign_guest_tls(ThreadId ctid, Addr tlsptr);
//ZZ static SysRes sys_set_tls ( ThreadId tid, Addr tlsptr );
-/*
- When a client clones, we need to keep track of the new thread. This means:
- 1. allocate a ThreadId+ThreadState+stack for the thread
-
- 2. initialize the thread's new VCPU state
-
- 3. create the thread using the same args as the client requested,
- but using the scheduler entrypoint for IP, and a separate stack
- for SP.
- */
-static SysRes do_clone ( ThreadId ptid,
- ULong flags,
- Addr child_xsp,
- Int* parent_tidptr,
- Int* child_tidptr,
- Addr child_tls )
-{
- ThreadId ctid = VG_(alloc_ThreadState)();
- ThreadState* ptst = VG_(get_ThreadState)(ptid);
- ThreadState* ctst = VG_(get_ThreadState)(ctid);
- UWord* stack;
- SysRes res;
- ULong x0;
- vki_sigset_t blockall, savedmask;
-
- VG_(sigfillset)(&blockall);
-
- vg_assert(VG_(is_running_thread)(ptid));
- vg_assert(VG_(is_valid_tid)(ctid));
-
- stack = (UWord*)ML_(allocstack)(ctid);
- if (stack == NULL) {
- res = VG_(mk_SysRes_Error)( VKI_ENOMEM );
- goto out;
- }
-
- /* Copy register state
-
- Both parent and child return to the same place, and the code
- following the clone syscall works out which is which, so we
- don't need to worry about it.
-
- The parent gets the child's new tid returned from clone, but the
- child gets 0.
-
- If the clone call specifies a NULL xsp for the new thread, then
- it actually gets a copy of the parent's xsp.
- */
- setup_child( &ctst->arch, &ptst->arch );
-
- /* Make sys_clone appear to have returned Success(0) in the
- child. */
- ctst->arch.vex.guest_X0 = 0;
-
- if (child_xsp != 0)
- ctst->arch.vex.guest_XSP = child_xsp;
-
- ctst->os_state.parent = ptid;
-
- /* inherit signal mask */
- ctst->sig_mask = ptst->sig_mask;
- ctst->tmp_sig_mask = ptst->sig_mask;
-
- /* Start the child with its threadgroup being the same as the
- parent's. This is so that any exit_group calls that happen
- after the child is created but before it sets its
- os_state.threadgroup field for real (in thread_wrapper in
- syswrap-linux.c), really kill the new thread. a.k.a this avoids
- a race condition in which the thread is unkillable (via
- exit_group) because its threadgroup is not set. The race window
- is probably only a few hundred or a few thousand cycles long.
- See #226116. */
- ctst->os_state.threadgroup = ptst->os_state.threadgroup;
-
- ML_(guess_and_register_stack)(child_xsp, ctst);
-
- /* Assume the clone will succeed, and tell any tool that wants to
- know that this thread has come into existence. If the clone
- fails, we'll send out a ll_exit notification for it at the out:
- label below, to clean up. */
- vg_assert(VG_(owns_BigLock_LL)(ptid));
- VG_TRACK ( pre_thread_ll_create, ptid, ctid );
-
- if (flags & VKI_CLONE_SETTLS) {
- /* Just assign the tls pointer in the guest TPIDR_EL0. */
- assign_guest_tls(ctid, child_tls);
- }
-
- flags &= ~VKI_CLONE_SETTLS;
-
- /* start the thread with everything blocked */
- VG_(sigprocmask)(VKI_SIG_SETMASK, &blockall, &savedmask);
-
- x0 = do_syscall_clone_arm64_linux(
- ML_(start_thread_NORETURN), stack, flags, &VG_(threads)[ctid],
- child_tidptr, parent_tidptr, NULL
- );
-
- res = VG_(mk_SysRes_arm64_linux)( x0 );
-
- VG_(sigprocmask)(VKI_SIG_SETMASK, &savedmask, NULL);
-
- out:
- if (sr_isError(res)) {
- /* clone failed */
- VG_(cleanup_thread)(&ctst->arch);
- ctst->status = VgTs_Empty;
- /* oops. Better tell the tool the thread exited in a hurry :-) */
- VG_TRACK( pre_thread_ll_exit, ctid );
- }
-
- return res;
-}
-
-
/* ---------------------------------------------------------------------
More thread stuff
------------------------------------------------------------------ */
@@ -321,19 +197,6 @@
{
}
-void setup_child ( /*OUT*/ ThreadArchState *child,
- /*IN*/ ThreadArchState *parent )
-{
- child->vex = parent->vex;
- child->vex_shadow1 = parent->vex_shadow1;
- child->vex_shadow2 = parent->vex_shadow2;
-}
-
-static void assign_guest_tls(ThreadId tid, Addr tlsptr)
-{
- VG_(threads)[tid].arch.vex.guest_TPIDR_EL0 = tlsptr;
-}
-
//ZZ /* Assigns tlsptr to the guest TPIDRURO.
//ZZ If needed for the specific hardware, really executes
//ZZ the set_tls syscall.
@@ -397,7 +260,6 @@
//ZZ DECL_TEMPLATE(arm_linux, sys_lstat64);
//ZZ DECL_TEMPLATE(arm_linux, sys_fstatat64);
//ZZ DECL_TEMPLATE(arm_linux, sys_fstat64);
-DECL_TEMPLATE(arm64_linux, sys_clone);
//ZZ DECL_TEMPLATE(arm_linux, sys_sigreturn);
DECL_TEMPLATE(arm64_linux, sys_rt_sigreturn);
//ZZ DECL_TEMPLATE(arm_linux, sys_sigsuspend);
@@ -512,110 +374,6 @@
//ZZ POST_MEM_WRITE( ARG2, sizeof(struct vki_stat64) );
//ZZ }
-/* Aarch64 seems to use CONFIG_CLONE_BACKWARDS in the kernel. See:
- http://dev.gentoo.org/~vapier/aarch64/linux-3.12.6.config
- http://people.redhat.com/wcohen/aarch64/aarch64_config
- from linux-3.10.5/kernel/fork.c
- #ifdef CONFIG_CLONE_BACKWARDS
- SYSCALL_DEFINE5(clone, unsigned long, clone_flags, unsigned long, newsp,
- int __user *, parent_tidptr,
- int, tls_val,
- int __user *, child_tidptr)
-*/
-PRE(sys_clone)
-{
- UInt cloneflags;
-
- PRINT("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )",ARG1,ARG2,ARG3,ARG4,ARG5);
- PRE_REG_READ5(int, "clone",
- unsigned long, flags,
- void *, child_stack,
- int *, parent_tidptr,
- void *, child_tls,
- int *, child_tidptr);
-
- if (ARG1 & VKI_CLONE_PARENT_SETTID) {
- PRE_MEM_WRITE("clone(parent_tidptr)", ARG3, sizeof(Int));
- if (!VG_(am_is_valid_for_client)(ARG3, sizeof(Int),
- VKI_PROT_WRITE)) {
- SET_STATUS_Failure( VKI_EFAULT );
- return;
- }
- }
-//ZZ if (ARG1 & VKI_CLONE_SETTLS) {
-//ZZ PRE_MEM_READ("clone(tls_user_desc)", ARG4, sizeof(vki_modify_ldt_t));
-//ZZ if (!VG_(am_is_valid_for_client)(ARG4, sizeof(vki_modify_ldt_t),
-//ZZ VKI_PROT_READ)) {
-//ZZ SET_STATUS_Failure( VKI_EFAULT );
-//ZZ return;
-//ZZ }
-//ZZ }
- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) {
- PRE_MEM_WRITE("clone(child_tidptr)", ARG5, sizeof(Int));
- if (!VG_(am_is_valid_for_client)(ARG5, sizeof(Int),
- VKI_PROT_WRITE)) {
- SET_STATUS_Failure( VKI_EFAULT );
- return;
- }
- }
-
- cloneflags = ARG1;
-
- if (!ML_(client_signal_OK)(ARG1 & VKI_CSIGNAL)) {
- SET_STATUS_Failure( VKI_EINVAL );
- return;
- }
-
- /* Only look at the flags we really care about */
- switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS
- | VKI_CLONE_FILES | VKI_CLONE_VFORK)) {
- case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES:
- /* thread creation */
- SET_STATUS_from_SysRes(
- do_clone(tid,
- ARG1, /* flags */
- (Addr)ARG2, /* child SP */
- (Int*)ARG3, /* parent_tidptr */
- (Int*)ARG5, /* child_tidptr */
- (Addr)ARG4)); /* tls_val */
- break;
-
- case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */
- /* FALLTHROUGH - assume vfork == fork */
- cloneflags &= ~(VKI_CLONE_VFORK | VKI_CLONE_VM);
-
- case 0: /* plain fork */
- SET_STATUS_from_SysRes(
- ML_(do_fork_clone)(tid,
- cloneflags, /* flags */
- (Int*)ARG3, /* parent_tidptr */
- (Int*)ARG5)); /* child_tidptr */
- break;
-
- default:
- /* should we just ENOSYS? */
- VG_(message)(Vg_UserMsg, "Unsupported clone() flags: 0x%lx\n", ARG1);
- VG_(message)(Vg_UserMsg, "\n");
- VG_(message)(Vg_UserMsg, "The only supported clone() uses are:\n");
- VG_(message)(Vg_UserMsg, " - via a threads library (LinuxThreads or NPTL)\n");
- VG_(message)(Vg_UserMsg, " - via the implementation of fork or vfork\n");
- VG_(message)(Vg_UserMsg, " - for the Quadrics Elan3 user-space driver\n");
- VG_(unimplemented)
- ("Valgrind does not support general clone().");
- }
-
- if (SUCCESS) {
- if (ARG1 & VKI_CLONE_PARENT_SETTID)
- POST_MEM_WRITE(ARG3, sizeof(Int));
- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID))
- POST_MEM_WRITE(ARG5, sizeof(Int));
-
- /* Thread creation was successful; let the child have the chance
- to run */
- *flags |= SfYieldAfter;
- }
-}
-
//ZZ PRE(sys_sigreturn)
//ZZ {
//ZZ /* See comments on PRE(sys_rt_sigreturn) in syswrap-amd64-linux.c for
@@ -893,10 +651,11 @@
LINX_(__NR_unlinkat, sys_unlinkat), // 35
LINX_(__NR_symlinkat, sys_symlinkat), // 36
LINX_(__NR_linkat, sys_linkat), // 37
- LINX_(__NR_renameat, sys_renameat), // 38
+ LINX_(__NR_renameat, sys_renameat), // 38
LINX_(__NR_umount2, sys_umount), // 39
LINX_(__NR_mount, sys_mount), // 40
-
+ LINX_(__NR_pivot_root, sys_pivot_root), // 41
+ // (__NR_nfsservctl, sys_ni_syscall), // 42
GENXY(__NR_statfs, sys_statfs), // 43
GENXY(__NR_fstatfs, sys_fstatfs), // 44
GENX_(__NR_truncate, sys_truncate), // 45
@@ -938,7 +697,7 @@
GENX_(__NR_sync, sys_sync), // 81
GENX_(__NR_fsync, sys_fsync), // 82
GENX_(__NR_fdatasync, sys_fdatasync), // 83
-
+ LINX_(__NR_sync_file_range, sys_sync_file_range), // 84
LINXY(__NR_timerfd_create, sys_timerfd_create), // 85
LINXY(__NR_timerfd_settime, sys_timerfd_settime), // 86
LINXY(__NR_timerfd_gettime, sys_timerfd_gettime), // 87
@@ -951,27 +710,27 @@
LINX_(__NR_exit_group, sys_exit_group), // 94
LINXY(__NR_waitid, sys_waitid), // 95
LINX_(__NR_set_tid_address, sys_set_tid_address), // 96
-
+ LINX_(__NR_unshare, sys_unshare), // 97
LINXY(__NR_futex, sys_futex), // 98
LINX_(__NR_set_robust_list, sys_set_robust_list), // 99
-
+ LINXY(__NR_get_robust_list, sys_get_robust_list), // 100
GENXY(__NR_nanosleep, sys_nanosleep), // 101
GENXY(__NR_getitimer, sys_getitimer), // 102
GENXY(__NR_setitimer, sys_setitimer), // 103
GENX_(__NR_kexec_load, sys_ni_syscall), // 104
LINX_(__NR_init_module, sys_init_module), // 105
-
+ LINX_(__NR_delete_module, sys_delete_module), // 106
LINXY(__NR_timer_create, sys_timer_create), // 107
- LINXY(__NR_timer_settime, sys_timer_settime), // 108
- LINXY(__NR_timer_gettime, sys_timer_gettime), // 109
- LINX_(__NR_timer_getoverrun, sys_timer_getoverrun), // 110
+ LINXY(__NR_timer_gettime, sys_timer_gettime), // 108
+ LINX_(__NR_timer_getoverrun, sys_timer_getoverrun), // 109
+ LINXY(__NR_timer_settime, sys_timer_settime), // 110
LINX_(__NR_timer_delete, sys_timer_delete), // 111
LINX_(__NR_clock_settime, sys_clock_settime), // 112
LINXY(__NR_clock_gettime, sys_clock_gettime), // 113
LINXY(__NR_clock_getres, sys_clock_getres), // 114
LINXY(__NR_clock_nanosleep, sys_clock_nanosleep), // 115
LINXY(__NR_syslog, sys_syslog), // 116
-
+ // (__NR_ptrace, sys_ptrace), // 117
LINXY(__NR_sched_setparam, sys_sched_setparam), // 118
LINX_(__NR_sched_setscheduler,sys_sched_setscheduler),// 119
LINX_(__NR_sched_getscheduler,sys_sched_getscheduler),// 120
@@ -981,9 +740,10 @@
LINX_(__NR_sched_yield, sys_sched_yield), // 124
LINX_(__NR_sched_get_priority_max, sys_sched_get_priority_max),// 125
LINX_(__NR_sched_get_priority_min, sys_sched_get_priority_min),// 126
-
+ LINXY(__NR_sched_rr_get_interval, sys_sched_rr_get_interval),// 127
+ // (__NR_restart_syscall, sys_ni_syscall), // 128
GENX_(__NR_kill, sys_kill), // 129
-
+ LINXY(__NR_tkill, sys_tkill), // 130
LINX_(__NR_tgkill, sys_tgkill), // 131
GENXY(__NR_sigaltstack, sys_sigaltstack), // 132
LINX_(__NR_rt_sigsuspend, sys_rt_sigsuspend), // 133
@@ -995,7 +755,7 @@
PLAX_(__NR_rt_sigreturn, sys_rt_sigreturn), // 139
GENX_(__NR_setpriority, sys_setpriority), // 140
GENX_(__NR_getpriority, sys_getpriority), // 141
-
+ // (__NR_reboot, sys_ni_syscall), // 142
GENX_(__NR_setregid, sys_setregid), // 143
GENX_(__NR_setgid, sys_setgid), // 144
GENX_(__NR_setreuid, sys_setreuid), // 145
@@ -1014,13 +774,14 @@
GENXY(__NR_getgroups, sys_getgroups), // 158
GENX_(__NR_setgroups, sys_setgroups), // 159
GENXY(__NR_uname, sys_newuname), // 160
-
+ GENX_(__NR_sethostname, sys_sethostname), // 161
+ // (__NR_setdomainname, sys_ni_syscall), // 162
GENXY(__NR_getrlimit, sys_old_getrlimit), // 163
GENX_(__NR_setrlimit, sys_setrlimit), // 164
GENXY(__NR_getrusage, sys_getrusage), // 165
GENX_(__NR_umask, sys_umask), // 166
LINXY(__NR_prctl, sys_prctl), // 167
-
+ LINXY(__NR_getcpu, sys_getcpu), // 168
GENXY(__NR_gettimeofday, sys_gettimeofday), // 169
GENX_(__NR_settimeofday, sys_settimeofday), // 170
LINXY(__NR_adjtimex, sys_adjtimex), // 171
@@ -1048,7 +809,7 @@
LINX_(__NR_semop, sys_semop), // 193
LINX_(__NR_shmget, sys_shmget), // 194
LINXY(__NR_shmctl, sys_shmctl), // 195
- LINXY(__NR_shmat, wrap_sys_shmat), // 196
+ LINXY(__NR_shmat, sys_shmat), // 196
LINXY(__NR_shmdt, sys_shmdt), // 197
LINXY(__NR_socket, sys_socket), // 198
LINXY(__NR_socketpair, sys_socketpair), // 199
@@ -1070,13 +831,14 @@
GENXY(__NR_munmap, sys_munmap), // 215
GENX_(__NR_mremap, sys_mremap), // 216
LINX_(__NR_add_key, sys_add_key), // 217
-
+ LINX_(__NR_request_key, sys_request_key), // 218
LINXY(__NR_keyctl, sys_keyctl), // 219
- PLAX_(__NR_clone, sys_clone), // 220
+ LINX_(__NR_clone, sys_clone), // 220
GENX_(__NR_execve, sys_execve), // 221
PLAX_(__NR_mmap, sys_mmap), // 222
PLAX_(__NR_fadvise64, sys_fadvise64), // 223
-
+ // (__NR_swapon, sys_swapon), // 224
+ // (__NR_swapoff, sys_swapoff), // 225
GENXY(__NR_mprotect, sys_mprotect), // 226
GENX_(__NR_msync, sys_msync), // 227
GENX_(__NR_mlock, sys_mlock), // 228
@@ -1085,300 +847,47 @@
LINX_(__NR_munlockall, sys_munlockall), // 231
GENXY(__NR_mincore, sys_mincore), // 232
GENX_(__NR_madvise, sys_madvise), // 233
-
+ // (__NR_remap_file_pages, sys_ni_syscall) // 234
LINX_(__NR_mbind, sys_mbind), // 235
LINXY(__NR_get_mempolicy, sys_get_mempolicy), // 236
LINX_(__NR_set_mempolicy, sys_set_mempolicy), // 237
-
+ // (__NR_migrate_pages, sys_ni_syscall), // 238
+ LINXY(__NR_move_pages, sys_move_pages), // 239
+ LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo), // 240
LINXY(__NR_perf_event_open, sys_perf_event_open), // 241
LINXY(__NR_accept4, sys_accept4), // 242
LINXY(__NR_recvmmsg, sys_recvmmsg), // 243
-
GENXY(__NR_wait4, sys_wait4), // 260
-
+ LINXY(__NR_prlimit64, sys_prlimit64), // 261
+ LINXY(__NR_fanotify_init, sys_fanotify_init), // 262
+ LINX_(__NR_fanotify_mark, sys_fanotify_mark), // 263
LINXY(__NR_name_to_handle_at, sys_name_to_handle_at), // 264
LINXY(__NR_open_by_handle_at, sys_open_by_handle_at), // 265
-
+ LINXY(__NR_clock_adjtime, sys_clock_adjtime), // 266
LINX_(__NR_syncfs, sys_syncfs), // 267
-
+ // (__NR_setns, sys_ni_syscall), // 268
LINXY(__NR_sendmmsg, sys_sendmmsg), // 269
LINXY(__NR_process_vm_readv, sys_process_vm_readv), // 270
LINX_(__NR_process_vm_writev, sys_process_vm_writev), // 271
-
+ LINX_(__NR_kcmp, sys_kcmp), // 272
+ // (__NR_finit_module, sys_ni_syscall), // 273
+ // (__NR_sched_setattr, sys_ni_syscall), // 274
+ // (__NR_sched_getattr, sys_ni_syscall), // 275
LINX_(__NR_renameat2, sys_renameat2), // 276
-
+ // (__NR_seccomp, sys_ni_syscall), // 277
LINXY(__NR_getrandom, sys_getrandom), // 278
LINXY(__NR_memfd_create, sys_memfd_create), // 279
-
-// The numbers below are bogus. (See comment further down.)
-// When pulling entries above this line, change the numbers
-// to be correct.
-
-//ZZ //zz // (restart_syscall) // 0
-//ZZ GENX_(__NR_fork, sys_fork), // 2
-//ZZ
-//ZZ GENXY(__NR_open, sys_open), // 5
-//ZZ // GENXY(__NR_waitpid, sys_waitpid), // 7
-//ZZ GENXY(__NR_creat, sys_creat), // 8
-//ZZ GENX_(__NR_link, sys_link), // 9
-//ZZ
-//ZZ GENX_(__NR_unlink, sys_unlink), // 10
-//ZZ GENXY(__NR_time, sys_time), // 13
-//ZZ GENX_(__NR_mknod, sys_mknod), // 14
-//ZZ
-//ZZ GENX_(__NR_chmod, sys_chmod), // 15
-//ZZ //zz LINX_(__NR_lchown, sys_lchown16), // 16
-//ZZ // GENX_(__NR_break, sys_ni_syscall), // 17
-//ZZ //zz // (__NR_oldstat, sys_stat), // 18 (obsolete)
-//ZZ LINX_(__NR_lseek, sys_lseek), // 19
-//ZZ
-//ZZ GENX_(__NR_getpid, sys_getpid), // 20
-//ZZ LINX_(__NR_umount, sys_oldumount), // 22
-//ZZ LINX_(__NR_setuid, sys_setuid16), // 23 ## P
-//ZZ LINX_(__NR_getuid, sys_getuid16), // 24 ## P
-//ZZ //zz
-//ZZ //zz // (__NR_stime, sys_stime), // 25 * (SVr4,SVID,X/OPEN)
-//ZZ PLAXY(__NR_ptrace, sys_ptrace), // 26
-//ZZ GENX_(__NR_alarm, sys_alarm), // 27
-//ZZ //zz // (__NR_oldfstat, sys_fstat), // 28 * L -- obsolete
-//ZZ GENX_(__NR_pause, sys_pause), // 29
-//ZZ
-//ZZ LINX_(__NR_utime, sys_utime), // 30
-//ZZ // GENX_(__NR_stty, sys_ni_syscall), // 31
-//ZZ // GENX_(__NR_gtty, sys_ni_syscall), // 32
-//ZZ GENX_(__NR_access, sys_access), // 33
-//ZZ GENX_(__NR_nice, sys_nice), // 34
-//ZZ
-//ZZ // GENX_(__NR_ftime, sys_ni_syscall), // 35
-//ZZ GENX_(__NR_rename, sys_rename), // 38
-//ZZ GENX_(__NR_mkdir, sys_mkdir), // 39
-//ZZ
-//ZZ GENX_(__NR_rmdir, sys_rmdir), // 40
-//ZZ LINXY(__NR_pipe, sys_pipe), // 42
-//ZZ // GENX_(__NR_prof, sys_ni_syscall), // 44
-
-//ZZ LINX_(__NR_getgid, sys_getgid16), // 47
-//ZZ //zz // (__NR_signal, sys_signal), // 48 */* (ANSI C)
-//ZZ LINX_(__NR_geteuid, sys_geteuid16), // 49
-//ZZ
-//ZZ LINX_(__NR_getegid, sys_getegid16), // 50
-//ZZ // GENX_(__NR_lock, sys_ni_syscall), // 53
-//ZZ
-//ZZ LINXY(__NR_fcntl, sys_fcntl), // 55
-//ZZ // GENX_(__NR_mpx, sys_ni_syscall), // 56
-//ZZ // GENX_(__NR_ulimit, sys_ni_syscall), // 58
-//ZZ //zz // (__NR_oldolduname, sys_olduname), // 59 Linux -- obsolete
-//ZZ //zz
-//ZZ //zz // (__NR_ustat, sys_ustat) // 62 SVr4 -- deprecated
-//ZZ GENXY(__NR_dup2, sys_dup2), // 63
-//ZZ GENX_(__NR_getppid, sys_getppid), // 64
-//ZZ
-//ZZ GENX_(__NR_getpgrp, sys_getpgrp), // 65
-//ZZ LINXY(__NR_sigaction, sys_sigaction), // 67
-//ZZ //zz // (__NR_sgetmask, sys_sgetmask), // 68 */* (ANSI C)
-//ZZ //zz // (__NR_ssetmask, sys_ssetmask), // 69 */* (ANSI C)
-//ZZ //zz
-//ZZ PLAX_(__NR_sigsuspend, sys_sigsuspend), // 72
-//ZZ LINXY(__NR_sigpending, sys_sigpending), // 73
-//ZZ //zz // (__NR_sethostname, sys_sethostname), // 74 */*
-//ZZ //zz
-//ZZ GENXY(__NR_getrlimit, sys_old_getrlimit), // 76
-//ZZ
-//ZZ LINXY(__NR_getgroups, sys_getgroups16), // 80
-//ZZ LINX_(__NR_setgroups, sys_setgroups16), // 81
-//ZZ // PLAX_(__NR_select, old_select), // 82
-//ZZ GENX_(__NR_symlink, sys_symlink), // 83
-//ZZ //zz // (__NR_oldlstat, sys_lstat), // 84 -- obsolete
-//ZZ //zz
-//ZZ GENX_(__NR_readlink, sys_readlink), // 85
-//ZZ //zz // (__NR_uselib, sys_uselib), // 86 */Linux
-//ZZ //zz // (__NR_swapon, sys_swapon), // 87 */Linux
-//ZZ //zz // (__NR_reboot, sys_reboot), // 88 */Linux
-//ZZ //zz // (__NR_readdir, old_readdir), // 89 -- superseded
-//ZZ //zz
-//ZZ // _____(__NR_mmap, old_mmap), // 90
-//ZZ GENXY(__NR_munmap, sys_munmap), // 91
-//ZZ GENX_(__NR_truncate, sys_truncate), // 92
-//ZZ GENX_(__NR_ftruncate, sys_ftruncate), // 93
-//ZZ
-//ZZ LINX_(__NR_fchown, sys_fchown16), // 95
-//ZZ // GENX_(__NR_profil, sys_ni_syscall), // 98
-//ZZ GENXY(__NR_statfs, sys_statfs), // 99
-//ZZ
-//ZZ GENXY(__NR_fstatfs, sys_fstatfs), // 100
-//ZZ // LINX_(__NR_ioperm, sys_ioperm), // 101
-//ZZ LINXY(__NR_socketcall, sys_socketcall), // 102
-//ZZ
-//ZZ GENXY(__NR_stat, sys_newstat), // 106
-//ZZ GENXY(__NR_lstat, sys_newlstat), // 107
-//ZZ GENXY(__NR_fstat, sys_newfstat), // 108
-//ZZ //zz // (__NR_olduname, sys_uname), // 109 -- obsolete
-//ZZ //zz
-//ZZ // GENX_(__NR_iopl, sys_iopl), // 110
-//ZZ // GENX_(__NR_idle, sys_ni_syscall), // 112
-//ZZ // PLAXY(__NR_vm86old, sys_vm86old), // 113 __NR_syscall... weird
-//ZZ //zz
-//ZZ //zz // (__NR_swapoff, sys_swapoff), // 115 */Linux
-//ZZ // _____(__NR_ipc, sys_ipc), // 117
-//ZZ GENX_(__NR_fsync, sys_fsync), // 118
-//ZZ PLAX_(__NR_sigreturn, sys_sigreturn), // 119 ?/Linux
-//ZZ
-//ZZ //zz // (__NR_setdomainname, sys_setdomainname), // 121 */*(?)
-//ZZ // PLAX_(__NR_modify_ldt, sys_modify_ldt), // 123
-//ZZ //zz
-//ZZ LINXY(__NR_sigprocmask, sys_sigprocmask), // 126
-//ZZ //zz // Nb: create_module() was removed 2.4-->2.6
-//ZZ // GENX_(__NR_create_module, sys_ni_syscall), // 127
-//ZZ LINX_(__NR_delete_module, sys_delete_module), // 129
-//ZZ //zz
-//ZZ //zz // Nb: get_kernel_syms() was removed 2.4-->2.6
-//ZZ // GENX_(__NR_get_kernel_syms, sys_ni_syscall), // 130
-//ZZ GENX_(__NR_getpgid, sys_getpgid), // 132
-//ZZ //zz // (__NR_bdflush, sys_bdflush), // 134 */Linux
-//ZZ //zz
-//ZZ //zz // (__NR_sysfs, sys_sysfs), // 135 SVr4
-//ZZ // GENX_(__NR_afs_syscall, sys_ni_syscall), // 137
-//ZZ
-//ZZ LINXY(__NR__llseek, sys_llseek), // 140
-//ZZ GENXY(__NR_getdents, sys_getdents), // 141
-//ZZ GENX_(__NR__newselect, sys_select), // 142
-//ZZ
-//ZZ LINXY(__NR__sysctl, sys_sysctl), // 149
-//ZZ
-//ZZ //zz //LINX?(__NR_sched_rr_get_interval, sys_sched_rr_get_interval), // 161 */*
-//ZZ LINX_(__NR_setresuid, sys_setresuid16), // 164
-//ZZ
-//ZZ LINXY(__NR_getresuid, sys_getresuid16), // 165
-//ZZ // PLAXY(__NR_vm86, sys_vm86), // 166 x86/Linux-only
-//ZZ // GENX_(__NR_query_module, sys_ni_syscall), // 167
-//ZZ GENXY(__NR_poll, sys_poll), // 168
-//ZZ //zz // (__NR_nfsservctl, sys_nfsservctl), // 169 */Linux
-//ZZ //zz
-//ZZ LINX_(__NR_setresgid, sys_setresgid16), // 170
-//ZZ LINXY(__NR_getresgid, sys_getresgid16), // 171
-//ZZ LINXY(__NR_prctl, sys_prctl), // 172
-//ZZ LINXY(__NR_rt_sigaction, sys_rt_sigaction), // 174
-//ZZ
-//ZZ LINXY(__NR_rt_sigtimedwait, sys_rt_sigtimedwait),// 177
-//ZZ
-//ZZ LINX_(__NR_chown, sys_chown16), // 182
-//ZZ
-//ZZ LINXY(__NR_sendfile, sys_sendfile), // 187
-//ZZ // GENXY(__NR_getpmsg, sys_getpmsg), // 188
-//ZZ // GENX_(__NR_putpmsg, sys_putpmsg), // 189
-//ZZ
-//ZZ // Nb: we treat vfork as fork
-//ZZ GENX_(__NR_vfork, sys_fork), // 190
-//ZZ GENXY(__NR_ugetrlimit, sys_getrlimit), // 191
-//ZZ GENX_(__NR_truncate64, sys_truncate64), // 193
-//ZZ GENX_(__NR_ftruncate64, sys_ftruncate64), // 194
-//ZZ
-//ZZ PLAXY(__NR_stat64, sys_stat64), // 195
-//ZZ PLAXY(__NR_lstat64, sys_lstat64), // 196
-//ZZ PLAXY(__NR_fstat64, sys_fstat64), // 197
-//ZZ GENX_(__NR_lchown32, sys_lchown), // 198
-//ZZ GENX_(__NR_getuid32, sys_getuid), // 199
-//ZZ
-//ZZ GENX_(__NR_getgid32, sys_getgid), // 200
-//ZZ GENX_(__NR_geteuid32, sys_geteuid), // 201
-//ZZ GENX_(__NR_getegid32, sys_getegid), // 202
-//ZZ GENX_(__NR_setreuid32, sys_setreuid), // 203
-//ZZ GENX_(__NR_setregid32, sys_setregid), // 204
-//ZZ
-//ZZ LINX_(__NR_setresuid32, sys_setresuid), // 208
-//ZZ LINXY(__NR_getresuid32, sys_getresuid), // 209
-//ZZ
-//ZZ LINX_(__NR_setresgid32, sys_setresgid), // 210
-//ZZ LINXY(__NR_getresgid32, sys_getresgid), // 211
-//ZZ GENX_(__NR_chown32, sys_chown), // 212
-//ZZ GENX_(__NR_setuid32, sys_setuid), // 213
-//ZZ GENX_(__NR_setgid32, sys_setgid), // 214
-//ZZ
-//ZZ LINX_(__NR_setfsuid32, sys_setfsuid), // 215
-//ZZ LINX_(__NR_setfsgid32, sys_setfsgid), // 216
-//ZZ //zz // (__NR_pivot_root, sys_pivot_root), // 217 */Linux
-//ZZ
-//ZZ LINXY(__NR_fcntl64, sys_fcntl64), // 221
-//ZZ // GENX_(222, sys_ni_syscall), // 222
-//ZZ // PLAXY(223, sys_syscall223), // 223 // sys_bproc?
-//ZZ
-//ZZ LINXY(__NR_tkill, sys_tkill), // 238 */Linux
-//ZZ
-//ZZ LINXY(__NR_futex, sys_futex), // 240
-//ZZ LINXY(__NR_sched_getaffinity, sys_sched_getaffinity), // 242
-//ZZ // PLAX_(__NR_set_thread_area, sys_set_thread_area), // 243
-//ZZ // PLAX_(__NR_get_thread_area, sys_get_thread_area), // 244
-//ZZ
-//ZZ // LINX_(__NR_fadvise64, sys_fadvise64), // 250 */(Linux?)
-//ZZ GENX_(251, sys_ni_syscall), // 251
-//ZZ LINXY(__NR_epoll_create, sys_epoll_create), // 254
-//ZZ
-//ZZ LINX_(__NR_epoll_ctl, sys_epoll_ctl), // 255
-//ZZ LINXY(__NR_epoll_wait, sys_epoll_wait), // 256
-//ZZ //zz // (__NR_remap_file_pages, sys_remap_file_pages), // 257 */Linux
-//ZZ LINX_(__NR_set_tid_address, sys_set_tid_address), // 258
-//ZZ
-//ZZ LINXY(__NR_clock_getres, sys_clock_getres), // (timer_create+7)
-//ZZ GENXY(__NR_statfs64, sys_statfs64), // 268
-//ZZ GENXY(__NR_fstatfs64, sys_fstatfs64), // 269
-//ZZ
-//ZZ GENX_(__NR_utimes, sys_utimes), // 271
-//ZZ // LINX_(__NR_fadvise64_64, sys_fadvise64_64), // 272 */(Linux?)
-//ZZ GENX_(__NR_vserver, sys_ni_syscall), // 273
-//ZZ LINX_(__NR_mbind, sys_mbind), // 274 ?/?
-//ZZ
-//ZZ LINXY(__NR_get_mempolicy, sys_get_mempolicy), // 275 ?/?
-//ZZ LINX_(__NR_set_mempolicy, sys_set_mempolicy), // 276 ?/?
-//ZZ
-//ZZ LINX_(__NR_send, sys_send),
-//ZZ LINXY(__NR_recv, sys_recv),
-//ZZ LINXY(__NR_recvfrom, sys_recvfrom), // 292
-//ZZ LINX_(__NR_semget, sys_semget), // 299
-//ZZ LINXY(__NR_semctl, sys_semctl), // 300
-//ZZ
-//ZZ LINX_(__NR_request_key, sys_request_key), // 287
-//ZZ LINX_(__NR_inotify_init, sys_inotify_init), // 291
-//ZZ // LINX_(__NR_migrate_pages, sys_migrate_pages), // 294
-//ZZ
-//ZZ LINX_(__NR_futimesat, sys_futimesat), // 326 on arm
-//ZZ
-//ZZ PLAXY(__NR_fstatat64, sys_fstatat64), // 300
-//ZZ LINX_(__NR_renameat, sys_renameat), // 302
-//ZZ LINX_(__NR_symlinkat, sys_symlinkat), // 304
-//ZZ
-//ZZ LINX_(__NR_shmget, sys_shmget), //307
-//ZZ // LINX_(__NR_pselect6, sys_pselect6), //
-//ZZ
-//ZZ // LINX_(__NR_unshare, sys_unshare), // 310
-//ZZ LINX_(__NR_set_robust_list, sys_set_robust_list), // 311
-//ZZ LINXY(__NR_get_robust_list, sys_get_robust_list), // 312
-//ZZ // LINX_(__NR_sync_file_range, sys_sync_file_range), // 314
-//ZZ
-//ZZ LINXY(__NR_move_pages, sys_move_pages), // 317
-//ZZ // LINX_(__NR_getcpu, sys_ni_syscall), // 318
-//ZZ
-//ZZ LINXY(__NR_signalfd, sys_signalfd), // 321
-//ZZ LINXY(__NR_eventfd, sys_eventfd), // 323
-//ZZ
-//ZZ
-//ZZ ///////////////
-//ZZ
-//ZZ // JRS 2010-Jan-03: I believe that all the numbers listed
-//ZZ // in comments in the table prior to this point (eg "// 326",
-//ZZ // etc) are bogus since it looks to me like they are copied
-//ZZ // verbatim from syswrap-x86-linux.c and they certainly do not
-//ZZ // correspond to what's in include/vki/vki-scnums-arm-linux.h.
-//ZZ // From here onwards, please ensure the numbers are correct.
-//ZZ
-//ZZ
-//ZZ LINXY(__NR_epoll_pwait, sys_epoll_pwait), // 346
-//ZZ
-//ZZ
-//ZZ LINXY(__NR_eventfd2, sys_eventfd2), // 356
-//ZZ LINXY(__NR_epoll_create1, sys_epoll_create1), // 357
-//ZZ LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo),// 363
-//ZZ
-//ZZ LINXY(__NR_clock_adjtime, sys_clock_adjtime) // 372
+ // (__NR_bpf, sys_ni_syscall) // 280
+ // (__NR_execveat, sys_ni_syscall), // 281
+ // (__NR_userfaultfd, sys_ni_syscall), // 282
+ // (__NR_membarrier, sys_ni_syscall), // 283
+ // (__NR_mlock2, sys_ni_syscall), // 284
+ // (__NR_copy_file_range, sys_ni_syscall), // 285
+ // (__NR_preadv2, sys_ni_syscall), // 286
+ // (__NR_pwritev2, sys_ni_syscall), // 287
+ // (__NR_pkey_mprotect, sys_ni_syscall), // 288
+ // (__NR_pkey_alloc, sys_ni_syscall), // 289
+ // (__NR_pkey_free, sys_ni_syscall), // 290
};
diff --git a/coregrind/m_syswrap/syswrap-darwin.c b/coregrind/m_syswrap/syswrap-darwin.c
index 206d57f..f219920 100644
--- a/coregrind/m_syswrap/syswrap-darwin.c
+++ b/coregrind/m_syswrap/syswrap-darwin.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Apple Inc.
+ Copyright (C) 2005-2017 Apple Inc.
Greg Parker gparker@apple.com
This program is free software; you can redistribute it and/or
@@ -53,6 +53,7 @@
#include "pub_core_scheduler.h"
#include "pub_core_sigframe.h" // For VG_(sigframe_destroy)()
#include "pub_core_signals.h"
+#include "pub_core_stacks.h"
#include "pub_core_syscall.h"
#include "pub_core_syswrap.h"
#include "pub_core_tooliface.h"
@@ -205,6 +206,10 @@
c = VG_(count_living_threads)();
vg_assert(c >= 1); /* stay sane */
+ /* Deregister thread's stack. */
+ if (tst->os_state.stk_id != NULL_STK_ID)
+ VG_(deregister_stack)(tst->os_state.stk_id);
+
// Tell the tool this thread is exiting
VG_TRACK( pre_thread_ll_exit, tid );
@@ -221,7 +226,7 @@
"WARNING: of the VALGRIND_DISABLE_ERROR_REPORTING macros.\n"
);
VG_(debugLog)(
- 1, "syswrap-linux",
+ 1, "syswrap-darwin",
"run_a_thread_NORETURN(tid=%u): "
"WARNING: exiting thread has err_disablement_level = %u\n",
tid, tst->err_disablement_level
@@ -4026,7 +4031,7 @@
}
POST(getdirentries64)
{
- /* Disabled; see coments in the PRE wrapper.
+ /* Disabled; see comments in the PRE wrapper.
POST_MEM_WRITE(ARG4, sizeof(vki_off_t));
*/
// GrP fixme be specific about d_name? (fixme copied from 32 bit version)
@@ -8202,6 +8207,16 @@
case 3420:
CALL_PRE(task_policy_set);
return;
+
+#if DARWIN_VERS >= DARWIN_10_12
+ case 3444:
+ CALL_PRE(task_register_dyld_image_infos);
+ return;
+
+ case 3447:
+ CALL_PRE(task_register_dyld_shared_cache_image_info);
+ return;
+#endif /* DARWIN_VERS >= DARWIN_10_12 */
case 3801:
CALL_PRE(vm_allocate);
@@ -9694,6 +9709,22 @@
POST_MEM_WRITE(ARG3, ARG4);
}
+PRE(faccessat)
+{
+ PRINT("faccessat(FIXME)(fd:%ld, path:%#lx(%s), amode:%#lx, flag:%#lx)",
+ ARG1, ARG2, (HChar*)ARG2, ARG3, ARG4);
+ PRE_REG_READ4(int, "faccessat",
+ int, fd, user_addr_t, path, int, amode, int, flag);
+}
+
+PRE(fstatat64)
+{
+ PRINT("fstatat64(FIXME)(fd:%ld, path:%#lx(%s), ub:%#lx, flag:%#lx)",
+ ARG1, ARG2, (HChar*)ARG2, ARG3, ARG4);
+ PRE_REG_READ4(int, "fstatat64",
+ int, fd, user_addr_t, path, user_addr_t, ub, int, flag);
+}
+
PRE(readlinkat)
{
Word saved = SYSNO;
@@ -9726,6 +9757,13 @@
void*, cmd, void*, arg1, void*, arg2, void*, arg3);
}
+PRE(csrctl)
+{
+ PRINT("csrctl(op:%ld, useraddr:%#lx, usersize:%#lx) FIXME", ARG1, ARG2, ARG3);
+ PRE_REG_READ3(int, "csrctl",
+ uint32_t, op, user_addr_t, useraddr, user_addr_t, usersize);
+}
+
PRE(guarded_open_dprotected_np)
{
PRINT("guarded_open_dprotected_np("
@@ -9756,6 +9794,113 @@
/* ---------------------------------------------------------------------
+ Added for macOS 10.12 (Sierra)
+ ------------------------------------------------------------------ */
+
+#if DARWIN_VERS >= DARWIN_10_12
+
+PRE(getentropy)
+{
+ PRINT("getentropy(buffer:%#lx, size:%ld) FIXME", ARG1, ARG2);
+ PRE_REG_READ2(int, "getentropy",
+ void*, buffer, size_t, size);
+}
+
+PRE(ulock_wake)
+{
+ PRINT("ulock_wake(operation:%ld, addr:%#lx, wake_value:%ld) FIXME",
+ ARG1, ARG2, ARG3);
+ PRE_REG_READ3(int, "ulock_wake",
+ uint32_t, operation, void*, addr, uint64_t, wake_value);
+}
+
+PRE(host_create_mach_voucher_trap)
+{
+ // munge_wwww -- no need to call helper
+ PRINT("host_create_mach_voucher_trap"
+ "(host:%#lx, recipes:%#lx, recipes_size:%ld, voucher:%#lx) FIXME",
+ ARG1, ARG2, ARG3, ARG4);
+}
+
+PRE(task_register_dyld_image_infos)
+{
+#pragma pack(4)
+ typedef struct {
+ mach_msg_header_t Head;
+ /* start of the kernel processed data */
+ mach_msg_body_t msgh_body;
+ mach_msg_ool_descriptor_t dyld_images;
+ /* end of the kernel processed data */
+ NDR_record_t NDR;
+ mach_msg_type_number_t dyld_imagesCnt;
+ } Request;
+#pragma pack()
+
+ // Request *req = (Request *)ARG1;
+
+ PRINT("task_register_dyld_image_infos(%s)", name_for_port(MACH_REMOTE));
+
+ AFTER = POST_FN(task_register_dyld_image_infos);
+}
+
+POST(task_register_dyld_image_infos)
+{
+#pragma pack(4)
+ typedef struct {
+ mach_msg_header_t Head;
+ NDR_record_t NDR;
+ kern_return_t RetCode;
+ } Reply;
+#pragma pack()
+
+ Reply *reply = (Reply *)ARG1;
+ if (!reply->RetCode) {
+ } else {
+ PRINT("mig return %d", reply->RetCode);
+ }
+}
+
+PRE(task_register_dyld_shared_cache_image_info)
+{
+#pragma pack(4)
+ typedef struct {
+ mach_msg_header_t Head;
+ NDR_record_t NDR;
+ dyld_kernel_image_info_t dyld_cache_image;
+ boolean_t no_cache;
+ boolean_t private_cache;
+ } Request;
+#pragma pack()
+
+ // Request *req = (Request *)ARG1;
+
+ PRINT("task_register_dyld_shared_cache_image_info(%s)",
+ name_for_port(MACH_REMOTE));
+
+ AFTER = POST_FN(task_register_dyld_shared_cache_image_info);
+}
+
+POST(task_register_dyld_shared_cache_image_info)
+{
+#pragma pack(4)
+ typedef struct {
+ mach_msg_header_t Head;
+ NDR_record_t NDR;
+ kern_return_t RetCode;
+ } Reply;
+#pragma pack()
+
+ Reply *reply = (Reply *)ARG1;
+ if (!reply->RetCode) {
+ } else {
+ PRINT("mig return %d", reply->RetCode);
+ }
+}
+
+#endif /* DARWIN_VERS >= DARWIN_10_12 */
+
+
+/* ---------------------------------------------------------------------
syscall tables
------------------------------------------------------------------ */
@@ -10274,6 +10419,16 @@
#endif
#if DARWIN_VERS >= DARWIN_10_9
MACX_(__NR_fileport_makeport, fileport_makeport),
+// _____(__NR_fileport_makefd), // 431
+// _____(__NR_audit_session_port), // 432
+// _____(__NR_pid_suspend), // 433
+// _____(__NR_pid_resume), // 434
+ _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(435)), // ???
+ _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(436)), // ???
+ _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(437)), // ???
+// _____(__NR_shared_region_map_and_slide_np), // 438
+// _____(__NR_kas_info), // 439
+// _____(__NR_memorystatus_control), // 440
MACX_(__NR_guarded_open_np, guarded_open_np),
MACX_(__NR_guarded_close_np, guarded_close_np),
MACX_(__NR_guarded_kqueue_np, guarded_kqueue_np),
@@ -10285,15 +10440,58 @@
MACXY(__NR_sysctlbyname, sysctlbyname), // 274
MACXY(__NR_necp_match_policy, necp_match_policy), // 460
MACXY(__NR_getattrlistbulk, getattrlistbulk), // 461
+ MACX_(__NR_faccessat, faccessat), // 466
+ MACX_(__NR_fstatat64, fstatat64), // 470
MACX_(__NR_readlinkat, readlinkat), // 473
MACX_(__NR_bsdthread_ctl, bsdthread_ctl), // 478
+ MACX_(__NR_csrctl, csrctl), // 483
MACX_(__NR_guarded_open_dprotected_np, guarded_open_dprotected_np), // 484
MACX_(__NR_guarded_write_np, guarded_write_np), // 485
MACX_(__NR_guarded_pwrite_np, guarded_pwrite_np), // 486
MACX_(__NR_guarded_writev_np, guarded_writev_np), // 487
-// _____(__NR___rename_ext), // 488
// _____(__NR___mremap_encrypted), // 489
#endif
+#if DARWIN_VERS >= DARWIN_10_11
+// _____(__NR_kdebug_trace_string), // 178
+// _____(__NR_kevent_qos), // 374
+// _____(__NR_netagent_trigger), // 490
+// _____(__NR_stack_snapshot_with_config), // 491
+// _____(__NR_microstackshot), // 492
+// _____(__NR_grab_pgo_data), // 493
+// _____(__NR_persona), // 494
+ _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(495)), // ???
+ _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(496)), // ???
+ _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(497)), // ???
+ _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(498)), // ???
+// _____(__NR_work_interval_ctl), // 499
+#endif
+#if DARWIN_VERS >= DARWIN_10_12
+// _____(__NR_kdebug_typefilter), // 177
+// _____(__NR_clonefileat), // 462
+// _____(__NR_renameatx_np), // 488
+ MACX_(__NR_getentropy, getentropy), // 500
+// _____(__NR_necp_open), // 501
+// _____(__NR_necp_client_action), // 502
+ _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(503)), // ???
+ _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(504)), // ???
+ _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(505)), // ???
+ _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(506)), // ???
+ _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(507)), // ???
+ _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(508)), // ???
+ _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(509)), // ???
+ _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(510)), // ???
+ _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(511)), // ???
+ _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(512)), // ???
+ _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(513)), // ???
+ _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(514)), // ???
+// _____(__NR_ulock_wait), // 515
+ MACX_(__NR_ulock_wake, ulock_wake), // 516
+// _____(__NR_fclonefileat), // 517
+// _____(__NR_fs_snapshot), // 518
+ _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(519)), // ???
+// _____(__NR_terminate_with_payload), // 520
+// _____(__NR_abort_with_payload), // 521
+#endif
// _____(__NR_MAXSYSCALL)
MACX_(__NR_DARWIN_FAKE_SIGRETURN, FAKE_SIGRETURN)
};
@@ -10444,8 +10642,12 @@
_____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(66)),
_____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(67)),
_____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(68)),
- _____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(69)),
+ _____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(69)),
+#if DARWIN_VERS >= DARWIN_10_12
+ MACX_(__NR_host_create_mach_voucher_trap, host_create_mach_voucher_trap),
+#else
_____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(70)),
+#endif
_____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(71)),
_____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(72)),
_____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(73)),
diff --git a/coregrind/m_syswrap/syswrap-generic.c b/coregrind/m_syswrap/syswrap-generic.c
index 957a615..b0fbfd9 100644
--- a/coregrind/m_syswrap/syswrap-generic.c
+++ b/coregrind/m_syswrap/syswrap-generic.c
@@ -9,7 +9,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -79,16 +79,19 @@
assume that sp starts near its highest possible value, and can
only go down to the start of the mmaped segment. */
seg = VG_(am_find_nsegment)(sp);
- if (seg &&
- VG_(am_is_valid_for_client)(sp, 1, VKI_PROT_READ | VKI_PROT_WRITE)) {
+ if (seg
+ && VG_(am_is_valid_for_client)(sp, 1, VKI_PROT_READ | VKI_PROT_WRITE)) {
tst->client_stack_highest_byte = (Addr)VG_PGROUNDUP(sp)-1;
tst->client_stack_szB = tst->client_stack_highest_byte - seg->start + 1;
- VG_(register_stack)(seg->start, tst->client_stack_highest_byte);
+ tst->os_state.stk_id
+ = VG_(register_stack)(seg->start, tst->client_stack_highest_byte);
if (debug)
- VG_(printf)("tid %u: guessed client stack range [%#lx-%#lx]\n",
- tst->tid, seg->start, tst->client_stack_highest_byte);
+ VG_(printf)("tid %u: guessed client stack range [%#lx-%#lx]"
+ " as stk_id %lu\n",
+ tst->tid, seg->start, tst->client_stack_highest_byte,
+ tst->os_state.stk_id);
} else {
VG_(message)(Vg_UserMsg,
"!? New thread %u starts with SP(%#lx) unmapped\n",
@@ -328,8 +331,8 @@
old_seg = VG_(am_find_nsegment)( old_addr );
if (old_addr < old_seg->start || old_addr+old_len-1 > old_seg->end)
goto eINVAL;
- if (old_seg->kind != SkAnonC && old_seg->kind != SkFileC &&
- old_seg->kind != SkShmC)
+ if (old_seg->kind != SkAnonC && old_seg->kind != SkFileC
+ && old_seg->kind != SkShmC)
goto eINVAL;
vg_assert(old_len > 0);
@@ -969,38 +972,25 @@
#endif
}
-static
-HChar *strdupcat ( const HChar* cc, const HChar *s1, const HChar *s2,
- ArenaId aid )
-{
- UInt len = VG_(strlen) ( s1 ) + VG_(strlen) ( s2 ) + 1;
- HChar *result = VG_(arena_malloc) ( aid, cc, len );
- VG_(strcpy) ( result, s1 );
- VG_(strcat) ( result, s2 );
- return result;
-}
-
static
void pre_mem_read_sendmsg ( ThreadId tid, Bool read,
const HChar *msg, Addr base, SizeT size )
{
- HChar *outmsg = strdupcat ( "di.syswrap.pmrs.1",
- "sendmsg", msg, VG_AR_CORE );
+ HChar outmsg[VG_(strlen)(msg) + 10]; // large enough
+ VG_(sprintf)(outmsg, "sendmsg%s", msg);
PRE_MEM_READ( outmsg, base, size );
- VG_(free) ( outmsg );
}
static
void pre_mem_write_recvmsg ( ThreadId tid, Bool read,
const HChar *msg, Addr base, SizeT size )
{
- HChar *outmsg = strdupcat ( "di.syswrap.pmwr.1",
- "recvmsg", msg, VG_AR_CORE );
+ HChar outmsg[VG_(strlen)(msg) + 10]; // large enough
+ VG_(sprintf)(outmsg, "recvmsg%s", msg);
if ( read )
PRE_MEM_READ( outmsg, base, size );
else
PRE_MEM_WRITE( outmsg, base, size );
- VG_(free) ( outmsg );
}
static
@@ -1021,21 +1011,36 @@
Bool rekv /* "recv" apparently shadows some header decl on OSX108 */
)
{
- HChar *fieldName;
+ HChar fieldName[VG_(strlen)(name) + 32]; // large enough.
+ Addr a;
+ SizeT s;
if ( !msg )
return;
- fieldName = VG_(malloc) ( "di.syswrap.mfef", VG_(strlen)(name) + 32 );
-
VG_(sprintf) ( fieldName, "(%s)", name );
- foreach_func ( tid, True, fieldName, (Addr)&msg->msg_name, sizeof( msg->msg_name ) );
- foreach_func ( tid, True, fieldName, (Addr)&msg->msg_namelen, sizeof( msg->msg_namelen ) );
- foreach_func ( tid, True, fieldName, (Addr)&msg->msg_iov, sizeof( msg->msg_iov ) );
- foreach_func ( tid, True, fieldName, (Addr)&msg->msg_iovlen, sizeof( msg->msg_iovlen ) );
- foreach_func ( tid, True, fieldName, (Addr)&msg->msg_control, sizeof( msg->msg_control ) );
- foreach_func ( tid, True, fieldName, (Addr)&msg->msg_controllen, sizeof( msg->msg_controllen ) );
+ /* FIELDPAIR helps the compiler do one call to foreach_func
+ for consecutive (no holes) fields. */
+#define FIELDPAIR(f1,f2) \
+ if (offsetof(struct vki_msghdr, f1) + sizeof(msg->f1) \
+ == offsetof(struct vki_msghdr, f2)) \
+ s += sizeof(msg->f2); \
+ else { \
+ foreach_func (tid, True, fieldName, a, s); \
+ a = (Addr)&msg->f2; \
+ s = sizeof(msg->f2); \
+ }
+
+ a = (Addr)&msg->msg_name;
+ s = sizeof(msg->msg_name);
+ FIELDPAIR(msg_name, msg_namelen);
+ FIELDPAIR(msg_namelen, msg_iov);
+ FIELDPAIR(msg_iov, msg_iovlen);
+ FIELDPAIR(msg_iovlen, msg_control);
+ FIELDPAIR(msg_control, msg_controllen);
+ foreach_func ( tid, True, fieldName, a, s);
+#undef FIELDPAIR
/* msg_flags is completely ignored for send_mesg, recv_mesg doesn't read
the field, but does write to it. */
@@ -1054,9 +1059,8 @@
struct vki_iovec *iov = msg->msg_iov;
UInt i;
- VG_(sprintf) ( fieldName, "(%s.msg_iov)", name );
-
if (ML_(safe_to_deref)(&msg->msg_iovlen, sizeof (UInt))) {
+ VG_(sprintf) ( fieldName, "(%s.msg_iov)", name );
foreach_func ( tid, True, fieldName, (Addr)iov,
msg->msg_iovlen * sizeof( struct vki_iovec ) );
@@ -1073,14 +1077,12 @@
}
if ( ML_(safe_to_deref) (&msg->msg_control, sizeof (void *))
- && msg->msg_control )
- {
+ && msg->msg_control ) {
VG_(sprintf) ( fieldName, "(%s.msg_control)", name );
foreach_func ( tid, False, fieldName,
(Addr)msg->msg_control, msg->msg_controllen );
}
- VG_(free) ( fieldName );
}
static void check_cmsg_for_fds(ThreadId tid, struct vki_msghdr *msg)
@@ -1088,8 +1090,8 @@
struct vki_cmsghdr *cm = VKI_CMSG_FIRSTHDR(msg);
while (cm) {
- if (cm->cmsg_level == VKI_SOL_SOCKET &&
- cm->cmsg_type == VKI_SCM_RIGHTS ) {
+ if (cm->cmsg_level == VKI_SOL_SOCKET
+ && cm->cmsg_type == VKI_SCM_RIGHTS ) {
Int *fds = (Int *) VKI_CMSG_DATA(cm);
Int fdc = (cm->cmsg_len - VKI_CMSG_ALIGN(sizeof(struct vki_cmsghdr)))
/ sizeof(int);
@@ -1112,7 +1114,7 @@
const HChar *description,
struct vki_sockaddr *sa, UInt salen )
{
- HChar *outmsg;
+ HChar outmsg[VG_(strlen)( description ) + 30]; // large enough
struct vki_sockaddr_un* saun = (struct vki_sockaddr_un *)sa;
struct vki_sockaddr_in* sin = (struct vki_sockaddr_in *)sa;
struct vki_sockaddr_in6* sin6 = (struct vki_sockaddr_in6 *)sa;
@@ -1126,17 +1128,12 @@
/* NULL/zero-length sockaddrs are legal */
if ( sa == NULL || salen == 0 ) return;
- outmsg = VG_(malloc) ( "di.syswrap.pmr_sockaddr.1",
- VG_(strlen)( description ) + 30 );
-
VG_(sprintf) ( outmsg, description, "sa_family" );
PRE_MEM_READ( outmsg, (Addr) &sa->sa_family, sizeof(vki_sa_family_t));
/* Don't do any extra checking if we cannot determine the sa_family. */
- if (! ML_(safe_to_deref) (&sa->sa_family, sizeof(vki_sa_family_t))) {
- VG_(free) (outmsg);
+ if (! ML_(safe_to_deref) (&sa->sa_family, sizeof(vki_sa_family_t)))
return;
- }
switch (sa->sa_family) {
@@ -1203,8 +1200,6 @@
salen - sizeof(sa->sa_family));
break;
}
-
- VG_(free) ( outmsg );
}
/* Dereference a pointer to a UInt. */
@@ -1327,16 +1322,29 @@
vg_assert(delta > 0);
vg_assert(VG_IS_PAGE_ALIGNED(delta));
- Bool overflow;
+ Bool overflow = False;
if (! VG_(am_extend_into_adjacent_reservation_client)( aseg->start, delta,
&overflow)) {
- if (overflow)
- VG_(umsg)("brk segment overflow in thread #%u: can't grow to %#lx\n",
- tid, newbrkP);
- else
- VG_(umsg)("Cannot map memory to grow brk segment in thread #%u "
- "to %#lx\n", tid, newbrkP);
- VG_(umsg)("(see section Limitations in user manual)\n");
+ if (overflow) {
+ static Bool alreadyComplained = False;
+ if (!alreadyComplained) {
+ alreadyComplained = True;
+ if (VG_(clo_verbosity) > 0) {
+ VG_(umsg)("brk segment overflow in thread #%u: "
+ "can't grow to %#lx\n",
+ tid, newbrkP);
+ VG_(umsg)("(see section Limitations in user manual)\n");
+ VG_(umsg)("NOTE: further instances of this message "
+ "will not be shown\n");
+ }
+ }
+ } else {
+ if (VG_(clo_verbosity) > 0) {
+ VG_(umsg)("Cannot map memory to grow brk segment in thread #%u "
+ "to %#lx\n", tid, newbrkP);
+ VG_(umsg)("(see section Limitations in user manual)\n");
+ }
+ }
goto bad;
}
@@ -2434,19 +2442,6 @@
#define PRE(name) DEFN_PRE_TEMPLATE(generic, name)
#define POST(name) DEFN_POST_TEMPLATE(generic, name)
-// Macros to support 64-bit syscall args split into two 32 bit values
-#if defined(VG_LITTLEENDIAN)
-#define MERGE64(lo,hi) ( ((ULong)(lo)) | (((ULong)(hi)) << 32) )
-#define MERGE64_FIRST(name) name##_low
-#define MERGE64_SECOND(name) name##_high
-#elif defined(VG_BIGENDIAN)
-#define MERGE64(hi,lo) ( ((ULong)(lo)) | (((ULong)(hi)) << 32) )
-#define MERGE64_FIRST(name) name##_high
-#define MERGE64_SECOND(name) name##_low
-#else
-#error Unknown endianness
-#endif
-
PRE(sys_exit)
{
ThreadState* tst;
@@ -2844,14 +2839,26 @@
SysRes res;
Bool setuid_allowed, trace_this_child;
- PRINT("sys_execve ( %#lx(%s), %#lx, %#lx )", ARG1, (char*)ARG1, ARG2, ARG3);
+ PRINT("sys_execve ( %#lx(%s), %#lx, %#lx )", ARG1, (HChar*)ARG1, ARG2, ARG3);
PRE_REG_READ3(vki_off_t, "execve",
char *, filename, char **, argv, char **, envp);
PRE_MEM_RASCIIZ( "execve(filename)", ARG1 );
- if (ARG2 != 0)
+ if (ARG2 != 0) {
+ /* At least the terminating NULL must be addressable. */
+ if (!ML_(safe_to_deref)((HChar **) ARG2, sizeof(HChar *))) {
+ SET_STATUS_Failure(VKI_EFAULT);
+ return;
+ }
ML_(pre_argv_envp)( ARG2, tid, "execve(argv)", "execve(argv[i])" );
- if (ARG3 != 0)
+ }
+ if (ARG3 != 0) {
+ /* At least the terminating NULL must be addressable. */
+ if (!ML_(safe_to_deref)((HChar **) ARG3, sizeof(HChar *))) {
+ SET_STATUS_Failure(VKI_EFAULT);
+ return;
+ }
ML_(pre_argv_envp)( ARG3, tid, "execve(envp)", "execve(envp[i])" );
+ }
vg_assert(VG_(is_valid_tid)(tid));
tst = VG_(get_ThreadState)(tid);
@@ -3319,18 +3326,6 @@
/* restore signal mask */
VG_(sigprocmask)(VKI_SIG_SETMASK, &fork_saved_mask, NULL);
-
- /* If --child-silent-after-fork=yes was specified, set the
- output file descriptors to 'impossible' values. This is
- noticed by send_bytes_to_logging_sink in m_libcprint.c, which
- duly stops writing any further output. */
- if (VG_(clo_child_silent_after_fork)) {
- if (!VG_(log_output_sink).is_socket)
- VG_(log_output_sink).fd = -1;
- if (!VG_(xml_output_sink).is_socket)
- VG_(xml_output_sink).fd = -1;
- }
-
} else {
VG_(do_atfork_parent)(tid);
@@ -3684,8 +3679,7 @@
UInt size = _VKI_IOC_SIZE(request);
if (size > 0 && (dir & _VKI_IOC_READ)
&& res == 0
- && arg != (Addr)NULL)
- {
+ && arg != (Addr)NULL) {
POST_MEM_WRITE(arg, size);
}
}
@@ -3836,10 +3830,10 @@
if (grows == VKI_PROT_GROWSDOWN) {
rseg = VG_(am_next_nsegment)( aseg, False/*backwards*/ );
- if (rseg &&
- rseg->kind == SkResvn &&
- rseg->smode == SmUpper &&
- rseg->end+1 == aseg->start) {
+ if (rseg
+ && rseg->kind == SkResvn
+ && rseg->smode == SmUpper
+ && rseg->end+1 == aseg->start) {
Addr end = ARG1 + ARG2;
ARG1 = aseg->start;
ARG2 = end - aseg->start;
@@ -3849,10 +3843,10 @@
}
} else if (grows == VKI_PROT_GROWSUP) {
rseg = VG_(am_next_nsegment)( aseg, True/*forwards*/ );
- if (rseg &&
- rseg->kind == SkResvn &&
- rseg->smode == SmLower &&
- aseg->end+1 == rseg->start) {
+ if (rseg
+ && rseg->kind == SkResvn
+ && rseg->smode == SmLower
+ && aseg->end+1 == rseg->start) {
ARG2 = aseg->end - ARG1 + 1;
ARG3 &= ~VKI_PROT_GROWSUP;
} else {
@@ -3993,10 +3987,8 @@
SysRes sres;
VG_(sprintf)(name, "/proc/%d/cmdline", VG_(getpid)());
- if (ML_(safe_to_deref)( arg1s, 1 ) &&
- (VG_STREQ(arg1s, name) || VG_STREQ(arg1s, "/proc/self/cmdline"))
- )
- {
+ if (ML_(safe_to_deref)( arg1s, 1 )
+ && (VG_STREQ(arg1s, name) || VG_STREQ(arg1s, "/proc/self/cmdline"))) {
sres = VG_(dup)( VG_(cl_cmdline_fd) );
SET_STATUS_from_SysRes( sres );
if (!sr_isError(sres)) {
@@ -4062,8 +4054,8 @@
&& SimHintiS(SimHint_enable_outer, VG_(clo_sim_hints)))
ok = True;
#if defined(VGO_solaris)
- if (!ok && VG_(vfork_fildes_addr) != NULL &&
- *VG_(vfork_fildes_addr) >= 0 && *VG_(vfork_fildes_addr) == ARG1)
+ if (!ok && VG_(vfork_fildes_addr) != NULL
+ && *VG_(vfork_fildes_addr) >= 0 && *VG_(vfork_fildes_addr) == ARG1)
ok = True;
#endif
if (!ok)
@@ -4139,37 +4131,31 @@
PRE_MEM_RASCIIZ( "readlink(path)", ARG1 );
PRE_MEM_WRITE( "readlink(buf)", ARG2,ARG3 );
+
{
+#if defined(VGO_linux) || defined(VGO_solaris)
#if defined(VGO_linux)
+#define PID_EXEPATH "/proc/%d/exe"
+#define SELF_EXEPATH "/proc/self/exe"
+#define SELF_EXEFD "/proc/self/fd/%d"
+#elif defined(VGO_solaris)
+#define PID_EXEPATH "/proc/%d/path/a.out"
+#define SELF_EXEPATH "/proc/self/path/a.out"
+#define SELF_EXEFD "/proc/self/path/%d"
+#endif
/*
* Handle the case where readlink is looking at /proc/self/exe or
- * /proc/<pid>/exe.
+ * /proc/<pid>/exe, or equivalent on Solaris.
*/
HChar name[30]; // large enough
HChar* arg1s = (HChar*) ARG1;
- VG_(sprintf)(name, "/proc/%d/exe", VG_(getpid)());
- if (ML_(safe_to_deref)(arg1s, 1) &&
- (VG_STREQ(arg1s, name) || VG_STREQ(arg1s, "/proc/self/exe"))
- )
- {
- VG_(sprintf)(name, "/proc/self/fd/%d", VG_(cl_exec_fd));
+ VG_(sprintf)(name, PID_EXEPATH, VG_(getpid)());
+ if (ML_(safe_to_deref)(arg1s, 1)
+ && (VG_STREQ(arg1s, name) || VG_STREQ(arg1s, SELF_EXEPATH))) {
+ VG_(sprintf)(name, SELF_EXEFD, VG_(cl_exec_fd));
SET_STATUS_from_SysRes( VG_(do_syscall3)(saved, (UWord)name,
ARG2, ARG3));
} else
-#elif defined(VGO_solaris)
- /* Same for Solaris, but /proc/self/path/a.out and
- /proc/<pid>/path/a.out. */
- HChar name[30]; // large enough
- HChar* arg1s = (HChar*) ARG1;
- VG_(sprintf)(name, "/proc/%d/path/a.out", VG_(getpid)());
- if (ML_(safe_to_deref)(arg1s, 1) &&
- (VG_STREQ(arg1s, name) || VG_STREQ(arg1s, "/proc/self/path/a.out"))
- )
- {
- VG_(sprintf)(name, "/proc/self/path/%d", VG_(cl_exec_fd));
- SET_STATUS_from_SysRes( VG_(do_syscall3)(saved, (UWord)name,
- ARG2, ARG3));
- } else
#endif
{
/* Normal case */
diff --git a/coregrind/m_syswrap/syswrap-linux-variants.c b/coregrind/m_syswrap/syswrap-linux-variants.c
index cd27091..d193520 100644
--- a/coregrind/m_syswrap/syswrap-linux-variants.c
+++ b/coregrind/m_syswrap/syswrap-linux-variants.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_syswrap/syswrap-linux.c b/coregrind/m_syswrap/syswrap-linux.c
index f2ebc16..26e02fd 100644
--- a/coregrind/m_syswrap/syswrap-linux.c
+++ b/coregrind/m_syswrap/syswrap-linux.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Nicholas Nethercote
+ Copyright (C) 2000-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -52,6 +52,7 @@
#include "pub_core_options.h"
#include "pub_core_scheduler.h"
#include "pub_core_signals.h"
+#include "pub_core_stacks.h"
#include "pub_core_syscall.h"
#include "pub_core_syswrap.h"
#include "pub_core_inner.h"
@@ -92,9 +93,8 @@
VG_TRACK(pre_thread_first_insn, tid);
tst->os_state.lwpid = VG_(gettid)();
- /* Set the threadgroup for real. This overwrites the provisional
- value set in do_clone() syswrap-*-linux.c. See comments in
- do_clone for background, also #226116. */
+ /* Set the threadgroup for real. This overwrites the provisional value set
+ in do_clone(). See comments in do_clone for background, also #226116. */
tst->os_state.threadgroup = VG_(getpid)();
/* Thread created with all signals blocked; scheduler will set the
@@ -162,6 +162,10 @@
c = VG_(count_living_threads)();
vg_assert(c >= 1); /* stay sane */
+ /* Deregister thread's stack. */
+ if (tst->os_state.stk_id != NULL_STK_ID)
+ VG_(deregister_stack)(tst->os_state.stk_id);
+
// Tell the tool this thread is exiting
VG_TRACK( pre_thread_ll_exit, tid );
@@ -297,15 +301,6 @@
: "r" (VgTs_Empty), "n" (__NR_exit), "m" (tst->os_state.exitcode)
: "cc", "memory" , "v0", "a0"
);
-#elif defined(VGP_tilegx_linux)
- asm volatile (
- "st4 %0, %1\n" /* set tst->status = VgTs_Empty */
- "moveli r10, %2\n" /* set r10 = __NR_exit */
- "move r0, %3\n" /* set r0 = tst->os_state.exitcode */
- "swint1\n" /* exit(tst->os_state.exitcode) */
- : "=m" (tst->status)
- : "r" (VgTs_Empty), "n" (__NR_exit), "r" (tst->os_state.exitcode)
- : "r0", "r1", "r2", "r3", "r4", "r5");
#else
# error Unknown platform
#endif
@@ -425,17 +420,308 @@
vg_assert(0);
}
+/* Clone a new thread. Note that in the clone syscalls, we hard-code
+ tlsaddr argument as NULL : the guest TLS is emulated via guest
+ registers, and Valgrind itself has no thread local storage. */
+static SysRes clone_new_thread ( Word (*fn)(void *),
+ void* stack,
+ Word flags,
+ ThreadState* ctst,
+ Int* child_tidptr,
+ Int* parent_tidptr)
+{
+ SysRes res;
+ /* Note that in all the below, we make sys_clone appear to have returned
+ Success(0) in the child, by assigning the relevant child guest
+ register(s) just before the clone syscall. */
+#if defined(VGP_x86_linux)
+ Int eax;
+ ctst->arch.vex.guest_EAX = 0;
+ eax = do_syscall_clone_x86_linux
+ (ML_(start_thread_NORETURN), stack, flags, ctst,
+ child_tidptr, parent_tidptr, NULL);
+ res = VG_(mk_SysRes_x86_linux)( eax );
+#elif defined(VGP_amd64_linux)
+ Long rax;
+ ctst->arch.vex.guest_RAX = 0;
+ rax = do_syscall_clone_amd64_linux
+ (ML_(start_thread_NORETURN), stack, flags, ctst,
+ child_tidptr, parent_tidptr, NULL);
+ res = VG_(mk_SysRes_amd64_linux)( rax );
+#elif defined(VGP_ppc32_linux)
+ ULong word64;
+ UInt old_cr = LibVEX_GuestPPC32_get_CR( &ctst->arch.vex );
+ /* %r3 = 0 */
+ ctst->arch.vex.guest_GPR3 = 0;
+ /* %cr0.so = 0 */
+ LibVEX_GuestPPC32_put_CR( old_cr & ~(1<<28), &ctst->arch.vex );
+ word64 = do_syscall_clone_ppc32_linux
+ (ML_(start_thread_NORETURN), stack, flags, ctst,
+ child_tidptr, parent_tidptr, NULL);
+ /* High half word64 is syscall return value. Low half is
+ the entire CR, from which we need to extract CR0.SO. */
+ /* VG_(printf)("word64 = 0x%llx\n", word64); */
+ res = VG_(mk_SysRes_ppc32_linux)(/*val*/(UInt)(word64 >> 32),
+ /*errflag*/ (((UInt)word64) >> 28) & 1);
+#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ ULong word64;
+ UInt old_cr = LibVEX_GuestPPC64_get_CR( &ctst->arch.vex );
+ /* %r3 = 0 */
+ ctst->arch.vex.guest_GPR3 = 0;
+ /* %cr0.so = 0 */
+ LibVEX_GuestPPC64_put_CR( old_cr & ~(1<<28), &ctst->arch.vex );
+ word64 = do_syscall_clone_ppc64_linux
+ (ML_(start_thread_NORETURN), stack, flags, ctst,
+ child_tidptr, parent_tidptr, NULL);
+ /* Low half word64 is syscall return value. Hi half is
+ the entire CR, from which we need to extract CR0.SO. */
+ /* VG_(printf)("word64 = 0x%llx\n", word64); */
+ res = VG_(mk_SysRes_ppc64_linux)
+ (/*val*/(UInt)(word64 & 0xFFFFFFFFULL),
+ /*errflag*/ (UInt)((word64 >> (32+28)) & 1));
+#elif defined(VGP_s390x_linux)
+ ULong r2;
+ ctst->arch.vex.guest_r2 = 0;
+ r2 = do_syscall_clone_s390x_linux
+ (stack, flags, parent_tidptr, child_tidptr, NULL,
+ ML_(start_thread_NORETURN), ctst);
+ res = VG_(mk_SysRes_s390x_linux)( r2 );
+#elif defined(VGP_arm64_linux)
+ ULong x0;
+ ctst->arch.vex.guest_X0 = 0;
+ x0 = do_syscall_clone_arm64_linux
+ (ML_(start_thread_NORETURN), stack, flags, ctst,
+ child_tidptr, parent_tidptr, NULL);
+ res = VG_(mk_SysRes_arm64_linux)( x0 );
+#elif defined(VGP_arm_linux)
+ UInt r0;
+ ctst->arch.vex.guest_R0 = 0;
+ r0 = do_syscall_clone_arm_linux
+ (ML_(start_thread_NORETURN), stack, flags, ctst,
+ child_tidptr, parent_tidptr, NULL);
+ res = VG_(mk_SysRes_arm_linux)( r0 );
+#elif defined(VGP_mips64_linux)
+ UInt ret = 0;
+ ctst->arch.vex.guest_r2 = 0;
+ ctst->arch.vex.guest_r7 = 0;
+ ret = do_syscall_clone_mips64_linux
+ (ML_(start_thread_NORETURN), stack, flags, ctst,
+ parent_tidptr, NULL, child_tidptr);
+ res = VG_(mk_SysRes_mips64_linux)( /* val */ ret, 0, /* errflag */ 0);
+#elif defined(VGP_mips32_linux)
+ UInt ret = 0;
+ ctst->arch.vex.guest_r2 = 0;
+ ctst->arch.vex.guest_r7 = 0;
+ ret = do_syscall_clone_mips_linux
+ (ML_(start_thread_NORETURN), stack, flags, ctst,
+ child_tidptr, parent_tidptr, NULL);
+ /* High half word64 is syscall return value. Low half is
+ the entire CR, from which we need to extract CR0.SO. */
+ res = VG_ (mk_SysRes_mips32_linux) (/*val */ ret, 0, /*errflag */ 0);
+#else
+# error Unknown platform
+#endif
+ return res;
+}
-/* Do a clone which is really a fork() */
-SysRes ML_(do_fork_clone) ( ThreadId tid, UInt flags,
- Int* parent_tidptr, Int* child_tidptr )
+static void setup_child ( /*OUT*/ ThreadArchState *child,
+ /*IN*/ ThreadArchState *parent )
+{
+ /* We inherit our parent's guest state. */
+ child->vex = parent->vex;
+ child->vex_shadow1 = parent->vex_shadow1;
+ child->vex_shadow2 = parent->vex_shadow2;
+
+#if defined(VGP_x86_linux)
+ extern void ML_(x86_setup_LDT_GDT) ( /*OUT*/ ThreadArchState *child,
+ /*IN*/ ThreadArchState *parent );
+ ML_(x86_setup_LDT_GDT)(child, parent);
+#endif
+}
+
+static SysRes setup_child_tls (ThreadId ctid, Addr tlsaddr)
+{
+ static const Bool debug = False;
+ ThreadState* ctst = VG_(get_ThreadState)(ctid);
+ // res is succesful by default, overriden if a real syscall is needed/done.
+ SysRes res = VG_(mk_SysRes_Success)(0);
+
+ if (debug)
+ VG_(printf)("clone child has SETTLS: tls at %#lx\n", tlsaddr);
+
+#if defined(VGP_x86_linux)
+ vki_modify_ldt_t* tlsinfo = (vki_modify_ldt_t*)tlsaddr;
+ if (debug)
+ VG_(printf)("clone child has SETTLS: tls info at %p: idx=%u "
+ "base=%#lx limit=%x; esp=%#x fs=%x gs=%x\n",
+ tlsinfo, tlsinfo->entry_number,
+ tlsinfo->base_addr, tlsinfo->limit,
+ ctst->arch.vex.guest_ESP,
+ ctst->arch.vex.guest_FS, ctst->arch.vex.guest_GS);
+ res = ML_(x86_sys_set_thread_area)(ctid, tlsinfo);
+#elif defined(VGP_amd64_linux)
+ ctst->arch.vex.guest_FS_CONST = tlsaddr;
+#elif defined(VGP_ppc32_linux)
+ ctst->arch.vex.guest_GPR2 = tlsaddr;
+#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ ctst->arch.vex.guest_GPR13 = tlsaddr;
+#elif defined(VGP_s390x_linux)
+ ctst->arch.vex.guest_a0 = (UInt) (tlsaddr >> 32);
+ ctst->arch.vex.guest_a1 = (UInt) tlsaddr;
+#elif defined(VGP_arm64_linux)
+ /* Just assign the tls pointer in the guest TPIDR_EL0. */
+ ctst->arch.vex.guest_TPIDR_EL0 = tlsaddr;
+#elif defined(VGP_arm_linux)
+ /* Just assign the tls pointer in the guest TPIDRURO. */
+ ctst->arch.vex.guest_TPIDRURO = tlsaddr;
+#elif defined(VGP_mips64_linux)
+ ctst->arch.vex.guest_ULR = tlsaddr;
+ ctst->arch.vex.guest_r27 = tlsaddr;
+#elif defined(VGP_mips32_linux)
+ ctst->arch.vex.guest_ULR = tlsaddr;
+ ctst->arch.vex.guest_r27 = tlsaddr;
+#else
+# error Unknown platform
+#endif
+ return res;
+}
+
+/*
+ When a client clones, we need to keep track of the new thread. This means:
+ 1. allocate a ThreadId+ThreadState+stack for the thread
+
+ 2. initialize the thread's new VCPU state
+
+ 3. create the thread using the same args as the client requested,
+ but using the scheduler entrypoint for EIP, and a separate stack
+ for ESP.
+ */
+static SysRes do_clone ( ThreadId ptid,
+ UWord flags, Addr sp,
+ Int* parent_tidptr,
+ Int* child_tidptr,
+ Addr tlsaddr)
+{
+ ThreadId ctid = VG_(alloc_ThreadState)();
+ ThreadState* ptst = VG_(get_ThreadState)(ptid);
+ ThreadState* ctst = VG_(get_ThreadState)(ctid);
+ UWord* stack;
+ SysRes res;
+ vki_sigset_t blockall, savedmask;
+
+ VG_(sigfillset)(&blockall);
+
+ vg_assert(VG_(is_running_thread)(ptid));
+ vg_assert(VG_(is_valid_tid)(ctid));
+
+ stack = (UWord*)ML_(allocstack)(ctid);
+ if (stack == NULL) {
+ res = VG_(mk_SysRes_Error)( VKI_ENOMEM );
+ goto out;
+ }
+
+ /* Copy register state
+
+ Both parent and child return to the same place, and the code
+ following the clone syscall works out which is which, so we
+ don't need to worry about it.
+
+ The parent gets the child's new tid returned from clone, but the
+ child gets 0.
+
+ If the clone call specifies a NULL sp for the new thread, then
+ it actually gets a copy of the parent's sp.
+ */
+ setup_child( &ctst->arch, &ptst->arch );
+
+ if (sp != 0)
+ VG_(set_SP)(ctid, sp);
+
+ ctst->os_state.parent = ptid;
+
+ /* inherit signal mask */
+ ctst->sig_mask = ptst->sig_mask;
+ ctst->tmp_sig_mask = ptst->sig_mask;
+
+ /* Start the child with its threadgroup being the same as the
+ parent's. This is so that any exit_group calls that happen
+ after the child is created but before it sets its
+ os_state.threadgroup field for real (in thread_wrapper in
+ syswrap-linux.c), really kill the new thread. a.k.a this avoids
+ a race condition in which the thread is unkillable (via
+ exit_group) because its threadgroup is not set. The race window
+ is probably only a few hundred or a few thousand cycles long.
+ See #226116. */
+ ctst->os_state.threadgroup = ptst->os_state.threadgroup;
+
+ ML_(guess_and_register_stack) (sp, ctst);
+
+ /* Assume the clone will succeed, and tell any tool that wants to
+ know that this thread has come into existence. We cannot defer
+ it beyond this point because setup_tls, just below,
+ causes checks to assert by making references to the new ThreadId
+ if we don't state the new thread exists prior to that point.
+ If the clone fails, we'll send out a ll_exit notification for it
+ at the out: label below, to clean up. */
+ vg_assert(VG_(owns_BigLock_LL)(ptid));
+ VG_TRACK ( pre_thread_ll_create, ptid, ctid );
+
+ if (flags & VKI_CLONE_SETTLS) {
+ res = setup_child_tls(ctid, tlsaddr);
+ if (sr_isError(res))
+ goto out;
+ }
+ flags &= ~VKI_CLONE_SETTLS;
+
+ /* start the thread with everything blocked */
+ VG_(sigprocmask)(VKI_SIG_SETMASK, &blockall, &savedmask);
+
+ /* Create the new thread */
+ res = clone_new_thread ( ML_(start_thread_NORETURN), stack, flags, ctst,
+ child_tidptr, parent_tidptr);
+
+ VG_(sigprocmask)(VKI_SIG_SETMASK, &savedmask, NULL);
+
+ out:
+ if (sr_isError(res)) {
+ /* clone failed */
+ VG_(cleanup_thread)(&ctst->arch);
+ ctst->status = VgTs_Empty;
+ /* oops. Better tell the tool the thread exited in a hurry :-) */
+ VG_TRACK( pre_thread_ll_exit, ctid );
+ }
+
+ return res;
+}
+
+/* Do a clone which is really a fork().
+ ML_(do_fork_clone) uses the clone syscall to fork a child process.
+ Note that this should not be called for a thread creation.
+ Also, some flags combinations are not supported, and such combinations
+ are handled either by masking the non supported flags or by asserting.
+
+ The CLONE_VFORK flag is accepted, as this just tells that the parent is
+ suspended till the child exits or calls execve. We better keep this flag,
+ just in case the guests parent/client code depends on this synchronisation.
+
+ We cannot keep the flag CLONE_VM, as Valgrind will do whatever host
+ instructions in the child process, that will mess up the parent host
+ memory. So, we hope for the best and assumes that the guest application does
+ not (really) depends on sharing the memory between parent and child in the
+ interval between clone and exits/execve.
+
+ If child_sp != 0, the child (guest) sp will be set to child_sp just after the
+ clone syscall, before child guest instructions are executed. */
+static SysRes ML_(do_fork_clone) ( ThreadId tid, UInt flags,
+ Int* parent_tidptr, Int* child_tidptr,
+ Addr child_sp)
{
vki_sigset_t fork_saved_mask;
vki_sigset_t mask;
SysRes res;
if (flags & (VKI_CLONE_SETTLS | VKI_CLONE_FS | VKI_CLONE_VM
- | VKI_CLONE_FILES | VKI_CLONE_VFORK))
+ | VKI_CLONE_FILES))
return VG_(mk_SysRes_Error)( VKI_EINVAL );
/* Block all signals during fork, so that we can fix things up in
@@ -455,7 +741,7 @@
res = VG_(do_syscall5)( __NR_clone, flags,
(UWord)NULL, (UWord)parent_tidptr,
(UWord)NULL, (UWord)child_tidptr );
-#elif defined(VGP_amd64_linux) || defined(VGP_tilegx_linux)
+#elif defined(VGP_amd64_linux)
/* note that the last two arguments are the opposite way round to x86 and
ppc32 as the amd64 kernel expects the arguments in a different order */
res = VG_(do_syscall5)( __NR_clone, flags,
@@ -471,21 +757,12 @@
if (!sr_isError(res) && sr_Res(res) == 0) {
/* child */
+ if (child_sp != 0)
+ VG_(set_SP)(tid, child_sp);
VG_(do_atfork_child)(tid);
/* restore signal mask */
VG_(sigprocmask)(VKI_SIG_SETMASK, &fork_saved_mask, NULL);
-
- /* If --child-silent-after-fork=yes was specified, set the
- output file descriptors to 'impossible' values. This is
- noticed by send_bytes_to_logging_sink in m_libcprint.c, which
- duly stops writing any further output. */
- if (VG_(clo_child_silent_after_fork)) {
- if (!VG_(log_output_sink).is_socket)
- VG_(log_output_sink).fd = -1;
- if (!VG_(xml_output_sink).is_socket)
- VG_(xml_output_sink).fd = -1;
- }
}
else
if (!sr_isError(res) && sr_Res(res) > 0) {
@@ -503,7 +780,6 @@
return res;
}
-
/* ---------------------------------------------------------------------
PRE/POST wrappers for arch-generic, Linux-specific syscalls
------------------------------------------------------------------ */
@@ -514,19 +790,155 @@
#define PRE(name) DEFN_PRE_TEMPLATE(linux, name)
#define POST(name) DEFN_POST_TEMPLATE(linux, name)
-// Macros to support 64-bit syscall args split into two 32 bit values
-#define LOHI64(lo,hi) ( ((ULong)(lo)) | (((ULong)(hi)) << 32) )
-#if defined(VG_LITTLEENDIAN)
-#define MERGE64(lo,hi) ( ((ULong)(lo)) | (((ULong)(hi)) << 32) )
-#define MERGE64_FIRST(name) name##_low
-#define MERGE64_SECOND(name) name##_high
-#elif defined(VG_BIGENDIAN)
-#define MERGE64(hi,lo) ( ((ULong)(lo)) | (((ULong)(hi)) << 32) )
-#define MERGE64_FIRST(name) name##_high
-#define MERGE64_SECOND(name) name##_low
+PRE(sys_clone)
+{
+ UInt cloneflags;
+ Bool badarg = False;
+
+ PRINT("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )",ARG1,ARG2,ARG3,ARG4,ARG5);
+
+// Order of arguments differs between platforms.
+#if defined(VGP_x86_linux) \
+ || defined(VGP_ppc32_linux) \
+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
+ || defined(VGP_arm_linux) || defined(VGP_mips32_linux) \
+ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux)
+#define ARG_CHILD_TIDPTR ARG5
+#define PRA_CHILD_TIDPTR PRA5
+#define ARG_TLS ARG4
+#define PRA_TLS PRA4
+#elif defined(VGP_amd64_linux) || defined(VGP_s390x_linux)
+#define ARG_CHILD_TIDPTR ARG4
+#define PRA_CHILD_TIDPTR PRA4
+#define ARG_TLS ARG5
+#define PRA_TLS PRA5
#else
-#error Unknown endianness
+# error Unknown platform
#endif
+// And s390x is even more special, and inverts flags and child stack args
+#if defined(VGP_s390x_linux)
+#define ARG_FLAGS ARG2
+#define PRA_FLAGS PRA2
+#define ARG_CHILD_STACK ARG1
+#define PRA_CHILD_STACK PRA1
+#else
+#define ARG_FLAGS ARG1
+#define PRA_FLAGS PRA1
+#define ARG_CHILD_STACK ARG2
+#define PRA_CHILD_STACK PRA2
+#endif
+
+ if (VG_(tdict).track_pre_reg_read) {
+ PRA_FLAGS("clone", unsigned long, flags);
+ PRA_CHILD_STACK("clone", void *, child_stack);
+ }
+
+ if (ARG_FLAGS & VKI_CLONE_PARENT_SETTID) {
+ if (VG_(tdict).track_pre_reg_read) {
+ PRA3("clone", int *, parent_tidptr);
+ }
+ PRE_MEM_WRITE("clone(parent_tidptr)", ARG3, sizeof(Int));
+ if (!VG_(am_is_valid_for_client)(ARG3, sizeof(Int),
+ VKI_PROT_WRITE)) {
+ badarg = True;
+ }
+ }
+ if (ARG_FLAGS & VKI_CLONE_SETTLS) {
+ if (VG_(tdict).track_pre_reg_read) {
+ PRA_TLS("clone", vki_modify_ldt_t *, tlsinfo);
+ }
+ /* Not very clear what is vki_modify_ldt_t: for many platforms, it is a
+ dummy type (that we define as a char). We only dereference/check the
+ ARG_TLS pointer if the type looks like a real type, i.e. sizeof > 1. */
+ if (sizeof(vki_modify_ldt_t) > 1) {
+ PRE_MEM_READ("clone(tlsinfo)", ARG_TLS, sizeof(vki_modify_ldt_t));
+ if (!VG_(am_is_valid_for_client)(ARG_TLS, sizeof(vki_modify_ldt_t),
+ VKI_PROT_READ)) {
+ badarg = True;
+ }
+ }
+ }
+ if (ARG_FLAGS & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) {
+ if (VG_(tdict).track_pre_reg_read) {
+ PRA_CHILD_TIDPTR("clone", int *, child_tidptr);
+ }
+ PRE_MEM_WRITE("clone(child_tidptr)", ARG_CHILD_TIDPTR, sizeof(Int));
+ if (!VG_(am_is_valid_for_client)(ARG_CHILD_TIDPTR, sizeof(Int),
+ VKI_PROT_WRITE)) {
+ badarg = True;
+ }
+ }
+
+ if (badarg) {
+ SET_STATUS_Failure( VKI_EFAULT );
+ return;
+ }
+
+ cloneflags = ARG_FLAGS;
+
+ if (!ML_(client_signal_OK)(ARG_FLAGS & VKI_CSIGNAL)) {
+ SET_STATUS_Failure( VKI_EINVAL );
+ return;
+ }
+
+ /* Only look at the flags we really care about */
+ switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS
+ | VKI_CLONE_FILES | VKI_CLONE_VFORK)) {
+ case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES:
+ /* thread creation */
+ SET_STATUS_from_SysRes(
+ do_clone(tid,
+ ARG_FLAGS, /* flags */
+ (Addr)ARG_CHILD_STACK, /* child ESP */
+ (Int*)ARG3, /* parent_tidptr */
+ (Int*)ARG_CHILD_TIDPTR, /* child_tidptr */
+ (Addr)ARG_TLS)); /* set_tls */
+ break;
+
+ case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */
+ // FALLTHROUGH - assume vfork (somewhat) == fork, see ML_(do_fork_clone).
+ cloneflags &= ~VKI_CLONE_VM;
+
+ case 0: /* plain fork */
+ SET_STATUS_from_SysRes(
+ ML_(do_fork_clone)(tid,
+ cloneflags, /* flags */
+ (Int*)ARG3, /* parent_tidptr */
+ (Int*)ARG_CHILD_TIDPTR, /* child_tidptr */
+ (Addr)ARG_CHILD_STACK));
+ break;
+
+ default:
+ /* should we just ENOSYS? */
+ VG_(message)(Vg_UserMsg, "Unsupported clone() flags: 0x%lx\n", ARG_FLAGS);
+ VG_(message)(Vg_UserMsg, "\n");
+ VG_(message)(Vg_UserMsg, "The only supported clone() uses are:\n");
+ VG_(message)(Vg_UserMsg, " - via a threads library (LinuxThreads or NPTL)\n");
+ VG_(message)(Vg_UserMsg, " - via the implementation of fork or vfork\n");
+ VG_(unimplemented)
+ ("Valgrind does not support general clone().");
+ }
+
+ if (SUCCESS) {
+ if (ARG_FLAGS & VKI_CLONE_PARENT_SETTID)
+ POST_MEM_WRITE(ARG3, sizeof(Int));
+ if (ARG_FLAGS & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID))
+ POST_MEM_WRITE(ARG_CHILD_TIDPTR, sizeof(Int));
+
+ /* Thread creation was successful; let the child have the chance
+ to run */
+ *flags |= SfYieldAfter;
+ }
+
+#undef ARG_CHILD_TIDPTR
+#undef PRA_CHILD_TIDPTR
+#undef ARG_TLS
+#undef PRA_TLS
+#undef ARG_FLAGS
+#undef PRA_FLAGS
+#undef ARG_CHILD_STACK
+#undef PRA_CHILD_STACK
+}
/* ---------------------------------------------------------------------
*mount wrappers
@@ -1014,7 +1426,26 @@
break;
case VKI_PR_SET_NAME:
PRE_REG_READ2(int, "prctl", int, option, char *, name);
- PRE_MEM_RASCIIZ("prctl(set-name)", ARG2);
+ /* The name can be up to TASK_COMM_LEN(16) bytes long, including
+ the terminating null byte. So do not check more than 16 bytes. */
+ if (ML_(safe_to_deref)((const HChar *) ARG2, VKI_TASK_COMM_LEN)) {
+ SizeT len = VG_(strnlen)((const HChar *) ARG2, VKI_TASK_COMM_LEN);
+ if (len < VKI_TASK_COMM_LEN) {
+ PRE_MEM_RASCIIZ("prctl(set-name)", ARG2);
+ } else {
+ PRE_MEM_READ("prctl(set-name)", ARG2, VKI_TASK_COMM_LEN);
+ }
+ } else {
+ /* Do it the slow way, one byte at a time, while checking for
+ terminating '\0'. */
+ const HChar *name = (const HChar *) ARG2;
+ for (UInt i = 0; i < VKI_TASK_COMM_LEN; i++) {
+ PRE_MEM_READ("prctl(set-name)", (Addr) &name[i], 1);
+ if (!ML_(safe_to_deref)(&name[i], 1) || name[i] == '\0') {
+ break;
+ }
+ }
+ }
break;
case VKI_PR_GET_NAME:
PRE_REG_READ2(int, "prctl", int, option, char *, name);
@@ -1078,12 +1509,12 @@
const HChar* new_name = (const HChar*) ARG2;
if (new_name) { // Paranoia
ThreadState* tst = VG_(get_ThreadState)(tid);
- SizeT new_len = VG_(strlen)(new_name);
+ SizeT new_len = VG_(strnlen)(new_name, VKI_TASK_COMM_LEN);
/* Don't bother reusing the memory. This is a rare event. */
tst->thread_name =
VG_(realloc)("syswrap.prctl", tst->thread_name, new_len + 1);
- VG_(strcpy)(tst->thread_name, new_name);
+ VG_(strlcpy)(tst->thread_name, new_name, new_len + 1);
}
}
break;
@@ -1172,9 +1603,11 @@
}
break;
case VKI_FUTEX_WAKE_BITSET:
- PRE_REG_READ6(long, "futex",
- vki_u32 *, futex, int, op, int, val,
- int, dummy, int, dummy2, int, val3);
+ PRE_REG_READ3(long, "futex",
+ vki_u32 *, futex, int, op, int, val);
+ if (VG_(tdict).track_pre_reg_read) {
+ PRA6("futex", int, val3);
+ }
break;
case VKI_FUTEX_WAIT:
case VKI_FUTEX_LOCK_PI:
@@ -1184,10 +1617,10 @@
break;
case VKI_FUTEX_WAKE:
case VKI_FUTEX_FD:
- case VKI_FUTEX_TRYLOCK_PI:
PRE_REG_READ3(long, "futex",
vki_u32 *, futex, int, op, int, val);
break;
+ case VKI_FUTEX_TRYLOCK_PI:
case VKI_FUTEX_UNLOCK_PI:
default:
PRE_REG_READ2(long, "futex", vki_u32 *, futex, int, op);
@@ -1217,13 +1650,10 @@
case VKI_FUTEX_FD:
case VKI_FUTEX_TRYLOCK_PI:
case VKI_FUTEX_UNLOCK_PI:
- PRE_MEM_READ( "futex(futex)", ARG1, sizeof(Int) );
- break;
-
case VKI_FUTEX_WAKE:
case VKI_FUTEX_WAKE_BITSET:
- /* no additional pointers */
- break;
+ PRE_MEM_READ( "futex(futex)", ARG1, sizeof(Int) );
+ break;
default:
SET_STATUS_Failure( VKI_ENOSYS ); // some futex function we don't understand
@@ -1634,7 +2064,7 @@
PRE(sys_tkill)
{
- PRINT("sys_tgkill ( %ld, %ld )", SARG1, SARG2);
+ PRINT("sys_tkill ( %ld, %ld )", SARG1, SARG2);
PRE_REG_READ2(long, "tkill", int, tid, int, sig);
if (!ML_(client_signal_OK)(ARG2)) {
SET_STATUS_Failure( VKI_EINVAL );
@@ -3277,7 +3707,7 @@
PRE_MEM_READ( "sigaction(act->sa_handler)", (Addr)&sa->ksa_handler, sizeof(sa->ksa_handler));
PRE_MEM_READ( "sigaction(act->sa_mask)", (Addr)&sa->sa_mask, sizeof(sa->sa_mask));
PRE_MEM_READ( "sigaction(act->sa_flags)", (Addr)&sa->sa_flags, sizeof(sa->sa_flags));
- if (ML_(safe_to_deref)(sa,sizeof(sa))
+ if (ML_(safe_to_deref)(sa,sizeof(struct vki_old_sigaction))
&& (sa->sa_flags & VKI_SA_RESTORER))
PRE_MEM_READ( "sigaction(act->sa_restorer)", (Addr)&sa->sa_restorer, sizeof(sa->sa_restorer));
}
@@ -3390,7 +3820,7 @@
PRE_MEM_READ( "rt_sigaction(act->sa_handler)", (Addr)&sa->ksa_handler, sizeof(sa->ksa_handler));
PRE_MEM_READ( "rt_sigaction(act->sa_mask)", (Addr)&sa->sa_mask, sizeof(sa->sa_mask));
PRE_MEM_READ( "rt_sigaction(act->sa_flags)", (Addr)&sa->sa_flags, sizeof(sa->sa_flags));
- if (ML_(safe_to_deref)(sa,sizeof(sa))
+ if (ML_(safe_to_deref)(sa,sizeof(vki_sigaction_toK_t))
&& (sa->sa_flags & VKI_SA_RESTORER))
PRE_MEM_READ( "rt_sigaction(act->sa_restorer)", (Addr)&sa->sa_restorer, sizeof(sa->sa_restorer));
}
@@ -3558,6 +3988,16 @@
PRE_REG_READ2(int, "rt_sigsuspend", vki_sigset_t *, mask, vki_size_t, size)
if (ARG1 != (Addr)NULL) {
PRE_MEM_READ( "rt_sigsuspend(mask)", ARG1, sizeof(vki_sigset_t) );
+ if (ML_(safe_to_deref)((vki_sigset_t *) ARG1, sizeof(vki_sigset_t))) {
+ VG_(sigdelset)((vki_sigset_t *) ARG1, VG_SIGVGKILL);
+ /* We cannot mask VG_SIGVGKILL, as otherwise this thread would not
+ be killable by VG_(nuke_all_threads_except).
+ We thus silently ignore the user request to mask this signal.
+ Note that this is similar to what is done for e.g.
+ sigprocmask (see m_signals.c calculate_SKSS_from_SCSS). */
+ } else {
+ SET_STATUS_Failure(VKI_EFAULT);
+ }
}
}
@@ -4004,10 +4444,10 @@
}
}
-PRE(wrap_sys_shmat)
+PRE(sys_shmat)
{
UWord arg2tmp;
- PRINT("wrap_sys_shmat ( %ld, %#lx, %ld )", SARG1, ARG2, SARG3);
+ PRINT("sys_shmat ( %ld, %#lx, %ld )", SARG1, ARG2, SARG3);
PRE_REG_READ3(long, "shmat",
int, shmid, const void *, shmaddr, int, shmflg);
#if defined(VGP_arm_linux)
@@ -4025,7 +4465,7 @@
ARG2 = arg2tmp; // used in POST
}
-POST(wrap_sys_shmat)
+POST(sys_shmat)
{
ML_(generic_POST_sys_shmat)(tid, RES,ARG1,ARG2,ARG3);
}
@@ -5282,6 +5722,17 @@
PRE_MEM_RASCIIZ( "init_module(uargs)", ARG3 );
}
+PRE(sys_finit_module)
+{
+ *flags |= SfMayBlock;
+
+ PRINT("sys_finit_module ( %lx, %#lx(\"%s\"), %lx )",
+ ARG1, ARG2, (HChar*)ARG2, ARG3);
+ PRE_REG_READ3(long, "finit_module",
+ int, fd, const char *, params, int, flags);
+ PRE_MEM_RASCIIZ("finit_module(params)", ARG2);
+}
+
PRE(sys_delete_module)
{
*flags |= SfMayBlock;
@@ -5399,7 +5850,7 @@
#endif
#if defined(VGP_amd64_linux) || defined(VGP_s390x_linux) \
- || defined(VGP_tilegx_linux) || defined(VGP_arm64_linux)
+ || defined(VGP_arm64_linux)
PRE(sys_lookup_dcookie)
{
*flags |= SfMayBlock;
@@ -5455,20 +5906,46 @@
case VKI_F_GETLK:
case VKI_F_SETLK:
case VKI_F_SETLKW:
-# if defined(VGP_x86_linux) || defined(VGP_mips64_linux)
- case VKI_F_GETLK64:
- case VKI_F_SETLK64:
- case VKI_F_SETLKW64:
-# endif
case VKI_F_OFD_GETLK:
case VKI_F_OFD_SETLK:
case VKI_F_OFD_SETLKW:
PRINT("sys_fcntl[ARG3=='lock'] ( %lu, %lu, %#lx )", ARG1, ARG2, ARG3);
PRE_REG_READ3(long, "fcntl",
unsigned int, fd, unsigned int, cmd,
- struct flock64 *, lock);
+ struct vki_flock *, lock);
+ {
+ struct vki_flock *lock = (struct vki_flock *) ARG3;
+ PRE_FIELD_READ("fcntl(lock->l_type)", lock->l_type);
+ PRE_FIELD_READ("fcntl(lock->l_whence)", lock->l_whence);
+ PRE_FIELD_READ("fcntl(lock->l_start)", lock->l_start);
+ PRE_FIELD_READ("fcntl(lock->l_len)", lock->l_len);
+ if (ARG2 == VKI_F_GETLK || ARG2 == VKI_F_OFD_GETLK) {
+ PRE_FIELD_WRITE("fcntl(lock->l_pid)", lock->l_pid);
+ }
+ }
break;
+# if defined(VGP_x86_linux) || defined(VGP_mips64_linux)
+ case VKI_F_GETLK64:
+ case VKI_F_SETLK64:
+ case VKI_F_SETLKW64:
+ PRINT("sys_fcntl[ARG3=='lock'] ( %lu, %lu, %#lx )", ARG1, ARG2, ARG3);
+ PRE_REG_READ3(long, "fcntl",
+ unsigned int, fd, unsigned int, cmd,
+ struct flock64 *, lock);
+ {
+ struct vki_flock64 *lock = (struct vki_flock64 *) ARG3;
+ PRE_FIELD_READ("fcntl(lock->l_type)", lock->l_type);
+ PRE_FIELD_READ("fcntl(lock->l_whence)", lock->l_whence);
+ PRE_FIELD_READ("fcntl(lock->l_start)", lock->l_start);
+ PRE_FIELD_READ("fcntl(lock->l_len)", lock->l_len);
+ if (ARG2 == VKI_F_GETLK64) {
+ PRE_FIELD_WRITE("fcntl(lock->l_pid)", lock->l_pid);
+ }
+ }
+ break;
+# endif
+
case VKI_F_SETOWN_EX:
PRINT("sys_fcntl[F_SETOWN_EX] ( %lu, %lu, %lu )", ARG1, ARG2, ARG3);
PRE_REG_READ3(long, "fcntl",
@@ -5522,6 +5999,14 @@
}
} else if (ARG2 == VKI_F_GETOWN_EX) {
POST_MEM_WRITE(ARG3, sizeof(struct vki_f_owner_ex));
+ } else if (ARG2 == VKI_F_GETLK || ARG2 == VKI_F_OFD_GETLK) {
+ struct vki_flock *lock = (struct vki_flock *) ARG3;
+ POST_FIELD_WRITE(lock->l_pid);
+# if defined(VGP_x86_linux) || defined(VGP_mips64_linux)
+ } else if (ARG2 == VKI_F_GETLK64) {
+ struct vki_flock64 *lock = (struct vki_flock64 *) ARG3;
+ PRE_FIELD_WRITE("fcntl(lock->l_pid)", lock->l_pid);
+# endif
}
}
@@ -5625,6 +6110,11 @@
ioctl wrappers
------------------------------------------------------------------ */
+struct vg_drm_version_info {
+ struct vki_drm_version data;
+ struct vki_drm_version *orig; // Original ARG3 pointer value at syscall entry.
+};
+
PRE(sys_ioctl)
{
*flags |= SfMayBlock;
@@ -5666,8 +6156,12 @@
/* CDROM stuff. */
case VKI_CDROM_DISC_STATUS:
+ case VKI_CDROMSTOP:
- /* KVM ioctls that dont check for a numeric value as parameter */
+ /* DVD stuff */
+ case VKI_DVD_READ_STRUCT:
+
+ /* KVM ioctls that don't check for a numeric value as parameter */
case VKI_KVM_S390_ENABLE_SIE:
case VKI_KVM_CREATE_IRQCHIP:
case VKI_KVM_S390_INITIAL_RESET:
@@ -6460,8 +6954,13 @@
PRE_MEM_WRITE( "ioctl(CDROMSUBCHNL)", ARG3,
sizeof(struct vki_cdrom_subchnl));
break;
- case VKI_CDROMREADMODE2:
- PRE_MEM_READ( "ioctl(CDROMREADMODE2)", ARG3, VKI_CD_FRAMESIZE_RAW0 );
+ case VKI_CDROMREADMODE1: /*0x530d*/
+ PRE_MEM_READ("ioctl(CDROMREADMODE1)", ARG3, VKI_CD_FRAMESIZE_RAW1);
+ PRE_MEM_WRITE("ioctl(CDROMREADMODE1)", ARG3, VKI_CD_FRAMESIZE_RAW1);
+ break;
+ case VKI_CDROMREADMODE2: /*0x530c*/
+ PRE_MEM_READ("ioctl(CDROMREADMODE2)", ARG3, VKI_CD_FRAMESIZE_RAW0);
+ PRE_MEM_WRITE("ioctl(CDROMREADMODE2)", ARG3, VKI_CD_FRAMESIZE_RAW0);
break;
case VKI_CDROMREADTOCHDR:
PRE_MEM_WRITE( "ioctl(CDROMREADTOCHDR)", ARG3,
@@ -7238,7 +7737,8 @@
case VKI_DRM_IOCTL_VERSION:
if (ARG3) {
- struct vki_drm_version *data = (struct vki_drm_version *)ARG3;
+ struct vki_drm_version* data = (struct vki_drm_version *)ARG3;
+ struct vg_drm_version_info* info;
PRE_MEM_WRITE("ioctl(DRM_VERSION).version_major", (Addr)&data->version_major, sizeof(data->version_major));
PRE_MEM_WRITE("ioctl(DRM_VERSION).version_minor", (Addr)&data->version_minor, sizeof(data->version_minor));
PRE_MEM_WRITE("ioctl(DRM_VERSION).version_patchlevel", (Addr)&data->version_patchlevel, sizeof(data->version_patchlevel));
@@ -7251,6 +7751,12 @@
PRE_MEM_READ("ioctl(DRM_VERSION).desc_len", (Addr)&data->desc_len, sizeof(data->desc_len));
PRE_MEM_READ("ioctl(DRM_VERSION).desc", (Addr)&data->desc, sizeof(data->desc));
PRE_MEM_WRITE("ioctl(DRM_VERSION).desc", (Addr)data->desc, data->desc_len);
+ info = VG_(malloc)("syswrap.ioctl.1", sizeof(*info));
+ // To ensure we VG_(free) info even when syscall fails:
+ *flags |= SfPostOnFail;
+ info->data = *data;
+ info->orig = data;
+ ARG3 = (Addr)&info->data;
}
break;
case VKI_DRM_IOCTL_GET_UNIQUE:
@@ -8553,10 +9059,10 @@
POST(sys_ioctl)
{
- vg_assert(SUCCESS);
-
ARG2 = (UInt)ARG2;
+ vg_assert(SUCCESS || (FAILURE && VKI_DRM_IOCTL_VERSION == ARG2));
+
/* --- BEGIN special IOCTL handlers for specific Android hardware --- */
/* BEGIN undocumented ioctls for PowerVR SGX 540 (the GPU on Nexus S) */
@@ -9072,6 +9578,8 @@
case VKI_SNDRV_TIMER_IOCTL_STOP:
case VKI_SNDRV_TIMER_IOCTL_CONTINUE:
case VKI_SNDRV_TIMER_IOCTL_PAUSE:
+ break;
+
case VKI_SNDRV_CTL_IOCTL_PVERSION: {
POST_MEM_WRITE( (Addr)ARG3, sizeof(int) );
break;
@@ -9182,6 +9690,7 @@
/* CD ROM stuff (??) */
case VKI_CDROM_DISC_STATUS:
+ case VKI_CDROMSTOP:
break;
case VKI_CDROMSUBCHNL:
POST_MEM_WRITE(ARG3, sizeof(struct vki_cdrom_subchnl));
@@ -9198,6 +9707,12 @@
case VKI_CDROMVOLREAD:
POST_MEM_WRITE(ARG3, sizeof(struct vki_cdrom_volctrl));
break;
+ case VKI_CDROMREADMODE1:
+ POST_MEM_WRITE(ARG3, VKI_CD_FRAMESIZE_RAW1);
+ break;
+ case VKI_CDROMREADMODE2:
+ POST_MEM_WRITE(ARG3, VKI_CD_FRAMESIZE_RAW0);
+ break;
case VKI_CDROMREADRAW:
POST_MEM_WRITE(ARG3, VKI_CD_FRAMESIZE_RAW);
break;
@@ -9218,6 +9733,10 @@
case VKI_CDROM_GET_CAPABILITY: /* 0x5331 */
break;
+ /* DVD stuff */
+ case VKI_DVD_READ_STRUCT:
+ break;
+
case VKI_FIGETBSZ:
POST_MEM_WRITE(ARG3, sizeof(unsigned long));
break;
@@ -9719,16 +10238,26 @@
case VKI_DRM_IOCTL_VERSION:
if (ARG3) {
- struct vki_drm_version *data = (struct vki_drm_version *)ARG3;
- POST_MEM_WRITE((Addr)&data->version_major, sizeof(data->version_major));
- POST_MEM_WRITE((Addr)&data->version_minor, sizeof(data->version_minor));
- POST_MEM_WRITE((Addr)&data->version_patchlevel, sizeof(data->version_patchlevel));
- POST_MEM_WRITE((Addr)&data->name_len, sizeof(data->name_len));
- POST_MEM_WRITE((Addr)data->name, data->name_len);
- POST_MEM_WRITE((Addr)&data->date_len, sizeof(data->date_len));
- POST_MEM_WRITE((Addr)data->date, data->date_len);
- POST_MEM_WRITE((Addr)&data->desc_len, sizeof(data->desc_len));
- POST_MEM_WRITE((Addr)data->desc, data->desc_len);
+ struct vki_drm_version* data = (struct vki_drm_version *)ARG3;
+ struct vg_drm_version_info* info = container_of(data, struct vg_drm_version_info, data);
+ const vki_size_t orig_name_len = info->orig->name_len;
+ const vki_size_t orig_date_len = info->orig->date_len;
+ const vki_size_t orig_desc_len = info->orig->desc_len;
+ *info->orig = info->data;
+ ARG3 = (Addr)info->orig;
+ data = info->orig;
+ VG_(free)(info);
+ if (SUCCESS) {
+ POST_MEM_WRITE((Addr)&data->version_major, sizeof(data->version_major));
+ POST_MEM_WRITE((Addr)&data->version_minor, sizeof(data->version_minor));
+ POST_MEM_WRITE((Addr)&data->version_patchlevel, sizeof(data->version_patchlevel));
+ POST_MEM_WRITE((Addr)&data->name_len, sizeof(data->name_len));
+ POST_MEM_WRITE((Addr)data->name, VG_MIN(data->name_len, orig_name_len));
+ POST_MEM_WRITE((Addr)&data->date_len, sizeof(data->date_len));
+ POST_MEM_WRITE((Addr)data->date, VG_MIN(data->date_len, orig_date_len));
+ POST_MEM_WRITE((Addr)&data->desc_len, sizeof(data->desc_len));
+ POST_MEM_WRITE((Addr)data->desc, VG_MIN(data->desc_len, orig_desc_len));
+ }
}
break;
case VKI_DRM_IOCTL_GET_UNIQUE:
@@ -10646,16 +11175,23 @@
------------------------------------------------------------------ */
void
+ML_(linux_POST_traceme) ( ThreadId tid )
+{
+ ThreadState *tst = VG_(get_ThreadState)(tid);
+ tst->ptrace = VKI_PT_PTRACED;
+}
+
+void
ML_(linux_PRE_getregset) ( ThreadId tid, long arg3, long arg4 )
{
struct vki_iovec *iov = (struct vki_iovec *) arg4;
- PRE_MEM_READ("ptrace(getregset iovec->iov_base)",
- (unsigned long) &iov->iov_base, sizeof(iov->iov_base));
- PRE_MEM_READ("ptrace(getregset iovec->iov_len)",
- (unsigned long) &iov->iov_len, sizeof(iov->iov_len));
- PRE_MEM_WRITE("ptrace(getregset *(iovec->iov_base))",
- (unsigned long) iov->iov_base, iov->iov_len);
+ PRE_FIELD_READ("ptrace(getregset iovec->iov_base)", iov->iov_base);
+ PRE_FIELD_READ("ptrace(getregset iovec->iov_len)", iov->iov_len);
+ if (ML_(safe_to_deref)(iov, sizeof(struct vki_iovec))) {
+ PRE_MEM_WRITE("ptrace(getregset *(iovec->iov_base))",
+ (Addr) iov->iov_base, iov->iov_len);
+ }
}
void
@@ -10663,12 +11199,12 @@
{
struct vki_iovec *iov = (struct vki_iovec *) arg4;
- PRE_MEM_READ("ptrace(setregset iovec->iov_base)",
- (unsigned long) &iov->iov_base, sizeof(iov->iov_base));
- PRE_MEM_READ("ptrace(setregset iovec->iov_len)",
- (unsigned long) &iov->iov_len, sizeof(iov->iov_len));
- PRE_MEM_READ("ptrace(setregset *(iovec->iov_base))",
- (unsigned long) iov->iov_base, iov->iov_len);
+ PRE_FIELD_READ("ptrace(setregset iovec->iov_base)", iov->iov_base);
+ PRE_FIELD_READ("ptrace(setregset iovec->iov_len)", iov->iov_len);
+ if (ML_(safe_to_deref)(iov, sizeof(struct vki_iovec))) {
+ PRE_MEM_READ("ptrace(setregset *(iovec->iov_base))",
+ (Addr) iov->iov_base, iov->iov_len);
+ }
}
void
diff --git a/coregrind/m_syswrap/syswrap-main.c b/coregrind/m_syswrap/syswrap-main.c
index d854194..ad560df 100644
--- a/coregrind/m_syswrap/syswrap-main.c
+++ b/coregrind/m_syswrap/syswrap-main.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -549,8 +549,9 @@
canonical->arg2 = gst->guest_r5; // a1
canonical->arg3 = gst->guest_r6; // a2
canonical->arg4 = gst->guest_r7; // a3
- canonical->arg5 = *((UInt*) (gst->guest_r29 + 16)); // 16(guest_SP/sp)
- canonical->arg6 = *((UInt*) (gst->guest_r29 + 20)); // 20(sp)
+ canonical->arg5 = *((UInt*) (gst->guest_r29 + 16)); // 16(guest_SP)
+ canonical->arg6 = *((UInt*) (gst->guest_r29 + 20)); // 20(guest_SP)
+ canonical->arg7 = *((UInt*) (gst->guest_r29 + 24)); // 24(guest_SP)
canonical->arg8 = 0;
} else {
// Fixme hack handle syscall()
@@ -705,18 +706,6 @@
canonical->arg7 = 0;
canonical->arg8 = 0;
-#elif defined(VGP_tilegx_linux)
- VexGuestTILEGXState* gst = (VexGuestTILEGXState*)gst_vanilla;
- canonical->sysno = gst->guest_r10;
- canonical->arg1 = gst->guest_r0;
- canonical->arg2 = gst->guest_r1;
- canonical->arg3 = gst->guest_r2;
- canonical->arg4 = gst->guest_r3;
- canonical->arg5 = gst->guest_r4;
- canonical->arg6 = gst->guest_r5;
- canonical->arg7 = 0;
- canonical->arg8 = 0;
-
#elif defined(VGP_x86_solaris)
VexGuestX86State* gst = (VexGuestX86State*)gst_vanilla;
UWord *stack = (UWord *)gst->guest_ESP;
@@ -925,16 +914,6 @@
gst->guest_r8 = canonical->arg5;
gst->guest_r9 = canonical->arg6;
-#elif defined(VGP_tilegx_linux)
- VexGuestTILEGXState* gst = (VexGuestTILEGXState*)gst_vanilla;
- gst->guest_r10 = canonical->sysno;
- gst->guest_r0 = canonical->arg1;
- gst->guest_r1 = canonical->arg2;
- gst->guest_r2 = canonical->arg3;
- gst->guest_r3 = canonical->arg4;
- gst->guest_r4 = canonical->arg5;
- gst->guest_r5 = canonical->arg6;
-
#elif defined(VGP_x86_solaris)
VexGuestX86State* gst = (VexGuestX86State*)gst_vanilla;
UWord *stack = (UWord *)gst->guest_ESP;
@@ -1099,11 +1078,6 @@
canonical->sres = VG_(mk_SysRes_s390x_linux)( gst->guest_r2 );
canonical->what = SsComplete;
-# elif defined(VGP_tilegx_linux)
- VexGuestTILEGXState* gst = (VexGuestTILEGXState*)gst_vanilla;
- canonical->sres = VG_(mk_SysRes_tilegx_linux)( gst->guest_r0 );
- canonical->what = SsComplete;
-
# elif defined(VGP_x86_solaris)
VexGuestX86State* gst = (VexGuestX86State*)gst_vanilla;
UInt carry = 1 & LibVEX_GuestX86_get_eflags(gst);
@@ -1335,18 +1309,6 @@
VG_TRACK( post_reg_write, Vg_CoreSysCall, tid,
OFFSET_mips64_r7, sizeof(UWord) );
-# elif defined(VGP_tilegx_linux)
- VexGuestTILEGXState* gst = (VexGuestTILEGXState*)gst_vanilla;
- vg_assert(canonical->what == SsComplete);
- if (sr_isError(canonical->sres)) {
- gst->guest_r0 = - (Long)sr_Err(canonical->sres);
- // r1 hold errno
- gst->guest_r1 = (Long)sr_Err(canonical->sres);
- } else {
- gst->guest_r0 = sr_Res(canonical->sres);
- gst->guest_r1 = 0;
- }
-
# elif defined(VGP_x86_solaris)
VexGuestX86State* gst = (VexGuestX86State*)gst_vanilla;
SysRes sres = canonical->sres;
@@ -1490,7 +1452,7 @@
layout->o_arg4 = OFFSET_mips32_r7;
layout->s_arg5 = sizeof(UWord) * 4;
layout->s_arg6 = sizeof(UWord) * 5;
- layout->uu_arg7 = -1; /* impossible value */
+ layout->s_arg7 = sizeof(UWord) * 6;
layout->uu_arg8 = -1; /* impossible value */
#elif defined(VGP_mips64_linux)
@@ -1538,17 +1500,6 @@
layout->uu_arg7 = -1; /* impossible value */
layout->uu_arg8 = -1; /* impossible value */
-#elif defined(VGP_tilegx_linux)
- layout->o_sysno = OFFSET_tilegx_r(10);
- layout->o_arg1 = OFFSET_tilegx_r(0);
- layout->o_arg2 = OFFSET_tilegx_r(1);
- layout->o_arg3 = OFFSET_tilegx_r(2);
- layout->o_arg4 = OFFSET_tilegx_r(3);
- layout->o_arg5 = OFFSET_tilegx_r(4);
- layout->o_arg6 = OFFSET_tilegx_r(5);
- layout->uu_arg7 = -1; /* impossible value */
- layout->uu_arg8 = -1; /* impossible value */
-
#elif defined(VGP_x86_solaris)
layout->o_sysno = OFFSET_x86_EAX;
/* Syscall parameters are on the stack. */
@@ -2498,21 +2449,6 @@
# error "Unknown endianness"
# endif
}
-#elif defined(VGP_tilegx_linux)
- arch->vex.guest_pc -= 8; // sizeof({ swint1 })
-
- /* Make sure our caller is actually sane, and we're really backing
- back over a syscall. no other instruction in same bundle.
- */
- {
- unsigned long *p = (unsigned long *)arch->vex.guest_pc;
-
- if (p[0] != 0x286b180051485000ULL ) // "swint1", little enidan only
- VG_(message)(Vg_DebugMsg,
- "?! restarting over syscall at 0x%lx %lx\n",
- arch->vex.guest_pc, p[0]);
- vg_assert(p[0] == 0x286b180051485000ULL);
- }
#elif defined(VGP_x86_solaris)
arch->vex.guest_EIP -= 2; // sizeof(int $0x91) or sizeof(syscall)
diff --git a/coregrind/m_syswrap/syswrap-mips32-linux.c b/coregrind/m_syswrap/syswrap-mips32-linux.c
index 97f9007..3dd43dd 100644
--- a/coregrind/m_syswrap/syswrap-mips32-linux.c
+++ b/coregrind/m_syswrap/syswrap-mips32-linux.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 RT-RK
+ Copyright (C) 2010-2017 RT-RK
mips-valgrind@rt-rk.com
This program is free software; you can redistribute it and/or
@@ -77,41 +77,41 @@
stack, and use 'retaddr' as f's return-to address. Also, clear all
the integer registers before entering f.*/
-__attribute__ ((noreturn))
-void ML_ (call_on_new_stack_0_1) (Addr stack, Addr retaddr,
+__attribute__ ((noreturn))
+void ML_ (call_on_new_stack_0_1) (Addr stack, Addr retaddr,
void (*f) (Word), Word arg1);
// a0 = stack
// a1 = retaddr
// a2 = f
// a3 = arg1
asm (
-".text\n"
-".globl vgModuleLocal_call_on_new_stack_0_1\n"
+".text\n"
+".globl vgModuleLocal_call_on_new_stack_0_1\n"
"vgModuleLocal_call_on_new_stack_0_1:\n"
-" move $29, $4\n\t" // stack to %sp
-" move $25, $6\n\t" // f to t9/$25
-" move $4, $7\n\t" // arg1 to $a0
-" li $2, 0\n\t" // zero all GP regs
-" li $3, 0\n\t"
-" li $5, 0\n\t"
-" li $6, 0\n\t"
-" li $7, 0\n\t"
-
-" li $12, 0\n\t"
-" li $13, 0\n\t"
-" li $14, 0\n\t"
-" li $15, 0\n\t"
-" li $16, 0\n\t"
-" li $17, 0\n\t"
-" li $18, 0\n\t"
-" li $19, 0\n\t"
-" li $20, 0\n\t"
-" li $21, 0\n\t"
-" li $22, 0\n\t"
-" li $23, 0\n\t"
-" li $24, 0\n\t"
-" jr $25\n\t" // jump to dst
-" break 0x7\n" // should never get here
+" move $29, $4\n\t" // stack to %sp
+" move $31, $5\n\t" // retaddr to $ra
+" move $25, $6\n\t" // f to t9/$25
+" move $4, $7\n\t" // arg1 to $a0
+" li $2, 0\n\t" // zero all GP regs
+" li $3, 0\n\t"
+" li $5, 0\n\t"
+" li $6, 0\n\t"
+" li $7, 0\n\t"
+" li $12, 0\n\t"
+" li $13, 0\n\t"
+" li $14, 0\n\t"
+" li $15, 0\n\t"
+" li $16, 0\n\t"
+" li $17, 0\n\t"
+" li $18, 0\n\t"
+" li $19, 0\n\t"
+" li $20, 0\n\t"
+" li $21, 0\n\t"
+" li $22, 0\n\t"
+" li $23, 0\n\t"
+" li $24, 0\n\t"
+" jr $25\n\t" // jump to dst
+" break 0x7\n" // should never get here
".previous\n"
);
@@ -144,14 +144,7 @@
#define __NR_CLONE VG_STRINGIFY(__NR_clone)
#define __NR_EXIT VG_STRINGIFY(__NR_exit)
-//extern
-UInt do_syscall_clone_mips_linux (Word (*fn) (void *), //a0 0 32
- void *stack, //a1 4 36
- Int flags, //a2 8 40
- void *arg, //a3 12 44
- Int * child_tid, //stack 16 48
- Int * parent_tid, //stack 20 52
- Int tls); //stack 24 56
+// See priv_syswrap-linux.h for arg profile.
asm (
".text\n"
" .globl do_syscall_clone_mips_linux\n"
@@ -219,109 +212,10 @@
#undef __NR_EXIT
// forward declarations
-
-static void setup_child (ThreadArchState *, ThreadArchState *);
static SysRes sys_set_tls (ThreadId tid, Addr tlsptr);
static SysRes mips_PRE_sys_mmap (ThreadId tid,
UWord arg1, UWord arg2, UWord arg3,
UWord arg4, UWord arg5, Off64T arg6);
-/*
- When a client clones, we need to keep track of the new thread. This means:
- 1. allocate a ThreadId+ThreadState+stack for the thread
- 2. initialize the thread's new VCPU state
- 3. create the thread using the same args as the client requested,
- but using the scheduler entrypoint for IP, and a separate stack
- for SP.
- */
-
-static SysRes do_clone (ThreadId ptid,
- UInt flags, Addr sp,
- Int * parent_tidptr,
- Int * child_tidptr,
- Addr child_tls)
-{
- const Bool debug = False;
- ThreadId ctid = VG_ (alloc_ThreadState) ();
- ThreadState * ptst = VG_ (get_ThreadState) (ptid);
- ThreadState * ctst = VG_ (get_ThreadState) (ctid);
- UInt ret = 0;
- UWord * stack;
- SysRes res;
- vki_sigset_t blockall, savedmask;
-
- VG_ (sigfillset) (&blockall);
- vg_assert (VG_ (is_running_thread) (ptid));
- vg_assert (VG_ (is_valid_tid) (ctid));
- stack = (UWord *) ML_ (allocstack) (ctid);
- if (stack == NULL) {
- res = VG_ (mk_SysRes_Error) (VKI_ENOMEM);
- goto out;
- }
- setup_child (&ctst->arch, &ptst->arch);
-
- /* on MIPS we need to set V0 and A3 to zero */
- ctst->arch.vex.guest_r2 = 0;
- ctst->arch.vex.guest_r7 = 0;
- if (sp != 0)
- ctst->arch.vex.guest_r29 = sp;
-
- ctst->os_state.parent = ptid;
- ctst->sig_mask = ptst->sig_mask;
- ctst->tmp_sig_mask = ptst->sig_mask;
-
- /* Start the child with its threadgroup being the same as the
- parent's. This is so that any exit_group calls that happen
- after the child is created but before it sets its
- os_state.threadgroup field for real (in thread_wrapper in
- syswrap-linux.c), really kill the new thread. a.k.a this avoids
- a race condition in which the thread is unkillable (via
- exit_group) because its threadgroup is not set. The race window
- is probably only a few hundred or a few thousand cycles long.
- See #226116. */
-
- ctst->os_state.threadgroup = ptst->os_state.threadgroup;
-
- ML_(guess_and_register_stack) (sp, ctst);
-
- VG_TRACK (pre_thread_ll_create, ptid, ctid);
- if (flags & VKI_CLONE_SETTLS) {
- if (debug)
- VG_(printf)("clone child has SETTLS: tls at %#lx\n", child_tls);
- ctst->arch.vex.guest_r27 = child_tls;
- res = sys_set_tls(ctid, child_tls);
- if (sr_isError(res))
- goto out;
- ctst->arch.vex.guest_r27 = child_tls;
- }
-
- flags &= ~VKI_CLONE_SETTLS;
- VG_ (sigprocmask) (VKI_SIG_SETMASK, &blockall, &savedmask);
- /* Create the new thread */
- ret = do_syscall_clone_mips_linux (ML_ (start_thread_NORETURN),
- stack, flags, &VG_ (threads)[ctid],
- child_tidptr, parent_tidptr,
- 0 /*child_tls*/);
-
- /* High half word64 is syscall return value. Low half is
- the entire CR, from which we need to extract CR0.SO. */
- if (debug)
- VG_(printf)("ret: 0x%x\n", ret);
-
- res = VG_ (mk_SysRes_mips32_linux) (/*val */ ret, 0, /*errflag */ 0);
-
- VG_ (sigprocmask) (VKI_SIG_SETMASK, &savedmask, NULL);
-
- out:
- if (sr_isError (res)) {
- VG_(cleanup_thread) (&ctst->arch);
- ctst->status = VgTs_Empty;
- VG_TRACK (pre_thread_ll_exit, ctid);
- }
- ptst->arch.vex.guest_r2 = 0;
-
- return res;
-}
-
/* ---------------------------------------------------------------------
More thread stuff
------------------------------------------------------------------ */
@@ -331,16 +225,6 @@
void
VG_ (cleanup_thread) (ThreadArchState * arch) { }
-void
-setup_child ( /*OUT*/ ThreadArchState * child,
- /*IN*/ ThreadArchState * parent)
-{
- /* We inherit our parent's guest state. */
- child->vex = parent->vex;
- child->vex_shadow1 = parent->vex_shadow1;
- child->vex_shadow2 = parent->vex_shadow2;
-}
-
SysRes sys_set_tls ( ThreadId tid, Addr tlsptr )
{
VG_(threads)[tid].arch.vex.guest_ULR = tlsptr;
@@ -518,15 +402,16 @@
DECL_TEMPLATE (mips_linux, sys_mmap2);
DECL_TEMPLATE (mips_linux, sys_stat64);
DECL_TEMPLATE (mips_linux, sys_lstat64);
+DECL_TEMPLATE (mips_linux, sys_fadvise64);
DECL_TEMPLATE (mips_linux, sys_fstatat64);
DECL_TEMPLATE (mips_linux, sys_fstat64);
-DECL_TEMPLATE (mips_linux, sys_clone);
DECL_TEMPLATE (mips_linux, sys_sigreturn);
DECL_TEMPLATE (mips_linux, sys_rt_sigreturn);
DECL_TEMPLATE (mips_linux, sys_cacheflush);
DECL_TEMPLATE (mips_linux, sys_set_thread_area);
DECL_TEMPLATE (mips_linux, sys_pipe);
DECL_TEMPLATE (mips_linux, sys_prctl);
+DECL_TEMPLATE (mips_linux, sys_ptrace);
PRE(sys_mmap2)
{
@@ -553,14 +438,68 @@
int, prot, int, flags, int, fd, unsigned long, offset);
r = mips_PRE_sys_mmap(tid, ARG1, ARG2, ARG3, ARG4, ARG5, (Off64T) ARG6);
SET_STATUS_from_SysRes(r);
-}
+}
+
+PRE(sys_ptrace)
+{
+ PRINT("sys_ptrace ( %ld, %ld, %#lx, %#lx )", SARG1, SARG2, ARG3, ARG4);
+ PRE_REG_READ4(int, "ptrace",
+ long, request, long, pid, unsigned long, addr,
+ unsigned long, data);
+ switch (ARG1) {
+ case VKI_PTRACE_PEEKTEXT:
+ case VKI_PTRACE_PEEKDATA:
+ case VKI_PTRACE_PEEKUSR:
+ PRE_MEM_WRITE("ptrace(peek)", ARG4, sizeof(long));
+ break;
+ case VKI_PTRACE_GETEVENTMSG:
+ PRE_MEM_WRITE("ptrace(geteventmsg)", ARG4, sizeof(unsigned long));
+ break;
+ case VKI_PTRACE_GETSIGINFO:
+ PRE_MEM_WRITE("ptrace(getsiginfo)", ARG4, sizeof(vki_siginfo_t));
+ break;
+ case VKI_PTRACE_SETSIGINFO:
+ PRE_MEM_READ("ptrace(setsiginfo)", ARG4, sizeof(vki_siginfo_t));
+ break;
+ case VKI_PTRACE_GETREGSET:
+ ML_(linux_PRE_getregset)(tid, ARG3, ARG4);
+ break;
+ default:
+ break;
+ }
+}
+
+POST(sys_ptrace)
+{
+ switch (ARG1) {
+ case VKI_PTRACE_TRACEME:
+ ML_(linux_POST_traceme)(tid);
+ break;
+ case VKI_PTRACE_PEEKTEXT:
+ case VKI_PTRACE_PEEKDATA:
+ case VKI_PTRACE_PEEKUSR:
+ POST_MEM_WRITE (ARG4, sizeof(long));
+ break;
+ case VKI_PTRACE_GETEVENTMSG:
+ POST_MEM_WRITE (ARG4, sizeof(unsigned long));
+ break;
+ case VKI_PTRACE_GETSIGINFO:
+ POST_MEM_WRITE (ARG4, sizeof(vki_siginfo_t));
+ break;
+ case VKI_PTRACE_GETREGSET:
+ ML_(linux_POST_getregset)(tid, ARG3, ARG4);
+ break;
+ default:
+ break;
+ }
+}
// XXX: lstat64/fstat64/stat64 are generic, but not necessarily
// applicable to every architecture -- I think only to 32-bit archs.
// We're going to need something like linux/core_os32.h for such
// things, eventually, I think. --njn
-PRE (sys_lstat64)
+PRE(sys_lstat64)
{
PRINT ("sys_lstat64 ( %#lx(%s), %#lx )", ARG1, (HChar *) ARG1, ARG2);
PRE_REG_READ2 (long, "lstat64", char *, file_name, struct stat64 *, buf);
@@ -568,7 +507,7 @@
PRE_MEM_WRITE ("lstat64(buf)", ARG2, sizeof (struct vki_stat64));
}
-POST (sys_lstat64)
+POST(sys_lstat64)
{
vg_assert (SUCCESS);
if (RES == 0)
@@ -577,7 +516,7 @@
}
}
-PRE (sys_stat64)
+PRE(sys_stat64)
{
PRINT ("sys_stat64 ( %#lx(%s), %#lx )", ARG1, (HChar *) ARG1, ARG2);
PRE_REG_READ2 (long, "stat64", char *, file_name, struct stat64 *, buf);
@@ -585,12 +524,28 @@
PRE_MEM_WRITE ("stat64(buf)", ARG2, sizeof (struct vki_stat64));
}
-POST (sys_stat64)
+POST(sys_stat64)
{
POST_MEM_WRITE (ARG2, sizeof (struct vki_stat64));
}
-PRE (sys_fstatat64)
+PRE(sys_fadvise64)
+{
+ PRINT("sys_fadvise64 ( %ld, %llu, %llu, %ld )",
+ SARG1, MERGE64(ARG3,ARG4), MERGE64(ARG5, ARG6), SARG7);
+
+ if (VG_(tdict).track_pre_reg_read) {
+ PRRSN;
+ PRA1("fadvise64", int, fd);
+ PRA3("fadvise64", vki_u32, MERGE64_FIRST(offset));
+ PRA4("fadvise64", vki_u32, MERGE64_SECOND(offset));
+ PRA5("fadvise64", vki_u32, MERGE64_FIRST(len));
+ PRA6("fadvise64", vki_u32, MERGE64_SECOND(len));
+ PRA7("fadvise64", int, advice);
+ }
+}
+
+PRE(sys_fstatat64)
{
// ARG4 = int flags; Flags are or'ed together, therefore writing them
// as a hex constant is more meaningful.
@@ -602,114 +557,24 @@
PRE_MEM_WRITE ("fstatat64(buf)", ARG3, sizeof (struct vki_stat64));
}
-POST (sys_fstatat64)
+POST(sys_fstatat64)
{
POST_MEM_WRITE (ARG3, sizeof (struct vki_stat64));
}
-PRE (sys_fstat64)
+PRE(sys_fstat64)
{
PRINT ("sys_fstat64 ( %lu, %#lx )", SARG1, ARG2);
PRE_REG_READ2 (long, "fstat64", unsigned long, fd, struct stat64 *, buf);
PRE_MEM_WRITE ("fstat64(buf)", ARG2, sizeof (struct vki_stat64));
}
-POST (sys_fstat64)
+POST(sys_fstat64)
{
POST_MEM_WRITE (ARG2, sizeof (struct vki_stat64));
}
-PRE (sys_clone)
- {
- Bool badarg = False;
- UInt cloneflags;
- PRINT ("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )", ARG1, ARG2, ARG3,
- ARG4, ARG5);
- PRE_REG_READ2 (int, "clone", unsigned long, flags, void *, child_stack);
- if (ARG1 & VKI_CLONE_PARENT_SETTID)
- {
- if (VG_ (tdict).track_pre_reg_read)
- {
- PRA3 ("clone", int *, parent_tidptr);
- }
- PRE_MEM_WRITE ("clone(parent_tidptr)", ARG3, sizeof (Int));
- if (!VG_ (am_is_valid_for_client)(ARG3, sizeof (Int), VKI_PROT_WRITE))
- {
- badarg = True;
- }
- }
- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID))
- {
- if (VG_ (tdict).track_pre_reg_read)
- {
- PRA5 ("clone", int *, child_tidptr);
- }
- PRE_MEM_WRITE ("clone(child_tidptr)", ARG5, sizeof (Int));
- if (!VG_ (am_is_valid_for_client)(ARG5, sizeof (Int), VKI_PROT_WRITE))
- {
- badarg = True;
- }
- }
- if (badarg)
- {
- SET_STATUS_Failure (VKI_EFAULT);
- return;
- }
- cloneflags = ARG1;
- if (!ML_ (client_signal_OK) (ARG1 & VKI_CSIGNAL))
- {
- SET_STATUS_Failure (VKI_EINVAL);
- return;
- }
- /* Only look at the flags we really care about */
- switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS
- |VKI_CLONE_FILES | VKI_CLONE_VFORK))
- {
- case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES:
- /* thread creation */
- PRINT ("sys_clone1 ( %#lx, %#lx, %#lx, %#lx, %#lx )",
- ARG1, ARG2, ARG3, ARG4, ARG5);
- SET_STATUS_from_SysRes (do_clone (tid,
- ARG1, /* flags */
- (Addr) ARG2, /* child SP */
- (Int *) ARG3, /* parent_tidptr */
- (Int *) ARG5, /* child_tidptr */
- (Addr) ARG4)); /* child_tls */
-
- break;
- case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */
- /* FALLTHROUGH - assume vfork == fork */
- cloneflags &= ~(VKI_CLONE_VFORK | VKI_CLONE_VM);
- case 0: /* plain fork */
- SET_STATUS_from_SysRes (ML_ (do_fork_clone) (tid,
- cloneflags, /* flags */
- (Int *) ARG3, /* parent_tidptr */
- (Int *) ARG5)); /* child_tidptr */
- break;
- default:
- /* should we just ENOSYS? */
- VG_ (message) (Vg_UserMsg, "Unsupported clone() flags: 0x%lx\n", ARG1);
- VG_ (message) (Vg_UserMsg, "\n");
- VG_ (message) (Vg_UserMsg, "The only supported clone() uses are:\n");
- VG_ (message) (Vg_UserMsg,
- " - via a threads library (LinuxThreads or NPTL)\n");
- VG_ (message) (Vg_UserMsg,
- " - via the implementation of fork or vfork\n");
- VG_ (unimplemented)("Valgrind does not support general clone().");
- }
- if (SUCCESS)
- {
- if (ARG1 & VKI_CLONE_PARENT_SETTID)
- POST_MEM_WRITE (ARG3, sizeof (Int));
- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID))
- POST_MEM_WRITE (ARG5, sizeof (Int));
- /* Thread creation was successful; let the child have the chance
- * to run */
- *flags |= SfYieldAfter;
- }
-}
-
-PRE (sys_sigreturn)
+PRE(sys_sigreturn)
{
PRINT ("sys_sigreturn ( )");
vg_assert (VG_ (is_valid_tid) (tid));
@@ -724,7 +589,7 @@
*flags |= SfPollAfter;
}
-PRE (sys_rt_sigreturn)
+PRE(sys_rt_sigreturn)
{
PRINT ("rt_sigreturn ( )");
vg_assert (VG_ (is_valid_tid) (tid));
@@ -740,7 +605,7 @@
*flags |= SfPollAfter;
}
-PRE (sys_set_thread_area)
+PRE(sys_set_thread_area)
{
PRINT ("set_thread_area (%lx)", ARG1);
PRE_REG_READ1(long, "set_thread_area", unsigned long, addr);
@@ -748,7 +613,7 @@
}
/* Very much MIPS specific */
-PRE (sys_cacheflush)
+PRE(sys_cacheflush)
{
PRINT ("cacheflush (%lx, %ld, %ld)", ARG1, SARG2, SARG3);
PRE_REG_READ3(long, "cacheflush", unsigned long, addr,
@@ -785,7 +650,7 @@
}
}
-PRE (sys_prctl)
+PRE(sys_prctl)
{
switch (ARG1) {
case VKI_PR_SET_FP_MODE:
@@ -831,6 +696,11 @@
}
}
+POST(sys_prctl)
+{
+ WRAPPER_POST_NAME(linux, sys_prctl)(tid, arrghs, status);
+}
+
#undef PRE
#undef POST
@@ -875,7 +745,7 @@
GENX_ (__NR_setuid, sys_setuid), // 23
GENX_ (__NR_getuid, sys_getuid), // 24
LINX_ (__NR_stime, sys_stime), // 25
- //.. PLAXY(__NR_ptrace, sys_ptrace), // 26
+ PLAXY(__NR_ptrace, sys_ptrace), // 26
GENX_ (__NR_alarm, sys_alarm), // 27
//.. // (__NR_oldfstat, sys_fstat), // 28
GENX_ (__NR_pause, sys_pause), // 29
@@ -969,7 +839,7 @@
LINXY (__NR_ipc, sys_ipc), // 117
GENX_ (__NR_fsync, sys_fsync), // 118
PLAX_ (__NR_sigreturn, sys_sigreturn), // 119
- PLAX_ (__NR_clone, sys_clone), // 120
+ LINX_ (__NR_clone, sys_clone), // 120
//.. // (__NR_setdomainname, sys_setdomainname), // 121
GENXY (__NR_uname, sys_newuname), // 122
//.. PLAX_(__NR_modify_ldt, sys_modify_ldt), // 123
@@ -1038,7 +908,7 @@
//..
LINX_ (__NR_setresgid, sys_setresgid), // 190
LINXY (__NR_getresgid, sys_getresgid), // 191
- PLAX_ (__NR_prctl, sys_prctl), // 192
+ PLAXY (__NR_prctl, sys_prctl), // 192
PLAX_ (__NR_rt_sigreturn, sys_rt_sigreturn), // 193
LINXY (__NR_rt_sigaction, sys_rt_sigaction), // 194
LINXY (__NR_rt_sigprocmask, sys_rt_sigprocmask), // 195
@@ -1096,7 +966,7 @@
LINXY (__NR_epoll_wait, sys_epoll_wait), // 250
//..
LINX_ (__NR_set_tid_address, sys_set_tid_address), // 252
- LINX_ (__NR_fadvise64, sys_fadvise64), // 254
+ PLAX_ (__NR_fadvise64, sys_fadvise64), // 254
GENXY (__NR_statfs64, sys_statfs64), // 255
GENXY (__NR_fstatfs64, sys_fstatfs64), // 256
//..
diff --git a/coregrind/m_syswrap/syswrap-mips64-linux.c b/coregrind/m_syswrap/syswrap-mips64-linux.c
index ed27495..4cdad75 100644
--- a/coregrind/m_syswrap/syswrap-mips64-linux.c
+++ b/coregrind/m_syswrap/syswrap-mips64-linux.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 RT-RK
+ Copyright (C) 2010-2017 RT-RK
mips-valgrind@rt-rk.com
This program is free software; you can redistribute it and/or
@@ -84,12 +84,30 @@
".text\n"
".globl vgModuleLocal_call_on_new_stack_0_1\n"
"vgModuleLocal_call_on_new_stack_0_1:\n"
-" move $29, $4\n" /* set stack */
-" move $4, $7\n" /* arg1 to $4 */
+" move $29, $4\n" /* set stack */
+" move $4, $7\n" /* arg1 to $4 */
" move $25, $6\n"
-" move $31, $5\n" /* retaddr to $ra */
-" jr $25\n" /* jump to f */
-" break 0x7\n" /* should never get here */
+" move $31, $5\n" /* retaddr to $ra */
+" li $2, 0\n\t" /* zero all GP regs */
+" li $3, 0\n\t"
+" li $5, 0\n\t"
+" li $6, 0\n\t"
+" li $7, 0\n\t"
+" li $12, 0\n\t"
+" li $13, 0\n\t"
+" li $14, 0\n\t"
+" li $15, 0\n\t"
+" li $16, 0\n\t"
+" li $17, 0\n\t"
+" li $18, 0\n\t"
+" li $19, 0\n\t"
+" li $20, 0\n\t"
+" li $21, 0\n\t"
+" li $22, 0\n\t"
+" li $23, 0\n\t"
+" li $24, 0\n\t"
+" jr $25\n" /* jump to f */
+" break 0x7\n" /* should never get here */
".previous\n"
);
@@ -118,14 +136,7 @@
#define __NR_CLONE __NR_clone
#define __NR_EXIT __NR_exit
-ULong do_syscall_clone_mips64_linux ( Word (*fn) (void *), /* a0 - 4 */
- void* stack, /* a1 - 5 */
- Int flags, /* a2 - 6 */
- void* arg, /* a3 - 7 */
- Int* parent_tid, /* a4 - 8 */
- void* /* Int tls */, /* a5 - 9 */
- Int* child_tid ); /* a6 - 10 */
-
+// See priv_syswrap-linux.h for arg profile.
asm(
".text\n"
".set noreorder\n"
@@ -181,104 +192,13 @@
#undef __NR_EXIT
/* forward declarations */
-static void setup_child ( ThreadArchState *, ThreadArchState *);
static SysRes sys_set_tls ( ThreadId tid, Addr tlsptr);
-/* When a client clones, we need to keep track of the new thread. This means:
- 1. allocate a ThreadId+ThreadState+stack for the thread
-
- 2. initialize the thread's new VCPU state
-
- 3. create the thread using the same args as the client requested, but using
- the scheduler entrypoint for IP, and a separate stack for SP. */
-static SysRes do_clone ( ThreadId ptid,
- UInt flags, Addr sp,
- Int* parent_tidptr,
- Int* child_tidptr,
- Addr child_tls )
-{
- const Bool debug = False;
- ThreadId ctid = VG_ (alloc_ThreadState) ();
- ThreadState * ptst = VG_ (get_ThreadState) (ptid);
- ThreadState * ctst = VG_ (get_ThreadState) (ctid);
- UInt ret = 0;
- UWord * stack;
- SysRes res;
- vki_sigset_t blockall, savedmask;
-
- VG_(sigfillset)(&blockall);
- vg_assert(VG_(is_running_thread)(ptid));
- vg_assert(VG_(is_valid_tid)(ctid));
- stack = (UWord *)ML_(allocstack)(ctid);
- if (stack == NULL) {
- res = VG_(mk_SysRes_Error)(VKI_ENOMEM);
- goto out;
- }
- setup_child(&ctst->arch, &ptst->arch);
-
- /* on MIPS we need to set V0 and A3 to zero */
- ctst->arch.vex.guest_r2 = 0;
- ctst->arch.vex.guest_r7 = 0;
- if (sp != 0)
- ctst->arch.vex.guest_r29 = sp;
-
- ctst->os_state.parent = ptid;
- ctst->sig_mask = ptst->sig_mask;
- ctst->tmp_sig_mask = ptst->sig_mask;
-
- ctst->os_state.threadgroup = ptst->os_state.threadgroup;
-
- ML_(guess_and_register_stack) (sp, ctst);
-
- VG_TRACK(pre_thread_ll_create, ptid, ctid);
- if (flags & VKI_CLONE_SETTLS) {
- if (debug)
- VG_(printf)("clone child has SETTLS: tls at %#lx\n", child_tls);
- res = sys_set_tls(ctid, child_tls);
- if (sr_isError(res))
- goto out;
- ctst->arch.vex.guest_r27 = child_tls;
- }
-
- flags &= ~VKI_CLONE_SETTLS;
- VG_ (sigprocmask) (VKI_SIG_SETMASK, &blockall, &savedmask);
- /* Create the new thread */
- ret = do_syscall_clone_mips64_linux(ML_(start_thread_NORETURN),
- stack, flags, &VG_(threads)[ctid],
- parent_tidptr, NULL /*child_tls*/,
- child_tidptr);
- if (debug)
- VG_(printf)("ret: 0x%x\n", ret);
-
- res = VG_(mk_SysRes_mips64_linux)( /* val */ ret, 0, /* errflag */ 0);
-
- VG_(sigprocmask)(VKI_SIG_SETMASK, &savedmask, NULL);
-
- out:
- if (sr_isError (res)) {
- VG_ (cleanup_thread) (&ctst->arch);
- ctst->status = VgTs_Empty;
- VG_TRACK (pre_thread_ll_exit, ctid);
- }
- ptst->arch.vex.guest_r2 = 0;
-
- return res;
-}
-
/* ---------------------------------------------------------------------
More thread stuff
------------------------------------------------------------------ */
void VG_(cleanup_thread) ( ThreadArchState * arch ) { };
-void setup_child ( /* OUT */ ThreadArchState * child,
- /* IN */ ThreadArchState * parent )
-{
- /* We inherit our parent's guest state. */
- child->vex = parent->vex;
- child->vex_shadow1 = parent->vex_shadow1;
- child->vex_shadow2 = parent->vex_shadow2;
-}
-
SysRes sys_set_tls ( ThreadId tid, Addr tlsptr )
{
VG_(threads)[tid].arch.vex.guest_ULR = tlsptr;
@@ -298,7 +218,6 @@
file, but that requires even more macro magic. */
DECL_TEMPLATE (mips_linux, sys_set_thread_area);
-DECL_TEMPLATE (mips_linux, sys_clone);
DECL_TEMPLATE (mips_linux, sys_tee);
DECL_TEMPLATE (mips_linux, sys_splice);
DECL_TEMPLATE (mips_linux, sys_vmsplice);
@@ -317,6 +236,7 @@
DECL_TEMPLATE (mips_linux, sys_mmap);
DECL_TEMPLATE (mips_linux, sys_rt_sigreturn);
DECL_TEMPLATE (mips_linux, sys_pipe);
+DECL_TEMPLATE (mips_linux, sys_fadvise64);
PRE(sys_tee)
{
@@ -445,6 +365,9 @@
POST(sys_ptrace)
{
switch (ARG1) {
+ case VKI_PTRACE_TRACEME:
+ ML_(linux_POST_traceme)(tid);
+ break;
case VKI_PTRACE_PEEKTEXT:
case VKI_PTRACE_PEEKDATA:
case VKI_PTRACE_PEEKUSR:
@@ -464,7 +387,7 @@
}
}
-PRE (sys_mmap)
+PRE(sys_mmap)
{
SysRes r;
PRINT("sys_mmap ( %#lx, %lu, %ld, %ld, %ld, %lu )",
@@ -475,84 +398,6 @@
(Off64T) ARG6);
SET_STATUS_from_SysRes(r);
}
-
-PRE(sys_clone)
-{
- Bool badarg = False;
- UInt cloneflags;
- PRINT("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )", ARG1, ARG2, ARG3,
- ARG4, ARG5);
- PRE_REG_READ2(int, "clone", unsigned long, flags, void *, child_stack);
- if (ARG1 & VKI_CLONE_PARENT_SETTID) {
- if (VG_(tdict).track_pre_reg_read) {
- PRA3("clone", int *, parent_tidptr);
- }
- PRE_MEM_WRITE("clone(parent_tidptr)", ARG3, sizeof(Int));
- if (!VG_(am_is_valid_for_client)(ARG3, sizeof(Int), VKI_PROT_WRITE)) {
- badarg = True;
- }
- }
- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) {
- if (VG_(tdict).track_pre_reg_read) {
- PRA5("clone", int *, child_tidptr);
- }
- PRE_MEM_WRITE("clone(child_tidptr)", ARG5, sizeof (Int));
- if (!VG_(am_is_valid_for_client)(ARG5, sizeof (Int), VKI_PROT_WRITE))
- badarg = True;
- }
- if (badarg) {
- SET_STATUS_Failure(VKI_EFAULT);
- return;
- }
- cloneflags = ARG1;
- if (!ML_(client_signal_OK)(ARG1 & VKI_CSIGNAL)) {
- SET_STATUS_Failure(VKI_EINVAL);
- return;
- }
- /* Only look at the flags we really care about */
- switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS
- |VKI_CLONE_FILES | VKI_CLONE_VFORK)) {
- case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES:
- /* thread creation */
- SET_STATUS_from_SysRes(do_clone(tid,
- ARG1, /* flags */
- (Addr)ARG2, /* child SP */
- (Int *)ARG3, /* parent_tidptr */
- (Int *)ARG5, /* child_tidptr */
- (Addr)ARG4)); /* child_tls */
- break;
-
- case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */
- /* FALLTHROUGH - assume vfork == fork */
- cloneflags &= ~(VKI_CLONE_VFORK | VKI_CLONE_VM);
- case 0: /* plain fork */
- SET_STATUS_from_SysRes(ML_(do_fork_clone)(tid,
- cloneflags, /* flags */
- (Int *)ARG3, /* parent_tidptr */
- (Int *)ARG5)); /* child_tidptr */
- break;
-
- default:
- /* should we just ENOSYS? */
- VG_(message)(Vg_UserMsg, "Unsupported clone() flags: 0x%lx\n", ARG1);
- VG_(message)(Vg_UserMsg, "\n");
- VG_(message)(Vg_UserMsg, "The only supported clone() uses are:\n");
- VG_(message)(Vg_UserMsg,
- " - via a threads library (LinuxThreads or NPTL)\n");
- VG_(message)(Vg_UserMsg,
- " - via the implementation of fork or vfork\n");
- VG_(unimplemented)("Valgrind does not support general clone().");
- }
- if (SUCCESS) {
- if (ARG1 & VKI_CLONE_PARENT_SETTID)
- POST_MEM_WRITE(ARG3, sizeof(Int));
- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID))
- POST_MEM_WRITE(ARG5, sizeof(Int));
- /* Thread creation was successful; let the child have the chance to run */
- *flags |= SfYieldAfter;
- }
-}
-
PRE(sys_rt_sigreturn)
{
/* See comments on PRE(sys_rt_sigreturn) in syswrap-s390x-linux.c for
@@ -616,7 +461,7 @@
}
}
-PRE (sys_prctl)
+PRE(sys_prctl)
{
switch (ARG1) {
case VKI_PR_SET_FP_MODE:
@@ -662,6 +507,18 @@
}
}
+POST(sys_prctl)
+{
+ WRAPPER_POST_NAME(linux, sys_prctl)(tid, arrghs, status);
+}
+
+PRE(sys_fadvise64)
+{
+ PRINT("sys_fadvise64 ( %ld, %ld, %lu, %ld )", SARG1, SARG2, ARG3, SARG4);
+ PRE_REG_READ4(long, "fadvise64",
+ int, fd, vki_loff_t, offset, vki_loff_t, len, int, advice);
+}
+
#undef PRE
#undef POST
@@ -706,7 +563,7 @@
GENXY (__NR_mincore, sys_mincore),
GENX_ (__NR_madvise, sys_madvise),
LINX_ (__NR_shmget, sys_shmget),
- LINXY (__NR_shmat, wrap_sys_shmat),
+ LINXY (__NR_shmat, sys_shmat),
LINXY (__NR_shmctl, sys_shmctl),
GENXY (__NR_dup, sys_dup),
GENXY (__NR_dup2, sys_dup2),
@@ -735,7 +592,7 @@
LINXY (__NR_socketpair, sys_socketpair),
LINX_ (__NR_setsockopt, sys_setsockopt),
LINXY (__NR_getsockopt, sys_getsockopt),
- PLAX_ (__NR_clone, sys_clone),
+ LINX_ (__NR_clone, sys_clone),
GENX_ (__NR_fork, sys_fork),
GENX_ (__NR_execve, sys_execve),
GENX_ (__NR_exit, sys_exit),
@@ -833,7 +690,7 @@
LINX_ (__NR_vhangup, sys_vhangup),
LINX_ (__NR_pivot_root,sys_pivot_root),
LINXY (__NR__sysctl, sys_sysctl),
- PLAX_ (__NR_prctl, sys_prctl),
+ PLAXY (__NR_prctl, sys_prctl),
LINXY (__NR_adjtimex, sys_adjtimex),
GENX_ (__NR_setrlimit, sys_setrlimit),
GENX_ (__NR_chroot, sys_chroot),
@@ -893,7 +750,7 @@
/* LINXY(__NR_fcntl64,sys_fcntl64), */
LINX_ (__NR_set_tid_address, sys_set_tid_address),
LINX_ (__NR_semtimedop, sys_semtimedop),
- LINX_ (__NR_fadvise64, sys_fadvise64),
+ PLAX_ (__NR_fadvise64, sys_fadvise64),
LINXY (__NR_timer_create, sys_timer_create),
LINXY (__NR_timer_settime, sys_timer_settime),
LINXY (__NR_timer_gettime, sys_timer_gettime),
diff --git a/coregrind/m_syswrap/syswrap-ppc32-linux.c b/coregrind/m_syswrap/syswrap-ppc32-linux.c
index 379fcb3..d150602 100644
--- a/coregrind/m_syswrap/syswrap-ppc32-linux.c
+++ b/coregrind/m_syswrap/syswrap-ppc32-linux.c
@@ -7,8 +7,8 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Nicholas Nethercote <njn@valgrind.org>
- Copyright (C) 2005-2015 Cerion Armour-Brown <cerion@open-works.co.uk>
+ Copyright (C) 2005-2017 Nicholas Nethercote <njn@valgrind.org>
+ Copyright (C) 2005-2017 Cerion Armour-Brown <cerion@open-works.co.uk>
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -146,14 +146,7 @@
#define __NR_CLONE VG_STRINGIFY(__NR_clone)
#define __NR_EXIT VG_STRINGIFY(__NR_exit)
-extern
-ULong do_syscall_clone_ppc32_linux ( Word (*fn)(void *),
- void* stack,
- Int flags,
- void* arg,
- Int* child_tid,
- Int* parent_tid,
- vki_modify_ldt_t * );
+// See priv_syswrap-linux.h for arg profile.
asm(
".text\n"
".globl do_syscall_clone_ppc32_linux\n"
@@ -216,145 +209,6 @@
#undef __NR_CLONE
#undef __NR_EXIT
-// forward declarations
-static void setup_child ( ThreadArchState*, ThreadArchState* );
-
-/*
- When a client clones, we need to keep track of the new thread. This means:
- 1. allocate a ThreadId+ThreadState+stack for the thread
-
- 2. initialize the thread's new VCPU state
-
- 3. create the thread using the same args as the client requested,
- but using the scheduler entrypoint for IP, and a separate stack
- for SP.
- */
-static SysRes do_clone ( ThreadId ptid,
- UInt flags, Addr sp,
- Int *parent_tidptr,
- Int *child_tidptr,
- Addr child_tls)
-{
- const Bool debug = False;
-
- ThreadId ctid = VG_(alloc_ThreadState)();
- ThreadState* ptst = VG_(get_ThreadState)(ptid);
- ThreadState* ctst = VG_(get_ThreadState)(ctid);
- ULong word64;
- UWord* stack;
- SysRes res;
- vki_sigset_t blockall, savedmask;
-
- VG_(sigfillset)(&blockall);
-
- vg_assert(VG_(is_running_thread)(ptid));
- vg_assert(VG_(is_valid_tid)(ctid));
-
- stack = (UWord*)ML_(allocstack)(ctid);
- if (stack == NULL) {
- res = VG_(mk_SysRes_Error)( VKI_ENOMEM );
- goto out;
- }
-
-//? /* make a stack frame */
-//? stack -= 16;
-//? *(UWord *)stack = 0;
-
-
- /* Copy register state
-
- Both parent and child return to the same place, and the code
- following the clone syscall works out which is which, so we
- don't need to worry about it.
-
- The parent gets the child's new tid returned from clone, but the
- child gets 0.
-
- If the clone call specifies a NULL SP for the new thread, then
- it actually gets a copy of the parent's SP.
-
- The child's TLS register (r2) gets set to the tlsaddr argument
- if the CLONE_SETTLS flag is set.
- */
- setup_child( &ctst->arch, &ptst->arch );
-
- /* Make sys_clone appear to have returned Success(0) in the
- child. */
- { UInt old_cr = LibVEX_GuestPPC32_get_CR( &ctst->arch.vex );
- /* %r3 = 0 */
- ctst->arch.vex.guest_GPR3 = 0;
- /* %cr0.so = 0 */
- LibVEX_GuestPPC32_put_CR( old_cr & ~(1<<28), &ctst->arch.vex );
- }
-
- if (sp != 0)
- ctst->arch.vex.guest_GPR1 = sp;
-
- ctst->os_state.parent = ptid;
-
- /* inherit signal mask */
- ctst->sig_mask = ptst->sig_mask;
- ctst->tmp_sig_mask = ptst->sig_mask;
-
- /* Start the child with its threadgroup being the same as the
- parent's. This is so that any exit_group calls that happen
- after the child is created but before it sets its
- os_state.threadgroup field for real (in thread_wrapper in
- syswrap-linux.c), really kill the new thread. a.k.a this avoids
- a race condition in which the thread is unkillable (via
- exit_group) because its threadgroup is not set. The race window
- is probably only a few hundred or a few thousand cycles long.
- See #226116. */
- ctst->os_state.threadgroup = ptst->os_state.threadgroup;
-
- ML_(guess_and_register_stack) (sp, ctst);
-
- /* Assume the clone will succeed, and tell any tool that wants to
- know that this thread has come into existence. If the clone
- fails, we'll send out a ll_exit notification for it at the out:
- label below, to clean up. */
- vg_assert(VG_(owns_BigLock_LL)(ptid));
- VG_TRACK ( pre_thread_ll_create, ptid, ctid );
-
- if (flags & VKI_CLONE_SETTLS) {
- if (debug)
- VG_(printf)("clone child has SETTLS: tls at %#lx\n", child_tls);
- ctst->arch.vex.guest_GPR2 = child_tls;
- }
-
- flags &= ~VKI_CLONE_SETTLS;
-
- /* start the thread with everything blocked */
- VG_(sigprocmask)(VKI_SIG_SETMASK, &blockall, &savedmask);
-
- /* Create the new thread */
- word64 = do_syscall_clone_ppc32_linux(
- ML_(start_thread_NORETURN), stack, flags, &VG_(threads)[ctid],
- child_tidptr, parent_tidptr, NULL
- );
- /* High half word64 is syscall return value. Low half is
- the entire CR, from which we need to extract CR0.SO. */
- /* VG_(printf)("word64 = 0x%llx\n", word64); */
- res = VG_(mk_SysRes_ppc32_linux)(
- /*val*/(UInt)(word64 >> 32),
- /*errflag*/ (((UInt)word64) >> 28) & 1
- );
-
- VG_(sigprocmask)(VKI_SIG_SETMASK, &savedmask, NULL);
-
- out:
- if (sr_isError(res)) {
- /* clone failed */
- VG_(cleanup_thread)(&ctst->arch);
- ctst->status = VgTs_Empty;
- /* oops. Better tell the tool the thread exited in a hurry :-) */
- VG_TRACK( pre_thread_ll_exit, ctid );
- }
-
- return res;
-}
-
-
/* ---------------------------------------------------------------------
More thread stuff
@@ -364,16 +218,6 @@
{
}
-void setup_child ( /*OUT*/ ThreadArchState *child,
- /*IN*/ ThreadArchState *parent )
-{
- /* We inherit our parent's guest state. */
- child->vex = parent->vex;
- child->vex_shadow1 = parent->vex_shadow1;
- child->vex_shadow2 = parent->vex_shadow2;
-}
-
-
/* ---------------------------------------------------------------------
PRE/POST wrappers for ppc32/Linux-specific syscalls
------------------------------------------------------------------ */
@@ -393,7 +237,6 @@
DECL_TEMPLATE(ppc32_linux, sys_lstat64);
DECL_TEMPLATE(ppc32_linux, sys_fstatat64);
DECL_TEMPLATE(ppc32_linux, sys_fstat64);
-DECL_TEMPLATE(ppc32_linux, sys_clone);
DECL_TEMPLATE(ppc32_linux, sys_sigreturn);
DECL_TEMPLATE(ppc32_linux, sys_rt_sigreturn);
DECL_TEMPLATE(ppc32_linux, sys_sigsuspend);
@@ -530,91 +373,6 @@
//.. }
//.. }
-PRE(sys_clone)
-{
- UInt cloneflags;
-
- PRINT("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )",ARG1,ARG2,ARG3,ARG4,ARG5);
- PRE_REG_READ5(int, "clone",
- unsigned long, flags,
- void *, child_stack,
- int *, parent_tidptr,
- void *, child_tls,
- int *, child_tidptr);
-
- if (ARG1 & VKI_CLONE_PARENT_SETTID) {
- PRE_MEM_WRITE("clone(parent_tidptr)", ARG3, sizeof(Int));
- if (!VG_(am_is_valid_for_client)(ARG3, sizeof(Int),
- VKI_PROT_WRITE)) {
- SET_STATUS_Failure( VKI_EFAULT );
- return;
- }
- }
- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) {
- PRE_MEM_WRITE("clone(child_tidptr)", ARG5, sizeof(Int));
- if (!VG_(am_is_valid_for_client)(ARG5, sizeof(Int),
- VKI_PROT_WRITE)) {
- SET_STATUS_Failure( VKI_EFAULT );
- return;
- }
- }
-
- cloneflags = ARG1;
-
- if (!ML_(client_signal_OK)(ARG1 & VKI_CSIGNAL)) {
- SET_STATUS_Failure( VKI_EINVAL );
- return;
- }
-
- /* Only look at the flags we really care about */
- switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS
- | VKI_CLONE_FILES | VKI_CLONE_VFORK)) {
- case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES:
- /* thread creation */
- SET_STATUS_from_SysRes(
- do_clone(tid,
- ARG1, /* flags */
- (Addr)ARG2, /* child SP */
- (Int *)ARG3, /* parent_tidptr */
- (Int *)ARG5, /* child_tidptr */
- (Addr)ARG4)); /* child_tls */
- break;
-
- case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */
- /* FALLTHROUGH - assume vfork == fork */
- cloneflags &= ~(VKI_CLONE_VFORK | VKI_CLONE_VM);
-
- case 0: /* plain fork */
- SET_STATUS_from_SysRes(
- ML_(do_fork_clone)(tid,
- cloneflags, /* flags */
- (Int *)ARG3, /* parent_tidptr */
- (Int *)ARG5)); /* child_tidptr */
- break;
-
- default:
- /* should we just ENOSYS? */
- VG_(message)(Vg_UserMsg, "Unsupported clone() flags: 0x%lx\n", ARG1);
- VG_(message)(Vg_UserMsg, "\n");
- VG_(message)(Vg_UserMsg, "The only supported clone() uses are:\n");
- VG_(message)(Vg_UserMsg, " - via a threads library (LinuxThreads or NPTL)\n");
- VG_(message)(Vg_UserMsg, " - via the implementation of fork or vfork\n");
- VG_(unimplemented)
- ("Valgrind does not support general clone().");
- }
-
- if (SUCCESS) {
- if (ARG1 & VKI_CLONE_PARENT_SETTID)
- POST_MEM_WRITE(ARG3, sizeof(Int));
- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID))
- POST_MEM_WRITE(ARG5, sizeof(Int));
-
- /* Thread creation was successful; let the child have the chance
- to run */
- *flags |= SfYieldAfter;
- }
-}
-
PRE(sys_sigreturn)
{
/* See comments on PRE(sys_rt_sigreturn) in syswrap-amd64-linux.c for
@@ -999,7 +757,7 @@
GENX_(__NR_fsync, sys_fsync), // 118
PLAX_(__NR_sigreturn, sys_sigreturn), // 119 ?/Linux
//..
- PLAX_(__NR_clone, sys_clone), // 120
+ LINX_(__NR_clone, sys_clone), // 120
//.. // (__NR_setdomainname, sys_setdomainname), // 121 */*(?)
GENXY(__NR_uname, sys_newuname), // 122
//.. PLAX_(__NR_modify_ldt, sys_modify_ldt), // 123
diff --git a/coregrind/m_syswrap/syswrap-ppc64-linux.c b/coregrind/m_syswrap/syswrap-ppc64-linux.c
index 1ae4454..46bb317 100644
--- a/coregrind/m_syswrap/syswrap-ppc64-linux.c
+++ b/coregrind/m_syswrap/syswrap-ppc64-linux.c
@@ -7,8 +7,8 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Nicholas Nethercote <njn@valgrind.org>
- Copyright (C) 2005-2015 Cerion Armour-Brown <cerion@open-works.co.uk>
+ Copyright (C) 2005-2017 Nicholas Nethercote <njn@valgrind.org>
+ Copyright (C) 2005-2017 Cerion Armour-Brown <cerion@open-works.co.uk>
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -209,14 +209,7 @@
#define __NR_CLONE VG_STRINGIFY(__NR_clone)
#define __NR_EXIT VG_STRINGIFY(__NR_exit)
-extern
-ULong do_syscall_clone_ppc64_linux ( Word (*fn)(void *),
- void* stack,
- Int flags,
- void* arg,
- Int* child_tid,
- Int* parent_tid,
- void/*vki_modify_ldt_t*/ * );
+// See priv_syswrap-linux.h for arg profile.
asm(
#if defined(VGP_ppc64be_linux)
" .align 2\n"
@@ -366,148 +359,6 @@
#undef __NR_CLONE
#undef __NR_EXIT
-// forward declarations
-static void setup_child ( ThreadArchState*, ThreadArchState* );
-
-/*
- When a client clones, we need to keep track of the new thread. This means:
- 1. allocate a ThreadId+ThreadState+stack for the thread
-
- 2. initialize the thread's new VCPU state
-
- 3. create the thread using the same args as the client requested,
- but using the scheduler entrypoint for IP, and a separate stack
- for SP.
- */
-static SysRes do_clone ( ThreadId ptid,
- UInt flags, Addr sp,
- Int *parent_tidptr,
- Int *child_tidptr,
- Addr child_tls)
-{
- const Bool debug = False;
-
- ThreadId ctid = VG_(alloc_ThreadState)();
- ThreadState* ptst = VG_(get_ThreadState)(ptid);
- ThreadState* ctst = VG_(get_ThreadState)(ctid);
- ULong word64;
- UWord* stack;
- SysRes res;
- vki_sigset_t blockall, savedmask;
-
- VG_(sigfillset)(&blockall);
-
- vg_assert(VG_(is_running_thread)(ptid));
- vg_assert(VG_(is_valid_tid)(ctid));
-
- stack = (UWord*)ML_(allocstack)(ctid);
- if (stack == NULL) {
- res = VG_(mk_SysRes_Error)( VKI_ENOMEM );
- goto out;
- }
-
-//? /* make a stack frame */
-//? stack -= 16;
-//? *(UWord *)stack = 0;
-
-
- /* Copy register state
-
- Both parent and child return to the same place, and the code
- following the clone syscall works out which is which, so we
- don't need to worry about it.
-
- The parent gets the child's new tid returned from clone, but the
- child gets 0.
-
- If the clone call specifies a NULL SP for the new thread, then
- it actually gets a copy of the parent's SP.
-
- The child's TLS register (r2) gets set to the tlsaddr argument
- if the CLONE_SETTLS flag is set.
- */
- setup_child( &ctst->arch, &ptst->arch );
-
- /* Make sys_clone appear to have returned Success(0) in the
- child. */
- { UInt old_cr = LibVEX_GuestPPC64_get_CR( &ctst->arch.vex );
- /* %r3 = 0 */
- ctst->arch.vex.guest_GPR3 = 0;
- /* %cr0.so = 0 */
- LibVEX_GuestPPC64_put_CR( old_cr & ~(1<<28), &ctst->arch.vex );
- }
-
- if (sp != 0)
- ctst->arch.vex.guest_GPR1 = sp;
-
- ctst->os_state.parent = ptid;
-
- /* inherit signal mask */
- ctst->sig_mask = ptst->sig_mask;
- ctst->tmp_sig_mask = ptst->sig_mask;
-
- /* Start the child with its threadgroup being the same as the
- parent's. This is so that any exit_group calls that happen
- after the child is created but before it sets its
- os_state.threadgroup field for real (in thread_wrapper in
- syswrap-linux.c), really kill the new thread. a.k.a this avoids
- a race condition in which the thread is unkillable (via
- exit_group) because its threadgroup is not set. The race window
- is probably only a few hundred or a few thousand cycles long.
- See #226116. */
- ctst->os_state.threadgroup = ptst->os_state.threadgroup;
-
- ML_(guess_and_register_stack) (sp, ctst);
-
- /* Assume the clone will succeed, and tell any tool that wants to
- know that this thread has come into existence. If the clone
- fails, we'll send out a ll_exit notification for it at the out:
- label below, to clean up. */
- vg_assert(VG_(owns_BigLock_LL)(ptid));
- VG_TRACK ( pre_thread_ll_create, ptid, ctid );
-
- if (flags & VKI_CLONE_SETTLS) {
- if (debug)
- VG_(printf)("clone child has SETTLS: tls at %#lx\n", child_tls);
- ctst->arch.vex.guest_GPR13 = child_tls;
- }
-
- flags &= ~VKI_CLONE_SETTLS;
-
- /* start the thread with everything blocked */
- VG_(sigprocmask)(VKI_SIG_SETMASK, &blockall, &savedmask);
-
- /* Create the new thread */
- word64 = do_syscall_clone_ppc64_linux(
- ML_(start_thread_NORETURN),
- stack, flags, &VG_(threads)[ctid],
- child_tidptr, parent_tidptr, NULL
- );
-
- /* Low half word64 is syscall return value. Hi half is
- the entire CR, from which we need to extract CR0.SO. */
- /* VG_(printf)("word64 = 0x%llx\n", word64); */
- res = VG_(mk_SysRes_ppc64_linux)(
- /*val*/(UInt)(word64 & 0xFFFFFFFFULL),
- /*errflag*/ (UInt)((word64 >> (32+28)) & 1)
- );
-
- VG_(sigprocmask)(VKI_SIG_SETMASK, &savedmask, NULL);
-
- out:
- if (sr_isError(res)) {
- /* clone failed */
- VG_(cleanup_thread)(&ctst->arch);
- ctst->status = VgTs_Empty;
- /* oops. Better tell the tool the thread exited in a hurry :-) */
- VG_TRACK( pre_thread_ll_exit, ctid );
- }
-
- return res;
-}
-
-
-
/* ---------------------------------------------------------------------
More thread stuff
------------------------------------------------------------------ */
@@ -516,16 +367,6 @@
{
}
-void setup_child ( /*OUT*/ ThreadArchState *child,
- /*IN*/ ThreadArchState *parent )
-{
- /* We inherit our parent's guest state. */
- child->vex = parent->vex;
- child->vex_shadow1 = parent->vex_shadow1;
- child->vex_shadow2 = parent->vex_shadow2;
-}
-
-
/* ---------------------------------------------------------------------
PRE/POST wrappers for ppc64/Linux-specific syscalls
------------------------------------------------------------------ */
@@ -544,7 +385,6 @@
//zz DECL_TEMPLATE(ppc64_linux, sys_stat64);
//zz DECL_TEMPLATE(ppc64_linux, sys_lstat64);
//zz DECL_TEMPLATE(ppc64_linux, sys_fstat64);
-DECL_TEMPLATE(ppc64_linux, sys_clone);
//zz DECL_TEMPLATE(ppc64_linux, sys_sigreturn);
DECL_TEMPLATE(ppc64_linux, sys_rt_sigreturn);
DECL_TEMPLATE(ppc64_linux, sys_fadvise64);
@@ -629,92 +469,6 @@
//zz POST_MEM_WRITE( ARG2, sizeof(struct vki_stat64) );
//zz }
-
-PRE(sys_clone)
-{
- UInt cloneflags;
-
- PRINT("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )",ARG1,ARG2,ARG3,ARG4,ARG5);
- PRE_REG_READ5(int, "clone",
- unsigned long, flags,
- void *, child_stack,
- int *, parent_tidptr,
- void *, child_tls,
- int *, child_tidptr);
-
- if (ARG1 & VKI_CLONE_PARENT_SETTID) {
- PRE_MEM_WRITE("clone(parent_tidptr)", ARG3, sizeof(Int));
- if (!VG_(am_is_valid_for_client)(ARG3, sizeof(Int),
- VKI_PROT_WRITE)) {
- SET_STATUS_Failure( VKI_EFAULT );
- return;
- }
- }
- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) {
- PRE_MEM_WRITE("clone(child_tidptr)", ARG5, sizeof(Int));
- if (!VG_(am_is_valid_for_client)(ARG5, sizeof(Int),
- VKI_PROT_WRITE)) {
- SET_STATUS_Failure( VKI_EFAULT );
- return;
- }
- }
-
- cloneflags = ARG1;
-
- if (!ML_(client_signal_OK)(ARG1 & VKI_CSIGNAL)) {
- SET_STATUS_Failure( VKI_EINVAL );
- return;
- }
-
- /* Only look at the flags we really care about */
- switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS
- | VKI_CLONE_FILES | VKI_CLONE_VFORK)) {
- case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES:
- /* thread creation */
- SET_STATUS_from_SysRes(
- do_clone(tid,
- ARG1, /* flags */
- (Addr)ARG2, /* child SP */
- (Int *)ARG3, /* parent_tidptr */
- (Int *)ARG5, /* child_tidptr */
- (Addr)ARG4)); /* child_tls */
- break;
-
- case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */
- /* FALLTHROUGH - assume vfork == fork */
- cloneflags &= ~(VKI_CLONE_VFORK | VKI_CLONE_VM);
-
- case 0: /* plain fork */
- SET_STATUS_from_SysRes(
- ML_(do_fork_clone)(tid,
- cloneflags, /* flags */
- (Int *)ARG3, /* parent_tidptr */
- (Int *)ARG5)); /* child_tidptr */
- break;
-
- default:
- /* should we just ENOSYS? */
- VG_(message)(Vg_UserMsg, "Unsupported clone() flags: 0x%lx\n", ARG1);
- VG_(message)(Vg_UserMsg, "\n");
- VG_(message)(Vg_UserMsg, "The only supported clone() uses are:\n");
- VG_(message)(Vg_UserMsg, " - via a threads library (LinuxThreads or NPTL)\n");
- VG_(message)(Vg_UserMsg, " - via the implementation of fork or vfork\n");
- VG_(unimplemented)
- ("Valgrind does not support general clone().");
- }
-
- if (SUCCESS) {
- if (ARG1 & VKI_CLONE_PARENT_SETTID)
- POST_MEM_WRITE(ARG3, sizeof(Int));
- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID))
- POST_MEM_WRITE(ARG5, sizeof(Int));
-
- /* Thread creation was successful; let the child have the chance
- to run */
- *flags |= SfYieldAfter;
- }
-}
-
PRE(sys_fadvise64)
{
PRINT("sys_fadvise64 ( %ld, %ld, %lu, %ld )", SARG1, SARG2, SARG3, SARG4);
@@ -922,7 +676,7 @@
GENX_(__NR_fsync, sys_fsync), // 118
// _____(__NR_sigreturn, sys_sigreturn), // 119
- PLAX_(__NR_clone, sys_clone), // 120
+ LINX_(__NR_clone, sys_clone), // 120
// _____(__NR_setdomainname, sys_setdomainname), // 121
GENXY(__NR_uname, sys_newuname), // 122
// _____(__NR_modify_ldt, sys_modify_ldt), // 123
@@ -1151,6 +905,7 @@
LINX_(__NR_pwritev, sys_pwritev), // 321
LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo),// 322
+ LINXY(__NR_prlimit64, sys_prlimit64), // 325
LINXY(__NR_socket, sys_socket), // 326
LINX_(__NR_bind, sys_bind), // 327
LINX_(__NR_connect, sys_connect), // 328
diff --git a/coregrind/m_syswrap/syswrap-s390x-linux.c b/coregrind/m_syswrap/syswrap-s390x-linux.c
index ebb8295..90dcc75 100644
--- a/coregrind/m_syswrap/syswrap-s390x-linux.c
+++ b/coregrind/m_syswrap/syswrap-s390x-linux.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2015
+ Copyright IBM Corp. 2010-2017
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -138,14 +138,7 @@
#define __NR_CLONE VG_STRINGIFY(__NR_clone)
#define __NR_EXIT VG_STRINGIFY(__NR_exit)
-extern
-ULong do_syscall_clone_s390x_linux ( void *stack,
- ULong flags,
- Int *parent_tid,
- Int *child_tid,
- Addr tlsaddr,
- Word (*fn)(void *),
- void *arg);
+// See priv_syswrap-linux.h for arg profile.
asm(
" .text\n"
" .align 4\n"
@@ -182,126 +175,6 @@
/* only used on x86 for descriptor tables */
}
-static void setup_child ( /*OUT*/ ThreadArchState *child,
- /*IN*/ ThreadArchState *parent )
-{
- /* We inherit our parent's guest state. */
- child->vex = parent->vex;
- child->vex_shadow1 = parent->vex_shadow1;
- child->vex_shadow2 = parent->vex_shadow2;
-}
-
-
-/*
- When a client clones, we need to keep track of the new thread. This means:
- 1. allocate a ThreadId+ThreadState+stack for the thread
-
- 2. initialize the thread's new VCPU state
-
- 3. create the thread using the same args as the client requested,
- but using the scheduler entrypoint for IP, and a separate stack
- for SP.
- */
-static SysRes do_clone ( ThreadId ptid,
- Addr sp, ULong flags,
- Int *parent_tidptr,
- Int *child_tidptr,
- Addr tlsaddr)
-{
- static const Bool debug = False;
-
- ThreadId ctid = VG_(alloc_ThreadState)();
- ThreadState* ptst = VG_(get_ThreadState)(ptid);
- ThreadState* ctst = VG_(get_ThreadState)(ctid);
- UWord* stack;
- SysRes res;
- ULong r2;
- vki_sigset_t blockall, savedmask;
-
- VG_(sigfillset)(&blockall);
-
- vg_assert(VG_(is_running_thread)(ptid));
- vg_assert(VG_(is_valid_tid)(ctid));
-
- stack = (UWord*)ML_(allocstack)(ctid);
- if (stack == NULL) {
- res = VG_(mk_SysRes_Error)( VKI_ENOMEM );
- goto out;
- }
-
- /* Copy register state
-
- Both parent and child return to the same place, and the code
- following the clone syscall works out which is which, so we
- don't need to worry about it.
-
- The parent gets the child's new tid returned from clone, but the
- child gets 0.
-
- If the clone call specifies a NULL sp for the new thread, then
- it actually gets a copy of the parent's sp.
- */
- setup_child( &ctst->arch, &ptst->arch );
-
- /* Make sys_clone appear to have returned Success(0) in the
- child. */
- ctst->arch.vex.guest_r2 = 0;
-
- if (sp != 0)
- ctst->arch.vex.guest_SP = sp;
-
- ctst->os_state.parent = ptid;
-
- /* inherit signal mask */
- ctst->sig_mask = ptst->sig_mask;
- ctst->tmp_sig_mask = ptst->sig_mask;
-
- /* have the parents thread group */
- ctst->os_state.threadgroup = ptst->os_state.threadgroup;
-
- ML_(guess_and_register_stack) (sp, ctst);
-
- /* Assume the clone will succeed, and tell any tool that wants to
- know that this thread has come into existence. If the clone
- fails, we'll send out a ll_exit notification for it at the out:
- label below, to clean up. */
- vg_assert(VG_(owns_BigLock_LL)(ptid));
- VG_TRACK ( pre_thread_ll_create, ptid, ctid );
-
- if (flags & VKI_CLONE_SETTLS) {
- if (debug)
- VG_(printf)("clone child has SETTLS: tls at %#lx\n", tlsaddr);
- ctst->arch.vex.guest_a0 = (UInt) (tlsaddr >> 32);
- ctst->arch.vex.guest_a1 = (UInt) tlsaddr;
- }
- flags &= ~VKI_CLONE_SETTLS;
-
- /* start the thread with everything blocked */
- VG_(sigprocmask)(VKI_SIG_SETMASK, &blockall, &savedmask);
-
- /* Create the new thread */
- r2 = do_syscall_clone_s390x_linux(
- stack, flags, parent_tidptr, child_tidptr, tlsaddr,
- ML_(start_thread_NORETURN), &VG_(threads)[ctid]);
-
- res = VG_(mk_SysRes_s390x_linux)( r2 );
-
- VG_(sigprocmask)(VKI_SIG_SETMASK, &savedmask, NULL);
-
- out:
- if (sr_isError(res)) {
- /* clone failed */
- ctst->status = VgTs_Empty;
- /* oops. Better tell the tool the thread exited in a hurry :-) */
- VG_TRACK( pre_thread_ll_exit, ctid );
- }
-
- return res;
-
-}
-
-
-
/* ---------------------------------------------------------------------
PRE/POST wrappers for s390x/Linux-specific syscalls
------------------------------------------------------------------ */
@@ -317,7 +190,6 @@
DECL_TEMPLATE(s390x_linux, sys_ptrace);
DECL_TEMPLATE(s390x_linux, sys_mmap);
-DECL_TEMPLATE(s390x_linux, sys_clone);
DECL_TEMPLATE(s390x_linux, sys_sigreturn);
DECL_TEMPLATE(s390x_linux, sys_rt_sigreturn);
DECL_TEMPLATE(s390x_linux, sys_fadvise64);
@@ -399,6 +271,9 @@
POST(sys_ptrace)
{
switch (ARG1) {
+ case VKI_PTRACE_TRACEME:
+ ML_(linux_POST_traceme)(tid);
+ break;
case VKI_PTRACE_PEEKTEXT:
case VKI_PTRACE_PEEKDATA:
case VKI_PTRACE_PEEKUSR:
@@ -452,99 +327,6 @@
SET_STATUS_from_SysRes(r);
}
-PRE(sys_clone)
-{
- UInt cloneflags;
-
- PRINT("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )",ARG1,ARG2,ARG3,ARG4, ARG5);
- PRE_REG_READ2(int, "clone",
- void *, child_stack,
- unsigned long, flags);
-
- if (ARG2 & VKI_CLONE_PARENT_SETTID) {
- if (VG_(tdict).track_pre_reg_read)
- PRA3("clone(parent_tidptr)", int *, parent_tidptr);
- PRE_MEM_WRITE("clone(parent_tidptr)", ARG3, sizeof(Int));
- if (!VG_(am_is_valid_for_client)(ARG3, sizeof(Int),
- VKI_PROT_WRITE)) {
- SET_STATUS_Failure( VKI_EFAULT );
- return;
- }
- }
- if (ARG2 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) {
- if (VG_(tdict).track_pre_reg_read)
- PRA4("clone(child_tidptr)", int *, child_tidptr);
- PRE_MEM_WRITE("clone(child_tidptr)", ARG4, sizeof(Int));
- if (!VG_(am_is_valid_for_client)(ARG4, sizeof(Int),
- VKI_PROT_WRITE)) {
- SET_STATUS_Failure( VKI_EFAULT );
- return;
- }
- }
-
- /* The kernel simply copies reg6 (ARG5) into AR0 and AR1, no checks */
- if (ARG2 & VKI_CLONE_SETTLS) {
- if (VG_(tdict).track_pre_reg_read) {
- PRA5("clone", Addr, tlsinfo);
- }
- }
-
- cloneflags = ARG2;
-
- if (!ML_(client_signal_OK)(ARG2 & VKI_CSIGNAL)) {
- SET_STATUS_Failure( VKI_EINVAL );
- return;
- }
-
- /* Only look at the flags we really care about */
- switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS
- | VKI_CLONE_FILES | VKI_CLONE_VFORK)) {
- case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES:
- /* thread creation */
- SET_STATUS_from_SysRes(
- do_clone(tid,
- (Addr)ARG1, /* child SP */
- ARG2, /* flags */
- (Int *)ARG3, /* parent_tidptr */
- (Int *)ARG4, /* child_tidptr */
- (Addr)ARG5)); /* tlsaddr */
- break;
-
- case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */
- /* FALLTHROUGH - assume vfork == fork */
- cloneflags &= ~(VKI_CLONE_VFORK | VKI_CLONE_VM);
-
- case 0: /* plain fork */
- SET_STATUS_from_SysRes(
- ML_(do_fork_clone)(tid,
- cloneflags, /* flags */
- (Int *)ARG3, /* parent_tidptr */
- (Int *)ARG4)); /* child_tidptr */
- break;
-
- default:
- /* should we just ENOSYS? */
- VG_(message)(Vg_UserMsg, "Unsupported clone() flags: 0x%lx\n", ARG2);
- VG_(message)(Vg_UserMsg, "\n");
- VG_(message)(Vg_UserMsg, "The only supported clone() uses are:\n");
- VG_(message)(Vg_UserMsg, " - via a threads library (NPTL)\n");
- VG_(message)(Vg_UserMsg, " - via the implementation of fork or vfork\n");
- VG_(unimplemented)
- ("Valgrind does not support general clone().");
- }
-
- if (SUCCESS) {
- if (ARG2 & VKI_CLONE_PARENT_SETTID)
- POST_MEM_WRITE(ARG3, sizeof(Int));
- if (ARG2 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID))
- POST_MEM_WRITE(ARG4, sizeof(Int));
-
- /* Thread creation was successful; let the child have the chance
- to run */
- *flags |= SfYieldAfter;
- }
-}
-
PRE(sys_sigreturn)
{
ThreadState* tst;
@@ -775,7 +557,7 @@
GENX_(__NR_fsync, sys_fsync), // 118
PLAX_(__NR_sigreturn, sys_sigreturn), // 119
- PLAX_(__NR_clone, sys_clone), // 120
+ LINX_(__NR_clone, sys_clone), // 120
// ?????(__NR_setdomainname, ), // 121
GENXY(__NR_uname, sys_newuname), // 122
GENX_(123, sys_ni_syscall), /* unimplemented (by the kernel) */ // 123
diff --git a/coregrind/m_syswrap/syswrap-solaris.c b/coregrind/m_syswrap/syswrap-solaris.c
index 64aeb82..22a7501 100644
--- a/coregrind/m_syswrap/syswrap-solaris.c
+++ b/coregrind/m_syswrap/syswrap-solaris.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2015 Petr Pavlu
+ Copyright (C) 2011-2017 Petr Pavlu
setup@dagobah.cz
This program is free software; you can redistribute it and/or
@@ -28,9 +28,9 @@
The GNU General Public License is contained in the file COPYING.
*/
-/* Copyright 2013-2016, Ivo Raisr <ivosh@ivosh.net>. */
+/* Copyright 2013-2017, Ivo Raisr <ivosh@ivosh.net>. */
-/* Copyright 2015-2015, Tomas Jedlicka <jedlickat@gmail.com>. */
+/* Copyright 2015-2017, Tomas Jedlicka <jedlickat@gmail.com>. */
/* Copyright 2013, OmniTI Computer Consulting, Inc. All rights reserved. */
@@ -195,7 +195,7 @@
VG_TRACK(die_mem_munmap, a, sizeof(struct vki_sc_shared));
/* Deregister thread's stack. */
- if (tst->os_state.stk_id != (UWord)-1)
+ if (tst->os_state.stk_id != NULL_STK_ID)
VG_(deregister_stack)(tst->os_state.stk_id);
/* Tell the tool this thread is exiting. */
@@ -708,14 +708,13 @@
new_start = new_end + 1 - new_size;
}
- if (tst->os_state.stk_id == (UWord)-1) {
+ if (tst->os_state.stk_id == NULL_STK_ID) {
/* This thread doesn't have a stack set yet. */
VG_(debugLog)(2, "syswrap-solaris",
"Stack set to %#lx-%#lx (new) for thread %u.\n",
new_start, new_end, tid);
tst->os_state.stk_id = VG_(register_stack)(new_start, new_end);
- }
- else {
+ } else {
/* Change a thread stack. */
VG_(debugLog)(2, "syswrap-solaris",
"Stack set to %#lx-%#lx (change) for thread %u.\n",
@@ -956,6 +955,7 @@
DECL_TEMPLATE(solaris, sys_putmsg);
DECL_TEMPLATE(solaris, sys_lstat);
DECL_TEMPLATE(solaris, sys_sigprocmask);
+DECL_TEMPLATE(solaris, sys_sigsuspend);
DECL_TEMPLATE(solaris, sys_sigaction);
DECL_TEMPLATE(solaris, sys_sigpending);
DECL_TEMPLATE(solaris, sys_getsetcontext);
@@ -965,6 +965,7 @@
DECL_TEMPLATE(solaris, sys_fstatvfs);
DECL_TEMPLATE(solaris, sys_nfssys);
DECL_TEMPLATE(solaris, sys_waitid);
+DECL_TEMPLATE(solaris, sys_sigsendsys);
#if defined(SOLARIS_UTIMESYS_SYSCALL)
DECL_TEMPLATE(solaris, sys_utimesys);
#endif /* SOLARIS_UTIMESYS_SYSCALL */
@@ -1024,6 +1025,7 @@
DECL_TEMPLATE(solaris, sys_lwp_cond_broadcast);
DECL_TEMPLATE(solaris, sys_pread);
DECL_TEMPLATE(solaris, sys_pwrite);
+DECL_TEMPLATE(solaris, sys_lgrpsys);
DECL_TEMPLATE(solaris, sys_rusagesys);
DECL_TEMPLATE(solaris, sys_port);
DECL_TEMPLATE(solaris, sys_pollsys);
@@ -1074,6 +1076,7 @@
DECL_TEMPLATE(solaris, fast_gethrtime);
DECL_TEMPLATE(solaris, fast_gethrvtime);
DECL_TEMPLATE(solaris, fast_gethrestime);
+DECL_TEMPLATE(solaris, fast_getlgrp);
#if defined(SOLARIS_GETHRT_FASTTRAP)
DECL_TEMPLATE(solaris, fast_gethrt);
#endif /* SOLARIS_GETHRT_FASTTRAP */
@@ -1963,6 +1966,24 @@
VG_TRACK(die_mem_brk, VG_(brk_base), seg->end + 1 - VG_(brk_base));
}
+static void PRINTF_CHECK(1, 2)
+possibly_complain_brk(const HChar *format, ...)
+{
+ static Bool alreadyComplained = False;
+ if (!alreadyComplained) {
+ alreadyComplained = True;
+ if (VG_(clo_verbosity) > 0) {
+ va_list vargs;
+ va_start(vargs, format);
+ VG_(vmessage)(Vg_UserMsg, format, vargs);
+ va_end(vargs);
+ VG_(umsg)("(See section Limitations in the user manual.)\n");
+ VG_(umsg)("NOTE: further instances of this message will not be "
+ "shown.\n");
+ }
+ }
+}
+
PRE(sys_brk)
{
/* unsigned long brk(caddr_t end_data_segment); */
@@ -2010,8 +2031,8 @@
vg_assert(VG_(brk_base) == VG_(brk_limit));
if (!VG_(setup_client_dataseg)()) {
- VG_(umsg)("Cannot map memory to initialize brk segment in thread #%d "
- "at %#lx\n", tid, VG_(brk_base));
+ possibly_complain_brk("Cannot map memory to initialize brk segment in "
+ "thread #%d at %#lx\n", tid, VG_(brk_base));
SET_STATUS_Failure(VKI_ENOMEM);
return;
}
@@ -2153,8 +2174,8 @@
Bool ok = VG_(am_create_reservation)(resvn_start, resvn_size, SmLower,
anon_size);
if (!ok) {
- VG_(umsg)("brk segment overflow in thread #%d: can't grow "
- "to %#lx\n", tid, new_brk);
+ possibly_complain_brk("brk segment overflow in thread #%d: can not "
+ "grow to %#lx\n", tid, new_brk);
SET_STATUS_Failure(VKI_ENOMEM);
return;
}
@@ -2167,8 +2188,8 @@
/* Address space manager will merge old and new data segments. */
sres = VG_(am_mmap_anon_fixed_client)(anon_start, anon_size, prot);
if (sr_isError(sres)) {
- VG_(umsg)("Cannot map memory to grow brk segment in thread #%d "
- "to %#lx\n", tid, new_brk);
+ possibly_complain_brk("Cannot map memory to grow brk segment in "
+ "thread #%d to %#lx\n", tid, new_brk);
SET_STATUS_Failure(VKI_ENOMEM);
return;
}
@@ -3938,6 +3959,7 @@
/* These ones use ARG3 as "arg". */
case VKI_F_DUPFD:
+ case VKI_F_DUPFD_CLOEXEC:
case VKI_F_SETFD:
case VKI_F_SETFL:
case VKI_F_DUP2FD:
@@ -4032,8 +4054,15 @@
if (!ML_(fd_allowed)(RES, "fcntl(F_DUPFD)", tid, True)) {
VG_(close)(RES);
SET_STATUS_Failure(VKI_EMFILE);
- }
- else if (VG_(clo_track_fds))
+ } else if (VG_(clo_track_fds))
+ ML_(record_fd_open_named)(tid, RES);
+ break;
+
+ case VKI_F_DUPFD_CLOEXEC:
+ if (!ML_(fd_allowed)(RES, "fcntl(F_DUPFD_CLOEXEC)", tid, True)) {
+ VG_(close)(RES);
+ SET_STATUS_Failure(VKI_EMFILE);
+ } else if (VG_(clo_track_fds))
ML_(record_fd_open_named)(tid, RES);
break;
@@ -4041,8 +4070,7 @@
if (!ML_(fd_allowed)(RES, "fcntl(F_DUP2FD)", tid, True)) {
VG_(close)(RES);
SET_STATUS_Failure(VKI_EMFILE);
- }
- else if (VG_(clo_track_fds))
+ } else if (VG_(clo_track_fds))
ML_(record_fd_open_named)(tid, RES);
break;
@@ -4800,6 +4828,26 @@
POST_MEM_WRITE(ARG3, sizeof(vki_sigset_t));
}
+PRE(sys_sigsuspend)
+{
+ *flags |= SfMayBlock;
+
+ /* int sigsuspend(const sigset_t *set); */
+ PRINT("sys_sigsuspend ( %#lx )", ARG1);
+ PRE_REG_READ1(long, "sigsuspend", vki_sigset_t *, set);
+ PRE_MEM_READ("sigsuspend(set)", ARG1, sizeof(vki_sigset_t));
+
+ /* Be safe. */
+ if (ARG1 && ML_(safe_to_deref((void *) ARG1, sizeof(vki_sigset_t)))) {
+ VG_(sigdelset)((vki_sigset_t *) ARG1, VG_SIGVGKILL);
+ /* We cannot mask VG_SIGVGKILL, as otherwise this thread would not
+ be killable by VG_(nuke_all_threads_except).
+ We thus silently ignore the user request to mask this signal.
+ Note that this is similar to what is done for e.g.
+ sigprocmask (see m_signals.c calculate_SKSS_from_SCSS). */
+ }
+}
+
PRE(sys_sigaction)
{
/* int sigaction(int signal, const struct sigaction *act,
@@ -5102,6 +5150,57 @@
POST_MEM_WRITE(ARG3, sizeof(vki_siginfo_t));
}
+PRE(sys_sigsendsys)
+{
+ /* int sigsendsys(procset_t *psp, int sig); */
+ PRINT("sys_sigsendsys( %#lx, %ld )", ARG1, SARG2);
+ PRE_REG_READ2(long, "sigsendsys", vki_procset_t *, psp, int, signal);
+ PRE_MEM_READ("sigsendsys(psp)", ARG1, sizeof(vki_procset_t));
+
+ if (!ML_(client_signal_OK)(ARG1)) {
+ SET_STATUS_Failure(VKI_EINVAL);
+ }
+ if (!ML_(safe_to_deref)((void *) ARG1, sizeof(vki_procset_t))) {
+ SET_STATUS_Failure(VKI_EFAULT);
+ }
+
+ /* Exit early if there are problems. */
+ if (FAILURE)
+ return;
+
+ vki_procset_t *psp = (vki_procset_t *) ARG1;
+ switch (psp->p_op) {
+ case VKI_POP_AND:
+ break;
+ default:
+ VG_(unimplemented)("Syswrap of the sigsendsys call with op %u.",
+ psp->p_op);
+ }
+
+ UInt pid;
+ if ((psp->p_lidtype == VKI_P_PID) && (psp->p_ridtype == VKI_P_ALL)) {
+ pid = psp->p_lid;
+ } else if ((psp->p_lidtype == VKI_P_ALL) && (psp->p_ridtype == VKI_P_PID)) {
+ pid = psp->p_rid;
+ } else {
+ VG_(unimplemented)("Syswrap of the sigsendsys call with lidtype %u and"
+ "ridtype %u.", psp->p_lidtype, psp->p_ridtype);
+ }
+
+ if (VG_(clo_trace_signals))
+ VG_(message)(Vg_DebugMsg, "sigsendsys: sending signal to process %d\n",
+ pid);
+
+ /* Handle SIGKILL specially. */
+ if (ARG2 == VKI_SIGKILL && ML_(do_sigkill)(pid, -1)) {
+ SET_STATUS_Success(0);
+ return;
+ }
+
+ /* Check to see if this gave us a pending signal. */
+ *flags |= SfPollAfter;
+}
+
#if defined(SOLARIS_UTIMESYS_SYSCALL)
PRE(sys_utimesys)
{
@@ -5220,7 +5319,7 @@
ARG4 = ARG3;
/* Fake the requested sigmask with a block-all mask. If the syscall
- suceeds then we will block "all" signals for a few instructions (in
+ succeeds then we will block "all" signals for a few instructions (in
syscall-x86-solaris.S) but the correct mask will be almost instantly set
again by a call to sigprocmask (also in syscall-x86-solaris.S). If the
syscall fails then the mask is not changed, so everything is ok too. */
@@ -6545,17 +6644,6 @@
if (RESHI) {
VG_(do_atfork_child)(tid);
- /* If --child-silent-after-fork=yes was specified, set the output file
- descriptors to 'impossible' values. This is noticed by
- send_bytes_to_logging_sink() in m_libcprint.c, which duly stops
- writing any further output. */
- if (VG_(clo_child_silent_after_fork)) {
- if (!VG_(log_output_sink).is_socket)
- VG_(log_output_sink).fd = -1;
- if (!VG_(xml_output_sink).is_socket)
- VG_(xml_output_sink).fd = -1;
- }
-
/* vfork */
if (ARG1 == 2)
VG_(close)(fds[1]);
@@ -6957,7 +7045,7 @@
later by libc by a setustack() call (the getsetcontext syscall). */
ctst->client_stack_highest_byte = 0;
ctst->client_stack_szB = 0;
- vg_assert(ctst->os_state.stk_id == (UWord)(-1));
+ vg_assert(ctst->os_state.stk_id == NULL_STK_ID);
/* Inform a tool that a new thread is created. This has to be done before
any other core->tool event is sent. */
@@ -7426,6 +7514,78 @@
POST_MEM_WRITE(ARG2, RES * sizeof(vki_size_t));
}
+PRE(sys_lgrpsys)
+{
+ /* Kernel: int lgrpsys(int subcode, long ia, void *ap); */
+ switch (ARG1 /*subcode*/) {
+ case VKI_LGRP_SYS_MEMINFO:
+ PRINT("sys_lgrpsys ( %ld, %ld, %#lx )", SARG1, SARG2, ARG3);
+ PRE_REG_READ3(long, SC2("lgrpsys", "meminfo"), int, subcode,
+ int, addr_count, vki_meminfo_t *, minfo);
+ PRE_MEM_READ("lgrpsys(minfo)", ARG3, sizeof(vki_meminfo_t));
+
+ if (ML_(safe_to_deref)((vki_meminfo_t *) ARG3, sizeof(vki_meminfo_t))) {
+ vki_meminfo_t *minfo = (vki_meminfo_t *) ARG3;
+ PRE_MEM_READ("lgrpsys(minfo->mi_inaddr)",
+ (Addr) minfo->mi_inaddr, SARG2 * sizeof(vki_uint64_t));
+ PRE_MEM_READ("lgrpsys(minfo->mi_info_req)", (Addr) minfo->mi_info_req,
+ minfo->mi_info_count * sizeof(vki_uint_t));
+ PRE_MEM_WRITE("lgrpsys(minfo->mi_outdata)", (Addr) minfo->mi_outdata,
+ SARG2 * minfo->mi_info_count * sizeof(vki_uint64_t));
+ PRE_MEM_WRITE("lgrpsys(minfo->mi_validity)",
+ (Addr) minfo->mi_validity, SARG2 * sizeof(vki_uint_t));
+ }
+ break;
+ case VKI_LGRP_SYS_GENERATION:
+ /* Liblgrp: lgrp_gen_t lgrp_generation(lgrp_view_t view); */
+ PRINT("sys_lgrpsys ( %ld, %ld )", SARG1, SARG2);
+ PRE_REG_READ2(long, SC2("lgrpsys", "generation"), int, subcode,
+ vki_lgrp_view_t, view);
+ break;
+ case VKI_LGRP_SYS_VERSION:
+ /* Liblgrp: int lgrp_version(int version); */
+ PRINT("sys_lgrpsys ( %ld, %ld )", SARG1, SARG2);
+ PRE_REG_READ2(long, SC2("lgrpsys", "version"), int, subcode,
+ int, version);
+ break;
+ case VKI_LGRP_SYS_SNAPSHOT:
+ /* Liblgrp: int lgrp_snapshot(void *buf, size_t bufsize); */
+ PRINT("sys_lgrpsys ( %ld, %lu, %#lx )", SARG1, ARG2, ARG3);
+ PRE_REG_READ3(long, SC2("lgrpsys", "snapshot"), int, subcode,
+ vki_size_t, bufsize, void *, buf);
+ PRE_MEM_WRITE("lgrpsys(buf)", ARG3, ARG2);
+ break;
+ default:
+ VG_(unimplemented)("Syswrap of the lgrpsys call with subcode %ld.",
+ SARG1);
+ /*NOTREACHED*/
+ break;
+ }
+}
+
+POST(sys_lgrpsys)
+{
+ switch (ARG1 /*subcode*/) {
+ case VKI_LGRP_SYS_MEMINFO:
+ {
+ vki_meminfo_t *minfo = (vki_meminfo_t *) ARG3;
+ POST_MEM_WRITE((Addr) minfo->mi_outdata,
+ SARG2 * minfo->mi_info_count * sizeof(vki_uint64_t));
+ POST_MEM_WRITE((Addr) minfo->mi_validity, SARG2 * sizeof(vki_uint_t));
+ }
+ break;
+ case VKI_LGRP_SYS_GENERATION:
+ case VKI_LGRP_SYS_VERSION:
+ break;
+ case VKI_LGRP_SYS_SNAPSHOT:
+ POST_MEM_WRITE(ARG3, RES);
+ break;
+ default:
+ vg_assert(0);
+ break;
+ }
+}
+
PRE(sys_rusagesys)
{
/* Kernel: int rusagesys(int code, void *arg1, void *arg2,
@@ -7486,7 +7646,6 @@
vg_assert(0);
break;
}
-
}
PRE(sys_port)
@@ -8269,8 +8428,8 @@
if (VG_(clo_trace_signals))
VG_(message)(Vg_DebugMsg,
- "sigqueue: signal %lu queued for pid %lu\n",
- ARG2, ARG1);
+ "sigqueue: signal %ld queued for pid %ld\n",
+ SARG2, SARG1);
/* Check to see if this gave us a pending signal. */
*flags |= SfPollAfter;
@@ -10534,6 +10693,13 @@
PRE_REG_READ0(long, "gethrestime");
}
+PRE(fast_getlgrp)
+{
+ /* Fasttrap number shared between gethomelgroup() and getcpuid(). */
+ PRINT("fast_getlgrp ( )");
+ PRE_REG_READ0(long, "getlgrp");
+}
+
#if defined(SOLARIS_GETHRT_FASTTRAP)
PRE(fast_gethrt)
{
@@ -10710,6 +10876,7 @@
GENX_(__NR_fchown, sys_fchown), /* 94 */
#endif /* SOLARIS_OLD_SYSCALLS */
SOLXY(__NR_sigprocmask, sys_sigprocmask), /* 95 */
+ SOLX_(__NR_sigsuspend, sys_sigsuspend), /* 96 */
GENXY(__NR_sigaltstack, sys_sigaltstack), /* 97 */
SOLXY(__NR_sigaction, sys_sigaction), /* 98 */
SOLXY(__NR_sigpending, sys_sigpending), /* 99 */
@@ -10720,6 +10887,7 @@
SOLXY(__NR_fstatvfs, sys_fstatvfs), /* 104 */
SOLXY(__NR_nfssys, sys_nfssys), /* 106 */
SOLXY(__NR_waitid, sys_waitid), /* 107 */
+ SOLX_(__NR_sigsendsys, sys_sigsendsys), /* 108 */
#if defined(SOLARIS_UTIMESYS_SYSCALL)
SOLX_(__NR_utimesys, sys_utimesys), /* 110 */
#endif /* SOLARIS_UTIMESYS_SYSCALL */
@@ -10794,6 +10962,7 @@
#if defined(VGP_x86_solaris)
PLAX_(__NR_llseek, sys_llseek32), /* 175 */
#endif /* VGP_x86_solaris */
+ SOLXY(__NR_lgrpsys, sys_lgrpsys), /* 180 */
SOLXY(__NR_rusagesys, sys_rusagesys), /* 181 */
SOLXY(__NR_port, sys_port), /* 182 */
SOLXY(__NR_pollsys, sys_pollsys), /* 183 */
@@ -10802,7 +10971,7 @@
SOLXY(__NR_auditsys, sys_auditsys), /* 186 */
SOLX_(__NR_p_online, sys_p_online), /* 189 */
SOLX_(__NR_sigqueue, sys_sigqueue), /* 190 */
- SOLX_(__NR_clock_gettime, sys_clock_gettime), /* 191 */
+ SOLXY(__NR_clock_gettime, sys_clock_gettime), /* 191 */
SOLX_(__NR_clock_settime, sys_clock_settime), /* 192 */
SOLXY(__NR_clock_getres, sys_clock_getres), /* 193 */
SOLXY(__NR_timer_create, sys_timer_create), /* 194 */
@@ -10868,7 +11037,8 @@
static SyscallTableEntry fasttrap_table[] = {
SOLX_(__NR_gethrtime, fast_gethrtime), /* 3 */
SOLX_(__NR_gethrvtime, fast_gethrvtime), /* 4 */
- SOLX_(__NR_gethrestime, fast_gethrestime) /* 5 */
+ SOLX_(__NR_gethrestime, fast_gethrestime), /* 5 */
+ SOLX_(__NR_getlgrp, fast_getlgrp) /* 6 */
#if defined(SOLARIS_GETHRT_FASTTRAP)
,
SOLXY(__NR_gethrt, fast_gethrt) /* 7 */
diff --git a/coregrind/m_syswrap/syswrap-tilegx-linux.c b/coregrind/m_syswrap/syswrap-tilegx-linux.c
deleted file mode 100644
index 4845f79..0000000
--- a/coregrind/m_syswrap/syswrap-tilegx-linux.c
+++ /dev/null
@@ -1,1396 +0,0 @@
-
-/*--------------------------------------------------------------------*/
-/*--- Platform-specific syscalls stuff. syswrap-tilegx-linux.c ----*/
-/*--------------------------------------------------------------------*/
-
-/*
- This file is part of Valgrind, a dynamic binary instrumentation
- framework.
-
- Copyright (C) 2010-2015 Tilera Corp.
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of the
- License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful, but
- WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
- 02111-1307, USA.
-
- The GNU General Public License is contained in the file COPYING.
-*/
-
-/* Contributed by Zhi-Gang Liu */
-
-#if defined(VGP_tilegx_linux)
-#include "pub_core_basics.h"
-#include "pub_core_vki.h"
-#include "pub_core_vkiscnums.h"
-#include "pub_core_threadstate.h"
-#include "pub_core_aspacemgr.h"
-#include "pub_core_debuglog.h"
-#include "pub_core_libcbase.h"
-#include "pub_core_libcassert.h"
-#include "pub_core_libcprint.h"
-#include "pub_core_libcproc.h"
-#include "pub_core_libcsignal.h"
-#include "pub_core_options.h"
-#include "pub_core_scheduler.h"
-#include "pub_core_sigframe.h" // For VG_(sigframe_destroy)()
-#include "pub_core_signals.h"
-#include "pub_core_syscall.h"
-#include "pub_core_syswrap.h"
-#include "pub_core_tooliface.h"
-#include "pub_core_stacks.h" // VG_(register_stack)
-#include "pub_core_transtab.h" // VG_(discard_translations)
-#include "priv_types_n_macros.h"
-#include "priv_syswrap-generic.h" /* for decls of generic wrappers */
-#include "priv_syswrap-linux.h" /* for decls of linux wrappers */
-#include "priv_syswrap-main.h"
-
-#include "pub_core_debuginfo.h" // VG_(di_notify_*)
-#include "pub_core_xarray.h"
-#include "pub_core_clientstate.h" // VG_(brk_base), VG_(brk_limit)
-#include "pub_core_errormgr.h"
-#include "pub_core_libcfile.h"
-#include "pub_core_machine.h" // VG_(get_SP)
-#include "pub_core_mallocfree.h"
-#include "pub_core_stacktrace.h" // For VG_(get_and_pp_StackTrace)()
-#include "pub_core_ume.h"
-
-#include "config.h"
-
-/* ---------------------------------------------------------------------
- clone() handling
- ------------------------------------------------------------------ */
-/* Call f(arg1), but first switch stacks, using 'stack' as the new
- stack, and use 'retaddr' as f's return-to address. Also, clear all
- the integer registers before entering f.*/
-
-__attribute__ ((noreturn))
-void ML_(call_on_new_stack_0_1) (Addr stack, Addr retaddr,
- void (*f) (Word), Word arg1);
- // r0 = stack
- // r1 = retaddr
- // r2 = f
- // r3 = arg1
- asm (
- ".text\n"
- ".globl vgModuleLocal_call_on_new_stack_0_1\n"
- "vgModuleLocal_call_on_new_stack_0_1:\n"
- " {\n"
- " move sp, r0\n\t"
- " move r51, r2\n\t"
- " }\n"
- " {\n"
- " move r0, r3\n\t"
- " move r1, zero\n\t"
- " }\n"
- " {\n"
- " move r2, zero\n\t"
- " move r3, zero\n\t"
- " }\n"
- " {\n"
- " move r4, zero\n\t"
- " move r5, zero\n\t"
- " }\n"
- " {\n"
- " move r6, zero\n\t"
- " move r7, zero\n\t"
- " }\n"
- " {\n"
- " move r8, zero\n\t"
- " move r9, zero\n\t"
- " }\n"
- " {\n"
- " move r10, zero\n\t"
- " move r11, zero\n\t"
- " }\n"
- " {\n"
- " move r12, zero\n\t"
- " move r13, zero\n\t"
- " }\n"
- " {\n"
- " move r14, zero\n\t"
- " move r15, zero\n\t"
- " }\n"
- " {\n"
- " move r16, zero\n\t"
- " move r17, zero\n\t"
- " }\n"
- " {\n"
- " move r18, zero\n\t"
- " move r19, zero\n\t"
- " }\n"
- " {\n"
- " move r20, zero\n\t"
- " move r21, zero\n\t"
- " }\n"
- " {\n"
- " move r22, zero\n\t"
- " move r23, zero\n\t"
- " }\n"
- " {\n"
- " move r24, zero\n\t"
- " move r25, zero\n\t"
- " }\n"
- " {\n"
- " move r26, zero\n\t"
- " move r27, zero\n\t"
- " }\n"
- " {\n"
- " move r28, zero\n\t"
- " move r29, zero\n\t"
- " }\n"
- " {\n"
- " move r30, zero\n\t"
- " move r31, zero\n\t"
- " }\n"
- " {\n"
- " move r32, zero\n\t"
- " move r33, zero\n\t"
- " }\n"
- " {\n"
- " move r34, zero\n\t"
- " move r35, zero\n\t"
- " }\n"
- " {\n"
- " move r36, zero\n\t"
- " move r37, zero\n\t"
- " }\n"
- " {\n"
- " move r38, zero\n\t"
- " move r39, zero\n\t"
- " }\n"
- " {\n"
- " move r40, zero\n\t"
- " move r41, zero\n\t"
- " }\n"
- " {\n"
- " move r42, zero\n\t"
- " move r43, zero\n\t"
- " }\n"
- " {\n"
- " move r44, zero\n\t"
- " move r45, zero\n\t"
- " }\n"
- " {\n"
- " move r46, zero\n\t"
- " move r47, zero\n\t"
- " }\n"
- " {\n"
- " move r48, zero\n\t"
- " move r49, zero\n\t"
- " }\n"
- " {\n"
- " move r50, zero\n\t"
- " jr r51\n\t"
- " }\n"
- " ill \n" // should never get here
- );
-/*
- Perform a clone system call. clone is strange because it has
- fork()-like return-twice semantics, so it needs special
- handling here.
- Upon entry, we have:
- int (fn)(void*) in r0
- void* child_stack in r1
- int flags in r2
- void* arg in r3
- pid_t* child_tid in r4
- pid_t* parent_tid in r5
- void* tls_ptr in r6
-
- System call requires:
- int $__NR_clone in r10
- int flags in r0
- void* child_stack in r1
- pid_t* parent_tid in r2
- void* tls_ptr in $r3
- pid_t* child_tid in sr4
-
- int clone(int (*fn)(void *arg), void *child_stack, int flags, void *arg,
- void *parent_tidptr, void *tls, void *child_tidptr)
-
- Returns an Int encoded in the linux-tilegx way, not a SysRes.
-*/
-#define __NR_CLONE VG_STRINGIFY(__NR_clone)
-#define __NR_EXIT VG_STRINGIFY(__NR_exit)
-
-Long do_syscall_clone_tilegx_linux ( Word (*fn) (void *), //r0
- void *stack, //r1
- Long flags, //r2
- void *arg, //r3
- Long * child_tid, //r4
- Long * parent_tid, //r5
- Long tls ); //r6
- /*
- stack
- high -> 4 r29
- 3
- 2
- 1 r10
- low -> 0 lr <- sp
- */
- asm (
- ".text\n"
- " .globl do_syscall_clone_tilegx_linux\n"
- " do_syscall_clone_tilegx_linux:\n"
- " beqz r0, .Linvalid\n"
- " beqz r1, .Linvalid\n"
- " {\n"
- " st sp, r29; " // save r29 at top
- " addli sp, sp, -32\n" // open new stack space
- " }\n"
-
- " move r29, sp; " // r29 <- sp
- " st r29, lr\n" // save lr at 0(sp)
-
- " addi r29, r29, 8\n"
- " {\n"
- " st r29, r10\n" // save r10 at 8(sp)
- /* setup child stack */
- " addi r1, r1, -32\n" // new stack frame for child
- " }\n"
- /* save fn */
- " { st r1, r0; addi r1, r1, 8 }\n"
- /* save args */
- " { st r1, r3; addi r1, r1, 8 }\n"
- /* save flags */
- " { st r1, r2; addi r1, r1, -16 }\n"
-
- /* Child stack layout
-
- flags
- args
- r1-> fn
- */
- " {\n"
- /* prepare args for clone. */
- " move r0, r2\n" // arg0 = flags
- /* arg1=r1 child stack */
- " move r2, r5\n" // arg2 = parent tid
- " }\n"
- " {\n"
- " move r3, r4\n" // arg3 = child tid
- " move r4, r6\n" // arg4 = tls
- " }\n"
- " moveli r10, " __NR_CLONE "\n"
- " swint1\n"
-
- " beqz r0, .Lchild\n"
- " move r29, sp\n"
- " ld lr, r29\n" // Restore lr
- " addi r29, r29, 8\n"
- " {\n"
- " ld r10, r29\n" // resotre r10
- " addi sp, sp, 32\n"
- " }\n"
- " ld r29, sp\n"
- " jrp lr\n"
-
- ".Lchild:"
- " move r2, sp\n"
- " {\n"
- " ld r3, r2\n"
- " addi r2, r2, 8\n"
- " }\n"
- " ld r0, r2\n"
- " jalr r3\n"
- " moveli r10, " __NR_EXIT "\n"
- " swint1\n"
-
- ".Linvalid:"
- " { movei r1, 22; jrp lr }\n"
- );
-
-#undef __NR_CLONE
-#undef __NR_EXIT
-
-// forward declarations
-static void setup_child ( ThreadArchState *, ThreadArchState * );
-static SysRes sys_set_tls ( ThreadId tid, Addr tlsptr );
- /*
- When a client clones, we need to keep track of the new thread. This means:
- 1. allocate a ThreadId+ThreadState+stack for the thread
- 2. initialize the thread's new VCPU state
- 3. create the thread using the same args as the client requested,
- but using the scheduler entrypoint for IP, and a separate stack
- for SP.
- */
-static SysRes do_clone ( ThreadId ptid,
- Long flags, Addr sp,
- Long * parent_tidptr,
- Long * child_tidptr,
- Addr child_tls )
-{
- const Bool debug = False;
- ThreadId ctid = VG_ (alloc_ThreadState) ();
- ThreadState * ptst = VG_ (get_ThreadState) (ptid);
- ThreadState * ctst = VG_ (get_ThreadState) (ctid);
- Long ret = 0;
- Long * stack;
- SysRes res;
- vki_sigset_t blockall, savedmask;
-
- VG_ (sigfillset) (&blockall);
- vg_assert (VG_ (is_running_thread) (ptid));
- vg_assert (VG_ (is_valid_tid) (ctid));
- stack = (Long *) ML_ (allocstack) (ctid);
- if (stack == NULL) {
- res = VG_ (mk_SysRes_Error) (VKI_ENOMEM);
- goto out;
- }
- setup_child (&ctst->arch, &ptst->arch);
-
- /* On TILEGX we need to set r0 and r3 to zero */
- ctst->arch.vex.guest_r0 = 0;
- ctst->arch.vex.guest_r3 = 0;
- if (sp != 0)
- ctst->arch.vex.guest_r54 = sp;
-
- ctst->os_state.parent = ptid;
- ctst->sig_mask = ptst->sig_mask;
- ctst->tmp_sig_mask = ptst->sig_mask;
-
- /* Start the child with its threadgroup being the same as the
- parent's. This is so that any exit_group calls that happen
- after the child is created but before it sets its
- os_state.threadgroup field for real (in thread_wrapper in
- syswrap-linux.c), really kill the new thread. a.k.a this avoids
- a race condition in which the thread is unkillable (via
- exit_group) because its threadgroup is not set. The race window
- is probably only a few hundred or a few thousand cycles long.
- See #226116. */
-
- ctst->os_state.threadgroup = ptst->os_state.threadgroup;
- ML_(guess_and_register_stack) (sp, ctst);
-
- VG_TRACK (pre_thread_ll_create, ptid, ctid);
- if (flags & VKI_CLONE_SETTLS) {
- if (debug)
- VG_(printf)("clone child has SETTLS: tls at %#lx\n", child_tls);
- ctst->arch.vex.guest_r53 = child_tls;
- res = sys_set_tls(ctid, child_tls);
- if (sr_isError(res))
- goto out;
- }
-
- flags &= ~VKI_CLONE_SETTLS;
- VG_ (sigprocmask) (VKI_SIG_SETMASK, &blockall, &savedmask);
- /* Create the new thread */
- ret = do_syscall_clone_tilegx_linux (ML_ (start_thread_NORETURN),
- stack, flags, &VG_ (threads)[ctid],
- child_tidptr, parent_tidptr,
- (Long)NULL /*child_tls*/);
-
- /* High half word64 is syscall return value. */
- if (debug)
- VG_(printf)("ret: 0x%llx\n", (ULong)ret);
-
- res = VG_(mk_SysRes_tilegx_linux) (/*val */ ret);
-
- VG_ (sigprocmask) (VKI_SIG_SETMASK, &savedmask, NULL);
-
- out:
- if (sr_isError (res)) {
- VG_(cleanup_thread) (&ctst->arch);
- ctst->status = VgTs_Empty;
- VG_TRACK (pre_thread_ll_exit, ctid);
- }
- ptst->arch.vex.guest_r0 = 0;
-
- return res;
-}
-
-extern Addr do_brk ( Addr newbrk );
-
-extern
-SysRes do_mremap( Addr old_addr, SizeT old_len,
- Addr new_addr, SizeT new_len,
- UWord flags, ThreadId tid );
-
-extern Bool linux_kernel_2_6_22(void);
-
-/* ---------------------------------------------------------------------
- More thread stuff
- ------------------------------------------------------------------ */
-
-// TILEGX doesn't have any architecture specific thread stuff that
-// needs to be cleaned up.
-void
-VG_ (cleanup_thread) ( ThreadArchState * arch ) { }
-
-void
-setup_child ( /*OUT*/ ThreadArchState * child,
- /*IN*/ ThreadArchState * parent )
-{
- /* We inherit our parent's guest state. */
- child->vex = parent->vex;
- child->vex_shadow1 = parent->vex_shadow1;
- child->vex_shadow2 = parent->vex_shadow2;
-}
-
-SysRes sys_set_tls ( ThreadId tid, Addr tlsptr )
-{
- VG_(threads)[tid].arch.vex.guest_r53 = tlsptr;
- return VG_(mk_SysRes_Success)( 0 );
-}
-
-
-/* ---------------------------------------------------------------------
- PRE/POST wrappers for tilegx/Linux-specific syscalls
- ------------------------------------------------------------------ */
-#define PRE(name) DEFN_PRE_TEMPLATE(tilegx_linux, name)
-#define POST(name) DEFN_POST_TEMPLATE(tilegx_linux, name)
-
-/* Add prototypes for the wrappers declared here, so that gcc doesn't
- harass us for not having prototypes. Really this is a kludge --
- the right thing to do is to make these wrappers 'static' since they
- aren't visible outside this file, but that requires even more macro
- magic. */
-
-DECL_TEMPLATE (tilegx_linux, sys_clone);
-DECL_TEMPLATE (tilegx_linux, sys_rt_sigreturn);
-DECL_TEMPLATE (tilegx_linux, sys_socket);
-DECL_TEMPLATE (tilegx_linux, sys_setsockopt);
-DECL_TEMPLATE (tilegx_linux, sys_getsockopt);
-DECL_TEMPLATE (tilegx_linux, sys_connect);
-DECL_TEMPLATE (tilegx_linux, sys_accept);
-DECL_TEMPLATE (tilegx_linux, sys_accept4);
-DECL_TEMPLATE (tilegx_linux, sys_sendto);
-DECL_TEMPLATE (tilegx_linux, sys_recvfrom);
-DECL_TEMPLATE (tilegx_linux, sys_sendmsg);
-DECL_TEMPLATE (tilegx_linux, sys_recvmsg);
-DECL_TEMPLATE (tilegx_linux, sys_shutdown);
-DECL_TEMPLATE (tilegx_linux, sys_bind);
-DECL_TEMPLATE (tilegx_linux, sys_listen);
-DECL_TEMPLATE (tilegx_linux, sys_getsockname);
-DECL_TEMPLATE (tilegx_linux, sys_getpeername);
-DECL_TEMPLATE (tilegx_linux, sys_socketpair);
-DECL_TEMPLATE (tilegx_linux, sys_semget);
-DECL_TEMPLATE (tilegx_linux, sys_semop);
-DECL_TEMPLATE (tilegx_linux, sys_semtimedop);
-DECL_TEMPLATE (tilegx_linux, sys_semctl);
-DECL_TEMPLATE (tilegx_linux, sys_msgget);
-DECL_TEMPLATE (tilegx_linux, sys_msgrcv);
-DECL_TEMPLATE (tilegx_linux, sys_msgsnd);
-DECL_TEMPLATE (tilegx_linux, sys_msgctl);
-DECL_TEMPLATE (tilegx_linux, sys_shmget);
-DECL_TEMPLATE (tilegx_linux, wrap_sys_shmat);
-DECL_TEMPLATE (tilegx_linux, sys_shmdt);
-DECL_TEMPLATE (tilegx_linux, sys_shmdt);
-DECL_TEMPLATE (tilegx_linux, sys_shmctl);
-DECL_TEMPLATE (tilegx_linux, sys_arch_prctl);
-DECL_TEMPLATE (tilegx_linux, sys_ptrace);
-DECL_TEMPLATE (tilegx_linux, sys_fadvise64);
-DECL_TEMPLATE (tilegx_linux, sys_mmap);
-DECL_TEMPLATE (tilegx_linux, sys_syscall184);
-DECL_TEMPLATE (tilegx_linux, sys_cacheflush);
-DECL_TEMPLATE (tilegx_linux, sys_set_dataplane);
-
-PRE(sys_clone)
-{
- ULong cloneflags;
-
- PRINT("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )",ARG1,ARG2,ARG3,ARG4,ARG5);
- PRE_REG_READ5(int, "clone",
- unsigned long, flags,
- void *, child_stack,
- int *, parent_tidptr,
- int *, child_tidptr,
- void *, tlsaddr);
-
- if (ARG1 & VKI_CLONE_PARENT_SETTID) {
- PRE_MEM_WRITE("clone(parent_tidptr)", ARG3, sizeof(Int));
- if (!VG_(am_is_valid_for_client)(ARG3, sizeof(Int), VKI_PROT_WRITE)) {
- SET_STATUS_Failure( VKI_EFAULT );
- return;
- }
- }
- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) {
- PRE_MEM_WRITE("clone(child_tidptr)", ARG4, sizeof(Int));
- if (!VG_(am_is_valid_for_client)(ARG4, sizeof(Int), VKI_PROT_WRITE)) {
- SET_STATUS_Failure( VKI_EFAULT );
- return;
- }
- }
-
- cloneflags = ARG1;
-
- if (!ML_(client_signal_OK)(ARG1 & VKI_CSIGNAL)) {
- SET_STATUS_Failure( VKI_EINVAL );
- return;
- }
-
- /* Only look at the flags we really care about */
- switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS
- | VKI_CLONE_FILES | VKI_CLONE_VFORK)) {
- case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES:
- /* thread creation */
- SET_STATUS_from_SysRes(
- do_clone(tid,
- ARG1, /* flags */
- (Addr)ARG2, /* child ESP */
- (Long *)ARG3, /* parent_tidptr */
- (Long *)ARG4, /* child_tidptr */
- (Addr)ARG5)); /* set_tls */
- break;
-
- case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */
- /* FALLTHROUGH - assume vfork == fork */
- cloneflags &= ~(VKI_CLONE_VFORK | VKI_CLONE_VM);
-
- case 0: /* plain fork */
- SET_STATUS_from_SysRes(
- ML_(do_fork_clone)(tid,
- cloneflags, /* flags */
- (Int *)ARG3, /* parent_tidptr */
- (Int *)ARG4)); /* child_tidptr */
- break;
-
- default:
- /* should we just ENOSYS? */
- VG_(message)(Vg_UserMsg,
- "Unsupported clone() flags: 0x%lx\n", ARG1);
- VG_(message)(Vg_UserMsg,
- "\n");
- VG_(message)(Vg_UserMsg,
- "The only supported clone() uses are:\n");
- VG_(message)(Vg_UserMsg,
- " - via a threads library (LinuxThreads or NPTL)\n");
- VG_(message)(Vg_UserMsg,
- " - via the implementation of fork or vfork\n");
- VG_(unimplemented)
- ("Valgrind does not support general clone().");
- }
-
- if (SUCCESS) {
- if (ARG1 & VKI_CLONE_PARENT_SETTID)
- POST_MEM_WRITE(ARG3, sizeof(Int));
- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID))
- POST_MEM_WRITE(ARG4, sizeof(Int));
-
- /* Thread creation was successful; let the child have the chance
- to run */
- *flags |= SfYieldAfter;
- }
-}
-
-PRE(sys_rt_sigreturn)
-{
- /* This isn't really a syscall at all - it's a misuse of the
- syscall mechanism by m_sigframe. VG_(sigframe_create) sets the
- return address of the signal frames it creates to be a short
- piece of code which does this "syscall". The only purpose of
- the syscall is to call VG_(sigframe_destroy), which restores the
- thread's registers from the frame and then removes it.
- Consequently we must ask the syswrap driver logic not to write
- back the syscall "result" as that would overwrite the
- just-restored register state. */
-
- ThreadState* tst;
- PRINT("sys_rt_sigreturn ( )");
-
- vg_assert(VG_(is_valid_tid)(tid));
- vg_assert(tid >= 1 && tid < VG_N_THREADS);
- vg_assert(VG_(is_running_thread)(tid));
-
- /* Adjust RSP to point to start of frame; skip back up over handler
- ret addr */
- tst = VG_(get_ThreadState)(tid);
- tst->arch.vex.guest_r54 -= sizeof(Addr);
-
- /* This is only so that the RIP is (might be) useful to report if
- something goes wrong in the sigreturn. JRS 20070318: no idea
- what this is for */
- ML_(fixup_guest_state_to_restart_syscall)(&tst->arch);
-
- /* Restore register state from frame and remove it, as
- described above */
- VG_(sigframe_destroy)(tid, True);
-
- /* Tell the driver not to update the guest state with the "result",
- and set a bogus result to keep it happy. */
- *flags |= SfNoWriteResult;
- SET_STATUS_Success(0);
-
- /* Check to see if any signals arose as a result of this. */
- *flags |= SfPollAfter;
-}
-
-PRE(sys_arch_prctl)
-{
- PRINT( "arch_prctl ( %ld, %lx )", SARG1, ARG2 );
-
- vg_assert(VG_(is_valid_tid)(tid));
- vg_assert(tid >= 1 && tid < VG_N_THREADS);
- vg_assert(VG_(is_running_thread)(tid));
-
- I_die_here;
-}
-
-// Parts of this are tilegx-specific, but the *PEEK* cases are generic.
-//
-// ARG3 is only used for pointers into the traced process's address
-// space and for offsets into the traced process's struct
-// user_regs_struct. It is never a pointer into this process's memory
-// space, and we should therefore not check anything it points to.
-PRE(sys_ptrace)
-{
- PRINT("sys_ptrace ( %ld, %ld, %#lx, %#lx )", SARG1, SARG2, ARG3, ARG4);
- PRE_REG_READ4(int, "ptrace",
- long, request, long, pid, unsigned long, addr, unsigned long, data);
- switch (ARG1) {
- case VKI_PTRACE_PEEKTEXT:
- case VKI_PTRACE_PEEKDATA:
- case VKI_PTRACE_PEEKUSR:
- PRE_MEM_WRITE( "ptrace(peek)", ARG4,
- sizeof (long));
- break;
- case VKI_PTRACE_GETREGS:
- PRE_MEM_WRITE( "ptrace(getregs)", ARG4,
- sizeof (struct vki_user_regs_struct));
- break;
-#if 0 // FIXME
- case VKI_PTRACE_GETFPREGS:
- PRE_MEM_WRITE( "ptrace(getfpregs)", ARG4,
- sizeof (struct vki_user_i387_struct));
- break;
-#endif
- case VKI_PTRACE_SETREGS:
- PRE_MEM_READ( "ptrace(setregs)", ARG4,
- sizeof (struct vki_user_regs_struct));
- break;
-#if 0 // FIXME
- case VKI_PTRACE_SETFPREGS:
- PRE_MEM_READ( "ptrace(setfpregs)", ARG4,
- sizeof (struct vki_user_i387_struct));
- break;
-#endif
- case VKI_PTRACE_GETEVENTMSG:
- PRE_MEM_WRITE( "ptrace(geteventmsg)", ARG4, sizeof(unsigned long));
- break;
- case VKI_PTRACE_GETSIGINFO:
- PRE_MEM_WRITE( "ptrace(getsiginfo)", ARG4, sizeof(vki_siginfo_t));
- break;
- case VKI_PTRACE_SETSIGINFO:
- PRE_MEM_READ( "ptrace(setsiginfo)", ARG4, sizeof(vki_siginfo_t));
- break;
- default:
- break;
- }
-}
-
-POST(sys_ptrace)
-{
- switch (ARG1) {
- case VKI_PTRACE_PEEKTEXT:
- case VKI_PTRACE_PEEKDATA:
- case VKI_PTRACE_PEEKUSR:
- POST_MEM_WRITE( ARG4, sizeof (long));
- break;
- case VKI_PTRACE_GETREGS:
- POST_MEM_WRITE( ARG4, sizeof (struct vki_user_regs_struct));
- break;
-#if 0 // FIXME
- case VKI_PTRACE_GETFPREGS:
- POST_MEM_WRITE( ARG4, sizeof (struct vki_user_i387_struct));
- break;
-#endif
- case VKI_PTRACE_GETEVENTMSG:
- POST_MEM_WRITE( ARG4, sizeof(unsigned long));
- break;
- case VKI_PTRACE_GETSIGINFO:
- /* XXX: This is a simplification. Different parts of the
- * siginfo_t are valid depending on the type of signal.
- */
- POST_MEM_WRITE( ARG4, sizeof(vki_siginfo_t));
- break;
- default:
- break;
- }
-}
-
-PRE(sys_socket)
-{
- PRINT("sys_socket ( %ld, %ld, %ld )", SARG1, SARG2, SARG3);
- PRE_REG_READ3(long, "socket", int, domain, int, type, int, protocol);
-}
-POST(sys_socket)
-{
- SysRes r;
- vg_assert(SUCCESS);
- r = ML_(generic_POST_sys_socket)(tid, VG_(mk_SysRes_Success)(RES));
- SET_STATUS_from_SysRes(r);
-}
-
-PRE(sys_setsockopt)
-{
- PRINT("sys_setsockopt ( %ld, %ld, %ld, %#lx, %ld )", SARG1, SARG2, SARG3,
- ARG4, SARG5);
- PRE_REG_READ5(long, "setsockopt",
- int, s, int, level, int, optname,
- const void *, optval, int, optlen);
- ML_(generic_PRE_sys_setsockopt)(tid, ARG1,ARG2,ARG3,ARG4,ARG5);
-}
-
-PRE(sys_getsockopt)
-{
- PRINT("sys_getsockopt ( %ld, %ld, %ld, %#lx, %#lx )", SARG1, SARG2, SARG3,
- ARG4, ARG5);
- PRE_REG_READ5(long, "getsockopt",
- int, s, int, level, int, optname,
- void *, optval, int, *optlen);
- ML_(linux_PRE_sys_getsockopt)(tid, ARG1,ARG2,ARG3,ARG4,ARG5);
-}
-POST(sys_getsockopt)
-{
- vg_assert(SUCCESS);
- ML_(linux_POST_sys_getsockopt)(tid, VG_(mk_SysRes_Success)(RES),
- ARG1,ARG2,ARG3,ARG4,ARG5);
-}
-
-PRE(sys_connect)
-{
- *flags |= SfMayBlock;
- PRINT("sys_connect ( %ld, %#lx, %ld )", SARG1, ARG2, SARG3);
- PRE_REG_READ3(long, "connect",
- int, sockfd, struct sockaddr *, serv_addr, int, addrlen);
- ML_(generic_PRE_sys_connect)(tid, ARG1,ARG2,ARG3);
-}
-
-PRE(sys_accept)
-{
- *flags |= SfMayBlock;
- PRINT("sys_accept ( %ld, %#lx, %#lx )", SARG1, ARG2, ARG3);
- PRE_REG_READ3(long, "accept",
- int, s, struct sockaddr *, addr, int *, addrlen);
- ML_(generic_PRE_sys_accept)(tid, ARG1,ARG2,ARG3);
-}
-POST(sys_accept)
-{
- SysRes r;
- vg_assert(SUCCESS);
- r = ML_(generic_POST_sys_accept)(tid, VG_(mk_SysRes_Success)(RES),
- ARG1,ARG2,ARG3);
- SET_STATUS_from_SysRes(r);
-}
-
-PRE(sys_accept4)
-{
- *flags |= SfMayBlock;
- PRINT("sys_accept4 ( %ld, %#lx, %#lx, %ld )", SARG1, ARG2, ARG3, SARG4);
- PRE_REG_READ4(long, "accept4",
- int, s, struct sockaddr *, addr, int *, addrlen, int, flags);
- ML_(generic_PRE_sys_accept)(tid, ARG1,ARG2,ARG3);
-}
-POST(sys_accept4)
-{
- SysRes r;
- vg_assert(SUCCESS);
- r = ML_(generic_POST_sys_accept)(tid, VG_(mk_SysRes_Success)(RES),
- ARG1,ARG2,ARG3);
- SET_STATUS_from_SysRes(r);
-}
-
-PRE(sys_sendto)
-{
- *flags |= SfMayBlock;
- PRINT("sys_sendto ( %ld, %#lx, %ld, %lu, %#lx, %ld )", SARG1, ARG2, SARG3,
- ARG4, ARG5, SARG6);
- PRE_REG_READ6(long, "sendto",
- int, s, const void *, msg, int, len,
- unsigned int, flags,
- const struct sockaddr *, to, int, tolen);
- ML_(generic_PRE_sys_sendto)(tid, ARG1,ARG2,ARG3,ARG4,ARG5,ARG6);
-}
-
-PRE(sys_recvfrom)
-{
- *flags |= SfMayBlock;
- PRINT("sys_recvfrom ( %ld, %#lx, %ld, %lu, %#lx, %#lx )", SARG1, ARG2, SARG3,
- ARG4, ARG5, ARG6);
- PRE_REG_READ6(long, "recvfrom",
- int, s, void *, buf, int, len, unsigned int, flags,
- struct sockaddr *, from, int *, fromlen);
- ML_(generic_PRE_sys_recvfrom)(tid, ARG1,ARG2,ARG3,ARG4,ARG5,ARG6);
-}
-POST(sys_recvfrom)
-{
- vg_assert(SUCCESS);
- ML_(generic_POST_sys_recvfrom)(tid, VG_(mk_SysRes_Success)(RES),
- ARG1,ARG2,ARG3,ARG4,ARG5,ARG6);
-}
-
-PRE(sys_sendmsg)
-{
- *flags |= SfMayBlock;
- PRINT("sys_sendmsg ( %ld, %#lx, %ld )", SARG1, ARG2, SARG3);
- PRE_REG_READ3(long, "sendmsg",
- int, s, const struct msghdr *, msg, int, flags);
- ML_(generic_PRE_sys_sendmsg)(tid, "msg", ARG2);
-}
-
-PRE(sys_recvmsg)
-{
- *flags |= SfMayBlock;
- PRINT("sys_recvmsg ( %ld, %#lx, %ld )", SARG1, ARG2, SARG3);
- PRE_REG_READ3(long, "recvmsg", int, s, struct msghdr *, msg, int, flags);
- ML_(generic_PRE_sys_recvmsg)(tid, "msg", (struct vki_msghdr *) ARG2);
-}
-
-POST(sys_recvmsg)
-{
- ML_(generic_POST_sys_recvmsg)(tid, "msg", (struct vki_msghdr *)ARG2, RES);
-}
-
-PRE(sys_shutdown)
-{
- *flags |= SfMayBlock;
- PRINT("sys_shutdown ( %ld, %ld )", SARG1, SARG2);
- PRE_REG_READ2(int, "shutdown", int, s, int, how);
-}
-
-PRE(sys_bind)
-{
- PRINT("sys_bind ( %ld, %#lx, %ld )", SARG1, ARG2, SARG3);
- PRE_REG_READ3(long, "bind",
- int, sockfd, struct sockaddr *, my_addr, int, addrlen);
- ML_(generic_PRE_sys_bind)(tid, ARG1,ARG2,ARG3);
-}
-
-PRE(sys_listen)
-{
- PRINT("sys_listen ( %ld, %ld )", SARG1, SARG2);
- PRE_REG_READ2(long, "listen", int, s, int, backlog);
-}
-
-PRE(sys_getsockname)
-{
- PRINT("sys_getsockname ( %ld, %#lx, %#lx )", SARG1, ARG2, ARG3);
- PRE_REG_READ3(long, "getsockname",
- int, s, struct sockaddr *, name, int *, namelen);
- ML_(generic_PRE_sys_getsockname)(tid, ARG1,ARG2,ARG3);
-}
-POST(sys_getsockname)
-{
- vg_assert(SUCCESS);
- ML_(generic_POST_sys_getsockname)(tid, VG_(mk_SysRes_Success)(RES),
- ARG1,ARG2,ARG3);
-}
-
-PRE(sys_getpeername)
-{
- PRINT("sys_getpeername ( %ld, %#lx, %#lx )", SARG1, ARG2, ARG3);
- PRE_REG_READ3(long, "getpeername",
- int, s, struct sockaddr *, name, int *, namelen);
- ML_(generic_PRE_sys_getpeername)(tid, ARG1,ARG2,ARG3);
-}
-POST(sys_getpeername)
-{
- vg_assert(SUCCESS);
- ML_(generic_POST_sys_getpeername)(tid, VG_(mk_SysRes_Success)(RES),
- ARG1,ARG2,ARG3);
-}
-
-PRE(sys_socketpair)
-{
- PRINT("sys_socketpair ( %ld, %ld, %ld, %#lx )", SARG1, SARG2, SARG3, ARG4);
- PRE_REG_READ4(long, "socketpair",
- int, d, int, type, int, protocol, int*, sv);
- ML_(generic_PRE_sys_socketpair)(tid, ARG1,ARG2,ARG3,ARG4);
-}
-POST(sys_socketpair)
-{
- vg_assert(SUCCESS);
- ML_(generic_POST_sys_socketpair)(tid, VG_(mk_SysRes_Success)(RES),
- ARG1,ARG2,ARG3,ARG4);
-}
-
-PRE(sys_semget)
-{
- PRINT("sys_semget ( %ld, %ld, %ld )", SARG1, SARG2, SARG3);
- PRE_REG_READ3(long, "semget", vki_key_t, key, int, nsems, int, semflg);
-}
-
-PRE(sys_semop)
-{
- *flags |= SfMayBlock;
- PRINT("sys_semop ( %ld, %#lx, %lu )", SARG1, ARG2, ARG3);
- PRE_REG_READ3(long, "semop",
- int, semid, struct sembuf *, sops, unsigned, nsoops);
- ML_(generic_PRE_sys_semop)(tid, ARG1,ARG2,ARG3);
-}
-
-PRE(sys_semtimedop)
-{
- *flags |= SfMayBlock;
- PRINT("sys_semtimedop ( %ld, %#lx, %lu, %#lx )", SARG1, ARG2, ARG3, ARG4);
- PRE_REG_READ4(long, "semtimedop",
- int, semid, struct sembuf *, sops, unsigned, nsoops,
- struct timespec *, timeout);
- ML_(generic_PRE_sys_semtimedop)(tid, ARG1,ARG2,ARG3,ARG4);
-}
-
-PRE(sys_semctl)
-{
- switch (ARG3 & ~VKI_IPC_64) {
- case VKI_IPC_INFO:
- case VKI_SEM_INFO:
- PRINT("sys_semctl ( %ld, %ld, %ld, %#lx )", SARG1, SARG2, SARG3, ARG4);
- PRE_REG_READ4(long, "semctl",
- int, semid, int, semnum, int, cmd, struct seminfo *, arg);
- break;
- case VKI_IPC_STAT:
- case VKI_SEM_STAT:
- case VKI_IPC_SET:
- PRINT("sys_semctl ( %ld, %ld, %ld, %#lx )", SARG1, SARG2, SARG3, ARG4);
- PRE_REG_READ4(long, "semctl",
- int, semid, int, semnum, int, cmd, struct semid_ds *, arg);
- break;
- case VKI_GETALL:
- case VKI_SETALL:
- PRINT("sys_semctl ( %ld, %ld, %ld, %#lx )", SARG1, SARG2, SARG3, ARG4);
- PRE_REG_READ4(long, "semctl",
- int, semid, int, semnum, int, cmd, unsigned short *, arg);
- break;
- default:
- PRINT("sys_semctl ( %ld, %ld, %ld )", SARG1, SARG2, SARG3);
- PRE_REG_READ3(long, "semctl",
- int, semid, int, semnum, int, cmd);
- break;
- }
- ML_(generic_PRE_sys_semctl)(tid, ARG1,ARG2,ARG3|VKI_IPC_64,ARG4);
-}
-POST(sys_semctl)
-{
- ML_(generic_POST_sys_semctl)(tid, RES,ARG1,ARG2,ARG3|VKI_IPC_64,ARG4);
-}
-
-PRE(sys_msgget)
-{
- PRINT("sys_msgget ( %ld, %ld )", SARG1, SARG2);
- PRE_REG_READ2(long, "msgget", vki_key_t, key, int, msgflg);
-}
-
-PRE(sys_msgsnd)
-{
- PRINT("sys_msgsnd ( %ld, %#lx, %lu, %ld )", SARG1, ARG2, ARG3, SARG4);
- PRE_REG_READ4(long, "msgsnd",
- int, msqid, struct msgbuf *, msgp, vki_size_t, msgsz,
- int, msgflg);
- ML_(linux_PRE_sys_msgsnd)(tid, ARG1,ARG2,ARG3,ARG4);
- if ((ARG4 & VKI_IPC_NOWAIT) == 0)
- *flags |= SfMayBlock;
-}
-
-PRE(sys_msgrcv)
-{
- PRINT("sys_msgrcv ( %ld, %#lx, %lu, %ld, %ld )", SARG1, ARG2, ARG3,
- SARG4, SARG5);
- PRE_REG_READ5(long, "msgrcv",
- int, msqid, struct msgbuf *, msgp, vki_size_t, msgsz,
- long, msgytp, int, msgflg);
- ML_(linux_PRE_sys_msgrcv)(tid, ARG1,ARG2,ARG3,ARG4,ARG5);
- if ((ARG4 & VKI_IPC_NOWAIT) == 0)
- *flags |= SfMayBlock;
-}
-POST(sys_msgrcv)
-{
- ML_(linux_POST_sys_msgrcv)(tid, RES,ARG1,ARG2,ARG3,ARG4,ARG5);
-}
-
-PRE(sys_msgctl)
-{
- PRINT("sys_msgctl ( %ld, %ld, %#lx )", SARG1, SARG2, ARG3);
- PRE_REG_READ3(long, "msgctl",
- int, msqid, int, cmd, struct msqid_ds *, buf);
- ML_(linux_PRE_sys_msgctl)(tid, ARG1,ARG2,ARG3);
-}
-POST(sys_msgctl)
-{
- ML_(linux_POST_sys_msgctl)(tid, RES,ARG1,ARG2,ARG3);
-}
-
-PRE(sys_shmget)
-{
- PRINT("sys_shmget ( %ld, %lu, %ld )", SARG1, ARG2, SARG3);
- PRE_REG_READ3(long, "shmget", vki_key_t, key, vki_size_t, size, int, shmflg);
-}
-
-PRE(wrap_sys_shmat)
-{
- UWord arg2tmp;
- PRINT("wrap_sys_shmat ( %ld, %#lx, %ld )", SARG1, ARG2, SARG3);
- PRE_REG_READ3(long, "shmat",
- int, shmid, const void *, shmaddr, int, shmflg);
- arg2tmp = ML_(generic_PRE_sys_shmat)(tid, ARG1,ARG2,ARG3);
- if (arg2tmp == 0)
- SET_STATUS_Failure( VKI_EINVAL );
- else
- ARG2 = arg2tmp; // used in POST
-}
-POST(wrap_sys_shmat)
-{
- ML_(generic_POST_sys_shmat)(tid, RES,ARG1,ARG2,ARG3);
-}
-
-PRE(sys_shmdt)
-{
- PRINT("sys_shmdt ( %#lx )",ARG1);
- PRE_REG_READ1(long, "shmdt", const void *, shmaddr);
- if (!ML_(generic_PRE_sys_shmdt)(tid, ARG1))
- SET_STATUS_Failure( VKI_EINVAL );
-}
-POST(sys_shmdt)
-{
- ML_(generic_POST_sys_shmdt)(tid, RES,ARG1);
-}
-
-PRE(sys_shmctl)
-{
- PRINT("sys_shmctl ( %ld, %ld, %#lx )", SARG1, SARG2, ARG3);
- PRE_REG_READ3(long, "shmctl",
- int, shmid, int, cmd, struct shmid_ds *, buf);
- ML_(generic_PRE_sys_shmctl)(tid, ARG1,ARG2|VKI_IPC_64,ARG3);
-}
-POST(sys_shmctl)
-{
- ML_(generic_POST_sys_shmctl)(tid, RES,ARG1,ARG2|VKI_IPC_64,ARG3);
-}
-
-PRE(sys_fadvise64)
-{
- PRINT("sys_fadvise64 ( %ld, %ld, %lu, %ld )", SARG1, SARG2, ARG3, SARG4);
- PRE_REG_READ4(long, "fadvise64",
- int, fd, vki_loff_t, offset, vki_size_t, len, int, advice);
-}
-
-PRE(sys_mmap)
-{
- SysRes r;
-
- PRINT("sys_mmap ( %#lx, %lu, %lu, %lu, %lu, %lu )",
- ARG1, ARG2, ARG3, ARG4, ARG5, ARG6 );
- PRE_REG_READ6(long, "mmap",
- unsigned long, start, unsigned long, length,
- unsigned long, prot, unsigned long, flags,
- unsigned long, fd, unsigned long, offset);
-
- r = ML_(generic_PRE_sys_mmap)( tid, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6 );
- SET_STATUS_from_SysRes(r);
-}
-
-
-/* ---------------------------------------------------------------
- PRE/POST wrappers for TILEGX/Linux-variant specific syscalls
- ------------------------------------------------------------ */
-PRE(sys_cacheflush)
-{
- PRINT("cacheflush (%lx, %ld, %ld)", ARG1, SARG2, SARG3);
- PRE_REG_READ3(long, "cacheflush", unsigned long, addr,
- int, nbytes, int, cache);
- VG_ (discard_translations) ((Addr)ARG1, (ULong) ARG2,
- "PRE(sys_cacheflush)");
- SET_STATUS_Success(0);
-}
-
-PRE(sys_set_dataplane)
-{
- *flags |= SfMayBlock;
- PRINT("sys_set_dataplane ( %lu )", ARG1);
- PRE_REG_READ1(long, "set_dataplane", unsigned long, flag);
-}
-
-#undef PRE
-#undef POST
-
-
-/* ---------------------------------------------------------------------
- The TILEGX/Linux syscall table
- ------------------------------------------------------------------ */
-
-/* Add an tilegx-linux specific wrapper to a syscall table. */
-#define PLAX_(const, name) WRAPPER_ENTRY_X_(tilegx_linux, const, name)
-#define PLAXY(const, name) WRAPPER_ENTRY_XY(tilegx_linux, const, name)
-
-// This table maps from __NR_xxx syscall numbers (from
-// linux/include/asm/unistd.h) to the appropriate PRE/POST sys_foo()
-//
-// When implementing these wrappers, you need to work out if the wrapper is
-// generic, Linux-only (but arch-independent), or TILEGX/Linux only.
-
-static SyscallTableEntry syscall_table[] = {
-
- LINXY(__NR_io_setup, sys_io_setup), // 0
- LINX_(__NR_io_destroy, sys_io_destroy), // 1
- LINX_(__NR_io_submit, sys_io_submit), // 2
- LINXY(__NR_io_cancel, sys_io_cancel), // 3
- LINXY(__NR_io_getevents, sys_io_getevents), // 4
- LINX_(__NR_setxattr, sys_setxattr), // 5
- LINX_(__NR_lsetxattr, sys_lsetxattr), // 6
- LINX_(__NR_fsetxattr, sys_fsetxattr), // 7
- LINXY(__NR_getxattr, sys_getxattr), // 8
- LINXY(__NR_lgetxattr, sys_lgetxattr), // 9
- LINXY(__NR_fgetxattr, sys_fgetxattr), // 10
- LINXY(__NR_listxattr, sys_listxattr), // 11
- LINXY(__NR_llistxattr, sys_llistxattr), // 12
- LINXY(__NR_flistxattr, sys_flistxattr), // 13
- LINX_(__NR_removexattr, sys_removexattr), // 14
- LINX_(__NR_lremovexattr, sys_lremovexattr), // 15
- LINX_(__NR_fremovexattr, sys_fremovexattr), // 16
- GENXY(__NR_getcwd, sys_getcwd), // 17
- LINXY(__NR_lookup_dcookie, sys_lookup_dcookie), // 18
- LINX_(__NR_eventfd2, sys_eventfd2), // 19
- LINXY(__NR_epoll_create1, sys_epoll_create1), // 20
- LINX_(__NR_epoll_ctl, sys_epoll_ctl), // 21
- LINXY(__NR_epoll_pwait, sys_epoll_pwait), // 22
- GENXY(__NR_dup, sys_dup), // 23
- GENXY(__NR_dup2, sys_dup2), // 23
- LINXY(__NR_dup3, sys_dup3), // 24
- LINXY(__NR_fcntl, sys_fcntl), // 25
- LINXY(__NR_inotify_init1, sys_inotify_init1), // 26
- LINX_(__NR_inotify_add_watch, sys_inotify_add_watch), // 27
- LINX_(__NR_inotify_rm_watch, sys_inotify_rm_watch), // 28
- LINXY(__NR_ioctl, sys_ioctl), // 29
- LINX_(__NR_ioprio_set, sys_ioprio_set), // 30
- LINX_(__NR_ioprio_get, sys_ioprio_get), // 31
- GENX_(__NR_flock, sys_flock), // 32
- LINX_(__NR_mknodat, sys_mknodat), // 33
- LINX_(__NR_mkdirat, sys_mkdirat), // 34
- LINX_(__NR_unlinkat, sys_unlinkat), // 35
- LINX_(__NR_symlinkat, sys_symlinkat), // 36
- LINX_(__NR_linkat, sys_linkat), // 37
- LINX_(__NR_renameat, sys_renameat), // 38
- LINX_(__NR_umount2, sys_umount), // 39
- LINX_(__NR_mount, sys_mount), // 40
-
- GENXY(__NR_statfs, sys_statfs), // 43
- GENXY(__NR_fstatfs, sys_fstatfs), // 44
- GENX_(__NR_truncate, sys_truncate), // 45
- GENX_(__NR_ftruncate, sys_ftruncate), // 46
- LINX_(__NR_fallocate, sys_fallocate), // 47
- LINX_(__NR_faccessat, sys_faccessat), // 48
- GENX_(__NR_chdir, sys_chdir), // 49
- GENX_(__NR_fchdir, sys_fchdir), // 50
- GENX_(__NR_chroot, sys_chroot), // 51
- GENX_(__NR_fchmod, sys_fchmod), // 52
- LINX_(__NR_fchmodat, sys_fchmodat), // 53
- LINX_(__NR_fchownat, sys_fchownat), // 54
- GENX_(__NR_fchown, sys_fchown), // 55
- LINXY(__NR_openat, sys_openat), // 56
- GENXY(__NR_close, sys_close), // 57
- LINX_(__NR_vhangup, sys_vhangup), // 58
- LINXY(__NR_pipe2, sys_pipe2), // 59
- LINX_(__NR_quotactl, sys_quotactl), // 60
- GENXY(__NR_getdents64, sys_getdents64), // 61
- LINX_(__NR_lseek, sys_lseek), // 62
- GENXY(__NR_read, sys_read), // 63
- GENX_(__NR_write, sys_write), // 64
- GENXY(__NR_readv, sys_readv), // 65
- GENX_(__NR_writev, sys_writev), // 66
- GENXY(__NR_pread64, sys_pread64), // 67
- GENX_(__NR_pwrite64, sys_pwrite64), // 68
- LINXY(__NR_preadv, sys_preadv), // 69
- LINX_(__NR_pwritev, sys_pwritev), // 70
- LINXY(__NR_sendfile, sys_sendfile), // 71
- LINXY(__NR_pselect6, sys_pselect6), // 72
- LINXY(__NR_ppoll, sys_ppoll), // 73
- LINXY(__NR_signalfd4, sys_signalfd4), // 74
- LINX_(__NR_splice, sys_splice), // 75
- LINX_(__NR_readlinkat, sys_readlinkat), // 78
- LINXY(__NR3264_fstatat, sys_newfstatat), // 79
- GENXY(__NR_fstat, sys_newfstat), // 80
- GENX_(__NR_sync, sys_sync), // 81
- GENX_(__NR_fsync, sys_fsync), // 82
- GENX_(__NR_fdatasync, sys_fdatasync), // 83
- LINX_(__NR_sync_file_range, sys_sync_file_range), // 84
- LINXY(__NR_timerfd_create, sys_timerfd_create), // 85
- LINXY(__NR_timerfd_settime, sys_timerfd_settime), // 86
- LINXY(__NR_timerfd_gettime, sys_timerfd_gettime), // 87
- LINX_(__NR_utimensat, sys_utimensat), // 88
-
- LINXY(__NR_capget, sys_capget), // 90
- LINX_(__NR_capset, sys_capset), // 91
- LINX_(__NR_personality, sys_personality), // 92
- GENX_(__NR_exit, sys_exit), // 93
- LINX_(__NR_exit_group, sys_exit_group), // 94
- LINXY(__NR_waitid, sys_waitid), // 95
- LINX_(__NR_set_tid_address, sys_set_tid_address), // 96
- LINXY(__NR_futex, sys_futex), // 98
- LINX_(__NR_set_robust_list, sys_set_robust_list), // 99
- LINXY(__NR_get_robust_list, sys_get_robust_list), // 100
- GENXY(__NR_nanosleep, sys_nanosleep), // 101
- GENXY(__NR_getitimer, sys_getitimer), // 102
- GENXY(__NR_setitimer, sys_setitimer), // 103
- LINX_(__NR_init_module, sys_init_module), // 105
- LINX_(__NR_delete_module, sys_delete_module), // 106
- LINXY(__NR_timer_create, sys_timer_create), // 107
- LINXY(__NR_timer_gettime, sys_timer_gettime), // 108
- LINX_(__NR_timer_getoverrun, sys_timer_getoverrun), // 109
- LINXY(__NR_timer_settime, sys_timer_settime), // 110
- LINX_(__NR_timer_delete, sys_timer_delete), // 111
- LINX_(__NR_clock_settime, sys_clock_settime), // 112
- LINXY(__NR_clock_gettime, sys_clock_gettime), // 113
- LINXY(__NR_clock_getres, sys_clock_getres), // 114
- LINXY(__NR_clock_nanosleep, sys_clock_nanosleep), // 115
- LINXY(__NR_syslog, sys_syslog), // 116
- PLAXY(__NR_ptrace, sys_ptrace), // 117
- LINXY(__NR_sched_setparam, sys_sched_setparam), // 118
- LINX_(__NR_sched_setscheduler, sys_sched_setscheduler), // 119
- LINX_(__NR_sched_getscheduler, sys_sched_getscheduler), // 120
- LINXY(__NR_sched_getparam, sys_sched_getparam), // 121
- LINX_(__NR_sched_setaffinity, sys_sched_setaffinity), // 122
- LINXY(__NR_sched_getaffinity, sys_sched_getaffinity), // 123
- LINX_(__NR_sched_yield, sys_sched_yield), // 124
- LINX_(__NR_sched_get_priority_max, sys_sched_get_priority_max), // 125
- LINX_(__NR_sched_get_priority_min, sys_sched_get_priority_min), // 126
- LINXY(__NR_sched_rr_get_interval, sys_sched_rr_get_interval), // 127
-
- GENX_(__NR_kill, sys_kill), // 129
- LINXY(__NR_tkill, sys_tkill), // 130
- LINXY(__NR_tgkill, sys_tgkill), // 131
- GENXY(__NR_sigaltstack, sys_sigaltstack), // 132
- LINX_(__NR_rt_sigsuspend, sys_rt_sigsuspend), // 133
- LINXY(__NR_rt_sigaction, sys_rt_sigaction), // 134
- LINXY(__NR_rt_sigprocmask, sys_rt_sigprocmask), // 135
- LINXY(__NR_rt_sigpending, sys_rt_sigpending), // 136
- LINXY(__NR_rt_sigtimedwait, sys_rt_sigtimedwait), // 137
- LINXY(__NR_rt_sigqueueinfo, sys_rt_sigqueueinfo), // 138
- PLAX_(__NR_rt_sigreturn, sys_rt_sigreturn), // 139
- GENX_(__NR_setpriority, sys_setpriority), // 140
- GENX_(__NR_getpriority, sys_getpriority), // 141
-
- GENX_(__NR_setregid, sys_setregid), // 143
- GENX_(__NR_setgid, sys_setgid), // 144
- GENX_(__NR_setreuid, sys_setreuid), // 145
- GENX_(__NR_setuid, sys_setuid), // 146
- LINX_(__NR_setresuid, sys_setresuid), // 147
- LINXY(__NR_getresuid, sys_getresuid), // 148
- LINX_(__NR_setresgid, sys_setresgid), // 149
- LINXY(__NR_getresgid, sys_getresgid), // 150
- LINX_(__NR_setfsuid, sys_setfsuid), // 151
- LINX_(__NR_setfsgid, sys_setfsgid), // 152
- GENXY(__NR_times, sys_times), // 153
- GENX_(__NR_setpgid, sys_setpgid), // 154
- GENX_(__NR_getpgid, sys_getpgid), // 155
- GENX_(__NR_getsid, sys_getsid), // 156
- GENX_(__NR_setsid, sys_setsid), // 157
- GENXY(__NR_getgroups, sys_getgroups), // 158
- GENX_(__NR_setgroups, sys_setgroups), // 159
- GENXY(__NR_uname, sys_newuname), // 160
- GENXY(__NR_getrlimit, sys_getrlimit), // 163
- GENX_(__NR_setrlimit, sys_setrlimit), // 164
- GENXY(__NR_getrusage, sys_getrusage), // 165
- GENX_(__NR_umask, sys_umask), // 166
- LINXY(__NR_prctl, sys_prctl), // 167
-
- GENXY(__NR_gettimeofday, sys_gettimeofday), // 169
- GENX_(__NR_settimeofday, sys_settimeofday), // 170
- LINXY(__NR_adjtimex, sys_adjtimex), // 171
- GENX_(__NR_getpid, sys_getpid), // 172
- GENX_(__NR_getppid, sys_getppid), // 173
- GENX_(__NR_getuid, sys_getuid), // 174
- GENX_(__NR_geteuid, sys_geteuid), // 175
- GENX_(__NR_getgid, sys_getgid), // 176
- GENX_(__NR_getegid, sys_getegid), // 177
- LINX_(__NR_gettid, sys_gettid), // 178
- LINXY(__NR_sysinfo, sys_sysinfo), // 179
- LINXY(__NR_mq_open, sys_mq_open), // 180
- LINX_(__NR_mq_unlink, sys_mq_unlink), // 181
- LINX_(__NR_mq_timedsend, sys_mq_timedsend), // 182
- LINXY(__NR_mq_timedreceive, sys_mq_timedreceive), // 183
- LINX_(__NR_mq_notify, sys_mq_notify), // 184
- LINXY(__NR_mq_getsetattr, sys_mq_getsetattr), // 185
- PLAX_(__NR_msgget, sys_msgget), // 186
- PLAXY(__NR_msgctl, sys_msgctl), // 187
- PLAXY(__NR_msgrcv, sys_msgrcv), // 188
- PLAX_(__NR_msgsnd, sys_msgsnd), // 189
- PLAX_(__NR_semget, sys_semget), // 190
- PLAXY(__NR_semctl, sys_semctl), // 191
- PLAX_(__NR_semtimedop, sys_semtimedop), // 192
- PLAX_(__NR_semop, sys_semop), // 193
- PLAX_(__NR_shmget, sys_shmget), // 194
- PLAXY(__NR_shmat, wrap_sys_shmat), // 196
- PLAXY(__NR_shmctl, sys_shmctl), // 195
- PLAXY(__NR_shmdt, sys_shmdt), // 197
- PLAXY(__NR_socket, sys_socket), // 198
- PLAXY(__NR_socketpair, sys_socketpair), // 199
- PLAX_(__NR_bind, sys_bind), // 200
- PLAX_(__NR_listen, sys_listen), // 201
- PLAXY(__NR_accept, sys_accept), // 202
- PLAX_(__NR_connect, sys_connect), // 203
- PLAXY(__NR_getsockname, sys_getsockname), // 204
- PLAXY(__NR_getpeername, sys_getpeername), // 205
- PLAX_(__NR_sendto, sys_sendto), // 206
- PLAXY(__NR_recvfrom, sys_recvfrom), // 207
- PLAX_(__NR_setsockopt, sys_setsockopt), // 208
- PLAXY(__NR_getsockopt, sys_getsockopt), // 209
- PLAX_(__NR_shutdown, sys_shutdown), // 210
- PLAX_(__NR_sendmsg, sys_sendmsg), // 211
- PLAXY(__NR_recvmsg, sys_recvmsg), // 212
- LINX_(__NR_readahead, sys_readahead), // 213
- GENX_(__NR_brk, sys_brk), // 214
- GENXY(__NR_munmap, sys_munmap), // 215
- GENX_(__NR_mremap, sys_mremap), // 216
- LINX_(__NR_add_key, sys_add_key), // 217
- LINX_(__NR_request_key, sys_request_key), // 218
- LINXY(__NR_keyctl, sys_keyctl), // 219
- PLAX_(__NR_clone, sys_clone), // 220
- GENX_(__NR_execve, sys_execve), // 221
- PLAX_(__NR_mmap, sys_mmap), // 222
- GENXY(__NR_mprotect, sys_mprotect), // 226
- GENX_(__NR_msync, sys_msync), // 227
- GENX_(__NR_mlock, sys_mlock), // 228
- GENX_(__NR_munlock, sys_munlock), // 229
- GENX_(__NR_mlockall, sys_mlockall), // 230
- LINX_(__NR_munlockall, sys_munlockall), // 231
- GENX_(__NR_mincore, sys_mincore), // 232
- GENX_(__NR_madvise, sys_madvise), // 233
-
- LINX_(__NR_mbind, sys_mbind), // 235
- LINXY(__NR_get_mempolicy, sys_get_mempolicy), // 236
- LINX_(__NR_set_mempolicy, sys_set_mempolicy), // 237
-
- LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo), // 240
-
- PLAXY(__NR_accept4, sys_accept4), // 242
-
- PLAX_(__NR_cacheflush, sys_cacheflush), // 245
- PLAX_(__NR_set_dataplane, sys_set_dataplane), // 246
-
- GENXY(__NR_wait4, sys_wait4), // 260
-};
-
-SyscallTableEntry* ML_(get_linux_syscall_entry) ( UInt sysno )
-{
- const UInt syscall_table_size
- = sizeof(syscall_table) / sizeof(syscall_table[0]);
-
- /* Is it in the contiguous initial section of the table? */
- if (sysno < syscall_table_size) {
- SyscallTableEntry* sys = &syscall_table[sysno];
- if (sys->before == NULL)
- return NULL; /* no entry */
- else
- return sys;
- }
- //vex_printf("sysno: %d\n", sysno);
-
- /* Can't find a wrapper */
- return NULL;
-}
-
-#endif // defined(VGP_tilegx_linux)
-
-/*--------------------------------------------------------------------*/
-/*--- end syswrap-tilegx-linux.c ---*/
-/*--------------------------------------------------------------------*/
diff --git a/coregrind/m_syswrap/syswrap-x86-darwin.c b/coregrind/m_syswrap/syswrap-x86-darwin.c
index a571f64..dac5c7d 100644
--- a/coregrind/m_syswrap/syswrap-x86-darwin.c
+++ b/coregrind/m_syswrap/syswrap-x86-darwin.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Apple Inc.
+ Copyright (C) 2005-2017 Apple Inc.
Greg Parker gparker@apple.com
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_syswrap/syswrap-x86-linux.c b/coregrind/m_syswrap/syswrap-x86-linux.c
index 0e5af98..bec145a 100644
--- a/coregrind/m_syswrap/syswrap-x86-linux.c
+++ b/coregrind/m_syswrap/syswrap-x86-linux.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Nicholas Nethercote
+ Copyright (C) 2000-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -131,14 +131,7 @@
#define __NR_CLONE VG_STRINGIFY(__NR_clone)
#define __NR_EXIT VG_STRINGIFY(__NR_exit)
-extern
-Int do_syscall_clone_x86_linux ( Word (*fn)(void *),
- void* stack,
- Int flags,
- void* arg,
- Int* child_tid,
- Int* parent_tid,
- vki_modify_ldt_t * );
+// See priv_syswrap-linux.h for arg profile.
asm(
".text\n"
".globl do_syscall_clone_x86_linux\n"
@@ -191,141 +184,6 @@
#undef __NR_EXIT
-// forward declarations
-static void setup_child ( ThreadArchState*, ThreadArchState*, Bool );
-static SysRes sys_set_thread_area ( ThreadId, vki_modify_ldt_t* );
-
-/*
- When a client clones, we need to keep track of the new thread. This means:
- 1. allocate a ThreadId+ThreadState+stack for the thread
-
- 2. initialize the thread's new VCPU state
-
- 3. create the thread using the same args as the client requested,
- but using the scheduler entrypoint for EIP, and a separate stack
- for ESP.
- */
-static SysRes do_clone ( ThreadId ptid,
- UInt flags, Addr esp,
- Int* parent_tidptr,
- Int* child_tidptr,
- vki_modify_ldt_t *tlsinfo)
-{
- static const Bool debug = False;
-
- ThreadId ctid = VG_(alloc_ThreadState)();
- ThreadState* ptst = VG_(get_ThreadState)(ptid);
- ThreadState* ctst = VG_(get_ThreadState)(ctid);
- UWord* stack;
- SysRes res;
- Int eax;
- vki_sigset_t blockall, savedmask;
-
- VG_(sigfillset)(&blockall);
-
- vg_assert(VG_(is_running_thread)(ptid));
- vg_assert(VG_(is_valid_tid)(ctid));
-
- stack = (UWord*)ML_(allocstack)(ctid);
- if (stack == NULL) {
- res = VG_(mk_SysRes_Error)( VKI_ENOMEM );
- goto out;
- }
-
- /* Copy register state
-
- Both parent and child return to the same place, and the code
- following the clone syscall works out which is which, so we
- don't need to worry about it.
-
- The parent gets the child's new tid returned from clone, but the
- child gets 0.
-
- If the clone call specifies a NULL esp for the new thread, then
- it actually gets a copy of the parent's esp.
- */
- /* Note: the clone call done by the Quadrics Elan3 driver specifies
- clone flags of 0xF00, and it seems to rely on the assumption
- that the child inherits a copy of the parent's GDT.
- setup_child takes care of setting that up. */
- setup_child( &ctst->arch, &ptst->arch, True );
-
- /* Make sys_clone appear to have returned Success(0) in the
- child. */
- ctst->arch.vex.guest_EAX = 0;
-
- if (esp != 0)
- ctst->arch.vex.guest_ESP = esp;
-
- ctst->os_state.parent = ptid;
-
- /* inherit signal mask */
- ctst->sig_mask = ptst->sig_mask;
- ctst->tmp_sig_mask = ptst->sig_mask;
-
- /* Start the child with its threadgroup being the same as the
- parent's. This is so that any exit_group calls that happen
- after the child is created but before it sets its
- os_state.threadgroup field for real (in thread_wrapper in
- syswrap-linux.c), really kill the new thread. a.k.a this avoids
- a race condition in which the thread is unkillable (via
- exit_group) because its threadgroup is not set. The race window
- is probably only a few hundred or a few thousand cycles long.
- See #226116. */
- ctst->os_state.threadgroup = ptst->os_state.threadgroup;
-
- ML_(guess_and_register_stack) (esp, ctst);
-
- /* Assume the clone will succeed, and tell any tool that wants to
- know that this thread has come into existence. We cannot defer
- it beyond this point because sys_set_thread_area, just below,
- causes tCheck to assert by making references to the new ThreadId
- if we don't state the new thread exists prior to that point.
- If the clone fails, we'll send out a ll_exit notification for it
- at the out: label below, to clean up. */
- vg_assert(VG_(owns_BigLock_LL)(ptid));
- VG_TRACK ( pre_thread_ll_create, ptid, ctid );
-
- if (flags & VKI_CLONE_SETTLS) {
- if (debug)
- VG_(printf)("clone child has SETTLS: tls info at %p: idx=%u "
- "base=%#lx limit=%x; esp=%#x fs=%x gs=%x\n",
- tlsinfo, tlsinfo->entry_number,
- tlsinfo->base_addr, tlsinfo->limit,
- ptst->arch.vex.guest_ESP,
- ctst->arch.vex.guest_FS, ctst->arch.vex.guest_GS);
- res = sys_set_thread_area(ctid, tlsinfo);
- if (sr_isError(res))
- goto out;
- }
-
- flags &= ~VKI_CLONE_SETTLS;
-
- /* start the thread with everything blocked */
- VG_(sigprocmask)(VKI_SIG_SETMASK, &blockall, &savedmask);
-
- /* Create the new thread */
- eax = do_syscall_clone_x86_linux(
- ML_(start_thread_NORETURN), stack, flags, &VG_(threads)[ctid],
- child_tidptr, parent_tidptr, NULL
- );
- res = VG_(mk_SysRes_x86_linux)( eax );
-
- VG_(sigprocmask)(VKI_SIG_SETMASK, &savedmask, NULL);
-
- out:
- if (sr_isError(res)) {
- /* clone failed */
- VG_(cleanup_thread)(&ctst->arch);
- ctst->status = VgTs_Empty;
- /* oops. Better tell the tool the thread exited in a hurry :-) */
- VG_TRACK( pre_thread_ll_exit, ctid );
- }
-
- return res;
-}
-
-
/* ---------------------------------------------------------------------
LDT/GDT simulation
------------------------------------------------------------------ */
@@ -436,11 +294,37 @@
out->LdtEnt.Words.word2 = entry_2;
}
-/* Create a zeroed-out GDT. */
-static VexGuestX86SegDescr* alloc_zeroed_x86_GDT ( void )
+/* Create initial GDT. */
+static VexGuestX86SegDescr* alloc_system_x86_GDT ( void )
{
Int nbytes = VEX_GUEST_X86_GDT_NENT * sizeof(VexGuestX86SegDescr);
- return VG_(calloc)("di.syswrap-x86.azxG.1", nbytes, 1);
+ VexGuestX86SegDescr* gdt = VG_(calloc)("di.syswrap-x86.azxG.1", nbytes, 1);
+ vki_modify_ldt_t info;
+ UShort seg;
+
+ VG_(memset)(&info, 0, sizeof(info));
+ info.entry_number = 0;
+ info.base_addr = 0;
+ info.limit = 0xfffff;
+ info.seg_32bit = 1;
+ info.contents = 0;
+ info.read_exec_only = 0;
+ info.limit_in_pages = 1;
+ info.seg_not_present = 0;
+ info.useable = 0;
+ info.reserved = 0;
+
+ asm volatile("movw %%ds, %0" : : "m" (seg));
+ if (!(seg & 4)) translate_to_hw_format(&info, &gdt[seg >> 3], 0);
+ asm volatile("movw %%ss, %0" : : "m" (seg));
+ if (!(seg & 4)) translate_to_hw_format(&info, &gdt[seg >> 3], 0);
+
+ info.contents = 2;
+
+ asm volatile("movw %%cs, %0" : : "m" (seg));
+ if (!(seg & 4)) translate_to_hw_format(&info, &gdt[seg >> 3], 0);
+
+ return gdt;
}
/* Create a zeroed-out LDT. */
@@ -486,16 +370,16 @@
if (0)
VG_(printf)("deallocate_LGDTs_for_thread: "
- "ldt = 0x%lx, gdt = 0x%lx\n",
+ "ldt = 0x%llx, gdt = 0x%llx\n",
vex->guest_LDT, vex->guest_GDT );
if (vex->guest_LDT != (HWord)NULL) {
- free_LDT_or_GDT( (VexGuestX86SegDescr*)vex->guest_LDT );
+ free_LDT_or_GDT( (VexGuestX86SegDescr*)(HWord)vex->guest_LDT );
vex->guest_LDT = (HWord)NULL;
}
if (vex->guest_GDT != (HWord)NULL) {
- free_LDT_or_GDT( (VexGuestX86SegDescr*)vex->guest_GDT );
+ free_LDT_or_GDT( (VexGuestX86SegDescr*)(HWord)vex->guest_GDT );
vex->guest_GDT = (HWord)NULL;
}
}
@@ -528,7 +412,7 @@
vg_assert(sizeof(HWord) == sizeof(VexGuestX86SegDescr*));
vg_assert(8 == sizeof(VexGuestX86SegDescr));
- ldt = (UChar*)(VG_(threads)[tid].arch.vex.guest_LDT);
+ ldt = (UChar*)(HWord)(VG_(threads)[tid].arch.vex.guest_LDT);
res = VG_(mk_SysRes_Success)( 0 );
if (ldt == NULL)
/* LDT not allocated, meaning all entries are null */
@@ -562,7 +446,7 @@
vg_assert(8 == sizeof(VexGuestX86SegDescr));
vg_assert(sizeof(HWord) == sizeof(VexGuestX86SegDescr*));
- ldt = (VexGuestX86SegDescr*)VG_(threads)[tid].arch.vex.guest_LDT;
+ ldt = (VexGuestX86SegDescr*)(HWord)VG_(threads)[tid].arch.vex.guest_LDT;
ldt_info = (vki_modify_ldt_t*)ptr;
res = VG_(mk_SysRes_Error)( VKI_EINVAL );
@@ -630,7 +514,7 @@
}
-static SysRes sys_set_thread_area ( ThreadId tid, vki_modify_ldt_t* info )
+SysRes ML_(x86_sys_set_thread_area) ( ThreadId tid, vki_modify_ldt_t* info )
{
Int idx;
VexGuestX86SegDescr* gdt;
@@ -643,11 +527,11 @@
return VG_(mk_SysRes_Error)( VKI_EFAULT );
}
- gdt = (VexGuestX86SegDescr*)VG_(threads)[tid].arch.vex.guest_GDT;
+ gdt = (VexGuestX86SegDescr*)(HWord)VG_(threads)[tid].arch.vex.guest_GDT;
/* If the thread doesn't have a GDT, allocate it now. */
if (!gdt) {
- gdt = alloc_zeroed_x86_GDT();
+ gdt = alloc_system_x86_GDT();
VG_(threads)[tid].arch.vex.guest_GDT = (HWord)gdt;
}
@@ -702,11 +586,11 @@
if (idx < 0 || idx >= VEX_GUEST_X86_GDT_NENT)
return VG_(mk_SysRes_Error)( VKI_EINVAL );
- gdt = (VexGuestX86SegDescr*)VG_(threads)[tid].arch.vex.guest_GDT;
+ gdt = (VexGuestX86SegDescr*)(HWord)VG_(threads)[tid].arch.vex.guest_GDT;
/* If the thread doesn't have a GDT, allocate it now. */
if (!gdt) {
- gdt = alloc_zeroed_x86_GDT();
+ gdt = alloc_system_x86_GDT();
VG_(threads)[tid].arch.vex.guest_GDT = (HWord)gdt;
}
@@ -738,15 +622,9 @@
}
-static void setup_child ( /*OUT*/ ThreadArchState *child,
- /*IN*/ ThreadArchState *parent,
- Bool inherit_parents_GDT )
+void ML_(x86_setup_LDT_GDT) ( /*OUT*/ ThreadArchState *child,
+ /*IN*/ ThreadArchState *parent )
{
- /* We inherit our parent's guest state. */
- child->vex = parent->vex;
- child->vex_shadow1 = parent->vex_shadow1;
- child->vex_shadow2 = parent->vex_shadow2;
-
/* We inherit our parent's LDT. */
if (parent->vex.guest_LDT == (HWord)NULL) {
/* We hope this is the common case. */
@@ -754,8 +632,8 @@
} else {
/* No luck .. we have to take a copy of the parent's. */
child->vex.guest_LDT = (HWord)alloc_zeroed_x86_LDT();
- copy_LDT_from_to( (VexGuestX86SegDescr*)parent->vex.guest_LDT,
- (VexGuestX86SegDescr*)child->vex.guest_LDT );
+ copy_LDT_from_to( (VexGuestX86SegDescr*)(HWord)parent->vex.guest_LDT,
+ (VexGuestX86SegDescr*)(HWord)child->vex.guest_LDT );
}
/* Either we start with an empty GDT (the usual case) or inherit a
@@ -763,10 +641,10 @@
only). */
child->vex.guest_GDT = (HWord)NULL;
- if (inherit_parents_GDT && parent->vex.guest_GDT != (HWord)NULL) {
- child->vex.guest_GDT = (HWord)alloc_zeroed_x86_GDT();
- copy_GDT_from_to( (VexGuestX86SegDescr*)parent->vex.guest_GDT,
- (VexGuestX86SegDescr*)child->vex.guest_GDT );
+ if (parent->vex.guest_GDT != (HWord)NULL) {
+ child->vex.guest_GDT = (HWord)alloc_system_x86_GDT();
+ copy_GDT_from_to( (VexGuestX86SegDescr*)(HWord)parent->vex.guest_GDT,
+ (VexGuestX86SegDescr*)(HWord)child->vex.guest_GDT );
}
}
@@ -787,7 +665,6 @@
DECL_TEMPLATE(x86_linux, sys_fstatat64);
DECL_TEMPLATE(x86_linux, sys_fstat64);
DECL_TEMPLATE(x86_linux, sys_lstat64);
-DECL_TEMPLATE(x86_linux, sys_clone);
DECL_TEMPLATE(x86_linux, old_mmap);
DECL_TEMPLATE(x86_linux, sys_mmap2);
DECL_TEMPLATE(x86_linux, sys_sigreturn);
@@ -835,137 +712,6 @@
}
}
-PRE(sys_clone)
-{
- UInt cloneflags;
- Bool badarg = False;
-
- PRINT("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )",ARG1,ARG2,ARG3,ARG4,ARG5);
- PRE_REG_READ2(int, "clone",
- unsigned long, flags,
- void *, child_stack);
-
- if (ARG1 & VKI_CLONE_PARENT_SETTID) {
- if (VG_(tdict).track_pre_reg_read) {
- PRA3("clone", int *, parent_tidptr);
- }
- PRE_MEM_WRITE("clone(parent_tidptr)", ARG3, sizeof(Int));
- if (!VG_(am_is_valid_for_client)(ARG3, sizeof(Int),
- VKI_PROT_WRITE)) {
- badarg = True;
- }
- }
- if (ARG1 & VKI_CLONE_SETTLS) {
- if (VG_(tdict).track_pre_reg_read) {
- PRA4("clone", vki_modify_ldt_t *, tlsinfo);
- }
- PRE_MEM_READ("clone(tlsinfo)", ARG4, sizeof(vki_modify_ldt_t));
- if (!VG_(am_is_valid_for_client)(ARG4, sizeof(vki_modify_ldt_t),
- VKI_PROT_READ)) {
- badarg = True;
- }
- }
- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) {
- if (VG_(tdict).track_pre_reg_read) {
- PRA5("clone", int *, child_tidptr);
- }
- PRE_MEM_WRITE("clone(child_tidptr)", ARG5, sizeof(Int));
- if (!VG_(am_is_valid_for_client)(ARG5, sizeof(Int),
- VKI_PROT_WRITE)) {
- badarg = True;
- }
- }
-
- if (badarg) {
- SET_STATUS_Failure( VKI_EFAULT );
- return;
- }
-
- cloneflags = ARG1;
-
- if (!ML_(client_signal_OK)(ARG1 & VKI_CSIGNAL)) {
- SET_STATUS_Failure( VKI_EINVAL );
- return;
- }
-
- /* Be ultra-paranoid and filter out any clone-variants we don't understand:
- - ??? specifies clone flags of 0x100011
- - ??? specifies clone flags of 0x1200011.
- - NPTL specifies clone flags of 0x7D0F00.
- - The Quadrics Elan3 driver specifies clone flags of 0xF00.
- - Newer Quadrics Elan3 drivers with NTPL support specify 0x410F00.
- Everything else is rejected.
- */
- if (
- 1 ||
- /* 11 Nov 05: for the time being, disable this ultra-paranoia.
- The switch below probably does a good enough job. */
- (cloneflags == 0x100011 || cloneflags == 0x1200011
- || cloneflags == 0x7D0F00
- || cloneflags == 0x790F00
- || cloneflags == 0x3D0F00
- || cloneflags == 0x410F00
- || cloneflags == 0xF00
- || cloneflags == 0xF21)) {
- /* OK */
- }
- else {
- /* Nah. We don't like it. Go away. */
- goto reject;
- }
-
- /* Only look at the flags we really care about */
- switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS
- | VKI_CLONE_FILES | VKI_CLONE_VFORK)) {
- case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES:
- /* thread creation */
- SET_STATUS_from_SysRes(
- do_clone(tid,
- ARG1, /* flags */
- (Addr)ARG2, /* child ESP */
- (Int *)ARG3, /* parent_tidptr */
- (Int *)ARG5, /* child_tidptr */
- (vki_modify_ldt_t *)ARG4)); /* set_tls */
- break;
-
- case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */
- /* FALLTHROUGH - assume vfork == fork */
- cloneflags &= ~(VKI_CLONE_VFORK | VKI_CLONE_VM);
-
- case 0: /* plain fork */
- SET_STATUS_from_SysRes(
- ML_(do_fork_clone)(tid,
- cloneflags, /* flags */
- (Int *)ARG3, /* parent_tidptr */
- (Int *)ARG5)); /* child_tidptr */
- break;
-
- default:
- reject:
- /* should we just ENOSYS? */
- VG_(message)(Vg_UserMsg, "\n");
- VG_(message)(Vg_UserMsg, "Unsupported clone() flags: 0x%lx\n", ARG1);
- VG_(message)(Vg_UserMsg, "\n");
- VG_(message)(Vg_UserMsg, "The only supported clone() uses are:\n");
- VG_(message)(Vg_UserMsg, " - via a threads library (LinuxThreads or NPTL)\n");
- VG_(message)(Vg_UserMsg, " - via the implementation of fork or vfork\n");
- VG_(message)(Vg_UserMsg, " - for the Quadrics Elan3 user-space driver\n");
- VG_(unimplemented)
- ("Valgrind does not support general clone().");
- }
-
- if (SUCCESS) {
- if (ARG1 & VKI_CLONE_PARENT_SETTID)
- POST_MEM_WRITE(ARG3, sizeof(Int));
- if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID))
- POST_MEM_WRITE(ARG5, sizeof(Int));
-
- /* Thread creation was successful; let the child have the chance
- to run */
- *flags |= SfYieldAfter;
- }
-}
-
PRE(sys_sigreturn)
{
/* See comments on PRE(sys_rt_sigreturn) in syswrap-amd64-linux.c for
@@ -1063,7 +809,7 @@
PRE_MEM_READ( "set_thread_area(u_info)", ARG1, sizeof(vki_modify_ldt_t) );
/* "do" the syscall ourselves; the kernel never sees it */
- SET_STATUS_from_SysRes( sys_set_thread_area( tid, (void *)ARG1 ) );
+ SET_STATUS_from_SysRes( ML_(x86_sys_set_thread_area)( tid, (void *)ARG1 ) );
}
PRE(sys_get_thread_area)
@@ -1154,6 +900,9 @@
POST(sys_ptrace)
{
switch (ARG1) {
+ case VKI_PTRACE_TRACEME:
+ ML_(linux_POST_traceme)(tid);
+ break;
case VKI_PTRACE_PEEKTEXT:
case VKI_PTRACE_PEEKDATA:
case VKI_PTRACE_PEEKUSR:
@@ -1553,7 +1302,7 @@
GENX_(__NR_fsync, sys_fsync), // 118
PLAX_(__NR_sigreturn, sys_sigreturn), // 119 ?/Linux
- PLAX_(__NR_clone, sys_clone), // 120
+ LINX_(__NR_clone, sys_clone), // 120
//zz // (__NR_setdomainname, sys_setdomainname), // 121 */*(?)
GENXY(__NR_uname, sys_newuname), // 122
PLAX_(__NR_modify_ldt, sys_modify_ldt), // 123
diff --git a/coregrind/m_syswrap/syswrap-x86-solaris.c b/coregrind/m_syswrap/syswrap-x86-solaris.c
index ed57729..2207cdc 100644
--- a/coregrind/m_syswrap/syswrap-x86-solaris.c
+++ b/coregrind/m_syswrap/syswrap-x86-solaris.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2015 Petr Pavlu
+ Copyright (C) 2011-2017 Petr Pavlu
setup@dagobah.cz
This program is free software; you can redistribute it and/or
@@ -576,7 +576,7 @@
{
if (!vex->guest_GDT)
return;
- VG_(free)((void*)vex->guest_GDT);
+ VG_(free)((void *) (HWord) vex->guest_GDT);
vex->guest_GDT = 0;
}
@@ -586,7 +586,8 @@
{
ThreadState *tst = VG_(get_ThreadState)(tid);
Addr base = tst->os_state.thrptr;
- VexGuestX86SegDescr *gdt = (VexGuestX86SegDescr*)tst->arch.vex.guest_GDT;
+ VexGuestX86SegDescr *gdt
+ = (VexGuestX86SegDescr *) (HWord) tst->arch.vex.guest_GDT;
VexGuestX86SegDescr desc;
vg_assert(gdt);
diff --git a/coregrind/m_syswrap/syswrap-xen.c b/coregrind/m_syswrap/syswrap-xen.c
index 20341c4..1e374ab 100644
--- a/coregrind/m_syswrap/syswrap-xen.c
+++ b/coregrind/m_syswrap/syswrap-xen.c
@@ -728,6 +728,8 @@
case 0x00000008:
case 0x00000009:
case 0x0000000a:
+ case 0x0000000b:
+ case 0x0000000c:
break;
default:
bad_intf_version(tid, layout, arrghs, status, flags,
@@ -789,6 +791,12 @@
(Addr)domctl->u.hvmcontext_partial.buffer.p,
VKI_HVM_SAVE_LENGTH(CPU));
break;
+ case VKI_HVM_SAVE_CODE(MTRR):
+ if ( domctl->u.hvmcontext_partial.buffer.p )
+ PRE_MEM_WRITE("XEN_DOMCTL_gethvmcontext_partial *buffer",
+ (Addr)domctl->u.hvmcontext_partial.buffer.p,
+ VKI_HVM_SAVE_LENGTH(MTRR));
+ break;
default:
bad_subop(tid, layout, arrghs, status, flags,
"__HYPERVISOR_domctl_gethvmcontext_partial type",
@@ -806,20 +814,114 @@
break;
case VKI_XEN_DOMCTL_test_assign_device:
- __PRE_XEN_DOMCTL_READ(test_assign_device, assign_device, machine_sbdf);
+ switch (domctl->interface_version) {
+ case 0x00000007: /* pre-4.6 */
+ case 0x00000008:
+ case 0x00000009:
+ case 0x0000000a:
+ __PRE_XEN_DOMCTL_READ(test_assign_device, assign_device_00000007, machine_sbdf);
+ break;
+ case 0x0000000b:
+ __PRE_XEN_DOMCTL_READ(test_assign_device, assign_device_0000000b, dev);
+ __PRE_XEN_DOMCTL_READ(test_assign_device, assign_device_0000000b, flag);
+ switch (domctl->u.assign_device_0000000b.dev) {
+ case VKI_XEN_DOMCTL_DEV_PCI:
+ __PRE_XEN_DOMCTL_READ(test_assign_device, assign_device_0000000b, u.pci);
+ break;
+ case VKI_XEN_DOMCTL_DEV_DT:
+ __PRE_XEN_DOMCTL_READ(test_assign_device, assign_device_0000000b, u.dt);
+ PRE_MEM_READ("XEN_DOMTCL_test_assign_device.dt",
+ (Addr)domctl->u.assign_device_0000000b.u.dt.path.p,
+ domctl->u.assign_device_0000000b.u.dt.size);
+ break;
+ default:
+ bad_subop(tid, layout, arrghs, status, flags,
+ "__HYPERVISOR_domctl_test_assign_device dev",
+ domctl->u.assign_device_0000000b.dev);
+ break;
+ }
+ break;
+ }
break;
case VKI_XEN_DOMCTL_assign_device:
- __PRE_XEN_DOMCTL_READ(assign_device, assign_device, machine_sbdf);
+ switch (domctl->interface_version) {
+ case 0x00000007: /* pre-4.6 */
+ case 0x00000008:
+ case 0x00000009:
+ case 0x0000000a:
+ __PRE_XEN_DOMCTL_READ(assign_device, assign_device_00000007, machine_sbdf);
+ break;
+ case 0x0000000b:
+ __PRE_XEN_DOMCTL_READ(assign_device, assign_device_0000000b, dev);
+ __PRE_XEN_DOMCTL_READ(assign_device, assign_device_0000000b, flag);
+ switch (domctl->u.assign_device_0000000b.dev) {
+ case VKI_XEN_DOMCTL_DEV_PCI:
+ __PRE_XEN_DOMCTL_READ(assign_device, assign_device_0000000b, u.pci);
+ break;
+ case VKI_XEN_DOMCTL_DEV_DT:
+ __PRE_XEN_DOMCTL_READ(assign_device, assign_device_0000000b, u.dt);
+ PRE_MEM_READ("XEN_DOMTCL_assign_device.dt",
+ (Addr)domctl->u.assign_device_0000000b.u.dt.path.p,
+ domctl->u.assign_device_0000000b.u.dt.size);
+ break;
+ default:
+ bad_subop(tid, layout, arrghs, status, flags,
+ "__HYPERVISOR_domctl_assign_device dev",
+ domctl->u.assign_device_0000000b.dev);
+ break;
+ }
+ break;
+ }
break;
case VKI_XEN_DOMCTL_deassign_device:
- __PRE_XEN_DOMCTL_READ(deassign_device, assign_device, machine_sbdf);
+ switch (domctl->interface_version) {
+ case 0x00000007: /* pre-4.6 */
+ case 0x00000008:
+ case 0x00000009:
+ case 0x0000000a:
+ __PRE_XEN_DOMCTL_READ(deassign_device, assign_device_00000007, machine_sbdf);
+ break;
+ case 0x0000000b:
+ __PRE_XEN_DOMCTL_READ(deassign_device, assign_device_0000000b, dev);
+ __PRE_XEN_DOMCTL_READ(deassign_device, assign_device_0000000b, flag);
+ switch (domctl->u.assign_device_0000000b.dev) {
+ case VKI_XEN_DOMCTL_DEV_PCI:
+ __PRE_XEN_DOMCTL_READ(deassign_device, assign_device_0000000b, u.pci);
+ break;
+ case VKI_XEN_DOMCTL_DEV_DT:
+ __PRE_XEN_DOMCTL_READ(deassign_device, assign_device_0000000b, u.dt);
+ PRE_MEM_READ("XEN_DOMTCL_assign_device.dt",
+ (Addr)domctl->u.assign_device_0000000b.u.dt.path.p,
+ domctl->u.assign_device_0000000b.u.dt.size);
+ break;
+ default:
+ bad_subop(tid, layout, arrghs, status, flags,
+ "__HYPERVISOR_domctl_deassign_device dev",
+ domctl->u.assign_device_0000000b.dev);
+ break;
+ }
+ break;
+ }
break;
case VKI_XEN_DOMCTL_settscinfo:
- __PRE_XEN_DOMCTL_READ(settscinfo, tsc_info, info.tsc_mode);
- __PRE_XEN_DOMCTL_READ(settscinfo, tsc_info, info.gtsc_khz);
- __PRE_XEN_DOMCTL_READ(settscinfo, tsc_info, info.incarnation);
- __PRE_XEN_DOMCTL_READ(settscinfo, tsc_info, info.elapsed_nsec);
+ switch (domctl->interface_version) {
+ case 0x00000007: /* pre-4.6 */
+ case 0x00000008:
+ case 0x00000009:
+ case 0x0000000a:
+ __PRE_XEN_DOMCTL_READ(settscinfo, tsc_info_00000007, info.tsc_mode);
+ __PRE_XEN_DOMCTL_READ(settscinfo, tsc_info_00000007, info.gtsc_khz);
+ __PRE_XEN_DOMCTL_READ(settscinfo, tsc_info_00000007, info.incarnation);
+ __PRE_XEN_DOMCTL_READ(settscinfo, tsc_info_00000007, info.elapsed_nsec);
+ break;
+ case 0x0000000b:
+ __PRE_XEN_DOMCTL_READ(settscinfo, tsc_info_0000000b, tsc_mode);
+ __PRE_XEN_DOMCTL_READ(settscinfo, tsc_info_0000000b, gtsc_khz);
+ __PRE_XEN_DOMCTL_READ(settscinfo, tsc_info_0000000b, incarnation);
+ __PRE_XEN_DOMCTL_READ(settscinfo, tsc_info_0000000b, elapsed_nsec);
+ break;
+ }
break;
case VKI_XEN_DOMCTL_irq_permission:
@@ -1136,8 +1238,20 @@
break;
case VKI_XEN_DOMCTL_mem_event_op:
- PRE_XEN_DOMCTL_READ(mem_event_op, op);
- PRE_XEN_DOMCTL_READ(mem_event_op, mode);
+ //case VKI_XEN_DOMCTL_vm_event_op: /* name change in 4.6 */
+ switch (domctl->interface_version) {
+ case 0x00000007: /* pre-4.6 */
+ case 0x00000008:
+ case 0x00000009:
+ case 0x0000000a:
+ __PRE_XEN_DOMCTL_READ(mem_event_op, mem_event_op_00000007, op);
+ __PRE_XEN_DOMCTL_READ(mem_event_op, mem_event_op_00000007, mode);
+ break;
+ case 0x0000000b:
+ __PRE_XEN_DOMCTL_READ(vm_event_op, vm_event_op_0000000b, op);
+ __PRE_XEN_DOMCTL_READ(vm_event_op, vm_event_op_0000000b, mode);
+ break;
+ }
break;
case VKI_XEN_DOMCTL_debug_op:
@@ -1161,6 +1275,30 @@
domctl->u.vcpu_msrs.msr_count);
break;
+ case VKI_XEN_DOMCTL_monitor_op:
+ switch (domctl->interface_version) {
+ case 0x000000b:
+ if (domctl->u.monitor_op_0000000b.op == VKI_XEN_DOMCTL_MONITOR_OP_ENABLE ||
+ domctl->u.monitor_op_0000000b.op == VKI_XEN_DOMCTL_MONITOR_OP_ENABLE) {
+ switch (domctl->u.monitor_op_0000000b.event) {
+ case VKI_XEN_DOMCTL_MONITOR_EVENT_WRITE_CTRLREG:
+ __PRE_XEN_DOMCTL_READ(monitor_op, monitor_op_0000000b, u.mov_to_cr);
+ break;
+ case VKI_XEN_DOMCTL_MONITOR_EVENT_MOV_TO_MSR:
+ __PRE_XEN_DOMCTL_READ(monitor_op, monitor_op_0000000b, u.mov_to_msr);
+ break;
+ case VKI_XEN_DOMCTL_MONITOR_EVENT_GUEST_REQUEST:
+ __PRE_XEN_DOMCTL_READ(monitor_op, monitor_op_0000000b, u.guest_request);
+ break;
+ case VKI_XEN_DOMCTL_MONITOR_OP_GET_CAPABILITIES:
+ break;
+ }
+ }
+
+ break;
+ }
+ break;
+
default:
bad_subop(tid, layout, arrghs, status, flags,
"__HYPERVISOR_domctl", domctl->cmd);
@@ -1669,6 +1807,7 @@
case 0x00000008:
case 0x00000009:
case 0x0000000a:
+ case 0x0000000b:
break;
default:
return;
@@ -1720,10 +1859,23 @@
break;
case VKI_XEN_DOMCTL_gettscinfo:
- __POST_XEN_DOMCTL_WRITE(settscinfo, tsc_info, info.tsc_mode);
- __POST_XEN_DOMCTL_WRITE(settscinfo, tsc_info, info.gtsc_khz);
- __POST_XEN_DOMCTL_WRITE(settscinfo, tsc_info, info.incarnation);
- __POST_XEN_DOMCTL_WRITE(settscinfo, tsc_info, info.elapsed_nsec);
+ switch (domctl->interface_version) {
+ case 0x00000007: /* pre-4.6 */
+ case 0x00000008:
+ case 0x00000009:
+ case 0x0000000a:
+ __POST_XEN_DOMCTL_WRITE(gettscinfo, tsc_info_00000007, out_info);
+ POST_MEM_WRITE((Addr)domctl->u.tsc_info_00000007.out_info.p,
+ sizeof(vki_xen_guest_tsc_info_t));
+ break;
+ case 0x0000000b:
+ __POST_XEN_DOMCTL_WRITE(gettscinfo, tsc_info_0000000b, tsc_mode);
+ __POST_XEN_DOMCTL_WRITE(gettscinfo, tsc_info_0000000b, gtsc_khz);
+ __POST_XEN_DOMCTL_WRITE(gettscinfo, tsc_info_0000000b, incarnation);
+ __POST_XEN_DOMCTL_WRITE(gettscinfo, tsc_info_0000000b, elapsed_nsec);
+ break;
+ }
+ break;
break;
case VKI_XEN_DOMCTL_getvcpuinfo:
@@ -1959,10 +2111,42 @@
break;
case VKI_XEN_DOMCTL_mem_event_op:
- POST_XEN_DOMCTL_WRITE(mem_event_op, port);
+ //case VKI_XEN_DOMCTL_vm_event_op: /* name change in 4.6 */
+ switch (domctl->interface_version) {
+ case 0x00000007: /* pre-4.6 */
+ case 0x00000008:
+ case 0x00000009:
+ case 0x0000000a:
+ __POST_XEN_DOMCTL_WRITE(mem_event_op, mem_event_op_00000007, port);
+ break;
+ case 0x0000000b:
+ __POST_XEN_DOMCTL_WRITE(vm_event_op, vm_event_op_0000000b, port);
+ break;
+ }
+ break;
- break;
+ case VKI_XEN_DOMCTL_monitor_op:
+ switch (domctl->interface_version) {
+ case 0x000000b:
+ if (domctl->u.monitor_op_0000000b.op == VKI_XEN_DOMCTL_MONITOR_OP_GET_CAPABILITIES) {
+ switch(domctl->u.monitor_op_0000000b.event) {
+ case VKI_XEN_DOMCTL_MONITOR_EVENT_WRITE_CTRLREG:
+ __POST_XEN_DOMCTL_WRITE(monitor_op, monitor_op_0000000b, u.mov_to_cr);
+ break;
+ case VKI_XEN_DOMCTL_MONITOR_EVENT_MOV_TO_MSR:
+ __POST_XEN_DOMCTL_WRITE(monitor_op, monitor_op_0000000b, u.mov_to_msr);
+ break;
+ case VKI_XEN_DOMCTL_MONITOR_EVENT_GUEST_REQUEST:
+ __POST_XEN_DOMCTL_WRITE(monitor_op, monitor_op_0000000b, u.guest_request);
+ break;
+ }
+ }
+
+ break;
+ }
+ break;
}
+
#undef POST_XEN_DOMCTL_WRITE
#undef __POST_XEN_DOMCTL_WRITE
}
@@ -1986,7 +2170,7 @@
case VKI_XEN_HVMOP_set_mem_type:
case VKI_XEN_HVMOP_set_mem_access:
case VKI_XEN_HVMOP_inject_trap:
- /* No output paramters */
+ /* No output parameters */
break;
case VKI_XEN_HVMOP_get_param:
diff --git a/coregrind/m_threadstate.c b/coregrind/m_threadstate.c
index 6cea270..6edf226 100644
--- a/coregrind/m_threadstate.c
+++ b/coregrind/m_threadstate.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -47,6 +47,8 @@
ThreadState *VG_(threads);
UInt VG_N_THREADS;
+ThreadState *VG_(inner_threads);
+
/*------------------------------------------------------------*/
/*--- Operations. ---*/
/*------------------------------------------------------------*/
@@ -68,6 +70,7 @@
sizeof(VG_(threads)[tid].os_state.exitcode),
""));
}
+ INNER_REQUEST(VALGRIND_INNER_THREADS(VG_(threads)));
}
const HChar* VG_(name_of_ThreadStatus) ( ThreadStatus status )
diff --git a/coregrind/m_tooliface.c b/coregrind/m_tooliface.c
index 38bc7c2..31b5f6c 100644
--- a/coregrind/m_tooliface.c
+++ b/coregrind/m_tooliface.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Nicholas Nethercote
+ Copyright (C) 2000-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_trampoline.S b/coregrind/m_trampoline.S
index ef7c4e6..a532071 100644
--- a/coregrind/m_trampoline.S
+++ b/coregrind/m_trampoline.S
@@ -7,9 +7,9 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
- Copyright (C) 2006-2015 OpenWorks LLP
+ Copyright (C) 2006-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -1217,7 +1217,7 @@
.type VG_(s390x_linux_REDIR_FOR_index),@function
VG_(s390x_linux_REDIR_FOR_index):
#
-# %r2 = addess of string
+# %r2 = address of string
# %r3 = character to find
#
lghi %r0,255
@@ -1269,24 +1269,43 @@
/* There's no particular reason that this needs to be handwritten
assembly, but since that's what this file contains, here's a
- simple strlen implementation (written in C and compiled by gcc.)
+ simple index() and strlen() implementations.
*/
+
+.set push
+.set noreorder
+
+.global VG_(mips32_linux_REDIR_FOR_index)
+.type VG_(mips32_linux_REDIR_FOR_index), @function
+VG_(mips32_linux_REDIR_FOR_index):
+ move $v0, $a0
+ index_loop:
+ lbu $t0, 0($v0)
+ beq $t0, $a1, index_end
+ nop
+ bne $t0, $zero, index_loop
+ addiu $v0, $v0, 1
+ move $v0, $zero
+ index_end:
+ jr $ra
+ nop
+.size VG_(mips32_linux_REDIR_FOR_index), .-VG_(mips32_linux_REDIR_FOR_index)
+
.global VG_(mips32_linux_REDIR_FOR_strlen)
.type VG_(mips32_linux_REDIR_FOR_strlen), @function
VG_(mips32_linux_REDIR_FOR_strlen):
- li $v0, 0
- //la $a0, string
- j strlen_cond
+ move $v0, $a0
strlen_loop:
- addiu $v0, $v0, 1
- addiu $a0, $a0, 1
- strlen_cond:
- lbu $t0, ($a0)
+ lbu $t0, 0($a0)
bne $t0, $zero, strlen_loop
- jr $ra
-
+ addiu $a0, $a0, 1
+ subu $v0, $a0, $v0
+ jr $ra
+ addiu $v0, $v0, -1
.size VG_(mips32_linux_REDIR_FOR_strlen), .-VG_(mips32_linux_REDIR_FOR_strlen)
+.set pop
+
.global VG_(trampoline_stuff_end)
VG_(trampoline_stuff_end):
@@ -1319,30 +1338,43 @@
/* There's no particular reason that this needs to be handwritten
assembly, but since that's what this file contains, here's a
- simple strlen implementation (written in C and compiled by gcc.)
+ simple index() and strlen() implementations.
*/
+
+.set push
+.set noreorder
+
+.global VG_(mips64_linux_REDIR_FOR_index)
+.type VG_(mips64_linux_REDIR_FOR_index), @function
+VG_(mips64_linux_REDIR_FOR_index):
+ move $v0, $a0
+ index_loop:
+ lbu $t0, 0($v0)
+ beq $t0, $a1, index_end
+ nop
+ bne $t0, $zero, index_loop
+ daddiu $v0, $v0, 1
+ move $v0, $zero
+ index_end:
+ jr $ra
+ nop
+.size VG_(mips64_linux_REDIR_FOR_index), .-VG_(mips64_linux_REDIR_FOR_index)
+
.global VG_(mips64_linux_REDIR_FOR_strlen)
.type VG_(mips64_linux_REDIR_FOR_strlen), @function
VG_(mips64_linux_REDIR_FOR_strlen):
- lbu $12, 0($4)
- li $13, 0
- beq $12, $0, M01
- nop
-
-M02:
- addiu $13, $13, 1
- addiu $4, $4, 1
- lbu $12, 0($4)
- bne $12, $0, M02
- nop
-
-M01:
- move $2, $13
- jr $31
- nop
-
+ move $v0, $a0
+ strlen_loop:
+ lbu $t0, 0($a0)
+ bne $t0, $zero, strlen_loop
+ daddiu $a0, $a0, 1
+ dsubu $v0, $a0, $v0
+ jr $ra
+ daddiu $v0, $v0, -1
.size VG_(mips64_linux_REDIR_FOR_strlen), .-VG_(mips64_linux_REDIR_FOR_strlen)
+.set pop
+
.global VG_(trampoline_stuff_end)
VG_(trampoline_stuff_end):
@@ -1353,78 +1385,6 @@
# undef UD2_1024
# undef UD2_PAGE
-/*---------------------- tilegx-linux ----------------------*/
-#else
-#if defined(VGP_tilegx_linux)
-
-# define UD2_16 ill ; ill
-# define UD2_64 UD2_16 ; UD2_16 ; UD2_16 ; UD2_16
-# define UD2_256 UD2_64 ; UD2_64 ; UD2_64 ; UD2_64
-# define UD2_1024 UD2_256 ; UD2_256 ; UD2_256 ; UD2_256
-# define UD2_4K UD2_1024 ; UD2_1024 ; UD2_1024 ; UD2_1024
-# define UD2_16K UD2_4K ; UD2_4K ; UD2_4K ; UD2_4K
-# define UD2_PAGE UD2_16K ; UD2_16K ; UD2_16K ; UD2_16K
- /* a leading page of unexecutable code */
- UD2_PAGE
-
-.global VG_(trampoline_stuff_start)
-VG_(trampoline_stuff_start):
-
-.global VG_(tilegx_linux_SUBST_FOR_rt_sigreturn)
-VG_(tilegx_linux_SUBST_FOR_rt_sigreturn):
- /* This is a very specific sequence which GDB uses to
- recognize signal handler frames. */
- moveli r10, __NR_rt_sigreturn
- swint1
- ill
-
-.global VG_(tilegx_linux_REDIR_FOR_vgettimeofday)
-.type VG_(tilegx_linux_REDIR_FOR_vgettimeofday), @function
-VG_(tilegx_linux_REDIR_FOR_vgettimeofday):
- moveli r10, __NR_gettimeofday
- swint1
- jrp lr
-.size VG_(tilegx_linux_REDIR_FOR_vgettimeofday), .-VG_(tilegx_linux_REDIR_FOR_vgettimeofday)
-
-.global VG_(tilegx_linux_REDIR_FOR_vtime)
-.type VG_(tilegx_linux_REDIR_FOR_vtime), @function
-VG_(tilegx_linux_REDIR_FOR_vtime):
- moveli r10, __NR_gettimeofday
- swint1
- jrp lr
-.size VG_(tilegx_linux_REDIR_FOR_vtime), .-VG_(tilegx_linux_REDIR_FOR_vtime)
-
-.global VG_(tilegx_linux_REDIR_FOR_strlen)
-.type VG_(tilegx_linux_REDIR_FOR_strlen), @function
-VG_(tilegx_linux_REDIR_FOR_strlen):
- {
- movei r1, 0
- beqz r0, 2f
- }
-1: {
- addi r1, r1, 1
- ld1s_add r2, r0, 1
- }
- bnezt r2, 1b
- addi r1, r1, -1
-2: move r0, r1
- jrp lr
-.size VG_(tilegx_linux_REDIR_FOR_strlen), .-VG_(tilegx_linux_REDIR_FOR_strlen)
-
-.global VG_(trampoline_stuff_end)
-VG_(trampoline_stuff_end):
-
- /* and a trailing page of unexecutable code */
- UD2_PAGE
-
-# undef UD2_16
-# undef UD2_64
-# undef UD2_256
-# undef UD2_1024
-# undef UD2_4K
-# undef UD2_16K
-# undef UD2_PAGE
-
/*---------------- x86-solaris ----------------*/
#else
#if defined(VGP_x86_solaris)
@@ -1495,7 +1455,7 @@
movq %rdi, %rdx /* copy s1 */
1:
movzbl (%rsi), %eax /* load one input character */
- movb %al, (%rdx) /* copy to output/s2 */
+ movb %al, (%rdx) /* copy to output/s1 */
incq %rsi /* skip to the next output character */
incq %rdx /* skip to the next input character */
testb %al, %al /* is the copied character null? */
@@ -1516,7 +1476,7 @@
testq %rdx, %rdx /* is the remaining size zero? */
jz 3f /* yes, all done */
movzbl (%rsi), %eax /* load one input character */
- movb %al, (%rcx) /* copy to output/s2 */
+ movb %al, (%rcx) /* copy to output/s1 */
decq %rdx /* decrement the remaining size */
incq %rsi /* skip to the next output character */
incq %rcx /* skip to the next input character */
@@ -1621,7 +1581,6 @@
#endif
#endif
#endif
-#endif
/* Let the linker know we don't need an executable stack */
MARK_STACK_NO_EXEC
diff --git a/coregrind/m_translate.c b/coregrind/m_translate.c
index 2d6d3ba..55c845d 100644
--- a/coregrind/m_translate.c
+++ b/coregrind/m_translate.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -760,7 +760,7 @@
static Bool translations_allowable_from_seg ( NSegment const* seg, Addr addr )
{
# if defined(VGA_x86) || defined(VGA_s390x) || defined(VGA_mips32) \
- || defined(VGA_mips64) || defined(VGA_tilegx)
+ || defined(VGA_mips64)
Bool allowR = True;
# else
Bool allowR = False;
@@ -1663,30 +1663,54 @@
vex_abiinfo.guest_amd64_assume_fs_is_const = True;
vex_abiinfo.guest_amd64_assume_gs_is_const = True;
# endif
+
# if defined(VGP_amd64_darwin)
vex_abiinfo.guest_amd64_assume_gs_is_const = True;
# endif
+
+# if defined(VGP_amd64_solaris)
+ vex_abiinfo.guest_amd64_assume_fs_is_const = True;
+# endif
+
# if defined(VGP_ppc32_linux)
vex_abiinfo.guest_ppc_zap_RZ_at_blr = False;
vex_abiinfo.guest_ppc_zap_RZ_at_bl = NULL;
# endif
+
# if defined(VGP_ppc64be_linux)
vex_abiinfo.guest_ppc_zap_RZ_at_blr = True;
vex_abiinfo.guest_ppc_zap_RZ_at_bl = const_True;
vex_abiinfo.host_ppc_calls_use_fndescrs = True;
# endif
+
# if defined(VGP_ppc64le_linux)
vex_abiinfo.guest_ppc_zap_RZ_at_blr = True;
vex_abiinfo.guest_ppc_zap_RZ_at_bl = const_True;
vex_abiinfo.host_ppc_calls_use_fndescrs = False;
# endif
-# if defined(VGP_amd64_solaris)
- vex_abiinfo.guest_amd64_assume_fs_is_const = True;
-# endif
+
# if defined(VGP_mips32_linux) || defined(VGP_mips64_linux)
ThreadArchState* arch = &VG_(threads)[tid].arch;
vex_abiinfo.guest_mips_fp_mode64 =
!!(arch->vex.guest_CP0_status & MIPS_CP0_STATUS_FR);
+ /* Compute guest__use_fallback_LLSC, overiding any settings of
+ VG_(clo_fallback_llsc) that we know would cause the guest to
+ fail (loop). */
+ if (VEX_MIPS_COMP_ID(vex_archinfo.hwcaps) == VEX_PRID_COMP_CAVIUM) {
+ /* We must use the fallback scheme. */
+ vex_abiinfo.guest__use_fallback_LLSC = True;
+ } else {
+ vex_abiinfo.guest__use_fallback_LLSC
+ = SimHintiS(SimHint_fallback_llsc, VG_(clo_sim_hints));
+ }
+# endif
+
+# if defined(VGP_arm64_linux)
+ vex_abiinfo.guest__use_fallback_LLSC
+ = /* The user asked explicitly */
+ SimHintiS(SimHint_fallback_llsc, VG_(clo_sim_hints))
+ || /* we autodetected that it is necessary */
+ vex_archinfo.arm64_requires_fallback_LLSC;
# endif
/* Set up closure args. */
diff --git a/coregrind/m_transtab.c b/coregrind/m_transtab.c
index 8b8969a..fa0a868 100644
--- a/coregrind/m_transtab.c
+++ b/coregrind/m_transtab.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_ume/elf.c b/coregrind/m_ume/elf.c
index 8a998db..21eb52b 100644
--- a/coregrind/m_ume/elf.c
+++ b/coregrind/m_ume/elf.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -578,7 +578,7 @@
/* Later .. it appears ppc32-linux tries to put [vdso] at 1MB,
which totally screws things up, because nothing else can go
there. The size of [vdso] is around 2 or 3 pages, so bump
- the hacky load addess along by 8 * VKI_PAGE_SIZE to be safe. */
+ the hacky load address along by 8 * VKI_PAGE_SIZE to be safe. */
/* Later .. on mips64 we can't use 0x108000, because mapelf will
fail. */
# if defined(VGP_mips64_linux)
diff --git a/coregrind/m_ume/macho.c b/coregrind/m_ume/macho.c
index efe0f59..7b988b6 100644
--- a/coregrind/m_ume/macho.c
+++ b/coregrind/m_ume/macho.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Apple Inc.
+ Copyright (C) 2005-2017 Apple Inc.
Greg Parker gparker@apple.com
This program is free software; you can redistribute it and/or
@@ -67,6 +67,15 @@
#define SECTION section_64
#endif
+typedef struct load_info_t {
+ vki_uint8_t *stack_start; // allocated thread stack (hot end)
+ vki_uint8_t *stack_end; // allocated thread stack (cold end)
+ vki_uint8_t *text; // start of text segment (i.e. the mach headers)
+ vki_uint8_t *entry; // static entry point
+ vki_uint8_t *linker_entry; // dylinker entry point
+ Addr linker_offset; // dylinker text offset
+ vki_size_t max_addr; // biggest address reached while loading segments
+} load_info_t;
static void print(const HChar *str)
{
@@ -99,30 +108,24 @@
static int
load_thin_file(int fd, vki_off_t offset, vki_off_t size, unsigned long filetype,
- const HChar *filename,
- vki_uint8_t **out_stack_start, vki_uint8_t **out_stack_end,
- vki_uint8_t **out_text, vki_uint8_t **out_entry, vki_uint8_t **out_linker_entry);
+ const HChar *filename, load_info_t *out_info);
static int
load_fat_file(int fd, vki_off_t offset, vki_off_t size, unsigned long filetype,
- const HChar *filename,
- vki_uint8_t **out_stack_start, vki_uint8_t **out_stack_end,
- vki_uint8_t **out_text, vki_uint8_t **out_entry, vki_uint8_t **out_linker_entry);
+ const HChar *filename, load_info_t *out_info);
static int
load_mach_file(int fd, vki_off_t offset, vki_off_t size, unsigned long filetype,
- const HChar *filename,
- vki_uint8_t **out_stack_start, vki_uint8_t **out_stack_end,
- vki_uint8_t **out_text, vki_uint8_t **out_entry, vki_uint8_t **out_linker_entry);
+ const HChar *filename, load_info_t *out_info);
/* Open and map a dylinker file.
Returns 0 on success, -1 on any failure.
filename must be an absolute path.
- The dylinker's entry point is returned in *out_linker_entry.
+ The dylinker's entry point is returned in out_info->linker_entry.
*/
static int
-open_dylinker(const HChar *filename, vki_uint8_t **out_linker_entry)
+open_dylinker(const HChar *filename, load_info_t *out_info)
{
struct vg_stat sb;
vki_size_t filesize;
@@ -138,27 +141,20 @@
res = VG_(open)(filename, VKI_O_RDONLY, 0);
fd = sr_Res(res);
if (sr_isError(res)) {
- print("couldn't open dylinker: ");
- print(filename);
- print("\n");
+ VG_(printf)("couldn't open dylinker: %s\n", filename);
return -1;
}
err = VG_(fstat)(fd, &sb);
if (err) {
- print("couldn't stat dylinker: ");
- print(filename);
- print("\n");
+ VG_(printf)("couldn't stat dylinker: %s\n", filename);
VG_(close)(fd);
return -1;
}
filesize = sb.size;
- err = load_mach_file(fd, 0, filesize, MH_DYLINKER, filename,
- NULL, NULL, NULL, out_linker_entry, NULL);
+ err = load_mach_file(fd, 0, filesize, MH_DYLINKER, filename, out_info);
if (err) {
- print("...while loading dylinker: ");
- print(filename);
- print("\n");
+ VG_(printf)("...while loading dylinker: %s\n", filename);
}
VG_(close)(fd);
return err;
@@ -170,20 +166,22 @@
fd[offset..size) is a Mach-O thin file.
Returns 0 on success, -1 on any failure.
If this segment contains the executable's Mach headers, their
- loaded address is returned in *text.
+ loaded address is returned in out_info->text.
If this segment is a __UNIXSTACK, its start address is returned in
- *stack_start.
+ out_info->stack_start.
*/
static int
load_segment(int fd, vki_off_t offset, vki_off_t size,
- vki_uint8_t **text, vki_uint8_t **stack_start,
- struct SEGMENT_COMMAND *segcmd, const HChar *filename)
+ struct SEGMENT_COMMAND *segcmd, const HChar *filename,
+ load_info_t *out_info)
{
SysRes res;
Addr addr;
vki_size_t filesize; // page-aligned
vki_size_t vmsize; // page-aligned
+ vki_size_t vmend; // page-aligned
unsigned int prot;
+ Addr slided_addr = segcmd->vmaddr + out_info->linker_offset;
// GrP fixme mark __UNIXSTACK as SF_STACK
@@ -212,12 +210,12 @@
// Record the segment containing the Mach headers themselves
if (segcmd->fileoff == 0 && segcmd->filesize != 0) {
- if (text) *text = (vki_uint8_t *)segcmd->vmaddr;
+ out_info->text = (vki_uint8_t *)slided_addr;
}
// Record the __UNIXSTACK start
if (0 == VG_(strcmp)(segcmd->segname, SEG_UNIXSTACK)) {
- if (stack_start) *stack_start = (vki_uint8_t *)segcmd->vmaddr;
+ out_info->stack_start = (vki_uint8_t *)slided_addr;
}
// Sanity-check the segment
@@ -225,6 +223,12 @@
print("bad executable (invalid segment command)\n");
return -1;
}
+
+ vmend = VG_PGROUNDUP(slided_addr + segcmd->vmsize);
+ if (vmend > out_info->max_addr) {
+ out_info->max_addr = vmend;
+ }
+
if (segcmd->vmsize == 0) {
return 0; // nothing to map - ok
}
@@ -239,7 +243,7 @@
filesize = VG_PGROUNDUP(segcmd->filesize);
vmsize = VG_PGROUNDUP(segcmd->vmsize);
if (filesize > 0) {
- addr = (Addr)segcmd->vmaddr;
+ addr = slided_addr;
VG_(debugLog)(2, "ume", "mmap fixed (file) (%#lx, %lu)\n", addr, filesize);
res = VG_(am_mmap_named_file_fixed_client)(addr, filesize, prot, fd,
offset + segcmd->fileoff,
@@ -256,7 +260,7 @@
if (filesize != vmsize) {
// page-aligned part
SizeT length = vmsize - filesize;
- addr = (Addr)(filesize + segcmd->vmaddr);
+ addr = (Addr)(filesize + slided_addr);
VG_(debugLog)(2, "ume", "mmap fixed (anon) (%#lx, %lu)\n", addr, length);
res = VG_(am_mmap_anon_fixed_client)(addr, length, prot);
check_mmap(res, addr, length, "load_segment2");
@@ -269,16 +273,15 @@
/*
Parse a LC_THREAD or LC_UNIXTHREAD command.
Return 0 on success, -1 on any failure.
- The stack address is returned in *stack. If the executable requested
- a non-default stack address, *customstack is set to TRUE. The thread's
- entry point is returned in *entry.
+ If the thread is a LC_UNIXTHREAD, the stack address is returned in out_info->stack_end.
+ If the executable requested a non-default stack address,
+ *customstack is set to TRUE. The thread's entry point is returned in out_info->entry.
The stack itself (if any) is not mapped.
Other custom register settings are silently ignored (GrP fixme).
*/
static int
-load_genericthread(vki_uint8_t **stack_end,
- int *customstack, vki_uint8_t **entry,
- struct thread_command *threadcmd)
+load_genericthread(struct thread_command *threadcmd, int type,
+ int *customstack, load_info_t *out_info)
{
unsigned int flavor;
unsigned int count;
@@ -304,12 +307,12 @@
#if defined(VGA_x86)
if (flavor == i386_THREAD_STATE && count == i386_THREAD_STATE_COUNT) {
i386_thread_state_t *state = (i386_thread_state_t *)p;
- if (entry) *entry = (vki_uint8_t *)state->__eip;
- if (stack_end) {
- *stack_end = (vki_uint8_t *)(state->__esp ? state->__esp
- : VKI_USRSTACK);
- vg_assert(VG_IS_PAGE_ALIGNED(*stack_end));
- (*stack_end)--;
+ out_info->entry = (vki_uint8_t *)state->__eip;
+ if (type == LC_UNIXTHREAD) {
+ out_info->stack_end =
+ (vki_uint8_t *)(state->__esp ? state->__esp : VKI_USRSTACK);
+ vg_assert(VG_IS_PAGE_ALIGNED(out_info->stack_end));
+ out_info->stack_end--;
}
if (customstack) *customstack = state->__esp;
return 0;
@@ -318,12 +321,12 @@
#elif defined(VGA_amd64)
if (flavor == x86_THREAD_STATE64 && count == x86_THREAD_STATE64_COUNT){
x86_thread_state64_t *state = (x86_thread_state64_t *)p;
- if (entry) *entry = (vki_uint8_t *)state->__rip;
- if (stack_end) {
- *stack_end = (vki_uint8_t *)(state->__rsp ? state->__rsp
- : VKI_USRSTACK64);
- vg_assert(VG_IS_PAGE_ALIGNED(*stack_end));
- (*stack_end)--;
+ out_info->entry = (vki_uint8_t *)state->__rip;
+ if (type == LC_UNIXTHREAD) {
+ out_info->stack_end =
+ (vki_uint8_t *)(state->__rsp ? state->__rsp : VKI_USRSTACK64);
+ vg_assert(VG_IS_PAGE_ALIGNED(out_info->stack_end));
+ out_info->stack_end--;
}
if (customstack) *customstack = state->__rsp;
return 0;
@@ -356,21 +359,19 @@
/*
Processes a LC_UNIXTHREAD command.
Returns 0 on success, -1 on any failure.
- The stack is mapped in and returned in *out_stack.
- The thread's entry point is returned in *out_entry.
+ The stack is mapped in and returned in out_info->stack_start and out_info->stack_end.
+ The thread's entry point is returned in out_info->entry.
*/
static int
-load_unixthread(vki_uint8_t **out_stack_start, vki_uint8_t **out_stack_end,
- vki_uint8_t **out_entry, struct thread_command *threadcmd)
+load_unixthread(struct thread_command *threadcmd, load_info_t *out_info)
{
int err;
- vki_uint8_t *stack_end;
int customstack;
- err = load_genericthread(&stack_end, &customstack, out_entry, threadcmd);
+ err = load_genericthread(threadcmd, LC_UNIXTHREAD, &customstack, out_info);
if (err) return -1;
- if (!stack_end) {
+ if (!out_info->stack_end) {
print("bad executable (no thread stack)\n");
return -1;
}
@@ -378,18 +379,16 @@
if (!customstack) {
// Map the stack
vki_size_t stacksize = VG_PGROUNDUP(default_stack_size());
- vm_address_t stackbase = VG_PGROUNDDN(stack_end+1-stacksize);
+ vm_address_t stackbase = VG_PGROUNDDN(out_info->stack_end+1-stacksize);
SysRes res;
res = VG_(am_mmap_anon_fixed_client)(stackbase, stacksize, VKI_PROT_READ|VKI_PROT_WRITE|VKI_PROT_EXEC);
check_mmap(res, stackbase, stacksize, "load_unixthread1");
- if (out_stack_start) *out_stack_start = (vki_uint8_t *)stackbase;
+ out_info->stack_start = (vki_uint8_t *)stackbase;
} else {
// custom stack - mapped via __UNIXTHREAD segment
}
- if (out_stack_end) *out_stack_end = stack_end;
-
return 0;
}
@@ -402,9 +401,8 @@
above zero. */
#if DARWIN_VERS >= DARWIN_10_8
static int
-handle_lcmain ( vki_uint8_t **out_stack_start,
- vki_uint8_t **out_stack_end,
- vki_size_t requested_size )
+handle_lcmain ( vki_size_t requested_size,
+ load_info_t *out_info )
{
if (requested_size == 0) {
requested_size = default_stack_size();
@@ -418,15 +416,15 @@
VKI_PROT_READ|VKI_PROT_WRITE|VKI_PROT_EXEC);
check_mmap_float(res, requested_size, "handle_lcmain");
vg_assert(!sr_isError(res));
- *out_stack_start = (vki_uint8_t*)sr_Res(res);
- *out_stack_end = *out_stack_start + requested_size - 1;
+ out_info->stack_start = (vki_uint8_t*)sr_Res(res);
+ out_info->stack_end = out_info->stack_start + requested_size - 1;
Bool need_discard = False;
- res = VG_(am_munmap_client)(&need_discard, (Addr)*out_stack_start, HACK);
+ res = VG_(am_munmap_client)(&need_discard, (Addr)out_info->stack_start, HACK);
if (sr_isError(res)) return -1;
vg_assert(!need_discard); // True == wtf?
- *out_stack_start += HACK;
+ out_info->stack_start += HACK;
return 0;
}
@@ -438,12 +436,21 @@
Processes an LC_LOAD_DYLINKER command.
Returns 0 on success, -1 on any error.
The linker itself is mapped into memory.
- The linker's entry point is returned in *linker_entry.
+ The linker's entry point is returned in out_info->linker_entry.
*/
static int
-load_dylinker(vki_uint8_t **linker_entry, struct dylinker_command *dycmd)
+load_dylinker(struct dylinker_command *dycmd, load_info_t *out_info)
{
const HChar *name;
+ int ret;
+ load_info_t linker_info;
+ linker_info.stack_start = NULL;
+ linker_info.stack_end = NULL;
+ linker_info.text = NULL;
+ linker_info.entry = NULL;
+ linker_info.linker_entry = NULL;
+ linker_info.linker_offset = 0;
+ linker_info.max_addr = out_info->max_addr;
if (dycmd->name.offset >= dycmd->cmdsize) {
print("bad executable (invalid dylinker command)\n");
@@ -453,22 +460,27 @@
name = dycmd->name.offset + (HChar *)dycmd;
// GrP fixme assumes name is terminated somewhere
- return open_dylinker(name, linker_entry);
+ ret = open_dylinker(name, &linker_info);
+ if (linker_info.entry) {
+ out_info->linker_entry = linker_info.entry + linker_info.linker_offset;
+ }
+ out_info->max_addr = linker_info.max_addr;
+ return ret;
}
/*
Process an LC_THREAD command.
Returns 0 on success, -1 on any failure.
- The thread's entry point is returned in *out_entry.
+ The thread's entry point is returned in out_info->entry.
*/
static int
-load_thread(vki_uint8_t **out_entry, struct thread_command *threadcmd)
+load_thread(struct thread_command *threadcmd, load_info_t *out_info)
{
int customstack;
int err;
- err = load_genericthread(NULL, &customstack, out_entry, threadcmd);
+ err = load_genericthread(threadcmd, LC_THREAD, &customstack, out_info);
if (err) return -1;
if (customstack) {
print("bad executable (stackless thread has stack)\n");
@@ -484,17 +496,16 @@
Returns 0 on success, -1 on any failure.
fd[offset..offset+size) is a Mach-O thin file.
filetype is MH_EXECUTE or MH_DYLINKER.
- The mapped but empty stack is returned in *out_stack.
- The executable's Mach headers are returned in *out_text.
- The executable's entry point is returned in *out_entry.
- The dylinker's entry point (if any) is returned in *out_linker_entry.
+ The mapped but empty stack is returned in out_info->stack_start.
+ The executable's Mach headers are returned in out_info->text.
+ The executable's entry point is returned in out_info->entry.
+ The dylinker's entry point (if any) is returned in out_info->linker_entry.
+ The dylinker's offset (macOS 10.12) is returned in out_info->linker_offset.
GrP fixme need to return whether dylinker was found - stack layout is different
*/
static int
load_thin_file(int fd, vki_off_t offset, vki_off_t size, unsigned long filetype,
- const HChar *filename,
- vki_uint8_t **out_stack_start, vki_uint8_t **out_stack_end,
- vki_uint8_t **out_text, vki_uint8_t **out_entry, vki_uint8_t **out_linker_entry)
+ const HChar *filename, load_info_t *out_info)
{
VG_(debugLog)(1, "ume", "load_thin_file: begin: %s\n", filename);
struct MACH_HEADER mh;
@@ -509,12 +520,6 @@
SysRes res;
vki_size_t len;
- vki_uint8_t *stack_start = NULL; // allocated thread stack (hot end)
- vki_uint8_t *stack_end = NULL; // allocated thread stack (cold end)
- vki_uint8_t *entry = NULL; // static entry point
- vki_uint8_t *text = NULL; // start of text segment (i.e. the mach headers)
- vki_uint8_t *linker_entry = NULL; // dylinker entry point
-
// Read Mach-O header
if (sizeof(mh) > size) {
print("bad executable (no Mach-O header)\n");
@@ -576,14 +581,14 @@
case LC_MAIN: { /* New in 10.8 */
struct entry_point_command* epcmd
= (struct entry_point_command*)lc;
- if (stack_start || stack_end) {
+ if (out_info->stack_start || out_info->stack_end) {
print("bad executable (multiple indications of stack)");
return -1;
}
- err = handle_lcmain ( &stack_start, &stack_end, epcmd->stacksize );
+ err = handle_lcmain(epcmd->stacksize, out_info);
if (err) return -1;
VG_(debugLog)(2, "ume", "lc_main: created stack %p-%p\n",
- stack_start, stack_end);
+ out_info->stack_start, out_info->stack_end);
break;
}
# endif
@@ -594,14 +599,19 @@
return -1;
}
segcmd = (struct SEGMENT_COMMAND *)lc;
- err = load_segment(fd, offset, size, &text, &stack_start,
- segcmd, filename);
+#if DARWIN_VERS >= DARWIN_10_12
+ /* dyld text address is relative instead of absolute in 10.12 */
+ if (filetype == MH_DYLINKER && segcmd->vmaddr == 0 && segcmd->fileoff == 0) {
+ out_info->linker_offset = out_info->max_addr;
+ }
+# endif
+ err = load_segment(fd, offset, size, segcmd, filename, out_info);
if (err) return -1;
break;
case LC_UNIXTHREAD:
- if (stack_end || entry) {
+ if (out_info->stack_end || out_info->entry) {
print("bad executable (multiple thread commands)\n");
return -1;
}
@@ -610,7 +620,7 @@
return -1;
}
threadcmd = (struct thread_command *)lc;
- err = load_unixthread(&stack_start, &stack_end, &entry, threadcmd);
+ err = load_unixthread(threadcmd, out_info);
if (err) return -1;
break;
@@ -619,7 +629,7 @@
print("bad executable (dylinker needs a dylinker)\n");
return -1;
}
- if (linker_entry) {
+ if (out_info->linker_entry) {
print("bad executable (multiple dylinker commands)\n");
}
if (lc->cmdsize < sizeof(struct dylinker_command)) {
@@ -627,7 +637,7 @@
return -1;
}
dycmd = (struct dylinker_command *)lc;
- err = load_dylinker(&linker_entry, dycmd);
+ err = load_dylinker(dycmd, out_info);
if (err) return -1;
break;
@@ -636,7 +646,7 @@
print("bad executable (stackless thread)\n");
return -1;
}
- if (stack_end || entry) {
+ if (out_info->stack_end || out_info->entry) {
print("bad executable (multiple thread commands)\n");
return -1;
}
@@ -645,7 +655,7 @@
return -1;
}
threadcmd = (struct thread_command *)lc;
- err = load_thread(&entry, threadcmd);
+ err = load_thread(threadcmd, out_info);
if (err) return -1;
break;
@@ -663,15 +673,15 @@
// a stack
// a text segment
// an entry point (static or linker)
- if (!stack_end || !stack_start) {
+ if (!out_info->stack_end || !out_info->stack_start) {
VG_(printf)("bad executable %s (no stack)\n", filename);
return -1;
}
- if (!text) {
+ if (!out_info->text) {
print("bad executable (no text segment)\n");
return -1;
}
- if (!entry && !linker_entry) {
+ if (!out_info->entry && !out_info->linker_entry) {
print("bad executable (no entry point)\n");
return -1;
}
@@ -679,18 +689,12 @@
else if (filetype == MH_DYLINKER) {
// Verify the necessary pieces for a dylinker:
// an entry point
- if (!entry) {
+ if (!out_info->entry) {
print("bad executable (no entry point)\n");
return -1;
}
}
- if (out_stack_start) *out_stack_start = stack_start;
- if (out_stack_end) *out_stack_end = stack_end;
- if (out_text) *out_text = text;
- if (out_entry) *out_entry = entry;
- if (out_linker_entry) *out_linker_entry = linker_entry;
-
VG_(debugLog)(1, "ume", "load_thin_file: success: %s\n", filename);
return 0;
}
@@ -701,9 +705,7 @@
*/
static int
load_fat_file(int fd, vki_off_t offset, vki_off_t size, unsigned long filetype,
- const HChar *filename,
- vki_uint8_t **out_stack_start, vki_uint8_t **out_stack_end,
- vki_uint8_t **out_text, vki_uint8_t **out_entry, vki_uint8_t **out_linker_entry)
+ const HChar *filename, load_info_t *out_info)
{
struct fat_header fh;
vki_off_t arch_offset;
@@ -766,9 +768,7 @@
print("bad executable (corrupt fat arch 2)\n");
return -1;
}
- return load_mach_file(fd, offset+arch.offset, arch.size, filetype,
- filename, out_stack_start, out_stack_end,
- out_text, out_entry, out_linker_entry);
+ return load_mach_file(fd, offset+arch.offset, arch.size, filetype, filename, out_info);
}
}
@@ -782,9 +782,7 @@
*/
static int
load_mach_file(int fd, vki_off_t offset, vki_off_t size, unsigned long filetype,
- const HChar *filename,
- vki_uint8_t **out_stack_start, vki_uint8_t **out_stack_end,
- vki_uint8_t **out_text, vki_uint8_t **out_entry, vki_uint8_t **out_linker_entry)
+ const HChar *filename, load_info_t *out_info)
{
vki_uint32_t magic;
SysRes res;
@@ -801,14 +799,10 @@
if (magic == MAGIC) {
// thin
- return load_thin_file(fd, offset, size, filetype, filename,
- out_stack_start, out_stack_end,
- out_text, out_entry, out_linker_entry);
+ return load_thin_file(fd, offset, size, filetype, filename, out_info);
} else if (magic == VG_(htonl)(FAT_MAGIC)) {
// fat
- return load_fat_file(fd, offset, size, filetype, filename,
- out_stack_start, out_stack_end,
- out_text, out_entry, out_linker_entry);
+ return load_fat_file(fd, offset, size, filetype, filename, out_info);
} else {
// huh?
print("bad executable (bad Mach-O magic)\n");
@@ -833,11 +827,14 @@
{
int err;
struct vg_stat sb;
- vki_uint8_t *stack_start;
- vki_uint8_t *stack_end;
- vki_uint8_t *text;
- vki_uint8_t *entry;
- vki_uint8_t *linker_entry;
+ load_info_t load_info;
+ load_info.stack_start = NULL;
+ load_info.stack_end = NULL;
+ load_info.text = NULL;
+ load_info.entry = NULL;
+ load_info.linker_entry = NULL;
+ load_info.linker_offset = 0;
+ load_info.max_addr = 0;
err = VG_(fstat)(fd, &sb);
if (err) {
@@ -845,22 +842,20 @@
return VKI_ENOEXEC;
}
- err = load_mach_file(fd, 0, sb.size, MH_EXECUTE, name,
- &stack_start, &stack_end,
- &text, &entry, &linker_entry);
+ err = load_mach_file(fd, 0, sb.size, MH_EXECUTE, name, &load_info);
if (err) return VKI_ENOEXEC;
// GrP fixme exe_base
// GrP fixme exe_end
- info->entry = (Addr)entry;
- info->init_ip = (Addr)(linker_entry ? linker_entry : entry);
+ info->entry = (Addr) load_info.entry;
+ info->init_ip = (Addr)(load_info.linker_entry ? load_info.linker_entry : load_info.entry);
info->brkbase = 0xffffffff; // GrP fixme hack
info->init_toc = 0; // GrP fixme unused
- info->stack_start = (Addr)stack_start;
- info->stack_end = (Addr)stack_end;
- info->text = (Addr)text;
- info->dynamic = linker_entry ? True : False;
+ info->stack_start = (Addr) load_info.stack_start;
+ info->stack_end = (Addr) load_info.stack_end;
+ info->text = (Addr) load_info.text;
+ info->dynamic = load_info.linker_entry ? True : False;
info->executable_path = VG_(strdup)("ume.macho.executable_path", name);
diff --git a/coregrind/m_ume/main.c b/coregrind/m_ume/main.c
index 3125a8e..9990b4d 100644
--- a/coregrind/m_ume/main.c
+++ b/coregrind/m_ume/main.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_ume/priv_ume.h b/coregrind/m_ume/priv_ume.h
index 7b3ccfd..c064458 100644
--- a/coregrind/m_ume/priv_ume.h
+++ b/coregrind/m_ume/priv_ume.h
@@ -6,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_ume/script.c b/coregrind/m_ume/script.c
index 3ebe6d9..0a2f489 100644
--- a/coregrind/m_ume/script.c
+++ b/coregrind/m_ume/script.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_vki.c b/coregrind/m_vki.c
index f1efa20..a5847ec 100644
--- a/coregrind/m_vki.c
+++ b/coregrind/m_vki.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2006-2015 OpenWorks LLP
+ Copyright (C) 2006-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_vkiscnums.c b/coregrind/m_vkiscnums.c
index 9807a82..03a64a4 100644
--- a/coregrind/m_vkiscnums.c
+++ b/coregrind/m_vkiscnums.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2006-2015 OpenWorks LLP
+ Copyright (C) 2006-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/coregrind/m_wordfm.c b/coregrind/m_wordfm.c
index 9717020..323ac57 100644
--- a/coregrind/m_wordfm.c
+++ b/coregrind/m_wordfm.c
@@ -9,13 +9,13 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2007-2015 Julian Seward
+ Copyright (C) 2007-2017 Julian Seward
jseward@acm.org
This code is based on previous work by Nicholas Nethercote
(coregrind/m_oset.c) which is
- Copyright (C) 2005-2015 Nicholas Nethercote
+ Copyright (C) 2005-2017 Nicholas Nethercote
njn@valgrind.org
which in turn was derived partially from:
@@ -93,7 +93,7 @@
/* forward */
static Bool avl_removeroot_wrk(AvlNode** t, Word(*kCmp)(UWord,UWord));
-/* Swing to the left. Warning: no balance maintainance. */
+/* Swing to the left. Warning: no balance maintenance. */
static void avl_swl ( AvlNode** root )
{
AvlNode* a = *root;
@@ -103,7 +103,7 @@
b->child[0] = a;
}
-/* Swing to the right. Warning: no balance maintainance. */
+/* Swing to the right. Warning: no balance maintenance. */
static void avl_swr ( AvlNode** root )
{
AvlNode* a = *root;
@@ -113,7 +113,7 @@
b->child[1] = a;
}
-/* Balance maintainance after especially nasty swings. */
+/* Balance maintenance after especially nasty swings. */
static void avl_nasty ( AvlNode* root )
{
switch (root->balance) {
diff --git a/coregrind/m_xarray.c b/coregrind/m_xarray.c
index 07f161f..c5c9e84 100644
--- a/coregrind/m_xarray.c
+++ b/coregrind/m_xarray.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2007-2015 OpenWorks LLP
+ Copyright (C) 2007-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -38,9 +38,9 @@
/* See pub_tool_xarray.h for details of what this is all about. */
struct _XArray {
- void* (*alloc_fn) ( const HChar*, SizeT ); /* alloc fn (nofail) */
+ Alloc_Fn_t alloc_fn; /* alloc fn (nofail) */
const HChar* cc; /* cost centre for alloc */
- void (*free_fn) ( void* ); /* free fn */
+ Free_Fn_t free_fn; /* free fn */
Int (*cmpFn) ( const void*, const void* ); /* cmp fn (may be NULL) */
Word elemSzB; /* element size in bytes */
void* arr; /* pointer to elements */
@@ -50,9 +50,9 @@
};
-XArray* VG_(newXA) ( void*(*alloc_fn)(const HChar*,SizeT),
+XArray* VG_(newXA) ( Alloc_Fn_t alloc_fn,
const HChar* cc,
- void(*free_fn)(void*),
+ Free_Fn_t free_fn,
Word elemSzB )
{
XArray* xa;
@@ -373,6 +373,16 @@
va_end(vargs);
}
+Bool VG_(strIsMemberXA)(const XArray* xa, const HChar* str )
+{
+ Word i;
+ HChar** members = (HChar**)xa->arr;
+
+ for (i = 0; i < xa->usedsizeE; i++)
+ if (VG_(strcmp)(str, members[i]) == 0)
+ return True;
+ return False;
+}
/*--------------------------------------------------------------------*/
/*--- end m_xarray.c ---*/
diff --git a/coregrind/m_xtmemory.c b/coregrind/m_xtmemory.c
new file mode 100644
index 0000000..b1bc3df
--- /dev/null
+++ b/coregrind/m_xtmemory.c
@@ -0,0 +1,342 @@
+
+/*--------------------------------------------------------------------*/
+/*--- Support functions for xtree memory reports. m_xtmemory.c ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2016-2017 Philippe Waroquiers
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#include "pub_core_libcassert.h"
+#include "pub_core_libcbase.h"
+#include "pub_core_libcprint.h"
+#include "pub_core_libcproc.h"
+#include "pub_core_mallocfree.h"
+#include "pub_core_options.h"
+#include "pub_core_xarray.h"
+#include "pub_core_xtree.h"
+#include "pub_core_xtmemory.h" /* self */
+
+static void VG_(XT_Allocs_init)(void* xt_allocs)
+{
+ VG_(memset) (xt_allocs, 0, sizeof(XT_Allocs));
+}
+static void VG_(XT_Allocs_add) (void* to, const void* xt_allocs)
+{
+ XT_Allocs* xto = to;
+ const XT_Allocs* xta = xt_allocs;
+
+ xto->nbytes += xta->nbytes;
+ xto->nblocks += xta->nblocks;
+}
+static void VG_(XT_Allocs_sub) (void* from, const void* xt_allocs)
+{
+ XT_Allocs* xfrom = from;
+ const XT_Allocs* xta = xt_allocs;
+
+ xfrom->nbytes -= xta->nbytes;
+ xfrom->nblocks -= xta->nblocks;
+}
+static const HChar* VG_(XT_Allocs_img) (const void* xt_allocs)
+{
+ static HChar buf[100];
+
+ const XT_Allocs* xta = xt_allocs;
+
+ if (xta->nbytes > 0 || xta->nblocks > 0) {
+ VG_(sprintf) (buf, "%lu %lu",
+ xta->nbytes, xta->nblocks);
+ return buf;
+ } else {
+ return NULL;
+ }
+}
+const HChar* XT_Allocs_events = "curB : currently allocated Bytes" ","
+ "curBk : currently allocated Blocks";
+
+/* Type and functions for full xtree memory profiling. */
+static XTree* full_xt;
+typedef
+ struct _XT_Full {
+ // Current nr of bytes/blocks allocated by this ec
+ SizeT cur_alloc_nbytes;
+ SizeT cur_alloc_nblocks;
+
+ // Total/cumulative nr of bytes/blocks allocated by this ec
+ ULong tot_alloc_nbytes;
+ ULong tot_alloc_nblocks;
+
+ // Total/cumulative nr of bytes/blocks freed by this ec
+ ULong tot_freed_nbytes;
+ ULong tot_freed_nblocks;
+ } XT_Full;
+/* Note: normally, an ec should never be used as both an alloc_ec and
+ a free_ec. This implies that we should never have a XT_Full that has
+ at the same time some alloc and some freed components > 0.
+ We however still will support this possibility, just in case very
+ strange ec are produced and/or given by the tool. */
+
+static void VG_(XT_Full_init)(void* xtfull)
+{
+ VG_(memset) (xtfull, 0, sizeof(XT_Full));
+}
+static void VG_(XT_Full_add) (void* to, const void* xtfull)
+{
+ XT_Full* xto = to;
+ const XT_Full* xtf = xtfull;
+
+ xto->cur_alloc_nbytes += xtf->cur_alloc_nbytes;
+ xto->cur_alloc_nblocks += xtf->cur_alloc_nblocks;
+ xto->tot_alloc_nbytes += xtf->tot_alloc_nbytes;
+ xto->tot_alloc_nblocks += xtf->tot_alloc_nblocks;
+ xto->tot_freed_nbytes += xtf->tot_freed_nbytes;
+ xto->tot_freed_nblocks += xtf->tot_freed_nblocks;
+}
+static void VG_(XT_Full_sub) (void* from, const void* xtfull)
+{
+ XT_Full* xfrom = from;
+ const XT_Full* xtf = xtfull;
+
+ xfrom->cur_alloc_nbytes -= xtf->cur_alloc_nbytes;
+ xfrom->cur_alloc_nblocks -= xtf->cur_alloc_nblocks;
+ xfrom->tot_alloc_nbytes -= xtf->tot_alloc_nbytes;
+ xfrom->tot_alloc_nblocks -= xtf->tot_alloc_nblocks;
+ xfrom->tot_freed_nbytes -= xtf->tot_freed_nbytes;
+ xfrom->tot_freed_nblocks -= xtf->tot_freed_nblocks;
+}
+static const HChar* VG_(XT_Full_img) (const void* xtfull)
+{
+ static HChar buf[300];
+
+ const XT_Full* xtf = xtfull;
+
+ if ( xtf->cur_alloc_nbytes > 0
+ || xtf->cur_alloc_nblocks > 0
+ || xtf->tot_alloc_nbytes > 0
+ || xtf->tot_alloc_nblocks > 0
+ || xtf->tot_freed_nbytes > 0
+ || xtf->tot_freed_nblocks > 0) {
+ VG_(sprintf) (buf,
+ "%lu %lu "
+ "%llu %llu "
+ "%llu %llu",
+ xtf->cur_alloc_nbytes, xtf->cur_alloc_nblocks,
+ xtf->tot_alloc_nbytes, xtf->tot_alloc_nblocks,
+ xtf->tot_freed_nbytes, xtf->tot_freed_nblocks);
+ return buf;
+ } else {
+ return NULL;
+ }
+}
+static const HChar* XT_Full_events =
+ "curB : currently allocated Bytes" ","
+ "curBk : currently allocated Blocks" ","
+ "totB : total allocated Bytes" ","
+ "totBk : total allocated Blocks" ","
+ "totFdB : total Freed Bytes" ","
+ "totFdBk : total Freed Blocks";
+void VG_(XTMemory_Full_init)(XT_filter_IPs_t filter_IPs_fn)
+{
+ full_xt = VG_(XT_create) (VG_(malloc),
+ "m_xtree.full_xt",
+ VG_(free),
+ sizeof(XT_Full),
+ VG_(XT_Full_init),
+ VG_(XT_Full_add),
+ VG_(XT_Full_sub),
+ filter_IPs_fn);
+}
+void VG_(XTMemory_Full_alloc)(SizeT szB,
+ ExeContext* ec_alloc)
+{
+ XT_Full xtf = {szB, 1, szB, 1, 0, 0};
+ VG_(XT_add_to_ec)(full_xt, ec_alloc, &xtf);
+}
+void VG_(XTMemory_Full_free)(SizeT szB,
+ ExeContext* ec_alloc,
+ ExeContext* ec_free)
+{
+ // substract from ec_alloc the freed memory.
+ XT_Full xtf_sub = {szB, 1, 0, 0, 0, 0};
+ VG_(XT_sub_from_ec)(full_xt, ec_alloc, &xtf_sub);
+
+ // add to ec_free the freed memory
+ XT_Full xtf_add = {0, 0, 0, 0, szB, 1};
+ VG_(XT_add_to_ec)(full_xt, ec_free, &xtf_add);
+}
+
+void VG_(XTMemory_Full_resize_in_place)(SizeT oldSzB, SizeT newSzB,
+ ExeContext* ec_alloc)
+{
+ if (oldSzB > newSzB) {
+ XT_Full xtf = {oldSzB - newSzB, 0, oldSzB - newSzB, 0, 0, 0};
+ VG_(XT_sub_from_ec)(full_xt, ec_alloc, &xtf);
+ } else {
+ XT_Full xtf = {newSzB - oldSzB, 0, newSzB - oldSzB, 0, 0, 0};
+ VG_(XT_add_to_ec)(full_xt, ec_alloc, &xtf);
+ }
+}
+
+// Indicates which event nr the report_value function must return.
+static UInt event_report_value_id;
+static ULong XT_Full_report_value(const void* xtfull)
+{
+ const XT_Full* xtf = xtfull;
+ switch (event_report_value_id) {
+ case 0: return (ULong) xtf->cur_alloc_nbytes;
+ case 1: return (ULong) xtf->cur_alloc_nblocks;
+ case 2: return xtf->tot_alloc_nbytes;
+ case 3: return xtf->tot_alloc_nblocks;
+ case 4: return xtf->tot_freed_nbytes;
+ case 5: return xtf->tot_freed_nblocks;
+ default: vg_assert(0);
+ }
+}
+static ULong XT_Allocs_report_value(const void* xt_allocs)
+{
+ const XT_Allocs* xta = xt_allocs;
+ switch (event_report_value_id) {
+ case 0: return (ULong) xta->nbytes;
+ case 1: return (ULong) xta->nblocks;
+ default: vg_assert(0);
+ }
+}
+
+static void produce_report(XTree* xt, const HChar* filename,
+ const HChar* events,
+ const HChar* (*img_value) (const void* value),
+ ULong (*report_value)(const void* value))
+{
+ /* The user can control the kind of report using filename extension. */
+ if (VG_(strstr)(filename, ".ms")) {
+ /* If needed, some harcoded value below could become parameters. */
+ MsFile* fp;
+ Massif_Header header = (Massif_Header) {
+ .snapshot_n = 0,
+ .time = VG_(read_millisecond_timer)(),
+ .sz_B = 0ul,
+ .extra_B = 0ul,
+ .stacks_B = 0ul,
+ .detailed = True,
+ .peak = False,
+ .top_node_desc = NULL,
+ .sig_threshold = 0.00000000000001
+ // Currently, we take a very small float value to not output
+ // the 0 values, but still output all the rest.
+ };
+
+ // Variables to parse events
+ HChar strtok_events[VG_(strlen)(events)+1];
+ HChar* e;
+ HChar* ssaveptr;
+
+ fp = VG_(XT_massif_open)(filename,
+ "xtree.produce_report",
+ NULL,
+ "ms");
+
+ event_report_value_id = 0;
+ VG_(strcpy)(strtok_events, events);
+ for (e = VG_(strtok_r) (strtok_events, ",", &ssaveptr);
+ e != NULL;
+ e = VG_(strtok_r) (NULL, ",", &ssaveptr)) {
+ header.top_node_desc = e;
+ VG_(XT_massif_print)(fp, xt, &header, report_value);
+ header.snapshot_n++;
+ event_report_value_id++;
+ }
+
+ VG_(XT_massif_close)(fp);
+ } else
+ VG_(XT_callgrind_print)(xt,
+ filename,
+ events,
+ img_value);
+}
+
+void VG_(XTMemory_report)
+ (const HChar* filename, Bool fini,
+ void (*next_block)(XT_Allocs* xta, ExeContext** ec_alloc),
+ XT_filter_IPs_t filter_IPs_fn)
+{
+ HChar* expanded_filename;
+
+ if (fini && VG_(clo_xtree_memory) == Vg_XTMemory_None)
+ return;
+
+ expanded_filename
+ = VG_(expand_file_name)("--xtree-memory-file",
+ (filename == NULL) ?
+ (fini ?
+ VG_(clo_xtree_memory_file)
+ : "xtmemory.kcg.%p.%n")
+ : filename);
+
+ /* fini is False => even if user kept --xtree-memory=none, we
+ produce a report when explicitely requested e.g. via a monitor
+ command. */
+ switch (VG_(clo_xtree_memory)) {
+ case Vg_XTMemory_None:
+ case Vg_XTMemory_Allocs: {
+ XTree* xt;
+ XT_Allocs xta;
+ ExeContext* ec_alloc;
+
+ xt = VG_(XT_create) (VG_(malloc),
+ "VG_(XTMemory_report)",
+ VG_(free),
+ sizeof(XT_Allocs),
+ VG_(XT_Allocs_init),
+ VG_(XT_Allocs_add),
+ VG_(XT_Allocs_sub),
+ filter_IPs_fn);
+ (*next_block)(&xta, &ec_alloc);
+ while ( xta.nblocks > 0 ) {
+ VG_(XT_add_to_ec) (xt, ec_alloc, &xta);
+ (*next_block)(&xta, &ec_alloc);
+ }
+
+ produce_report(xt, expanded_filename,
+ XT_Allocs_events, VG_(XT_Allocs_img),
+ XT_Allocs_report_value);
+
+ VG_(XT_delete)(xt);
+ break;
+ }
+ case Vg_XTMemory_Full:
+ produce_report(full_xt, expanded_filename,
+ XT_Full_events, VG_(XT_Full_img),
+ XT_Full_report_value);
+ break;
+ default:
+ vg_assert(0);
+ }
+ if (VG_(clo_verbosity) >= 1 || !fini)
+ VG_(umsg)("xtree memory report: %s\n", expanded_filename);
+
+ VG_(free)(expanded_filename);
+}
+
+/*--------------------------------------------------------------------*/
+/*--- end m_xtree.c ---*/
+/*--------------------------------------------------------------------*/
diff --git a/coregrind/m_xtree.c b/coregrind/m_xtree.c
new file mode 100644
index 0000000..98d36bb
--- /dev/null
+++ b/coregrind/m_xtree.c
@@ -0,0 +1,1044 @@
+
+/*--------------------------------------------------------------------*/
+/*--- An xtree, tree of stacktraces with data m_xtree.c ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2016-2017 Philippe Waroquiers
+
+ This code generalises the XTree idea that was implemented in
+ the massif tool in Valgrind versions <= 3.12, which is
+ Copyright (C) 2005-2017 Nicholas Nethercote
+ njn@valgrind.org
+
+ The XTree implementation in this file is however implemented completely
+ differently. Some code has been re-used for the production of the
+ massif file header (e.g. FP_cmd function).
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#include "pub_core_basics.h"
+#include "pub_core_debuglog.h"
+#include "pub_core_clientstate.h"
+#include "pub_core_stacktrace.h"
+#include "pub_core_execontext.h"
+#include "pub_core_libcbase.h"
+#include "pub_core_libcassert.h"
+#include "pub_core_libcfile.h"
+#include "pub_core_libcprint.h"
+#include "pub_core_libcproc.h"
+#include "pub_core_hashtable.h"
+#include "pub_core_mallocfree.h"
+#include "pub_core_options.h"
+#include "pub_core_debuginfo.h"
+#include "pub_core_deduppoolalloc.h"
+#include "pub_core_xtree.h" /* self */
+
+#define DMSG(level, ...) (level <= VG_(debugLog_getLevel)() ? \
+ VG_(dmsg)(__VA_ARGS__) \
+ : 0)
+
+/* Defines the relevant part of an ec. This is shared between an xt
+ and its snapshots (see XT_shared XArray of xec). */
+typedef
+ struct _xec {
+ ExeContext* ec;
+ UShort top; // The first ips of ec to take into account.
+ UShort n_ips_sel; // The nr of ips from top to take into account.
+ }
+ xec;
+
+/* XT_shared maintains the information shared between an XT and all
+ its snapshots. */
+typedef
+ struct _XT_shared {
+ UWord nrRef; /* nr of XTrees referencing this shared memory. */
+
+ Alloc_Fn_t alloc_fn; /* alloc fn (nofail) */
+ const HChar* cc; /* cost centre for alloc */
+ Free_Fn_t free_fn; /* free fn */
+
+ /* The data associated to each ec is stored in 2 arrays:
+ an xec array, shared between an xt and all its snapshots.
+ a data array, private to each XTree.
+ For an ec with an ECU ecu, d4ecu2xecu[ecu/4] gives the offset in
+ xec and data arrays where the ec information is located (this
+ indirection is used to avoid huge xec and data arrays, in
+ case an XTree contains data only for a small number of ec.
+ The offset in the xec and data array is used as xtree ec unique
+ id i.e. an xecu. */
+
+ UInt d4ecu2xecu_sz; /* size of d4ecu2xecu (in nr of elements). */
+ UInt* d4ecu2xecu;
+
+ /* ec information common to an xt and its snapshots. */
+ XArray* xec; /* XArray of xec, indexed by xecu (== d4ecu2xecu[ecu/4]). */
+
+ /* XArray of xecu, sorted by StackTrace ips[top..top+n_ips_sel-1].
+ See ips_order_cmp. */
+ XArray* ips_order_xecu;
+ } XT_shared;
+
+/* NO_OFFSET indicates in d4ecu2xecu there is no data (yet) for this ec
+ (with the index ecu/4). */
+#define NO_OFFSET 0xffffffff
+
+static XT_shared* new_XT_shared (Alloc_Fn_t alloc_fn,
+ const HChar* cc,
+ void (*free_fn)(void*))
+{
+ XT_shared* shared;
+
+ vg_assert(alloc_fn);
+ vg_assert(cc);
+ vg_assert(free_fn);
+ shared = alloc_fn(cc, sizeof(*shared));
+ shared->nrRef = 0;
+ shared->alloc_fn = alloc_fn;
+ shared->cc = cc;
+ shared->free_fn = free_fn;
+
+ shared->d4ecu2xecu_sz = 0;
+ shared->d4ecu2xecu = NULL;
+ shared->xec = VG_(newXA)(alloc_fn, cc, free_fn, sizeof(xec));
+ shared->ips_order_xecu = NULL; // Allocated when needed.
+
+ return shared;
+}
+
+static void delete_XT_shared (XT_shared* shared)
+{
+ vg_assert(shared->nrRef == 0);
+ shared->free_fn(shared->d4ecu2xecu);
+ VG_(deleteXA)(shared->xec);
+ if (shared->ips_order_xecu != NULL)
+ VG_(deleteXA)(shared->ips_order_xecu);
+ shared->free_fn(shared);
+}
+
+/* Compare 2 entries in ips_order_xecu by StackTrace elements.
+ In case stack traces are of different length, an 'absent' ips is
+ considered smaller than any other address. */
+static XArray* xec_data_for_sort; // Needed to translate an xecu into an xec
+static Int ips_order_cmp(const void* vleft, const void* vright)
+{
+ const Xecu left_xecu = *(const Xecu*)vleft;
+ const Xecu right_xecu = *(const Xecu*)vright;
+ const xec* left = VG_(indexXA)(xec_data_for_sort, left_xecu);
+ const xec* right = VG_(indexXA)(xec_data_for_sort, right_xecu);
+ const StackTrace left_ips = VG_(get_ExeContext_StackTrace)(left->ec)
+ + left->top;
+ const StackTrace right_ips = VG_(get_ExeContext_StackTrace)(right->ec)
+ + right->top;
+ UInt i;
+
+ const UInt c_n_ips_sel = left->n_ips_sel < right->n_ips_sel
+ ? left->n_ips_sel : right->n_ips_sel;
+
+ // First see if we have a difference on the common nr of ips selected
+ for (i = 0; i < c_n_ips_sel; i++) {
+ if (left_ips[i] == right_ips[i]) continue;
+ if (left_ips[i] < right_ips[i]) return -1;
+ return 1;
+ }
+ // Common part is equal => compare lengths.
+ if (left->n_ips_sel < right->n_ips_sel) return -1;
+ if (left->n_ips_sel > right->n_ips_sel) return 1;
+ return 0;
+}
+
+// If needed, build or refresh shared->ips_order_xecu
+static void ensure_ips_order_xecu_valid(XT_shared* shared)
+{
+ UInt i;
+ UInt n_xecu;
+
+ if (shared->ips_order_xecu == NULL) {
+ shared->ips_order_xecu = VG_(newXA)(shared->alloc_fn, shared->cc,
+ shared->free_fn, sizeof(Xecu));
+ VG_(hintSizeXA)(shared->ips_order_xecu, VG_(sizeXA)(shared->xec));
+ VG_(setCmpFnXA)(shared->ips_order_xecu, ips_order_cmp);
+ }
+
+ if (VG_(sizeXA)(shared->xec) == VG_(sizeXA)(shared->ips_order_xecu))
+ return;
+
+ n_xecu = VG_(sizeXA)(shared->xec);
+ for (i = VG_(sizeXA)(shared->ips_order_xecu); i < n_xecu; i++)
+ VG_(addToXA)(shared->ips_order_xecu, &i);
+
+ xec_data_for_sort = shared->xec;
+ VG_(sortXA)(shared->ips_order_xecu);
+}
+
+static void addRef_XT_shared (XT_shared* shared)
+{
+ shared->nrRef++;
+}
+
+static UWord release_XT_shared(XT_shared* shared)
+{
+ UWord nrRef;
+
+ vg_assert(shared->nrRef > 0);
+ nrRef = --shared->nrRef;
+ if (nrRef == 0)
+ delete_XT_shared(shared);
+ return nrRef;
+}
+
+
+struct _XTree {
+ Alloc_Fn_t alloc_fn; /* alloc fn (nofail) */
+ const HChar* cc; /* cost centre for alloc */
+ Free_Fn_t free_fn; /* free fn */
+ Word dataSzB; /* data size in bytes */
+ XT_init_data_t init_data_fn;
+ XT_add_data_t add_data_fn;
+ XT_sub_data_t sub_data_fn;
+ XT_filter_IPs_t filter_IPs_fn;
+
+ XT_shared* shared;
+
+ HChar* tmp_data; /* temporary buffer, to insert new elements. */
+ XArray* data; /* of elements of size dataSzB */
+};
+
+
+XTree* VG_(XT_create) ( Alloc_Fn_t alloc_fn,
+ const HChar* cc,
+ Free_Fn_t free_fn,
+ Word dataSzB,
+ XT_init_data_t init_data_fn,
+ XT_add_data_t add_data_fn,
+ XT_sub_data_t sub_data_fn,
+ XT_filter_IPs_t filter_IPs_fn)
+{
+ XTree* xt;
+
+ /* check user-supplied info .. */
+ vg_assert(alloc_fn);
+ vg_assert(free_fn);
+ vg_assert(dataSzB >= 0);
+ vg_assert(init_data_fn);
+ vg_assert(add_data_fn);
+ vg_assert(sub_data_fn);
+
+ xt = alloc_fn(cc, sizeof(struct _XTree) );
+ xt->alloc_fn = alloc_fn;
+ xt->cc = cc;
+ xt->free_fn = free_fn;
+ xt->dataSzB = dataSzB;
+ xt->init_data_fn = init_data_fn;
+ xt->add_data_fn = add_data_fn;
+ xt->sub_data_fn = sub_data_fn;
+ xt->filter_IPs_fn = filter_IPs_fn;
+
+ xt->shared = new_XT_shared(alloc_fn, cc, free_fn);
+ addRef_XT_shared(xt->shared);
+ xt->tmp_data = alloc_fn(cc, xt->dataSzB);
+ xt->data = VG_(newXA)(alloc_fn, cc, free_fn, dataSzB);
+
+ return xt;
+}
+
+XTree* VG_(XT_snapshot)(XTree* xt)
+{
+ XTree* nxt;
+
+ vg_assert(xt);
+
+ nxt = xt->alloc_fn(xt->cc, sizeof(struct _XTree) );
+
+ *nxt = *xt;
+ addRef_XT_shared(nxt->shared);
+ nxt->tmp_data = nxt->alloc_fn(nxt->cc, nxt->dataSzB);
+ nxt->data = VG_(cloneXA)(nxt->cc, xt->data);
+
+ return nxt;
+}
+
+void VG_(XT_delete) ( XTree* xt )
+{
+ vg_assert(xt);
+
+ release_XT_shared(xt->shared);
+ xt->free_fn(xt->tmp_data);
+ VG_(deleteXA)(xt->data);
+ xt->free_fn(xt);
+}
+
+static Xecu find_or_insert (XTree* xt, ExeContext* ec)
+{
+
+ const UInt d4ecu = VG_(get_ECU_from_ExeContext)(ec) / 4;
+ XT_shared* shared = xt->shared;
+
+ /* First grow the d4ecu2xecu array if needed. */
+ if (d4ecu >= shared->d4ecu2xecu_sz) {
+ UInt old_sz = shared->d4ecu2xecu_sz;
+ UInt new_sz = (3 * d4ecu) / 2;
+
+ if (new_sz < 1000)
+ new_sz = 1000;
+ shared->d4ecu2xecu = VG_(realloc)(xt->cc, shared->d4ecu2xecu,
+ new_sz * sizeof(UInt));
+ shared->d4ecu2xecu_sz = new_sz;
+ for (UInt i = old_sz; i < new_sz; i++)
+ shared->d4ecu2xecu[i] = NO_OFFSET;
+ }
+
+ if (shared->d4ecu2xecu[d4ecu] == NO_OFFSET) {
+ xec xe;
+
+ xe.ec = ec;
+ if (xt->filter_IPs_fn == NULL) {
+ xe.top = 0;
+ xe.n_ips_sel = (UShort)VG_(get_ExeContext_n_ips)(xe.ec);
+ } else {
+ UInt top;
+ UInt n_ips_sel = VG_(get_ExeContext_n_ips)(xe.ec);
+ xt->filter_IPs_fn(VG_(get_ExeContext_StackTrace)(xe.ec), n_ips_sel,
+ &top, &n_ips_sel);
+ xe.top = (UShort)top;
+ xe.n_ips_sel = (UShort)n_ips_sel;
+ }
+ xt->init_data_fn(xt->tmp_data);
+ VG_(addToXA)(shared->xec, &xe);
+ shared->d4ecu2xecu[d4ecu] = (UInt)VG_(addToXA)(xt->data, xt->tmp_data);
+ }
+
+ return shared->d4ecu2xecu[d4ecu];
+}
+
+Xecu VG_(XT_add_to_ec) (XTree* xt, ExeContext* ec, const void* value)
+{
+ Xecu xecu = find_or_insert(xt, ec);
+ void* data = VG_(indexXA)(xt->data, xecu);
+
+ xt->add_data_fn(data, value);
+ return xecu;
+}
+
+Xecu VG_(XT_sub_from_ec) (XTree* xt, ExeContext* ec, const void* value)
+{
+ Xecu xecu = find_or_insert(xt, ec);
+ void* data = VG_(indexXA)(xt->data, xecu);
+
+ xt->sub_data_fn(data, value);
+ return xecu;
+}
+
+void VG_(XT_add_to_xecu) (XTree* xt, Xecu xecu, const void* value)
+{
+ void* data = VG_(indexXA)(xt->data, xecu);
+ xt->add_data_fn(data, value);
+}
+
+void VG_(XT_sub_from_xecu) (XTree* xt, Xecu xecu, const void* value)
+{
+ void* data = VG_(indexXA)(xt->data, xecu);
+ xt->sub_data_fn(data, value);
+}
+
+UInt VG_(XT_n_ips_sel) (XTree* xt, Xecu xecu)
+{
+ xec* xe = (xec*)VG_(indexXA)(xt->shared->xec, xecu);
+ return (UInt)xe->n_ips_sel;
+}
+
+ExeContext* VG_(XT_get_ec_from_xecu) (XTree* xt, Xecu xecu)
+{
+ xec* xe = (xec*)VG_(indexXA)(xt->shared->xec, xecu);
+ return xe->ec;
+}
+
+static VgFile* xt_open (const HChar* outfilename)
+{
+ VgFile* fp;
+
+ fp = VG_(fopen)(outfilename, VKI_O_CREAT|VKI_O_WRONLY|VKI_O_TRUNC,
+ VKI_S_IRUSR|VKI_S_IWUSR);
+ if (fp == NULL) {
+ VG_(message)(Vg_UserMsg,
+ "Error: can not open xtree output file `%s'\n",
+ outfilename);
+ }
+ return fp;
+}
+
+#define FP(format, args...) ({ VG_(fprintf)(fp, format, ##args); })
+
+// Print "cmd:" line.
+static void FP_cmd(VgFile* fp)
+{
+ UInt i;
+
+ FP("cmd: ");
+ FP("%s", VG_(args_the_exename));
+ for (i = 0; i < VG_(sizeXA)(VG_(args_for_client)); i++) {
+ HChar* arg = * (HChar**) VG_(indexXA)(VG_(args_for_client), i);
+ FP(" %s", arg);
+ }
+ FP("\n");
+}
+
+/* ----------- Callgrind output ------------------------------------------- */
+
+/* Output a callgrind format element in compressed format:
+ "name=(pos)" or "name=(pos) value" (if value_new)
+ or not compressed format: "name=value"
+ VG_(clo_xtree_compress_strings) indicates if the compressed format is used.
+ name is the format element (e.g. fl, fn, cfi, cfn, ...).
+ pos is the value dictionary position, used for compressed format.
+ value_new is True if this is the first usage of value. */
+static void FP_pos_str(VgFile* fp, const HChar* name, UInt pos,
+ const HChar* value, Bool value_new)
+{
+ if (!VG_(clo_xtree_compress_strings))
+ FP("%s=%s\n", name, value);
+ else if (value_new)
+ FP("%s=(%d) %s\n", name, pos, value);
+ else
+ FP("%s=(%d)\n", name, pos);
+}
+
+void VG_(XT_callgrind_print)
+ (XTree* xt,
+ const HChar* outfilename,
+ const HChar* events,
+ const HChar* (*img_value)(const void* value))
+{
+ UInt n_xecu;
+ XT_shared* shared = xt->shared;
+ VgFile* fp = xt_open(outfilename);
+ DedupPoolAlloc* fnname_ddpa;
+ DedupPoolAlloc* filename_ddpa;
+ HChar* filename_buf = NULL;
+ UInt filename_buf_size = 0;
+ const HChar* filename_dir;
+ const HChar* filename_name;
+
+ if (fp == NULL)
+ return;
+
+ fnname_ddpa = VG_(newDedupPA)(16000, 1, xt->alloc_fn,
+ "XT_callgrind_print.fn", xt->free_fn);
+ filename_ddpa = VG_(newDedupPA)(16000, 1, xt->alloc_fn,
+ "XT_callgrind_print.fl", xt->free_fn);
+
+ FP("# callgrind format\n");
+ FP("version: 1\n");
+ FP("creator: xtree-1\n");
+ FP("pid: %d\n", VG_(getpid)());
+ FP_cmd(fp);
+
+ /* Currently, we only need/support line positions. */
+ FP("\npositions:%s\n", " line");
+
+ /* Produce one "event:" line for each event, and the "events:" line. */
+ {
+ HChar strtok_events[VG_(strlen)(events)+1];
+ HChar* e;
+ HChar* ssaveptr;
+ HChar* p;
+
+ VG_(strcpy)(strtok_events, events);
+ for (e = VG_(strtok_r)(strtok_events, ",", &ssaveptr);
+ e != NULL;
+ e = VG_(strtok_r)(NULL, ",", &ssaveptr))
+ FP("event: %s\n", e);
+ FP("events:");
+ VG_(strcpy)(strtok_events, events);
+ for (e = VG_(strtok_r)(strtok_events, ",", &ssaveptr);
+ e != NULL;
+ e = VG_(strtok_r)(NULL, ",", &ssaveptr)) {
+ p = e;
+ while (*p) {
+ if (*p == ':')
+ *p = 0;
+ p++;
+ }
+ FP(" %s", e);
+ }
+ FP("\n");
+ }
+ xt->init_data_fn(xt->tmp_data); // to compute totals
+
+ n_xecu = VG_(sizeXA)(xt->data);
+ vg_assert (n_xecu <= VG_(sizeXA)(shared->xec));
+ for (Xecu xecu = 0; xecu < n_xecu; xecu++) {
+ xec* xe = (xec*)VG_(indexXA)(shared->xec, xecu);
+ if (xe->n_ips_sel == 0)
+ continue;
+
+ const HChar* img = img_value(VG_(indexXA)(xt->data, xecu));
+
+ // CALLED_FLF gets the Dir+Filename/Line number/Function name for ips[n]
+ // in the variables called_filename/called_linenum/called_fnname.
+ // The booleans called_filename_new/called_fnname_new are set to True
+ // the first time the called_filename/called_fnname are encountered.
+ // The called_filename_nr/called_fnname_nr are numbers identifying
+ // the strings called_filename/called_fnname.
+#define CALLED_FLF(n) \
+ if ((n) < 0 \
+ || !VG_(get_filename_linenum)(ips[(n)], \
+ &filename_name, \
+ &filename_dir, \
+ &called_linenum)) { \
+ filename_name = "UnknownFile???"; \
+ called_linenum = 0; \
+ } \
+ if ((n) < 0 \
+ || !VG_(get_fnname)(ips[(n)], &called_fnname)) { \
+ called_fnname = "UnknownFn???"; \
+ } \
+ { \
+ UInt needed_size = VG_(strlen)(filename_dir) + 1 \
+ + VG_(strlen)(filename_name) + 1; \
+ if (filename_buf_size < needed_size) { \
+ filename_buf_size = needed_size; \
+ filename_buf = VG_(realloc)(xt->cc, filename_buf, \
+ filename_buf_size); \
+ } \
+ } \
+ VG_(strcpy)(filename_buf, filename_dir); \
+ if (filename_buf[0] != '\0') { \
+ VG_(strcat)(filename_buf, "/"); \
+ } \
+ VG_(strcat)(filename_buf, filename_name); \
+ called_filename_nr = VG_(allocStrDedupPA)(filename_ddpa, \
+ filename_buf, \
+ &called_filename_new); \
+ called_filename = filename_buf; \
+ called_fnname_nr = VG_(allocStrDedupPA)(fnname_ddpa, \
+ called_fnname, \
+ &called_fnname_new);
+
+ /* Instead of unknown fnname ???, CALLED_FLF could use instead:
+ VG_(sprintf)(unknown_fn, "%p", (void*)ips[(n)]);
+ but that creates a lot of (useless) nodes at least for
+ valgrind self-hosting. */
+
+ if (img) {
+ const HChar* called_filename;
+ UInt called_filename_nr;
+ Bool called_filename_new; // True the first time we see this filename.
+ const HChar* called_fnname;
+ UInt called_fnname_nr;
+ Bool called_fnname_new; // True the first time we see this fnname.
+ UInt called_linenum;
+ UInt prev_linenum;
+
+ const Addr* ips = VG_(get_ExeContext_StackTrace)(xe->ec) + xe->top;
+ Int ips_idx = xe->n_ips_sel - 1;
+
+ if (0) {
+ VG_(printf)("entry img %s\n", img);
+ VG_(pp_ExeContext)(xe->ec);
+ VG_(printf)("\n");
+ }
+ xt->add_data_fn(xt->tmp_data, VG_(indexXA)(xt->data, xecu));
+ CALLED_FLF(ips_idx);
+ for (;
+ ips_idx >= 0;
+ ips_idx--) {
+ FP_pos_str(fp, "fl", called_filename_nr,
+ called_filename, called_filename_new);
+ FP_pos_str(fp, "fn", called_fnname_nr,
+ called_fnname, called_fnname_new);
+ if (ips_idx == 0)
+ FP("%d %s\n", called_linenum, img);
+ else
+ FP("%d\n", called_linenum); //no self cost.
+ prev_linenum = called_linenum;
+ if (ips_idx >= 1) {
+ CALLED_FLF(ips_idx-1);
+ FP_pos_str(fp, "cfi", called_filename_nr,
+ called_filename, called_filename_new);
+ FP_pos_str(fp, "cfn", called_fnname_nr,
+ called_fnname, called_fnname_new);
+ called_filename_new = False;
+ called_fnname_new = False;
+ /* Giving a call count of 0 allows kcachegrind to hide the calls
+ column. A call count of 1 means kcachegrind would show in the
+ calls column the nr of stacktrace containing this arc, which
+ is very confusing. So, the less bad is to give a 0 call
+ count. */
+ FP("calls=0 %d\n", called_linenum);
+ FP("%d %s\n", prev_linenum, img);
+ }
+ }
+ FP("\n");
+ }
+ }
+ /* callgrind format is not really fully supporting (yet?) execution trees:
+ in an execution tree, self and inclusive costs are identical, and
+ cannot be added together.
+ If no totals: line is given, callgrind_annotate calculates the addition
+ of all costs, and so gives a wrong totals.
+ Giving a totals: line solves this, but the user must give the option
+ --inclusive=yes (kind of hack) to have all the functions given
+ in the output file. */
+ FP("totals: %s\n", img_value(xt->tmp_data));
+ VG_(fclose)(fp);
+ VG_(deleteDedupPA)(fnname_ddpa);
+ VG_(deleteDedupPA)(filename_ddpa);
+ VG_(free)(filename_buf);
+}
+
+
+/* ----------- Massif output ---------------------------------------------- */
+
+/* For Massif output, some functions from the execontext are not output, a.o.
+ the allocation functions at the top of the stack and the functions below
+ main. So, the StackTrace of the execontexts in the xtree must be filtered.
+ Ms_Ec defines the subset of the stacktrace relevant for the report. */
+typedef
+ struct {
+ StackTrace ips; // ips and n_ips provides the subset of the xtree ec
+ UInt n_ips; // to use for a massif report.
+
+ SizeT report_value; // The value to report for this stack trace.
+ } Ms_Ec;
+
+/* Ms_Group defines (at a certain depth) a group of ec context that
+ have the same IPs at the given depth, and have the same 'parent'.
+ total is the sum of the values of all group elements.
+ A Ms_Group can also represent a set of ec contexts that do not
+ have the same IP, but that have each a total which is below the
+ significant size. Such a group has a NULL ms_ec, a zero group_io.
+ n_ec is the nr of insignificant ec that have been collected inside this
+ insignificant group, and total is the sum of all non significant ec
+ at the given depth. */
+typedef
+ struct {
+ Ms_Ec* ms_ec; // The group consists in ms_ec[0 .. n_ec-1]
+ Addr group_ip;
+ UInt n_ec;
+ SizeT total;
+ } Ms_Group;
+
+/* Compare 2 groups by total, to have bigger total first. */
+static Int ms_group_revcmp_total(const void* vleft, const void* vright)
+{
+ const Ms_Group* left = (const Ms_Group*)vleft;
+ const Ms_Group* right = (const Ms_Group*)vright;
+
+ // First reverse compare total
+ if (left->total > right->total) return -1;
+ if (left->total < right->total) return 1;
+
+ /* Equal size => compare IPs.
+ This (somewhat?) helps to have deterministic test results.
+ If this would change between platforms, then we should compare
+ function names/filename/linenr */
+ if (left->group_ip < right->group_ip) return -1;
+ if (left->group_ip > right->group_ip) return 1;
+ return 0;
+}
+
+/* Scan the addresses in ms_ec at the given depth.
+ On return,
+ *groups points to an array of Ms_Group sorted by total.
+ *n_groups is the nr of groups
+ The caller is responsible to free the allocated group array. */
+static void ms_make_groups (UInt depth, Ms_Ec* ms_ec, UInt n_ec, SizeT sig_sz,
+ UInt* n_groups, Ms_Group** groups)
+{
+ UInt i, g;
+ Addr cur_group_ip = 0;
+
+ *n_groups = 0;
+
+ /* Handle special case somewhat more efficiently */
+ if (n_ec == 0) {
+ *groups = NULL;
+ return;
+ }
+
+ /* Compute how many groups we have. */
+ for (i = 0; i < n_ec; i++) {
+ if (ms_ec[i].n_ips > depth
+ && (*n_groups == 0 || cur_group_ip != ms_ec[i].ips[depth])) {
+ (*n_groups)++;
+ cur_group_ip = ms_ec[i].ips[depth];
+ }
+ }
+
+ /* make the group array. */
+ *groups = VG_(malloc)("ms_make_groups", *n_groups * sizeof(Ms_Group));
+ i = 0;
+ for (g = 0; g < *n_groups; g++) {
+ while (ms_ec[i].n_ips <= depth)
+ i++;
+ cur_group_ip = ms_ec[i].ips[depth];
+ (*groups)[g].group_ip = cur_group_ip;
+ (*groups)[g].ms_ec = &ms_ec[i];
+ (*groups)[g].n_ec = 1;
+ (*groups)[g].total = ms_ec[i].report_value;
+ i++;
+ while (i < n_ec
+ && ms_ec[i].n_ips > depth
+ && cur_group_ip == ms_ec[i].ips[depth]) {
+ (*groups)[g].total += ms_ec[i].report_value;
+ i++;
+ (*groups)[g].n_ec++;
+ }
+ }
+
+ /* Search for insignificant groups, collect them all together
+ in the first insignificant group, and compact the group array. */
+ {
+ UInt insig1; // Position of first insignificant group.
+ UInt n_insig = 0; // Nr of insignificant groups found.
+
+ for (g = 0; g < *n_groups; g++) {
+ if ((*groups)[g].total < sig_sz) {
+ if (n_insig == 0) {
+ // First insig group => transform it into the special group
+ (*groups)[g].ms_ec = NULL;
+ (*groups)[g].group_ip = 0;
+ (*groups)[g].n_ec = 0;
+ // start the sum of insig total as total
+ insig1 = g;
+ } else {
+ // Add this insig group total into insig1 first group
+ (*groups)[insig1].total += (*groups)[g].total;
+ }
+ n_insig++;
+ } else {
+ if (n_insig > 1)
+ (*groups)[g - n_insig + 1] = (*groups)[g];
+ }
+ }
+ if (n_insig > 0) {
+ (*groups)[insig1].n_ec = n_insig;
+ *n_groups -= n_insig - 1;
+ }
+ DMSG(1, "depth %u n_groups %u n_insig %u\n", depth, *n_groups, n_insig);
+ }
+
+ /* Sort on total size, bigger size first. */
+ VG_(ssort)(*groups, *n_groups, sizeof(Ms_Group), ms_group_revcmp_total);
+}
+
+static void ms_output_group (VgFile* fp, UInt depth, Ms_Group* group,
+ SizeT sig_sz, double sig_pct_threshold)
+{
+ UInt i;
+ Ms_Group* groups;
+ UInt n_groups;
+
+ // If this is an insignificant group, handle it specially
+ if (group->ms_ec == NULL) {
+ const HChar* s = ( 1 == group->n_ec? "," : "s, all" );
+ vg_assert(group->group_ip == 0);
+ FP("%*sn0: %lu in %d place%s below massif's threshold (%.2f%%)\n",
+ depth+1, "", group->total, group->n_ec, s, sig_pct_threshold);
+ return;
+ }
+
+ // Normal group => output the group and its subgroups.
+ ms_make_groups(depth+1, group->ms_ec, group->n_ec, sig_sz,
+ &n_groups, &groups);
+
+ FP("%*s" "n%u: %ld %s\n",
+ depth + 1, "",
+ n_groups,
+ group->total,
+ VG_(describe_IP)(group->ms_ec->ips[depth] - 1, NULL));
+ /* XTREE??? Massif original code removes 1 to get the IP description. I am
+ wondering if this is not something that predates revision r8818,
+ which introduced a -1 in the stack unwind (see m_stacktrace.c)
+ Kept for the moment to allow exact comparison with massif output, but
+ probably we should remove this, as we very probably end up 2 bytes before
+ the RA Return Address. */
+
+ /* Output sub groups of this group. */
+ for (i = 0; i < n_groups; i++)
+ ms_output_group(fp, depth+1, &groups[i], sig_sz, sig_pct_threshold);
+
+ VG_(free)(groups);
+}
+
+/* Allocate and build an array of Ms_Ec sorted by addresses in the
+ Ms_Ec StackTrace. */
+static void prepare_ms_ec (XTree* xt,
+ ULong (*report_value)(const void* value),
+ ULong* top_total, Ms_Ec** vms_ec, UInt* vn_ec)
+{
+ XT_shared* shared = xt->shared;
+ const UInt n_xecu = VG_(sizeXA)(shared->xec);
+ const UInt n_data_xecu = VG_(sizeXA)(xt->data);
+ Ms_Ec* ms_ec = VG_(malloc)("XT_massif_print.ms_ec", n_xecu * sizeof(Ms_Ec));
+ UInt n_xecu_sel = 0; // Nr of xecu that are selected for output.
+
+ vg_assert(n_data_xecu <= n_xecu);
+
+ // Ensure we have in shared->ips_order_xecu our xecu sorted by StackTrace.
+ ensure_ips_order_xecu_valid(shared);
+
+ *top_total = 0;
+ DMSG(1, "iteration %u\n", n_xecu);
+ for (UInt i = 0; i < n_xecu; i++) {
+ Xecu xecu = *(Xecu*)VG_(indexXA)(shared->ips_order_xecu, i);
+ xec* xe = (xec*)VG_(indexXA)(shared->xec, xecu);
+
+ if (xecu >= n_data_xecu)
+ continue; // No data for this xecu in xt->data.
+ ms_ec[n_xecu_sel].n_ips = xe->n_ips_sel;
+ if (ms_ec[n_xecu_sel].n_ips == 0)
+ continue;
+
+ ms_ec[n_xecu_sel].ips = VG_(get_ExeContext_StackTrace)(xe->ec) + xe->top;
+ ms_ec[n_xecu_sel].report_value
+ = (*report_value)(VG_(indexXA)(xt->data, xecu));
+ *top_total += ms_ec[n_xecu_sel].report_value;
+
+ n_xecu_sel++;
+ }
+ vg_assert(n_xecu_sel <= n_xecu);
+
+ *vms_ec = ms_ec;
+ *vn_ec = n_xecu_sel;
+}
+
+MsFile* VG_(XT_massif_open)
+ (const HChar* outfilename,
+ const HChar* desc,
+ const XArray* desc_args,
+ const HChar* time_unit)
+{
+ UInt i;
+ VgFile* fp = xt_open(outfilename);
+
+ if (fp == NULL)
+ return NULL; // xt_open reported the error.
+
+ /* ------ file header ------------------------------- */
+ FP("desc:");
+ if (desc)
+ FP(" %s", desc);
+ i = 0;
+ if (desc_args) {
+ for (i = 0; i < VG_(sizeXA)(desc_args); i++) {
+ HChar* arg = *(HChar**)VG_(indexXA)(desc_args, i);
+ FP(" %s", arg);
+ }
+ }
+ if (0 == i && desc == NULL) FP(" (none)");
+ FP("\n");
+
+ FP_cmd(fp);
+
+ FP("time_unit: %s\n", time_unit);
+
+ return fp;
+}
+
+void VG_(XT_massif_close)(MsFile* fp)
+{
+ if (fp == NULL)
+ return; // Error should have been reported by VG_(XT_massif_open)
+
+ VG_(fclose)(fp);
+}
+
+void VG_(XT_massif_print)
+ (MsFile* fp,
+ XTree* xt,
+ const Massif_Header* header,
+ ULong (*report_value)(const void* value))
+{
+ UInt i;
+
+ if (fp == NULL)
+ return; // Normally VG_(XT_massif_open) already reported an error.
+
+ /* Compute/prepare Snapshot totals/data/... */
+ ULong top_total;
+
+ /* Following variables only used for detailed snapshot. */
+ UInt n_ec = 0;
+ Ms_Ec* ms_ec = NULL;
+ const HChar* kind =
+ header->detailed ? (header->peak ? "peak" : "detailed") : "empty";
+
+ DMSG(1, "XT_massif_print %s\n", kind);
+ if (header->detailed) {
+ /* Prepare the Ms_Ec sorted array of stacktraces and the groups
+ at level 0. */
+ prepare_ms_ec(xt, report_value, &top_total, &ms_ec, &n_ec);
+ DMSG(1, "XT_print_massif ms_ec n_ec %u\n", n_ec);
+ } else if (xt == NULL) {
+ /* Non detailed, no xt => use the sz provided in the header. */
+ top_total = header->sz_B;
+ } else {
+ /* For non detailed snapshot, compute total directly from the xec. */
+ const XT_shared* shared = xt->shared;
+ const UInt n_xecu = VG_(sizeXA)(xt->data);
+ top_total = 0;
+
+ for (UInt xecu = 0; xecu < n_xecu; xecu++) {
+ xec* xe = (xec*)VG_(indexXA)(shared->xec, xecu);
+ if (xe->n_ips_sel == 0)
+ continue;
+ top_total += (*report_value)(VG_(indexXA)(xt->data, xecu));
+ }
+ }
+
+ /* ------ snapshot header --------------------------- */
+ FP("#-----------\n");
+ FP("snapshot=%d\n", header->snapshot_n);
+ FP("#-----------\n");
+ FP("time=%lld\n", header->time);
+
+ FP("mem_heap_B=%llu\n", top_total); // without extra_B and without stacks_B
+ FP("mem_heap_extra_B=%llu\n", header->extra_B);
+ FP("mem_stacks_B=%llu\n", header->stacks_B);
+ FP("heap_tree=%s\n", kind);
+
+ /* ------ detailed snapshot data ----------------------------- */
+ if (header->detailed) {
+ UInt n_groups;
+ Ms_Group* groups;
+
+ ULong sig_sz;
+ // Work out how big a child must be to be significant. If the current
+ // top_total is zero, then we set it to 1, which means everything will be
+ // judged insignificant -- this is sensible, as there's no point showing
+ // any detail for this case. Unless they used threshold=0, in which
+ // case we show them everything because that's what they asked for.
+ //
+ // Nb: We do this once now, rather than once per child, because if we do
+ // that the cost of all the divisions adds up to something significant.
+ if (0 == top_total && 0 != header->sig_threshold)
+ sig_sz = 1;
+ else
+ sig_sz = ((top_total + header->extra_B + header->stacks_B)
+ * header->sig_threshold) / 100;
+
+ /* Produce the groups at depth 0 */
+ DMSG(1, "XT_massif_print producing depth 0 groups\n");
+ ms_make_groups(0, ms_ec, n_ec, sig_sz, &n_groups, &groups);
+
+ /* Output the top node. */
+ FP("n%u: %llu %s\n", n_groups, top_total, header->top_node_desc);
+
+ /* Output depth 0 groups. */
+ DMSG(1, "XT_massif_print outputing %u depth 0 groups\n", n_groups);
+ for (i = 0; i < n_groups; i++)
+ ms_output_group(fp, 0, &groups[i], sig_sz, header->sig_threshold);
+
+ VG_(free)(groups);
+ VG_(free)(ms_ec);
+ }
+}
+
+Int VG_(XT_offset_main_or_below_main)(Addr* ips, Int n_ips)
+{
+ /* Search for main or below main function.
+ To limit the nr of ips to examine, we maintain the deepest
+ offset where main was found, and we first search main
+ from there.
+ If no main is found, we will then do a search for main or
+ below main function till the top. */
+ static Int deepest_main = 0;
+ Vg_FnNameKind kind = Vg_FnNameNormal;
+ Int mbm = n_ips - 1; // Position of deepest main or below main.
+ Vg_FnNameKind mbmkind = Vg_FnNameNormal;
+ Int i;
+
+ for (i = n_ips - 1 - deepest_main;
+ i < n_ips;
+ i++) {
+ mbmkind = VG_(get_fnname_kind_from_IP)(ips[i]);
+ if (mbmkind != Vg_FnNameNormal) {
+ mbm = i;
+ break;
+ }
+ }
+
+ /* Search for main or below main function till top. */
+ for (i = mbm - 1;
+ i >= 0 && mbmkind != Vg_FnNameMain;
+ i--) {
+ kind = VG_(get_fnname_kind_from_IP)(ips[i]);
+ if (kind != Vg_FnNameNormal) {
+ mbm = i;
+ mbmkind = kind;
+ }
+ }
+ if (Vg_FnNameMain == mbmkind || Vg_FnNameBelowMain == mbmkind) {
+ if (mbmkind == Vg_FnNameMain && (n_ips - 1 - mbm) > deepest_main)
+ deepest_main = n_ips - 1 - mbm;
+ return mbm;
+ } else
+ return n_ips-1;
+}
+
+void VG_(XT_filter_1top_and_maybe_below_main)
+ (Addr* ips, Int n_ips,
+ UInt* top, UInt* n_ips_sel)
+{
+ Int mbm;
+
+ *n_ips_sel = n_ips;
+ if (n_ips == 0) {
+ *top = 0;
+ return;
+ }
+
+ /* Filter top function. */
+ *top = 1;
+
+ if (VG_(clo_show_below_main))
+ mbm = n_ips - 1;
+ else
+ mbm = VG_(XT_offset_main_or_below_main)(ips, n_ips);
+
+ *n_ips_sel = mbm - *top + 1;
+}
+
+void VG_(XT_filter_maybe_below_main)
+ (Addr* ips, Int n_ips,
+ UInt* top, UInt* n_ips_sel)
+{
+ Int mbm;
+
+ *n_ips_sel = n_ips;
+ *top = 0;
+ if (n_ips == 0)
+ return;
+
+ if (VG_(clo_show_below_main))
+ mbm = n_ips - 1;
+ else
+ mbm = VG_(XT_offset_main_or_below_main)(ips, n_ips);
+
+ *n_ips_sel = mbm - *top + 1;
+}
+
+/*--------------------------------------------------------------------*/
+/*--- end m_xtree.c ---*/
+/*--------------------------------------------------------------------*/
diff --git a/coregrind/pub_core_addrinfo.h b/coregrind/pub_core_addrinfo.h
index d5ee2db..48e1b4e 100644
--- a/coregrind/pub_core_addrinfo.h
+++ b/coregrind/pub_core_addrinfo.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2014-2015 Philippe Waroquiers
+ Copyright (C) 2014-2017 Philippe Waroquiers
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/pub_core_aspacehl.h b/coregrind/pub_core_aspacehl.h
index 66bca0c..3aef352 100644
--- a/coregrind/pub_core_aspacehl.h
+++ b/coregrind/pub_core_aspacehl.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2009-2015 Julian Seward
+ Copyright (C) 2009-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_aspacemgr.h b/coregrind/pub_core_aspacemgr.h
index a46b258..67ec528 100644
--- a/coregrind/pub_core_aspacemgr.h
+++ b/coregrind/pub_core_aspacemgr.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -337,7 +337,7 @@
#if defined(VGP_ppc32_linux) \
|| defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
|| defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \
- || defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
+ || defined(VGP_arm64_linux)
# define VG_STACK_GUARD_SZB 65536 // 1 or 16 pages
#else
# define VG_STACK_GUARD_SZB 8192 // 2 pages
diff --git a/coregrind/pub_core_basics.h b/coregrind/pub_core_basics.h
index 278e3dc..0d46ce5 100644
--- a/coregrind/pub_core_basics.h
+++ b/coregrind/pub_core_basics.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -96,10 +96,6 @@
ULong r31; /* Return address of the last subroutine call */
ULong r28;
} MIPS64;
- struct {
- ULong r52;
- ULong r55;
- } TILEGX;
} misc;
}
UnwindStartRegs;
diff --git a/coregrind/pub_core_basics_asm.h b/coregrind/pub_core_basics_asm.h
index 0dccce8..f3741d2 100644
--- a/coregrind/pub_core_basics_asm.h
+++ b/coregrind/pub_core_basics_asm.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_clientstate.h b/coregrind/pub_core_clientstate.h
index ddd1c09..73bd4e8 100644
--- a/coregrind/pub_core_clientstate.h
+++ b/coregrind/pub_core_clientstate.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_clreq.h b/coregrind/pub_core_clreq.h
index ce1493c..7a4a9e8 100644
--- a/coregrind/pub_core_clreq.h
+++ b/coregrind/pub_core_clreq.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_commandline.h b/coregrind/pub_core_commandline.h
index bac902e..06f659c 100644
--- a/coregrind/pub_core_commandline.h
+++ b/coregrind/pub_core_commandline.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_coredump.h b/coregrind/pub_core_coredump.h
index 851b3ff..5bb3da0 100644
--- a/coregrind/pub_core_coredump.h
+++ b/coregrind/pub_core_coredump.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_cpuid.h b/coregrind/pub_core_cpuid.h
index f34e56e..e228beb 100644
--- a/coregrind/pub_core_cpuid.h
+++ b/coregrind/pub_core_cpuid.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_debuginfo.h b/coregrind/pub_core_debuginfo.h
index 8f26f25..ae688e4 100644
--- a/coregrind/pub_core_debuginfo.h
+++ b/coregrind/pub_core_debuginfo.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -130,10 +130,6 @@
typedef
struct { Addr pc; Addr sp; Addr fp; Addr ra; }
D3UnwindRegs;
-#elif defined(VGA_tilegx)
-typedef
- struct { Addr pc; Addr sp; Addr fp; Addr lr; }
- D3UnwindRegs;
#else
# error "Unsupported arch"
#endif
@@ -153,7 +149,7 @@
/* True if some FPO information is loaded.
It is useless to call VG_(use_FPO_info) if this returns False.
- Note that the return value should preferrably be cached in
+ Note that the return value should preferably be cached in
the stack unwind code, and re-queried when the debug info generation
changes. */
extern Bool VG_(FPO_info_present)(void);
diff --git a/coregrind/pub_core_debuglog.h b/coregrind/pub_core_debuglog.h
index c5006ca..74bf2af 100644
--- a/coregrind/pub_core_debuglog.h
+++ b/coregrind/pub_core_debuglog.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_deduppoolalloc.h b/coregrind/pub_core_deduppoolalloc.h
index 956fe17..416110c 100644
--- a/coregrind/pub_core_deduppoolalloc.h
+++ b/coregrind/pub_core_deduppoolalloc.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2014-2015 Philippe Waroquiers philippe.waroquiers@skynet.be
+ Copyright (C) 2014-2017 Philippe Waroquiers philippe.waroquiers@skynet.be
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/pub_core_demangle.h b/coregrind/pub_core_demangle.h
index 57b2f7b..837d6f1 100644
--- a/coregrind/pub_core_demangle.h
+++ b/coregrind/pub_core_demangle.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_dispatch.h b/coregrind/pub_core_dispatch.h
index 222879b..4abef24 100644
--- a/coregrind/pub_core_dispatch.h
+++ b/coregrind/pub_core_dispatch.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_dispatch_asm.h b/coregrind/pub_core_dispatch_asm.h
index 297efa3..14c4cc7 100644
--- a/coregrind/pub_core_dispatch_asm.h
+++ b/coregrind/pub_core_dispatch_asm.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_errormgr.h b/coregrind/pub_core_errormgr.h
index 5dc01b7..c1cf5dc 100644
--- a/coregrind/pub_core_errormgr.h
+++ b/coregrind/pub_core_errormgr.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_execontext.h b/coregrind/pub_core_execontext.h
index b553cc0..cb52b46 100644
--- a/coregrind/pub_core_execontext.h
+++ b/coregrind/pub_core_execontext.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_gdbserver.h b/coregrind/pub_core_gdbserver.h
index eca92a0..ab9f755 100644
--- a/coregrind/pub_core_gdbserver.h
+++ b/coregrind/pub_core_gdbserver.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2015 Philippe Waroquiers
+ Copyright (C) 2011-2017 Philippe Waroquiers
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -230,7 +230,7 @@
} VgdbShared64;
// The below typedef makes the life of valgrind easier.
-// vgdb must however work explicitely with the specific 32 or 64 bits version.
+// vgdb must however work explicitly with the specific 32 or 64 bits version.
#if VEX_HOST_WORDSIZE == 8
typedef VgdbShared64 VgdbShared;
diff --git a/coregrind/pub_core_guest.h b/coregrind/pub_core_guest.h
index d7025c6..b1928c7 100644
--- a/coregrind/pub_core_guest.h
+++ b/coregrind/pub_core_guest.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2014-2015 OpenWorks LLP
+ Copyright (C) 2014-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_hashtable.h b/coregrind/pub_core_hashtable.h
index e5eb46f..506029c 100644
--- a/coregrind/pub_core_hashtable.h
+++ b/coregrind/pub_core_hashtable.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Nicholas Nethercote
+ Copyright (C) 2005-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_initimg.h b/coregrind/pub_core_initimg.h
index 276ab36..5ac4411 100644
--- a/coregrind/pub_core_initimg.h
+++ b/coregrind/pub_core_initimg.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2006-2015 OpenWorks LLP
+ Copyright (C) 2006-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_inner.h b/coregrind/pub_core_inner.h
index 0e59844..4dbf1b0 100644
--- a/coregrind/pub_core_inner.h
+++ b/coregrind/pub_core_inner.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2012-2015 Philippe Waroquiers
+ Copyright (C) 2012-2017 Philippe Waroquiers
philippe.waroquiers@skynet.be
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_libcassert.h b/coregrind/pub_core_libcassert.h
index 9313350..1ea5192 100644
--- a/coregrind/pub_core_libcassert.h
+++ b/coregrind/pub_core_libcassert.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_libcbase.h b/coregrind/pub_core_libcbase.h
index cdb4c49..36c2052 100644
--- a/coregrind/pub_core_libcbase.h
+++ b/coregrind/pub_core_libcbase.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_libcfile.h b/coregrind/pub_core_libcfile.h
index 9d32b9f..d36c762 100644
--- a/coregrind/pub_core_libcfile.h
+++ b/coregrind/pub_core_libcfile.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_libcprint.h b/coregrind/pub_core_libcprint.h
index 7b2d4a8..1bc9e12 100644
--- a/coregrind/pub_core_libcprint.h
+++ b/coregrind/pub_core_libcprint.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -38,16 +38,36 @@
#include "pub_tool_libcprint.h"
-/* An output file descriptor wrapped up with a Bool indicating whether
- or not the fd is a socket. */
typedef
- struct { Int fd; Bool is_socket; }
+ enum {
+ VgLogTo_Fd,
+ VgLogTo_File,
+ VgLogTo_Socket
+ }
+ VgLogTo;
+
+/* An output file descriptor wrapped up with its type and expanded name. */
+typedef
+ struct {
+ Int fd;
+ VgLogTo type;
+ HChar *fsname_expanded; // 'fs' stands for file or socket
+ }
OutputSink;
/* And the destinations for normal and XML output. */
extern OutputSink VG_(log_output_sink);
extern OutputSink VG_(xml_output_sink);
+/* Initializes normal log and xml sinks (of type fd, file, or socket).
+ Any problem encountered is considered a hard error and causes V. to exit. */
+extern void VG_(init_log_xml_sinks)(VgLogTo log_to, VgLogTo xml_to,
+ Int /*initial*/log_fd, Int /*initial*/xml_fd);
+
+extern void VG_(print_preamble)(Bool logging_to_fd);
+
+extern void VG_(logging_atfork_child)(ThreadId tid);
+
/* Get the elapsed wallclock time since startup into buf which has size
bufsize. The function will assert if bufsize is not large enough.
Upon return, buf will contain the zero-terminated wallclock time as
diff --git a/coregrind/pub_core_libcproc.h b/coregrind/pub_core_libcproc.h
index 1bb27ba..6ef5686 100644
--- a/coregrind/pub_core_libcproc.h
+++ b/coregrind/pub_core_libcproc.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -39,7 +39,7 @@
#include "config.h" // Crucial: ensure we get ENABLE_INNER
#include "pub_tool_libcproc.h"
-/* The directory we look for all our auxillary files in. Useful for
+/* The directory we look for all our auxiliary files in. Useful for
running Valgrind out of a build tree without having to do "make
install". Inner valgrinds require a different lib variable, else
they end up picking up .so's etc intended for the outer
diff --git a/coregrind/pub_core_libcsetjmp.h b/coregrind/pub_core_libcsetjmp.h
index 105c304..91c6801 100644
--- a/coregrind/pub_core_libcsetjmp.h
+++ b/coregrind/pub_core_libcsetjmp.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 Mozilla Inc
+ Copyright (C) 2010-2017 Mozilla Inc
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/pub_core_libcsignal.h b/coregrind/pub_core_libcsignal.h
index 8f45a46..5b22905 100644
--- a/coregrind/pub_core_libcsignal.h
+++ b/coregrind/pub_core_libcsignal.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_mach.h b/coregrind/pub_core_mach.h
index 3dd882c..eac1a61 100644
--- a/coregrind/pub_core_mach.h
+++ b/coregrind/pub_core_mach.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Apple Inc.
+ Copyright (C) 2005-2017 Apple Inc.
Greg Parker gparker@apple.com
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_machine.h b/coregrind/pub_core_machine.h
index a72381b..a8b8bc8 100644
--- a/coregrind/pub_core_machine.h
+++ b/coregrind/pub_core_machine.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -108,14 +108,6 @@
# define VG_ELF_MACHINE EM_MIPS
# define VG_ELF_CLASS ELFCLASS64
# undef VG_PLAT_USES_PPCTOC
-#elif defined(VGP_tilegx_linux)
-# define VG_ELF_DATA2XXX ELFDATA2LSB
- #ifndef EM_TILEGX
- #define EM_TILEGX 191
- #endif
-# define VG_ELF_MACHINE EM_TILEGX
-# define VG_ELF_CLASS ELFCLASS64
-# undef VG_PLAT_USES_PPCTOC
#else
# error Unknown platform
#endif
@@ -157,10 +149,6 @@
# define VG_INSTR_PTR guest_PC
# define VG_STACK_PTR guest_r29
# define VG_FRAME_PTR guest_r30
-#elif defined(VGA_tilegx)
-# define VG_INSTR_PTR guest_pc
-# define VG_STACK_PTR guest_r54
-# define VG_FRAME_PTR guest_r52
#else
# error Unknown arch
#endif
diff --git a/coregrind/pub_core_mallocfree.h b/coregrind/pub_core_mallocfree.h
index 87fe7d9..b59717b 100644
--- a/coregrind/pub_core_mallocfree.h
+++ b/coregrind/pub_core_mallocfree.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -81,7 +81,6 @@
defined(VGP_x86_darwin) || \
defined(VGP_amd64_darwin) || \
defined(VGP_arm64_linux) || \
- defined(VGP_tilegx_linux) || \
defined(VGP_amd64_solaris)
# define VG_MIN_MALLOC_SZB 16
#else
diff --git a/coregrind/pub_core_options.h b/coregrind/pub_core_options.h
index 7a887fc..88eeaf4 100644
--- a/coregrind/pub_core_options.h
+++ b/coregrind/pub_core_options.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -39,6 +39,9 @@
#include "pub_tool_options.h"
#include "pub_core_xarray.h"
+/* Valgrind tool name. Defaults to "memcheck". */
+extern const HChar *VG_(clo_toolname);
+
/* Should we stop collecting errors if too many appear? default: YES */
extern Bool VG_(clo_error_limit);
/* Alternative exit code to hand to parent if errors were found.
@@ -117,9 +120,9 @@
extern Bool VG_(clo_child_silent_after_fork);
/* If the user specified --log-file=STR and/or --xml-file=STR, these
- hold STR after expansion of the %p and %q templates. */
-extern const HChar* VG_(clo_log_fname_expanded);
-extern const HChar* VG_(clo_xml_fname_expanded);
+ hold STR before expansion. */
+extern const HChar *VG_(clo_log_fname_unexpanded);
+extern const HChar *VG_(clo_xml_fname_unexpanded);
/* Add timestamps to log messages? default: NO */
extern Bool VG_(clo_time_stamp);
@@ -207,7 +210,6 @@
extern Int VG_(clo_core_redzone_size);
// VG_(clo_redzone_size) has default value -1, indicating to keep
// the tool provided value.
-extern Int VG_(clo_redzone_size);
/* DEBUG: display gory details for the k'th most popular error.
default: Infinity. */
extern Int VG_(clo_dump_error);
@@ -220,14 +222,15 @@
SimHint_fuse_compatible,
SimHint_enable_outer,
SimHint_no_inner_prefix,
- SimHint_no_nptl_pthread_stackcache
+ SimHint_no_nptl_pthread_stackcache,
+ SimHint_fallback_llsc
}
SimHint;
// Build mask to check or set SimHint a membership
#define SimHint2S(a) (1 << (a))
// SimHint h is member of the Set s ?
-#define SimHintiS(h,s) ((s) & SimHint2S(h))
+#define SimHintiS(h,s) (((s) & SimHint2S(h)) != 0)
extern UInt VG_(clo_sim_hints);
/* Show symbols in the form 'name+offset' ? Default: NO */
diff --git a/coregrind/pub_core_oset.h b/coregrind/pub_core_oset.h
index 67a1e91..29a15bb 100644
--- a/coregrind/pub_core_oset.h
+++ b/coregrind/pub_core_oset.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Nicholas Nethercote
+ Copyright (C) 2005-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_poolalloc.h b/coregrind/pub_core_poolalloc.h
index 7744e8c..0d3c9d1 100644
--- a/coregrind/pub_core_poolalloc.h
+++ b/coregrind/pub_core_poolalloc.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2013-2015 Florian Krohm florian@eich-krohm.de
+ Copyright (C) 2013-2017 Florian Krohm florian@eich-krohm.de
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/pub_core_rangemap.h b/coregrind/pub_core_rangemap.h
index 39d24a4..9784eaf 100644
--- a/coregrind/pub_core_rangemap.h
+++ b/coregrind/pub_core_rangemap.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2014-2015 Mozilla Foundation
+ Copyright (C) 2014-2017 Mozilla Foundation
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/pub_core_redir.h b/coregrind/pub_core_redir.h
index 5d40429..fd4706f 100644
--- a/coregrind/pub_core_redir.h
+++ b/coregrind/pub_core_redir.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_replacemalloc.h b/coregrind/pub_core_replacemalloc.h
index 4cb3e6f..ea0fc3f 100644
--- a/coregrind/pub_core_replacemalloc.h
+++ b/coregrind/pub_core_replacemalloc.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_sbprofile.h b/coregrind/pub_core_sbprofile.h
index c17366d..2c53242 100644
--- a/coregrind/pub_core_sbprofile.h
+++ b/coregrind/pub_core_sbprofile.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2012-2015 Mozilla Foundation
+ Copyright (C) 2012-2017 Mozilla Foundation
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/pub_core_scheduler.h b/coregrind/pub_core_scheduler.h
index aa9610e..aef7ad8 100644
--- a/coregrind/pub_core_scheduler.h
+++ b/coregrind/pub_core_scheduler.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_seqmatch.h b/coregrind/pub_core_seqmatch.h
index 3e30e4d..fe384a2 100644
--- a/coregrind/pub_core_seqmatch.h
+++ b/coregrind/pub_core_seqmatch.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2015 OpenWorks Ltd
+ Copyright (C) 2008-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_sigframe.h b/coregrind/pub_core_sigframe.h
index 3e6b682..a8867ff 100644
--- a/coregrind/pub_core_sigframe.h
+++ b/coregrind/pub_core_sigframe.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_signals.h b/coregrind/pub_core_signals.h
index 88d7d62..6a65cf4 100644
--- a/coregrind/pub_core_signals.h
+++ b/coregrind/pub_core_signals.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_sparsewa.h b/coregrind/pub_core_sparsewa.h
index b1a210b..0d9dd10 100644
--- a/coregrind/pub_core_sparsewa.h
+++ b/coregrind/pub_core_sparsewa.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2015 OpenWorks Ltd
+ Copyright (C) 2008-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_stacks.h b/coregrind/pub_core_stacks.h
index 3d83f4e..0895d63 100644
--- a/coregrind/pub_core_stacks.h
+++ b/coregrind/pub_core_stacks.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_stacktrace.h b/coregrind/pub_core_stacktrace.h
index e8aee04..b7122f1 100644
--- a/coregrind/pub_core_stacktrace.h
+++ b/coregrind/pub_core_stacktrace.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_syscall.h b/coregrind/pub_core_syscall.h
index d8fe50e..b62d861 100644
--- a/coregrind/pub_core_syscall.h
+++ b/coregrind/pub_core_syscall.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -86,7 +86,6 @@
UWord a3 );
extern SysRes VG_(mk_SysRes_mips64_linux)( ULong v0, ULong v1,
ULong a3 );
-extern SysRes VG_(mk_SysRes_tilegx_linux)( Long val );
extern SysRes VG_(mk_SysRes_x86_solaris) ( Bool isErr, UInt val, UInt val2 );
extern SysRes VG_(mk_SysRes_amd64_solaris) ( Bool isErr, ULong val, ULong val2 );
extern SysRes VG_(mk_SysRes_Error) ( UWord val );
diff --git a/coregrind/pub_core_syswrap.h b/coregrind/pub_core_syswrap.h
index 0b5b54b..e8ba005 100644
--- a/coregrind/pub_core_syswrap.h
+++ b/coregrind/pub_core_syswrap.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_threadstate.h b/coregrind/pub_core_threadstate.h
index d2aa251..19a9982 100644
--- a/coregrind/pub_core_threadstate.h
+++ b/coregrind/pub_core_threadstate.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -114,6 +114,8 @@
ThreadArchState;
+#define NULL_STK_ID (~(UWord)0)
+
/* OS-specific thread state. IMPORTANT: if you add fields to this,
you _must_ add code to os_state_clear() to initialise those
fields. */
@@ -129,6 +131,12 @@
Addr valgrind_stack_base; // Valgrind's stack (VgStack*)
Addr valgrind_stack_init_SP; // starting value for SP
+ /* Client stack is registered as stk_id (on linux/darwin, by
+ ML_(guess_and_register_stack)).
+ Stack id NULL_STK_ID means that the user stack is not (yet)
+ registered. */
+ UWord stk_id;
+
/* exit details */
Word exitcode; // in the case of exitgroup, set by someone else
Int fatalsig; // fatal signal
@@ -281,10 +289,6 @@
the 64-bit offset associated with a %fs value of zero. */
# endif
- /* Stack id (value (UWord)(-1) means that there is no stack). This
- tracks a stack that is set in restore_stack(). */
- UWord stk_id;
-
/* Simulation of the kernel's lwp->lwp_ustack. Set in the PRE wrapper
of the getsetcontext syscall, for SETUSTACK. Used in
VG_(save_context)(), VG_(restore_context)() and
@@ -354,7 +358,9 @@
different values is during the execution of a sigsuspend, where
tmp_sig_mask is the temporary mask which sigsuspend installs.
It is only consulted to compute the signal mask applied to a
- signal handler. */
+ signal handler.
+ PW Nov 2016 : it is not clear if and where this tmp_sig_mask
+ is set when an handler runs "inside" a sigsuspend. */
vki_sigset_t tmp_sig_mask;
/* A little signal queue for signals we can't get the kernel to
@@ -401,6 +407,7 @@
/* This thread's name. NULL, if no name. */
HChar *thread_name;
+ UInt ptrace;
}
ThreadState;
@@ -409,11 +416,16 @@
/*--- The thread table. ---*/
/*------------------------------------------------------------*/
-/* A statically allocated array of threads. NOTE: [0] is
- never used, to simplify the simulation of initialisers for
- LinuxThreads. */
+/* An array of threads, dynamically allocated by VG_(init_Threads).
+ NOTE: [0] is never used, to simplify the simulation of initialisers
+ for LinuxThreads. */
extern ThreadState *VG_(threads);
+/* In an outer valgrind, VG_(inner_threads) stores the address of
+ the inner VG_(threads) array, as reported by the inner using
+ the client request INNER_THREADS. */
+extern ThreadState *VG_(inner_threads);
+
// The running thread. m_scheduler should be the only other module
// to write to this.
extern ThreadId VG_(running_tid);
diff --git a/coregrind/pub_core_tooliface.h b/coregrind/pub_core_tooliface.h
index 83758a8..e02969d 100644
--- a/coregrind/pub_core_tooliface.h
+++ b/coregrind/pub_core_tooliface.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_trampoline.h b/coregrind/pub_core_trampoline.h
index 1396519..3a9bafe 100644
--- a/coregrind/pub_core_trampoline.h
+++ b/coregrind/pub_core_trampoline.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -105,11 +105,6 @@
extern void* VG_(arm_linux_REDIR_FOR_strcmp)( void*, void* );
#endif
-#if defined(VGP_tilegx_linux)
-extern Addr VG_(tilegx_linux_SUBST_FOR_rt_sigreturn);
-extern UInt VG_(tilegx_linux_REDIR_FOR_strlen)( void* );
-#endif
-
#if defined(VGP_arm64_linux)
extern Addr VG_(arm64_linux_SUBST_FOR_rt_sigreturn);
extern ULong VG_(arm64_linux_REDIR_FOR_strlen)( void* );
@@ -154,11 +149,13 @@
#if defined(VGP_mips32_linux)
extern Addr VG_(mips32_linux_SUBST_FOR_sigreturn);
extern Addr VG_(mips32_linux_SUBST_FOR_rt_sigreturn);
+extern Char* VG_(mips32_linux_REDIR_FOR_index)( const Char*, Int );
extern UInt VG_(mips32_linux_REDIR_FOR_strlen)( void* );
#endif
#if defined(VGP_mips64_linux)
extern Addr VG_(mips64_linux_SUBST_FOR_rt_sigreturn);
+extern Char* VG_(mips64_linux_REDIR_FOR_index)( const Char*, Int );
extern UInt VG_(mips64_linux_REDIR_FOR_strlen)( void* );
#endif
diff --git a/coregrind/pub_core_translate.h b/coregrind/pub_core_translate.h
index 4c0b068..c54fae3 100644
--- a/coregrind/pub_core_translate.h
+++ b/coregrind/pub_core_translate.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_transtab.h b/coregrind/pub_core_transtab.h
index e9f3bc2..951cbd9 100644
--- a/coregrind/pub_core_transtab.h
+++ b/coregrind/pub_core_transtab.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -66,20 +66,20 @@
/* Limits for number of sectors the TC is divided into. If you need a larger
overall translation cache, increase MAX_N_SECTORS. */
#define MIN_N_SECTORS 2
-#define MAX_N_SECTORS 24
+#define MAX_N_SECTORS 48
-/* Default for the nr of sectors, if not overriden by command line.
+/* Default for the nr of sectors, if not overridden by command line.
On Android, space is limited, so try to get by with fewer sectors.
- On other platforms we can go to town. 16 sectors gives theoretical
- capacity of about 440MB of JITted code in 1.05 million translations
+ On other platforms we can go to town. 32 sectors gives theoretical
+ capacity of about 880MB of JITted code in 2.1 million translations
(realistically, about 2/3 of that) for Memcheck. */
#if defined(VGPV_arm_linux_android) \
|| defined(VGPV_x86_linux_android) \
|| defined(VGPV_mips32_linux_android) \
|| defined(VGPV_arm64_linux_android)
-# define N_SECTORS_DEFAULT 6
+# define N_SECTORS_DEFAULT 12
#else
-# define N_SECTORS_DEFAULT 16
+# define N_SECTORS_DEFAULT 32
#endif
extern
@@ -116,6 +116,7 @@
extern void VG_(print_tt_tc_stats) ( void );
extern UInt VG_(get_bbs_translated) ( void );
+extern UInt VG_(get_bbs_discarded_or_dumped) ( void );
/* Add to / search the auxiliary, small, unredirected translation
table. */
diff --git a/coregrind/pub_core_transtab_asm.h b/coregrind/pub_core_transtab_asm.h
index a54b393..e1e2687 100644
--- a/coregrind/pub_core_transtab_asm.h
+++ b/coregrind/pub_core_transtab_asm.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -66,9 +66,6 @@
|| defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_arm64)
# define VG_TT_FAST_HASH(_addr) ((((UWord)(_addr)) >> 2) & VG_TT_FAST_MASK)
-#elif defined(VGA_tilegx)
-# define VG_TT_FAST_HASH(_addr) ((((UWord)(_addr)) >> 3) & VG_TT_FAST_MASK)
-
#else
# error "VG_TT_FAST_HASH: unknown platform"
#endif
diff --git a/coregrind/pub_core_ume.h b/coregrind/pub_core_ume.h
index b20506a..7bf70c6 100644
--- a/coregrind/pub_core_ume.h
+++ b/coregrind/pub_core_ume.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_vki.h b/coregrind/pub_core_vki.h
index 8e88600..7fbcb01 100644
--- a/coregrind/pub_core_vki.h
+++ b/coregrind/pub_core_vki.h
@@ -8,11 +8,11 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
- Copyright (C) 2005-2015 Nicholas Nethercote
+ Copyright (C) 2005-2017 Nicholas Nethercote
njn@valgrind.org
- Copyright (C) 2006-2015 OpenWorks LLP
+ Copyright (C) 2006-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_vkiscnums.h b/coregrind/pub_core_vkiscnums.h
index dcdfc89..d402d08 100644
--- a/coregrind/pub_core_vkiscnums.h
+++ b/coregrind/pub_core_vkiscnums.h
@@ -7,11 +7,11 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
- Copyright (C) 2005-2015 Nicholas Nethercote
+ Copyright (C) 2005-2017 Nicholas Nethercote
njn@valgrind.org
- Copyright (C) 2006-2015 OpenWorks LLP
+ Copyright (C) 2006-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_vkiscnums_asm.h b/coregrind/pub_core_vkiscnums_asm.h
index b472edb..29b1f9b 100644
--- a/coregrind/pub_core_vkiscnums_asm.h
+++ b/coregrind/pub_core_vkiscnums_asm.h
@@ -7,11 +7,11 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
- Copyright (C) 2005-2015 Nicholas Nethercote
+ Copyright (C) 2005-2017 Nicholas Nethercote
njn@valgrind.org
- Copyright (C) 2006-2015 OpenWorks LLP
+ Copyright (C) 2006-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_wordfm.h b/coregrind/pub_core_wordfm.h
index 11dc830..4f504af 100644
--- a/coregrind/pub_core_wordfm.h
+++ b/coregrind/pub_core_wordfm.h
@@ -9,13 +9,13 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2007-2015 Julian Seward
+ Copyright (C) 2007-2017 Julian Seward
jseward@acm.org
This code is based on previous work by Nicholas Nethercote
(coregrind/m_oset.c) which is
- Copyright (C) 2005-2015 Nicholas Nethercote
+ Copyright (C) 2005-2017 Nicholas Nethercote
njn@valgrind.org
which in turn was derived partially from:
diff --git a/coregrind/pub_core_xarray.h b/coregrind/pub_core_xarray.h
index bbe5f94..c24f29b 100644
--- a/coregrind/pub_core_xarray.h
+++ b/coregrind/pub_core_xarray.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2007-2015 OpenWorks LLP
+ Copyright (C) 2007-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/coregrind/pub_core_xtmemory.h b/coregrind/pub_core_xtmemory.h
new file mode 100644
index 0000000..e44f5fe
--- /dev/null
+++ b/coregrind/pub_core_xtmemory.h
@@ -0,0 +1,42 @@
+
+/*--------------------------------------------------------------------*/
+/*--- Support functions for xtree memory reports. pub_tool_xtmemory.h ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2016-2017 Philippe Waroquiers
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#ifndef __PUB_CORE_XTMEMORY_H
+#define __PUB_CORE_XTMEMORY_H
+
+// No core-only exports; everything in this module is visible to both
+// the core and tools.
+
+#include "pub_tool_xtmemory.h"
+
+#endif // __PUB_CORE_XTMEMORY_H
+
+/*-----------------------------------------------------------------------*/
+/*--- end pub_core_xtmemory.h ---*/
+/*-----------------------------------------------------------------------*/
diff --git a/coregrind/pub_core_xtree.h b/coregrind/pub_core_xtree.h
new file mode 100644
index 0000000..7f8ba75
--- /dev/null
+++ b/coregrind/pub_core_xtree.h
@@ -0,0 +1,42 @@
+
+/*--------------------------------------------------------------------*/
+/*--- An xtree, tree of stacktraces with data pub_core_xtree.h ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2015-2017 Philippe Waroquiers
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#ifndef __PUB_CORE_XTREE_H
+#define __PUB_CORE_XTREE_H
+
+// No core-only exports; everything in this module is visible to both
+// the core and tools.
+
+#include "pub_tool_xtree.h"
+
+#endif // __PUB_CORE_XTREE_H
+
+/*--------------------------------------------------------------------*/
+/*--- end pub_core_xtree.h ---*/
+/*--------------------------------------------------------------------*/
diff --git a/coregrind/vg_preloaded.c b/coregrind/vg_preloaded.c
index 6f5ab8e..73de7ef 100644
--- a/coregrind/vg_preloaded.c
+++ b/coregrind/vg_preloaded.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -57,12 +57,12 @@
void VG_NOTIFY_ON_LOAD(freeres)(Vg_FreeresToRun to_run);
void VG_NOTIFY_ON_LOAD(freeres)(Vg_FreeresToRun to_run)
{
-# if !defined(__UCLIBC__) \
+# if !defined(__UCLIBC__) && !defined(MUSL_LIBC) \
&& !defined(VGPV_amd64_linux_android) \
&& !defined(VGPV_arm_linux_android) \
&& !defined(VGPV_x86_linux_android) \
&& !defined(VGPV_mips32_linux_android) \
- && !defined(VGPV_arm64_linux_android)
+ && !defined(VGPV_arm64_linux_android) \
/* g++ mangled __gnu_cxx::__freeres yields -> _ZN9__gnu_cxx9__freeresEv */
extern void _ZN9__gnu_cxx9__freeresEv(void) __attribute__((weak));
diff --git a/coregrind/vgdb-invoker-none.c b/coregrind/vgdb-invoker-none.c
index 4b1fe2d..1a755c4 100644
--- a/coregrind/vgdb-invoker-none.c
+++ b/coregrind/vgdb-invoker-none.c
@@ -6,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2015 Philippe Waroquiers
+ Copyright (C) 2011-2017 Philippe Waroquiers
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/vgdb-invoker-ptrace.c b/coregrind/vgdb-invoker-ptrace.c
index d65f59a..98092c7 100644
--- a/coregrind/vgdb-invoker-ptrace.c
+++ b/coregrind/vgdb-invoker-ptrace.c
@@ -6,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2015 Philippe Waroquiers
+ Copyright (C) 2011-2017 Philippe Waroquiers
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -510,7 +510,7 @@
if (!pid_found && pid) {
/* No threads are live. Process is busy stopping.
- We need to detach from pid explicitely. */
+ We need to detach from pid explicitly. */
DEBUG(1, "no thread live => PTRACE_DETACH pid %d\n", pid);
res = ptrace (PTRACE_DETACH, pid, NULL, NULL);
if (res != 0)
@@ -518,7 +518,7 @@
}
}
-# if defined(VGA_arm64) || defined(VGA_tilegx)
+# if defined(VGA_arm64)
/* arm64 is extra special, old glibc defined kernel user_pt_regs, but
newer glibc instead define user_regs_struct. */
# ifdef HAVE_SYS_USER_REGS
@@ -794,7 +794,7 @@
{
long res;
Bool stopped;
-# if defined(VGA_arm64) || defined(VGA_tilegx)
+# if defined(VGA_arm64)
/* arm64 is extra special, old glibc defined kernel user_pt_regs, but
newer glibc instead define user_regs_struct. */
# ifdef HAVE_SYS_USER_REGS
@@ -871,8 +871,6 @@
sp = p[29];
#elif defined(VGA_mips64)
sp = user_mod.regs[29];
-#elif defined(VGA_tilegx)
- sp = user_mod.sp;
#else
I_die_here : (sp) architecture missing in vgdb-invoker-ptrace.c
#endif
@@ -958,7 +956,7 @@
/* make stack space for args */
p[29] = sp - 32;
-#elif defined(VGA_mips64) || defined(VGA_tilegx)
+#elif defined(VGA_mips64)
assert(0); // cannot vgdb a 32 bits executable with a 64 bits exe
#else
I_die_here : architecture missing in vgdb-invoker-ptrace.c
@@ -1065,12 +1063,6 @@
user_mod.regs[31] = bad_return;
user_mod.regs[34] = shared64->invoke_gdbserver;
user_mod.regs[25] = shared64->invoke_gdbserver;
-#elif defined(VGA_tilegx)
- /* put check arg in register r0 */
- user_mod.regs[0] = check;
- /* put NULL return address in lr */
- user_mod.lr = bad_return;
- user_mod.pc = shared64->invoke_gdbserver;
#else
I_die_here: architecture missing in vgdb-invoker-ptrace.c
#endif
diff --git a/coregrind/vgdb-invoker-solaris.c b/coregrind/vgdb-invoker-solaris.c
index 019441b..8185e70 100644
--- a/coregrind/vgdb-invoker-solaris.c
+++ b/coregrind/vgdb-invoker-solaris.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2014-2015 Ivo Raisr <ivosh@ivosh.net>
+ Copyright (C) 2014-2017 Ivo Raisr <ivosh@ivosh.net>
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/coregrind/vgdb.c b/coregrind/vgdb.c
index f546011..8cf34ce 100644
--- a/coregrind/vgdb.c
+++ b/coregrind/vgdb.c
@@ -6,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2015 Philippe Waroquiers
+ Copyright (C) 2011-2017 Philippe Waroquiers
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -682,11 +682,7 @@
sigpipe++;
} else if (signum == SIGALRM) {
sigalrm++;
-#if defined(VGPV_amd64_linux_android) \
- || defined(VGPV_arm_linux_android) \
- || defined(VGPV_x86_linux_android) \
- || defined(VGPV_mips32_linux_android) \
- || defined(VGPV_arm64_linux_android)
+#if defined(__BIONIC__)
/* Android has no pthread_cancel. As it also does not have
an invoker implementation, there is no need for cleanup action.
So, we just do nothing. */
@@ -1011,7 +1007,7 @@
write_buf(to_pid, hexcommand, strlen(hexcommand),
"writing hex command to pid", /* notify */ True);
- /* we exit of the below loop explicitely when the command has
+ /* we exit of the below loop explicitly when the command has
been handled or because a signal handler will set
shutting_down. */
while (!shutting_down) {
diff --git a/coregrind/vgdb.h b/coregrind/vgdb.h
index 6d4c081..3854793 100644
--- a/coregrind/vgdb.h
+++ b/coregrind/vgdb.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2015 Philippe Waroquiers
+ Copyright (C) 2011-2017 Philippe Waroquiers
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/darwin16.supp b/darwin16.supp
index 91f48ff..b3f9dbd 100644
--- a/darwin16.supp
+++ b/darwin16.supp
@@ -525,6 +525,31 @@
}
{
+ OSX1012:dyld-3
+ Memcheck:Cond
+ fun:bcmp
+ fun:_ZN16ImageLoaderMachO18validateFirstPagesEPK21linkedit_data_commandiPKhmxRKN11ImageLoader11LinkContextE
+ ...
+}
+
+{
+ OSX1012:dyld-4
+ Memcheck:Value8
+ fun:bcmp
+ fun:_ZN16ImageLoaderMachO18validateFirstPagesEPK21linkedit_data_commandiPKhmxRKN11ImageLoader11LinkContextE
+ ...
+}
+
+{
+ OSX1012:dyld-5
+ Memcheck:Cond
+ fun:_ZN16ImageLoaderMachO18validateFirstPagesEPK21linkedit_data_commandiPKhmxRKN11ImageLoader11LinkContextE
+ fun:_ZN26ImageLoaderMachOCompressed19instantiateFromFileEPKciPKhmyyRK4statjjPK21linkedit_data_commandPK23encryption_info_commandRKN11ImageLoader11LinkContextE
+ fun:_ZN16ImageLoaderMachO19instantiateFromFileEPKciPKhmyyRK4statRKN11ImageLoader11LinkContextE
+ fun:_ZN4dyldL10loadPhase6EiRK4statPKcRKNS_11LoadContextE
+}
+
+{
OSX1012:libsystem_kernel-1
Memcheck:Cond
obj:*libsystem_kernel*dylib*
diff --git a/docs/Makefile.am b/docs/Makefile.am
index 43f80b1..81e644c 100644
--- a/docs/Makefile.am
+++ b/docs/Makefile.am
@@ -19,6 +19,7 @@
images/next.png \
images/prev.png \
images/up.png \
+ images/kcachegrind_xtree.png \
internals/3_0_BUGSTATUS.txt \
internals/3_1_BUGSTATUS.txt \
internals/3_2_BUGSTATUS.txt \
@@ -30,6 +31,7 @@
internals/3_9_BUGSTATUS.txt \
internals/3_10_BUGSTATUS.txt \
internals/3_11_BUGSTATUS.txt \
+ internals/3_12_BUGSTATUS.txt \
internals/MERGE_3_10_1.txt \
internals/arm_thumb_notes_gdbserver.txt \
internals/avx-notes.txt \
@@ -173,6 +175,7 @@
export XML_CATALOG_FILES=$(XML_CATALOG_FILES) && \
mkdir -p $(myprintdir) && \
mkdir -p $(myprintdir)/images && \
+ cp $(myimgdir)/*.png $(myprintdir)/images && \
$(XSLTPROC) $(XSLTPROC_FLAGS) -o $(myprintdir)/index.fo $(XSL_FO_STYLE) $(myxmldir)/index.xml && \
(cd $(myprintdir) && \
( pdfxmltex index.fo && \
diff --git a/docs/Makefile.in b/docs/Makefile.in
index f5e4db9..904c378 100644
--- a/docs/Makefile.in
+++ b/docs/Makefile.in
@@ -163,6 +163,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -303,6 +304,7 @@
images/next.png \
images/prev.png \
images/up.png \
+ images/kcachegrind_xtree.png \
internals/3_0_BUGSTATUS.txt \
internals/3_1_BUGSTATUS.txt \
internals/3_2_BUGSTATUS.txt \
@@ -314,6 +316,7 @@
internals/3_9_BUGSTATUS.txt \
internals/3_10_BUGSTATUS.txt \
internals/3_11_BUGSTATUS.txt \
+ internals/3_12_BUGSTATUS.txt \
internals/MERGE_3_10_1.txt \
internals/arm_thumb_notes_gdbserver.txt \
internals/avx-notes.txt \
@@ -640,6 +643,7 @@
export XML_CATALOG_FILES=$(XML_CATALOG_FILES) && \
mkdir -p $(myprintdir) && \
mkdir -p $(myprintdir)/images && \
+ cp $(myimgdir)/*.png $(myprintdir)/images && \
$(XSLTPROC) $(XSLTPROC_FLAGS) -o $(myprintdir)/index.fo $(XSL_FO_STYLE) $(myxmldir)/index.xml && \
(cd $(myprintdir) && \
( pdfxmltex index.fo && \
diff --git a/docs/README b/docs/README
index 2f4c57e..676d660 100644
--- a/docs/README
+++ b/docs/README
@@ -81,6 +81,24 @@
Below are random notes and recollections about how to build PDF / PS
documents from the XML source at various times on various Linux distros.
+Notes [May 2017]
+----------------
+Fedora 25: the "Notes [Sept 2015]" are still valid. But to summarise,
+two steps are necessary:
+
+(1) install packages as listed below
+(2) apply Mark's epstopdf-base.sty hack as documented in "Notes [Mar 2015]"
+
+Packages to install:
+
+ sudo dnf install texlive-xmltex texlive-xmltex-bin texlive-xmltex-doc \
+ texlive dblatex texlive-xmltex docbook-style-xsl docbook-dtds \
+ docbook-style-xsl.noarch docbook-simple.noarch docbook-simple.noarch \
+ docbook-slides.noarch docbook-style-dsssl.noarch docbook-utils.noarch \
+ docbook-utils-pdf.noarch docbook5-schemas.noarch \
+ docbook5-style-xsl.noarch passivetex
+
+
Notes [Sept 2015]
-----------------
Fedora 21 and 22: Had mucho trouble with building the print docs on
diff --git a/docs/callgrind_annotate.1 b/docs/callgrind_annotate.1
index 09a57d3..c99fb4c 100644
--- a/docs/callgrind_annotate.1
+++ b/docs/callgrind_annotate.1
@@ -1,13 +1,13 @@
'\" t
.\" Title: Callgrind Annotate
.\" Author: [see the "Author" section]
-.\" Generator: DocBook XSL Stylesheets v1.78.1 <http://docbook.sf.net/>
-.\" Date: 10/21/2016
-.\" Manual: Release 3.12.0
-.\" Source: Release 3.12.0
+.\" Generator: DocBook XSL Stylesheets v1.79.1 <http://docbook.sf.net/>
+.\" Date: 06/15/2017
+.\" Manual: Release 3.13.0
+.\" Source: Release 3.13.0
.\" Language: English
.\"
-.TH "CALLGRIND ANNOTATE" "1" "10/21/2016" "Release 3.12.0" "Release 3.12.0"
+.TH "CALLGRIND ANNOTATE" "1" "06/15/2017" "Release 3.13.0" "Release 3.13.0"
.\" -----------------------------------------------------------------
.\" * Define some portability stuff
.\" -----------------------------------------------------------------
@@ -56,6 +56,8 @@
\fB\-\-sort=A,B,C\fR
.RS 4
Sort columns by events A,B,C [event column order]\&.
+.sp
+Optionally, each event is followed by a : and a threshold, to specify different thresholds depending on the event\&.
.RE
.PP
\fB\-\-threshold=<0\-\-100> [default: 99%] \fR
diff --git a/docs/callgrind_control.1 b/docs/callgrind_control.1
index af68603..1073f0a 100644
--- a/docs/callgrind_control.1
+++ b/docs/callgrind_control.1
@@ -1,13 +1,13 @@
'\" t
.\" Title: Callgrind Control
.\" Author: [see the "Author" section]
-.\" Generator: DocBook XSL Stylesheets v1.78.1 <http://docbook.sf.net/>
-.\" Date: 10/21/2016
-.\" Manual: Release 3.12.0
-.\" Source: Release 3.12.0
+.\" Generator: DocBook XSL Stylesheets v1.79.1 <http://docbook.sf.net/>
+.\" Date: 06/15/2017
+.\" Manual: Release 3.13.0
+.\" Source: Release 3.13.0
.\" Language: English
.\"
-.TH "CALLGRIND CONTROL" "1" "10/21/2016" "Release 3.12.0" "Release 3.12.0"
+.TH "CALLGRIND CONTROL" "1" "06/15/2017" "Release 3.13.0" "Release 3.13.0"
.\" -----------------------------------------------------------------
.\" * Define some portability stuff
.\" -----------------------------------------------------------------
diff --git a/docs/cg_annotate.1 b/docs/cg_annotate.1
index 61eb993..ad81d40 100644
--- a/docs/cg_annotate.1
+++ b/docs/cg_annotate.1
@@ -1,13 +1,13 @@
'\" t
.\" Title: cg_annotate
.\" Author: [see the "Author" section]
-.\" Generator: DocBook XSL Stylesheets v1.78.1 <http://docbook.sf.net/>
-.\" Date: 10/21/2016
-.\" Manual: Release 3.12.0
-.\" Source: Release 3.12.0
+.\" Generator: DocBook XSL Stylesheets v1.79.1 <http://docbook.sf.net/>
+.\" Date: 06/15/2017
+.\" Manual: Release 3.13.0
+.\" Source: Release 3.13.0
.\" Language: English
.\"
-.TH "CG_ANNOTATE" "1" "10/21/2016" "Release 3.12.0" "Release 3.12.0"
+.TH "CG_ANNOTATE" "1" "06/15/2017" "Release 3.13.0" "Release 3.13.0"
.\" -----------------------------------------------------------------
.\" * Define some portability stuff
.\" -----------------------------------------------------------------
diff --git a/docs/cg_diff.1 b/docs/cg_diff.1
index 88878c2..3e83131 100644
--- a/docs/cg_diff.1
+++ b/docs/cg_diff.1
@@ -1,13 +1,13 @@
'\" t
.\" Title: cg_diff
.\" Author: [see the "Author" section]
-.\" Generator: DocBook XSL Stylesheets v1.78.1 <http://docbook.sf.net/>
-.\" Date: 10/21/2016
-.\" Manual: Release 3.12.0
-.\" Source: Release 3.12.0
+.\" Generator: DocBook XSL Stylesheets v1.79.1 <http://docbook.sf.net/>
+.\" Date: 06/15/2017
+.\" Manual: Release 3.13.0
+.\" Source: Release 3.13.0
.\" Language: English
.\"
-.TH "CG_DIFF" "1" "10/21/2016" "Release 3.12.0" "Release 3.12.0"
+.TH "CG_DIFF" "1" "06/15/2017" "Release 3.13.0" "Release 3.13.0"
.\" -----------------------------------------------------------------
.\" * Define some portability stuff
.\" -----------------------------------------------------------------
diff --git a/docs/cg_merge.1 b/docs/cg_merge.1
index 9ed8827..ab7891e 100644
--- a/docs/cg_merge.1
+++ b/docs/cg_merge.1
@@ -1,13 +1,13 @@
'\" t
.\" Title: cg_merge
.\" Author: [see the "Author" section]
-.\" Generator: DocBook XSL Stylesheets v1.78.1 <http://docbook.sf.net/>
-.\" Date: 10/21/2016
-.\" Manual: Release 3.12.0
-.\" Source: Release 3.12.0
+.\" Generator: DocBook XSL Stylesheets v1.79.1 <http://docbook.sf.net/>
+.\" Date: 06/15/2017
+.\" Manual: Release 3.13.0
+.\" Source: Release 3.13.0
.\" Language: English
.\"
-.TH "CG_MERGE" "1" "10/21/2016" "Release 3.12.0" "Release 3.12.0"
+.TH "CG_MERGE" "1" "06/15/2017" "Release 3.13.0" "Release 3.13.0"
.\" -----------------------------------------------------------------
.\" * Define some portability stuff
.\" -----------------------------------------------------------------
diff --git a/docs/html/FAQ.html b/docs/html/FAQ.html
index 17c6491..d71a37b 100644
--- a/docs/html/FAQ.html
+++ b/docs/html/FAQ.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>Valgrind FAQ</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="index.html" title="Valgrind Documentation">
<link rel="prev" href="nl-manual.html" title="14. Nulgrind: the minimal Valgrind tool">
@@ -22,10 +22,10 @@
<div>
<div><h1 class="title">
<a name="FAQ"></a>Valgrind FAQ</h1></div>
-<div><p class="releaseinfo">Release 3.12.0 20 October 2016</p></div>
-<div><p class="copyright">Copyright © 2000-2016 <a class="ulink" href="http://www.valgrind.org/info/developers.html" target="_top">Valgrind Developers</a></p></div>
+<div><p class="releaseinfo">Release 3.13.0 15 June 2017</p></div>
+<div><p class="copyright">Copyright © 2000-2017 <a class="ulink" href="http://www.valgrind.org/info/developers.html" target="_top">Valgrind Developers</a></p></div>
<div><div class="legalnotice">
-<a name="idm140639119221280"></a><p>Email: <a class="ulink" href="mailto:valgrind@valgrind.org" target="_top">valgrind@valgrind.org</a></p>
+<a name="idm140394923825504"></a><p>Email: <a class="ulink" href="mailto:valgrind@valgrind.org" target="_top">valgrind@valgrind.org</a></p>
</div></div>
</div>
<hr>
diff --git a/docs/html/QuickStart.html b/docs/html/QuickStart.html
index a304edb..89d8ffc 100644
--- a/docs/html/QuickStart.html
+++ b/docs/html/QuickStart.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>The Valgrind Quick Start Guide</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="index.html" title="Valgrind Documentation">
<link rel="prev" href="index.html" title="Valgrind Documentation">
@@ -22,10 +22,10 @@
<div>
<div><h1 class="title">
<a name="QuickStart"></a>The Valgrind Quick Start Guide</h1></div>
-<div><p class="releaseinfo">Release 3.12.0 20 October 2016</p></div>
-<div><p class="copyright">Copyright © 2000-2016 <a class="ulink" href="http://www.valgrind.org/info/developers.html" target="_top">Valgrind Developers</a></p></div>
+<div><p class="releaseinfo">Release 3.13.0 15 June 2017</p></div>
+<div><p class="copyright">Copyright © 2000-2017 <a class="ulink" href="http://www.valgrind.org/info/developers.html" target="_top">Valgrind Developers</a></p></div>
<div><div class="legalnotice">
-<a name="idm140639120054432"></a><p>Email: <a class="ulink" href="mailto:valgrind@valgrind.org" target="_top">valgrind@valgrind.org</a></p>
+<a name="idm140394929811680"></a><p>Email: <a class="ulink" href="mailto:valgrind@valgrind.org" target="_top">valgrind@valgrind.org</a></p>
</div></div>
</div>
<hr>
diff --git a/docs/html/bbv-manual.html b/docs/html/bbv-manual.html
index 2039193..b8981b0 100644
--- a/docs/html/bbv-manual.html
+++ b/docs/html/bbv-manual.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>12. BBV: an experimental basic block vector generation tool</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="manual.html" title="Valgrind User Manual">
<link rel="prev" href="sg-manual.html" title="11. SGCheck: an experimental stack and global array overrun detector">
diff --git a/docs/html/cg-manual.html b/docs/html/cg-manual.html
index fabf6fa..99ec6cd 100644
--- a/docs/html/cg-manual.html
+++ b/docs/html/cg-manual.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>5. Cachegrind: a cache and branch-prediction profiler</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="manual.html" title="Valgrind User Manual">
<link rel="prev" href="mc-manual.html" title="4. Memcheck: a memory error detector">
diff --git a/docs/html/cl-format.html b/docs/html/cl-format.html
index 7cf30de..4c35b5a 100644
--- a/docs/html/cl-format.html
+++ b/docs/html/cl-format.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>3. Callgrind Format Specification</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="tech-docs.html" title="Valgrind Technical Documentation">
<link rel="prev" href="manual-writing-tools.html" title="2. Writing a New Valgrind Tool">
@@ -41,9 +41,7 @@
</dl></dd>
</dl>
</div>
-<p>This chapter describes the Callgrind Profile Format, Version 1.</p>
-<p>A synonymous name is "Calltree Profile Format". These names actually mean
-the same since Callgrind was previously named Calltree.</p>
+<p>This chapter describes the Callgrind Format, Version 1.</p>
<p>The format description is meant for the user to be able to understand the
file contents; but more important, it is given for authors of measurement or
visualization tools to be able to write and read this format.</p>
@@ -59,6 +57,9 @@
<div class="sect2">
<div class="titlepage"><div><div><h3 class="title">
<a name="cl-format.overview.basics"></a>3.1.1. Basic Structure</h3></div></div></div>
+<p>To uniquely specify that a file is a callgrind profile, it
+should add "# callgrind format" as first line. This is optional but
+recommended for easy format detection.</p>
<p>Each file has a header part of an arbitrary number of lines of the
format "key: value". After the header, lines specifying profile costs
follow. Everywhere, comments on own lines starting with '#' are allowed.
@@ -85,7 +86,8 @@
However, any profiling tool could use the format described in this chapter.</p>
<p>
</p>
-<pre class="screen">events: Cycles Instructions Flops
+<pre class="screen"># callgrind format
+events: Cycles Instructions Flops
fl=file.f
fn=main
15 90 14 2
@@ -147,8 +149,10 @@
<code class="function">main</code> calls <code class="function">func1</code> once and
<code class="function">func2</code> 3 times. <code class="function">func1</code> calls
<code class="function">func2</code> 2 times.
+
</p>
-<pre class="screen">events: Instructions
+<pre class="screen"># callgrind format
+events: Instructions
fl=file1.c
fn=main
@@ -197,9 +201,10 @@
integer ID to a name, and "spec=(ID)" to reference a previously defined ID
mapping. There is a separate ID mapping for each position specification,
i.e. you can use ID 1 for both a file name and a symbol name.</p>
-<p>With string compression, the example from 1.4 looks like this:
+<p>With string compression, the example from above looks like this:
</p>
-<pre class="screen">events: Instructions
+<pre class="screen"># callgrind format
+events: Instructions
fl=(1) file1.c
fn=(1) main
@@ -228,7 +233,8 @@
define name compression mappings directly after the header, and before any cost
lines. Thus, the above example can also be written as
</p>
-<pre class="screen">events: Instructions
+<pre class="screen"># callgrind format
+events: Instructions
# define file ID mapping
fl=(1) file1.c
@@ -265,7 +271,8 @@
Assume the following example (subpositions can always be specified
as hexadecimal numbers, beginning with "0x"):
</p>
-<pre class="screen">positions: instr line
+<pre class="screen"># callgrind format
+positions: instr line
events: ticks
fn=func
@@ -274,7 +281,8 @@
0x80001238 91 6</pre>
<p>With subposition compression, this looks like
</p>
-<pre class="screen">positions: instr line
+<pre class="screen"># callgrind format
+positions: instr line
events: ticks
fn=func
@@ -328,7 +336,10 @@
<a name="cl-format.reference.grammar"></a>3.2.1. Grammar</h3></div></div></div>
<p>
</p>
-<pre class="screen">ProfileDataFile := FormatVersion? Creator? PartData*</pre>
+<pre class="screen">ProfileDataFile := FormatSpec? FormatVersion? Creator? PartData*</pre>
+<p>
+</p>
+<pre class="screen">FormatSpec := "# callgrind format\n"</pre>
<p>
</p>
<pre class="screen">FormatVersion := "version: 1\n"</pre>
@@ -451,7 +462,7 @@
<p>
</p>
<p>A profile data file ("ProfileDataFile") starts with basic information
- such as the version and creator information, and then has a list of parts, where
+ such as a format marker, the version and creator information, and then has a list of parts, where
each part has its own header and body. Parts typically are different threads
and/or time spans/phases within a profiled application run.</p>
<p>Note that callgrind_annotate currently only supports profile data files with
@@ -464,11 +475,22 @@
<p>Basic information in the first lines of a profile data file:</p>
<div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; ">
<li class="listitem">
+<p><code class="computeroutput"># callgrind format</code> [Callgrind]</p>
+<p>This line specifies that the file is a callgrind profile,
+ and it has to be the first line. It was added late to the
+ format (with Valgrind 3.13) and is optional, as all readers also
+ should work with older callgrind profiles not including this line.
+ However, generation of this line is recommended to allow desktop
+ environments and file managers to uniquely detect the format.</p>
+</li>
+<li class="listitem">
<p><code class="computeroutput">version: number</code> [Callgrind]</p>
<p>This is used to distinguish future profile data formats. A
major version of 0 or 1 is supposed to be upwards compatible with
Cachegrind's format. It is optional; if not appearing, version 1
- is assumed. Otherwise, this has to be the first header line.</p>
+ is assumed. Otherwise, it has to follow directly after the format
+ specification (i.e. be the first line if the optional format
+ specification is skipped).</p>
</li>
<li class="listitem">
<p><code class="computeroutput">creator: string</code> [Callgrind]</p>
diff --git a/docs/html/cl-manual.html b/docs/html/cl-manual.html
index 35f29cf..2cc4e95 100644
--- a/docs/html/cl-manual.html
+++ b/docs/html/cl-manual.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>6. Callgrind: a call-graph generating cache and branch prediction profiler</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="manual.html" title="Valgrind User Manual">
<link rel="prev" href="cg-manual.html" title="5. Cachegrind: a cache and branch-prediction profiler">
@@ -315,7 +315,7 @@
what is happening within a given function or starting from a given
program phase. To this end, you can disable event aggregation for
uninteresting program parts. While attribution of events to
- functions as well as producing seperate output per program phase
+ functions as well as producing separate output per program phase
can be done by other means (see previous section), there are two
benefits by disabling aggregation. First, this is very
fine-granular (e.g. just for a loop within a function). Second,
@@ -423,7 +423,7 @@
cycles, this does not hold true: callees of a function in a cycle include
the function itself. Therefore, KCachegrind does cycle detection
and skips visualization of any inclusive cost for calls inside
- of cycles. Further, all functions in a cycle are collapsed into artifical
+ of cycles. Further, all functions in a cycle are collapsed into artificial
functions called like <code class="computeroutput">Cycle 1</code>.</p>
<p>Now, when a program exposes really big cycles (as is
true for some GUI code, or in general code using event or callback based
@@ -1005,7 +1005,7 @@
</dt>
<dd><p>Start full Callgrind instrumentation if not already enabled.
When cache simulation is done, this will flush the simulated cache
- and lead to an artifical cache warmup phase afterwards with
+ and lead to an artificial cache warmup phase afterwards with
cache misses which would not have happened in reality. See also
option <code class="option"><a class="xref" href="cl-manual.html#opt.instr-atstart">--instr-atstart</a></code>.</p></dd>
<dt>
@@ -1040,7 +1040,11 @@
<dt><span class="term">
<code class="option">--sort=A,B,C</code>
</span></dt>
-<dd><p>Sort columns by events A,B,C [event column order].</p></dd>
+<dd>
+<p>Sort columns by events A,B,C [event column order].</p>
+<p>Optionally, each event is followed by a : and a threshold,
+ to specify different thresholds depending on the event.</p>
+</dd>
<dt><span class="term">
<code class="option">--threshold=<0--100> [default: 99%] </code>
</span></dt>
diff --git a/docs/html/design-impl.html b/docs/html/design-impl.html
index 22f8c6e..6571555 100644
--- a/docs/html/design-impl.html
+++ b/docs/html/design-impl.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>1. The Design and Implementation of Valgrind</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="tech-docs.html" title="Valgrind Technical Documentation">
<link rel="prev" href="tech-docs.html" title="Valgrind Technical Documentation">
diff --git a/docs/html/dh-manual.html b/docs/html/dh-manual.html
index 4557e7d..4b4356f 100644
--- a/docs/html/dh-manual.html
+++ b/docs/html/dh-manual.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>10. DHAT: a dynamic heap analysis tool</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="manual.html" title="Valgrind User Manual">
<link rel="prev" href="ms-manual.html" title="9. Massif: a heap profiler">
@@ -26,9 +26,9 @@
<dt><span class="sect1"><a href="dh-manual.html#dh-manual.overview">10.1. Overview</a></span></dt>
<dt><span class="sect1"><a href="dh-manual.html#dh-manual.understanding">10.2. Understanding DHAT's output</a></span></dt>
<dd><dl>
-<dt><span class="sect2"><a href="dh-manual.html#idm140639117126160">10.2.1. Interpreting the max-live, tot-alloc and deaths fields</a></span></dt>
-<dt><span class="sect2"><a href="dh-manual.html#idm140639113841488">10.2.2. Interpreting the acc-ratios fields</a></span></dt>
-<dt><span class="sect2"><a href="dh-manual.html#idm140639116741152">10.2.3. Interpreting "Aggregated access counts by offset" data</a></span></dt>
+<dt><span class="sect2"><a href="dh-manual.html#idm140394924138288">10.2.1. Interpreting the max-live, tot-alloc and deaths fields</a></span></dt>
+<dt><span class="sect2"><a href="dh-manual.html#idm140394926128304">10.2.2. Interpreting the acc-ratios fields</a></span></dt>
+<dt><span class="sect2"><a href="dh-manual.html#idm140394925890256">10.2.3. Interpreting "Aggregated access counts by offset" data</a></span></dt>
</dl></dd>
<dt><span class="sect1"><a href="dh-manual.html#dh-manual.options">10.3. DHAT Command-line Options</a></span></dt>
</dl>
@@ -90,9 +90,9 @@
numbers. That is best illustrated via a set of examples.</p>
<div class="sect2">
<div class="titlepage"><div><div><h3 class="title">
-<a name="idm140639117126160"></a>10.2.1. Interpreting the max-live, tot-alloc and deaths fields</h3></div></div></div>
+<a name="idm140394924138288"></a>10.2.1. Interpreting the max-live, tot-alloc and deaths fields</h3></div></div></div>
<div class="sect3"><div class="titlepage"><div><div><h4 class="title">
-<a name="idm140639117125456"></a>10.2.1.1. A simple example</h4></div></div></div></div>
+<a name="idm140394924137584"></a>10.2.1.1. A simple example</h4></div></div></div></div>
<pre class="screen">
======== SUMMARY STATISTICS ========
@@ -123,7 +123,7 @@
for 1,045,339,534 instructions, and so the average age at death is
about 2% of the program's total run time.</p>
<div class="sect3"><div class="titlepage"><div><div><h4 class="title">
-<a name="idm140639113980544"></a>10.2.1.2. Example of a potential process-lifetime leak</h4></div></div></div></div>
+<a name="idm140394923815680"></a>10.2.1.2. Example of a potential process-lifetime leak</h4></div></div></div></div>
<p>This next example (from a different program than the above)
shows a potential process lifetime leak. A process lifetime leak
occurs when a program keeps allocating data, but only frees the
@@ -158,9 +158,9 @@
</div>
<div class="sect2">
<div class="titlepage"><div><div><h3 class="title">
-<a name="idm140639113841488"></a>10.2.2. Interpreting the acc-ratios fields</h3></div></div></div>
+<a name="idm140394926128304"></a>10.2.2. Interpreting the acc-ratios fields</h3></div></div></div>
<div class="sect3"><div class="titlepage"><div><div><h4 class="title">
-<a name="idm140639113840736"></a>10.2.2.1. A fairly harmless allocation point record</h4></div></div></div></div>
+<a name="idm140394923814880"></a>10.2.2.1. A fairly harmless allocation point record</h4></div></div></div></div>
<pre class="screen">
max-live: 49,398 in 808 blocks
tot-alloc: 1,481,940 in 24,240 blocks (avg size 61.13)
@@ -193,7 +193,7 @@
that they must have varying sizes since the average block size, 61.13,
isn't a whole number.</p>
<div class="sect3"><div class="titlepage"><div><div><h4 class="title">
-<a name="idm140639118134560"></a>10.2.2.2. A more suspicious looking example</h4></div></div></div></div>
+<a name="idm140394922011696"></a>10.2.2.2. A more suspicious looking example</h4></div></div></div></div>
<pre class="screen">
max-live: 180,224 in 22 blocks
tot-alloc: 180,224 in 22 blocks (avg size 8192.00)
@@ -213,7 +213,7 @@
DHAT can tell us, that Memcheck can't, is that not only are the blocks
leaked, they are also never used.</p>
<div class="sect3"><div class="titlepage"><div><div><h4 class="title">
-<a name="idm140639111498432"></a>10.2.2.3. Another suspicious example</h4></div></div></div></div>
+<a name="idm140394922008704"></a>10.2.2.3. Another suspicious example</h4></div></div></div></div>
<p>Here's one where blocks are allocated, written to,
but never read from. We see this immediately from the zero read
access ratio. They do get freed, though:</p>
@@ -241,7 +241,7 @@
</div>
<div class="sect2">
<div class="titlepage"><div><div><h3 class="title">
-<a name="idm140639116741152"></a>10.2.3. Interpreting "Aggregated access counts by offset" data</h3></div></div></div>
+<a name="idm140394925890256"></a>10.2.3. Interpreting "Aggregated access counts by offset" data</h3></div></div></div>
<p>For allocation points that always allocate blocks of the same
size, and which are 4096 bytes or smaller, DHAT counts accesses
per offset, for example:</p>
@@ -341,7 +341,7 @@
</dl>
</div>
<p>One important point to note is that each allocation stack counts
-as a seperate allocation point. Because stacks by default have 12
+as a separate allocation point. Because stacks by default have 12
frames, this tends to spread data out over multiple allocation points.
You may want to use the flag --num-callers=4 or some such small
number, to reduce the spreading.</p>
diff --git a/docs/html/dist.authors.html b/docs/html/dist.authors.html
index b69494e..9c895b2 100644
--- a/docs/html/dist.authors.html
+++ b/docs/html/dist.authors.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>1. AUTHORS</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="dist.html" title="Valgrind Distribution Documents">
<link rel="prev" href="dist.html" title="Valgrind Distribution Documents">
diff --git a/docs/html/dist.html b/docs/html/dist.html
index b50087b..26c14ee 100644
--- a/docs/html/dist.html
+++ b/docs/html/dist.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>Valgrind Distribution Documents</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="index.html" title="Valgrind Documentation">
<link rel="prev" href="cl-format.html" title="3. Callgrind Format Specification">
@@ -22,10 +22,10 @@
<div>
<div><h1 class="title">
<a name="dist"></a>Valgrind Distribution Documents</h1></div>
-<div><p class="releaseinfo">Release 3.12.0 20 October 2016</p></div>
-<div><p class="copyright">Copyright © 2000-2016 <a class="ulink" href="http://www.valgrind.org/info/developers.html" target="_top">Valgrind Developers</a></p></div>
+<div><p class="releaseinfo">Release 3.13.0 15 June 2017</p></div>
+<div><p class="copyright">Copyright © 2000-2017 <a class="ulink" href="http://www.valgrind.org/info/developers.html" target="_top">Valgrind Developers</a></p></div>
<div><div class="legalnotice">
-<a name="idm140639116581280"></a><p>Email: <a class="ulink" href="mailto:valgrind@valgrind.org" target="_top">valgrind@valgrind.org</a></p>
+<a name="idm140394926016768"></a><p>Email: <a class="ulink" href="mailto:valgrind@valgrind.org" target="_top">valgrind@valgrind.org</a></p>
</div></div>
</div>
<hr>
diff --git a/docs/html/dist.news.html b/docs/html/dist.news.html
index cb91bf8..048fe05 100644
--- a/docs/html/dist.news.html
+++ b/docs/html/dist.news.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>2. NEWS</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="dist.html" title="Valgrind Distribution Documents">
<link rel="prev" href="dist.authors.html" title="1. AUTHORS">
@@ -21,7 +21,266 @@
<div class="titlepage"><div><div><h1 class="title">
<a name="dist.news"></a>2. NEWS</h1></div></div></div>
<div class="literallayout"><p><br>
- <br>
+ Release 3.13.0 (15 June 2017)<br>
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~<br>
+<br>
+3.13.0 is a feature release with many improvements and the usual collection of<br>
+bug fixes.<br>
+<br>
+This release supports X86/Linux, AMD64/Linux, ARM32/Linux, ARM64/Linux,<br>
+PPC32/Linux, PPC64BE/Linux, PPC64LE/Linux, S390X/Linux, MIPS32/Linux,<br>
+MIPS64/Linux, ARM/Android, ARM64/Android, MIPS32/Android, X86/Android,<br>
+X86/Solaris, AMD64/Solaris and AMD64/MacOSX 10.12.<br>
+<br>
+* ==================== CORE CHANGES ===================<br>
+<br>
+* The translation cache size has been increased to keep up with the demands of<br>
+ large applications. The maximum number of sectors has increased from 24 to<br>
+ 48. The default number of sectors has increased from 16 to 32 on all<br>
+ targets except Android, where the increase is from 6 to 12.<br>
+<br>
+* The amount of memory that Valgrind can use has been increased from 64GB to<br>
+ 128GB. In particular this means your application can allocate up to about<br>
+ 60GB when running on Memcheck.<br>
+<br>
+* Valgrind's default load address has been changed from 0x3800'0000 to<br>
+ 0x5800'0000, so as to make it possible to load larger executables. This<br>
+ should make it possible to load executables of size at least 1200MB.<br>
+<br>
+* A massive spaceleak caused by reading compressed debuginfo files has been<br>
+ fixed. Valgrind should now be entirely usable with gcc-7.0 "-gz" created<br>
+ debuginfo.<br>
+<br>
+* The C++ demangler has been updated.<br>
+<br>
+* Support for demangling Rust symbols has been added.<br>
+<br>
+* A new representation of stack traces, the "XTree", has been added. An XTree<br>
+ is a tree of stacktraces with data associated with the stacktraces. This is<br>
+ used by various tools (Memcheck, Helgrind, Massif) to report on the heap<br>
+ consumption of your program. Reporting is controlled by the new options<br>
+ --xtree-memory=none|allocs|full and --xtree-memory-file=<file>.<br>
+<br>
+ A report can also be produced on demand using the gdbserver monitor command<br>
+ 'xtmemory [<filename>]>'. The XTree can be output in 2 formats: 'callgrind<br>
+ format' and 'massif format. The existing visualisers for these formats (e.g.<br>
+ callgrind_annotate, KCachegrind, ms_print) can be used to visualise and<br>
+ analyse these reports.<br>
+<br>
+ Memcheck can also produce XTree leak reports using the Callgrind file<br>
+ format. For more details, see the user manual.<br>
+<br>
+* ================== PLATFORM CHANGES =================<br>
+<br>
+* ppc64: support for ISA 3.0B and various fixes for existing 3.0 support<br>
+<br>
+* amd64: fixes for JIT failure problems on long AVX2 code blocks<br>
+<br>
+* amd64 and x86: support for CET prefixes has been added<br>
+<br>
+* arm32: a few missing ARMv8 instructions have been implemented<br>
+<br>
+* arm64, mips64, mips32: an alternative implementation of Load-Linked and<br>
+ Store-Conditional instructions has been added. This is to deal with<br>
+ processor implementations that implement the LL/SC specifications strictly<br>
+ and as a result cause Valgrind to hang in certain situations. The<br>
+ alternative implementation is automatically enabled at startup, as required.<br>
+ You can use the option --sim-hints=fallback-llsc to force-enable it if you<br>
+ want.<br>
+<br>
+* Support for OSX 10.12 has been improved.<br>
+<br>
+* On Linux, clone handling has been improved to honour CLONE_VFORK that<br>
+ involves a child stack. Note however that CLONE_VFORK | CLONE_VM is handled<br>
+ like CLONE_VFORK (by removing CLONE_VM), so applications that depend on<br>
+ CLONE_VM exact semantics will (still) not work.<br>
+<br>
+* The TileGX/Linux port has been removed because it appears to be both unused<br>
+ and unsupported.<br>
+<br>
+* ==================== TOOL CHANGES ====================<br>
+<br>
+* Memcheck:<br>
+<br>
+ - Memcheck should give fewer false positives when running optimised<br>
+ Clang/LLVM generated code.<br>
+<br>
+ - Support for --xtree-memory and 'xtmemory [<filename>]>'.<br>
+<br>
+ - New command line options --xtree-leak=no|yes and --xtree-leak-file=<file><br>
+ to produce the end of execution leak report in a xtree callgrind format<br>
+ file.<br>
+<br>
+ - New option 'xtleak' in the memcheck leak_check monitor command, to produce<br>
+ the leak report in an xtree file.<br>
+<br>
+* Massif:<br>
+<br>
+ - Support for --xtree-memory and 'xtmemory [<filename>]>'.<br>
+<br>
+ - For some workloads (typically, for big applications), Massif memory<br>
+ consumption and CPU consumption has decreased significantly.<br>
+<br>
+* Helgrind:<br>
+<br>
+ - Support for --xtree-memory and 'xtmemory [<filename>]>'.<br>
+<br>
+ - addition of client request VALGRIND_HG_GNAT_DEPENDENT_MASTER_JOIN, useful<br>
+ for Ada gnat compiled applications.<br>
+<br>
+* ==================== OTHER CHANGES ====================<br>
+<br>
+* For Valgrind developers: in an outer/inner setup, the outer Valgrind will<br>
+ append the inner guest stacktrace to the inner host stacktrace. This helps<br>
+ to investigate the errors reported by the outer, when they are caused by the<br>
+ inner guest program (such as an inner regtest). See README_DEVELOPERS for<br>
+ more info.<br>
+<br>
+* To allow fast detection of callgrind files by desktop environments and file<br>
+ managers, the format was extended to have an optional first line that<br>
+ uniquely identifies the format ("# callgrind format"). Callgrind creates<br>
+ this line now, as does the new xtree functionality.<br>
+<br>
+* File name template arguments (such as --log-file, --xtree-memory-file, ...)<br>
+ have a new %n format letter that is replaced by a sequence number.<br>
+<br>
+* "--version -v" now shows the SVN revision numbers from which Valgrind was<br>
+ built.<br>
+<br>
+* ==================== FIXED BUGS ====================<br>
+<br>
+The following bugs have been fixed or resolved. Note that "n-i-bz"<br>
+stands for "not in bugzilla" -- that is, a bug that was reported to us<br>
+but never got a bugzilla entry. We encourage you to file bugs in<br>
+bugzilla (https://bugs.kde.org/enter_bug.cgi?product=valgrind) rather<br>
+than mailing the developers (or mailing lists) directly -- bugs that<br>
+are not entered into bugzilla tend to get forgotten about or ignored.<br>
+<br>
+To see details of a given bug, visit<br>
+ https://bugs.kde.org/show_bug.cgi?id=XXXXXX<br>
+where XXXXXX is the bug number as listed below.<br>
+<br>
+162848 --log-file output isn't split when a program forks<br>
+340777 Illegal instruction on mips (ar71xx)<br>
+341481 MIPS64: Iop_CmpNE32 triggers false warning on MIPS64 platforms<br>
+342040 Valgrind mishandles clone with CLONE_VFORK | CLONE_VM that clones<br>
+ to a different stack.<br>
+344139 x86 stack-seg overrides, needed by the Wine people<br>
+344524 store conditional of guest applications always fail - observed on<br>
+ Octeon3(MIPS)<br>
+348616 Wine/valgrind: noted but unhandled ioctl 0x5390 [..] (DVD_READ_STRUCT)<br>
+352395 Please provide SVN revision info in --version -v<br>
+352767 Wine/valgrind: noted but unhandled ioctl 0x5307 [..] (CDROMSTOP)<br>
+356374 Assertion 'DRD_(g_threadinfo)[tid].pt_threadid !=<br>
+ INVALID_POSIX_THREADID' failed<br>
+358213 helgrind/drd bar_bad testcase hangs or crashes with new glibc pthread<br>
+ barrier implementation<br>
+358697 valgrind.h: Some code remains even when defining NVALGRIND<br>
+359202 Add musl libc configure/compile<br>
+360415 amd64 instructions ADCX and ADOX are not implemented in VEX<br>
+ == 372828 (vex amd64->IR: 0x66 0xF 0x3A 0x62 0x4A 0x10)<br>
+360429 unhandled ioctl 0x530d with no size/direction hints (CDROMREADMODE1)<br>
+362223 assertion failed when .valgrindrc is a directory instead of a file<br>
+367543 bt/btc/btr/bts x86/x86_64 instructions are poorly-handled wrt flags<br>
+367942 Segfault vgPlain_do_sys_sigaction (m_signals.c:1138)<br>
+368507 can't malloc chunks larger than about 34GB<br>
+368529 Android arm target link error, missing atexit and pthread_atfork<br>
+368863 WARNING: unhandled arm64-linux syscall: 100 (get_robust_list)<br>
+368865 WARNING: unhandled arm64-linux syscall: 272 (kcmp)<br>
+368868 disInstr(arm64): unhandled instruction 0xD53BE000 = cntfrq_el0 (ARMv8)<br>
+368917 WARNING: unhandled arm64-linux syscall: 218 (request_key)<br>
+368918 WARNING: unhandled arm64-linux syscall: 127 (sched_rr_get_interval)<br>
+368922 WARNING: unhandled arm64-linux syscall: 161 (sethostname)<br>
+368924 WARNING: unhandled arm64-linux syscall: 84 (sync_file_range)<br>
+368925 WARNING: unhandled arm64-linux syscall: 130 (tkill)<br>
+368926 WARNING: unhandled arm64-linux syscall: 97 (unshare)<br>
+369459 valgrind on arm64 violates the ARMv8 spec (ldxr/stxr)<br>
+370028 Reduce the number of compiler warnings on MIPS platforms<br>
+370635 arm64 missing syscall getcpu<br>
+371225 Fix order of timer_{gettime,getoverrun,settime} syscalls on arm64<br>
+371227 Clean AArch64 syscall table<br>
+371412 Rename wrap_sys_shmat to sys_shmat like other wrappers<br>
+371471 Valgrind complains about non legit memory leaks on placement new (C++)<br>
+371491 handleAddrOverrides() is [incorrect] when ASO prefix is used<br>
+371503 disInstr(arm64): unhandled instruction 0xF89F0000<br>
+371869 support '%' in symbol Z-encoding<br>
+371916 execution tree xtree concept<br>
+372120 c++ demangler demangles symbols which are not c++<br>
+372185 Support of valgrind on ARMv8 with 32 bit executable<br>
+372188 vex amd64->IR: 0x66 0xF 0x3A 0x62 0x4A 0x10 0x10 0x48 (PCMPxSTRx $0x10)<br>
+372195 Power PC, xxsel instruction is not always recognized.<br>
+372504 Hanging on exit_group<br>
+372600 process loops forever when fatal signals are arriving quickly<br>
+372794 LibVEX (arm32 front end): 'Assertion szBlg2 <= 3' failed<br>
+373046 Stacks registered by core are never deregistered<br>
+373069 memcheck/tests/leak_cpp_interior fails with GCC 5.1+<br>
+373086 Implement additional Xen hypercalls<br>
+373192 Calling posix_spawn in glibc 2.24 completely broken<br>
+373488 Support for fanotify API on ARM64 architecture<br>
+ == 368864 WARNING: unhandled arm64-linux syscall: 262 (fanotify_init)<br>
+373555 Rename BBPTR to GSPTR as it denotes guest state pointer only<br>
+373938 const IRExpr arguments for matchIRExpr()<br>
+374719 some spelling fixes<br>
+374963 increase valgrind's load address to prevent mmap failure<br>
+375514 valgrind_get_tls_addr() does not work in case of static TLS<br>
+375772 +1 error in get_elf_symbol_info() when computing value of 'hi' address<br>
+ for ML_(find_rx_mapping)()<br>
+375806 Test helgrind/tests/tc22_exit_w_lock fails with glibc 2.24<br>
+375839 Temporary storage exhausted, with long sequence of vfmadd231ps insns<br>
+ == 377159 "vex: the `impossible' happened" still present<br>
+ == 375150 Assertion 'tres.status == VexTransOK' failed<br>
+ == 378068 valgrind crashes on AVX2 function in FFmpeg<br>
+376142 Segfaults on MIPS Cavium Octeon boards<br>
+376279 disInstr(arm64): unhandled instruction 0xD50320FF<br>
+376455 Solaris: unhandled syscall lgrpsys(180)<br>
+376518 Solaris: unhandled fast trap getlgrp(6)<br>
+376611 ppc64 and arm64 don't know about prlimit64 syscall<br>
+376729 PPC64, remove R2 from the clobber list<br>
+ == 371668<br>
+376956 syswrap of SNDDRV and DRM_IOCTL_VERSION causing some addresses<br>
+ to be wrongly marked as addressable<br>
+377066 Some Valgrind unit tests fail to compile on Ubuntu 16.10 with<br>
+ PIE enabled by default<br>
+377376 memcheck/tests/linux/getregset fails with glibc2.24<br>
+377427 PPC64, lxv instruction failing on odd destination register <br>
+377478 PPC64: ISA 3.0 setup fixes<br>
+377698 Missing memory check for futex() uaddr arg for FUTEX_WAKE<br>
+ and FUTEX_WAKE_BITSET, check only 4 args for FUTEX_WAKE_BITSET,<br>
+ and 2 args for FUTEX_TRYLOCK_PI<br>
+377717 Fix massive space leak when reading compressed debuginfo sections<br>
+377891 Update Xen 4.6 domctl wrappers<br>
+377930 fcntl syscall wrapper is missing flock structure check<br>
+378524 libvexmultiarch_test regression on s390x and ppc64<br>
+378535 Valgrind reports INTERNAL ERROR in execve syscall wrapper<br>
+378673 Update libiberty demangler<br>
+378931 Add ISA 3.0B additional isnstructions, add OV32, CA32 setting support<br>
+379039 syscall wrapper for prctl(PR_SET_NAME) must not check more than 16 bytes<br>
+379094 Valgrind reports INTERNAL ERROR in rt_sigsuspend syscall wrapper<br>
+379371 UNKNOWN task message [id 3444, to mach_task_self(), reply 0x603]<br>
+ (task_register_dyld_image_infos)<br>
+379372 UNKNOWN task message [id 3447, to mach_task_self(), reply 0x603]<br>
+ (task_register_dyld_shared_cache_image_info)<br>
+379390 unhandled syscall: mach:70 (host_create_mach_voucher_trap)<br>
+379473 MIPS: add support for rdhwr cycle counter register<br>
+379504 remove TileGX/Linux port<br>
+379525 Support more x86 nop opcodes<br>
+379838 disAMode(x86): not an addr!<br>
+379703 PC ISA 3.0 fixes: stxvx, stxv, xscmpexpdp instructions<br>
+379890 arm: unhandled instruction: 0xEBAD 0x1B05 (sub.w fp, sp, r5, lsl #4)<br>
+379895 clock_gettime does not execute POST syscall wrapper<br>
+379925 PPC64, mtffs does not set the FPCC and C bits in the FPSCR correctly<br>
+379966 WARNING: unhandled amd64-linux syscall: 313 (finit_module)<br>
+380200 xtree generated callgrind files refer to files without directory name<br>
+380202 Assertion failure for cache line size (cls == 64) on aarch64.<br>
+380397 s390x: __GI_strcspn() replacement needed<br>
+n-i-bz Fix pub_tool_basics.h build issue with g++ 4.4.7.<br>
+<br>
+(3.13.0.RC1: 2 June 2017, vex r3386, valgrind r16434)<br>
+(3.13.0.RC2: 9 June 2017, vex r3389, valgrind r16443)<br>
+(3.13.0: 14 June 2017, vex r3396, valgrind r16446)<br>
+<br>
+<br>
+<br>
Release 3.12.0 (20 October 2016)<br>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~<br>
<br>
@@ -142,6 +401,7 @@
303877 valgrind doesn't support compressed debuginfo sections.<br>
345307 Warning about "still reachable" memory when using libstdc++ from gcc 5<br>
348345 Assertion fails for negative lineno<br>
+348924 MIPS: Load doubles through memory so the code compiles with the FPXX ABI<br>
351282 V 3.10.1 MIPS softfloat build broken with GCC 4.9.3 / binutils 2.25.1<br>
351692 Dumps created by valgrind are not readable by gdb (mips32 specific)<br>
351804 Crash on generating suppressions for "printf" call on OS X 10.10<br>
@@ -269,6 +529,8 @@
369468 Remove quadratic metapool algorithm using VG_(HT_remove_at_Iter)<br>
370265 ISA 3.0 HW cap stuff needs updating<br>
371128 BCD add and subtract instructions on Power BE in 32-bit mode do not work<br>
+372195 Power PC, xxsel instruction is not always recognized<br>
+<br>
n-i-bz Fix incorrect (or infinite loop) unwind on RHEL7 x86 and amd64<br>
n-i-bz massif --pages-as-heap=yes does not report peak caused by mmap+munmap<br>
n-i-bz false positive leaks due to aspacemgr merging heap & non heap segments<br>
diff --git a/docs/html/dist.news.old.html b/docs/html/dist.news.old.html
index d5747d5..74501de 100644
--- a/docs/html/dist.news.old.html
+++ b/docs/html/dist.news.old.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>3. OLDER NEWS</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="dist.html" title="Valgrind Distribution Documents">
<link rel="prev" href="dist.news.html" title="2. NEWS">
diff --git a/docs/html/dist.readme-android.html b/docs/html/dist.readme-android.html
index 4fcbfb7..87c1d1d 100644
--- a/docs/html/dist.readme-android.html
+++ b/docs/html/dist.readme-android.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>9. README.android</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="dist.html" title="Valgrind Distribution Documents">
<link rel="prev" href="dist.readme-s390.html" title="8. README.S390">
diff --git a/docs/html/dist.readme-android_emulator.html b/docs/html/dist.readme-android_emulator.html
index 6c788fd..b90366c 100644
--- a/docs/html/dist.readme-android_emulator.html
+++ b/docs/html/dist.readme-android_emulator.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>10. README.android_emulator</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="dist.html" title="Valgrind Distribution Documents">
<link rel="prev" href="dist.readme-android.html" title="9. README.android">
diff --git a/docs/html/dist.readme-developers.html b/docs/html/dist.readme-developers.html
index 29ad4d5..ae18432 100644
--- a/docs/html/dist.readme-developers.html
+++ b/docs/html/dist.readme-developers.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>6. README_DEVELOPERS</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="dist.html" title="Valgrind Distribution Documents">
<link rel="prev" href="dist.readme-missing.html" title="5. README_MISSING_SYSCALL_OR_IOCTL">
@@ -256,6 +256,45 @@
The file tests/outer_inner.supp contains suppressions for <br>
the irrelevant or benign errors found in the inner.<br>
<br>
+An regression test running in the inner (e.g. memcheck/tests/badrw) will<br>
+cause the inner to report an error, which is expected and checked<br>
+as usual when running the regtests in an outer/inner setup.<br>
+However, the outer will often also observe an error, e.g. a jump<br>
+using uninitialised data, or a read/write outside the bounds of a heap<br>
+block. When the outer reports such an error, it will output the<br>
+inner host stacktrace. To this stacktrace, it will append the<br>
+stacktrace of the inner guest program. For example, this is an error<br>
+reported by the outer when the inner runs the badrw regtest:<br>
+ ==8119== Invalid read of size 2<br>
+ ==8119== at 0x7F2EFD7AF: ???<br>
+ ==8119== by 0x7F2C82EAF: ???<br>
+ ==8119== by 0x7F180867F: ???<br>
+ ==8119== by 0x40051D: main (badrw.c:5)<br>
+ ==8119== by 0x7F180867F: ???<br>
+ ==8119== by 0x1BFF: ???<br>
+ ==8119== by 0x3803B7F0: _______VVVVVVVV_appended_inner_guest_stack_VVVVVVVV_______ (m_execontext.c:332)<br>
+ ==8119== by 0x40055C: main (badrw.c:22)<br>
+ ==8119== Address 0x55cd03c is 4 bytes before a block of size 16 alloc'd<br>
+ ==8119== at 0x2804E26D: vgPlain_arena_malloc (m_mallocfree.c:1914)<br>
+ ==8119== by 0x2800BAB4: vgMemCheck_new_block (mc_malloc_wrappers.c:368)<br>
+ ==8119== by 0x2800BC87: vgMemCheck_malloc (mc_malloc_wrappers.c:403)<br>
+ ==8119== by 0x28097EAE: do_client_request (scheduler.c:1861)<br>
+ ==8119== by 0x28097EAE: vgPlain_scheduler (scheduler.c:1425)<br>
+ ==8119== by 0x280A7237: thread_wrapper (syswrap-linux.c:103)<br>
+ ==8119== by 0x280A7237: run_a_thread_NORETURN (syswrap-linux.c:156)<br>
+ ==8119== by 0x3803B7F0: _______VVVVVVVV_appended_inner_guest_stack_VVVVVVVV_______ (m_execontext.c:332)<br>
+ ==8119== by 0x4C294C4: malloc (vg_replace_malloc.c:298)<br>
+ ==8119== by 0x40051D: main (badrw.c:5)<br>
+In the above, the first stacktrace starts with the inner host stacktrace,<br>
+which in this case is some JITted code. Such code sometimes contains IPs<br>
+that points in the inner guest code (0x40051D: main (badrw.c:5)).<br>
+After the separator, we have the inner guest stacktrace.<br>
+The second stacktrace gives the stacktrace where the heap block that was<br>
+overrun was allocated. We see it was allocated by the inner valgrind<br>
+in the client arena (first part of the stacktrace). The second part is<br>
+the guest stacktrace that did the allocation.<br>
+<br>
+<br>
(C) Performance tests in an outer/inner setup:<br>
<br>
To run all the performance tests with an outer cachegrind, do :<br>
diff --git a/docs/html/dist.readme-mips.html b/docs/html/dist.readme-mips.html
index bd7c477..bd47d06 100644
--- a/docs/html/dist.readme-mips.html
+++ b/docs/html/dist.readme-mips.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>11. README.mips</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="dist.html" title="Valgrind Distribution Documents">
<link rel="prev" href="dist.readme-android_emulator.html" title="10. README.android_emulator">
diff --git a/docs/html/dist.readme-missing.html b/docs/html/dist.readme-missing.html
index 7273b51..eae0a04 100644
--- a/docs/html/dist.readme-missing.html
+++ b/docs/html/dist.readme-missing.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>5. README_MISSING_SYSCALL_OR_IOCTL</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="dist.html" title="Valgrind Distribution Documents">
<link rel="prev" href="dist.readme.html" title="4. README">
@@ -163,7 +163,7 @@
LINX_, LINXY, PLAX_, PLAXY.<br>
GEN* for generic syscalls (in syswrap-generic.c), LIN* for linux<br>
specific ones (in syswrap-linux.c) and PLA* for the platform<br>
- dependant ones (in syswrap-$(PLATFORM)-linux.c).<br>
+ dependent ones (in syswrap-$(PLATFORM)-linux.c).<br>
The *XY variant if it requires a PRE() and POST() function, and<br>
the *X_ variant if it only requires a PRE()<br>
function. <br>
diff --git a/docs/html/dist.readme-packagers.html b/docs/html/dist.readme-packagers.html
index 12b6685..a37248d 100644
--- a/docs/html/dist.readme-packagers.html
+++ b/docs/html/dist.readme-packagers.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>7. README_PACKAGERS</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="dist.html" title="Valgrind Distribution Documents">
<link rel="prev" href="dist.readme-developers.html" title="6. README_DEVELOPERS">
diff --git a/docs/html/dist.readme-s390.html b/docs/html/dist.readme-s390.html
index 003d5c8..6970064 100644
--- a/docs/html/dist.readme-s390.html
+++ b/docs/html/dist.readme-s390.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>8. README.S390</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="dist.html" title="Valgrind Distribution Documents">
<link rel="prev" href="dist.readme-packagers.html" title="7. README_PACKAGERS">
diff --git a/docs/html/dist.readme-solaris.html b/docs/html/dist.readme-solaris.html
index fa10fe3..baf392b 100644
--- a/docs/html/dist.readme-solaris.html
+++ b/docs/html/dist.readme-solaris.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>12. README.solaris</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="dist.html" title="Valgrind Distribution Documents">
<link rel="prev" href="dist.readme-mips.html" title="11. README.mips">
@@ -34,12 +34,14 @@
- A working combination of autotools is required: aclocal, autoheader,<br>
automake and autoconf have to be found in the PATH. You should be able to<br>
install pkg:/developer/build/automake and pkg:/developer/build/autoconf<br>
- packages to fullfil this requirement.<br>
+ packages to fulfil this requirement.<br>
- System header files are required. On Solaris, these can be installed with:<br>
# pkg install system/header<br>
- GNU make is also required. On Solaris, this can be quickly achieved with:<br>
$ PATH=/usr/gnu/bin:$PATH; export PATH<br>
- For remote debugging support, working GDB is required (see below).<br>
+- For running regression tests, GNU sed, grep, awk, diff are required.<br>
+ This can be quickly achieved on Solaris by prepending /usr/gnu/bin to PATH.<br>
<br>
<br>
Compilation<br>
@@ -146,7 +148,6 @@
- Provide better error reporting for various subsyscalls.<br>
- Implement storing of extra register state in signal frame.<br>
- Performance comparison against other platforms.<br>
-<br>
- Prevent SIGPIPE when writing to a socket (coregrind/m_libcfile.c).<br>
- Implement ticket locking for fair scheduling (--fair-sched=yes).<br>
- Implement support in DRD and Helgrind tools for thr_join() with thread == 0.<br>
@@ -160,6 +161,8 @@
to see this in effect. Would require awareness of syscall parameter semantics.<br>
- Correctly print arguments of DW_CFA_ORCL_arg_loc in show_CF_instruction() when<br>
it is implemented in libdwarf.<br>
+- Handle a situation when guest program sets SC_CANCEL_FLG in schedctl and<br>
+ Valgrind needs to invoke a syscall on its own.<br>
<br>
<br>
Contacts<br>
diff --git a/docs/html/dist.readme.html b/docs/html/dist.readme.html
index 2904de3..8d93d00 100644
--- a/docs/html/dist.readme.html
+++ b/docs/html/dist.readme.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>4. README</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="dist.html" title="Valgrind Distribution Documents">
<link rel="prev" href="dist.news.old.html" title="3. OLDER NEWS">
diff --git a/docs/html/drd-manual.html b/docs/html/drd-manual.html
index 0de0955..62d214e 100644
--- a/docs/html/drd-manual.html
+++ b/docs/html/drd-manual.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>8. DRD: a thread error detector</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="manual.html" title="Valgrind User Manual">
<link rel="prev" href="hg-manual.html" title="7. Helgrind: a thread error detector">
diff --git a/docs/html/faq.html b/docs/html/faq.html
index b17361e..c993974 100644
--- a/docs/html/faq.html
+++ b/docs/html/faq.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>Valgrind Frequently Asked Questions</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="FAQ.html" title="Valgrind FAQ">
<link rel="prev" href="FAQ.html" title="Valgrind FAQ">
@@ -187,7 +187,7 @@
<tr><td colspan="2"> </td></tr>
<tr class="question">
<td align="left" valign="top">
-<a name="faq.glibc_devel"></a><a name="idm140639118203536"></a><b>2.2.</b>
+<a name="faq.glibc_devel"></a><a name="idm140394923880656"></a><b>2.2.</b>
</td>
<td align="left" valign="top">
<b>When building Valgrind, 'make' fails with this:</b><pre class="screen">
diff --git a/docs/html/hg-manual.html b/docs/html/hg-manual.html
index 4156c05..cec55e4 100644
--- a/docs/html/hg-manual.html
+++ b/docs/html/hg-manual.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>7. Helgrind: a thread error detector</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="manual.html" title="Valgrind User Manual">
<link rel="prev" href="cl-manual.html" title="6. Callgrind: a call-graph generating cache and branch prediction profiler">
@@ -81,6 +81,10 @@
primitives, you can describe their behaviour to Helgrind using the
<code class="varname">ANNOTATE_*</code> macros defined
in <code class="varname">helgrind.h</code>.</p>
+<p>Helgrind also provides <a class="xref" href="manual-core.html#manual-core.xtree" title="2.9. Execution Trees">Execution Trees</a> memory
+ profiling using the command line
+ option <code class="computeroutput">--xtree-memory</code> and the monitor command
+ <code class="computeroutput">xtmemory</code>.</p>
<p>Following those is a section containing
<a class="link" href="hg-manual.html#hg-manual.effective-use" title="7.5. Hints and Tips for Effective Use of Helgrind">
hints and tips on how to get the best out of Helgrind.</a>
diff --git a/docs/html/images/kcachegrind_xtree.png b/docs/html/images/kcachegrind_xtree.png
new file mode 100644
index 0000000..6006bbd
--- /dev/null
+++ b/docs/html/images/kcachegrind_xtree.png
Binary files differ
diff --git a/docs/html/index.html b/docs/html/index.html
index 8e27063..7898a1e 100644
--- a/docs/html/index.html
+++ b/docs/html/index.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>Valgrind Documentation</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="next" href="QuickStart.html" title="The Valgrind Quick Start Guide">
</head>
@@ -14,12 +14,12 @@
<div>
<div align="center"><h1 class="title">
<a name="set-index"></a>Valgrind Documentation</h1></div>
-<div align="center"><p class="releaseinfo">Release 3.12.0 20 October 2016</p></div>
-<div align="center"><p class="copyright">Copyright © 2000-2016
+<div align="center"><p class="releaseinfo">Release 3.13.0 15 June 2017</p></div>
+<div align="center"><p class="copyright">Copyright © 2000-2017
<a class="link" href="dist.authors.html" title="1. AUTHORS">AUTHORS</a>
</p></div>
<div align="center"><div class="legalnotice">
-<a name="idm140639127546768"></a><p>Permission is granted to copy, distribute and/or modify
+<a name="idm140394938157648"></a><p>Permission is granted to copy, distribute and/or modify
this document under the terms of the GNU Free Documentation
License, Version 1.2 or any later version published by the
Free Software Foundation; with no Invariant Sections, with no
diff --git a/docs/html/license.gfdl.html b/docs/html/license.gfdl.html
index b4f9e11..fceebee 100644
--- a/docs/html/license.gfdl.html
+++ b/docs/html/license.gfdl.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>2. The GNU Free Documentation License</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="licenses.html" title="GNU Licenses">
<link rel="prev" href="license.gpl.html" title="1. The GNU General Public License">
diff --git a/docs/html/license.gpl.html b/docs/html/license.gpl.html
index e48a6c4..2673ea7 100644
--- a/docs/html/license.gpl.html
+++ b/docs/html/license.gpl.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>1. The GNU General Public License</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="licenses.html" title="GNU Licenses">
<link rel="prev" href="licenses.html" title="GNU Licenses">
diff --git a/docs/html/licenses.html b/docs/html/licenses.html
index 924a130..4016d64 100644
--- a/docs/html/licenses.html
+++ b/docs/html/licenses.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>GNU Licenses</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="index.html" title="Valgrind Documentation">
<link rel="prev" href="dist.readme-solaris.html" title="12. README.solaris">
diff --git a/docs/html/lk-manual.html b/docs/html/lk-manual.html
index 0713143..51a190a 100644
--- a/docs/html/lk-manual.html
+++ b/docs/html/lk-manual.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>13. Lackey: an example tool</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="manual.html" title="Valgrind User Manual">
<link rel="prev" href="bbv-manual.html" title="12. BBV: an experimental basic block vector generation tool">
diff --git a/docs/html/manual-core-adv.html b/docs/html/manual-core-adv.html
index 0e6738c..de6355a 100644
--- a/docs/html/manual-core-adv.html
+++ b/docs/html/manual-core-adv.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>3. Using and understanding the Valgrind core: Advanced Topics</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="manual.html" title="Valgrind User Manual">
<link rel="prev" href="manual-core.html" title="2. Using and understanding the Valgrind core">
@@ -213,7 +213,7 @@
memcheck leak search can be requested from the client program
using VALGRIND_DO_LEAK_CHECK or via the monitor command "leak_search".
Note that the syntax of the command string is only verified at
- run-time. So, if it exists, it is preferrable to use a specific
+ run-time. So, if it exists, it is preferable to use a specific
client request to have better compile time verifications of the
arguments.
</p></dd>
@@ -354,8 +354,8 @@
and indicates it is waiting for a connection from a GDB:</p>
<pre class="programlisting">
==2418== Memcheck, a memory error detector
-==2418== Copyright (C) 2002-2010, and GNU GPL'd, by Julian Seward et al.
-==2418== Using Valgrind-3.7.0.SVN and LibVEX; rerun with -h for copyright info
+==2418== Copyright (C) 2002-2017, and GNU GPL'd, by Julian Seward et al.
+==2418== Using Valgrind-3.13.0.SVN and LibVEX; rerun with -h for copyright info
==2418== Command: ./prog
==2418==
==2418== (action at startup) vgdb me ...
@@ -940,6 +940,12 @@
connect to or interrupt a process blocked in a system call on Mac
OS X or Android.
</p>
+<p>Unblocking processes blocked in system calls is implemented
+ via agent thread on Solaris. This is quite a different approach
+ than using ptrace on Linux, but leads to equivalent result - Valgrind
+ gdbserver is invoked. Note that agent thread is a Solaris OS
+ feature and cannot be disabled.
+ </p>
</li>
<li class="listitem">
<p>Changing register values.</p>
@@ -1204,6 +1210,10 @@
<code class="option">--vgdb-error=0</code> on the
command line, then set a few breakpoints, set the vgdb-error value
to a huge value and continue execution.</p></li>
+<li class="listitem"><p><code class="varname">xtmemory [<filename> default xtmemory.kcg.%p.%n]</code>
+ requests the tool to produce an xtree heap memory report.
+ See <a class="xref" href="manual-core.html#manual-core.xtree" title="2.9. Execution Trees">Execution Trees</a> for
+ a detailed explanation about execution trees. </p></li>
</ul></div>
<p>The following Valgrind monitor commands are useful for
investigating the behaviour of Valgrind or its gdbserver in case of
@@ -1236,7 +1246,7 @@
by valgrind address space manager will be output. Note that
this list of segments is always output on the Valgrind log.
</p></li>
-<li class="listitem"><p><code class="varname">v.info exectxt</code> shows informations about
+<li class="listitem"><p><code class="varname">v.info exectxt</code> shows information about
the "executable contexts" (i.e. the stack traces) recorded by
Valgrind. For some programs, Valgrind can record a very high
number of such stack traces, causing a high memory usage. This
@@ -1291,9 +1301,9 @@
variable of the memcheck tool on an x86, do the following setup:</p>
<pre class="screen">
(gdb) monitor v.set hostvisibility yes
-(gdb) add-symbol-file /path/to/tool/executable/file/memcheck-x86-linux 0x38000000
+(gdb) add-symbol-file /path/to/tool/executable/file/memcheck-x86-linux 0x58000000
add symbol table from file "/path/to/tool/executable/file/memcheck-x86-linux" at
- .text_addr = 0x38000000
+ .text_addr = 0x58000000
(y or n) y
Reading symbols from /path/to/tool/executable/file/memcheck-x86-linux...done.
(gdb)
diff --git a/docs/html/manual-core.html b/docs/html/manual-core.html
index 480d038..0a98fce 100644
--- a/docs/html/manual-core.html
+++ b/docs/html/manual-core.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>2. Using and understanding the Valgrind core</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="manual.html" title="Valgrind User Manual">
<link rel="prev" href="manual-intro.html" title="1. Introduction">
@@ -41,11 +41,12 @@
<dt><span class="sect1"><a href="manual-core.html#manual-core.pthreads">2.7. Support for Threads</a></span></dt>
<dd><dl><dt><span class="sect2"><a href="manual-core.html#manual-core.pthreads_perf_sched">2.7.1. Scheduling and Multi-Thread Performance</a></span></dt></dl></dd>
<dt><span class="sect1"><a href="manual-core.html#manual-core.signals">2.8. Handling of Signals</a></span></dt>
-<dt><span class="sect1"><a href="manual-core.html#manual-core.install">2.9. Building and Installing Valgrind</a></span></dt>
-<dt><span class="sect1"><a href="manual-core.html#manual-core.problems">2.10. If You Have Problems</a></span></dt>
-<dt><span class="sect1"><a href="manual-core.html#manual-core.limits">2.11. Limitations</a></span></dt>
-<dt><span class="sect1"><a href="manual-core.html#manual-core.example">2.12. An Example Run</a></span></dt>
-<dt><span class="sect1"><a href="manual-core.html#manual-core.warnings">2.13. Warning Messages You Might See</a></span></dt>
+<dt><span class="sect1"><a href="manual-core.html#manual-core.xtree">2.9. Execution Trees</a></span></dt>
+<dt><span class="sect1"><a href="manual-core.html#manual-core.install">2.10. Building and Installing Valgrind</a></span></dt>
+<dt><span class="sect1"><a href="manual-core.html#manual-core.problems">2.11. If You Have Problems</a></span></dt>
+<dt><span class="sect1"><a href="manual-core.html#manual-core.limits">2.12. Limitations</a></span></dt>
+<dt><span class="sect1"><a href="manual-core.html#manual-core.example">2.13. An Example Run</a></span></dt>
+<dt><span class="sect1"><a href="manual-core.html#manual-core.warnings">2.14. Warning Messages You Might See</a></span></dt>
</dl>
</div>
<p>This chapter describes the Valgrind core services, command-line
@@ -760,7 +761,15 @@
calling exec afterwards, and you don't use this specifier
(or the <code class="option">%q</code> specifier below), the Valgrind output from
all those processes will go into one file, possibly jumbled up, and
- possibly incomplete.</p>
+ possibly incomplete. Note: If the program forks and calls exec afterwards,
+ Valgrind output of the child from the period between fork and exec
+ will be lost. Fortunately this gap is really tiny for most programs;
+ and modern programs use <code class="computeroutput">posix_spawn</code>
+ anyway.</p>
+<p><code class="option">%n</code> is replaced with a file sequence number
+ unique for this process.
+ This is useful for processes that produces several files
+ from the same filename template.</p>
<p><code class="option">%q{FOO}</code> is replaced with the contents of the
environment variable <code class="varname">FOO</code>. If the
<code class="option">{FOO}</code> part is malformed, it causes an abort. This
@@ -776,7 +785,7 @@
<p>If an <code class="option">%</code> is followed by any other character, it
causes an abort.</p>
<p>If the file name specifies a relative file name, it is put
- in the program's initial working directory : this is the current
+ in the program's initial working directory: this is the current
directory when the program started its execution after the fork
or after the exec. If it specifies an absolute file name (ie.
starts with '/') then it is put there.
@@ -864,7 +873,7 @@
<code class="option">--xml=yes</code>. Any <code class="option">%p</code> or
<code class="option">%q</code> sequences appearing in the filename are expanded
in exactly the same way as they are for <code class="option">--log-file</code>.
- See the description of <code class="option">--log-file</code> for details.
+ See the description of <a class="xref" href="manual-core.html#opt.log-file">--log-file</a> for details.
</p></dd>
<dt>
<a name="opt.xml-socket"></a><span class="term">
@@ -1443,6 +1452,68 @@
memory needed by Valgrind but also reduces the chances of
detecting over/underruns, so is not recommended.</p>
</dd>
+<dt>
+<a name="opt.xtree-memory"></a><span class="term">
+ <code class="option">--xtree-memory=none|allocs|full [none] </code>
+ </span>
+</dt>
+<dd>
+<p> Tools replacing Valgrind's <code class="function">malloc,
+ realloc,</code> etc, can optionally produce an execution
+ tree detailing which piece of code is responsible for heap
+ memory usage. See <a class="xref" href="manual-core.html#manual-core.xtree" title="2.9. Execution Trees">Execution Trees</a>
+ for a detailed explanation about execution trees. </p>
+<p> When set to <code class="varname">none</code>, no memory execution
+ tree is produced.</p>
+<p> When set to <code class="varname">allocs</code>, the memory
+ execution tree gives the current number of allocated bytes and
+ the current number of allocated blocks. </p>
+<p> When set to <code class="varname">full</code>, the memory execution
+ tree gives 6 different measurements : the current number of
+ allocated bytes and blocks (same values as
+ for <code class="varname">allocs</code>), the total number of allocated
+ bytes and blocks, the total number of freed bytes and
+ blocks.</p>
+<p>Note that the overhead in cpu and memory to produce
+ an xtree depends on the tool. The overhead in cpu is small for
+ the value <code class="varname">allocs</code>, as the information needed
+ to produce this report is maintained in any case by the tool.
+ For massif and helgrind, specifying <code class="varname">full</code>
+ implies to capture a stack trace for each free operation,
+ while normally these tools only capture an allocation stack
+ trace. For memcheck, the cpu overhead for the
+ value <code class="varname">full</code> is small, as this can only be
+ used in combination with
+ <code class="option">--keep-stacktraces=alloc-and-free</code> or
+ <code class="option">--keep-stacktraces=alloc-then-free</code>, which
+ already records a stack trace for each free operation. The
+ memory overhead varies between 5 and 10 words per unique
+ stacktrace in the xtree, plus the memory needed to record the
+ stack trace for the free operations, if needed specifically
+ for the xtree.
+ </p>
+</dd>
+<dt>
+<a name="opt.xtree-memory-file"></a><span class="term">
+ <code class="option">--xtree-memory-file=<filename> [default:
+ xtmemory.kcg.%p] </code>
+ </span>
+</dt>
+<dd>
+<p>Specifies that Valgrind should produce the xtree memory
+ report in the specified file. Any <code class="option">%p</code> or
+ <code class="option">%q</code> sequences appearing in the filename are expanded
+ in exactly the same way as they are for <code class="option">--log-file</code>.
+ See the description of <a class="xref" href="manual-core.html#opt.log-file">--log-file</a>
+ for details. </p>
+<p>If the filename contains the extension <code class="option">.ms</code>,
+ then the produced file format will be a massif output file format.
+ If the filename contains the extension <code class="option">.kcg</code>
+ or no extension is provided or recognised,
+ then the produced file format will be a callgrind output format.</p>
+<p>See <a class="xref" href="manual-core.html#manual-core.xtree" title="2.9. Execution Trees">Execution Trees</a>
+ for a detailed explanation about execution trees formats. </p>
+</dd>
</dl>
</div>
</div>
@@ -1749,7 +1820,7 @@
knowledge of the glibc stack cache implementation and by
examining the debug information of the pthread
library. This technique is thus somewhat fragile and might
- not work for all glibc versions. This has been succesfully
+ not work for all glibc versions. This has been successfully
tested with various glibc versions (e.g. 2.11, 2.16, 2.18)
on various platforms.</p>
</li>
@@ -1759,6 +1830,37 @@
when writing. Without this, programs using libdoor(3LIB)
functionality with completely proprietary semantics may report
large number of false positives.</p></li>
+<li class="listitem"><p><code class="option">fallback-llsc: </code>(MIPS and ARM64 only): Enables
+ an alternative implementation of Load-Linked (LL) and
+ Store-Conditional (SC) instructions. The standard implementation
+ gives more correct behaviour, but can cause indefinite looping on
+ certain processor implementations that are intolerant of extra
+ memory references between LL and SC. So far this is known only to
+ happen on Cavium 3 cores.
+
+ You should not need to use this flag, since the relevant cores are
+ detected at startup and the alternative implementation is
+ automatically enabled if necessary. There is no equivalent
+ anti-flag: you cannot force-disable the alternative
+ implementation, if it is automatically enabled.
+
+ The underlying problem exists because the "standard"
+ implementation of LL and SC is done by copying through LL and SC
+ instructions into the instrumented code. However, tools may
+ insert extra instrumentation memory references in between the LL
+ and SC instructions. These memory references are not present in
+ the original uninstrumented code, and their presence in the
+ instrumented code can cause the SC instructions to persistently
+ fail, leading to indefinite looping in LL-SC blocks.
+
+ The alternative implementation gives correct behaviour of LL and
+ SC instructions between threads in a process, up to and including
+ the ABA scenario. It also gives correct behaviour between a
+ Valgrinded thread and a non-Valgrinded thread running in a
+ different process, that communicate via shared memory, but only up
+ to and including correct CAS behaviour -- in this case the ABA
+ scenario may not be correctly handled.
+ </p></li>
</ul></div>
</dd>
<dt>
@@ -2125,8 +2227,8 @@
<code class="computeroutput">~/.valgrindrc</code>.
</p>
<p>Please note that the <code class="computeroutput">./.valgrindrc</code>
-file is ignored if it is marked as world writeable or not owned
-by the current user. This is because the
+file is ignored if it is not a regular file, or is marked as world writeable,
+or is not owned by the current user. This is because the
<code class="computeroutput">./.valgrindrc</code> can contain options that are
potentially harmful or can be used by a local attacker to execute code under
your user account.
@@ -2278,7 +2380,206 @@
</div>
<div class="sect1">
<div class="titlepage"><div><div><h2 class="title" style="clear: both">
-<a name="manual-core.install"></a>2.9. Building and Installing Valgrind</h2></div></div></div>
+<a name="manual-core.xtree"></a>2.9. Execution Trees</h2></div></div></div>
+<p>An execution tree (xtree) is made of a set of stack traces, each
+ stack trace is associated with some resource consumptions or event
+ counts. Depending on the xtree, different event counts/resource
+ consumptions can be recorded in the xtree. Multiple tools can
+ produce memory use xtree. Memcheck can output the leak search results
+ in an xtree.</p>
+<p> A typical usage for an xtree is to show a graphical or textual
+ representation of the heap usage of a program. The below figure is
+ a heap usage xtree graphical representation produced by
+ kcachegrind. In the kcachegrind output, you can see that main
+ current heap usage (allocated indirectly) is 528 bytes : 388 bytes
+ allocated indirectly via a call to function f1 and 140 bytes
+ indirectly allocated via a call to function f2. f2 has allocated
+ memory by calling g2, while f1 has allocated memory by calling g11
+ and g12. g11, g12 and g1 have directly called a memory allocation
+ function (malloc), and so have a non zero 'Self' value. Note that when
+ kcachegrind shows an xtree, the 'Called' column and call nr indications in
+ the Call Graph are not significant (always set to 0 or 1, independently
+ of the real nr of calls. The kcachegrind versions >= 0.8.0 do not show
+ anymore such irrelevant xtree call number information.</p>
+<div><img src="images/kcachegrind_xtree.png"></div>
+<p>An xtree heap memory report is produced at the end of the
+ execution when required using the
+ option <code class="option">--xtree-memory</code>. It can also be produced on
+ demand using the <code class="option">xtmemory</code> monitor command (see
+ <a class="xref" href="manual-core-adv.html#manual-core-adv.valgrind-monitor-commands" title="3.2.10. Valgrind monitor commands">Valgrind monitor commands</a>). Currently,
+ an xtree heap memory report can be produced by
+ the <code class="option">memcheck</code>, <code class="option">helgrind</code>
+ and <code class="option">massif</code> tools.</p>
+<p>The xtrees produced by the option
+ <a class="xref" href="manual-core.html#opt.xtree-memory">--xtree-memory</a> or the <code class="option">xtmemory</code>
+ monitor command are showing the following events/resource
+ consumption describing heap usage:</p>
+<div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; ">
+<li class="listitem"><p><code class="option">curB</code> current number of Bytes allocated. The
+ number of allocated bytes is added to the <code class="option">curB</code>
+ value of a stack trace for each allocation. It is decreased when
+ a block allocated by this stack trace is released (by another
+ "freeing" stack trace)</p></li>
+<li class="listitem"><p><code class="option">curBk</code> current number of Blocks allocated,
+ maintained similary to curB : +1 for each allocation, -1 when
+ the block is freed.</p></li>
+<li class="listitem"><p><code class="option">totB</code> total allocated Bytes. This is
+ increased for each allocation with the number of allocated bytes.</p></li>
+<li class="listitem"><p><code class="option">totBk</code> total allocated Blocks, maintained similary
+ to totB : +1 for each allocation.</p></li>
+<li class="listitem"><p><code class="option">totFdB</code> total Freed Bytes, increased each time
+ a block is released by this ("freeing") stack trace : + nr freed bytes
+ for each free operation.</p></li>
+<li class="listitem"><p><code class="option">totFdBk</code> total Freed Blocks, maintained similarly
+ to totFdB : +1 for each free operation.</p></li>
+</ul></div>
+<p>Note that the last 4 counts are produced only when the
+ <code class="option">--xtree-memory=full</code> was given at startup.</p>
+<p>Xtrees can be saved in 2 file formats, the "Callgrind Format" and
+the "Massif Format".</p>
+<div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; ">
+<li class="listitem">
+<p>Callgrind Format</p>
+<p>An xtree file in the Callgrind Format contains a single callgraph,
+ associating each stack trace with the values recorded
+ in the xtree. </p>
+<p>Different Callgrind Format file visualisers are available:</p>
+<p>Valgrind distribution includes the <code class="option">callgrind_annotate</code>
+ command line utility that reads in the xtree data, and prints a sorted
+ lists of functions, optionally with source annotation. Note that due to
+ xtree specificities, you must give the option
+ <code class="option">--inclusive=yes</code> to callgrind_annotate.</p>
+<p>For graphical visualization of the data, you can use
+ <a class="ulink" href="http://kcachegrind.sourceforge.net/cgi-bin/show.cgi/KcacheGrindIndex" target="_top">KCachegrind</a>, which is a KDE/Qt based
+ GUI that makes it easy to navigate the large amount of data that
+ an xtree can contain.</p>
+</li>
+<li class="listitem">
+<p>Massif Format</p>
+<p>An xtree file in the Massif Format contains one detailed tree
+ callgraph data for each type of event recorded in the xtree. So,
+ for <code class="option">--xtree-memory=alloc</code>, the output file will
+ contain 2 detailed trees (for the counts <code class="option">curB</code>
+ and <code class="option">curBk</code>),
+ while <code class="option">--xtree-memory=full</code> will give a file
+ with 6 detailed trees.</p>
+<p>Different Massif Format file visualisers are available. Valgrind
+ distribution includes the <code class="option">ms_print</code>
+ command line utility that produces an easy to read reprentation of
+ a massif output file. See <a class="xref" href="ms-manual.html#ms-manual.running-massif" title="9.2.2. Running Massif">Running Massif</a> and
+ <a class="xref" href="ms-manual.html#ms-manual.using" title="9.2. Using Massif and ms_print">Using Massif and ms_print</a> for more details
+ about visualising Massif Format output files.</p>
+</li>
+</ul></div>
+<p>Note that for equivalent information, the Callgrind Format is more compact
+ than the Massif Format. However, the Callgrind Format always contains the
+ full data: there is no filtering done during file production, filtering is
+ done by visualisers such as kcachegrind. kcachegrind is particularly easy to
+ use to analyse big xtree data containing multiple events counts or resources
+ consumption. The Massif Format (optionally) only contains a part of the data.
+ For example, the Massif tool might filter some of the data, according to the
+ <code class="option">--threshold</code> option.
+</p>
+<p>To clarify the xtree concept, the below gives several extracts of
+ the output produced by the following commands:
+</p>
+<pre class="screen">
+valgrind --xtree-memory=full --xtree-memory-file=xtmemory.kcg mfg
+callgrind_annotate --auto=yes --inclusive=yes --sort=curB:100,curBk:100,totB:100,totBk:100,totFdB:100,totFdBk:100 xtmemory.kcg
+</pre>
+<p>
+</p>
+<p>The below extract shows that the program mfg has allocated in
+ total 770 bytes in 60 different blocks. Of these 60 blocks, 19 were
+ freed, releasing a total of 242 bytes. The heap currently contains
+ 528 bytes in 41 blocks.</p>
+<pre class="screen">
+--------------------------------------------------------------------------------
+curB curBk totB totBk totFdB totFdBk
+--------------------------------------------------------------------------------
+ 528 41 770 60 242 19 PROGRAM TOTALS
+</pre>
+<p>The below gives more details about which functions have
+ allocated or released memory. As an example, we see that main has
+ (directly or indirectly) allocated 770 bytes of memory and freed
+ (directly or indirectly) 242 bytes of memory. The function f1 has
+ (directly or indirectly) allocated 570 bytes of memory, and has not
+ (directly or indirectly) freed memory. Of the 570 bytes allocated
+ by function f1, 388 bytes (34 blocks) have not been
+ released.</p>
+<pre class="screen">
+--------------------------------------------------------------------------------
+curB curBk totB totBk totFdB totFdBk file:function
+--------------------------------------------------------------------------------
+ 528 41 770 60 242 19 mfg.c:main
+ 388 34 570 50 0 0 mfg.c:f1
+ 220 20 330 30 0 0 mfg.c:g11
+ 168 14 240 20 0 0 mfg.c:g12
+ 140 7 200 10 0 0 mfg.c:g2
+ 140 7 200 10 0 0 mfg.c:f2
+ 0 0 0 0 131 10 mfg.c:freeY
+ 0 0 0 0 111 9 mfg.c:freeX
+</pre>
+<p>The below gives a more detailed information about the callgraph
+ and which source lines/calls have (directly or indirectly) allocated or
+ released memory. The below shows that the 770 bytes allocated by
+ main have been indirectly allocated by calls to f1 and f2.
+ Similarly, we see that the 570 bytes allocated by f1 have been
+ indirectly allocated by calls to g11 and g12. Of the 330 bytes allocated
+ by the 30 calls to g11, 168 bytes have not been freed.
+ The function freeY (called once by main) has released in total
+ 10 blocks and 131 bytes. </p>
+<pre class="screen">
+--------------------------------------------------------------------------------
+-- Auto-annotated source: /home/philippe/valgrind/littleprogs/ + mfg.c
+--------------------------------------------------------------------------------
+curB curBk totB totBk totFdB totFdBk
+....
+ . . . . . . static void freeY(void)
+ . . . . . . {
+ . . . . . . int i;
+ . . . . . . for (i = 0; i < next_ptr; i++)
+ . . . . . . if(i % 5 == 0 && ptrs[i] != NULL)
+ 0 0 0 0 131 10 free(ptrs[i]);
+ . . . . . . }
+ . . . . . . static void f1(void)
+ . . . . . . {
+ . . . . . . int i;
+ . . . . . . for (i = 0; i < 30; i++)
+ 220 20 330 30 0 0 g11();
+ . . . . . . for (i = 0; i < 20; i++)
+ 168 14 240 20 0 0 g12();
+ . . . . . . }
+ . . . . . . int main()
+ . . . . . . {
+ 388 34 570 50 0 0 f1();
+ 140 7 200 10 0 0 f2();
+ 0 0 0 0 111 9 freeX();
+ 0 0 0 0 131 10 freeY();
+ . . . . . . return 0;
+ . . . . . . }
+</pre>
+<p>Heap memory xtrees are helping to understand how your (big)
+ program is using the heap. A full heap memory xtree helps to pin
+ point some code that allocates a lot of small objects : allocating
+ such small objects might be replaced by more efficient technique,
+ such as allocating a big block using malloc, and then diviving this
+ block into smaller blocks in order to decrease the cpu and/or memory
+ overhead of allocating a lot of small blocks. Such full xtree information
+ complements e.g. what callgrind can show: callgrind can show the number
+ of calls to a function (such as malloc) but does not indicate the volume
+ of memory allocated (or freed).</p>
+<p>A full heap memory xtree also can identify the code that allocates
+ and frees a lot of blocks : the total foot print of the program might
+ not reflect the fact that the same memory was over and over allocated
+ then released.</p>
+<p>Finally, Xtree visualisers such as kcachegrind are helping to
+ identify big memory consumers, in order to possibly optimise the
+ amount of memory needed by your program.</p>
+</div>
+<div class="sect1">
+<div class="titlepage"><div><div><h2 class="title" style="clear: both">
+<a name="manual-core.install"></a>2.10. Building and Installing Valgrind</h2></div></div></div>
<p>We use the standard Unix
<code class="computeroutput">./configure</code>,
<code class="computeroutput">make</code>, <code class="computeroutput">make
@@ -2332,9 +2633,9 @@
</div>
<div class="sect1">
<div class="titlepage"><div><div><h2 class="title" style="clear: both">
-<a name="manual-core.problems"></a>2.10. If You Have Problems</h2></div></div></div>
+<a name="manual-core.problems"></a>2.11. If You Have Problems</h2></div></div></div>
<p>Contact us at <a class="ulink" href="http://www.valgrind.org/" target="_top">http://www.valgrind.org/</a>.</p>
-<p>See <a class="xref" href="manual-core.html#manual-core.limits" title="2.11. Limitations">Limitations</a> for the known
+<p>See <a class="xref" href="manual-core.html#manual-core.limits" title="2.12. Limitations">Limitations</a> for the known
limitations of Valgrind, and for a list of programs which are
known not to work on it.</p>
<p>All parts of the system make heavy use of assertions and
@@ -2350,7 +2651,7 @@
</div>
<div class="sect1">
<div class="titlepage"><div><div><h2 class="title" style="clear: both">
-<a name="manual-core.limits"></a>2.11. Limitations</h2></div></div></div>
+<a name="manual-core.limits"></a>2.12. Limitations</h2></div></div></div>
<p>The following list of limitations seems long. However, most
programs actually work fine.</p>
<p>Valgrind will run programs on the supported platforms
@@ -2539,7 +2840,7 @@
</div>
<div class="sect1">
<div class="titlepage"><div><div><h2 class="title" style="clear: both">
-<a name="manual-core.example"></a>2.12. An Example Run</h2></div></div></div>
+<a name="manual-core.example"></a>2.13. An Example Run</h2></div></div></div>
<p>This is the log for a run of a small program using Memcheck.
The program is in fact correct, and the reported error is as the
result of a potentially serious code generation bug in GNU g++
@@ -2573,7 +2874,7 @@
</div>
<div class="sect1">
<div class="titlepage"><div><div><h2 class="title" style="clear: both">
-<a name="manual-core.warnings"></a>2.13. Warning Messages You Might See</h2></div></div></div>
+<a name="manual-core.warnings"></a>2.14. Warning Messages You Might See</h2></div></div></div>
<p>Some of these only appear if you run in verbose mode
(enabled by <code class="option">-v</code>):</p>
<div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; ">
diff --git a/docs/html/manual-intro.html b/docs/html/manual-intro.html
index 965c051..e98c777 100644
--- a/docs/html/manual-intro.html
+++ b/docs/html/manual-intro.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>1. Introduction</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="manual.html" title="Valgrind User Manual">
<link rel="prev" href="manual.html" title="Valgrind User Manual">
diff --git a/docs/html/manual-writing-tools.html b/docs/html/manual-writing-tools.html
index 59fc84d..04c3b36 100644
--- a/docs/html/manual-writing-tools.html
+++ b/docs/html/manual-writing-tools.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>2. Writing a New Valgrind Tool</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="tech-docs.html" title="Valgrind Technical Documentation">
<link rel="prev" href="design-impl.html" title="1. The Design and Implementation of Valgrind">
@@ -159,8 +159,8 @@
The output should be something like this:</p>
<pre class="programlisting">
==738== foobar-0.0.1, a foobarring tool.
- ==738== Copyright (C) 2002-2009, and GNU GPL'd, by J. Programmer.
- ==738== Using Valgrind-3.5.0.SVN and LibVEX; rerun with -h for copyright info
+ ==738== Copyright (C) 2002-2017, and GNU GPL'd, by J. Programmer.
+ ==738== Using Valgrind-3.13.0.SVN and LibVEX; rerun with -h for copyright info
==738== Command: date
==738==
Tue Nov 27 12:40:49 EST 2007
diff --git a/docs/html/manual.html b/docs/html/manual.html
index ed44036..e4d465e 100644
--- a/docs/html/manual.html
+++ b/docs/html/manual.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>Valgrind User Manual</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="index.html" title="Valgrind Documentation">
<link rel="prev" href="quick-start.html" title="The Valgrind Quick Start Guide">
@@ -22,10 +22,10 @@
<div>
<div><h1 class="title">
<a name="manual"></a>Valgrind User Manual</h1></div>
-<div><p class="releaseinfo">Release 3.12.0 20 October 2016</p></div>
-<div><p class="copyright">Copyright © 2000-2016 <a class="ulink" href="http://www.valgrind.org/info/developers.html" target="_top">Valgrind Developers</a></p></div>
+<div><p class="releaseinfo">Release 3.13.0 15 June 2017</p></div>
+<div><p class="copyright">Copyright © 2000-2017 <a class="ulink" href="http://www.valgrind.org/info/developers.html" target="_top">Valgrind Developers</a></p></div>
<div><div class="legalnotice">
-<a name="idm140639115873632"></a><p>Email: <a class="ulink" href="mailto:valgrind@valgrind.org" target="_top">valgrind@valgrind.org</a></p>
+<a name="idm140394925654576"></a><p>Email: <a class="ulink" href="mailto:valgrind@valgrind.org" target="_top">valgrind@valgrind.org</a></p>
</div></div>
</div>
<hr>
@@ -58,11 +58,12 @@
<dt><span class="sect1"><a href="manual-core.html#manual-core.pthreads">2.7. Support for Threads</a></span></dt>
<dd><dl><dt><span class="sect2"><a href="manual-core.html#manual-core.pthreads_perf_sched">2.7.1. Scheduling and Multi-Thread Performance</a></span></dt></dl></dd>
<dt><span class="sect1"><a href="manual-core.html#manual-core.signals">2.8. Handling of Signals</a></span></dt>
-<dt><span class="sect1"><a href="manual-core.html#manual-core.install">2.9. Building and Installing Valgrind</a></span></dt>
-<dt><span class="sect1"><a href="manual-core.html#manual-core.problems">2.10. If You Have Problems</a></span></dt>
-<dt><span class="sect1"><a href="manual-core.html#manual-core.limits">2.11. Limitations</a></span></dt>
-<dt><span class="sect1"><a href="manual-core.html#manual-core.example">2.12. An Example Run</a></span></dt>
-<dt><span class="sect1"><a href="manual-core.html#manual-core.warnings">2.13. Warning Messages You Might See</a></span></dt>
+<dt><span class="sect1"><a href="manual-core.html#manual-core.xtree">2.9. Execution Trees</a></span></dt>
+<dt><span class="sect1"><a href="manual-core.html#manual-core.install">2.10. Building and Installing Valgrind</a></span></dt>
+<dt><span class="sect1"><a href="manual-core.html#manual-core.problems">2.11. If You Have Problems</a></span></dt>
+<dt><span class="sect1"><a href="manual-core.html#manual-core.limits">2.12. Limitations</a></span></dt>
+<dt><span class="sect1"><a href="manual-core.html#manual-core.example">2.13. An Example Run</a></span></dt>
+<dt><span class="sect1"><a href="manual-core.html#manual-core.warnings">2.14. Warning Messages You Might See</a></span></dt>
</dl></dd>
<dt><span class="chapter"><a href="manual-core-adv.html">3. Using and understanding the Valgrind core: Advanced Topics</a></span></dt>
<dd><dl>
@@ -270,9 +271,9 @@
<dt><span class="sect1"><a href="dh-manual.html#dh-manual.overview">10.1. Overview</a></span></dt>
<dt><span class="sect1"><a href="dh-manual.html#dh-manual.understanding">10.2. Understanding DHAT's output</a></span></dt>
<dd><dl>
-<dt><span class="sect2"><a href="dh-manual.html#idm140639117126160">10.2.1. Interpreting the max-live, tot-alloc and deaths fields</a></span></dt>
-<dt><span class="sect2"><a href="dh-manual.html#idm140639113841488">10.2.2. Interpreting the acc-ratios fields</a></span></dt>
-<dt><span class="sect2"><a href="dh-manual.html#idm140639116741152">10.2.3. Interpreting "Aggregated access counts by offset" data</a></span></dt>
+<dt><span class="sect2"><a href="dh-manual.html#idm140394924138288">10.2.1. Interpreting the max-live, tot-alloc and deaths fields</a></span></dt>
+<dt><span class="sect2"><a href="dh-manual.html#idm140394926128304">10.2.2. Interpreting the acc-ratios fields</a></span></dt>
+<dt><span class="sect2"><a href="dh-manual.html#idm140394925890256">10.2.3. Interpreting "Aggregated access counts by offset" data</a></span></dt>
</dl></dd>
<dt><span class="sect1"><a href="dh-manual.html#dh-manual.options">10.3. DHAT Command-line Options</a></span></dt>
</dl></dd>
diff --git a/docs/html/mc-manual.html b/docs/html/mc-manual.html
index b47da7d..2ae7d16 100644
--- a/docs/html/mc-manual.html
+++ b/docs/html/mc-manual.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>4. Memcheck: a memory error detector</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="manual.html" title="Valgrind User Manual">
<link rel="prev" href="manual-core-adv.html" title="3. Using and understanding the Valgrind core: Advanced Topics">
@@ -90,7 +90,11 @@
</ul></div>
<p>Problems like these can be difficult to find by other means,
often remaining undetected for long periods, then causing occasional,
-difficult-to-diagnose crashes.</p>
+ difficult-to-diagnose crashes.</p>
+<p>Memcheck also provides <a class="xref" href="manual-core.html#manual-core.xtree" title="2.9. Execution Trees">Execution Trees</a> memory
+ profiling using the command line
+ option <code class="computeroutput">--xtree-memory</code> and the monitor command
+ <code class="computeroutput">xtmemory</code>.</p>
</div>
<div class="sect1">
<div class="titlepage"><div><div><h2 class="title" style="clear: both">
@@ -726,6 +730,54 @@
</ul></div>
</dd>
<dt>
+<a name="opt.xtree-leak"></a><span class="term">
+ <code class="option">--xtree-leak=<no|yes> [no] </code>
+ </span>
+</dt>
+<dd>
+<p>If set to yes, the results for the leak search done at exit will be
+ output in a 'Callgrind Format' execution tree file. Note that this
+ automatically sets the option <code class="option">--leak-check=full</code>.
+ The produced file
+ will contain the following events:</p>
+<div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; ">
+<li class="listitem"><p><code class="option">RB</code> : Reachable Bytes</p></li>
+<li class="listitem"><p><code class="option">PB</code> : Possibly lost Bytes</p></li>
+<li class="listitem"><p><code class="option">IB</code> : Indirectly lost Bytes</p></li>
+<li class="listitem"><p><code class="option">DB</code> : Definitely lost Bytes (direct plus indirect)</p></li>
+<li class="listitem"><p><code class="option">DIB</code> : Definitely Indirectly lost Bytes (subset of DB)</p></li>
+<li class="listitem"><p><code class="option">RBk</code> : reachable Blocks</p></li>
+<li class="listitem"><p><code class="option">PBk</code> : Possibly lost Blocks</p></li>
+<li class="listitem"><p><code class="option">IBk</code> : Indirectly lost Blocks</p></li>
+<li class="listitem"><p><code class="option">DBk</code> : Definitely lost Blocks</p></li>
+</ul></div>
+<p>The increase or decrease for all events above will also be output in
+ the file to provide the delta (increase or decreaseà between 2
+ successive leak searches. For example, <code class="option">iRB</code> is the
+ increase of the <code class="option">RB</code> event, <code class="option">dPBk</code> is the
+ decrease of <code class="option">PBk</code> event. The values for the increase and
+ decrease events will be zero for the first leak search done.</p>
+<p>See <a class="xref" href="manual-core.html#manual-core.xtree" title="2.9. Execution Trees">Execution Trees</a> for a detailed explanation
+ about execution trees.</p>
+</dd>
+<dt>
+<a name="opt.xtree-leak-file"></a><span class="term">
+ <code class="option">--xtree-leak-file=<filename> [default:
+ xtleak.kcg.%p] </code>
+ </span>
+</dt>
+<dd>
+<p>Specifies that Valgrind should produce the xtree leak
+ report in the specified file. Any <code class="option">%p</code>,
+ <code class="option">%q</code> or <code class="option">%n</code> sequences appearing in
+ the filename are expanded
+ in exactly the same way as they are for <code class="option">--log-file</code>.
+ See the description of <a class="xref" href="manual-core.html#opt.log-file">--log-file</a>
+ for details. </p>
+<p>See <a class="xref" href="manual-core.html#manual-core.xtree" title="2.9. Execution Trees">Execution Trees</a>
+ for a detailed explanation about execution trees formats. </p>
+</dd>
+<dt>
<a name="opt.undef-value-errors"></a><span class="term">
<code class="option">--undef-value-errors=<yes|no> [default: yes] </code>
</span>
@@ -874,6 +926,11 @@
and/or by using a smaller value for the
option <code class="varname">--num-callers</code>.
</p>
+<p>If you want to use
+ <code class="computeroutput">--xtree-memory=full</code> memory profiling
+ (see <a class="xref" href="manual-core.html#manual-core.xtree" title="2.9. Execution Trees">Execution Trees</a> ), then you cannot
+ specify <code class="varname">--keep-stacktraces=free</code>
+ or <code class="varname">--keep-stacktraces=none</code>.</p>
</dd>
<dt>
<a name="opt.freelist-vol"></a><span class="term">
@@ -1500,7 +1557,7 @@
</pre>
</li>
<li class="listitem">
-<p><code class="varname">leak_check [full*|summary]
+<p><code class="varname">leak_check [full*|summary|xtleak]
[kinds <set>|reachable|possibleleak*|definiteleak]
[heuristics heur1,heur2,...]
[increased*|changed|any]
@@ -1508,7 +1565,7 @@
</code>
performs a leak check. The <code class="varname">*</code> in the arguments
indicates the default values. </p>
-<p> If the <code class="varname">[full*|summary]</code> argument is
+<p> If the <code class="varname">[full*|summary|xtleak]</code> argument is
<code class="varname">summary</code>, only a summary of the leak search is given;
otherwise a full leak report is produced. A full leak report gives
detailed information for each leak: the stack trace where the leaked blocks
@@ -1522,6 +1579,13 @@
of leak records to output. If this maximum is reached, the leak
search outputs the records with the biggest number of bytes.
</p>
+<p>The value <code class="varname">xtleak</code> also produces a full leak report,
+ but output it as an xtree in a file xtleak.kcg.%p.%n (see <a class="xref" href="manual-core.html#opt.log-file">--log-file</a>).
+ See <a class="xref" href="manual-core.html#manual-core.xtree" title="2.9. Execution Trees">Execution Trees</a>
+ for a detailed explanation about execution trees formats.
+ See <a class="xref" href="mc-manual.html#opt.xtree-leak">--xtree-leak</a> for the description of the events
+ in a xtree leak file.
+ </p>
<p>The <code class="varname">kinds</code> argument controls what kind of blocks
are shown for a <code class="varname">full</code> leak search. The set of leak kinds
to show can be specified using a <code class="varname"><set></code> similarly
diff --git a/docs/html/ms-manual.html b/docs/html/ms-manual.html
index fbb0e5a..b6e933e 100644
--- a/docs/html/ms-manual.html
+++ b/docs/html/ms-manual.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>9. Massif: a heap profiler</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="manual.html" title="Valgrind User Manual">
<link rel="prev" href="drd-manual.html" title="8. DRD: a thread error detector">
@@ -75,6 +75,10 @@
program is using, it also gives very detailed information that indicates
which parts of your program are responsible for allocating the heap memory.
</p>
+<p>Massif also provides <a class="xref" href="manual-core.html#manual-core.xtree" title="2.9. Execution Trees">Execution Trees</a> memory
+ profiling using the command line
+ option <code class="computeroutput">--xtree-memory</code> and the monitor command
+ <code class="computeroutput">xtmemory</code>.</p>
</div>
<div class="sect1">
<div class="titlepage"><div><div><h2 class="title" style="clear: both">
diff --git a/docs/html/nl-manual.html b/docs/html/nl-manual.html
index 643a272..d6b0f62 100644
--- a/docs/html/nl-manual.html
+++ b/docs/html/nl-manual.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>14. Nulgrind: the minimal Valgrind tool</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="manual.html" title="Valgrind User Manual">
<link rel="prev" href="lk-manual.html" title="13. Lackey: an example tool">
diff --git a/docs/html/quick-start.html b/docs/html/quick-start.html
index 00d7b07..afd3911 100644
--- a/docs/html/quick-start.html
+++ b/docs/html/quick-start.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>The Valgrind Quick Start Guide</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="QuickStart.html" title="The Valgrind Quick Start Guide">
<link rel="prev" href="QuickStart.html" title="The Valgrind Quick Start Guide">
diff --git a/docs/html/sg-manual.html b/docs/html/sg-manual.html
index ec96ab9..ab229dc 100644
--- a/docs/html/sg-manual.html
+++ b/docs/html/sg-manual.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>11. SGCheck: an experimental stack and global array overrun detector</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="manual.html" title="Valgrind User Manual">
<link rel="prev" href="dh-manual.html" title="10. DHAT: a dynamic heap analysis tool">
diff --git a/docs/html/tech-docs.html b/docs/html/tech-docs.html
index f2fc1e0..bf29eba 100644
--- a/docs/html/tech-docs.html
+++ b/docs/html/tech-docs.html
@@ -3,7 +3,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<title>Valgrind Technical Documentation</title>
<link rel="stylesheet" type="text/css" href="vg_basic.css">
-<meta name="generator" content="DocBook XSL Stylesheets V1.78.1">
+<meta name="generator" content="DocBook XSL Stylesheets V1.79.1">
<link rel="home" href="index.html" title="Valgrind Documentation">
<link rel="up" href="index.html" title="Valgrind Documentation">
<link rel="prev" href="faq.html" title="Valgrind Frequently Asked Questions">
@@ -22,10 +22,10 @@
<div>
<div><h1 class="title">
<a name="tech-docs"></a>Valgrind Technical Documentation</h1></div>
-<div><p class="releaseinfo">Release 3.12.0 20 October 2016</p></div>
-<div><p class="copyright">Copyright © 2000-2016 <a class="ulink" href="http://www.valgrind.org/info/developers.html" target="_top">Valgrind Developers</a></p></div>
+<div><p class="releaseinfo">Release 3.13.0 15 June 2017</p></div>
+<div><p class="copyright">Copyright © 2000-2017 <a class="ulink" href="http://www.valgrind.org/info/developers.html" target="_top">Valgrind Developers</a></p></div>
<div><div class="legalnotice">
-<a name="idm140639109670320"></a><p>Email: <a class="ulink" href="mailto:valgrind@valgrind.org" target="_top">valgrind@valgrind.org</a></p>
+<a name="idm140394919379488"></a><p>Email: <a class="ulink" href="mailto:valgrind@valgrind.org" target="_top">valgrind@valgrind.org</a></p>
</div></div>
</div>
<hr>
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(e)
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(,)
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-(wi)
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-(th)
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-(an)
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-(of)
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--265 TJm
-(the)
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-(e)
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-(as)
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-(hours,)
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-3.875451
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-(minutes,)
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-(seconds)
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-(and)
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-(xt)
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-(Note)
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-(that)
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-(stack)
-[3.875451
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-(is)
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-(an)
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-(imprecise,)
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-(mechanism)
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-(that)
-[2.769603
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-0
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-0
-2.769603
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-(may)
-[7.750903
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-(gi)
-[4.9813
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-25 TJm
-(v)
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-15 TJm
-(e)
-[4.423394
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--305 TJm
-(v)
-[4.9813
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-15 TJm
-(ery)
-[4.423394
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-(misleading)
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-(results,)
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-2.769603
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-(or)
-[4.9813
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-(none)
-[4.9813
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-(at)
-[4.423394
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-(all.)
-[4.423394
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-2.769603
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-(It)
-[3.317546
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--318 TJm
-(should)
-[3.875451
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-0
-4.9813
-0
-2.769603
-0
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--317 TJm
-(be)
-[4.9813
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-(used)
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-(only)
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-(in)
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-(emer)
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-(gencies,)
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-(when)
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-(normal)
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-(ails,)
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-(and)
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-(it)
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-(is)
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-(important)
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-(to)
-[2.769603
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-(ne)
-[4.9813
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-(ha)
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-(v)
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-(e)
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-(stack)
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-(traces.)
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-(Stack)
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-(scanning)
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-(is)
-[2.769603
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-(a)
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-(simple)
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-2.769603
-0
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--220 TJm
-(t)
-[2.769603
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-(echnique:)
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-(the)
-[2.769603
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-(unwinder)
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-(reads)
-[3.317546
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-(w)
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-(ords)
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-(from)
-[3.317546
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-(the)
-[2.769603
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-(and)
-[4.423394
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-(tries)
-[2.769603
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-2.769603
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-0
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--219 TJm
-(to)
-[2.769603
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--219 TJm
-(guess)
-[4.9813
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-0
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-(which)
-[7.192997
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-(of)
-[4.9813
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-(them)
-[2.769603
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-(might)
-[7.750903
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-(be)
-[4.9813
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-(return)
-[3.317546
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-0
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-(addresses,)
-[4.423394
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-(by)
-[4.9813
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-(checking)
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--307 TJm
-(to)
-[2.769603
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-(see)
-[3.875451
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-(if)
-[2.769603
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-(the)
-[2.769603
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-(y)
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-(point)
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-(just)
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-(ARM)
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-(or)
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-(Thumb)
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-(call)
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-(ions.)
-[2.769603
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-(If)
-[3.317546
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-(so,)
-[3.875451
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-(the)
-[2.769603
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-(w)
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-(ord)
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-(is)
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-(added)
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-(to)
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-(The)
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-(mai)
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-1 TJm
-(n)
-[4.9813
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-(danger)
-[4.9813
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--250 TJm
-(occurs)
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-3.317546
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-(when)
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-(a)
-[4.423394
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-(function)
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--250 TJm
-(call)
-[4.423394
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-(lea)
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-(its)
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-(e)
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-(xposed,)
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-(and)
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-(a)
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-(is)
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-(b)
-[4.9813
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-20 TJm
-(ut)
-[4.9813
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-(the)
-[2.769603
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--239 TJm
-(ne)
-[4.9813
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-25 TJm
-(w)
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--239 TJm
-(does)
-[4.9813
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-(not)
-[4.9813
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(,)
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-(check)
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-(==15363==)
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-(Address)
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-0
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-0
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-0
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-0
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-0] Tj
--852 TJm
-(a)
-[5.97756
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--426 TJm
-(global)
-[5.97756
-0
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-0
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-0
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-0
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-0
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-0] Tj
--426 TJm
-(variable)
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-0
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-0
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-0
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-0
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-0
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-0
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-0] Tj
--426 TJm
-(declared)
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-0
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-0
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-0
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-0
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-0] Tj
--426 TJm
-(at)
-[5.97756
-0
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-0] Tj
--426 TJm
-(varinfo1.c:41)
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-0
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-0] Tj
--426 TJm
-(Uninitialised)
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--426 TJm
-(byte\(s\))
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-0
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-0
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-0
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--426 TJm
-(found)
-[5.97756
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-0
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-0
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-0] Tj
--426 TJm
-(during)
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-0
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--426 TJm
-(client)
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-0
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-0
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-0
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--426 TJm
-(check)
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-0
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-0
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-0] Tj
--426 TJm
-(request)
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-(==15370==)
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--1704 TJm
-(at)
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--426 TJm
-(0x80484A9:)
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--426 TJm
-(croak)
-[5.97756
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-0
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-0
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-0] Tj
--426 TJm
-(\(varinfo1.c:28\))
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-(==15370==)
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-(by)
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-(0x8048550:)
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--426 TJm
-(main)
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--426 TJm
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-(0xbeb4a0cc)
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-(is)
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-(0)
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-(bytes)
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-(inside)
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-(local)
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-(var)
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-(at)
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-(in)
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-(1)
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-(e)
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-(the)
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3.875451
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10 TJm
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10 TJm
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--264 TJm
-(support)
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-0
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--264 TJm
-(handling)
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-0
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-(of)
-[4.9813
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-(proprietary)
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-(for)
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-(the)
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-(Po)
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--264 TJm
-(SGX)
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--264 TJm
-(5XX)
-[4.9813
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-0
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--264 TJm
-(series)
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-0
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-(of)
-[4.9813
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-(GPUs)
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-0
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--301 TJm
-(on)
-[4.9813
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-(Android)
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--301 TJm
-(de)
-[4.9813
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-25 TJm
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-(F)
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-0
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--302 TJm
-(to)
-[2.769603
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--301 TJm
-(select)
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-0
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--301 TJm
-(this)
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-0
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--302 TJm
-(does)
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-0
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--301 TJm
-(not)
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-(cause)
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--302 TJm
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--301 TJm
-(problems,)
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--314 TJm
-(b)
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-(cause)
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-(to)
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-(the)
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-(to)
-[2.769603
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-(3XX)
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--250 TJm
-(de)
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(e)
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-(e)
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-(balanced)
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-(tree)
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-(w)
-[7.192997
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-(orking)
-[4.9813
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-0
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--268 TJm
-(set)
-[3.875451
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--268 TJm
-(of)
-[4.9813
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--268 TJm
-(a)
-[4.423394
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-(program)
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--269 TJm
-(is)
-[2.769603
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--268 TJm
-(big,)
-[4.9813
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-0
-2.49065
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--272 TJm
-(increasing)
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3.317546
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4.9813
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--268 TJm
-(the)
-[2.769603
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--269 TJm
-(number)
-[4.9813
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--268 TJm
-(of)
-[4.9813
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--268 TJm
-(sectors)
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--268 TJm
-(may)
-[7.750903
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--268 TJm
-(impro)
-[2.769603
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-0
-3.317546
-0
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-15 TJm
-(v)
-[4.9813
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-15 TJm
-(e)
-[4.423394
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--268 TJm
-(performance)
-[4.9813
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-(by)
-[4.9813
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--268 TJm
-(reducing)
-[3.317546
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-0
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--269 TJm
-(the)
-[2.769603
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-0] Tj
--268 TJm
-(number)
-[4.9813
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-72 626.351 Td
-(of)
-[4.9813
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-(re-translations)
-[3.317546
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-0
-4.9813
-0
-3.875451
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--244 TJm
-(needed.)
-[4.9813
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-0
-4.9813
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--308 TJm
-(Sectors)
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--244 TJm
-(are)
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-(allocated)
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-4.423394
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--244 TJm
-(on)
-[4.9813
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--244 TJm
-(demand.)
-[4.9813
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-0
-4.423394
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-0
-4.9813
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-2.49065
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--616 TJm
-(Once)
-[7.192997
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--244 TJm
-(allocated,)
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-4.423394
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-0
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--245 TJm
-(a)
-[4.423394
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--244 TJm
-(sector)
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-2.769603
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-4.9813
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-3.317546
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--244 TJm
-(can)
-[4.423394
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--244 TJm
-(ne)
-[4.9813
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-25 TJm
-(v)
-[4.9813
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-15 TJm
-(er)
-[4.423394
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-3.317546
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--244 TJm
-(be)
-[4.9813
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--244 TJm
-(freed,)
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--246 TJm
-(and)
-[4.423394
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--244 TJm
-(occupies)
-[4.9813
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-2.769603
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-72 614.396 Td
-(considerable)
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--319 TJm
-(space,)
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0] Tj
-335 TJm
-(d)
-[4.9813
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--1 TJm
-(e)
-[4.423394
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-1 TJm
-(pending)
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-2.769603
-0
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--319 TJm
-(on)
-[4.9813
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--319 TJm
-(the)
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[2.769603
0
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--319 TJm
-(tool)
-[2.769603
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--318 TJm
-(and)
-[4.423394
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--319 TJm
-(the)
-[2.769603
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--319 TJm
-(v)
-[4.9813
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-25 TJm
-(alue)
-[4.423394
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--318 TJm
-(of)
-[4.9813
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--319 TJm
-(40)
-[4.9813
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-(MB)
-[8.856751
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-(per)
-[4.9813
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-72 602.441 Td
-(sector)
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--307 TJm
-(for)
-[3.317546
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--965 TJm
-(Use)
-[7.192997
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-(the)
-[2.769603
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--308 TJm
-(option)
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-[2.769603
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--307 TJm
-(obtain)
-[4.9813
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-2.769603
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--308 TJm
-(precise)
-[4.9813
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-2.769603
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-3.875451
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--307 TJm
-(information)
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-2.769603
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--308 TJm
-(about)
-[4.423394
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--307 TJm
-(the)
-[2.769603
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--308 TJm
-(memory)
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-3.317546
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--307 TJm
-(used)
-[4.9813
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--308 TJm
-(by)
-[4.9813
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--307 TJm
-(a)
-[4.423394
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-(sector)
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--250 TJm
-(and)
-[4.423394
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--250 TJm
-(the)
-[2.769603
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--250 TJm
-(allocation)
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--250 TJm
-(and)
-[4.423394
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--250 TJm
-(rec)
-[3.317546
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-15 TJm
-(ycling)
-[4.9813
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--250 TJm
-(of)
-[4.9813
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--250 TJm
-(sectors.)
-[3.875451
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-(0,)
-[5.97756
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-(meaning)
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-(use)
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--600 TJm
-(tool)
-[5.97756
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-(erage)
-[4.423394
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--422 TJm
-(of)
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-(basic)
-[4.9813
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0
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(on)
[4.9813
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-(linux\).)
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+-750 TJm
+(On)
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+(linux,)
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4.9813
0
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-(By)
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0] Tj
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(def)
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0
2.49065
0] Tj
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-(no)
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0] Tj
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-(replacement)
-[3.317546
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0
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--299 TJm
-(is)
-[2.769603
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--299 TJm
-(done)
-[4.9813
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-(for)
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0
3.317546
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(a)
[4.423394
0] Tj
--299 TJm
-(statically)
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-0
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--299 TJm
-(link)
-[2.769603
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-10 TJm
-(ed)
-[4.423394
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-(binary)
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--251 TJm
-(or)
-[4.9813
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--251 TJm
-(for)
-[3.317546
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-(alternati)
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-25 TJm
+20 TJm
(v)
[4.9813
0] Tj
-15 TJm
-(e)
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--251 TJm
-(libraries,)
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--251 TJm
-(e)
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-15 TJm
-(xcept)
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[4.9813
0
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2.769603
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--251 TJm
-(for)
-[3.317546
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--251 TJm
-(the)
-[2.769603
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--250 TJm
-(allocation)
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--251 TJm
-(functions)
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0
4.9813
0
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0] Tj
--251 TJm
-(\(malloc,)
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--251 TJm
-(free,)
-[3.317546
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-0
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--251 TJm
-(calloc,)
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--252 TJm
-(memal)
-[7.750903
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-1 TJm
-(ign,)
-[2.769603
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-0
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-0
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--252 TJm
-(realloc,)
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--251 TJm
-(operator)
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-(ne)
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-25 TJm
-(w)
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-65 TJm
-(,)
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--213 TJm
-(operator)
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--203 TJm
-(delete,)
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--213 TJm
-(etc.\))
-[4.423394
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--294 TJm
-(Such)
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--204 TJm
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--204 TJm
-(are)
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--203 TJm
-(intercepted)
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--204 TJm
-(by)
-[4.9813
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--203 TJm
-(def)
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-10 TJm
-(ault)
-[4.423394
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--204 TJm
-(in)
-[2.769603
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--203 TJm
-(an)
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-15 TJm
-(y)
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--203 TJm
-(shared)
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--204 TJm
-(library)
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--203 TJm
-(or)
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--204 TJm
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--203 TJm
-(the)
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--204 TJm
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-(x)
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-(ecutable)
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-(if)
-[2.769603
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-(the)
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-15 TJm
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--212 TJm
-(are)
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--213 TJm
-(e)
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-(xported)
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--213 TJm
-(as)
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--212 TJm
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--213 TJm
-(symbols.)
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-(This)
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-(means)
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-(that)
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--213 TJm
-(if)
-[2.769603
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--212 TJm
-(a)
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-(replacement)
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--213 TJm
-(allocation)
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--212 TJm
-(library)
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-(such)
-[3.875451
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--213 TJm
-(as)
-[4.423394
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--213 TJm
-(is)
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--213 TJm
-(found,)
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-0
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--220 TJm
-(its)
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-(functions)
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--283 TJm
-(are)
-[4.423394
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--283 TJm
-(also)
-[4.423394
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--283 TJm
-(intercepted)
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--283 TJm
-(by)
-[4.9813
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--283 TJm
-(def)
-[4.9813
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-10 TJm
-(ault.)
-[4.423394
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-0
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-(In)
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--283 TJm
-(some)
-[3.875451
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--283 TJm
-(cases,)
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--292 TJm
-(the)
-[2.769603
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--283 TJm
-(replacements)
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--283 TJm
-(allo)
-[4.423394
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-0
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-25 TJm
-(w)
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-4.9813
-0
-3.875451
-0] Tj
--327 TJm
-(of)
-[4.9813
-0
-3.317546
-0] Tj
--327 TJm
-(code)
-[4.423394
-0
-4.9813
-0
-4.9813
-0
-4.423394
-0] Tj
--327 TJm
-(in)
-[2.769603
-0
-4.9813
-0] Tj
--328 TJm
-(the)
-[2.769603
-0
-4.9813
-0
-4.423394
-0] Tj
--327 TJm
-(speci\002ed)
-[3.875451
-0
-4.9813
-0
-4.423394
-0
-4.423394
-0
-2.769603
-0
-5.539206
-0
-4.423394
-0
-4.9813
-0] Tj
--327 TJm
-(address)
-[4.423394
-0
-4.9813
-0
-4.9813
-0
-3.317546
-0
-4.423394
-0
-3.875451
-0
-3.875451
-0] Tj
--327 TJm
-(range.)
-[3.317546
-0
-4.423394
-0
-4.9813
-0
-4.9813
-0
-4.423394
-0
-2.49065
-0] Tj
--1083 TJm
-(Useful)
-[7.192997
-0
-3.875451
-0
-4.423394
-0
-3.317546
-0
-4.9813
-0
-2.769603
-0] Tj
--327 TJm
-(if)
-[2.769603
-0
-3.317546
-0] Tj
--327 TJm
-(you)
-[4.9813
-0
-4.9813
-0
-4.9813
-0] Tj
--327 TJm
-(are)
-[4.423394
-0
-3.317546
-0
-4.423394
-0] Tj
--327 TJm
-(deb)
-[4.9813
-0
-4.423394
-0
-4.9813
-0] Tj
-20 TJm
-(ugging)
-[4.9813
-0
-4.9813
-0
-4.9813
-0
-2.769603
-0
-4.9813
-0
-4.9813
-0] Tj
--327 TJm
-(a)
-[4.423394
-0] Tj
--327 TJm
-(JIT)
-[3.875451
-0
-3.317546
-0
-6.087149
-0] Tj
--327 TJm
-(compiler)
-[4.423394
-0
-4.9813
-0
-7.750903
-0
-4.9813
-0
-2.769603
-0
-2.769603
-0
-4.423394
-0
-3.317546
-0] Tj
--328 TJm
-(or)
-[4.9813
-0
-3.317546
-0] Tj
--327 TJm
-(some)
-[3.875451
-0
-4.9813
-0
-7.750903
-0
-4.423394
-0] Tj
-72 686.127 Td
-(other)
-[4.9813
-0
-2.769603
-0
-4.9813
-0
-4.423394
-0
-3.317546
-0] Tj
--261 TJm
-(dynamic)
-[4.9813
-0
-4.9813
-0
-4.9813
-0
-4.423394
-0
-7.750903
-0
-2.769603
-0
-4.423394
-0] Tj
--260 TJm
-(code)
-[4.423394
-0
-4.9813
-0
-4.9813
-0
-4.423394
-0] Tj
--261 TJm
-(generation)
-[4.9813
-0
-4.423394
-0
-4.9813
-0
-4.423394
-0
-3.317546
-0
-4.423394
-0
-2.769603
-0
-2.769603
-0
-4.9813
-0
-4.9813
-0] Tj
--261 TJm
-(system.)
-[3.875451
-0
-4.9813
-0
-3.875451
-0
-2.769603
-0
-4.423394
-0
-7.750903
-0
-2.49065
-0] Tj
--683 TJm
-(After)
-[7.192997
-0
-3.317546
-0
-2.769603
-0
-4.423394
-0
-3.317546
-0] Tj
--261 TJm
-(this)
-[2.769603
-0
-4.9813
-0
-2.769603
-0
-3.875451
-0] Tj
--261 TJm
-(call,)
-[4.423394
-0
-4.423394
-0
-2.769603
-0
-2.769603
-0
-2.49065
-0] Tj
--263 TJm
-(attempts)
-[4.423394
-0
-2.769603
-0
-2.769603
-0
-4.423394
-0
-7.750903
-0
-4.9813
-0
-2.769603
-0
-3.875451
-0] Tj
--261 TJm
-(to)
-[2.769603
-0
-4.9813
-0] Tj
--260 TJm
-(e)
-[4.423394
-0] Tj
-15 TJm
-(x)
-[4.9813
-0] Tj
-15 TJm
-(ecute)
-[4.423394
-0
-4.423394
-0
-4.9813
-0
-2.769603
-0
-4.423394
-0] Tj
--261 TJm
-(code)
-[4.423394
-0
-4.9813
-0
-4.9813
-0
-4.423394
-0] Tj
--261 TJm
-(in)
-[2.769603
-0
-4.9813
-0] Tj
--260 TJm
-(the)
-[2.769603
-0
-4.9813
-0
-4.423394
-0] Tj
--261 TJm
-(in)
-[2.769603
-0
-4.9813
-0] Tj
-40 TJm
-(v)
-[4.9813
-0] Tj
-25 TJm
-(alidated)
-[4.423394
-0
-2.769603
-0
-2.769603
-0
-4.9813
-0
-4.423394
-0
-2.769603
-0
-4.423394
-0
-4.9813
-0] Tj
--260 TJm
-(address)
-[4.423394
-0
-4.9813
-0
-4.9813
-0
-3.317546
-0
-4.423394
-0
-3.875451
-0
-3.875451
-0] Tj
--261 TJm
-(range)
-[3.317546
-0
-4.423394
-0
-4.9813
-0
-4.9813
-0
-4.423394
-0] Tj
--261 TJm
-(will)
-[7.192997
-0
-2.769603
-0
-2.769603
-0
-2.769603
-0] Tj
-72 674.172 Td
-(cause)
-[4.423394
-0
-4.423394
-0
-4.9813
-0
-3.875451
-0
-4.423394
-0] Tj
--333 TJm
-(V)
-[7.192997
-0] Tj
-111 TJm
-(algrind)
-[4.423394
-0
-2.769603
-0
-4.9813
-0
-3.317546
-0
-2.769603
-0
-4.9813
-0
-4.9813
-0] Tj
--333 TJm
-(to)
-[2.769603
-0
-4.9813
-0] Tj
--334 TJm
-(mak)
-[7.750903
-0
-4.423394
-0
-4.9813
-0] Tj
-10 TJm
-(e)
-[4.423394
-0] Tj
--333 TJm
-(ne)
-[4.9813
-0
-4.423394
-0] Tj
-25 TJm
-(w)
-[7.192997
-0] Tj
--333 TJm
-(translations)
-[2.769603
-0
-3.317546
-0
-4.423394
-0
-4.9813
-0
-3.875451
-0
-2.769603
-0
-4.423394
-0
-2.769603
-0
-2.769603
-0
-4.9813
-0
-4.9813
-0
-3.875451
-0] Tj
--333 TJm
-(of)
-[4.9813
-0
-3.317546
-0] Tj
--334 TJm
-(that)
-[2.769603
-0
-4.9813
-0
-4.423394
-0
-2.769603
-0] Tj
--333 TJm
-(code,)
-[4.423394
-0
-4.9813
-0
-4.9813
-0
-4.423394
-0
-2.49065
-0] Tj
--354 TJm
-(which)
-[7.192997
-0
-4.9813
-0
-2.769603
-0
-4.423394
-0
-4.9813
-0] Tj
--333 TJm
-(is)
-[2.769603
-0
-3.875451
-0] Tj
--334 TJm
-(probably)
-[4.9813
-0
-3.317546
-0
-4.9813
-0
-4.9813
-0
-4.423394
-0
-4.9813
-0
-2.769603
-0
-4.9813
-0] Tj
--333 TJm
-(the)
-[2.769603
-0
-4.9813
-0
-4.423394
-0] Tj
--333 TJm
-(semantics)
-[3.875451
-0
-4.423394
-0
-7.750903
-0
-4.423394
-0
-4.9813
-0
-2.769603
-0
-2.769603
-0
-4.423394
-0
-3.875451
-0] Tj
--333 TJm
-(you)
-[4.9813
-0
-4.9813
-0
-4.9813
-0] Tj
--334 TJm
-(w)
-[7.192997
-0] Tj
-10 TJm
-(ant.)
-[4.423394
-0
-4.9813
-0
-2.769603
-0
-2.49065
-0] Tj
--1119 TJm
-(Note)
-[7.192997
-0
-4.9813
-0
-2.769603
-0
-4.423394
-0] Tj
--333 TJm
-(that)
-[2.769603
-0
-4.9813
-0
-4.423394
-0
-2.769603
-0] Tj
--334 TJm
-(code)
-[4.423394
-0
-4.9813
-0
-4.9813
-0
-4.423394
-0] Tj
-72 662.217 Td
-(in)
-[2.769603
-0
-4.9813
-0] Tj
-40 TJm
-(v)
-[4.9813
-0] Tj
-25 TJm
-(alidations)
-[4.423394
-0
-2.769603
-0
-2.769603
-0
-4.9813
-0
-4.423394
-0
-2.769603
-0
-2.769603
-0
-4.9813
-0
-4.9813
-0
-3.875451
-0] Tj
--323 TJm
-(are)
-[4.423394
-0
-3.317546
-0
-4.423394
-0] Tj
--323 TJm
-(e)
-[4.423394
-0] Tj
-15 TJm
-(xpensi)
-[4.9813
-0
-4.9813
-0
-4.423394
-0
-4.9813
-0
-3.875451
-0
-2.769603
-0] Tj
-25 TJm
-(v)
-[4.9813
-0] Tj
-15 TJm
-(e)
-[4.423394
-0] Tj
--322 TJm
-(because)
-[4.9813
-0
-4.423394
-0
-4.423394
-0
-4.423394
-0
-4.9813
-0
-3.875451
-0
-4.423394
-0] Tj
--323 TJm
-(\002nding)
-[5.539206
-0
-4.9813
-0
-4.9813
-0
-2.769603
-0
-4.9813
-0
-4.9813
-0] Tj
--323 TJm
-(all)
-[4.423394
-0
-2.769603
-0
-2.769603
-0] Tj
--323 TJm
-(the)
-[2.769603
-0
-4.9813
-0
-4.423394
-0] Tj
--323 TJm
-(rele)
-[3.317546
-0
-4.423394
-0
-2.769603
-0
-4.423394
-0] Tj
-25 TJm
-(v)
-[4.9813
-0] Tj
-25 TJm
-(ant)
-[4.423394
-0
-4.9813
-0
-2.769603
-0] Tj
--322 TJm
-(translations)
-[2.769603
-0
-3.317546
-0
-4.423394
-0
-4.9813
-0
-3.875451
-0
-2.769603
-0
-4.423394
-0
-2.769603
-0
-2.769603
-0
-4.9813
-0
-4.9813
-0
-3.875451
-0] Tj
--323 TJm
-(quickly)
-[4.9813
-0
-4.9813
-0
-2.769603
-0
-4.423394
-0
-4.9813
-0
-2.769603
-0
-4.9813
-0] Tj
--323 TJm
-(is)
-[2.769603
-0
-3.875451
-0] Tj
--323 TJm
-(v)
-[4.9813
-0] Tj
-15 TJm
-(ery)
-[4.423394
-0
-3.317546
-0
-4.9813
-0] Tj
--323 TJm
-(dif)
-[4.9813
-0
-2.769603
-0
-3.317546
-0] Tj
-25 TJm
-(\002cult,)
-[5.539206
-0
-4.423394
-0
-4.9813
-0
-2.769603
-0
-2.769603
-0
-2.49065
-0] Tj
--341 TJm
-(so)
-[3.875451
-0
-4.9813
-0] Tj
--322 TJm
-(try)
-[2.769603
-0
-3.317546
-0
-4.9813
-0] Tj
--323 TJm
-(not)
-[4.9813
-0
-4.9813
-0
-2.769603
-0] Tj
--323 TJm
-(to)
-[2.769603
-0
-4.9813
-0] Tj
--323 TJm
-(call)
-[4.423394
-0
-4.423394
-0
-2.769603
-0
-2.769603
-0] Tj
--323 TJm
-(it)
-[2.769603
-0
-2.769603
-0] Tj
-72 650.261 Td
-(often.)
-[4.9813
-0
-3.317546
-0
-2.769603
-0
-4.423394
-0
-4.9813
-0
-2.49065
-0] Tj
--304 TJm
-(Note)
-[7.192997
-0
-4.9813
-0
-2.769603
-0
-4.423394
-0] Tj
--232 TJm
-(that)
-[2.769603
-0
-4.9813
-0
-4.423394
-0
-2.769603
-0] Tj
--232 TJm
-(you)
-[4.9813
-0
-4.9813
-0
-4.9813
-0] Tj
--232 TJm
-(can)
-[4.423394
-0
-4.423394
-0
-4.9813
-0] Tj
--232 TJm
-(be)
-[4.9813
-0
-4.423394
-0] Tj
--232 TJm
-(cle)
-[4.423394
-0
-2.769603
-0
-4.423394
-0] Tj
-25 TJm
-(v)
-[4.9813
-0] Tj
-15 TJm
-(er)
-[4.423394
-0
-3.317546
-0] Tj
--232 TJm
-(about)
-[4.423394
-0
-4.9813
-0
-4.9813
-0
-4.9813
-0
-2.769603
-0] Tj
--232 TJm
-(this:)
-[2.769603
-0
-4.9813
-0
-2.769603
-0
-3.875451
-0
-2.769603
-0] Tj
--301 TJm
-(you)
-[4.9813
-0
-4.9813
-0
-4.9813
-0] Tj
--231 TJm
-(only)
-[4.9813
-0
-4.9813
-0
-2.769603
-0
-4.9813
-0] Tj
--232 TJm
-(need)
-[4.9813
-0
-4.423394
-0
-4.423394
-0
-4.9813
-0] Tj
--232 TJm
-(to)
-[2.769603
-0
-4.9813
-0] Tj
--232 TJm
-(call)
-[4.423394
-0
-4.423394
-0
-2.769603
-0
-2.769603
-0] Tj
--232 TJm
-(it)
-[2.769603
-0
-2.769603
-0] Tj
--232 TJm
-(when)
-[7.192997
-0
-4.9813
-0
-4.423394
-0
-4.9813
-0] Tj
--232 TJm
-(an)
-[4.423394
-0
-4.9813
-0] Tj
--232 TJm
-(area)
-[4.423394
-0
-3.317546
-0
-4.423394
-0
-4.423394
-0] Tj
--232 TJm
-(which)
-[7.192997
-0
-4.9813
-0
-2.769603
-0
-4.423394
-0
-4.9813
-0] Tj
--232 TJm
-(pre)
-[4.9813
-0
-3.317546
-0
-4.423394
-0] Tj
-25 TJm
-(viously)
-[4.9813
-0
-2.769603
-0
-4.9813
-0
-4.9813
-0
-3.875451
-0
-2.769603
-0
-4.9813
-0] Tj
--232 TJm
-(contained)
-[4.423394
-0
-4.9813
-0
-4.9813
-0
-2.769603
-0
-4.423394
-0
-2.769603
-0
-4.9813
-0
-4.423394
-0
-4.9813
-0] Tj
--232 TJm
-(code)
-[4.423394
-0
-4.9813
-0
-4.9813
-0
-4.423394
-0] Tj
--232 TJm
-(is)
-[2.769603
-0
-3.875451
-0] Tj
-72 638.306 Td
-(o)
-[4.9813
-0] Tj
-15 TJm
-(v)
-[4.9813
-0] Tj
-15 TJm
-(erwritten)
-[4.423394
-0
-3.317546
-0
-7.192997
-0
-3.317546
-0
-2.769603
-0
-2.769603
-0
-2.769603
-0
-4.423394
-0
-4.9813
-0] Tj
--234 TJm
-(with)
-[7.192997
-0
-2.769603
-0
-2.769603
-0
-4.9813
-0] Tj
--234 TJm
-(ne)
-[4.9813
-0
-4.423394
-0] Tj
-25 TJm
-(w)
-[7.192997
-0] Tj
--234 TJm
-(code.)
-[4.423394
-0
-4.9813
-0
-4.9813
-0
-4.423394
-0
-2.49065
-0] Tj
--609 TJm
-(Y)
-[7.192997
-0] Tj
-110 TJm
-(ou)
-[4.9813
-0
-4.9813
-0] Tj
--234 TJm
-(can)
-[4.423394
-0
-4.423394
-0
-4.9813
-0] Tj
--234 TJm
-(choose)
-[4.423394
-0
-4.9813
-0
-4.9813
-0
-4.9813
-0
-3.875451
-0
-4.423394
-0] Tj
--234 TJm
-(to)
-[2.769603
-0
-4.9813
-0] Tj
--234 TJm
-(write)
-[7.192997
-0
-3.317546
-0
-2.769603
-0
-2.769603
-0
-4.423394
-0] Tj
--234 TJm
-(code)
-[4.423394
-0
-4.9813
-0
-4.9813
-0
-4.423394
-0] Tj
--234 TJm
-(into)
-[2.769603
-0
-4.9813
-0
-2.769603
-0
-4.9813
-0] Tj
--234 TJm
-(fresh)
-[3.317546
-0
-3.317546
-0
-4.423394
-0
-3.875451
-0
-4.9813
-0] Tj
--234 TJm
-(memory)
-[7.750903
-0
-4.423394
-0
-7.750903
-0
-4.9813
-0
-3.317546
-0
-4.9813
-0] Tj
-65 TJm
-(,)
-[2.49065
-0] Tj
--238 TJm
-(and)
-[4.423394
-0
-4.9813
-0
-4.9813
-0] Tj
--234 TJm
-(just)
-[2.769603
-0
-4.9813
-0
-3.875451
-0
-2.769603
-0] Tj
--234 TJm
-(call)
-[4.423394
-0
-4.423394
-0
-2.769603
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-(to)
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-5.97756
-0] Tj
--426 TJm
-(arg)
-[5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(given)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(and)
-[5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(multiple)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(valgrind)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(pids)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(found:)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
-72 663.811 Td
-(use)
-[5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(--pid=2479)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(for)
-[5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(valgrind)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(--tool=memcheck)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(--vgdb=yes)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(--vgdb-error=0)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(./prog)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
-72 651.856 Td
-(use)
-[5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(--pid=2481)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(for)
-[5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(valgrind)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(--tool=memcheck)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(--vgdb=yes)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(--vgdb-error=0)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(./prog)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
-72 639.9 Td
-(use)
-[5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(--pid=2483)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(for)
-[5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(valgrind)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(--vgdb=yes)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(--vgdb-error=0)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(./another_prog)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
-72 627.945 Td
-(Remote)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(communication)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(error:)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(Resource)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(temporarily)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(unavailable.)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
-72 615.99 Td
-(\(gdb\))
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--852 TJm
-(target)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(remote)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(|)
-[5.97756
-0] Tj
--426 TJm
-(vgdb)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(--pid=2479)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
-72 604.035 Td
-(Remote)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(debugging)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(using)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(|)
-[5.97756
-0] Tj
--426 TJm
-(vgdb)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(--pid=2479)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
-72 592.08 Td
-(relaying)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(data)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(between)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(gdb)
-[5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(and)
-[5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(process)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(2479)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
-72 580.125 Td
-(Reading)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(symbols)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(from)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(/lib/ld-linux.so.2...done.)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
-72 568.169 Td
-(Reading)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(symbols)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(from)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(/usr/lib/debug/lib/ld-2.11.2.so.debug...done.)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
-72 556.214 Td
-(Loaded)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(symbols)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(for)
-[5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(/lib/ld-linux.so.2)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
-72 544.259 Td
-([Switching)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(to)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(Thread)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(2479])
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
-72 532.304 Td
-(0x001f2850)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(in)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(_start)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(\(\))
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(from)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(/lib/ld-linux.so.2)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
-72 520.349 Td
-(\(gdb\))
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
-/DeviceRGB {} cs
-[0 0 0] sc
-/DeviceRGB {} CS
-[0 0 0] SC
-/DeviceRGB {} cs
-[0 0 0] sc
-/DeviceRGB {} CS
-[0 0 0] SC
-/DeviceRGB {} cs
-[0 0 0] sc
-/DeviceRGB {} CS
-[0 0 0] SC
-/DeviceRGB {} cs
-[0 0 0] sc
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-(1)
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(of)
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2.769603
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--395 TJm
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--395 TJm
-(the)
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-(V)
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-(scheduler)
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--250 TJm
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--250 TJm
-(state:)
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--426 TJm
-(info)
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--426 TJm
-(threads)
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-(4)
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--426 TJm
-(Thread)
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--426 TJm
-(6239)
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--426 TJm
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--426 TJm
-(4)
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--426 TJm
-(VgTs_Yielding\))
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--852 TJm
-(0x001f2832)
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--426 TJm
-(in)
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--426 TJm
-(_dl_sysinfo_int80)
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--426 TJm
-(\(\))
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--426 TJm
-(from)
-[5.97756
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--426 TJm
-(/lib/ld-linux.so.2)
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-(*)
-[5.97756
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-82.222 468.642 Td
-(3)
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--426 TJm
-(Thread)
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--426 TJm
-(6238)
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--426 TJm
-(\(tid)
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--426 TJm
-(3)
-[5.97756
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--426 TJm
-(VgTs_Runnable\))
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--852 TJm
-(make_error)
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--426 TJm
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--426 TJm
-("called)
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--426 TJm
-(from)
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--426 TJm
-(at)
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--426 TJm
-(prog.c:20)
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-(2)
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--426 TJm
-(Thread)
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--426 TJm
-(6237)
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--426 TJm
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--426 TJm
-(2)
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--426 TJm
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--852 TJm
-(0x001f2832)
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--426 TJm
-(in)
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--426 TJm
-(_dl_sysinfo_int80)
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--426 TJm
-(\(\))
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--426 TJm
-(from)
-[5.97756
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--426 TJm
-(/lib/ld-linux.so.2)
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-(1)
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--426 TJm
-(Thread)
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--426 TJm
-(6234)
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--426 TJm
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--426 TJm
-(1)
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--426 TJm
-(VgTs_Yielding\))
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--852 TJm
-(main)
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--426 TJm
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--426 TJm
-(argv=0xbedcc274\))
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-0] Tj
--426 TJm
-(at)
-[5.97756
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--426 TJm
-(prog.c:105)
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--278 TJm
-(Examining)
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--278 TJm
-(and)
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--278 TJm
-(modifying)
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--278 TJm
-(V)
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-(algrind)
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--278 TJm
-(shado)
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-15 TJm
-(w)
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--403 TJm
-(the)
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--403 TJm
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-(is)
-[2.769603
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--403 TJm
-(gi)
-[4.9813
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-25 TJm
-(v)
-[4.9813
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-15 TJm
-(en,)
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--442 TJm
-(the)
-[2.769603
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--403 TJm
-(V)
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-(algrind)
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-4.9813
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-2.769603
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-(pro)
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[4.9813
0
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3.317546
0
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-15 TJm
-(vides)
-[4.9813
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2.769603
0
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4.423394
0
3.875451
0] Tj
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-(support)
-[3.875451
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-3.317546
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-(for)
-[3.317546
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-(it.)
-[2.769603
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-2.769603
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-2.49065
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-2.769603
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-65 TJm
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-[4.9813
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-(Memcheck)
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-(pro)
-[4.9813
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-3.317546
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-[4.9813
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-4.9813
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-4.423394
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-3.875451
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-[4.9813
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-[4.423394
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-[7.192997
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-(atchpoint)
-[4.423394
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-(simulati)
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-[4.9813
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-[6.087149
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-[4.9813
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-3.317546
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-4.9813
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-(are)
-[4.423394
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-[7.192997
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-(pro)
-[4.9813
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-15 TJm
-(vided)
-[4.9813
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-4.423394
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-(by)
-[4.9813
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-(Memcheck)
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-[2.769603
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-(f)
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-[4.423394
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-(that)
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-[4.9813
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-(by)
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(V)
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-(ugged.)
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-(Such)
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-(are)
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-(named)
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-(in)
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-(GDB)
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-(.)
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-(A)
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-(of)
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-(an)
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-(is)
-[2.769603
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-(to)
-[2.769603
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-(e)
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-(x)
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-(ecute)
-[4.423394
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-(a)
-[4.423394
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-(that)
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-(prints)
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-(a)
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--230 TJm
-(v)
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-(ersion)
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-[4.9813
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-(a)
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-0
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-(data)
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--801 TJm
-(T)
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-(o)
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-(GDB)
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--281 TJm
-(to)
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-(call)
-[4.423394
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(and)
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0] Tj
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-(ar)
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-(As)
-[7.192997
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-(an)
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15 TJm
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0
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2.769603
0
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-(the)
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-(follo)
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-(wing)
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0
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-(an)
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0
3.317546
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-(libc)
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-(p)
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-4.423394
-0
-3.317546
-0
-2.769603
-0
-4.9813
-0
-3.317546
-0] Tj
--334 TJm
-(call.)
-[4.423394
-0
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-0
-2.769603
-0
-2.769603
-0
-2.49065
-0] Tj
--1122 TJm
-(If)
-[3.317546
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--333 TJm
-(another)
-[4.423394
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-0
-4.423394
-0
-3.317546
-0] Tj
--334 TJm
-(thread)
-[2.769603
-0
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-0
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-0
-4.423394
-0
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-0
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--334 TJm
-(reports)
-[3.317546
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-0
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-0
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-0
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-0
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--334 TJm
-(an)
-[4.423394
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-0] Tj
--333 TJm
-(error)
-[4.423394
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-0
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-0
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-0
-3.317546
-0] Tj
--334 TJm
-(or)
-[4.9813
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--334 TJm
-(encounters)
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-0
-3.317546
-0
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--333 TJm
-(a)
-[4.423394
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--334 TJm
-(breakpoint,)
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-0
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-0
-2.49065
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--355 TJm
-(the)
-[2.769603
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--333 TJm
-(e)
-[4.423394
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-25 TJm
-(v)
-[4.9813
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-25 TJm
-(aluation)
-[4.423394
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-2.769603
-0
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-0
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-0
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--334 TJm
-(of)
-[4.9813
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--334 TJm
-(the)
-[2.769603
-0
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-0
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--333 TJm
-(inferior)
-[2.769603
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-4.423394
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-0
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--334 TJm
-(call)
-[4.423394
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-0
-2.769603
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--334 TJm
-(is)
-[2.769603
-0
-3.875451
-0] Tj
-81.963 203.935 Td
-(abandoned.)
-[4.423394
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-0
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-0
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-/DeviceRGB {} cs
-[0 0 0] sc
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-/DeviceRGB {} cs
-[0 0 0] sc
-/DeviceRGB {} CS
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-81.963 182.017 Td
-(Note)
-[7.192997
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-0
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-0
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-0] Tj
--281 TJm
-(that)
-[2.769603
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-0
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-0
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--281 TJm
-(inferior)
-[2.769603
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-0
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-0
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-0
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--281 TJm
-(function)
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-0
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-0
-2.769603
-0
-2.769603
-0
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-0
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-0] Tj
--281 TJm
-(calls)
-[4.423394
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-0
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-0
-2.769603
-0
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--281 TJm
-(are)
-[4.423394
-0
-3.317546
-0
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--281 TJm
-(a)
-[4.423394
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--281 TJm
-(po)
-[4.9813
-0
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-25 TJm
-(werful)
-[7.192997
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-0
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-0
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-0
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-0
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--281 TJm
-(GDB)
-[7.192997
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-6.645054
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--281 TJm
-(feature,)
-[3.317546
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-0
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-0
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-0
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--288 TJm
-(b)
-[4.9813
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-20 TJm
-(ut)
-[4.9813
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--281 TJm
-(should)
-[3.875451
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-0
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-0
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--281 TJm
+-250 TJm
(be)
[4.9813
0
4.423394
0] Tj
--281 TJm
-(used)
-[4.9813
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--281 TJm
-(with)
-[7.192997
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-0
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-0
-4.9813
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--281 TJm
-(caution.)
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--403 TJm
-(F)
-[5.539206
0] Tj
15 TJm
+(xamined)
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+-250 TJm
(or)
[4.9813
0
3.317546
0] Tj
--281 TJm
-(e)
-[4.423394
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-15 TJm
-(xample,)
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--289 TJm
-(if)
-[2.769603
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--281 TJm
-(the)
-[2.769603
-0
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-0
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-81.963 170.062 Td
-(program)
-[4.9813
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-0
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-3.317546
-0
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--249 TJm
-(being)
-[4.9813
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-0
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-0
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--248 TJm
-(deb)
-[4.9813
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-0
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-20 TJm
-(ugged)
-[4.9813
-0
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-0
-4.9813
-0
-4.423394
-0
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--249 TJm
-(is)
-[2.769603
-0
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-0] Tj
--249 TJm
-(stopped)
-[3.875451
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-0
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-0
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-0
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--249 TJm
-(inside)
-[2.769603
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--248 TJm
-(the)
-[2.769603
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--249 TJm
-(function)
-[3.317546
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--249 TJm
-("printf",)
-[4.064741
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--249 TJm
-(forcing)
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-0
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-0
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--249 TJm
-(a)
-[4.423394
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--248 TJm
-(recursi)
-[3.317546
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-25 TJm
-(v)
-[4.9813
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-15 TJm
-(e)
-[4.423394
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--249 TJm
-(call)
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--249 TJm
-(to)
-[2.769603
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-0] Tj
--249 TJm
-(printf)
-[4.9813
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-0
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-0
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-0
-2.769603
-0
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--248 TJm
-(via)
-[4.9813
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-0
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--249 TJm
-(an)
-[4.423394
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--249 TJm
-(inferior)
-[2.769603
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-3.317546
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-0
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--249 TJm
-(call)
-[4.423394
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-0
-2.769603
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-81.963 158.107 Td
-(will)
-[7.192997
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-2.769603
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-2.769603
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--254 TJm
-(v)
-[4.9813
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-15 TJm
-(ery)
-[4.423394
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--255 TJm
-(probably)
-[4.9813
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-0
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-0
-4.423394
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-0
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--254 TJm
-(create)
-[4.423394
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-0
-2.769603
-0
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--255 TJm
-(problems.)
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-0
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-0
-2.769603
-0
-4.423394
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-0
-3.875451
-0
-2.49065
-0] Tj
--647 TJm
-(The)
-[6.087149
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--254 TJm
-(V)
-[7.192997
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-111 TJm
-(algrind)
-[4.423394
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--255 TJm
-(tool)
-[2.769603
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--254 TJm
-(might)
+-250 TJm
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[7.750903
0
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--255 TJm
-(also)
-[4.423394
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--254 TJm
-(add)
-[4.423394
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-0
-4.9813
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--255 TJm
-(another)
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0
4.9813
0
2.769603
0
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0
4.423394
0
-3.317546
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--254 TJm
-(le)
-[2.769603
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-25 TJm
-(v)
-[4.9813
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-15 TJm
-(el)
-[4.423394
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--255 TJm
-(of)
-[4.9813
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--254 TJm
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-15 TJm
-(xity)
-[4.9813
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--255 TJm
-(to)
-[2.769603
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--254 TJm
-(inferior)
-[2.769603
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--255 TJm
-(calls,)
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-(e.g.)
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0
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+/DeviceRGB {} CS
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+76.483 96.01 Td
+(\225)
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+/DeviceRGB {} cs
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+(Signal)
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0
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-250 TJm
-(reporting)
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4.9813
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@@ -413939,148 +426074,80 @@
4.9813
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-250 TJm
-(tool)
-[2.769603
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-(during)
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-(the)
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0
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--250 TJm
-(call)
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-(or)
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-(due)
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4.9813
0
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-(to)
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0
4.9813
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-(to)
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-(a)
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--250 TJm
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-[2.769603
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-[2.769603
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-(in)
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(be)
[4.9813
0
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[4.9813
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-[4.9813
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-(so)
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-(a)
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-(As)
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-(as)
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-(GDB)
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0
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0
4.9813
0
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0
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0
3.317546
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--205 TJm
-(unwind)
-[4.9813
0
4.9813
0
7.192997
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0
4.9813
0] Tj
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[4.9813
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3.317546
0
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0
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0] Tj
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(the)
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0
4.423394
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(address)
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0
3.875451
0] Tj
--205 TJm
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(range)
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0
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0] Tj
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-([addr)
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[3.317546
0
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0
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-(,)
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--214 TJm
-(addr+len-)
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4.423394
0
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-(1].)
-[4.9813
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--310 TJm
-(The)
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-(def)
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2.769603
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--250 TJm
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-(alue)
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0] Tj
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(of)
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3.317546
0] Tj
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(is)
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3.875451
0] Tj
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-(1,)
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--250 TJm
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-25 TJm
-(ving)
-[4.9813
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-0
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--250 TJm
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0
4.423394
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--250 TJm
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4.9813
0] Tj
--250 TJm
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0
3.317546
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0] Tj
--250 TJm
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(the)
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--620 TJm
-(An)
-[7.192997
-0
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-15 TJm
-(y)
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-0
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-0
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-0
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-(of)
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-(functions)
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-0
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-0
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-0
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-(may)
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-0
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-0
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-0
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-0
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-0
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-[0 0 0] sc
-/DeviceRGB {} CS
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-/DeviceRGB {} cs
-[0 0 0] sc
-/DeviceRGB {} CS
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-(Function)
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-(s)
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+-231 TJm
(in)
[2.769603
0
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0] Tj
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0
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0
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0] Tj
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0] Tj
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0
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@@ -454740,17 +461907,497 @@
(.)
[2.49065
0] Tj
--1387 TJm
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0] Tj
-15 TJm
-(or)
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[4.9813
0
3.317546
0] Tj
--378 TJm
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+-229 TJm
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+0
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+80 TJm
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+0
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+0
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+0
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+0
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+0
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+-316 TJm
(e)
[4.423394
0] Tj
@@ -454770,154 +462417,82 @@
0
2.49065
0] Tj
--409 TJm
-(Helgrind)
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0
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-0
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-0
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-0
-3.317546
-0
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-0
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-0
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0] Tj
--378 TJm
-(wraps)
-[7.192997
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-0
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-0
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-0
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--378 TJm
-(functions)
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0
4.9813
0
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-0
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-0
2.769603
0
2.769603
0
4.9813
-0
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-0
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--378 TJm
-(in)
-[2.769603
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-72 107.865 Td
-(the)
-[2.769603
-0
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-0
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--339 TJm
-(POSIX)
-[5.539206
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-0
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-0
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-0
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--339 TJm
-(pthreads)
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-0
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-0
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-0
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-0
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-0
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-0
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--340 TJm
-(API)
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-0
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--339 TJm
-(so)
-[3.875451
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--339 TJm
-(it)
-[2.769603
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--339 TJm
-(can)
-[4.423394
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-0
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--340 TJm
-(kno)
-[4.9813
-0
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-0
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0] Tj
25 TJm
-(w)
+(wing)
[7.192997
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+0
+4.9813
+0
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0] Tj
--339 TJm
-(about)
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+(GDB)
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+0
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0
4.9813
0
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+0
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+0
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0
4.9813
0
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0] Tj
--339 TJm
-(thread)
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+0
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+-315 TJm
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0
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@@ -454926,127 +462501,31 @@
0
4.423394
0
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--339 TJm
-(status)
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0
2.769603
0
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--340 TJm
-(changes,)
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--361 TJm
-(and)
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--340 TJm
-(the)
-[2.769603
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--339 TJm
-(core)
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4.9813
0
3.317546
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0] Tj
--339 TJm
-(is)
-[2.769603
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--339 TJm
-(able)
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[4.423394
0
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0
2.769603
0
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0] Tj
--340 TJm
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(to)
[2.769603
0
4.9813
0] Tj
--339 TJm
-(wrap)
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--339 TJm
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--339 TJm
-(in)
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--340 TJm
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(the)
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0
@@ -455054,254 +462533,42 @@
0
4.423394
0] Tj
-72 95.91 Td
-(MPI)
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0
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0
3.317546
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+0
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0] Tj
--383 TJm
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0
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4.9813
0
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0
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--383 TJm
-(API)
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--383 TJm
-(so)
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-(it)
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--383 TJm
-(can)
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-(of)
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-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(call)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(an)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(original)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(of)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(type)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--852 TJm
-(void)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(fn)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(\()
-[5.97756
-0] Tj
--426 TJm
-(void)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(\))
-[5.97756
-0] Tj
-72 386.345 Td
-(CALL_FN_W_v)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--1704 TJm
-(--)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(call)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(an)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(original)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(of)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(type)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--852 TJm
-(long)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(fn)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(\()
-[5.97756
-0] Tj
--426 TJm
-(void)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(\))
-[5.97756
-0] Tj
-72 362.434 Td
-(CALL_FN_v_W)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--1704 TJm
-(--)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(call)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(an)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(original)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(of)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(type)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--852 TJm
-(void)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(fn)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(\()
-[5.97756
-0] Tj
--426 TJm
-(long)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(\))
-[5.97756
-0] Tj
-72 350.479 Td
-(CALL_FN_W_W)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--1704 TJm
-(--)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(call)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(an)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(original)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(of)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(type)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--852 TJm
-(long)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(fn)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(\()
-[5.97756
-0] Tj
--426 TJm
-(long)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(\))
-[5.97756
-0] Tj
-72 326.569 Td
-(CALL_FN_v_WW)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--1278 TJm
-(--)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(call)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(an)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(original)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(of)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(type)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--852 TJm
-(void)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(fn)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(\()
-[5.97756
-0] Tj
--426 TJm
-(long,)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(long)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(\))
-[5.97756
-0] Tj
-72 314.614 Td
-(CALL_FN_W_WW)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--1278 TJm
-(--)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(call)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(an)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(original)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(of)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(type)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--852 TJm
-(long)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(fn)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(\()
-[5.97756
-0] Tj
--426 TJm
-(long,)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(long)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(\))
-[5.97756
-0] Tj
-72 290.703 Td
-(CALL_FN_v_WWW)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--852 TJm
-(--)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(call)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(an)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(original)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(of)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(type)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--852 TJm
-(void)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(fn)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(\()
-[5.97756
-0] Tj
--426 TJm
-(long,)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(long,)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(long)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(\))
-[5.97756
-0] Tj
-72 278.748 Td
-(CALL_FN_W_WWW)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--852 TJm
-(--)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(call)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(an)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(original)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(of)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(type)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--852 TJm
-(long)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(fn)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(\()
-[5.97756
-0] Tj
--426 TJm
-(long,)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(long,)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(long)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(\))
-[5.97756
-0] Tj
-72 254.838 Td
-(CALL_FN_W_WWWW)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(--)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(call)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(an)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(original)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(of)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(type)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--852 TJm
-(long)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(fn)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(\()
-[5.97756
-0] Tj
--426 TJm
-(long,)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(long,)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(long,)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(long)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(\))
-[5.97756
-0] Tj
-72 242.883 Td
-(CALL_FN_W_5W)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--1278 TJm
-(--)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(call)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(an)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(original)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(of)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(type)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--852 TJm
-(long)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(fn)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(\()
-[5.97756
-0] Tj
--426 TJm
-(long,)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(long,)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(long,)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(long,)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(long)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(\))
-[5.97756
-0] Tj
-72 218.972 Td
-(CALL_FN_W_6W)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--1278 TJm
-(--)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(call)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(an)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(original)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(of)
-[5.97756
-0
-5.97756
-0] Tj
--426 TJm
-(type)
-[5.97756
-0
-5.97756
-0
-5.97756
-0
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diff --git a/docs/internals/3_11_BUGSTATUS.txt b/docs/internals/3_11_BUGSTATUS.txt
index d27e471..68e4042 100644
--- a/docs/internals/3_11_BUGSTATUS.txt
+++ b/docs/internals/3_11_BUGSTATUS.txt
@@ -298,6 +298,8 @@
Wed 19 Oct 17:07:42 CEST 2016
+344139 x86 stack-seg overrides, needed by the Wine people
+
========================================================================
========================================================================
@@ -426,7 +428,10 @@
16080 -> 16089 mips: fix coredump creation in Valgrind
16081 -> 16090 Add another incompatibility between illumos and Solaris kernels.
-(tracked up to and including 16090/3282)
+16095 (B) -> 16099 (T) Build fixes for MacOS X 10.10.5.
+
+(tracked up to and including 16098/3282)
+3.12.0 final is 16098/3282.
========================================================================
========================================================================
diff --git a/docs/internals/3_12_BUGSTATUS.txt b/docs/internals/3_12_BUGSTATUS.txt
new file mode 100644
index 0000000..4aa1cc2
--- /dev/null
+++ b/docs/internals/3_12_BUGSTATUS.txt
@@ -0,0 +1,521 @@
+
+Created Mon 21 Nov 12:58:23 CET 2016. All bugs after the release of
+3.12.0 go in here. Also, this contains bugs from 3_11_BUGSTATUS.txt
+that didn't get fixed in 3.12. These are marked "(carried over)".
+
+=== VEX/amd64 ==========================================================
+
+(carried over)
+356715 vex amd64->IR: 0xC4 0xE2 0x7D 0x13 0x4 0x4A 0xC5 0xFC
+ vcvtph2ps (%rdx,%rcx,2),%ymm0
+
+369409 vex amd64->IR: 0x48 0xF 0xC7 0xF0 0x72 0x2 0xE2 0xF8 (
+
+372828 vex amd64->IR: 0x66 0x4D 0xF 0x38 0xF6 0xD2 0x66 0x4D
+
+373166 vex amd64->IR: 0xFF 0xFF 0x48 0x85 0xC0 0x74 0x8 0x4D 0x89 0xE7
+ [not clear what's going on here]
+
+AMD XOP-prefixed insns:
+
+(carried over)
+356611 vex amd64->IR: 0x8F 0xEA 0xF8 0x10 0xC9 0x3 0x1D 0x0
+ [== 328357, still open]
+
+(carried over)
+339596 AMD64 xop instructions unsupported.
+ vex amd64->IR: 0x8F 0xE8 0x78 0xCD 0xC1 0x4 0xC5 0xF9
+ [has patch, could possibly take it, but needs
+ cleanup/verification with Mark]
+ == 356138
+
+369053 AMD64 fma4 instructions missing 256 bit support
+
+375008 amd64->IR: 0x8F 0x6A 0x78 0x10 0xD8 0x4 0x4 0x0 0x0 0x8F
+
+=== VEX/arm ============================================================
+
+(carried over)
+352630 valgrind: Unrecognised instruction at address 0x4fc4d33.
+ [what insn is this?]
+
+(carried over)
+355526 disInstr(arm): unhandled instruction: 0x1823E91
+ [what insn is this?]
+
+(carried over)
+n-i-bz Remove limit on strd's negative immediates
+ [dev@, Michael Daniels, 19 Nov 2015, easy fix, should land]
+
+373990 Potential shift left overflow in guest_arm_toIR.c
+
+369509 ARMv8.1 LSE instructions are not supported
+
+369723 __builtin_longjmp not supported in clang/llvm on Android arm64 target
+ [has patch at android-review.googlesource.com]
+
+373990 Potential shift left overflow in guest_arm_toIR.c
+ [suggested fix available]
+
+378249 Valgrind Crashed on raspberian armv71 instrtuction set
+
+=== VEX/arm64 ==========================================================
+
+369509 ARMv8.1 LSE instructions are not supported
+
+377966 disInstr(arm64): unhandled instruction 0xD50B7425
+
+=== VEX/x86 ============================================================
+
+=== VEX/mips ===========================================================
+
+=== VEX/ppc ============================================================
+
+(carried over)
+361405 disInstr(ppc): unhandled instruction: 0xFF81010C
+
+=== VEX/s390x ==========================================================
+
+(carried over)
+366413 s390x: New z13 instructions not implemented
+ [Per cborntraeger, is not important for 3.12.0]
+
+=== VEX general ========================================================
+
+=== Syscalls/ioctls on Linux ===========================================
+
+(carried over)
+352742 Custom allocator using sbrk() fails after about 800MB when running
+ under memcheck
+
+(carried over)
+355803 Add Lustre's IOC_MDC_GETFILESTRIPE ioctl [has patch]
+
+(carried over)
+357781 unhandled amd64-linux syscall: 317
+ [== 345414, still open]
+
+(carried over)
+359705 memcheck causes segfault on a dynamically-linked test from
+ rustlang's test suite on i686
+
+(carried over)
+361726 WARNING:unhandled syscall on ppc64
+
+(carried over)
+361770 Missing F_ADD_SEALS
+
+(carried over)
+362892 test apk in android5.0.2,after fix the bug 344802,android log
+ "Unable to create protected region in stack for implicit overflow
+ check. Reason: Out of memory size: 4096"
+ [the patch looks bogus, more info requested]
+
+(carried over)
+362939 test apk in android 5.0 or most,at 0x6A23AB4:
+ art::Thread::InstallImplicitProtection() (in /system/lib/libart.so)
+ [initimg problems on Android]
+
+(carried over)
+364359 Valgrind crashes on fcntl(F_SETFL, O_NONBLOCK, fd)
+ [fcntl(F_SETFL) is supported, perhaps stale bug]
+
+(carried over)
+368791 unhandled syscall: 167 (swapon, amd64-linux)
+ (should fix this for 3.12.1)
+
+368866 WARNING: unhandled arm64-linux syscall: 238 (migrate_pages)
+368913 WARNING: unhandled arm64-linux syscall: 117
+368914 WARNING: unhandled arm64-linux syscall: 142
+368916 WARNING: unhandled arm64-linux syscall: 234
+368919 WARNING: unhandled arm64-linux syscall: 274
+368920 WARNING: unhandled arm64-linux syscall: 275
+368921 WARNING: unhandled arm64-linux syscall: 162
+368923 WARNING: unhandled arm64-linux syscall: 268
+
+368960 WARNING: unhandled amd64-linux syscall: 163
+369026 WARNING: unhandled amd64-linux syscall: 169
+369027 WARNING: unhandled amd64-linux syscall: 216 (remap_file_pages)
+369028 WARNING: unhandled amd64-linux syscall: 314 (sched_setattr)
+369029 WARNING: unhandled amd64-linux syscall: 315 (sched_getattr)
+369030 WARNING: unhandled amd64-linux syscall: 171 (setdomainname)
+369031 WARNING: unhandled amd64-linux syscall: 308 (setns)
+369032 WARNING: unhandled amd64-linux syscall: 205 (set_thread_area)
+369033 WARNING: unhandled amd64-linux syscall: 139 (sysfs)
+369034 WARNING: unhandled amd64-linux syscall: 136 (ustat)
+
+371411 Unify fstat64/fstatat64 wrappers
+ [legit check needed]
+
+372513 WARNING: unhandled ppc64be-linux syscall: utimes(251)
+
+372861 Test pselect_alarm for Bug 359871 seg faults on RHEL 4
+ [has a suggested solution]
+
+378892 Unhandled amd64-linux syscall: 324
+
+=== Syscalls/ioctls on OSX =============================================
+
+(carried over)
+351632 UNKNOWN fcntl 97 on OS X 10.11
+
+(carried over)
+352021 Signals are ignored in OS X 10.10
+
+(carried over)
+353346 WARNING: unhandled amd64-darwin syscall: unix:330
+ == 211362 [not fixed]
+
+376870 unhandled amd64-darwin syscall: unix:446 (proc_rlimit_control)
+
+=== Debuginfo reader ===================================================
+
+(carried over)
+353192 Debug info/data section not detected on AMD64
+ [To do with rwx, combined code+data sections]
+
+(carried over)
+355197 Too strong assert in variable debug info code
+ [Still relevant?]
+
+(carried over)
+365750 Valgrind fails on binary with .text section not in default place
+ [Horrible hack to do with relocating .text section]
+
+372182 Support more languages/demangling styles than just C++ (and Rust)
+
+=== Tools/Memcheck =====================================================
+
+(carried over)
+352364 ppc64: --expensive-definedness-checks=yes is not quite working here
+
+(carried over)
+353282 False uninitialised memory after bittwiddling
+
+(carried over)
+358980 32 byte leak reported when code uses dlopen and links against pthread
+ [native program crashes as well]
+
+(carried over)
+361504 dlopen()/dlclose() and shared object usage check
+ [wishlist]
+
+(carried over)
+361810 valgrind duplicate stdin after fork
+ [supposedly a bug in glibc when __libc_freeres should not be run]
+
+(carried over)
+364279 False "Uninitialized" on atomic_compare_exchange
+
+(carried over)
+366035 valgrind misses buffer overflow, segfaults in malloc in localtime
+
+(carried over)
+366817 VALGRIND_MEMPOOL_CHANGE has a performance bug
+
+371989 PCMPISTRM $0x72 validity bit propagation is imprecise
+
+369854 Valgrind reports an Invalid Read in __intel_new_memcpy
+ Should be handled by --partial-loads-ok=yes
+
+371966 No uninitialised values reported with PGI -Mstack_arrays
+
+375415 free list of blocks, mempool blocks and describe addr
+ do not work properly together
+
+371770 Memleak trace back for overwritten or freed memory pointers
+ [wishlist]
+
+377463 Uninitialized parameters to VALGRIND_MAKE_MEM_NOACCESS() not warned
+ about. [wishlist]
+
+378622 False positive with GCC 6.3.1 and -funswitch-loops (-O3)
+
+378627 False positive with GCC 6.3.1 and -fno-ipa-cp-clone (-O3)
+
+=== Tools/DRD ==========================================================
+
+(carried over)
+356374 Assertion 'DRD_(g_threadinfo)[tid].pt_threadid
+ != INVALID_POSIX_THREADID' failed
+
+=== Tools/Helgrind =====================================================
+
+(carried over)
+360557 helgrind reports data race which I can't see (involves rwlocks)
+ [probably a legit bug]
+
+(carried over)
+363740 Possible data race in vgPlain_amd64_linux_REDIR_FOR_vgettimeofday
+
+371396 helgrind and drd pth_cond_destroy_busy testcase hang with
+ new glibc cond var implementation (workaround committed as 16097)
+
+376257 helgrind history full speed up using a cached stack
+
+=== Tools/SGCheck ======================================================
+
+=== Tools/Massif =======================================================
+
+=== Tools/Cachegrind ===================================================
+
+=== Tools/Callgrind ====================================================
+
+369456 callgrind_control failed to find an active callgrind run.
+ OSX specific
+
+=== Tools/Lackey =======================================================
+
+=== other/amd64 ========================================================
+
+375171 VG_(scheduler): run_innerloop detected host state invariant failure
+ == 374482
+ == 374850
+
+=== other/x86 ==========================================================
+
+=== other/ppc ==========================================================
+
+365208 valgrind stuck after redirecting "memcpy"
+
+=== other/arm ==========================================================
+
+(carried over)
+356675 callgrind test apk in android 5.0.2
+ [Unclear what this is.]
+
+(carried over)
+364533 Process terminating with default action of signal 4 (SIGILL): dumping
+ core, : at 0x4000E7C: ??? (in /lib/ld-uClibc.so.0)
+
+374814 VALGRIND INTERNAL ERROR: signal 11 (SIGSEGV) - exiting
+ possibly TLS related
+
+=== other/arm64 ========================================================
+
+369723 __builtin_longjmp not supported in clang/llvm on Android arm64 target
+ Has patch
+
+371439 Get coredump working on arm64
+ [has an incomplete patch]
+
+=== other/mips =========================================================
+
+=== other/s390 =========================================================
+
+=== other/Android ======================================================
+
+374814 VALGRIND INTERNAL ERROR: signal 11 (SIGSEGV) - exiting
+
+=== other/OS X =========================================================
+
+(carried over)
+351855 Possible false positive on OS X with setlocale
+
+(carried over)
+352384 mmap-FIXED failed in UME (load_segment2)
+
+(carried over)
+352567 Assertion tres.status == VexTransOK failed in m_translate.c
+ vgPlain_translate
+
+(carried over)
+353470 memcheck/tests/execve2 fails on OS X 10.11
+
+(carried over)
+353471 memcheck/tests/x86/xor-undef-x86 fails on OS X 10.11
+
+(carried over)
+354428 Bad report memory leak in OS X 10.11
+ == 258140 [still open]
+
+(carried over)
+356122 Apparent infinite loop calling GLib g_get_user_special_dir() function
+
+(carried over)
+359264 Memcheck shows 2,064 bytes possibly lost and 20,036 suppressed bytes
+ in simplistic program on OS X El Capitan
+
+(carried over)
+363123 SIGSEGV on Mac OS with very simple threaded code
+ == 349128 [still open]
+
+(carried over)
+365327 Support macOS Sierra (10.12)
+
+(carried over)
+366131 Illegal opcode in OS X 11.0 when using function getpwuid()
+
+372772 Brew doesn't allow for Valgrind 3.12.0 installation on Sierra OSX
+ == 365327
+
+372779 valgrind will hang
+
+376870 The impossible happened on Mavericks 10.9
+
+379373 Syscall param msg->desc.port.name points to uninitialised byte(s)
+ on macOS 10.12
+
+=== other/Win32 ========================================================
+
+=== other/*BSD =========================================================
+
+368873 Please add FreeBSD to supported OS list
+
+=== GDB server =========================================================
+
+(carried over)
+351792 vgdb doesn't support remote file transfers
+ [wishlist]
+
+(carried over)
+356174 Enhance the embedded gdbserver to allow LLDB to use it
+
+=== Output =============================================================
+
+(carried over)
+351857 confusing error message about valid command line option
+
+(carried over)
+358569 Unhandled instructions cause creation of "orphan" stack traces
+ in XML output
+
+374719 some spelling fixes
+
+=== MPI ================================================================
+
+=== Documentation ======================================================
+
+368873 Please add FreeBSD to supported OS list
+
+=== Uncategorised/run ==================================================
+
+(carried over)
+359249 valgrind unable to load 64-bit linux executable
+ linked with -mcmodel=medium
+
+(carried over)
+362680 --error-exitcode not honored when file descriptor leaks are found
+
+377006 valgrind/memcheck segfaults under certain kernel versions (amd64)
+ but not others.
+
+379273 Phone restarts when run with valgrind
+
+=== Uncategorised/build ================================================
+
+(carried over)
+359920 Configure fails with relative DESTDIR
+
+(carried over)
+362033 undeclared identifier build failures for getpid(), usleep(),
+ and getuid() [Valkyrie]
+
+(carried over)
+366345 Dirty compile from m_libcbase.c and vgdb-invoker-ptrace.c
+
+379502 Checking the code of Valgrind dynamic analyzer by a static analyzer
+
+379537 Client requests can't be used in C++11 constexpr functions
+
+=== Intel Compiler problems ============================================
+
+(carried over)
+357010 drd regression tests fail to compile with Intel compiler
+
+(carried over)
+357011 Memcheck regression tests do not generate expected frame numbers
+ if compiled with intel compiler
+ [asked for rebased patch]
+
+(carried over)
+357012 Memcheck regression tests do not match expected results
+ if compiled with intel compiler
+
+(carried over)
+357014 Helgrind regression tests do not match expected results
+ if compiled with intel compiler
+
+========================================================================
+========================================================================
+========================================================================
+========================================================================
+========================================================================
+
+Wed 10 May 10:24:16 CEST 2017
+
+========================================================================
+========================================================================
+========================================================================
+
+Should fix for 3.13:
+** = higher priority, do these first
+* = lower priority, do these if time available
+
+**
+n-i-bz major perf problems w/ stack registration + stack recycling
+Should be fixed. Try again with ./mach gtest
+
+*
+371989 PCMPISTRM $0x72 validity bit propagation is imprecise
+(at least comment on it)
+
+*
+322935 disInstr(arm): unhandled instruction: 0xF1010200, valgrind:
+ Unrecognised instruction on Raspbian
+ [should document that Raspian is not supported]
+
+*
+(carried over)
+353192 Debug info/data section not detected on AMD64
+ [To do with rwx, combined code+data sections]
+
+*
+(carried over)
+358980 32 byte leak reported when code uses dlopen and links against pthread
+
+*
+(carried over)
+364279 False "Uninitialized" on atomic_compare_exchange
+
+*
+368791 unhandled syscall: 167 (swapon, amd64-linux)
+ [hoist mips64-linux specific wrapper as a linux specific one]
+
+*
+369723 __builtin_longjmp not supported in clang/llvm on Android arm64 target
+ [has patch at android-review.googlesource.com]
+
+*
+369854 Valgrind reports an Invalid Read in __intel_new_memcpy
+ Should be handled by --partial-loads-ok=yes
+
+*
+371396 helgrind and drd pth_cond_destroy_busy testcase hang with
+ new glibc cond var implementation (workaround committed as 16097)
+
+*
+373990 Potential shift left overflow in guest_arm_toIR.c
+ [suggested fix available]
+
+*
+377966 disInstr(arm64): unhandled instruction 0xD50B7425
+
+*
+378622 False positive with GCC 6.3.1 and -funswitch-loops (-O3)
+
+*
+378627 False positive with GCC 6.3.1 and -fno-ipa-cp-clone (-O3)
+
+*
+378892 Unhandled amd64-linux syscall: 324
+
+*
+n-i-bz Remove limit on strd's negative immediates
+ [dev@, Michael Daniels, 19 Nov 2015, easy fix, should land]
+
+--------------------
+
+========================================================================
+========================================================================
+
diff --git a/docs/internals/Darwin-notes.txt b/docs/internals/Darwin-notes.txt
index 85c9e8e..8c320a3 100644
--- a/docs/internals/Darwin-notes.txt
+++ b/docs/internals/Darwin-notes.txt
@@ -39,7 +39,7 @@
using native Darwin semaphores.
Because the pipe-based semaphore intensively uses sys_read/sys_write,
-it is not surprising that it inadvertantly was eating up cancellation
+it is not surprising that it inadvertently was eating up cancellation
requests directed to client threads. With abovementioned change in
force the pipe-based semaphore appears to work correctly.
diff --git a/docs/internals/arm_thumb_notes_gdbserver.txt b/docs/internals/arm_thumb_notes_gdbserver.txt
index fc40284..56ac682 100644
--- a/docs/internals/arm_thumb_notes_gdbserver.txt
+++ b/docs/internals/arm_thumb_notes_gdbserver.txt
@@ -45,8 +45,8 @@
instruction must be discarded to have the SB re-instrumented for gdbserver.
At least at this moment (r2155/r11786), the extents for ARM/thumb blocks
contains addresses with the thumb bit set. It is not clear that this is
- a good thing: extents should preferrably reference the real address range of
- instructions, not an adress range which can be "off by one" due to the
+ a good thing: extents should preferably reference the real address range of
+ instructions, not an address range which can be "off by one" due to the
fact that the instruction is a thumb instruction.
Due to this "off by one", gdbserver is discarding a range of two bytes
@@ -77,7 +77,7 @@
* use the debug info : this solution was discarded as often debug
info does not allow a 100% correct solution. debug info is acceptable
for vg.translate (which is only for internal valgrind debugging),
- but is better not used for 'end user functionnality'.
+ but is better not used for 'end user functionality'.
* Derive the thumb bit for a SB from the extent address.
This was discarded as this implies that an SB cannot mix thumb
and ARM code. This implied to disable chasing at transition between
diff --git a/docs/internals/multiple-architectures.txt b/docs/internals/multiple-architectures.txt
index fee423f..b0ddcfa 100644
--- a/docs/internals/multiple-architectures.txt
+++ b/docs/internals/multiple-architectures.txt
@@ -129,7 +129,7 @@
* the launcher, valgrind.c
* all the architecture-independent regression tests
* the performance tests
-* optionally, auxilary programs like hp2ps and valgrind-listener
+* optionally, auxiliary programs like hp2ps and valgrind-listener
In order to do that, we need to know what flags to use to build for
the primary target, and in particular whether to hand -m32 or -m64 to
@@ -148,7 +148,7 @@
This leads to the final complication: building the regression tests.
Most of them are architecture-neutral and so should be built for the
primary target. The /test/ Makefile.am's duly include
-AM_FLAG_M3264_PRI in the compilation invokations, and you should
+AM_FLAG_M3264_PRI in the compilation invocations, and you should
ensure you preserve that when adding more tests.
However, there are some arch-specific test directories (eg,
diff --git a/docs/internals/notes.txt b/docs/internals/notes.txt
index e15966f..5c7e7bc 100644
--- a/docs/internals/notes.txt
+++ b/docs/internals/notes.txt
@@ -127,7 +127,7 @@
Redirection mechanism
~~~~~~~~~~~~~~~~~~~~~
How this works is difficult to understand. This should be fixed. The
-list of unresolved redirections should be a seperate data structure
+list of unresolved redirections should be a separate data structure
from the currently active (addr, addr) mapping.
There's a whole big #ifdef TEST section in vg_symtab2.c which has
diff --git a/docs/internals/register-uses.txt b/docs/internals/register-uses.txt
index f26ccca..f6693b4 100644
--- a/docs/internals/register-uses.txt
+++ b/docs/internals/register-uses.txt
@@ -247,67 +247,3 @@
xer n
fpscr
-
-TileGx-linux
-~~~~~~~~~~~~
-
-Reg Callee Arg
-Name Saves? Reg? Comment Vex-uses?
----------------------------------------------------------------------
-r0 n int#1
-r1 n int#2
-r2 n int#3
-r3 n int#4
-r4 n int#5
-r5 n int#6
-r6 n int#7
-r7 n int#8
-r8 n int#9
-r9 n int#10
-r10 n syscall# y
-r11 n Next Guest State
-r12 n y
-r13 n y
-r14 n y
-r15 n y
-r16 n y
-r17 n y
-r18 n y
-r19 n y
-r20 n y
-r21 n y
-r22 n y
-r23 n y
-r24 n y
-r25 n y
-r26 n y
-r27 n y
-r28 n y
-r29 n y
-r30 y y
-r31 y y
-r32 y y
-r33 y y
-r34 y y
-r35 y y
-r36 y y
-r37 y y
-r38 y y
-r39 y y
-r40 y y
-r41 y y
-r42 y y
-r43 y y
-r44 y y
-r45 y y
-r46 y y
-r47 y y
-r48 y y
-r49 y y
-r50 y Guest State
-r51 y used for memory Load/Store
-r52 y frame
-r53 y tls
-r54 y stock
-r55 y return address
-r63 n zero
diff --git a/docs/internals/segments-seginfos.txt b/docs/internals/segments-seginfos.txt
index c712e5c..fbf137c 100644
--- a/docs/internals/segments-seginfos.txt
+++ b/docs/internals/segments-seginfos.txt
@@ -9,7 +9,7 @@
Segments describe memory mapped into the address space, and so any
address-space chaging operation needs to update the Segment structure.
-After the process is initalized, this means one of:
+After the process is initialized, this means one of:
* mmap
* munmap
diff --git a/docs/internals/xml-output-protocol4.txt b/docs/internals/xml-output-protocol4.txt
index 50828c0..65c055d 100644
--- a/docs/internals/xml-output-protocol4.txt
+++ b/docs/internals/xml-output-protocol4.txt
@@ -791,5 +791,5 @@
If the signal reason is not related to an address, the tag is omitted.
* STACK is defined above and shows where the thread was when it
- catched the signal. When sending the signal to itself using raise,
+ caught the signal. When sending the signal to itself using raise,
then raise is visible in this stack.
diff --git a/docs/ms_print.1 b/docs/ms_print.1
index 852a977..153767e 100644
--- a/docs/ms_print.1
+++ b/docs/ms_print.1
@@ -1,13 +1,13 @@
'\" t
.\" Title: ms_print
.\" Author: [see the "Author" section]
-.\" Generator: DocBook XSL Stylesheets v1.78.1 <http://docbook.sf.net/>
-.\" Date: 10/21/2016
-.\" Manual: Release 3.12.0
-.\" Source: Release 3.12.0
+.\" Generator: DocBook XSL Stylesheets v1.79.1 <http://docbook.sf.net/>
+.\" Date: 06/15/2017
+.\" Manual: Release 3.13.0
+.\" Source: Release 3.13.0
.\" Language: English
.\"
-.TH "MS_PRINT" "1" "10/21/2016" "Release 3.12.0" "Release 3.12.0"
+.TH "MS_PRINT" "1" "06/15/2017" "Release 3.13.0" "Release 3.13.0"
.\" -----------------------------------------------------------------
.\" * Define some portability stuff
.\" -----------------------------------------------------------------
diff --git a/docs/valgrind-listener.1 b/docs/valgrind-listener.1
index 6211f04..e9df270 100644
--- a/docs/valgrind-listener.1
+++ b/docs/valgrind-listener.1
@@ -1,13 +1,13 @@
'\" t
.\" Title: valgrind-listener
.\" Author: [see the "Author" section]
-.\" Generator: DocBook XSL Stylesheets v1.78.1 <http://docbook.sf.net/>
-.\" Date: 10/21/2016
-.\" Manual: Release 3.12.0
-.\" Source: Release 3.12.0
+.\" Generator: DocBook XSL Stylesheets v1.79.1 <http://docbook.sf.net/>
+.\" Date: 06/15/2017
+.\" Manual: Release 3.13.0
+.\" Source: Release 3.13.0
.\" Language: English
.\"
-.TH "VALGRIND\-LISTENER" "1" "10/21/2016" "Release 3.12.0" "Release 3.12.0"
+.TH "VALGRIND\-LISTENER" "1" "06/15/2017" "Release 3.13.0" "Release 3.13.0"
.\" -----------------------------------------------------------------
.\" * Define some portability stuff
.\" -----------------------------------------------------------------
diff --git a/docs/valgrind.1 b/docs/valgrind.1
index d0c2354..ee9e5b6 100644
--- a/docs/valgrind.1
+++ b/docs/valgrind.1
@@ -1,13 +1,13 @@
'\" t
.\" Title: VALGRIND
.\" Author: [see the "Author" section]
-.\" Generator: DocBook XSL Stylesheets v1.78.1 <http://docbook.sf.net/>
-.\" Date: 10/21/2016
-.\" Manual: Release 3.12.0
-.\" Source: Release 3.12.0
+.\" Generator: DocBook XSL Stylesheets v1.79.1 <http://docbook.sf.net/>
+.\" Date: 06/15/2017
+.\" Manual: Release 3.13.0
+.\" Source: Release 3.13.0
.\" Language: English
.\"
-.TH "VALGRIND" "1" "10/21/2016" "Release 3.12.0" "Release 3.12.0"
+.TH "VALGRIND" "1" "06/15/2017" "Release 3.13.0" "Release 3.13.0"
.\" -----------------------------------------------------------------
.\" * Define some portability stuff
.\" -----------------------------------------------------------------
@@ -172,7 +172,9 @@
\fBstartup exit valgrindabexit\fR\&.
.sp
The values
-\fBstartup\fR\fBexit\fR\fBvalgrindabexit\fR
+\fBstartup\fR
+\fBexit\fR
+\fBvalgrindabexit\fR
respectively indicate to invoke gdbserver before your program is executed, after the last instruction of your program, on Valgrind abnormal exit (e\&.g\&. internal error, out of memory, \&.\&.\&.)\&.
.sp
Note:
@@ -235,7 +237,12 @@
\fB\-\-trace\-children=yes\fR
and your program invokes multiple processes OR your program forks without calling exec afterwards, and you don\*(Aqt use this specifier (or the
\fB%q\fR
-specifier below), the Valgrind output from all those processes will go into one file, possibly jumbled up, and possibly incomplete\&.
+specifier below), the Valgrind output from all those processes will go into one file, possibly jumbled up, and possibly incomplete\&. Note: If the program forks and calls exec afterwards, Valgrind output of the child from the period between fork and exec will be lost\&. Fortunately this gap is really tiny for most programs; and modern programs use
+posix_spawn
+anyway\&.
+.sp
+\fB%n\fR
+is replaced with a file sequence number unique for this process\&. This is useful for processes that produces several files from the same filename template\&.
.sp
\fB%q{FOO}\fR
is replaced with the contents of the environment variable
@@ -257,7 +264,7 @@
\fB%\fR
is followed by any other character, it causes an abort\&.
.sp
-If the file name specifies a relative file name, it is put in the program\*(Aqs initial working directory : this is the current directory when the program started its execution after the fork or after the exec\&. If it specifies an absolute file name (ie\&. starts with \*(Aq/\*(Aq) then it is put there\&.
+If the file name specifies a relative file name, it is put in the program\*(Aqs initial working directory: this is the current directory when the program started its execution after the fork or after the exec\&. If it specifies an absolute file name (ie\&. starts with \*(Aq/\*(Aq) then it is put there\&.
.RE
.PP
\fB\-\-log\-socket=<ip\-address:port\-number> \fR
@@ -268,7 +275,7 @@
the commentary
in the manual\&.
.RE
-.SH "ERROR-RELATED OPTIONS"
+.SH "ERROR\-RELATED OPTIONS"
.PP
These options are used by all tools that can report errors, e\&.g\&. Memcheck, but not Cachegrind\&.
.PP
@@ -318,7 +325,7 @@
\fB%q\fR
sequences appearing in the filename are expanded in exactly the same way as they are for
\fB\-\-log\-file\fR\&. See the description of
-\fB\-\-log\-file\fR
+--log-file
for details\&.
.RE
.PP
@@ -671,7 +678,7 @@
By default, Valgrind can handle to up to 500 threads\&. Occasionally, that number is too small\&. Use this option to provide a different limit\&. E\&.g\&.
\-\-max\-threads=3000\&.
.RE
-.SH "MALLOC()-RELATED OPTIONS"
+.SH "MALLOC()\-RELATED OPTIONS"
.PP
For tools that use their own version of
malloc
@@ -692,6 +699,56 @@
.sp
Increasing the redzone size makes it possible to detect overruns of larger distances, but increases the amount of memory used by Valgrind\&. Decreasing the redzone size will reduce the memory needed by Valgrind but also reduces the chances of detecting over/underruns, so is not recommended\&.
.RE
+.PP
+\fB\-\-xtree\-memory=none|allocs|full [none] \fR
+.RS 4
+Tools replacing Valgrind\*(Aqs
+\fBmalloc, realloc,\fR
+etc, can optionally produce an execution tree detailing which piece of code is responsible for heap memory usage\&. See
+???
+for a detailed explanation about execution trees\&.
+.sp
+When set to
+\fInone\fR, no memory execution tree is produced\&.
+.sp
+When set to
+\fIallocs\fR, the memory execution tree gives the current number of allocated bytes and the current number of allocated blocks\&.
+.sp
+When set to
+\fIfull\fR, the memory execution tree gives 6 different measurements : the current number of allocated bytes and blocks (same values as for
+\fIallocs\fR), the total number of allocated bytes and blocks, the total number of freed bytes and blocks\&.
+.sp
+Note that the overhead in cpu and memory to produce an xtree depends on the tool\&. The overhead in cpu is small for the value
+\fIallocs\fR, as the information needed to produce this report is maintained in any case by the tool\&. For massif and helgrind, specifying
+\fIfull\fR
+implies to capture a stack trace for each free operation, while normally these tools only capture an allocation stack trace\&. For memcheck, the cpu overhead for the value
+\fIfull\fR
+is small, as this can only be used in combination with
+\fB\-\-keep\-stacktraces=alloc\-and\-free\fR
+or
+\fB\-\-keep\-stacktraces=alloc\-then\-free\fR, which already records a stack trace for each free operation\&. The memory overhead varies between 5 and 10 words per unique stacktrace in the xtree, plus the memory needed to record the stack trace for the free operations, if needed specifically for the xtree\&.
+.RE
+.PP
+\fB\-\-xtree\-memory\-file=<filename> [default: xtmemory\&.kcg\&.%p] \fR
+.RS 4
+Specifies that Valgrind should produce the xtree memory report in the specified file\&. Any
+\fB%p\fR
+or
+\fB%q\fR
+sequences appearing in the filename are expanded in exactly the same way as they are for
+\fB\-\-log\-file\fR\&. See the description of
+--log-file
+for details\&.
+.sp
+If the filename contains the extension
+\fB\&.ms\fR, then the produced file format will be a massif output file format\&. If the filename contains the extension
+\fB\&.kcg\fR
+or no extension is provided or recognised, then the produced file format will be a callgrind output format\&.
+.sp
+See
+???
+for a detailed explanation about execution trees formats\&.
+.RE
.SH "UNCOMMON OPTIONS"
.PP
These options apply to all tools, as they affect certain obscure workings of the Valgrind core\&. Most people won\*(Aqt need to use them\&.
@@ -955,7 +1012,7 @@
.sp
When using the memcheck tool, disabling the cache ensures the memory used by glibc to handle __thread variables is directly released when a thread terminates\&.
.sp
-Note: Valgrind disables the cache using some internal knowledge of the glibc stack cache implementation and by examining the debug information of the pthread library\&. This technique is thus somewhat fragile and might not work for all glibc versions\&. This has been succesfully tested with various glibc versions (e\&.g\&. 2\&.11, 2\&.16, 2\&.18) on various platforms\&.
+Note: Valgrind disables the cache using some internal knowledge of the glibc stack cache implementation and by examining the debug information of the pthread library\&. This technique is thus somewhat fragile and might not work for all glibc versions\&. This has been successfully tested with various glibc versions (e\&.g\&. 2\&.11, 2\&.16, 2\&.18) on various platforms\&.
.RE
.sp
.RS 4
@@ -969,6 +1026,17 @@
\fBlax\-doors: \fR
(Solaris only) Be very lax about door syscall handling over unrecognised door file descriptors\&. Does not require that full buffer is initialised when writing\&. Without this, programs using libdoor(3LIB) functionality with completely proprietary semantics may report large number of false positives\&.
.RE
+.sp
+.RS 4
+.ie n \{\
+\h'-04'\(bu\h'+03'\c
+.\}
+.el \{\
+.sp -1
+.IP \(bu 2.3
+.\}
+\fBfallback\-llsc: \fR(MIPS and ARM64 only): Enables an alternative implementation of Load\-Linked (LL) and Store\-Conditional (SC) instructions\&. The standard implementation gives more correct behaviour, but can cause indefinite looping on certain processor implementations that are intolerant of extra memory references between LL and SC\&. So far this is known only to happen on Cavium 3 cores\&. You should not need to use this flag, since the relevant cores are detected at startup and the alternative implementation is automatically enabled if necessary\&. There is no equivalent anti\-flag: you cannot force\-disable the alternative implementation, if it is automatically enabled\&. The underlying problem exists because the "standard" implementation of LL and SC is done by copying through LL and SC instructions into the instrumented code\&. However, tools may insert extra instrumentation memory references in between the LL and SC instructions\&. These memory references are not present in the original uninstrumented code, and their presence in the instrumented code can cause the SC instructions to persistently fail, leading to indefinite looping in LL\-SC blocks\&. The alternative implementation gives correct behaviour of LL and SC instructions between threads in a process, up to and including the ABA scenario\&. It also gives correct behaviour between a Valgrinded thread and a non\-Valgrinded thread running in a different process, that communicate via shared memory, but only up to and including correct CAS behaviour \-\- in this case the ABA scenario may not be correctly handled\&.
+.RE
.RE
.PP
\fB\-\-fair\-sched=<no|yes|try> [default: no] \fR
@@ -1442,6 +1510,151 @@
is specified\&.
.RE
.PP
+\fB\-\-xtree\-leak=<no|yes> [no] \fR
+.RS 4
+If set to yes, the results for the leak search done at exit will be output in a \*(AqCallgrind Format\*(Aq execution tree file\&. Note that this automatically sets the option
+\fB\-\-leak\-check=full\fR\&. The produced file will contain the following events:
+.sp
+.RS 4
+.ie n \{\
+\h'-04'\(bu\h'+03'\c
+.\}
+.el \{\
+.sp -1
+.IP \(bu 2.3
+.\}
+\fBRB\fR
+: Reachable Bytes
+.RE
+.sp
+.RS 4
+.ie n \{\
+\h'-04'\(bu\h'+03'\c
+.\}
+.el \{\
+.sp -1
+.IP \(bu 2.3
+.\}
+\fBPB\fR
+: Possibly lost Bytes
+.RE
+.sp
+.RS 4
+.ie n \{\
+\h'-04'\(bu\h'+03'\c
+.\}
+.el \{\
+.sp -1
+.IP \(bu 2.3
+.\}
+\fBIB\fR
+: Indirectly lost Bytes
+.RE
+.sp
+.RS 4
+.ie n \{\
+\h'-04'\(bu\h'+03'\c
+.\}
+.el \{\
+.sp -1
+.IP \(bu 2.3
+.\}
+\fBDB\fR
+: Definitely lost Bytes (direct plus indirect)
+.RE
+.sp
+.RS 4
+.ie n \{\
+\h'-04'\(bu\h'+03'\c
+.\}
+.el \{\
+.sp -1
+.IP \(bu 2.3
+.\}
+\fBDIB\fR
+: Definitely Indirectly lost Bytes (subset of DB)
+.RE
+.sp
+.RS 4
+.ie n \{\
+\h'-04'\(bu\h'+03'\c
+.\}
+.el \{\
+.sp -1
+.IP \(bu 2.3
+.\}
+\fBRBk\fR
+: reachable Blocks
+.RE
+.sp
+.RS 4
+.ie n \{\
+\h'-04'\(bu\h'+03'\c
+.\}
+.el \{\
+.sp -1
+.IP \(bu 2.3
+.\}
+\fBPBk\fR
+: Possibly lost Blocks
+.RE
+.sp
+.RS 4
+.ie n \{\
+\h'-04'\(bu\h'+03'\c
+.\}
+.el \{\
+.sp -1
+.IP \(bu 2.3
+.\}
+\fBIBk\fR
+: Indirectly lost Blocks
+.RE
+.sp
+.RS 4
+.ie n \{\
+\h'-04'\(bu\h'+03'\c
+.\}
+.el \{\
+.sp -1
+.IP \(bu 2.3
+.\}
+\fBDBk\fR
+: Definitely lost Blocks
+.RE
+.sp
+The increase or decrease for all events above will also be output in the file to provide the delta (increase or decreaseà between 2 successive leak searches\&. For example,
+\fBiRB\fR
+is the increase of the
+\fBRB\fR
+event,
+\fBdPBk\fR
+is the decrease of
+\fBPBk\fR
+event\&. The values for the increase and decrease events will be zero for the first leak search done\&.
+.sp
+See
+???
+for a detailed explanation about execution trees\&.
+.RE
+.PP
+\fB\-\-xtree\-leak\-file=<filename> [default: xtleak\&.kcg\&.%p] \fR
+.RS 4
+Specifies that Valgrind should produce the xtree leak report in the specified file\&. Any
+\fB%p\fR,
+\fB%q\fR
+or
+\fB%n\fR
+sequences appearing in the filename are expanded in exactly the same way as they are for
+\fB\-\-log\-file\fR\&. See the description of
+--log-file
+for details\&.
+.sp
+See
+???
+for a detailed explanation about execution trees formats\&.
+.RE
+.PP
\fB\-\-undef\-value\-errors=<yes|no> [default: yes] \fR
.RS 4
Controls whether Memcheck reports uses of undefined value errors\&. Set this to
@@ -1510,6 +1723,15 @@
\fI\-\-keep\-stacktraces\fR
and/or by using a smaller value for the option
\fI\-\-num\-callers\fR\&.
+.sp
+If you want to use
+\-\-xtree\-memory=full
+memory profiling (see
+???
+), then you cannot specify
+\fI\-\-keep\-stacktraces=free\fR
+or
+\fI\-\-keep\-stacktraces=none\fR\&.
.RE
.PP
\fB\-\-freelist\-vol=<number> [default: 20000000] \fR
@@ -2322,7 +2544,8 @@
$INSTALL/share/doc/valgrind/html/index\&.html
or
http://www\&.valgrind\&.org/docs/manual/index\&.html,
-\m[blue]\fBDebugging your program using Valgrind\*(Aqs gdbserver and GDB\fR\m[]\&\s-2\u[1]\d\s+2\m[blue]\fBvgdb\fR\m[]\&\s-2\u[2]\d\s+2,
+\m[blue]\fBDebugging your program using Valgrind\*(Aqs gdbserver and GDB\fR\m[]\&\s-2\u[1]\d\s+2
+\m[blue]\fBvgdb\fR\m[]\&\s-2\u[2]\d\s+2,
\m[blue]\fBValgrind monitor commands\fR\m[]\&\s-2\u[3]\d\s+2,
\m[blue]\fBThe Commentary\fR\m[]\&\s-2\u[4]\d\s+2,
\m[blue]\fBScheduling and Multi\-Thread Performance\fR\m[]\&\s-2\u[5]\d\s+2,
diff --git a/docs/vgdb.1 b/docs/vgdb.1
index c4034b6..bdaacd6 100644
--- a/docs/vgdb.1
+++ b/docs/vgdb.1
@@ -1,13 +1,13 @@
'\" t
.\" Title: vgdb
.\" Author: [see the "Author" section]
-.\" Generator: DocBook XSL Stylesheets v1.78.1 <http://docbook.sf.net/>
-.\" Date: 10/21/2016
-.\" Manual: Release 3.12.0
-.\" Source: Release 3.12.0
+.\" Generator: DocBook XSL Stylesheets v1.79.1 <http://docbook.sf.net/>
+.\" Date: 06/15/2017
+.\" Manual: Release 3.13.0
+.\" Source: Release 3.13.0
.\" Language: English
.\"
-.TH "VGDB" "1" "10/21/2016" "Release 3.12.0" "Release 3.12.0"
+.TH "VGDB" "1" "06/15/2017" "Release 3.13.0" "Release 3.13.0"
.\" -----------------------------------------------------------------
.\" * Define some portability stuff
.\" -----------------------------------------------------------------
@@ -185,7 +185,8 @@
$INSTALL/share/doc/valgrind/html/index\&.html
or
http://www\&.valgrind\&.org/docs/manual/index\&.html,
-\m[blue]\fBDebugging your program using Valgrind\*(Aqs gdbserver and GDB\fR\m[]\&\s-2\u[1]\d\s+2\m[blue]\fBvgdb\fR\m[]\&\s-2\u[2]\d\s+2,
+\m[blue]\fBDebugging your program using Valgrind\*(Aqs gdbserver and GDB\fR\m[]\&\s-2\u[1]\d\s+2
+\m[blue]\fBvgdb\fR\m[]\&\s-2\u[2]\d\s+2,
\m[blue]\fBValgrind monitor commands\fR\m[]\&\s-2\u[3]\d\s+2\&.
.SH "AUTHOR"
.PP
diff --git a/docs/xml/manual-core-adv.xml b/docs/xml/manual-core-adv.xml
index b767825..80190d6 100644
--- a/docs/xml/manual-core-adv.xml
+++ b/docs/xml/manual-core-adv.xml
@@ -233,7 +233,7 @@
memcheck leak search can be requested from the client program
using VALGRIND_DO_LEAK_CHECK or via the monitor command "leak_search".
Note that the syntax of the command string is only verified at
- run-time. So, if it exists, it is preferrable to use a specific
+ run-time. So, if it exists, it is preferable to use a specific
client request to have better compile time verifications of the
arguments.
</para>
@@ -411,8 +411,8 @@
<programlisting><![CDATA[
==2418== Memcheck, a memory error detector
-==2418== Copyright (C) 2002-2010, and GNU GPL'd, by Julian Seward et al.
-==2418== Using Valgrind-3.7.0.SVN and LibVEX; rerun with -h for copyright info
+==2418== Copyright (C) 2002-2017, and GNU GPL'd, by Julian Seward et al.
+==2418== Using Valgrind-3.13.0.SVN and LibVEX; rerun with -h for copyright info
==2418== Command: ./prog
==2418==
==2418== (action at startup) vgdb me ...
@@ -1057,6 +1057,12 @@
OS X or Android.
</para>
+ <para>Unblocking processes blocked in system calls is implemented
+ via agent thread on Solaris. This is quite a different approach
+ than using ptrace on Linux, but leads to equivalent result - Valgrind
+ gdbserver is invoked. Note that agent thread is a Solaris OS
+ feature and cannot be disabled.
+ </para>
</listitem>
<listitem>
@@ -1390,6 +1396,13 @@
to a huge value and continue execution.</para>
</listitem>
+ <listitem>
+ <para><varname>xtmemory [<filename> default xtmemory.kcg.%p.%n]</varname>
+ requests the tool to produce an xtree heap memory report.
+ See <xref linkend="manual-core.xtree"/> for
+ a detailed explanation about execution trees. </para>
+ </listitem>
+
</itemizedlist>
<para>The following Valgrind monitor commands are useful for
@@ -1435,7 +1448,7 @@
</listitem>
<listitem>
- <para><varname>v.info exectxt</varname> shows informations about
+ <para><varname>v.info exectxt</varname> shows information about
the "executable contexts" (i.e. the stack traces) recorded by
Valgrind. For some programs, Valgrind can record a very high
number of such stack traces, causing a high memory usage. This
@@ -1503,9 +1516,9 @@
<screen><![CDATA[
(gdb) monitor v.set hostvisibility yes
-(gdb) add-symbol-file /path/to/tool/executable/file/memcheck-x86-linux 0x38000000
+(gdb) add-symbol-file /path/to/tool/executable/file/memcheck-x86-linux 0x58000000
add symbol table from file "/path/to/tool/executable/file/memcheck-x86-linux" at
- .text_addr = 0x38000000
+ .text_addr = 0x58000000
(y or n) y
Reading symbols from /path/to/tool/executable/file/memcheck-x86-linux...done.
(gdb)
diff --git a/docs/xml/manual-core.xml b/docs/xml/manual-core.xml
index 7334995..88dadaf 100644
--- a/docs/xml/manual-core.xml
+++ b/docs/xml/manual-core.xml
@@ -886,7 +886,17 @@
calling exec afterwards, and you don't use this specifier
(or the <option>%q</option> specifier below), the Valgrind output from
all those processes will go into one file, possibly jumbled up, and
- possibly incomplete.</para>
+ possibly incomplete. Note: If the program forks and calls exec afterwards,
+ Valgrind output of the child from the period between fork and exec
+ will be lost. Fortunately this gap is really tiny for most programs;
+ and modern programs use <computeroutput>posix_spawn</computeroutput>
+ anyway.</para>
+
+ <para><option>%n</option> is replaced with a file sequence number
+ unique for this process.
+ This is useful for processes that produces several files
+ from the same filename template.</para>
+
<para><option>%q{FOO}</option> is replaced with the contents of the
environment variable <varname>FOO</varname>. If the
@@ -906,7 +916,7 @@
causes an abort.</para>
<para>If the file name specifies a relative file name, it is put
- in the program's initial working directory : this is the current
+ in the program's initial working directory: this is the current
directory when the program started its execution after the fork
or after the exec. If it specifies an absolute file name (ie.
starts with '/') then it is put there.
@@ -1011,7 +1021,7 @@
<option>--xml=yes</option>. Any <option>%p</option> or
<option>%q</option> sequences appearing in the filename are expanded
in exactly the same way as they are for <option>--log-file</option>.
- See the description of <option>--log-file</option> for details.
+ See the description of <xref linkend="opt.log-file"/> for details.
</para>
</listitem>
</varlistentry>
@@ -1686,6 +1696,74 @@
</listitem>
</varlistentry>
+ <varlistentry id="opt.xtree-memory" xreflabel="--xtree-memory">
+ <term>
+ <option><![CDATA[--xtree-memory=none|allocs|full [none] ]]></option>
+ </term>
+ <listitem>
+ <para> Tools replacing Valgrind's <function>malloc,
+ realloc,</function> etc, can optionally produce an execution
+ tree detailing which piece of code is responsible for heap
+ memory usage. See <xref linkend="manual-core.xtree"/>
+ for a detailed explanation about execution trees. </para>
+
+ <para> When set to <varname>none</varname>, no memory execution
+ tree is produced.</para>
+
+ <para> When set to <varname>allocs</varname>, the memory
+ execution tree gives the current number of allocated bytes and
+ the current number of allocated blocks. </para>
+
+ <para> When set to <varname>full</varname>, the memory execution
+ tree gives 6 different measurements : the current number of
+ allocated bytes and blocks (same values as
+ for <varname>allocs</varname>), the total number of allocated
+ bytes and blocks, the total number of freed bytes and
+ blocks.</para>
+
+ <para>Note that the overhead in cpu and memory to produce
+ an xtree depends on the tool. The overhead in cpu is small for
+ the value <varname>allocs</varname>, as the information needed
+ to produce this report is maintained in any case by the tool.
+ For massif and helgrind, specifying <varname>full</varname>
+ implies to capture a stack trace for each free operation,
+ while normally these tools only capture an allocation stack
+ trace. For memcheck, the cpu overhead for the
+ value <varname>full</varname> is small, as this can only be
+ used in combination with
+ <option>--keep-stacktraces=alloc-and-free</option> or
+ <option>--keep-stacktraces=alloc-then-free</option>, which
+ already records a stack trace for each free operation. The
+ memory overhead varies between 5 and 10 words per unique
+ stacktrace in the xtree, plus the memory needed to record the
+ stack trace for the free operations, if needed specifically
+ for the xtree.
+ </para>
+ </listitem>
+ </varlistentry>
+
+ <varlistentry id="opt.xtree-memory-file" xreflabel="--xtree-memory-file">
+ <term>
+ <option><![CDATA[--xtree-memory-file=<filename> [default:
+ xtmemory.kcg.%p] ]]></option>
+ </term>
+ <listitem>
+ <para>Specifies that Valgrind should produce the xtree memory
+ report in the specified file. Any <option>%p</option> or
+ <option>%q</option> sequences appearing in the filename are expanded
+ in exactly the same way as they are for <option>--log-file</option>.
+ See the description of <xref linkend="opt.log-file"/>
+ for details. </para>
+ <para>If the filename contains the extension <option>.ms</option>,
+ then the produced file format will be a massif output file format.
+ If the filename contains the extension <option>.kcg</option>
+ or no extension is provided or recognised,
+ then the produced file format will be a callgrind output format.</para>
+ <para>See <xref linkend="manual-core.xtree"/>
+ for a detailed explanation about execution trees formats. </para>
+ </listitem>
+ </varlistentry>
+
</variablelist>
<!-- end of xi:include in the manpage -->
@@ -2037,7 +2115,7 @@
knowledge of the glibc stack cache implementation and by
examining the debug information of the pthread
library. This technique is thus somewhat fragile and might
- not work for all glibc versions. This has been succesfully
+ not work for all glibc versions. This has been successfully
tested with various glibc versions (e.g. 2.11, 2.16, 2.18)
on various platforms.</para>
</listitem>
@@ -2049,6 +2127,39 @@
functionality with completely proprietary semantics may report
large number of false positives.</para>
</listitem>
+ <listitem>
+ <para><option>fallback-llsc: </option>(MIPS and ARM64 only): Enables
+ an alternative implementation of Load-Linked (LL) and
+ Store-Conditional (SC) instructions. The standard implementation
+ gives more correct behaviour, but can cause indefinite looping on
+ certain processor implementations that are intolerant of extra
+ memory references between LL and SC. So far this is known only to
+ happen on Cavium 3 cores.
+
+ You should not need to use this flag, since the relevant cores are
+ detected at startup and the alternative implementation is
+ automatically enabled if necessary. There is no equivalent
+ anti-flag: you cannot force-disable the alternative
+ implementation, if it is automatically enabled.
+
+ The underlying problem exists because the "standard"
+ implementation of LL and SC is done by copying through LL and SC
+ instructions into the instrumented code. However, tools may
+ insert extra instrumentation memory references in between the LL
+ and SC instructions. These memory references are not present in
+ the original uninstrumented code, and their presence in the
+ instrumented code can cause the SC instructions to persistently
+ fail, leading to indefinite looping in LL-SC blocks.
+
+ The alternative implementation gives correct behaviour of LL and
+ SC instructions between threads in a process, up to and including
+ the ABA scenario. It also gives correct behaviour between a
+ Valgrinded thread and a non-Valgrinded thread running in a
+ different process, that communicate via shared memory, but only up
+ to and including correct CAS behaviour -- in this case the ABA
+ scenario may not be correctly handled.
+ </para>
+ </listitem>
</itemizedlist>
</listitem>
</varlistentry>
@@ -2489,8 +2600,8 @@
</para>
<para>Please note that the <computeroutput>./.valgrindrc</computeroutput>
-file is ignored if it is marked as world writeable or not owned
-by the current user. This is because the
+file is ignored if it is not a regular file, or is marked as world writeable,
+or is not owned by the current user. This is because the
<computeroutput>./.valgrindrc</computeroutput> can contain options that are
potentially harmful or can be used by a local attacker to execute code under
your user account.
@@ -2673,11 +2784,237 @@
</sect1>
+<sect1 id="manual-core.xtree" xreflabel="Execution Trees">
+<title>Execution Trees</title>
+<para>An execution tree (xtree) is made of a set of stack traces, each
+ stack trace is associated with some resource consumptions or event
+ counts. Depending on the xtree, different event counts/resource
+ consumptions can be recorded in the xtree. Multiple tools can
+ produce memory use xtree. Memcheck can output the leak search results
+ in an xtree.</para>
+<para> A typical usage for an xtree is to show a graphical or textual
+ representation of the heap usage of a program. The below figure is
+ a heap usage xtree graphical representation produced by
+ kcachegrind. In the kcachegrind output, you can see that main
+ current heap usage (allocated indirectly) is 528 bytes : 388 bytes
+ allocated indirectly via a call to function f1 and 140 bytes
+ indirectly allocated via a call to function f2. f2 has allocated
+ memory by calling g2, while f1 has allocated memory by calling g11
+ and g12. g11, g12 and g1 have directly called a memory allocation
+ function (malloc), and so have a non zero 'Self' value. Note that when
+ kcachegrind shows an xtree, the 'Called' column and call nr indications in
+ the Call Graph are not significant (always set to 0 or 1, independently
+ of the real nr of calls. The kcachegrind versions >= 0.8.0 do not show
+ anymore such irrelevant xtree call number information.</para>
+<graphic fileref="images/kcachegrind_xtree.png" scalefit="1"/>
+<para>An xtree heap memory report is produced at the end of the
+ execution when required using the
+ option <option>--xtree-memory</option>. It can also be produced on
+ demand using the <option>xtmemory</option> monitor command (see
+ <xref linkend="manual-core-adv.valgrind-monitor-commands"/>). Currently,
+ an xtree heap memory report can be produced by
+ the <option>memcheck</option>, <option>helgrind</option>
+ and <option>massif</option> tools.</para>
+ <para>The xtrees produced by the option
+ <xref linkend="opt.xtree-memory"/> or the <option>xtmemory</option>
+ monitor command are showing the following events/resource
+ consumption describing heap usage:</para>
+<itemizedlist>
+ <listitem>
+ <para><option>curB</option> current number of Bytes allocated. The
+ number of allocated bytes is added to the <option>curB</option>
+ value of a stack trace for each allocation. It is decreased when
+ a block allocated by this stack trace is released (by another
+ "freeing" stack trace)</para>
+ </listitem>
+
+ <listitem>
+ <para><option>curBk</option> current number of Blocks allocated,
+ maintained similary to curB : +1 for each allocation, -1 when
+ the block is freed.</para>
+ </listitem>
+
+ <listitem>
+ <para><option>totB</option> total allocated Bytes. This is
+ increased for each allocation with the number of allocated bytes.</para>
+ </listitem>
+
+ <listitem>
+ <para><option>totBk</option> total allocated Blocks, maintained similary
+ to totB : +1 for each allocation.</para>
+ </listitem>
+
+ <listitem>
+ <para><option>totFdB</option> total Freed Bytes, increased each time
+ a block is released by this ("freeing") stack trace : + nr freed bytes
+ for each free operation.</para>
+ </listitem>
+
+ <listitem>
+ <para><option>totFdBk</option> total Freed Blocks, maintained similarly
+ to totFdB : +1 for each free operation.</para>
+ </listitem>
+</itemizedlist>
+<para>Note that the last 4 counts are produced only when the
+ <option>--xtree-memory=full</option> was given at startup.</para>
+
+<para>Xtrees can be saved in 2 file formats, the "Callgrind Format" and
+the "Massif Format".</para>
+<itemizedlist>
+
+ <listitem>
+ <para>Callgrind Format</para>
+ <para>An xtree file in the Callgrind Format contains a single callgraph,
+ associating each stack trace with the values recorded
+ in the xtree. </para>
+ <para>Different Callgrind Format file visualisers are available:</para>
+ <para>Valgrind distribution includes the <option>callgrind_annotate</option>
+ command line utility that reads in the xtree data, and prints a sorted
+ lists of functions, optionally with source annotation. Note that due to
+ xtree specificities, you must give the option
+ <option>--inclusive=yes</option> to callgrind_annotate.</para>
+ <para>For graphical visualization of the data, you can use
+ <ulink url="&cl-gui-url;">KCachegrind</ulink>, which is a KDE/Qt based
+ GUI that makes it easy to navigate the large amount of data that
+ an xtree can contain.</para>
+ </listitem>
+
+ <listitem>
+ <para>Massif Format</para>
+ <para>An xtree file in the Massif Format contains one detailed tree
+ callgraph data for each type of event recorded in the xtree. So,
+ for <option>--xtree-memory=alloc</option>, the output file will
+ contain 2 detailed trees (for the counts <option>curB</option>
+ and <option>curBk</option>),
+ while <option>--xtree-memory=full</option> will give a file
+ with 6 detailed trees.</para>
+ <para>Different Massif Format file visualisers are available. Valgrind
+ distribution includes the <option>ms_print</option>
+ command line utility that produces an easy to read reprentation of
+ a massif output file. See <xref linkend="ms-manual.running-massif"/> and
+ <xref linkend="ms-manual.using"/> for more details
+ about visualising Massif Format output files.</para>
+ </listitem>
+
+</itemizedlist>
+
+<para>Note that for equivalent information, the Callgrind Format is more compact
+ than the Massif Format. However, the Callgrind Format always contains the
+ full data: there is no filtering done during file production, filtering is
+ done by visualisers such as kcachegrind. kcachegrind is particularly easy to
+ use to analyse big xtree data containing multiple events counts or resources
+ consumption. The Massif Format (optionally) only contains a part of the data.
+ For example, the Massif tool might filter some of the data, according to the
+ <option>--threshold</option> option.
+</para>
+
+<para>To clarify the xtree concept, the below gives several extracts of
+ the output produced by the following commands:
+<screen><![CDATA[
+valgrind --xtree-memory=full --xtree-memory-file=xtmemory.kcg mfg
+callgrind_annotate --auto=yes --inclusive=yes --sort=curB:100,curBk:100,totB:100,totBk:100,totFdB:100,totFdBk:100 xtmemory.kcg
+]]></screen>
+</para>
+
+<para>The below extract shows that the program mfg has allocated in
+ total 770 bytes in 60 different blocks. Of these 60 blocks, 19 were
+ freed, releasing a total of 242 bytes. The heap currently contains
+ 528 bytes in 41 blocks.</para>
+<screen><![CDATA[
+--------------------------------------------------------------------------------
+curB curBk totB totBk totFdB totFdBk
+--------------------------------------------------------------------------------
+ 528 41 770 60 242 19 PROGRAM TOTALS
+]]></screen>
+
+<para>The below gives more details about which functions have
+ allocated or released memory. As an example, we see that main has
+ (directly or indirectly) allocated 770 bytes of memory and freed
+ (directly or indirectly) 242 bytes of memory. The function f1 has
+ (directly or indirectly) allocated 570 bytes of memory, and has not
+ (directly or indirectly) freed memory. Of the 570 bytes allocated
+ by function f1, 388 bytes (34 blocks) have not been
+ released.</para>
+<screen><![CDATA[
+--------------------------------------------------------------------------------
+curB curBk totB totBk totFdB totFdBk file:function
+--------------------------------------------------------------------------------
+ 528 41 770 60 242 19 mfg.c:main
+ 388 34 570 50 0 0 mfg.c:f1
+ 220 20 330 30 0 0 mfg.c:g11
+ 168 14 240 20 0 0 mfg.c:g12
+ 140 7 200 10 0 0 mfg.c:g2
+ 140 7 200 10 0 0 mfg.c:f2
+ 0 0 0 0 131 10 mfg.c:freeY
+ 0 0 0 0 111 9 mfg.c:freeX
+]]></screen>
+
+<para>The below gives a more detailed information about the callgraph
+ and which source lines/calls have (directly or indirectly) allocated or
+ released memory. The below shows that the 770 bytes allocated by
+ main have been indirectly allocated by calls to f1 and f2.
+ Similarly, we see that the 570 bytes allocated by f1 have been
+ indirectly allocated by calls to g11 and g12. Of the 330 bytes allocated
+ by the 30 calls to g11, 168 bytes have not been freed.
+ The function freeY (called once by main) has released in total
+ 10 blocks and 131 bytes. </para>
+<screen><![CDATA[
+--------------------------------------------------------------------------------
+-- Auto-annotated source: /home/philippe/valgrind/littleprogs/ + mfg.c
+--------------------------------------------------------------------------------
+curB curBk totB totBk totFdB totFdBk
+....
+ . . . . . . static void freeY(void)
+ . . . . . . {
+ . . . . . . int i;
+ . . . . . . for (i = 0; i < next_ptr; i++)
+ . . . . . . if(i % 5 == 0 && ptrs[i] != NULL)
+ 0 0 0 0 131 10 free(ptrs[i]);
+ . . . . . . }
+ . . . . . . static void f1(void)
+ . . . . . . {
+ . . . . . . int i;
+ . . . . . . for (i = 0; i < 30; i++)
+ 220 20 330 30 0 0 g11();
+ . . . . . . for (i = 0; i < 20; i++)
+ 168 14 240 20 0 0 g12();
+ . . . . . . }
+ . . . . . . int main()
+ . . . . . . {
+ 388 34 570 50 0 0 f1();
+ 140 7 200 10 0 0 f2();
+ 0 0 0 0 111 9 freeX();
+ 0 0 0 0 131 10 freeY();
+ . . . . . . return 0;
+ . . . . . . }
+]]></screen>
+
+<para>Heap memory xtrees are helping to understand how your (big)
+ program is using the heap. A full heap memory xtree helps to pin
+ point some code that allocates a lot of small objects : allocating
+ such small objects might be replaced by more efficient technique,
+ such as allocating a big block using malloc, and then diviving this
+ block into smaller blocks in order to decrease the cpu and/or memory
+ overhead of allocating a lot of small blocks. Such full xtree information
+ complements e.g. what callgrind can show: callgrind can show the number
+ of calls to a function (such as malloc) but does not indicate the volume
+ of memory allocated (or freed).</para>
+
+<para>A full heap memory xtree also can identify the code that allocates
+ and frees a lot of blocks : the total foot print of the program might
+ not reflect the fact that the same memory was over and over allocated
+ then released.</para>
+
+<para>Finally, Xtree visualisers such as kcachegrind are helping to
+ identify big memory consumers, in order to possibly optimise the
+ amount of memory needed by your program.</para>
+
+</sect1>
<sect1 id="manual-core.install" xreflabel="Building and Installing">
<title>Building and Installing Valgrind</title>
diff --git a/docs/xml/manual-writing-tools.xml b/docs/xml/manual-writing-tools.xml
index 5ee037d..9f1761d 100644
--- a/docs/xml/manual-writing-tools.xml
+++ b/docs/xml/manual-writing-tools.xml
@@ -155,8 +155,8 @@
The output should be something like this:</para>
<programlisting><![CDATA[
==738== foobar-0.0.1, a foobarring tool.
- ==738== Copyright (C) 2002-2009, and GNU GPL'd, by J. Programmer.
- ==738== Using Valgrind-3.5.0.SVN and LibVEX; rerun with -h for copyright info
+ ==738== Copyright (C) 2002-2017, and GNU GPL'd, by J. Programmer.
+ ==738== Using Valgrind-3.13.0.SVN and LibVEX; rerun with -h for copyright info
==738== Command: date
==738==
Tue Nov 27 12:40:49 EST 2007
diff --git a/docs/xml/vg-entities.xml b/docs/xml/vg-entities.xml
index 9512301..2bf146d 100644
--- a/docs/xml/vg-entities.xml
+++ b/docs/xml/vg-entities.xml
@@ -2,12 +2,12 @@
<!ENTITY vg-jemail "julian@valgrind.org">
<!ENTITY vg-vemail "valgrind@valgrind.org">
<!ENTITY cl-email "Josef.Weidendorfer@gmx.de">
-<!ENTITY vg-lifespan "2000-2016">
+<!ENTITY vg-lifespan "2000-2017">
<!-- valgrind release + version stuff -->
<!ENTITY rel-type "Release">
-<!ENTITY rel-version "3.12.0">
-<!ENTITY rel-date "20 October 2016">
+<!ENTITY rel-version "3.13.0">
+<!ENTITY rel-date "15 June 2017">
<!-- where the docs are installed -->
<!ENTITY vg-docs-path "$INSTALL/share/doc/valgrind/html/index.html">
diff --git a/drd/Makefile.in b/drd/Makefile.in
index 13f921f..6f86173 100644
--- a/drd/Makefile.in
+++ b/drd/Makefile.in
@@ -394,6 +394,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -565,6 +566,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -575,6 +577,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -649,8 +652,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -695,7 +696,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
@@ -773,9 +773,6 @@
-static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \
@FLAG_M64@
-TOOL_LDFLAGS_TILEGX_LINUX = \
- $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-
TOOL_LDFLAGS_X86_SOLARIS = \
$(TOOL_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
@@ -830,9 +827,6 @@
LIBREPLACEMALLOC_MIPS64_LINUX = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a
-LIBREPLACEMALLOC_TILEGX_LINUX = \
- $(top_builddir)/coregrind/libreplacemalloc_toolpreload-tilegx-linux.a
-
LIBREPLACEMALLOC_X86_SOLARIS = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-solaris.a
@@ -895,11 +889,6 @@
$(LIBREPLACEMALLOC_MIPS64_LINUX) \
-Wl,--no-whole-archive
-LIBREPLACEMALLOC_LDFLAGS_TILEGX_LINUX = \
- -Wl,--whole-archive \
- $(LIBREPLACEMALLOC_TILEGX_LINUX) \
- -Wl,--no-whole-archive
-
LIBREPLACEMALLOC_LDFLAGS_X86_SOLARIS = \
-Wl,--whole-archive \
$(LIBREPLACEMALLOC_X86_SOLARIS) \
diff --git a/drd/drd.h b/drd/drd.h
index 4615e5b..d63b3dd 100644
--- a/drd/drd.h
+++ b/drd/drd.h
@@ -12,7 +12,7 @@
This file is part of DRD, a Valgrind tool for verification of
multithreaded programs.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
All rights reserved.
Redistribution and use in source and binary forms, with or without
diff --git a/drd/drd_barrier.c b/drd/drd_barrier.c
index e1ab131..f1f57fb 100644
--- a/drd/drd_barrier.c
+++ b/drd/drd_barrier.c
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_barrier.h b/drd/drd_barrier.h
index c571807..6df29e9 100644
--- a/drd/drd_barrier.h
+++ b/drd/drd_barrier.h
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_basics.h b/drd/drd_basics.h
index 57b2df0..eb8c10f 100644
--- a/drd/drd_basics.h
+++ b/drd/drd_basics.h
@@ -1,7 +1,7 @@
/*
This file is part of DRD, a thread error detector.
- Copyright (C) 2009-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2009-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_bitmap.c b/drd/drd_bitmap.c
index df7691a..2b9db28 100644
--- a/drd/drd_bitmap.c
+++ b/drd/drd_bitmap.c
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_bitmap.h b/drd/drd_bitmap.h
index 94b5285..488d895 100644
--- a/drd/drd_bitmap.h
+++ b/drd/drd_bitmap.h
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -140,8 +140,7 @@
|| defined(VGA_mips32)
#define BITS_PER_BITS_PER_UWORD 5
#elif defined(VGA_amd64) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \
- || defined(VGA_s390x) || defined(VGA_mips64) || defined(VGA_arm64) \
- || defined(VGA_tilegx)
+ || defined(VGA_s390x) || defined(VGA_mips64) || defined(VGA_arm64)
#define BITS_PER_BITS_PER_UWORD 6
#else
#error Unknown platform.
diff --git a/drd/drd_clientobj.c b/drd/drd_clientobj.c
index 7bc1018..decd436 100644
--- a/drd/drd_clientobj.c
+++ b/drd/drd_clientobj.c
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_clientobj.h b/drd/drd_clientobj.h
index 16fe562..1425da2 100644
--- a/drd/drd_clientobj.h
+++ b/drd/drd_clientobj.h
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_clientreq.c b/drd/drd_clientreq.c
index cd8dca4..70f8a10 100644
--- a/drd/drd_clientreq.c
+++ b/drd/drd_clientreq.c
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -68,8 +68,7 @@
* DRD's handler for Valgrind client requests. The code below handles both
* DRD's public and tool-internal client requests.
*/
-#if defined(VGP_mips32_linux) || defined(VGP_mips64_linux) || \
- defined(VGP_tilegx_linux)
+#if defined(VGP_mips32_linux) || defined(VGP_mips64_linux)
/* There is a cse related issue in gcc for MIPS. Optimization level
has to be lowered, so cse related optimizations are not
included. */
@@ -85,7 +84,7 @@
|| (VG_USERREQ__GDB_MONITOR_COMMAND == arg[0]
&& vg_tid == VG_INVALID_THREADID));
/* Check the consistency of vg_tid and drd_tid, unless
- vgdb has forced the invokation of a gdb monitor cmd
+ vgdb has forced the invocation of a gdb monitor cmd
when no threads was running (i.e. all threads blocked
in a syscall. In such a case, vg_tid is invalid,
its conversion to a drd thread id gives also an invalid
diff --git a/drd/drd_clientreq.h b/drd/drd_clientreq.h
index 5d9b9b3..04078b9 100644
--- a/drd/drd_clientreq.h
+++ b/drd/drd_clientreq.h
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_cond.c b/drd/drd_cond.c
index efc8e23..4aae526 100644
--- a/drd/drd_cond.c
+++ b/drd/drd_cond.c
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_cond.h b/drd/drd_cond.h
index 3f5857d..6f5af43 100644
--- a/drd/drd_cond.h
+++ b/drd/drd_cond.h
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_darwin_intercepts.c b/drd/drd_darwin_intercepts.c
index 25ce9fb..f70adc3 100644
--- a/drd/drd_darwin_intercepts.c
+++ b/drd/drd_darwin_intercepts.c
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_error.c b/drd/drd_error.c
index cec3a2b..0dfab2c 100644
--- a/drd/drd_error.c
+++ b/drd/drd_error.c
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_error.h b/drd/drd_error.h
index 7f80d44..7a2bbac 100644
--- a/drd/drd_error.h
+++ b/drd/drd_error.h
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_hb.c b/drd/drd_hb.c
index 5688feb..819b3c0 100644
--- a/drd/drd_hb.c
+++ b/drd/drd_hb.c
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_hb.h b/drd/drd_hb.h
index 86432fc..e45ba17 100644
--- a/drd/drd_hb.h
+++ b/drd/drd_hb.h
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_libstdcxx_intercepts.c b/drd/drd_libstdcxx_intercepts.c
index 82a583d..354f8da 100644
--- a/drd/drd_libstdcxx_intercepts.c
+++ b/drd/drd_libstdcxx_intercepts.c
@@ -5,7 +5,7 @@
/*
This file is part of DRD, a thread error detector.
- Copyright (C) 2014-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2014-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_load_store.c b/drd/drd_load_store.c
index 928e3d6..051f4f0 100644
--- a/drd/drd_load_store.c
+++ b/drd/drd_load_store.c
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -55,8 +55,6 @@
#define STACK_POINTER_OFFSET OFFSET_mips32_r29
#elif defined(VGA_mips64)
#define STACK_POINTER_OFFSET OFFSET_mips64_r29
-#elif defined(VGA_tilegx)
-#define STACK_POINTER_OFFSET OFFSET_tilegx_r54
#else
#error Unknown architecture.
#endif
diff --git a/drd/drd_load_store.h b/drd/drd_load_store.h
index 9e649e8..31f846b 100644
--- a/drd/drd_load_store.h
+++ b/drd/drd_load_store.h
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_main.c b/drd/drd_main.c
index 69b7f45..79bdce2 100644
--- a/drd/drd_main.c
+++ b/drd/drd_main.c
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -829,7 +829,7 @@
VG_(details_name) ("drd");
VG_(details_version) (NULL);
VG_(details_description) ("a thread error detector");
- VG_(details_copyright_author)("Copyright (C) 2006-2015, and GNU GPL'd,"
+ VG_(details_copyright_author)("Copyright (C) 2006-2017, and GNU GPL'd,"
" by Bart Van Assche.");
VG_(details_bug_reports_to) (VG_BUGS_TO);
diff --git a/drd/drd_malloc_wrappers.c b/drd/drd_malloc_wrappers.c
index e742ed7..9585cd2 100644
--- a/drd/drd_malloc_wrappers.c
+++ b/drd/drd_malloc_wrappers.c
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_malloc_wrappers.h b/drd/drd_malloc_wrappers.h
index 79bb67d..100ac66 100644
--- a/drd/drd_malloc_wrappers.h
+++ b/drd/drd_malloc_wrappers.h
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_mutex.c b/drd/drd_mutex.c
index 4fe30e5..2e9eecc 100644
--- a/drd/drd_mutex.c
+++ b/drd/drd_mutex.c
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_mutex.h b/drd/drd_mutex.h
index e2bbc1b..71503bc 100644
--- a/drd/drd_mutex.h
+++ b/drd/drd_mutex.h
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_pthread_intercepts.c b/drd/drd_pthread_intercepts.c
index 2793660..d6abd43 100644
--- a/drd/drd_pthread_intercepts.c
+++ b/drd/drd_pthread_intercepts.c
@@ -5,7 +5,7 @@
/*
This file is part of DRD, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -228,7 +228,7 @@
static void DRD_(init)(void) __attribute__((constructor));
static void DRD_(check_threading_library)(void);
-static void DRD_(set_main_thread_state)(void);
+static void DRD_(set_pthread_id)(void);
static void DRD_(sema_init)(DrdSema* sema);
static void DRD_(sema_destroy)(DrdSema* sema);
static void DRD_(sema_down)(DrdSema* sema);
@@ -250,7 +250,7 @@
static void DRD_(init)(void)
{
DRD_(check_threading_library)();
- DRD_(set_main_thread_state)();
+ DRD_(set_pthread_id)();
#if defined(VGO_solaris)
if ((DRD_(rtld_bind_guard) == NULL) || (DRD_(rtld_bind_clear) == NULL)) {
fprintf(stderr,
@@ -501,12 +501,10 @@
}
/**
- * The main thread is the only thread not created by pthread_create().
- * Update DRD's state information about the main thread.
+ * Update DRD's state information about the current thread.
*/
-static void DRD_(set_main_thread_state)(void)
+static void DRD_(set_pthread_id)(void)
{
- // Make sure that DRD knows about the main thread's POSIX thread ID.
VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__SET_PTHREADID,
pthread_self(), 0, 0, 0, 0);
}
@@ -558,6 +556,14 @@
assert(thread_args.detachstate == PTHREAD_CREATE_JOINABLE
|| thread_args.detachstate == PTHREAD_CREATE_DETACHED);
+ /*
+ * The DRD_(set_pthread_id)() from DRD_(init)() may encounter that
+ * pthread_self() == 0, e.g. when the main program is not linked with the
+ * pthread library and when a pthread_create() call occurs from within a
+ * shared library. Hence call DRD_(set_pthread_id)() again to ensure that
+ * DRD knows the identity of the current thread. See also B.Z. 356374.
+ */
+ DRD_(set_pthread_id)();
DRD_(entering_pthread_create)();
CALL_FN_W_WWWW(ret, fn, thread, attr, DRD_(thread_wrapper), &thread_args);
DRD_(left_pthread_create)();
diff --git a/drd/drd_qtcore_intercepts.c b/drd/drd_qtcore_intercepts.c
index 9a6b8e9..ed80a6f 100644
--- a/drd/drd_qtcore_intercepts.c
+++ b/drd/drd_qtcore_intercepts.c
@@ -5,7 +5,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_rwlock.c b/drd/drd_rwlock.c
index 30c0f20..fd09e0a 100644
--- a/drd/drd_rwlock.c
+++ b/drd/drd_rwlock.c
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_rwlock.h b/drd/drd_rwlock.h
index 8728c9c..e3e2b88 100644
--- a/drd/drd_rwlock.h
+++ b/drd/drd_rwlock.h
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_segment.c b/drd/drd_segment.c
index a6c0bbc..9d81b66 100644
--- a/drd/drd_segment.c
+++ b/drd/drd_segment.c
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_segment.h b/drd/drd_segment.h
index de265db..420e673 100644
--- a/drd/drd_segment.h
+++ b/drd/drd_segment.h
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_semaphore.c b/drd/drd_semaphore.c
index f5bad6c..7125381 100644
--- a/drd/drd_semaphore.c
+++ b/drd/drd_semaphore.c
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_semaphore.h b/drd/drd_semaphore.h
index aa6b6f3..7185405 100644
--- a/drd/drd_semaphore.h
+++ b/drd/drd_semaphore.h
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_strmem_intercepts.c b/drd/drd_strmem_intercepts.c
index a538134..6150f81 100644
--- a/drd/drd_strmem_intercepts.c
+++ b/drd/drd_strmem_intercepts.c
@@ -9,7 +9,7 @@
from memchec/mc_replace_strmem.c, which has the following copyright
notice:
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/drd/drd_suppression.c b/drd/drd_suppression.c
index c879078..df5ad3d 100644
--- a/drd/drd_suppression.c
+++ b/drd/drd_suppression.c
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_thread.c b/drd/drd_thread.c
index 9bb3200..9ada77d 100644
--- a/drd/drd_thread.c
+++ b/drd/drd_thread.c
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -602,8 +602,8 @@
/**
* Store the POSIX thread ID for the specified thread.
*
- * @note This function can be called two times for the same thread -- see also
- * the comment block preceding the pthread_create() wrapper in
+ * @note This function can be called multiple times for the same thread -- see
+ * also the comment block preceding the pthread_create() wrapper in
* drd_pthread_intercepts.c.
*/
void DRD_(thread_set_pthreadid)(const DrdThreadId tid, const PThreadId ptid)
@@ -613,6 +613,10 @@
tl_assert(DRD_(g_threadinfo)[tid].pt_threadid == INVALID_POSIX_THREADID
|| DRD_(g_threadinfo)[tid].pt_threadid == ptid);
tl_assert(ptid != INVALID_POSIX_THREADID);
+ if (DRD_(g_threadinfo)[tid].posix_thread_exists) {
+ tl_assert(DRD_(g_threadinfo)[tid].pt_threadid == ptid);
+ return;
+ }
DRD_(g_threadinfo)[tid].posix_thread_exists = True;
DRD_(g_threadinfo)[tid].pt_threadid = ptid;
diff --git a/drd/drd_thread.h b/drd/drd_thread.h
index eece0a4..b91caa9 100644
--- a/drd/drd_thread.h
+++ b/drd/drd_thread.h
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -88,9 +88,9 @@
* a corresponding OS thread that is detached.
*/
Bool detached_posix_thread;
- /** Wether recording of memory load accesses is currently enabled. */
+ /** Whether recording of memory load accesses is currently enabled. */
Bool is_recording_loads;
- /** Wether recording of memory load accesses is currently enabled. */
+ /** Whether recording of memory load accesses is currently enabled. */
Bool is_recording_stores;
/** pthread_create() nesting level. */
Int pthread_create_nesting_level;
diff --git a/drd/drd_thread_bitmap.h b/drd/drd_thread_bitmap.h
index dce884e..9a41b7c 100644
--- a/drd/drd_thread_bitmap.h
+++ b/drd/drd_thread_bitmap.h
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_vc.c b/drd/drd_vc.c
index 49e8aa3..f238ecd 100644
--- a/drd/drd_vc.c
+++ b/drd/drd_vc.c
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/drd_vc.h b/drd/drd_vc.h
index fe3cf0b..c51079b 100644
--- a/drd/drd_vc.h
+++ b/drd/drd_vc.h
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/pub_drd_bitmap.h b/drd/pub_drd_bitmap.h
index ac5918b..ddf01f5 100644
--- a/drd/pub_drd_bitmap.h
+++ b/drd/pub_drd_bitmap.h
@@ -1,7 +1,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2015 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2017 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/drd/tests/Makefile.am b/drd/tests/Makefile.am
index 13620dc..bafa412 100644
--- a/drd/tests/Makefile.am
+++ b/drd/tests/Makefile.am
@@ -19,7 +19,8 @@
noinst_HEADERS = \
tsan_thread_wrappers_pthread.h \
- unified_annotations.h
+ unified_annotations.h \
+ dlopen_lib.h
EXTRA_DIST = \
annotate_barrier.stderr.exp \
@@ -103,6 +104,9 @@
custom_alloc.vgtest \
custom_alloc_fiw.stderr.exp \
custom_alloc_fiw.vgtest \
+ dlopen.stderr.exp \
+ dlopen.stdout.exp \
+ dlopen.vgtest \
fp_race.stderr.exp \
fp_race.stderr.exp-mips32-be \
fp_race.stderr.exp-mips32-le \
@@ -361,6 +365,8 @@
bug-235681 \
custom_alloc \
concurrent_close \
+ dlopen_main \
+ dlopen_lib.so \
fp_race \
free_is_write \
hold_lock \
@@ -455,6 +461,10 @@
concurrent_close_SOURCES = concurrent_close.cpp
+dlopen_main_LDADD = -ldl
+dlopen_lib_so_SOURCES = dlopen_lib.c
+dlopen_lib_so_CFLAGS = -fPIC
+dlopen_lib_so_LDFLAGS = -shared -fPIC
monitor_example_SOURCES = monitor_example.cpp
new_delete_SOURCES = new_delete.cpp
new_delete_CXXFLAGS = $(AM_CXXFLAGS) @FLAG_W_NO_MISMATCHED_NEW_DELETE@
diff --git a/drd/tests/Makefile.in b/drd/tests/Makefile.in
index 3073e38..fae2ccd 100644
--- a/drd/tests/Makefile.in
+++ b/drd/tests/Makefile.in
@@ -112,7 +112,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -126,7 +126,8 @@
annotate_publish_hg$(EXEEXT) annotate_static$(EXEEXT) \
annotate_trace_memory$(EXEEXT) bug-235681$(EXEEXT) \
custom_alloc$(EXEEXT) concurrent_close$(EXEEXT) \
- fp_race$(EXEEXT) free_is_write$(EXEEXT) hold_lock$(EXEEXT) \
+ dlopen_main$(EXEEXT) dlopen_lib.so$(EXEEXT) fp_race$(EXEEXT) \
+ free_is_write$(EXEEXT) hold_lock$(EXEEXT) \
linuxthreads_det$(EXEEXT) local_static$(EXEEXT) \
memory_allocation$(EXEEXT) monitor_example$(EXEEXT) \
new_delete$(EXEEXT) pth_broadcast$(EXEEXT) \
@@ -294,6 +295,15 @@
custom_alloc_OBJECTS = custom_alloc.$(OBJEXT)
custom_alloc_LDADD = $(LDADD)
custom_alloc_DEPENDENCIES =
+am_dlopen_lib_so_OBJECTS = dlopen_lib_so-dlopen_lib.$(OBJEXT)
+dlopen_lib_so_OBJECTS = $(am_dlopen_lib_so_OBJECTS)
+dlopen_lib_so_LDADD = $(LDADD)
+dlopen_lib_so_DEPENDENCIES =
+dlopen_lib_so_LINK = $(CCLD) $(dlopen_lib_so_CFLAGS) $(CFLAGS) \
+ $(dlopen_lib_so_LDFLAGS) $(LDFLAGS) -o $@
+dlopen_main_SOURCES = dlopen_main.c
+dlopen_main_OBJECTS = dlopen_main.$(OBJEXT)
+dlopen_main_DEPENDENCIES =
fp_race_SOURCES = fp_race.c
fp_race_OBJECTS = fp_race.$(OBJEXT)
fp_race_LDADD = $(LDADD)
@@ -579,17 +589,17 @@
$(annotate_smart_pointer_SOURCES) $(annotate_static_SOURCES) \
annotate_trace_memory.c atomic_var.c $(boost_thread_SOURCES) \
bug-235681.c circular_buffer.c $(concurrent_close_SOURCES) \
- custom_alloc.c fp_race.c free_is_write.c hold_lock.c \
- linuxthreads_det.c $(local_static_SOURCES) matinv.c \
- memory_allocation.c $(monitor_example_SOURCES) \
- $(new_delete_SOURCES) omp_matinv.c omp_prime.c omp_printf.c \
- pth_barrier.c pth_barrier_race.c pth_barrier_reinit.c \
- pth_barrier_thr_cr.c pth_broadcast.c pth_cancel_locked.c \
- pth_cleanup_handler.c pth_cond_destroy_busy.c pth_cond_race.c \
- pth_create_chain.c pth_create_glibc_2_0.c pth_detached.c \
- pth_detached3.c pth_detached_sem.c \
- pth_inconsistent_cond_wait.c pth_mutex_reinit.c \
- pth_process_shared_mutex.c pth_spinlock.c \
+ custom_alloc.c $(dlopen_lib_so_SOURCES) dlopen_main.c \
+ fp_race.c free_is_write.c hold_lock.c linuxthreads_det.c \
+ $(local_static_SOURCES) matinv.c memory_allocation.c \
+ $(monitor_example_SOURCES) $(new_delete_SOURCES) omp_matinv.c \
+ omp_prime.c omp_printf.c pth_barrier.c pth_barrier_race.c \
+ pth_barrier_reinit.c pth_barrier_thr_cr.c pth_broadcast.c \
+ pth_cancel_locked.c pth_cleanup_handler.c \
+ pth_cond_destroy_busy.c pth_cond_race.c pth_create_chain.c \
+ pth_create_glibc_2_0.c pth_detached.c pth_detached3.c \
+ pth_detached_sem.c pth_inconsistent_cond_wait.c \
+ pth_mutex_reinit.c pth_process_shared_mutex.c pth_spinlock.c \
pth_uninitialized_cond.c recursive_mutex.c rwlock_race.c \
rwlock_test.c rwlock_type_checking.c sem_as_mutex.c sem_open.c \
$(sem_wait_SOURCES) sigalrm.c $(std_atomic_SOURCES) \
@@ -604,7 +614,8 @@
$(annotate_static_SOURCES) annotate_trace_memory.c \
atomic_var.c $(am__boost_thread_SOURCES_DIST) bug-235681.c \
circular_buffer.c $(concurrent_close_SOURCES) custom_alloc.c \
- fp_race.c free_is_write.c hold_lock.c linuxthreads_det.c \
+ $(dlopen_lib_so_SOURCES) dlopen_main.c fp_race.c \
+ free_is_write.c hold_lock.c linuxthreads_det.c \
$(local_static_SOURCES) matinv.c memory_allocation.c \
$(monitor_example_SOURCES) $(new_delete_SOURCES) omp_matinv.c \
omp_prime.c omp_printf.c pth_barrier.c pth_barrier_race.c \
@@ -693,6 +704,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -863,6 +875,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -873,6 +886,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -947,8 +961,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -993,7 +1005,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
@@ -1036,7 +1047,8 @@
noinst_HEADERS = \
tsan_thread_wrappers_pthread.h \
- unified_annotations.h
+ unified_annotations.h \
+ dlopen_lib.h
EXTRA_DIST = \
annotate_barrier.stderr.exp \
@@ -1120,6 +1132,9 @@
custom_alloc.vgtest \
custom_alloc_fiw.stderr.exp \
custom_alloc_fiw.vgtest \
+ dlopen.stderr.exp \
+ dlopen.stdout.exp \
+ dlopen.vgtest \
fp_race.stderr.exp \
fp_race.stderr.exp-mips32-be \
fp_race.stderr.exp-mips32-le \
@@ -1368,6 +1383,10 @@
LDADD = -lpthread
concurrent_close_SOURCES = concurrent_close.cpp
+dlopen_main_LDADD = -ldl
+dlopen_lib_so_SOURCES = dlopen_lib.c
+dlopen_lib_so_CFLAGS = -fPIC
+dlopen_lib_so_LDFLAGS = -shared -fPIC
monitor_example_SOURCES = monitor_example.cpp
new_delete_SOURCES = new_delete.cpp
new_delete_CXXFLAGS = $(AM_CXXFLAGS) @FLAG_W_NO_MISMATCHED_NEW_DELETE@
@@ -1528,6 +1547,14 @@
@rm -f custom_alloc$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(custom_alloc_OBJECTS) $(custom_alloc_LDADD) $(LIBS)
+dlopen_lib.so$(EXEEXT): $(dlopen_lib_so_OBJECTS) $(dlopen_lib_so_DEPENDENCIES) $(EXTRA_dlopen_lib_so_DEPENDENCIES)
+ @rm -f dlopen_lib.so$(EXEEXT)
+ $(AM_V_CCLD)$(dlopen_lib_so_LINK) $(dlopen_lib_so_OBJECTS) $(dlopen_lib_so_LDADD) $(LIBS)
+
+dlopen_main$(EXEEXT): $(dlopen_main_OBJECTS) $(dlopen_main_DEPENDENCIES) $(EXTRA_dlopen_main_DEPENDENCIES)
+ @rm -f dlopen_main$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(dlopen_main_OBJECTS) $(dlopen_main_LDADD) $(LIBS)
+
fp_race$(EXEEXT): $(fp_race_OBJECTS) $(fp_race_DEPENDENCIES) $(EXTRA_fp_race_DEPENDENCIES)
@rm -f fp_race$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(fp_race_OBJECTS) $(fp_race_LDADD) $(LIBS)
@@ -1751,6 +1778,8 @@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/circular_buffer.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/concurrent_close.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/custom_alloc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dlopen_lib_so-dlopen_lib.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dlopen_main.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fp_race.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/free_is_write-free_is_write.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/hold_lock.Po@am__quote@
@@ -1818,6 +1847,20 @@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(COMPILE) -c -o $@ `$(CYGPATH_W) '$<'`
+dlopen_lib_so-dlopen_lib.o: dlopen_lib.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(dlopen_lib_so_CFLAGS) $(CFLAGS) -MT dlopen_lib_so-dlopen_lib.o -MD -MP -MF $(DEPDIR)/dlopen_lib_so-dlopen_lib.Tpo -c -o dlopen_lib_so-dlopen_lib.o `test -f 'dlopen_lib.c' || echo '$(srcdir)/'`dlopen_lib.c
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/dlopen_lib_so-dlopen_lib.Tpo $(DEPDIR)/dlopen_lib_so-dlopen_lib.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='dlopen_lib.c' object='dlopen_lib_so-dlopen_lib.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(dlopen_lib_so_CFLAGS) $(CFLAGS) -c -o dlopen_lib_so-dlopen_lib.o `test -f 'dlopen_lib.c' || echo '$(srcdir)/'`dlopen_lib.c
+
+dlopen_lib_so-dlopen_lib.obj: dlopen_lib.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(dlopen_lib_so_CFLAGS) $(CFLAGS) -MT dlopen_lib_so-dlopen_lib.obj -MD -MP -MF $(DEPDIR)/dlopen_lib_so-dlopen_lib.Tpo -c -o dlopen_lib_so-dlopen_lib.obj `if test -f 'dlopen_lib.c'; then $(CYGPATH_W) 'dlopen_lib.c'; else $(CYGPATH_W) '$(srcdir)/dlopen_lib.c'; fi`
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/dlopen_lib_so-dlopen_lib.Tpo $(DEPDIR)/dlopen_lib_so-dlopen_lib.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='dlopen_lib.c' object='dlopen_lib_so-dlopen_lib.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(dlopen_lib_so_CFLAGS) $(CFLAGS) -c -o dlopen_lib_so-dlopen_lib.obj `if test -f 'dlopen_lib.c'; then $(CYGPATH_W) 'dlopen_lib.c'; else $(CYGPATH_W) '$(srcdir)/dlopen_lib.c'; fi`
+
free_is_write-free_is_write.o: free_is_write.c
@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(free_is_write_CFLAGS) $(CFLAGS) -MT free_is_write-free_is_write.o -MD -MP -MF $(DEPDIR)/free_is_write-free_is_write.Tpo -c -o free_is_write-free_is_write.o `test -f 'free_is_write.c' || echo '$(srcdir)/'`free_is_write.c
@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/free_is_write-free_is_write.Tpo $(DEPDIR)/free_is_write-free_is_write.Po
diff --git a/drd/tests/annotate_smart_pointer.cpp b/drd/tests/annotate_smart_pointer.cpp
index 4334302..ccefc47 100644
--- a/drd/tests/annotate_smart_pointer.cpp
+++ b/drd/tests/annotate_smart_pointer.cpp
@@ -7,7 +7,7 @@
* - whether or not the smart pointer objects are shared over threads.
* - whether or not the smart pointer object itself is thread-safe.
*
- * Most smart pointer implemenations are not thread-safe
+ * Most smart pointer implementations are not thread-safe
* (e.g. boost::shared_ptr<>, tr1::shared_ptr<> and the smart_ptr<>
* implementation below). This means that it is not safe to modify a shared
* pointer object that is shared over threads without proper synchronization.
diff --git a/drd/tests/bar_bad.vgtest b/drd/tests/bar_bad.vgtest
index 14cdf19..08be062 100644
--- a/drd/tests/bar_bad.vgtest
+++ b/drd/tests/bar_bad.vgtest
@@ -1,2 +1,3 @@
prereq: test -e ../../helgrind/tests/bar_bad && ./supported_libpthread
prog: ../../helgrind/tests/bar_bad
+vgopts: --fair-sched=try
diff --git a/drd/tests/bar_bad_xml.vgtest b/drd/tests/bar_bad_xml.vgtest
index d626dc3..65e5c2d 100644
--- a/drd/tests/bar_bad_xml.vgtest
+++ b/drd/tests/bar_bad_xml.vgtest
@@ -1,4 +1,4 @@
prereq: test -e ../../helgrind/tests/bar_bad && ./supported_libpthread
-vgopts: --xml=yes --xml-fd=2
+vgopts: --xml=yes --xml-fd=2 --fair-sched=try
prog: ../../helgrind/tests/bar_bad
stderr_filter: ../../memcheck/tests/filter_xml
diff --git a/drd/tests/dlopen.stderr.exp b/drd/tests/dlopen.stderr.exp
new file mode 100644
index 0000000..d18786f
--- /dev/null
+++ b/drd/tests/dlopen.stderr.exp
@@ -0,0 +1,3 @@
+
+
+ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0)
diff --git a/drd/tests/dlopen.stdout.exp b/drd/tests/dlopen.stdout.exp
new file mode 100644
index 0000000..1f8a141
--- /dev/null
+++ b/drd/tests/dlopen.stdout.exp
@@ -0,0 +1,2 @@
+In main: creating thread 1
+Hello World! It's me, thread #1!
diff --git a/drd/tests/dlopen.vgtest b/drd/tests/dlopen.vgtest
new file mode 100644
index 0000000..ad114e8
--- /dev/null
+++ b/drd/tests/dlopen.vgtest
@@ -0,0 +1,4 @@
+prereq: test -e dlopen_main && ./supported_libpthread
+vgopts: --read-var-info=yes --check-stack-var=yes --show-confl-seg=no
+prog: dlopen_main ./dlopen_lib.so
+stderr_filter: filter_stderr
diff --git a/drd/tests/dlopen_lib.c b/drd/tests/dlopen_lib.c
new file mode 100644
index 0000000..ea18fc5
--- /dev/null
+++ b/drd/tests/dlopen_lib.c
@@ -0,0 +1,27 @@
+#include <stdio.h>
+#include <stdint.h>
+#include <pthread.h>
+#include "dlopen_lib.h"
+
+void *PrintHello(void *threadid)
+{
+ const long tid = (uintptr_t)threadid;
+
+ printf("Hello World! It's me, thread #%ld!\n", tid);
+ pthread_exit(NULL);
+}
+
+
+void foo()
+{
+ pthread_t thread;
+ int rc;
+ uintptr_t t = 1;
+
+ printf("In main: creating thread %ld\n", t);
+ rc = pthread_create(&thread, NULL, PrintHello, (void *)t);
+ if (rc)
+ printf("ERROR; return code from pthread_create() is %d\n", rc);
+ else
+ pthread_join(thread, NULL);
+}
diff --git a/drd/tests/dlopen_lib.h b/drd/tests/dlopen_lib.h
new file mode 100644
index 0000000..7fdb54e
--- /dev/null
+++ b/drd/tests/dlopen_lib.h
@@ -0,0 +1 @@
+extern void foo();
diff --git a/drd/tests/dlopen_main.c b/drd/tests/dlopen_main.c
new file mode 100644
index 0000000..f879735
--- /dev/null
+++ b/drd/tests/dlopen_main.c
@@ -0,0 +1,29 @@
+#include <stdlib.h>
+#include <stdio.h>
+#include <dlfcn.h>
+#include "dlopen_lib.h"
+
+int main(int argc, char **argv)
+{
+ const char *lib = argc > 1 ? argv[1] : "./libfoo.so";
+ void *handle;
+ void (*function)();
+ const char *error;
+
+ handle = dlopen(lib, RTLD_NOW);
+ if (!handle) {
+ fputs (dlerror(), stderr);
+ exit(1);
+ }
+
+ function = dlsym(handle, "foo");
+ error = dlerror();
+ if (error) {
+ fputs(error, stderr);
+ exit(1);
+ }
+
+ (*function)();
+ dlclose(handle);
+ return 0;
+}
diff --git a/drd/tests/monitor_example.cpp b/drd/tests/monitor_example.cpp
index 4a660cc..3237d16 100644
--- a/drd/tests/monitor_example.cpp
+++ b/drd/tests/monitor_example.cpp
@@ -16,7 +16,7 @@
This file is part of DRD, a heavyweight Valgrind tool for detecting
errors in multithreaded programs.
- Copyright (C) 2008-2009 Bart Van Assche. All rights reserved.
+ Copyright (C) 2008-2017 Bart Van Assche. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
diff --git a/drd/tests/pth_cond_destroy_busy.vgtest b/drd/tests/pth_cond_destroy_busy.vgtest
index eafbd74..f3cf778 100644
--- a/drd/tests/pth_cond_destroy_busy.vgtest
+++ b/drd/tests/pth_cond_destroy_busy.vgtest
@@ -1,2 +1,2 @@
-prereq: ./supported_libpthread
+prereq: ./supported_libpthread && ! ../../tests/libc_test glibc 2.24.90
prog: pth_cond_destroy_busy
diff --git a/drd/tests/tc23_bogus_condwait.stderr.exp-darwin-amd64 b/drd/tests/tc23_bogus_condwait.stderr.exp-darwin-amd64
index d305391..3310390 100644
--- a/drd/tests/tc23_bogus_condwait.stderr.exp-darwin-amd64
+++ b/drd/tests/tc23_bogus_condwait.stderr.exp-darwin-amd64
@@ -8,7 +8,7 @@
by 0x........: main (tc23_bogus_condwait.c:72)
mutex 0x........ was first observed at:
at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
- by 0x........: main (tc23_bogus_condwait.c:51)
+ by 0x........: main (tc23_bogus_condwait.c:54)
Thread 3:
Probably a race condition: condition variable 0x........ has been signaled but the associated mutex 0x........ is not locked by the signalling thread.
@@ -20,7 +20,7 @@
by 0x........: main (tc23_bogus_condwait.c:56)
mutex 0x........ was first observed at:
at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
- by 0x........: main (tc23_bogus_condwait.c:51)
+ by 0x........: main (tc23_bogus_condwait.c:54)
Thread 1:
The object at address 0x........ is not a mutex.
diff --git a/drd/tests/tc23_bogus_condwait.stderr.exp-darwin-x86 b/drd/tests/tc23_bogus_condwait.stderr.exp-darwin-x86
index 577e146..2908dd8 100644
--- a/drd/tests/tc23_bogus_condwait.stderr.exp-darwin-x86
+++ b/drd/tests/tc23_bogus_condwait.stderr.exp-darwin-x86
@@ -8,7 +8,7 @@
by 0x........: main (tc23_bogus_condwait.c:72)
mutex 0x........ was first observed at:
at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
- by 0x........: main (tc23_bogus_condwait.c:51)
+ by 0x........: main (tc23_bogus_condwait.c:54)
Thread 3:
Probably a race condition: condition variable 0x........ has been signaled but the associated mutex 0x........ is not locked by the signalling thread.
@@ -20,7 +20,7 @@
by 0x........: main (tc23_bogus_condwait.c:56)
mutex 0x........ was first observed at:
at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
- by 0x........: main (tc23_bogus_condwait.c:51)
+ by 0x........: main (tc23_bogus_condwait.c:54)
Thread 1:
The object at address 0x........ is not a mutex.
diff --git a/drd/tests/tc23_bogus_condwait.stderr.exp-linux-ppc b/drd/tests/tc23_bogus_condwait.stderr.exp-linux-ppc
index fb4e73d..f78f6d7 100644
--- a/drd/tests/tc23_bogus_condwait.stderr.exp-linux-ppc
+++ b/drd/tests/tc23_bogus_condwait.stderr.exp-linux-ppc
@@ -18,7 +18,7 @@
by 0x........: main (tc23_bogus_condwait.c:72)
mutex 0x........ was first observed at:
at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
- by 0x........: main (tc23_bogus_condwait.c:51)
+ by 0x........: main (tc23_bogus_condwait.c:54)
The object at address 0x........ is not a mutex.
at 0x........: pthread_cond_wait (drd_pthread_intercepts.c:?)
diff --git a/drd/tests/tc23_bogus_condwait.stderr.exp-linux-x86 b/drd/tests/tc23_bogus_condwait.stderr.exp-linux-x86
index 1411151..753b589 100644
--- a/drd/tests/tc23_bogus_condwait.stderr.exp-linux-x86
+++ b/drd/tests/tc23_bogus_condwait.stderr.exp-linux-x86
@@ -18,7 +18,7 @@
by 0x........: main (tc23_bogus_condwait.c:72)
mutex 0x........ was first observed at:
at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
- by 0x........: main (tc23_bogus_condwait.c:51)
+ by 0x........: main (tc23_bogus_condwait.c:54)
Thread 3:
Probably a race condition: condition variable 0x........ has been signaled but the associated mutex 0x........ is not locked by the signalling thread.
@@ -30,7 +30,7 @@
by 0x........: main (tc23_bogus_condwait.c:56)
mutex 0x........ was first observed at:
at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
- by 0x........: main (tc23_bogus_condwait.c:51)
+ by 0x........: main (tc23_bogus_condwait.c:54)
Thread 1:
The object at address 0x........ is not a mutex.
diff --git a/drd/tests/unit_bitmap.c b/drd/tests/unit_bitmap.c
index 6e8064a..5778753 100644
--- a/drd/tests/unit_bitmap.c
+++ b/drd/tests/unit_bitmap.c
@@ -44,6 +44,8 @@
abort();
}
+Int VG_(strcmp)( const HChar* s1, const HChar* s2 )
+{ return strcmp(s1, s2); }
void* VG_(memset)(void *s, Int c, SizeT sz)
{ return memset(s, c, sz); }
void* VG_(memcpy)(void *d, const void *s, SizeT sz)
diff --git a/exp-bbv/Makefile.in b/exp-bbv/Makefile.in
index 2ca6537..9fbf98e 100644
--- a/exp-bbv/Makefile.in
+++ b/exp-bbv/Makefile.in
@@ -284,6 +284,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -455,6 +456,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -465,6 +467,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -539,8 +542,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -585,7 +586,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
@@ -663,9 +663,6 @@
-static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \
@FLAG_M64@
-TOOL_LDFLAGS_TILEGX_LINUX = \
- $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-
TOOL_LDFLAGS_X86_SOLARIS = \
$(TOOL_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
@@ -720,9 +717,6 @@
LIBREPLACEMALLOC_MIPS64_LINUX = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a
-LIBREPLACEMALLOC_TILEGX_LINUX = \
- $(top_builddir)/coregrind/libreplacemalloc_toolpreload-tilegx-linux.a
-
LIBREPLACEMALLOC_X86_SOLARIS = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-solaris.a
@@ -785,11 +779,6 @@
$(LIBREPLACEMALLOC_MIPS64_LINUX) \
-Wl,--no-whole-archive
-LIBREPLACEMALLOC_LDFLAGS_TILEGX_LINUX = \
- -Wl,--whole-archive \
- $(LIBREPLACEMALLOC_TILEGX_LINUX) \
- -Wl,--no-whole-archive
-
LIBREPLACEMALLOC_LDFLAGS_X86_SOLARIS = \
-Wl,--whole-archive \
$(LIBREPLACEMALLOC_X86_SOLARIS) \
diff --git a/exp-bbv/bbv_main.c b/exp-bbv/bbv_main.c
index 5a55593..fa3a077 100644
--- a/exp-bbv/bbv_main.c
+++ b/exp-bbv/bbv_main.c
@@ -8,10 +8,10 @@
This file is part of BBV, a Valgrind tool for generating SimPoint
basic block vectors.
- Copyright (C) 2006-2015 Vince Weaver
+ Copyright (C) 2006-2017 Vince Weaver
vince _at_ csl.cornell.edu
- pcfile code is Copyright (C) 2006-2015 Oriol Prat
+ pcfile code is Copyright (C) 2006-2017 Oriol Prat
oriol.prat _at _ bsc.es
This program is free software; you can redistribute it and/or
@@ -597,7 +597,7 @@
VG_(details_version) (NULL);
VG_(details_description) ("a SimPoint basic block vector generator");
VG_(details_copyright_author)(
- "Copyright (C) 2006-2015 Vince Weaver");
+ "Copyright (C) 2006-2017 Vince Weaver");
VG_(details_bug_reports_to) (VG_BUGS_TO);
VG_(basic_tool_funcs) (bbv_post_clo_init,
diff --git a/exp-bbv/tests/Makefile.in b/exp-bbv/tests/Makefile.in
index 981c3e9..1f51d05 100644
--- a/exp-bbv/tests/Makefile.in
+++ b/exp-bbv/tests/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -266,6 +266,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -436,6 +437,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -446,6 +448,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -520,8 +523,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -566,7 +567,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/exp-bbv/tests/amd64-linux/Makefile.am b/exp-bbv/tests/amd64-linux/Makefile.am
index 7ff8966..67bcc02 100644
--- a/exp-bbv/tests/amd64-linux/Makefile.am
+++ b/exp-bbv/tests/amd64-linux/Makefile.am
@@ -40,3 +40,10 @@
check_PROGRAMS += ll
ll_SOURCES = ll.S
endif
+
+clone_test_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
+complex_rep_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
+fldcw_check_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
+ll_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
+million_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
+rep_prefix_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
diff --git a/exp-bbv/tests/amd64-linux/Makefile.in b/exp-bbv/tests/amd64-linux/Makefile.in
index 64241c9..bd9a307 100644
--- a/exp-bbv/tests/amd64-linux/Makefile.in
+++ b/exp-bbv/tests/amd64-linux/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -143,22 +143,34 @@
am_clone_test_OBJECTS = clone_test.$(OBJEXT)
clone_test_OBJECTS = $(am_clone_test_OBJECTS)
clone_test_LDADD = $(LDADD)
+clone_test_LINK = $(CCLD) $(clone_test_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
am_complex_rep_OBJECTS = complex_rep.$(OBJEXT)
complex_rep_OBJECTS = $(am_complex_rep_OBJECTS)
complex_rep_LDADD = $(LDADD)
+complex_rep_LINK = $(CCLD) $(complex_rep_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
am_fldcw_check_OBJECTS = fldcw_check.$(OBJEXT)
fldcw_check_OBJECTS = $(am_fldcw_check_OBJECTS)
fldcw_check_LDADD = $(LDADD)
+fldcw_check_LINK = $(CCLD) $(fldcw_check_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
am__ll_SOURCES_DIST = ll.S
@COMPILER_IS_ICC_FALSE@am_ll_OBJECTS = ll.$(OBJEXT)
ll_OBJECTS = $(am_ll_OBJECTS)
ll_LDADD = $(LDADD)
+ll_LINK = $(CCLD) $(ll_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o \
+ $@
am_million_OBJECTS = million.$(OBJEXT)
million_OBJECTS = $(am_million_OBJECTS)
million_LDADD = $(LDADD)
+million_LINK = $(CCLD) $(million_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
am_rep_prefix_OBJECTS = rep_prefix.$(OBJEXT)
rep_prefix_OBJECTS = $(am_rep_prefix_OBJECTS)
rep_prefix_LDADD = $(LDADD)
+rep_prefix_LINK = $(CCLD) $(rep_prefix_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
SCRIPTS = $(dist_noinst_SCRIPTS)
AM_V_P = $(am__v_P_@AM_V@)
am__v_P_ = $(am__v_P_@AM_DEFAULT_V@)
@@ -271,6 +283,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -441,6 +454,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -451,6 +465,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -525,8 +540,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -571,7 +584,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
@@ -618,6 +630,12 @@
million_SOURCES = million.S
rep_prefix_SOURCES = rep_prefix.S
@COMPILER_IS_ICC_FALSE@ll_SOURCES = ll.S
+clone_test_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
+complex_rep_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
+fldcw_check_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
+ll_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
+million_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
+rep_prefix_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
all: all-am
.SUFFIXES:
@@ -658,27 +676,27 @@
clone_test$(EXEEXT): $(clone_test_OBJECTS) $(clone_test_DEPENDENCIES) $(EXTRA_clone_test_DEPENDENCIES)
@rm -f clone_test$(EXEEXT)
- $(AM_V_CCLD)$(LINK) $(clone_test_OBJECTS) $(clone_test_LDADD) $(LIBS)
+ $(AM_V_CCLD)$(clone_test_LINK) $(clone_test_OBJECTS) $(clone_test_LDADD) $(LIBS)
complex_rep$(EXEEXT): $(complex_rep_OBJECTS) $(complex_rep_DEPENDENCIES) $(EXTRA_complex_rep_DEPENDENCIES)
@rm -f complex_rep$(EXEEXT)
- $(AM_V_CCLD)$(LINK) $(complex_rep_OBJECTS) $(complex_rep_LDADD) $(LIBS)
+ $(AM_V_CCLD)$(complex_rep_LINK) $(complex_rep_OBJECTS) $(complex_rep_LDADD) $(LIBS)
fldcw_check$(EXEEXT): $(fldcw_check_OBJECTS) $(fldcw_check_DEPENDENCIES) $(EXTRA_fldcw_check_DEPENDENCIES)
@rm -f fldcw_check$(EXEEXT)
- $(AM_V_CCLD)$(LINK) $(fldcw_check_OBJECTS) $(fldcw_check_LDADD) $(LIBS)
+ $(AM_V_CCLD)$(fldcw_check_LINK) $(fldcw_check_OBJECTS) $(fldcw_check_LDADD) $(LIBS)
ll$(EXEEXT): $(ll_OBJECTS) $(ll_DEPENDENCIES) $(EXTRA_ll_DEPENDENCIES)
@rm -f ll$(EXEEXT)
- $(AM_V_CCLD)$(LINK) $(ll_OBJECTS) $(ll_LDADD) $(LIBS)
+ $(AM_V_CCLD)$(ll_LINK) $(ll_OBJECTS) $(ll_LDADD) $(LIBS)
million$(EXEEXT): $(million_OBJECTS) $(million_DEPENDENCIES) $(EXTRA_million_DEPENDENCIES)
@rm -f million$(EXEEXT)
- $(AM_V_CCLD)$(LINK) $(million_OBJECTS) $(million_LDADD) $(LIBS)
+ $(AM_V_CCLD)$(million_LINK) $(million_OBJECTS) $(million_LDADD) $(LIBS)
rep_prefix$(EXEEXT): $(rep_prefix_OBJECTS) $(rep_prefix_DEPENDENCIES) $(EXTRA_rep_prefix_DEPENDENCIES)
@rm -f rep_prefix$(EXEEXT)
- $(AM_V_CCLD)$(LINK) $(rep_prefix_OBJECTS) $(rep_prefix_LDADD) $(LIBS)
+ $(AM_V_CCLD)$(rep_prefix_LINK) $(rep_prefix_OBJECTS) $(rep_prefix_LDADD) $(LIBS)
mostlyclean-compile:
-rm -f *.$(OBJEXT)
diff --git a/exp-bbv/tests/arm-linux/Makefile.in b/exp-bbv/tests/arm-linux/Makefile.in
index 1a14596..4a6b5b4 100644
--- a/exp-bbv/tests/arm-linux/Makefile.in
+++ b/exp-bbv/tests/arm-linux/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -246,6 +246,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -416,6 +417,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -426,6 +428,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -500,8 +503,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -546,7 +547,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/exp-bbv/tests/ppc32-linux/Makefile.in b/exp-bbv/tests/ppc32-linux/Makefile.in
index 84936b1..6f1fdfc 100644
--- a/exp-bbv/tests/ppc32-linux/Makefile.in
+++ b/exp-bbv/tests/ppc32-linux/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -246,6 +246,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -416,6 +417,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -426,6 +428,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -500,8 +503,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -546,7 +547,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/exp-bbv/tests/x86-linux/Makefile.in b/exp-bbv/tests/x86-linux/Makefile.in
index a2d0dda..9b9ce57 100644
--- a/exp-bbv/tests/x86-linux/Makefile.in
+++ b/exp-bbv/tests/x86-linux/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -246,6 +246,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -416,6 +417,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -426,6 +428,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -500,8 +503,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -546,7 +547,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/exp-bbv/tests/x86/Makefile.in b/exp-bbv/tests/x86/Makefile.in
index bf56a1c..a045ce3 100644
--- a/exp-bbv/tests/x86/Makefile.in
+++ b/exp-bbv/tests/x86/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -255,6 +255,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -425,6 +426,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -435,6 +437,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -509,8 +512,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -555,7 +556,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/exp-dhat/Makefile.in b/exp-dhat/Makefile.in
index b125979..c5c43a5 100644
--- a/exp-dhat/Makefile.in
+++ b/exp-dhat/Makefile.in
@@ -308,6 +308,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -479,6 +480,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -489,6 +491,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -563,8 +566,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -609,7 +610,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
@@ -687,9 +687,6 @@
-static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \
@FLAG_M64@
-TOOL_LDFLAGS_TILEGX_LINUX = \
- $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-
TOOL_LDFLAGS_X86_SOLARIS = \
$(TOOL_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
@@ -744,9 +741,6 @@
LIBREPLACEMALLOC_MIPS64_LINUX = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a
-LIBREPLACEMALLOC_TILEGX_LINUX = \
- $(top_builddir)/coregrind/libreplacemalloc_toolpreload-tilegx-linux.a
-
LIBREPLACEMALLOC_X86_SOLARIS = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-solaris.a
@@ -809,11 +803,6 @@
$(LIBREPLACEMALLOC_MIPS64_LINUX) \
-Wl,--no-whole-archive
-LIBREPLACEMALLOC_LDFLAGS_TILEGX_LINUX = \
- -Wl,--whole-archive \
- $(LIBREPLACEMALLOC_TILEGX_LINUX) \
- -Wl,--no-whole-archive
-
LIBREPLACEMALLOC_LDFLAGS_X86_SOLARIS = \
-Wl,--whole-archive \
$(LIBREPLACEMALLOC_X86_SOLARIS) \
diff --git a/exp-dhat/dh_main.c b/exp-dhat/dh_main.c
index 1589fee..c23134b 100644
--- a/exp-dhat/dh_main.c
+++ b/exp-dhat/dh_main.c
@@ -7,7 +7,7 @@
This file is part of DHAT, a Valgrind tool for profiling the
heap usage of programs.
- Copyright (C) 2010-2015 Mozilla Inc
+ Copyright (C) 2010-2017 Mozilla Inc
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -1357,7 +1357,7 @@
VG_(details_version) (NULL);
VG_(details_description) ("a dynamic heap analysis tool");
VG_(details_copyright_author)(
- "Copyright (C) 2010-2015, and GNU GPL'd, by Mozilla Inc");
+ "Copyright (C) 2010-2017, and GNU GPL'd, by Mozilla Inc");
VG_(details_bug_reports_to) (VG_BUGS_TO);
// Basic functions.
diff --git a/exp-dhat/docs/dh-manual.xml b/exp-dhat/docs/dh-manual.xml
index 4836c39..66b7c68 100644
--- a/exp-dhat/docs/dh-manual.xml
+++ b/exp-dhat/docs/dh-manual.xml
@@ -389,7 +389,7 @@
</variablelist>
<para>One important point to note is that each allocation stack counts
-as a seperate allocation point. Because stacks by default have 12
+as a separate allocation point. Because stacks by default have 12
frames, this tends to spread data out over multiple allocation points.
You may want to use the flag --num-callers=4 or some such small
number, to reduce the spreading.</para>
diff --git a/exp-dhat/tests/Makefile.in b/exp-dhat/tests/Makefile.in
index 0ac8c23..57cf31f 100644
--- a/exp-dhat/tests/Makefile.in
+++ b/exp-dhat/tests/Makefile.in
@@ -163,6 +163,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
diff --git a/exp-sgcheck/Makefile.in b/exp-sgcheck/Makefile.in
index a7168e4..f34de63 100644
--- a/exp-sgcheck/Makefile.in
+++ b/exp-sgcheck/Makefile.in
@@ -327,6 +327,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -498,6 +499,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -508,6 +510,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -582,8 +585,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -628,7 +629,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
@@ -706,9 +706,6 @@
-static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \
@FLAG_M64@
-TOOL_LDFLAGS_TILEGX_LINUX = \
- $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-
TOOL_LDFLAGS_X86_SOLARIS = \
$(TOOL_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
@@ -763,9 +760,6 @@
LIBREPLACEMALLOC_MIPS64_LINUX = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a
-LIBREPLACEMALLOC_TILEGX_LINUX = \
- $(top_builddir)/coregrind/libreplacemalloc_toolpreload-tilegx-linux.a
-
LIBREPLACEMALLOC_X86_SOLARIS = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-solaris.a
@@ -828,11 +822,6 @@
$(LIBREPLACEMALLOC_MIPS64_LINUX) \
-Wl,--no-whole-archive
-LIBREPLACEMALLOC_LDFLAGS_TILEGX_LINUX = \
- -Wl,--whole-archive \
- $(LIBREPLACEMALLOC_TILEGX_LINUX) \
- -Wl,--no-whole-archive
-
LIBREPLACEMALLOC_LDFLAGS_X86_SOLARIS = \
-Wl,--whole-archive \
$(LIBREPLACEMALLOC_X86_SOLARIS) \
diff --git a/exp-sgcheck/h_intercepts.c b/exp-sgcheck/h_intercepts.c
index 2ec1836..81f846e 100644
--- a/exp-sgcheck/h_intercepts.c
+++ b/exp-sgcheck/h_intercepts.c
@@ -7,7 +7,7 @@
This file is part of Ptrcheck, a Valgrind tool for checking pointer
use in programs.
- Copyright (C) 2003-2015 Nicholas Nethercote
+ Copyright (C) 2003-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
diff --git a/exp-sgcheck/h_main.c b/exp-sgcheck/h_main.c
index 84a3cfc..073e66a 100644
--- a/exp-sgcheck/h_main.c
+++ b/exp-sgcheck/h_main.c
@@ -11,12 +11,12 @@
Initial version (Annelid):
- Copyright (C) 2003-2015 Nicholas Nethercote
+ Copyright (C) 2003-2017 Nicholas Nethercote
njn@valgrind.org
Valgrind-3.X port:
- Copyright (C) 2008-2015 OpenWorks Ltd
+ Copyright (C) 2008-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/exp-sgcheck/h_main.h b/exp-sgcheck/h_main.h
index ddba8a5..74af1f8 100644
--- a/exp-sgcheck/h_main.h
+++ b/exp-sgcheck/h_main.h
@@ -9,9 +9,9 @@
This file is part of Ptrcheck, a Valgrind tool for checking pointer
use in programs.
- Copyright (C) 2003-2015 Nicholas Nethercote
+ Copyright (C) 2003-2017 Nicholas Nethercote
njn@valgrind.org
- Copyright (C) 2008-2015 OpenWorks Ltd
+ Copyright (C) 2008-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/exp-sgcheck/pc_common.c b/exp-sgcheck/pc_common.c
index 827a3db..e5a3364 100644
--- a/exp-sgcheck/pc_common.c
+++ b/exp-sgcheck/pc_common.c
@@ -9,7 +9,7 @@
This file is part of Ptrcheck, a Valgrind tool for checking pointer
use in programs.
- Copyright (C) 2008-2015 OpenWorks Ltd
+ Copyright (C) 2008-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/exp-sgcheck/pc_common.h b/exp-sgcheck/pc_common.h
index 22e87b4..0af20f9 100644
--- a/exp-sgcheck/pc_common.h
+++ b/exp-sgcheck/pc_common.h
@@ -9,7 +9,7 @@
This file is part of Ptrcheck, a Valgrind tool for checking pointer
use in programs.
- Copyright (C) 2008-2015 OpenWorks Ltd
+ Copyright (C) 2008-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/exp-sgcheck/pc_main.c b/exp-sgcheck/pc_main.c
index f3f5907..6866eb8 100644
--- a/exp-sgcheck/pc_main.c
+++ b/exp-sgcheck/pc_main.c
@@ -9,7 +9,7 @@
This file is part of Ptrcheck, a Valgrind tool for checking pointer
use in programs.
- Copyright (C) 2008-2015 OpenWorks Ltd
+ Copyright (C) 2008-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -77,10 +77,6 @@
VG_(printf)("SGCheck doesn't work on MIPS yet, sorry.\n");
VG_(exit)(1);
#endif
-#if defined(VGA_tilegx)
- VG_(printf)("SGCheck doesn't work on TileGx yet, sorry.\n");
- VG_(exit)(1);
-#endif
// Can't change the name until we change the names in suppressions
// too.
@@ -89,7 +85,7 @@
VG_(details_description) ("a stack and global array "
"overrun detector");
VG_(details_copyright_author)(
- "Copyright (C) 2003-2015, and GNU GPL'd, by OpenWorks Ltd et al.");
+ "Copyright (C) 2003-2017, and GNU GPL'd, by OpenWorks Ltd et al.");
VG_(details_bug_reports_to) (VG_BUGS_TO);
VG_(details_avg_translation_sizeB) ( 496 );
diff --git a/exp-sgcheck/sg_main.c b/exp-sgcheck/sg_main.c
index d961abf..1daf65e 100644
--- a/exp-sgcheck/sg_main.c
+++ b/exp-sgcheck/sg_main.c
@@ -9,7 +9,7 @@
This file is part of Ptrcheck, a Valgrind tool for checking pointer
use in programs.
- Copyright (C) 2008-2015 OpenWorks Ltd
+ Copyright (C) 2008-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/exp-sgcheck/sg_main.h b/exp-sgcheck/sg_main.h
index 2d3d846..929dba4 100644
--- a/exp-sgcheck/sg_main.h
+++ b/exp-sgcheck/sg_main.h
@@ -9,7 +9,7 @@
This file is part of Ptrcheck, a Valgrind tool for checking pointer
use in programs.
- Copyright (C) 2008-2015 OpenWorks Ltd
+ Copyright (C) 2008-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/exp-sgcheck/tests/Makefile.in b/exp-sgcheck/tests/Makefile.in
index 92ee355..8a647d1 100644
--- a/exp-sgcheck/tests/Makefile.in
+++ b/exp-sgcheck/tests/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -271,6 +271,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -441,6 +442,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -451,6 +453,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -525,8 +528,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -571,7 +572,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/exp-sgcheck/tests/is_arch_supported b/exp-sgcheck/tests/is_arch_supported
index 328b9b6..818cc61 100755
--- a/exp-sgcheck/tests/is_arch_supported
+++ b/exp-sgcheck/tests/is_arch_supported
@@ -10,6 +10,6 @@
# architectures.
case `uname -m` in
- ppc*|arm*|s390x|mips*|tilegx) exit 1;;
+ ppc*|arm*|s390x|mips*) exit 1;;
*) exit 0;;
esac
diff --git a/gdbserver_tests/Makefile.in b/gdbserver_tests/Makefile.in
index c3c650a..1ef30b6 100644
--- a/gdbserver_tests/Makefile.in
+++ b/gdbserver_tests/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -325,6 +325,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -495,6 +496,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -505,6 +507,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -579,8 +582,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -625,7 +626,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/gdbserver_tests/filter_passsigalrm b/gdbserver_tests/filter_passsigalrm
index 6b86f38..2a67190 100755
--- a/gdbserver_tests/filter_passsigalrm
+++ b/gdbserver_tests/filter_passsigalrm
@@ -5,6 +5,6 @@
$dir/filter_gdb |
# Filter the number of real-time signal SIGRTMIN which
-# varies accross systems.
+# varies across systems.
sed 's/Program received signal SIG[0-9]*, Real-time event [0-9]*./Program received signal SIGxx, Real-time event xx./'
diff --git a/gdbserver_tests/mcblocklistsearch.stderrB.exp b/gdbserver_tests/mcblocklistsearch.stderrB.exp
index eb4c7e4..312d776 100644
--- a/gdbserver_tests/mcblocklistsearch.stderrB.exp
+++ b/gdbserver_tests/mcblocklistsearch.stderrB.exp
@@ -6,8 +6,8 @@
Breakpoint 1, f () at leak-tree.c:42
42 t->l = mk(); // B
Continuing.
-Breakpoint 2, main () at leak-tree.c:67
-67 PRINT_LEAK_COUNTS(stderr);
+Breakpoint 2, main () at leak-tree.c:68
+68 PRINT_LEAK_COUNTS(stderr);
Searching for pointers to 0x........
*0x........ points at 0x........
Address 0x........ is 0 bytes inside data symbol "t"
diff --git a/gdbserver_tests/mcblocklistsearch.vgtest b/gdbserver_tests/mcblocklistsearch.vgtest
index eb597e8..bced1cd 100644
--- a/gdbserver_tests/mcblocklistsearch.vgtest
+++ b/gdbserver_tests/mcblocklistsearch.vgtest
@@ -1,7 +1,7 @@
# test the memcheck block_list and search monitor commands.
prog: ../memcheck/tests/leak-tree
vgopts: --tool=memcheck --vgdb=yes --vgdb-error=0 --vgdb-prefix=./vgdb-prefix-mcblocklistsearch -q
-prereq: test -e gdb.eval && ! ../tests/arch_test tilegx
+prereq: test -e gdb.eval
stdout_filter: filter_make_empty
stderr_filter: filter_make_empty
progB: gdb
diff --git a/gdbserver_tests/mchelp.stdoutB.exp b/gdbserver_tests/mchelp.stdoutB.exp
index 6d6bdb1..9fd12ca 100644
--- a/gdbserver_tests/mchelp.stdoutB.exp
+++ b/gdbserver_tests/mchelp.stdoutB.exp
@@ -27,12 +27,13 @@
check_memory [addressable|defined] <addr> [<len>]
check that <len> (or 1) bytes at <addr> have the given accessibility
and outputs a description of <addr>
- leak_check [full*|summary]
+ leak_check [full*|summary|xtleak]
[kinds kind1,kind2,...|reachable|possibleleak*|definiteleak]
[heuristics heur1,heur2,...]
[increased*|changed|any]
[unlimited*|limited <max_loss_records_output>]
* = defaults
+ xtleak produces an xtree full leak result in xtleak.kcg.%p.%n
where kind is one of:
definite indirect possible reachable all none
where heur is one of:
@@ -52,6 +53,8 @@
shows places pointing inside <len> (default 1) bytes at <addr>
(with len 1, only shows "start pointers" pointing exactly to <addr>,
with len > 1, will also show "interior pointers")
+ xtmemory [<filename>]
+ dump xtree memory profile in <filename> (default xtmemory.kcg.%p.%n)
general valgrind monitor commands:
help [debug] : monitor command help. With debug: + debugging commands
v.wait [<ms>] : sleep <ms> (default 0) then continue
@@ -96,12 +99,13 @@
check_memory [addressable|defined] <addr> [<len>]
check that <len> (or 1) bytes at <addr> have the given accessibility
and outputs a description of <addr>
- leak_check [full*|summary]
+ leak_check [full*|summary|xtleak]
[kinds kind1,kind2,...|reachable|possibleleak*|definiteleak]
[heuristics heur1,heur2,...]
[increased*|changed|any]
[unlimited*|limited <max_loss_records_output>]
* = defaults
+ xtleak produces an xtree full leak result in xtleak.kcg.%p.%n
where kind is one of:
definite indirect possible reachable all none
where heur is one of:
@@ -121,4 +125,6 @@
shows places pointing inside <len> (default 1) bytes at <addr>
(with len 1, only shows "start pointers" pointing exactly to <addr>,
with len > 1, will also show "interior pointers")
+ xtmemory [<filename>]
+ dump xtree memory profile in <filename> (default xtmemory.kcg.%p.%n)
monitor command request to kill this process
diff --git a/gdbserver_tests/mcinfcallRU.stderr.exp b/gdbserver_tests/mcinfcallRU.stderr.exp
index 502dd8a..492c9c4 100644
--- a/gdbserver_tests/mcinfcallRU.stderr.exp
+++ b/gdbserver_tests/mcinfcallRU.stderr.exp
@@ -1,4 +1,4 @@
-loops/sleep_ms/burn/threads_spec: 1 0 2000000000 ------B-
+loops/sleep_ms/burn/threads_spec/affinity: 1 0 2000000000 ------B- 1
main ready to sleep and/or burn
pid .... Thread .... inferior call pushed from gdb in mcinfcallRU.stdinB.gdb
Reset valgrind output to log (orderly_finish)
diff --git a/gdbserver_tests/mcinfcallRU.vgtest b/gdbserver_tests/mcinfcallRU.vgtest
index 0c7b079..e16df04 100644
--- a/gdbserver_tests/mcinfcallRU.vgtest
+++ b/gdbserver_tests/mcinfcallRU.vgtest
@@ -2,7 +2,7 @@
prog: sleepers
# We would like to use B-B-B-B- instead of ------B- but this gives
# too much dependencies to the scheduler fairness.
-args: 1 0 2000000000 ------B-
+args: 1 0 2000000000 ------B- 1
vgopts: --tool=memcheck --vgdb=yes --vgdb-error=0 --vgdb-prefix=./vgdb-prefix-mcinfcallRU
# filter_gdb to replace pid and Thread numbers in the output of the program:
stderr_filter: filter_gdb
diff --git a/gdbserver_tests/mcinfcallWSRU.stderr.exp b/gdbserver_tests/mcinfcallWSRU.stderr.exp
index a6ac617..8a9939c 100644
--- a/gdbserver_tests/mcinfcallWSRU.stderr.exp
+++ b/gdbserver_tests/mcinfcallWSRU.stderr.exp
@@ -1,4 +1,4 @@
-loops/sleep_ms/burn/threads_spec: 100 100000000 1000000000 -S-S-SB-
+loops/sleep_ms/burn/threads_spec/affinity: 100 100000000 1000000000 -S-S-SB- 1
Brussels ready to sleep and/or burn
London ready to sleep and/or burn
Petaouchnok ready to sleep and/or burn
diff --git a/gdbserver_tests/mcinfcallWSRU.vgtest b/gdbserver_tests/mcinfcallWSRU.vgtest
index fd3922f..af260ff 100644
--- a/gdbserver_tests/mcinfcallWSRU.vgtest
+++ b/gdbserver_tests/mcinfcallWSRU.vgtest
@@ -3,7 +3,7 @@
prog: sleepers
# We would like to have two threads running (i.e. -S-SB-B-)
# but this introduces too much dependencies to scheduler fairness.
-args: 100 100000000 1000000000 -S-S-SB-
+args: 100 100000000 1000000000 -S-S-SB- 1
vgopts: --tool=memcheck --vgdb=yes --vgdb-error=0 --vgdb-prefix=./vgdb-prefix-mcinfcallWSRU
# We need a non buggy gdb.step on arm thumb.
# Disable on Darwin: inferior call rejected as it cannot find malloc.
diff --git a/gdbserver_tests/mcinvokeRU.vgtest b/gdbserver_tests/mcinvokeRU.vgtest
index 1d56b7f..ab9ada7 100644
--- a/gdbserver_tests/mcinvokeRU.vgtest
+++ b/gdbserver_tests/mcinvokeRU.vgtest
@@ -1,7 +1,7 @@
# test that vgdb can invoke a process when all threads are in Runnable or Yielding mode
# If the test goes wrong, it might consume CPU during a long time.
prog: sleepers
-args: 1 0 1000000000 B-B-B-B-
+args: 1 0 1000000000 B-B-B-B- 1
vgopts: --tool=memcheck --vgdb=yes --vgdb-prefix=./vgdb-prefix-mcinvokeRU
stderr_filter: filter_make_empty
# as the Valgrind process is always busy, we do not need the vgdb.invoker prereq.
diff --git a/gdbserver_tests/mcmain_pic.stdinB.gdb b/gdbserver_tests/mcmain_pic.stdinB.gdb
index 8ec0a6f..a43052e 100644
--- a/gdbserver_tests/mcmain_pic.stdinB.gdb
+++ b/gdbserver_tests/mcmain_pic.stdinB.gdb
@@ -1,6 +1,7 @@
# connect gdb to Valgrind gdbserver:
target remote | ./vgdb --wait=60 --vgdb-prefix=./vgdb-prefix-mcmain_pic
echo vgdb launched process attached\n
+source mcmain_pic.heur
monitor v.set vgdb-error 999999
#
# break
diff --git a/gdbserver_tests/mcmain_pic.vgtest b/gdbserver_tests/mcmain_pic.vgtest
index 1fab67f..6211105 100644
--- a/gdbserver_tests/mcmain_pic.vgtest
+++ b/gdbserver_tests/mcmain_pic.vgtest
@@ -3,7 +3,7 @@
# information via the gdbserver protocol packet qXfer:auxv:read:
# The content of the auxv data can be shown by gdb using
# gdb command 'info auxv'
-prereq: test -e gdb.pic
+prereq: test -e gdb.pic && if ../tests/arch_test mips32 || ../tests/arch_test mips64 ; then echo "set heuristic-fence-post 999999" ; else echo '' ; fi > mcmain_pic.heur
prog: main_pic
vgopts: --tool=memcheck --vgdb=yes --vgdb-error=0 --vgdb-prefix=./vgdb-prefix-mcmain_pic
stdout_filter: filter_gdb
diff --git a/gdbserver_tests/mcsignopass.vgtest b/gdbserver_tests/mcsignopass.vgtest
index 61992aa..73def5e 100644
--- a/gdbserver_tests/mcsignopass.vgtest
+++ b/gdbserver_tests/mcsignopass.vgtest
@@ -2,7 +2,7 @@
# We detect this two ways:
# the gdb output will not contain the signal handling
# faultstatus C code will report a failure for the signal not passed
-# (i.e. SIGBUG, Test 3). Other tests will be succesful, because signals
+# (i.e. SIGBUG, Test 3). Other tests will be successful, because signals
# are eventually passed.
prereq: test -e gdb
prog: ../none/tests/faultstatus
diff --git a/gdbserver_tests/mssnapshot.stderrB.exp b/gdbserver_tests/mssnapshot.stderrB.exp
index 93ba9c9..8bee8fc 100644
--- a/gdbserver_tests/mssnapshot.stderrB.exp
+++ b/gdbserver_tests/mssnapshot.stderrB.exp
@@ -23,5 +23,7 @@
all_snapshots [<filename>]
saves all snapshot(s) taken so far in <filename>
default <filename> is massif.vgdb.out
+ xtmemory [<filename>]
+ dump xtree memory profile in <filename> (default xtmemory.kcg)
monitor command request to kill this process
Remote connection closed
diff --git a/gdbserver_tests/nlcontrolc.stderr.exp b/gdbserver_tests/nlcontrolc.stderr.exp
index 0f27d71..ac75bb3 100644
--- a/gdbserver_tests/nlcontrolc.stderr.exp
+++ b/gdbserver_tests/nlcontrolc.stderr.exp
@@ -3,7 +3,7 @@
(action at startup) vgdb me ...
-loops/sleep_ms/burn/threads_spec: 1000000000 1000000000 1000000000 BSBSBSBS
+loops/sleep_ms/burn/threads_spec/affinity: 1000000000 1000000000 1000000000 BSBSBSBS 1
Brussels ready to sleep and/or burn
London ready to sleep and/or burn
Petaouchnok ready to sleep and/or burn
diff --git a/gdbserver_tests/nlcontrolc.vgtest b/gdbserver_tests/nlcontrolc.vgtest
index 077b2bb..bb53084 100644
--- a/gdbserver_tests/nlcontrolc.vgtest
+++ b/gdbserver_tests/nlcontrolc.vgtest
@@ -9,11 +9,11 @@
# This test is disabled on Solaris because modifying select/poll/ppoll timeout
# has no effect if a thread is already blocked in that syscall.
prog: sleepers
-args: 1000000000 1000000000 1000000000 BSBSBSBS
+args: 1000000000 1000000000 1000000000 BSBSBSBS 1
vgopts: --tool=none --vgdb=yes --vgdb-error=0 --vgdb-prefix=./vgdb-prefix-nlcontrolc
stderr_filter: filter_stderr
# Bug 338633 nlcontrol hangs on arm64 currently.
-prereq: test -e gdb -a -f vgdb.invoker && ! ../tests/arch_test arm64 && ! ../tests/arch_test tilegx && ! ../tests/os_test solaris
+prereq: test -e gdb -a -f vgdb.invoker && ! ../tests/arch_test arm64 && ! ../tests/os_test solaris
progB: gdb
argsB: --quiet -l 60 --nx ./sleepers
stdinB: nlcontrolc.stdinB.gdb
diff --git a/gdbserver_tests/nlgone_return.vgtest b/gdbserver_tests/nlgone_return.vgtest
index f6f869c..996f01c 100644
--- a/gdbserver_tests/nlgone_return.vgtest
+++ b/gdbserver_tests/nlgone_return.vgtest
@@ -4,7 +4,7 @@
args: return
vgopts: --tool=none --vgdb=yes --vgdb-error=0 --vgdb-prefix=./vgdb-prefix-nlgone-return
stderr_filter: filter_stderr
-prereq: test -e gdb && ! ../tests/arch_test tilegx
+prereq: test -e gdb
progB: gdb
argsB: --quiet -l 60 --nx ./gone
stdinB: nlgone_return.stdinB.gdb
diff --git a/gdbserver_tests/nlself_invalidate.vgtest b/gdbserver_tests/nlself_invalidate.vgtest
index 3902538..2031130 100644
--- a/gdbserver_tests/nlself_invalidate.vgtest
+++ b/gdbserver_tests/nlself_invalidate.vgtest
@@ -1,5 +1,5 @@
# reproduces a bug triggered by translation chaining and gdbserver
-# invalidation due to breakpoint, when there is a jump from a tranlation
+# invalidation due to breakpoint, when there is a jump from a translation
# block into itself.
prog: self_invalidate
vgopts: --tool=none --vgdb=yes --vgdb-error=0 --vgdb-prefix=./vgdb-prefix-nlself_invalidate
diff --git a/gdbserver_tests/nlsigvgdb.vgtest b/gdbserver_tests/nlsigvgdb.vgtest
index f488748..0b03b04 100644
--- a/gdbserver_tests/nlsigvgdb.vgtest
+++ b/gdbserver_tests/nlsigvgdb.vgtest
@@ -4,7 +4,7 @@
# But if this signal is masked, then vgdb does not recuperate the control
# and Valgrind dies. See function give_control_back_to_vgdb in m_gdbserver.c
prog: sleepers
-args: 1 10000000 0 -S-S-S-S
+args: 1 10000000 0 -S-S-S-S 1
vgopts: --tool=none --vgdb=yes --vgdb-error=0 --vgdb-prefix=./vgdb-prefix-nlsigvgdb
stderr_filter: filter_stderr
prereq: test -e gdb -a -f vgdb.invoker
diff --git a/gdbserver_tests/nlvgdbsigqueue.stderr.exp b/gdbserver_tests/nlvgdbsigqueue.stderr.exp
index 616c0a8..52b10c9 100644
--- a/gdbserver_tests/nlvgdbsigqueue.stderr.exp
+++ b/gdbserver_tests/nlvgdbsigqueue.stderr.exp
@@ -3,7 +3,7 @@
(action at startup) vgdb me ...
-loops/sleep_ms/burn/threads_spec: 1000000000 1000000000 1 BSBSBSBS
+loops/sleep_ms/burn/threads_spec/affinity: 1000000000 1000000000 1 BSBSBSBS 1
Brussels ready to sleep and/or burn
London ready to sleep and/or burn
Petaouchnok ready to sleep and/or burn
diff --git a/gdbserver_tests/nlvgdbsigqueue.vgtest b/gdbserver_tests/nlvgdbsigqueue.vgtest
index d8aa1c2..8775682 100644
--- a/gdbserver_tests/nlvgdbsigqueue.vgtest
+++ b/gdbserver_tests/nlvgdbsigqueue.vgtest
@@ -3,7 +3,7 @@
# vgdb must queue these signals and deliver them before PTRACE_DETACHing.
# sleepers is started with argument so that it will mostly sleep.
prog: sleepers
-args: 1000000000 1000000000 1 BSBSBSBS
+args: 1000000000 1000000000 1 BSBSBSBS 1
vgopts: --tool=none --vgdb=yes --vgdb-error=0 --vgdb-prefix=./vgdb-prefix-nlvgdbsigqueue
stderr_filter: filter_stderr
prereq: test -e gdb -a -f vgdb.invoker
diff --git a/gdbserver_tests/send_signal b/gdbserver_tests/send_signal
index 3f4442f..0657a7a 100755
--- a/gdbserver_tests/send_signal
+++ b/gdbserver_tests/send_signal
@@ -2,7 +2,7 @@
# send_signal sends signal $1 to the Valgrind process using prefix $2 in $3 seconds
# If there are some args after $3, the rest of these args is a command and its arg
-# which is run every second. When this command is succesful, then the sleep and
+# which is run every second. When this command is successful, then the sleep and
# the signal sending is done
SIG=$1
shift
diff --git a/gdbserver_tests/simulate_control_c b/gdbserver_tests/simulate_control_c
index d380d65..30428b2 100755
--- a/gdbserver_tests/simulate_control_c
+++ b/gdbserver_tests/simulate_control_c
@@ -2,7 +2,7 @@
# simulate control_c by sending SIGUSR1 to the vgdb using prefix $1 in $2 seconds
# If there are some args after $2, the rest of these args is a command and its arg
-# which is run every second. When this command is succesful, then the sleep and
+# which is run every second. When this command is successful, then the sleep and
# the control c simul is done.
PREFIX=$1
shift
diff --git a/gdbserver_tests/sleepers.c b/gdbserver_tests/sleepers.c
index 64ab0ea..5ffc6f8 100644
--- a/gdbserver_tests/sleepers.c
+++ b/gdbserver_tests/sleepers.c
@@ -137,7 +137,7 @@
pthread_t ebbr, egll, zzzz;
struct spec b, l, p, m;
char *some_mem __attribute__((unused)) = malloc(100);
- setaffinity();
+ if (argc > 5 && atoi(argv[5])) setaffinity();
setup_sigusr_handler();
if (argc > 1)
loops = atoi(argv[1]);
@@ -153,8 +153,8 @@
else
threads_spec = "BSBSBSBS";
- fprintf(stderr, "loops/sleep_ms/burn/threads_spec: %d %d %d %s\n",
- loops, sleepms, burn, threads_spec);
+ fprintf(stderr, "loops/sleep_ms/burn/threads_spec/affinity: %d %d %d %s %d\n",
+ loops, sleepms, burn, threads_spec, argc > 5 && atoi(argv[5]));
fflush(stderr);
b.name = "Brussels";
diff --git a/gdbserver_tests/solaris/Makefile.in b/gdbserver_tests/solaris/Makefile.in
index e184b9b..0d7c691 100644
--- a/gdbserver_tests/solaris/Makefile.in
+++ b/gdbserver_tests/solaris/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -199,6 +199,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -369,6 +370,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -379,6 +381,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -453,8 +456,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -499,7 +500,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/gdbserver_tests/solaris/nlcontrolc.stderr.exp b/gdbserver_tests/solaris/nlcontrolc.stderr.exp
index 3f06448..b508d37 100644
--- a/gdbserver_tests/solaris/nlcontrolc.stderr.exp
+++ b/gdbserver_tests/solaris/nlcontrolc.stderr.exp
@@ -3,7 +3,7 @@
(action at startup) vgdb me ...
-loops/sleep_ms/burn/threads_spec: 1000000000 5000 1000000000 BSBSBSBS
+loops/sleep_ms/burn/threads_spec/affinity: 1000000000 5000 1000000000 BSBSBSBS 1
Brussels ready to sleep and/or burn
London ready to sleep and/or burn
Petaouchnok ready to sleep and/or burn
diff --git a/gdbserver_tests/solaris/nlcontrolc.vgtest b/gdbserver_tests/solaris/nlcontrolc.vgtest
index 2723570..8fed700 100644
--- a/gdbserver_tests/solaris/nlcontrolc.vgtest
+++ b/gdbserver_tests/solaris/nlcontrolc.vgtest
@@ -6,7 +6,7 @@
# sleepers is started with argument so that it will compute during ages.
# The variable modifications means it will exit in a reasonable time.
prog: ../sleepers
-args: 1000000000 5000 1000000000 BSBSBSBS
+args: 1000000000 5000 1000000000 BSBSBSBS 1
vgopts: --tool=none --vgdb=yes --vgdb-error=0 --vgdb-prefix=./vgdb-prefix-solaris-nlcontrolc
stderr_filter: filter_stderr
prereq: test -e ../gdb -a -f ../vgdb.invoker
diff --git a/glibc-2.34567-NPTL-helgrind.supp b/glibc-2.34567-NPTL-helgrind.supp
index ed105b8..7ebd2c4 100644
--- a/glibc-2.34567-NPTL-helgrind.supp
+++ b/glibc-2.34567-NPTL-helgrind.supp
@@ -267,6 +267,18 @@
fun:pthread_create@*
}
+{
+ helgrind---_dl_allocate_tls2
+ Helgrind:Race
+ fun:memcpy
+ fun:__mempcpy_inline
+ fun:_dl_allocate_tls_init
+ ...
+ fun:pthread_create@@GLIBC_2.2*
+ fun:pthread_create_WRK
+ fun:pthread_create@*
+}
+
####################################################
# To do with GNU libgomp
#
diff --git a/glibc-2.X-drd.supp b/glibc-2.X-drd.supp
index e66f1c4..abddb51 100644
--- a/glibc-2.X-drd.supp
+++ b/glibc-2.X-drd.supp
@@ -115,6 +115,12 @@
fun:pthread_cancel_init
}
{
+ drd-libpthread-pthread_cancel
+ drd:ConflictingAccess
+ fun:pthread_cancel
+ fun:pthread_cancel_intercept
+}
+{
drd-libpthread-_Unwind_ForcedUnwind
drd:ConflictingAccess
...
diff --git a/helgrind/Makefile.in b/helgrind/Makefile.in
index 58623f2..7e34ea7 100644
--- a/helgrind/Makefile.in
+++ b/helgrind/Makefile.in
@@ -359,6 +359,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -530,6 +531,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -540,6 +542,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -614,8 +617,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -660,7 +661,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
@@ -738,9 +738,6 @@
-static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \
@FLAG_M64@
-TOOL_LDFLAGS_TILEGX_LINUX = \
- $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-
TOOL_LDFLAGS_X86_SOLARIS = \
$(TOOL_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
@@ -795,9 +792,6 @@
LIBREPLACEMALLOC_MIPS64_LINUX = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a
-LIBREPLACEMALLOC_TILEGX_LINUX = \
- $(top_builddir)/coregrind/libreplacemalloc_toolpreload-tilegx-linux.a
-
LIBREPLACEMALLOC_X86_SOLARIS = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-solaris.a
@@ -860,11 +854,6 @@
$(LIBREPLACEMALLOC_MIPS64_LINUX) \
-Wl,--no-whole-archive
-LIBREPLACEMALLOC_LDFLAGS_TILEGX_LINUX = \
- -Wl,--whole-archive \
- $(LIBREPLACEMALLOC_TILEGX_LINUX) \
- -Wl,--no-whole-archive
-
LIBREPLACEMALLOC_LDFLAGS_X86_SOLARIS = \
-Wl,--whole-archive \
$(LIBREPLACEMALLOC_X86_SOLARIS) \
diff --git a/helgrind/docs/hg-manual.xml b/helgrind/docs/hg-manual.xml
index 28d4d9b..ff7d65b 100644
--- a/helgrind/docs/hg-manual.xml
+++ b/helgrind/docs/hg-manual.xml
@@ -64,6 +64,11 @@
<varname>ANNOTATE_*</varname> macros defined
in <varname>helgrind.h</varname>.</para>
+<para>Helgrind also provides <xref linkend="manual-core.xtree"/> memory
+ profiling using the command line
+ option <computeroutput>--xtree-memory</computeroutput> and the monitor command
+ <computeroutput>xtmemory</computeroutput>.</para>
+
<para>Following those is a section containing
diff --git a/helgrind/helgrind.h b/helgrind/helgrind.h
index d194c44..d6fa1f4 100644
--- a/helgrind/helgrind.h
+++ b/helgrind/helgrind.h
@@ -11,7 +11,7 @@
This file is part of Helgrind, a Valgrind tool for detecting errors
in threaded programs.
- Copyright (C) 2007-2015 OpenWorks LLP
+ Copyright (C) 2007-2017 OpenWorks LLP
info@open-works.co.uk
Redistribution and use in source and binary forms, with or without
@@ -133,7 +133,8 @@
_VG_USERREQ__HG_PTHREAD_COND_SIGNAL_POST, /* pth_cond_t* */
_VG_USERREQ__HG_PTHREAD_COND_BROADCAST_POST,/* pth_cond_t* */
_VG_USERREQ__HG_RTLD_BIND_GUARD, /* int flags */
- _VG_USERREQ__HG_RTLD_BIND_CLEAR /* int flags */
+ _VG_USERREQ__HG_RTLD_BIND_CLEAR, /* int flags */
+ _VG_USERREQ__HG_GNAT_DEPENDENT_MASTER_JOIN /* void*d, void*m */
} Vg_TCheckClientRequest;
@@ -424,6 +425,37 @@
_res; \
}))
+/* End-user request for Ada applications compiled with GNAT.
+ Helgrind understands the Ada concept of Ada task dependencies and
+ terminations. See Ada Reference Manual section 9.3 "Task Dependence
+ - Termination of Tasks".
+ However, in some cases, the master of (terminated) tasks completes
+ only when the application exits. An example of this is dynamically
+ allocated tasks with an access type defined at Library Level.
+ By default, the state of such tasks in Helgrind will be 'exited but
+ join not done yet'. Many tasks in such a state are however causing
+ Helgrind CPU and memory to increase significantly.
+ VALGRIND_HG_GNAT_DEPENDENT_MASTER_JOIN can be used to indicate
+ to Helgrind that a not yet completed master has however already
+ 'seen' the termination of a dependent : this is conceptually the
+ same as a pthread_join and causes the cleanup of the dependent
+ as done by Helgrind when a master completes.
+ This allows to avoid the overhead in helgrind caused by such tasks.
+ A typical usage for a master to indicate it has done conceptually a join
+ with a dependent task before the master completes is:
+ while not Dep_Task'Terminated loop
+ ... do whatever to wait for Dep_Task termination.
+ end loop;
+ VALGRIND_HG_GNAT_DEPENDENT_MASTER_JOIN
+ (Dep_Task'Identity,
+ Ada.Task_Identification.Current_Task);
+ Note that VALGRIND_HG_GNAT_DEPENDENT_MASTER_JOIN should be a binding
+ to a C function built with the below macro. */
+#define VALGRIND_HG_GNAT_DEPENDENT_MASTER_JOIN(_qzz_dep, _qzz_master) \
+ DO_CREQ_v_WW(_VG_USERREQ__HG_GNAT_DEPENDENT_MASTER_JOIN, \
+ void*,(_qzz_dep), \
+ void*,(_qzz_master))
+
/*----------------------------------------------------------------*/
/*--- ---*/
/*--- ThreadSanitizer-compatible requests ---*/
diff --git a/helgrind/hg_addrdescr.c b/helgrind/hg_addrdescr.c
index 53f98fc..90a9aa5 100644
--- a/helgrind/hg_addrdescr.c
+++ b/helgrind/hg_addrdescr.c
@@ -8,7 +8,7 @@
This file is part of Helgrind, a Valgrind tool for detecting errors
in threaded programs.
- Copyright (C) 2007-2015 OpenWorks Ltd
+ Copyright (C) 2007-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/helgrind/hg_addrdescr.h b/helgrind/hg_addrdescr.h
index 14f712a..f799597 100644
--- a/helgrind/hg_addrdescr.h
+++ b/helgrind/hg_addrdescr.h
@@ -9,7 +9,7 @@
This file is part of Helgrind, a Valgrind tool for detecting errors
in threaded programs.
- Copyright (C) 2007-2015 OpenWorks Ltd
+ Copyright (C) 2007-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/helgrind/hg_basics.c b/helgrind/hg_basics.c
index 6794683..7c6a941 100644
--- a/helgrind/hg_basics.c
+++ b/helgrind/hg_basics.c
@@ -8,7 +8,7 @@
This file is part of Helgrind, a Valgrind tool for detecting errors
in threaded programs.
- Copyright (C) 2007-2015 OpenWorks Ltd
+ Copyright (C) 2007-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/helgrind/hg_basics.h b/helgrind/hg_basics.h
index 040765d..b50d48e 100644
--- a/helgrind/hg_basics.h
+++ b/helgrind/hg_basics.h
@@ -8,7 +8,7 @@
This file is part of Helgrind, a Valgrind tool for detecting errors
in threaded programs.
- Copyright (C) 2007-2015 OpenWorks Ltd
+ Copyright (C) 2007-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/helgrind/hg_errors.c b/helgrind/hg_errors.c
index dcb502a..273a7fd 100644
--- a/helgrind/hg_errors.c
+++ b/helgrind/hg_errors.c
@@ -8,7 +8,7 @@
This file is part of Helgrind, a Valgrind tool for detecting errors
in threaded programs.
- Copyright (C) 2007-2015 OpenWorks Ltd
+ Copyright (C) 2007-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/helgrind/hg_errors.h b/helgrind/hg_errors.h
index e8b0e57..f9ca9ff 100644
--- a/helgrind/hg_errors.h
+++ b/helgrind/hg_errors.h
@@ -8,7 +8,7 @@
This file is part of Helgrind, a Valgrind tool for detecting errors
in threaded programs.
- Copyright (C) 2007-2015 OpenWorks Ltd
+ Copyright (C) 2007-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/helgrind/hg_intercepts.c b/helgrind/hg_intercepts.c
index ff36e93..e186716 100644
--- a/helgrind/hg_intercepts.c
+++ b/helgrind/hg_intercepts.c
@@ -8,7 +8,7 @@
This file is part of Helgrind, a Valgrind tool for detecting errors
in threaded programs.
- Copyright (C) 2007-2015 OpenWorks LLP
+ Copyright (C) 2007-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -673,7 +673,11 @@
// We wrap two hook procedures called by the gnat gcc Ada runtime
// that allows helgrind to understand the semantic of Ada task dependencies
// and termination.
-
+// procedure Master_Hook
+// (Dependent : Task_Id;
+// Parent : Task_Id;
+// Master_Level : Integer);
+// where type Task_Id is access all Ada_Task_Control_Block;
// System.Tasking.Debug.Master_Hook is called by a task Dependent to
// indicate that its master is identified by master+master_level.
void I_WRAP_SONAME_FNNAME_ZU
@@ -707,6 +711,10 @@
// System.Tasking.Debug.Master_Completed_Hook is called by a task to
// indicate that it has completed a master.
+// procedure Master_Completed_Hook
+// (Self_ID : Task_Id;
+// Master_Level : Integer);
+// where type Task_Id is access all Ada_Task_Control_Block;
// This indicates that all its Dependent tasks (that identified themselves
// with the Master_Hook call) are terminated. Helgrind can consider
// at this point that the equivalent of a 'pthread_join' has been done
diff --git a/helgrind/hg_lock_n_thread.c b/helgrind/hg_lock_n_thread.c
index a452753..42a3a59 100644
--- a/helgrind/hg_lock_n_thread.c
+++ b/helgrind/hg_lock_n_thread.c
@@ -8,7 +8,7 @@
This file is part of Helgrind, a Valgrind tool for detecting errors
in threaded programs.
- Copyright (C) 2007-2015 OpenWorks Ltd
+ Copyright (C) 2007-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/helgrind/hg_lock_n_thread.h b/helgrind/hg_lock_n_thread.h
index 9fb4c8a..30ee02b 100644
--- a/helgrind/hg_lock_n_thread.h
+++ b/helgrind/hg_lock_n_thread.h
@@ -8,7 +8,7 @@
This file is part of Helgrind, a Valgrind tool for detecting errors
in threaded programs.
- Copyright (C) 2007-2015 OpenWorks Ltd
+ Copyright (C) 2007-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -100,7 +100,7 @@
the same thing implicitly. This is necessary because for example
Solaris libc caches many objects and reuses them for different threads
and that confuses Helgrind. With libvki it would be possible to
- explictly use VG_USERREQ__HG_CLEAN_MEMORY on such objects.
+ explicitly use VG_USERREQ__HG_CLEAN_MEMORY on such objects.
Also mutex activity is ignored so that they do not impose false
ordering between creator and created thread. */
Int pthread_create_nesting_level;
diff --git a/helgrind/hg_main.c b/helgrind/hg_main.c
index 3c1f12c..5c302e5 100644
--- a/helgrind/hg_main.c
+++ b/helgrind/hg_main.c
@@ -8,10 +8,10 @@
This file is part of Helgrind, a Valgrind tool for detecting errors
in threaded programs.
- Copyright (C) 2007-2015 OpenWorks LLP
+ Copyright (C) 2007-2017 OpenWorks LLP
info@open-works.co.uk
- Copyright (C) 2007-2015 Apple, Inc.
+ Copyright (C) 2007-2017 Apple, Inc.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -57,6 +57,8 @@
#include "pub_tool_aspacemgr.h" // VG_(am_is_valid_for_client)
#include "pub_tool_poolalloc.h"
#include "pub_tool_addrinfo.h"
+#include "pub_tool_xtree.h"
+#include "pub_tool_xtmemory.h"
#include "hg_basics.h"
#include "hg_wordset.h"
@@ -3457,7 +3459,7 @@
The common case is that some thread T holds (eg) L1 L2 and L3 and
is repeatedly acquiring and releasing Ln, and there is no ordering
- error in what it is doing. Hence it repeatly:
+ error in what it is doing. Hence it repeatedly:
(1) searches laog to see if Ln --*--> {L1,L2,L3}, which always
produces the answer No (because there is no error).
@@ -4157,6 +4159,8 @@
md->thr = map_threads_lookup( tid );
VG_(HT_add_node)( hg_mallocmeta_table, (VgHashNode*)md );
+ if (UNLIKELY(VG_(clo_xtree_memory) == Vg_XTMemory_Full))
+ VG_(XTMemory_Full_alloc)(md->szB, md->where);
/* Tell the lower level memory wranglers. */
evh__new_mem_heap( p, szB, is_zeroed );
@@ -4211,6 +4215,10 @@
tl_assert(md->payload == (Addr)p);
szB = md->szB;
+ if (UNLIKELY(VG_(clo_xtree_memory) == Vg_XTMemory_Full)) {
+ ExeContext* ec_free = VG_(record_ExeContext)( tid, 0 );
+ VG_(XTMemory_Full_free)(md->szB, md->where, ec_free);
+ }
/* Nuke the metadata block */
old_md = (MallocMeta*)
@@ -4875,7 +4883,7 @@
Word master_level; // level of dependency between master and dependent
Thread* hg_dependent; // helgrind Thread* for dependent task.
}
- GNAT_dmml;
+ GNAT_dmml; // (d)ependent (m)aster (m)aster_(l)evel.
static XArray* gnat_dmmls; /* of GNAT_dmml */
static void gnat_dmmls_INIT (void)
{
@@ -4885,6 +4893,25 @@
sizeof(GNAT_dmml) );
}
}
+
+static void xtmemory_report_next_block(XT_Allocs* xta, ExeContext** ec_alloc)
+{
+ const MallocMeta* md = VG_(HT_Next)(hg_mallocmeta_table);
+ if (md) {
+ xta->nbytes = md->szB;
+ xta->nblocks = 1;
+ *ec_alloc = md->where;
+ } else
+ xta->nblocks = 0;
+}
+static void HG_(xtmemory_report) ( const HChar* filename, Bool fini )
+{
+ // Make xtmemory_report_next_block ready to be called.
+ VG_(HT_ResetIter)(hg_mallocmeta_table);
+ VG_(XTMemory_report)(filename, fini, xtmemory_report_next_block,
+ VG_(XT_filter_1top_and_maybe_below_main));
+}
+
static void print_monitor_help ( void )
{
VG_(gdb_printf)
@@ -4895,6 +4922,8 @@
" with no lock_addr, show status of all locks\n"
" accesshistory <addr> [<len>] : show access history recorded\n"
" for <len> (or 1) bytes at <addr>\n"
+" xtmemory [<filename>]\n"
+" dump xtree memory profile in <filename> (default xtmemory.kcg)\n"
"\n");
}
@@ -4913,7 +4942,7 @@
starts with the same first letter(s) as an already existing
command. This ensures a shorter abbreviation for the user. */
switch (VG_(keyword_id)
- ("help info accesshistory",
+ ("help info accesshistory xtmemory",
wcmd, kwd_report_duplicated_matches)) {
case -2: /* multiple matches */
return True;
@@ -4986,6 +5015,13 @@
return True;
}
+ case 3: { /* xtmemory */
+ HChar* filename;
+ filename = VG_(strtok_r) (NULL, " ", &ssaveptr);
+ HG_(xtmemory_report)(filename, False);
+ return True;
+ }
+
default:
tl_assert(0);
return False;
@@ -5071,6 +5107,41 @@
*ret = -1;
break;
+ /* This thread (tid) (a master) is informing us that it has
+ seen the termination of a dependent task, and that this should
+ be considered as a join between master and dependent. */
+ case _VG_USERREQ__HG_GNAT_DEPENDENT_MASTER_JOIN: {
+ Word n;
+ const Thread *stayer = map_threads_maybe_lookup( tid );
+ const void *dependent = (void*)args[1];
+ const void *master = (void*)args[2];
+
+ if (0)
+ VG_(printf)("HG_GNAT_DEPENDENT_MASTER_JOIN (tid %d): "
+ "self_id = %p Thread* = %p dependent %p\n",
+ (Int)tid, master, stayer, dependent);
+
+ gnat_dmmls_INIT();
+ /* Similar loop as for master completed hook below, but stops at
+ the first matching occurence, only comparing master and
+ dependent. */
+ for (n = VG_(sizeXA) (gnat_dmmls) - 1; n >= 0; n--) {
+ GNAT_dmml *dmml = (GNAT_dmml*) VG_(indexXA)(gnat_dmmls, n);
+ if (dmml->master == master
+ && dmml->dependent == dependent) {
+ if (0)
+ VG_(printf)("quitter %p dependency to stayer %p (join)\n",
+ dmml->hg_dependent->hbthr, stayer->hbthr);
+ tl_assert(dmml->hg_dependent->hbthr != stayer->hbthr);
+ generate_quitter_stayer_dependence (dmml->hg_dependent->hbthr,
+ stayer->hbthr);
+ VG_(removeIndexXA) (gnat_dmmls, n);
+ break;
+ }
+ }
+ break;
+ }
+
/* --- --- Client requests for Helgrind's use only --- --- */
/* Some thread is telling us its pthread_t value. Record the
@@ -5668,6 +5739,7 @@
static void hg_fini ( Int exitcode )
{
+ HG_(xtmemory_report) (VG_(clo_xtree_memory_file), True);
if (VG_(clo_verbosity) == 1 && !VG_(clo_xml)) {
VG_(message)(Vg_UserMsg,
"For counts of detected and suppressed errors, "
@@ -5740,6 +5812,9 @@
laog__init();
initialise_data_structures(hbthr_root);
+ if (VG_(clo_xtree_memory) == Vg_XTMemory_Full)
+ // Activate full xtree memory profiling.
+ VG_(XTMemory_Full_init)(VG_(XT_filter_1top_and_maybe_below_main));
}
static void hg_info_location (Addr a)
@@ -5753,7 +5828,7 @@
VG_(details_version) (NULL);
VG_(details_description) ("a thread error detector");
VG_(details_copyright_author)(
- "Copyright (C) 2007-2015, and GNU GPL'd, by OpenWorks LLP et al.");
+ "Copyright (C) 2007-2017, and GNU GPL'd, by OpenWorks LLP et al.");
VG_(details_bug_reports_to) (VG_BUGS_TO);
VG_(details_avg_translation_sizeB) ( 320 );
diff --git a/helgrind/hg_wordset.c b/helgrind/hg_wordset.c
index e0f6845..7a8320e 100644
--- a/helgrind/hg_wordset.c
+++ b/helgrind/hg_wordset.c
@@ -8,7 +8,7 @@
This file is part of Helgrind, a Valgrind tool for detecting errors
in threaded programs.
- Copyright (C) 2007-2015 OpenWorks LLP
+ Copyright (C) 2007-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/helgrind/hg_wordset.h b/helgrind/hg_wordset.h
index b431a05..844ca7f 100644
--- a/helgrind/hg_wordset.h
+++ b/helgrind/hg_wordset.h
@@ -8,7 +8,7 @@
This file is part of Helgrind, a Valgrind tool for detecting errors
in threaded programs.
- Copyright (C) 2007-2015 OpenWorks LLP
+ Copyright (C) 2007-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/helgrind/libhb.h b/helgrind/libhb.h
index 963c490..ffbf5fe 100644
--- a/helgrind/libhb.h
+++ b/helgrind/libhb.h
@@ -9,7 +9,7 @@
This file is part of LibHB, a library for implementing and checking
the happens-before relationship in concurrent programs.
- Copyright (C) 2008-2015 OpenWorks Ltd
+ Copyright (C) 2008-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/helgrind/libhb_core.c b/helgrind/libhb_core.c
index 15a57dd..4e102ab 100644
--- a/helgrind/libhb_core.c
+++ b/helgrind/libhb_core.c
@@ -9,7 +9,7 @@
This file is part of LibHB, a library for implementing and checking
the happens-before relationship in concurrent programs.
- Copyright (C) 2008-2015 OpenWorks Ltd
+ Copyright (C) 2008-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/helgrind/tests/Makefile.am b/helgrind/tests/Makefile.am
index df82169..48f5233 100644
--- a/helgrind/tests/Makefile.am
+++ b/helgrind/tests/Makefile.am
@@ -46,7 +46,8 @@
pth_barrier2.vgtest pth_barrier2.stdout.exp pth_barrier2.stderr.exp \
pth_barrier3.vgtest pth_barrier3.stdout.exp pth_barrier3.stderr.exp \
pth_destroy_cond.vgtest \
- pth_destroy_cond.stdout.exp pth_destroy_cond.stderr.exp \
+ pth_destroy_cond.stdout.exp \
+ pth_destroy_cond.stderr.exp pth_destroy_cond.stderr.exp2 \
pth_cond_destroy_busy.vgtest pth_cond_destroy_busy.stderr.exp \
pth_cond_destroy_busy.stderr.exp-ppc64 \
pth_cond_destroy_busy.stderr.exp-solaris \
diff --git a/helgrind/tests/Makefile.in b/helgrind/tests/Makefile.in
index 93a5383..5c43f05 100644
--- a/helgrind/tests/Makefile.in
+++ b/helgrind/tests/Makefile.in
@@ -112,7 +112,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -508,6 +508,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -678,6 +679,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -688,6 +690,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -762,8 +765,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -808,7 +809,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
@@ -876,7 +876,8 @@
pth_barrier2.vgtest pth_barrier2.stdout.exp pth_barrier2.stderr.exp \
pth_barrier3.vgtest pth_barrier3.stdout.exp pth_barrier3.stderr.exp \
pth_destroy_cond.vgtest \
- pth_destroy_cond.stdout.exp pth_destroy_cond.stderr.exp \
+ pth_destroy_cond.stdout.exp \
+ pth_destroy_cond.stderr.exp pth_destroy_cond.stderr.exp2 \
pth_cond_destroy_busy.vgtest pth_cond_destroy_busy.stderr.exp \
pth_cond_destroy_busy.stderr.exp-ppc64 \
pth_cond_destroy_busy.stderr.exp-solaris \
diff --git a/helgrind/tests/annotate_hbefore.c b/helgrind/tests/annotate_hbefore.c
index 9f3636c..74cf9d8 100644
--- a/helgrind/tests/annotate_hbefore.c
+++ b/helgrind/tests/annotate_hbefore.c
@@ -285,16 +285,6 @@
return success;
}
-#elif defined(VGA_tilegx)
-
-/* return 1 if success, 0 if failure */
-UWord do_acasW(UWord* addr, UWord expected, UWord nyu )
-{
- /* Load the compare value into special register 0x2780 */
- __insn_mtspr(0x2780, expected);
- return __insn_cmpexch(addr, nyu);
-}
-
#endif
void atomic_incW ( UWord* w )
diff --git a/helgrind/tests/bar_bad.c b/helgrind/tests/bar_bad.c
index 19cf81c..0882b03 100644
--- a/helgrind/tests/bar_bad.c
+++ b/helgrind/tests/bar_bad.c
@@ -81,6 +81,8 @@
/* and now destroy */
pthread_barrier_destroy(bar4);
+ pthread_cancel(slp2);
+
/* destroy a barrier that was never initialised. This is a bit
tricky, in that we have to fill the barrier with bytes which
ensure that the pthread_barrier_destroy call doesn't crash for
diff --git a/helgrind/tests/bar_bad.stderr.exp b/helgrind/tests/bar_bad.stderr.exp
index d0901b2..a675a18 100644
--- a/helgrind/tests/bar_bad.stderr.exp
+++ b/helgrind/tests/bar_bad.stderr.exp
@@ -60,5 +60,5 @@
Thread #x: pthread_barrier_destroy: barrier was never initialised
at 0x........: pthread_barrier_destroy (hg_intercepts.c:...)
- by 0x........: main (bar_bad.c:96)
+ by 0x........: main (bar_bad.c:98)
diff --git a/helgrind/tests/bar_bad.stderr.exp-destroy-hang b/helgrind/tests/bar_bad.stderr.exp-destroy-hang
index ddf5624..f76663f 100644
--- a/helgrind/tests/bar_bad.stderr.exp-destroy-hang
+++ b/helgrind/tests/bar_bad.stderr.exp-destroy-hang
@@ -68,5 +68,5 @@
Thread #x: pthread_barrier_destroy: barrier was never initialised
at 0x........: pthread_barrier_destroy (hg_intercepts.c:...)
- by 0x........: main (bar_bad.c:96)
+ by 0x........: main (bar_bad.c:98)
diff --git a/helgrind/tests/bar_bad.vgtest b/helgrind/tests/bar_bad.vgtest
index fe946f5..cb3a1ca 100644
--- a/helgrind/tests/bar_bad.vgtest
+++ b/helgrind/tests/bar_bad.vgtest
@@ -1,3 +1,3 @@
prereq: test -e bar_bad
prog: bar_bad
-vgopts: -q
+vgopts: -q --fair-sched=try
diff --git a/helgrind/tests/pth_cond_destroy_busy.vgtest b/helgrind/tests/pth_cond_destroy_busy.vgtest
index 45d7853..2957cc3 100644
--- a/helgrind/tests/pth_cond_destroy_busy.vgtest
+++ b/helgrind/tests/pth_cond_destroy_busy.vgtest
@@ -1,2 +1,2 @@
-prereq: ! ../../tests/os_test darwin
+prereq: ! ../../tests/os_test darwin && ! ../../tests/libc_test glibc 2.24.90
prog: ../../drd/tests/pth_cond_destroy_busy
diff --git a/helgrind/tests/pth_destroy_cond.stderr.exp2 b/helgrind/tests/pth_destroy_cond.stderr.exp2
new file mode 100644
index 0000000..593b4ef
--- /dev/null
+++ b/helgrind/tests/pth_destroy_cond.stderr.exp2
@@ -0,0 +1,44 @@
+---Thread-Announcement------------------------------------------
+
+Thread #x was created
+ ...
+ by 0x........: pthread_create@* (hg_intercepts.c:...)
+ by 0x........: main (pth_destroy_cond.c:29)
+
+---Thread-Announcement------------------------------------------
+
+Thread #x is the program's root thread
+
+----------------------------------------------------------------
+
+ Lock at 0x........ was first observed
+ at 0x........: pthread_mutex_init (hg_intercepts.c:...)
+ by 0x........: main (pth_destroy_cond.c:25)
+ Address 0x........ is 0 bytes inside data symbol "mutex"
+
+Possible data race during read of size 1 at 0x........ by thread #x
+Locks held: 1, at address 0x........
+ at 0x........: my_memcmp (hg_intercepts.c:...)
+ by 0x........: pthread_cond_destroy_WRK (hg_intercepts.c:...)
+ by 0x........: pthread_cond_destroy@* (hg_intercepts.c:...)
+ by 0x........: ThreadFunction (pth_destroy_cond.c:18)
+ by 0x........: mythread_wrapper (hg_intercepts.c:...)
+ ...
+
+This conflicts with a previous write of size 4 by thread #x
+Locks held: none
+ ...
+ by 0x........: pthread_cond_wait_WRK (hg_intercepts.c:...)
+ by 0x........: pthread_cond_wait@* (hg_intercepts.c:...)
+ by 0x........: main (pth_destroy_cond.c:31)
+ Address 0x........ is 4 bytes inside data symbol "cond"
+
+----------------------------------------------------------------
+
+Thread #x: pthread_cond_destroy: destruction of condition variable being waited upon
+ at 0x........: pthread_cond_destroy_WRK (hg_intercepts.c:...)
+ by 0x........: pthread_cond_destroy@* (hg_intercepts.c:...)
+ by 0x........: ThreadFunction (pth_destroy_cond.c:18)
+ by 0x........: mythread_wrapper (hg_intercepts.c:...)
+ ...
+
diff --git a/helgrind/tests/tc07_hbl1.c b/helgrind/tests/tc07_hbl1.c
index e46a405..1744dc1 100644
--- a/helgrind/tests/tc07_hbl1.c
+++ b/helgrind/tests/tc07_hbl1.c
@@ -16,7 +16,6 @@
#undef PLAT_arm64_linux
#undef PLAT_s390x_linux
#undef PLAT_mips32_linux
-#undef PLAT_tilegx_linux
#undef PLAT_x86_solaris
#undef PLAT_amd64_solaris
@@ -40,8 +39,6 @@
# define PLAT_s390x_linux 1
#elif defined(__linux__) && defined(__mips__)
# define PLAT_mips32_linux 1
-#elif defined(__linux__) && defined(__tilegx__)
-# define PLAT_tilegx_linux 1
#elif defined(__sun__) && defined(__i386__)
# define PLAT_x86_solaris 1
#elif defined(__sun__) && defined(__x86_64__)
@@ -113,12 +110,6 @@
: /*out*/ : /*in*/ "r"(&(_lval)) \
: /*trash*/ "$8", "$9", "$10", "cc", "memory" \
)
-#elif defined(PLAT_tilegx_linux)
-# define INC(_lval,_lqual) \
- if (sizeof(_lval) == 4) \
- __insn_fetchadd(&(_lval), 1); \
- else if(sizeof(_lval) == 8) \
- __insn_fetchadd(&(_lval), 1)
#else
# error "Fix Me for this platform"
#endif
diff --git a/helgrind/tests/tc08_hbl2.c b/helgrind/tests/tc08_hbl2.c
index 4913abe..2a757a0 100644
--- a/helgrind/tests/tc08_hbl2.c
+++ b/helgrind/tests/tc08_hbl2.c
@@ -33,7 +33,6 @@
#undef PLAT_s390x_linux
#undef PLAT_mips32_linux
#undef PLAT_mips64_linux
-#undef PLAT_tilegx_linux
#undef PLAT_x86_solaris
#undef PLAT_amd64_solaris
@@ -61,8 +60,6 @@
#else
# define PLAT_mips32_linux 1
#endif
-#elif defined(__linux__) && defined(__tilegx__)
-# define PLAT_tilegx_linux 1
#elif defined(__sun__) && defined(__i386__)
# define PLAT_x86_solaris 1
#elif defined(__sun__) && defined(__x86_64__)
@@ -133,12 +130,6 @@
: /*out*/ : /*in*/ "r"(&(_lval)) \
: /*trash*/ "t0", "t1", "memory" \
)
-#elif defined(PLAT_tilegx_linux)
-# define INC(_lval,_lqual) \
- if (sizeof(_lval) == 4) \
- __insn_fetchadd(&(_lval), 1); \
- else if(sizeof(_lval) == 8) \
- __insn_fetchadd(&(_lval), 1)
#else
# error "Fix Me for this platform"
#endif
diff --git a/helgrind/tests/tc11_XCHG.c b/helgrind/tests/tc11_XCHG.c
index 30fccee..48fc1b1 100644
--- a/helgrind/tests/tc11_XCHG.c
+++ b/helgrind/tests/tc11_XCHG.c
@@ -18,7 +18,6 @@
#undef PLAT_arm_linux
#undef PLAT_s390x_linux
#undef PLAT_mips32_linux
-#undef PLAT_tilegx_linux
#undef PLAT_x86_solaris
#undef PLAT_amd64_solaris
@@ -42,8 +41,6 @@
# define PLAT_s390x_linux 1
#elif defined(__linux__) && defined(__mips__)
# define PLAT_mips32_linux 1
-#elif defined(__linux__) && defined(__tilegx__)
-# define PLAT_tilegx_linux 1
#elif defined(__sun__) && defined(__i386__)
# define PLAT_x86_solaris 1
#elif defined(__sun__) && defined(__x86_64__)
@@ -125,12 +122,6 @@
# define XCHG_M_R_with_redundant_LOCK(_addr,_lval) \
XCHG_M_R(_addr,_lval)
-#elif defined(PLAT_tilegx_linux)
-# define XCHG_M_R(_addr,_lval) \
- _lval = __insn_exch4(&_addr, _lval)
-
-# define XCHG_M_R_with_redundant_LOCK(_addr,_lval) \
- XCHG_M_R(_addr, _lval)
#else
# error "Unsupported architecture"
diff --git a/helgrind/tests/tc23_bogus_condwait.c b/helgrind/tests/tc23_bogus_condwait.c
index 0a1b5f3..6ea5ad9 100644
--- a/helgrind/tests/tc23_bogus_condwait.c
+++ b/helgrind/tests/tc23_bogus_condwait.c
@@ -69,7 +69,7 @@
r= pthread_cond_wait(&cv, (pthread_mutex_t*)(4 + (char*)&mx[0]) );
/* mx is not locked */
- r= pthread_cond_wait(&cv, &mx[0]);
+ r= pthread_cond_wait(&cv, &mx[3]);
/* wrong flavour of lock */
r= pthread_cond_wait(&cv, (pthread_mutex_t*)&rwl );
diff --git a/include/Makefile.am b/include/Makefile.am
index ccfcd27..11c7ca8 100644
--- a/include/Makefile.am
+++ b/include/Makefile.am
@@ -43,6 +43,8 @@
pub_tool_vkiscnums_asm.h \
pub_tool_wordfm.h \
pub_tool_xarray.h \
+ pub_tool_xtree.h \
+ pub_tool_xtmemory.h \
valgrind.h \
vki/vki-linux.h \
vki/vki-darwin.h \
diff --git a/include/Makefile.in b/include/Makefile.in
index 687ab2f..38c483e 100644
--- a/include/Makefile.in
+++ b/include/Makefile.in
@@ -212,6 +212,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -386,6 +387,8 @@
pub_tool_vkiscnums_asm.h \
pub_tool_wordfm.h \
pub_tool_xarray.h \
+ pub_tool_xtree.h \
+ pub_tool_xtmemory.h \
valgrind.h \
vki/vki-linux.h \
vki/vki-darwin.h \
diff --git a/include/pub_tool_addrinfo.h b/include/pub_tool_addrinfo.h
index 5dc66cd..5808878 100644
--- a/include/pub_tool_addrinfo.h
+++ b/include/pub_tool_addrinfo.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -145,7 +145,7 @@
// blocks and Arena blocks.
// alloc_tinfo identifies the thread that has allocated the block.
// This is used by tools such as helgrind that maintain
- // more detailed informations about client blocks.
+ // more detailed information about client blocks.
struct {
BlockKind block_kind;
const HChar* block_desc; // "block","mempool","user-defined",arena
diff --git a/include/pub_tool_aspacehl.h b/include/pub_tool_aspacehl.h
index 4210367..fd523ca 100644
--- a/include/pub_tool_aspacehl.h
+++ b/include/pub_tool_aspacehl.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2009-2015 Julian Seward
+ Copyright (C) 2009-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/pub_tool_aspacemgr.h b/include/pub_tool_aspacemgr.h
index 4a83e35..5ea671d 100644
--- a/include/pub_tool_aspacemgr.h
+++ b/include/pub_tool_aspacemgr.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/pub_tool_basics.h b/include/pub_tool_basics.h
index 810e27e..e3af283 100644
--- a/include/pub_tool_basics.h
+++ b/include/pub_tool_basics.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -129,6 +129,17 @@
/* ThreadIds are simply indices into the VG_(threads)[] array. */
typedef UInt ThreadId;
+/* Many data structures need to allocate and release memory.
+ The allocation/release functions must be provided by the caller.
+ The Alloc_Fn_t function must allocate a chunk of memory of size szB.
+ cc is the Cost Centre for this allocated memory. This constant string
+ is used to provide Valgrind's heap profiling, activated by
+ --profile-heap=no|yes.
+ The corresponding Free_Fn_t frees the memory chunk p. */
+
+typedef void* (*Alloc_Fn_t) ( const HChar* cc, SizeT szB );
+typedef void (*Free_Fn_t) ( void* p );
+
/* An abstraction of syscall return values.
Linux/MIPS32 and Linux/MIPS64:
When _isError == False,
@@ -231,7 +242,7 @@
}
static inline Bool sr_EQ ( UInt sysno, SysRes sr1, SysRes sr2 ) {
/* This uglyness of hardcoding syscall numbers is necessary to
- avoid having this header file be dependant on
+ avoid having this header file be dependent on
include/vki/vki-scnums-mips{32,64}-linux.h. It seems pretty
safe given that it is inconceivable that the syscall numbers
for such simple syscalls would ever change. To make it
@@ -348,8 +359,8 @@
static inline Bool sr_EQ ( UInt sysno, SysRes sr1, SysRes sr2 ) {
/* sysno is ignored for Solaris */
return sr1._val == sr2._val
- && sr1._val2 == sr2._val2
- && sr1._isError == sr2._isError;
+ && sr1._isError == sr2._isError
+ && (!sr1._isError) ? (sr1._val2 == sr2._val2) : True;
}
#else
@@ -371,7 +382,7 @@
#if defined(VGA_x86) || defined(VGA_amd64) || defined (VGA_arm) \
|| ((defined(VGA_mips32) || defined(VGA_mips64)) && defined (_MIPSEL)) \
- || defined(VGA_arm64) || defined(VGA_ppc64le) || defined(VGA_tilegx)
+ || defined(VGA_arm64) || defined(VGA_ppc64le)
# define VG_LITTLEENDIAN 1
#elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_s390x) \
|| ((defined(VGA_mips32) || defined(VGA_mips64)) && defined (_MIPSEB))
@@ -385,6 +396,10 @@
# define offsetof(type,memb) ((SizeT)(HWord)&((type*)0)->memb)
#endif
+#if !defined(container_of)
+# define container_of(ptr, type, member) ((type *)((char *)(ptr) - offsetof(type, member)))
+#endif
+
/* Alignment */
/* We use a prefix vg_ for vg_alignof as its behaviour slightly
differs from the standard alignof/gcc defined __alignof__
@@ -414,7 +429,7 @@
|| defined(VGA_ppc64be) || defined(VGA_ppc64le) \
|| defined(VGA_arm) || defined(VGA_s390x) \
|| defined(VGA_mips32) || defined(VGA_mips64) \
- || defined(VGA_arm64) || defined(VGA_tilegx)
+ || defined(VGA_arm64)
# define VG_REGPARM(n) /* */
#else
# error Unknown arch
@@ -457,6 +472,18 @@
} var = { .in = x }; var.out; \
})
+/* Some architectures (eg. mips, arm) do not support unaligned memory access
+ by hardware, so GCC warns about suspicious situations. This macro could
+ be used to avoid these warnings but only after careful examination. */
+#define ASSUME_ALIGNED(D, x) \
+ ({ \
+ union { \
+ void *in; \
+ D out; \
+ } var; \
+ var.in = (void *) (x); var.out; \
+ })
+
// Poor man's static assert
#define STATIC_ASSERT(x) extern int VG_(VG_(VG_(unused)))[(x) ? 1 : -1] \
__attribute__((unused))
diff --git a/include/pub_tool_basics_asm.h b/include/pub_tool_basics_asm.h
index d73c91e..a2f1056 100644
--- a/include/pub_tool_basics_asm.h
+++ b/include/pub_tool_basics_asm.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/pub_tool_clientstate.h b/include/pub_tool_clientstate.h
index af0fbbf..d1b764e 100644
--- a/include/pub_tool_clientstate.h
+++ b/include/pub_tool_clientstate.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/pub_tool_clreq.h b/include/pub_tool_clreq.h
index b3798e0..37af2ce 100644
--- a/include/pub_tool_clreq.h
+++ b/include/pub_tool_clreq.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/pub_tool_debuginfo.h b/include/pub_tool_debuginfo.h
index 49ceffb..6250e1b 100644
--- a/include/pub_tool_debuginfo.h
+++ b/include/pub_tool_debuginfo.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -38,12 +38,44 @@
/*=== Obtaining debug information ===*/
/*====================================================================*/
+/* IMPORTANT COMMENT about memory persistence and ownership.
+
+ Many functions below are returning a string in a HChar** argument.
+ This memory must not be freed by the caller : it belongs to the debuginfo
+ module. The returned string is *not* guaranteed to be persistent.
+ The exact persistence depends on the kind of information returned,
+ and of the internal implementation of the debuginfo module.
+ In other words: use the memory directly after the call, and if in doubt,
+ save it away.
+
+ In general, all returned strings will be invalidated when the
+ DebugInfo they correspond to is discarded. This is the case for
+ the filename, dirname, fnname and objname.
+ An objname might also be invalidated by changes to the address
+ space manager segments, e.g. if a segment is merged with another
+ segment.
+
+ Retrieving a fnname might imply a call to the c++ demangler.
+ A returned fnname is invalidated if any other call to the demangler
+ is done. In particular, this means that the memory returned by one of
+ the VG_(get_fnname...) functions is invalidated by :
+ * another call to any of the functions VG_(get_fnname...).
+ * any other call that will directly or indirectly invoke the
+ c++ demangler. Such an indirect call to the demangler can a.o. be
+ done by calls to pub_tool_errormgr.h functions.
+ So, among others, the following is WRONG:
+ VG_(get_fnname)(a1, &fnname1);
+ VG_(get_fnname)(a2, &fnname2);
+ ... it is WRONG to use fnname1 here ....
+*/
+
/* Get the file/function/line number of the instruction at address
'a'. For these four, if debug info for the address is found, it
copies the info into the buffer/UInt and returns True. If not, it
returns False. VG_(get_fnname) always
demangles C++ function names. VG_(get_fnname_w_offset) is the
- same, except it appends "+N" to symbol names to indicate offsets. */
+ same, except it appends "+N" to symbol names to indicate offsets.
+ NOTE: See IMPORTANT COMMENT above about persistence and ownership. */
extern Bool VG_(get_filename) ( Addr a, const HChar** filename );
extern Bool VG_(get_fnname) ( Addr a, const HChar** fnname );
extern Bool VG_(get_linenum) ( Addr a, UInt* linenum );
@@ -58,9 +90,7 @@
it is available; if not available, '\0' is written to the first
byte.
- The character strings returned in *filename and *dirname are not
- persistent. They will be freed when the DebugInfo they belong to
- is discarded.
+ NOTE: See IMPORTANT COMMENT above about persistence and ownership.
Returned value indicates whether any filename/line info could be
found. */
@@ -76,7 +106,8 @@
instruction in a function. Use this to instrument the start of
a particular function. Nb: if an executable/shared object is stripped
of its symbols, this function will not be able to recognise function
- entry points within it. */
+ entry points within it.
+ NOTE: See IMPORTANT COMMENT above about persistence and ownership. */
extern Bool VG_(get_fnname_if_entry) ( Addr a, const HChar** fnname );
typedef
@@ -120,7 +151,9 @@
);
/* Succeeds if the address is within a shared object or the main executable.
- It doesn't matter if debug info is present or not. */
+ It first searches if Addr a belongs to the text segment of debug info.
+ If not found, it asks the address space manager whether it
+ knows the name of the file associated with this mapping. */
extern Bool VG_(get_objname) ( Addr a, const HChar** objname );
@@ -261,10 +294,10 @@
const HChar* VG_(pp_SectKind)( VgSectKind kind );
/* Given an address 'a', make a guess of which section of which object
- it comes from. If name is non-NULL, then the object's name is put
- into *name. The returned name is persistent as long as the debuginfo
- it belongs to isn't discarded. */
-VgSectKind VG_(DebugInfo_sect_kind)( /*OUT*/const HChar** name, Addr a);
+ it comes from. If objname is non-NULL, then the object's name is put
+ into *objname. This only looks in debug info, it does not examine
+ the address space manager mapped files. */
+VgSectKind VG_(DebugInfo_sect_kind)( /*OUT*/const HChar** objname, Addr a);
#endif // __PUB_TOOL_DEBUGINFO_H
diff --git a/include/pub_tool_deduppoolalloc.h b/include/pub_tool_deduppoolalloc.h
index a4c1a09..e9eced8 100644
--- a/include/pub_tool_deduppoolalloc.h
+++ b/include/pub_tool_deduppoolalloc.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2014-2015 Philippe Waroquiers philippe.waroquiers@skynet.be
+ Copyright (C) 2014-2017 Philippe Waroquiers philippe.waroquiers@skynet.be
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -44,8 +44,8 @@
// individually.
// Once allocated, an element must not be modified anymore.
//
-// Elements can be inserted in the pool using VG_(allocEltDedupPA)
-// or using VG_(allocFixedEltDedupPA).
+// Elements can be inserted in the pool using VG_(allocEltDedupPA),
+// VG_(allocFixedEltDedupPA) or VG_(allocStrDedupPA).
//
// Use VG_(allocFixedEltDedupPA) to allocate elements that are all of
// the same size and that you want to identify with a (small) number:
@@ -65,6 +65,10 @@
// The address of an element allocated with VG_(allocEltDedupPA) does
// not change, even if new elements are inserted in the pool.
//
+// Use VG_(allocStrDedupPA) to create a pool of strings (in other words, a
+// dictionnary of strings). Similarly to VG_(allocFixedEltDedupPA), strings
+// inserted in a dedup pool can be identified by an element number.
+//
// In the same pool, you can only use one of the allocate element functions.
//
// A dedup pool allocator has significantly less memory overhead than
@@ -89,33 +93,46 @@
This function never returns NULL. */
extern DedupPoolAlloc* VG_(newDedupPA) ( SizeT poolSzB,
SizeT eltAlign,
- void* (*alloc)(const HChar*, SizeT),
+ Alloc_Fn_t alloc_fn,
const HChar* cc,
- void (*free_fn)(void*) );
+ Free_Fn_t free_fn );
-/* Allocates a new element from ddpa with eltSzB bytes to store elt.
+/* Allocates or retrieve element from ddpa with eltSzB bytes to store elt.
This function never returns NULL.
If ddpa already contains an element equal to elt, then the address of
the already existing element is returned.
Equality between elements is done by comparing all bytes.
So, if void *elt points to a struct, be sure to initialise all components
and the holes between components. */
-extern const void* VG_(allocEltDedupPA) (DedupPoolAlloc *ddpa,
- SizeT eltSzB, const void *elt);
+extern const void* VG_(allocEltDedupPA) (DedupPoolAlloc* ddpa,
+ SizeT eltSzB, const void* elt);
-/* Allocates a new (fixed size) element from ddpa. Returns the
- unique number identifying this element. This function never returns NULL.
+/* Allocates or retrieve a (fixed size) element from ddpa. Returns the
+ unique number identifying this element.
Similarly to VG_(allocEltDedupPA), this will return the unique number
of an already existing identical element to elt. */
-extern UInt VG_(allocFixedEltDedupPA) (DedupPoolAlloc *ddpa,
- SizeT eltSzB, const void *elt);
+extern UInt VG_(allocFixedEltDedupPA) (DedupPoolAlloc* ddpa,
+ SizeT eltSzB, const void* elt);
/* Translate an element number to its address. Note that the address
corresponding to eltNr can change if new elements are inserted
in the pool. */
-extern void* VG_(indexEltNumber) (DedupPoolAlloc *ddpa,
+extern void* VG_(indexEltNumber) (DedupPoolAlloc* ddpa,
UInt eltNr);
+/* Allocates or retrieve a string element from ddpa. Returns the
+ unique number identifying this string.
+ newStr is set to True if the str is a newly inserted string, False
+ if the str was already present in the pool.
+ Similarly to VG_(allocEltDedupPA), this will return the unique number
+ of an already existing identical string. */
+extern UInt VG_(allocStrDedupPA) (DedupPoolAlloc *ddpa,
+ const HChar* str,
+ Bool* newStr);
+/* Note: Implementing a function to return the string value from its strNr
+ implies some overhead, so will be done only if/when needed. */
+
+
/* The Dedup Pool Allocator must maintain a data structure to avoid
duplicates as long as new elements can be allocated from the pool.
Once no new elements will be allocated, this dedup data structure
@@ -123,14 +140,14 @@
it is an error to call VG_(allocEltDedupPA) or VG_(allocFixedEltDedupPA).
If shrink_block is not NULL, the last pool will be shrunk using
shrink_block. */
-extern void VG_(freezeDedupPA) (DedupPoolAlloc *ddpa,
+extern void VG_(freezeDedupPA) (DedupPoolAlloc* ddpa,
void (*shrink_block)(void*, SizeT));
/* How many (unique) elements are there in this ddpa now? */
-extern UInt VG_(sizeDedupPA) (DedupPoolAlloc *ddpa);
+extern UInt VG_(sizeDedupPA) (DedupPoolAlloc* ddpa);
/* Free all memory associated with a DedupPoolAlloc. */
-extern void VG_(deleteDedupPA) ( DedupPoolAlloc *ddpa);
+extern void VG_(deleteDedupPA) ( DedupPoolAlloc* ddpa);
#endif // __PUB_TOOL_DEDUPPOOLALLOC_
diff --git a/include/pub_tool_errormgr.h b/include/pub_tool_errormgr.h
index 1b9fdfe..7af6783 100644
--- a/include/pub_tool_errormgr.h
+++ b/include/pub_tool_errormgr.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/pub_tool_execontext.h b/include/pub_tool_execontext.h
index 9ce3a24..9841962 100644
--- a/include/pub_tool_execontext.h
+++ b/include/pub_tool_execontext.h
@@ -6,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/pub_tool_gdbserver.h b/include/pub_tool_gdbserver.h
index d4c826b..061c594 100644
--- a/include/pub_tool_gdbserver.h
+++ b/include/pub_tool_gdbserver.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2015 Philippe Waroquiers
+ Copyright (C) 2011-2017 Philippe Waroquiers
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/include/pub_tool_guest.h b/include/pub_tool_guest.h
index 2178aca..b28e4ec 100644
--- a/include/pub_tool_guest.h
+++ b/include/pub_tool_guest.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2014-2015 OpenWorks LLP
+ Copyright (C) 2014-2017 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -64,9 +64,6 @@
#elif defined(VGA_mips64)
# include "libvex_guest_mips64.h"
typedef VexGuestMIPS64State VexGuestArchState;
-#elif defined(VGA_tilegx)
-# include "libvex_guest_tilegx.h"
- typedef VexGuestTILEGXState VexGuestArchState;
#else
# error Unknown arch
#endif
diff --git a/include/pub_tool_hashtable.h b/include/pub_tool_hashtable.h
index a6cbe1c..2267367 100644
--- a/include/pub_tool_hashtable.h
+++ b/include/pub_tool_hashtable.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Nicholas Nethercote
+ Copyright (C) 2005-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
diff --git a/include/pub_tool_libcassert.h b/include/pub_tool_libcassert.h
index b606d00..1b9dd7f 100644
--- a/include/pub_tool_libcassert.h
+++ b/include/pub_tool_libcassert.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/pub_tool_libcbase.h b/include/pub_tool_libcbase.h
index 3433173..f68579a 100644
--- a/include/pub_tool_libcbase.h
+++ b/include/pub_tool_libcbase.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -80,11 +80,13 @@
&& VG_(strncmp)((s1),(s2),(n))==0) ? True : False )
extern SizeT VG_(strlen) ( const HChar* str );
+extern SizeT VG_(strnlen) ( const HChar* str, SizeT n );
extern HChar* VG_(strcat) ( HChar* dest, const HChar* src );
extern HChar* VG_(strncat) ( HChar* dest, const HChar* src, SizeT n );
extern HChar* VG_(strpbrk) ( const HChar* s, const HChar* accpt );
extern HChar* VG_(strcpy) ( HChar* dest, const HChar* src );
extern HChar* VG_(strncpy) ( HChar* dest, const HChar* src, SizeT ndest );
+extern SizeT VG_(strlcpy) ( HChar* dest, const HChar* src, SizeT n );
extern Int VG_(strcmp) ( const HChar* s1, const HChar* s2 );
extern Int VG_(strcasecmp) ( const HChar* s1, const HChar* s2 );
extern Int VG_(strncmp) ( const HChar* s1, const HChar* s2, SizeT nmax );
diff --git a/include/pub_tool_libcfile.h b/include/pub_tool_libcfile.h
index c126e1d..c03842a 100644
--- a/include/pub_tool_libcfile.h
+++ b/include/pub_tool_libcfile.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/pub_tool_libcprint.h b/include/pub_tool_libcprint.h
index bda41c2..fe74628 100644
--- a/include/pub_tool_libcprint.h
+++ b/include/pub_tool_libcprint.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/pub_tool_libcproc.h b/include/pub_tool_libcproc.h
index cc1f9a8..a3a186b 100644
--- a/include/pub_tool_libcproc.h
+++ b/include/pub_tool_libcproc.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/pub_tool_libcsetjmp.h b/include/pub_tool_libcsetjmp.h
index 61f897b..d6c6b98 100644
--- a/include/pub_tool_libcsetjmp.h
+++ b/include/pub_tool_libcsetjmp.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 Mozilla Inc
+ Copyright (C) 2010-2017 Mozilla Inc
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -114,7 +114,15 @@
#elif defined(VGP_mips32_linux)
-#define VG_MINIMAL_JMP_BUF(_name) UInt _name [8+1+1+1+1]
+#define VG_MINIMAL_JMP_BUF(_name) ULong _name [104 / sizeof(ULong)]
+__attribute__((returns_twice))
+UWord VG_MINIMAL_SETJMP(VG_MINIMAL_JMP_BUF(_env));
+__attribute__((noreturn))
+void VG_MINIMAL_LONGJMP(VG_MINIMAL_JMP_BUF(_env));
+
+#elif defined(VGP_mips64_linux)
+
+#define VG_MINIMAL_JMP_BUF(_name) ULong _name [168 / sizeof(ULong)]
__attribute__((returns_twice))
UWord VG_MINIMAL_SETJMP(VG_MINIMAL_JMP_BUF(_env));
__attribute__((noreturn))
diff --git a/include/pub_tool_libcsignal.h b/include/pub_tool_libcsignal.h
index 88770d8..82d3082 100644
--- a/include/pub_tool_libcsignal.h
+++ b/include/pub_tool_libcsignal.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/pub_tool_machine.h b/include/pub_tool_machine.h
index 4ec31ab..07b7b95 100644
--- a/include/pub_tool_machine.h
+++ b/include/pub_tool_machine.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -104,12 +104,6 @@
# define VG_CLREQ_SZB 20
# define VG_STACK_REDZONE_SZB 0
-#elif defined(VGP_tilegx_linux)
-# define VG_MIN_INSTR_SZB 8
-# define VG_MAX_INSTR_SZB 8
-# define VG_CLREQ_SZB 24
-# define VG_STACK_REDZONE_SZB 0
-
#else
# error Unknown platform
#endif
diff --git a/include/pub_tool_mallocfree.h b/include/pub_tool_mallocfree.h
index 0217f67..46db0ff 100644
--- a/include/pub_tool_mallocfree.h
+++ b/include/pub_tool_mallocfree.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/pub_tool_options.h b/include/pub_tool_options.h
index 94ed544..0f93483 100644
--- a/include/pub_tool_options.h
+++ b/include/pub_tool_options.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -223,6 +223,26 @@
extern VexControl VG_(clo_vex_control);
extern VexRegisterUpdates VG_(clo_px_file_backed);
+extern Int VG_(clo_redzone_size);
+
+typedef
+ enum {
+ Vg_XTMemory_None, // Do not do any xtree memory profiling.
+ Vg_XTMemory_Allocs, // Currently allocated size xtree memory profiling
+ Vg_XTMemory_Full, // Full profiling : Current allocated size, total
+ // allocated size, nr of blocks, total freed size, ...
+ }
+ VgXTMemory;
+// Tools that replace malloc can optionally implement memory profiling
+// following the value of VG_(clo_xtree_profile_memory) to produce a report
+// at the end of execution.
+extern VgXTMemory VG_(clo_xtree_memory);
+/* Holds the filename to use for xtree memory profiling output, before expansion
+ of %p and %q templates. */
+extern const HChar* VG_(clo_xtree_memory_file);
+/* Compress strings in xtree dumps. */
+extern Bool VG_(clo_xtree_compress_strings);
+
/* Number of parents of a backtrace. Default: 12 */
extern Int VG_(clo_backtrace_size);
diff --git a/include/pub_tool_oset.h b/include/pub_tool_oset.h
index 0c97997..cfdb603 100644
--- a/include/pub_tool_oset.h
+++ b/include/pub_tool_oset.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Nicholas Nethercote
+ Copyright (C) 2005-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -77,13 +77,8 @@
typedef struct _OSet OSet;
-// - Cmp: returns -1, 0 or 1 if key is <, == or > elem.
-// - Alloc: allocates a chunk of memory.
-// - Free: frees a chunk of memory allocated with Alloc.
-
+// - OSetCmp_t: returns -1, 0 or 1 if key is <, == or > elem.
typedef Word (*OSetCmp_t) ( const void* key, const void* elem );
-typedef void* (*OSetAlloc_t) ( const HChar* cc, SizeT szB );
-typedef void (*OSetFree_t) ( void* p );
/*--------------------------------------------------------------------*/
/*--- Creating and destroying OSets (UWord) ---*/
@@ -103,8 +98,8 @@
// to allow the destruction of any attached resources; if NULL it is not
// called.
-extern OSet* VG_(OSetWord_Create) ( OSetAlloc_t alloc_fn, const HChar* cc,
- OSetFree_t free_fn );
+extern OSet* VG_(OSetWord_Create) ( Alloc_Fn_t alloc_fn, const HChar* cc,
+ Free_Fn_t free_fn );
extern void VG_(OSetWord_Destroy) ( OSet* os );
/*--------------------------------------------------------------------*/
@@ -204,14 +199,14 @@
// lead to assertions in Valgrind's allocator.
extern OSet* VG_(OSetGen_Create) ( PtrdiffT keyOff, OSetCmp_t cmp,
- OSetAlloc_t alloc_fn, const HChar* cc,
- OSetFree_t free_fn);
+ Alloc_Fn_t alloc_fn, const HChar* cc,
+ Free_Fn_t free_fn);
extern OSet* VG_(OSetGen_Create_With_Pool) ( PtrdiffT keyOff, OSetCmp_t cmp,
- OSetAlloc_t alloc_fn,
+ Alloc_Fn_t alloc_fn,
const HChar* cc,
- OSetFree_t free_fn,
+ Free_Fn_t free_fn,
SizeT poolSize,
SizeT maxEltSize);
// Same as VG_(OSetGen_Create) but created OSet will use a pool allocator to
diff --git a/include/pub_tool_poolalloc.h b/include/pub_tool_poolalloc.h
index 549569f..cc54b7e 100644
--- a/include/pub_tool_poolalloc.h
+++ b/include/pub_tool_poolalloc.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2015 OpenWorks LLP info@open-works.co.uk,
+ Copyright (C) 2011-2017 OpenWorks LLP info@open-works.co.uk,
Philippe Waroquiers philippe.waroquiers@skynet.be
This program is free software; you can redistribute it and/or
@@ -56,9 +56,9 @@
This function never returns NULL. */
extern PoolAlloc* VG_(newPA) ( UWord elemSzB,
UWord nPerPool,
- void* (*alloc)(const HChar*, SizeT),
+ Alloc_Fn_t alloc_fn,
const HChar* cc,
- void (*free_fn)(void*) );
+ Free_Fn_t free_fn );
/* Free all memory associated with a PoolAlloc. */
diff --git a/include/pub_tool_rangemap.h b/include/pub_tool_rangemap.h
index 208b9dc..080fa95 100644
--- a/include/pub_tool_rangemap.h
+++ b/include/pub_tool_rangemap.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2014-2015 Mozilla Foundation
+ Copyright (C) 2014-2017 Mozilla Foundation
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -47,9 +47,9 @@
succeeded.) The new array will contain a single range covering the
entire key space, which will be bound to the value |initialVal|.
This function never returns NULL. */
-RangeMap* VG_(newRangeMap) ( void*(*alloc_fn)(const HChar*,SizeT),
+RangeMap* VG_(newRangeMap) ( Alloc_Fn_t alloc_fn,
const HChar* cc,
- void(*free_fn)(void*),
+ Free_Fn_t free_fn,
UWord initialVal );
/* Free all memory associated with a RangeMap. */
diff --git a/include/pub_tool_redir.h b/include/pub_tool_redir.h
index 4ff5155..c97941f 100644
--- a/include/pub_tool_redir.h
+++ b/include/pub_tool_redir.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -185,9 +185,10 @@
@ --> ZA (at)
$ --> ZD (dollar)
( --> ZL (left)
+ % --> ZP (percent)
) --> ZR (right)
+ / --> ZS (slash)
Z --> ZZ (Z)
- / --> ZS (slash)
Everything else is left unchanged.
*/
@@ -243,8 +244,11 @@
/* --- Soname of the standard C library. --- */
#if defined(VGO_linux) || defined(VGO_solaris)
+# if defined(MUSL_LIBC)
+# define VG_Z_LIBC_SONAME libcZdZa // libc.*
+#else
# define VG_Z_LIBC_SONAME libcZdsoZa // libc.so*
-
+#endif
#elif defined(VGO_darwin) && (DARWIN_VERS <= DARWIN_10_6)
# define VG_Z_LIBC_SONAME libSystemZdZaZddylib // libSystem.*.dylib
@@ -275,7 +279,11 @@
/* --- Soname of the pthreads library. --- */
#if defined(VGO_linux)
+# if defined(MUSL_LIBC)
+# define VG_Z_LIBPTHREAD_SONAME libcZdZa // libc.*
+#else
# define VG_Z_LIBPTHREAD_SONAME libpthreadZdsoZd0 // libpthread.so.0
+#endif
#elif defined(VGO_darwin)
# define VG_Z_LIBPTHREAD_SONAME libSystemZdZaZddylib // libSystem.*.dylib
#elif defined(VGO_solaris)
diff --git a/include/pub_tool_replacemalloc.h b/include/pub_tool_replacemalloc.h
index 2ce7ba5..e237fff 100644
--- a/include/pub_tool_replacemalloc.h
+++ b/include/pub_tool_replacemalloc.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/pub_tool_seqmatch.h b/include/pub_tool_seqmatch.h
index 3b0b210..760aecb 100644
--- a/include/pub_tool_seqmatch.h
+++ b/include/pub_tool_seqmatch.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2015 OpenWorks Ltd
+ Copyright (C) 2008-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/include/pub_tool_signals.h b/include/pub_tool_signals.h
index 1bab478..045e1d4 100644
--- a/include/pub_tool_signals.h
+++ b/include/pub_tool_signals.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/pub_tool_sparsewa.h b/include/pub_tool_sparsewa.h
index 982bfac..84c983d 100644
--- a/include/pub_tool_sparsewa.h
+++ b/include/pub_tool_sparsewa.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2015 OpenWorks Ltd
+ Copyright (C) 2008-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/include/pub_tool_stacktrace.h b/include/pub_tool_stacktrace.h
index 57dfbce..c442d39 100644
--- a/include/pub_tool_stacktrace.h
+++ b/include/pub_tool_stacktrace.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -66,7 +66,7 @@
// Apply a function to every element in the StackTrace. The parameter
// 'n' gives the index of the passed ip. 'opaque' is an arbitrary
-// pointer provided to each invokation of 'action' (a poor man's
+// pointer provided to each invocation of 'action' (a poor man's
// closure). Doesn't go below main() unless --show-below-main=yes is
// set.
extern void VG_(apply_StackTrace)(
diff --git a/include/pub_tool_threadstate.h b/include/pub_tool_threadstate.h
index 7ad176c..5aec49d 100644
--- a/include/pub_tool_threadstate.h
+++ b/include/pub_tool_threadstate.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/pub_tool_tooliface.h b/include/pub_tool_tooliface.h
index f7805e9..9f9d20a 100644
--- a/include/pub_tool_tooliface.h
+++ b/include/pub_tool_tooliface.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/pub_tool_transtab.h b/include/pub_tool_transtab.h
index fcfc1e0..63a2aa5 100644
--- a/include/pub_tool_transtab.h
+++ b/include/pub_tool_transtab.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2014-2015 Florian Krohm (florian@eich-krohm.de)
+ Copyright (C) 2014-2017 Florian Krohm (florian@eich-krohm.de)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/include/pub_tool_vki.h b/include/pub_tool_vki.h
index db7b84f..9c1615e 100644
--- a/include/pub_tool_vki.h
+++ b/include/pub_tool_vki.h
@@ -8,11 +8,11 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
- Copyright (C) 2005-2015 Nicholas Nethercote
+ Copyright (C) 2005-2017 Nicholas Nethercote
njn@valgrind.org
- Copyright (C) 2006-2015 OpenWorks LLP
+ Copyright (C) 2006-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/include/pub_tool_vkiscnums.h b/include/pub_tool_vkiscnums.h
index ff5df58..721948b 100644
--- a/include/pub_tool_vkiscnums.h
+++ b/include/pub_tool_vkiscnums.h
@@ -7,9 +7,9 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Nicholas Nethercote
+ Copyright (C) 2005-2017 Nicholas Nethercote
njn@valgrind.org
- Copyright (C) 2006-2015 OpenWorks LLP
+ Copyright (C) 2006-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/include/pub_tool_vkiscnums_asm.h b/include/pub_tool_vkiscnums_asm.h
index d6ea52a..2181757 100644
--- a/include/pub_tool_vkiscnums_asm.h
+++ b/include/pub_tool_vkiscnums_asm.h
@@ -7,9 +7,9 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Nicholas Nethercote
+ Copyright (C) 2005-2017 Nicholas Nethercote
njn@valgrind.org
- Copyright (C) 2006-2015 OpenWorks LLP
+ Copyright (C) 2006-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -63,9 +63,6 @@
#elif defined(VGP_x86_darwin) || defined(VGP_amd64_darwin)
# include "vki/vki-scnums-darwin.h"
-#elif defined(VGP_tilegx_linux)
-# include "vki/vki-scnums-tilegx-linux.h"
-
#elif defined(VGP_x86_solaris) || (VGP_amd64_solaris)
# include "vki/vki-scnums-solaris.h"
diff --git a/include/pub_tool_wordfm.h b/include/pub_tool_wordfm.h
index 239ae94..5a3d6da 100644
--- a/include/pub_tool_wordfm.h
+++ b/include/pub_tool_wordfm.h
@@ -9,13 +9,13 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2007-2015 Julian Seward
+ Copyright (C) 2007-2017 Julian Seward
jseward@acm.org
This code is based on previous work by Nicholas Nethercote
(coregrind/m_oset.c) which is
- Copyright (C) 2005-2015 Nicholas Nethercote
+ Copyright (C) 2005-2017 Nicholas Nethercote
njn@valgrind.org
which in turn was derived partially from:
diff --git a/include/pub_tool_xarray.h b/include/pub_tool_xarray.h
index 2b0fe99..fd3faaf 100644
--- a/include/pub_tool_xarray.h
+++ b/include/pub_tool_xarray.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2007-2015 OpenWorks LLP
+ Copyright (C) 2007-2017 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -54,9 +54,9 @@
for elements of the specified size. alloc_fn must not return NULL (that
is, if it returns it must have succeeded.)
This function never returns NULL. */
-extern XArray* VG_(newXA) ( void*(*alloc_fn)(const HChar*,SizeT),
+extern XArray* VG_(newXA) ( Alloc_Fn_t alloc_fn,
const HChar* cc,
- void(*free_fn)(void*),
+ Free_Fn_t free_fn,
Word elemSzB );
/* Free all memory associated with an XArray. */
@@ -166,6 +166,8 @@
extern void VG_(xaprintf)( XArray* dst, const HChar* format, ... )
PRINTF_CHECK(2, 3);
+/* Convenience function: linear search in an XArray of HChar*. */
+extern Bool VG_(strIsMemberXA)(const XArray* xa, const HChar* str );
#endif // __PUB_TOOL_XARRAY_H
/*--------------------------------------------------------------------*/
diff --git a/include/pub_tool_xtmemory.h b/include/pub_tool_xtmemory.h
new file mode 100644
index 0000000..4b899d4
--- /dev/null
+++ b/include/pub_tool_xtmemory.h
@@ -0,0 +1,86 @@
+
+/*-----------------------------------------------------------------------*/
+/*--- Support functions for xtree memory reports. pub_tool_xtmemory.h ---*/
+/*-----------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2016-2017 Philippe Waroquiers
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#ifndef __PUB_TOOL_XTMEMORY_H
+#define __PUB_TOOL_XTMEMORY_H
+
+/* Type to profile allocated size and nr of blocks, typically used for
+ --xtree-memory=allocs. */
+typedef
+ struct _XT_Allocs {
+ SizeT nbytes;
+ SizeT nblocks;
+ } XT_Allocs;
+
+/* Support functions to produce a full xtree memory profiling. */
+/* tool must call VG_(XTMemory_Full_init) to ini full xtree memory profiling. */
+extern void VG_(XTMemory_Full_init) (XT_filter_IPs_t filter_IPs_Fn);
+/* Then each time a certain nr of blocks are allocated or freed, the below
+ functions must be called. The arguments are:
+ szB: nr of bytes for the allocated/freed block(s)
+ ec_alloc : ExeContext of the allocation (original allocation for
+ free and resize_in_place).
+ ec_free : ExeContext of the free.
+ The tool is responsible to properly provide the ExeContext for
+ the allocation and free. For VG_(XTMemory_Full_free), ec_alloc
+ must be the one that was used for the allocation of the just released
+ block. */
+extern void VG_(XTMemory_Full_alloc)(SizeT szB,
+ ExeContext* ec_alloc);
+extern void VG_(XTMemory_Full_free)(SizeT szB,
+ ExeContext* ec_alloc,
+ ExeContext* ec_free);
+extern void VG_(XTMemory_Full_resize_in_place)(SizeT oldSzB, SizeT newSzB,
+ ExeContext* ec_alloc);
+
+/* Handle the production of a xtree memory report, either during run (fini False
+ e.g. via a gdb monitor command), or at the end of execution (fini True).
+
+ VG_(XTMemory_report) behaviour depends on the value of the command line
+ options --xtree-memory=none|allocs|full and --xtree-memory-file=<filename> :
+ If --xtree-memory=full, the report will be produced from the data
+ provided via the calls to void VG_(XTMemory_Full_*).
+ Otherwise, for --xtree-memory=allocs or for --xtree-memory=none (if fini
+ is False), next_block is used to get the data for the report:
+ next_block is called repetitively to get information about all allocated
+ blocks, till xta->nblocks is 0.
+ If filename is NULL, --xtree-memory-file is used to produce the name.
+ filter_IPs_fn : used for --xtree-memory=allocs/none filtering (see
+ VG_(XT_create) and XT_filter_IPs_t typdef for more information). */
+extern void VG_(XTMemory_report)
+ (const HChar* filename, Bool fini,
+ void (*next_block)(XT_Allocs* xta, ExeContext** ec_alloc),
+ XT_filter_IPs_t filter_IPs_fn);
+
+#endif // __PUB_TOOL_XTMEMORY_H
+
+
+/*-----------------------------------------------------------------------*/
+/*--- end pub_tool_xtmemory.h ---*/
+/*-----------------------------------------------------------------------*/
diff --git a/include/pub_tool_xtree.h b/include/pub_tool_xtree.h
new file mode 100644
index 0000000..ba9ad34
--- /dev/null
+++ b/include/pub_tool_xtree.h
@@ -0,0 +1,248 @@
+
+/*--------------------------------------------------------------------*/
+/*--- An xtree, tree of stacktraces with data pub_tool_xtree.h ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2015-2017 Philippe Waroquiers
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#ifndef __PUB_TOOL_XTREE_H
+#define __PUB_TOOL_XTREE_H
+
+#include "pub_tool_basics.h"
+#include "pub_tool_execontext.h"
+
+//--------------------------------------------------------------------
+// PURPOSE: an XTree is conceptually a set of stacktraces organised
+// as a tree structure.
+// A stacktrace (an Addr* ips, i.e. an array of IPs : Instruction Pointers)
+// can be added to the tree once transformed into an execontext (ec).
+// Some data (typically one or more integer values) can be attached to
+// leafs of the tree.
+// Non-leaf nodes data is build by combining (typically adding together)
+// the data of their children nodes.
+// An XTree can be output in various formats.
+//
+//--------------------------------------------------------------------
+
+
+/* It's an abstract type. */
+typedef struct _XTree XTree;
+
+/* 3 functions types used by an xtree to manipulate the data attached to leafs
+ of an XTree.
+ XT_init_data_t function is used to initialise (typically to 0) the data
+ of a new node.
+ XT_add_data_t function is used to add 'value' to the data 'to'.
+ XT_sub_data_t function is used to substract 'value' from the data 'from'.
+
+ Note that the add/sub functions can do whatever operations to
+ combine/integrate value with/into to or from. In other words, add/sub
+ functions are in fact equivalent to 'Reduce' functions. Add/sub is used
+ as it is assumed that this module will be mostly used to follow
+ resource consumption, which can be more clearly modelled with add/sub.
+ For such resource consumption usage, typically, a call to add means that
+ some additional resource has been allocated or consumed or ... by the
+ given ExeContext. Similarly, a call to sub means that some resource
+ has been released/freed/... by the given execontext.
+
+ Note however that there is no constraints in what add (or sub) can do. For
+ example, the add function could maintain Min/Max values, or an histogram of
+ values, or ... */
+typedef void (*XT_init_data_t) (void* value);
+typedef void (*XT_add_data_t) (void* to, const void* value);
+typedef void (*XT_sub_data_t) (void* from, const void* value);
+
+/* If not NULL, the XT_filter_IPs_t function is called when a new ec is inserted
+ in the XTree.
+ It indicates to the XTree to filter a range of IPs at the top and/or at
+ the bottom of the ec Stacktrace : *top is the offset of the first IP to take
+ into account. *n_ips_sel is the nr of IPs selected starting from *top.
+
+ If XT_filter_IPs_t gives *n_ips_sel equal to 0, then the inserted ec will
+ be fully ignored when outputting the xtree:
+ the ec value(s) will not be counted in the XTree total,
+ the ec will not be printed/shown.
+ Note however that the filtering only influences the output of an XTree :
+ the ec is still inserted in the XTree, and the XT_*_data_t functions are
+ called in any case for such filtered ec. */
+typedef void (*XT_filter_IPs_t) (Addr* ips, Int n_ips,
+ UInt* top, UInt* n_ips_sel);
+
+/* Create new XTree, using given allocation and free function.
+ This function never returns NULL.
+ cc is the allocation cost centre.
+ alloc_fn must not return NULL (that is, if it returns it must have
+ succeeded.).
+ See respective typedef for *_fn arguments. */
+extern XTree* VG_(XT_create) ( Alloc_Fn_t alloc_fn,
+ const HChar* cc,
+ Free_Fn_t free_fn,
+ Word dataSzB,
+ XT_init_data_t init_data_fn,
+ XT_add_data_t add_data_fn,
+ XT_sub_data_t sub_data_fn,
+ XT_filter_IPs_t filter_IPs_fn);
+
+
+/* General useful filtering functions. */
+
+/* Filter functions below main, unless VG_(clo_show_below_main) is True. */
+extern void VG_(XT_filter_maybe_below_main)
+ (Addr* ips, Int n_ips,
+ UInt* top, UInt* n_ips_sel);
+/* Same as VG_(XT_filter_maybe_below_main) but also filters one top function
+ (typically to ignore the top level malloc/new/... fn). */
+extern void VG_(XT_filter_1top_and_maybe_below_main)
+ (Addr* ips, Int n_ips,
+ UInt* top, UInt* n_ips_sel);
+
+/* Search in ips[0..n_ips-1] the first function which is main or below main
+ and return its offset.
+ If no main or below main is found, return n_ips-1 */
+extern Int VG_(XT_offset_main_or_below_main)(Addr* ips, Int n_ips);
+
+
+/* Take a (frozen) snapshot of xt.
+ Note that the resulting XTree is 'read-only' : calls to
+ VG_(XT_add_to_*)/VG_(XT_sub_from_*) will assert.
+
+ Note: to spare memory, some data is shared between an xt and all its
+ snapshots. This memory is released when the last XTree using this memory
+ is deleted. */
+extern XTree* VG_(XT_snapshot)(XTree* xt);
+
+/* Non frozen dup currently not needed :
+ extern XTree* VG_(XT_dup)(XTree* xt); */
+
+/* Free all memory associated with an XTRee. */
+extern void VG_(XT_delete)(XTree* xt);
+
+/* an Xecu identifies an exe context+its associated data in an XTree. */
+typedef UInt Xecu;
+
+/* If not yet in xt, inserts the provided ec and initialises its
+ data by calling init_data_fn.
+ If already present (or after insertion), updates the data by calling
+ add_data_fn. */
+extern Xecu VG_(XT_add_to_ec)(XTree* xt, ExeContext* ec, const void* value);
+
+/* If not yet in xt, inserts the provided ec and initialises its
+ data by calling init_data_fn.
+ If already present (or after insertion), updates the data by calling
+ sub_data_fn to substract value from the data associated to ec. */
+extern Xecu VG_(XT_sub_from_ec)(XTree* xt, ExeContext* ec, const void* value);
+
+/* Same as (but more efficient than) VG_(XT_add_to_ec) and VG_(XT_sub_from_ec)
+ for an ec already inserted in xt. */
+extern void VG_(XT_add_to_xecu)(XTree* xt, Xecu xecu, const void* value);
+extern void VG_(XT_sub_from_xecu)(XTree* xt, Xecu xecu, const void* value);
+
+/* Return the nr of IPs selected for xecu. 0 means fully filtered. */
+extern UInt VG_(XT_n_ips_sel)(XTree* xt, Xecu xecu);
+
+/* Return the ExeContext associated to the Xecu. */
+extern ExeContext* VG_(XT_get_ec_from_xecu) (XTree* xt, Xecu xecu);
+
+/* -------------------- CALLGRIND/KCACHEGRIND OUTPUT FORMAT --------------*/
+/* Prints xt in outfilename in callgrind/kcachegrind format.
+ events is a comma separated list of events, used by
+ kcachegrind/callgrind_annotate/... to name the value various components.
+ An event can optionally have a longer description, separated from the
+ event name by " : ", e.g.
+ "curB : currently allocated Bytes,curBk : Currently allocated Blocks"
+ img_value returns an image of the value. The image must be a space
+ separated set of integers, matching the corresponding event in events.
+ Note that the returned pointer can be static data.
+ img_value can return NULL if value (and its associated ExeContext) should
+ not be printed.
+*/
+extern void VG_(XT_callgrind_print)
+ (XTree* xt,
+ const HChar* outfilename,
+ const HChar* events,
+ const HChar* (*img_value) (const void* value));
+
+
+/* -------------------- MASSIF OUTPUT FORMAT --------------*/
+// Time is measured either in i or ms or bytes, depending on the --time-unit
+// option. It's a Long because it can exceed 32-bits reasonably easily, and
+// because we need to allow negative values to represent unset times.
+typedef Long Time;
+
+typedef void MsFile;
+
+/* Create a new file or truncate existing file for printing xtrees in
+ massif format. time_unit is a string describing the unit used
+ in Massif_Header time.
+ Produces a user error msg and returns NULL if file cannot be opened.
+ Caller must VG_(XT_massif_close) the returned file. */
+extern MsFile* VG_(XT_massif_open)(const HChar* outfilename,
+ const HChar* desc, // can be NULL
+ const XArray* desc_args, // can be NULL
+ const HChar* time_unit);
+
+extern void VG_(XT_massif_close)(MsFile* fp);
+
+typedef
+ struct {
+ int snapshot_n; // starting at 0.
+ Time time;
+
+ ULong sz_B; // sum of values, only used when printing a NULL xt.
+ ULong extra_B;
+ ULong stacks_B;
+
+ Bool detailed;
+ Bool peak;
+
+ /* top_node_desc: description for the top node.
+ Typically for memory usage, give xt_heap_alloc_functions_desc. */
+ const HChar* top_node_desc;
+
+ /* children with less than sig_threshold * total xt sz will be aggregated
+ and printed as one single child. */
+ double sig_threshold;
+
+ } Massif_Header;
+
+/* Prints xt in outfilename in massif format.
+ If a NULL xt is provided, then only the header information is used
+ to produce the (necessarily not detailed) snapshot.
+ report_value must return the value to be used for the report production.
+ It will typically be the nr of bytes allocated stored with the execontext
+ but it could be anything measured with a ULong (e.g. the nr of blocks
+ allocated, or a number of calls, ...).
+*/
+extern void VG_(XT_massif_print)
+ (MsFile* fp,
+ XTree* xt,
+ const Massif_Header* header,
+ ULong (*report_value)(const void* value));
+
+#endif // __PUB_TOOL_XTREE_H
+
+/*--------------------------------------------------------------------*/
+/*--- end pub_tool_xtree.h ---*/
+/*--------------------------------------------------------------------*/
diff --git a/include/valgrind.h b/include/valgrind.h
index 6892007..5aed0df 100644
--- a/include/valgrind.h
+++ b/include/valgrind.h
@@ -12,7 +12,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward. All rights reserved.
+ Copyright (C) 2000-2017 Julian Seward. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
@@ -89,7 +89,7 @@
|| (__VALGRIND_MAJOR__ == 3 && __VALGRIND_MINOR__ >= 6))
*/
#define __VALGRIND_MAJOR__ 3
-#define __VALGRIND_MINOR__ 12
+#define __VALGRIND_MINOR__ 13
#include <stdarg.h>
@@ -122,7 +122,6 @@
#undef PLAT_s390x_linux
#undef PLAT_mips32_linux
#undef PLAT_mips64_linux
-#undef PLAT_tilegx_linux
#undef PLAT_x86_solaris
#undef PLAT_amd64_solaris
@@ -160,8 +159,6 @@
# define PLAT_mips64_linux 1
#elif defined(__linux__) && defined(__mips__) && (__mips!=64)
# define PLAT_mips32_linux 1
-#elif defined(__linux__) && defined(__tilegx__)
-# define PLAT_tilegx_linux 1
#elif defined(__sun) && defined(__i386__)
# define PLAT_x86_solaris 1
#elif defined(__sun) && defined(__x86_64__)
@@ -1048,73 +1045,6 @@
#endif /* PLAT_mips64_linux */
-/* ------------------------ tilegx-linux --------------- */
-#if defined(PLAT_tilegx_linux)
-
-typedef
- struct {
- unsigned long long int nraddr; /* where's the code? */
- }
- OrigFn;
-/*** special instruction sequence.
- 0:02b3c7ff91234fff { moveli zero, 4660 ; moveli zero, 22136 }
- 8:0091a7ff95678fff { moveli zero, 22136 ; moveli zero, 4660 }
-****/
-
-#define __SPECIAL_INSTRUCTION_PREAMBLE \
- ".quad 0x02b3c7ff91234fff\n" \
- ".quad 0x0091a7ff95678fff\n"
-
-#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \
- _zzq_default, _zzq_request, \
- _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
- ({ volatile unsigned long long int _zzq_args[6]; \
- volatile unsigned long long int _zzq_result; \
- _zzq_args[0] = (unsigned long long int)(_zzq_request); \
- _zzq_args[1] = (unsigned long long int)(_zzq_arg1); \
- _zzq_args[2] = (unsigned long long int)(_zzq_arg2); \
- _zzq_args[3] = (unsigned long long int)(_zzq_arg3); \
- _zzq_args[4] = (unsigned long long int)(_zzq_arg4); \
- _zzq_args[5] = (unsigned long long int)(_zzq_arg5); \
- __asm__ volatile("move r11, %1\n\t" /*default*/ \
- "move r12, %2\n\t" /*ptr*/ \
- __SPECIAL_INSTRUCTION_PREAMBLE \
- /* r11 = client_request */ \
- "or r13, r13, r13\n\t" \
- "move %0, r11\n\t" /*result*/ \
- : "=r" (_zzq_result) \
- : "r" (_zzq_default), "r" (&_zzq_args[0]) \
- : "memory", "r11", "r12"); \
- _zzq_result; \
- })
-
-#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \
- { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \
- volatile unsigned long long int __addr; \
- __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
- /* r11 = guest_NRADDR */ \
- "or r14, r14, r14\n" \
- "move %0, r11\n" \
- : "=r" (__addr) \
- : \
- : "memory", "r11" \
- ); \
- _zzq_orig->nraddr = __addr; \
- }
-
-#define VALGRIND_CALL_NOREDIR_R12 \
- __SPECIAL_INSTRUCTION_PREAMBLE \
- "or r15, r15, r15\n\t"
-
-#define VALGRIND_VEX_INJECT_IR() \
- do { \
- __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
- "or r11, r11, r11\n\t" \
- ); \
- } while (0)
-
-#endif /* PLAT_tilegx_linux */
-
/* Insert assembly code for other platforms here... */
#endif /* NVALGRIND */
@@ -2708,7 +2638,7 @@
#define __CALLER_SAVED_REGS \
"lr", "ctr", "xer", \
"cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \
- "r0", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \
+ "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \
"r11", "r12", "r13"
/* Macros to save and align the stack before making a function
@@ -3264,7 +3194,7 @@
#define __CALLER_SAVED_REGS \
"lr", "ctr", "xer", \
"cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \
- "r0", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \
+ "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \
"r11", "r12", "r13"
/* Macros to save and align the stack before making a function
@@ -6165,461 +6095,6 @@
#endif /* PLAT_mips64_linux */
-/* ------------------------ tilegx-linux ------------------------- */
-
-#if defined(PLAT_tilegx_linux)
-
-/* These regs are trashed by the hidden call. */
-#define __CALLER_SAVED_REGS "r0", "r1", "r2", "r3", "r4", "r5", \
- "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", \
- "r15", "r16", "r17", "r18", "r19", "r20", "r21", "r22", \
- "r23", "r24", "r25", "r26", "r27", "r28", "r29", "lr"
-
-/* These CALL_FN_ macros assume that on tilegx-linux, sizeof(unsigned
- long) == 8. */
-
-#define CALL_FN_W_v(lval, orig) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[1]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- __asm__ volatile( \
- "addi sp, sp, -8 \n\t" \
- "st_add sp, lr, -8 \n\t" \
- "ld r12, %1 \n\t" /* target->r11 */ \
- VALGRIND_CALL_NOREDIR_R12 \
- "addi sp, sp, 8\n\t" \
- "ld_add lr, sp, 8 \n\t" \
- "move %0, r0 \n" \
- : /*out*/ "=r" (_res) \
- : /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "memory", __CALLER_SAVED_REGS); \
- \
- lval = (__typeof__(lval)) _res; \
- } while (0)
-
-#define CALL_FN_W_W(lval, orig, arg1) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[2]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- _argvec[1] = (unsigned long)(arg1); \
- __asm__ volatile( \
- "addi sp, sp, -8 \n\t" \
- "st_add sp, lr, -8 \n\t" \
- "move r29, %1 \n\t" \
- "ld_add r12, r29, 8 \n\t" /* target->r11 */ \
- "ld_add r0, r29, 8 \n\t" /*arg1 -> r0 */ \
- VALGRIND_CALL_NOREDIR_R12 \
- "addi sp, sp, 8\n\t" \
- "ld_add lr, sp, 8 \n\t" \
- "move %0, r0\n" \
- : /*out*/ "=r" (_res) \
- : /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "memory", __CALLER_SAVED_REGS); \
- lval = (__typeof__(lval)) _res; \
- } while (0)
-
-#define CALL_FN_W_WW(lval, orig, arg1,arg2) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[3]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- _argvec[1] = (unsigned long)(arg1); \
- _argvec[2] = (unsigned long)(arg2); \
- __asm__ volatile( \
- "addi sp, sp, -8 \n\t" \
- "st_add sp, lr, -8 \n\t" \
- "move r29, %1 \n\t" \
- "ld_add r12, r29, 8 \n\t" /* target->r11 */ \
- "ld_add r0, r29, 8 \n\t" /*arg1 -> r0 */ \
- "ld_add r1, r29, 8 \n\t" /*arg2 -> r1 */ \
- VALGRIND_CALL_NOREDIR_R12 \
- "addi sp, sp, 8\n\t" \
- "ld_add lr, sp, 8 \n\t" \
- "move %0, r0\n" \
- : /*out*/ "=r" (_res) \
- : /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "memory", __CALLER_SAVED_REGS); \
- lval = (__typeof__(lval)) _res; \
- } while (0)
-
-#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[4]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- _argvec[1] = (unsigned long)(arg1); \
- _argvec[2] = (unsigned long)(arg2); \
- _argvec[3] = (unsigned long)(arg3); \
- __asm__ volatile( \
- "addi sp, sp, -8 \n\t" \
- "st_add sp, lr, -8 \n\t" \
- "move r29, %1 \n\t" \
- "ld_add r12, r29, 8 \n\t" /* target->r11 */ \
- "ld_add r0, r29, 8 \n\t" /*arg1 -> r0 */ \
- "ld_add r1, r29, 8 \n\t" /*arg2 -> r1 */ \
- "ld_add r2, r29, 8 \n\t" /*arg3 -> r2 */ \
- VALGRIND_CALL_NOREDIR_R12 \
- "addi sp, sp, 8 \n\t" \
- "ld_add lr, sp, 8 \n\t" \
- "move %0, r0\n" \
- : /*out*/ "=r" (_res) \
- : /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "memory", __CALLER_SAVED_REGS); \
- lval = (__typeof__(lval)) _res; \
- } while (0)
-
-#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[5]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- _argvec[1] = (unsigned long)(arg1); \
- _argvec[2] = (unsigned long)(arg2); \
- _argvec[3] = (unsigned long)(arg3); \
- _argvec[4] = (unsigned long)(arg4); \
- __asm__ volatile( \
- "addi sp, sp, -8 \n\t" \
- "st_add sp, lr, -8 \n\t" \
- "move r29, %1 \n\t" \
- "ld_add r12, r29, 8 \n\t" /* target->r11 */ \
- "ld_add r0, r29, 8 \n\t" /*arg1 -> r0 */ \
- "ld_add r1, r29, 8 \n\t" /*arg2 -> r1 */ \
- "ld_add r2, r29, 8 \n\t" /*arg3 -> r2 */ \
- "ld_add r3, r29, 8 \n\t" /*arg4 -> r3 */ \
- VALGRIND_CALL_NOREDIR_R12 \
- "addi sp, sp, 8\n\t" \
- "ld_add lr, sp, 8 \n\t" \
- "move %0, r0\n" \
- : /*out*/ "=r" (_res) \
- : /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "memory", __CALLER_SAVED_REGS); \
- lval = (__typeof__(lval)) _res; \
- } while (0)
-
-#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[6]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- _argvec[1] = (unsigned long)(arg1); \
- _argvec[2] = (unsigned long)(arg2); \
- _argvec[3] = (unsigned long)(arg3); \
- _argvec[4] = (unsigned long)(arg4); \
- _argvec[5] = (unsigned long)(arg5); \
- __asm__ volatile( \
- "addi sp, sp, -8 \n\t" \
- "st_add sp, lr, -8 \n\t" \
- "move r29, %1 \n\t" \
- "ld_add r12, r29, 8 \n\t" /* target->r11 */ \
- "ld_add r0, r29, 8 \n\t" /*arg1 -> r0 */ \
- "ld_add r1, r29, 8 \n\t" /*arg2 -> r1 */ \
- "ld_add r2, r29, 8 \n\t" /*arg3 -> r2 */ \
- "ld_add r3, r29, 8 \n\t" /*arg4 -> r3 */ \
- "ld_add r4, r29, 8 \n\t" /*arg5 -> r4 */ \
- VALGRIND_CALL_NOREDIR_R12 \
- "addi sp, sp, 8\n\t" \
- "ld_add lr, sp, 8 \n\t" \
- "move %0, r0\n" \
- : /*out*/ "=r" (_res) \
- : /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "memory", __CALLER_SAVED_REGS); \
- lval = (__typeof__(lval)) _res; \
- } while (0)
-#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[7]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- _argvec[1] = (unsigned long)(arg1); \
- _argvec[2] = (unsigned long)(arg2); \
- _argvec[3] = (unsigned long)(arg3); \
- _argvec[4] = (unsigned long)(arg4); \
- _argvec[5] = (unsigned long)(arg5); \
- _argvec[6] = (unsigned long)(arg6); \
- __asm__ volatile( \
- "addi sp, sp, -8 \n\t" \
- "st_add sp, lr, -8 \n\t" \
- "move r29, %1 \n\t" \
- "ld_add r12, r29, 8 \n\t" /* target->r11 */ \
- "ld_add r0, r29, 8 \n\t" /*arg1 -> r0 */ \
- "ld_add r1, r29, 8 \n\t" /*arg2 -> r1 */ \
- "ld_add r2, r29, 8 \n\t" /*arg3 -> r2 */ \
- "ld_add r3, r29, 8 \n\t" /*arg4 -> r3 */ \
- "ld_add r4, r29, 8 \n\t" /*arg5 -> r4 */ \
- "ld_add r5, r29, 8 \n\t" /*arg6 -> r5 */ \
- VALGRIND_CALL_NOREDIR_R12 \
- "addi sp, sp, 8\n\t" \
- "ld_add lr, sp, 8 \n\t" \
- "move %0, r0\n" \
- : /*out*/ "=r" (_res) \
- : /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "memory", __CALLER_SAVED_REGS); \
- lval = (__typeof__(lval)) _res; \
- } while (0)
-
-#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
- arg7) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[8]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- _argvec[1] = (unsigned long)(arg1); \
- _argvec[2] = (unsigned long)(arg2); \
- _argvec[3] = (unsigned long)(arg3); \
- _argvec[4] = (unsigned long)(arg4); \
- _argvec[5] = (unsigned long)(arg5); \
- _argvec[6] = (unsigned long)(arg6); \
- _argvec[7] = (unsigned long)(arg7); \
- __asm__ volatile( \
- "addi sp, sp, -8 \n\t" \
- "st_add sp, lr, -8 \n\t" \
- "move r29, %1 \n\t" \
- "ld_add r12, r29, 8 \n\t" /* target->r11 */ \
- "ld_add r0, r29, 8 \n\t" /*arg1 -> r0 */ \
- "ld_add r1, r29, 8 \n\t" /*arg2 -> r1 */ \
- "ld_add r2, r29, 8 \n\t" /*arg3 -> r2 */ \
- "ld_add r3, r29, 8 \n\t" /*arg4 -> r3 */ \
- "ld_add r4, r29, 8 \n\t" /*arg5 -> r4 */ \
- "ld_add r5, r29, 8 \n\t" /*arg6 -> r5 */ \
- "ld_add r6, r29, 8 \n\t" /*arg7 -> r6 */ \
- VALGRIND_CALL_NOREDIR_R12 \
- "addi sp, sp, 8\n\t" \
- "ld_add lr, sp, 8 \n\t" \
- "move %0, r0\n" \
- : /*out*/ "=r" (_res) \
- : /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "memory", __CALLER_SAVED_REGS); \
- lval = (__typeof__(lval)) _res; \
- } while (0)
-
-#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
- arg7,arg8) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[9]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- _argvec[1] = (unsigned long)(arg1); \
- _argvec[2] = (unsigned long)(arg2); \
- _argvec[3] = (unsigned long)(arg3); \
- _argvec[4] = (unsigned long)(arg4); \
- _argvec[5] = (unsigned long)(arg5); \
- _argvec[6] = (unsigned long)(arg6); \
- _argvec[7] = (unsigned long)(arg7); \
- _argvec[8] = (unsigned long)(arg8); \
- __asm__ volatile( \
- "addi sp, sp, -8 \n\t" \
- "st_add sp, lr, -8 \n\t" \
- "move r29, %1 \n\t" \
- "ld_add r12, r29, 8 \n\t" /* target->r11 */ \
- "ld_add r0, r29, 8 \n\t" /*arg1 -> r0 */ \
- "ld_add r1, r29, 8 \n\t" /*arg2 -> r1 */ \
- "ld_add r2, r29, 8 \n\t" /*arg3 -> r2 */ \
- "ld_add r3, r29, 8 \n\t" /*arg4 -> r3 */ \
- "ld_add r4, r29, 8 \n\t" /*arg5 -> r4 */ \
- "ld_add r5, r29, 8 \n\t" /*arg6 -> r5 */ \
- "ld_add r6, r29, 8 \n\t" /*arg7 -> r6 */ \
- "ld_add r7, r29, 8 \n\t" /*arg8 -> r7 */ \
- VALGRIND_CALL_NOREDIR_R12 \
- "addi sp, sp, 8\n\t" \
- "ld_add lr, sp, 8 \n\t" \
- "move %0, r0\n" \
- : /*out*/ "=r" (_res) \
- : /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "memory", __CALLER_SAVED_REGS); \
- lval = (__typeof__(lval)) _res; \
- } while (0)
-
-#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
- arg7,arg8,arg9) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[10]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- _argvec[1] = (unsigned long)(arg1); \
- _argvec[2] = (unsigned long)(arg2); \
- _argvec[3] = (unsigned long)(arg3); \
- _argvec[4] = (unsigned long)(arg4); \
- _argvec[5] = (unsigned long)(arg5); \
- _argvec[6] = (unsigned long)(arg6); \
- _argvec[7] = (unsigned long)(arg7); \
- _argvec[8] = (unsigned long)(arg8); \
- _argvec[9] = (unsigned long)(arg9); \
- __asm__ volatile( \
- "addi sp, sp, -8 \n\t" \
- "st_add sp, lr, -8 \n\t" \
- "move r29, %1 \n\t" \
- "ld_add r12, r29, 8 \n\t" /* target->r11 */ \
- "ld_add r0, r29, 8 \n\t" /*arg1 -> r0 */ \
- "ld_add r1, r29, 8 \n\t" /*arg2 -> r1 */ \
- "ld_add r2, r29, 8 \n\t" /*arg3 -> r2 */ \
- "ld_add r3, r29, 8 \n\t" /*arg4 -> r3 */ \
- "ld_add r4, r29, 8 \n\t" /*arg5 -> r4 */ \
- "ld_add r5, r29, 8 \n\t" /*arg6 -> r5 */ \
- "ld_add r6, r29, 8 \n\t" /*arg7 -> r6 */ \
- "ld_add r7, r29, 8 \n\t" /*arg8 -> r7 */ \
- "ld_add r8, r29, 8 \n\t" /*arg9 -> r8 */ \
- VALGRIND_CALL_NOREDIR_R12 \
- "addi sp, sp, 8\n\t" \
- "ld_add lr, sp, 8 \n\t" \
- "move %0, r0\n" \
- : /*out*/ "=r" (_res) \
- : /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "memory", __CALLER_SAVED_REGS); \
- lval = (__typeof__(lval)) _res; \
- } while (0)
-
-#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
- arg7,arg8,arg9,arg10) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[11]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- _argvec[1] = (unsigned long)(arg1); \
- _argvec[2] = (unsigned long)(arg2); \
- _argvec[3] = (unsigned long)(arg3); \
- _argvec[4] = (unsigned long)(arg4); \
- _argvec[5] = (unsigned long)(arg5); \
- _argvec[6] = (unsigned long)(arg6); \
- _argvec[7] = (unsigned long)(arg7); \
- _argvec[8] = (unsigned long)(arg8); \
- _argvec[9] = (unsigned long)(arg9); \
- _argvec[10] = (unsigned long)(arg10); \
- __asm__ volatile( \
- "addi sp, sp, -8 \n\t" \
- "st_add sp, lr, -8 \n\t" \
- "move r29, %1 \n\t" \
- "ld_add r12, r29, 8 \n\t" /* target->r11 */ \
- "ld_add r0, r29, 8 \n\t" /*arg1 -> r0 */ \
- "ld_add r1, r29, 8 \n\t" /*arg2 -> r1 */ \
- "ld_add r2, r29, 8 \n\t" /*arg3 -> r2 */ \
- "ld_add r3, r29, 8 \n\t" /*arg4 -> r3 */ \
- "ld_add r4, r29, 8 \n\t" /*arg5 -> r4 */ \
- "ld_add r5, r29, 8 \n\t" /*arg6 -> r5 */ \
- "ld_add r6, r29, 8 \n\t" /*arg7 -> r6 */ \
- "ld_add r7, r29, 8 \n\t" /*arg8 -> r7 */ \
- "ld_add r8, r29, 8 \n\t" /*arg9 -> r8 */ \
- "ld_add r9, r29, 8 \n\t" /*arg10 -> r9 */ \
- VALGRIND_CALL_NOREDIR_R12 \
- "addi sp, sp, 8\n\t" \
- "ld_add lr, sp, 8 \n\t" \
- "move %0, r0\n" \
- : /*out*/ "=r" (_res) \
- : /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "memory", __CALLER_SAVED_REGS); \
- lval = (__typeof__(lval)) _res; \
- } while (0)
-
-#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5, \
- arg6,arg7,arg8,arg9,arg10, \
- arg11) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[12]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- _argvec[1] = (unsigned long)(arg1); \
- _argvec[2] = (unsigned long)(arg2); \
- _argvec[3] = (unsigned long)(arg3); \
- _argvec[4] = (unsigned long)(arg4); \
- _argvec[5] = (unsigned long)(arg5); \
- _argvec[6] = (unsigned long)(arg6); \
- _argvec[7] = (unsigned long)(arg7); \
- _argvec[8] = (unsigned long)(arg8); \
- _argvec[9] = (unsigned long)(arg9); \
- _argvec[10] = (unsigned long)(arg10); \
- _argvec[11] = (unsigned long)(arg11); \
- __asm__ volatile( \
- "addi sp, sp, -8 \n\t" \
- "st_add sp, lr, -8 \n\t" \
- "move r29, %1 \n\t" \
- "ld_add r12, r29, 8 \n\t" /* target->r11 */ \
- "ld_add r0, r29, 8 \n\t" /*arg1 -> r0 */ \
- "ld_add r1, r29, 8 \n\t" /*arg2 -> r1 */ \
- "ld_add r2, r29, 8 \n\t" /*arg3 -> r2 */ \
- "ld_add r3, r29, 8 \n\t" /*arg4 -> r3 */ \
- "ld_add r4, r29, 8 \n\t" /*arg5 -> r4 */ \
- "ld_add r5, r29, 8 \n\t" /*arg6 -> r5 */ \
- "ld_add r6, r29, 8 \n\t" /*arg7 -> r6 */ \
- "ld_add r7, r29, 8 \n\t" /*arg8 -> r7 */ \
- "ld_add r8, r29, 8 \n\t" /*arg9 -> r8 */ \
- "ld_add r9, r29, 8 \n\t" /*arg10 -> r9 */ \
- "ld r10, r29 \n\t" \
- "st_add sp, r10, -16 \n\t" \
- VALGRIND_CALL_NOREDIR_R12 \
- "addi sp, sp, 24 \n\t" \
- "ld_add lr, sp, 8 \n\t" \
- "move %0, r0\n" \
- : /*out*/ "=r" (_res) \
- : /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "memory", __CALLER_SAVED_REGS); \
- lval = (__typeof__(lval)) _res; \
- } while (0)
-
-#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5, \
- arg6,arg7,arg8,arg9,arg10, \
- arg11,arg12) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[13]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- _argvec[1] = (unsigned long)(arg1); \
- _argvec[2] = (unsigned long)(arg2); \
- _argvec[3] = (unsigned long)(arg3); \
- _argvec[4] = (unsigned long)(arg4); \
- _argvec[5] = (unsigned long)(arg5); \
- _argvec[6] = (unsigned long)(arg6); \
- _argvec[7] = (unsigned long)(arg7); \
- _argvec[8] = (unsigned long)(arg8); \
- _argvec[9] = (unsigned long)(arg9); \
- _argvec[10] = (unsigned long)(arg10); \
- _argvec[11] = (unsigned long)(arg11); \
- _argvec[12] = (unsigned long)(arg12); \
- __asm__ volatile( \
- "addi sp, sp, -8 \n\t" \
- "st_add sp, lr, -8 \n\t" \
- "move r29, %1 \n\t" \
- "ld_add r12, r29, 8 \n\t" /* target->r11 */ \
- "ld_add r0, r29, 8 \n\t" /*arg1 -> r0 */ \
- "ld_add r1, r29, 8 \n\t" /*arg2 -> r1 */ \
- "ld_add r2, r29, 8 \n\t" /*arg3 -> r2 */ \
- "ld_add r3, r29, 8 \n\t" /*arg4 -> r3 */ \
- "ld_add r4, r29, 8 \n\t" /*arg5 -> r4 */ \
- "ld_add r5, r29, 8 \n\t" /*arg6 -> r5 */ \
- "ld_add r6, r29, 8 \n\t" /*arg7 -> r6 */ \
- "ld_add r7, r29, 8 \n\t" /*arg8 -> r7 */ \
- "ld_add r8, r29, 8 \n\t" /*arg9 -> r8 */ \
- "ld_add r9, r29, 8 \n\t" /*arg10 -> r9 */ \
- "addi r28, sp, -8 \n\t" \
- "addi sp, sp, -24 \n\t" \
- "ld_add r10, r29, 8 \n\t" \
- "ld r11, r29 \n\t" \
- "st_add r28, r10, 8 \n\t" \
- "st r28, r11 \n\t" \
- VALGRIND_CALL_NOREDIR_R12 \
- "addi sp, sp, 32 \n\t" \
- "ld_add lr, sp, 8 \n\t" \
- "move %0, r0\n" \
- : /*out*/ "=r" (_res) \
- : /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "memory", __CALLER_SAVED_REGS); \
- lval = (__typeof__(lval)) _res; \
- } while (0)
-#endif /* PLAT_tilegx_linux */
-
/* ------------------------------------------------------------------ */
/* ARCHITECTURE INDEPENDENT MACROS for CLIENT REQUESTS. */
/* */
@@ -6642,8 +6117,9 @@
/* !! ABIWARNING !! ABIWARNING !! ABIWARNING !! ABIWARNING !!
This enum comprises an ABI exported by Valgrind to programs
- which use client requests. DO NOT CHANGE THE ORDER OF THESE
- ENTRIES, NOR DELETE ANY -- add new ones at the end. */
+ which use client requests. DO NOT CHANGE THE NUMERIC VALUES OF THESE
+ ENTRIES, NOR DELETE ANY -- add new ones at the end of the most
+ relevant group. */
typedef
enum { VG_USERREQ__RUNNING_ON_VALGRIND = 0x1001,
VG_USERREQ__DISCARD_TRANSLATIONS = 0x1002,
@@ -6713,8 +6189,13 @@
Other values are not allowed. */
VG_USERREQ__CHANGE_ERR_DISABLEMENT = 0x1801,
+ /* Some requests used for Valgrind internal, such as
+ self-test or self-hosting. */
/* Initialise IR injection */
- VG_USERREQ__VEX_INIT_FOR_IRI = 0x1901
+ VG_USERREQ__VEX_INIT_FOR_IRI = 0x1901,
+ /* Used by Inner Valgrind to inform Outer Valgrind where to
+ find the list of inner guest threads */
+ VG_USERREQ__INNER_THREADS = 0x1902
} Vg_ClientRequest;
#if !defined(__GNUC__)
@@ -6740,6 +6221,10 @@
VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DISCARD_TRANSLATIONS, \
_qzz_addr, _qzz_len, 0, 0, 0)
+#define VALGRIND_INNER_THREADS(_qzz_addr) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__INNER_THREADS, \
+ _qzz_addr, 0, 0, 0, 0)
+
/* These requests are for getting Valgrind itself to print something.
Possibly with a backtrace. This is a really ugly hack. The return value
@@ -6759,7 +6244,7 @@
VALGRIND_PRINTF(const char *format, ...)
{
#if defined(NVALGRIND)
- if (format) *(volatile const char *)format; /* avoid compiler warning */
+ (void)format;
return 0;
#else /* NVALGRIND */
#if defined(_MSC_VER) || defined(__MINGW64__)
@@ -6798,7 +6283,7 @@
VALGRIND_PRINTF_BACKTRACE(const char *format, ...)
{
#if defined(NVALGRIND)
- if (format) *(volatile const char *)format; /* avoid compiler warning */
+ (void)format;
return 0;
#else /* NVALGRIND */
#if defined(_MSC_VER) || defined(__MINGW64__)
@@ -6828,7 +6313,7 @@
/* These requests allow control to move from the simulated CPU to the
- real CPU, calling an arbitary function.
+ real CPU, calling an arbitrary function.
Note that the current ThreadId is inserted as the first argument.
So this call:
@@ -7153,7 +6638,6 @@
#undef PLAT_s390x_linux
#undef PLAT_mips32_linux
#undef PLAT_mips64_linux
-#undef PLAT_tilegx_linux
#undef PLAT_x86_solaris
#undef PLAT_amd64_solaris
diff --git a/include/vgversion.h b/include/vgversion.h
new file mode 100644
index 0000000..6d9e22c
--- /dev/null
+++ b/include/vgversion.h
@@ -0,0 +1,6 @@
+/* Do not edit: file generated by auxprogs/make_or_upd_vgversion_h.
+ This file defines VGSVN and VEXSVN, used to report SVN revision
+ when using command line options: -v --version
+*/
+#define VGSVN "16445:16446"
+#define VEXSVN "3396"
diff --git a/include/vgversion_dist.h b/include/vgversion_dist.h
new file mode 100644
index 0000000..6d9e22c
--- /dev/null
+++ b/include/vgversion_dist.h
@@ -0,0 +1,6 @@
+/* Do not edit: file generated by auxprogs/make_or_upd_vgversion_h.
+ This file defines VGSVN and VEXSVN, used to report SVN revision
+ when using command line options: -v --version
+*/
+#define VGSVN "16445:16446"
+#define VEXSVN "3396"
diff --git a/include/vki/vki-amd64-linux.h b/include/vki/vki-amd64-linux.h
index db85b92..a506ade 100644
--- a/include/vki/vki-amd64-linux.h
+++ b/include/vki/vki-amd64-linux.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/vki/vki-arm-linux.h b/include/vki/vki-arm-linux.h
index fe7a171..46577e9 100644
--- a/include/vki/vki-arm-linux.h
+++ b/include/vki/vki-arm-linux.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/vki/vki-arm64-linux.h b/include/vki/vki-arm64-linux.h
index df34dd6..af6b435 100644
--- a/include/vki/vki-arm64-linux.h
+++ b/include/vki/vki-arm64-linux.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2013-2015 OpenWorks
+ Copyright (C) 2013-2017 OpenWorks
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -586,7 +586,8 @@
//ZZ };
//ZZ
//ZZ // [[Nb: for our convenience within Valgrind, use a more specific name]]
-//ZZ typedef struct vki_user_desc vki_modify_ldt_t;
+
+typedef char vki_modify_ldt_t;
//----------------------------------------------------------------------
// From linux-3.10.5/include/asm-generic/ipcbuf.h
diff --git a/include/vki/vki-darwin.h b/include/vki/vki-darwin.h
index 49d0d4c..72b66bf 100644
--- a/include/vki/vki-darwin.h
+++ b/include/vki/vki-darwin.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2007-2015 Apple Inc.
+ Copyright (C) 2007-2017 Apple Inc.
Greg Parker gparker@apple.com
This program is free software; you can redistribute it and/or
diff --git a/include/vki/vki-linux.h b/include/vki/vki-linux.h
index bdb8f33..4840a53 100644
--- a/include/vki/vki-linux.h
+++ b/include/vki/vki-linux.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -97,8 +97,6 @@
# include "vki-posixtypes-mips32-linux.h"
#elif defined(VGA_mips64)
# include "vki-posixtypes-mips64-linux.h"
-#elif defined(VGA_tilegx)
-# include "vki-posixtypes-tilegx-linux.h"
#else
# error Unknown platform
#endif
@@ -225,8 +223,6 @@
# include "vki-mips32-linux.h"
#elif defined(VGA_mips64)
# include "vki-mips64-linux.h"
-#elif defined(VGA_tilegx)
-# include "vki-tilegx-linux.h"
#else
# error Unknown platform
#endif
@@ -527,7 +523,7 @@
* SIGBUS si_codes
*/
#define VKI_BUS_ADRALN (__VKI_SI_FAULT|1) /* invalid address alignment */
-#define VKI_BUS_ADRERR (__VKI_SI_FAULT|2) /* non-existant physical address */
+#define VKI_BUS_ADRERR (__VKI_SI_FAULT|2) /* non-existent physical address */
#define VKI_BUS_OBJERR (__VKI_SI_FAULT|3) /* object specific hardware error */
/*
@@ -674,7 +670,8 @@
{
struct vki_cmsghdr * __ptr;
- __ptr = (struct vki_cmsghdr*)(((unsigned char *) __cmsg) + VKI_CMSG_ALIGN(__cmsg->cmsg_len));
+ __ptr = ASSUME_ALIGNED(struct vki_cmsghdr *,
+ ((unsigned char *) __cmsg) + VKI_CMSG_ALIGN(__cmsg->cmsg_len));
if ((unsigned long)((char*)(__ptr+1) - (char *) __ctl) > __size)
return (struct vki_cmsghdr *)0;
@@ -1415,6 +1412,22 @@
#define VKI_F_SETPIPE_SZ (VKI_F_LINUX_SPECIFIC_BASE + 7)
#define VKI_F_GETPIPE_SZ (VKI_F_LINUX_SPECIFIC_BASE + 8)
+struct vki_flock {
+ short l_type;
+ short l_whence;
+ __vki_kernel_off_t l_start;
+ __vki_kernel_off_t l_len;
+ __vki_kernel_pid_t l_pid;
+};
+
+struct vki_flock64 {
+ short l_type;
+ short l_whence;
+ __vki_kernel_loff_t l_start;
+ __vki_kernel_loff_t l_len;
+ __vki_kernel_pid_t l_pid;
+};
+
//----------------------------------------------------------------------
// From linux-2.6.8.1/include/linux/sysctl.h
//----------------------------------------------------------------------
@@ -1865,10 +1878,13 @@
(struct cdrom_tochdr) */
#define VKI_CDROMREADTOCENTRY 0x5306 /* Read TOC entry
(struct cdrom_tocentry) */
+#define VKI_CDROMSTOP 0x5307 /* Stop the cdrom drive */
#define VKI_CDROMSUBCHNL 0x530b /* Read subchannel data
(struct cdrom_subchnl) */
#define VKI_CDROMREADMODE2 0x530c /* Read CDROM mode 2 data (2336 Bytes)
(struct cdrom_read) */
+#define VKI_CDROMREADMODE1 0x530d /* Read CDROM mode 1 data (2048 Bytes)
+ (struct cdrom_read) */
#define VKI_CDROMREADAUDIO 0x530e /* (struct cdrom_read_audio) */
#define VKI_CDROMMULTISESSION 0x5310 /* Obtain the start-of-last-session
address of multi session disks
@@ -1884,6 +1900,7 @@
#define VKI_CDROM_DISC_STATUS 0x5327 /* get CD type information */
#define VKI_CDROM_GET_CAPABILITY 0x5331 /* get capabilities */
+#define VKI_DVD_READ_STRUCT 0x5390 /* read structure */
#define VKI_CDROM_SEND_PACKET 0x5393 /* send a packet to the drive */
struct vki_cdrom_msf0
@@ -1994,6 +2011,7 @@
#define VKI_CD_HEAD_SIZE 4 /* header (address) bytes per raw data frame */
#define VKI_CD_FRAMESIZE_RAW 2352 /* bytes per frame, "raw" mode */
#define VKI_CD_FRAMESIZE_RAW0 (VKI_CD_FRAMESIZE_RAW-VKI_CD_SYNC_SIZE-VKI_CD_HEAD_SIZE) /*2336*/
+#define VKI_CD_FRAMESIZE_RAW1 2048 /* bytes per frame, mode 1*/
//----------------------------------------------------------------------
// From linux-2.6.8.1/include/linux/soundcard.h
@@ -2321,6 +2339,8 @@
#define VKI_PTRACE_GETREGSET 0x4204
#define VKI_PTRACE_SETREGSET 0x4205
+#define VKI_PT_PTRACED 0x00000001
+
//----------------------------------------------------------------------
// From linux-2.6.14/include/sound/asound.h
//----------------------------------------------------------------------
@@ -2773,7 +2793,7 @@
#define VKI_SIOCSIWPOWER 0x8B2C /* set Power Management settings */
#define VKI_SIOCGIWPOWER 0x8B2D /* get Power Management settings */
-/* WPA : Generic IEEE 802.11 informatiom element (e.g., for WPA/RSN/WMM). */
+/* WPA : Generic IEEE 802.11 information element (e.g., for WPA/RSN/WMM). */
#define VKI_SIOCSIWGENIE 0x8B30 /* set generic IE */
#define VKI_SIOCGIWGENIE 0x8B31 /* get generic IE */
@@ -2800,7 +2820,7 @@
__vki_s32 value; /* The value of the parameter itself */
__vki_u8 fixed; /* Hardware should not use auto select */
__vki_u8 disabled; /* Disable the feature */
- __vki_u16 flags; /* Various specifc flags (if any) */
+ __vki_u16 flags; /* Various specific flags (if any) */
};
struct vki_iw_point
diff --git a/include/vki/vki-mips32-linux.h b/include/vki/vki-mips32-linux.h
index 5be8e15..7aba355 100644
--- a/include/vki/vki-mips32-linux.h
+++ b/include/vki/vki-mips32-linux.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 RT-RK
+ Copyright (C) 2010-2017 RT-RK
mips-valgrind@rt-rk.com
This program is free software; you can redistribute it and/or
@@ -679,7 +679,7 @@
};
// CAB: TODO
-typedef void vki_modify_ldt_t;
+typedef char vki_modify_ldt_t;
//----------------------------------------------------------------------
// From linux-2.6.35.5/include/asm-mips/ipcbuf.h
diff --git a/include/vki/vki-mips64-linux.h b/include/vki/vki-mips64-linux.h
index 26b8e9f..c20c298 100644
--- a/include/vki/vki-mips64-linux.h
+++ b/include/vki/vki-mips64-linux.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 RT-RK
+ Copyright (C) 2010-2017 RT-RK
mips-valgrind@rt-rk.com
This program is free software; you can redistribute it and/or
@@ -710,6 +710,7 @@
vki_sigset_t uc_sigmask; /* mask last for extensibility */
};
+typedef char vki_modify_ldt_t;
//----------------------------------------------------------------------
// From linux-2.6.35.9/include/asm-mips/ipcbuf.h
//----------------------------------------------------------------------
diff --git a/include/vki/vki-posixtypes-amd64-linux.h b/include/vki/vki-posixtypes-amd64-linux.h
index e68e214..342e416 100644
--- a/include/vki/vki-posixtypes-amd64-linux.h
+++ b/include/vki/vki-posixtypes-amd64-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/vki/vki-posixtypes-arm-linux.h b/include/vki/vki-posixtypes-arm-linux.h
index 59943a8..bc06ec9 100644
--- a/include/vki/vki-posixtypes-arm-linux.h
+++ b/include/vki/vki-posixtypes-arm-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/vki/vki-posixtypes-arm64-linux.h b/include/vki/vki-posixtypes-arm64-linux.h
index 7df5345..d9acee0 100644
--- a/include/vki/vki-posixtypes-arm64-linux.h
+++ b/include/vki/vki-posixtypes-arm64-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2013-2015 OpenWorks
+ Copyright (C) 2013-2017 OpenWorks
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/include/vki/vki-posixtypes-mips32-linux.h b/include/vki/vki-posixtypes-mips32-linux.h
index 4abe38a..b65e3ed 100644
--- a/include/vki/vki-posixtypes-mips32-linux.h
+++ b/include/vki/vki-posixtypes-mips32-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 RT-RK
+ Copyright (C) 2010-2017 RT-RK
mips-valgrind@rt-rk.com
This program is free software; you can redistribute it and/or
diff --git a/include/vki/vki-posixtypes-mips64-linux.h b/include/vki/vki-posixtypes-mips64-linux.h
index 4ebd597..96d2728 100644
--- a/include/vki/vki-posixtypes-mips64-linux.h
+++ b/include/vki/vki-posixtypes-mips64-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 RT-RK
+ Copyright (C) 2010-2017 RT-RK
mips-valgrind@rt-rk.com
This program is free software; you can redistribute it and/or
diff --git a/include/vki/vki-posixtypes-ppc32-linux.h b/include/vki/vki-posixtypes-ppc32-linux.h
index 246195b..e72a8f6 100644
--- a/include/vki/vki-posixtypes-ppc32-linux.h
+++ b/include/vki/vki-posixtypes-ppc32-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Julian Seward
+ Copyright (C) 2005-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/vki/vki-posixtypes-ppc64-linux.h b/include/vki/vki-posixtypes-ppc64-linux.h
index afd0a50..ac385ea 100644
--- a/include/vki/vki-posixtypes-ppc64-linux.h
+++ b/include/vki/vki-posixtypes-ppc64-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Julian Seward
+ Copyright (C) 2005-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/vki/vki-posixtypes-s390x-linux.h b/include/vki/vki-posixtypes-s390x-linux.h
index 6de95fc..8e04c3d 100644
--- a/include/vki/vki-posixtypes-s390x-linux.h
+++ b/include/vki/vki-posixtypes-s390x-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2015
+ Copyright IBM Corp. 2010-2017
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/include/vki/vki-posixtypes-x86-linux.h b/include/vki/vki-posixtypes-x86-linux.h
index dedaa67..7f131d7 100644
--- a/include/vki/vki-posixtypes-x86-linux.h
+++ b/include/vki/vki-posixtypes-x86-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/vki/vki-ppc32-linux.h b/include/vki/vki-ppc32-linux.h
index 70c2835..0582e43 100644
--- a/include/vki/vki-ppc32-linux.h
+++ b/include/vki/vki-ppc32-linux.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Julian Seward
+ Copyright (C) 2005-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -811,10 +811,9 @@
//.. };
//..
//.. // [[Nb: for our convenience within Valgrind, use a more specific name]]
-//.. typedef struct vki_user_desc vki_modify_ldt_t;
// CAB: TODO
-typedef void vki_modify_ldt_t;
+typedef char vki_modify_ldt_t;
//----------------------------------------------------------------------
diff --git a/include/vki/vki-ppc64-linux.h b/include/vki/vki-ppc64-linux.h
index b410663..b82dc37 100644
--- a/include/vki/vki-ppc64-linux.h
+++ b/include/vki/vki-ppc64-linux.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Julian Seward
+ Copyright (C) 2005-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -685,6 +685,9 @@
struct vki_sigcontext uc_mcontext; /* last for extensibility */
};
+// CAB: TODO
+typedef char vki_modify_ldt_t;
+
//----------------------------------------------------------------------
// From linux-2.6.13/include/asm-ppc64/ipcbuf.h
//----------------------------------------------------------------------
diff --git a/include/vki/vki-s390x-linux.h b/include/vki/vki-s390x-linux.h
index c3f6d00..8fdeadd 100644
--- a/include/vki/vki-s390x-linux.h
+++ b/include/vki/vki-s390x-linux.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2015
+ Copyright IBM Corp. 2010-2017
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -822,6 +822,8 @@
vki_sigset_t uc_sigmask; /* mask last for extensibility */
};
+typedef char vki_modify_ldt_t;
+
//----------------------------------------------------------------------
// From linux-2.6.16.60/include/asm-s390/ipcbuf.h
//----------------------------------------------------------------------
diff --git a/include/vki/vki-scnums-amd64-linux.h b/include/vki/vki-scnums-amd64-linux.h
index 820cd02..adeee00 100644
--- a/include/vki/vki-scnums-amd64-linux.h
+++ b/include/vki/vki-scnums-amd64-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/vki/vki-scnums-arm-linux.h b/include/vki/vki-scnums-arm-linux.h
index df35729..4430e69 100644
--- a/include/vki/vki-scnums-arm-linux.h
+++ b/include/vki/vki-scnums-arm-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2015 Evan Geller
+ Copyright (C) 2008-2017 Evan Geller
gaze@bea.ms
This program is free software; you can redistribute it and/or
diff --git a/include/vki/vki-scnums-arm64-linux.h b/include/vki/vki-scnums-arm64-linux.h
index e963c45..d53e7d7 100644
--- a/include/vki/vki-scnums-arm64-linux.h
+++ b/include/vki/vki-scnums-arm64-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2013-2015 OpenWorks
+ Copyright (C) 2013-2017 OpenWorks
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/include/vki/vki-scnums-darwin.h b/include/vki/vki-scnums-darwin.h
index b775849..04b42c8 100644
--- a/include/vki/vki-scnums-darwin.h
+++ b/include/vki/vki-scnums-darwin.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2007-2015 Apple Inc.
+ Copyright (C) 2007-2017 Apple Inc.
Greg Parker gparker@apple.com
This program is free software; you can redistribute it and/or
@@ -202,6 +202,10 @@
#define __NR_syscall_thread_switch VG_DARWIN_SYSCALL_CONSTRUCT_MACH(61)
#define __NR_clock_sleep_trap VG_DARWIN_SYSCALL_CONSTRUCT_MACH(62)
+#if DARWIN_VERS >= DARWIN_10_12
+#define __NR_host_create_mach_voucher_trap VG_DARWIN_SYSCALL_CONSTRUCT_MACH(70)
+#endif
+
#define __NR_mach_timebase_info VG_DARWIN_SYSCALL_CONSTRUCT_MACH(89)
#define __NR_mach_wait_until VG_DARWIN_SYSCALL_CONSTRUCT_MACH(90)
#define __NR_mk_timer_create VG_DARWIN_SYSCALL_CONSTRUCT_MACH(91)
@@ -391,8 +395,13 @@
/* 174 old getdents */
/* 175 old gc_control */
#define __NR_add_profil VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(176)
- /* 177 */
- /* 178 */
+
+#if DARWIN_VERS >= DARWIN_10_12
+#define __NR_kdebug_typefilter VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(177)
+#endif /* DARWIN_VERS >= DARWIN_10_12 */
+#if DARWIN_VERS >= DARWIN_10_11
+#define __NR_kdebug_trace_string VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(178)
+#endif /* DARWIN_VERS >= DARWIN_10_11 */
/* 179 */
#define __NR_kdebug_trace VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(180)
#define __NR_setgid VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(181)
@@ -642,7 +651,9 @@
/* 372 */
#endif
/* 373 */
- /* 374 */
+#if DARWIN_VERS >= DARWIN_10_11
+#define __NR_kevent_qos VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(374)
+#endif /* DARWIN_VERS >= DARWIN_10_11 */
/* 375 */
/* 376 */
/* 377 */
@@ -706,9 +717,9 @@
#define __NR_audit_session_port VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(432)
#define __NR_pid_suspend VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(433)
#define __NR_pid_resume VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(434)
-
-
-
+ /* 435 */
+ /* 436 */
+ /* 437 */
#define __NR_shared_region_map_and_slide_np VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(438)
#define __NR_kas_info VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(439)
#define __NR_memorystatus_control VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(440)
@@ -716,7 +727,7 @@
#define __NR_guarded_close_np VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(442)
#define __NR_guarded_kqueue_np VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(443)
#define __NR_change_fdguard_np VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(444)
-
+ /* 445 */
#define __NR_proc_rlimit_control VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(446)
#define __NR_connectx VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(447)
#define __NR_disconnectx VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(448)
@@ -732,35 +743,46 @@
#if DARWIN_VERS >= DARWIN_10_10
#define __NR_necp_match_policy VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(460)
#define __NR_getattrlistbulk VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(461)
+#endif /* DARWIN_VERS >= DARWIN_10_10 */
+
+#if DARWIN_VERS >= DARWIN_10_12
+#define __NR_clonefileat VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(462)
+#endif /* DARWIN_VERS >= DARWIN_10_12 */
+
+#if DARWIN_VERS >= DARWIN_10_10
+#define __NR_faccessat VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(466)
+#define __NR_fstatat64 VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(470)
#define __NR_readlinkat VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(473)
#define __NR_bsdthread_ctl VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(478)
+#define __NR_csrctl VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(483)
#define __NR_guarded_open_dprotected_np VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(484)
#define __NR_guarded_write_np VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(485)
#define __NR_guarded_pwrite_np VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(486)
#define __NR_guarded_writev_np VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(487)
- /* 488 */
- /* 489 */
#endif /* DARWIN_VERS >= DARWIN_10_10 */
-// TODO Update with OS X 10.11 kernel (xnu) source code release
+#if DARWIN_VERS >= DARWIN_10_12
+#define __NR_renameatx_np VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(488)
+#endif /* DARWIN_VERS >= DARWIN_10_12 */
+ /* 489 */
+
#if DARWIN_VERS >= DARWIN_10_11
- /* 490 */
- /* 491 */
- /* 492 */
- /* 493 */
- /* 494 */
+#define __NR_netagent_trigger VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(490)
+#define __NR_stack_snapshot_with_config VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(491)
+#define __NR_microstackshot VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(492)
+#define __NR_grab_pgo_data VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(493)
+#define __NR_persona VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(494)
/* 495 */
/* 496 */
/* 497 */
/* 498 */
- /* 499 */
+#define __NR_work_interval_ctl VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(499)
#endif /* DARWIN_VERS >= DARWIN_10_11 */
-// TODO Update with macOS 10.12 kernel (xnu) source code release
#if DARWIN_VERS >= DARWIN_10_12
- /* 500 */
- /* 501 */
- /* 502 */
+#define __NR_getentropy VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(500)
+#define __NR_necp_open VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(501)
+#define __NR_necp_client_action VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(502)
/* 503 */
/* 504 */
/* 505 */
@@ -773,13 +795,13 @@
/* 512 */
/* 513 */
/* 514 */
- /* 515 */
- /* 516 */
- /* 517 */
- /* 518 */
+#define __NR_ulock_wait VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(515)
+#define __NR_ulock_wake VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(516)
+#define __NR_fclonefileat VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(517)
+#define __NR_fs_snapshot VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(518)
/* 519 */
- /* 520 */
- /* 521 */
+#define __NR_terminate_with_payload VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(520)
+#define __NR_abort_with_payload VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(521)
#endif /* DARWIN_VERS >= DARWIN_10_12 */
#if DARWIN_VERS < DARWIN_10_6
@@ -795,7 +817,6 @@
#elif DARWIN_VERS == DARWIN_10_11
#define __NR_MAXSYSCALL VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(500)
#elif DARWIN_VERS == DARWIN_10_12
-// TODO Confirm against final release
#define __NR_MAXSYSCALL VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(522)
#else
#error unknown darwin version
diff --git a/include/vki/vki-scnums-mips32-linux.h b/include/vki/vki-scnums-mips32-linux.h
index 5103b43..0187e90 100644
--- a/include/vki/vki-scnums-mips32-linux.h
+++ b/include/vki/vki-scnums-mips32-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 RT-RK
+ Copyright (C) 2010-2017 RT-RK
mips-valgrind@rt-rk.com
This program is free software; you can redistribute it and/or
diff --git a/include/vki/vki-scnums-mips64-linux.h b/include/vki/vki-scnums-mips64-linux.h
index 79cc553..e3d8536 100644
--- a/include/vki/vki-scnums-mips64-linux.h
+++ b/include/vki/vki-scnums-mips64-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2015 RT-RK
+ Copyright (C) 2010-2017 RT-RK
mips-valgrind@rt-rk.com
This program is free software; you can redistribute it and/or
diff --git a/include/vki/vki-scnums-ppc32-linux.h b/include/vki/vki-scnums-ppc32-linux.h
index 644ac8a..c2859ed 100644
--- a/include/vki/vki-scnums-ppc32-linux.h
+++ b/include/vki/vki-scnums-ppc32-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Julian Seward
+ Copyright (C) 2005-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/vki/vki-scnums-ppc64-linux.h b/include/vki/vki-scnums-ppc64-linux.h
index 2a20161..a195c01 100644
--- a/include/vki/vki-scnums-ppc64-linux.h
+++ b/include/vki/vki-scnums-ppc64-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2015 Julian Seward
+ Copyright (C) 2005-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/vki/vki-scnums-s390x-linux.h b/include/vki/vki-scnums-s390x-linux.h
index 0187045..bc436dd 100644
--- a/include/vki/vki-scnums-s390x-linux.h
+++ b/include/vki/vki-scnums-s390x-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2015
+ Copyright IBM Corp. 2010-2017
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/include/vki/vki-scnums-solaris.h b/include/vki/vki-scnums-solaris.h
index 2a6b6de..f9056ab 100644
--- a/include/vki/vki-scnums-solaris.h
+++ b/include/vki/vki-scnums-solaris.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2015 Petr Pavlu
+ Copyright (C) 2011-2017 Petr Pavlu
setup@dagobah.cz
This program is free software; you can redistribute it and/or
@@ -28,7 +28,7 @@
The GNU General Public License is contained in the file COPYING.
*/
-/* Copyright 2013-2016, Ivo Raisr <ivosh@ivosh.net>. */
+/* Copyright 2013-2017, Ivo Raisr <ivosh@ivosh.net>. */
/* Copyright 2013, OmniTI Computer Consulting, Inc. All rights reserved. */
@@ -144,7 +144,7 @@
#define __NR_setgroups SYS_setgroups
#define __NR_getgroups SYS_getgroups
#define __NR_sigprocmask SYS_sigprocmask
-//#define __NR_sigsuspend SYS_sigsuspend
+#define __NR_sigsuspend SYS_sigsuspend
#define __NR_sigaltstack SYS_sigaltstack
#define __NR_sigaction SYS_sigaction
#define __NR_sigpending SYS_sigpending
@@ -157,7 +157,7 @@
#define __NR_nfssys SYS_nfssys
#define __NR_waitid SYS_waitid
#define __NR_waitsys SYS_waitsys /* = SYS_waitid (historical) */
-//#define __NR_sigsendsys SYS_sigsendsys
+#define __NR_sigsendsys SYS_sigsendsys
//#define __NR_hrtsys SYS_hrtsys
#if defined(SOLARIS_UTIMESYS_SYSCALL)
#define __NR_utimesys SYS_utimesys
@@ -237,8 +237,7 @@
//#define __NR_brand SYS_brand
//#define __NR_kaio SYS_kaio
//#define __NR_cpc SYS_cpc
-//#define __NR_lgrpsys SYS_lgrpsys
-//#define __NR_meminfosys SYS_meminfosys /* = SYS_lgrpsys */
+#define __NR_lgrpsys SYS_lgrpsys
#define __NR_rusagesys SYS_rusagesys
#define __NR_port SYS_port
#define __NR_pollsys SYS_pollsys
@@ -354,10 +353,8 @@
VG_SOLARIS_SYSCALL_CONSTRUCT_FASTTRAP(T_GETHRVTIME)
#define __NR_gethrestime \
VG_SOLARIS_SYSCALL_CONSTRUCT_FASTTRAP(T_GETHRESTIME)
-/*
#define __NR_getlgrp \
VG_SOLARIS_SYSCALL_CONSTRUCT_FASTTRAP(T_GETLGRP)
-*/
#if defined(SOLARIS_GETHRT_FASTTRAP)
#define __NR_gethrt \
VG_SOLARIS_SYSCALL_CONSTRUCT_FASTTRAP(T_GETHRT)
diff --git a/include/vki/vki-scnums-x86-linux.h b/include/vki/vki-scnums-x86-linux.h
index a4e75a7..8a6376b 100644
--- a/include/vki/vki-scnums-x86-linux.h
+++ b/include/vki/vki-scnums-x86-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/vki/vki-solaris-repcache.h b/include/vki/vki-solaris-repcache.h
index e2ad269..57f031e 100644
--- a/include/vki/vki-solaris-repcache.h
+++ b/include/vki/vki-solaris-repcache.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2015-2016 Ivo Raisr
+ Copyright (C) 2015-2017 Ivo Raisr
ivosh@ivosh.net
This program is free software; you can redistribute it and/or
@@ -28,7 +28,7 @@
The GNU General Public License is contained in the file COPYING.
*/
-/* Copyright 2015-2015, Tomas Jedlicka <jedlickat@gmail.com>. */
+/* Copyright 2015-2017, Tomas Jedlicka <jedlickat@gmail.com>. */
#ifndef __VKI_SOLARIS_REPCACHE_H
#define __VKI_SOLARIS_REPCACHE_H
@@ -343,7 +343,7 @@
#error Unsupported repcache protocol version
#endif
-/* The following definitions are currently stable accross all repcache protocol
+/* The following definitions are currently stable across all repcache protocol
versions. If there is any change to them, they need to be versioned
properly so that Valgrind works on older versions. */
diff --git a/include/vki/vki-solaris.h b/include/vki/vki-solaris.h
index 002b2df..5b7bb21 100644
--- a/include/vki/vki-solaris.h
+++ b/include/vki/vki-solaris.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2015 Petr Pavlu
+ Copyright (C) 2011-2017 Petr Pavlu
setup@dagobah.cz
This program is free software; you can redistribute it and/or
@@ -28,7 +28,7 @@
The GNU General Public License is contained in the file COPYING.
*/
-/* Copyright 2013-2016, Ivo Raisr <ivosh@ivosh.net> */
+/* Copyright 2013-2017, Ivo Raisr <ivosh@ivosh.net> */
/* Copyright 2013, OmniTI Computer Consulting, Inc. All rights reserved. */
@@ -500,13 +500,14 @@
#define VKI_O_LARGEFILE O_LARGEFILE
#define VKI_F_DUPFD F_DUPFD
+#define VKI_F_DUPFD_CLOEXEC F_DUPFD_CLOEXEC
#define VKI_F_GETFD F_GETFD
#define VKI_F_SETFD F_SETFD
#define VKI_F_GETFL F_GETFL
#define VKI_F_GETXFL F_GETXFL
#define VKI_F_SETFL F_SETFL
-/* SVR3 rfs compability const, declared only if _KERNEL or _KMEMUSER is
+/* SVR3 rfs compatibility const, declared only if _KERNEL or _KMEMUSER is
defined. */
#if 0
#define VKI_F_O_GETLK F_O_GETLK
@@ -603,6 +604,26 @@
#define vki_semid64_ds semid_ds64
+#include <sys/lgrp_user.h>
+#if defined(HAVE_SYS_LGRP_USER_IMPL_H)
+/* Include implementation specific header file on newer Solaris. */
+#include <sys/lgrp_user_impl.h>
+#endif /* HAVE_SYS_LGRP_USER_IMPL_H */
+#define VKI_LGRP_SYS_MEMINFO LGRP_SYS_MEMINFO
+#define VKI_LGRP_SYS_GENERATION LGRP_SYS_GENERATION
+#define VKI_LGRP_SYS_VERSION LGRP_SYS_VERSION
+#define VKI_LGRP_SYS_SNAPSHOT LGRP_SYS_SNAPSHOT
+#define VKI_LGRP_SYS_AFFINITY_GET LGRP_SYS_AFFINITY_GET
+#define VKI_LGRP_SYS_AFFINITY_SET LGRP_SYS_AFFINITY_SET
+#define VKI_LGRP_SYS_LATENCY LGRP_SYS_LATENCY
+#define VKI_LGRP_SYS_HOME LGRP_SYS_HOME
+#define VKI_LGRP_SYS_AFF_INHERIT_GET LGRP_SYS_AFF_INHERIT_GET
+#define VKI_LGRP_SYS_AFF_INHERIT_SET LGRP_SYS_AFF_INHERIT_SET
+#define VKI_LGRP_SYS_DEVICE_LGRPS LGRP_SYS_DEVICE_LGRPS
+#define VKI_LGRP_SYS_MAXSOCKETS_GET LGRP_SYS_MAXSOCKETS_GET
+#define vki_lgrp_view_t lgrp_view_t
+
+
#include <sys/loadavg.h>
#define VKI_LOADAVG_NSTATS LOADAVG_NSTATS
@@ -642,6 +663,8 @@
#define VKI_MC_UNLOCKAS MC_UNLOCKAS
#define VKI_MC_HAT_ADVISE MC_HAT_ADVISE
+#define vki_meminfo_t meminfo_t
+
#include <sys/mntio.h>
#define VKI_MNTIOC_GETEXTMNTENT MNTIOC_GETEXTMNTENT
@@ -813,6 +836,7 @@
#define VKI_P_PID P_PID
#define VKI_P_PGID P_PGID
#define VKI_P_ALL P_ALL
+#define VKI_POP_AND POP_AND
#define vki_procset_t procset_t
diff --git a/include/vki/vki-x86-linux.h b/include/vki/vki-x86-linux.h
index 345b8a4..12ded91 100644
--- a/include/vki/vki-x86-linux.h
+++ b/include/vki/vki-x86-linux.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/include/vki/vki-xen-domctl.h b/include/vki/vki-xen-domctl.h
index d381ee6..9e8b5ef 100644
--- a/include/vki/vki-xen-domctl.h
+++ b/include/vki/vki-xen-domctl.h
@@ -2,7 +2,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2012-2015 Citrix
+ Copyright (C) 2012-2017 Citrix
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -36,6 +36,8 @@
* - 0x00000008: Xen 4.2
* - 0x00000009: Xen 4.3 & 4.4
* - 0x0000000a: Xen 4.5
+ * - 0x0000000b: Xen 4.6
+ * - 0x0000000c: Xen 4.7
*
* When adding a new subop be sure to include the variants used by all
* of the above, both here and in syswrap-xen.c
@@ -99,6 +101,7 @@
#define VKI_XEN_DOMCTL_debug_op 54
#define VKI_XEN_DOMCTL_gethvmcontext_partial 55
#define VKI_XEN_DOMCTL_mem_event_op 56
+#define VKI_XEN_DOMCTL_vm_event_op 56 /* name change in 4.6 */
#define VKI_XEN_DOMCTL_mem_sharing_op 57
#define VKI_XEN_DOMCTL_disable_migrate 58
#define VKI_XEN_DOMCTL_gettscinfo 59
@@ -116,6 +119,7 @@
#define VKI_XEN_DOMCTL_cacheflush 71
#define VKI_XEN_DOMCTL_get_vcpu_msrs 72
#define VKI_XEN_DOMCTL_set_vcpu_msrs 73
+#define VKI_XEN_DOMCTL_monitor_op 77 /* new in 4.6 */
#define VKI_XEN_DOMCTL_gdbsx_guestmemio 1000
#define VKI_XEN_DOMCTL_gdbsx_pausevcpu 1001
#define VKI_XEN_DOMCTL_gdbsx_unpausevcpu 1002
@@ -351,6 +355,22 @@
typedef struct vki_xen_guest_tsc_info vki_xen_guest_tsc_info_t;
DEFINE_VKI_XEN_GUEST_HANDLE(vki_xen_guest_tsc_info_t);
+struct vki_xen_domctl_tsc_info_00000007 {
+ VKI_XEN_GUEST_HANDLE_64(vki_xen_guest_tsc_info_t) out_info; /* OUT */
+ vki_xen_guest_tsc_info_t info; /* IN */
+};
+
+/* 4.6 removed the output pointer */
+struct vki_xen_domctl_tsc_info_0000000b {
+ /* IN/OUT */
+ vki_uint32_t tsc_mode;
+ vki_uint32_t gtsc_khz;
+ vki_uint32_t incarnation;
+ vki_uint32_t pad;
+ vki_xen_uint64_aligned_t elapsed_nsec;
+};
+
+
struct vki_xen_domctl_hvmcontext {
vki_uint32_t size; /* IN/OUT size of buffer */
VKI_XEN_GUEST_HANDLE_64(vki_uint8) buffer; /* IN/OUT */
@@ -366,10 +386,6 @@
typedef struct vki_xen_domctl_hvmcontext_partial vki_xen_domctl_hvmcontext_partial_t;
DEFINE_VKI_XEN_GUEST_HANDLE(vki_xen_domctl_hvmcontext_partial_t);
-struct vki_xen_domctl_tsc_info {
- VKI_XEN_GUEST_HANDLE_64(vki_xen_guest_tsc_info_t) out_info; /* OUT */
- vki_xen_guest_tsc_info_t info; /* IN */
-};
struct vki_xen_domctl_pin_mem_cacheattr {
vki_xen_uint64_aligned_t start, end; /* IN */
@@ -425,22 +441,44 @@
vki_uint32_t size;
};
-struct vki_xen_domctl_assign_device {
+/* vki_xen_domctl_assign_device_00000007 is the same up to version 0x0000000b */
+struct vki_xen_domctl_assign_device_00000007 {
vki_uint32_t machine_sbdf; /* machine PCI ID of assigned device */
};
+#define VKI_XEN_DOMCTL_DEV_PCI 0
+#define VKI_XEN_DOMCTL_DEV_DT 1
+struct vki_xen_domctl_assign_device_0000000b {
+ vki_uint32_t dev; /* XEN_DOMCTL_DEV_* */
+ union {
+ struct {
+ vki_uint32_t machine_sbdf; /* machine PCI ID of assigned device */
+ } pci;
+ struct {
+ vki_uint32_t size; /* Length of the path */
+ VKI_XEN_GUEST_HANDLE_64(vki_uint8) path; /* path to the device tree node */
+ } dt;
+ } u;
+ /* IN */
+//#define XEN_DOMCTL_DEV_RDM_RELAXED 1
+ vki_uint32_t flag; /* flag of assigned device */
+};
+
struct vki_xen_domctl_debug_op {
vki_uint32_t op; /* IN */
vki_uint32_t vcpu; /* IN */
};
typedef struct vki_xen_domctl_debug_op vki_xen_domctl_debug_op_t;
-struct vki_xen_domctl_mem_event_op {
+struct vki_xen_domctl_mem_event_op_00000007 {
vki_uint32_t op; /* IN */
vki_uint32_t mode; /* IN */
vki_uint32_t port; /* OUT */
};
+/* only a name change in 4.6 */
+typedef struct vki_xen_domctl_mem_event_op_00000007 vki_xen_domctl_vm_event_op_0000000b;
+
struct vki_xen_domctl_set_access_required {
vki_uint8_t access_required; /* IN */
};
@@ -468,6 +506,76 @@
VKI_XEN_GUEST_HANDLE_64(vki_xen_domctl_vcpu_msr_t) msrs;
};
+#define VKI_XEN_DOMCTL_MONITOR_OP_ENABLE 0
+#define VKI_XEN_DOMCTL_MONITOR_OP_DISABLE 1
+#define VKI_XEN_DOMCTL_MONITOR_OP_GET_CAPABILITIES 2
+
+#define VKI_XEN_DOMCTL_MONITOR_EVENT_WRITE_CTRLREG 0
+#define VKI_XEN_DOMCTL_MONITOR_EVENT_MOV_TO_MSR 1
+#define VKI_XEN_DOMCTL_MONITOR_EVENT_SINGLESTEP 2
+#define VKI_XEN_DOMCTL_MONITOR_EVENT_SOFTWARE_BREAKPOINT 3
+#define VKI_XEN_DOMCTL_MONITOR_EVENT_GUEST_REQUEST 4
+
+struct vki_xen_domctl_monitor_op_0000000b {
+ vki_uint32_t op; /* vki_xen_DOMCTL_MONITOR_OP_* */
+
+ /*
+ * When used with ENABLE/DISABLE this has to be set to
+ * the requested vki_xen_DOMCTL_MONITOR_EVENT_* value.
+ * With GET_CAPABILITIES this field returns a bitmap of
+ * events supported by the platform, in the format
+ * (1 << vki_xen_DOMCTL_MONITOR_EVENT_*).
+ */
+ vki_uint32_t event;
+
+ /*
+ * Further options when issuing vki_xen_DOMCTL_MONITOR_OP_ENABLE.
+ */
+ union {
+ struct {
+ /* Which control register */
+ vki_uint8_t index;
+ /* Pause vCPU until response */
+ vki_uint8_t sync;
+ /* Send event only on a change of value */
+ vki_uint8_t onchangeonly;
+ } mov_to_cr;
+
+ struct {
+ /* Enable the capture of an extended set of MSRs */
+ vki_uint8_t extended_capture;
+ } mov_to_msr;
+
+ struct {
+ /* Pause vCPU until response */
+ vki_uint8_t sync;
+ } guest_request;
+ } u;
+};
+
+
+struct vki_xen_domctl_monitor_op {
+ vki_uint32_t op;
+#define VKI_XEN_DOMCTL_MONITOR_OP_ENABLE 0
+#define VKI_XEN_DOMCTL_MONITOR_OP_DISABLE 1
+#define VKI_XEN_DOMCTL_MONITOR_OP_GET_CAPABILITIES 2
+#define VKI_XEN_DOMCTL_MONITOR_OP_EMULATE_EACH_REP 3
+ vki_uint32_t event;
+ union {
+ struct {
+ vki_uint8_t index;
+ vki_uint8_t sync;
+ vki_uint8_t onchangeonly;
+ } mov_to_cr;
+ struct {
+ vki_uint8_t extended_capture;
+ } mov_to_msr;
+ struct {
+ vki_uint8_t sync;
+ } guest_request;
+ } u;
+};
+
struct vki_xen_domctl {
vki_uint32_t cmd;
vki_uint32_t interface_version; /* XEN_DOMCTL_INTERFACE_VERSION */
@@ -499,14 +607,16 @@
//struct vki_xen_domctl_arch_setup arch_setup;
struct vki_xen_domctl_settimeoffset settimeoffset;
//struct vki_xen_domctl_disable_migrate disable_migrate;
- struct vki_xen_domctl_tsc_info tsc_info;
+ struct vki_xen_domctl_tsc_info_00000007 tsc_info_00000007;
+ struct vki_xen_domctl_tsc_info_0000000b tsc_info_0000000b;
//struct vki_xen_domctl_real_mode_area real_mode_area;
struct vki_xen_domctl_hvmcontext hvmcontext;
struct vki_xen_domctl_hvmcontext_partial hvmcontext_partial;
struct vki_xen_domctl_address_size address_size;
//struct vki_xen_domctl_sendtrigger sendtrigger;
//struct vki_xen_domctl_get_device_group get_device_group;
- struct vki_xen_domctl_assign_device assign_device;
+ struct vki_xen_domctl_assign_device_00000007 assign_device_00000007;
+ struct vki_xen_domctl_assign_device_0000000b assign_device_0000000b;
//struct vki_xen_domctl_bind_pt_irq bind_pt_irq;
//struct vki_xen_domctl_memory_mapping memory_mapping;
//struct vki_xen_domctl_ioport_mapping ioport_mapping;
@@ -516,7 +626,8 @@
//struct vki_xen_domctl_set_target set_target;
//struct vki_xen_domctl_subscribe subscribe;
struct vki_xen_domctl_debug_op debug_op;
- struct vki_xen_domctl_mem_event_op mem_event_op;
+ struct vki_xen_domctl_mem_event_op_00000007 mem_event_op_00000007;
+ vki_xen_domctl_vm_event_op_0000000b vm_event_op_0000000b;
//struct vki_xen_domctl_mem_sharing_op mem_sharing_op;
#if defined(__i386__) || defined(__x86_64__)
struct vki_xen_domctl_cpuid cpuid;
@@ -532,6 +643,7 @@
struct vki_xen_domctl_cacheflush cacheflush;
//struct vki_xen_domctl_gdbsx_pauseunp_vcpu gdbsx_pauseunp_vcpu;
//struct vki_xen_domctl_gdbsx_domstatus gdbsx_domstatus;
+ struct vki_xen_domctl_monitor_op_0000000b monitor_op_0000000b;
vki_uint8_t pad[128];
} u;
};
diff --git a/include/vki/vki-xen-evtchn.h b/include/vki/vki-xen-evtchn.h
index d8ff600..9d4e4c3 100644
--- a/include/vki/vki-xen-evtchn.h
+++ b/include/vki/vki-xen-evtchn.h
@@ -2,7 +2,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2012-2015 Citrix
+ Copyright (C) 2012-2017 Citrix
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/include/vki/vki-xen-gnttab.h b/include/vki/vki-xen-gnttab.h
index 11c4219..3e6c36c 100644
--- a/include/vki/vki-xen-gnttab.h
+++ b/include/vki/vki-xen-gnttab.h
@@ -2,7 +2,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2012-2015 Citrix
+ Copyright (C) 2012-2017 Citrix
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/include/vki/vki-xen-hvm.h b/include/vki/vki-xen-hvm.h
index 0664b73..0c34570 100644
--- a/include/vki/vki-xen-hvm.h
+++ b/include/vki/vki-xen-hvm.h
@@ -2,7 +2,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2012-2015 Citrix
+ Copyright (C) 2012-2017 Citrix
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/include/vki/vki-xen-memory.h b/include/vki/vki-xen-memory.h
index c307690..3b6f9e5 100644
--- a/include/vki/vki-xen-memory.h
+++ b/include/vki/vki-xen-memory.h
@@ -2,7 +2,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2012-2015 Citrix
+ Copyright (C) 2012-2017 Citrix
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/include/vki/vki-xen-mmuext.h b/include/vki/vki-xen-mmuext.h
index 5e758b3..817269c 100644
--- a/include/vki/vki-xen-mmuext.h
+++ b/include/vki/vki-xen-mmuext.h
@@ -2,7 +2,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2012-2015 Citrix
+ Copyright (C) 2012-2017 Citrix
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/include/vki/vki-xen-physdev.h b/include/vki/vki-xen-physdev.h
index d3111a0..6f8c2c8 100644
--- a/include/vki/vki-xen-physdev.h
+++ b/include/vki/vki-xen-physdev.h
@@ -2,7 +2,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2012-2015 Citrix
+ Copyright (C) 2012-2017 Citrix
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/include/vki/vki-xen-schedop.h b/include/vki/vki-xen-schedop.h
index 30f8a33..3c5b2ce 100644
--- a/include/vki/vki-xen-schedop.h
+++ b/include/vki/vki-xen-schedop.h
@@ -2,7 +2,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2012-2015 Citrix
+ Copyright (C) 2012-2017 Citrix
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/include/vki/vki-xen-tmem.h b/include/vki/vki-xen-tmem.h
index e372ae6..bc51f93 100644
--- a/include/vki/vki-xen-tmem.h
+++ b/include/vki/vki-xen-tmem.h
@@ -2,7 +2,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2012-2015 Citrix
+ Copyright (C) 2012-2017 Citrix
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/include/vki/vki-xen-version.h b/include/vki/vki-xen-version.h
index a022c94..dfaf7c0 100644
--- a/include/vki/vki-xen-version.h
+++ b/include/vki/vki-xen-version.h
@@ -2,7 +2,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2012-2015 Citrix
+ Copyright (C) 2012-2017 Citrix
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/include/vki/vki-xen-x86.h b/include/vki/vki-xen-x86.h
index a54a4de..a26b3ea 100644
--- a/include/vki/vki-xen-x86.h
+++ b/include/vki/vki-xen-x86.h
@@ -2,7 +2,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2012-2015 Citrix
+ Copyright (C) 2012-2017 Citrix
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -270,6 +270,19 @@
VKI_DECLARE_HVM_SAVE_TYPE(CPU, 2, struct vki_hvm_hw_cpu);
+struct vki_hvm_hw_mtrr {
+#define VKI_MTRR_VCNT 8
+#define VKI_NUM_FIXED_MSR 11
+ vki_uint64_t msr_pat_cr;
+ /* mtrr physbase & physmask msr pair*/
+ vki_uint64_t msr_mtrr_var[VKI_MTRR_VCNT*2];
+ vki_uint64_t msr_mtrr_fixed[VKI_NUM_FIXED_MSR];
+ vki_uint64_t msr_mtrr_cap;
+ vki_uint64_t msr_mtrr_def_type;
+};
+
+VKI_DECLARE_HVM_SAVE_TYPE(MTRR, 14, struct vki_hvm_hw_mtrr);
+
#endif // __VKI_XEN_H
/*--------------------------------------------------------------------*/
diff --git a/include/vki/vki-xen-xsm.h b/include/vki/vki-xen-xsm.h
index b8eb50d..2e4b17f 100644
--- a/include/vki/vki-xen-xsm.h
+++ b/include/vki/vki-xen-xsm.h
@@ -2,7 +2,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2012-2015 Citrix
+ Copyright (C) 2012-2017 Citrix
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/include/vki/vki-xen.h b/include/vki/vki-xen.h
index 924a1e9..c0dfee3 100644
--- a/include/vki/vki-xen.h
+++ b/include/vki/vki-xen.h
@@ -2,7 +2,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2012-2015 Citrix
+ Copyright (C) 2012-2017 Citrix
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/lackey/Makefile.in b/lackey/Makefile.in
index 62f3b60..f1caee5 100644
--- a/lackey/Makefile.in
+++ b/lackey/Makefile.in
@@ -284,6 +284,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -455,6 +456,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -465,6 +467,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -539,8 +542,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -585,7 +586,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
@@ -663,9 +663,6 @@
-static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \
@FLAG_M64@
-TOOL_LDFLAGS_TILEGX_LINUX = \
- $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-
TOOL_LDFLAGS_X86_SOLARIS = \
$(TOOL_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
@@ -720,9 +717,6 @@
LIBREPLACEMALLOC_MIPS64_LINUX = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a
-LIBREPLACEMALLOC_TILEGX_LINUX = \
- $(top_builddir)/coregrind/libreplacemalloc_toolpreload-tilegx-linux.a
-
LIBREPLACEMALLOC_X86_SOLARIS = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-solaris.a
@@ -785,11 +779,6 @@
$(LIBREPLACEMALLOC_MIPS64_LINUX) \
-Wl,--no-whole-archive
-LIBREPLACEMALLOC_LDFLAGS_TILEGX_LINUX = \
- -Wl,--whole-archive \
- $(LIBREPLACEMALLOC_TILEGX_LINUX) \
- -Wl,--no-whole-archive
-
LIBREPLACEMALLOC_LDFLAGS_X86_SOLARIS = \
-Wl,--whole-archive \
$(LIBREPLACEMALLOC_X86_SOLARIS) \
diff --git a/lackey/lk_main.c b/lackey/lk_main.c
index bc0f63a..707ba97 100644
--- a/lackey/lk_main.c
+++ b/lackey/lk_main.c
@@ -7,7 +7,7 @@
This file is part of Lackey, an example Valgrind tool that does
some simple program measurement and tracing.
- Copyright (C) 2002-2015 Nicholas Nethercote
+ Copyright (C) 2002-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -1011,7 +1011,7 @@
VG_(umsg)("Jccs:\n");
VG_(umsg)(" total: %'llu\n", total_Jccs);
VG_(umsg)(" taken: %'llu (%.0f%%)\n",
- taken_Jccs, taken_Jccs * 100.0 / total_Jccs ?: 1);
+ taken_Jccs, taken_Jccs * 100.0 / (total_Jccs ? total_Jccs : 1));
VG_(umsg)("\n");
VG_(umsg)("Executed:\n");
@@ -1050,7 +1050,7 @@
VG_(details_version) (NULL);
VG_(details_description) ("an example Valgrind tool");
VG_(details_copyright_author)(
- "Copyright (C) 2002-2015, and GNU GPL'd, by Nicholas Nethercote.");
+ "Copyright (C) 2002-2017, and GNU GPL'd, by Nicholas Nethercote.");
VG_(details_bug_reports_to) (VG_BUGS_TO);
VG_(details_avg_translation_sizeB) ( 200 );
diff --git a/lackey/tests/Makefile.in b/lackey/tests/Makefile.in
index 03f1c43..242d798 100644
--- a/lackey/tests/Makefile.in
+++ b/lackey/tests/Makefile.in
@@ -166,6 +166,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
diff --git a/massif/Makefile.in b/massif/Makefile.in
index 8b16352..8fc6889 100644
--- a/massif/Makefile.in
+++ b/massif/Makefile.in
@@ -339,6 +339,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -510,6 +511,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -520,6 +522,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -594,8 +597,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -640,7 +641,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
@@ -718,9 +718,6 @@
-static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \
@FLAG_M64@
-TOOL_LDFLAGS_TILEGX_LINUX = \
- $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-
TOOL_LDFLAGS_X86_SOLARIS = \
$(TOOL_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
@@ -775,9 +772,6 @@
LIBREPLACEMALLOC_MIPS64_LINUX = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a
-LIBREPLACEMALLOC_TILEGX_LINUX = \
- $(top_builddir)/coregrind/libreplacemalloc_toolpreload-tilegx-linux.a
-
LIBREPLACEMALLOC_X86_SOLARIS = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-solaris.a
@@ -840,11 +834,6 @@
$(LIBREPLACEMALLOC_MIPS64_LINUX) \
-Wl,--no-whole-archive
-LIBREPLACEMALLOC_LDFLAGS_TILEGX_LINUX = \
- -Wl,--whole-archive \
- $(LIBREPLACEMALLOC_TILEGX_LINUX) \
- -Wl,--no-whole-archive
-
LIBREPLACEMALLOC_LDFLAGS_X86_SOLARIS = \
-Wl,--whole-archive \
$(LIBREPLACEMALLOC_X86_SOLARIS) \
diff --git a/massif/docs/ms-manual.xml b/massif/docs/ms-manual.xml
index 4c555a9..b330335 100644
--- a/massif/docs/ms-manual.xml
+++ b/massif/docs/ms-manual.xml
@@ -46,6 +46,11 @@
which parts of your program are responsible for allocating the heap memory.
</para>
+<para>Massif also provides <xref linkend="manual-core.xtree"/> memory
+ profiling using the command line
+ option <computeroutput>--xtree-memory</computeroutput> and the monitor command
+ <computeroutput>xtmemory</computeroutput>.</para>
+
</sect1>
diff --git a/massif/ms_main.c b/massif/ms_main.c
index 628a37b..a2c1f39 100644
--- a/massif/ms_main.c
+++ b/massif/ms_main.c
@@ -6,7 +6,7 @@
This file is part of Massif, a Valgrind tool for profiling memory
usage of programs.
- Copyright (C) 2003-2015 Nicholas Nethercote
+ Copyright (C) 2003-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -69,11 +69,6 @@
// [Introduction of --time-unit=i as the default slowed things down by
// roughly 0--20%.]
//
-// - get_XCon accounts for about 9% of konqueror startup time. Try
-// keeping XPt children sorted by 'ip' and use binary search in get_XCon.
-// Requires factoring out binary search code from various places into a
-// VG_(bsearch) function.
-//
// Todo -- low priority:
// - In each XPt, record both bytes and the number of allocations, and
// possibly the global number of allocations.
@@ -168,11 +163,14 @@
#include "pub_tool_machine.h"
#include "pub_tool_mallocfree.h"
#include "pub_tool_options.h"
+#include "pub_tool_poolalloc.h"
#include "pub_tool_replacemalloc.h"
#include "pub_tool_stacktrace.h"
#include "pub_tool_threadstate.h"
#include "pub_tool_tooliface.h"
#include "pub_tool_xarray.h"
+#include "pub_tool_xtree.h"
+#include "pub_tool_xtmemory.h"
#include "pub_tool_clientstate.h"
#include "pub_tool_gdbserver.h"
@@ -184,7 +182,7 @@
// The size of the stacks and heap is tracked. The heap is tracked in a lot
// of detail, enough to tell how many bytes each line of code is responsible
-// for, more or less. The main data structure is a tree representing the
+// for, more or less. The main data structure is an xtree maintaining the
// call tree beneath all the allocation functions like malloc().
// (Alternatively, if --pages-as-heap=yes is specified, memory is tracked at
// the page level, and each page is treated much like a heap block. We use
@@ -216,8 +214,8 @@
// Used for printing things when clo_verbosity > 1.
#define VERB(verb, format, args...) \
- if (VG_(clo_verbosity) > verb) { \
- VG_(dmsg)("Massif: " format, ##args); \
+ if (UNLIKELY(VG_(clo_verbosity) > verb)) { \
+ VG_(dmsg)("Massif: " format, ##args); \
}
//------------------------------------------------------------//
@@ -241,17 +239,12 @@
static UInt n_ignored_heap_reallocs = 0;
static UInt n_stack_allocs = 0;
static UInt n_stack_frees = 0;
-static UInt n_xpts = 0;
-static UInt n_xpt_init_expansions = 0;
-static UInt n_xpt_later_expansions = 0;
-static UInt n_sxpt_allocs = 0;
-static UInt n_sxpt_frees = 0;
+
static UInt n_skipped_snapshots = 0;
static UInt n_real_snapshots = 0;
static UInt n_detailed_snapshots = 0;
static UInt n_peak_snapshots = 0;
static UInt n_cullings = 0;
-static UInt n_XCon_redos = 0;
//------------------------------------------------------------//
//--- Globals ---//
@@ -348,25 +341,6 @@
VG_(free), sizeof(HChar*));
}
-// Determines if the named function is a member of the XArray.
-static Bool is_member_fn(const XArray* fns, const HChar* fnname)
-{
- HChar** fn_ptr;
- Int i;
-
- // Nb: It's a linear search through the list, because we're comparing
- // strings rather than pointers to strings.
- // Nb: This gets called a lot. It was an OSet, but they're quite slow to
- // iterate through so it wasn't a good choice.
- for (i = 0; i < VG_(sizeXA)(fns); i++) {
- fn_ptr = VG_(indexXA)(fns, i);
- if (VG_STREQ(fnname, *fn_ptr))
- return True;
- }
- return False;
-}
-
-
//------------------------------------------------------------//
//--- Command line args ---//
//------------------------------------------------------------//
@@ -481,511 +455,165 @@
//------------------------------------------------------------//
-//--- XPts, XTrees and XCons ---//
+//--- XTrees ---//
//------------------------------------------------------------//
-// An XPt represents an "execution point", ie. a code address. Each XPt is
-// part of a tree of XPts (an "execution tree", or "XTree"). The details of
-// the heap are represented by a single XTree.
+// The details of the heap are represented by a single XTree.
+// This XTree maintains the nr of allocated bytes for each
+// stacktrace/execontext.
//
-// The root of the tree is 'alloc_xpt', which represents all allocation
-// functions, eg:
+// The root of the Xtree will be output as a top node 'alloc functions',
+// which represents all allocation functions, eg:
// - malloc/calloc/realloc/memalign/new/new[];
// - user-specified allocation functions (using --alloc-fn);
// - custom allocation (MALLOCLIKE) points
-// It's a bit of a fake XPt (ie. its 'ip' is zero), and is only used because
-// it makes the code simpler.
-//
-// Any child of 'alloc_xpt' is called a "top-XPt". The XPts at the bottom
-// of an XTree (leaf nodes) are "bottom-XPTs".
-//
-// Each path from a top-XPt to a bottom-XPt through an XTree gives an
-// execution context ("XCon"), ie. a stack trace. (And sub-paths represent
-// stack sub-traces.) The number of XCons in an XTree is equal to the
-// number of bottom-XPTs in that XTree.
-//
-// alloc_xpt XTrees are bi-directional.
-// | ^
-// v |
-// > parent < Example: if child1() calls parent() and child2()
-// / | \ also calls parent(), and parent() calls malloc(),
-// | / \ | the XTree will look like this.
-// | v v |
-// child1 child2
-//
-// (Note that malformed stack traces can lead to difficulties. See the
-// comment at the bottom of get_XCon.)
-//
-// XTrees and XPts are mirrored by SXTrees and SXPts, where the 'S' is short
-// for "saved". When the XTree is duplicated for a snapshot, we duplicate
-// it as an SXTree, which is similar but omits some things it does not need,
-// and aggregates up insignificant nodes. This is important as an SXTree is
-// typically much smaller than an XTree.
-
-// XXX: make XPt and SXPt extensible arrays, to avoid having to do two
-// allocations per Pt.
-
-typedef struct _XPt XPt;
-struct _XPt {
- Addr ip; // code address
-
- // Bottom-XPts: space for the precise context.
- // Other XPts: space of all the descendent bottom-XPts.
- // Nb: this value goes up and down as the program executes.
- SizeT szB;
-
- XPt* parent; // pointer to parent XPt
-
- // Children.
- // n_children and max_children are 32-bit integers. 16-bit integers
- // are too small -- a very big program might have more than 65536
- // allocation points (ie. top-XPts) -- Konqueror starting up has 1800.
- UInt n_children; // number of children
- UInt max_children; // capacity of children array
- XPt** children; // pointers to children XPts
-};
-
-typedef
- enum {
- SigSXPt,
- InsigSXPt
- }
- SXPtTag;
-
-typedef struct _SXPt SXPt;
-struct _SXPt {
- SXPtTag tag;
- SizeT szB; // memory size for the node, be it Sig or Insig
- union {
- // An SXPt representing a single significant code location. Much like
- // an XPt, minus the fields that aren't necessary.
- struct {
- Addr ip;
- UInt n_children;
- SXPt** children;
- }
- Sig;
-
- // An SXPt representing one or more code locations, all below the
- // significance threshold.
- struct {
- Int n_xpts; // number of aggregated XPts
- }
- Insig;
- };
-};
-
-// Fake XPt representing all allocation functions like malloc(). Acts as
-// parent node to all top-XPts.
-static XPt* alloc_xpt;
-
-static XPt* new_XPt(Addr ip, XPt* parent)
+static XTree* heap_xt;
+/* heap_xt contains a SizeT: the nr of allocated bytes by this execontext. */
+static void init_szB(void* value)
{
- // XPts are never freed, so we can use VG_(perm_malloc) to allocate them.
- // Note that we cannot use VG_(perm_malloc) for the 'children' array, because
- // that needs to be resizable.
- XPt* xpt = VG_(perm_malloc)(sizeof(XPt), vg_alignof(XPt));
- xpt->ip = ip;
- xpt->szB = 0;
- xpt->parent = parent;
-
- // We don't initially allocate any space for children. We let that
- // happen on demand. Many XPts (ie. all the bottom-XPts) don't have any
- // children anyway.
- xpt->n_children = 0;
- xpt->max_children = 0;
- xpt->children = NULL;
-
- // Update statistics
- n_xpts++;
-
- return xpt;
+ *((SizeT*)value) = 0;
+}
+static void add_szB(void* to, const void* value)
+{
+ *((SizeT*)to) += *((const SizeT*)value);
+}
+static void sub_szB(void* from, const void* value)
+{
+ *((SizeT*)from) -= *((const SizeT*)value);
+}
+static ULong alloc_szB(const void* value)
+{
+ return (ULong)*((const SizeT*)value);
}
-static void add_child_xpt(XPt* parent, XPt* child)
-{
- // Expand 'children' if necessary.
- tl_assert(parent->n_children <= parent->max_children);
- if (parent->n_children == parent->max_children) {
- if (0 == parent->max_children) {
- parent->max_children = 4;
- parent->children = VG_(malloc)( "ms.main.acx.1",
- parent->max_children * sizeof(XPt*) );
- n_xpt_init_expansions++;
- } else {
- parent->max_children *= 2; // Double size
- parent->children = VG_(realloc)( "ms.main.acx.2",
- parent->children,
- parent->max_children * sizeof(XPt*) );
- n_xpt_later_expansions++;
- }
- }
-
- // Insert new child XPt in parent's children list.
- parent->children[ parent->n_children++ ] = child;
-}
-
-// Reverse comparison for a reverse sort -- biggest to smallest.
-static Int SXPt_revcmp_szB(const void* n1, const void* n2)
-{
- const SXPt* sxpt1 = *(const SXPt *const *)n1;
- const SXPt* sxpt2 = *(const SXPt *const *)n2;
- return ( sxpt1->szB < sxpt2->szB ? 1
- : sxpt1->szB > sxpt2->szB ? -1
- : 0);
-}
//------------------------------------------------------------//
//--- XTree Operations ---//
//------------------------------------------------------------//
-// Duplicates an XTree as an SXTree.
-static SXPt* dup_XTree(XPt* xpt, SizeT total_szB)
-{
- Int i, n_sig_children, n_insig_children, n_child_sxpts;
- SizeT sig_child_threshold_szB;
- SXPt* sxpt;
-
- // Number of XPt children Action for SXPT
- // ------------------ ---------------
- // 0 sig, 0 insig alloc 0 children
- // N sig, 0 insig alloc N children, dup all
- // N sig, M insig alloc N+1, dup first N, aggregate remaining M
- // 0 sig, M insig alloc 1, aggregate M
-
- // Work out how big a child must be to be significant. If the current
- // total_szB is zero, then we set it to 1, which means everything will be
- // judged insignificant -- this is sensible, as there's no point showing
- // any detail for this case. Unless they used --threshold=0, in which
- // case we show them everything because that's what they asked for.
- //
- // Nb: We do this once now, rather than once per child, because if we do
- // that the cost of all the divisions adds up to something significant.
- if (0 == total_szB && 0 != clo_threshold) {
- sig_child_threshold_szB = 1;
- } else {
- sig_child_threshold_szB = (SizeT)((total_szB * clo_threshold) / 100);
- }
-
- // How many children are significant? And do we need an aggregate SXPt?
- n_sig_children = 0;
- for (i = 0; i < xpt->n_children; i++) {
- if (xpt->children[i]->szB >= sig_child_threshold_szB) {
- n_sig_children++;
- }
- }
- n_insig_children = xpt->n_children - n_sig_children;
- n_child_sxpts = n_sig_children + ( n_insig_children > 0 ? 1 : 0 );
-
- // Duplicate the XPt.
- sxpt = VG_(malloc)("ms.main.dX.1", sizeof(SXPt));
- n_sxpt_allocs++;
- sxpt->tag = SigSXPt;
- sxpt->szB = xpt->szB;
- sxpt->Sig.ip = xpt->ip;
- sxpt->Sig.n_children = n_child_sxpts;
-
- // Create the SXPt's children.
- if (n_child_sxpts > 0) {
- Int j;
- SizeT sig_children_szB = 0, insig_children_szB = 0;
- sxpt->Sig.children = VG_(malloc)("ms.main.dX.2",
- n_child_sxpts * sizeof(SXPt*));
-
- // Duplicate the significant children. (Nb: sig_children_szB +
- // insig_children_szB doesn't necessarily equal xpt->szB.)
- j = 0;
- for (i = 0; i < xpt->n_children; i++) {
- if (xpt->children[i]->szB >= sig_child_threshold_szB) {
- sxpt->Sig.children[j++] = dup_XTree(xpt->children[i], total_szB);
- sig_children_szB += xpt->children[i]->szB;
- } else {
- insig_children_szB += xpt->children[i]->szB;
- }
- }
-
- // Create the SXPt for the insignificant children, if any, and put it
- // in the last child entry.
- if (n_insig_children > 0) {
- // Nb: We 'n_sxpt_allocs' here because creating an Insig SXPt
- // doesn't involve a call to dup_XTree().
- SXPt* insig_sxpt = VG_(malloc)("ms.main.dX.3", sizeof(SXPt));
- n_sxpt_allocs++;
- insig_sxpt->tag = InsigSXPt;
- insig_sxpt->szB = insig_children_szB;
- insig_sxpt->Insig.n_xpts = n_insig_children;
- sxpt->Sig.children[n_sig_children] = insig_sxpt;
- }
- } else {
- sxpt->Sig.children = NULL;
- }
-
- return sxpt;
-}
-
-static void free_SXTree(SXPt* sxpt)
-{
- Int i;
- tl_assert(sxpt != NULL);
-
- switch (sxpt->tag) {
- case SigSXPt:
- // Free all children SXPts, then the children array.
- for (i = 0; i < sxpt->Sig.n_children; i++) {
- free_SXTree(sxpt->Sig.children[i]);
- sxpt->Sig.children[i] = NULL;
- }
- VG_(free)(sxpt->Sig.children); sxpt->Sig.children = NULL;
- break;
-
- case InsigSXPt:
- break;
-
- default: tl_assert2(0, "free_SXTree: unknown SXPt tag");
- }
-
- // Free the SXPt itself.
- VG_(free)(sxpt); sxpt = NULL;
- n_sxpt_frees++;
-}
-
-// Sanity checking: we periodically check the heap XTree with
-// ms_expensive_sanity_check.
-static void sanity_check_XTree(XPt* xpt, XPt* parent)
-{
- tl_assert(xpt != NULL);
-
- // Check back-pointer.
- tl_assert2(xpt->parent == parent,
- "xpt->parent = %p, parent = %p\n", xpt->parent, parent);
-
- // Check children counts look sane.
- tl_assert(xpt->n_children <= xpt->max_children);
-
- // Unfortunately, xpt's size is not necessarily equal to the sum of xpt's
- // children's sizes. See comment at the bottom of get_XCon.
-}
-
-// Sanity checking: we check SXTrees (which are in snapshots) after
-// snapshots are created, before they are deleted, and before they are
-// printed.
-static void sanity_check_SXTree(SXPt* sxpt)
-{
- Int i;
-
- tl_assert(sxpt != NULL);
-
- // Check the sum of any children szBs equals the SXPt's szB. Check the
- // children at the same time.
- switch (sxpt->tag) {
- case SigSXPt: {
- if (sxpt->Sig.n_children > 0) {
- for (i = 0; i < sxpt->Sig.n_children; i++) {
- sanity_check_SXTree(sxpt->Sig.children[i]);
- }
- }
- break;
- }
- case InsigSXPt:
- break; // do nothing
-
- default: tl_assert2(0, "sanity_check_SXTree: unknown SXPt tag");
- }
-}
-
-
-//------------------------------------------------------------//
-//--- XCon Operations ---//
-//------------------------------------------------------------//
-
-// This is the limit on the number of removed alloc-fns that can be in a
-// single XCon.
+// This is the limit on the number of filtered alloc-fns that can be in a
+// single stacktrace.
#define MAX_OVERESTIMATE 50
#define MAX_IPS (MAX_DEPTH + MAX_OVERESTIMATE)
-// Determine if the given IP belongs to a function that should be ignored.
-static Bool fn_should_be_ignored(Addr ip)
-{
- const HChar *buf;
- return
- ( VG_(get_fnname)(ip, &buf) && is_member_fn(ignore_fns, buf)
- ? True : False );
-}
-
-// Get the stack trace for an XCon, filtering out uninteresting entries:
+// filtering out uninteresting entries:
// alloc-fns and entries above alloc-fns, and entries below main-or-below-main.
// Eg: alloc-fn1 / alloc-fn2 / a / b / main / (below main) / c
// becomes: a / b / main
// Nb: it's possible to end up with an empty trace, eg. if 'main' is marked
// as an alloc-fn. This is ok.
static
-Int get_IPs( ThreadId tid, Bool exclude_first_entry, Addr ips[])
+void filter_IPs (Addr* ips, Int n_ips,
+ UInt* top, UInt* n_ips_sel)
{
- Int n_ips, i, n_alloc_fns_removed;
- Int overestimate;
- Bool redo;
+ Int i;
+ Bool top_has_fnname;
+ const HChar *fnname;
- // We ask for a few more IPs than clo_depth suggests we need. Then we
- // remove every entry that is an alloc-fn. Depending on the
- // circumstances, we may need to redo it all, asking for more IPs.
- // Details:
- // - If the original stack trace is smaller than asked-for, redo=False
- // - Else if after filtering we have >= clo_depth IPs, redo=False
- // - Else redo=True
- // In other words, to redo, we'd have to get a stack trace as big as we
- // asked for and remove more than 'overestimate' alloc-fns.
+ *top = 0;
+ *n_ips_sel = n_ips;
- // Main loop.
- redo = True; // Assume this to begin with.
- for (overestimate = 3; redo; overestimate += 6) {
- // This should never happen -- would require MAX_OVERESTIMATE
- // alloc-fns to be removed from the stack trace.
- if (overestimate > MAX_OVERESTIMATE)
- VG_(tool_panic)("get_IPs: ips[] too small, inc. MAX_OVERESTIMATE?");
-
- // Ask for more IPs than clo_depth suggests we need.
- n_ips = VG_(get_StackTrace)( tid, ips, clo_depth + overestimate,
- NULL/*array to dump SP values in*/,
- NULL/*array to dump FP values in*/,
- 0/*first_ip_delta*/ );
- tl_assert(n_ips > 0);
-
- // If the original stack trace is smaller than asked-for, redo=False.
- if (n_ips < clo_depth + overestimate) { redo = False; }
-
- // Filter out alloc fns. If requested, we automatically remove the
- // first entry (which presumably will be something like malloc or
- // __builtin_new that we're sure to filter out) without looking at it,
- // because VG_(get_fnname) is expensive.
- n_alloc_fns_removed = ( exclude_first_entry ? 1 : 0 );
- for (i = n_alloc_fns_removed; i < n_ips; i++) {
- const HChar *buf;
- if (VG_(get_fnname)(ips[i], &buf)) {
- if (is_member_fn(alloc_fns, buf)) {
- n_alloc_fns_removed++;
- } else {
- break;
- }
- }
- }
- // Remove the alloc fns by shuffling the rest down over them.
- n_ips -= n_alloc_fns_removed;
- for (i = 0; i < n_ips; i++) {
- ips[i] = ips[i + n_alloc_fns_removed];
- }
-
- // If after filtering we have >= clo_depth IPs, redo=False
- if (n_ips >= clo_depth) {
- redo = False;
- n_ips = clo_depth; // Ignore any IPs below --depth.
- }
-
- if (redo) {
- n_XCon_redos++;
+ // Advance *top as long as we find alloc functions
+ // PW Nov 2016 xtree work:
+ // old massif code was doing something really strange(?buggy):
+ // 'sliding' a bunch of functions without names by removing an
+ // alloc function 'inside' a stacktrace e.g.
+ // 0x1 0x2 0x3 alloc func1 main
+ // becomes 0x1 0x2 0x3 func1 main
+ for (i = *top; i < n_ips; i++) {
+ top_has_fnname = VG_(get_fnname)(ips[*top], &fnname);
+ if (top_has_fnname && VG_(strIsMemberXA)(alloc_fns, fnname)) {
+ VERB(4, "filtering alloc fn %s\n", fnname);
+ (*top)++;
+ (*n_ips_sel)--;
+ } else {
+ break;
}
}
- return n_ips;
+
+ // filter the whole stacktrace if this allocation has to be ignored.
+ if (*n_ips_sel > 0
+ && top_has_fnname
+ && VG_(strIsMemberXA)(ignore_fns, fnname)) {
+ VERB(4, "ignored allocation from fn %s\n", fnname);
+ *top = n_ips;
+ *n_ips_sel = 0;
+ }
+
+
+ if (!VG_(clo_show_below_main) && *n_ips_sel > 0 ) {
+ Int mbm = VG_(XT_offset_main_or_below_main)(ips, n_ips);
+
+ if (mbm < *top) {
+ // Special case: the first main (or below main) function is an
+ // alloc function.
+ *n_ips_sel = 1;
+ VERB(4, "main/below main: keeping 1 fn\n");
+ } else {
+ *n_ips_sel -= n_ips - mbm - 1;
+ VERB(4, "main/below main: filtering %d\n", n_ips - mbm - 1);
+ }
+ }
+
+ // filter the frames if we have more than clo_depth
+ if (*n_ips_sel > clo_depth) {
+ VERB(4, "filtering IPs above clo_depth\n");
+ *n_ips_sel = clo_depth;
+ }
}
-// Gets an XCon and puts it in the tree. Returns the XCon's bottom-XPt.
-// Unless the allocation should be ignored, in which case we return NULL.
-static XPt* get_XCon( ThreadId tid, Bool exclude_first_entry )
+// Capture a stacktrace, and make an ec of it, without the first entry
+// if exclude_first_entry is True.
+static ExeContext* make_ec(ThreadId tid, Bool exclude_first_entry)
{
static Addr ips[MAX_IPS];
- Int i;
- XPt* xpt = alloc_xpt;
// After this call, the IPs we want are in ips[0]..ips[n_ips-1].
- Int n_ips = get_IPs(tid, exclude_first_entry, ips);
-
- // Should we ignore this allocation? (Nb: n_ips can be zero, eg. if
- // 'main' is marked as an alloc-fn.)
- if (n_ips > 0 && fn_should_be_ignored(ips[0])) {
- return NULL;
- }
-
- // Now do the search/insertion of the XCon.
- for (i = 0; i < n_ips; i++) {
- Addr ip = ips[i];
- Int ch;
- // Look for IP in xpt's children.
- // Linear search, ugh -- about 10% of time for konqueror startup tried
- // caching last result, only hit about 4% for konqueror.
- // Nb: this search hits about 98% of the time for konqueror
- for (ch = 0; True; ch++) {
- if (ch == xpt->n_children) {
- // IP not found in the children.
- // Create and add new child XPt, then stop.
- XPt* new_child_xpt = new_XPt(ip, xpt);
- add_child_xpt(xpt, new_child_xpt);
- xpt = new_child_xpt;
- break;
-
- } else if (ip == xpt->children[ch]->ip) {
- // Found the IP in the children, stop.
- xpt = xpt->children[ch];
- break;
- }
- }
- }
-
- // [Note: several comments refer to this comment. Do not delete it
- // without updating them.]
- //
- // A complication... If all stack traces were well-formed, then the
- // returned xpt would always be a bottom-XPt. As a consequence, an XPt's
- // size would always be equal to the sum of its children's sizes, which
- // is an excellent sanity check.
- //
- // Unfortunately, stack traces occasionally are malformed, ie. truncated.
- // This allows a stack trace to be a sub-trace of another, eg. a/b/c is a
- // sub-trace of a/b/c/d. So we can't assume this xpt is a bottom-XPt;
- // nor can we do sanity check an XPt's size against its children's sizes.
- // This is annoying, but must be dealt with. (Older versions of Massif
- // had this assertion in, and it was reported to fail by real users a
- // couple of times.) Even more annoyingly, I can't come up with a simple
- // test case that exhibit such a malformed stack trace, so I can't
- // regression test it. Sigh.
- //
- // However, we can print a warning, so that if it happens (unexpectedly)
- // in existing regression tests we'll know. Also, it warns users that
- // the output snapshots may not add up the way they might expect.
- //
- //tl_assert(0 == xpt->n_children); // Must be bottom-XPt
- if (0 != xpt->n_children) {
- static Int n_moans = 0;
- if (n_moans < 3) {
- VG_(umsg)(
- "Warning: Malformed stack trace detected. In Massif's output,\n");
- VG_(umsg)(
- " the size of an entry's child entries may not sum up\n");
- VG_(umsg)(
- " to the entry's size as they normally do.\n");
- n_moans++;
- if (3 == n_moans)
- VG_(umsg)(
- " (And Massif now won't warn about this again.)\n");
- }
- }
- return xpt;
+ Int n_ips = VG_(get_StackTrace)( tid, ips, clo_depth + MAX_OVERESTIMATE,
+ NULL/*array to dump SP values in*/,
+ NULL/*array to dump FP values in*/,
+ 0/*first_ip_delta*/ );
+ if (exclude_first_entry && n_ips > 0) {
+ const HChar *fnname;
+ VERB(4, "removing top fn %s from stacktrace\n",
+ VG_(get_fnname)(ips[0], &fnname) ? fnname : "???");
+ return VG_(make_ExeContext_from_StackTrace)(ips+1, n_ips-1);
+ } else
+ return VG_(make_ExeContext_from_StackTrace)(ips, n_ips);
}
-// Update 'szB' of every XPt in the XCon, by percolating upwards.
-static void update_XCon(XPt* xpt, SSizeT space_delta)
+// Create (or update) in heap_xt an xec corresponding to the stacktrace of tid.
+// req_szB is added to the xec (unless ec is fully filtered).
+// Returns the correspding XTree xec.
+// exclude_first_entry is an optimisation: if True, automatically removes
+// the top level IP from the stacktrace. Should be set to True if it is known
+// that this is an alloc fn. The top function presumably will be something like
+// malloc or __builtin_new that we're sure to filter out).
+static Xecu add_heap_xt( ThreadId tid, SizeT req_szB, Bool exclude_first_entry)
+{
+ ExeContext *ec = make_ec(tid, exclude_first_entry);
+
+ if (UNLIKELY(VG_(clo_xtree_memory) == Vg_XTMemory_Full))
+ VG_(XTMemory_Full_alloc)(req_szB, ec);
+ return VG_(XT_add_to_ec) (heap_xt, ec, &req_szB);
+}
+
+// Substract req_szB from the heap_xt where.
+static void sub_heap_xt(Xecu where, SizeT req_szB, Bool exclude_first_entry)
{
tl_assert(clo_heap);
- tl_assert(NULL != xpt);
- if (0 == space_delta)
+ if (0 == req_szB)
return;
- while (xpt != alloc_xpt) {
- if (space_delta < 0) tl_assert(xpt->szB >= -space_delta);
- xpt->szB += space_delta;
- xpt = xpt->parent;
+ VG_(XT_sub_from_xecu) (heap_xt, where, &req_szB);
+ if (UNLIKELY(VG_(clo_xtree_memory) == Vg_XTMemory_Full)) {
+ ExeContext *ec_free = make_ec(VG_(get_running_tid)(),
+ exclude_first_entry);
+ VG_(XTMemory_Full_free)(req_szB,
+ VG_(XT_get_ec_from_xecu)(heap_xt, where),
+ ec_free);
}
- if (space_delta < 0) tl_assert(alloc_xpt->szB >= -space_delta);
- alloc_xpt->szB += space_delta;
}
@@ -999,11 +627,6 @@
// limit again, we again cull and then take them even more slowly, and so
// on.
-// Time is measured either in i or ms or bytes, depending on the --time-unit
-// option. It's a Long because it can exceed 32-bits reasonably easily, and
-// because we need to allow negative values to represent unset times.
-typedef Long Time;
-
#define UNUSED_SNAPSHOT_TIME -333 // A conspicuous negative number.
typedef
@@ -1021,8 +644,8 @@
SizeT heap_szB;
SizeT heap_extra_szB;// Heap slop + admin bytes.
SizeT stacks_szB;
- SXPt* alloc_sxpt; // Heap XTree root, if a detailed snapshot,
- } // otherwise NULL.
+ XTree* xt; // Snapshot of heap_xt, if a detailed snapshot,
+ } // otherwise NULL.
Snapshot;
static UInt next_snapshot_i = 0; // Index of where next snapshot will go.
@@ -1036,7 +659,7 @@
tl_assert(snapshot->heap_extra_szB == 0);
tl_assert(snapshot->heap_szB == 0);
tl_assert(snapshot->stacks_szB == 0);
- tl_assert(snapshot->alloc_sxpt == NULL);
+ tl_assert(snapshot->xt == NULL);
return False;
} else {
tl_assert(snapshot->time != UNUSED_SNAPSHOT_TIME);
@@ -1046,7 +669,7 @@
static Bool is_detailed_snapshot(Snapshot* snapshot)
{
- return (snapshot->alloc_sxpt ? True : False);
+ return (snapshot->xt ? True : False);
}
static Bool is_uncullable_snapshot(Snapshot* snapshot)
@@ -1058,9 +681,8 @@
static void sanity_check_snapshot(Snapshot* snapshot)
{
- if (snapshot->alloc_sxpt) {
- sanity_check_SXTree(snapshot->alloc_sxpt);
- }
+ // Not much we can sanity check.
+ tl_assert(snapshot->xt == NULL || snapshot->kind != Unused);
}
// All the used entries should look used, all the unused ones should be clear.
@@ -1075,7 +697,7 @@
}
}
-// This zeroes all the fields in the snapshot, but does not free the heap
+// This zeroes all the fields in the snapshot, but does not free the xt
// XTree if present. It also does a sanity check unless asked not to; we
// can't sanity check at startup when clearing the initial snapshots because
// they're full of junk.
@@ -1087,20 +709,20 @@
snapshot->heap_extra_szB = 0;
snapshot->heap_szB = 0;
snapshot->stacks_szB = 0;
- snapshot->alloc_sxpt = NULL;
+ snapshot->xt = NULL;
}
-// This zeroes all the fields in the snapshot, and frees the heap XTree if
+// This zeroes all the fields in the snapshot, and frees the heap XTree xt if
// present.
static void delete_snapshot(Snapshot* snapshot)
{
// Nb: if there's an XTree, we free it after calling clear_snapshot,
// because clear_snapshot does a sanity check which includes checking the
// XTree.
- SXPt* tmp_sxpt = snapshot->alloc_sxpt;
+ XTree* tmp_xt = snapshot->xt;
clear_snapshot(snapshot, /*do_sanity_check*/True);
- if (tmp_sxpt) {
- free_SXTree(tmp_sxpt);
+ if (tmp_xt) {
+ VG_(XT_delete)(tmp_xt);
}
}
@@ -1308,10 +930,7 @@
if (clo_heap) {
snapshot->heap_szB = heap_szB;
if (is_detailed) {
- SizeT total_szB = heap_szB + heap_extra_szB + stacks_szB;
- snapshot->alloc_sxpt = dup_XTree(alloc_xpt, total_szB);
- tl_assert( alloc_xpt->szB == heap_szB);
- tl_assert(snapshot->alloc_sxpt->szB == heap_szB);
+ snapshot->xt = VG_(XT_snapshot)(heap_xt);
}
snapshot->heap_extra_szB = heap_extra_szB;
}
@@ -1448,7 +1067,7 @@
static Bool ms_expensive_sanity_check ( void )
{
- sanity_check_XTree(alloc_xpt, /*parent*/NULL);
+ tl_assert(heap_xt);
sanity_check_snapshots_array();
return True;
}
@@ -1458,9 +1077,9 @@
//--- Heap management ---//
//------------------------------------------------------------//
-// Metadata for heap blocks. Each one contains a pointer to a bottom-XPt,
-// which is a foothold into the XCon at which it was allocated. From
-// HP_Chunks, XPt 'space' fields are incremented (at allocation) and
+// Metadata for heap blocks. Each one contains an Xecu,
+// which identifies the XTree ec at which it was allocated. From
+// HP_Chunks, XTree ec 'space' field is incremented (at allocation) and
// decremented (at deallocation).
//
// Nb: first two fields must match core's VgHashNode.
@@ -1470,10 +1089,13 @@
Addr data; // Ptr to actual block
SizeT req_szB; // Size requested
SizeT slop_szB; // Extra bytes given above those requested
- XPt* where; // Where allocated; bottom-XPt
+ Xecu where; // Where allocated; XTree xecu from heap_xt
}
HP_Chunk;
+/* Pool allocator for HP_Chunk. */
+static PoolAlloc *HP_chunk_poolalloc = NULL;
+
static VgHashTable *malloc_list = NULL; // HP_Chunks
static void update_alloc_stats(SSizeT szB_delta)
@@ -1501,28 +1123,25 @@
Bool exclude_first_entry, Bool maybe_snapshot )
{
// Make new HP_Chunk node, add to malloc_list
- HP_Chunk* hc = VG_(malloc)("ms.main.rb.1", sizeof(HP_Chunk));
+ HP_Chunk* hc = VG_(allocEltPA)(HP_chunk_poolalloc);
hc->req_szB = req_szB;
hc->slop_szB = slop_szB;
hc->data = (Addr)p;
- hc->where = NULL;
+ hc->where = 0;
VG_(HT_add_node)(malloc_list, hc);
if (clo_heap) {
VERB(3, "<<< record_block (%lu, %lu)\n", req_szB, slop_szB);
- hc->where = get_XCon( tid, exclude_first_entry );
+ hc->where = add_heap_xt( tid, req_szB, exclude_first_entry);
- if (hc->where) {
+ if (VG_(XT_n_ips_sel)(heap_xt, hc->where) > 0) {
// Update statistics.
n_heap_allocs++;
// Update heap stats.
update_heap_stats(req_szB, clo_heap_admin + slop_szB);
- // Update XTree.
- update_XCon(hc->where, req_szB);
-
// Maybe take a snapshot.
if (maybe_snapshot) {
maybe_take_snapshot(Normal, " alloc");
@@ -1568,7 +1187,7 @@
}
static __inline__
-void unrecord_block ( void* p, Bool maybe_snapshot )
+void unrecord_block ( void* p, Bool maybe_snapshot, Bool exclude_first_entry )
{
// Remove HP_Chunk from malloc_list
HP_Chunk* hc = VG_(HT_remove)(malloc_list, (UWord)p);
@@ -1579,7 +1198,7 @@
if (clo_heap) {
VERB(3, "<<< unrecord_block\n");
- if (hc->where) {
+ if (VG_(XT_n_ips_sel)(heap_xt, hc->where) > 0) {
// Update statistics.
n_heap_frees++;
@@ -1592,7 +1211,7 @@
update_heap_stats(-hc->req_szB, -clo_heap_admin - hc->slop_szB);
// Update XTree.
- update_XCon(hc->where, -hc->req_szB);
+ sub_heap_xt(hc->where, hc->req_szB, exclude_first_entry);
// Maybe take a snapshot.
if (maybe_snapshot) {
@@ -1609,7 +1228,7 @@
}
// Actually free the chunk, and the heap block (if necessary)
- VG_(free)( hc ); hc = NULL;
+ VG_(freeEltPA) (HP_chunk_poolalloc, hc); hc = NULL;
}
// Nb: --ignore-fn is tricky for realloc. If the block's original alloc was
@@ -1618,13 +1237,17 @@
// could end up with negative heap sizes. This isn't a danger if we are
// growing such a block, but for consistency (it also simplifies things) we
// ignore such reallocs as well.
+// PW Nov 2016 xtree work: why can't we just consider that a realloc of an
+// ignored alloc is just a new alloc (i.e. do not remove the old sz from the
+// stats). Then everything would be fine, and a non ignored realloc would be
+// counted properly.
static __inline__
void* realloc_block ( ThreadId tid, void* p_old, SizeT new_req_szB )
{
HP_Chunk* hc;
void* p_new;
SizeT old_req_szB, old_slop_szB, new_slop_szB, new_actual_szB;
- XPt *old_where, *new_where;
+ Xecu old_where;
Bool is_ignored = False;
// Remove the old block
@@ -1640,7 +1263,7 @@
if (clo_heap) {
VERB(3, "<<< realloc_block (%lu)\n", new_req_szB);
- if (hc->where) {
+ if (VG_(XT_n_ips_sel)(heap_xt, hc->where) > 0) {
// Update statistics.
n_heap_reallocs++;
@@ -1682,19 +1305,27 @@
hc->req_szB = new_req_szB;
hc->slop_szB = new_slop_szB;
old_where = hc->where;
- hc->where = NULL;
+ hc->where = 0;
// Update XTree.
if (clo_heap) {
- new_where = get_XCon( tid, /*exclude_first_entry*/True);
- if (!is_ignored && new_where) {
- hc->where = new_where;
- update_XCon(old_where, -old_req_szB);
- update_XCon(new_where, new_req_szB);
+ hc->where = add_heap_xt( tid, new_req_szB,
+ /*exclude_first_entry*/True);
+ if (!is_ignored && VG_(XT_n_ips_sel)(heap_xt, hc->where) > 0) {
+ sub_heap_xt(old_where, old_req_szB, /*exclude_first_entry*/True);
} else {
// The realloc itself is ignored.
is_ignored = True;
+ /* XTREE??? hack to have something compatible with pre
+ m_xtree massif: if the previous alloc/realloc was
+ ignored, and this one is not ignored, then keep the
+ previous where, to continue marking this memory as
+ ignored. */
+ if (VG_(XT_n_ips_sel)(heap_xt, hc->where) > 0
+ && VG_(XT_n_ips_sel)(heap_xt, old_where) == 0)
+ hc->where = old_where;
+
// Update statistics.
n_ignored_heap_reallocs++;
}
@@ -1712,7 +1343,7 @@
if (!is_ignored) {
// Update heap stats.
update_heap_stats(new_req_szB - old_req_szB,
- new_slop_szB - old_slop_szB);
+ new_slop_szB - old_slop_szB);
// Maybe take a snapshot.
maybe_take_snapshot(Normal, "realloc");
@@ -1761,19 +1392,19 @@
static void ms_free ( ThreadId tid __attribute__((unused)), void* p )
{
- unrecord_block(p, /*maybe_snapshot*/True);
+ unrecord_block(p, /*maybe_snapshot*/True, /*exclude_first_entry*/True);
VG_(cli_free)(p);
}
static void ms___builtin_delete ( ThreadId tid, void* p )
{
- unrecord_block(p, /*maybe_snapshot*/True);
+ unrecord_block(p, /*maybe_snapshot*/True, /*exclude_first_entry*/True);
VG_(cli_free)(p);
}
static void ms___builtin_vec_delete ( ThreadId tid, void* p )
{
- unrecord_block(p, /*maybe_snapshot*/True);
+ unrecord_block(p, /*maybe_snapshot*/True, /*exclude_first_entry*/True);
VG_(cli_free)(p);
}
@@ -1817,11 +1448,13 @@
tl_assert(VG_IS_PAGE_ALIGNED(len));
tl_assert(len >= VKI_PAGE_SIZE);
// Unrecord the first page. This might be the peak, so do a snapshot.
- unrecord_block((void*)a, /*maybe_snapshot*/True);
+ unrecord_block((void*)a, /*maybe_snapshot*/True,
+ /*exclude_first_entry*/False);
a += VKI_PAGE_SIZE;
// Then unrecord the remaining pages, but without snapshots.
for (end = a + len - VKI_PAGE_SIZE; a < end; a += VKI_PAGE_SIZE) {
- unrecord_block((void*)a, /*maybe_snapshot*/False);
+ unrecord_block((void*)a, /*maybe_snapshot*/False,
+ /*exclude_first_entry*/False);
}
}
@@ -1953,17 +1586,20 @@
static void print_monitor_help ( void )
{
- VG_(gdb_printf) ("\n");
- VG_(gdb_printf) ("massif monitor commands:\n");
- VG_(gdb_printf) (" snapshot [<filename>]\n");
- VG_(gdb_printf) (" detailed_snapshot [<filename>]\n");
- VG_(gdb_printf) (" takes a snapshot (or a detailed snapshot)\n");
- VG_(gdb_printf) (" and saves it in <filename>\n");
- VG_(gdb_printf) (" default <filename> is massif.vgdb.out\n");
- VG_(gdb_printf) (" all_snapshots [<filename>]\n");
- VG_(gdb_printf) (" saves all snapshot(s) taken so far in <filename>\n");
- VG_(gdb_printf) (" default <filename> is massif.vgdb.out\n");
- VG_(gdb_printf) ("\n");
+ VG_(gdb_printf) (
+"\n"
+"massif monitor commands:\n"
+" snapshot [<filename>]\n"
+" detailed_snapshot [<filename>]\n"
+" takes a snapshot (or a detailed snapshot)\n"
+" and saves it in <filename>\n"
+" default <filename> is massif.vgdb.out\n"
+" all_snapshots [<filename>]\n"
+" saves all snapshot(s) taken so far in <filename>\n"
+" default <filename> is massif.vgdb.out\n"
+" xtmemory [<filename>]\n"
+" dump xtree memory profile in <filename> (default xtmemory.kcg)\n"
+"\n");
}
@@ -1985,14 +1621,14 @@
void* p = (void*)argv[1];
SizeT newSizeB = argv[3];
- unrecord_block(p, /*maybe_snapshot*/True);
+ unrecord_block(p, /*maybe_snapshot*/True, /*exclude_first_entry*/False);
record_block(tid, p, newSizeB, /*slop_szB*/0,
/*exclude_first_entry*/False, /*maybe_snapshot*/True);
return True;
}
case VG_USERREQ__FREELIKE_BLOCK: {
void* p = (void*)argv[1];
- unrecord_block(p, /*maybe_snapshot*/True);
+ unrecord_block(p, /*maybe_snapshot*/True, /*exclude_first_entry*/False);
*ret = 0;
return True;
}
@@ -2107,157 +1743,25 @@
//--- Writing snapshots ---//
//------------------------------------------------------------//
-#define FP(format, args...) ({ VG_(fprintf)(fp, format, ##args); })
-
-static void pp_snapshot_SXPt(VgFile *fp, SXPt* sxpt, Int depth,
- HChar* depth_str, Int depth_str_len,
- SizeT snapshot_heap_szB, SizeT snapshot_total_szB)
+static void pp_snapshot(MsFile *fp, Snapshot* snapshot, Int snapshot_n)
{
- Int i, j, n_insig_children_sxpts;
- SXPt* child = NULL;
+ const Massif_Header header = (Massif_Header) {
+ .snapshot_n = snapshot_n,
+ .time = snapshot->time,
+ .sz_B = snapshot->heap_szB,
+ .extra_B = snapshot->heap_extra_szB,
+ .stacks_B = snapshot->stacks_szB,
+ .detailed = is_detailed_snapshot(snapshot),
+ .peak = Peak == snapshot->kind,
+ .top_node_desc = clo_pages_as_heap ?
+ "(page allocation syscalls) mmap/mremap/brk, --alloc-fns, etc."
+ : "(heap allocation functions) malloc/new/new[], --alloc-fns, etc.",
+ .sig_threshold = clo_threshold
+ };
- // Used for printing function names. Is made static to keep it out
- // of the stack frame -- this function is recursive. Obviously this
- // now means its contents are trashed across the recursive call.
- const HChar* ip_desc;
-
- switch (sxpt->tag) {
- case SigSXPt:
- // Print the SXPt itself.
- if (0 == depth) {
- if (clo_heap) {
- ip_desc =
- ( clo_pages_as_heap
- ? "(page allocation syscalls) mmap/mremap/brk, --alloc-fns, etc."
- : "(heap allocation functions) malloc/new/new[], --alloc-fns, etc."
- );
- } else {
- // XXX: --alloc-fns?
-
- // Nick thinks this case cannot happen. ip_desc would be
- // conceptually uninitialised here. Therefore:
- tl_assert2(0, "pp_snapshot_SXPt: unexpected");
- }
- } else {
- // If it's main-or-below-main, we (if appropriate) ignore everything
- // below it by pretending it has no children.
- if ( ! VG_(clo_show_below_main) ) {
- Vg_FnNameKind kind = VG_(get_fnname_kind_from_IP)(sxpt->Sig.ip);
- if (Vg_FnNameMain == kind || Vg_FnNameBelowMain == kind) {
- sxpt->Sig.n_children = 0;
- }
- }
-
- // We need the -1 to get the line number right, But I'm not sure why.
- ip_desc = VG_(describe_IP)(sxpt->Sig.ip-1, NULL);
- }
-
- // Do the non-ip_desc part first...
- FP("%sn%u: %lu ", depth_str, sxpt->Sig.n_children, sxpt->szB);
-
- // For ip_descs beginning with "0xABCD...:" addresses, we first
- // measure the length of the "0xabcd: " address at the start of the
- // ip_desc.
- j = 0;
- if ('0' == ip_desc[0] && 'x' == ip_desc[1]) {
- j = 2;
- while (True) {
- if (ip_desc[j]) {
- if (':' == ip_desc[j]) break;
- j++;
- } else {
- tl_assert2(0, "ip_desc has unexpected form: %s\n", ip_desc);
- }
- }
- }
- // It used to be that ip_desc was truncated at the end.
- // But there does not seem to be a good reason for that. Besides,
- // the string was truncated at the right, which is less than ideal.
- // Truncation at the beginning of the string would have been preferable.
- // Think several nested namespaces in C++....
- // Anyhow, we spit out the full-length string now.
- FP("%s\n", ip_desc);
-
- // Indent.
- tl_assert(depth+1 < depth_str_len-1); // -1 for end NUL char
- depth_str[depth+0] = ' ';
- depth_str[depth+1] = '\0';
-
- // Sort SXPt's children by szB (reverse order: biggest to smallest).
- // Nb: we sort them here, rather than earlier (eg. in dup_XTree), for
- // two reasons. First, if we do it during dup_XTree, it can get
- // expensive (eg. 15% of execution time for konqueror
- // startup/shutdown). Second, this way we get the Insig SXPt (if one
- // is present) in its sorted position, not at the end.
- VG_(ssort)(sxpt->Sig.children, sxpt->Sig.n_children, sizeof(SXPt*),
- SXPt_revcmp_szB);
-
- // Print the SXPt's children. They should already be in sorted order.
- n_insig_children_sxpts = 0;
- for (i = 0; i < sxpt->Sig.n_children; i++) {
- child = sxpt->Sig.children[i];
-
- if (InsigSXPt == child->tag)
- n_insig_children_sxpts++;
-
- // Ok, print the child. NB: contents of ip_desc will be
- // trashed by this recursive call. Doesn't matter currently,
- // but worth noting.
- pp_snapshot_SXPt(fp, child, depth+1, depth_str, depth_str_len,
- snapshot_heap_szB, snapshot_total_szB);
- }
-
- // Unindent.
- depth_str[depth+0] = '\0';
- depth_str[depth+1] = '\0';
-
- // There should be 0 or 1 Insig children SXPts.
- tl_assert(n_insig_children_sxpts <= 1);
- break;
-
- case InsigSXPt: {
- const HChar* s = ( 1 == sxpt->Insig.n_xpts ? "," : "s, all" );
- FP("%sn0: %lu in %d place%s below massif's threshold (%.2f%%)\n",
- depth_str, sxpt->szB, sxpt->Insig.n_xpts, s, clo_threshold);
- break;
- }
-
- default:
- tl_assert2(0, "pp_snapshot_SXPt: unrecognised SXPt tag");
- }
-}
-
-static void pp_snapshot(VgFile *fp, Snapshot* snapshot, Int snapshot_n)
-{
sanity_check_snapshot(snapshot);
- FP("#-----------\n");
- FP("snapshot=%d\n", snapshot_n);
- FP("#-----------\n");
- FP("time=%lld\n", snapshot->time);
- FP("mem_heap_B=%lu\n", snapshot->heap_szB);
- FP("mem_heap_extra_B=%lu\n", snapshot->heap_extra_szB);
- FP("mem_stacks_B=%lu\n", snapshot->stacks_szB);
-
- if (is_detailed_snapshot(snapshot)) {
- // Detailed snapshot -- print heap tree.
- Int depth_str_len = clo_depth + 3;
- HChar* depth_str = VG_(malloc)("ms.main.pps.1",
- sizeof(HChar) * depth_str_len);
- SizeT snapshot_total_szB =
- snapshot->heap_szB + snapshot->heap_extra_szB + snapshot->stacks_szB;
- depth_str[0] = '\0'; // Initialise depth_str to "".
-
- FP("heap_tree=%s\n", ( Peak == snapshot->kind ? "peak" : "detailed" ));
- pp_snapshot_SXPt(fp, snapshot->alloc_sxpt, 0, depth_str,
- depth_str_len, snapshot->heap_szB,
- snapshot_total_szB);
-
- VG_(free)(depth_str);
-
- } else {
- FP("heap_tree=empty\n");
- }
+ VG_(XT_massif_print)(fp, snapshot->xt, &header, alloc_szB);
}
static void write_snapshots_to_file(const HChar* massif_out_file,
@@ -2265,46 +1769,20 @@
Int nr_elements)
{
Int i;
- VgFile *fp;
+ MsFile *fp;
- fp = VG_(fopen)(massif_out_file, VKI_O_CREAT|VKI_O_TRUNC|VKI_O_WRONLY,
- VKI_S_IRUSR|VKI_S_IWUSR);
- if (fp == NULL) {
- // If the file can't be opened for whatever reason (conflict
- // between multiple cachegrinded processes?), give up now.
- VG_(umsg)("error: can't open output file '%s'\n", massif_out_file );
- VG_(umsg)(" ... so profiling results will be missing.\n");
- return;
- }
-
- // Print massif-specific options that were used.
- // XXX: is it worth having a "desc:" line? Could just call it "options:"
- // -- this file format isn't as generic as Cachegrind's, so the
- // implied genericity of "desc:" is bogus.
- FP("desc:");
- for (i = 0; i < VG_(sizeXA)(args_for_massif); i++) {
- HChar* arg = *(HChar**)VG_(indexXA)(args_for_massif, i);
- FP(" %s", arg);
- }
- if (0 == i) FP(" (none)");
- FP("\n");
-
- // Print "cmd:" line.
- FP("cmd: ");
- FP("%s", VG_(args_the_exename));
- for (i = 0; i < VG_(sizeXA)( VG_(args_for_client) ); i++) {
- HChar* arg = * (HChar**) VG_(indexXA)( VG_(args_for_client), i );
- FP(" %s", arg);
- }
- FP("\n");
-
- FP("time_unit: %s\n", TimeUnit_to_string(clo_time_unit));
+ fp = VG_(XT_massif_open)(massif_out_file,
+ NULL,
+ args_for_massif,
+ TimeUnit_to_string(clo_time_unit));
+ if (fp == NULL)
+ return; // Error reported by VG_(XT_massif_open)
for (i = 0; i < nr_elements; i++) {
Snapshot* snapshot = & snapshots_array[i];
pp_snapshot(fp, snapshot, i); // Detailed snapshot!
}
- VG_(fclose) (fp);
+ VG_(XT_massif_close) (fp);
}
static void write_snapshots_array_to_file(void)
@@ -2355,6 +1833,26 @@
snapshots, next_snapshot_i);
}
+static void xtmemory_report_next_block(XT_Allocs* xta, ExeContext** ec_alloc)
+{
+ const HP_Chunk* hc = VG_(HT_Next)(malloc_list);
+ if (hc) {
+ xta->nbytes = hc->req_szB;
+ xta->nblocks = 1;
+ *ec_alloc = VG_(XT_get_ec_from_xecu)(heap_xt, hc->where);
+ } else
+ xta->nblocks = 0;
+}
+static void ms_xtmemory_report ( const HChar* filename, Bool fini )
+{
+ // Make xtmemory_report_next_block ready to be called.
+ VG_(HT_ResetIter)(malloc_list);
+ VG_(XTMemory_report)(filename, fini, xtmemory_report_next_block,
+ VG_(XT_filter_maybe_below_main));
+ /* As massif already filters one top function, use as filter
+ VG_(XT_filter_maybe_below_main). */
+}
+
static Bool handle_gdb_monitor_command (ThreadId tid, HChar *req)
{
HChar* wcmd;
@@ -2364,7 +1862,8 @@
VG_(strcpy) (s, req);
wcmd = VG_(strtok_r) (s, " ", &ssaveptr);
- switch (VG_(keyword_id) ("help snapshot detailed_snapshot all_snapshots",
+ switch (VG_(keyword_id) ("help snapshot detailed_snapshot all_snapshots"
+ " xtmemory",
wcmd, kwd_report_duplicated_matches)) {
case -2: /* multiple matches */
return True;
@@ -2391,6 +1890,12 @@
handle_all_snapshots_monitor_command (filename);
return True;
}
+ case 4: { /* xtmemory */
+ HChar* filename;
+ filename = VG_(strtok_r) (NULL, " ", &ssaveptr);
+ ms_xtmemory_report (filename, False);
+ return True;
+ }
default:
tl_assert(0);
return False;
@@ -2409,36 +1914,26 @@
STATS("ignored heap frees: %u\n", n_ignored_heap_frees);
STATS("ignored heap reallocs: %u\n", n_ignored_heap_reallocs);
STATS("stack allocs: %u\n", n_stack_allocs);
- STATS("stack frees: %u\n", n_stack_frees);
- STATS("XPts: %u\n", n_xpts);
- STATS("top-XPts: %u (%u%%)\n",
- alloc_xpt->n_children,
- ( n_xpts ? alloc_xpt->n_children * 100 / n_xpts : 0));
- STATS("XPt init expansions: %u\n", n_xpt_init_expansions);
- STATS("XPt later expansions: %u\n", n_xpt_later_expansions);
- STATS("SXPt allocs: %u\n", n_sxpt_allocs);
- STATS("SXPt frees: %u\n", n_sxpt_frees);
STATS("skipped snapshots: %u\n", n_skipped_snapshots);
STATS("real snapshots: %u\n", n_real_snapshots);
STATS("detailed snapshots: %u\n", n_detailed_snapshots);
STATS("peak snapshots: %u\n", n_peak_snapshots);
STATS("cullings: %u\n", n_cullings);
- STATS("XCon redos: %u\n", n_XCon_redos);
#undef STATS
}
+
//------------------------------------------------------------//
//--- Finalisation ---//
//------------------------------------------------------------//
static void ms_fini(Int exit_status)
{
+ ms_xtmemory_report(VG_(clo_xtree_memory_file), True);
+
// Output.
write_snapshots_array_to_file();
- // Stats
- tl_assert(n_xpts > 0); // always have alloc_xpt
-
if (VG_(clo_stats))
ms_print_stats();
}
@@ -2452,8 +1947,12 @@
{
Int i;
HChar* LD_PRELOAD_val;
- HChar* s;
- HChar* s2;
+
+ /* We will record execontext up to clo_depth + overestimate and
+ we will store this as ec => we need to increase the backtrace size
+ if smaller than what we will store. */
+ if (VG_(clo_backtrace_size) < clo_depth + MAX_OVERESTIMATE)
+ VG_(clo_backtrace_size) = clo_depth + MAX_OVERESTIMATE;
// Check options.
if (clo_pages_as_heap) {
@@ -2468,35 +1967,42 @@
// If --pages-as-heap=yes we don't want malloc replacement to occur. So we
// disable vgpreload_massif-$PLATFORM.so by removing it from LD_PRELOAD (or
- // platform-equivalent). We replace it entirely with spaces because then
- // the linker doesn't complain (it does complain if we just change the name
- // to a bogus file). This is a bit of a hack, but LD_PRELOAD is setup well
- // before tool initialisation, so this seems the best way to do it.
+ // platform-equivalent). This is a bit of a hack, but LD_PRELOAD is setup
+ // well before tool initialisation, so this seems the best way to do it.
if (clo_pages_as_heap) {
+ HChar* s1;
+ HChar* s2;
+
clo_heap_admin = 0; // No heap admin on pages.
LD_PRELOAD_val = VG_(getenv)( VG_(LD_PRELOAD_var_name) );
tl_assert(LD_PRELOAD_val);
+ VERB(2, "clo_pages_as_heap orig LD_PRELOAD '%s'\n", LD_PRELOAD_val);
+
// Make sure the vgpreload_core-$PLATFORM entry is there, for sanity.
- s2 = VG_(strstr)(LD_PRELOAD_val, "vgpreload_core");
- tl_assert(s2);
+ s1 = VG_(strstr)(LD_PRELOAD_val, "vgpreload_core");
+ tl_assert(s1);
// Now find the vgpreload_massif-$PLATFORM entry.
- s2 = VG_(strstr)(LD_PRELOAD_val, "vgpreload_massif");
- tl_assert(s2);
+ s1 = VG_(strstr)(LD_PRELOAD_val, "vgpreload_massif");
+ tl_assert(s1);
+ s2 = s1;
- // Blank out everything to the previous ':', which must be there because
+ // Position s1 on the previous ':', which must be there because
// of the preceding vgpreload_core-$PLATFORM entry.
- for (s = s2; *s != ':'; s--) {
- *s = ' ';
- }
+ for (; *s1 != ':'; s1--)
+ ;
- // Blank out everything to the end of the entry, which will be '\0' if
- // LD_PRELOAD was empty before Valgrind started, or ':' otherwise.
- for (s = s2; *s != ':' && *s != '\0'; s++) {
- *s = ' ';
- }
+ // Position s2 on the next ':' or \0
+ for (; *s2 != ':' && *s2 != '\0'; s2++)
+ ;
+
+ // Move all characters from s2 to s1
+ while ((*s1++ = *s2++))
+ ;
+
+ VERB(2, "clo_pages_as_heap cleaned LD_PRELOAD '%s'\n", LD_PRELOAD_val);
}
// Print alloc-fns and ignore-fns, if necessary.
@@ -2545,6 +2051,13 @@
clear_snapshot( & snapshots[i], /*do_sanity_check*/False );
}
sanity_check_snapshots_array();
+
+ if (VG_(clo_xtree_memory) == Vg_XTMemory_Full)
+ // Activate full xtree memory profiling.
+ // As massif already filters one top function, use as filter
+ // VG_(XT_filter_maybe_below_main).
+ VG_(XTMemory_Full_init)(VG_(XT_filter_maybe_below_main));
+
}
static void ms_pre_clo_init(void)
@@ -2553,7 +2066,7 @@
VG_(details_version) (NULL);
VG_(details_description) ("a heap profiler");
VG_(details_copyright_author)(
- "Copyright (C) 2003-2015, and GNU GPL'd, by Nicholas Nethercote");
+ "Copyright (C) 2003-2017, and GNU GPL'd, by Nicholas Nethercote");
VG_(details_bug_reports_to) (VG_BUGS_TO);
VG_(details_avg_translation_sizeB) ( 330 );
@@ -2590,10 +2103,21 @@
0 );
// HP_Chunks.
+ HP_chunk_poolalloc = VG_(newPA)
+ (sizeof(HP_Chunk),
+ 1000,
+ VG_(malloc),
+ "massif MC_Chunk pool",
+ VG_(free));
malloc_list = VG_(HT_construct)( "Massif's malloc list" );
- // Dummy node at top of the context structure.
- alloc_xpt = new_XPt(/*ip*/0, /*parent*/NULL);
+ // Heap XTree
+ heap_xt = VG_(XT_create)(VG_(malloc),
+ "ms.xtrees",
+ VG_(free),
+ sizeof(SizeT),
+ init_szB, add_szB, sub_szB,
+ filter_IPs);
// Initialise alloc_fns and ignore_fns.
init_alloc_fns();
diff --git a/massif/ms_print.in b/massif/ms_print.in
index e6fae89..565fd65 100755
--- a/massif/ms_print.in
+++ b/massif/ms_print.in
@@ -7,7 +7,7 @@
# This file is part of Massif, a Valgrind tool for profiling memory
# usage of programs.
#
-# Copyright (C) 2007-2015 Nicholas Nethercote
+# Copyright (C) 2007-2017 Nicholas Nethercote
# njn@valgrind.org
#
# This program is free software; you can redistribute it and/or
@@ -76,7 +76,7 @@
--x=<4..1000> graph width, in columns [72]
--y=<4..1000> graph height, in rows [20]
- ms_print is Copyright (C) 2007-2015 Nicholas Nethercote.
+ ms_print is Copyright (C) 2007-2017 Nicholas Nethercote.
and licensed under the GNU General Public License, version 2.
Bug reports, feedback, admiration, abuse, etc, to: njn\@valgrind.org.
diff --git a/massif/tests/Makefile.in b/massif/tests/Makefile.in
index de05a43..122addd 100644
--- a/massif/tests/Makefile.in
+++ b/massif/tests/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -331,6 +331,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -501,6 +502,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -511,6 +513,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -585,8 +588,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -631,7 +632,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/massif/tests/alloc-fns-B.post.exp b/massif/tests/alloc-fns-B.post.exp
index 76baa28..c74a623 100644
--- a/massif/tests/alloc-fns-B.post.exp
+++ b/massif/tests/alloc-fns-B.post.exp
@@ -55,6 +55,10 @@
| |
| ->11.11% (400B) 0x........: main (alloc-fns.c:27)
|
+->11.11% (400B) 0x........: b2 (alloc-fns.c:10)
+| ->11.11% (400B) 0x........: b1 (alloc-fns.c:11)
+| ->11.11% (400B) 0x........: main (alloc-fns.c:28)
+|
->11.11% (400B) 0x........: c1 (alloc-fns.c:16)
| ->11.11% (400B) 0x........: main (alloc-fns.c:29)
|
@@ -65,8 +69,4 @@
->11.11% (400B) 0x........: main (alloc-fns.c:32)
|
->11.11% (400B) 0x........: main (alloc-fns.c:33)
-|
-->11.11% (400B) 0x........: b2 (alloc-fns.c:10)
- ->11.11% (400B) 0x........: b1 (alloc-fns.c:11)
- ->11.11% (400B) 0x........: main (alloc-fns.c:28)
-
+
diff --git a/massif/tests/culling1.stderr.exp b/massif/tests/culling1.stderr.exp
index a4a91e2..19858ff 100644
--- a/massif/tests/culling1.stderr.exp
+++ b/massif/tests/culling1.stderr.exp
@@ -433,16 +433,8 @@
Massif: ignored heap frees: ...
Massif: ignored heap reallocs: ...
Massif: stack allocs: 0
-Massif: stack frees: 0
-Massif: XPts: ...
-Massif: top-XPts: ...
-Massif: XPt init expansions: ...
-Massif: XPt later expansions: ...
-Massif: SXPt allocs: ...
-Massif: SXPt frees: ...
Massif: skipped snapshots: 51
Massif: real snapshots: 150
Massif: detailed snapshots: 15
Massif: peak snapshots: 0
Massif: cullings: 2
-Massif: XCon redos: ...
diff --git a/massif/tests/culling2.stderr.exp b/massif/tests/culling2.stderr.exp
index b5fdf36..0454d15 100644
--- a/massif/tests/culling2.stderr.exp
+++ b/massif/tests/culling2.stderr.exp
@@ -536,16 +536,8 @@
Massif: ignored heap frees: ...
Massif: ignored heap reallocs: ...
Massif: stack allocs: 0
-Massif: stack frees: 0
-Massif: XPts: ...
-Massif: top-XPts: ...
-Massif: XPt init expansions: ...
-Massif: XPt later expansions: ...
-Massif: SXPt allocs: ...
-Massif: SXPt frees: ...
Massif: skipped snapshots: 1
Massif: real snapshots: 200
Massif: detailed snapshots: 20
Massif: peak snapshots: 0
Massif: cullings: 3
-Massif: XCon redos: ...
diff --git a/massif/tests/deep-B.stderr.exp b/massif/tests/deep-B.stderr.exp
index e4b20e8..74187be 100644
--- a/massif/tests/deep-B.stderr.exp
+++ b/massif/tests/deep-B.stderr.exp
@@ -45,16 +45,8 @@
Massif: ignored heap frees: ...
Massif: ignored heap reallocs: ...
Massif: stack allocs: 0
-Massif: stack frees: 0
-Massif: XPts: ...
-Massif: top-XPts: ...
-Massif: XPt init expansions: ...
-Massif: XPt later expansions: ...
-Massif: SXPt allocs: ...
-Massif: SXPt frees: ...
Massif: skipped snapshots: 0
Massif: real snapshots: 11
Massif: detailed snapshots: 1
Massif: peak snapshots: 0
Massif: cullings: 0
-Massif: XCon redos: ...
diff --git a/massif/tests/deep-C.stderr.exp b/massif/tests/deep-C.stderr.exp
index 3243ca6..e1b7295 100644
--- a/massif/tests/deep-C.stderr.exp
+++ b/massif/tests/deep-C.stderr.exp
@@ -48,16 +48,8 @@
Massif: ignored heap frees: ...
Massif: ignored heap reallocs: ...
Massif: stack allocs: 0
-Massif: stack frees: 0
-Massif: XPts: ...
-Massif: top-XPts: ...
-Massif: XPt init expansions: ...
-Massif: XPt later expansions: ...
-Massif: SXPt allocs: ...
-Massif: SXPt frees: ...
Massif: skipped snapshots: 0
Massif: real snapshots: 11
Massif: detailed snapshots: 1
Massif: peak snapshots: 0
Massif: cullings: 0
-Massif: XCon redos: ...
diff --git a/massif/tests/long-names.post.exp b/massif/tests/long-names.post.exp
index d7015e8..7a7ab9c 100644
--- a/massif/tests/long-names.post.exp
+++ b/massif/tests/long-names.post.exp
@@ -40,11 +40,11 @@
2 4,000 4,000 4,000 0 0
100.00% (4,000B) (heap allocation functions) malloc/new/new[], --alloc-fns, etc.
->100.00% (4,000B) 0x........: abcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghij (long-names.c:61)
- ->50.00% (2,000B) 0x........: main (long-names.c:68)
- |
->50.00% (2,000B) 0x........: abcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghijabcdefghijABCDEFGHIJabcdefghijABCDEFGHIJabcdefghij (long-names.c:62)
- ->50.00% (2,000B) 0x........: main (long-names.c:68)
-
+ | ->50.00% (2,000B) 0x........: main (long-names.c:68)
+ |
+ ->50.00% (2,000B) 0x........: main (long-names.c:68)
+
--------------------------------------------------------------------------------
n time(B) total(B) useful-heap(B) extra-heap(B) stacks(B)
--------------------------------------------------------------------------------
diff --git a/massif/tests/overloaded-new.cpp b/massif/tests/overloaded-new.cpp
index 6c61d8e..8fb8707 100644
--- a/massif/tests/overloaded-new.cpp
+++ b/massif/tests/overloaded-new.cpp
@@ -14,32 +14,32 @@
int array[1000];
} s;
-__attribute__((noinline)) void* operator new (std::size_t n) throw (std::bad_alloc)
+__attribute__((noinline)) void* operator new (std::size_t n)
{
return malloc(n);
}
-__attribute__((noinline)) void* operator new (std::size_t n, std::nothrow_t const &) throw ()
+__attribute__((noinline)) void* operator new (std::size_t n, std::nothrow_t const &)
{
return malloc(n);
}
-__attribute__((noinline)) void* operator new[] (std::size_t n) throw (std::bad_alloc)
+__attribute__((noinline)) void* operator new[] (std::size_t n)
{
return malloc(n);
}
-__attribute__((noinline)) void* operator new[] (std::size_t n, std::nothrow_t const &) throw ()
+__attribute__((noinline)) void* operator new[] (std::size_t n, std::nothrow_t const &)
{
return malloc(n);
}
-__attribute__((noinline)) void operator delete (void* p) throw()
+__attribute__((noinline)) void operator delete (void* p)
{
return free(p);
}
-__attribute__((noinline)) void operator delete[] (void* p) throw()
+__attribute__((noinline)) void operator delete[] (void* p)
{
return free(p);
}
diff --git a/massif/tests/peak2.stderr.exp b/massif/tests/peak2.stderr.exp
index b5f190c..78d37b6 100644
--- a/massif/tests/peak2.stderr.exp
+++ b/massif/tests/peak2.stderr.exp
@@ -103,16 +103,8 @@
Massif: ignored heap frees: ...
Massif: ignored heap reallocs: ...
Massif: stack allocs: 0
-Massif: stack frees: 0
-Massif: XPts: ...
-Massif: top-XPts: ...
-Massif: XPt init expansions: ...
-Massif: XPt later expansions: ...
-Massif: SXPt allocs: ...
-Massif: SXPt frees: ...
Massif: skipped snapshots: 0
Massif: real snapshots: 76
Massif: detailed snapshots: 15
Massif: peak snapshots: 15
Massif: cullings: 0
-Massif: XCon redos: ...
diff --git a/massif/tests/realloc.stderr.exp b/massif/tests/realloc.stderr.exp
index 2df136d..4ed52b2 100644
--- a/massif/tests/realloc.stderr.exp
+++ b/massif/tests/realloc.stderr.exp
@@ -35,16 +35,8 @@
Massif: ignored heap frees: ...
Massif: ignored heap reallocs: ...
Massif: stack allocs: 0
-Massif: stack frees: 0
-Massif: XPts: ...
-Massif: top-XPts: ...
-Massif: XPt init expansions: ...
-Massif: XPt later expansions: ...
-Massif: SXPt allocs: ...
-Massif: SXPt frees: ...
Massif: skipped snapshots: 0
Massif: real snapshots: 8
Massif: detailed snapshots: 2
Massif: peak snapshots: 2
Massif: cullings: 0
-Massif: XCon redos: ...
diff --git a/memcheck/Makefile.in b/memcheck/Makefile.in
index 6bb77ae..7958f48 100644
--- a/memcheck/Makefile.in
+++ b/memcheck/Makefile.in
@@ -357,6 +357,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -528,6 +529,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -538,6 +540,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -612,8 +615,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -658,7 +659,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
@@ -736,9 +736,6 @@
-static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \
@FLAG_M64@
-TOOL_LDFLAGS_TILEGX_LINUX = \
- $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-
TOOL_LDFLAGS_X86_SOLARIS = \
$(TOOL_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
@@ -793,9 +790,6 @@
LIBREPLACEMALLOC_MIPS64_LINUX = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a
-LIBREPLACEMALLOC_TILEGX_LINUX = \
- $(top_builddir)/coregrind/libreplacemalloc_toolpreload-tilegx-linux.a
-
LIBREPLACEMALLOC_X86_SOLARIS = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-solaris.a
@@ -858,11 +852,6 @@
$(LIBREPLACEMALLOC_MIPS64_LINUX) \
-Wl,--no-whole-archive
-LIBREPLACEMALLOC_LDFLAGS_TILEGX_LINUX = \
- -Wl,--whole-archive \
- $(LIBREPLACEMALLOC_TILEGX_LINUX) \
- -Wl,--no-whole-archive
-
LIBREPLACEMALLOC_LDFLAGS_X86_SOLARIS = \
-Wl,--whole-archive \
$(LIBREPLACEMALLOC_X86_SOLARIS) \
diff --git a/memcheck/docs/mc-manual.xml b/memcheck/docs/mc-manual.xml
index 0fdd266..39538b5 100644
--- a/memcheck/docs/mc-manual.xml
+++ b/memcheck/docs/mc-manual.xml
@@ -57,8 +57,12 @@
<para>Problems like these can be difficult to find by other means,
often remaining undetected for long periods, then causing occasional,
-difficult-to-diagnose crashes.</para>
+ difficult-to-diagnose crashes.</para>
+<para>Memcheck also provides <xref linkend="manual-core.xtree"/> memory
+ profiling using the command line
+ option <computeroutput>--xtree-memory</computeroutput> and the monitor command
+ <computeroutput>xtmemory</computeroutput>.</para>
</sect1>
@@ -876,6 +880,58 @@
<para> Note that <option>--show-possibly-lost=no</option> has no effect
if <option>--show-reachable=yes</option> is specified.</para>
</varlistentry>
+
+ <varlistentry id="opt.xtree-leak" xreflabel="--xtree-leak">
+ <term>
+ <option><![CDATA[--xtree-leak=<no|yes> [no] ]]></option>
+ </term>
+ <listitem>
+ <para>If set to yes, the results for the leak search done at exit will be
+ output in a 'Callgrind Format' execution tree file. Note that this
+ automatically sets the option <option>--leak-check=full</option>.
+ The produced file
+ will contain the following events:</para>
+ <itemizedlist>
+ <listitem><para><option>RB</option> : Reachable Bytes</para></listitem>
+ <listitem><para><option>PB</option> : Possibly lost Bytes</para></listitem>
+ <listitem><para><option>IB</option> : Indirectly lost Bytes</para></listitem>
+ <listitem><para><option>DB</option> : Definitely lost Bytes (direct plus indirect)</para></listitem>
+ <listitem><para><option>DIB</option> : Definitely Indirectly lost Bytes (subset of DB)</para></listitem>
+ <listitem><para><option>RBk</option> : reachable Blocks</para></listitem>
+ <listitem><para><option>PBk</option> : Possibly lost Blocks</para></listitem>
+ <listitem><para><option>IBk</option> : Indirectly lost Blocks</para></listitem>
+ <listitem><para><option>DBk</option> : Definitely lost Blocks</para></listitem>
+ </itemizedlist>
+
+ <para>The increase or decrease for all events above will also be output in
+ the file to provide the delta (increase or decreaseà between 2
+ successive leak searches. For example, <option>iRB</option> is the
+ increase of the <option>RB</option> event, <option>dPBk</option> is the
+ decrease of <option>PBk</option> event. The values for the increase and
+ decrease events will be zero for the first leak search done.</para>
+
+ <para>See <xref linkend="manual-core.xtree"/> for a detailed explanation
+ about execution trees.</para>
+ </listitem>
+ </varlistentry>
+
+ <varlistentry id="opt.xtree-leak-file" xreflabel="--xtree-leak-file">
+ <term>
+ <option><![CDATA[--xtree-leak-file=<filename> [default:
+ xtleak.kcg.%p] ]]></option>
+ </term>
+ <listitem>
+ <para>Specifies that Valgrind should produce the xtree leak
+ report in the specified file. Any <option>%p</option>,
+ <option>%q</option> or <option>%n</option> sequences appearing in
+ the filename are expanded
+ in exactly the same way as they are for <option>--log-file</option>.
+ See the description of <xref linkend="opt.log-file"/>
+ for details. </para>
+ <para>See <xref linkend="manual-core.xtree"/>
+ for a detailed explanation about execution trees formats. </para>
+ </listitem>
+ </varlistentry>
<varlistentry id="opt.undef-value-errors" xreflabel="--undef-value-errors">
<term>
@@ -1040,6 +1096,13 @@
and/or by using a smaller value for the
option <varname>--num-callers</varname>.
</para>
+
+ <para>If you want to use
+ <computeroutput>--xtree-memory=full</computeroutput> memory profiling
+ (see <xref linkend="manual-core.xtree"/> ), then you cannot
+ specify <varname>--keep-stacktraces=free</varname>
+ or <varname>--keep-stacktraces=none</varname>.</para>
+
</listitem>
</varlistentry>
@@ -1823,7 +1886,7 @@
</listitem>
<listitem>
- <para><varname>leak_check [full*|summary]
+ <para><varname>leak_check [full*|summary|xtleak]
[kinds <set>|reachable|possibleleak*|definiteleak]
[heuristics heur1,heur2,...]
[increased*|changed|any]
@@ -1832,7 +1895,7 @@
performs a leak check. The <varname>*</varname> in the arguments
indicates the default values. </para>
- <para> If the <varname>[full*|summary]</varname> argument is
+ <para> If the <varname>[full*|summary|xtleak]</varname> argument is
<varname>summary</varname>, only a summary of the leak search is given;
otherwise a full leak report is produced. A full leak report gives
detailed information for each leak: the stack trace where the leaked blocks
@@ -1846,6 +1909,13 @@
of leak records to output. If this maximum is reached, the leak
search outputs the records with the biggest number of bytes.
</para>
+ <para>The value <varname>xtleak</varname> also produces a full leak report,
+ but output it as an xtree in a file xtleak.kcg.%p.%n (see <xref linkend="opt.log-file"/>).
+ See <xref linkend="manual-core.xtree"/>
+ for a detailed explanation about execution trees formats.
+ See <xref linkend="opt.xtree-leak"/> for the description of the events
+ in a xtree leak file.
+ </para>
<para>The <varname>kinds</varname> argument controls what kind of blocks
are shown for a <varname>full</varname> leak search. The set of leak kinds
diff --git a/memcheck/mc_errors.c b/memcheck/mc_errors.c
index 07d4c7b..7390348 100644
--- a/memcheck/mc_errors.c
+++ b/memcheck/mc_errors.c
@@ -8,7 +8,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -1098,7 +1098,7 @@
}
/* -- Search for a recently freed block which might bracket it. -- */
mc = MC_(get_freed_block_bracketting)( a );
- if (mc && !MC_(is_mempool_block)(mc)) {
+ if (mc) {
ai->tag = Addr_Block;
ai->Addr.Block.block_kind = Block_Freed;
ai->Addr.Block.block_desc = "block";
diff --git a/memcheck/mc_include.h b/memcheck/mc_include.h
index d36ea0b..cffe627 100644
--- a/memcheck/mc_include.h
+++ b/memcheck/mc_include.h
@@ -8,7 +8,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -144,6 +144,8 @@
void MC_(make_mem_defined) ( Addr a, SizeT len );
void MC_(copy_address_range_state) ( Addr src, Addr dst, SizeT len );
+void MC_(xtmemory_report) ( const HChar* filename, Bool fini );
+
void MC_(print_malloc_stats) ( void );
/* nr of free operations done */
SizeT MC_(get_cmalloc_n_frees) ( void );
@@ -384,7 +386,7 @@
// least one interior-pointer along the way.
IndirectLeak =2, // Leaked, but reachable from another leaked block
// (be it Unreached or IndirectLeak).
- Unreached =3, // Not reached, ie. leaked.
+ Unreached =3 // Not reached, ie. leaked.
// (At best, only reachable from itself via a cycle.)
}
Reachedness;
@@ -459,6 +461,7 @@
LeakCheckDeltaMode deltamode;
UInt max_loss_records_output; // limit on the nr of loss records output.
Bool requested_by_monitor_command; // True when requested by gdb/vgdb.
+ const HChar* xt_filename; // if != NULL, produce an xtree leak file.
}
LeakCheckParams;
diff --git a/memcheck/mc_leakcheck.c b/memcheck/mc_leakcheck.c
index f8ae72e..c026d27 100644
--- a/memcheck/mc_leakcheck.c
+++ b/memcheck/mc_leakcheck.c
@@ -7,7 +7,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -46,6 +46,8 @@
#include "pub_tool_signals.h" // Needed for mc_include.h
#include "pub_tool_libcsetjmp.h" // setjmp facilities
#include "pub_tool_tooliface.h" // Needed for mc_include.h
+#include "pub_tool_xarray.h"
+#include "pub_tool_xtree.h"
#include "mc_include.h"
@@ -712,7 +714,7 @@
/* Signal handler runs with the signal masked.
Unmask the handled signal before longjmp-ing or return-ing.
Note that during leak search, we expect only SIGSEGV or SIGBUS
- and we do not expect another occurence until we longjmp-ed!return-ed
+ and we do not expect another occurrence until we longjmp-ed!return-ed
to resume the leak search. So, it is safe to unmask the signal
here. */
/* First get current mask (by passing NULL as first arg) */
@@ -1301,6 +1303,189 @@
&& RiS(lr->key.state,lcp->errors_for_leak_kinds);
}
+//
+// Types and functions for xtree leak report.
+//
+
+static XTree* leak_xt;
+
+/* Sizes and delta sizes for a loss record output in an xtree.
+ As the output format can only show positive values, we need values for
+ the increase and decrease cases. */
+typedef
+ struct _XT_BIBK {
+ ULong szB; // Current values
+ ULong indirect_szB;
+ ULong num_blocks;
+ } XT_BIBK; // Bytes, Indirect bytes, BlocKs
+
+typedef
+ enum {
+ XT_Value =0,
+ XT_Increase =1,
+ XT_Decrease =2
+ }
+ XT_VID; // Value or Increase or Decrease
+
+typedef
+ struct _XT_lr {
+ XT_BIBK vid[3]; // indexed by XT_VID
+ } XT_lr;
+
+typedef
+ struct _XT_Leak {
+ XT_lr xt_lr[4]; // indexed by Reachedness
+ } XT_Leak;
+
+static void MC_(XT_Leak_init)(void* xtl)
+{
+ VG_(memset) (xtl, 0, sizeof(XT_Leak));
+}
+static void MC_(XT_Leak_add) (void* to, const void* xtleak)
+{
+ XT_Leak* xto = to;
+ const XT_Leak* xtl = xtleak;
+
+ for (int r = Reachable; r <= Unreached; r++)
+ for (int d = 0; d < 3; d++) {
+ xto->xt_lr[r].vid[d].szB += xtl->xt_lr[r].vid[d].szB;
+ xto->xt_lr[r].vid[d].indirect_szB += xtl->xt_lr[r].vid[d].indirect_szB;
+ xto->xt_lr[r].vid[d].num_blocks += xtl->xt_lr[r].vid[d].num_blocks;
+ }
+}
+static void XT_insert_lr (LossRecord* lr)
+{
+ XT_Leak xtl;
+ Reachedness i = lr->key.state;
+
+ MC_(XT_Leak_init)(&xtl);
+
+ xtl.xt_lr[i].vid[XT_Value].szB = lr->szB;
+ xtl.xt_lr[i].vid[XT_Value].indirect_szB = lr->indirect_szB;
+ xtl.xt_lr[i].vid[XT_Value].num_blocks = lr->num_blocks;
+
+ if (lr->szB > lr->old_szB)
+ xtl.xt_lr[i].vid[XT_Increase].szB = lr->szB - lr->old_szB;
+ else
+ xtl.xt_lr[i].vid[XT_Decrease].szB = lr->old_szB - lr->szB;
+ if (lr->indirect_szB > lr->old_indirect_szB)
+ xtl.xt_lr[i].vid[XT_Increase].indirect_szB
+ = lr->indirect_szB - lr->old_indirect_szB;
+ else
+ xtl.xt_lr[i].vid[XT_Decrease].indirect_szB
+ = lr->old_indirect_szB - lr->indirect_szB;
+ if (lr->num_blocks > lr->old_num_blocks)
+ xtl.xt_lr[i].vid[XT_Increase].num_blocks
+ = lr->num_blocks - lr->old_num_blocks;
+ else
+ xtl.xt_lr[i].vid[XT_Decrease].num_blocks
+ = lr->old_num_blocks - lr->num_blocks;
+
+ VG_(XT_add_to_ec)(leak_xt, lr->key.allocated_at, &xtl);
+}
+
+static void MC_(XT_Leak_sub) (void* from, const void* xtleak)
+{
+ tl_assert(0); // Should not be called.
+}
+static const HChar* MC_(XT_Leak_img) (const void* xtleak)
+{
+ static XT_Leak zero;
+ static HChar buf[600];
+ UInt off = 0;
+
+ const XT_Leak* xtl = xtleak;
+
+ if (VG_(memcmp)(xtl, &zero, sizeof(XT_Leak)) != 0) {
+ for (UInt d = XT_Value; d <= XT_Decrease; d++) {
+ // print szB. We add indirect_szB to have the Unreachable showing
+ // the total bytes loss, including indirect loss. This is similar
+ // to the textual and xml reports.
+ for (UInt r = Reachable; r <= Unreached; r++)
+ off += VG_(sprintf) (buf + off, " %llu",
+ xtl->xt_lr[r].vid[d].szB
+ + xtl->xt_lr[r].vid[d].indirect_szB);
+ // print indirect_szB, only for reachedness having such values)
+ for (UInt r = Reachable; r <= Unreached; r++)
+ if (r == Unreached)
+ off += VG_(sprintf) (buf + off, " %llu",
+ xtl->xt_lr[r].vid[d].indirect_szB);
+ // print num_blocks
+ for (UInt r = Reachable; r <= Unreached; r++)
+ off += VG_(sprintf) (buf + off, " %llu",
+ xtl->xt_lr[r].vid[d].num_blocks);
+ }
+ return buf + 1; // + 1 to skip the useless first space
+ } else {
+ return NULL;
+ }
+}
+
+/* The short event name is made of 2 or 3 or 4 letters:
+ an optional delta indication: i = increase d = decrease
+ a loss kind: R = Reachable P = Possibly I = Indirectly D = Definitely
+ an optional i to indicate this loss record has indirectly lost bytes
+ B = Bytes or Bk = Blocks.
+ Note that indirectly lost bytes/blocks can thus be counted in 2
+ loss records: the loss records for their "own" allocation stack trace,
+ and the loss record of the 'main' Definitely or Possibly loss record
+ in the indirectly lost count for these loss records. */
+static const HChar* XT_Leak_events =
+ ////// XT_Value szB
+ "RB : Reachable Bytes" ","
+ "PB : Possibly lost Bytes" ","
+ "IB : Indirectly lost Bytes" ","
+ "DB : Definitely lost Bytes (direct plus indirect)" ","
+
+ ////// XT_Value indirect_szB
+ // no RIB
+ // no PIB
+ // no IIB
+ "DIB : Definitely Indirectly lost Bytes (subset of DB)" ","
+
+ ////// XT_Value num_blocks
+ "RBk : reachable Blocks" ","
+ "PBk : Possibly lost Blocks" ","
+ "IBk : Indirectly lost Blocks" ","
+ "DBk : Definitely lost Blocks" ","
+
+ ////// XT_Increase szB
+ "iRB : increase Reachable Bytes" ","
+ "iPB : increase Possibly lost Bytes" ","
+ "iIB : increase Indirectly lost Bytes" ","
+ "iDB : increase Definitely lost Bytes" ","
+
+ ////// XT_Increase indirect_szB
+ // no iRIB
+ // no iPIB
+ // no iIIB
+ "iDIB : increase Definitely Indirectly lost Bytes" ","
+
+ ////// XT_Increase num_blocks
+ "iRBk : increase reachable Blocks" ","
+ "iPBk : increase Possibly lost Blocks" ","
+ "iIBk : increase Indirectly lost Blocks" ","
+ "iDBk : increase Definitely lost Blocks" ","
+
+
+ ////// XT_Decrease szB
+ "dRB : decrease Reachable Bytes" ","
+ "dPB : decrease Possibly lost Bytes" ","
+ "dIB : decrease Indirectly lost Bytes" ","
+ "dDB : decrease Definitely lost Bytes" ","
+
+ ////// XT_Decrease indirect_szB
+ // no dRIB
+ // no dPIB
+ // no dIIB
+ "dDIB : decrease Definitely Indirectly lost Bytes" ","
+
+ ////// XT_Decrease num_blocks
+ "dRBk : decrease reachable Blocks" ","
+ "dPBk : decrease Possibly lost Blocks" ","
+ "dIBk : decrease Indirectly lost Blocks" ","
+ "dDBk : decrease Definitely lost Blocks";
+
static void print_results(ThreadId tid, LeakCheckParams* lcp)
{
Int i, n_lossrecords, start_lr_output_scan;
@@ -1452,14 +1637,28 @@
}
}
+ if (lcp->xt_filename != NULL)
+ leak_xt = VG_(XT_create) (VG_(malloc),
+ "mc_leakcheck.leak_xt",
+ VG_(free),
+ sizeof(XT_Leak),
+ MC_(XT_Leak_init),
+ MC_(XT_Leak_add),
+ MC_(XT_Leak_sub),
+ VG_(XT_filter_maybe_below_main));
+
// Print the loss records (in size order) and collect summary stats.
for (i = start_lr_output_scan; i < n_lossrecords; i++) {
Bool count_as_error, print_record;
lr = lr_array[i];
get_printing_rules(lcp, lr, &count_as_error, &print_record);
is_suppressed =
- MC_(record_leak_error) ( tid, i+1, n_lossrecords, lr, print_record,
- count_as_error );
+ MC_(record_leak_error)
+ ( tid, i+1, n_lossrecords, lr,
+ lcp->xt_filename == NULL ? print_record : False,
+ count_as_error );
+ if (lcp->xt_filename != NULL && !is_suppressed && print_record)
+ XT_insert_lr (lr);
if (is_suppressed) {
MC_(blocks_suppressed) += lr->num_blocks;
@@ -1486,6 +1685,16 @@
}
}
+ if (lcp->xt_filename != NULL) {
+ VG_(XT_callgrind_print)(leak_xt,
+ lcp->xt_filename,
+ XT_Leak_events,
+ MC_(XT_Leak_img));
+ if (VG_(clo_verbosity) >= 1 || lcp->requested_by_monitor_command)
+ VG_(umsg)("xtree leak report: %s\n", lcp->xt_filename);
+ VG_(XT_delete)(leak_xt);
+ }
+
if (VG_(clo_verbosity) > 0 && !VG_(clo_xml)) {
HChar d_bytes[31];
HChar d_blocks[31];
diff --git a/memcheck/mc_machine.c b/memcheck/mc_machine.c
index 44932a4..3ff7c44 100644
--- a/memcheck/mc_machine.c
+++ b/memcheck/mc_machine.c
@@ -9,7 +9,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2008-2015 OpenWorks Ltd
+ Copyright (C) 2008-2017 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -48,11 +48,6 @@
#define MC_SIZEOF_GUEST_STATE sizeof(VexGuestArchState)
__attribute__((unused))
-#if defined(VGA_tilegx)
-# include "libvex_guest_tilegx.h"
-# define MC_SIZEOF_GUEST_STATE sizeof(VexGuestTILEGXState)
-#endif
-
static inline Bool host_is_big_endian ( void ) {
UInt x = 0x11223344;
return 0x1122 == *(UShort*)(&x);
@@ -1040,6 +1035,10 @@
if (o == GOF(CMSTART) && sz == 8) return -1; // untracked
if (o == GOF(CMLEN) && sz == 8) return -1; // untracked
+ if (o == GOF(LLSC_SIZE) && sz == 8) return -1; // untracked
+ if (o == GOF(LLSC_ADDR) && sz == 8) return o;
+ if (o == GOF(LLSC_DATA) && sz == 8) return o;
+
VG_(printf)("MC_(get_otrack_shadow_offset)(arm64)(off=%d,sz=%d)\n",
offset,szB);
tl_assert(0);
@@ -1159,6 +1158,9 @@
if (o == GOF(ac2) && sz == 8) return o;
if (o == GOF(ac3) && sz == 8) return o;
+ if (o == GOF(LLaddr) && sz == 4) return -1; /* slot unused */
+ if (o == GOF(LLdata) && sz == 4) return -1; /* slot unused */
+
VG_(printf)("MC_(get_otrack_shadow_offset)(mips)(off=%d,sz=%d)\n",
offset,szB);
tl_assert(0);
@@ -1238,44 +1240,15 @@
if ((o > GOF(NRADDR)) && (o <= GOF(NRADDR) +12 )) return -1;
+ if (o == GOF(LLaddr) && sz == 8) return -1; /* slot unused */
+ if (o == GOF(LLdata) && sz == 8) return -1; /* slot unused */
+
VG_(printf)("MC_(get_otrack_shadow_offset)(mips)(off=%d,sz=%d)\n",
offset,szB);
tl_assert(0);
# undef GOF
# undef SZB
- /* --------------------- tilegx --------------------- */
-# elif defined(VGA_tilegx)
-
-# define GOF(_fieldname) \
- (offsetof(VexGuestTILEGXState,guest_##_fieldname))
-# define SZB(_fieldname) \
- (sizeof(((VexGuestTILEGXState*)0)->guest_##_fieldname))
-
- Int o = offset;
- Int sz = szB;
- Bool is1248 = sz == 8 || sz == 4 || sz == 2 || sz == 1;
-
- tl_assert(sz > 0);
- tl_assert(host_is_little_endian());
-
- if (o >= GOF(r0) && is1248 && o <= (GOF(r63) + 8 - sz))
- return GOF(r0) + ((o-GOF(r0)) & -8) ;
-
- if (o == GOF(pc) && sz == 8) return o;
- if (o == GOF(EMNOTE) && sz == 8) return o;
- if (o == GOF(CMSTART) && sz == 8) return o;
- if (o == GOF(CMLEN) && sz == 8) return o;
- if (o == GOF(NRADDR) && sz == 8) return o;
- if (o == GOF(cmpexch) && sz == 8) return o;
- if (o == GOF(zero) && sz == 8) return o;
-
- VG_(printf)("MC_(get_otrack_shadow_offset)(tilegx)(off=%d,sz=%d)\n",
- offset,szB);
- tl_assert(0);
-# undef GOF
-# undef SZB
-
# else
# error "FIXME: not implemented for this architecture"
# endif
@@ -1391,13 +1364,6 @@
VG_(printf)("\n");
tl_assert(0);
- /* --------------------- tilegx --------------------- */
-# elif defined(VGA_tilegx)
- VG_(printf)("get_reg_array_equiv_int_type(tilegx): unhandled: ");
- ppIRRegArray(arr);
- VG_(printf)("\n");
- tl_assert(0);
-
# else
# error "FIXME: not implemented for this architecture"
# endif
diff --git a/memcheck/mc_main.c b/memcheck/mc_main.c
index 30fa008..a9a565b 100644
--- a/memcheck/mc_main.c
+++ b/memcheck/mc_main.c
@@ -10,7 +10,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -47,6 +47,9 @@
#include "pub_tool_replacemalloc.h"
#include "pub_tool_tooliface.h"
#include "pub_tool_threadstate.h"
+#include "pub_tool_xarray.h"
+#include "pub_tool_xtree.h"
+#include "pub_tool_xtmemory.h"
#include "mc_include.h"
#include "memcheck.h" /* for client requests */
@@ -173,10 +176,10 @@
#else
-/* Just handle the first 64G fast and the rest via auxiliary
+/* Just handle the first 128G fast and the rest via auxiliary
primaries. If you change this, Memcheck will assert at startup.
See the definition of UNALIGNED_OR_HIGH for extensive comments. */
-# define N_PRIMARY_BITS 20
+# define N_PRIMARY_BITS 21
#endif
@@ -274,9 +277,12 @@
return (start_of_this_sm(a) == a);
}
+STATIC_ASSERT(SM_CHUNKS % 2 == 0);
+
typedef
- struct {
+ union {
UChar vabits8[SM_CHUNKS];
+ UShort vabits16[SM_CHUNKS/2];
}
SecMap;
@@ -1380,7 +1386,7 @@
&& nBits == 64 && VG_IS_8_ALIGNED(a))) {
SecMap* sm = get_secmap_for_reading(a);
UWord sm_off16 = SM_OFF_16(a);
- UWord vabits16 = ((UShort*)(sm->vabits8))[sm_off16];
+ UWord vabits16 = sm->vabits16[sm_off16];
if (LIKELY(vabits16 == VA_BITS16_DEFINED))
return V_BITS64_DEFINED;
if (LIKELY(vabits16 == VA_BITS16_UNDEFINED))
@@ -1533,7 +1539,7 @@
&& nBits == 64 && VG_IS_8_ALIGNED(a))) {
SecMap* sm = get_secmap_for_reading(a);
UWord sm_off16 = SM_OFF_16(a);
- UWord vabits16 = ((UShort*)(sm->vabits8))[sm_off16];
+ UWord vabits16 = sm->vabits16[sm_off16];
if (LIKELY( !is_distinguished_sm(sm) &&
(VA_BITS16_DEFINED == vabits16 ||
VA_BITS16_UNDEFINED == vabits16) )) {
@@ -1541,10 +1547,10 @@
/* is mapped, and is addressible. */
// Convert full V-bits in register to compact 2-bit form.
if (LIKELY(V_BITS64_DEFINED == vbytes)) {
- ((UShort*)(sm->vabits8))[sm_off16] = (UShort)VA_BITS16_DEFINED;
+ sm->vabits16[sm_off16] = VA_BITS16_DEFINED;
return;
} else if (V_BITS64_UNDEFINED == vbytes) {
- ((UShort*)(sm->vabits8))[sm_off16] = (UShort)VA_BITS16_UNDEFINED;
+ sm->vabits16[sm_off16] = VA_BITS16_UNDEFINED;
return;
}
/* else fall into the slow case */
@@ -1741,7 +1747,7 @@
if (lenA < 8) break;
PROF_EVENT(MCPE_SET_ADDRESS_RANGE_PERMS_LOOP8A);
sm_off16 = SM_OFF_16(a);
- ((UShort*)(sm->vabits8))[sm_off16] = vabits16;
+ sm->vabits16[sm_off16] = vabits16;
a += 8;
lenA -= 8;
}
@@ -1814,7 +1820,7 @@
if (lenB < 8) break;
PROF_EVENT(MCPE_SET_ADDRESS_RANGE_PERMS_LOOP8B);
sm_off16 = SM_OFF_16(a);
- ((UShort*)(sm->vabits8))[sm_off16] = vabits16;
+ sm->vabits16[sm_off16] = vabits16;
a += 8;
lenB -= 8;
}
@@ -2757,7 +2763,7 @@
sm = get_secmap_for_writing_low(a);
sm_off16 = SM_OFF_16(a);
- ((UShort*)(sm->vabits8))[sm_off16] = VA_BITS16_UNDEFINED;
+ sm->vabits16[sm_off16] = VA_BITS16_UNDEFINED;
}
#endif
}
@@ -2801,7 +2807,7 @@
sm = get_secmap_for_writing_low(a);
sm_off16 = SM_OFF_16(a);
- ((UShort*)(sm->vabits8))[sm_off16] = VA_BITS16_NOACCESS;
+ sm->vabits16[sm_off16] = VA_BITS16_NOACCESS;
//// BEGIN inlined, specialised version of MC_(helperc_b_store8)
//// Clear the origins for a+0 .. a+7.
@@ -3630,9 +3636,9 @@
/* Now we know that the entire address range falls within a
single secondary map, and that that secondary 'lives' in
the main primary map. */
- SecMap* sm = get_secmap_for_writing_low(a_lo);
- UWord v_off = SM_OFF(a_lo);
- UShort* p = (UShort*)(&sm->vabits8[v_off]);
+ SecMap* sm = get_secmap_for_writing_low(a_lo);
+ UWord v_off16 = SM_OFF_16(a_lo);
+ UShort* p = &sm->vabits16[v_off16];
p[ 0] = VA_BITS16_UNDEFINED;
p[ 1] = VA_BITS16_UNDEFINED;
p[ 2] = VA_BITS16_UNDEFINED;
@@ -3683,9 +3689,9 @@
/* Now we know that the entire address range falls within a
single secondary map, and that that secondary 'lives' in
the main primary map. */
- SecMap* sm = get_secmap_for_writing_low(a_lo);
- UWord v_off = SM_OFF(a_lo);
- UShort* p = (UShort*)(&sm->vabits8[v_off]);
+ SecMap* sm = get_secmap_for_writing_low(a_lo);
+ UWord v_off16 = SM_OFF_16(a_lo);
+ UShort* p = &sm->vabits16[v_off16];
p[ 0] = VA_BITS16_UNDEFINED;
p[ 1] = VA_BITS16_UNDEFINED;
p[ 2] = VA_BITS16_UNDEFINED;
@@ -3827,9 +3833,9 @@
/* Now we know that the entire address range falls within a
single secondary map, and that that secondary 'lives' in
the main primary map. */
- SecMap* sm = get_secmap_for_writing_low(a_lo);
- UWord v_off = SM_OFF(a_lo);
- UShort* p = (UShort*)(&sm->vabits8[v_off]);
+ SecMap* sm = get_secmap_for_writing_low(a_lo);
+ UWord v_off16 = SM_OFF_16(a_lo);
+ UShort* p = &sm->vabits16[v_off16];
p[ 0] = VA_BITS16_UNDEFINED;
p[ 1] = VA_BITS16_UNDEFINED;
p[ 2] = VA_BITS16_UNDEFINED;
@@ -3864,9 +3870,9 @@
/* Now we know that the entire address range falls within a
single secondary map, and that that secondary 'lives' in
the main primary map. */
- SecMap* sm = get_secmap_for_writing_low(a_lo);
- UWord v_off = SM_OFF(a_lo);
- UShort* p = (UShort*)(&sm->vabits8[v_off]);
+ SecMap* sm = get_secmap_for_writing_low(a_lo);
+ UWord v_off16 = SM_OFF_16(a_lo);
+ UShort* p = &sm->vabits16[v_off16];
p[ 0] = VA_BITS16_UNDEFINED;
p[ 1] = VA_BITS16_UNDEFINED;
p[ 2] = VA_BITS16_UNDEFINED;
@@ -3979,7 +3985,7 @@
PROF_EVENT(MCPE_MAKE_STACK_UNINIT_128_NO_O_ALIGNED_16);
SecMap* sm = get_secmap_for_writing_low(a_lo);
UWord v_off = SM_OFF(a_lo);
- UInt* w32 = (UInt*)(&sm->vabits8[v_off]);
+ UInt* w32 = ASSUME_ALIGNED(UInt*, &sm->vabits8[v_off]);
w32[ 0] = VA_BITS32_UNDEFINED;
w32[ 1] = VA_BITS32_UNDEFINED;
w32[ 2] = VA_BITS32_UNDEFINED;
@@ -4012,10 +4018,10 @@
/* Now we know that the entire address range falls within a
single secondary map, and that that secondary 'lives' in
the main primary map. */
- SecMap* sm = get_secmap_for_writing_low(a_lo);
- UWord v_off = SM_OFF(a_lo);
- UShort* w16 = (UShort*)(&sm->vabits8[v_off]);
- UInt* w32 = (UInt*)(&w16[1]);
+ SecMap* sm = get_secmap_for_writing_low(a_lo);
+ UWord v_off16 = SM_OFF_16(a_lo);
+ UShort* w16 = &sm->vabits16[v_off16];
+ UInt* w32 = ASSUME_ALIGNED(UInt*, &w16[1]);
/* The following assertion is commented out for obvious
performance reasons, but was verified as valid when
running the entire testsuite and also Firefox. */
@@ -4462,7 +4468,7 @@
static void mc_post_reg_write ( CorePart part, ThreadId tid,
PtrdiffT offset, SizeT size)
{
-# define MAX_REG_WRITE_SIZE 1712
+# define MAX_REG_WRITE_SIZE 1728
UChar area[MAX_REG_WRITE_SIZE];
tl_assert(size <= MAX_REG_WRITE_SIZE);
VG_(memset)(area, V_BITS8_DEFINED, size);
@@ -4766,7 +4772,7 @@
for (j = 0; j < nULongs; j++) {
sm = get_secmap_for_reading_low(a + 8*j);
sm_off16 = SM_OFF_16(a + 8*j);
- vabits16 = ((UShort*)(sm->vabits8))[sm_off16];
+ vabits16 = sm->vabits16[sm_off16];
// Convert V bits from compact memory form to expanded
// register form.
@@ -4828,7 +4834,7 @@
sm = get_secmap_for_reading_low(a);
sm_off16 = SM_OFF_16(a);
- vabits16 = ((UShort*)(sm->vabits8))[sm_off16];
+ vabits16 = sm->vabits16[sm_off16];
// Handle common case quickly: a is suitably aligned, is mapped, and
// addressible.
@@ -4962,7 +4968,7 @@
sm = get_secmap_for_reading_low(a);
sm_off16 = SM_OFF_16(a);
- vabits16 = ((UShort*)(sm->vabits8))[sm_off16];
+ vabits16 = sm->vabits16[sm_off16];
// To understand the below cleverness, see the extensive comments
// in MC_(helperc_STOREV8).
@@ -4971,7 +4977,7 @@
return;
}
if (!is_distinguished_sm(sm) && VA_BITS16_UNDEFINED == vabits16) {
- ((UShort*)(sm->vabits8))[sm_off16] = (UShort)VA_BITS16_DEFINED;
+ sm->vabits16[sm_off16] = VA_BITS16_DEFINED;
return;
}
PROF_EVENT(MCPE_STOREV64_SLOW2);
@@ -4983,7 +4989,7 @@
return;
}
if (!is_distinguished_sm(sm) && VA_BITS16_DEFINED == vabits16) {
- ((UShort*)(sm->vabits8))[sm_off16] = (UShort)VA_BITS16_UNDEFINED;
+ sm->vabits16[sm_off16] = VA_BITS16_UNDEFINED;
return;
}
PROF_EVENT(MCPE_STOREV64_SLOW3);
@@ -6009,6 +6015,8 @@
| H2S( LchLength64)
| H2S( LchNewArray)
| H2S( LchMultipleInheritance);
+Bool MC_(clo_xtree_leak) = False;
+const HChar* MC_(clo_xtree_leak_file) = "xtleak.kcg.%p";
Bool MC_(clo_workaround_gcc296_bugs) = False;
Int MC_(clo_malloc_fill) = -1;
Int MC_(clo_free_fill) = -1;
@@ -6210,6 +6218,11 @@
else if VG_BOOL_CLO(arg, "--expensive-definedness-checks",
MC_(clo_expensive_definedness_checks)) {}
+ else if VG_BOOL_CLO(arg, "--xtree-leak",
+ MC_(clo_xtree_leak)) {}
+ else if VG_STR_CLO (arg, "--xtree-leak-file",
+ MC_(clo_xtree_leak_file)) {}
+
else
return VG_(replacement_malloc_process_cmd_line_option)(arg);
@@ -6241,6 +6254,8 @@
" same as --show-leak-kinds=definite,possible\n"
" --show-reachable=no --show-possibly-lost=no\n"
" same as --show-leak-kinds=definite\n"
+" --xtree-leak=no|yes output leak result in xtree format? [no]\n"
+" --xtree-leak-file=<file> xtree leak report file [xtleak.kcg.%%p]\n"
" --undef-value-errors=no|yes check for undefined value errors [yes]\n"
" --track-origins=no|yes show origins of undefined values? [no]\n"
" --partial-loads-ok=no|yes too hard to explain here; see manual [yes]\n"
@@ -6375,12 +6390,13 @@
" check_memory [addressable|defined] <addr> [<len>]\n"
" check that <len> (or 1) bytes at <addr> have the given accessibility\n"
" and outputs a description of <addr>\n"
-" leak_check [full*|summary]\n"
+" leak_check [full*|summary|xtleak]\n"
" [kinds kind1,kind2,...|reachable|possibleleak*|definiteleak]\n"
" [heuristics heur1,heur2,...]\n"
" [increased*|changed|any]\n"
" [unlimited*|limited <max_loss_records_output>]\n"
" * = defaults\n"
+" xtleak produces an xtree full leak result in xtleak.kcg.%%p.%%n\n"
" where kind is one of:\n"
" definite indirect possible reachable all none\n"
" where heur is one of:\n"
@@ -6400,6 +6416,8 @@
" shows places pointing inside <len> (default 1) bytes at <addr>\n"
" (with len 1, only shows \"start pointers\" pointing exactly to <addr>,\n"
" with len > 1, will also show \"interior pointers\")\n"
+" xtmemory [<filename>]\n"
+" dump xtree memory profile in <filename> (default xtmemory.kcg.%%p.%%n)\n"
"\n");
}
@@ -6515,7 +6533,7 @@
command. This ensures a shorter abbreviation for the user. */
switch (VG_(keyword_id)
("help get_vbits leak_check make_memory check_memory "
- "block_list who_points_at xb",
+ "block_list who_points_at xb xtmemory",
wcmd, kwd_report_duplicated_matches)) {
case -2: /* multiple matches */
return True;
@@ -6562,6 +6580,7 @@
case 2: { /* leak_check */
Int err = 0;
LeakCheckParams lcp;
+ HChar* xt_filename = NULL;
HChar* kw;
lcp.mode = LC_Full;
@@ -6571,12 +6590,13 @@
lcp.deltamode = LCD_Increased;
lcp.max_loss_records_output = 999999999;
lcp.requested_by_monitor_command = True;
+ lcp.xt_filename = NULL;
for (kw = VG_(strtok_r) (NULL, " ", &ssaveptr);
kw != NULL;
kw = VG_(strtok_r) (NULL, " ", &ssaveptr)) {
switch (VG_(keyword_id)
- ("full summary "
+ ("full summary xtleak "
"kinds reachable possibleleak definiteleak "
"heuristics "
"increased changed any "
@@ -6588,7 +6608,14 @@
lcp.mode = LC_Full; break;
case 1: /* summary */
lcp.mode = LC_Summary; break;
- case 2: { /* kinds */
+ case 2: /* xtleak */
+ lcp.mode = LC_Full;
+ xt_filename
+ = VG_(expand_file_name)("--xtleak-mc_main.c",
+ "xtleak.kcg.%p.%n");
+ lcp.xt_filename = xt_filename;
+ break;
+ case 3: { /* kinds */
wcmd = VG_(strtok_r) (NULL, " ", &ssaveptr);
if (wcmd == NULL
|| !VG_(parse_enum_set)(MC_(parse_leak_kinds_tokens),
@@ -6600,17 +6627,17 @@
}
break;
}
- case 3: /* reachable */
+ case 4: /* reachable */
lcp.show_leak_kinds = MC_(all_Reachedness)();
break;
- case 4: /* possibleleak */
+ case 5: /* possibleleak */
lcp.show_leak_kinds
= R2S(Possible) | R2S(IndirectLeak) | R2S(Unreached);
break;
- case 5: /* definiteleak */
+ case 6: /* definiteleak */
lcp.show_leak_kinds = R2S(Unreached);
break;
- case 6: { /* heuristics */
+ case 7: { /* heuristics */
wcmd = VG_(strtok_r) (NULL, " ", &ssaveptr);
if (wcmd == NULL
|| !VG_(parse_enum_set)(MC_(parse_leak_heuristics_tokens),
@@ -6622,15 +6649,15 @@
}
break;
}
- case 7: /* increased */
+ case 8: /* increased */
lcp.deltamode = LCD_Increased; break;
- case 8: /* changed */
+ case 9: /* changed */
lcp.deltamode = LCD_Changed; break;
- case 9: /* any */
+ case 10: /* any */
lcp.deltamode = LCD_Any; break;
- case 10: /* unlimited */
+ case 11: /* unlimited */
lcp.max_loss_records_output = 999999999; break;
- case 11: { /* limited */
+ case 12: { /* limited */
Int int_value;
const HChar* endptr;
@@ -6658,6 +6685,8 @@
}
if (!err)
MC_(detect_memory_leaks)(tid, &lcp);
+ if (xt_filename != NULL)
+ VG_(free)(xt_filename);
return True;
}
@@ -6874,6 +6903,13 @@
return True;
}
+ case 8: { /* xtmemory */
+ HChar* filename;
+ filename = VG_(strtok_r) (NULL, " ", &ssaveptr);
+ MC_(xtmemory_report)(filename, False);
+ return True;
+ }
+
default:
tl_assert(0);
return False;
@@ -6978,6 +7014,7 @@
}
lcp.max_loss_records_output = 999999999;
lcp.requested_by_monitor_command = False;
+ lcp.xt_filename = NULL;
MC_(detect_memory_leaks)(tid, &lcp);
*ret = 0; /* return value is meaningless */
@@ -7842,7 +7879,7 @@
// As for the portability of all this:
//
// sbrk and brk are not POSIX. However, any system that is a derivative
- // of *nix has sbrk and brk because there are too many softwares (such as
+ // of *nix has sbrk and brk because there are too many software (such as
// the Bourne shell) which rely on the traditional memory map (.text,
// .data+.bss, stack) and the existence of sbrk/brk.
//
@@ -7889,6 +7926,17 @@
/* Do not check definedness of guest state if --undef-value-errors=no */
if (MC_(clo_mc_level) >= 2)
VG_(track_pre_reg_read) ( mc_pre_reg_read );
+
+ if (VG_(clo_xtree_memory) == Vg_XTMemory_Full) {
+ if (MC_(clo_keep_stacktraces) == KS_none
+ || MC_(clo_keep_stacktraces) == KS_free)
+ VG_(fmsg_bad_option)("--keep-stacktraces",
+ "To use --xtree-memory=full, you must"
+ " keep at least the alloc stacktrace\n");
+ // Activate full xtree memory profiling.
+ VG_(XTMemory_Full_init)(VG_(XT_filter_1top_and_maybe_below_main));
+ }
+
}
static void print_SM_info(const HChar* type, Int n_SMs)
@@ -7997,10 +8045,12 @@
static void mc_fini ( Int exitcode )
{
+ MC_(xtmemory_report) (VG_(clo_xtree_memory_file), True);
MC_(print_malloc_stats)();
if (MC_(clo_leak_check) != LC_Off) {
LeakCheckParams lcp;
+ HChar* xt_filename = NULL;
lcp.mode = MC_(clo_leak_check);
lcp.show_leak_kinds = MC_(clo_show_leak_kinds);
lcp.heuristics = MC_(clo_leak_check_heuristics);
@@ -8008,7 +8058,17 @@
lcp.deltamode = LCD_Any;
lcp.max_loss_records_output = 999999999;
lcp.requested_by_monitor_command = False;
+ if (MC_(clo_xtree_leak)) {
+ xt_filename = VG_(expand_file_name)("--xtree-leak-file",
+ MC_(clo_xtree_leak_file));
+ lcp.xt_filename = xt_filename;
+ lcp.mode = LC_Full;
+ }
+ else
+ lcp.xt_filename = NULL;
MC_(detect_memory_leaks)(1/*bogus ThreadId*/, &lcp);
+ if (MC_(clo_xtree_leak))
+ VG_(free)(xt_filename);
} else {
if (VG_(clo_verbosity) == 1 && !VG_(clo_xml)) {
VG_(umsg)(
@@ -8099,7 +8159,7 @@
VG_(details_version) (NULL);
VG_(details_description) ("a memory error detector");
VG_(details_copyright_author)(
- "Copyright (C) 2002-2015, and GNU GPL'd, by Julian Seward et al.");
+ "Copyright (C) 2002-2017, and GNU GPL'd, by Julian Seward et al.");
VG_(details_bug_reports_to) (VG_BUGS_TO);
VG_(details_avg_translation_sizeB) ( 640 );
@@ -8240,11 +8300,11 @@
tl_assert(sizeof(Addr) == 8);
tl_assert(sizeof(UWord) == 8);
tl_assert(sizeof(Word) == 8);
- tl_assert(MAX_PRIMARY_ADDRESS == 0xFFFFFFFFFULL);
- tl_assert(MASK(1) == 0xFFFFFFF000000000ULL);
- tl_assert(MASK(2) == 0xFFFFFFF000000001ULL);
- tl_assert(MASK(4) == 0xFFFFFFF000000003ULL);
- tl_assert(MASK(8) == 0xFFFFFFF000000007ULL);
+ tl_assert(MAX_PRIMARY_ADDRESS == 0x1FFFFFFFFFULL);
+ tl_assert(MASK(1) == 0xFFFFFFE000000000ULL);
+ tl_assert(MASK(2) == 0xFFFFFFE000000001ULL);
+ tl_assert(MASK(4) == 0xFFFFFFE000000003ULL);
+ tl_assert(MASK(8) == 0xFFFFFFE000000007ULL);
# endif
/* Check some assertions to do with the instrumentation machinery. */
diff --git a/memcheck/mc_malloc_wrappers.c b/memcheck/mc_malloc_wrappers.c
index f488178..875eba7 100644
--- a/memcheck/mc_malloc_wrappers.c
+++ b/memcheck/mc_malloc_wrappers.c
@@ -8,7 +8,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -36,12 +36,16 @@
#include "pub_tool_libcbase.h"
#include "pub_tool_libcassert.h"
#include "pub_tool_libcprint.h"
+#include "pub_tool_libcproc.h"
#include "pub_tool_mallocfree.h"
#include "pub_tool_options.h"
#include "pub_tool_replacemalloc.h"
#include "pub_tool_threadstate.h"
#include "pub_tool_tooliface.h" // Needed for mc_include.h
#include "pub_tool_stacktrace.h" // For VG_(get_and_pp_StackTrace)
+#include "pub_tool_xarray.h"
+#include "pub_tool_xtree.h"
+#include "pub_tool_xtmemory.h"
#include "mc_include.h"
@@ -303,20 +307,37 @@
default: tl_assert (0);
}
mc->where[0] = VG_(record_ExeContext) ( tid, 0/*first_ip_delta*/ );
+ if (UNLIKELY(VG_(clo_xtree_memory) == Vg_XTMemory_Full))
+ VG_(XTMemory_Full_alloc)(mc->szB, mc->where[0]);
}
void MC_(set_freed_at) (ThreadId tid, MC_Chunk* mc)
{
- UInt pos;
+ Int pos;
+ ExeContext* ec_free;
+
switch (MC_(clo_keep_stacktraces)) {
case KS_none: return;
- case KS_alloc: return;
+ case KS_alloc:
+ if (LIKELY(VG_(clo_xtree_memory)
+ != Vg_XTMemory_Full))
+ return;
+ pos = -1; break;
case KS_free: pos = 0; break;
case KS_alloc_then_free: pos = 0; break;
case KS_alloc_and_free: pos = 1; break;
default: tl_assert (0);
}
- mc->where[pos] = VG_(record_ExeContext) ( tid, 0/*first_ip_delta*/ );
+ /* We need the execontext for the free operation, either to store
+ it in the mc chunk and/or for full xtree memory profiling.
+ Note: we are guaranteed to find the ec_alloc in mc->where[0], as
+ mc_post_clo_init verifies the consistency of --xtree-memory and
+ --keep-stacktraces. */
+ ec_free = VG_(record_ExeContext) ( tid, 0/*first_ip_delta*/ );
+ if (UNLIKELY(VG_(clo_xtree_memory) == Vg_XTMemory_Full))
+ VG_(XTMemory_Full_free)(mc->szB, mc->where[0], ec_free);
+ if (LIKELY(pos >= 0))
+ mc->where[pos] = ec_free;
}
UInt MC_(n_where_pointers) (void)
@@ -651,6 +672,9 @@
if (oldSizeB == newSizeB)
return;
+ if (UNLIKELY(VG_(clo_xtree_memory) == Vg_XTMemory_Full))
+ VG_(XTMemory_Full_resize_in_place)(oldSizeB, newSizeB, mc->where[0]);
+
mc->szB = newSizeB;
if (newSizeB < oldSizeB) {
MC_(make_mem_noaccess)( p + newSizeB, oldSizeB - newSizeB + rzB );
@@ -1117,6 +1141,25 @@
return True;
}
+static void xtmemory_report_next_block(XT_Allocs* xta, ExeContext** ec_alloc)
+{
+ MC_Chunk* mc = VG_(HT_Next)(MC_(malloc_list));
+ if (mc) {
+ xta->nbytes = mc->szB;
+ xta->nblocks = 1;
+ *ec_alloc = MC_(allocated_at)(mc);
+ } else
+ xta->nblocks = 0;
+}
+
+void MC_(xtmemory_report) ( const HChar* filename, Bool fini )
+{
+ // Make xtmemory_report_next_block ready to be called.
+ VG_(HT_ResetIter)(MC_(malloc_list));
+
+ VG_(XTMemory_report)(filename, fini, xtmemory_report_next_block,
+ VG_(XT_filter_1top_and_maybe_below_main));
+}
/*------------------------------------------------------------*/
/*--- Statistics printing ---*/
diff --git a/memcheck/mc_replace_strmem.c b/memcheck/mc_replace_strmem.c
index 2fddc90..c90574c 100644
--- a/memcheck/mc_replace_strmem.c
+++ b/memcheck/mc_replace_strmem.c
@@ -9,7 +9,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c
index 999276b..8429301 100644
--- a/memcheck/mc_translate.c
+++ b/memcheck/mc_translate.c
@@ -8,7 +8,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -1611,6 +1611,14 @@
return at;
}
+ /* I32 x I32 -> I32 */
+ if (t1 == Ity_I32 && t2 == Ity_I32 && finalVty == Ity_I32) {
+ if (0) VG_(printf)("mkLazy2: I32 x I32 -> I32\n");
+ at = mkUifU(mce, Ity_I32, va1, va2);
+ at = mkPCastTo(mce, Ity_I32, at);
+ return at;
+ }
+
if (0) {
VG_(printf)("mkLazy2 ");
ppIRType(t1);
@@ -3942,6 +3950,16 @@
case Iop_CmpExpD128:
return mkLazy2(mce, Ity_I32, vatom1, vatom2);
+ case Iop_MaxNumF32:
+ case Iop_MinNumF32:
+ /* F32 x F32 -> F32 */
+ return mkLazy2(mce, Ity_I32, vatom1, vatom2);
+
+ case Iop_MaxNumF64:
+ case Iop_MinNumF64:
+ /* F64 x F64 -> F64 */
+ return mkLazy2(mce, Ity_I64, vatom1, vatom2);
+
/* non-FP after here */
case Iop_DivModU64to32:
@@ -5370,7 +5388,7 @@
for (i = 0; d->args[i]; i++) {
IRAtom* arg = d->args[i];
if ( (d->cee->mcx_mask & (1<<i))
- || UNLIKELY(is_IRExpr_VECRET_or_BBPTR(arg)) ) {
+ || UNLIKELY(is_IRExpr_VECRET_or_GSPTR(arg)) ) {
/* ignore this arg */
} else {
here = mkPCastTo( mce, Ity_I32, expr2vbits(mce, arg) );
@@ -6268,7 +6286,7 @@
d = st->Ist.Dirty.details;
for (i = 0; d->args[i]; i++) {
IRAtom* atom = d->args[i];
- if (LIKELY(!is_IRExpr_VECRET_or_BBPTR(atom))) {
+ if (LIKELY(!is_IRExpr_VECRET_or_GSPTR(atom))) {
if (isBogusAtom(atom))
return True;
}
@@ -7273,7 +7291,7 @@
for (i = 0; d->args[i]; i++) {
IRAtom* arg = d->args[i];
if ( (d->cee->mcx_mask & (1<<i))
- || UNLIKELY(is_IRExpr_VECRET_or_BBPTR(arg)) ) {
+ || UNLIKELY(is_IRExpr_VECRET_or_GSPTR(arg)) ) {
/* ignore this arg */
} else {
here = schemeE( mce, arg );
diff --git a/memcheck/memcheck.h b/memcheck/memcheck.h
index 811930e..8450f0b 100644
--- a/memcheck/memcheck.h
+++ b/memcheck/memcheck.h
@@ -13,7 +13,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2000-2015 Julian Seward. All rights reserved.
+ Copyright (C) 2000-2017 Julian Seward. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
diff --git a/memcheck/tests/Makefile.am b/memcheck/tests/Makefile.am
index 252298d..b8529f6 100644
--- a/memcheck/tests/Makefile.am
+++ b/memcheck/tests/Makefile.am
@@ -10,6 +10,12 @@
if VGCONF_ARCHS_INCLUDE_AMD64
SUBDIRS += amd64
endif
+if VGCONF_ARCHS_INCLUDE_MIPS32
+SUBDIRS += mips32
+endif
+if VGCONF_ARCHS_INCLUDE_MIPS64
+SUBDIRS += mips64
+endif
if VGCONF_ARCHS_INCLUDE_PPC32
SUBDIRS += ppc32
endif
@@ -50,7 +56,7 @@
DIST_SUBDIRS = x86 amd64 ppc32 ppc64 s390x linux \
darwin solaris x86-linux amd64-linux arm64-linux \
- x86-solaris amd64-solaris \
+ x86-solaris amd64-solaris mips32 mips64 \
common .
dist_noinst_SCRIPTS = \
@@ -214,11 +220,9 @@
origin5-bz2.stderr.exp-glibc212-s390x \
origin5-bz2.stderr.exp-glibc234-s390x \
origin5-bz2.stderr.exp-glibc218-mips32 \
- origin5-bz2.stderr.exp-glibc212-tilegx \
origin6-fp.vgtest origin6-fp.stdout.exp \
origin6-fp.stderr.exp-glibc25-amd64 \
origin6-fp.stderr.exp-glibc27-ppc64 \
- origin6-fp.stderr.exp-glibc212-tilegx \
overlap.stderr.exp overlap.stdout.exp overlap.vgtest \
partiallydefinedeq.vgtest partiallydefinedeq.stderr.exp \
partiallydefinedeq.stderr.exp4 \
diff --git a/memcheck/tests/Makefile.in b/memcheck/tests/Makefile.in
index 01e2c46..1eaade9 100644
--- a/memcheck/tests/Makefile.in
+++ b/memcheck/tests/Makefile.in
@@ -112,7 +112,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -125,21 +125,23 @@
# Arch-specific tests.
@VGCONF_ARCHS_INCLUDE_X86_TRUE@am__append_8 = x86
@VGCONF_ARCHS_INCLUDE_AMD64_TRUE@am__append_9 = amd64
-@VGCONF_ARCHS_INCLUDE_PPC32_TRUE@am__append_10 = ppc32
-@VGCONF_ARCHS_INCLUDE_PPC64_TRUE@am__append_11 = ppc64
-@VGCONF_ARCHS_INCLUDE_S390X_TRUE@am__append_12 = s390x
+@VGCONF_ARCHS_INCLUDE_MIPS32_TRUE@am__append_10 = mips32
+@VGCONF_ARCHS_INCLUDE_MIPS64_TRUE@am__append_11 = mips64
+@VGCONF_ARCHS_INCLUDE_PPC32_TRUE@am__append_12 = ppc32
+@VGCONF_ARCHS_INCLUDE_PPC64_TRUE@am__append_13 = ppc64
+@VGCONF_ARCHS_INCLUDE_S390X_TRUE@am__append_14 = s390x
# OS-specific tests
-@VGCONF_OS_IS_LINUX_TRUE@am__append_13 = linux
-@VGCONF_OS_IS_DARWIN_TRUE@am__append_14 = darwin
-@VGCONF_OS_IS_SOLARIS_TRUE@am__append_15 = solaris
+@VGCONF_OS_IS_LINUX_TRUE@am__append_15 = linux
+@VGCONF_OS_IS_DARWIN_TRUE@am__append_16 = darwin
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_17 = solaris
# Platform-specific tests
-@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_16 = x86-linux
-@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_17 = amd64-linux
-@VGCONF_PLATFORMS_INCLUDE_ARM64_LINUX_TRUE@am__append_18 = arm64-linux
-@VGCONF_PLATFORMS_INCLUDE_X86_SOLARIS_TRUE@am__append_19 = x86-solaris
-@VGCONF_PLATFORMS_INCLUDE_AMD64_SOLARIS_TRUE@am__append_20 = amd64-solaris
+@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_18 = x86-linux
+@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_19 = amd64-linux
+@VGCONF_PLATFORMS_INCLUDE_ARM64_LINUX_TRUE@am__append_20 = arm64-linux
+@VGCONF_PLATFORMS_INCLUDE_X86_SOLARIS_TRUE@am__append_21 = x86-solaris
+@VGCONF_PLATFORMS_INCLUDE_AMD64_SOLARIS_TRUE@am__append_22 = amd64-solaris
check_PROGRAMS = accounting$(EXEEXT) addressable$(EXEEXT) \
atomic_incs$(EXEEXT) badaddrvalue$(EXEEXT) badfree$(EXEEXT) \
badjump$(EXEEXT) badjump2$(EXEEXT) badloop$(EXEEXT) \
@@ -199,16 +201,16 @@
$(am__EXEEXT_5) $(am__EXEEXT_6) $(am__EXEEXT_7)
# Sun Studio assembler fails on "IDENT too long"
-@SOLARIS_SUN_STUDIO_AS_FALSE@am__append_21 = long_namespace_xml
-@DWARF4_TRUE@am__append_22 = dw4
-@GZ_ZLIB_TRUE@am__append_23 = cdebug_zlib
-@GZ_ZLIB_GNU_TRUE@am__append_24 = cdebug_zlib_gnu
-@HAVE_GNU_STPNCPY_TRUE@am__append_25 = stpncpy
-@HAVE_PTHREAD_SETNAME_NP_TRUE@am__append_26 = threadname
-@HAVE_PTHREAD_BARRIER_TRUE@am__append_27 = reach_thread_register
-@VGCONF_OS_IS_SOLARIS_TRUE@am__append_28 = -std=c99 -D_XOPEN_SOURCE=600
-@VGCONF_OS_IS_SOLARIS_TRUE@am__append_29 = -std=c99 -D__EXTENSIONS__
+@SOLARIS_SUN_STUDIO_AS_FALSE@am__append_23 = long_namespace_xml
+@DWARF4_TRUE@am__append_24 = dw4
+@GZ_ZLIB_TRUE@am__append_25 = cdebug_zlib
+@GZ_ZLIB_GNU_TRUE@am__append_26 = cdebug_zlib_gnu
+@HAVE_GNU_STPNCPY_TRUE@am__append_27 = stpncpy
+@HAVE_PTHREAD_SETNAME_NP_TRUE@am__append_28 = threadname
+@HAVE_PTHREAD_BARRIER_TRUE@am__append_29 = reach_thread_register
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_30 = -std=c99 -D_XOPEN_SOURCE=600
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_31 = -std=c99 -D__EXTENSIONS__
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_32 = -std=c99 -D_XOPEN_SOURCE=600
subdir = memcheck/tests
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/configure.ac
@@ -1030,6 +1032,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -1200,6 +1203,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -1210,6 +1214,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -1284,8 +1289,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -1330,7 +1333,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
@@ -1357,10 +1359,10 @@
$(am__append_11) $(am__append_12) $(am__append_13) \
$(am__append_14) $(am__append_15) $(am__append_16) \
$(am__append_17) $(am__append_18) $(am__append_19) \
- $(am__append_20)
+ $(am__append_20) $(am__append_21) $(am__append_22)
DIST_SUBDIRS = x86 amd64 ppc32 ppc64 s390x linux \
darwin solaris x86-linux amd64-linux arm64-linux \
- x86-solaris amd64-solaris \
+ x86-solaris amd64-solaris mips32 mips64 \
common .
dist_noinst_SCRIPTS = \
@@ -1523,11 +1525,9 @@
origin5-bz2.stderr.exp-glibc212-s390x \
origin5-bz2.stderr.exp-glibc234-s390x \
origin5-bz2.stderr.exp-glibc218-mips32 \
- origin5-bz2.stderr.exp-glibc212-tilegx \
origin6-fp.vgtest origin6-fp.stdout.exp \
origin6-fp.stderr.exp-glibc25-amd64 \
origin6-fp.stderr.exp-glibc27-ppc64 \
- origin6-fp.stderr.exp-glibc212-tilegx \
overlap.stderr.exp overlap.stdout.exp overlap.vgtest \
partiallydefinedeq.vgtest partiallydefinedeq.stderr.exp \
partiallydefinedeq.stderr.exp4 \
@@ -1643,7 +1643,7 @@
descr_belowsp_LDADD = -lpthread
err_disable3_LDADD = -lpthread
err_disable4_LDADD = -lpthread
-err_disable4_CFLAGS = $(AM_CFLAGS) $(am__append_28)
+err_disable4_CFLAGS = $(AM_CFLAGS) $(am__append_30)
reach_thread_register_CFLAGS = $(AM_CFLAGS) -O2
reach_thread_register_LDADD = -lpthread
thread_alloca_LDADD = -lpthread
@@ -1658,7 +1658,7 @@
inltemplate_CXXFLAGS = $(AM_CXXFLAGS) @FLAG_W_NO_UNINITIALIZED@
long_namespace_xml_SOURCES = long_namespace_xml.cpp
manuel1_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_UNINITIALIZED@
-memalign2_CFLAGS = $(AM_CFLAGS) $(am__append_29)
+memalign2_CFLAGS = $(AM_CFLAGS) $(am__append_31)
memcmptest_CFLAGS = $(AM_CFLAGS) -fno-builtin-memcmp
mismatches_SOURCES = mismatches.cpp
mismatches_CXXFLAGS = $(AM_CXXFLAGS) @FLAG_W_NO_MISMATCHED_NEW_DELETE@
@@ -1680,7 +1680,7 @@
# because then we can't intercept it
overlap_CFLAGS = $(AM_CFLAGS) -fno-builtin-memcpy -fno-builtin-strcpy
resvn_stack_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_UNINITIALIZED@
-sendmsg_CFLAGS = $(AM_CFLAGS) $(am__append_30)
+sendmsg_CFLAGS = $(AM_CFLAGS) $(am__append_32)
@VGCONF_OS_IS_SOLARIS_TRUE@sendmsg_LDADD = -lsocket -lnsl
str_tester_CFLAGS = $(AM_CFLAGS) -Wno-shadow \
@FLAG_W_NO_MEMSET_TRANSPOSED_ARGS@
diff --git a/memcheck/tests/amd64-linux/Makefile.am b/memcheck/tests/amd64-linux/Makefile.am
index 56a390b..94f5d0f 100644
--- a/memcheck/tests/amd64-linux/Makefile.am
+++ b/memcheck/tests/amd64-linux/Makefile.am
@@ -23,4 +23,4 @@
AM_CCASFLAGS += @FLAG_M64@
defcfaexpr_SOURCES = defcfaexpr.S
-
+defcfaexpr_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
diff --git a/memcheck/tests/amd64-linux/Makefile.in b/memcheck/tests/amd64-linux/Makefile.in
index e853af3..671174e 100644
--- a/memcheck/tests/amd64-linux/Makefile.in
+++ b/memcheck/tests/amd64-linux/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -139,6 +139,8 @@
am_defcfaexpr_OBJECTS = defcfaexpr.$(OBJEXT)
defcfaexpr_OBJECTS = $(am_defcfaexpr_OBJECTS)
defcfaexpr_LDADD = $(LDADD)
+defcfaexpr_LINK = $(CCLD) $(defcfaexpr_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
int3_amd64_SOURCES = int3-amd64.c
int3_amd64_OBJECTS = int3-amd64.$(OBJEXT)
int3_amd64_LDADD = $(LDADD)
@@ -250,6 +252,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -420,6 +423,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -430,6 +434,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -504,8 +509,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -550,7 +553,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
@@ -584,6 +586,7 @@
int3-amd64.vgtest int3-amd64.stderr.exp int3-amd64.stdout.exp
defcfaexpr_SOURCES = defcfaexpr.S
+defcfaexpr_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
all: all-am
.SUFFIXES:
@@ -628,7 +631,7 @@
defcfaexpr$(EXEEXT): $(defcfaexpr_OBJECTS) $(defcfaexpr_DEPENDENCIES) $(EXTRA_defcfaexpr_DEPENDENCIES)
@rm -f defcfaexpr$(EXEEXT)
- $(AM_V_CCLD)$(LINK) $(defcfaexpr_OBJECTS) $(defcfaexpr_LDADD) $(LIBS)
+ $(AM_V_CCLD)$(defcfaexpr_LINK) $(defcfaexpr_OBJECTS) $(defcfaexpr_LDADD) $(LIBS)
int3-amd64$(EXEEXT): $(int3_amd64_OBJECTS) $(int3_amd64_DEPENDENCIES) $(EXTRA_int3_amd64_DEPENDENCIES)
@rm -f int3-amd64$(EXEEXT)
diff --git a/memcheck/tests/amd64-solaris/Makefile.am b/memcheck/tests/amd64-solaris/Makefile.am
index 4d0ea14..7ed2bc3 100644
--- a/memcheck/tests/amd64-solaris/Makefile.am
+++ b/memcheck/tests/amd64-solaris/Makefile.am
@@ -9,7 +9,8 @@
context_rflags.stderr.exp context_rflags.stdout.exp context_rflags.vgtest \
context_rflags2.stderr.exp context_rflags2.stdout.exp context_rflags2.vgtest \
context_sse.stderr.exp context_sse.stdout.exp context_sse.vgtest \
- ldsoexec.stderr.exp ldsoexec.vgtest
+ ldsoexec.stderr.exp ldsoexec.vgtest \
+ scalar.stderr.exp scalar.stdout.exp scalar.vgtest
check_PROGRAMS = \
context_fpu \
@@ -17,9 +18,11 @@
context_rflags \
context_rflags2 \
context_sse \
- ldsoexec
+ ldsoexec \
+ scalar
AM_CFLAGS += @FLAG_M64@
AM_CXXFLAGS += @FLAG_M64@
AM_CCASFLAGS += @FLAG_M64@
+scalar_CFLAGS = $(AM_CFLAGS) -I../solaris
diff --git a/memcheck/tests/amd64-solaris/Makefile.in b/memcheck/tests/amd64-solaris/Makefile.in
index 65b89be..e07a843 100644
--- a/memcheck/tests/amd64-solaris/Makefile.in
+++ b/memcheck/tests/amd64-solaris/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -122,7 +122,7 @@
@COMPILER_IS_CLANG_TRUE@am__append_7 = -Wno-unused-private-field # drd/tests/tsan_unittest.cpp
check_PROGRAMS = context_fpu$(EXEEXT) context_gpr$(EXEEXT) \
context_rflags$(EXEEXT) context_rflags2$(EXEEXT) \
- context_sse$(EXEEXT) ldsoexec$(EXEEXT)
+ context_sse$(EXEEXT) ldsoexec$(EXEEXT) scalar$(EXEEXT)
subdir = memcheck/tests/amd64-solaris
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/configure.ac
@@ -152,6 +152,11 @@
ldsoexec_SOURCES = ldsoexec.c
ldsoexec_OBJECTS = ldsoexec.$(OBJEXT)
ldsoexec_LDADD = $(LDADD)
+scalar_SOURCES = scalar.c
+scalar_OBJECTS = scalar-scalar.$(OBJEXT)
+scalar_LDADD = $(LDADD)
+scalar_LINK = $(CCLD) $(scalar_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
SCRIPTS = $(dist_noinst_SCRIPTS)
AM_V_P = $(am__v_P_@AM_V@)
am__v_P_ = $(am__v_P_@AM_DEFAULT_V@)
@@ -169,6 +174,10 @@
depcomp = $(SHELL) $(top_srcdir)/depcomp
am__depfiles_maybe = depfiles
am__mv = mv -f
+AM_V_lt = $(am__v_lt_@AM_V@)
+am__v_lt_ = $(am__v_lt_@AM_DEFAULT_V@)
+am__v_lt_0 = --silent
+am__v_lt_1 =
COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
$(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
AM_V_CC = $(am__v_CC_@AM_V@)
@@ -182,9 +191,9 @@
am__v_CCLD_0 = @echo " CCLD " $@;
am__v_CCLD_1 =
SOURCES = context_fpu.c context_gpr.c context_rflags.c \
- context_rflags2.c context_sse.c ldsoexec.c
+ context_rflags2.c context_sse.c ldsoexec.c scalar.c
DIST_SOURCES = context_fpu.c context_gpr.c context_rflags.c \
- context_rflags2.c context_sse.c ldsoexec.c
+ context_rflags2.c context_sse.c ldsoexec.c scalar.c
am__can_run_installinfo = \
case $$AM_UPDATE_INFO_DIR in \
n|no|NO) false;; \
@@ -256,6 +265,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -426,6 +436,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -436,6 +447,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -510,8 +522,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -556,7 +566,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
@@ -585,8 +594,10 @@
context_rflags.stderr.exp context_rflags.stdout.exp context_rflags.vgtest \
context_rflags2.stderr.exp context_rflags2.stdout.exp context_rflags2.vgtest \
context_sse.stderr.exp context_sse.stdout.exp context_sse.vgtest \
- ldsoexec.stderr.exp ldsoexec.vgtest
+ ldsoexec.stderr.exp ldsoexec.vgtest \
+ scalar.stderr.exp scalar.stdout.exp scalar.vgtest
+scalar_CFLAGS = $(AM_CFLAGS) -I../solaris
all: all-am
.SUFFIXES:
@@ -649,6 +660,10 @@
@rm -f ldsoexec$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(ldsoexec_OBJECTS) $(ldsoexec_LDADD) $(LIBS)
+scalar$(EXEEXT): $(scalar_OBJECTS) $(scalar_DEPENDENCIES) $(EXTRA_scalar_DEPENDENCIES)
+ @rm -f scalar$(EXEEXT)
+ $(AM_V_CCLD)$(scalar_LINK) $(scalar_OBJECTS) $(scalar_LDADD) $(LIBS)
+
mostlyclean-compile:
-rm -f *.$(OBJEXT)
@@ -661,6 +676,7 @@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/context_rflags2.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/context_sse.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ldsoexec.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scalar-scalar.Po@am__quote@
.c.o:
@am__fastdepCC_TRUE@ $(AM_V_CC)depbase=`echo $@ | sed 's|[^/]*$$|$(DEPDIR)/&|;s|\.o$$||'`;\
@@ -678,6 +694,20 @@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(COMPILE) -c -o $@ `$(CYGPATH_W) '$<'`
+scalar-scalar.o: scalar.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(scalar_CFLAGS) $(CFLAGS) -MT scalar-scalar.o -MD -MP -MF $(DEPDIR)/scalar-scalar.Tpo -c -o scalar-scalar.o `test -f 'scalar.c' || echo '$(srcdir)/'`scalar.c
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/scalar-scalar.Tpo $(DEPDIR)/scalar-scalar.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='scalar.c' object='scalar-scalar.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(scalar_CFLAGS) $(CFLAGS) -c -o scalar-scalar.o `test -f 'scalar.c' || echo '$(srcdir)/'`scalar.c
+
+scalar-scalar.obj: scalar.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(scalar_CFLAGS) $(CFLAGS) -MT scalar-scalar.obj -MD -MP -MF $(DEPDIR)/scalar-scalar.Tpo -c -o scalar-scalar.obj `if test -f 'scalar.c'; then $(CYGPATH_W) 'scalar.c'; else $(CYGPATH_W) '$(srcdir)/scalar.c'; fi`
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/scalar-scalar.Tpo $(DEPDIR)/scalar-scalar.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='scalar.c' object='scalar-scalar.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(scalar_CFLAGS) $(CFLAGS) -c -o scalar-scalar.obj `if test -f 'scalar.c'; then $(CYGPATH_W) 'scalar.c'; else $(CYGPATH_W) '$(srcdir)/scalar.c'; fi`
+
ID: $(am__tagged_files)
$(am__define_uniq_tagged_files); mkid -fID $$unique
tags: tags-am
diff --git a/memcheck/tests/amd64-solaris/scalar.c b/memcheck/tests/amd64-solaris/scalar.c
new file mode 100644
index 0000000..bcd3139
--- /dev/null
+++ b/memcheck/tests/amd64-solaris/scalar.c
@@ -0,0 +1,18 @@
+/* Basic syscall test for Solaris/amd64 specific syscalls. */
+
+#include "scalar.h"
+
+#include <sys/lwp.h>
+
+int main(void)
+{
+ /* Uninitialised, but we know px[0] is 0x0. */
+ long *px = malloc(sizeof(long));
+ x0 = px[0];
+
+ /* SYS_lwp_private 166 */
+ GO(SYS_lwp_private, "3s 1m");
+ SY(SYS_lwp_private, x0 + _LWP_GETPRIVATE, x0 + _LWP_FSBASE, x0); FAIL;
+
+ return 0;
+}
diff --git a/memcheck/tests/amd64-solaris/scalar.stderr.exp b/memcheck/tests/amd64-solaris/scalar.stderr.exp
new file mode 100644
index 0000000..6287024
--- /dev/null
+++ b/memcheck/tests/amd64-solaris/scalar.stderr.exp
@@ -0,0 +1,16 @@
+---------------------------------------------------------
+166: SYS_lwp_private 3s 1m
+---------------------------------------------------------
+Syscall param lwp_private(cmd) contains uninitialised byte(s)
+ ...
+
+Syscall param lwp_private(which) contains uninitialised byte(s)
+ ...
+
+Syscall param lwp_private(base) contains uninitialised byte(s)
+ ...
+
+Syscall param lwp_private(base) points to unaddressable byte(s)
+ ...
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
diff --git a/memcheck/tests/amd64-solaris/scalar.stdout.exp b/memcheck/tests/amd64-solaris/scalar.stdout.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/memcheck/tests/amd64-solaris/scalar.stdout.exp
diff --git a/memcheck/tests/amd64-solaris/scalar.vgtest b/memcheck/tests/amd64-solaris/scalar.vgtest
new file mode 100644
index 0000000..6509a3e
--- /dev/null
+++ b/memcheck/tests/amd64-solaris/scalar.vgtest
@@ -0,0 +1,3 @@
+prog: scalar
+vgopts: -q
+stderr_filter_args:
diff --git a/memcheck/tests/amd64/Makefile.am b/memcheck/tests/amd64/Makefile.am
index ef085d0..2b28dce 100644
--- a/memcheck/tests/amd64/Makefile.am
+++ b/memcheck/tests/amd64/Makefile.am
@@ -63,6 +63,7 @@
AM_CXXFLAGS += @FLAG_M64@
AM_CCASFLAGS += @FLAG_M64@
+fxsave_amd64_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
insn_pcmpistri_CFLAGS = $(AM_CFLAGS)
if VGCONF_OS_IS_SOLARIS
insn_pcmpistri_CFLAGS += --std=c99
@@ -70,4 +71,4 @@
more_x87_fp_CFLAGS = $(AM_CFLAGS) -O -ffast-math -mfpmath=387 \
-mfancy-math-387
more_x87_fp_LDADD = -lm
-
+shr_edx_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
diff --git a/memcheck/tests/amd64/Makefile.in b/memcheck/tests/amd64/Makefile.in
index 2d5de3e..d7646e9 100644
--- a/memcheck/tests/amd64/Makefile.in
+++ b/memcheck/tests/amd64/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -159,8 +159,10 @@
bug279698_OBJECTS = bug279698.$(OBJEXT)
bug279698_LDADD = $(LDADD)
fxsave_amd64_SOURCES = fxsave-amd64.c
-fxsave_amd64_OBJECTS = fxsave-amd64.$(OBJEXT)
+fxsave_amd64_OBJECTS = fxsave_amd64-fxsave-amd64.$(OBJEXT)
fxsave_amd64_LDADD = $(LDADD)
+fxsave_amd64_LINK = $(CCLD) $(fxsave_amd64_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
insn_bsfl_SOURCES = insn-bsfl.c
insn_bsfl_OBJECTS = insn-bsfl.$(OBJEXT)
insn_bsfl_LDADD = $(LDADD)
@@ -184,8 +186,10 @@
sh_mem_vec256_OBJECTS = sh-mem-vec256.$(OBJEXT)
sh_mem_vec256_LDADD = $(LDADD)
shr_edx_SOURCES = shr_edx.c
-shr_edx_OBJECTS = shr_edx.$(OBJEXT)
+shr_edx_OBJECTS = shr_edx-shr_edx.$(OBJEXT)
shr_edx_LDADD = $(LDADD)
+shr_edx_LINK = $(CCLD) $(shr_edx_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
sse_memory_SOURCES = sse_memory.c
sse_memory_OBJECTS = sse_memory.$(OBJEXT)
sse_memory_LDADD = $(LDADD)
@@ -307,6 +311,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -477,6 +482,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -487,6 +493,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -561,8 +568,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -607,7 +612,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
@@ -662,11 +666,13 @@
xor-undef-amd64.vgtest \
xsave-avx.vgtest xsave-avx.stdout.exp xsave-avx.stderr.exp
+fxsave_amd64_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
insn_pcmpistri_CFLAGS = $(AM_CFLAGS) $(am__append_11)
more_x87_fp_CFLAGS = $(AM_CFLAGS) -O -ffast-math -mfpmath=387 \
-mfancy-math-387
more_x87_fp_LDADD = -lm
+shr_edx_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
all: all-am
.SUFFIXES:
@@ -719,7 +725,7 @@
fxsave-amd64$(EXEEXT): $(fxsave_amd64_OBJECTS) $(fxsave_amd64_DEPENDENCIES) $(EXTRA_fxsave_amd64_DEPENDENCIES)
@rm -f fxsave-amd64$(EXEEXT)
- $(AM_V_CCLD)$(LINK) $(fxsave_amd64_OBJECTS) $(fxsave_amd64_LDADD) $(LIBS)
+ $(AM_V_CCLD)$(fxsave_amd64_LINK) $(fxsave_amd64_OBJECTS) $(fxsave_amd64_LDADD) $(LIBS)
insn-bsfl$(EXEEXT): $(insn_bsfl_OBJECTS) $(insn_bsfl_DEPENDENCIES) $(EXTRA_insn_bsfl_DEPENDENCIES)
@rm -f insn-bsfl$(EXEEXT)
@@ -747,7 +753,7 @@
shr_edx$(EXEEXT): $(shr_edx_OBJECTS) $(shr_edx_DEPENDENCIES) $(EXTRA_shr_edx_DEPENDENCIES)
@rm -f shr_edx$(EXEEXT)
- $(AM_V_CCLD)$(LINK) $(shr_edx_OBJECTS) $(shr_edx_LDADD) $(LIBS)
+ $(AM_V_CCLD)$(shr_edx_LINK) $(shr_edx_OBJECTS) $(shr_edx_LDADD) $(LIBS)
sse_memory$(EXEEXT): $(sse_memory_OBJECTS) $(sse_memory_DEPENDENCIES) $(EXTRA_sse_memory_DEPENDENCIES)
@rm -f sse_memory$(EXEEXT)
@@ -770,14 +776,14 @@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bt_everything.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug132146.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug279698.Po@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fxsave-amd64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fxsave_amd64-fxsave-amd64.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn-bsfl.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn-pmovmskb.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_pcmpistri-insn-pcmpistri.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/more_x87_fp-more_x87_fp.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sh-mem-vec128.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sh-mem-vec256.Po@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/shr_edx.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/shr_edx-shr_edx.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sse_memory.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xor-undef-amd64.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xsave-avx.Po@am__quote@
@@ -798,6 +804,20 @@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(COMPILE) -c -o $@ `$(CYGPATH_W) '$<'`
+fxsave_amd64-fxsave-amd64.o: fxsave-amd64.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fxsave_amd64_CFLAGS) $(CFLAGS) -MT fxsave_amd64-fxsave-amd64.o -MD -MP -MF $(DEPDIR)/fxsave_amd64-fxsave-amd64.Tpo -c -o fxsave_amd64-fxsave-amd64.o `test -f 'fxsave-amd64.c' || echo '$(srcdir)/'`fxsave-amd64.c
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/fxsave_amd64-fxsave-amd64.Tpo $(DEPDIR)/fxsave_amd64-fxsave-amd64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='fxsave-amd64.c' object='fxsave_amd64-fxsave-amd64.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fxsave_amd64_CFLAGS) $(CFLAGS) -c -o fxsave_amd64-fxsave-amd64.o `test -f 'fxsave-amd64.c' || echo '$(srcdir)/'`fxsave-amd64.c
+
+fxsave_amd64-fxsave-amd64.obj: fxsave-amd64.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fxsave_amd64_CFLAGS) $(CFLAGS) -MT fxsave_amd64-fxsave-amd64.obj -MD -MP -MF $(DEPDIR)/fxsave_amd64-fxsave-amd64.Tpo -c -o fxsave_amd64-fxsave-amd64.obj `if test -f 'fxsave-amd64.c'; then $(CYGPATH_W) 'fxsave-amd64.c'; else $(CYGPATH_W) '$(srcdir)/fxsave-amd64.c'; fi`
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/fxsave_amd64-fxsave-amd64.Tpo $(DEPDIR)/fxsave_amd64-fxsave-amd64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='fxsave-amd64.c' object='fxsave_amd64-fxsave-amd64.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fxsave_amd64_CFLAGS) $(CFLAGS) -c -o fxsave_amd64-fxsave-amd64.obj `if test -f 'fxsave-amd64.c'; then $(CYGPATH_W) 'fxsave-amd64.c'; else $(CYGPATH_W) '$(srcdir)/fxsave-amd64.c'; fi`
+
insn_pcmpistri-insn-pcmpistri.o: insn-pcmpistri.c
@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(insn_pcmpistri_CFLAGS) $(CFLAGS) -MT insn_pcmpistri-insn-pcmpistri.o -MD -MP -MF $(DEPDIR)/insn_pcmpistri-insn-pcmpistri.Tpo -c -o insn_pcmpistri-insn-pcmpistri.o `test -f 'insn-pcmpistri.c' || echo '$(srcdir)/'`insn-pcmpistri.c
@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/insn_pcmpistri-insn-pcmpistri.Tpo $(DEPDIR)/insn_pcmpistri-insn-pcmpistri.Po
@@ -826,6 +846,20 @@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(more_x87_fp_CFLAGS) $(CFLAGS) -c -o more_x87_fp-more_x87_fp.obj `if test -f 'more_x87_fp.c'; then $(CYGPATH_W) 'more_x87_fp.c'; else $(CYGPATH_W) '$(srcdir)/more_x87_fp.c'; fi`
+shr_edx-shr_edx.o: shr_edx.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(shr_edx_CFLAGS) $(CFLAGS) -MT shr_edx-shr_edx.o -MD -MP -MF $(DEPDIR)/shr_edx-shr_edx.Tpo -c -o shr_edx-shr_edx.o `test -f 'shr_edx.c' || echo '$(srcdir)/'`shr_edx.c
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/shr_edx-shr_edx.Tpo $(DEPDIR)/shr_edx-shr_edx.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='shr_edx.c' object='shr_edx-shr_edx.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(shr_edx_CFLAGS) $(CFLAGS) -c -o shr_edx-shr_edx.o `test -f 'shr_edx.c' || echo '$(srcdir)/'`shr_edx.c
+
+shr_edx-shr_edx.obj: shr_edx.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(shr_edx_CFLAGS) $(CFLAGS) -MT shr_edx-shr_edx.obj -MD -MP -MF $(DEPDIR)/shr_edx-shr_edx.Tpo -c -o shr_edx-shr_edx.obj `if test -f 'shr_edx.c'; then $(CYGPATH_W) 'shr_edx.c'; else $(CYGPATH_W) '$(srcdir)/shr_edx.c'; fi`
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/shr_edx-shr_edx.Tpo $(DEPDIR)/shr_edx-shr_edx.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='shr_edx.c' object='shr_edx-shr_edx.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(shr_edx_CFLAGS) $(CFLAGS) -c -o shr_edx-shr_edx.obj `if test -f 'shr_edx.c'; then $(CYGPATH_W) 'shr_edx.c'; else $(CYGPATH_W) '$(srcdir)/shr_edx.c'; fi`
+
ID: $(am__tagged_files)
$(am__define_uniq_tagged_files); mkid -fID $$unique
tags: tags-am
diff --git a/memcheck/tests/amd64/sh-mem-vec256.c b/memcheck/tests/amd64/sh-mem-vec256.c
index 5a28e15..d8eb5f1 100644
--- a/memcheck/tests/amd64/sh-mem-vec256.c
+++ b/memcheck/tests/amd64/sh-mem-vec256.c
@@ -8,7 +8,7 @@
static __attribute__((noinline))
void vector_copy ( void* dst, void* src )
{
- /* Note: Verions of GCC through 4.8.1 do not allow "ymm7" in the
+ /* Note: Versions of GCC through 4.8.1 do not allow "ymm7" in the
clobber list. (See http://stackoverflow.com/a/15767111/768469).
Simulate it with "xmm7". */
__asm__ __volatile__(
diff --git a/memcheck/tests/arm64-linux/Makefile.in b/memcheck/tests/arm64-linux/Makefile.in
index 6c07ff9..241a3d1 100644
--- a/memcheck/tests/arm64-linux/Makefile.in
+++ b/memcheck/tests/arm64-linux/Makefile.in
@@ -112,7 +112,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -239,6 +239,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -409,6 +410,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -419,6 +421,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -493,8 +496,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -539,7 +540,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/memcheck/tests/arm64-linux/scalar.c b/memcheck/tests/arm64-linux/scalar.c
index e8f2e43..fd49db6 100644
--- a/memcheck/tests/arm64-linux/scalar.c
+++ b/memcheck/tests/arm64-linux/scalar.c
@@ -279,7 +279,7 @@
// For F_GETLK the 3rd arg is 'lock'. On x86, this fails w/EBADF. But
// on amd64 in 32-bit mode it fails w/EFAULT. We don't check the 1st two
// args for the reason given above.
- GO(__NR_fcntl, "(GETLK) 1s 0m");
+ GO(__NR_fcntl, "(GETLK) 1s 5m");
SY(__NR_fcntl, -1, F_GETLK, x0); FAIL; //FAILx(EBADF);
// __NR_mpx arm64 doesn't implement mpx
@@ -1068,8 +1068,8 @@
#define FUTEX_WAIT 0
#endif
// XXX: again, glibc not doing 6th arg means we have only 5s errors
- GO(__NR_futex, "5s 2m");
- SY(__NR_futex, x0+FUTEX_WAIT, x0, x0, x0+1, x0, x0); FAIL;
+ GO(__NR_futex, "4s 2m");
+ SY(__NR_futex, x0+FUTEX_WAIT, x0, x0, x0+1); FAIL;
// __NR_sched_setaffinity 241
GO(__NR_sched_setaffinity, "3s 1m");
diff --git a/memcheck/tests/arm64-linux/scalar.stderr.exp b/memcheck/tests/arm64-linux/scalar.stderr.exp
index 1dc2035..8f9d8b6 100644
--- a/memcheck/tests/arm64-linux/scalar.stderr.exp
+++ b/memcheck/tests/arm64-linux/scalar.stderr.exp
@@ -271,12 +271,37 @@
by 0x........: main (scalar.c:277)
-----------------------------------------------------
- 25: __NR_fcntl (GETLK) 1s 0m
+ 25: __NR_fcntl (GETLK) 1s 5m
-----------------------------------------------------
Syscall param fcntl(lock) contains uninitialised byte(s)
...
by 0x........: main (scalar.c:283)
+Syscall param fcntl(lock->l_type) points to unaddressable byte(s)
+ ...
+ by 0x........: main (scalar.c:283)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+Syscall param fcntl(lock->l_whence) points to unaddressable byte(s)
+ ...
+ by 0x........: main (scalar.c:283)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+Syscall param fcntl(lock->l_start) points to unaddressable byte(s)
+ ...
+ by 0x........: main (scalar.c:283)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+Syscall param fcntl(lock->l_len) points to unaddressable byte(s)
+ ...
+ by 0x........: main (scalar.c:283)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+Syscall param fcntl(lock->l_pid) points to unaddressable byte(s)
+ ...
+ by 0x........: main (scalar.c:283)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
-----------------------------------------------------
154: __NR_setpgid 2s 0m
-----------------------------------------------------
@@ -555,6 +580,9 @@
...
by 0x........: main (scalar.c:458)
+
+More than 100 errors detected. Subsequent errors
+will still be recorded, but in less detail than before.
Syscall param setpriority(who) contains uninitialised byte(s)
...
by 0x........: main (scalar.c:458)
@@ -579,9 +607,6 @@
by 0x........: main (scalar.c:466)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-
-More than 100 errors detected. Subsequent errors
-will still be recorded, but in less detail than before.
Syscall param statfs(buf) points to unaddressable byte(s)
...
by 0x........: main (scalar.c:466)
@@ -1958,7 +1983,7 @@
130: __NR_tkill n/a
-----------------------------------------------------
-----------------------------------------------------
- 98: __NR_futex 5s 2m
+ 98: __NR_futex 4s 2m
-----------------------------------------------------
Syscall param futex(futex) contains uninitialised byte(s)
...
diff --git a/memcheck/tests/atomic_incs.c b/memcheck/tests/atomic_incs.c
index 8f2c464..1fede8c 100644
--- a/memcheck/tests/atomic_incs.c
+++ b/memcheck/tests/atomic_incs.c
@@ -233,20 +233,6 @@
);
} while (block[2] != 1);
#endif
-#elif defined(VGA_tilegx)
- int i;
- unsigned int *p4 = (unsigned int *)(((unsigned long long)p + 3) & (~3ULL));
- unsigned int mask = (0xff) << ((int)p & 3);
- unsigned int add = (n & 0xff) << ((int)p & 3);
- unsigned int x, new;
-
- while(1) {
- x = *p4;
- new = (x & (~mask)) | ((x + add) & mask);
- __insn_mtspr(0x2780, x);
- if ( __insn_cmpexch4(p4, new) == x)
- break;
- }
#else
# error "Unsupported arch"
#endif
@@ -463,20 +449,6 @@
);
} while (block[2] != 1);
#endif
-#elif defined(VGA_tilegx)
- int i;
- unsigned int *p4 = (unsigned int *)(((unsigned long long)p + 3) & (~3ULL));
- unsigned int mask = (0xffff) << ((int)p & 3);
- unsigned int add = (n & 0xffff) << ((int)p & 3);
- unsigned int x, new;
-
- while(1) {
- x = *p4;
- new = (x & (~mask)) | ((x + add) & mask);
- __insn_mtspr(0x2780, x);
- if ( __insn_cmpexch4(p4, new) == x)
- break;
- }
#else
# error "Unsupported arch"
#endif
@@ -632,8 +604,6 @@
: /*trash*/ "memory", "t0", "t1", "t2", "t3"
);
} while (block[2] != 1);
-#elif defined(VGA_tilegx)
- __insn_fetchadd4(p, n);
#else
# error "Unsupported arch"
#endif
@@ -735,8 +705,6 @@
: /*trash*/ "memory", "t0", "t1", "t2", "t3"
);
} while (block[2] != 1);
-#elif defined(VGA_tilegx)
- __insn_fetchadd(p, n);
#else
# error "Unsupported arch"
#endif
diff --git a/memcheck/tests/common/Makefile.in b/memcheck/tests/common/Makefile.in
index 6bd6527..beedb94 100644
--- a/memcheck/tests/common/Makefile.in
+++ b/memcheck/tests/common/Makefile.in
@@ -110,7 +110,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -196,6 +196,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -366,6 +367,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -376,6 +378,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -450,8 +453,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -496,7 +497,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/memcheck/tests/darwin/Makefile.in b/memcheck/tests/darwin/Makefile.in
index 53efcfe..53cba87 100644
--- a/memcheck/tests/darwin/Makefile.in
+++ b/memcheck/tests/darwin/Makefile.in
@@ -112,7 +112,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -277,6 +277,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -447,6 +448,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -457,6 +459,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -531,8 +534,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -577,7 +578,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/memcheck/tests/darwin/scalar.c b/memcheck/tests/darwin/scalar.c
index af4def4..d74996c 100644
--- a/memcheck/tests/darwin/scalar.c
+++ b/memcheck/tests/darwin/scalar.c
@@ -1654,8 +1654,8 @@
#define FUTEX_WAIT 0
#endif
// XXX: again, glibc not doing 6th arg means we have only 5s errors
- GO(__NR_futex, "5s 2m");
- SY(__NR_futex, x0+FUTEX_WAIT, x0, x0, x0+1, x0, x0); FAIL;
+ GO(__NR_futex, "4s 2m");
+ SY(__NR_futex, x0+FUTEX_WAIT, x0, x0, x0+1); FAIL;
// __NR_sched_setaffinity 241
GO(__NR_sched_setaffinity, "3s 1m");
diff --git a/memcheck/tests/filter_stderr b/memcheck/tests/filter_stderr
index b55f24a..c6f6cd4 100755
--- a/memcheck/tests/filter_stderr
+++ b/memcheck/tests/filter_stderr
@@ -24,6 +24,7 @@
# Filter out glibc debuginfo if installed.
perl -p -e "s/\(syscall-template.S:[0-9]*\)/(in \/...libc...)/" |
+perl -p -e "s/sendmsg \(sendmsg.c:[0-9]*\)/sendmsg (in \/...libc...)/" |
perl -p -e "s/\(socket.S:[0-9]*\)/(in \/...libc...)/" |
# Newer architectures (aarch64) implement poll by calling ppoll directly.
diff --git a/memcheck/tests/leak-segv-jmp.c b/memcheck/tests/leak-segv-jmp.c
index 1d1f84c..2a175c6 100644
--- a/memcheck/tests/leak-segv-jmp.c
+++ b/memcheck/tests/leak-segv-jmp.c
@@ -163,30 +163,6 @@
: "v0", "v1", "a0", "a1", "a2", "a3", "$8", "$9");
return out;
}
-#elif defined(VGP_tilegx_linux)
-extern UWord do_syscall_WRK (
- UWord syscall_no,
- UWord a1, UWord a2, UWord a3,
- UWord a4, UWord a5, UWord a6
- )
-{
- UWord out;
- __asm__ __volatile__ (
- "move r10, %1\n\t"
- "move r0, %2\n\t"
- "move r1, %3\n\t"
- "move r2, %4\n\t"
- "move r3, %5\n\t"
- "move r4, %6\n\t"
- "move r5, %7\n\t"
- "swint1 \n\t"
- "move %0, r0\n\t"
- : /*out*/ "=r" (out)
- : "r"(syscall_no), "r"(a1), "r"(a2), "r"(a3),
- "r"(a4), "r"(a5), "r"(a6)
- : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r10");
- return out;
-}
#elif defined(VGP_x86_solaris)
extern ULong
@@ -287,7 +263,7 @@
long pagesize;
#define RNDPAGEDOWN(a) ((long)a & ~(pagesize-1))
int i;
- const int nr_ptr = (10000 * 4)/sizeof(char*);
+ const int nr_ptr = (10000 * 20)/sizeof(char*);
b10 = calloc (nr_ptr * sizeof(char*), 1);
for (i = 0; i < nr_ptr; i++)
diff --git a/memcheck/tests/leak-segv-jmp.stderr.exp b/memcheck/tests/leak-segv-jmp.stderr.exp
index 1ee37cd..21ef2df 100644
--- a/memcheck/tests/leak-segv-jmp.stderr.exp
+++ b/memcheck/tests/leak-segv-jmp.stderr.exp
@@ -6,7 +6,7 @@
definitely lost: 0 bytes in 0 blocks
indirectly lost: 0 bytes in 0 blocks
possibly lost: 0 bytes in 0 blocks
- still reachable: 41,000 bytes in 2 blocks
+ still reachable: 201,000 bytes in 2 blocks
suppressed: 0 bytes in 0 blocks
Reachable blocks (those to which a pointer was found) are not shown.
To see them, rerun with: --leak-check=full --show-leak-kinds=all
@@ -14,14 +14,14 @@
expecting a leak
1,000 bytes in 1 blocks are definitely lost in loss record ... of ...
at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: f (leak-segv-jmp.c:295)
- by 0x........: main (leak-segv-jmp.c:370)
+ by 0x........: f (leak-segv-jmp.c:271)
+ by 0x........: main (leak-segv-jmp.c:346)
LEAK SUMMARY:
definitely lost: 1,000 bytes in 1 blocks
indirectly lost: 0 bytes in 0 blocks
possibly lost: 0 bytes in 0 blocks
- still reachable: 40,000 bytes in 1 blocks
+ still reachable: 200,000 bytes in 1 blocks
suppressed: 0 bytes in 0 blocks
Reachable blocks (those to which a pointer was found) are not shown.
To see them, rerun with: --leak-check=full --show-leak-kinds=all
@@ -30,14 +30,14 @@
expecting a leak again
1,000 bytes in 1 blocks are definitely lost in loss record ... of ...
at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: f (leak-segv-jmp.c:295)
- by 0x........: main (leak-segv-jmp.c:370)
+ by 0x........: f (leak-segv-jmp.c:271)
+ by 0x........: main (leak-segv-jmp.c:346)
LEAK SUMMARY:
definitely lost: 1,000 bytes in 1 blocks
indirectly lost: 0 bytes in 0 blocks
possibly lost: 0 bytes in 0 blocks
- still reachable: 40,000 bytes in 1 blocks
+ still reachable: 200,000 bytes in 1 blocks
suppressed: 0 bytes in 0 blocks
Reachable blocks (those to which a pointer was found) are not shown.
To see them, rerun with: --leak-check=full --show-leak-kinds=all
@@ -46,14 +46,14 @@
expecting a leak again after full mprotect
1,000 bytes in 1 blocks are definitely lost in loss record ... of ...
at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: f (leak-segv-jmp.c:295)
- by 0x........: main (leak-segv-jmp.c:370)
+ by 0x........: f (leak-segv-jmp.c:271)
+ by 0x........: main (leak-segv-jmp.c:346)
LEAK SUMMARY:
definitely lost: 1,000 bytes in 1 blocks
indirectly lost: 0 bytes in 0 blocks
possibly lost: 0 bytes in 0 blocks
- still reachable: 40,000 bytes in 1 blocks
+ still reachable: 200,000 bytes in 1 blocks
suppressed: 0 bytes in 0 blocks
Reachable blocks (those to which a pointer was found) are not shown.
To see them, rerun with: --leak-check=full --show-leak-kinds=all
@@ -62,19 +62,19 @@
expecting heuristic not to crash after full mprotect
1,000 bytes in 1 blocks are definitely lost in loss record ... of ...
at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: f (leak-segv-jmp.c:295)
- by 0x........: main (leak-segv-jmp.c:370)
+ by 0x........: f (leak-segv-jmp.c:271)
+ by 0x........: main (leak-segv-jmp.c:346)
-40,000 bytes in 1 blocks are possibly lost in loss record ... of ...
+200,000 bytes in 1 blocks are possibly lost in loss record ... of ...
at 0x........: calloc (vg_replace_malloc.c:...)
- by 0x........: f (leak-segv-jmp.c:342)
- by 0x........: main (leak-segv-jmp.c:370)
+ by 0x........: f (leak-segv-jmp.c:318)
+ by 0x........: main (leak-segv-jmp.c:346)
LEAK SUMMARY:
definitely lost: 1,000 bytes in 1 blocks
indirectly lost: 0 bytes in 0 blocks
- possibly lost: 40,000 bytes in 1 blocks
- still reachable: 40,000 bytes in 1 blocks
+ possibly lost: 200,000 bytes in 1 blocks
+ still reachable: 200,000 bytes in 1 blocks
suppressed: 0 bytes in 0 blocks
Reachable blocks (those to which a pointer was found) are not shown.
To see them, rerun with: --leak-check=full --show-leak-kinds=all
@@ -83,19 +83,19 @@
LEAK SUMMARY:
definitely lost: 1,000 bytes in 1 blocks
indirectly lost: 0 bytes in 0 blocks
- possibly lost: 40,000 bytes in 1 blocks
- still reachable: 40,000 bytes in 1 blocks
+ possibly lost: 200,000 bytes in 1 blocks
+ still reachable: 200,000 bytes in 1 blocks
suppressed: 0 bytes in 0 blocks
Rerun with --leak-check=full to see details of leaked memory
leaked: 1000 bytes in 1 blocks
-dubious: 40000 bytes in 1 blocks
-reachable: 40000 bytes in 1 blocks
+dubious: 200000 bytes in 1 blocks
+reachable: 200000 bytes in 1 blocks
suppressed: 0 bytes in 0 blocks
HEAP SUMMARY:
- in use at exit: 81,000 bytes in 3 blocks
- total heap usage: 3 allocs, 0 frees, 81,000 bytes allocated
+ in use at exit: 401,000 bytes in 3 blocks
+ total heap usage: 3 allocs, 0 frees, 401,000 bytes allocated
For a detailed leak analysis, rerun with: --leak-check=full
diff --git a/memcheck/tests/leak-tree.c b/memcheck/tests/leak-tree.c
index 99575f9..59b1ccd 100644
--- a/memcheck/tests/leak-tree.c
+++ b/memcheck/tests/leak-tree.c
@@ -62,6 +62,7 @@
// See leak-cases.c for why we do the work in f().
f();
+ CLEAR_CALLER_SAVED_REGS;
GET_FINAL_LEAK_COUNTS;
PRINT_LEAK_COUNTS(stderr);
diff --git a/memcheck/tests/leak.h b/memcheck/tests/leak.h
index ac8a64c..7809ace 100644
--- a/memcheck/tests/leak.h
+++ b/memcheck/tests/leak.h
@@ -60,6 +60,60 @@
__asm__ __volatile__( "li 11, 0" : : :/*trash*/"r11" ); \
__asm__ __volatile__( "li 12, 0" : : :/*trash*/"r12" ); \
} while (0)
+#elif (__mips == 32)
+#define CLEAR_CALLER_SAVED_REGS \
+ do { \
+ __asm__ __volatile__ (".set push \n\t" \
+ ".set noat \n\t" \
+ "move $1, $0 \n\t" /* at = 0 */ \
+ "move $2, $0 \n\t" /* v0 = 0 */ \
+ "move $3, $0 \n\t" /* v1 = 0 */ \
+ "move $4, $0 \n\t" /* a0 = 0 */ \
+ "move $5, $0 \n\t" /* a1 = 0 */ \
+ "move $6, $0 \n\t" /* a2 = 0 */ \
+ "move $7, $0 \n\t" /* a3 = 0 */ \
+ "move $8, $0 \n\t" /* t0 = 0 */ \
+ "move $9, $0 \n\t" /* t1 = 0 */ \
+ "move $10, $0 \n\t" /* t2 = 0 */ \
+ "move $11, $0 \n\t" /* t3 = 0 */ \
+ "move $12, $0 \n\t" /* t4 = 0 */ \
+ "move $13, $0 \n\t" /* t5 = 0 */ \
+ "move $14, $0 \n\t" /* t6 = 0 */ \
+ "move $15, $0 \n\t" /* t7 = 0 */ \
+ "move $24, $0 \n\t" /* t8 = 0 */ \
+ "move $25, $0 \n\t" /* t9 = 0 */ \
+ ".set pop \n\t" \
+ : : : "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
+ "$8", "$9", "$10", "$11", "$12", "$13", \
+ "$14", "$15", "$24", "$25"); \
+ } while (0)
+#elif (__mips == 64)
+#define CLEAR_CALLER_SAVED_REGS \
+ do { \
+ __asm__ __volatile__ (".set push \n\t" \
+ ".set noat \n\t" \
+ "move $1, $0 \n\t" /* at = 0 */ \
+ "move $2, $0 \n\t" /* v0 = 0 */ \
+ "move $3, $0 \n\t" /* v1 = 0 */ \
+ "move $4, $0 \n\t" /* a0 = 0 */ \
+ "move $5, $0 \n\t" /* a1 = 0 */ \
+ "move $6, $0 \n\t" /* a2 = 0 */ \
+ "move $7, $0 \n\t" /* a3 = 0 */ \
+ "move $8, $0 \n\t" /* a4 = 0 */ \
+ "move $9, $0 \n\t" /* a5 = 0 */ \
+ "move $10, $0 \n\t" /* a6 = 0 */ \
+ "move $11, $0 \n\t" /* a7 = 0 */ \
+ "move $12, $0 \n\t" /* t0 = 0 */ \
+ "move $13, $0 \n\t" /* t1 = 0 */ \
+ "move $14, $0 \n\t" /* t2 = 0 */ \
+ "move $15, $0 \n\t" /* t3 = 0 */ \
+ "move $24, $0 \n\t" /* t8 = 0 */ \
+ "move $25, $0 \n\t" /* t9 = 0 */ \
+ ".set pop \n\t" \
+ : : : "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
+ "$8", "$9", "$10", "$11", "$12", "$13", \
+ "$14", "$15", "$24", "$25"); \
+ } while (0)
#else
#define CLEAR_CALLER_SAVED_REGS /*nothing*/
#endif
diff --git a/memcheck/tests/leak_cpp_interior.cpp b/memcheck/tests/leak_cpp_interior.cpp
index f66fc89..a4b4824 100644
--- a/memcheck/tests/leak_cpp_interior.cpp
+++ b/memcheck/tests/leak_cpp_interior.cpp
@@ -1,3 +1,4 @@
+#define _GLIBCXX_USE_CXX11_ABI 0
#define __STDC_FORMAT_MACROS
#include <inttypes.h>
#include <stdio.h>
diff --git a/memcheck/tests/leak_cpp_interior.stderr.exp b/memcheck/tests/leak_cpp_interior.stderr.exp
index 3228f74..70e2764 100644
--- a/memcheck/tests/leak_cpp_interior.stderr.exp
+++ b/memcheck/tests/leak_cpp_interior.stderr.exp
@@ -2,8 +2,8 @@
valgrind output will go to log
VALGRIND_DO_LEAK_CHECK
4 bytes in 1 blocks are definitely lost in loss record ... of ...
- by 0x........: doit() (leak_cpp_interior.cpp:115)
- by 0x........: main (leak_cpp_interior.cpp:130)
+ by 0x........: doit() (leak_cpp_interior.cpp:116)
+ by 0x........: main (leak_cpp_interior.cpp:131)
LEAK SUMMARY:
definitely lost: 4 bytes in 1 blocks
diff --git a/memcheck/tests/leak_cpp_interior.stderr.exp-64bit b/memcheck/tests/leak_cpp_interior.stderr.exp-64bit
index 7a862a3..612fa3e 100644
--- a/memcheck/tests/leak_cpp_interior.stderr.exp-64bit
+++ b/memcheck/tests/leak_cpp_interior.stderr.exp-64bit
@@ -2,8 +2,8 @@
valgrind output will go to log
VALGRIND_DO_LEAK_CHECK
8 bytes in 1 blocks are definitely lost in loss record ... of ...
- by 0x........: doit() (leak_cpp_interior.cpp:115)
- by 0x........: main (leak_cpp_interior.cpp:130)
+ by 0x........: doit() (leak_cpp_interior.cpp:116)
+ by 0x........: main (leak_cpp_interior.cpp:131)
LEAK SUMMARY:
definitely lost: 8 bytes in 1 blocks
diff --git a/memcheck/tests/leak_cpp_interior.stderr.exp-64bit-solaris b/memcheck/tests/leak_cpp_interior.stderr.exp-64bit-solaris
index d53e4ce..f7e1a07 100644
--- a/memcheck/tests/leak_cpp_interior.stderr.exp-64bit-solaris
+++ b/memcheck/tests/leak_cpp_interior.stderr.exp-64bit-solaris
@@ -2,8 +2,8 @@
valgrind output will go to log
VALGRIND_DO_LEAK_CHECK
8 bytes in 1 blocks are definitely lost in loss record ... of ...
- by 0x........: doit() (leak_cpp_interior.cpp:115)
- by 0x........: main (leak_cpp_interior.cpp:130)
+ by 0x........: doit() (leak_cpp_interior.cpp:116)
+ by 0x........: main (leak_cpp_interior.cpp:131)
LEAK SUMMARY:
definitely lost: 8 bytes in 1 blocks
diff --git a/memcheck/tests/leak_cpp_interior.stderr.exp-solaris b/memcheck/tests/leak_cpp_interior.stderr.exp-solaris
index 80cd5c3..f9fc390 100644
--- a/memcheck/tests/leak_cpp_interior.stderr.exp-solaris
+++ b/memcheck/tests/leak_cpp_interior.stderr.exp-solaris
@@ -2,8 +2,8 @@
valgrind output will go to log
VALGRIND_DO_LEAK_CHECK
4 bytes in 1 blocks are definitely lost in loss record ... of ...
- by 0x........: doit() (leak_cpp_interior.cpp:115)
- by 0x........: main (leak_cpp_interior.cpp:130)
+ by 0x........: doit() (leak_cpp_interior.cpp:116)
+ by 0x........: main (leak_cpp_interior.cpp:131)
LEAK SUMMARY:
definitely lost: 4 bytes in 1 blocks
diff --git a/memcheck/tests/linux/Makefile.in b/memcheck/tests/linux/Makefile.in
index ebaa9c2..ed3b387 100644
--- a/memcheck/tests/linux/Makefile.in
+++ b/memcheck/tests/linux/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -292,6 +292,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -462,6 +463,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -472,6 +474,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -546,8 +549,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -592,7 +593,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/memcheck/tests/linux/brk.stderr.exp b/memcheck/tests/linux/brk.stderr.exp
index 8cbe622..ff83c1f 100644
--- a/memcheck/tests/linux/brk.stderr.exp
+++ b/memcheck/tests/linux/brk.stderr.exp
@@ -1,8 +1,7 @@
brk segment overflow in thread #1: can't grow to 0x........
(see section Limitations in user manual)
-brk segment overflow in thread #1: can't grow to 0x........
-(see section Limitations in user manual)
+NOTE: further instances of this message will not be shown
HEAP SUMMARY:
in use at exit: ... bytes in ... blocks
diff --git a/memcheck/tests/linux/getregset.vgtest b/memcheck/tests/linux/getregset.vgtest
index 1bd6ef0..4c66108 100644
--- a/memcheck/tests/linux/getregset.vgtest
+++ b/memcheck/tests/linux/getregset.vgtest
@@ -1,4 +1,4 @@
prog: getregset
vgopts: -q
-prereq: ../../../tests/os_test linux 2.6.33 && ! ../../../tests/arch_test mips32 && ! ../../../tests/arch_test ppc64
+prereq: ((../../../tests/os_test linux 2.6.33 && ! ../../../tests/arch_test mips32) || ../../../tests/os_test linux 3.10.0 ) && ! ../../../tests/arch_test ppc64
diff --git a/memcheck/tests/memalign2.c b/memcheck/tests/memalign2.c
index b35a70e..39069a6 100644
--- a/memcheck/tests/memalign2.c
+++ b/memcheck/tests/memalign2.c
@@ -36,9 +36,9 @@
// if the superblock is used to provide a big aligned block
// (see bug 250101, comment #14).
// Valgrind m_mallocfree.c will allocate a big superblock for the memalign
- // call and will split it in two. This splitted superblock was
+ // call and will split it in two. This split superblock was
// wrongly marked as reclaimable, which was then causing
- // assert failures (as reclaimable blocks cannot be splitted).
+ // assert failures (as reclaimable blocks cannot be split).
p = memalign(1024 * 1024, 4 * 1024 * 1024 + 1); assert(0 == (long)p % (1024 * 1024));
// We allocate (and then free) a piece of memory smaller than
// the hole created in the big superblock.
diff --git a/memcheck/tests/mempool2.c b/memcheck/tests/mempool2.c
index 8fa3d5c..4c8683c 100644
--- a/memcheck/tests/mempool2.c
+++ b/memcheck/tests/mempool2.c
@@ -141,22 +141,26 @@
res += x2[20]; // invalid
fprintf(stderr,
+ "\n------ Illegal memory pool address ------\n\n");
+ VALGRIND_MEMPOOL_FREE(p1, x1); // Should be p1->mem
+
+ fprintf(stderr,
"\n------ read free in malloc-backed pool ------\n\n");
- VALGRIND_MEMPOOL_FREE(p1, x1);
+ VALGRIND_MEMPOOL_FREE(p1->mem, x1);
res += x1[5];
fprintf(stderr,
"\n------ read free in mmap-backed pool ------\n\n");
- VALGRIND_MEMPOOL_FREE(p2, x2);
+ VALGRIND_MEMPOOL_FREE(p2->mem, x2);
res += x2[11];
fprintf(stderr,
"\n------ double free in malloc-backed pool ------\n\n");
- VALGRIND_MEMPOOL_FREE(p1, x1);
+ VALGRIND_MEMPOOL_FREE(p1->mem, x1);
fprintf(stderr,
"\n------ double free in mmap-backed pool ------\n\n");
- VALGRIND_MEMPOOL_FREE(p2, x2);
+ VALGRIND_MEMPOOL_FREE(p2->mem, x2);
{
// test that redzone are still protected even if the user forgets
diff --git a/memcheck/tests/mempool2.stderr.exp b/memcheck/tests/mempool2.stderr.exp
index 16b1f38..8dda2ce 100644
--- a/memcheck/tests/mempool2.stderr.exp
+++ b/memcheck/tests/mempool2.stderr.exp
@@ -3,95 +3,119 @@
Invalid read of size 1
at 0x........: test (mempool2.c:135)
- by 0x........: main (mempool2.c:196)
+ by 0x........: main (mempool2.c:200)
Address 0x........ is 1 bytes before a block of size 10 client-defined
at 0x........: allocate (mempool2.c:108)
by 0x........: test (mempool2.c:130)
- by 0x........: main (mempool2.c:196)
+ by 0x........: main (mempool2.c:200)
Invalid read of size 1
at 0x........: test (mempool2.c:136)
- by 0x........: main (mempool2.c:196)
+ by 0x........: main (mempool2.c:200)
Address 0x........ is 0 bytes after a block of size 10 client-defined
at 0x........: allocate (mempool2.c:108)
by 0x........: test (mempool2.c:130)
- by 0x........: main (mempool2.c:196)
+ by 0x........: main (mempool2.c:200)
------ out of range reads in mmap-backed pool ------
Invalid read of size 1
at 0x........: test (mempool2.c:140)
- by 0x........: main (mempool2.c:196)
+ by 0x........: main (mempool2.c:200)
Address 0x........ is 1 bytes before a block of size 20 client-defined
at 0x........: allocate (mempool2.c:108)
by 0x........: test (mempool2.c:131)
- by 0x........: main (mempool2.c:196)
+ by 0x........: main (mempool2.c:200)
Invalid read of size 1
at 0x........: test (mempool2.c:141)
- by 0x........: main (mempool2.c:196)
+ by 0x........: main (mempool2.c:200)
Address 0x........ is 0 bytes after a block of size 20 client-defined
at 0x........: allocate (mempool2.c:108)
by 0x........: test (mempool2.c:131)
- by 0x........: main (mempool2.c:196)
+ by 0x........: main (mempool2.c:200)
+
+
+------ Illegal memory pool address ------
+
+Illegal memory pool address
+ at 0x........: test (mempool2.c:145)
+ by 0x........: main (mempool2.c:200)
+ Address 0x........ is 0 bytes inside a block of size 32 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: make_pool (mempool2.c:46)
+ by 0x........: test (mempool2.c:122)
+ by 0x........: main (mempool2.c:200)
------ read free in malloc-backed pool ------
-Illegal memory pool address
- at 0x........: test (mempool2.c:145)
- by 0x........: main (mempool2.c:196)
- Address 0x........ is 0 bytes inside a block of size 32 alloc'd
+Invalid read of size 1
+ at 0x........: test (mempool2.c:150)
+ by 0x........: main (mempool2.c:200)
+ Address 0x........ is 13 bytes inside a recently re-allocated block of size 100,000 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: make_pool (mempool2.c:46)
+ by 0x........: make_pool (mempool2.c:47)
by 0x........: test (mempool2.c:122)
- by 0x........: main (mempool2.c:196)
+ by 0x........: main (mempool2.c:200)
------ read free in mmap-backed pool ------
-Illegal memory pool address
- at 0x........: test (mempool2.c:150)
- by 0x........: main (mempool2.c:196)
- Address 0x........ is in a rwx anonymous segment
+Invalid read of size 1
+ at 0x........: test (mempool2.c:155)
+ by 0x........: main (mempool2.c:200)
+ Address 0x........ is 11 bytes inside a block of size 20 free'd
+ at 0x........: test (mempool2.c:154)
+ by 0x........: main (mempool2.c:200)
+ Block was alloc'd at
+ at 0x........: allocate (mempool2.c:108)
+ by 0x........: test (mempool2.c:131)
+ by 0x........: main (mempool2.c:200)
------ double free in malloc-backed pool ------
-Illegal memory pool address
- at 0x........: test (mempool2.c:155)
- by 0x........: main (mempool2.c:196)
- Address 0x........ is 0 bytes inside a block of size 32 alloc'd
+Invalid free() / delete / delete[] / realloc()
+ at 0x........: test (mempool2.c:159)
+ by 0x........: main (mempool2.c:200)
+ Address 0x........ is 8 bytes inside a recently re-allocated block of size 100,000 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: make_pool (mempool2.c:46)
+ by 0x........: make_pool (mempool2.c:47)
by 0x........: test (mempool2.c:122)
- by 0x........: main (mempool2.c:196)
+ by 0x........: main (mempool2.c:200)
------ double free in mmap-backed pool ------
-Illegal memory pool address
- at 0x........: test (mempool2.c:159)
- by 0x........: main (mempool2.c:196)
- Address 0x........ is in a rwx anonymous segment
+Invalid free() / delete / delete[] / realloc()
+ at 0x........: test (mempool2.c:163)
+ by 0x........: main (mempool2.c:200)
+ Address 0x........ is 0 bytes inside a block of size 20 free'd
+ at 0x........: test (mempool2.c:154)
+ by 0x........: main (mempool2.c:200)
+ Block was alloc'd at
+ at 0x........: allocate (mempool2.c:108)
+ by 0x........: test (mempool2.c:131)
+ by 0x........: main (mempool2.c:200)
------ 2 invalid access in 'no no-access superblock' ---
Invalid read of size 1
- at 0x........: test (mempool2.c:178)
- by 0x........: main (mempool2.c:196)
+ at 0x........: test (mempool2.c:182)
+ by 0x........: main (mempool2.c:200)
Address 0x........ is 1 bytes before a block of size 10 client-defined
- at 0x........: test (mempool2.c:171)
- by 0x........: main (mempool2.c:196)
+ at 0x........: test (mempool2.c:175)
+ by 0x........: main (mempool2.c:200)
Invalid read of size 1
- at 0x........: test (mempool2.c:179)
- by 0x........: main (mempool2.c:196)
+ at 0x........: test (mempool2.c:183)
+ by 0x........: main (mempool2.c:200)
Address 0x........ is 0 bytes after a block of size 10 client-defined
- at 0x........: test (mempool2.c:171)
- by 0x........: main (mempool2.c:196)
+ at 0x........: test (mempool2.c:175)
+ by 0x........: main (mempool2.c:200)
------ done ------
diff --git a/memcheck/tests/mips32/Makefile.am b/memcheck/tests/mips32/Makefile.am
new file mode 100644
index 0000000..9413788
--- /dev/null
+++ b/memcheck/tests/mips32/Makefile.am
@@ -0,0 +1,11 @@
+
+include $(top_srcdir)/Makefile.tool-tests.am
+
+dist_noinst_SCRIPTS = \
+ filter_stderr
+
+EXTRA_DIST = $(noinst_SCRIPTS) \
+ fadvise64.stderr.exp fadvise64.stdout.exp fadvise64.vgtest
+
+check_PROGRAMS = \
+ fadvise64
diff --git a/memcheck/tests/mips32/Makefile.in b/memcheck/tests/mips32/Makefile.in
new file mode 100644
index 0000000..d0bfe71
--- /dev/null
+++ b/memcheck/tests/mips32/Makefile.in
@@ -0,0 +1,923 @@
+# Makefile.in generated by automake 1.15 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994-2014 Free Software Foundation, Inc.
+
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+am__is_gnu_make = { \
+ if test -z '$(MAKELEVEL)'; then \
+ false; \
+ elif test -n '$(MAKE_HOST)'; then \
+ true; \
+ elif test -n '$(MAKE_VERSION)' && test -n '$(CURDIR)'; then \
+ true; \
+ else \
+ false; \
+ fi; \
+}
+am__make_running_with_option = \
+ case $${target_option-} in \
+ ?) ;; \
+ *) echo "am__make_running_with_option: internal error: invalid" \
+ "target option '$${target_option-}' specified" >&2; \
+ exit 1;; \
+ esac; \
+ has_opt=no; \
+ sane_makeflags=$$MAKEFLAGS; \
+ if $(am__is_gnu_make); then \
+ sane_makeflags=$$MFLAGS; \
+ else \
+ case $$MAKEFLAGS in \
+ *\\[\ \ ]*) \
+ bs=\\; \
+ sane_makeflags=`printf '%s\n' "$$MAKEFLAGS" \
+ | sed "s/$$bs$$bs[$$bs $$bs ]*//g"`;; \
+ esac; \
+ fi; \
+ skip_next=no; \
+ strip_trailopt () \
+ { \
+ flg=`printf '%s\n' "$$flg" | sed "s/$$1.*$$//"`; \
+ }; \
+ for flg in $$sane_makeflags; do \
+ test $$skip_next = yes && { skip_next=no; continue; }; \
+ case $$flg in \
+ *=*|--*) continue;; \
+ -*I) strip_trailopt 'I'; skip_next=yes;; \
+ -*I?*) strip_trailopt 'I';; \
+ -*O) strip_trailopt 'O'; skip_next=yes;; \
+ -*O?*) strip_trailopt 'O';; \
+ -*l) strip_trailopt 'l'; skip_next=yes;; \
+ -*l?*) strip_trailopt 'l';; \
+ -[dEDm]) skip_next=yes;; \
+ -[JT]) skip_next=yes;; \
+ esac; \
+ case $$flg in \
+ *$$target_option*) has_opt=yes; break;; \
+ esac; \
+ done; \
+ test $$has_opt = yes
+am__make_dryrun = (target_option=n; $(am__make_running_with_option))
+am__make_keepgoing = (target_option=k; $(am__make_running_with_option))
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+@COMPILER_IS_CLANG_TRUE@am__append_1 = -Wno-cast-align -Wno-self-assign \
+@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-compare
+
+@SOLARIS_XPG_SYMBOLS_PRESENT_TRUE@am__append_2 = -Wl,-M,$(top_srcdir)/solaris/vgpreload-solaris.mapfile
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_3 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_4 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+
+# Make sure that all test programs have threaded errno.
+# Disable largefile support as there are test cases explicitly enabling it.
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
+@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
+@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
+@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-constant-out-of-range-compare \
+@COMPILER_IS_CLANG_TRUE@ -Wno-self-assign -Wno-string-plus-int \
+@COMPILER_IS_CLANG_TRUE@ -Wno-uninitialized -Wno-unused-value # \
+@COMPILER_IS_CLANG_TRUE@ clang 3.0.0
+@COMPILER_IS_CLANG_TRUE@am__append_7 = -Wno-unused-private-field # drd/tests/tsan_unittest.cpp
+check_PROGRAMS = fadvise64$(EXEEXT)
+subdir = memcheck/tests/mips32
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.ac
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+DIST_COMMON = $(srcdir)/Makefile.am $(dist_noinst_SCRIPTS) \
+ $(am__DIST_COMMON)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+fadvise64_SOURCES = fadvise64.c
+fadvise64_OBJECTS = fadvise64.$(OBJEXT)
+fadvise64_LDADD = $(LDADD)
+SCRIPTS = $(dist_noinst_SCRIPTS)
+AM_V_P = $(am__v_P_@AM_V@)
+am__v_P_ = $(am__v_P_@AM_DEFAULT_V@)
+am__v_P_0 = false
+am__v_P_1 = :
+AM_V_GEN = $(am__v_GEN_@AM_V@)
+am__v_GEN_ = $(am__v_GEN_@AM_DEFAULT_V@)
+am__v_GEN_0 = @echo " GEN " $@;
+am__v_GEN_1 =
+AM_V_at = $(am__v_at_@AM_V@)
+am__v_at_ = $(am__v_at_@AM_DEFAULT_V@)
+am__v_at_0 = @
+am__v_at_1 =
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+AM_V_CC = $(am__v_CC_@AM_V@)
+am__v_CC_ = $(am__v_CC_@AM_DEFAULT_V@)
+am__v_CC_0 = @echo " CC " $@;
+am__v_CC_1 =
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+AM_V_CCLD = $(am__v_CCLD_@AM_V@)
+am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@)
+am__v_CCLD_0 = @echo " CCLD " $@;
+am__v_CCLD_1 =
+SOURCES = fadvise64.c
+DIST_SOURCES = fadvise64.c
+am__can_run_installinfo = \
+ case $$AM_UPDATE_INFO_DIR in \
+ n|no|NO) false;; \
+ *) (install-info --version) >/dev/null 2>&1;; \
+ esac
+am__tagged_files = $(HEADERS) $(SOURCES) $(TAGS_FILES) $(LISP)
+# Read a list of newline-separated strings from the standard input,
+# and print each of them once, without duplicates. Input order is
+# *not* preserved.
+am__uniquify_input = $(AWK) '\
+ BEGIN { nonempty = 0; } \
+ { items[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in items) print i; }; } \
+'
+# Make sure the list of sources is unique. This is necessary because,
+# e.g., the same source file might be shared among _SOURCES variables
+# for different programs/libraries.
+am__define_uniq_tagged_files = \
+ list='$(am__tagged_files)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | $(am__uniquify_input)`
+ETAGS = etags
+CTAGS = ctags
+am__DIST_COMMON = $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/depcomp
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AM_DEFAULT_VERBOSITY = @AM_DEFAULT_VERBOSITY@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
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+DIFF = @DIFF@
+DIS_PATH = @DIS_PATH@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_IPA_ICF = @FLAG_FNO_IPA_ICF@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_FSANITIZE = @FLAG_FSANITIZE@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MIPS32 = @FLAG_MIPS32@
+FLAG_MIPS64 = @FLAG_MIPS64@
+FLAG_MLONG_DOUBLE_128 = @FLAG_MLONG_DOUBLE_128@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
+FLAG_OCTEON = @FLAG_OCTEON@
+FLAG_OCTEON2 = @FLAG_OCTEON2@
+FLAG_T_TEXT = @FLAG_T_TEXT@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_CAST_ALIGN = @FLAG_W_CAST_ALIGN@
+FLAG_W_CAST_QUAL = @FLAG_W_CAST_QUAL@
+FLAG_W_EMPTY_BODY = @FLAG_W_EMPTY_BODY@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_FORMAT = @FLAG_W_FORMAT@
+FLAG_W_FORMAT_SECURITY = @FLAG_W_FORMAT_SECURITY@
+FLAG_W_FORMAT_SIGNEDNESS = @FLAG_W_FORMAT_SIGNEDNESS@
+FLAG_W_IGNORED_QUALIFIERS = @FLAG_W_IGNORED_QUALIFIERS@
+FLAG_W_MISSING_PARAMETER_TYPE = @FLAG_W_MISSING_PARAMETER_TYPE@
+FLAG_W_NO_INFINITE_RECURSION = @FLAG_W_NO_INFINITE_RECURSION@
+FLAG_W_NO_MEMSET_TRANSPOSED_ARGS = @FLAG_W_NO_MEMSET_TRANSPOSED_ARGS@
+FLAG_W_NO_MISMATCHED_NEW_DELETE = @FLAG_W_NO_MISMATCHED_NEW_DELETE@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_POINTER_SIGN = @FLAG_W_NO_POINTER_SIGN@
+FLAG_W_NO_STATIC_LOCAL_IN_INLINE = @FLAG_W_NO_STATIC_LOCAL_IN_INLINE@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+FLAG_W_NO_UNUSED_FUNCTION = @FLAG_W_NO_UNUSED_FUNCTION@
+FLAG_W_OLD_STYLE_DECLARATION = @FLAG_W_OLD_STYLE_DECLARATION@
+FLAG_W_WRITE_STRINGS = @FLAG_W_WRITE_STRINGS@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+HWCAP_HAS_ALTIVEC = @HWCAP_HAS_ALTIVEC@
+HWCAP_HAS_DFP = @HWCAP_HAS_DFP@
+HWCAP_HAS_HTM = @HWCAP_HAS_HTM@
+HWCAP_HAS_ISA_2_05 = @HWCAP_HAS_ISA_2_05@
+HWCAP_HAS_ISA_2_06 = @HWCAP_HAS_ISA_2_06@
+HWCAP_HAS_ISA_2_07 = @HWCAP_HAS_ISA_2_07@
+HWCAP_HAS_ISA_3_00 = @HWCAP_HAS_ISA_3_00@
+HWCAP_HAS_VSX = @HWCAP_HAS_VSX@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
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+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
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+LIBS = @LIBS@
+LIB_UBSAN = @LIB_UBSAN@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
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+MPI_CC = @MPI_CC@
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+PACKAGE = @PACKAGE@
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+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY_2 = @PREFERRED_STACK_BOUNDARY_2@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+SOLARIS_UNDEF_LARGESOURCE = @SOLARIS_UNDEF_LARGESOURCE@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+VG_TMPDIR = @VG_TMPDIR@
+abs_builddir = @abs_builddir@
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+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = -O2 -g -std=gnu99 -Wall -Wmissing-prototypes -Wshadow \
+ -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations \
+ @FLAG_W_CAST_ALIGN@ @FLAG_W_CAST_QUAL@ @FLAG_W_WRITE_STRINGS@ \
+ @FLAG_W_EMPTY_BODY@ @FLAG_W_FORMAT@ @FLAG_W_FORMAT_SIGNEDNESS@ \
+ @FLAG_W_FORMAT_SECURITY@ @FLAG_W_IGNORED_QUALIFIERS@ \
+ @FLAG_W_MISSING_PARAMETER_TYPE@ @FLAG_W_OLD_STYLE_DECLARATION@ \
+ @FLAG_FNO_STACK_PROTECTOR@ @FLAG_FSANITIZE@ \
+ -fno-strict-aliasing -fno-builtin $(am__append_1)
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PSO_BASE = -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fpic -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# These flags are used for building the preload shared objects (PSOs).
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads. Also, we must use any
+# -mpreferred-stack-boundary flag to build the preload shared
+# objects, since that risks misaligning the client's stack and
+# results in segfaults like (eg) #324050.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PSO_BASE = -dynamic \
+@VGCONF_OS_IS_DARWIN_TRUE@ -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fpic -fPIC -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_X86_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64BE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64BE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC64LE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64LE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CFLAGS_PSO_ARM_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) \
+ -marm -mcpu=cortex-a8 $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_ARM64_LINUX = @FLAG_M64@
+AM_CFLAGS_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_ARM64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CFLAGS_PSO_X86_DARWIN = $(AM_CFLAGS_X86_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 -fno-stack-protector
+
+AM_CFLAGS_PSO_AMD64_DARWIN = $(AM_CFLAGS_AMD64_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CFLAGS_PSO_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@
+AM_CFLAGS_PSO_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -g @FLAG_MIPS32@
+AM_FLAG_M3264_MIPS64_LINUX = @FLAG_M64@
+AM_CFLAGS_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@
+AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
+AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
+AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer \
+ @SOLARIS_UNDEF_LARGESOURCE@
+
+AM_CFLAGS_PSO_X86_SOLARIS = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_SOLARIS = @FLAG_M32@ -g -D_ASM
+AM_FLAG_M3264_AMD64_SOLARIS = @FLAG_M64@
+AM_CFLAGS_AMD64_SOLARIS = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_SOLARIS = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_SOLARIS = @FLAG_M64@ -g -D_ASM
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_3)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_COMMON_SOLARIS = -nodefaultlibs -shared \
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+ filter_stderr
+
+EXTRA_DIST = $(noinst_SCRIPTS) \
+ fadvise64.stderr.exp fadvise64.stdout.exp fadvise64.vgtest
+
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
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+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign memcheck/tests/mips32/Makefile
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+ @case '$?' in \
+ *config.status*) \
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+
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+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fadvise64.Po@am__quote@
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+.c.o:
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+ else \
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+ fi; \
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+
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+
+distdir: $(DISTFILES)
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+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
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+ fi
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+.PRECIOUS: Makefile
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make uninstall". It removes $(noinst_PROGRAMS) from $prefix/lib/valgrind/.
+# It needs to be depended on by an 'uninstall-local' rule.
+uninstall-noinst_PROGRAMS:
+ for f in $(noinst_PROGRAMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f; \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to uninstall-noinst_PROGRAMS.
+uninstall-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f.dSYM; \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/memcheck/tests/mips32/fadvise64.c b/memcheck/tests/mips32/fadvise64.c
new file mode 100644
index 0000000..c740395
--- /dev/null
+++ b/memcheck/tests/mips32/fadvise64.c
@@ -0,0 +1,21 @@
+#include <errno.h>
+#include <fcntl.h>
+#include <stdio.h>
+
+#define BAD_FD 42
+
+int main() {
+ int x;
+
+ (void)posix_fadvise(x, 1, 2, POSIX_FADV_NORMAL);
+ (void)posix_fadvise(BAD_FD, x, 2, POSIX_FADV_NORMAL);
+ (void)posix_fadvise(BAD_FD, 1, x, POSIX_FADV_NORMAL);
+ (void)posix_fadvise(BAD_FD, 1, 2, x);
+
+ x = posix_fadvise(BAD_FD, 1, 2, POSIX_FADV_NORMAL);
+
+ if (x != EBADF)
+ fprintf(stderr, "Unexpected return value: %d\n", x);
+
+ return 0;
+}
diff --git a/memcheck/tests/mips32/fadvise64.stderr.exp b/memcheck/tests/mips32/fadvise64.stderr.exp
new file mode 100644
index 0000000..eca7448
--- /dev/null
+++ b/memcheck/tests/mips32/fadvise64.stderr.exp
@@ -0,0 +1,24 @@
+Syscall param fadvise64(fd) contains uninitialised byte(s)
+ ...
+ by 0x........: main (fadvise64.c:10)
+
+Syscall param fadvise64(offset_low) contains uninitialised byte(s)
+ ...
+ by 0x........: main (fadvise64.c:11)
+
+Syscall param fadvise64(offset_high) contains uninitialised byte(s)
+ ...
+ by 0x........: main (fadvise64.c:11)
+
+Syscall param fadvise64(len_low) contains uninitialised byte(s)
+ ...
+ by 0x........: main (fadvise64.c:12)
+
+Syscall param fadvise64(len_high) contains uninitialised byte(s)
+ ...
+ by 0x........: main (fadvise64.c:12)
+
+Syscall param fadvise64(advice) contains uninitialised byte(s)
+ ...
+ by 0x........: main (fadvise64.c:13)
+
diff --git a/memcheck/tests/mips32/fadvise64.stdout.exp b/memcheck/tests/mips32/fadvise64.stdout.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/memcheck/tests/mips32/fadvise64.stdout.exp
diff --git a/memcheck/tests/mips32/fadvise64.vgtest b/memcheck/tests/mips32/fadvise64.vgtest
new file mode 100644
index 0000000..daccdb9
--- /dev/null
+++ b/memcheck/tests/mips32/fadvise64.vgtest
@@ -0,0 +1,2 @@
+prog: fadvise64
+vgopts: -q
diff --git a/memcheck/tests/mips32/filter_stderr b/memcheck/tests/mips32/filter_stderr
new file mode 100755
index 0000000..a778e97
--- /dev/null
+++ b/memcheck/tests/mips32/filter_stderr
@@ -0,0 +1,3 @@
+#! /bin/sh
+
+../filter_stderr "$@"
diff --git a/memcheck/tests/mips64/Makefile.am b/memcheck/tests/mips64/Makefile.am
new file mode 100644
index 0000000..9413788
--- /dev/null
+++ b/memcheck/tests/mips64/Makefile.am
@@ -0,0 +1,11 @@
+
+include $(top_srcdir)/Makefile.tool-tests.am
+
+dist_noinst_SCRIPTS = \
+ filter_stderr
+
+EXTRA_DIST = $(noinst_SCRIPTS) \
+ fadvise64.stderr.exp fadvise64.stdout.exp fadvise64.vgtest
+
+check_PROGRAMS = \
+ fadvise64
diff --git a/memcheck/tests/mips64/Makefile.in b/memcheck/tests/mips64/Makefile.in
new file mode 100644
index 0000000..525aa0a
--- /dev/null
+++ b/memcheck/tests/mips64/Makefile.in
@@ -0,0 +1,923 @@
+# Makefile.in generated by automake 1.15 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994-2014 Free Software Foundation, Inc.
+
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+am__is_gnu_make = { \
+ if test -z '$(MAKELEVEL)'; then \
+ false; \
+ elif test -n '$(MAKE_HOST)'; then \
+ true; \
+ elif test -n '$(MAKE_VERSION)' && test -n '$(CURDIR)'; then \
+ true; \
+ else \
+ false; \
+ fi; \
+}
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+ case $${target_option-} in \
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+ else \
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+ *\\[\ \ ]*) \
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+ sane_makeflags=`printf '%s\n' "$$MAKEFLAGS" \
+ | sed "s/$$bs$$bs[$$bs $$bs ]*//g"`;; \
+ esac; \
+ fi; \
+ skip_next=no; \
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+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
+AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
+AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer \
+ @SOLARIS_UNDEF_LARGESOURCE@
+
+AM_CFLAGS_PSO_X86_SOLARIS = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_SOLARIS = @FLAG_M32@ -g -D_ASM
+AM_FLAG_M3264_AMD64_SOLARIS = @FLAG_M64@
+AM_CFLAGS_AMD64_SOLARIS = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_SOLARIS = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_SOLARIS = @FLAG_M64@ -g -D_ASM
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_3)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_COMMON_SOLARIS = -nodefaultlibs -shared \
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+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64BE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
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+ -DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_4)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_5) $(am__append_6)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_7)
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS)
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = \
+ filter_stderr
+
+EXTRA_DIST = $(noinst_SCRIPTS) \
+ fadvise64.stderr.exp fadvise64.stdout.exp fadvise64.vgtest
+
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign memcheck/tests/mips64/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign memcheck/tests/mips64/Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
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+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+
+fadvise64$(EXEEXT): $(fadvise64_OBJECTS) $(fadvise64_DEPENDENCIES) $(EXTRA_fadvise64_DEPENDENCIES)
+ @rm -f fadvise64$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(fadvise64_OBJECTS) $(fadvise64_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fadvise64.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(AM_V_CC)depbase=`echo $@ | sed 's|[^/]*$$|$(DEPDIR)/&|;s|\.o$$||'`;\
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $$depbase.Tpo -c -o $@ $< &&\
+@am__fastdepCC_TRUE@ $(am__mv) $$depbase.Tpo $$depbase.Po
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+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(COMPILE) -c -o $@ $<
+
+.c.obj:
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+
+ID: $(am__tagged_files)
+ $(am__define_uniq_tagged_files); mkid -fID $$unique
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+ set x; \
+ here=`pwd`; \
+ $(am__define_uniq_tagged_files); \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
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+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
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+ $$unique; \
+ fi; \
+ fi
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+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
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+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
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+ case "$(srcdir)" in \
+ [\\/]* | ?:[\\/]*) sdir="$(srcdir)" ;; \
+ *) sdir=$(subdir)/$(srcdir) ;; \
+ esac; \
+ for i in $$list; do \
+ if test -f "$$i"; then \
+ echo "$(subdir)/$$i"; \
+ else \
+ echo "$$sdir/$$i"; \
+ fi; \
+ done >> $(top_builddir)/cscope.files
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
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+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
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+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'" install; \
+ fi
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
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+ distclean-tags
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+dvi: dvi-am
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+ -rm -f Makefile
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+ install-dvi-am install-exec install-exec-am install-html \
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+ install-strip installcheck installcheck-am installdirs \
+ maintainer-clean maintainer-clean-generic mostlyclean \
+ mostlyclean-compile mostlyclean-generic pdf pdf-am ps ps-am \
+ tags tags-am uninstall uninstall-am
+
+.PRECIOUS: Makefile
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make uninstall". It removes $(noinst_PROGRAMS) from $prefix/lib/valgrind/.
+# It needs to be depended on by an 'uninstall-local' rule.
+uninstall-noinst_PROGRAMS:
+ for f in $(noinst_PROGRAMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f; \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to uninstall-noinst_PROGRAMS.
+uninstall-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f.dSYM; \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/memcheck/tests/mips64/fadvise64.c b/memcheck/tests/mips64/fadvise64.c
new file mode 100644
index 0000000..c740395
--- /dev/null
+++ b/memcheck/tests/mips64/fadvise64.c
@@ -0,0 +1,21 @@
+#include <errno.h>
+#include <fcntl.h>
+#include <stdio.h>
+
+#define BAD_FD 42
+
+int main() {
+ int x;
+
+ (void)posix_fadvise(x, 1, 2, POSIX_FADV_NORMAL);
+ (void)posix_fadvise(BAD_FD, x, 2, POSIX_FADV_NORMAL);
+ (void)posix_fadvise(BAD_FD, 1, x, POSIX_FADV_NORMAL);
+ (void)posix_fadvise(BAD_FD, 1, 2, x);
+
+ x = posix_fadvise(BAD_FD, 1, 2, POSIX_FADV_NORMAL);
+
+ if (x != EBADF)
+ fprintf(stderr, "Unexpected return value: %d\n", x);
+
+ return 0;
+}
diff --git a/memcheck/tests/mips64/fadvise64.stderr.exp b/memcheck/tests/mips64/fadvise64.stderr.exp
new file mode 100644
index 0000000..6759a08
--- /dev/null
+++ b/memcheck/tests/mips64/fadvise64.stderr.exp
@@ -0,0 +1,16 @@
+Syscall param fadvise64(fd) contains uninitialised byte(s)
+ ...
+ by 0x........: main (fadvise64.c:10)
+
+Syscall param fadvise64(offset) contains uninitialised byte(s)
+ ...
+ by 0x........: main (fadvise64.c:11)
+
+Syscall param fadvise64(len) contains uninitialised byte(s)
+ ...
+ by 0x........: main (fadvise64.c:12)
+
+Syscall param fadvise64(advice) contains uninitialised byte(s)
+ ...
+ by 0x........: main (fadvise64.c:13)
+
diff --git a/memcheck/tests/mips64/fadvise64.stdout.exp b/memcheck/tests/mips64/fadvise64.stdout.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/memcheck/tests/mips64/fadvise64.stdout.exp
diff --git a/memcheck/tests/mips64/fadvise64.vgtest b/memcheck/tests/mips64/fadvise64.vgtest
new file mode 100644
index 0000000..daccdb9
--- /dev/null
+++ b/memcheck/tests/mips64/fadvise64.vgtest
@@ -0,0 +1,2 @@
+prog: fadvise64
+vgopts: -q
diff --git a/memcheck/tests/mips64/filter_stderr b/memcheck/tests/mips64/filter_stderr
new file mode 100755
index 0000000..a778e97
--- /dev/null
+++ b/memcheck/tests/mips64/filter_stderr
@@ -0,0 +1,3 @@
+#! /bin/sh
+
+../filter_stderr "$@"
diff --git a/memcheck/tests/new_override.cpp b/memcheck/tests/new_override.cpp
index 2001736..f462a9c 100644
--- a/memcheck/tests/new_override.cpp
+++ b/memcheck/tests/new_override.cpp
@@ -7,7 +7,7 @@
int a, b, c, d;
};
-void *operator new[](size_t size) throw(std::bad_alloc)
+void *operator new[](size_t size)
{
void *ret = malloc(size);
printf("Here.\n");
diff --git a/memcheck/tests/new_override.vgtest b/memcheck/tests/new_override.vgtest
index 435e330..7febc13 100644
--- a/memcheck/tests/new_override.vgtest
+++ b/memcheck/tests/new_override.vgtest
@@ -1,6 +1,6 @@
prog: new_override
# Don't override the user defined somalloc functions in this test.
# The test depends on some side effects and initializing memory done by
-# the user overidden operator new.
+# the user overridden operator new.
vgopts: --soname-synonyms=somalloc=nouseroverride
stderr_filter: filter_allocs
diff --git a/memcheck/tests/origin5-bz2.stderr.exp-glibc212-tilegx b/memcheck/tests/origin5-bz2.stderr.exp-glibc212-tilegx
deleted file mode 100644
index cca6411..0000000
--- a/memcheck/tests/origin5-bz2.stderr.exp-glibc212-tilegx
+++ /dev/null
@@ -1,28 +0,0 @@
-Conditional jump or move depends on uninitialised value(s)
- at 0x........: main (origin5-bz2.c:6481)
- Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6479)
-
-Conditional jump or move depends on uninitialised value(s)
- at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
- by 0x........: handle_compress (origin5-bz2.c:4750)
- by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
- by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
- by 0x........: main (origin5-bz2.c:6484)
- Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6479)
-
-Use of uninitialised value of size 8
- at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
- by 0x........: handle_compress (origin5-bz2.c:4750)
- by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
- by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
- by 0x........: main (origin5-bz2.c:6484)
- Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6479)
-
-Conditional jump or move depends on uninitialised value(s)
- at 0x........: main (origin5-bz2.c:6512)
- Uninitialised value was created by a client request
- at 0x........: main (origin5-bz2.c:6479)
-
diff --git a/memcheck/tests/origin6-fp.stderr.exp-glibc212-tilegx b/memcheck/tests/origin6-fp.stderr.exp-glibc212-tilegx
deleted file mode 100644
index fa55d0e..0000000
--- a/memcheck/tests/origin6-fp.stderr.exp-glibc212-tilegx
+++ /dev/null
@@ -1,76 +0,0 @@
-Conditional jump or move depends on uninitialised value(s)
- at 0x........: __divdf3 (in /u/zliu/WS1/valgrind/valgrind-latest/memcheck/tests/origin6-fp)
- by 0x........: do3x3smooth (origin6-fp.c:47)
- by 0x........: main (origin6-fp.c:89)
- Uninitialised value was created by a client request
- at 0x........: setup_arr (origin6-fp.c:75)
- by 0x........: main (origin6-fp.c:87)
-
-Conditional jump or move depends on uninitialised value(s)
- at 0x........: __divdf3 (in /u/zliu/WS1/valgrind/valgrind-latest/memcheck/tests/origin6-fp)
- by 0x........: do3x3smooth (origin6-fp.c:47)
- by 0x........: main (origin6-fp.c:89)
- Uninitialised value was created by a client request
- at 0x........: setup_arr (origin6-fp.c:75)
- by 0x........: main (origin6-fp.c:87)
-
-Conditional jump or move depends on uninitialised value(s)
- at 0x........: __divdf3 (in /u/zliu/WS1/valgrind/valgrind-latest/memcheck/tests/origin6-fp)
- by 0x........: do3x3smooth (origin6-fp.c:47)
- by 0x........: main (origin6-fp.c:89)
- Uninitialised value was created by a client request
- at 0x........: setup_arr (origin6-fp.c:75)
- by 0x........: main (origin6-fp.c:87)
-
-Conditional jump or move depends on uninitialised value(s)
- at 0x........: __float_estimateDiv128To64 (in /u/zliu/WS1/valgrind/valgrind-latest/memcheck/tests/origin6-fp)
- by 0x........: __divdf3 (in /u/zliu/WS1/valgrind/valgrind-latest/memcheck/tests/origin6-fp)
- by 0x........: do3x3smooth (origin6-fp.c:47)
- by 0x........: main (origin6-fp.c:89)
- Uninitialised value was created by a client request
- at 0x........: setup_arr (origin6-fp.c:75)
- by 0x........: main (origin6-fp.c:87)
-
-Conditional jump or move depends on uninitialised value(s)
- at 0x........: __float_estimateDiv128To64 (in /u/zliu/WS1/valgrind/valgrind-latest/memcheck/tests/origin6-fp)
- by 0x........: __divdf3 (in /u/zliu/WS1/valgrind/valgrind-latest/memcheck/tests/origin6-fp)
- by 0x........: do3x3smooth (origin6-fp.c:47)
- by 0x........: main (origin6-fp.c:89)
- Uninitialised value was created by a client request
- at 0x........: setup_arr (origin6-fp.c:75)
- by 0x........: main (origin6-fp.c:87)
-
-Conditional jump or move depends on uninitialised value(s)
- at 0x........: __float_estimateDiv128To64 (in /u/zliu/WS1/valgrind/valgrind-latest/memcheck/tests/origin6-fp)
- by 0x........: __divdf3 (in /u/zliu/WS1/valgrind/valgrind-latest/memcheck/tests/origin6-fp)
- by 0x........: do3x3smooth (origin6-fp.c:47)
- by 0x........: main (origin6-fp.c:89)
- Uninitialised value was created by a client request
- at 0x........: setup_arr (origin6-fp.c:75)
- by 0x........: main (origin6-fp.c:87)
-
-Conditional jump or move depends on uninitialised value(s)
- at 0x........: __float_estimateDiv128To64 (in /u/zliu/WS1/valgrind/valgrind-latest/memcheck/tests/origin6-fp)
- by 0x........: __divdf3 (in /u/zliu/WS1/valgrind/valgrind-latest/memcheck/tests/origin6-fp)
- by 0x........: do3x3smooth (origin6-fp.c:47)
- by 0x........: main (origin6-fp.c:89)
- Uninitialised value was created by a client request
- at 0x........: setup_arr (origin6-fp.c:75)
- by 0x........: main (origin6-fp.c:87)
-
-Conditional jump or move depends on uninitialised value(s)
- at 0x........: __divdf3 (in /u/zliu/WS1/valgrind/valgrind-latest/memcheck/tests/origin6-fp)
- by 0x........: do3x3smooth (origin6-fp.c:47)
- by 0x........: main (origin6-fp.c:89)
- Uninitialised value was created by a client request
- at 0x........: setup_arr (origin6-fp.c:75)
- by 0x........: main (origin6-fp.c:87)
-
-Conditional jump or move depends on uninitialised value(s)
- at 0x........: __float_roundAndPackFloat64 (in /u/zliu/WS1/valgrind/valgrind-latest/memcheck/tests/origin6-fp)
- by 0x........: main (origin6-fp.c:89)
- Uninitialised value was created by a client request
- at 0x........: setup_arr (origin6-fp.c:75)
- by 0x........: main (origin6-fp.c:87)
-
-Test succeeded.
diff --git a/memcheck/tests/ppc32/Makefile.in b/memcheck/tests/ppc32/Makefile.in
index c524b09..c48cfe3 100644
--- a/memcheck/tests/ppc32/Makefile.in
+++ b/memcheck/tests/ppc32/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -248,6 +248,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -418,6 +419,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -428,6 +430,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -502,8 +505,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -548,7 +549,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/memcheck/tests/ppc64/Makefile.in b/memcheck/tests/ppc64/Makefile.in
index b8ce165..0432825 100644
--- a/memcheck/tests/ppc64/Makefile.in
+++ b/memcheck/tests/ppc64/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -248,6 +248,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -418,6 +419,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -428,6 +430,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -502,8 +505,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -548,7 +549,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/memcheck/tests/s390x/Makefile.in b/memcheck/tests/s390x/Makefile.in
index d48dbb4..288d10c 100644
--- a/memcheck/tests/s390x/Makefile.in
+++ b/memcheck/tests/s390x/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -267,6 +267,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -437,6 +438,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -447,6 +449,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -521,8 +524,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -567,7 +568,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/memcheck/tests/solaris/Makefile.in b/memcheck/tests/solaris/Makefile.in
index 913508a..8dd7dd6 100644
--- a/memcheck/tests/solaris/Makefile.in
+++ b/memcheck/tests/solaris/Makefile.in
@@ -112,7 +112,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -482,6 +482,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -652,6 +653,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -662,6 +664,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -736,8 +739,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -782,7 +783,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/memcheck/tests/solaris/brk.stderr.exp b/memcheck/tests/solaris/brk.stderr.exp
index 3e981d5..d391c95 100644
--- a/memcheck/tests/solaris/brk.stderr.exp
+++ b/memcheck/tests/solaris/brk.stderr.exp
@@ -1,3 +1,4 @@
+
Invalid read of size 1
at 0x........: test_begin (brk.c:19)
by 0x........: main (brk.c:78)
@@ -8,4 +9,15 @@
by 0x........: main (brk.c:78)
Address 0x........ is 0 bytes after the brk data segment limit 0x........
-brk segment overflow in thread #1: can't grow to 0x........
+brk segment overflow in thread #1: can not grow to 0x........
+(See section Limitations in the user manual.)
+NOTE: further instances of this message will not be shown.
+
+HEAP SUMMARY:
+ in use at exit: 0 bytes in 0 blocks
+ total heap usage: 0 allocs, 0 frees, 0 bytes allocated
+
+For a detailed leak analysis, rerun with: --leak-check=full
+
+For counts of detected and suppressed errors, rerun with: -v
+ERROR SUMMARY: 2 errors from 2 contexts (suppressed: 0 from 0)
diff --git a/memcheck/tests/solaris/brk.vgtest b/memcheck/tests/solaris/brk.vgtest
index 1306b77..b1766ff 100644
--- a/memcheck/tests/solaris/brk.vgtest
+++ b/memcheck/tests/solaris/brk.vgtest
@@ -1,2 +1 @@
prog: brk
-vgopts: -q
diff --git a/memcheck/tests/solaris/scalar.c b/memcheck/tests/solaris/scalar.c
index d660ca2..fef2d69 100644
--- a/memcheck/tests/solaris/scalar.c
+++ b/memcheck/tests/solaris/scalar.c
@@ -1,6 +1,7 @@
/* Basic syscall test, see memcheck/tests/x86-linux/scalar.c for more info. */
#include "scalar.h"
+#include "config.h"
#include <bsm/audit.h>
#include <nfs/nfs.h>
@@ -9,7 +10,10 @@
#include <sys/door.h>
#include <sys/fcntl.h>
#include <sys/fstyp.h>
-#include <sys/lwp.h>
+#include <sys/lgrp_user.h>
+#if defined(HAVE_SYS_LGRP_USER_IMPL_H)
+#include <sys/lgrp_user_impl.h>
+#endif /* HAVE_SYS_LGRP_USER_IMPL_H */
#include <sys/mman.h>
#include <sys/modctl.h>
#include <sys/mount.h>
@@ -308,6 +312,13 @@
__attribute__((noinline))
static void sys_fcntl3(void)
{
+ GO(SYS_fcntl, "(DUPFD_CLOEXEC) 3s 0m");
+ SY(SYS_fcntl, x0 - 1, x0 + F_DUPFD_CLOEXEC, x0); FAILx(EBADF);
+}
+
+__attribute__((noinline))
+static void sys_fcntl4(void)
+{
GO(SYS_fcntl, "(GETLK) 3s 5m");
SY(SYS_fcntl, x0 - 1, x0 + F_GETLK, x0); FAILx(EBADF);
}
@@ -695,6 +706,55 @@
}
__attribute__((noinline))
+static void sys_lgrpsys(void)
+{
+ GO(SYS_lgrpsys, "(LGRP_SYS_MEMINFO) 3s 1m");
+ SY(SYS_lgrpsys, x0 + LGRP_SYS_MEMINFO, x0 + 0, x0 + 1); FAIL;
+}
+
+__attribute__((noinline))
+static void sys_lgrpsys2(void)
+{
+ GO(SYS_lgrpsys, "(LGRP_SYS_MEMINFO) 3s 1m");
+ SY(SYS_lgrpsys, x0 + LGRP_SYS_MEMINFO, x0 + 1, x0 + 1); FAIL;
+}
+
+__attribute__((noinline))
+static void sys_lgrpsys3(void)
+{
+ meminfo_t minfo;
+ minfo.mi_inaddr = (void *)(x0 + 1);
+ minfo.mi_info_req = (void *)(x0 + 1);
+ minfo.mi_info_count = x0 + 1;
+ minfo.mi_outdata = (void *)(x0 + 1);
+ minfo.mi_validity = (void *)(x0 + 1);
+
+ GO(SYS_lgrpsys, "(LGRP_SYS_MEMINFO) 4s 4m");
+ SY(SYS_lgrpsys, x0 + LGRP_SYS_MEMINFO, x0 + 1, x0 + &minfo); FAIL;
+}
+
+__attribute__((noinline))
+static void sys_lgrpsys4(void)
+{
+ GO(SYS_lgrpsys, "(LGRP_SYS_GENERATION) 2s 0m");
+ SY(SYS_lgrpsys, x0 + LGRP_SYS_GENERATION, x0 + 0); SUCC;
+}
+
+__attribute__((noinline))
+static void sys_lgrpsys5(void)
+{
+ GO(SYS_lgrpsys, "(LGRP_SYS_VERSION) 2s 0m");
+ SY(SYS_lgrpsys, x0 + LGRP_SYS_VERSION, x0 + 0); SUCC;
+}
+
+__attribute__((noinline))
+static void sys_lgrpsys6(void)
+{
+ GO(SYS_lgrpsys, "(LGRP_SYS_SNAPSHOT) 3s 1m");
+ SY(SYS_lgrpsys, x0 + LGRP_SYS_SNAPSHOT, x0 + 10, x0 + 1); FAIL;
+}
+
+__attribute__((noinline))
static void sys_rusagesys(void)
{
GO(SYS_rusagesys, "(_RUSAGESYS_GETRUSAGE) 2s 1m");
@@ -1755,6 +1815,7 @@
sys_fcntl();
sys_fcntl2();
sys_fcntl3();
+ sys_fcntl4();
/* SYS_ulimit 63 */
/* XXX Missing wrapper. */
@@ -1878,7 +1939,8 @@
SY(SYS_sigprocmask, x0, x0 + 1, x0 + 1); FAILx(EFAULT);
/* SYS_sigsuspend 96 */
- /* XXX Missing wrapper. */
+ GO(SYS_sigsuspend, "1s 1m");
+ SY(SYS_sigsuspend, x0 + 1); FAILx(EFAULT);
/* SYS_sigaltstack 97 */
GO(SYS_sigaltstack, "2s 2m");
@@ -1926,7 +1988,8 @@
SY(SYS_waitid, x0 - 1, x0, x0, x0); FAIL;
/* SYS_sigsendsys 108 */
- /* XXX Missing wrapper. */
+ GO(SYS_sigsendsys, "2s 1m");
+ SY(SYS_sigsendsys, x0 - 1, x0); FAIL;
/* SYS_hrtsys 109 */
/* XXX Missing wrapper. */
@@ -2130,14 +2193,7 @@
SY(SYS_lwp_sigmask, x0, x0, x0, x0, x0); FAIL;
/* SYS_lwp_private 166 */
- GO(SYS_lwp_private, "3s 1m");
-#if defined(__i386)
- SY(SYS_lwp_private, x0 + _LWP_GETPRIVATE, x0 + _LWP_GSBASE, x0); FAIL;
-#elif defined(__amd64)
- SY(SYS_lwp_private, x0 + _LWP_GETPRIVATE, x0 + _LWP_FSBASE, x0); FAIL;
-#else
-#error Unsupported platform
-#endif
+ /* Tested in amd64-solaris/scalar and x86-solaris/scalar */
/* SYS_lwp_wait 167 */
GO(SYS_lwp_wait, "2s 1m");
@@ -2183,7 +2239,12 @@
/* XXX Missing wrapper. */
/* SYS_lgrpsys 180 */
- /* XXX Missing wrapper. */
+ sys_lgrpsys();
+ sys_lgrpsys2();
+ sys_lgrpsys3();
+ sys_lgrpsys4();
+ sys_lgrpsys5();
+ sys_lgrpsys6();
/* SYS_rusagesys 181 */
sys_rusagesys();
diff --git a/memcheck/tests/solaris/scalar.stderr.exp b/memcheck/tests/solaris/scalar.stderr.exp
index 83bfdd7..df1f974 100644
--- a/memcheck/tests/solaris/scalar.stderr.exp
+++ b/memcheck/tests/solaris/scalar.stderr.exp
@@ -1049,6 +1049,18 @@
...
---------------------------------------------------------
+ 62: SYS_fcntl (DUPFD_CLOEXEC) 3s 0m
+---------------------------------------------------------
+Syscall param fcntl(fildes) contains uninitialised byte(s)
+ ...
+
+Syscall param fcntl(cmd) contains uninitialised byte(s)
+ ...
+
+Syscall param fcntl(arg) contains uninitialised byte(s)
+ ...
+
+---------------------------------------------------------
62: SYS_fcntl (GETLK) 3s 5m
---------------------------------------------------------
Syscall param fcntl(fildes) contains uninitialised byte(s)
@@ -1611,6 +1623,16 @@
Address 0x........ is not stack'd, malloc'd or (recently) free'd
---------------------------------------------------------
+ 96: SYS_sigsuspend 1s 1m
+---------------------------------------------------------
+Syscall param sigsuspend(set) contains uninitialised byte(s)
+ ...
+
+Syscall param sigsuspend(set) points to unaddressable byte(s)
+ ...
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+---------------------------------------------------------
97: SYS_sigaltstack 2s 2m
---------------------------------------------------------
Syscall param sigaltstack(ss) contains uninitialised byte(s)
@@ -1829,6 +1851,19 @@
Address 0x........ is not stack'd, malloc'd or (recently) free'd
---------------------------------------------------------
+108: SYS_sigsendsys 2s 1m
+---------------------------------------------------------
+Syscall param sigsendsys(psp) contains uninitialised byte(s)
+ ...
+
+Syscall param sigsendsys(signal) contains uninitialised byte(s)
+ ...
+
+Syscall param sigsendsys(psp) points to unaddressable byte(s)
+ ...
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+---------------------------------------------------------
111: SYS_sigresend 3s 2m
---------------------------------------------------------
Syscall param sigresend(signal) contains uninitialised byte(s)
@@ -2640,22 +2675,6 @@
sigprocmask: unknown 'how' field 0
---------------------------------------------------------
-166: SYS_lwp_private 3s 1m
----------------------------------------------------------
-Syscall param lwp_private(cmd) contains uninitialised byte(s)
- ...
-
-Syscall param lwp_private(which) contains uninitialised byte(s)
- ...
-
-Syscall param lwp_private(base) contains uninitialised byte(s)
- ...
-
-Syscall param lwp_private(base) points to unaddressable byte(s)
- ...
- Address 0x........ is not stack'd, malloc'd or (recently) free'd
-
----------------------------------------------------------
167: SYS_lwp_wait 2s 1m
---------------------------------------------------------
Syscall param lwp_wait(lwpid) contains uninitialised byte(s)
@@ -2787,6 +2806,104 @@
Address 0x........ is not stack'd, malloc'd or (recently) free'd
---------------------------------------------------------
+180: SYS_lgrpsys (LGRP_SYS_MEMINFO) 3s 1m
+---------------------------------------------------------
+Syscall param lgrpsys_meminfo(subcode) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys_meminfo(addr_count) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys_meminfo(minfo) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys(minfo) points to unaddressable byte(s)
+ ...
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+---------------------------------------------------------
+180: SYS_lgrpsys (LGRP_SYS_MEMINFO) 3s 1m
+---------------------------------------------------------
+Syscall param lgrpsys_meminfo(subcode) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys_meminfo(addr_count) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys_meminfo(minfo) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys(minfo) points to unaddressable byte(s)
+ ...
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+---------------------------------------------------------
+180: SYS_lgrpsys (LGRP_SYS_MEMINFO) 4s 4m
+---------------------------------------------------------
+Syscall param lgrpsys_meminfo(subcode) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys_meminfo(addr_count) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys_meminfo(minfo) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys(minfo) points to uninitialised byte(s)
+ ...
+ Address 0x........ is on thread 1's stack
+
+Syscall param lgrpsys(minfo->mi_inaddr) points to unaddressable byte(s)
+ ...
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+Syscall param lgrpsys(minfo->mi_info_req) points to unaddressable byte(s)
+ ...
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+Syscall param lgrpsys(minfo->mi_outdata) points to unaddressable byte(s)
+ ...
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+Syscall param lgrpsys(minfo->mi_validity) points to unaddressable byte(s)
+ ...
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+---------------------------------------------------------
+180: SYS_lgrpsys (LGRP_SYS_GENERATION) 2s 0m
+---------------------------------------------------------
+Syscall param lgrpsys_generation(subcode) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys_generation(view) contains uninitialised byte(s)
+ ...
+
+---------------------------------------------------------
+180: SYS_lgrpsys (LGRP_SYS_VERSION) 2s 0m
+---------------------------------------------------------
+Syscall param lgrpsys_version(subcode) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys_version(version) contains uninitialised byte(s)
+ ...
+
+---------------------------------------------------------
+180: SYS_lgrpsys (LGRP_SYS_SNAPSHOT) 3s 1m
+---------------------------------------------------------
+Syscall param lgrpsys_snapshot(subcode) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys_snapshot(bufsize) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys_snapshot(buf) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys(buf) points to unaddressable byte(s)
+ ...
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+---------------------------------------------------------
181: SYS_rusagesys (_RUSAGESYS_GETRUSAGE) 2s 1m
---------------------------------------------------------
Syscall param rusagesys_getrusage(code) contains uninitialised byte(s)
diff --git a/memcheck/tests/suppfreecollision.vgtest b/memcheck/tests/suppfreecollision.vgtest
index cda50aa..c2feebd 100644
--- a/memcheck/tests/suppfreecollision.vgtest
+++ b/memcheck/tests/suppfreecollision.vgtest
@@ -1,6 +1,6 @@
# this test the case of two errors, one considered not dangerous and
# suppressed, the other considered dangerous, and the user does
-# not want to supress it.
+# not want to suppress it.
# The suppression entry only match the non dangerous error.
# However, when a medium resolution is used to compare 2 errors,
# only the last 4 calls are used to determine that two errors are similar
diff --git a/memcheck/tests/unit_oset.c b/memcheck/tests/unit_oset.c
index 6b82445..ff93398 100644
--- a/memcheck/tests/unit_oset.c
+++ b/memcheck/tests/unit_oset.c
@@ -28,6 +28,7 @@
#define vgPlain_memset memset
#define vgPlain_memcpy memcpy
#define vgPlain_memmove memmove
+#define vgPlain_strcmp strcmp
// Crudely replace some functions (in m_xarray.c, but not needed for
// this unit test) by (hopefully) failing asserts.
@@ -207,7 +208,8 @@
// Check that we can remove half of the elements, and that their values
// are as expected.
for (i = 0; i < NN; i += 2) {
- assert( pv = VG_(OSetGen_Remove)(oset, vs[i]) );
+ pv = VG_(OSetGen_Remove)(oset, vs[i]);
+ assert( pv );
assert( pv == vs[i] );
}
@@ -216,7 +218,8 @@
// Check we can find the remaining elements (with the right values).
for (i = 1; i < NN; i += 2) {
- assert( pv = VG_(OSetGen_LookupWithCmp)(oset, vs[i], NULL) );
+ pv = VG_(OSetGen_LookupWithCmp)(oset, vs[i], NULL);
+ assert( pv );
assert( pv == vs[i] );
}
@@ -228,7 +231,8 @@
// Check that we can remove the remaining half of the elements, and that
// their values are as expected.
for (i = 1; i < NN; i += 2) {
- assert( pv = VG_(OSetGen_Remove)(oset, vs[i]) );
+ pv = VG_(OSetGen_Remove)(oset, vs[i]);
+ assert( pv );
assert( pv == vs[i] );
}
diff --git a/memcheck/tests/vbit-test/Makefile.in b/memcheck/tests/vbit-test/Makefile.in
index 3952328..03f66df 100644
--- a/memcheck/tests/vbit-test/Makefile.in
+++ b/memcheck/tests/vbit-test/Makefile.in
@@ -262,6 +262,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -432,6 +433,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -442,6 +444,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -516,8 +519,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -562,7 +563,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
EXTRA_DIST = vbit-test.vgtest vbit-test.stderr.exp
diff --git a/memcheck/tests/vbit-test/binary.c b/memcheck/tests/vbit-test/binary.c
index 5fc712d..89a7237 100644
--- a/memcheck/tests/vbit-test/binary.c
+++ b/memcheck/tests/vbit-test/binary.c
@@ -4,7 +4,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2012-2015 Florian Krohm
+ Copyright (C) 2012-2017 Florian Krohm
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/memcheck/tests/vbit-test/irops.c b/memcheck/tests/vbit-test/irops.c
index 5b1106a..d0e8298 100644
--- a/memcheck/tests/vbit-test/irops.c
+++ b/memcheck/tests/vbit-test/irops.c
@@ -5,7 +5,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2012-2015 Florian Krohm
+ Copyright (C) 2012-2017 Florian Krohm
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -36,265 +36,271 @@
That is not necessary but helpful when supporting a new architecture.
*/
static irop_t irops[] = {
- { DEFOP(Iop_Add8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_Add16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_Add32, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_Add64, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 1 }, // mips asserts
- { DEFOP(Iop_Sub8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_Sub16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_Sub32, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_Sub64, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .tilegx = 1 }, // ppc32, mips assert
- { DEFOP(Iop_Mul8, UNDEF_LEFT), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_Mul16, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_Mul32, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_Mul64, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .tilegx = 0 }, // ppc32, mips assert
- { DEFOP(Iop_Or8, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_Or16, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_Or32, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_Or64, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 1 }, // mips asserts
- { DEFOP(Iop_And8, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_And16, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_And32, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_And64, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_Xor8, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_Xor16, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_Xor32, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_Xor64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_Shl8, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_Shl16, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_Shl32, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_Shl64, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .tilegx = 1 }, // ppc32 asserts
- { DEFOP(Iop_Shr8, UNDEF_SHR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 }, // ppc32/64 assert
- { DEFOP(Iop_Shr16, UNDEF_SHR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 }, // ppc32/64 assert
- { DEFOP(Iop_Shr32, UNDEF_SHR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_Shr64, UNDEF_SHR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .tilegx = 1 }, // ppc32 asserts
- { DEFOP(Iop_Sar8, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 }, // ppc32/64 assert
- { DEFOP(Iop_Sar16, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 }, // ppc32/64 assert
- { DEFOP(Iop_Sar32, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_Sar64, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .tilegx = 1 }, // ppc32 asserts
- { DEFOP(Iop_CmpEQ8, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_CmpEQ16, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_CmpEQ32, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_CmpEQ64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .tilegx = 1 }, // ppc32, mips assert
- { DEFOP(Iop_CmpNE8, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_CmpNE16, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_CmpNE32, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_CmpNE64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .tilegx = 1 }, // ppc32, mips assert
- { DEFOP(Iop_Not8, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_Not16, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_Not32, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_Not64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .tilegx = 1 },
- { DEFOP(Iop_CasCmpEQ8, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_CasCmpEQ16, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_CasCmpEQ32, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_CasCmpEQ64, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
+ { DEFOP(Iop_Add8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Add16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Add32, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Add64, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_Sub8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Sub16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Sub32, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Sub64, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
+ { DEFOP(Iop_Mul8, UNDEF_LEFT), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_Mul16, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_Mul32, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Mul64, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
+ { DEFOP(Iop_Or8, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Or16, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Or32, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Or64, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_And8, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_And16, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_And32, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_And64, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Xor8, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Xor16, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Xor32, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Xor64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Shl8, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_Shl16, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_Shl32, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Shl64, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 asserts
+ { DEFOP(Iop_Shr8, UNDEF_SHR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32/64 assert
+ { DEFOP(Iop_Shr16, UNDEF_SHR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32/64 assert
+ { DEFOP(Iop_Shr32, UNDEF_SHR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Shr64, UNDEF_SHR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 asserts
+ { DEFOP(Iop_Sar8, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32/64 assert
+ { DEFOP(Iop_Sar16, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32/64 assert
+ { DEFOP(Iop_Sar32, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Sar64, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 asserts
+ { DEFOP(Iop_CmpEQ8, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_CmpEQ16, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_CmpEQ32, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_CmpEQ64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
+ { DEFOP(Iop_CmpNE8, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_CmpNE16, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_CmpNE32, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_CmpNE64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
+ { DEFOP(Iop_Not8, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Not16, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Not32, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_Not64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_CasCmpEQ8, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_CasCmpEQ16, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_CasCmpEQ32, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_CasCmpEQ64, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
- { DEFOP(Iop_CasCmpNE8, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_CasCmpNE16, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_CasCmpNE32, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_CasCmpNE64, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
+ { DEFOP(Iop_CasCmpNE8, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_CasCmpNE16, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_CasCmpNE32, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_CasCmpNE64, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
{ DEFOP(Iop_ExpCmpNE8, UNDEF_UNKNOWN), }, // exact (expensive) equality
{ DEFOP(Iop_ExpCmpNE16, UNDEF_UNKNOWN), }, // exact (expensive) equality
{ DEFOP(Iop_ExpCmpNE32, UNDEF_UNKNOWN), }, // exact (expensive) equality
{ DEFOP(Iop_ExpCmpNE64, UNDEF_UNKNOWN), }, // exact (expensive) equality
- { DEFOP(Iop_MullS8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_MullS16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_MullS32, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 1 }, // mips asserts
+ { DEFOP(Iop_MullS8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_MullS16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_MullS32, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
// s390 has signed multiplication of 64-bit values but the result
// is 64-bit (not 128-bit). So we cannot test this op standalone.
- { DEFOP(Iop_MullS64, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1, .tilegx = 0 }, // ppc32, mips assert
- { DEFOP(Iop_MullU8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_MullU16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_MullU32, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =0, .mips64 = 1, .tilegx = 1 }, // mips asserts
- { DEFOP(Iop_MullU64, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1, .tilegx = 0 }, // ppc32, mips assert
- { DEFOP(Iop_Clz64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1, .tilegx = 1 }, // ppc32 asserts
- { DEFOP(Iop_Clz32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_Ctz64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0, .tilegx = 1 },
- { DEFOP(Iop_Ctz32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_CmpLT32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_CmpLT64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 1, .tilegx = 1 }, // ppc, mips assert
- { DEFOP(Iop_CmpLE32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_CmpLE64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 1, .tilegx = 1 }, // ppc, mips assert
- { DEFOP(Iop_CmpLT32U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_CmpLT64U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1, .tilegx = 1}, // ppc32, mips assert
- { DEFOP(Iop_CmpLE32U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_CmpLE64U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0, .tilegx = 0 }, // ppc32 asserts
+ { DEFOP(Iop_MullS64, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc32, mips assert
+ { DEFOP(Iop_MullU8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 },
+ { DEFOP(Iop_MullU16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 },
+ { DEFOP(Iop_MullU32, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_MullU64, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc32, mips assert
+ { DEFOP(Iop_Clz64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc32 asserts
+ { DEFOP(Iop_Clz32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 },
+ { DEFOP(Iop_Ctz64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 },
+ { DEFOP(Iop_Ctz32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 },
+ { DEFOP(Iop_CmpLT32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 },
+ { DEFOP(Iop_CmpLT64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc, mips assert
+ { DEFOP(Iop_CmpLE32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 },
+ { DEFOP(Iop_CmpLE64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc, mips assert
+ { DEFOP(Iop_CmpLT32U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 },
+ { DEFOP(Iop_CmpLT64U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1}, // ppc32, mips assert
+ { DEFOP(Iop_CmpLE32U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 },
+ { DEFOP(Iop_CmpLE64U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, // ppc32 asserts
{ DEFOP(Iop_CmpNEZ8, UNDEF_ALL), }, // not supported by mc_translate
{ DEFOP(Iop_CmpNEZ16, UNDEF_ALL), }, // not supported by mc_translate
{ DEFOP(Iop_CmpNEZ32, UNDEF_ALL), }, // not supported by mc_translate
{ DEFOP(Iop_CmpNEZ64, UNDEF_ALL), }, // not supported by mc_translate
- { DEFOP(Iop_CmpwNEZ32, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_CmpwNEZ64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 1 }, // mips asserts
+ { DEFOP(Iop_CmpwNEZ32, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_CmpwNEZ64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
{ DEFOP(Iop_Left8, UNDEF_UNKNOWN), }, // not supported by mc_translate
{ DEFOP(Iop_Left16, UNDEF_UNKNOWN), }, // not supported by mc_translate
{ DEFOP(Iop_Left32, UNDEF_UNKNOWN), }, // not supported by mc_translate
{ DEFOP(Iop_Left64, UNDEF_UNKNOWN), }, // not supported by mc_translate
{ DEFOP(Iop_Max32U, UNDEF_UNKNOWN), }, // not supported by mc_translate
- { DEFOP(Iop_CmpORD32U, UNDEF_ORD), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .tilegx = 0 }, // support added in vbit-test
- { DEFOP(Iop_CmpORD64U, UNDEF_ORD), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 }, // support added in vbit-test
- { DEFOP(Iop_CmpORD32S, UNDEF_ORD), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .tilegx = 0 }, // support added in vbit-test
- { DEFOP(Iop_CmpORD64S, UNDEF_ORD), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 }, // support added in vbit-test
- { DEFOP(Iop_DivU32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_DivS32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_DivU64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 }, // ppc32 asserts
- { DEFOP(Iop_DivS64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 }, // ppc32 asserts
- { DEFOP(Iop_DivU64E, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 }, // ppc32 asserts
- { DEFOP(Iop_DivS64E, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 }, // ppc32 asserts
- { DEFOP(Iop_DivU32E, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_DivS32E, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
+ { DEFOP(Iop_CmpORD32U, UNDEF_ORD), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, // support added in vbit-test
+ { DEFOP(Iop_CmpORD64U, UNDEF_ORD), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // support added in vbit-test
+ { DEFOP(Iop_CmpORD32S, UNDEF_ORD), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, // support added in vbit-test
+ { DEFOP(Iop_CmpORD64S, UNDEF_ORD), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // support added in vbit-test
+ { DEFOP(Iop_DivU32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_DivS32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_DivU64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32 asserts
+ { DEFOP(Iop_DivS64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32 asserts
+ { DEFOP(Iop_DivU64E, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32 asserts
+ { DEFOP(Iop_DivS64E, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32 asserts
+ { DEFOP(Iop_DivU32E, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_DivS32E, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
// On s390 the DivMod operations always appear in a certain context
// So they cannot be tested in isolation on that platform.
- { DEFOP(Iop_DivModU64to32, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_DivModS64to32, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_DivModU128to64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .tilegx = 0 }, // mips asserts
- { DEFOP(Iop_DivModS128to64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .tilegx = 0 }, // mips asserts
- { DEFOP(Iop_DivModS64to64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 }, // mips asserts
- { DEFOP(Iop_8Uto16, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_8Uto32, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_8Uto64, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .tilegx = 1 }, // ppc32 assert
- { DEFOP(Iop_16Uto32, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_16Uto64, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .tilegx = 1 }, // ppc32 assert
- { DEFOP(Iop_32Uto64, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 1 }, // mips asserts
- { DEFOP(Iop_8Sto16, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_8Sto32, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_8Sto64, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .tilegx = 1 }, // ppc32, mips assert
- { DEFOP(Iop_16Sto32, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_16Sto64, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .tilegx = 1 }, // ppc32, mips assert
- { DEFOP(Iop_32Sto64, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 1 }, // mips asserts
- { DEFOP(Iop_64to8, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .tilegx = 1 }, // ppc32, mips assert
- { DEFOP(Iop_32to8, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_64to16, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .tilegx = 1 }, // ppc32, mips assert
- { DEFOP(Iop_16to8, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_16HIto8, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_8HLto16, UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .tilegx = 0 }, // ppc isel
- { DEFOP(Iop_32to16, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_32HIto16, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_16HLto32, UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .tilegx = 0 }, // ppc isel
- { DEFOP(Iop_64to32, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 0 }, // mips asserts
- { DEFOP(Iop_64HIto32, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_32HLto64, UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 1 }, // mips asserts
- { DEFOP(Iop_128to64, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 0 }, // mips asserts
- { DEFOP(Iop_128HIto64, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 0 }, // mips asserts
- { DEFOP(Iop_64HLto128, UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 0 }, // mips asserts
- { DEFOP(Iop_Not1, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_32to1, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_64to1, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .tilegx = 1 }, // ppc32, mips assert
- { DEFOP(Iop_1Uto8, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_1Uto32, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_1Uto64, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .tilegx = 1 }, // ppc32 assert
- { DEFOP(Iop_1Sto8, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
+ { DEFOP(Iop_DivModU64to32, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_DivModS64to32, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_DivModU128to64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_DivModS128to64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_DivModS64to64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // mips asserts
+ { DEFOP(Iop_8Uto16, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_8Uto32, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_8Uto64, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 assert
+ { DEFOP(Iop_16Uto32, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_16Uto64, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 assert
+ { DEFOP(Iop_32Uto64, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_8Sto16, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_8Sto32, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_8Sto64, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
+ { DEFOP(Iop_16Sto32, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_16Sto64, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
+ { DEFOP(Iop_32Sto64, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_64to8, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
+ { DEFOP(Iop_32to8, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_64to16, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
+ { DEFOP(Iop_16to8, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_16HIto8, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_8HLto16, UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, // ppc isel
+ { DEFOP(Iop_32to16, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_32HIto16, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_16HLto32, UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, // ppc isel
+ { DEFOP(Iop_64to32, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_64HIto32, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
+ { DEFOP(Iop_32HLto64, UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_128to64, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_128HIto64, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_64HLto128, UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_Not1, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_32to1, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_64to1, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert
+ { DEFOP(Iop_1Uto8, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_1Uto32, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_1Uto64, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 assert
+ { DEFOP(Iop_1Sto8, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
{ DEFOP(Iop_1Sto16, UNDEF_ALL), }, // not handled by mc_translate
- { DEFOP(Iop_1Sto32, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_1Sto64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 1 },
- { DEFOP(Iop_AddF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 0 }, // mips asserts
- { DEFOP(Iop_SubF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 0 }, // mips asserts
- { DEFOP(Iop_MulF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 0 }, // mips asserts
- { DEFOP(Iop_DivF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 0 }, // mips asserts
- { DEFOP(Iop_AddF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_SubF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_MulF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_DivF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_AddF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_SubF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_MulF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_DivF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_NegF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_AbsF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_NegF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_AbsF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_SqrtF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 0 }, // mips asserts
- { DEFOP(Iop_SqrtF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_CmpF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_CmpF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 }, // mips asserts
- { DEFOP(Iop_CmpF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_F64toI16S, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_F64toI32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_F64toI64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_F64toI64U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_F64toI32U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_I32StoF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_I64StoF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_I64UtoF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .tilegx = 0 }, // mips asserts
- { DEFOP(Iop_I64UtoF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_I32UtoF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_I32UtoF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_F32toI32S, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_F32toI64S, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_F32toI32U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_F32toI64U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_I32StoF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_I64StoF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_F32toF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_F64toF32, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .tilegx = 0 }, // mips asserts
- { DEFOP(Iop_ReinterpF64asI64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 0 }, // mips asserts
- { DEFOP(Iop_ReinterpI64asF64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 0 }, // mips asserts
- { DEFOP(Iop_ReinterpF32asI32, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
+ { DEFOP(Iop_1Sto32, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_1Sto64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_AddF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_SubF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_MulF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_DivF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_AddF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_SubF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_MulF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_DivF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_AddF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_SubF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_MulF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_DivF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_NegF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_AbsF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_NegF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_AbsF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_SqrtF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_SqrtF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_CmpF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_CmpF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // mips asserts
+ { DEFOP(Iop_CmpF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_F64toI16S, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_F64toI32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_F64toI64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_F64toI64U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_F64toI32U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_I32StoF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_I64StoF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
+ { DEFOP(Iop_I64UtoF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, // mips asserts
+ { DEFOP(Iop_I64UtoF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_I32UtoF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_I32UtoF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_F32toI32S, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_F32toI64S, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 },
+ { DEFOP(Iop_F32toI32U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_F32toI64U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_I32StoF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_I64StoF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 },
+ { DEFOP(Iop_F32toF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_F64toF32, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_ReinterpF64asI64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_ReinterpI64asF64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_ReinterpF32asI32, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 },
// ppc requires this op to show up in a specific context. So it cannot be
// tested standalone on that platform.
- { DEFOP(Iop_ReinterpI32asF32, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_F64HLtoF128, UNDEF_CONCAT), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_F128HItoF64, UNDEF_UPPER), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_F128LOtoF64, UNDEF_TRUNC), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_AddF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_SubF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_MulF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_DivF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_MAddF128, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_MSubF128, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_NegMAddF128, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_NegMSubF128, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_NegF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_AbsF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_SqrtF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_I32StoF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_I64StoF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_I32UtoF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_I64UtoF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_F32toF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_F64toF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_F128toI32S, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_F128toI64S, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_F128toI32U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_F128toI64U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_F128toI128S, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_F128toF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_F128toF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_RndF128, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_TruncF128toI32S,UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_TruncF128toI32U,UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_TruncF128toI64U,UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_TruncF128toI64S,UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_AtanF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_Yl2xF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_Yl2xp1F64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_PRemF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_PRemC3210F64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_PRem1F64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_PRem1C3210F64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_ScaleF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_SinF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_CosF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_TanF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_2xm1F64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_RoundF128toInt, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_RoundF64toInt, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_RoundF32toInt, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_MAddF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_MSubF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_MAddF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_MSubF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_MAddF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_MSubF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_RSqrtEst5GoodF64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
- { DEFOP(Iop_RoundF64toF64_NEAREST, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_RoundF64toF64_NegINF, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_RoundF64toF64_PosINF, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_RoundF64toF64_ZERO, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 0 },
- { DEFOP(Iop_TruncF64asF32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1, .tilegx = 0 }, // mips asserts
- { DEFOP(Iop_RoundF64toF32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0, .tilegx = 0 },
+ { DEFOP(Iop_ReinterpI32asF32, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_F64HLtoF128, UNDEF_CONCAT), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_F128HItoF64, UNDEF_UPPER), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_F128LOtoF64, UNDEF_TRUNC), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_AddF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_SubF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_MulF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_DivF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_MAddF128, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_MSubF128, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_NegMAddF128, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_NegMSubF128, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_NegF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_AbsF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_SqrtF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_I32StoF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_I64StoF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_I32UtoF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_I64UtoF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_F32toF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_F64toF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_F128toI32S, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_F128toI64S, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_F128toI32U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_F128toI64U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_F128toI128S, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_F128toF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_F128toF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_RndF128, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_TruncF128toI32S,UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_TruncF128toI32U,UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_TruncF128toI64U,UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_TruncF128toI64S,UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_AtanF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_Yl2xF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_Yl2xp1F64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_PRemF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_PRemC3210F64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_PRem1F64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_PRem1C3210F64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_ScaleF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_SinF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_CosF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_TanF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_2xm1F64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_RoundF128toInt, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_RoundF64toInt, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 },
+ { DEFOP(Iop_RoundF32toInt, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 },
+ { DEFOP(Iop_MAddF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 },
+ { DEFOP(Iop_MSubF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 },
+ { DEFOP(Iop_MAddF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
+ { DEFOP(Iop_MSubF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
+ { DEFOP(Iop_MAddF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_MSubF64r32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_RSqrtEst5GoodF64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
+ { DEFOP(Iop_RoundF64toF64_NEAREST, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
+ { DEFOP(Iop_RoundF64toF64_NegINF, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
+ { DEFOP(Iop_RoundF64toF64_PosINF, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
+ { DEFOP(Iop_RoundF64toF64_ZERO, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 },
+ { DEFOP(Iop_TruncF64asF32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts
+ { DEFOP(Iop_RoundF64toF32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 },
{ DEFOP(Iop_RecpExpF64, UNDEF_UNKNOWN), },
{ DEFOP(Iop_RecpExpF32, UNDEF_UNKNOWN), },
+ /* --------- Possibly required by IEEE 754-2008. --------- */
+ { DEFOP(Iop_MaxNumF64, UNDEF_ALL), .arm = 1 },
+ { DEFOP(Iop_MinNumF64, UNDEF_ALL), .arm = 1 },
+ { DEFOP(Iop_MaxNumF32, UNDEF_ALL), .arm = 1 },
+ { DEFOP(Iop_MinNumF32, UNDEF_ALL), .arm = 1 },
+
/* ------------------ 16-bit scalar FP ------------------ */
{ DEFOP(Iop_F16toF64, UNDEF_ALL), .arm64 = 1 },
{ DEFOP(Iop_F64toF16, UNDEF_ALL), .arm64 = 1 },
@@ -1325,9 +1331,6 @@
#ifdef __i386__
return p->x86 ? p : NULL;
#endif
-#ifdef __tilegx__
- return p->tilegx ? p : NULL;
-#endif
return NULL;
}
}
diff --git a/memcheck/tests/vbit-test/main.c b/memcheck/tests/vbit-test/main.c
index d6bd72a..ba5d2eb 100644
--- a/memcheck/tests/vbit-test/main.c
+++ b/memcheck/tests/vbit-test/main.c
@@ -4,7 +4,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2012-2015 Florian Krohm
+ Copyright (C) 2012-2017 Florian Krohm
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/memcheck/tests/vbit-test/qernary.c b/memcheck/tests/vbit-test/qernary.c
index fbe2eaa..7643333 100644
--- a/memcheck/tests/vbit-test/qernary.c
+++ b/memcheck/tests/vbit-test/qernary.c
@@ -4,7 +4,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2012-2015 Florian Krohm
+ Copyright (C) 2012-2017 Florian Krohm
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/memcheck/tests/vbit-test/ternary.c b/memcheck/tests/vbit-test/ternary.c
index c84570c..1658c55 100644
--- a/memcheck/tests/vbit-test/ternary.c
+++ b/memcheck/tests/vbit-test/ternary.c
@@ -4,7 +4,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2012-2015 Florian Krohm
+ Copyright (C) 2012-2017 Florian Krohm
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/memcheck/tests/vbit-test/unary.c b/memcheck/tests/vbit-test/unary.c
index d47cc8a..aa0aeb9 100644
--- a/memcheck/tests/vbit-test/unary.c
+++ b/memcheck/tests/vbit-test/unary.c
@@ -4,7 +4,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2012-2015 Florian Krohm
+ Copyright (C) 2012-2017 Florian Krohm
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/memcheck/tests/vbit-test/util.c b/memcheck/tests/vbit-test/util.c
index 29a6883..d829d74 100644
--- a/memcheck/tests/vbit-test/util.c
+++ b/memcheck/tests/vbit-test/util.c
@@ -4,7 +4,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2012-2015 Florian Krohm
+ Copyright (C) 2012-2017 Florian Krohm
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/memcheck/tests/vbit-test/valgrind.c b/memcheck/tests/vbit-test/valgrind.c
index 7786f11..870c535 100644
--- a/memcheck/tests/vbit-test/valgrind.c
+++ b/memcheck/tests/vbit-test/valgrind.c
@@ -4,7 +4,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2012-2015 Florian Krohm
+ Copyright (C) 2012-2017 Florian Krohm
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/memcheck/tests/vbit-test/vbits.c b/memcheck/tests/vbit-test/vbits.c
index 47eabdb..8ba6532 100644
--- a/memcheck/tests/vbit-test/vbits.c
+++ b/memcheck/tests/vbit-test/vbits.c
@@ -4,7 +4,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2012-2015 Florian Krohm
+ Copyright (C) 2012-2017 Florian Krohm
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -1055,7 +1055,7 @@
assert( v1_num_bits == v2_num_bits);
/* Comparison only produces 32-bit or 64-bit value where
- * the lower 3 bits are set to indicate, less than, equal and greater then.
+ * the lower 3 bits are set to indicate, less than, equal and greater than.
*/
switch (v1_num_bits) {
case 32:
diff --git a/memcheck/tests/vbit-test/vbits.h b/memcheck/tests/vbit-test/vbits.h
index c6f7540..0782e2d 100644
--- a/memcheck/tests/vbit-test/vbits.h
+++ b/memcheck/tests/vbit-test/vbits.h
@@ -4,7 +4,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2012-2015 Florian Krohm
+ Copyright (C) 2012-2017 Florian Krohm
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/memcheck/tests/vbit-test/vtest.h b/memcheck/tests/vbit-test/vtest.h
index 7831b51..540e783 100644
--- a/memcheck/tests/vbit-test/vtest.h
+++ b/memcheck/tests/vbit-test/vtest.h
@@ -4,7 +4,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2012-2015 Florian Krohm
+ Copyright (C) 2012-2017 Florian Krohm
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -183,7 +183,6 @@
unsigned x86 : 1;
unsigned mips32 : 1;
unsigned mips64 : 1;
- unsigned tilegx : 1;
} irop_t;
diff --git a/memcheck/tests/x86-linux/Makefile.in b/memcheck/tests/x86-linux/Makefile.in
index 275c4b6..04f2e20 100644
--- a/memcheck/tests/x86-linux/Makefile.in
+++ b/memcheck/tests/x86-linux/Makefile.in
@@ -112,7 +112,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -261,6 +261,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -431,6 +432,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -441,6 +443,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -515,8 +518,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -561,7 +562,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/memcheck/tests/x86-linux/scalar.c b/memcheck/tests/x86-linux/scalar.c
index c0a318b..213a5ad 100644
--- a/memcheck/tests/x86-linux/scalar.c
+++ b/memcheck/tests/x86-linux/scalar.c
@@ -6,6 +6,7 @@
#include <sched.h>
#include <signal.h>
#include <linux/mman.h> // MREMAP_FIXED
+#include <sys/prctl.h>
// Here we are trying to trigger every syscall error (scalar errors and
// memory errors) for every syscall. We do this by passing a lot of bogus
@@ -85,10 +86,18 @@
SY(__NR_unlink, x0); FAIL;
// __NR_execve 11
- // Nb: could have 3 memory errors if we pass x0+1 as the 2nd and 3rd
- // args, except for bug #93174.
GO(__NR_execve, "3s 1m");
- SY(__NR_execve, x0, x0, x0); FAIL;
+ SY(__NR_execve, x0 + 1, x0 + 1, x0); FAIL;
+
+ GO(__NR_execve, "3s 1m");
+ SY(__NR_execve, x0 + 1, x0, x0 + 1); FAIL;
+
+ char *argv_envp[] = {(char *) (x0 + 1), NULL};
+ GO(__NR_execve, "4s 2m");
+ SY(__NR_execve, x0 + 1, x0 + argv_envp, x0); FAIL;
+
+ GO(__NR_execve, "4s 2m");
+ SY(__NR_execve, x0 + 1, x0, x0 + argv_envp); FAIL;
// __NR_chdir 12
GO(__NR_chdir, "1s 1m");
@@ -279,7 +288,7 @@
// For F_GETLK the 3rd arg is 'lock'. On x86, this fails w/EBADF. But
// on amd64 in 32-bit mode it fails w/EFAULT. We don't check the 1st two
// args for the reason given above.
- GO(__NR_fcntl, "(GETLK) 1s 0m");
+ GO(__NR_fcntl, "(GETLK) 1s 5m");
SY(__NR_fcntl, -1, F_GETLK, x0); FAIL; //FAILx(EBADF);
// __NR_mpx 56
@@ -767,6 +776,16 @@
GO(__NR_prctl, "5s 0m");
SY(__NR_prctl, x0, x0, x0, x0, x0); FAIL;
+ char buf16[16] = "123456789012345.";
+ buf16[15] = x0; // this will cause 'using unitialised value'
+ GO(__NR_prctl, "2s 0m");
+ SY(__NR_prctl, x0 + PR_SET_NAME, buf16); SUCC;
+
+ char buf17[17] = "1234567890123456.";
+ buf17[16] = x0; // this must not cause 'using unitialised value'
+ GO(__NR_prctl, "1s 0m");
+ SY(__NR_prctl, x0 + PR_SET_NAME, buf17); SUCC;
+
// __NR_rt_sigreturn 173
GO(__NR_rt_sigreturn, "n/a");
//SY(__NR_rt_sigreturn); // (Not yet handled by Valgrind) FAIL;
@@ -792,8 +811,8 @@
SY(__NR_rt_sigqueueinfo, x0, x0+1, x0); FAIL;
// __NR_rt_sigsuspend 179
- GO(__NR_rt_sigsuspend, "ignore");
- // (I don't know how to test this...)
+ GO(__NR_rt_sigsuspend, "2s 1m");
+ SY(__NR_rt_sigsuspend, x0 + 1, x0 + sizeof(sigset_t)); FAILx(EFAULT);
// __NR_pread64 180
GO(__NR_pread64, "5s 1m");
@@ -1068,8 +1087,8 @@
#define FUTEX_WAIT 0
#endif
// XXX: again, glibc not doing 6th arg means we have only 5s errors
- GO(__NR_futex, "5s 2m");
- SY(__NR_futex, x0+FUTEX_WAIT, x0, x0, x0+1, x0, x0); FAIL;
+ GO(__NR_futex, "4s 2m");
+ SY(__NR_futex, x0+FUTEX_WAIT, x0, x0, x0+1); FAIL;
// __NR_sched_setaffinity 241
GO(__NR_sched_setaffinity, "3s 1m");
diff --git a/memcheck/tests/x86-linux/scalar.stderr.exp b/memcheck/tests/x86-linux/scalar.stderr.exp
index d1af313..470023f 100644
--- a/memcheck/tests/x86-linux/scalar.stderr.exp
+++ b/memcheck/tests/x86-linux/scalar.stderr.exp
@@ -12,23 +12,23 @@
-----------------------------------------------------
Syscall param (syscallno) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:51)
+ by 0x........: main (scalar.c:52)
Syscall param read(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:51)
+ by 0x........: main (scalar.c:52)
Syscall param read(buf) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:51)
+ by 0x........: main (scalar.c:52)
Syscall param read(count) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:51)
+ by 0x........: main (scalar.c:52)
Syscall param read(buf) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:51)
+ by 0x........: main (scalar.c:52)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -36,19 +36,19 @@
-----------------------------------------------------
Syscall param write(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:55)
+ by 0x........: main (scalar.c:56)
Syscall param write(buf) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:55)
+ by 0x........: main (scalar.c:56)
Syscall param write(count) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:55)
+ by 0x........: main (scalar.c:56)
Syscall param write(buf) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:55)
+ by 0x........: main (scalar.c:56)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -56,15 +56,15 @@
-----------------------------------------------------
Syscall param open(filename) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:59)
+ by 0x........: main (scalar.c:60)
Syscall param open(flags) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:59)
+ by 0x........: main (scalar.c:60)
Syscall param open(filename) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:59)
+ by 0x........: main (scalar.c:60)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -72,33 +72,33 @@
-----------------------------------------------------
Syscall param open(mode) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:65)
+ by 0x........: main (scalar.c:66)
-----------------------------------------------------
6: __NR_close 1s 0m
-----------------------------------------------------
Syscall param close(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:69)
+ by 0x........: main (scalar.c:70)
-----------------------------------------------------
7: __NR_waitpid 3s 1m
-----------------------------------------------------
Syscall param waitpid(pid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:73)
+ by 0x........: main (scalar.c:74)
Syscall param waitpid(status) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:73)
+ by 0x........: main (scalar.c:74)
Syscall param waitpid(options) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:73)
+ by 0x........: main (scalar.c:74)
Syscall param waitpid(status) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:73)
+ by 0x........: main (scalar.c:74)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -106,15 +106,15 @@
-----------------------------------------------------
Syscall param creat(pathname) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:77)
+ by 0x........: main (scalar.c:78)
Syscall param creat(mode) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:77)
+ by 0x........: main (scalar.c:78)
Syscall param creat(pathname) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:77)
+ by 0x........: main (scalar.c:78)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -122,20 +122,20 @@
-----------------------------------------------------
Syscall param link(oldpath) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:81)
+ by 0x........: main (scalar.c:82)
Syscall param link(newpath) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:81)
+ by 0x........: main (scalar.c:82)
Syscall param link(oldpath) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:81)
+ by 0x........: main (scalar.c:82)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param link(newpath) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:81)
+ by 0x........: main (scalar.c:82)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -143,11 +143,11 @@
-----------------------------------------------------
Syscall param unlink(pathname) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:85)
+ by 0x........: main (scalar.c:86)
Syscall param unlink(pathname) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:85)
+ by 0x........: main (scalar.c:86)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -155,19 +155,101 @@
-----------------------------------------------------
Syscall param execve(filename) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:91)
+ by 0x........: main (scalar.c:90)
Syscall param execve(argv) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:91)
+ by 0x........: main (scalar.c:90)
Syscall param execve(envp) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:91)
+ by 0x........: main (scalar.c:90)
Syscall param execve(filename) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:91)
+ by 0x........: main (scalar.c:90)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+-----------------------------------------------------
+ 11: __NR_execve 3s 1m
+-----------------------------------------------------
+Syscall param execve(filename) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:93)
+
+Syscall param execve(argv) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:93)
+
+Syscall param execve(envp) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:93)
+
+Syscall param execve(filename) points to unaddressable byte(s)
+ ...
+ by 0x........: main (scalar.c:93)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+-----------------------------------------------------
+ 11: __NR_execve 4s 2m
+-----------------------------------------------------
+Syscall param execve(filename) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:97)
+
+Syscall param execve(argv) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:97)
+
+Syscall param execve(envp) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:97)
+
+Syscall param execve(filename) points to unaddressable byte(s)
+ ...
+ by 0x........: main (scalar.c:97)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+Syscall param execve(argv) points to uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:97)
+ Address 0x........ is on thread 1's stack
+ in frame #1, created by main (scalar.c:29)
+
+Syscall param execve(argv[i]) points to unaddressable byte(s)
+ ...
+ by 0x........: main (scalar.c:97)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+-----------------------------------------------------
+ 11: __NR_execve 4s 2m
+-----------------------------------------------------
+Syscall param execve(filename) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:100)
+
+Syscall param execve(argv) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:100)
+
+Syscall param execve(envp) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:100)
+
+Syscall param execve(filename) points to unaddressable byte(s)
+ ...
+ by 0x........: main (scalar.c:100)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+Syscall param execve(envp) points to uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:100)
+ Address 0x........ is on thread 1's stack
+ in frame #1, created by main (scalar.c:29)
+
+Syscall param execve(envp[i]) points to unaddressable byte(s)
+ ...
+ by 0x........: main (scalar.c:100)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -175,11 +257,11 @@
-----------------------------------------------------
Syscall param chdir(path) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:95)
+ by 0x........: main (scalar.c:104)
Syscall param chdir(path) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:95)
+ by 0x........: main (scalar.c:104)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -187,11 +269,11 @@
-----------------------------------------------------
Syscall param time(t) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:99)
+ by 0x........: main (scalar.c:108)
Syscall param time(t) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:99)
+ by 0x........: main (scalar.c:108)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -199,19 +281,19 @@
-----------------------------------------------------
Syscall param mknod(pathname) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:103)
+ by 0x........: main (scalar.c:112)
Syscall param mknod(mode) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:103)
+ by 0x........: main (scalar.c:112)
Syscall param mknod(dev) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:103)
+ by 0x........: main (scalar.c:112)
Syscall param mknod(pathname) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:103)
+ by 0x........: main (scalar.c:112)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -219,15 +301,15 @@
-----------------------------------------------------
Syscall param chmod(path) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:107)
+ by 0x........: main (scalar.c:116)
Syscall param chmod(mode) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:107)
+ by 0x........: main (scalar.c:116)
Syscall param chmod(path) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:107)
+ by 0x........: main (scalar.c:116)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -244,15 +326,15 @@
-----------------------------------------------------
Syscall param lseek(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:123)
+ by 0x........: main (scalar.c:132)
Syscall param lseek(offset) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:123)
+ by 0x........: main (scalar.c:132)
Syscall param lseek(whence) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:123)
+ by 0x........: main (scalar.c:132)
-----------------------------------------------------
20: __NR_getpid 0s 0m
@@ -262,32 +344,32 @@
-----------------------------------------------------
Syscall param mount(source) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:131)
+ by 0x........: main (scalar.c:140)
Syscall param mount(target) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:131)
+ by 0x........: main (scalar.c:140)
Syscall param mount(type) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:131)
+ by 0x........: main (scalar.c:140)
Syscall param mount(flags) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:131)
+ by 0x........: main (scalar.c:140)
Syscall param mount(data) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:131)
+ by 0x........: main (scalar.c:140)
Syscall param mount(target) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:131)
+ by 0x........: main (scalar.c:140)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param mount(type) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:131)
+ by 0x........: main (scalar.c:140)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -295,11 +377,11 @@
-----------------------------------------------------
Syscall param umount(path) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:135)
+ by 0x........: main (scalar.c:144)
Syscall param umount(path) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:135)
+ by 0x........: main (scalar.c:144)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -307,7 +389,7 @@
-----------------------------------------------------
Syscall param setuid16(uid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:139)
+ by 0x........: main (scalar.c:148)
-----------------------------------------------------
24: __NR_getuid 0s 0m
@@ -320,23 +402,23 @@
-----------------------------------------------------
Syscall param ptrace(request) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:152)
+ by 0x........: main (scalar.c:161)
Syscall param ptrace(pid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:152)
+ by 0x........: main (scalar.c:161)
Syscall param ptrace(addr) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:152)
+ by 0x........: main (scalar.c:161)
Syscall param ptrace(data) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:152)
+ by 0x........: main (scalar.c:161)
Syscall param ptrace(getregs) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:152)
+ by 0x........: main (scalar.c:161)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -344,7 +426,7 @@
-----------------------------------------------------
Syscall param alarm(seconds) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:156)
+ by 0x........: main (scalar.c:165)
-----------------------------------------------------
28: __NR_oldfstat n/a
@@ -357,20 +439,20 @@
-----------------------------------------------------
Syscall param utime(filename) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:168)
+ by 0x........: main (scalar.c:177)
Syscall param utime(buf) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:168)
+ by 0x........: main (scalar.c:177)
Syscall param utime(filename) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:168)
+ by 0x........: main (scalar.c:177)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param utime(buf) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:168)
+ by 0x........: main (scalar.c:177)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -384,15 +466,15 @@
-----------------------------------------------------
Syscall param access(pathname) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:180)
+ by 0x........: main (scalar.c:189)
Syscall param access(mode) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:180)
+ by 0x........: main (scalar.c:189)
Syscall param access(pathname) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:180)
+ by 0x........: main (scalar.c:189)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -400,7 +482,7 @@
-----------------------------------------------------
Syscall param nice(inc) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:184)
+ by 0x........: main (scalar.c:193)
-----------------------------------------------------
35: __NR_ftime ni
@@ -413,31 +495,31 @@
-----------------------------------------------------
Syscall param kill(pid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:196)
+ by 0x........: main (scalar.c:205)
Syscall param kill(signal) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:196)
+ by 0x........: main (scalar.c:205)
-----------------------------------------------------
38: __NR_rename 2s 2m
-----------------------------------------------------
Syscall param rename(oldpath) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:200)
+ by 0x........: main (scalar.c:209)
Syscall param rename(newpath) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:200)
+ by 0x........: main (scalar.c:209)
Syscall param rename(oldpath) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:200)
+ by 0x........: main (scalar.c:209)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param rename(newpath) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:200)
+ by 0x........: main (scalar.c:209)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -445,15 +527,15 @@
-----------------------------------------------------
Syscall param mkdir(pathname) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:204)
+ by 0x........: main (scalar.c:213)
Syscall param mkdir(mode) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:204)
+ by 0x........: main (scalar.c:213)
Syscall param mkdir(pathname) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:204)
+ by 0x........: main (scalar.c:213)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -461,11 +543,11 @@
-----------------------------------------------------
Syscall param rmdir(pathname) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:208)
+ by 0x........: main (scalar.c:217)
Syscall param rmdir(pathname) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:208)
+ by 0x........: main (scalar.c:217)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -473,18 +555,18 @@
-----------------------------------------------------
Syscall param dup(oldfd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:212)
+ by 0x........: main (scalar.c:221)
-----------------------------------------------------
42: __NR_pipe 1s 1m
-----------------------------------------------------
Syscall param pipe(filedes) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:216)
+ by 0x........: main (scalar.c:225)
Syscall param pipe(filedes) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:216)
+ by 0x........: main (scalar.c:225)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -492,11 +574,14 @@
-----------------------------------------------------
Syscall param times(buf) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:220)
+ by 0x........: main (scalar.c:229)
+
+More than 100 errors detected. Subsequent errors
+will still be recorded, but in less detail than before.
Syscall param times(buf) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:220)
+ by 0x........: main (scalar.c:229)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -507,14 +592,14 @@
-----------------------------------------------------
Syscall param brk(end_data_segment) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:228)
+ by 0x........: main (scalar.c:237)
-----------------------------------------------------
46: __NR_setgid 1s 0m
-----------------------------------------------------
Syscall param setgid16(gid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:232)
+ by 0x........: main (scalar.c:241)
-----------------------------------------------------
47: __NR_getgid 0s 0m
@@ -533,11 +618,11 @@
-----------------------------------------------------
Syscall param acct(filename) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:252)
+ by 0x........: main (scalar.c:261)
Syscall param acct(filename) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:252)
+ by 0x........: main (scalar.c:261)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -545,15 +630,15 @@
-----------------------------------------------------
Syscall param umount2(path) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:256)
+ by 0x........: main (scalar.c:265)
Syscall param umount2(flags) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:256)
+ by 0x........: main (scalar.c:265)
Syscall param umount2(path) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:256)
+ by 0x........: main (scalar.c:265)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -564,19 +649,19 @@
-----------------------------------------------------
Syscall param ioctl(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:265)
+ by 0x........: main (scalar.c:274)
Syscall param ioctl(request) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:265)
+ by 0x........: main (scalar.c:274)
Syscall param ioctl(arg) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:265)
+ by 0x........: main (scalar.c:274)
Syscall param ioctl(TCSET{S,SW,SF}) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:265)
+ by 0x........: main (scalar.c:274)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -584,25 +669,50 @@
-----------------------------------------------------
Syscall param fcntl(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:271)
+ by 0x........: main (scalar.c:280)
Syscall param fcntl(cmd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:271)
+ by 0x........: main (scalar.c:280)
-----------------------------------------------------
55: __NR_fcntl (DUPFD) 1s 0m
-----------------------------------------------------
Syscall param fcntl(arg) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:277)
+ by 0x........: main (scalar.c:286)
-----------------------------------------------------
- 55: __NR_fcntl (GETLK) 1s 0m
+ 55: __NR_fcntl (GETLK) 1s 5m
-----------------------------------------------------
Syscall param fcntl(lock) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:283)
+ by 0x........: main (scalar.c:292)
+
+Syscall param fcntl(lock->l_type) points to unaddressable byte(s)
+ ...
+ by 0x........: main (scalar.c:292)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+Syscall param fcntl(lock->l_whence) points to unaddressable byte(s)
+ ...
+ by 0x........: main (scalar.c:292)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+Syscall param fcntl(lock->l_start) points to unaddressable byte(s)
+ ...
+ by 0x........: main (scalar.c:292)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+Syscall param fcntl(lock->l_len) points to unaddressable byte(s)
+ ...
+ by 0x........: main (scalar.c:292)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+Syscall param fcntl(lock->l_pid) points to unaddressable byte(s)
+ ...
+ by 0x........: main (scalar.c:292)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
56: __NR_mpx ni
@@ -610,16 +720,13 @@
-----------------------------------------------------
57: __NR_setpgid 2s 0m
-----------------------------------------------------
-
-More than 100 errors detected. Subsequent errors
-will still be recorded, but in less detail than before.
Syscall param setpgid(pid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:291)
+ by 0x........: main (scalar.c:300)
Syscall param setpgid(pgid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:291)
+ by 0x........: main (scalar.c:300)
-----------------------------------------------------
58: __NR_ulimit ni
@@ -632,18 +739,18 @@
-----------------------------------------------------
Syscall param umask(mask) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:303)
+ by 0x........: main (scalar.c:312)
-----------------------------------------------------
61: __NR_chroot 1s 1m
-----------------------------------------------------
Syscall param chroot(path) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:307)
+ by 0x........: main (scalar.c:316)
Syscall param chroot(path) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:307)
+ by 0x........: main (scalar.c:316)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -654,11 +761,11 @@
-----------------------------------------------------
Syscall param dup2(oldfd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:315)
+ by 0x........: main (scalar.c:324)
Syscall param dup2(newfd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:315)
+ by 0x........: main (scalar.c:324)
-----------------------------------------------------
64: __NR_getppid 0s 0m
@@ -674,43 +781,43 @@
-----------------------------------------------------
Syscall param sigaction(signum) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:331)
+ by 0x........: main (scalar.c:340)
Syscall param sigaction(act) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:331)
+ by 0x........: main (scalar.c:340)
Syscall param sigaction(oldact) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:331)
+ by 0x........: main (scalar.c:340)
Syscall param sigaction(act->sa_handler) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:331)
+ by 0x........: main (scalar.c:340)
Address 0x........ is 0 bytes after a block of size 4 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: main (scalar.c:30)
+ by 0x........: main (scalar.c:31)
Syscall param sigaction(act->sa_mask) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:331)
+ by 0x........: main (scalar.c:340)
Address 0x........ is 4 bytes after a block of size 4 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: main (scalar.c:30)
+ by 0x........: main (scalar.c:31)
Syscall param sigaction(act->sa_flags) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:331)
+ by 0x........: main (scalar.c:340)
Address 0x........ is 8 bytes after a block of size 4 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: main (scalar.c:30)
+ by 0x........: main (scalar.c:31)
Syscall param sigaction(oldact) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:331)
+ by 0x........: main (scalar.c:340)
Address 0x........ is 0 bytes after a block of size 4 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: main (scalar.c:30)
+ by 0x........: main (scalar.c:31)
-----------------------------------------------------
68: __NR_sgetmask n/a
@@ -723,22 +830,22 @@
-----------------------------------------------------
Syscall param setreuid16(ruid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:343)
+ by 0x........: main (scalar.c:352)
Syscall param setreuid16(euid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:343)
+ by 0x........: main (scalar.c:352)
-----------------------------------------------------
71: __NR_setregid 2s 0m
-----------------------------------------------------
Syscall param setregid16(rgid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:347)
+ by 0x........: main (scalar.c:356)
Syscall param setregid16(egid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:347)
+ by 0x........: main (scalar.c:356)
-----------------------------------------------------
72: __NR_sigsuspend ignore
@@ -748,11 +855,11 @@
-----------------------------------------------------
Syscall param sigpending(set) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:356)
+ by 0x........: main (scalar.c:365)
Syscall param sigpending(set) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:356)
+ by 0x........: main (scalar.c:365)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -763,15 +870,15 @@
-----------------------------------------------------
Syscall param setrlimit(resource) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:364)
+ by 0x........: main (scalar.c:373)
Syscall param setrlimit(rlim) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:364)
+ by 0x........: main (scalar.c:373)
Syscall param setrlimit(rlim) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:364)
+ by 0x........: main (scalar.c:373)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -779,15 +886,15 @@
-----------------------------------------------------
Syscall param old_getrlimit(resource) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:368)
+ by 0x........: main (scalar.c:377)
Syscall param old_getrlimit(rlim) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:368)
+ by 0x........: main (scalar.c:377)
Syscall param old_getrlimit(rlim) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:368)
+ by 0x........: main (scalar.c:377)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -795,15 +902,15 @@
-----------------------------------------------------
Syscall param getrusage(who) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:372)
+ by 0x........: main (scalar.c:381)
Syscall param getrusage(usage) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:372)
+ by 0x........: main (scalar.c:381)
Syscall param getrusage(usage) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:372)
+ by 0x........: main (scalar.c:381)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -811,20 +918,20 @@
-----------------------------------------------------
Syscall param gettimeofday(tv) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:376)
+ by 0x........: main (scalar.c:385)
Syscall param gettimeofday(tz) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:376)
+ by 0x........: main (scalar.c:385)
Syscall param gettimeofday(tv) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:376)
+ by 0x........: main (scalar.c:385)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param gettimeofday(tz) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:376)
+ by 0x........: main (scalar.c:385)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -832,20 +939,20 @@
-----------------------------------------------------
Syscall param settimeofday(tv) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:380)
+ by 0x........: main (scalar.c:389)
Syscall param settimeofday(tz) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:380)
+ by 0x........: main (scalar.c:389)
Syscall param settimeofday(tv) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:380)
+ by 0x........: main (scalar.c:389)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param settimeofday(tz) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:380)
+ by 0x........: main (scalar.c:389)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -853,15 +960,15 @@
-----------------------------------------------------
Syscall param getgroups16(size) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:384)
+ by 0x........: main (scalar.c:393)
Syscall param getgroups16(list) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:384)
+ by 0x........: main (scalar.c:393)
Syscall param getgroups16(list) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:384)
+ by 0x........: main (scalar.c:393)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -869,15 +976,15 @@
-----------------------------------------------------
Syscall param setgroups16(size) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:388)
+ by 0x........: main (scalar.c:397)
Syscall param setgroups16(list) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:388)
+ by 0x........: main (scalar.c:397)
Syscall param setgroups16(list) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:388)
+ by 0x........: main (scalar.c:397)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -885,32 +992,32 @@
-----------------------------------------------------
Syscall param old_select(args) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:394)
+ by 0x........: main (scalar.c:403)
Syscall param old_select(args) points to uninitialised byte(s)
...
- by 0x........: main (scalar.c:394)
+ by 0x........: main (scalar.c:403)
Address 0x........ is on thread 1's stack
- in frame #1, created by main (scalar.c:28)
+ in frame #1, created by main (scalar.c:29)
Syscall param old_select(readfds) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:394)
+ by 0x........: main (scalar.c:403)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param old_select(writefds) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:394)
+ by 0x........: main (scalar.c:403)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param old_select(exceptfds) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:394)
+ by 0x........: main (scalar.c:403)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param old_select(timeout) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:394)
+ by 0x........: main (scalar.c:403)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -918,20 +1025,20 @@
-----------------------------------------------------
Syscall param symlink(oldpath) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:399)
+ by 0x........: main (scalar.c:408)
Syscall param symlink(newpath) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:399)
+ by 0x........: main (scalar.c:408)
Syscall param symlink(oldpath) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:399)
+ by 0x........: main (scalar.c:408)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param symlink(newpath) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:399)
+ by 0x........: main (scalar.c:408)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -942,24 +1049,24 @@
-----------------------------------------------------
Syscall param readlink(path) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:407)
+ by 0x........: main (scalar.c:416)
Syscall param readlink(buf) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:407)
+ by 0x........: main (scalar.c:416)
Syscall param readlink(bufsiz) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:407)
+ by 0x........: main (scalar.c:416)
Syscall param readlink(path) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:407)
+ by 0x........: main (scalar.c:416)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param readlink(buf) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:407)
+ by 0x........: main (scalar.c:416)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -979,39 +1086,39 @@
-----------------------------------------------------
Syscall param old_mmap(args) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:429)
+ by 0x........: main (scalar.c:438)
Syscall param old_mmap(args) points to uninitialised byte(s)
...
- by 0x........: main (scalar.c:429)
+ by 0x........: main (scalar.c:438)
Address 0x........ is on thread 1's stack
- in frame #1, created by main (scalar.c:28)
+ in frame #1, created by main (scalar.c:29)
-----------------------------------------------------
91: __NR_munmap 2s 0m
-----------------------------------------------------
Syscall param munmap(start) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:434)
+ by 0x........: main (scalar.c:443)
Syscall param munmap(length) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:434)
+ by 0x........: main (scalar.c:443)
-----------------------------------------------------
92: __NR_truncate 2s 1m
-----------------------------------------------------
Syscall param truncate(path) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:438)
+ by 0x........: main (scalar.c:447)
Syscall param truncate(length) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:438)
+ by 0x........: main (scalar.c:447)
Syscall param truncate(path) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:438)
+ by 0x........: main (scalar.c:447)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1019,63 +1126,63 @@
-----------------------------------------------------
Syscall param ftruncate(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:442)
+ by 0x........: main (scalar.c:451)
Syscall param ftruncate(length) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:442)
+ by 0x........: main (scalar.c:451)
-----------------------------------------------------
94: __NR_fchmod 2s 0m
-----------------------------------------------------
Syscall param fchmod(fildes) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:446)
+ by 0x........: main (scalar.c:455)
Syscall param fchmod(mode) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:446)
+ by 0x........: main (scalar.c:455)
-----------------------------------------------------
95: __NR_fchown 3s 0m
-----------------------------------------------------
Syscall param fchown16(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:450)
+ by 0x........: main (scalar.c:459)
Syscall param fchown16(owner) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:450)
+ by 0x........: main (scalar.c:459)
Syscall param fchown16(group) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:450)
+ by 0x........: main (scalar.c:459)
-----------------------------------------------------
96: __NR_getpriority 2s 0m
-----------------------------------------------------
Syscall param getpriority(which) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:454)
+ by 0x........: main (scalar.c:463)
Syscall param getpriority(who) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:454)
+ by 0x........: main (scalar.c:463)
-----------------------------------------------------
97: __NR_setpriority 3s 0m
-----------------------------------------------------
Syscall param setpriority(which) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:458)
+ by 0x........: main (scalar.c:467)
Syscall param setpriority(who) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:458)
+ by 0x........: main (scalar.c:467)
Syscall param setpriority(prio) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:458)
+ by 0x........: main (scalar.c:467)
-----------------------------------------------------
98: __NR_profil ni
@@ -1085,20 +1192,20 @@
-----------------------------------------------------
Syscall param statfs(path) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:466)
+ by 0x........: main (scalar.c:475)
Syscall param statfs(buf) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:466)
+ by 0x........: main (scalar.c:475)
Syscall param statfs(path) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:466)
+ by 0x........: main (scalar.c:475)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param statfs(buf) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:466)
+ by 0x........: main (scalar.c:475)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1106,15 +1213,15 @@
-----------------------------------------------------
Syscall param fstatfs(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:470)
+ by 0x........: main (scalar.c:479)
Syscall param fstatfs(buf) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:470)
+ by 0x........: main (scalar.c:479)
Syscall param fstatfs(buf) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:470)
+ by 0x........: main (scalar.c:479)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1122,15 +1229,15 @@
-----------------------------------------------------
Syscall param ioperm(from) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:474)
+ by 0x........: main (scalar.c:483)
Syscall param ioperm(num) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:474)
+ by 0x........: main (scalar.c:483)
Syscall param ioperm(turn_on) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:474)
+ by 0x........: main (scalar.c:483)
-----------------------------------------------------
102: __NR_socketcall XXX
@@ -1140,19 +1247,19 @@
-----------------------------------------------------
Syscall param syslog(type) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:482)
+ by 0x........: main (scalar.c:491)
Syscall param syslog(bufp) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:482)
+ by 0x........: main (scalar.c:491)
Syscall param syslog(len) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:482)
+ by 0x........: main (scalar.c:491)
Syscall param syslog(bufp) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:482)
+ by 0x........: main (scalar.c:491)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1160,34 +1267,34 @@
-----------------------------------------------------
Syscall param setitimer(which) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:486)
+ by 0x........: main (scalar.c:495)
Syscall param setitimer(value) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:486)
+ by 0x........: main (scalar.c:495)
Syscall param setitimer(ovalue) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:486)
+ by 0x........: main (scalar.c:495)
Syscall param setitimer(&value->it_interval) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:486)
+ by 0x........: main (scalar.c:495)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param setitimer(&value->it_value) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:486)
+ by 0x........: main (scalar.c:495)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param setitimer(&ovalue->it_interval) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:486)
+ by 0x........: main (scalar.c:495)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param setitimer(&ovalue->it_value) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:486)
+ by 0x........: main (scalar.c:495)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1195,20 +1302,20 @@
-----------------------------------------------------
Syscall param getitimer(which) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:490)
+ by 0x........: main (scalar.c:499)
Syscall param getitimer(value) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:490)
+ by 0x........: main (scalar.c:499)
Syscall param getitimer(&value->it_interval) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:490)
+ by 0x........: main (scalar.c:499)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param getitimer(&value->it_value) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:490)
+ by 0x........: main (scalar.c:499)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1216,20 +1323,20 @@
-----------------------------------------------------
Syscall param stat(file_name) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:494)
+ by 0x........: main (scalar.c:503)
Syscall param stat(buf) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:494)
+ by 0x........: main (scalar.c:503)
Syscall param stat(file_name) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:494)
+ by 0x........: main (scalar.c:503)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param stat(buf) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:494)
+ by 0x........: main (scalar.c:503)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1237,20 +1344,20 @@
-----------------------------------------------------
Syscall param lstat(file_name) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:498)
+ by 0x........: main (scalar.c:507)
Syscall param lstat(buf) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:498)
+ by 0x........: main (scalar.c:507)
Syscall param lstat(file_name) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:498)
+ by 0x........: main (scalar.c:507)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param lstat(buf) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:498)
+ by 0x........: main (scalar.c:507)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1258,15 +1365,15 @@
-----------------------------------------------------
Syscall param fstat(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:502)
+ by 0x........: main (scalar.c:511)
Syscall param fstat(buf) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:502)
+ by 0x........: main (scalar.c:511)
Syscall param fstat(buf) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:502)
+ by 0x........: main (scalar.c:511)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1277,7 +1384,7 @@
-----------------------------------------------------
Syscall param iopl(level) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:510)
+ by 0x........: main (scalar.c:519)
-----------------------------------------------------
111: __NR_vhangup 0s 0m
@@ -1293,28 +1400,28 @@
-----------------------------------------------------
Syscall param wait4(pid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:526)
+ by 0x........: main (scalar.c:535)
Syscall param wait4(status) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:526)
+ by 0x........: main (scalar.c:535)
Syscall param wait4(options) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:526)
+ by 0x........: main (scalar.c:535)
Syscall param wait4(rusage) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:526)
+ by 0x........: main (scalar.c:535)
Syscall param wait4(status) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:526)
+ by 0x........: main (scalar.c:535)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param wait4(rusage) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:526)
+ by 0x........: main (scalar.c:535)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1325,11 +1432,11 @@
-----------------------------------------------------
Syscall param sysinfo(info) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:534)
+ by 0x........: main (scalar.c:543)
Syscall param sysinfo(info) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:534)
+ by 0x........: main (scalar.c:543)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1337,34 +1444,34 @@
-----------------------------------------------------
Syscall param ipc(call) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:541)
+ by 0x........: main (scalar.c:550)
Syscall param ipc(first) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:541)
+ by 0x........: main (scalar.c:550)
Syscall param ipc(second) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:541)
+ by 0x........: main (scalar.c:550)
Syscall param ipc(third) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:541)
+ by 0x........: main (scalar.c:550)
Syscall param ipc(ptr) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:541)
+ by 0x........: main (scalar.c:550)
Syscall param ipc(fifth) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:541)
+ by 0x........: main (scalar.c:550)
-----------------------------------------------------
118: __NR_fsync 1s 0m
-----------------------------------------------------
Syscall param fsync(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:545)
+ by 0x........: main (scalar.c:554)
-----------------------------------------------------
119: __NR_sigreturn n/a
@@ -1374,37 +1481,37 @@
-----------------------------------------------------
Syscall param clone(flags) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:556)
+ by 0x........: main (scalar.c:565)
Syscall param clone(child_stack) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:556)
+ by 0x........: main (scalar.c:565)
Syscall param clone(parent_tidptr) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:556)
+ by 0x........: main (scalar.c:565)
Syscall param clone(parent_tidptr) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:556)
+ by 0x........: main (scalar.c:565)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param clone(tlsinfo) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:556)
+ by 0x........: main (scalar.c:565)
Syscall param clone(tlsinfo) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:556)
+ by 0x........: main (scalar.c:565)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param clone(child_tidptr) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:556)
+ by 0x........: main (scalar.c:565)
Syscall param clone(child_tidptr) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:556)
+ by 0x........: main (scalar.c:565)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1415,11 +1522,11 @@
-----------------------------------------------------
Syscall param uname(buf) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:567)
+ by 0x........: main (scalar.c:576)
Syscall param uname(buf) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:567)
+ by 0x........: main (scalar.c:576)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1427,19 +1534,19 @@
-----------------------------------------------------
Syscall param modify_ldt(func) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:571)
+ by 0x........: main (scalar.c:580)
Syscall param modify_ldt(ptr) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:571)
+ by 0x........: main (scalar.c:580)
Syscall param modify_ldt(bytecount) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:571)
+ by 0x........: main (scalar.c:580)
Syscall param modify_ldt(ptr) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:571)
+ by 0x........: main (scalar.c:580)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1450,44 +1557,44 @@
-----------------------------------------------------
Syscall param mprotect(addr) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:580)
+ by 0x........: main (scalar.c:589)
Syscall param mprotect(len) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:580)
+ by 0x........: main (scalar.c:589)
Syscall param mprotect(prot) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:580)
+ by 0x........: main (scalar.c:589)
-----------------------------------------------------
126: __NR_sigprocmask 3s 2m
-----------------------------------------------------
Syscall param sigprocmask(how) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:584)
+ by 0x........: main (scalar.c:593)
Syscall param sigprocmask(set) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:584)
+ by 0x........: main (scalar.c:593)
Syscall param sigprocmask(oldset) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:584)
+ by 0x........: main (scalar.c:593)
Syscall param sigprocmask(set) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:584)
+ by 0x........: main (scalar.c:593)
Address 0x........ is 0 bytes after a block of size 4 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: main (scalar.c:30)
+ by 0x........: main (scalar.c:31)
Syscall param sigprocmask(oldset) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:584)
+ by 0x........: main (scalar.c:593)
Address 0x........ is 0 bytes after a block of size 4 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: main (scalar.c:30)
+ by 0x........: main (scalar.c:31)
-----------------------------------------------------
127: __NR_create_module ni
@@ -1497,24 +1604,24 @@
-----------------------------------------------------
Syscall param init_module(umod) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:592)
+ by 0x........: main (scalar.c:601)
Syscall param init_module(len) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:592)
+ by 0x........: main (scalar.c:601)
Syscall param init_module(uargs) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:592)
+ by 0x........: main (scalar.c:601)
Syscall param init_module(umod) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:592)
+ by 0x........: main (scalar.c:601)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param init_module(uargs) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:592)
+ by 0x........: main (scalar.c:601)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1528,23 +1635,23 @@
-----------------------------------------------------
Syscall param quotactl(cmd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:604)
+ by 0x........: main (scalar.c:613)
Syscall param quotactl(special) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:604)
+ by 0x........: main (scalar.c:613)
Syscall param quotactl(id) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:604)
+ by 0x........: main (scalar.c:613)
Syscall param quotactl(addr) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:604)
+ by 0x........: main (scalar.c:613)
Syscall param quotactl(special) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:604)
+ by 0x........: main (scalar.c:613)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1552,14 +1659,14 @@
-----------------------------------------------------
Syscall param getpgid(pid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:608)
+ by 0x........: main (scalar.c:617)
-----------------------------------------------------
133: __NR_fchdir 1s 0m
-----------------------------------------------------
Syscall param fchdir(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:612)
+ by 0x........: main (scalar.c:621)
-----------------------------------------------------
134: __NR_bdflush n/a
@@ -1572,7 +1679,7 @@
-----------------------------------------------------
Syscall param personality(persona) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:624)
+ by 0x........: main (scalar.c:633)
-----------------------------------------------------
137: __NR_afs_syscall ni
@@ -1582,41 +1689,41 @@
-----------------------------------------------------
Syscall param setfsuid16(uid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:632)
+ by 0x........: main (scalar.c:641)
-----------------------------------------------------
139: __NR_setfsgid 1s 0m
-----------------------------------------------------
Syscall param setfsgid16(gid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:636)
+ by 0x........: main (scalar.c:645)
-----------------------------------------------------
140: __NR__llseek 5s 1m
-----------------------------------------------------
Syscall param llseek(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:640)
+ by 0x........: main (scalar.c:649)
Syscall param llseek(offset_high) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:640)
+ by 0x........: main (scalar.c:649)
Syscall param llseek(offset_low) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:640)
+ by 0x........: main (scalar.c:649)
Syscall param llseek(result) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:640)
+ by 0x........: main (scalar.c:649)
Syscall param llseek(whence) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:640)
+ by 0x........: main (scalar.c:649)
Syscall param llseek(result) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:640)
+ by 0x........: main (scalar.c:649)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1624,19 +1731,19 @@
-----------------------------------------------------
Syscall param getdents(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:644)
+ by 0x........: main (scalar.c:653)
Syscall param getdents(dirp) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:644)
+ by 0x........: main (scalar.c:653)
Syscall param getdents(count) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:644)
+ by 0x........: main (scalar.c:653)
Syscall param getdents(dirp) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:644)
+ by 0x........: main (scalar.c:653)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1644,42 +1751,42 @@
-----------------------------------------------------
Syscall param select(n) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:648)
+ by 0x........: main (scalar.c:657)
Syscall param select(readfds) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:648)
+ by 0x........: main (scalar.c:657)
Syscall param select(writefds) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:648)
+ by 0x........: main (scalar.c:657)
Syscall param select(exceptfds) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:648)
+ by 0x........: main (scalar.c:657)
Syscall param select(timeout) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:648)
+ by 0x........: main (scalar.c:657)
Syscall param select(readfds) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:648)
+ by 0x........: main (scalar.c:657)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param select(writefds) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:648)
+ by 0x........: main (scalar.c:657)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param select(exceptfds) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:648)
+ by 0x........: main (scalar.c:657)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param select(timeout) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:648)
+ by 0x........: main (scalar.c:657)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1687,30 +1794,30 @@
-----------------------------------------------------
Syscall param flock(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:652)
+ by 0x........: main (scalar.c:661)
Syscall param flock(operation) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:652)
+ by 0x........: main (scalar.c:661)
-----------------------------------------------------
144: __NR_msync 3s 1m
-----------------------------------------------------
Syscall param msync(start) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:656)
+ by 0x........: main (scalar.c:665)
Syscall param msync(length) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:656)
+ by 0x........: main (scalar.c:665)
Syscall param msync(flags) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:656)
+ by 0x........: main (scalar.c:665)
Syscall param msync(start) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:656)
+ by 0x........: main (scalar.c:665)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1718,19 +1825,19 @@
-----------------------------------------------------
Syscall param readv(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:660)
+ by 0x........: main (scalar.c:669)
Syscall param readv(vector) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:660)
+ by 0x........: main (scalar.c:669)
Syscall param readv(count) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:660)
+ by 0x........: main (scalar.c:669)
Syscall param readv(vector) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:660)
+ by 0x........: main (scalar.c:669)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1738,19 +1845,19 @@
-----------------------------------------------------
Syscall param writev(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:664)
+ by 0x........: main (scalar.c:673)
Syscall param writev(vector) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:664)
+ by 0x........: main (scalar.c:673)
Syscall param writev(count) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:664)
+ by 0x........: main (scalar.c:673)
Syscall param writev(vector) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:664)
+ by 0x........: main (scalar.c:673)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1758,25 +1865,25 @@
-----------------------------------------------------
Syscall param getsid(pid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:668)
+ by 0x........: main (scalar.c:677)
-----------------------------------------------------
148: __NR_fdatasync 1s 0m
-----------------------------------------------------
Syscall param fdatasync(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:672)
+ by 0x........: main (scalar.c:681)
-----------------------------------------------------
149: __NR__sysctl 1s 1m
-----------------------------------------------------
Syscall param sysctl(args) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:676)
+ by 0x........: main (scalar.c:685)
Syscall param sysctl(args) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:676)
+ by 0x........: main (scalar.c:685)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1784,29 +1891,29 @@
-----------------------------------------------------
Syscall param mlock(addr) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:680)
+ by 0x........: main (scalar.c:689)
Syscall param mlock(len) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:680)
+ by 0x........: main (scalar.c:689)
-----------------------------------------------------
151: __NR_munlock 2s 0m
-----------------------------------------------------
Syscall param munlock(addr) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:684)
+ by 0x........: main (scalar.c:693)
Syscall param munlock(len) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:684)
+ by 0x........: main (scalar.c:693)
-----------------------------------------------------
152: __NR_mlockall 1s 0m
-----------------------------------------------------
Syscall param mlockall(flags) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:688)
+ by 0x........: main (scalar.c:697)
-----------------------------------------------------
153: __NR_munlockall 0s 0m
@@ -1816,15 +1923,15 @@
-----------------------------------------------------
Syscall param sched_setparam(pid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:696)
+ by 0x........: main (scalar.c:705)
Syscall param sched_setparam(p) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:696)
+ by 0x........: main (scalar.c:705)
Syscall param sched_setparam(p) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:696)
+ by 0x........: main (scalar.c:705)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1832,15 +1939,15 @@
-----------------------------------------------------
Syscall param sched_getparam(pid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:700)
+ by 0x........: main (scalar.c:709)
Syscall param sched_getparam(p) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:700)
+ by 0x........: main (scalar.c:709)
Syscall param sched_getparam(p) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:700)
+ by 0x........: main (scalar.c:709)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1848,19 +1955,19 @@
-----------------------------------------------------
Syscall param sched_setscheduler(pid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:704)
+ by 0x........: main (scalar.c:713)
Syscall param sched_setscheduler(policy) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:704)
+ by 0x........: main (scalar.c:713)
Syscall param sched_setscheduler(p) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:704)
+ by 0x........: main (scalar.c:713)
Syscall param sched_setscheduler(p) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:704)
+ by 0x........: main (scalar.c:713)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1868,7 +1975,7 @@
-----------------------------------------------------
Syscall param sched_getscheduler(pid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:708)
+ by 0x........: main (scalar.c:717)
-----------------------------------------------------
158: __NR_sched_yield 0s 0m
@@ -1878,14 +1985,14 @@
-----------------------------------------------------
Syscall param sched_get_priority_max(policy) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:716)
+ by 0x........: main (scalar.c:725)
-----------------------------------------------------
160:__NR_sched_get_priority_min 1s 0m
-----------------------------------------------------
Syscall param sched_get_priority_min(policy) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:720)
+ by 0x........: main (scalar.c:729)
-----------------------------------------------------
161:__NR_sched_rr_get_interval n/a
@@ -1895,20 +2002,20 @@
-----------------------------------------------------
Syscall param nanosleep(req) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:728)
+ by 0x........: main (scalar.c:737)
Syscall param nanosleep(rem) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:728)
+ by 0x........: main (scalar.c:737)
Syscall param nanosleep(req) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:728)
+ by 0x........: main (scalar.c:737)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param nanosleep(rem) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:728)
+ by 0x........: main (scalar.c:737)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1916,67 +2023,67 @@
-----------------------------------------------------
Syscall param mremap(old_addr) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:732)
+ by 0x........: main (scalar.c:741)
Syscall param mremap(old_size) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:732)
+ by 0x........: main (scalar.c:741)
Syscall param mremap(new_size) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:732)
+ by 0x........: main (scalar.c:741)
Syscall param mremap(flags) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:732)
+ by 0x........: main (scalar.c:741)
Syscall param mremap(new_addr) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:732)
+ by 0x........: main (scalar.c:741)
-----------------------------------------------------
164: __NR_setresuid 3s 0m
-----------------------------------------------------
Syscall param setresuid16(ruid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:736)
+ by 0x........: main (scalar.c:745)
Syscall param setresuid16(euid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:736)
+ by 0x........: main (scalar.c:745)
Syscall param setresuid16(suid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:736)
+ by 0x........: main (scalar.c:745)
-----------------------------------------------------
165: __NR_getresuid 3s 3m
-----------------------------------------------------
Syscall param getresuid16(ruid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:740)
+ by 0x........: main (scalar.c:749)
Syscall param getresuid16(euid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:740)
+ by 0x........: main (scalar.c:749)
Syscall param getresuid16(suid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:740)
+ by 0x........: main (scalar.c:749)
Syscall param getresuid16(ruid) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:740)
+ by 0x........: main (scalar.c:749)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param getresuid16(euid) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:740)
+ by 0x........: main (scalar.c:749)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param getresuid16(suid) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:740)
+ by 0x........: main (scalar.c:749)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -1990,29 +2097,29 @@
-----------------------------------------------------
Syscall param poll(ufds) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:752)
+ by 0x........: main (scalar.c:761)
Syscall param poll(nfds) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:752)
+ by 0x........: main (scalar.c:761)
Syscall param poll(timeout) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:752)
+ by 0x........: main (scalar.c:761)
Syscall param poll(ufds.fd) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:752)
+ by 0x........: main (scalar.c:761)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param poll(ufds.events) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:752)
+ by 0x........: main (scalar.c:761)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param poll(ufds.revents) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:752)
+ by 0x........: main (scalar.c:761)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2023,44 +2130,44 @@
-----------------------------------------------------
Syscall param setresgid16(rgid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:760)
+ by 0x........: main (scalar.c:769)
Syscall param setresgid16(egid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:760)
+ by 0x........: main (scalar.c:769)
Syscall param setresgid16(sgid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:760)
+ by 0x........: main (scalar.c:769)
-----------------------------------------------------
171: __NR_getresgid 3s 3m
-----------------------------------------------------
Syscall param getresgid16(rgid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:764)
+ by 0x........: main (scalar.c:773)
Syscall param getresgid16(egid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:764)
+ by 0x........: main (scalar.c:773)
Syscall param getresgid16(sgid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:764)
+ by 0x........: main (scalar.c:773)
Syscall param getresgid16(rgid) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:764)
+ by 0x........: main (scalar.c:773)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param getresgid16(egid) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:764)
+ by 0x........: main (scalar.c:773)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param getresgid16(sgid) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:764)
+ by 0x........: main (scalar.c:773)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2068,23 +2175,43 @@
-----------------------------------------------------
Syscall param prctl(option) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:768)
+ by 0x........: main (scalar.c:777)
Syscall param prctl(arg2) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:768)
+ by 0x........: main (scalar.c:777)
Syscall param prctl(arg3) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:768)
+ by 0x........: main (scalar.c:777)
Syscall param prctl(arg4) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:768)
+ by 0x........: main (scalar.c:777)
Syscall param prctl(arg5) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:768)
+ by 0x........: main (scalar.c:777)
+
+-----------------------------------------------------
+172: __NR_prctl 2s 0m
+-----------------------------------------------------
+Syscall param prctl(option) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:782)
+
+Syscall param prctl(set-name) points to uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:782)
+ Address 0x........ is on thread 1's stack
+ in frame #1, created by main (scalar.c:29)
+
+-----------------------------------------------------
+172: __NR_prctl 1s 0m
+-----------------------------------------------------
+Syscall param prctl(option) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:787)
-----------------------------------------------------
173: __NR_rt_sigreturn n/a
@@ -2094,75 +2221,75 @@
-----------------------------------------------------
Syscall param rt_sigaction(signum) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:776)
+ by 0x........: main (scalar.c:795)
Syscall param rt_sigaction(act) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:776)
+ by 0x........: main (scalar.c:795)
Syscall param rt_sigaction(oldact) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:776)
+ by 0x........: main (scalar.c:795)
Syscall param rt_sigaction(sigsetsize) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:776)
+ by 0x........: main (scalar.c:795)
Syscall param rt_sigaction(act->sa_handler) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:776)
+ by 0x........: main (scalar.c:795)
Address 0x........ is 4 bytes after a block of size 4 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: main (scalar.c:30)
+ by 0x........: main (scalar.c:31)
Syscall param rt_sigaction(act->sa_mask) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:776)
+ by 0x........: main (scalar.c:795)
Address 0x........ is 16 bytes after a block of size 4 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: main (scalar.c:30)
+ by 0x........: main (scalar.c:31)
Syscall param rt_sigaction(act->sa_flags) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:776)
+ by 0x........: main (scalar.c:795)
Address 0x........ is 8 bytes after a block of size 4 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: main (scalar.c:30)
+ by 0x........: main (scalar.c:31)
Syscall param rt_sigaction(oldact) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:776)
+ by 0x........: main (scalar.c:795)
Address 0x........ is 4 bytes after a block of size 4 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: main (scalar.c:30)
+ by 0x........: main (scalar.c:31)
-----------------------------------------------------
175: __NR_rt_sigprocmask 4s 2m
-----------------------------------------------------
Syscall param rt_sigprocmask(how) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:780)
+ by 0x........: main (scalar.c:799)
Syscall param rt_sigprocmask(set) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:780)
+ by 0x........: main (scalar.c:799)
Syscall param rt_sigprocmask(oldset) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:780)
+ by 0x........: main (scalar.c:799)
Syscall param rt_sigprocmask(sigsetsize) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:780)
+ by 0x........: main (scalar.c:799)
Syscall param rt_sigprocmask(set) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:780)
+ by 0x........: main (scalar.c:799)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param rt_sigprocmask(oldset) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:780)
+ by 0x........: main (scalar.c:799)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2170,15 +2297,15 @@
-----------------------------------------------------
Syscall param rt_sigpending(set) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:784)
+ by 0x........: main (scalar.c:803)
Syscall param rt_sigpending(sigsetsize) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:784)
+ by 0x........: main (scalar.c:803)
Syscall param rt_sigpending(set) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:784)
+ by 0x........: main (scalar.c:803)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2186,33 +2313,33 @@
-----------------------------------------------------
Syscall param rt_sigtimedwait(set) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:788)
+ by 0x........: main (scalar.c:807)
Syscall param rt_sigtimedwait(info) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:788)
+ by 0x........: main (scalar.c:807)
Syscall param rt_sigtimedwait(timeout) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:788)
+ by 0x........: main (scalar.c:807)
Syscall param rt_sigtimedwait(sigsetsize) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:788)
+ by 0x........: main (scalar.c:807)
Syscall param rt_sigtimedwait(set) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:788)
+ by 0x........: main (scalar.c:807)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param rt_sigtimedwait(info) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:788)
+ by 0x........: main (scalar.c:807)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param rt_sigtimedwait(timeout) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:788)
+ by 0x........: main (scalar.c:807)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2220,50 +2347,63 @@
-----------------------------------------------------
Syscall param rt_sigqueueinfo(pid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:792)
+ by 0x........: main (scalar.c:811)
Syscall param rt_sigqueueinfo(sig) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:792)
+ by 0x........: main (scalar.c:811)
Syscall param rt_sigqueueinfo(uinfo) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:792)
+ by 0x........: main (scalar.c:811)
Syscall param rt_sigqueueinfo(uinfo) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:792)
+ by 0x........: main (scalar.c:811)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
-179: __NR_rt_sigsuspend ignore
+179: __NR_rt_sigsuspend 2s 1m
-----------------------------------------------------
+Syscall param rt_sigsuspend(mask) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:815)
+
+Syscall param rt_sigsuspend(size) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:815)
+
+Syscall param rt_sigsuspend(mask) points to unaddressable byte(s)
+ ...
+ by 0x........: main (scalar.c:815)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
-----------------------------------------------------
180: __NR_pread64 5s 1m
-----------------------------------------------------
Syscall param pread64(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:800)
+ by 0x........: main (scalar.c:819)
Syscall param pread64(buf) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:800)
+ by 0x........: main (scalar.c:819)
Syscall param pread64(count) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:800)
+ by 0x........: main (scalar.c:819)
Syscall param pread64(offset_low) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:800)
+ by 0x........: main (scalar.c:819)
Syscall param pread64(offset_high) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:800)
+ by 0x........: main (scalar.c:819)
Syscall param pread64(buf) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:800)
+ by 0x........: main (scalar.c:819)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2271,27 +2411,27 @@
-----------------------------------------------------
Syscall param pwrite64(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:804)
+ by 0x........: main (scalar.c:823)
Syscall param pwrite64(buf) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:804)
+ by 0x........: main (scalar.c:823)
Syscall param pwrite64(count) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:804)
+ by 0x........: main (scalar.c:823)
Syscall param pwrite64(offset_low) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:804)
+ by 0x........: main (scalar.c:823)
Syscall param pwrite64(offset_high) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:804)
+ by 0x........: main (scalar.c:823)
Syscall param pwrite64(buf) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:804)
+ by 0x........: main (scalar.c:823)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2299,19 +2439,19 @@
-----------------------------------------------------
Syscall param chown16(path) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:808)
+ by 0x........: main (scalar.c:827)
Syscall param chown16(owner) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:808)
+ by 0x........: main (scalar.c:827)
Syscall param chown16(group) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:808)
+ by 0x........: main (scalar.c:827)
Syscall param chown16(path) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:808)
+ by 0x........: main (scalar.c:827)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2319,15 +2459,15 @@
-----------------------------------------------------
Syscall param getcwd(buf) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:812)
+ by 0x........: main (scalar.c:831)
Syscall param getcwd(size) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:812)
+ by 0x........: main (scalar.c:831)
Syscall param getcwd(buf) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:812)
+ by 0x........: main (scalar.c:831)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2335,20 +2475,20 @@
-----------------------------------------------------
Syscall param capget(header) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:816)
+ by 0x........: main (scalar.c:835)
Syscall param capget(data) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:816)
+ by 0x........: main (scalar.c:835)
Syscall param capget(header) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:816)
+ by 0x........: main (scalar.c:835)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param capget(data) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:816)
+ by 0x........: main (scalar.c:835)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2356,20 +2496,20 @@
-----------------------------------------------------
Syscall param capset(header) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:820)
+ by 0x........: main (scalar.c:839)
Syscall param capset(data) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:820)
+ by 0x........: main (scalar.c:839)
Syscall param capset(header) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:820)
+ by 0x........: main (scalar.c:839)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param capset(data) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:820)
+ by 0x........: main (scalar.c:839)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2377,46 +2517,46 @@
-----------------------------------------------------
Syscall param sigaltstack(ss) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:834)
+ by 0x........: main (scalar.c:853)
Syscall param sigaltstack(oss) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:834)
+ by 0x........: main (scalar.c:853)
Syscall param sigaltstack(ss) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:834)
+ by 0x........: main (scalar.c:853)
Address 0x........ is on thread 1's stack
- in frame #1, created by main (scalar.c:28)
+ in frame #1, created by main (scalar.c:29)
Syscall param sigaltstack(oss) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:834)
+ by 0x........: main (scalar.c:853)
Address 0x........ is on thread 1's stack
- in frame #1, created by main (scalar.c:28)
+ in frame #1, created by main (scalar.c:29)
-----------------------------------------------------
187: __NR_sendfile 4s 1m
-----------------------------------------------------
Syscall param sendfile(out_fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:839)
+ by 0x........: main (scalar.c:858)
Syscall param sendfile(in_fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:839)
+ by 0x........: main (scalar.c:858)
Syscall param sendfile(offset) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:839)
+ by 0x........: main (scalar.c:858)
Syscall param sendfile(count) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:839)
+ by 0x........: main (scalar.c:858)
Syscall param sendfile(offset) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:839)
+ by 0x........: main (scalar.c:858)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2424,46 +2564,46 @@
-----------------------------------------------------
Syscall param getpmsg(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:845)
+ by 0x........: main (scalar.c:864)
Syscall param getpmsg(ctrl) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:845)
+ by 0x........: main (scalar.c:864)
Syscall param getpmsg(data) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:845)
+ by 0x........: main (scalar.c:864)
Syscall param getpmsg(bandp) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:845)
+ by 0x........: main (scalar.c:864)
Syscall param getpmsg(flagsp) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:845)
+ by 0x........: main (scalar.c:864)
-----------------------------------------------------
189: __NR_putpmsg 5s 0m
-----------------------------------------------------
Syscall param putpmsg(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:851)
+ by 0x........: main (scalar.c:870)
Syscall param putpmsg(ctrl) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:851)
+ by 0x........: main (scalar.c:870)
Syscall param putpmsg(data) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:851)
+ by 0x........: main (scalar.c:870)
Syscall param putpmsg(band) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:851)
+ by 0x........: main (scalar.c:870)
Syscall param putpmsg(flags) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:851)
+ by 0x........: main (scalar.c:870)
-----------------------------------------------------
190: __NR_vfork other
@@ -2473,15 +2613,15 @@
-----------------------------------------------------
Syscall param getrlimit(resource) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:859)
+ by 0x........: main (scalar.c:878)
Syscall param getrlimit(rlim) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:859)
+ by 0x........: main (scalar.c:878)
Syscall param getrlimit(rlim) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:859)
+ by 0x........: main (scalar.c:878)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2489,46 +2629,46 @@
-----------------------------------------------------
Syscall param mmap2(start) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:863)
+ by 0x........: main (scalar.c:882)
Syscall param mmap2(length) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:863)
+ by 0x........: main (scalar.c:882)
Syscall param mmap2(prot) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:863)
+ by 0x........: main (scalar.c:882)
Syscall param mmap2(flags) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:863)
+ by 0x........: main (scalar.c:882)
Syscall param mmap2(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:863)
+ by 0x........: main (scalar.c:882)
Syscall param mmap2(offset) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:863)
+ by 0x........: main (scalar.c:882)
-----------------------------------------------------
193: __NR_truncate64 3s 1m
-----------------------------------------------------
Syscall param truncate64(path) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:867)
+ by 0x........: main (scalar.c:886)
Syscall param truncate64(length_low) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:867)
+ by 0x........: main (scalar.c:886)
Syscall param truncate64(length_high) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:867)
+ by 0x........: main (scalar.c:886)
Syscall param truncate64(path) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:867)
+ by 0x........: main (scalar.c:886)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2536,35 +2676,35 @@
-----------------------------------------------------
Syscall param ftruncate64(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:871)
+ by 0x........: main (scalar.c:890)
Syscall param ftruncate64(length_low) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:871)
+ by 0x........: main (scalar.c:890)
Syscall param ftruncate64(length_high) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:871)
+ by 0x........: main (scalar.c:890)
-----------------------------------------------------
195: __NR_stat64 2s 2m
-----------------------------------------------------
Syscall param stat64(file_name) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:875)
+ by 0x........: main (scalar.c:894)
Syscall param stat64(buf) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:875)
+ by 0x........: main (scalar.c:894)
Syscall param stat64(file_name) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:875)
+ by 0x........: main (scalar.c:894)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param stat64(buf) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:875)
+ by 0x........: main (scalar.c:894)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2572,20 +2712,20 @@
-----------------------------------------------------
Syscall param lstat64(file_name) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:879)
+ by 0x........: main (scalar.c:898)
Syscall param lstat64(buf) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:879)
+ by 0x........: main (scalar.c:898)
Syscall param lstat64(file_name) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:879)
+ by 0x........: main (scalar.c:898)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param lstat64(buf) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:879)
+ by 0x........: main (scalar.c:898)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2593,15 +2733,15 @@
-----------------------------------------------------
Syscall param fstat64(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:883)
+ by 0x........: main (scalar.c:902)
Syscall param fstat64(buf) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:883)
+ by 0x........: main (scalar.c:902)
Syscall param fstat64(buf) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:883)
+ by 0x........: main (scalar.c:902)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2609,19 +2749,19 @@
-----------------------------------------------------
Syscall param lchown(path) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:887)
+ by 0x........: main (scalar.c:906)
Syscall param lchown(owner) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:887)
+ by 0x........: main (scalar.c:906)
Syscall param lchown(group) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:887)
+ by 0x........: main (scalar.c:906)
Syscall param lchown(path) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:887)
+ by 0x........: main (scalar.c:906)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2641,37 +2781,37 @@
-----------------------------------------------------
Syscall param setreuid(ruid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:907)
+ by 0x........: main (scalar.c:926)
Syscall param setreuid(euid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:907)
+ by 0x........: main (scalar.c:926)
-----------------------------------------------------
204: __NR_setregid32 2s 0m
-----------------------------------------------------
Syscall param setregid(rgid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:911)
+ by 0x........: main (scalar.c:930)
Syscall param setregid(egid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:911)
+ by 0x........: main (scalar.c:930)
-----------------------------------------------------
205: __NR_getgroups32 2s 1m
-----------------------------------------------------
Syscall param getgroups(size) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:915)
+ by 0x........: main (scalar.c:934)
Syscall param getgroups(list) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:915)
+ by 0x........: main (scalar.c:934)
Syscall param getgroups(list) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:915)
+ by 0x........: main (scalar.c:934)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2679,15 +2819,15 @@
-----------------------------------------------------
Syscall param setgroups(size) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:919)
+ by 0x........: main (scalar.c:938)
Syscall param setgroups(list) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:919)
+ by 0x........: main (scalar.c:938)
Syscall param setgroups(list) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:919)
+ by 0x........: main (scalar.c:938)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2695,59 +2835,59 @@
-----------------------------------------------------
Syscall param fchown(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:923)
+ by 0x........: main (scalar.c:942)
Syscall param fchown(owner) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:923)
+ by 0x........: main (scalar.c:942)
Syscall param fchown(group) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:923)
+ by 0x........: main (scalar.c:942)
-----------------------------------------------------
208: __NR_setresuid32 3s 0m
-----------------------------------------------------
Syscall param setresuid(ruid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:927)
+ by 0x........: main (scalar.c:946)
Syscall param setresuid(euid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:927)
+ by 0x........: main (scalar.c:946)
Syscall param setresuid(suid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:927)
+ by 0x........: main (scalar.c:946)
-----------------------------------------------------
209: __NR_getresuid32 3s 3m
-----------------------------------------------------
Syscall param getresuid(ruid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:931)
+ by 0x........: main (scalar.c:950)
Syscall param getresuid(euid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:931)
+ by 0x........: main (scalar.c:950)
Syscall param getresuid(suid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:931)
+ by 0x........: main (scalar.c:950)
Syscall param getresuid(ruid) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:931)
+ by 0x........: main (scalar.c:950)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param getresuid(euid) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:931)
+ by 0x........: main (scalar.c:950)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param getresuid(suid) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:931)
+ by 0x........: main (scalar.c:950)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2755,44 +2895,44 @@
-----------------------------------------------------
Syscall param setresgid(rgid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:935)
+ by 0x........: main (scalar.c:954)
Syscall param setresgid(egid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:935)
+ by 0x........: main (scalar.c:954)
Syscall param setresgid(sgid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:935)
+ by 0x........: main (scalar.c:954)
-----------------------------------------------------
211: __NR_getresgid32 3s 3m
-----------------------------------------------------
Syscall param getresgid(rgid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:939)
+ by 0x........: main (scalar.c:958)
Syscall param getresgid(egid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:939)
+ by 0x........: main (scalar.c:958)
Syscall param getresgid(sgid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:939)
+ by 0x........: main (scalar.c:958)
Syscall param getresgid(rgid) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:939)
+ by 0x........: main (scalar.c:958)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param getresgid(egid) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:939)
+ by 0x........: main (scalar.c:958)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param getresgid(sgid) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:939)
+ by 0x........: main (scalar.c:958)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2800,19 +2940,19 @@
-----------------------------------------------------
Syscall param chown(path) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:943)
+ by 0x........: main (scalar.c:962)
Syscall param chown(owner) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:943)
+ by 0x........: main (scalar.c:962)
Syscall param chown(group) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:943)
+ by 0x........: main (scalar.c:962)
Syscall param chown(path) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:943)
+ by 0x........: main (scalar.c:962)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2820,28 +2960,28 @@
-----------------------------------------------------
Syscall param setuid(uid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:947)
+ by 0x........: main (scalar.c:966)
-----------------------------------------------------
214: __NR_setgid32 1s 0m
-----------------------------------------------------
Syscall param setgid(gid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:951)
+ by 0x........: main (scalar.c:970)
-----------------------------------------------------
215: __NR_setfsuid32 1s 0m
-----------------------------------------------------
Syscall param setfsuid(uid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:955)
+ by 0x........: main (scalar.c:974)
-----------------------------------------------------
216: __NR_setfsgid32 1s 0m
-----------------------------------------------------
Syscall param setfsgid(gid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:959)
+ by 0x........: main (scalar.c:978)
-----------------------------------------------------
217: __NR_pivot_root n/a
@@ -2851,19 +2991,19 @@
-----------------------------------------------------
Syscall param mincore(start) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:967)
+ by 0x........: main (scalar.c:986)
Syscall param mincore(length) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:967)
+ by 0x........: main (scalar.c:986)
Syscall param mincore(vec) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:967)
+ by 0x........: main (scalar.c:986)
Syscall param mincore(vec) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:967)
+ by 0x........: main (scalar.c:986)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2871,34 +3011,34 @@
-----------------------------------------------------
Syscall param madvise(start) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:971)
+ by 0x........: main (scalar.c:990)
Syscall param madvise(length) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:971)
+ by 0x........: main (scalar.c:990)
Syscall param madvise(advice) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:971)
+ by 0x........: main (scalar.c:990)
-----------------------------------------------------
220: __NR_getdents64 3s 1m
-----------------------------------------------------
Syscall param getdents64(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:975)
+ by 0x........: main (scalar.c:994)
Syscall param getdents64(dirp) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:975)
+ by 0x........: main (scalar.c:994)
Syscall param getdents64(count) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:975)
+ by 0x........: main (scalar.c:994)
Syscall param getdents64(dirp) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:975)
+ by 0x........: main (scalar.c:994)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2906,25 +3046,25 @@
-----------------------------------------------------
Syscall param fcntl64(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:982)
+ by 0x........: main (scalar.c:1001)
Syscall param fcntl64(cmd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:982)
+ by 0x........: main (scalar.c:1001)
-----------------------------------------------------
221: __NR_fcntl64 (DUPFD) 1s 0m
-----------------------------------------------------
Syscall param fcntl64(arg) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:986)
+ by 0x........: main (scalar.c:1005)
-----------------------------------------------------
221: __NR_fcntl64 (GETLK) 1s 0m
-----------------------------------------------------
Syscall param fcntl64(lock) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:992)
+ by 0x........: main (scalar.c:1011)
-----------------------------------------------------
222: 222 ni
@@ -2943,37 +3083,37 @@
-----------------------------------------------------
Syscall param setxattr(path) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1012)
+ by 0x........: main (scalar.c:1031)
Syscall param setxattr(name) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1012)
+ by 0x........: main (scalar.c:1031)
Syscall param setxattr(value) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1012)
+ by 0x........: main (scalar.c:1031)
Syscall param setxattr(size) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1012)
+ by 0x........: main (scalar.c:1031)
Syscall param setxattr(flags) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1012)
+ by 0x........: main (scalar.c:1031)
Syscall param setxattr(path) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1012)
+ by 0x........: main (scalar.c:1031)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param setxattr(name) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1012)
+ by 0x........: main (scalar.c:1031)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param setxattr(value) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1012)
+ by 0x........: main (scalar.c:1031)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -2981,37 +3121,37 @@
-----------------------------------------------------
Syscall param lsetxattr(path) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1016)
+ by 0x........: main (scalar.c:1035)
Syscall param lsetxattr(name) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1016)
+ by 0x........: main (scalar.c:1035)
Syscall param lsetxattr(value) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1016)
+ by 0x........: main (scalar.c:1035)
Syscall param lsetxattr(size) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1016)
+ by 0x........: main (scalar.c:1035)
Syscall param lsetxattr(flags) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1016)
+ by 0x........: main (scalar.c:1035)
Syscall param lsetxattr(path) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1016)
+ by 0x........: main (scalar.c:1035)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param lsetxattr(name) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1016)
+ by 0x........: main (scalar.c:1035)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param lsetxattr(value) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1016)
+ by 0x........: main (scalar.c:1035)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3019,32 +3159,32 @@
-----------------------------------------------------
Syscall param fsetxattr(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1020)
+ by 0x........: main (scalar.c:1039)
Syscall param fsetxattr(name) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1020)
+ by 0x........: main (scalar.c:1039)
Syscall param fsetxattr(value) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1020)
+ by 0x........: main (scalar.c:1039)
Syscall param fsetxattr(size) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1020)
+ by 0x........: main (scalar.c:1039)
Syscall param fsetxattr(flags) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1020)
+ by 0x........: main (scalar.c:1039)
Syscall param fsetxattr(name) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1020)
+ by 0x........: main (scalar.c:1039)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param fsetxattr(value) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1020)
+ by 0x........: main (scalar.c:1039)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3052,33 +3192,33 @@
-----------------------------------------------------
Syscall param getxattr(path) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1024)
+ by 0x........: main (scalar.c:1043)
Syscall param getxattr(name) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1024)
+ by 0x........: main (scalar.c:1043)
Syscall param getxattr(value) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1024)
+ by 0x........: main (scalar.c:1043)
Syscall param getxattr(size) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1024)
+ by 0x........: main (scalar.c:1043)
Syscall param getxattr(path) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1024)
+ by 0x........: main (scalar.c:1043)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param getxattr(name) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1024)
+ by 0x........: main (scalar.c:1043)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param getxattr(value) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1024)
+ by 0x........: main (scalar.c:1043)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3086,33 +3226,33 @@
-----------------------------------------------------
Syscall param lgetxattr(path) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1028)
+ by 0x........: main (scalar.c:1047)
Syscall param lgetxattr(name) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1028)
+ by 0x........: main (scalar.c:1047)
Syscall param lgetxattr(value) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1028)
+ by 0x........: main (scalar.c:1047)
Syscall param lgetxattr(size) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1028)
+ by 0x........: main (scalar.c:1047)
Syscall param lgetxattr(path) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1028)
+ by 0x........: main (scalar.c:1047)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param lgetxattr(name) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1028)
+ by 0x........: main (scalar.c:1047)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param lgetxattr(value) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1028)
+ by 0x........: main (scalar.c:1047)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3120,28 +3260,28 @@
-----------------------------------------------------
Syscall param fgetxattr(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1032)
+ by 0x........: main (scalar.c:1051)
Syscall param fgetxattr(name) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1032)
+ by 0x........: main (scalar.c:1051)
Syscall param fgetxattr(value) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1032)
+ by 0x........: main (scalar.c:1051)
Syscall param fgetxattr(size) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1032)
+ by 0x........: main (scalar.c:1051)
Syscall param fgetxattr(name) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1032)
+ by 0x........: main (scalar.c:1051)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param fgetxattr(value) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1032)
+ by 0x........: main (scalar.c:1051)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3149,24 +3289,24 @@
-----------------------------------------------------
Syscall param listxattr(path) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1036)
+ by 0x........: main (scalar.c:1055)
Syscall param listxattr(list) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1036)
+ by 0x........: main (scalar.c:1055)
Syscall param listxattr(size) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1036)
+ by 0x........: main (scalar.c:1055)
Syscall param listxattr(path) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1036)
+ by 0x........: main (scalar.c:1055)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param listxattr(list) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1036)
+ by 0x........: main (scalar.c:1055)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3174,24 +3314,24 @@
-----------------------------------------------------
Syscall param llistxattr(path) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1040)
+ by 0x........: main (scalar.c:1059)
Syscall param llistxattr(list) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1040)
+ by 0x........: main (scalar.c:1059)
Syscall param llistxattr(size) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1040)
+ by 0x........: main (scalar.c:1059)
Syscall param llistxattr(path) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1040)
+ by 0x........: main (scalar.c:1059)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param llistxattr(list) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1040)
+ by 0x........: main (scalar.c:1059)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3199,19 +3339,19 @@
-----------------------------------------------------
Syscall param flistxattr(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1044)
+ by 0x........: main (scalar.c:1063)
Syscall param flistxattr(list) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1044)
+ by 0x........: main (scalar.c:1063)
Syscall param flistxattr(size) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1044)
+ by 0x........: main (scalar.c:1063)
Syscall param flistxattr(list) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1044)
+ by 0x........: main (scalar.c:1063)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3219,20 +3359,20 @@
-----------------------------------------------------
Syscall param removexattr(path) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1048)
+ by 0x........: main (scalar.c:1067)
Syscall param removexattr(name) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1048)
+ by 0x........: main (scalar.c:1067)
Syscall param removexattr(path) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1048)
+ by 0x........: main (scalar.c:1067)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param removexattr(name) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1048)
+ by 0x........: main (scalar.c:1067)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3240,20 +3380,20 @@
-----------------------------------------------------
Syscall param lremovexattr(path) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1052)
+ by 0x........: main (scalar.c:1071)
Syscall param lremovexattr(name) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1052)
+ by 0x........: main (scalar.c:1071)
Syscall param lremovexattr(path) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1052)
+ by 0x........: main (scalar.c:1071)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param lremovexattr(name) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1052)
+ by 0x........: main (scalar.c:1071)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3261,15 +3401,15 @@
-----------------------------------------------------
Syscall param fremovexattr(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1056)
+ by 0x........: main (scalar.c:1075)
Syscall param fremovexattr(name) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1056)
+ by 0x........: main (scalar.c:1075)
Syscall param fremovexattr(name) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1056)
+ by 0x........: main (scalar.c:1075)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3280,52 +3420,52 @@
-----------------------------------------------------
Syscall param sendfile64(out_fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1064)
+ by 0x........: main (scalar.c:1083)
Syscall param sendfile64(in_fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1064)
+ by 0x........: main (scalar.c:1083)
Syscall param sendfile64(offset) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1064)
+ by 0x........: main (scalar.c:1083)
Syscall param sendfile64(count) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1064)
+ by 0x........: main (scalar.c:1083)
Syscall param sendfile64(offset) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1064)
+ by 0x........: main (scalar.c:1083)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
-240: __NR_futex 5s 2m
+240: __NR_futex 4s 2m
-----------------------------------------------------
Syscall param futex(futex) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1072)
+ by 0x........: main (scalar.c:1091)
Syscall param futex(op) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1072)
+ by 0x........: main (scalar.c:1091)
Syscall param futex(val) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1072)
+ by 0x........: main (scalar.c:1091)
Syscall param futex(utime) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1072)
+ by 0x........: main (scalar.c:1091)
Syscall param futex(futex) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1072)
+ by 0x........: main (scalar.c:1091)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param futex(timeout) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1072)
+ by 0x........: main (scalar.c:1091)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3333,19 +3473,19 @@
-----------------------------------------------------
Syscall param sched_setaffinity(pid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1076)
+ by 0x........: main (scalar.c:1095)
Syscall param sched_setaffinity(len) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1076)
+ by 0x........: main (scalar.c:1095)
Syscall param sched_setaffinity(mask) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1076)
+ by 0x........: main (scalar.c:1095)
Syscall param sched_setaffinity(mask) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1076)
+ by 0x........: main (scalar.c:1095)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3353,19 +3493,19 @@
-----------------------------------------------------
Syscall param sched_getaffinity(pid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1080)
+ by 0x........: main (scalar.c:1099)
Syscall param sched_getaffinity(len) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1080)
+ by 0x........: main (scalar.c:1099)
Syscall param sched_getaffinity(mask) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1080)
+ by 0x........: main (scalar.c:1099)
Syscall param sched_getaffinity(mask) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1080)
+ by 0x........: main (scalar.c:1099)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3373,11 +3513,11 @@
-----------------------------------------------------
Syscall param set_thread_area(u_info) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1084)
+ by 0x........: main (scalar.c:1103)
Syscall param set_thread_area(u_info) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1084)
+ by 0x........: main (scalar.c:1103)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Warning: bad u_info address 0x........ in set_thread_area
@@ -3386,11 +3526,11 @@
-----------------------------------------------------
Syscall param get_thread_area(u_info) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1088)
+ by 0x........: main (scalar.c:1107)
Syscall param get_thread_area(u_info) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1088)
+ by 0x........: main (scalar.c:1107)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Warning: bad u_info address 0x........ in get_thread_area
@@ -3399,15 +3539,15 @@
-----------------------------------------------------
Syscall param io_setup(nr_events) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1092)
+ by 0x........: main (scalar.c:1111)
Syscall param io_setup(ctxp) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1092)
+ by 0x........: main (scalar.c:1111)
Syscall param io_setup(ctxp) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1092)
+ by 0x........: main (scalar.c:1111)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3415,39 +3555,39 @@
-----------------------------------------------------
Syscall param io_destroy(ctx) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1105)
+ by 0x........: main (scalar.c:1124)
-----------------------------------------------------
247: __NR_io_getevents 5s 2m
-----------------------------------------------------
Syscall param io_getevents(ctx_id) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1110)
+ by 0x........: main (scalar.c:1129)
Syscall param io_getevents(min_nr) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1110)
+ by 0x........: main (scalar.c:1129)
Syscall param io_getevents(nr) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1110)
+ by 0x........: main (scalar.c:1129)
Syscall param io_getevents(events) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1110)
+ by 0x........: main (scalar.c:1129)
Syscall param io_getevents(timeout) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1110)
+ by 0x........: main (scalar.c:1129)
Syscall param io_getevents(events) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1110)
+ by 0x........: main (scalar.c:1129)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param io_getevents(timeout) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1110)
+ by 0x........: main (scalar.c:1129)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3455,19 +3595,19 @@
-----------------------------------------------------
Syscall param io_submit(ctx_id) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1114)
+ by 0x........: main (scalar.c:1133)
Syscall param io_submit(nr) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1114)
+ by 0x........: main (scalar.c:1133)
Syscall param io_submit(iocbpp) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1114)
+ by 0x........: main (scalar.c:1133)
Syscall param io_submit(iocbpp) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1114)
+ by 0x........: main (scalar.c:1133)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3475,24 +3615,24 @@
-----------------------------------------------------
Syscall param io_cancel(ctx_id) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1118)
+ by 0x........: main (scalar.c:1137)
Syscall param io_cancel(iocb) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1118)
+ by 0x........: main (scalar.c:1137)
Syscall param io_cancel(result) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1118)
+ by 0x........: main (scalar.c:1137)
Syscall param io_cancel(iocb) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1118)
+ by 0x........: main (scalar.c:1137)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param io_cancel(result) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1118)
+ by 0x........: main (scalar.c:1137)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3509,23 +3649,23 @@
-----------------------------------------------------
Syscall param lookup_dcookie(cookie_low) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1134)
+ by 0x........: main (scalar.c:1153)
Syscall param lookup_dcookie(cookie_high) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1134)
+ by 0x........: main (scalar.c:1153)
Syscall param lookup_dcookie(buf) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1134)
+ by 0x........: main (scalar.c:1153)
Syscall param lookup_dcookie(len) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1134)
+ by 0x........: main (scalar.c:1153)
Syscall param lookup_dcookie(buf) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1134)
+ by 0x........: main (scalar.c:1153)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3533,30 +3673,30 @@
-----------------------------------------------------
Syscall param epoll_create(size) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1138)
+ by 0x........: main (scalar.c:1157)
-----------------------------------------------------
255: __NR_epoll_ctl 4s 1m
-----------------------------------------------------
Syscall param epoll_ctl(epfd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1142)
+ by 0x........: main (scalar.c:1161)
Syscall param epoll_ctl(op) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1142)
+ by 0x........: main (scalar.c:1161)
Syscall param epoll_ctl(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1142)
+ by 0x........: main (scalar.c:1161)
Syscall param epoll_ctl(event) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1142)
+ by 0x........: main (scalar.c:1161)
Syscall param epoll_ctl(event) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1142)
+ by 0x........: main (scalar.c:1161)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3564,23 +3704,23 @@
-----------------------------------------------------
Syscall param epoll_wait(epfd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1146)
+ by 0x........: main (scalar.c:1165)
Syscall param epoll_wait(events) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1146)
+ by 0x........: main (scalar.c:1165)
Syscall param epoll_wait(maxevents) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1146)
+ by 0x........: main (scalar.c:1165)
Syscall param epoll_wait(timeout) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1146)
+ by 0x........: main (scalar.c:1165)
Syscall param epoll_wait(events) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1146)
+ by 0x........: main (scalar.c:1165)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3591,41 +3731,41 @@
-----------------------------------------------------
Syscall param set_tid_address(tidptr) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1154)
+ by 0x........: main (scalar.c:1173)
-----------------------------------------------------
259: __NR_timer_create 3s 2m
-----------------------------------------------------
Syscall param timer_create(clockid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1158)
+ by 0x........: main (scalar.c:1177)
Syscall param timer_create(evp) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1158)
+ by 0x........: main (scalar.c:1177)
Syscall param timer_create(timerid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1158)
+ by 0x........: main (scalar.c:1177)
Syscall param timer_create(evp.sigev_value) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1158)
+ by 0x........: main (scalar.c:1177)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param timer_create(evp.sigev_signo) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1158)
+ by 0x........: main (scalar.c:1177)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param timer_create(evp.sigev_notify) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1158)
+ by 0x........: main (scalar.c:1177)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param timer_create(timerid) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1158)
+ by 0x........: main (scalar.c:1177)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3633,28 +3773,28 @@
-----------------------------------------------------
Syscall param timer_settime(timerid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1162)
+ by 0x........: main (scalar.c:1181)
Syscall param timer_settime(flags) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1162)
+ by 0x........: main (scalar.c:1181)
Syscall param timer_settime(value) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1162)
+ by 0x........: main (scalar.c:1181)
Syscall param timer_settime(ovalue) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1162)
+ by 0x........: main (scalar.c:1181)
Syscall param timer_settime(value) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1162)
+ by 0x........: main (scalar.c:1181)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param timer_settime(ovalue) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1162)
+ by 0x........: main (scalar.c:1181)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3662,15 +3802,15 @@
-----------------------------------------------------
Syscall param timer_gettime(timerid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1166)
+ by 0x........: main (scalar.c:1185)
Syscall param timer_gettime(value) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1166)
+ by 0x........: main (scalar.c:1185)
Syscall param timer_gettime(value) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1166)
+ by 0x........: main (scalar.c:1185)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3678,29 +3818,29 @@
-----------------------------------------------------
Syscall param timer_getoverrun(timerid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1170)
+ by 0x........: main (scalar.c:1189)
-----------------------------------------------------
263: __NR_timer_delete 1s 0m
-----------------------------------------------------
Syscall param timer_delete(timerid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1174)
+ by 0x........: main (scalar.c:1193)
-----------------------------------------------------
264: __NR_clock_settime 2s 1m
-----------------------------------------------------
Syscall param clock_settime(clk_id) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1178)
+ by 0x........: main (scalar.c:1197)
Syscall param clock_settime(tp) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1178)
+ by 0x........: main (scalar.c:1197)
Syscall param clock_settime(tp) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1178)
+ by 0x........: main (scalar.c:1197)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3708,15 +3848,15 @@
-----------------------------------------------------
Syscall param clock_gettime(clk_id) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1182)
+ by 0x........: main (scalar.c:1201)
Syscall param clock_gettime(tp) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1182)
+ by 0x........: main (scalar.c:1201)
Syscall param clock_gettime(tp) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1182)
+ by 0x........: main (scalar.c:1201)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3724,15 +3864,15 @@
-----------------------------------------------------
Syscall param clock_getres(clk_id) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1186)
+ by 0x........: main (scalar.c:1205)
Syscall param clock_getres(res) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1186)
+ by 0x........: main (scalar.c:1205)
Syscall param clock_getres(res) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1186)
+ by 0x........: main (scalar.c:1205)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3743,24 +3883,24 @@
-----------------------------------------------------
Syscall param statfs64(path) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1194)
+ by 0x........: main (scalar.c:1213)
Syscall param statfs64(size) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1194)
+ by 0x........: main (scalar.c:1213)
Syscall param statfs64(buf) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1194)
+ by 0x........: main (scalar.c:1213)
Syscall param statfs64(path) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1194)
+ by 0x........: main (scalar.c:1213)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param statfs64(buf) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1194)
+ by 0x........: main (scalar.c:1213)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3768,19 +3908,19 @@
-----------------------------------------------------
Syscall param fstatfs64(fd) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1198)
+ by 0x........: main (scalar.c:1217)
Syscall param fstatfs64(size) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1198)
+ by 0x........: main (scalar.c:1217)
Syscall param fstatfs64(buf) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1198)
+ by 0x........: main (scalar.c:1217)
Syscall param fstatfs64(buf) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1198)
+ by 0x........: main (scalar.c:1217)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3791,25 +3931,25 @@
-----------------------------------------------------
Syscall param utimes(filename) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1206)
+ by 0x........: main (scalar.c:1225)
Syscall param utimes(tvp) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1206)
+ by 0x........: main (scalar.c:1225)
Syscall param utimes(filename) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1206)
+ by 0x........: main (scalar.c:1225)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param utimes(tvp[0]) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1206)
+ by 0x........: main (scalar.c:1225)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param utimes(tvp[1]) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1206)
+ by 0x........: main (scalar.c:1225)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3832,33 +3972,33 @@
-----------------------------------------------------
Syscall param mq_open(name) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1230)
+ by 0x........: main (scalar.c:1249)
Syscall param mq_open(oflag) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1230)
+ by 0x........: main (scalar.c:1249)
Syscall param mq_open(mode) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1230)
+ by 0x........: main (scalar.c:1249)
Syscall param mq_open(attr) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1230)
+ by 0x........: main (scalar.c:1249)
Syscall param mq_open(name) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1230)
+ by 0x........: main (scalar.c:1249)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param mq_open(attr->mq_maxmsg) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1230)
+ by 0x........: main (scalar.c:1249)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param mq_open(attr->mq_msgsize) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1230)
+ by 0x........: main (scalar.c:1249)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3866,11 +4006,11 @@
-----------------------------------------------------
Syscall param mq_unlink(name) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1234)
+ by 0x........: main (scalar.c:1253)
Syscall param mq_unlink(name) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1234)
+ by 0x........: main (scalar.c:1253)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3878,32 +4018,32 @@
-----------------------------------------------------
Syscall param mq_timedsend(mqdes) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1238)
+ by 0x........: main (scalar.c:1257)
Syscall param mq_timedsend(msg_ptr) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1238)
+ by 0x........: main (scalar.c:1257)
Syscall param mq_timedsend(msg_len) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1238)
+ by 0x........: main (scalar.c:1257)
Syscall param mq_timedsend(msg_prio) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1238)
+ by 0x........: main (scalar.c:1257)
Syscall param mq_timedsend(abs_timeout) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1238)
+ by 0x........: main (scalar.c:1257)
Syscall param mq_timedsend(msg_ptr) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1238)
+ by 0x........: main (scalar.c:1257)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param mq_timedsend(abs_timeout) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1238)
+ by 0x........: main (scalar.c:1257)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3911,37 +4051,37 @@
-----------------------------------------------------
Syscall param mq_timedreceive(mqdes) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1242)
+ by 0x........: main (scalar.c:1261)
Syscall param mq_timedreceive(msg_ptr) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1242)
+ by 0x........: main (scalar.c:1261)
Syscall param mq_timedreceive(msg_len) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1242)
+ by 0x........: main (scalar.c:1261)
Syscall param mq_timedreceive(msg_prio) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1242)
+ by 0x........: main (scalar.c:1261)
Syscall param mq_timedreceive(abs_timeout) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1242)
+ by 0x........: main (scalar.c:1261)
Syscall param mq_timedreceive(msg_ptr) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1242)
+ by 0x........: main (scalar.c:1261)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param mq_timedreceive(msg_prio) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1242)
+ by 0x........: main (scalar.c:1261)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param mq_timedreceive(abs_timeout) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1242)
+ by 0x........: main (scalar.c:1261)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3949,15 +4089,15 @@
-----------------------------------------------------
Syscall param mq_notify(mqdes) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1246)
+ by 0x........: main (scalar.c:1265)
Syscall param mq_notify(notification) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1246)
+ by 0x........: main (scalar.c:1265)
Syscall param mq_notify(notification) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1246)
+ by 0x........: main (scalar.c:1265)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3965,24 +4105,24 @@
-----------------------------------------------------
Syscall param mq_getsetattr(mqdes) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1250)
+ by 0x........: main (scalar.c:1269)
Syscall param mq_getsetattr(mqstat) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1250)
+ by 0x........: main (scalar.c:1269)
Syscall param mq_getsetattr(omqstat) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1250)
+ by 0x........: main (scalar.c:1269)
Syscall param mq_getsetattr(mqstat->mq_flags) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1250)
+ by 0x........: main (scalar.c:1269)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param mq_getsetattr(omqstat) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1250)
+ by 0x........: main (scalar.c:1269)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -3993,43 +4133,43 @@
-----------------------------------------------------
Syscall param epoll_create1(flags) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1258)
+ by 0x........: main (scalar.c:1277)
-----------------------------------------------------
347:__NR_process_vm_readv 6s 2m
-----------------------------------------------------
Syscall param process_vm_readv(pid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1262)
+ by 0x........: main (scalar.c:1281)
Syscall param process_vm_readv(lvec) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1262)
+ by 0x........: main (scalar.c:1281)
Syscall param process_vm_readv(liovcnt) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1262)
+ by 0x........: main (scalar.c:1281)
Syscall param process_vm_readv(rvec) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1262)
+ by 0x........: main (scalar.c:1281)
Syscall param process_vm_readv(riovcnt) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1262)
+ by 0x........: main (scalar.c:1281)
Syscall param process_vm_readv(flags) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1262)
+ by 0x........: main (scalar.c:1281)
Syscall param process_vm_readv(lvec) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1262)
+ by 0x........: main (scalar.c:1281)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param process_vm_readv(rvec) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1262)
+ by 0x........: main (scalar.c:1281)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -4037,36 +4177,36 @@
-----------------------------------------------------
Syscall param process_vm_writev(pid) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1266)
+ by 0x........: main (scalar.c:1285)
Syscall param process_vm_writev(lvec) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1266)
+ by 0x........: main (scalar.c:1285)
Syscall param process_vm_writev(liovcnt) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1266)
+ by 0x........: main (scalar.c:1285)
Syscall param process_vm_writev(rvec) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1266)
+ by 0x........: main (scalar.c:1285)
Syscall param process_vm_writev(riovcnt) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1266)
+ by 0x........: main (scalar.c:1285)
Syscall param process_vm_writev(flags) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1266)
+ by 0x........: main (scalar.c:1285)
Syscall param process_vm_writev(lvec) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1266)
+ by 0x........: main (scalar.c:1285)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Syscall param process_vm_writev(rvec) points to unaddressable byte(s)
...
- by 0x........: main (scalar.c:1266)
+ by 0x........: main (scalar.c:1285)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
-----------------------------------------------------
@@ -4082,5 +4222,5 @@
-----------------------------------------------------
Syscall param exit(status) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1274)
+ by 0x........: main (scalar.c:1293)
diff --git a/memcheck/tests/x86-solaris/Makefile.am b/memcheck/tests/x86-solaris/Makefile.am
index 3759fe6..c5c2e68 100644
--- a/memcheck/tests/x86-solaris/Makefile.am
+++ b/memcheck/tests/x86-solaris/Makefile.am
@@ -30,3 +30,4 @@
AM_CXXFLAGS += @FLAG_M32@
AM_CCASFLAGS += @FLAG_M32@
+scalar_CFLAGS = $(AM_CFLAGS) -I../solaris
diff --git a/memcheck/tests/x86-solaris/Makefile.in b/memcheck/tests/x86-solaris/Makefile.in
index c3cef80..22a8f55 100644
--- a/memcheck/tests/x86-solaris/Makefile.in
+++ b/memcheck/tests/x86-solaris/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -156,8 +156,10 @@
ldsoexec_OBJECTS = ldsoexec.$(OBJEXT)
ldsoexec_LDADD = $(LDADD)
scalar_SOURCES = scalar.c
-scalar_OBJECTS = scalar.$(OBJEXT)
+scalar_OBJECTS = scalar-scalar.$(OBJEXT)
scalar_LDADD = $(LDADD)
+scalar_LINK = $(CCLD) $(scalar_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
scalar_obsolete_SOURCES = scalar_obsolete.c
scalar_obsolete_OBJECTS = scalar_obsolete.$(OBJEXT)
scalar_obsolete_LDADD = $(LDADD)
@@ -178,6 +180,10 @@
depcomp = $(SHELL) $(top_srcdir)/depcomp
am__depfiles_maybe = depfiles
am__mv = mv -f
+AM_V_lt = $(am__v_lt_@AM_V@)
+am__v_lt_ = $(am__v_lt_@AM_DEFAULT_V@)
+am__v_lt_0 = --silent
+am__v_lt_1 =
COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
$(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
AM_V_CC = $(am__v_CC_@AM_V@)
@@ -267,6 +273,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -437,6 +444,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -447,6 +455,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -521,8 +530,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -567,7 +574,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
@@ -600,6 +606,7 @@
context_sse.stderr.exp context_sse.stdout.exp context_sse.vgtest \
ldsoexec.stderr.exp ldsoexec.vgtest
+scalar_CFLAGS = $(AM_CFLAGS) -I../solaris
all: all-am
.SUFFIXES:
@@ -664,7 +671,7 @@
scalar$(EXEEXT): $(scalar_OBJECTS) $(scalar_DEPENDENCIES) $(EXTRA_scalar_DEPENDENCIES)
@rm -f scalar$(EXEEXT)
- $(AM_V_CCLD)$(LINK) $(scalar_OBJECTS) $(scalar_LDADD) $(LIBS)
+ $(AM_V_CCLD)$(scalar_LINK) $(scalar_OBJECTS) $(scalar_LDADD) $(LIBS)
scalar_obsolete$(EXEEXT): $(scalar_obsolete_OBJECTS) $(scalar_obsolete_DEPENDENCIES) $(EXTRA_scalar_obsolete_DEPENDENCIES)
@rm -f scalar_obsolete$(EXEEXT)
@@ -682,7 +689,7 @@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/context_gpr.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/context_sse.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ldsoexec.Po@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scalar.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scalar-scalar.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scalar_obsolete.Po@am__quote@
.c.o:
@@ -701,6 +708,20 @@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(COMPILE) -c -o $@ `$(CYGPATH_W) '$<'`
+scalar-scalar.o: scalar.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(scalar_CFLAGS) $(CFLAGS) -MT scalar-scalar.o -MD -MP -MF $(DEPDIR)/scalar-scalar.Tpo -c -o scalar-scalar.o `test -f 'scalar.c' || echo '$(srcdir)/'`scalar.c
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/scalar-scalar.Tpo $(DEPDIR)/scalar-scalar.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='scalar.c' object='scalar-scalar.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(scalar_CFLAGS) $(CFLAGS) -c -o scalar-scalar.o `test -f 'scalar.c' || echo '$(srcdir)/'`scalar.c
+
+scalar-scalar.obj: scalar.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(scalar_CFLAGS) $(CFLAGS) -MT scalar-scalar.obj -MD -MP -MF $(DEPDIR)/scalar-scalar.Tpo -c -o scalar-scalar.obj `if test -f 'scalar.c'; then $(CYGPATH_W) 'scalar.c'; else $(CYGPATH_W) '$(srcdir)/scalar.c'; fi`
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/scalar-scalar.Tpo $(DEPDIR)/scalar-scalar.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='scalar.c' object='scalar-scalar.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(scalar_CFLAGS) $(CFLAGS) -c -o scalar-scalar.obj `if test -f 'scalar.c'; then $(CYGPATH_W) 'scalar.c'; else $(CYGPATH_W) '$(srcdir)/scalar.c'; fi`
+
ID: $(am__tagged_files)
$(am__define_uniq_tagged_files); mkid -fID $$unique
tags: tags-am
diff --git a/memcheck/tests/x86-solaris/scalar.c b/memcheck/tests/x86-solaris/scalar.c
index 37e1c28..f23a0f9 100644
--- a/memcheck/tests/x86-solaris/scalar.c
+++ b/memcheck/tests/x86-solaris/scalar.c
@@ -1,9 +1,10 @@
/* Basic syscall test for Solaris/x86 specific syscalls. */
-#include "../solaris/scalar.h"
+#include "scalar.h"
#include <string.h>
#include <sys/fcntl.h>
+#include <sys/lwp.h>
#include <sys/statvfs.h>
/* Helper functions. These are necessary if we've got two tests for a single
@@ -63,6 +64,10 @@
sys_openat64();
sys_openat642();
+ /* SYS_lwp_private 166 */
+ GO(SYS_lwp_private, "3s 1m");
+ SY(SYS_lwp_private, x0 + _LWP_GETPRIVATE, x0 + _LWP_GSBASE, x0); FAIL;
+
/* SYS_llseek 175 */
GO(SYS_llseek, "4s 0m");
SY(SYS_llseek, x0 - 1, x0, x0, x0); FAILx(EBADF);
diff --git a/memcheck/tests/x86-solaris/scalar.stderr.exp b/memcheck/tests/x86-solaris/scalar.stderr.exp
index 0e11522..50ab62e 100644
--- a/memcheck/tests/x86-solaris/scalar.stderr.exp
+++ b/memcheck/tests/x86-solaris/scalar.stderr.exp
@@ -57,6 +57,22 @@
Address 0x........ is not stack'd, malloc'd or (recently) free'd
---------------------------------------------------------
+166: SYS_lwp_private 3s 1m
+---------------------------------------------------------
+Syscall param lwp_private(cmd) contains uninitialised byte(s)
+ ...
+
+Syscall param lwp_private(which) contains uninitialised byte(s)
+ ...
+
+Syscall param lwp_private(base) contains uninitialised byte(s)
+ ...
+
+Syscall param lwp_private(base) points to unaddressable byte(s)
+ ...
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+---------------------------------------------------------
175: SYS_llseek 4s 0m
---------------------------------------------------------
Syscall param llseek(fildes) contains uninitialised byte(s)
diff --git a/memcheck/tests/x86/Makefile.in b/memcheck/tests/x86/Makefile.in
index 01e161c..6e5e7f4 100644
--- a/memcheck/tests/x86/Makefile.in
+++ b/memcheck/tests/x86/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -297,6 +297,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -467,6 +468,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -477,6 +479,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -551,8 +554,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -597,7 +598,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/mpi/Makefile.in b/mpi/Makefile.in
index a83fb99..8eb0b57 100644
--- a/mpi/Makefile.in
+++ b/mpi/Makefile.in
@@ -235,6 +235,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -405,6 +406,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -415,6 +417,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -489,8 +492,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -535,7 +536,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
DEFAULT_INCLUDES =
diff --git a/mpi/libmpiwrap.c b/mpi/libmpiwrap.c
index cae725b..488bb13 100644
--- a/mpi/libmpiwrap.c
+++ b/mpi/libmpiwrap.c
@@ -18,7 +18,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2006-2015 OpenWorks LLP. All rights reserved.
+ Copyright (C) 2006-2017 OpenWorks LLP. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
diff --git a/none/Makefile.in b/none/Makefile.in
index 19a61d1..6f7bb9b 100644
--- a/none/Makefile.in
+++ b/none/Makefile.in
@@ -282,6 +282,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -453,6 +454,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -463,6 +465,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -537,8 +540,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -583,7 +584,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
@@ -661,9 +661,6 @@
-static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \
@FLAG_M64@
-TOOL_LDFLAGS_TILEGX_LINUX = \
- $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-
TOOL_LDFLAGS_X86_SOLARIS = \
$(TOOL_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
@@ -718,9 +715,6 @@
LIBREPLACEMALLOC_MIPS64_LINUX = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a
-LIBREPLACEMALLOC_TILEGX_LINUX = \
- $(top_builddir)/coregrind/libreplacemalloc_toolpreload-tilegx-linux.a
-
LIBREPLACEMALLOC_X86_SOLARIS = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-solaris.a
@@ -783,11 +777,6 @@
$(LIBREPLACEMALLOC_MIPS64_LINUX) \
-Wl,--no-whole-archive
-LIBREPLACEMALLOC_LDFLAGS_TILEGX_LINUX = \
- -Wl,--whole-archive \
- $(LIBREPLACEMALLOC_TILEGX_LINUX) \
- -Wl,--no-whole-archive
-
LIBREPLACEMALLOC_LDFLAGS_X86_SOLARIS = \
-Wl,--whole-archive \
$(LIBREPLACEMALLOC_X86_SOLARIS) \
diff --git a/none/nl_main.c b/none/nl_main.c
index ffe19e1..e0790b1 100644
--- a/none/nl_main.c
+++ b/none/nl_main.c
@@ -7,7 +7,7 @@
This file is part of Nulgrind, the minimal Valgrind tool,
which does no instrumentation or analysis.
- Copyright (C) 2002-2015 Nicholas Nethercote
+ Copyright (C) 2002-2017 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -56,7 +56,7 @@
VG_(details_version) (NULL);
VG_(details_description) ("the minimal Valgrind tool");
VG_(details_copyright_author)(
- "Copyright (C) 2002-2015, and GNU GPL'd, by Nicholas Nethercote.");
+ "Copyright (C) 2002-2017, and GNU GPL'd, by Nicholas Nethercote.");
VG_(details_bug_reports_to) (VG_BUGS_TO);
VG_(details_avg_translation_sizeB) ( 275 );
diff --git a/none/tests/Makefile.am b/none/tests/Makefile.am
index ffe55d4..34816c0 100644
--- a/none/tests/Makefile.am
+++ b/none/tests/Makefile.am
@@ -32,9 +32,6 @@
if VGCONF_ARCHS_INCLUDE_MIPS64
SUBDIRS += mips64
endif
-if VGCONF_ARCHS_INCLUDE_TILEGX
-SUBDIRS += tilegx
-endif
# OS-specific tests
if VGCONF_OS_IS_LINUX
@@ -67,7 +64,7 @@
SUBDIRS += x86-solaris
endif
-DIST_SUBDIRS = x86 amd64 ppc32 ppc64 arm arm64 s390x mips32 mips64 tilegx \
+DIST_SUBDIRS = x86 amd64 ppc32 ppc64 arm arm64 s390x mips32 mips64 \
linux darwin solaris amd64-linux x86-linux amd64-darwin \
x86-darwin amd64-solaris x86-solaris scripts .
@@ -168,6 +165,7 @@
pth_rwlock.stderr.exp pth_rwlock.vgtest \
pth_stackalign.stderr.exp \
pth_stackalign.stdout.exp pth_stackalign.vgtest \
+ pth_2sig.stderr.exp-linux pth_2sig.stderr.exp-solaris pth_2sig.vgtest \
pth_term_signal.stderr.exp pth_term_signal.vgtest \
rcrl.stderr.exp rcrl.stdout.exp rcrl.vgtest \
readline1.stderr.exp readline1.stdout.exp \
@@ -188,6 +186,7 @@
shortpush.stderr.exp shortpush.vgtest \
shorts.stderr.exp shorts.vgtest \
sigstackgrowth.stdout.exp sigstackgrowth.stderr.exp sigstackgrowth.vgtest \
+ sigsusp.stderr.exp sigsusp.vgtest \
stackgrowth.stdout.exp stackgrowth.stderr.exp stackgrowth.vgtest \
syscall-restart1.vgtest syscall-restart1.stdout.exp syscall-restart1.stderr.exp \
syscall-restart2.vgtest syscall-restart2.stdout.exp syscall-restart2.stderr.exp \
@@ -201,6 +200,7 @@
tls.vgtest tls.stderr.exp tls.stdout.exp \
unit_debuglog.stderr.exp unit_debuglog.vgtest \
vgprintf.stderr.exp vgprintf.vgtest \
+ vgprintf_nvalgrind.stderr.exp vgprintf_nvalgrind.vgtest \
process_vm_readv_writev.stderr.exp process_vm_readv_writev.vgtest
check_PROGRAMS = \
@@ -227,12 +227,12 @@
pselect_sigmask_null \
pth_atfork1 pth_blockedsig pth_cancel1 pth_cancel2 pth_cvsimple \
pth_empty pth_exit pth_exit2 pth_mutexspeed pth_once pth_rwlock \
- pth_stackalign pth_term_signal\
+ pth_stackalign pth_2sig pth_term_signal\
rcrl readline1 \
require-text-symbol \
res_search resolv \
rlimit_nofile selfrun sem semlimit sha1_test \
- shortpush shorts stackgrowth sigstackgrowth \
+ shortpush shorts stackgrowth sigstackgrowth sigsusp \
syscall-restart1 syscall-restart2 \
syslog \
system \
@@ -246,6 +246,7 @@
unit_debuglog \
valgrind_cpp_test \
vgprintf \
+ vgprintf_nvalgrind \
coolo_sigaction \
gxx304 \
process_vm_readv_writev
@@ -318,6 +319,7 @@
pth_rwlock_CFLAGS += --std=c99
endif
pth_stackalign_LDADD = -lpthread
+pth_2sig_LDADD = -lpthread
pth_term_signal_LDADD = -lpthread
res_search_LDADD = -lresolv -lpthread
resolv_CFLAGS = $(AM_CFLAGS)
@@ -330,6 +332,7 @@
if VGCONF_OS_IS_SOLARIS
sha1_test_CFLAGS += -Du_int32_t=uint32_t
endif
+sigsusp_LDADD = -lpthread
thread_exits_LDADD = -lpthread
threaded_fork_LDADD = -lpthread
threadederrno_CFLAGS = $(AM_CFLAGS)
@@ -358,6 +361,9 @@
tls2_so_LDFLAGS = -shared
endif
+vgprintf_nvalgrind_SOURCES = vgprintf.c
+vgprintf_nvalgrind_CFLAGS = -DNVALGRIND
+
valgrind_cpp_test_SOURCES = valgrind_cpp_test.cpp
valgrind_cpp_test_LDADD = -lstdc++
diff --git a/none/tests/Makefile.in b/none/tests/Makefile.in
index d9ffe8d..8c2fe6b 100644
--- a/none/tests/Makefile.in
+++ b/none/tests/Makefile.in
@@ -112,7 +112,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -132,20 +132,19 @@
@VGCONF_ARCHS_INCLUDE_S390X_TRUE@am__append_14 = s390x
@VGCONF_ARCHS_INCLUDE_MIPS32_TRUE@am__append_15 = mips32
@VGCONF_ARCHS_INCLUDE_MIPS64_TRUE@am__append_16 = mips64
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@am__append_17 = tilegx
# OS-specific tests
-@VGCONF_OS_IS_LINUX_TRUE@am__append_18 = linux
-@VGCONF_OS_IS_DARWIN_TRUE@am__append_19 = darwin
-@VGCONF_OS_IS_SOLARIS_TRUE@am__append_20 = solaris
+@VGCONF_OS_IS_LINUX_TRUE@am__append_17 = linux
+@VGCONF_OS_IS_DARWIN_TRUE@am__append_18 = darwin
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_19 = solaris
# Platform-specific tests
-@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_21 = amd64-linux
-@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_22 = x86-linux
-@VGCONF_PLATFORMS_INCLUDE_AMD64_DARWIN_TRUE@am__append_23 = amd64-darwin
-@VGCONF_PLATFORMS_INCLUDE_X86_DARWIN_TRUE@am__append_24 = x86-darwin
-@VGCONF_PLATFORMS_INCLUDE_AMD64_SOLARIS_TRUE@am__append_25 = amd64-solaris
-@VGCONF_PLATFORMS_INCLUDE_X86_SOLARIS_TRUE@am__append_26 = x86-solaris
+@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_20 = amd64-linux
+@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_21 = x86-linux
+@VGCONF_PLATFORMS_INCLUDE_AMD64_DARWIN_TRUE@am__append_22 = amd64-darwin
+@VGCONF_PLATFORMS_INCLUDE_X86_DARWIN_TRUE@am__append_23 = x86-darwin
+@VGCONF_PLATFORMS_INCLUDE_AMD64_SOLARIS_TRUE@am__append_24 = amd64-solaris
+@VGCONF_PLATFORMS_INCLUDE_X86_SOLARIS_TRUE@am__append_25 = x86-solaris
check_PROGRAMS = args$(EXEEXT) async-sigs$(EXEEXT) bitfield1$(EXEEXT) \
bug129866$(EXEEXT) bug234814$(EXEEXT) closeall$(EXEEXT) \
coolo_strlen$(EXEEXT) discard$(EXEEXT) exec-sigmask$(EXEEXT) \
@@ -164,35 +163,37 @@
pth_cancel1$(EXEEXT) pth_cancel2$(EXEEXT) \
pth_cvsimple$(EXEEXT) pth_empty$(EXEEXT) pth_exit$(EXEEXT) \
pth_exit2$(EXEEXT) pth_mutexspeed$(EXEEXT) pth_once$(EXEEXT) \
- pth_rwlock$(EXEEXT) pth_stackalign$(EXEEXT) \
+ pth_rwlock$(EXEEXT) pth_stackalign$(EXEEXT) pth_2sig$(EXEEXT) \
pth_term_signal$(EXEEXT) rcrl$(EXEEXT) readline1$(EXEEXT) \
require-text-symbol$(EXEEXT) res_search$(EXEEXT) \
resolv$(EXEEXT) rlimit_nofile$(EXEEXT) selfrun$(EXEEXT) \
sem$(EXEEXT) semlimit$(EXEEXT) sha1_test$(EXEEXT) \
shortpush$(EXEEXT) shorts$(EXEEXT) stackgrowth$(EXEEXT) \
- sigstackgrowth$(EXEEXT) syscall-restart1$(EXEEXT) \
- syscall-restart2$(EXEEXT) syslog$(EXEEXT) system$(EXEEXT) \
- thread-exits$(EXEEXT) threaded-fork$(EXEEXT) \
- threadederrno$(EXEEXT) timestamp$(EXEEXT) tls$(EXEEXT) \
- tls.so$(EXEEXT) tls2.so$(EXEEXT) unit_debuglog$(EXEEXT) \
+ sigstackgrowth$(EXEEXT) sigsusp$(EXEEXT) \
+ syscall-restart1$(EXEEXT) syscall-restart2$(EXEEXT) \
+ syslog$(EXEEXT) system$(EXEEXT) thread-exits$(EXEEXT) \
+ threaded-fork$(EXEEXT) threadederrno$(EXEEXT) \
+ timestamp$(EXEEXT) tls$(EXEEXT) tls.so$(EXEEXT) \
+ tls2.so$(EXEEXT) unit_debuglog$(EXEEXT) \
valgrind_cpp_test$(EXEEXT) vgprintf$(EXEEXT) \
- coolo_sigaction$(EXEEXT) gxx304$(EXEEXT) \
- process_vm_readv_writev$(EXEEXT) $(am__EXEEXT_1) \
- $(am__EXEEXT_2) $(am__EXEEXT_3) $(am__EXEEXT_4)
-@HAVE_NESTED_FUNCTIONS_TRUE@am__append_27 = nestedfns
+ vgprintf_nvalgrind$(EXEEXT) coolo_sigaction$(EXEEXT) \
+ gxx304$(EXEEXT) process_vm_readv_writev$(EXEEXT) \
+ $(am__EXEEXT_1) $(am__EXEEXT_2) $(am__EXEEXT_3) \
+ $(am__EXEEXT_4)
+@HAVE_NESTED_FUNCTIONS_TRUE@am__append_26 = nestedfns
# This doesn't appear to be compilable on Darwin.
-@VGCONF_OS_IS_DARWIN_FALSE@am__append_28 = rlimit64_nofile \
+@VGCONF_OS_IS_DARWIN_FALSE@am__append_27 = rlimit64_nofile \
@VGCONF_OS_IS_DARWIN_FALSE@ ppoll_alarm
# clang does not know -ansi
-@COMPILER_IS_CLANG_FALSE@am__append_29 = ansi
-@BUILD_IFUNC_TESTS_TRUE@am__append_30 = ifunc
-@VGCONF_OS_IS_SOLARIS_TRUE@am__append_31 = --std=c99
-@VGCONF_OS_IS_SOLARIS_TRUE@am__append_32 = -U_REENTRANT
-@VGCONF_OS_IS_SOLARIS_TRUE@am__append_33 = -Du_int32_t=uint32_t
-@VGCONF_OS_IS_SOLARIS_TRUE@am__append_34 = --std=c99
+@COMPILER_IS_CLANG_FALSE@am__append_28 = ansi
+@BUILD_IFUNC_TESTS_TRUE@am__append_29 = ifunc
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_30 = --std=c99
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_31 = -U_REENTRANT
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_32 = -Du_int32_t=uint32_t
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_33 = --std=c99
subdir = none/tests
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/configure.ac
@@ -360,6 +361,9 @@
pselect_sigmask_null_SOURCES = pselect_sigmask_null.c
pselect_sigmask_null_OBJECTS = pselect_sigmask_null.$(OBJEXT)
pselect_sigmask_null_LDADD = $(LDADD)
+pth_2sig_SOURCES = pth_2sig.c
+pth_2sig_OBJECTS = pth_2sig.$(OBJEXT)
+pth_2sig_DEPENDENCIES =
pth_atfork1_SOURCES = pth_atfork1.c
pth_atfork1_OBJECTS = pth_atfork1.$(OBJEXT)
pth_atfork1_DEPENDENCIES =
@@ -449,6 +453,9 @@
sigstackgrowth_SOURCES = sigstackgrowth.c
sigstackgrowth_OBJECTS = sigstackgrowth.$(OBJEXT)
sigstackgrowth_LDADD = $(LDADD)
+sigsusp_SOURCES = sigsusp.c
+sigsusp_OBJECTS = sigsusp.$(OBJEXT)
+sigsusp_DEPENDENCIES =
stackgrowth_SOURCES = stackgrowth.c
stackgrowth_OBJECTS = stackgrowth.$(OBJEXT)
stackgrowth_LDADD = $(LDADD)
@@ -500,6 +507,11 @@
vgprintf_SOURCES = vgprintf.c
vgprintf_OBJECTS = vgprintf.$(OBJEXT)
vgprintf_LDADD = $(LDADD)
+am_vgprintf_nvalgrind_OBJECTS = vgprintf_nvalgrind-vgprintf.$(OBJEXT)
+vgprintf_nvalgrind_OBJECTS = $(am_vgprintf_nvalgrind_OBJECTS)
+vgprintf_nvalgrind_LDADD = $(LDADD)
+vgprintf_nvalgrind_LINK = $(CCLD) $(vgprintf_nvalgrind_CFLAGS) \
+ $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
SCRIPTS = $(dist_noinst_SCRIPTS)
AM_V_P = $(am__v_P_@AM_V@)
am__v_P_ = $(am__v_P_@AM_DEFAULT_V@)
@@ -557,17 +569,18 @@
map_unmap.c mmap_fcntl_bug.c mq.c munmap_exe.c nestedfns.c \
nocwd.c pending.c ppoll_alarm.c process_vm_readv_writev.c \
procfs-cmdline-exe.c pselect_alarm.c pselect_sigmask_null.c \
- pth_atfork1.c pth_blockedsig.c pth_cancel1.c pth_cancel2.c \
- pth_cvsimple.c pth_empty.c pth_exit.c pth_exit2.c \
- pth_mutexspeed.c pth_once.c pth_rwlock.c pth_stackalign.c \
- pth_term_signal.c rcrl.c readline1.c require-text-symbol.c \
- res_search.c resolv.c rlimit64_nofile.c rlimit_nofile.c \
- selfrun.c sem.c semlimit.c sha1_test.c shortpush.c shorts.c \
- sigstackgrowth.c stackgrowth.c syscall-restart1.c \
- syscall-restart2.c syslog.c system.c thread-exits.c \
- threaded-fork.c threadederrno.c timestamp.c $(tls_SOURCES) \
- $(tls_so_SOURCES) $(tls2_so_SOURCES) unit_debuglog.c \
- $(valgrind_cpp_test_SOURCES) vgprintf.c
+ pth_2sig.c pth_atfork1.c pth_blockedsig.c pth_cancel1.c \
+ pth_cancel2.c pth_cvsimple.c pth_empty.c pth_exit.c \
+ pth_exit2.c pth_mutexspeed.c pth_once.c pth_rwlock.c \
+ pth_stackalign.c pth_term_signal.c rcrl.c readline1.c \
+ require-text-symbol.c res_search.c resolv.c rlimit64_nofile.c \
+ rlimit_nofile.c selfrun.c sem.c semlimit.c sha1_test.c \
+ shortpush.c shorts.c sigstackgrowth.c sigsusp.c stackgrowth.c \
+ syscall-restart1.c syscall-restart2.c syslog.c system.c \
+ thread-exits.c threaded-fork.c threadederrno.c timestamp.c \
+ $(tls_SOURCES) $(tls_so_SOURCES) $(tls2_so_SOURCES) \
+ unit_debuglog.c $(valgrind_cpp_test_SOURCES) vgprintf.c \
+ $(vgprintf_nvalgrind_SOURCES)
DIST_SOURCES = ansi.c args.c async-sigs.c bitfield1.c bug129866.c \
bug234814.c closeall.c $(coolo_sigaction_SOURCES) \
coolo_strlen.c discard.c exec-sigmask.c execve.c faultstatus.c \
@@ -579,17 +592,18 @@
map_unmap.c mmap_fcntl_bug.c mq.c munmap_exe.c nestedfns.c \
nocwd.c pending.c ppoll_alarm.c process_vm_readv_writev.c \
procfs-cmdline-exe.c pselect_alarm.c pselect_sigmask_null.c \
- pth_atfork1.c pth_blockedsig.c pth_cancel1.c pth_cancel2.c \
- pth_cvsimple.c pth_empty.c pth_exit.c pth_exit2.c \
- pth_mutexspeed.c pth_once.c pth_rwlock.c pth_stackalign.c \
- pth_term_signal.c rcrl.c readline1.c require-text-symbol.c \
- res_search.c resolv.c rlimit64_nofile.c rlimit_nofile.c \
- selfrun.c sem.c semlimit.c sha1_test.c shortpush.c shorts.c \
- sigstackgrowth.c stackgrowth.c syscall-restart1.c \
- syscall-restart2.c syslog.c system.c thread-exits.c \
- threaded-fork.c threadederrno.c timestamp.c $(tls_SOURCES) \
- $(tls_so_SOURCES) $(tls2_so_SOURCES) unit_debuglog.c \
- $(valgrind_cpp_test_SOURCES) vgprintf.c
+ pth_2sig.c pth_atfork1.c pth_blockedsig.c pth_cancel1.c \
+ pth_cancel2.c pth_cvsimple.c pth_empty.c pth_exit.c \
+ pth_exit2.c pth_mutexspeed.c pth_once.c pth_rwlock.c \
+ pth_stackalign.c pth_term_signal.c rcrl.c readline1.c \
+ require-text-symbol.c res_search.c resolv.c rlimit64_nofile.c \
+ rlimit_nofile.c selfrun.c sem.c semlimit.c sha1_test.c \
+ shortpush.c shorts.c sigstackgrowth.c sigsusp.c stackgrowth.c \
+ syscall-restart1.c syscall-restart2.c syslog.c system.c \
+ thread-exits.c threaded-fork.c threadederrno.c timestamp.c \
+ $(tls_SOURCES) $(tls_so_SOURCES) $(tls2_so_SOURCES) \
+ unit_debuglog.c $(valgrind_cpp_test_SOURCES) vgprintf.c \
+ $(vgprintf_nvalgrind_SOURCES)
RECURSIVE_TARGETS = all-recursive check-recursive cscopelist-recursive \
ctags-recursive dvi-recursive html-recursive info-recursive \
install-data-recursive install-dvi-recursive \
@@ -703,6 +717,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -873,6 +888,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -883,6 +899,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -957,8 +974,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -1003,7 +1018,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
@@ -1031,9 +1045,8 @@
$(am__append_14) $(am__append_15) $(am__append_16) \
$(am__append_17) $(am__append_18) $(am__append_19) \
$(am__append_20) $(am__append_21) $(am__append_22) \
- $(am__append_23) $(am__append_24) $(am__append_25) \
- $(am__append_26)
-DIST_SUBDIRS = x86 amd64 ppc32 ppc64 arm arm64 s390x mips32 mips64 tilegx \
+ $(am__append_23) $(am__append_24) $(am__append_25)
+DIST_SUBDIRS = x86 amd64 ppc32 ppc64 arm arm64 s390x mips32 mips64 \
linux darwin solaris amd64-linux x86-linux amd64-darwin \
x86-darwin amd64-solaris x86-solaris scripts .
@@ -1133,6 +1146,7 @@
pth_rwlock.stderr.exp pth_rwlock.vgtest \
pth_stackalign.stderr.exp \
pth_stackalign.stdout.exp pth_stackalign.vgtest \
+ pth_2sig.stderr.exp-linux pth_2sig.stderr.exp-solaris pth_2sig.vgtest \
pth_term_signal.stderr.exp pth_term_signal.vgtest \
rcrl.stderr.exp rcrl.stdout.exp rcrl.vgtest \
readline1.stderr.exp readline1.stdout.exp \
@@ -1153,6 +1167,7 @@
shortpush.stderr.exp shortpush.vgtest \
shorts.stderr.exp shorts.vgtest \
sigstackgrowth.stdout.exp sigstackgrowth.stderr.exp sigstackgrowth.vgtest \
+ sigsusp.stderr.exp sigsusp.vgtest \
stackgrowth.stdout.exp stackgrowth.stderr.exp stackgrowth.vgtest \
syscall-restart1.vgtest syscall-restart1.stdout.exp syscall-restart1.stderr.exp \
syscall-restart2.vgtest syscall-restart2.stdout.exp syscall-restart2.stderr.exp \
@@ -1166,6 +1181,7 @@
tls.vgtest tls.stderr.exp tls.stdout.exp \
unit_debuglog.stderr.exp unit_debuglog.vgtest \
vgprintf.stderr.exp vgprintf.vgtest \
+ vgprintf_nvalgrind.stderr.exp vgprintf_nvalgrind.vgtest \
process_vm_readv_writev.stderr.exp process_vm_readv_writev.vgtest
@@ -1207,17 +1223,19 @@
pth_mutexspeed_LDADD = -lpthread
pth_once_LDADD = -lpthread
pth_rwlock_LDADD = -lpthread
-pth_rwlock_CFLAGS = $(AM_CFLAGS) $(am__append_31)
+pth_rwlock_CFLAGS = $(AM_CFLAGS) $(am__append_30)
pth_stackalign_LDADD = -lpthread
+pth_2sig_LDADD = -lpthread
pth_term_signal_LDADD = -lpthread
res_search_LDADD = -lresolv -lpthread
-resolv_CFLAGS = $(AM_CFLAGS) $(am__append_32)
+resolv_CFLAGS = $(AM_CFLAGS) $(am__append_31)
resolv_LDADD = -lresolv -lpthread
semlimit_LDADD = -lpthread
-sha1_test_CFLAGS = $(AM_CFLAGS) $(am__append_33)
+sha1_test_CFLAGS = $(AM_CFLAGS) $(am__append_32)
+sigsusp_LDADD = -lpthread
thread_exits_LDADD = -lpthread
threaded_fork_LDADD = -lpthread
-threadederrno_CFLAGS = $(AM_CFLAGS) $(am__append_34)
+threadederrno_CFLAGS = $(AM_CFLAGS) $(am__append_33)
threadederrno_LDADD = -lpthread
tls_SOURCES = tls.c tls2.c
tls_DEPENDENCIES = tls.so tls2.so
@@ -1233,6 +1251,8 @@
tls2_so_SOURCES = tls2_so.c
@VGCONF_OS_IS_DARWIN_FALSE@tls2_so_LDFLAGS = -shared
@VGCONF_OS_IS_DARWIN_TRUE@tls2_so_LDFLAGS = -dynamic -dynamiclib -all_load
+vgprintf_nvalgrind_SOURCES = vgprintf.c
+vgprintf_nvalgrind_CFLAGS = -DNVALGRIND
valgrind_cpp_test_SOURCES = valgrind_cpp_test.cpp
valgrind_cpp_test_LDADD = -lstdc++
@@ -1457,6 +1477,10 @@
@rm -f pselect_sigmask_null$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(pselect_sigmask_null_OBJECTS) $(pselect_sigmask_null_LDADD) $(LIBS)
+pth_2sig$(EXEEXT): $(pth_2sig_OBJECTS) $(pth_2sig_DEPENDENCIES) $(EXTRA_pth_2sig_DEPENDENCIES)
+ @rm -f pth_2sig$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(pth_2sig_OBJECTS) $(pth_2sig_LDADD) $(LIBS)
+
pth_atfork1$(EXEEXT): $(pth_atfork1_OBJECTS) $(pth_atfork1_DEPENDENCIES) $(EXTRA_pth_atfork1_DEPENDENCIES)
@rm -f pth_atfork1$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(pth_atfork1_OBJECTS) $(pth_atfork1_LDADD) $(LIBS)
@@ -1565,6 +1589,10 @@
@rm -f sigstackgrowth$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(sigstackgrowth_OBJECTS) $(sigstackgrowth_LDADD) $(LIBS)
+sigsusp$(EXEEXT): $(sigsusp_OBJECTS) $(sigsusp_DEPENDENCIES) $(EXTRA_sigsusp_DEPENDENCIES)
+ @rm -f sigsusp$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(sigsusp_OBJECTS) $(sigsusp_LDADD) $(LIBS)
+
stackgrowth$(EXEEXT): $(stackgrowth_OBJECTS) $(stackgrowth_DEPENDENCIES) $(EXTRA_stackgrowth_DEPENDENCIES)
@rm -f stackgrowth$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(stackgrowth_OBJECTS) $(stackgrowth_LDADD) $(LIBS)
@@ -1625,6 +1653,10 @@
@rm -f vgprintf$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(vgprintf_OBJECTS) $(vgprintf_LDADD) $(LIBS)
+vgprintf_nvalgrind$(EXEEXT): $(vgprintf_nvalgrind_OBJECTS) $(vgprintf_nvalgrind_DEPENDENCIES) $(EXTRA_vgprintf_nvalgrind_DEPENDENCIES)
+ @rm -f vgprintf_nvalgrind$(EXEEXT)
+ $(AM_V_CCLD)$(vgprintf_nvalgrind_LINK) $(vgprintf_nvalgrind_OBJECTS) $(vgprintf_nvalgrind_LDADD) $(LIBS)
+
mostlyclean-compile:
-rm -f *.$(OBJEXT)
@@ -1676,6 +1708,7 @@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/procfs-cmdline-exe.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pselect_alarm.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pselect_sigmask_null.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_2sig.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_atfork1.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_blockedsig.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_cancel1-pth_cancel1.Po@am__quote@
@@ -1703,6 +1736,7 @@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/shortpush.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/shorts.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sigstackgrowth.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sigsusp.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/stackgrowth.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/syscall-restart1.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/syscall-restart2.Po@am__quote@
@@ -1719,6 +1753,7 @@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/unit_debuglog.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/valgrind_cpp_test.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vgprintf.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vgprintf_nvalgrind-vgprintf.Po@am__quote@
.c.o:
@am__fastdepCC_TRUE@ $(AM_V_CC)depbase=`echo $@ | sed 's|[^/]*$$|$(DEPDIR)/&|;s|\.o$$||'`;\
@@ -1904,6 +1939,20 @@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tls_so_CFLAGS) $(CFLAGS) -c -o tls_so-tls_so.obj `if test -f 'tls_so.c'; then $(CYGPATH_W) 'tls_so.c'; else $(CYGPATH_W) '$(srcdir)/tls_so.c'; fi`
+vgprintf_nvalgrind-vgprintf.o: vgprintf.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vgprintf_nvalgrind_CFLAGS) $(CFLAGS) -MT vgprintf_nvalgrind-vgprintf.o -MD -MP -MF $(DEPDIR)/vgprintf_nvalgrind-vgprintf.Tpo -c -o vgprintf_nvalgrind-vgprintf.o `test -f 'vgprintf.c' || echo '$(srcdir)/'`vgprintf.c
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/vgprintf_nvalgrind-vgprintf.Tpo $(DEPDIR)/vgprintf_nvalgrind-vgprintf.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='vgprintf.c' object='vgprintf_nvalgrind-vgprintf.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vgprintf_nvalgrind_CFLAGS) $(CFLAGS) -c -o vgprintf_nvalgrind-vgprintf.o `test -f 'vgprintf.c' || echo '$(srcdir)/'`vgprintf.c
+
+vgprintf_nvalgrind-vgprintf.obj: vgprintf.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vgprintf_nvalgrind_CFLAGS) $(CFLAGS) -MT vgprintf_nvalgrind-vgprintf.obj -MD -MP -MF $(DEPDIR)/vgprintf_nvalgrind-vgprintf.Tpo -c -o vgprintf_nvalgrind-vgprintf.obj `if test -f 'vgprintf.c'; then $(CYGPATH_W) 'vgprintf.c'; else $(CYGPATH_W) '$(srcdir)/vgprintf.c'; fi`
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/vgprintf_nvalgrind-vgprintf.Tpo $(DEPDIR)/vgprintf_nvalgrind-vgprintf.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='vgprintf.c' object='vgprintf_nvalgrind-vgprintf.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vgprintf_nvalgrind_CFLAGS) $(CFLAGS) -c -o vgprintf_nvalgrind-vgprintf.obj `if test -f 'vgprintf.c'; then $(CYGPATH_W) 'vgprintf.c'; else $(CYGPATH_W) '$(srcdir)/vgprintf.c'; fi`
+
.cpp.o:
@am__fastdepCXX_TRUE@ $(AM_V_CXX)depbase=`echo $@ | sed 's|[^/]*$$|$(DEPDIR)/&|;s|\.o$$||'`;\
@am__fastdepCXX_TRUE@ $(CXXCOMPILE) -MT $@ -MD -MP -MF $$depbase.Tpo -c -o $@ $< &&\
diff --git a/none/tests/allexec_prepare_prereq b/none/tests/allexec_prepare_prereq
index 2c70a08..09958b5 100755
--- a/none/tests/allexec_prepare_prereq
+++ b/none/tests/allexec_prepare_prereq
@@ -33,6 +33,5 @@
pair s390x_unexisting_in_32bits s390x
pair arm arm64
pair mips32 mips64
-pair tilegx_unexisting_32bits tilegx
exit 0
diff --git a/none/tests/amd64-darwin/Makefile.am b/none/tests/amd64-darwin/Makefile.am
index b231b30..260221f 100644
--- a/none/tests/amd64-darwin/Makefile.am
+++ b/none/tests/amd64-darwin/Makefile.am
@@ -5,10 +5,12 @@
filter_stderr filter_minimal
EXTRA_DIST = \
- bug341419.vgtest bug341419.stderr.exp
+ bug341419.vgtest bug341419.stderr.exp \
+ cet_nops_gs.stderr.exp cet_nops_gs.stdout.exp cet_nops_gs.vgtest
check_PROGRAMS = \
- bug341419
+ bug341419 \
+ cet_nops_gs
AM_CFLAGS += @FLAG_M64@
AM_CXXFLAGS += @FLAG_M64@
diff --git a/none/tests/amd64-darwin/Makefile.in b/none/tests/amd64-darwin/Makefile.in
index b33185a..380ab58 100644
--- a/none/tests/amd64-darwin/Makefile.in
+++ b/none/tests/amd64-darwin/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -120,7 +120,7 @@
@COMPILER_IS_CLANG_TRUE@ -Wno-uninitialized -Wno-unused-value # \
@COMPILER_IS_CLANG_TRUE@ clang 3.0.0
@COMPILER_IS_CLANG_TRUE@am__append_7 = -Wno-unused-private-field # drd/tests/tsan_unittest.cpp
-check_PROGRAMS = bug341419$(EXEEXT)
+check_PROGRAMS = bug341419$(EXEEXT) cet_nops_gs$(EXEEXT)
subdir = none/tests/amd64-darwin
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/configure.ac
@@ -135,6 +135,9 @@
bug341419_SOURCES = bug341419.c
bug341419_OBJECTS = bug341419.$(OBJEXT)
bug341419_LDADD = $(LDADD)
+cet_nops_gs_SOURCES = cet_nops_gs.c
+cet_nops_gs_OBJECTS = cet_nops_gs.$(OBJEXT)
+cet_nops_gs_LDADD = $(LDADD)
SCRIPTS = $(dist_noinst_SCRIPTS)
AM_V_P = $(am__v_P_@AM_V@)
am__v_P_ = $(am__v_P_@AM_DEFAULT_V@)
@@ -164,8 +167,8 @@
am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@)
am__v_CCLD_0 = @echo " CCLD " $@;
am__v_CCLD_1 =
-SOURCES = bug341419.c
-DIST_SOURCES = bug341419.c
+SOURCES = bug341419.c cet_nops_gs.c
+DIST_SOURCES = bug341419.c cet_nops_gs.c
am__can_run_installinfo = \
case $$AM_UPDATE_INFO_DIR in \
n|no|NO) false;; \
@@ -237,6 +240,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -407,6 +411,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -417,6 +422,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -491,8 +497,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -537,7 +541,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
@@ -563,7 +566,8 @@
filter_stderr filter_minimal
EXTRA_DIST = \
- bug341419.vgtest bug341419.stderr.exp
+ bug341419.vgtest bug341419.stderr.exp \
+ cet_nops_gs.stderr.exp cet_nops_gs.stdout.exp cet_nops_gs.vgtest
all: all-am
@@ -607,6 +611,10 @@
@rm -f bug341419$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(bug341419_OBJECTS) $(bug341419_LDADD) $(LIBS)
+cet_nops_gs$(EXEEXT): $(cet_nops_gs_OBJECTS) $(cet_nops_gs_DEPENDENCIES) $(EXTRA_cet_nops_gs_DEPENDENCIES)
+ @rm -f cet_nops_gs$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(cet_nops_gs_OBJECTS) $(cet_nops_gs_LDADD) $(LIBS)
+
mostlyclean-compile:
-rm -f *.$(OBJEXT)
@@ -614,6 +622,7 @@
-rm -f *.tab.c
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug341419.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cet_nops_gs.Po@am__quote@
.c.o:
@am__fastdepCC_TRUE@ $(AM_V_CC)depbase=`echo $@ | sed 's|[^/]*$$|$(DEPDIR)/&|;s|\.o$$||'`;\
diff --git a/none/tests/amd64-darwin/cet_nops_gs.c b/none/tests/amd64-darwin/cet_nops_gs.c
new file mode 100644
index 0000000..c03f02c
--- /dev/null
+++ b/none/tests/amd64-darwin/cet_nops_gs.c
@@ -0,0 +1,311 @@
+#include <stdio.h>
+
+int main ()
+{
+ printf("start testing GS prefix ..\n");
+ fflush(stdout);
+
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
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+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+
+ printf ("done\n");
+ return 0;
+}
diff --git a/none/tests/amd64-darwin/cet_nops_gs.stderr.exp b/none/tests/amd64-darwin/cet_nops_gs.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/amd64-darwin/cet_nops_gs.stderr.exp
diff --git a/none/tests/amd64-darwin/cet_nops_gs.stdout.exp b/none/tests/amd64-darwin/cet_nops_gs.stdout.exp
new file mode 100644
index 0000000..b9673a7
--- /dev/null
+++ b/none/tests/amd64-darwin/cet_nops_gs.stdout.exp
@@ -0,0 +1,2 @@
+start testing GS prefix ..
+done
diff --git a/none/tests/amd64-darwin/cet_nops_gs.vgtest b/none/tests/amd64-darwin/cet_nops_gs.vgtest
new file mode 100644
index 0000000..085e266
--- /dev/null
+++ b/none/tests/amd64-darwin/cet_nops_gs.vgtest
@@ -0,0 +1,2 @@
+prog: cet_nops_gs
+vgopts: -q
diff --git a/none/tests/amd64-linux/Makefile.am b/none/tests/amd64-linux/Makefile.am
index 3e5a959..c3e217d 100644
--- a/none/tests/amd64-linux/Makefile.am
+++ b/none/tests/amd64-linux/Makefile.am
@@ -6,10 +6,15 @@
EXTRA_DIST = \
bug345887.stderr.exp bug345887.vgtest \
+ cet_nops_fs.stderr.exp cet_nops_fs.stdout.exp cet_nops_fs.vgtest \
+ cet_nops_gs.stderr.exp cet_nops_gs.stdout.exp cet_nops_gs.vgtest \
map_32bits.stderr.exp map_32bits.vgtest
check_PROGRAMS = \
- bug345887 map_32bits
+ bug345887 \
+ cet_nops_fs \
+ cet_nops_gs \
+ map_32bits
AM_CFLAGS += @FLAG_M64@
AM_CXXFLAGS += @FLAG_M64@
diff --git a/none/tests/amd64-linux/Makefile.in b/none/tests/amd64-linux/Makefile.in
index c25012b..afe3928 100644
--- a/none/tests/amd64-linux/Makefile.in
+++ b/none/tests/amd64-linux/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -120,7 +120,8 @@
@COMPILER_IS_CLANG_TRUE@ -Wno-uninitialized -Wno-unused-value # \
@COMPILER_IS_CLANG_TRUE@ clang 3.0.0
@COMPILER_IS_CLANG_TRUE@am__append_7 = -Wno-unused-private-field # drd/tests/tsan_unittest.cpp
-check_PROGRAMS = bug345887$(EXEEXT) map_32bits$(EXEEXT)
+check_PROGRAMS = bug345887$(EXEEXT) cet_nops_fs$(EXEEXT) \
+ cet_nops_gs$(EXEEXT) map_32bits$(EXEEXT)
subdir = none/tests/amd64-linux
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/configure.ac
@@ -135,6 +136,12 @@
bug345887_SOURCES = bug345887.c
bug345887_OBJECTS = bug345887.$(OBJEXT)
bug345887_LDADD = $(LDADD)
+cet_nops_fs_SOURCES = cet_nops_fs.c
+cet_nops_fs_OBJECTS = cet_nops_fs.$(OBJEXT)
+cet_nops_fs_LDADD = $(LDADD)
+cet_nops_gs_SOURCES = cet_nops_gs.c
+cet_nops_gs_OBJECTS = cet_nops_gs.$(OBJEXT)
+cet_nops_gs_LDADD = $(LDADD)
map_32bits_SOURCES = map_32bits.c
map_32bits_OBJECTS = map_32bits.$(OBJEXT)
map_32bits_LDADD = $(LDADD)
@@ -167,8 +174,8 @@
am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@)
am__v_CCLD_0 = @echo " CCLD " $@;
am__v_CCLD_1 =
-SOURCES = bug345887.c map_32bits.c
-DIST_SOURCES = bug345887.c map_32bits.c
+SOURCES = bug345887.c cet_nops_fs.c cet_nops_gs.c map_32bits.c
+DIST_SOURCES = bug345887.c cet_nops_fs.c cet_nops_gs.c map_32bits.c
am__can_run_installinfo = \
case $$AM_UPDATE_INFO_DIR in \
n|no|NO) false;; \
@@ -240,6 +247,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -410,6 +418,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -420,6 +429,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -494,8 +504,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -540,7 +548,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
@@ -567,6 +574,8 @@
EXTRA_DIST = \
bug345887.stderr.exp bug345887.vgtest \
+ cet_nops_fs.stderr.exp cet_nops_fs.stdout.exp cet_nops_fs.vgtest \
+ cet_nops_gs.stderr.exp cet_nops_gs.stdout.exp cet_nops_gs.vgtest \
map_32bits.stderr.exp map_32bits.vgtest
all: all-am
@@ -611,6 +620,14 @@
@rm -f bug345887$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(bug345887_OBJECTS) $(bug345887_LDADD) $(LIBS)
+cet_nops_fs$(EXEEXT): $(cet_nops_fs_OBJECTS) $(cet_nops_fs_DEPENDENCIES) $(EXTRA_cet_nops_fs_DEPENDENCIES)
+ @rm -f cet_nops_fs$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(cet_nops_fs_OBJECTS) $(cet_nops_fs_LDADD) $(LIBS)
+
+cet_nops_gs$(EXEEXT): $(cet_nops_gs_OBJECTS) $(cet_nops_gs_DEPENDENCIES) $(EXTRA_cet_nops_gs_DEPENDENCIES)
+ @rm -f cet_nops_gs$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(cet_nops_gs_OBJECTS) $(cet_nops_gs_LDADD) $(LIBS)
+
map_32bits$(EXEEXT): $(map_32bits_OBJECTS) $(map_32bits_DEPENDENCIES) $(EXTRA_map_32bits_DEPENDENCIES)
@rm -f map_32bits$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(map_32bits_OBJECTS) $(map_32bits_LDADD) $(LIBS)
@@ -622,6 +639,8 @@
-rm -f *.tab.c
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug345887.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cet_nops_fs.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cet_nops_gs.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/map_32bits.Po@am__quote@
.c.o:
diff --git a/none/tests/amd64-linux/cet_nops_fs.c b/none/tests/amd64-linux/cet_nops_fs.c
new file mode 100644
index 0000000..70645f7
--- /dev/null
+++ b/none/tests/amd64-linux/cet_nops_fs.c
@@ -0,0 +1,311 @@
+#include <stdio.h>
+
+int main ()
+{
+ printf("start testing FS prefix ..\n");
+ fflush(stdout);
+
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+
+ printf ("done\n");
+ return 0;
+}
diff --git a/none/tests/amd64-linux/cet_nops_fs.stderr.exp b/none/tests/amd64-linux/cet_nops_fs.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/amd64-linux/cet_nops_fs.stderr.exp
diff --git a/none/tests/amd64-linux/cet_nops_fs.stdout.exp b/none/tests/amd64-linux/cet_nops_fs.stdout.exp
new file mode 100644
index 0000000..909e188
--- /dev/null
+++ b/none/tests/amd64-linux/cet_nops_fs.stdout.exp
@@ -0,0 +1,2 @@
+start testing FS prefix ..
+done
diff --git a/none/tests/amd64-linux/cet_nops_fs.vgtest b/none/tests/amd64-linux/cet_nops_fs.vgtest
new file mode 100644
index 0000000..8681e9a
--- /dev/null
+++ b/none/tests/amd64-linux/cet_nops_fs.vgtest
@@ -0,0 +1,2 @@
+prog: cet_nops_fs
+vgopts: -q
diff --git a/none/tests/amd64-linux/cet_nops_gs.c b/none/tests/amd64-linux/cet_nops_gs.c
new file mode 100644
index 0000000..c03f02c
--- /dev/null
+++ b/none/tests/amd64-linux/cet_nops_gs.c
@@ -0,0 +1,311 @@
+#include <stdio.h>
+
+int main ()
+{
+ printf("start testing GS prefix ..\n");
+ fflush(stdout);
+
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+
+ printf ("done\n");
+ return 0;
+}
diff --git a/none/tests/amd64-linux/cet_nops_gs.stderr.exp b/none/tests/amd64-linux/cet_nops_gs.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/amd64-linux/cet_nops_gs.stderr.exp
diff --git a/none/tests/amd64-linux/cet_nops_gs.stdout.exp b/none/tests/amd64-linux/cet_nops_gs.stdout.exp
new file mode 100644
index 0000000..b9673a7
--- /dev/null
+++ b/none/tests/amd64-linux/cet_nops_gs.stdout.exp
@@ -0,0 +1,2 @@
+start testing GS prefix ..
+done
diff --git a/none/tests/amd64-linux/cet_nops_gs.vgtest b/none/tests/amd64-linux/cet_nops_gs.vgtest
new file mode 100644
index 0000000..085e266
--- /dev/null
+++ b/none/tests/amd64-linux/cet_nops_gs.vgtest
@@ -0,0 +1,2 @@
+prog: cet_nops_gs
+vgopts: -q
diff --git a/none/tests/amd64-solaris/Makefile.am b/none/tests/amd64-solaris/Makefile.am
index 3830fbe..0f5d80a 100644
--- a/none/tests/amd64-solaris/Makefile.am
+++ b/none/tests/amd64-solaris/Makefile.am
@@ -7,6 +7,7 @@
filter_stderr
EXTRA_DIST = \
+ cet_nops_fs.stderr.exp cet_nops_fs.stdout.exp cet_nops_fs.vgtest \
coredump_single_thread.post.exp coredump_single_thread.stderr.exp \
coredump_single_thread.stdout.exp coredump_single_thread.vgtest \
coredump_single_thread_sse.post.exp coredump_single_thread_sse.stderr.exp \
@@ -14,6 +15,7 @@
syscall_return_args.stderr.exp syscall_return_args.vgtest
check_PROGRAMS = \
+ cet_nops_fs \
coredump_single_thread \
coredump_single_thread_sse \
syscall_return_args
diff --git a/none/tests/amd64-solaris/Makefile.in b/none/tests/amd64-solaris/Makefile.in
index 31cd83d..4a855e9 100644
--- a/none/tests/amd64-solaris/Makefile.in
+++ b/none/tests/amd64-solaris/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -120,7 +120,7 @@
@COMPILER_IS_CLANG_TRUE@ -Wno-uninitialized -Wno-unused-value # \
@COMPILER_IS_CLANG_TRUE@ clang 3.0.0
@COMPILER_IS_CLANG_TRUE@am__append_7 = -Wno-unused-private-field # drd/tests/tsan_unittest.cpp
-check_PROGRAMS = coredump_single_thread$(EXEEXT) \
+check_PROGRAMS = cet_nops_fs$(EXEEXT) coredump_single_thread$(EXEEXT) \
coredump_single_thread_sse$(EXEEXT) \
syscall_return_args$(EXEEXT)
subdir = none/tests/amd64-solaris
@@ -134,6 +134,9 @@
CONFIG_HEADER = $(top_builddir)/config.h
CONFIG_CLEAN_FILES =
CONFIG_CLEAN_VPATH_FILES =
+cet_nops_fs_SOURCES = cet_nops_fs.c
+cet_nops_fs_OBJECTS = cet_nops_fs.$(OBJEXT)
+cet_nops_fs_LDADD = $(LDADD)
coredump_single_thread_SOURCES = coredump_single_thread.c
coredump_single_thread_OBJECTS = coredump_single_thread.$(OBJEXT)
coredump_single_thread_LDADD = $(LDADD)
@@ -173,10 +176,10 @@
am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@)
am__v_CCLD_0 = @echo " CCLD " $@;
am__v_CCLD_1 =
-SOURCES = coredump_single_thread.c coredump_single_thread_sse.c \
- syscall_return_args.c
-DIST_SOURCES = coredump_single_thread.c coredump_single_thread_sse.c \
- syscall_return_args.c
+SOURCES = cet_nops_fs.c coredump_single_thread.c \
+ coredump_single_thread_sse.c syscall_return_args.c
+DIST_SOURCES = cet_nops_fs.c coredump_single_thread.c \
+ coredump_single_thread_sse.c syscall_return_args.c
am__can_run_installinfo = \
case $$AM_UPDATE_INFO_DIR in \
n|no|NO) false;; \
@@ -248,6 +251,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -418,6 +422,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -428,6 +433,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -502,8 +508,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -548,7 +552,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
@@ -576,6 +579,7 @@
filter_stderr
EXTRA_DIST = \
+ cet_nops_fs.stderr.exp cet_nops_fs.stdout.exp cet_nops_fs.vgtest \
coredump_single_thread.post.exp coredump_single_thread.stderr.exp \
coredump_single_thread.stdout.exp coredump_single_thread.vgtest \
coredump_single_thread_sse.post.exp coredump_single_thread_sse.stderr.exp \
@@ -620,6 +624,10 @@
clean-checkPROGRAMS:
-test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+cet_nops_fs$(EXEEXT): $(cet_nops_fs_OBJECTS) $(cet_nops_fs_DEPENDENCIES) $(EXTRA_cet_nops_fs_DEPENDENCIES)
+ @rm -f cet_nops_fs$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(cet_nops_fs_OBJECTS) $(cet_nops_fs_LDADD) $(LIBS)
+
coredump_single_thread$(EXEEXT): $(coredump_single_thread_OBJECTS) $(coredump_single_thread_DEPENDENCIES) $(EXTRA_coredump_single_thread_DEPENDENCIES)
@rm -f coredump_single_thread$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(coredump_single_thread_OBJECTS) $(coredump_single_thread_LDADD) $(LIBS)
@@ -638,6 +646,7 @@
distclean-compile:
-rm -f *.tab.c
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cet_nops_fs.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coredump_single_thread.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coredump_single_thread_sse.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/syscall_return_args.Po@am__quote@
diff --git a/none/tests/amd64-solaris/cet_nops_fs.c b/none/tests/amd64-solaris/cet_nops_fs.c
new file mode 100644
index 0000000..70645f7
--- /dev/null
+++ b/none/tests/amd64-solaris/cet_nops_fs.c
@@ -0,0 +1,311 @@
+#include <stdio.h>
+
+int main ()
+{
+ printf("start testing FS prefix ..\n");
+ fflush(stdout);
+
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+
+ printf ("done\n");
+ return 0;
+}
diff --git a/none/tests/amd64-solaris/cet_nops_fs.stderr.exp b/none/tests/amd64-solaris/cet_nops_fs.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/amd64-solaris/cet_nops_fs.stderr.exp
diff --git a/none/tests/amd64-solaris/cet_nops_fs.stdout.exp b/none/tests/amd64-solaris/cet_nops_fs.stdout.exp
new file mode 100644
index 0000000..909e188
--- /dev/null
+++ b/none/tests/amd64-solaris/cet_nops_fs.stdout.exp
@@ -0,0 +1,2 @@
+start testing FS prefix ..
+done
diff --git a/none/tests/amd64-solaris/cet_nops_fs.vgtest b/none/tests/amd64-solaris/cet_nops_fs.vgtest
new file mode 100644
index 0000000..8681e9a
--- /dev/null
+++ b/none/tests/amd64-solaris/cet_nops_fs.vgtest
@@ -0,0 +1,2 @@
+prog: cet_nops_fs
+vgopts: -q
diff --git a/none/tests/amd64/Makefile.am b/none/tests/amd64/Makefile.am
index f0cd081..e5a0e7e 100644
--- a/none/tests/amd64/Makefile.am
+++ b/none/tests/amd64/Makefile.am
@@ -27,6 +27,7 @@
avx2-1.vgtest avx2-1.stdout.exp avx2-1.stderr.exp \
asorep.stderr.exp asorep.stdout.exp asorep.vgtest \
bmi.stderr.exp bmi.stdout.exp bmi.vgtest \
+ bt_flags.stderr.exp bt_flags.stdout.exp bt_flags.vgtest \
fma.stderr.exp fma.stdout.exp fma.vgtest \
bug127521-64.vgtest bug127521-64.stdout.exp bug127521-64.stderr.exp \
bug132813-amd64.vgtest bug132813-amd64.stdout.exp \
@@ -37,10 +38,14 @@
bug132918.stdout.exp-older-glibc \
bug156404-amd64.vgtest bug156404-amd64.stdout.exp \
bug156404-amd64.stderr.exp \
+ cet_nops.vgtest cet_nops.stdout.exp cet_nops.stderr.exp \
clc.vgtest clc.stdout.exp clc.stderr.exp \
crc32.vgtest crc32.stdout.exp crc32.stderr.exp \
cmpxchg.vgtest cmpxchg.stdout.exp cmpxchg.stderr.exp \
faultstatus.disabled faultstatus.stderr.exp \
+ fb_test_amd64.vgtest \
+ fb_test_amd64.stderr.exp fb_test_amd64.stdout.exp \
+ fb_test_amd64.h fb_test_amd64_muldiv.h fb_test_amd64_shift.h \
fcmovnu.vgtest fcmovnu.stderr.exp fcmovnu.stdout.exp \
fma4.vgtest fma4.stdout.exp fma4.stderr.exp \
fxtract.vgtest fxtract.stderr.exp fxtract.stdout.exp \
@@ -90,7 +95,9 @@
check_PROGRAMS = \
allexec \
amd64locked \
+ bt_flags \
bug127521-64 bug132813-amd64 bug132918 bug137714-amd64 \
+ cet_nops \
clc \
cmpxchg \
getseg \
@@ -106,6 +113,9 @@
if BUILD_ADDR32_TESTS
check_PROGRAMS += asorep
endif
+if BUILD_ADX_TESTS
+ check_PROGRAMS += fb_test_amd64
+endif
if BUILD_AVX_TESTS
if BUILD_VPCLMULQDQ_TESTS
check_PROGRAMS += avx-1
@@ -172,7 +182,11 @@
# generic C ones
amd64locked_CFLAGS = $(AM_CFLAGS) -O
bug132918_LDADD = -lm
-fxtract_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_OVERFLOW@
+cmpxchg_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
+fb_test_amd64_CFLAGS = $(AM_CFLAGS) -O -fno-strict-aliasing
+fb_test_amd64_LDADD = -lm
+fcmovnu_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
+fxtract_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_OVERFLOW@ @FLAG_NO_PIE@
insn_basic_SOURCES = insn_basic.def
insn_basic_LDADD = -lm
insn_mmx_SOURCES = insn_mmx.def
@@ -194,6 +208,10 @@
fma4_CFLAGS += -D__EXTENSIONS__
endif
fma4_LDADD = -lm
+jrcxz_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
+looper_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
+sbbmisc_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
+shrld_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
.def.c: $(srcdir)/gen_insn_test.pl
$(PERL) $(srcdir)/gen_insn_test.pl < $< > $@
diff --git a/none/tests/amd64/Makefile.in b/none/tests/amd64/Makefile.in
index 7ebb77f..d2dc09f 100644
--- a/none/tests/amd64/Makefile.in
+++ b/none/tests/amd64/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -124,8 +124,9 @@
@BUILD_SSSE3_TESTS_TRUE@am__append_9 = insn_ssse3
@BUILD_PCLMULQDQ_TESTS_TRUE@am__append_10 = insn_pclmulqdq
check_PROGRAMS = allexec$(EXEEXT) amd64locked$(EXEEXT) \
- bug127521-64$(EXEEXT) bug132813-amd64$(EXEEXT) \
- bug132918$(EXEEXT) bug137714-amd64$(EXEEXT) clc$(EXEEXT) \
+ bt_flags$(EXEEXT) bug127521-64$(EXEEXT) \
+ bug132813-amd64$(EXEEXT) bug132918$(EXEEXT) \
+ bug137714-amd64$(EXEEXT) cet_nops$(EXEEXT) clc$(EXEEXT) \
cmpxchg$(EXEEXT) getseg$(EXEEXT) $(am__EXEEXT_4) \
nan80and64$(EXEEXT) rcl-amd64$(EXEEXT) redundantRexW$(EXEEXT) \
smc1$(EXEEXT) sbbmisc$(EXEEXT) nibz_bennee_mmap$(EXEEXT) \
@@ -134,25 +135,26 @@
$(am__EXEEXT_9) $(am__EXEEXT_10) $(am__EXEEXT_11) \
$(am__EXEEXT_12) $(am__EXEEXT_13) $(am__EXEEXT_14) \
$(am__EXEEXT_15) $(am__EXEEXT_16) $(am__EXEEXT_17) \
- $(am__EXEEXT_18)
+ $(am__EXEEXT_18) $(am__EXEEXT_19)
@BUILD_ADDR32_TESTS_TRUE@am__append_11 = asorep
-@BUILD_AVX_TESTS_TRUE@@BUILD_VPCLMULQDQ_TESTS_TRUE@am__append_12 = avx-1
-@BUILD_AVX_TESTS_TRUE@@BUILD_FMA4_TESTS_TRUE@am__append_13 = fma4
-@BUILD_AVX2_TESTS_TRUE@@COMPILER_IS_ICC_FALSE@am__append_14 = avx2-1
-@BUILD_SSSE3_TESTS_TRUE@am__append_15 = ssse3_misaligned
-@BUILD_LZCNT_TESTS_TRUE@am__append_16 = lzcnt64
-@BUILD_MOVBE_TESTS_TRUE@am__append_17 = movbe
-@BUILD_SSE42_TESTS_TRUE@am__append_18 = \
+@BUILD_ADX_TESTS_TRUE@am__append_12 = fb_test_amd64
+@BUILD_AVX_TESTS_TRUE@@BUILD_VPCLMULQDQ_TESTS_TRUE@am__append_13 = avx-1
+@BUILD_AVX_TESTS_TRUE@@BUILD_FMA4_TESTS_TRUE@am__append_14 = fma4
+@BUILD_AVX2_TESTS_TRUE@@COMPILER_IS_ICC_FALSE@am__append_15 = avx2-1
+@BUILD_SSSE3_TESTS_TRUE@am__append_16 = ssse3_misaligned
+@BUILD_LZCNT_TESTS_TRUE@am__append_17 = lzcnt64
+@BUILD_MOVBE_TESTS_TRUE@am__append_18 = movbe
+@BUILD_SSE42_TESTS_TRUE@am__append_19 = \
@BUILD_SSE42_TESTS_TRUE@ pcmpstr64 pcmpxstrx64 sse4-64 crc32 aes \
@BUILD_SSE42_TESTS_TRUE@ pcmpstr64w pcmpxstrx64w
-@BUILD_TSX_TESTS_TRUE@am__append_19 = tm1 xacq_xrel
-@BUILD_BMI_TESTS_TRUE@am__append_20 = bmi
-@BUILD_FMA_TESTS_TRUE@am__append_21 = fma
-@BUILD_MPX_TESTS_TRUE@am__append_22 = mpx
+@BUILD_TSX_TESTS_TRUE@am__append_20 = tm1 xacq_xrel
+@BUILD_BMI_TESTS_TRUE@am__append_21 = bmi
+@BUILD_FMA_TESTS_TRUE@am__append_22 = fma
+@BUILD_MPX_TESTS_TRUE@am__append_23 = mpx
# DDD: these need to be made to work on Darwin like the x86/ ones were.
-@VGCONF_OS_IS_DARWIN_FALSE@am__append_23 = \
+@VGCONF_OS_IS_DARWIN_FALSE@am__append_24 = \
@VGCONF_OS_IS_DARWIN_FALSE@ bug156404-amd64 \
@VGCONF_OS_IS_DARWIN_FALSE@ faultstatus \
@VGCONF_OS_IS_DARWIN_FALSE@ fcmovnu \
@@ -162,8 +164,8 @@
@VGCONF_OS_IS_DARWIN_FALSE@ shrld \
@VGCONF_OS_IS_DARWIN_FALSE@ slahf-amd64
-@BUILD_LOOPNEL_TESTS_TRUE@@VGCONF_OS_IS_DARWIN_FALSE@am__append_24 = loopnel
-@VGCONF_OS_IS_SOLARIS_TRUE@am__append_25 = -D__EXTENSIONS__
+@BUILD_LOOPNEL_TESTS_TRUE@@VGCONF_OS_IS_DARWIN_FALSE@am__append_25 = loopnel
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_26 = -D__EXTENSIONS__
subdir = none/tests/amd64
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/configure.ac
@@ -182,29 +184,30 @@
insn_sse2$(EXEEXT) insn_fpu$(EXEEXT) $(am__EXEEXT_1) \
$(am__EXEEXT_2) $(am__EXEEXT_3)
@BUILD_ADDR32_TESTS_TRUE@am__EXEEXT_5 = asorep$(EXEEXT)
-@BUILD_AVX_TESTS_TRUE@@BUILD_VPCLMULQDQ_TESTS_TRUE@am__EXEEXT_6 = avx-1$(EXEEXT)
-@BUILD_AVX_TESTS_TRUE@@BUILD_FMA4_TESTS_TRUE@am__EXEEXT_7 = \
+@BUILD_ADX_TESTS_TRUE@am__EXEEXT_6 = fb_test_amd64$(EXEEXT)
+@BUILD_AVX_TESTS_TRUE@@BUILD_VPCLMULQDQ_TESTS_TRUE@am__EXEEXT_7 = avx-1$(EXEEXT)
+@BUILD_AVX_TESTS_TRUE@@BUILD_FMA4_TESTS_TRUE@am__EXEEXT_8 = \
@BUILD_AVX_TESTS_TRUE@@BUILD_FMA4_TESTS_TRUE@ fma4$(EXEEXT)
-@BUILD_AVX2_TESTS_TRUE@@COMPILER_IS_ICC_FALSE@am__EXEEXT_8 = \
+@BUILD_AVX2_TESTS_TRUE@@COMPILER_IS_ICC_FALSE@am__EXEEXT_9 = \
@BUILD_AVX2_TESTS_TRUE@@COMPILER_IS_ICC_FALSE@ avx2-1$(EXEEXT)
-@BUILD_SSSE3_TESTS_TRUE@am__EXEEXT_9 = ssse3_misaligned$(EXEEXT)
-@BUILD_LZCNT_TESTS_TRUE@am__EXEEXT_10 = lzcnt64$(EXEEXT)
-@BUILD_MOVBE_TESTS_TRUE@am__EXEEXT_11 = movbe$(EXEEXT)
-@BUILD_SSE42_TESTS_TRUE@am__EXEEXT_12 = pcmpstr64$(EXEEXT) \
+@BUILD_SSSE3_TESTS_TRUE@am__EXEEXT_10 = ssse3_misaligned$(EXEEXT)
+@BUILD_LZCNT_TESTS_TRUE@am__EXEEXT_11 = lzcnt64$(EXEEXT)
+@BUILD_MOVBE_TESTS_TRUE@am__EXEEXT_12 = movbe$(EXEEXT)
+@BUILD_SSE42_TESTS_TRUE@am__EXEEXT_13 = pcmpstr64$(EXEEXT) \
@BUILD_SSE42_TESTS_TRUE@ pcmpxstrx64$(EXEEXT) sse4-64$(EXEEXT) \
@BUILD_SSE42_TESTS_TRUE@ crc32$(EXEEXT) aes$(EXEEXT) \
@BUILD_SSE42_TESTS_TRUE@ pcmpstr64w$(EXEEXT) \
@BUILD_SSE42_TESTS_TRUE@ pcmpxstrx64w$(EXEEXT)
-@BUILD_TSX_TESTS_TRUE@am__EXEEXT_13 = tm1$(EXEEXT) xacq_xrel$(EXEEXT)
-@BUILD_BMI_TESTS_TRUE@am__EXEEXT_14 = bmi$(EXEEXT)
-@BUILD_FMA_TESTS_TRUE@am__EXEEXT_15 = fma$(EXEEXT)
-@BUILD_MPX_TESTS_TRUE@am__EXEEXT_16 = mpx$(EXEEXT)
-@VGCONF_OS_IS_DARWIN_FALSE@am__EXEEXT_17 = bug156404-amd64$(EXEEXT) \
+@BUILD_TSX_TESTS_TRUE@am__EXEEXT_14 = tm1$(EXEEXT) xacq_xrel$(EXEEXT)
+@BUILD_BMI_TESTS_TRUE@am__EXEEXT_15 = bmi$(EXEEXT)
+@BUILD_FMA_TESTS_TRUE@am__EXEEXT_16 = fma$(EXEEXT)
+@BUILD_MPX_TESTS_TRUE@am__EXEEXT_17 = mpx$(EXEEXT)
+@VGCONF_OS_IS_DARWIN_FALSE@am__EXEEXT_18 = bug156404-amd64$(EXEEXT) \
@VGCONF_OS_IS_DARWIN_FALSE@ faultstatus$(EXEEXT) \
@VGCONF_OS_IS_DARWIN_FALSE@ fcmovnu$(EXEEXT) fxtract$(EXEEXT) \
@VGCONF_OS_IS_DARWIN_FALSE@ looper$(EXEEXT) jrcxz$(EXEEXT) \
@VGCONF_OS_IS_DARWIN_FALSE@ shrld$(EXEEXT) slahf-amd64$(EXEEXT)
-@BUILD_LOOPNEL_TESTS_TRUE@@VGCONF_OS_IS_DARWIN_FALSE@am__EXEEXT_18 = loopnel$(EXEEXT)
+@BUILD_LOOPNEL_TESTS_TRUE@@VGCONF_OS_IS_DARWIN_FALSE@am__EXEEXT_19 = loopnel$(EXEEXT)
aes_SOURCES = aes.c
aes_OBJECTS = aes.$(OBJEXT)
aes_LDADD = $(LDADD)
@@ -230,6 +233,9 @@
bmi_SOURCES = bmi.c
bmi_OBJECTS = bmi.$(OBJEXT)
bmi_LDADD = $(LDADD)
+bt_flags_SOURCES = bt_flags.c
+bt_flags_OBJECTS = bt_flags.$(OBJEXT)
+bt_flags_LDADD = $(LDADD)
bug127521_64_SOURCES = bug127521-64.c
bug127521_64_OBJECTS = bug127521-64.$(OBJEXT)
bug127521_64_LDADD = $(LDADD)
@@ -245,21 +251,33 @@
bug156404_amd64_SOURCES = bug156404-amd64.c
bug156404_amd64_OBJECTS = bug156404-amd64.$(OBJEXT)
bug156404_amd64_LDADD = $(LDADD)
+cet_nops_SOURCES = cet_nops.c
+cet_nops_OBJECTS = cet_nops.$(OBJEXT)
+cet_nops_LDADD = $(LDADD)
clc_SOURCES = clc.c
clc_OBJECTS = clc.$(OBJEXT)
clc_LDADD = $(LDADD)
cmpxchg_SOURCES = cmpxchg.c
-cmpxchg_OBJECTS = cmpxchg.$(OBJEXT)
+cmpxchg_OBJECTS = cmpxchg-cmpxchg.$(OBJEXT)
cmpxchg_LDADD = $(LDADD)
+cmpxchg_LINK = $(CCLD) $(cmpxchg_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
crc32_SOURCES = crc32.c
crc32_OBJECTS = crc32.$(OBJEXT)
crc32_LDADD = $(LDADD)
faultstatus_SOURCES = faultstatus.c
faultstatus_OBJECTS = faultstatus.$(OBJEXT)
faultstatus_LDADD = $(LDADD)
+fb_test_amd64_SOURCES = fb_test_amd64.c
+fb_test_amd64_OBJECTS = fb_test_amd64-fb_test_amd64.$(OBJEXT)
+fb_test_amd64_DEPENDENCIES =
+fb_test_amd64_LINK = $(CCLD) $(fb_test_amd64_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
fcmovnu_SOURCES = fcmovnu.c
-fcmovnu_OBJECTS = fcmovnu.$(OBJEXT)
+fcmovnu_OBJECTS = fcmovnu-fcmovnu.$(OBJEXT)
fcmovnu_LDADD = $(LDADD)
+fcmovnu_LINK = $(CCLD) $(fcmovnu_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
fma_SOURCES = fma.c
fma_OBJECTS = fma.$(OBJEXT)
fma_LDADD = $(LDADD)
@@ -301,11 +319,15 @@
insn_ssse3_OBJECTS = $(am_insn_ssse3_OBJECTS)
insn_ssse3_DEPENDENCIES =
jrcxz_SOURCES = jrcxz.c
-jrcxz_OBJECTS = jrcxz.$(OBJEXT)
+jrcxz_OBJECTS = jrcxz-jrcxz.$(OBJEXT)
jrcxz_LDADD = $(LDADD)
+jrcxz_LINK = $(CCLD) $(jrcxz_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
looper_SOURCES = looper.c
-looper_OBJECTS = looper.$(OBJEXT)
+looper_OBJECTS = looper-looper.$(OBJEXT)
looper_LDADD = $(LDADD)
+looper_LINK = $(CCLD) $(looper_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
loopnel_SOURCES = loopnel.c
loopnel_OBJECTS = loopnel.$(OBJEXT)
loopnel_LDADD = $(LDADD)
@@ -343,11 +365,15 @@
redundantRexW_OBJECTS = redundantRexW.$(OBJEXT)
redundantRexW_LDADD = $(LDADD)
sbbmisc_SOURCES = sbbmisc.c
-sbbmisc_OBJECTS = sbbmisc.$(OBJEXT)
+sbbmisc_OBJECTS = sbbmisc-sbbmisc.$(OBJEXT)
sbbmisc_LDADD = $(LDADD)
+sbbmisc_LINK = $(CCLD) $(sbbmisc_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
shrld_SOURCES = shrld.c
-shrld_OBJECTS = shrld.$(OBJEXT)
+shrld_OBJECTS = shrld-shrld.$(OBJEXT)
shrld_LDADD = $(LDADD)
+shrld_LINK = $(CCLD) $(shrld_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
slahf_amd64_SOURCES = slahf-amd64.c
slahf_amd64_OBJECTS = slahf-amd64.$(OBJEXT)
slahf_amd64_LDADD = $(LDADD)
@@ -406,12 +432,12 @@
am__v_CCLD_0 = @echo " CCLD " $@;
am__v_CCLD_1 =
SOURCES = aes.c allexec.c amd64locked.c asorep.c avx-1.c avx2-1.c \
- bmi.c bug127521-64.c bug132813-amd64.c bug132918.c \
- bug137714-amd64.c bug156404-amd64.c clc.c cmpxchg.c crc32.c \
- faultstatus.c fcmovnu.c fma.c fma4.c fxtract.c getseg.c \
- $(insn_basic_SOURCES) $(insn_fpu_SOURCES) $(insn_mmx_SOURCES) \
- $(insn_pclmulqdq_SOURCES) $(insn_sse_SOURCES) \
- $(insn_sse2_SOURCES) $(insn_sse3_SOURCES) \
+ bmi.c bt_flags.c bug127521-64.c bug132813-amd64.c bug132918.c \
+ bug137714-amd64.c bug156404-amd64.c cet_nops.c clc.c cmpxchg.c \
+ crc32.c faultstatus.c fb_test_amd64.c fcmovnu.c fma.c fma4.c \
+ fxtract.c getseg.c $(insn_basic_SOURCES) $(insn_fpu_SOURCES) \
+ $(insn_mmx_SOURCES) $(insn_pclmulqdq_SOURCES) \
+ $(insn_sse_SOURCES) $(insn_sse2_SOURCES) $(insn_sse3_SOURCES) \
$(insn_ssse3_SOURCES) jrcxz.c looper.c loopnel.c lzcnt64.c \
movbe.c mpx.c nan80and64.c nibz_bennee_mmap.c pcmpstr64.c \
pcmpstr64w.c pcmpxstrx64.c pcmpxstrx64w.c rcl-amd64.c \
@@ -419,12 +445,12 @@
sse4-64.c ssse3_misaligned.c tm1.c x87trigOOR.c xacq_xrel.c \
xadd.c
DIST_SOURCES = aes.c allexec.c amd64locked.c asorep.c avx-1.c avx2-1.c \
- bmi.c bug127521-64.c bug132813-amd64.c bug132918.c \
- bug137714-amd64.c bug156404-amd64.c clc.c cmpxchg.c crc32.c \
- faultstatus.c fcmovnu.c fma.c fma4.c fxtract.c getseg.c \
- $(insn_basic_SOURCES) $(insn_fpu_SOURCES) $(insn_mmx_SOURCES) \
- $(insn_pclmulqdq_SOURCES) $(insn_sse_SOURCES) \
- $(insn_sse2_SOURCES) $(insn_sse3_SOURCES) \
+ bmi.c bt_flags.c bug127521-64.c bug132813-amd64.c bug132918.c \
+ bug137714-amd64.c bug156404-amd64.c cet_nops.c clc.c cmpxchg.c \
+ crc32.c faultstatus.c fb_test_amd64.c fcmovnu.c fma.c fma4.c \
+ fxtract.c getseg.c $(insn_basic_SOURCES) $(insn_fpu_SOURCES) \
+ $(insn_mmx_SOURCES) $(insn_pclmulqdq_SOURCES) \
+ $(insn_sse_SOURCES) $(insn_sse2_SOURCES) $(insn_sse3_SOURCES) \
$(insn_ssse3_SOURCES) jrcxz.c looper.c loopnel.c lzcnt64.c \
movbe.c mpx.c nan80and64.c nibz_bennee_mmap.c pcmpstr64.c \
pcmpstr64w.c pcmpxstrx64.c pcmpxstrx64w.c rcl-amd64.c \
@@ -502,6 +528,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -672,6 +699,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -682,6 +710,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -756,8 +785,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -802,7 +829,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
@@ -839,6 +865,7 @@
avx2-1.vgtest avx2-1.stdout.exp avx2-1.stderr.exp \
asorep.stderr.exp asorep.stdout.exp asorep.vgtest \
bmi.stderr.exp bmi.stdout.exp bmi.vgtest \
+ bt_flags.stderr.exp bt_flags.stdout.exp bt_flags.vgtest \
fma.stderr.exp fma.stdout.exp fma.vgtest \
bug127521-64.vgtest bug127521-64.stdout.exp bug127521-64.stderr.exp \
bug132813-amd64.vgtest bug132813-amd64.stdout.exp \
@@ -849,10 +876,14 @@
bug132918.stdout.exp-older-glibc \
bug156404-amd64.vgtest bug156404-amd64.stdout.exp \
bug156404-amd64.stderr.exp \
+ cet_nops.vgtest cet_nops.stdout.exp cet_nops.stderr.exp \
clc.vgtest clc.stdout.exp clc.stderr.exp \
crc32.vgtest crc32.stdout.exp crc32.stderr.exp \
cmpxchg.vgtest cmpxchg.stdout.exp cmpxchg.stderr.exp \
faultstatus.disabled faultstatus.stderr.exp \
+ fb_test_amd64.vgtest \
+ fb_test_amd64.stderr.exp fb_test_amd64.stdout.exp \
+ fb_test_amd64.h fb_test_amd64_muldiv.h fb_test_amd64_shift.h \
fcmovnu.vgtest fcmovnu.stderr.exp fcmovnu.stdout.exp \
fma4.vgtest fma4.stdout.exp fma4.stderr.exp \
fxtract.vgtest fxtract.stderr.exp fxtract.stdout.exp \
@@ -904,7 +935,11 @@
# generic C ones
amd64locked_CFLAGS = $(AM_CFLAGS) -O
bug132918_LDADD = -lm
-fxtract_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_OVERFLOW@
+cmpxchg_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
+fb_test_amd64_CFLAGS = $(AM_CFLAGS) -O -fno-strict-aliasing
+fb_test_amd64_LDADD = -lm
+fcmovnu_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
+fxtract_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_OVERFLOW@ @FLAG_NO_PIE@
insn_basic_SOURCES = insn_basic.def
insn_basic_LDADD = -lm
insn_mmx_SOURCES = insn_mmx.def
@@ -921,8 +956,12 @@
insn_fpu_LDADD = -lm
insn_pclmulqdq_SOURCES = insn_pclmulqdq.def
fxtract_LDADD = -lm
-fma4_CFLAGS = $(AM_CFLAGS) -std=c99 $(am__append_25)
+fma4_CFLAGS = $(AM_CFLAGS) -std=c99 $(am__append_26)
fma4_LDADD = -lm
+jrcxz_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
+looper_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
+sbbmisc_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
+shrld_CFLAGS = $(AM_CFLAGS) @FLAG_NO_PIE@
all: all-am
.SUFFIXES:
@@ -989,6 +1028,10 @@
@rm -f bmi$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(bmi_OBJECTS) $(bmi_LDADD) $(LIBS)
+bt_flags$(EXEEXT): $(bt_flags_OBJECTS) $(bt_flags_DEPENDENCIES) $(EXTRA_bt_flags_DEPENDENCIES)
+ @rm -f bt_flags$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(bt_flags_OBJECTS) $(bt_flags_LDADD) $(LIBS)
+
bug127521-64$(EXEEXT): $(bug127521_64_OBJECTS) $(bug127521_64_DEPENDENCIES) $(EXTRA_bug127521_64_DEPENDENCIES)
@rm -f bug127521-64$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(bug127521_64_OBJECTS) $(bug127521_64_LDADD) $(LIBS)
@@ -1009,13 +1052,17 @@
@rm -f bug156404-amd64$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(bug156404_amd64_OBJECTS) $(bug156404_amd64_LDADD) $(LIBS)
+cet_nops$(EXEEXT): $(cet_nops_OBJECTS) $(cet_nops_DEPENDENCIES) $(EXTRA_cet_nops_DEPENDENCIES)
+ @rm -f cet_nops$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(cet_nops_OBJECTS) $(cet_nops_LDADD) $(LIBS)
+
clc$(EXEEXT): $(clc_OBJECTS) $(clc_DEPENDENCIES) $(EXTRA_clc_DEPENDENCIES)
@rm -f clc$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(clc_OBJECTS) $(clc_LDADD) $(LIBS)
cmpxchg$(EXEEXT): $(cmpxchg_OBJECTS) $(cmpxchg_DEPENDENCIES) $(EXTRA_cmpxchg_DEPENDENCIES)
@rm -f cmpxchg$(EXEEXT)
- $(AM_V_CCLD)$(LINK) $(cmpxchg_OBJECTS) $(cmpxchg_LDADD) $(LIBS)
+ $(AM_V_CCLD)$(cmpxchg_LINK) $(cmpxchg_OBJECTS) $(cmpxchg_LDADD) $(LIBS)
crc32$(EXEEXT): $(crc32_OBJECTS) $(crc32_DEPENDENCIES) $(EXTRA_crc32_DEPENDENCIES)
@rm -f crc32$(EXEEXT)
@@ -1025,9 +1072,13 @@
@rm -f faultstatus$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(faultstatus_OBJECTS) $(faultstatus_LDADD) $(LIBS)
+fb_test_amd64$(EXEEXT): $(fb_test_amd64_OBJECTS) $(fb_test_amd64_DEPENDENCIES) $(EXTRA_fb_test_amd64_DEPENDENCIES)
+ @rm -f fb_test_amd64$(EXEEXT)
+ $(AM_V_CCLD)$(fb_test_amd64_LINK) $(fb_test_amd64_OBJECTS) $(fb_test_amd64_LDADD) $(LIBS)
+
fcmovnu$(EXEEXT): $(fcmovnu_OBJECTS) $(fcmovnu_DEPENDENCIES) $(EXTRA_fcmovnu_DEPENDENCIES)
@rm -f fcmovnu$(EXEEXT)
- $(AM_V_CCLD)$(LINK) $(fcmovnu_OBJECTS) $(fcmovnu_LDADD) $(LIBS)
+ $(AM_V_CCLD)$(fcmovnu_LINK) $(fcmovnu_OBJECTS) $(fcmovnu_LDADD) $(LIBS)
fma$(EXEEXT): $(fma_OBJECTS) $(fma_DEPENDENCIES) $(EXTRA_fma_DEPENDENCIES)
@rm -f fma$(EXEEXT)
@@ -1079,11 +1130,11 @@
jrcxz$(EXEEXT): $(jrcxz_OBJECTS) $(jrcxz_DEPENDENCIES) $(EXTRA_jrcxz_DEPENDENCIES)
@rm -f jrcxz$(EXEEXT)
- $(AM_V_CCLD)$(LINK) $(jrcxz_OBJECTS) $(jrcxz_LDADD) $(LIBS)
+ $(AM_V_CCLD)$(jrcxz_LINK) $(jrcxz_OBJECTS) $(jrcxz_LDADD) $(LIBS)
looper$(EXEEXT): $(looper_OBJECTS) $(looper_DEPENDENCIES) $(EXTRA_looper_DEPENDENCIES)
@rm -f looper$(EXEEXT)
- $(AM_V_CCLD)$(LINK) $(looper_OBJECTS) $(looper_LDADD) $(LIBS)
+ $(AM_V_CCLD)$(looper_LINK) $(looper_OBJECTS) $(looper_LDADD) $(LIBS)
loopnel$(EXEEXT): $(loopnel_OBJECTS) $(loopnel_DEPENDENCIES) $(EXTRA_loopnel_DEPENDENCIES)
@rm -f loopnel$(EXEEXT)
@@ -1135,11 +1186,11 @@
sbbmisc$(EXEEXT): $(sbbmisc_OBJECTS) $(sbbmisc_DEPENDENCIES) $(EXTRA_sbbmisc_DEPENDENCIES)
@rm -f sbbmisc$(EXEEXT)
- $(AM_V_CCLD)$(LINK) $(sbbmisc_OBJECTS) $(sbbmisc_LDADD) $(LIBS)
+ $(AM_V_CCLD)$(sbbmisc_LINK) $(sbbmisc_OBJECTS) $(sbbmisc_LDADD) $(LIBS)
shrld$(EXEEXT): $(shrld_OBJECTS) $(shrld_DEPENDENCIES) $(EXTRA_shrld_DEPENDENCIES)
@rm -f shrld$(EXEEXT)
- $(AM_V_CCLD)$(LINK) $(shrld_OBJECTS) $(shrld_LDADD) $(LIBS)
+ $(AM_V_CCLD)$(shrld_LINK) $(shrld_OBJECTS) $(shrld_LDADD) $(LIBS)
slahf-amd64$(EXEEXT): $(slahf_amd64_OBJECTS) $(slahf_amd64_DEPENDENCIES) $(EXTRA_slahf_amd64_DEPENDENCIES)
@rm -f slahf-amd64$(EXEEXT)
@@ -1186,16 +1237,19 @@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/avx-1.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/avx2-1.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bmi.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bt_flags.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug127521-64.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug132813-amd64.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug132918.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug137714-amd64.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug156404-amd64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cet_nops.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/clc.Po@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cmpxchg.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cmpxchg-cmpxchg.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/crc32.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/faultstatus.Po@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fcmovnu.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fb_test_amd64-fb_test_amd64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fcmovnu-fcmovnu.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fma.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fma4-fma4.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fxtract-fxtract.Po@am__quote@
@@ -1208,8 +1262,8 @@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_sse2.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_sse3.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_ssse3.Po@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/jrcxz.Po@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/looper.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/jrcxz-jrcxz.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/looper-looper.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/loopnel.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/lzcnt64.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/movbe.Po@am__quote@
@@ -1222,8 +1276,8 @@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pcmpxstrx64w.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rcl-amd64.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/redundantRexW.Po@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sbbmisc.Po@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/shrld.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sbbmisc-sbbmisc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/shrld-shrld.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/slahf-amd64.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/smc1.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sse4-64.Po@am__quote@
@@ -1277,6 +1331,48 @@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(amd64locked_CFLAGS) $(CFLAGS) -c -o amd64locked-amd64locked.obj `if test -f 'amd64locked.c'; then $(CYGPATH_W) 'amd64locked.c'; else $(CYGPATH_W) '$(srcdir)/amd64locked.c'; fi`
+cmpxchg-cmpxchg.o: cmpxchg.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(cmpxchg_CFLAGS) $(CFLAGS) -MT cmpxchg-cmpxchg.o -MD -MP -MF $(DEPDIR)/cmpxchg-cmpxchg.Tpo -c -o cmpxchg-cmpxchg.o `test -f 'cmpxchg.c' || echo '$(srcdir)/'`cmpxchg.c
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/cmpxchg-cmpxchg.Tpo $(DEPDIR)/cmpxchg-cmpxchg.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='cmpxchg.c' object='cmpxchg-cmpxchg.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(cmpxchg_CFLAGS) $(CFLAGS) -c -o cmpxchg-cmpxchg.o `test -f 'cmpxchg.c' || echo '$(srcdir)/'`cmpxchg.c
+
+cmpxchg-cmpxchg.obj: cmpxchg.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(cmpxchg_CFLAGS) $(CFLAGS) -MT cmpxchg-cmpxchg.obj -MD -MP -MF $(DEPDIR)/cmpxchg-cmpxchg.Tpo -c -o cmpxchg-cmpxchg.obj `if test -f 'cmpxchg.c'; then $(CYGPATH_W) 'cmpxchg.c'; else $(CYGPATH_W) '$(srcdir)/cmpxchg.c'; fi`
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/cmpxchg-cmpxchg.Tpo $(DEPDIR)/cmpxchg-cmpxchg.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='cmpxchg.c' object='cmpxchg-cmpxchg.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(cmpxchg_CFLAGS) $(CFLAGS) -c -o cmpxchg-cmpxchg.obj `if test -f 'cmpxchg.c'; then $(CYGPATH_W) 'cmpxchg.c'; else $(CYGPATH_W) '$(srcdir)/cmpxchg.c'; fi`
+
+fb_test_amd64-fb_test_amd64.o: fb_test_amd64.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fb_test_amd64_CFLAGS) $(CFLAGS) -MT fb_test_amd64-fb_test_amd64.o -MD -MP -MF $(DEPDIR)/fb_test_amd64-fb_test_amd64.Tpo -c -o fb_test_amd64-fb_test_amd64.o `test -f 'fb_test_amd64.c' || echo '$(srcdir)/'`fb_test_amd64.c
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/fb_test_amd64-fb_test_amd64.Tpo $(DEPDIR)/fb_test_amd64-fb_test_amd64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='fb_test_amd64.c' object='fb_test_amd64-fb_test_amd64.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fb_test_amd64_CFLAGS) $(CFLAGS) -c -o fb_test_amd64-fb_test_amd64.o `test -f 'fb_test_amd64.c' || echo '$(srcdir)/'`fb_test_amd64.c
+
+fb_test_amd64-fb_test_amd64.obj: fb_test_amd64.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fb_test_amd64_CFLAGS) $(CFLAGS) -MT fb_test_amd64-fb_test_amd64.obj -MD -MP -MF $(DEPDIR)/fb_test_amd64-fb_test_amd64.Tpo -c -o fb_test_amd64-fb_test_amd64.obj `if test -f 'fb_test_amd64.c'; then $(CYGPATH_W) 'fb_test_amd64.c'; else $(CYGPATH_W) '$(srcdir)/fb_test_amd64.c'; fi`
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/fb_test_amd64-fb_test_amd64.Tpo $(DEPDIR)/fb_test_amd64-fb_test_amd64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='fb_test_amd64.c' object='fb_test_amd64-fb_test_amd64.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fb_test_amd64_CFLAGS) $(CFLAGS) -c -o fb_test_amd64-fb_test_amd64.obj `if test -f 'fb_test_amd64.c'; then $(CYGPATH_W) 'fb_test_amd64.c'; else $(CYGPATH_W) '$(srcdir)/fb_test_amd64.c'; fi`
+
+fcmovnu-fcmovnu.o: fcmovnu.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fcmovnu_CFLAGS) $(CFLAGS) -MT fcmovnu-fcmovnu.o -MD -MP -MF $(DEPDIR)/fcmovnu-fcmovnu.Tpo -c -o fcmovnu-fcmovnu.o `test -f 'fcmovnu.c' || echo '$(srcdir)/'`fcmovnu.c
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/fcmovnu-fcmovnu.Tpo $(DEPDIR)/fcmovnu-fcmovnu.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='fcmovnu.c' object='fcmovnu-fcmovnu.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fcmovnu_CFLAGS) $(CFLAGS) -c -o fcmovnu-fcmovnu.o `test -f 'fcmovnu.c' || echo '$(srcdir)/'`fcmovnu.c
+
+fcmovnu-fcmovnu.obj: fcmovnu.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fcmovnu_CFLAGS) $(CFLAGS) -MT fcmovnu-fcmovnu.obj -MD -MP -MF $(DEPDIR)/fcmovnu-fcmovnu.Tpo -c -o fcmovnu-fcmovnu.obj `if test -f 'fcmovnu.c'; then $(CYGPATH_W) 'fcmovnu.c'; else $(CYGPATH_W) '$(srcdir)/fcmovnu.c'; fi`
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/fcmovnu-fcmovnu.Tpo $(DEPDIR)/fcmovnu-fcmovnu.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='fcmovnu.c' object='fcmovnu-fcmovnu.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fcmovnu_CFLAGS) $(CFLAGS) -c -o fcmovnu-fcmovnu.obj `if test -f 'fcmovnu.c'; then $(CYGPATH_W) 'fcmovnu.c'; else $(CYGPATH_W) '$(srcdir)/fcmovnu.c'; fi`
+
fma4-fma4.o: fma4.c
@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fma4_CFLAGS) $(CFLAGS) -MT fma4-fma4.o -MD -MP -MF $(DEPDIR)/fma4-fma4.Tpo -c -o fma4-fma4.o `test -f 'fma4.c' || echo '$(srcdir)/'`fma4.c
@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/fma4-fma4.Tpo $(DEPDIR)/fma4-fma4.Po
@@ -1305,6 +1401,62 @@
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tags: tags-am
diff --git a/none/tests/amd64/bt_flags.c b/none/tests/amd64/bt_flags.c
new file mode 100644
index 0000000..2991783
--- /dev/null
+++ b/none/tests/amd64/bt_flags.c
@@ -0,0 +1,88 @@
+
+#include <stdio.h>
+#include <string.h>
+
+typedef unsigned long long int ULong;
+typedef unsigned int UInt;
+
+#define CC_SHIFT_O 11
+#define CC_SHIFT_S 7
+#define CC_SHIFT_Z 6
+#define CC_SHIFT_A 4
+#define CC_SHIFT_C 0
+#define CC_SHIFT_P 2
+
+#define CC_MASK_O (1ULL << CC_SHIFT_O)
+#define CC_MASK_S (1ULL << CC_SHIFT_S)
+#define CC_MASK_Z (1ULL << CC_SHIFT_Z)
+#define CC_MASK_A (1ULL << CC_SHIFT_A)
+#define CC_MASK_C (1ULL << CC_SHIFT_C)
+#define CC_MASK_P (1ULL << CC_SHIFT_P)
+
+#define CC_MASK_OSZACP \
+ (CC_MASK_O | CC_MASK_S | CC_MASK_Z | CC_MASK_A | CC_MASK_C | CC_MASK_P)
+
+
+void showFlags(/*OUT*/char* str, int nStr, ULong flags)
+{
+ // Ignore everything except OSZACP, because V differs from real h/w in
+ // flags other than OSZACP, and we don't want that to confuse the
+ // results here
+ memset(str, 0, nStr);
+ sprintf(str, "%c%c%c%c%c%c",
+ (flags & CC_MASK_O) ? 'o' : '-',
+ (flags & CC_MASK_S) ? 's' : '-',
+ (flags & CC_MASK_Z) ? 'z' : '-',
+ (flags & CC_MASK_A) ? 'a' : '-',
+ (flags & CC_MASK_C) ? 'c' : '-',
+ (flags & CC_MASK_P) ? 'p' : '-');
+}
+
+__attribute__((noinline))
+void do_test ( ULong val, UInt ix )
+{
+ ULong o, s, z, a, c, p, flags_before;
+ for (o = 0; o < 2; o++) {
+ for (s = 0; s < 2; s++) {
+ for (z = 0; z < 2; z++) {
+ for (a = 0; a < 2; a++) {
+ for (c = 0; c < 2; c++) {
+ for (p = 0; p < 2; p++) {
+ flags_before = (o ? CC_MASK_O : 0)
+ | (s ? CC_MASK_S : 0)
+ | (z ? CC_MASK_Z : 0)
+ | (a ? CC_MASK_A : 0)
+ | (c ? CC_MASK_C : 0)
+ | (p ? CC_MASK_P : 0);
+ ULong block[4] = { flags_before, val, ix, 0 };
+ __asm__ __volatile__(
+ "movq 0(%0), %%r15" "\n\t" // flags_before
+ "pushq %%r15" "\n\t"
+ "popfq" "\n\t"
+ "movq 8(%0), %%r14" "\n\t" // val
+ "movq 16(%0), %%r13" "\n\t" // ix
+ "bt %%r13, %%r14" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%r15" "\n\t"
+ "movq %%r15, 24(%0)" "\n" // block[3]
+ : : "r"(&block[0]) : "cc","memory","r13","r14","r15"
+ );
+ ULong flags_after = block[3];
+ flags_after &= CC_MASK_OSZACP;
+ char flags_after_str[100];
+ char flags_before_str[100];
+ showFlags(flags_before_str, 100, flags_before);
+ showFlags(flags_after_str, 100, flags_after);
+ printf("flags 0x%03llx(%s) val 0x%llx ix %d -> flags 0x%03llx(%s)\n",
+ flags_before, flags_before_str, val, ix,
+ flags_after, flags_after_str);
+ }}}}}}
+}
+
+int main ( void )
+{
+ do_test(0x8000, 14); // should always return C == 0
+ printf("\n");
+ do_test(0x8000, 15); // should always return C == 1
+ return 0;
+}
diff --git a/none/tests/amd64/bt_flags.stderr.exp b/none/tests/amd64/bt_flags.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/none/tests/amd64/bt_flags.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/none/tests/amd64/bt_flags.stdout.exp b/none/tests/amd64/bt_flags.stdout.exp
new file mode 100644
index 0000000..5139f9a
--- /dev/null
+++ b/none/tests/amd64/bt_flags.stdout.exp
@@ -0,0 +1,129 @@
+flags 0x000(------) val 0x8000 ix 14 -> flags 0x000(------)
+flags 0x004(-----p) val 0x8000 ix 14 -> flags 0x004(-----p)
+flags 0x001(----c-) val 0x8000 ix 14 -> flags 0x000(------)
+flags 0x005(----cp) val 0x8000 ix 14 -> flags 0x004(-----p)
+flags 0x010(---a--) val 0x8000 ix 14 -> flags 0x010(---a--)
+flags 0x014(---a-p) val 0x8000 ix 14 -> flags 0x014(---a-p)
+flags 0x011(---ac-) val 0x8000 ix 14 -> flags 0x010(---a--)
+flags 0x015(---acp) val 0x8000 ix 14 -> flags 0x014(---a-p)
+flags 0x040(--z---) val 0x8000 ix 14 -> flags 0x040(--z---)
+flags 0x044(--z--p) val 0x8000 ix 14 -> flags 0x044(--z--p)
+flags 0x041(--z-c-) val 0x8000 ix 14 -> flags 0x040(--z---)
+flags 0x045(--z-cp) val 0x8000 ix 14 -> flags 0x044(--z--p)
+flags 0x050(--za--) val 0x8000 ix 14 -> flags 0x050(--za--)
+flags 0x054(--za-p) val 0x8000 ix 14 -> flags 0x054(--za-p)
+flags 0x051(--zac-) val 0x8000 ix 14 -> flags 0x050(--za--)
+flags 0x055(--zacp) val 0x8000 ix 14 -> flags 0x054(--za-p)
+flags 0x080(-s----) val 0x8000 ix 14 -> flags 0x080(-s----)
+flags 0x084(-s---p) val 0x8000 ix 14 -> flags 0x084(-s---p)
+flags 0x081(-s--c-) val 0x8000 ix 14 -> flags 0x080(-s----)
+flags 0x085(-s--cp) val 0x8000 ix 14 -> flags 0x084(-s---p)
+flags 0x090(-s-a--) val 0x8000 ix 14 -> flags 0x090(-s-a--)
+flags 0x094(-s-a-p) val 0x8000 ix 14 -> flags 0x094(-s-a-p)
+flags 0x091(-s-ac-) val 0x8000 ix 14 -> flags 0x090(-s-a--)
+flags 0x095(-s-acp) val 0x8000 ix 14 -> flags 0x094(-s-a-p)
+flags 0x0c0(-sz---) val 0x8000 ix 14 -> flags 0x0c0(-sz---)
+flags 0x0c4(-sz--p) val 0x8000 ix 14 -> flags 0x0c4(-sz--p)
+flags 0x0c1(-sz-c-) val 0x8000 ix 14 -> flags 0x0c0(-sz---)
+flags 0x0c5(-sz-cp) val 0x8000 ix 14 -> flags 0x0c4(-sz--p)
+flags 0x0d0(-sza--) val 0x8000 ix 14 -> flags 0x0d0(-sza--)
+flags 0x0d4(-sza-p) val 0x8000 ix 14 -> flags 0x0d4(-sza-p)
+flags 0x0d1(-szac-) val 0x8000 ix 14 -> flags 0x0d0(-sza--)
+flags 0x0d5(-szacp) val 0x8000 ix 14 -> flags 0x0d4(-sza-p)
+flags 0x800(o-----) val 0x8000 ix 14 -> flags 0x800(o-----)
+flags 0x804(o----p) val 0x8000 ix 14 -> flags 0x804(o----p)
+flags 0x801(o---c-) val 0x8000 ix 14 -> flags 0x800(o-----)
+flags 0x805(o---cp) val 0x8000 ix 14 -> flags 0x804(o----p)
+flags 0x810(o--a--) val 0x8000 ix 14 -> flags 0x810(o--a--)
+flags 0x814(o--a-p) val 0x8000 ix 14 -> flags 0x814(o--a-p)
+flags 0x811(o--ac-) val 0x8000 ix 14 -> flags 0x810(o--a--)
+flags 0x815(o--acp) val 0x8000 ix 14 -> flags 0x814(o--a-p)
+flags 0x840(o-z---) val 0x8000 ix 14 -> flags 0x840(o-z---)
+flags 0x844(o-z--p) val 0x8000 ix 14 -> flags 0x844(o-z--p)
+flags 0x841(o-z-c-) val 0x8000 ix 14 -> flags 0x840(o-z---)
+flags 0x845(o-z-cp) val 0x8000 ix 14 -> flags 0x844(o-z--p)
+flags 0x850(o-za--) val 0x8000 ix 14 -> flags 0x850(o-za--)
+flags 0x854(o-za-p) val 0x8000 ix 14 -> flags 0x854(o-za-p)
+flags 0x851(o-zac-) val 0x8000 ix 14 -> flags 0x850(o-za--)
+flags 0x855(o-zacp) val 0x8000 ix 14 -> flags 0x854(o-za-p)
+flags 0x880(os----) val 0x8000 ix 14 -> flags 0x880(os----)
+flags 0x884(os---p) val 0x8000 ix 14 -> flags 0x884(os---p)
+flags 0x881(os--c-) val 0x8000 ix 14 -> flags 0x880(os----)
+flags 0x885(os--cp) val 0x8000 ix 14 -> flags 0x884(os---p)
+flags 0x890(os-a--) val 0x8000 ix 14 -> flags 0x890(os-a--)
+flags 0x894(os-a-p) val 0x8000 ix 14 -> flags 0x894(os-a-p)
+flags 0x891(os-ac-) val 0x8000 ix 14 -> flags 0x890(os-a--)
+flags 0x895(os-acp) val 0x8000 ix 14 -> flags 0x894(os-a-p)
+flags 0x8c0(osz---) val 0x8000 ix 14 -> flags 0x8c0(osz---)
+flags 0x8c4(osz--p) val 0x8000 ix 14 -> flags 0x8c4(osz--p)
+flags 0x8c1(osz-c-) val 0x8000 ix 14 -> flags 0x8c0(osz---)
+flags 0x8c5(osz-cp) val 0x8000 ix 14 -> flags 0x8c4(osz--p)
+flags 0x8d0(osza--) val 0x8000 ix 14 -> flags 0x8d0(osza--)
+flags 0x8d4(osza-p) val 0x8000 ix 14 -> flags 0x8d4(osza-p)
+flags 0x8d1(oszac-) val 0x8000 ix 14 -> flags 0x8d0(osza--)
+flags 0x8d5(oszacp) val 0x8000 ix 14 -> flags 0x8d4(osza-p)
+
+flags 0x000(------) val 0x8000 ix 15 -> flags 0x001(----c-)
+flags 0x004(-----p) val 0x8000 ix 15 -> flags 0x005(----cp)
+flags 0x001(----c-) val 0x8000 ix 15 -> flags 0x001(----c-)
+flags 0x005(----cp) val 0x8000 ix 15 -> flags 0x005(----cp)
+flags 0x010(---a--) val 0x8000 ix 15 -> flags 0x011(---ac-)
+flags 0x014(---a-p) val 0x8000 ix 15 -> flags 0x015(---acp)
+flags 0x011(---ac-) val 0x8000 ix 15 -> flags 0x011(---ac-)
+flags 0x015(---acp) val 0x8000 ix 15 -> flags 0x015(---acp)
+flags 0x040(--z---) val 0x8000 ix 15 -> flags 0x041(--z-c-)
+flags 0x044(--z--p) val 0x8000 ix 15 -> flags 0x045(--z-cp)
+flags 0x041(--z-c-) val 0x8000 ix 15 -> flags 0x041(--z-c-)
+flags 0x045(--z-cp) val 0x8000 ix 15 -> flags 0x045(--z-cp)
+flags 0x050(--za--) val 0x8000 ix 15 -> flags 0x051(--zac-)
+flags 0x054(--za-p) val 0x8000 ix 15 -> flags 0x055(--zacp)
+flags 0x051(--zac-) val 0x8000 ix 15 -> flags 0x051(--zac-)
+flags 0x055(--zacp) val 0x8000 ix 15 -> flags 0x055(--zacp)
+flags 0x080(-s----) val 0x8000 ix 15 -> flags 0x081(-s--c-)
+flags 0x084(-s---p) val 0x8000 ix 15 -> flags 0x085(-s--cp)
+flags 0x081(-s--c-) val 0x8000 ix 15 -> flags 0x081(-s--c-)
+flags 0x085(-s--cp) val 0x8000 ix 15 -> flags 0x085(-s--cp)
+flags 0x090(-s-a--) val 0x8000 ix 15 -> flags 0x091(-s-ac-)
+flags 0x094(-s-a-p) val 0x8000 ix 15 -> flags 0x095(-s-acp)
+flags 0x091(-s-ac-) val 0x8000 ix 15 -> flags 0x091(-s-ac-)
+flags 0x095(-s-acp) val 0x8000 ix 15 -> flags 0x095(-s-acp)
+flags 0x0c0(-sz---) val 0x8000 ix 15 -> flags 0x0c1(-sz-c-)
+flags 0x0c4(-sz--p) val 0x8000 ix 15 -> flags 0x0c5(-sz-cp)
+flags 0x0c1(-sz-c-) val 0x8000 ix 15 -> flags 0x0c1(-sz-c-)
+flags 0x0c5(-sz-cp) val 0x8000 ix 15 -> flags 0x0c5(-sz-cp)
+flags 0x0d0(-sza--) val 0x8000 ix 15 -> flags 0x0d1(-szac-)
+flags 0x0d4(-sza-p) val 0x8000 ix 15 -> flags 0x0d5(-szacp)
+flags 0x0d1(-szac-) val 0x8000 ix 15 -> flags 0x0d1(-szac-)
+flags 0x0d5(-szacp) val 0x8000 ix 15 -> flags 0x0d5(-szacp)
+flags 0x800(o-----) val 0x8000 ix 15 -> flags 0x801(o---c-)
+flags 0x804(o----p) val 0x8000 ix 15 -> flags 0x805(o---cp)
+flags 0x801(o---c-) val 0x8000 ix 15 -> flags 0x801(o---c-)
+flags 0x805(o---cp) val 0x8000 ix 15 -> flags 0x805(o---cp)
+flags 0x810(o--a--) val 0x8000 ix 15 -> flags 0x811(o--ac-)
+flags 0x814(o--a-p) val 0x8000 ix 15 -> flags 0x815(o--acp)
+flags 0x811(o--ac-) val 0x8000 ix 15 -> flags 0x811(o--ac-)
+flags 0x815(o--acp) val 0x8000 ix 15 -> flags 0x815(o--acp)
+flags 0x840(o-z---) val 0x8000 ix 15 -> flags 0x841(o-z-c-)
+flags 0x844(o-z--p) val 0x8000 ix 15 -> flags 0x845(o-z-cp)
+flags 0x841(o-z-c-) val 0x8000 ix 15 -> flags 0x841(o-z-c-)
+flags 0x845(o-z-cp) val 0x8000 ix 15 -> flags 0x845(o-z-cp)
+flags 0x850(o-za--) val 0x8000 ix 15 -> flags 0x851(o-zac-)
+flags 0x854(o-za-p) val 0x8000 ix 15 -> flags 0x855(o-zacp)
+flags 0x851(o-zac-) val 0x8000 ix 15 -> flags 0x851(o-zac-)
+flags 0x855(o-zacp) val 0x8000 ix 15 -> flags 0x855(o-zacp)
+flags 0x880(os----) val 0x8000 ix 15 -> flags 0x881(os--c-)
+flags 0x884(os---p) val 0x8000 ix 15 -> flags 0x885(os--cp)
+flags 0x881(os--c-) val 0x8000 ix 15 -> flags 0x881(os--c-)
+flags 0x885(os--cp) val 0x8000 ix 15 -> flags 0x885(os--cp)
+flags 0x890(os-a--) val 0x8000 ix 15 -> flags 0x891(os-ac-)
+flags 0x894(os-a-p) val 0x8000 ix 15 -> flags 0x895(os-acp)
+flags 0x891(os-ac-) val 0x8000 ix 15 -> flags 0x891(os-ac-)
+flags 0x895(os-acp) val 0x8000 ix 15 -> flags 0x895(os-acp)
+flags 0x8c0(osz---) val 0x8000 ix 15 -> flags 0x8c1(osz-c-)
+flags 0x8c4(osz--p) val 0x8000 ix 15 -> flags 0x8c5(osz-cp)
+flags 0x8c1(osz-c-) val 0x8000 ix 15 -> flags 0x8c1(osz-c-)
+flags 0x8c5(osz-cp) val 0x8000 ix 15 -> flags 0x8c5(osz-cp)
+flags 0x8d0(osza--) val 0x8000 ix 15 -> flags 0x8d1(oszac-)
+flags 0x8d4(osza-p) val 0x8000 ix 15 -> flags 0x8d5(oszacp)
+flags 0x8d1(oszac-) val 0x8000 ix 15 -> flags 0x8d1(oszac-)
+flags 0x8d5(oszacp) val 0x8000 ix 15 -> flags 0x8d5(oszacp)
diff --git a/none/tests/amd64/bt_flags.vgtest b/none/tests/amd64/bt_flags.vgtest
new file mode 100644
index 0000000..d5f14c1
--- /dev/null
+++ b/none/tests/amd64/bt_flags.vgtest
@@ -0,0 +1 @@
+prog: bt_flags
diff --git a/none/tests/amd64/bug132918.c b/none/tests/amd64/bug132918.c
index 77eefd0..c2cdb4d 100644
--- a/none/tests/amd64/bug132918.c
+++ b/none/tests/amd64/bug132918.c
@@ -24,8 +24,8 @@
"fnstsw %%ax\n\t"
"movq %%rax,%0\n\t"
"movq %%r15,%%rax"
- : /*out*/ "=r" (c3210)
- : /*in*/ "m" (f64), "m" (xx), "m" (yy)
+ : /*out*/ "=r" (c3210), "=m" (f64)
+ : /*in*/ "m" (xx), "m" (yy)
: /*trash*/ "r15", "rax", "%st", "%st(1)", "cc"
);
res->d = f64;
diff --git a/none/tests/amd64/cet_nops.c b/none/tests/amd64/cet_nops.c
new file mode 100644
index 0000000..7f1644e
--- /dev/null
+++ b/none/tests/amd64/cet_nops.c
@@ -0,0 +1,1511 @@
+#include <stdio.h>
+
+int main ()
+{
+ printf("start doing absolutely nothing without fs and gs prefixes ..\n");
+ fflush(stdout);
+__asm__ __volatile__ (".byte 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1f, 0xff" :::"cc","memory");
+
+ printf ("done\n");
+ return 0;
+}
diff --git a/none/tests/amd64/cet_nops.stderr.exp b/none/tests/amd64/cet_nops.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/amd64/cet_nops.stderr.exp
diff --git a/none/tests/amd64/cet_nops.stdout.exp b/none/tests/amd64/cet_nops.stdout.exp
new file mode 100644
index 0000000..7186474
--- /dev/null
+++ b/none/tests/amd64/cet_nops.stdout.exp
@@ -0,0 +1,2 @@
+start doing absolutely nothing without fs and gs prefixes ..
+done
diff --git a/none/tests/amd64/cet_nops.vgtest b/none/tests/amd64/cet_nops.vgtest
new file mode 100644
index 0000000..025eefe
--- /dev/null
+++ b/none/tests/amd64/cet_nops.vgtest
@@ -0,0 +1,2 @@
+prog: cet_nops
+vgopts: -q
diff --git a/none/tests/amd64/fb_test_amd64.c b/none/tests/amd64/fb_test_amd64.c
new file mode 100644
index 0000000..f4b06e6
--- /dev/null
+++ b/none/tests/amd64/fb_test_amd64.c
@@ -0,0 +1,1234 @@
+
+/* Contrary to what the next comment says, this is now an amd64 CPU
+ test. */
+
+/*
+ * x86 CPU test
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <inttypes.h>
+#include <math.h>
+#include <stdarg.h>
+#include <assert.h>
+
+
+//////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////
+
+/*
+ * This is an OpenSSL-compatible implementation of the RSA Data Security, Inc.
+ * MD5 Message-Digest Algorithm (RFC 1321).
+ *
+ * Homepage:
+ * http://openwall.info/wiki/people/solar/software/public-domain-source-code/md5
+ *
+ * Author:
+ * Alexander Peslyak, better known as Solar Designer <solar at openwall.com>
+ *
+ * This software was written by Alexander Peslyak in 2001. No copyright is
+ * claimed, and the software is hereby placed in the public domain.
+ * In case this attempt to disclaim copyright and place the software in the
+ * public domain is deemed null and void, then the software is
+ * Copyright (c) 2001 Alexander Peslyak and it is hereby released to the
+ * general public under the following terms:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted.
+ *
+ * There's ABSOLUTELY NO WARRANTY, express or implied.
+ *
+ * (This is a heavily cut-down "BSD license".)
+ *
+ * This differs from Colin Plumb's older public domain implementation in that
+ * no exactly 32-bit integer data type is required (any 32-bit or wider
+ * unsigned integer data type will do), there's no compile-time endianness
+ * configuration, and the function prototypes match OpenSSL's. No code from
+ * Colin Plumb's implementation has been reused; this comment merely compares
+ * the properties of the two independent implementations.
+ *
+ * The primary goals of this implementation are portability and ease of use.
+ * It is meant to be fast, but not as fast as possible. Some known
+ * optimizations are not included to reduce source code size and avoid
+ * compile-time configuration.
+ */
+
+#include <string.h>
+
+// BEGIN #include "md5.h"
+/* Any 32-bit or wider unsigned integer data type will do */
+typedef unsigned int MD5_u32plus;
+
+typedef struct {
+ MD5_u32plus lo, hi;
+ MD5_u32plus a, b, c, d;
+ unsigned char buffer[64];
+ MD5_u32plus block[16];
+} MD5_CTX;
+
+void MD5_Init(MD5_CTX *ctx);
+void MD5_Update(MD5_CTX *ctx, const void *data, unsigned long size);
+void MD5_Final(unsigned char *result, MD5_CTX *ctx);
+// END #include "md5.h"
+
+/*
+ * The basic MD5 functions.
+ *
+ * F and G are optimized compared to their RFC 1321 definitions for
+ * architectures that lack an AND-NOT instruction, just like in Colin Plumb's
+ * implementation.
+ */
+#define F(x, y, z) ((z) ^ ((x) & ((y) ^ (z))))
+#define G(x, y, z) ((y) ^ ((z) & ((x) ^ (y))))
+#define H(x, y, z) (((x) ^ (y)) ^ (z))
+#define H2(x, y, z) ((x) ^ ((y) ^ (z)))
+#define I(x, y, z) ((y) ^ ((x) | ~(z)))
+
+/*
+ * The MD5 transformation for all four rounds.
+ */
+#define STEP(f, a, b, c, d, x, t, s) \
+ (a) += f((b), (c), (d)) + (x) + (t); \
+ (a) = (((a) << (s)) | (((a) & 0xffffffff) >> (32 - (s)))); \
+ (a) += (b);
+
+/*
+ * SET reads 4 input bytes in little-endian byte order and stores them in a
+ * properly aligned word in host byte order.
+ *
+ * The check for little-endian architectures that tolerate unaligned memory
+ * accesses is just an optimization. Nothing will break if it fails to detect
+ * a suitable architecture.
+ *
+ * Unfortunately, this optimization may be a C strict aliasing rules violation
+ * if the caller's data buffer has effective type that cannot be aliased by
+ * MD5_u32plus. In practice, this problem may occur if these MD5 routines are
+ * inlined into a calling function, or with future and dangerously advanced
+ * link-time optimizations. For the time being, keeping these MD5 routines in
+ * their own translation unit avoids the problem.
+ */
+#if defined(__i386__) || defined(__x86_64__) || defined(__vax__)
+#define SET(n) \
+ (*(MD5_u32plus *)&ptr[(n) * 4])
+#define GET(n) \
+ SET(n)
+#else
+#define SET(n) \
+ (ctx->block[(n)] = \
+ (MD5_u32plus)ptr[(n) * 4] | \
+ ((MD5_u32plus)ptr[(n) * 4 + 1] << 8) | \
+ ((MD5_u32plus)ptr[(n) * 4 + 2] << 16) | \
+ ((MD5_u32plus)ptr[(n) * 4 + 3] << 24))
+#define GET(n) \
+ (ctx->block[(n)])
+#endif
+
+/*
+ * This processes one or more 64-byte data blocks, but does NOT update the bit
+ * counters. There are no alignment requirements.
+ */
+static const void *body(MD5_CTX *ctx, const void *data, unsigned long size)
+{
+ const unsigned char *ptr;
+ MD5_u32plus a, b, c, d;
+ MD5_u32plus saved_a, saved_b, saved_c, saved_d;
+
+ ptr = (const unsigned char *)data;
+
+ a = ctx->a;
+ b = ctx->b;
+ c = ctx->c;
+ d = ctx->d;
+
+ do {
+ saved_a = a;
+ saved_b = b;
+ saved_c = c;
+ saved_d = d;
+
+/* Round 1 */
+ STEP(F, a, b, c, d, SET(0), 0xd76aa478, 7)
+ STEP(F, d, a, b, c, SET(1), 0xe8c7b756, 12)
+ STEP(F, c, d, a, b, SET(2), 0x242070db, 17)
+ STEP(F, b, c, d, a, SET(3), 0xc1bdceee, 22)
+ STEP(F, a, b, c, d, SET(4), 0xf57c0faf, 7)
+ STEP(F, d, a, b, c, SET(5), 0x4787c62a, 12)
+ STEP(F, c, d, a, b, SET(6), 0xa8304613, 17)
+ STEP(F, b, c, d, a, SET(7), 0xfd469501, 22)
+ STEP(F, a, b, c, d, SET(8), 0x698098d8, 7)
+ STEP(F, d, a, b, c, SET(9), 0x8b44f7af, 12)
+ STEP(F, c, d, a, b, SET(10), 0xffff5bb1, 17)
+ STEP(F, b, c, d, a, SET(11), 0x895cd7be, 22)
+ STEP(F, a, b, c, d, SET(12), 0x6b901122, 7)
+ STEP(F, d, a, b, c, SET(13), 0xfd987193, 12)
+ STEP(F, c, d, a, b, SET(14), 0xa679438e, 17)
+ STEP(F, b, c, d, a, SET(15), 0x49b40821, 22)
+
+/* Round 2 */
+ STEP(G, a, b, c, d, GET(1), 0xf61e2562, 5)
+ STEP(G, d, a, b, c, GET(6), 0xc040b340, 9)
+ STEP(G, c, d, a, b, GET(11), 0x265e5a51, 14)
+ STEP(G, b, c, d, a, GET(0), 0xe9b6c7aa, 20)
+ STEP(G, a, b, c, d, GET(5), 0xd62f105d, 5)
+ STEP(G, d, a, b, c, GET(10), 0x02441453, 9)
+ STEP(G, c, d, a, b, GET(15), 0xd8a1e681, 14)
+ STEP(G, b, c, d, a, GET(4), 0xe7d3fbc8, 20)
+ STEP(G, a, b, c, d, GET(9), 0x21e1cde6, 5)
+ STEP(G, d, a, b, c, GET(14), 0xc33707d6, 9)
+ STEP(G, c, d, a, b, GET(3), 0xf4d50d87, 14)
+ STEP(G, b, c, d, a, GET(8), 0x455a14ed, 20)
+ STEP(G, a, b, c, d, GET(13), 0xa9e3e905, 5)
+ STEP(G, d, a, b, c, GET(2), 0xfcefa3f8, 9)
+ STEP(G, c, d, a, b, GET(7), 0x676f02d9, 14)
+ STEP(G, b, c, d, a, GET(12), 0x8d2a4c8a, 20)
+
+/* Round 3 */
+ STEP(H, a, b, c, d, GET(5), 0xfffa3942, 4)
+ STEP(H2, d, a, b, c, GET(8), 0x8771f681, 11)
+ STEP(H, c, d, a, b, GET(11), 0x6d9d6122, 16)
+ STEP(H2, b, c, d, a, GET(14), 0xfde5380c, 23)
+ STEP(H, a, b, c, d, GET(1), 0xa4beea44, 4)
+ STEP(H2, d, a, b, c, GET(4), 0x4bdecfa9, 11)
+ STEP(H, c, d, a, b, GET(7), 0xf6bb4b60, 16)
+ STEP(H2, b, c, d, a, GET(10), 0xbebfbc70, 23)
+ STEP(H, a, b, c, d, GET(13), 0x289b7ec6, 4)
+ STEP(H2, d, a, b, c, GET(0), 0xeaa127fa, 11)
+ STEP(H, c, d, a, b, GET(3), 0xd4ef3085, 16)
+ STEP(H2, b, c, d, a, GET(6), 0x04881d05, 23)
+ STEP(H, a, b, c, d, GET(9), 0xd9d4d039, 4)
+ STEP(H2, d, a, b, c, GET(12), 0xe6db99e5, 11)
+ STEP(H, c, d, a, b, GET(15), 0x1fa27cf8, 16)
+ STEP(H2, b, c, d, a, GET(2), 0xc4ac5665, 23)
+
+/* Round 4 */
+ STEP(I, a, b, c, d, GET(0), 0xf4292244, 6)
+ STEP(I, d, a, b, c, GET(7), 0x432aff97, 10)
+ STEP(I, c, d, a, b, GET(14), 0xab9423a7, 15)
+ STEP(I, b, c, d, a, GET(5), 0xfc93a039, 21)
+ STEP(I, a, b, c, d, GET(12), 0x655b59c3, 6)
+ STEP(I, d, a, b, c, GET(3), 0x8f0ccc92, 10)
+ STEP(I, c, d, a, b, GET(10), 0xffeff47d, 15)
+ STEP(I, b, c, d, a, GET(1), 0x85845dd1, 21)
+ STEP(I, a, b, c, d, GET(8), 0x6fa87e4f, 6)
+ STEP(I, d, a, b, c, GET(15), 0xfe2ce6e0, 10)
+ STEP(I, c, d, a, b, GET(6), 0xa3014314, 15)
+ STEP(I, b, c, d, a, GET(13), 0x4e0811a1, 21)
+ STEP(I, a, b, c, d, GET(4), 0xf7537e82, 6)
+ STEP(I, d, a, b, c, GET(11), 0xbd3af235, 10)
+ STEP(I, c, d, a, b, GET(2), 0x2ad7d2bb, 15)
+ STEP(I, b, c, d, a, GET(9), 0xeb86d391, 21)
+
+ a += saved_a;
+ b += saved_b;
+ c += saved_c;
+ d += saved_d;
+
+ ptr += 64;
+ } while (size -= 64);
+
+ ctx->a = a;
+ ctx->b = b;
+ ctx->c = c;
+ ctx->d = d;
+
+ return ptr;
+}
+
+void MD5_Init(MD5_CTX *ctx)
+{
+ ctx->a = 0x67452301;
+ ctx->b = 0xefcdab89;
+ ctx->c = 0x98badcfe;
+ ctx->d = 0x10325476;
+
+ ctx->lo = 0;
+ ctx->hi = 0;
+}
+
+void MD5_Update(MD5_CTX *ctx, const void *data, unsigned long size)
+{
+ MD5_u32plus saved_lo;
+ unsigned long used, available;
+
+ saved_lo = ctx->lo;
+ if ((ctx->lo = (saved_lo + size) & 0x1fffffff) < saved_lo)
+ ctx->hi++;
+ ctx->hi += size >> 29;
+
+ used = saved_lo & 0x3f;
+
+ if (used) {
+ available = 64 - used;
+
+ if (size < available) {
+ memcpy(&ctx->buffer[used], data, size);
+ return;
+ }
+
+ memcpy(&ctx->buffer[used], data, available);
+ data = (const unsigned char *)data + available;
+ size -= available;
+ body(ctx, ctx->buffer, 64);
+ }
+
+ if (size >= 64) {
+ data = body(ctx, data, size & ~(unsigned long)0x3f);
+ size &= 0x3f;
+ }
+
+ memcpy(ctx->buffer, data, size);
+}
+
+#define OUT(dst, src) \
+ (dst)[0] = (unsigned char)(src); \
+ (dst)[1] = (unsigned char)((src) >> 8); \
+ (dst)[2] = (unsigned char)((src) >> 16); \
+ (dst)[3] = (unsigned char)((src) >> 24);
+
+void MD5_Final(unsigned char *result, MD5_CTX *ctx)
+{
+ unsigned long used, available;
+
+ used = ctx->lo & 0x3f;
+
+ ctx->buffer[used++] = 0x80;
+
+ available = 64 - used;
+
+ if (available < 8) {
+ memset(&ctx->buffer[used], 0, available);
+ body(ctx, ctx->buffer, 64);
+ used = 0;
+ available = 64;
+ }
+
+ memset(&ctx->buffer[used], 0, available - 8);
+
+ ctx->lo <<= 3;
+ OUT(&ctx->buffer[56], ctx->lo)
+ OUT(&ctx->buffer[60], ctx->hi)
+
+ body(ctx, ctx->buffer, 64);
+
+ OUT(&result[0], ctx->a)
+ OUT(&result[4], ctx->b)
+ OUT(&result[8], ctx->c)
+ OUT(&result[12], ctx->d)
+
+ memset(ctx, 0, sizeof(*ctx));
+}
+
+
+//////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////
+
+static MD5_CTX md5ctx;
+
+void xxprintf_start(void)
+{
+ MD5_Init(&md5ctx);
+}
+
+void xxprintf_done(void)
+{
+ const char hexchar[16] = "0123456789abcdef";
+ unsigned char result[100];
+ memset(result, 0, sizeof(result));
+ MD5_Final(&result[0], &md5ctx);
+ printf("final MD5 = ");
+ int i;
+ for (i = 0; i < 16; i++) {
+ printf("%c%c", hexchar[0xF & (result[i] >> 4)],
+ hexchar[0xF & (result[i] >> 0)]);
+ }
+ printf("\n");
+}
+
+__attribute__((format(__printf__, 1, 2)))
+void xxprintf (const char *format, ...)
+{
+ char buf[128];
+ memset(buf, 0, sizeof(buf));
+
+ va_list vargs;
+ va_start(vargs, format);
+ int n = vsnprintf(buf, sizeof(buf)-1, format, vargs);
+ va_end(vargs);
+
+ assert(n < sizeof(buf)-1);
+ assert(buf[sizeof(buf)-1] == 0);
+ assert(buf[sizeof(buf)-2] == 0);
+
+ MD5_Update(&md5ctx, buf, strlen(buf));
+ if (0) printf("QQQ %s", buf);
+}
+
+//////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////
+
+
+/* Setting this to 1 creates a very comprehensive test of
+ integer condition codes. */
+#define TEST_INTEGER_VERBOSE 1
+
+typedef long long int int64;
+
+//#define LINUX_VM86_IOPL_FIX
+//#define TEST_P4_FLAGS
+
+#define xglue(x, y) x ## y
+#define glue(x, y) xglue(x, y)
+#define stringify(s) tostring(s)
+#define tostring(s) #s
+
+#define CC_C 0x0001
+#define CC_P 0x0004
+#define CC_A 0x0010
+#define CC_Z 0x0040
+#define CC_S 0x0080
+#define CC_O 0x0800
+
+#define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A)
+
+#define OP add
+#include "fb_test_amd64.h"
+
+#define OP sub
+#include "fb_test_amd64.h"
+
+#define OP xor
+#include "fb_test_amd64.h"
+
+#define OP and
+#include "fb_test_amd64.h"
+
+#define OP or
+#include "fb_test_amd64.h"
+
+#define OP cmp
+#include "fb_test_amd64.h"
+
+#define OP adc
+#define OP_CC
+#include "fb_test_amd64.h"
+
+#define OP sbb
+#define OP_CC
+#include "fb_test_amd64.h"
+
+#define OP adcx
+#define NSH
+#define OP_CC
+#include "fb_test_amd64.h"
+
+#define OP adox
+#define NSH
+#define OP_CC
+#include "fb_test_amd64.h"
+
+#define OP inc
+#define OP_CC
+#define OP1
+#include "fb_test_amd64.h"
+
+#define OP dec
+#define OP_CC
+#define OP1
+#include "fb_test_amd64.h"
+
+#define OP neg
+#define OP_CC
+#define OP1
+#include "fb_test_amd64.h"
+
+#define OP not
+#define OP_CC
+#define OP1
+#include "fb_test_amd64.h"
+
+#undef CC_MASK
+#define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O)
+
+#define OP shl
+#include "fb_test_amd64_shift.h"
+
+#define OP shr
+#include "fb_test_amd64_shift.h"
+
+#define OP sar
+#include "fb_test_amd64_shift.h"
+
+#define OP rol
+#include "fb_test_amd64_shift.h"
+
+#define OP ror
+#include "fb_test_amd64_shift.h"
+
+#define OP rcr
+#define OP_CC
+#include "fb_test_amd64_shift.h"
+
+#define OP rcl
+#define OP_CC
+#include "fb_test_amd64_shift.h"
+
+/* XXX: should be more precise ? */
+#undef CC_MASK
+#define CC_MASK (CC_C)
+
+/* lea test (modrm support) */
+#define TEST_LEA(STR)\
+{\
+ asm("leaq " STR ", %0"\
+ : "=r" (res)\
+ : "a" (rax), "b" (rbx), "c" (rcx), "d" (rdx), "S" (rsi), "D" (rdi));\
+ xxprintf("lea %s = %016llx\n", STR, res);\
+}
+
+#define TEST_LEA16(STR)\
+{\
+ asm(".code16 ; .byte 0x67 ; leal " STR ", %0 ; .code32"\
+ : "=wq" (res)\
+ : "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
+ xxprintf("lea %s = %08x\n", STR, res);\
+}
+
+
+void test_lea(void)
+{
+ int64 rax, rbx, rcx, rdx, rsi, rdi, res;
+ rax = 0x0001;
+ rbx = 0x0002;
+ rcx = 0x0004;
+ rdx = 0x0008;
+ rsi = 0x0010;
+ rdi = 0x0020;
+
+ TEST_LEA("0x4000");
+
+ TEST_LEA("(%%rax)");
+ TEST_LEA("(%%rbx)");
+ TEST_LEA("(%%rcx)");
+ TEST_LEA("(%%rdx)");
+ TEST_LEA("(%%rsi)");
+ TEST_LEA("(%%rdi)");
+
+ TEST_LEA("0x40(%%rax)");
+ TEST_LEA("0x40(%%rbx)");
+ TEST_LEA("0x40(%%rcx)");
+ TEST_LEA("0x40(%%rdx)");
+ TEST_LEA("0x40(%%rsi)");
+ TEST_LEA("0x40(%%rdi)");
+
+ TEST_LEA("0x4000(%%rax)");
+ TEST_LEA("0x4000(%%rbx)");
+ TEST_LEA("0x4000(%%rcx)");
+ TEST_LEA("0x4000(%%rdx)");
+ TEST_LEA("0x4000(%%rsi)");
+ TEST_LEA("0x4000(%%rdi)");
+
+ TEST_LEA("(%%rax, %%rcx)");
+ TEST_LEA("(%%rbx, %%rdx)");
+ TEST_LEA("(%%rcx, %%rcx)");
+ TEST_LEA("(%%rdx, %%rcx)");
+ TEST_LEA("(%%rsi, %%rcx)");
+ TEST_LEA("(%%rdi, %%rcx)");
+
+ TEST_LEA("0x40(%%rax, %%rcx)");
+ TEST_LEA("0x4000(%%rbx, %%rdx)");
+
+ TEST_LEA("(%%rcx, %%rcx, 2)");
+ TEST_LEA("(%%rdx, %%rcx, 4)");
+ TEST_LEA("(%%rsi, %%rcx, 8)");
+
+ TEST_LEA("(,%%rax, 2)");
+ TEST_LEA("(,%%rbx, 4)");
+ TEST_LEA("(,%%rcx, 8)");
+
+ TEST_LEA("0x40(,%%rax, 2)");
+ TEST_LEA("0x40(,%%rbx, 4)");
+ TEST_LEA("0x40(,%%rcx, 8)");
+
+
+ TEST_LEA("-10(%%rcx, %%rcx, 2)");
+ TEST_LEA("-10(%%rdx, %%rcx, 4)");
+ TEST_LEA("-10(%%rsi, %%rcx, 8)");
+
+ TEST_LEA("0x4000(%%rcx, %%rcx, 2)");
+ TEST_LEA("0x4000(%%rdx, %%rcx, 4)");
+ TEST_LEA("0x4000(%%rsi, %%rcx, 8)");
+}
+
+#define TEST_JCC(JCC, v1, v2)\
+{ int one = 1; \
+ int res;\
+ asm("movl $1, %0\n\t"\
+ "cmpl %2, %1\n\t"\
+ "j" JCC " 1f\n\t"\
+ "movl $0, %0\n\t"\
+ "1:\n\t"\
+ : "=r" (res)\
+ : "r" (v1), "r" (v2));\
+ xxprintf("%-10s %d\n", "j" JCC, res);\
+\
+ asm("movl $0, %0\n\t"\
+ "cmpl %2, %1\n\t"\
+ "set" JCC " %b0\n\t"\
+ : "=r" (res)\
+ : "r" (v1), "r" (v2));\
+ xxprintf("%-10s %d\n", "set" JCC, res);\
+ {\
+ asm("movl $0x12345678, %0\n\t"\
+ "cmpl %2, %1\n\t"\
+ "cmov" JCC "l %3, %0\n\t"\
+ : "=r" (res)\
+ : "r" (v1), "r" (v2), "m" (one));\
+ xxprintf("%-10s R=0x%08x\n", "cmov" JCC "l", res);\
+ asm("movl $0x12345678, %0\n\t"\
+ "cmpl %2, %1\n\t"\
+ "cmov" JCC "w %w3, %w0\n\t"\
+ : "=r" (res)\
+ : "r" (v1), "r" (v2), "r" (one));\
+ xxprintf("%-10s R=0x%08x\n", "cmov" JCC "w", res);\
+ } \
+}
+
+/* various jump tests */
+void test_jcc(void)
+{
+ TEST_JCC("ne", 1, 1);
+ TEST_JCC("ne", 1, 0);
+
+ TEST_JCC("e", 1, 1);
+ TEST_JCC("e", 1, 0);
+
+ TEST_JCC("l", 1, 1);
+ TEST_JCC("l", 1, 0);
+ TEST_JCC("l", 1, -1);
+
+ TEST_JCC("le", 1, 1);
+ TEST_JCC("le", 1, 0);
+ TEST_JCC("le", 1, -1);
+
+ TEST_JCC("ge", 1, 1);
+ TEST_JCC("ge", 1, 0);
+ TEST_JCC("ge", -1, 1);
+
+ TEST_JCC("g", 1, 1);
+ TEST_JCC("g", 1, 0);
+ TEST_JCC("g", 1, -1);
+
+ TEST_JCC("b", 1, 1);
+ TEST_JCC("b", 1, 0);
+ TEST_JCC("b", 1, -1);
+
+ TEST_JCC("be", 1, 1);
+ TEST_JCC("be", 1, 0);
+ TEST_JCC("be", 1, -1);
+
+ TEST_JCC("ae", 1, 1);
+ TEST_JCC("ae", 1, 0);
+ TEST_JCC("ae", 1, -1);
+
+ TEST_JCC("a", 1, 1);
+ TEST_JCC("a", 1, 0);
+ TEST_JCC("a", 1, -1);
+
+
+ TEST_JCC("p", 1, 1);
+ TEST_JCC("p", 1, 0);
+
+ TEST_JCC("np", 1, 1);
+ TEST_JCC("np", 1, 0);
+
+ TEST_JCC("o", 0x7fffffff, 0);
+ TEST_JCC("o", 0x7fffffff, -1);
+
+ TEST_JCC("no", 0x7fffffff, 0);
+ TEST_JCC("no", 0x7fffffff, -1);
+
+ TEST_JCC("s", 0, 1);
+ TEST_JCC("s", 0, -1);
+ TEST_JCC("s", 0, 0);
+
+ TEST_JCC("ns", 0, 1);
+ TEST_JCC("ns", 0, -1);
+ TEST_JCC("ns", 0, 0);
+}
+
+#undef CC_MASK
+#ifdef TEST_P4_FLAGS
+#define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A)
+#else
+#define CC_MASK (CC_O | CC_C)
+#endif
+
+#define OP mul
+#include "fb_test_amd64_muldiv.h"
+
+#define OP imul
+#include "fb_test_amd64_muldiv.h"
+
+void test_imulw2(int64 op0, int64 op1)
+{
+ int64 res, s1, s0, flags;
+ s0 = op0;
+ s1 = op1;
+ res = s0;
+ flags = 0;
+ asm ("pushq %4\n\t"
+ "popfq\n\t"
+ "imulw %w2, %w0\n\t"
+ "pushfq\n\t"
+ "popq %1\n\t"
+ : "=q" (res), "=g" (flags)
+ : "q" (s1), "0" (res), "1" (flags));
+ xxprintf("%-10s A=%016llx B=%016llx R=%016llx CC=%04llx\n",
+ "imulw", s0, s1, res, flags & CC_MASK);
+}
+
+void test_imull2(int64 op0, int64 op1)
+{
+ int res, s1;
+ int64 s0, flags;
+ s0 = op0;
+ s1 = op1;
+ res = s0;
+ flags = 0;
+ asm ("pushq %4\n\t"
+ "popfq\n\t"
+ "imull %2, %0\n\t"
+ "pushfq\n\t"
+ "popq %1\n\t"
+ : "=q" (res), "=g" (flags)
+ : "q" (s1), "0" (res), "1" (flags));
+ xxprintf("%-10s A=%016llx B=%08x R=%08x CC=%04llx\n",
+ "imull", s0, s1, res, flags & CC_MASK);
+}
+
+#define TEST_IMUL_IM(size, size1, op0, op1)\
+{\
+ int64 res, flags;\
+ flags = 0;\
+ res = 0;\
+ asm ("pushq %3\n\t"\
+ "popfq\n\t"\
+ "imul" size " $" #op0 ", %" size1 "2, %" size1 "0\n\t" \
+ "pushfq\n\t"\
+ "popq %1\n\t"\
+ : "=r" (res), "=g" (flags)\
+ : "r" (op1), "1" (flags), "0" (res));\
+ xxprintf("%-10s A=%08x B=%08x R=%016llx CC=%04llx\n",\
+ "imul" size, op0, op1, res, flags & CC_MASK);\
+}
+
+#define TEST_IMUL_IM_L(op0, op1)\
+{\
+ int64 flags = 0;\
+ int res = 0;\
+ int res64 = 0;\
+ asm ("pushq %3\n\t"\
+ "popfq\n\t"\
+ "imul $" #op0 ", %2, %0\n\t" \
+ "pushfq\n\t"\
+ "popq %1\n\t"\
+ : "=r" (res64), "=g" (flags)\
+ : "r" (op1), "1" (flags), "0" (res));\
+ xxprintf("%-10s A=%08x B=%08x R=%08x CC=%04llx\n",\
+ "imull", op0, op1, res, flags & CC_MASK);\
+}
+
+
+#undef CC_MASK
+#define CC_MASK (0)
+
+#define OP div
+#include "fb_test_amd64_muldiv.h"
+
+#define OP idiv
+#include "fb_test_amd64_muldiv.h"
+
+void test_mul(void)
+{
+ test_imulb(0x1234561d, 4);
+ test_imulb(3, -4);
+ test_imulb(0x80, 0x80);
+ test_imulb(0x10, 0x10);
+
+ test_imulw(0, 0, 0);
+ test_imulw(0, 0xFF, 0xFF);
+ test_imulw(0, 0xFF, 0x100);
+ test_imulw(0, 0x1234001d, 45);
+ test_imulw(0, 23, -45);
+ test_imulw(0, 0x8000, 0x8000);
+ test_imulw(0, 0x100, 0x100);
+
+ test_imull(0, 0, 0);
+ test_imull(0, 0xFFFF, 0xFFFF);
+ test_imull(0, 0xFFFF, 0x10000);
+ test_imull(0, 0x1234001d, 45);
+ test_imull(0, 23, -45);
+ test_imull(0, 0x80000000, 0x80000000);
+ test_imull(0, 0x10000, 0x10000);
+
+ test_mulb(0x1234561d, 4);
+ test_mulb(3, -4);
+ test_mulb(0x80, 0x80);
+ test_mulb(0x10, 0x10);
+
+ test_mulw(0, 0x1234001d, 45);
+ test_mulw(0, 23, -45);
+ test_mulw(0, 0x8000, 0x8000);
+ test_mulw(0, 0x100, 0x100);
+
+ test_mull(0, 0x1234001d, 45);
+ test_mull(0, 23, -45);
+ test_mull(0, 0x80000000, 0x80000000);
+ test_mull(0, 0x10000, 0x10000);
+
+ test_imulw2(0x1234001d, 45);
+ test_imulw2(23, -45);
+ test_imulw2(0x8000, 0x8000);
+ test_imulw2(0x100, 0x100);
+
+ test_imull2(0x1234001d, 45);
+ test_imull2(23, -45);
+ test_imull2(0x80000000, 0x80000000);
+ test_imull2(0x10000, 0x10000);
+
+ TEST_IMUL_IM("w", "w", 45, 0x1234);
+ TEST_IMUL_IM("w", "w", -45, 23);
+ TEST_IMUL_IM("w", "w", 0x8000, 0x80000000);
+ TEST_IMUL_IM("w", "w", 0x7fff, 0x1000);
+
+ TEST_IMUL_IM_L(45, 0x1234);
+ TEST_IMUL_IM_L(-45, 23);
+ TEST_IMUL_IM_L(0x8000, 0x80000000);
+ TEST_IMUL_IM_L(0x7fff, 0x1000);
+
+ test_idivb(0x12341678, 0x127e);
+ test_idivb(0x43210123, -5);
+ test_idivb(0x12340004, -1);
+
+ test_idivw(0, 0x12345678, 12347);
+ test_idivw(0, -23223, -45);
+ test_idivw(0, 0x12348000, -1);
+ test_idivw(0x12343, 0x12345678, 0x81238567);
+
+ test_idivl(0, 0x12345678, 12347);
+ test_idivl(0, -233223, -45);
+ test_idivl(0, 0x80000000, -1);
+ test_idivl(0x12343, 0x12345678, 0x81234567);
+
+ test_idivq(0, 0x12345678, 12347);
+ test_idivq(0, -233223, -45);
+ test_idivq(0, 0x80000000, -1);
+ test_idivq(0x12343, 0x12345678, 0x81234567);
+
+ test_divb(0x12341678, 0x127e);
+ test_divb(0x43210123, -5);
+ test_divb(0x12340004, -1);
+
+ test_divw(0, 0x12345678, 12347);
+ test_divw(0, -23223, -45);
+ test_divw(0, 0x12348000, -1);
+ test_divw(0x12343, 0x12345678, 0x81238567);
+
+ test_divl(0, 0x12345678, 12347);
+ test_divl(0, -233223, -45);
+ test_divl(0, 0x80000000, -1);
+ test_divl(0x12343, 0x12345678, 0x81234567);
+
+ test_divq(0, 0x12345678, 12347);
+ test_divq(0, -233223, -45);
+ test_divq(0, 0x80000000, -1);
+ test_divq(0x12343, 0x12345678, 0x81234567);
+}
+
+#define TEST_BSX(op, size, op0)\
+{\
+ int res, val, resz;\
+ val = op0;\
+ asm("xorl %1, %1\n"\
+ "movl $0x12345678, %0\n"\
+ #op " %" size "2, %" size "0 ; setz %b1" \
+ : "=r" (res), "=q" (resz)\
+ : "r" (val));\
+ xxprintf("%-10s A=%08x R=%08x %d\n", #op, val, res, resz);\
+}
+
+void test_bsx(void)
+{
+ TEST_BSX(bsrw, "w", 0);
+ TEST_BSX(bsrw, "w", 0x12340128);
+ TEST_BSX(bsrl, "", 0);
+ TEST_BSX(bsrl, "", 0x00340128);
+ TEST_BSX(bsfw, "w", 0);
+ TEST_BSX(bsfw, "w", 0x12340128);
+ TEST_BSX(bsfl, "", 0);
+ TEST_BSX(bsfl, "", 0x00340128);
+}
+
+/**********************************************/
+
+void test_fops(double a, double b)
+{
+ xxprintf("a=%f b=%f a+b=%f\n", a, b, a + b);
+ xxprintf("a=%f b=%f a-b=%f\n", a, b, a - b);
+ xxprintf("a=%f b=%f a*b=%f\n", a, b, a * b);
+ xxprintf("a=%f b=%f a/b=%f\n", a, b, a / b);
+ xxprintf("a=%f b=%f fmod(a, b)=%f\n", a, b, fmod(a, b));
+ xxprintf("a=%f sqrt(a)=%f\n", a, sqrt(a));
+ xxprintf("a=%f sin(a)=%f\n", a, sin(a));
+ xxprintf("a=%f cos(a)=%f\n", a, cos(a));
+ xxprintf("a=%f tan(a)=%f\n", a, tan(a));
+ xxprintf("a=%f log(a)=%f\n", a, log(a));
+ xxprintf("a=%f exp(a)=%f\n", a, exp(a));
+ xxprintf("a=%f b=%f atan2(a, b)=%f\n", a, b, atan2(a, b));
+ /* just to test some op combining */
+ xxprintf("a=%f asin(sin(a))=%f\n", a, asin(sin(a)));
+ xxprintf("a=%f acos(cos(a))=%f\n", a, acos(cos(a)));
+ xxprintf("a=%f atan(tan(a))=%f\n", a, atan(tan(a)));
+}
+
+void test_fcmp(double a, double b)
+{
+ xxprintf("(%f<%f)=%d\n",
+ a, b, a < b);
+ xxprintf("(%f<=%f)=%d\n",
+ a, b, a <= b);
+ xxprintf("(%f==%f)=%d\n",
+ a, b, a == b);
+ xxprintf("(%f>%f)=%d\n",
+ a, b, a > b);
+ xxprintf("(%f<=%f)=%d\n",
+ a, b, a >= b);
+ {
+ unsigned long long int rflags;
+ /* test f(u)comi instruction */
+ asm("fcomi %2, %1\n"
+ "pushfq\n"
+ "popq %0\n"
+ : "=r" (rflags)
+ : "t" (a), "u" (b));
+ xxprintf("fcomi(%f %f)=%016llx\n", a, b, rflags & (CC_Z | CC_P | CC_C));
+ }
+}
+
+void test_fcvt(double a)
+{
+ float fa;
+ long double la;
+ int16_t fpuc;
+ int i;
+ int64 lla;
+ int ia;
+ int16_t wa;
+ double ra;
+
+ fa = a;
+ la = a;
+ xxprintf("(float)%f = %f\n", a, fa);
+ xxprintf("(long double)%f = %Lf\n", a, la);
+ xxprintf("a=%016llx\n", *(unsigned long long int *) &a);
+ xxprintf("la=%016llx %04x\n", *(unsigned long long int *) &la,
+ *(unsigned short *) ((char *)(&la) + 8));
+
+ /* test all roundings */
+ asm volatile ("fstcw %0" : "=m" (fpuc));
+ for(i=0;i<4;i++) {
+ short zz = (fpuc & ~0x0c00) | (i << 10);
+ asm volatile ("fldcw %0" : : "m" (zz));
+ asm volatile ("fists %0" : "=m" (wa) : "t" (a));
+ asm volatile ("fistl %0" : "=m" (ia) : "t" (a));
+ asm volatile ("fistpll %0" : "=m" (lla) : "t" (a) : "st");
+ asm volatile ("frndint ; fstl %0" : "=m" (ra) : "t" (a));
+ asm volatile ("fldcw %0" : : "m" (fpuc));
+ xxprintf("(short)a = %d\n", wa);
+ xxprintf("(int)a = %d\n", ia);
+ xxprintf("(int64_t)a = %lld\n", lla);
+ xxprintf("rint(a) = %f\n", ra);
+ }
+}
+
+#define TEST(N) \
+ asm("fld" #N : "=t" (a)); \
+ xxprintf("fld" #N "= %f\n", a);
+
+void test_fconst(void)
+{
+ double a;
+ TEST(1);
+ TEST(l2t);
+ TEST(l2e);
+ TEST(pi);
+ TEST(lg2);
+ TEST(ln2);
+ TEST(z);
+}
+
+void test_fbcd(double a)
+{
+ unsigned short bcd[5];
+ double b;
+
+ asm("fbstp %0" : "=m" (bcd[0]) : "t" (a) : "st");
+ asm("fbld %1" : "=t" (b) : "m" (bcd[0]));
+ xxprintf("a=%f bcd=%04x%04x%04x%04x%04x b=%f\n",
+ a, bcd[4], bcd[3], bcd[2], bcd[1], bcd[0], b);
+}
+
+#define TEST_ENV(env, save, restore)\
+{\
+ memset((env), 0xaa, sizeof(*(env)));\
+ for(i=0;i<5;i++)\
+ asm volatile ("fldl %0" : : "m" (dtab[i]));\
+ asm(save " %0\n" : : "m" (*(env)));\
+ asm(restore " %0\n": : "m" (*(env)));\
+ for(i=0;i<5;i++)\
+ asm volatile ("fstpl %0" : "=m" (rtab[i]));\
+ for(i=0;i<5;i++)\
+ xxprintf("res[%d]=%f\n", i, rtab[i]);\
+ xxprintf("fpuc=%04x fpus=%04x fptag=%04x\n",\
+ (env)->fpuc,\
+ (env)->fpus & 0xff00,\
+ (env)->fptag);\
+}
+
+void test_fenv(void)
+{
+ struct __attribute__((packed)) {
+ uint16_t fpuc;
+ uint16_t dummy1;
+ uint16_t fpus;
+ uint16_t dummy2;
+ uint16_t fptag;
+ uint16_t dummy3;
+ uint32_t ignored[4];
+ long double fpregs[8];
+ } float_env32;
+ double dtab[8];
+ double rtab[8];
+ int i;
+
+ for(i=0;i<8;i++)
+ dtab[i] = i + 1;
+
+ TEST_ENV(&float_env32, "fnstenv", "fldenv");
+ TEST_ENV(&float_env32, "fnsave", "frstor");
+
+ /* test for ffree */
+ for(i=0;i<5;i++)
+ asm volatile ("fldl %0" : : "m" (dtab[i]));
+ asm volatile("ffree %st(2)");
+ asm volatile ("fnstenv %0\n" : : "m" (float_env32));
+ asm volatile ("fninit");
+ xxprintf("fptag=%04x\n", float_env32.fptag);
+}
+
+
+#define TEST_FCMOV(a, b, rflags, CC)\
+{\
+ double res;\
+ asm("pushq %3\n"\
+ "popfq\n"\
+ "fcmov" CC " %2, %0\n"\
+ : "=t" (res)\
+ : "0" (a), "u" (b), "g" (rflags));\
+ xxprintf("fcmov%s rflags=0x%04llx-> %f\n", \
+ CC, rflags, res);\
+}
+
+void test_fcmov(void)
+{
+ double a, b;
+ int64 rflags, i;
+
+ a = 1.0;
+ b = 2.0;
+ for(i = 0; i < 4; i++) {
+ rflags = 0;
+ if (i & 1)
+ rflags |= CC_C;
+ if (i & 2)
+ rflags |= CC_Z;
+ TEST_FCMOV(a, b, rflags, "b");
+ TEST_FCMOV(a, b, rflags, "e");
+ TEST_FCMOV(a, b, rflags, "be");
+ TEST_FCMOV(a, b, rflags, "nb");
+ TEST_FCMOV(a, b, rflags, "ne");
+ TEST_FCMOV(a, b, rflags, "nbe");
+ }
+ TEST_FCMOV(a, b, (int64)0, "u");
+ TEST_FCMOV(a, b, (int64)CC_P, "u");
+ TEST_FCMOV(a, b, (int64)0, "nu");
+ TEST_FCMOV(a, b, (int64)CC_P, "nu");
+}
+
+void test_floats(void)
+{
+ test_fops(2, 3);
+ test_fops(1.4, -5);
+ test_fcmp(2, -1);
+ test_fcmp(2, 2);
+ test_fcmp(2, 3);
+ test_fcvt(0.5);
+ test_fcvt(-0.5);
+ test_fcvt(1.0/7.0);
+ test_fcvt(-1.0/9.0);
+ test_fcvt(32768);
+ test_fcvt(-1e20);
+ test_fconst();
+ // REINSTATE (maybe): test_fbcd(1234567890123456);
+ // REINSTATE (maybe): test_fbcd(-123451234567890);
+ // REINSTATE: test_fenv();
+ // REINSTATE: test_fcmov();
+}
+
+/**********************************************/
+
+#define TEST_XCHG(op, size, opconst)\
+{\
+ int op0, op1;\
+ op0 = 0x12345678;\
+ op1 = 0xfbca7654;\
+ asm(#op " %" size "0, %" size "1" \
+ : "=q" (op0), opconst (op1) \
+ : "0" (op0), "1" (op1));\
+ xxprintf("%-10s A=%08x B=%08x\n",\
+ #op, op0, op1);\
+}
+
+#define TEST_CMPXCHG(op, size, opconst, eax)\
+{\
+ int op0, op1;\
+ op0 = 0x12345678;\
+ op1 = 0xfbca7654;\
+ asm(#op " %" size "0, %" size "1" \
+ : "=q" (op0), opconst (op1) \
+ : "0" (op0), "1" (op1), "a" (eax));\
+ xxprintf("%-10s EAX=%08x A=%08x C=%08x\n",\
+ #op, eax, op0, op1);\
+}
+
+
+/**********************************************/
+/* segmentation tests */
+
+extern char func_lret32;
+extern char func_iret32;
+
+uint8_t str_buffer[4096];
+
+#define TEST_STRING1(OP, size, DF, REP)\
+{\
+ int64 rsi, rdi, rax, rcx, rflags;\
+\
+ rsi = (long)(str_buffer + sizeof(str_buffer) / 2);\
+ rdi = (long)(str_buffer + sizeof(str_buffer) / 2) + 16;\
+ rax = 0x12345678;\
+ rcx = 17;\
+\
+ asm volatile ("pushq $0\n\t"\
+ "popfq\n\t"\
+ DF "\n\t"\
+ REP #OP size "\n\t"\
+ "cld\n\t"\
+ "pushfq\n\t"\
+ "popq %4\n\t"\
+ : "=S" (rsi), "=D" (rdi), "=a" (rax), "=c" (rcx), "=g" (rflags)\
+ : "0" (rsi), "1" (rdi), "2" (rax), "3" (rcx));\
+ xxprintf("%-10s ESI=%016llx EDI=%016llx EAX=%016llx ECX=%016llx EFL=%04llx\n",\
+ REP #OP size, rsi, rdi, rax, rcx,\
+ rflags & (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A));\
+}
+
+#define TEST_STRING(OP, REP)\
+ TEST_STRING1(OP, "b", "", REP);\
+ TEST_STRING1(OP, "w", "", REP);\
+ TEST_STRING1(OP, "l", "", REP);\
+ TEST_STRING1(OP, "b", "std", REP);\
+ TEST_STRING1(OP, "w", "std", REP);\
+ TEST_STRING1(OP, "l", "std", REP)
+
+void test_string(void)
+{
+ int64 i;
+ for(i = 0;i < sizeof(str_buffer); i++)
+ str_buffer[i] = i + 0x56;
+ TEST_STRING(stos, "");
+ TEST_STRING(stos, "rep ");
+ TEST_STRING(lods, ""); /* to verify stos */
+ // TEST_STRING(lods, "rep ");
+ TEST_STRING(movs, "");
+ TEST_STRING(movs, "rep ");
+ TEST_STRING(lods, ""); /* to verify stos */
+
+ /* XXX: better tests */
+ TEST_STRING(scas, "");
+ TEST_STRING(scas, "repz ");
+ TEST_STRING(scas, "repnz ");
+ // REINSTATE? TEST_STRING(cmps, "");
+ TEST_STRING(cmps, "repz ");
+ // REINSTATE? TEST_STRING(cmps, "repnz ");
+}
+
+int main(int argc, char **argv)
+{
+ // The three commented out test cases produce different results at different
+ // compiler optimisation levels. This suggests to me that their inline
+ // assembly is incorrect. I don't have time to investigate now, though. So
+ // they are disabled.
+ xxprintf_start();
+ test_adc();
+ test_adcx();
+ test_add();
+ test_adox();
+ test_and();
+ // test_bsx();
+ test_cmp();
+ test_dec();
+ test_fcmov();
+ test_fconst();
+ test_fenv();
+ test_floats();
+ test_inc();
+ // test_jcc();
+ test_lea();
+ test_mul();
+ test_neg();
+ test_not();
+ test_or();
+ test_rcl();
+ test_rcr();
+ test_rol();
+ test_ror();
+ test_sar();
+ test_sbb();
+ test_shl();
+ test_shr();
+ // test_string();
+ test_sub();
+ test_xor();
+ xxprintf_done();
+ // the expected MD5SUM is 66802c845574c7c69f30d29ef85f7ca3
+ return 0;
+}
diff --git a/none/tests/amd64/fb_test_amd64.h b/none/tests/amd64/fb_test_amd64.h
new file mode 100644
index 0000000..5dc4405
--- /dev/null
+++ b/none/tests/amd64/fb_test_amd64.h
@@ -0,0 +1,229 @@
+
+#define exec_op glue(exec_, OP)
+#define exec_opq glue(glue(exec_, OP), q)
+#define exec_opl glue(glue(exec_, OP), l)
+#define exec_opw glue(glue(exec_, OP), w)
+#define exec_opb glue(glue(exec_, OP), b)
+
+#define EXECOP2(size, mod, res, s1, flags) \
+ asm ("pushq %4\n\t"\
+ "popfq\n\t"\
+ stringify(OP) size " %" mod "2, %" mod "0\n\t" \
+ "pushfq\n\t"\
+ "popq %1\n\t"\
+ : "=q" (res), "=g" (flags)\
+ : "q" (s1), "0" (res), "1" (flags));
+
+#define EXECOP1(size, mod, res, flags) \
+ asm ("pushq %3\n\t"\
+ "popfq\n\t"\
+ stringify(OP) size " %" mod "0\n\t" \
+ "pushfq\n\t"\
+ "popq %1\n\t"\
+ : "=q" (res), "=g" (flags)\
+ : "0" (res), "1" (flags));
+
+#ifdef OP1
+static inline void exec_opq(int64 s0, int64 s1, int64 iflags)
+{
+ int64 res, flags;
+ res = s0;
+ flags = iflags;
+ EXECOP1("q", "q", res, flags);
+ xxprintf("%-6s A=%016llx R=%016llx CCIN=%04llx CC=%04llx\n",
+ stringify(OP) "q", s0, res, iflags, flags & CC_MASK);
+}
+static inline void exec_opl(int64 s0, int64 s1, int64 iflags)
+{
+ int64 res, flags;
+ res = s0;
+ flags = iflags;
+ EXECOP1("l", "k", res, flags);
+ xxprintf("%-6s A=%016llx R=%016llx CCIN=%04llx CC=%04llx\n",
+ stringify(OP) "l", s0, res, iflags, flags & CC_MASK);
+}
+static inline void exec_opw(int64 s0, int64 s1, int64 iflags)
+{
+ int64 res, flags;
+ res = s0;
+ flags = iflags;
+ EXECOP1("w", "w", res, flags);
+ xxprintf("%-6s A=%016llx R=%016llx CCIN=%04llx CC=%04llx\n",
+ stringify(OP) "w", s0, res, iflags, flags & CC_MASK);
+}
+static inline void exec_opb(int64 s0, int64 s1, int64 iflags)
+{
+ int64 res, flags;
+ res = s0;
+ flags = iflags;
+ EXECOP1("b", "b", res, flags);
+ xxprintf("%-6s A=%016llx R=%016llx CCIN=%04llx CC=%04llx\n",
+ stringify(OP) "b", s0, res, iflags, flags & CC_MASK);
+}
+#else
+static inline void exec_opq(int64 s0, int64 s1, int64 iflags)
+{
+ int64 res, flags;
+ res = s0;
+ flags = iflags;
+ EXECOP2("q", "q", res, s1, flags);
+ xxprintf("%-6s A=%016llx B=%016llx R=%016llx CCIN=%04llx CC=%04llx\n",
+ stringify(OP) "q", s0, s1, res, iflags, flags & CC_MASK);
+}
+
+static inline void exec_opl(int64 s0, int64 s1, int64 iflags)
+{
+ int64 res, flags;
+ res = s0;
+ flags = iflags;
+ EXECOP2("l", "k", res, s1, flags);
+ xxprintf("%-6s A=%016llx B=%016llx R=%016llx CCIN=%04llx CC=%04llx\n",
+ stringify(OP) "l", s0, s1, res, iflags, flags & CC_MASK);
+}
+#ifndef NSH
+static inline void exec_opw(int64 s0, int64 s1, int64 iflags)
+{
+ int64 res, flags;
+ res = s0;
+ flags = iflags;
+ EXECOP2("w", "w", res, s1, flags);
+ xxprintf("%-6s A=%016llx B=%016llx R=%016llx CCIN=%04llx CC=%04llx\n",
+ stringify(OP) "w", s0, s1, res, iflags, flags & CC_MASK);
+}
+
+static inline void exec_opb(int64 s0, int64 s1, int64 iflags)
+{
+ int64 res, flags;
+ res = s0;
+ flags = iflags;
+ EXECOP2("b", "b", res, s1, flags);
+ xxprintf("%-6s A=%016llx B=%016llx R=%016llx CCIN=%04llx CC=%04llx\n",
+ stringify(OP) "b", s0, s1, res, iflags, flags & CC_MASK);
+}
+#endif
+#endif
+
+void exec_op(int64 s0, int64 s1)
+{
+#if 1
+ int64 o,s,z,a,c,p,flags_in;
+ for (o = 0; o < 2; o++) {
+ for (s = 0; s < 2; s++) {
+ for (z = 0; z < 2; z++) {
+ for (a = 0; a < 2; a++) {
+ for (c = 0; c < 2; c++) {
+ for (p = 0; p < 2; p++) {
+
+ flags_in = (o ? CC_O : 0)
+ | (s ? CC_S : 0)
+ | (z ? CC_Z : 0)
+ | (a ? CC_A : 0)
+ | (c ? CC_C : 0)
+ | (p ? CC_P : 0);
+ exec_opq(s0, s1, flags_in);
+ exec_opl(s0, s1, flags_in);
+#ifndef NSH
+ exec_opw(s0, s1, flags_in);
+ exec_opb(s0, s1, flags_in);
+#endif
+ }}}}}}
+#else
+ exec_opq(s0, s1, 0);
+ exec_opl(s0, s1, 0);
+ exec_opw(s0, s1, 0);
+ exec_opb(s0, s1, 0);
+ exec_opq(s0, s1, CC_C);
+ exec_opl(s0, s1, CC_C);
+ exec_opw(s0, s1, CC_C);
+ exec_opb(s0, s1, CC_C);
+#endif
+}
+
+void glue(test_, OP)(void)
+{
+#define NVALS 57
+ int64 i, j;
+ static unsigned int val[NVALS]
+ = { 0x00, 0x01, 0x02, 0x03,
+ 0x3F, 0x40, 0x41,
+ 0x7E, 0x7F, 0x80, 0x81, 0x82,
+ 0xBF, 0xC0, 0xC1,
+ 0xFC, 0xFD, 0xFE, 0xFF,
+
+ 0xFF00, 0xFF01, 0xFF02, 0xFF03,
+ 0xFF3F, 0xFF40, 0xFF41,
+ 0xFF7E, 0xFF7F, 0xFF80, 0xFF81, 0xFF82,
+ 0xFFBF, 0xFFC0, 0xFFC1,
+ 0xFFFC, 0xFFFD, 0xFFFE, 0xFFFF,
+
+ 0xFFFFFF00, 0xFFFFFF01, 0xFFFFFF02, 0xFFFFFF03,
+ 0xFFFFFF3F, 0xFFFFFF40, 0xFFFFFF41,
+ 0xFFFFFF7E, 0xFFFFFF7F, 0xFFFFFF80, 0xFFFFFF81, 0xFFFFFF82,
+ 0xFFFFFFBF, 0xFFFFFFC0, 0xFFFFFFC1,
+ 0xFFFFFFFC, 0xFFFFFFFD, 0xFFFFFFFE, 0xFFFFFFFF
+ };
+
+ exec_op(0xabcd12345678, 0x4321812FADA);
+ exec_op(0x12345678, 0x812FADA);
+ exec_op(0xabcd00012341, 0xabcd00012341);
+ exec_op(0x12341, 0x12341);
+ exec_op(0x12341, -0x12341);
+ exec_op(0xffffffff, 0);
+ exec_op(0xffffffff, -1);
+ exec_op(0xffffffff, 1);
+ exec_op(0xffffffff, 2);
+ exec_op(0x7fffffff, 0);
+ exec_op(0x7fffffff, 1);
+ exec_op(0x7fffffff, -1);
+ exec_op(0x80000000, -1);
+ exec_op(0x80000000, 1);
+ exec_op(0x80000000, -2);
+ exec_op(0x12347fff, 0);
+ exec_op(0x12347fff, 1);
+ exec_op(0x12347fff, -1);
+ exec_op(0x12348000, -1);
+ exec_op(0x12348000, 1);
+ exec_op(0x12348000, -2);
+ exec_op(0x12347f7f, 0);
+ exec_op(0x12347f7f, 1);
+ exec_op(0x12347f7f, -1);
+ exec_op(0x12348080, -1);
+ exec_op(0x12348080, 1);
+ exec_op(0x12348080, -2);
+
+ exec_op(0xFFFFFFFFffffffff, 0);
+ exec_op(0xFFFFFFFFffffffff, -1);
+ exec_op(0xFFFFFFFFffffffff, 1);
+ exec_op(0xFFFFFFFFffffffff, 2);
+ exec_op(0x7fffffffFFFFFFFF, 0);
+ exec_op(0x7fffffffFFFFFFFF, 1);
+ exec_op(0x7fffffffFFFFFFFF, -1);
+ exec_op(0x8000000000000000, -1);
+ exec_op(0x8000000000000000, 1);
+ exec_op(0x8000000000000000, -2);
+ exec_op(0x123443217FFFFFFF, 0);
+ exec_op(0x123443217FFFFFFF, 1);
+ exec_op(0x123443217FFFFFFF, -1);
+ exec_op(0x1234432180000000, -1);
+ exec_op(0x1234432180000000, 1);
+ exec_op(0x1234432180000000, -2);
+ exec_op(0x123443217F7F7f7f, 0);
+ exec_op(0x123443217F7F7f7f, 1);
+ exec_op(0x123443217F7F7f7f, -1);
+ exec_op(0x1234432180808080, -1);
+ exec_op(0x1234432180808080, 1);
+ exec_op(0x1234432180808080, -2);
+
+#if TEST_INTEGER_VERBOSE
+ if (1)
+ for (i = 0; i < NVALS; i++)
+ for (j = 0; j < NVALS; j++)
+ exec_op(val[i], val[j]);
+#endif
+
+#undef NVALS
+}
+
+#undef OP
+#undef OP_CC
+#undef NSH
diff --git a/none/tests/amd64/fb_test_amd64.stderr.exp b/none/tests/amd64/fb_test_amd64.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/none/tests/amd64/fb_test_amd64.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/none/tests/amd64/fb_test_amd64.stdout.exp b/none/tests/amd64/fb_test_amd64.stdout.exp
new file mode 100644
index 0000000..0bdd44c
--- /dev/null
+++ b/none/tests/amd64/fb_test_amd64.stdout.exp
@@ -0,0 +1 @@
+final MD5 = 66802c845574c7c69f30d29ef85f7ca3
diff --git a/none/tests/amd64/fb_test_amd64.vgtest b/none/tests/amd64/fb_test_amd64.vgtest
new file mode 100644
index 0000000..43286d6
--- /dev/null
+++ b/none/tests/amd64/fb_test_amd64.vgtest
@@ -0,0 +1,2 @@
+prog: fb_test_amd64
+prereq: test -x fb_test_amd64 && ../../../tests/x86_amd64_features amd64-avx
diff --git a/none/tests/amd64/fb_test_amd64_muldiv.h b/none/tests/amd64/fb_test_amd64_muldiv.h
new file mode 100644
index 0000000..c681cc9
--- /dev/null
+++ b/none/tests/amd64/fb_test_amd64_muldiv.h
@@ -0,0 +1,74 @@
+
+void glue(glue(test_, OP), b)(int64 op0, int64 op1)
+{
+ int64 res, s1, s0, flags;
+ s0 = op0;
+ s1 = op1;
+ res = s0;
+ flags = 0;
+ asm ("pushq %4\n\t"
+ "popfq\n\t"
+ stringify(OP)"b %b2\n\t"
+ "pushfq\n\t"
+ "popq %1\n\t"
+ : "=a" (res), "=g" (flags)
+ : "q" (s1), "0" (res), "1" (flags));
+ xxprintf("%-10s A=%016llx B=%016llx R=%016llx CC=%04llx\n",
+ stringify(OP) "b", s0, s1, res, flags & CC_MASK);
+}
+
+void glue(glue(test_, OP), w)(int64 op0h, int64 op0, int64 op1)
+{
+ int64 res, s1, flags, resh;
+ s1 = op1;
+ resh = op0h;
+ res = op0;
+ flags = 0;
+ asm ("pushq %5\n\t"
+ "popfq\n\t"
+ stringify(OP) "w %w3\n\t"
+ "pushfq\n\t"
+ "popq %1\n\t"
+ : "=a" (res), "=g" (flags), "=d" (resh)
+ : "q" (s1), "0" (res), "1" (flags), "2" (resh));
+ xxprintf("%-10s AH=%016llx AL=%016llx B=%016llx RH=%016llx RL=%016llx CC=%04llx\n",
+ stringify(OP) "w", op0h, op0, s1, resh, res, flags & CC_MASK);
+}
+
+void glue(glue(test_, OP), l)(int64 op0h, int64 op0, int64 op1)
+{
+ int64 res, s1, flags, resh;
+ s1 = op1;
+ resh = op0h;
+ res = op0;
+ flags = 0;
+ asm ("pushq %5\n\t"
+ "popfq\n\t"
+ stringify(OP) "l %3\n\t"
+ "pushfq\n\t"
+ "popq %1\n\t"
+ : "=a" (res), "=g" (flags), "=d" (resh)
+ : "q" ((int)s1), "0" (res), "1" (flags), "2" (resh));
+ xxprintf("%-10s AH=%016llx AL=%016llx B=%016llx RH=%016llx RL=%016llx CC=%04llx\n",
+ stringify(OP) "l", op0h, op0, s1, resh, res, flags & CC_MASK);
+}
+
+void glue(glue(test_, OP), q)(int64 op0h, int64 op0, int64 op1)
+{
+ int64 res, s1, flags, resh;
+ s1 = op1;
+ resh = op0h;
+ res = op0;
+ flags = 0;
+ asm ("pushq %5\n\t"
+ "popfq\n\t"
+ stringify(OP) "q %3\n\t"
+ "pushfq\n\t"
+ "popq %1\n\t"
+ : "=a" (res), "=g" (flags), "=d" (resh)
+ : "q" (s1), "0" (res), "1" (flags), "2" (resh));
+ xxprintf("%-10s AH=%016llx AL=%016llx B=%016llx RH=%016llx RL=%016llx CC=%04llx\n",
+ stringify(OP) "q", op0h, op0, s1, resh, res, flags & CC_MASK);
+}
+
+#undef OP
diff --git a/none/tests/amd64/fb_test_amd64_shift.h b/none/tests/amd64/fb_test_amd64_shift.h
new file mode 100644
index 0000000..4bc495a
--- /dev/null
+++ b/none/tests/amd64/fb_test_amd64_shift.h
@@ -0,0 +1,176 @@
+
+#define exec_op glue(exec_, OP)
+#define exec_opq glue(glue(exec_, OP), q)
+#define exec_opl glue(glue(exec_, OP), l)
+#define exec_opw glue(glue(exec_, OP), w)
+#define exec_opb glue(glue(exec_, OP), b)
+
+#ifndef OP_SHIFTD
+
+#ifdef OP_NOBYTE
+#define EXECSHIFT(size, res, s1, s2, flags) \
+ asm ("pushq %4\n\t"\
+ "popfq\n\t"\
+ stringify(OP) size " %" size "2, %" size "0\n\t" \
+ "pushfq\n\t"\
+ "popq %1\n\t"\
+ : "=g" (res), "=g" (flags)\
+ : "r" (s1), "0" (res), "1" (flags));
+#else
+#define EXECSHIFT(size, res, s1, s2, flags) \
+ asm ("pushq %4\n\t"\
+ "popfq\n\t"\
+ stringify(OP) size " %%cl, %" size "0\n\t" \
+ "pushfq\n\t"\
+ "popq %1\n\t"\
+ : "=q" (res), "=g" (flags)\
+ : "c" (s1), "0" (res), "1" (flags));
+#endif
+
+void exec_opq(int64 s2, int64 s0, int64 s1, int64 iflags)
+{
+ int64 res, flags;
+ res = s0;
+ flags = iflags;
+ EXECSHIFT("q", res, s1, s2, flags);
+ /* overflow is undefined if count != 1 */
+ if (s1 != 1)
+ flags &= ~CC_O;
+ xxprintf("%-10s A=%016llx B=%016llx R=%016llx CCIN=%04llx CC=%04llx\n",
+ stringify(OP) "q", s0, s1, res, iflags, flags & CC_MASK);
+}
+
+void exec_opl(int64 s2, int64 s0, int64 s1, int64 iflags)
+{
+ int64 res, flags;
+ res = s0;
+ flags = iflags;
+ EXECSHIFT("", res, s1, s2, flags);
+ /* overflow is undefined if count != 1 */
+ if (s1 != 1)
+ flags &= ~CC_O;
+ xxprintf("%-10s A=%016llx B=%016llx R=%016llx CCIN=%04llx CC=%04llx\n",
+ stringify(OP) "l", s0, s1, res, iflags, flags & CC_MASK);
+}
+
+void exec_opw(int64 s2, int64 s0, int64 s1, int64 iflags)
+{
+ int64 res, flags;
+ res = s0;
+ flags = iflags;
+ EXECSHIFT("w", res, s1, s2, flags);
+ /* overflow is undefined if count != 1 */
+ if (s1 != 1)
+ flags &= ~CC_O;
+ xxprintf("%-10s A=%016llx B=%016llx R=%016llx CCIN=%04llx CC=%04llx\n",
+ stringify(OP) "w", s0, s1, res, iflags, flags & CC_MASK);
+}
+
+#else
+#define EXECSHIFT(size, res, s1, s2, flags) \
+ asm ("pushq %4\n\t"\
+ "popfq\n\t"\
+ stringify(OP) size " %%cl, %" size "5, %" size "0\n\t" \
+ "pushfq\n\t"\
+ "popq %1\n\t"\
+ : "=g" (res), "=g" (flags)\
+ : "c" (s1), "0" (res), "1" (flags), "r" (s2));
+
+void exec_opl(int64 s2, int64 s0, int64 s1, int64 iflags)
+{
+ int64 res, flags;
+ res = s0;
+ flags = iflags;
+ EXECSHIFT("", res, s1, s2, flags);
+ /* overflow is undefined if count != 1 */
+ if (s1 != 1)
+ flags &= ~CC_O;
+ xxprintf("%-10s A=%016llx B=%016llx C=%016llx R=%016llx CCIN=%04llx CC=%04llx\n",
+ stringify(OP) "l", s0, s2, s1, res, iflags, flags & CC_MASK);
+}
+
+void exec_opw(int64 s2, int64 s0, int64 s1, int64 iflags)
+{
+ int64 res, flags;
+ res = s0;
+ flags = iflags;
+ EXECSHIFT("w", res, s1, s2, flags);
+ /* overflow is undefined if count != 1 */
+ if (s1 != 1)
+ flags &= ~CC_O;
+ xxprintf("%-10s A=%016llx B=%016llx C=%016llx R=%016llx CCIN=%04llx CC=%04llx\n",
+ stringify(OP) "w", s0, s2, s1, res, iflags, flags & CC_MASK);
+}
+
+#endif
+
+#ifndef OP_NOBYTE
+void exec_opb(int64 s0, int64 s1, int64 iflags)
+{
+ int64 res, flags;
+ res = s0;
+ flags = iflags;
+ EXECSHIFT("b", res, s1, 0, flags);
+ /* overflow is undefined if count != 1 */
+ if (s1 != 1)
+ flags &= ~CC_O;
+ xxprintf("%-10s A=%016llx B=%016llx R=%016llx CCIN=%04llx CC=%04llx\n",
+ stringify(OP) "b", s0, s1, res, iflags, flags & CC_MASK);
+}
+#endif
+
+void exec_op(int64 s2, int64 s0, int64 s1)
+{
+ int64 o,s,z,a,c,p,flags_in;
+ for (o = 0; o < 2; o++) {
+ for (s = 0; s < 2; s++) {
+ for (z = 0; z < 2; z++) {
+ for (a = 0; a < 2; a++) {
+ for (c = 0; c < 2; c++) {
+ for (p = 0; p < 2; p++) {
+
+ flags_in = (o ? CC_O : 0)
+ | (s ? CC_S : 0)
+ | (z ? CC_Z : 0)
+ | (a ? CC_A : 0)
+ | (c ? CC_C : 0)
+ | (p ? CC_P : 0);
+
+ exec_opq(s2, s0, s1, flags_in);
+ if (s1 <= 31)
+ exec_opl(s2, s0, s1, flags_in);
+#ifdef OP_SHIFTD
+ if (s1 <= 15)
+ exec_opw(s2, s0, s1, flags_in);
+#else
+ exec_opw(s2, s0, s1, flags_in);
+#endif
+#ifndef OP_NOBYTE
+ exec_opb(s0, s1, flags_in);
+#endif
+#ifdef OP_CC
+ exec_opq(s2, s0, s1, flags_in);
+ exec_opl(s2, s0, s1, flags_in);
+ exec_opw(s2, s0, s1, flags_in);
+ exec_opb(s0, s1, flags_in);
+#endif
+
+ }}}}}}
+
+}
+
+void glue(test_, OP)(void)
+{
+ int64 i;
+ for(i = 0; i < 64; i++)
+ exec_op(0x3141592721ad3d34, 0x2718284612345678, i);
+ for(i = 0; i < 64; i++)
+ exec_op(0x31415927813f3421, 0x2718284682345678, i);
+}
+
+#undef OP
+#undef OP_CC
+#undef OP_SHIFTD
+#undef OP_NOBYTE
+#undef EXECSHIFT
+
diff --git a/none/tests/amd64/pcmpstr64.c b/none/tests/amd64/pcmpstr64.c
index a76ec55..9feae45 100644
--- a/none/tests/amd64/pcmpstr64.c
+++ b/none/tests/amd64/pcmpstr64.c
@@ -205,7 +205,7 @@
switch (imm8) {
case 0x00: case 0x02:
case 0x08: case 0x0A: case 0x0C: case 0x0E:
- case 0x12: case 0x14:
+ case 0x10: case 0x12: case 0x14:
case 0x18: case 0x1A:
case 0x30: case 0x34:
case 0x38: case 0x3A:
@@ -2217,6 +2217,88 @@
//////////////////////////////////////////////////////////
// //
+// ISTRI_10 //
+// //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_10 ( V128* argL, V128* argR )
+{
+ V128 block[2];
+ memcpy(&block[0], argL, sizeof(V128));
+ memcpy(&block[1], argR, sizeof(V128));
+ ULong res, flags;
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu 0(%2), %%xmm2" "\n\t"
+ "movdqu 16(%2), %%xmm11" "\n\t"
+ "pcmpistri $0x10, %%xmm2, %%xmm11" "\n\t"
+//"pcmpistrm $0x10, %%xmm2, %%xmm11" "\n\t"
+//"movd %%xmm0, %%ecx" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%rdx" "\n\t"
+ "movq %%rcx, %0" "\n\t"
+ "movq %%rdx, %1" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+ : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+ );
+ return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_10 ( V128* argLU, V128* argRU )
+{
+ V128 resV;
+ UInt resOSZACP, resECX;
+ Bool ok
+ = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU,
+ zmask_from_V128(argLU),
+ zmask_from_V128(argRU),
+ 0x10, False/*!isSTRM*/
+ );
+ assert(ok);
+ resECX = resV.uInt[0];
+ return (resOSZACP << 16) | resECX;
+}
+
+void istri_10 ( void )
+{
+ char* wot = "10";
+ UInt(*h)(V128*,V128*) = h_pcmpistri_10;
+ UInt(*s)(V128*,V128*) = s_pcmpistri_10;
+
+ try_istri(wot,h,s, "abcdacbdabcdabcd", "000000000000000a");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000000b");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "00000000000000ab");
+ try_istri(wot,h,s, "abcdabc0abcdabcd", "000000000000abcd");
+
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "0bcdabcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "abcdabcdabcda0cd", "000000000000abcd");
+ try_istri(wot,h,s, "abcdabcdabcdab0d", "000000000000abcd");
+ try_istri(wot,h,s, "abcdabcdabcdabc0", "000000000000abcd");
+
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000a0cd");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000ab0d");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abc0");
+
+ try_istri(wot,h,s, "0000000000000000", "0000000000000000");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000dcba");
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000bbbb");
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000baba");
+
+ try_istri(wot,h,s, "0000abcdabcdabcd", "00000000000baba0");
+
+ try_istri(wot,h,s, "0ddc0ffeebadf00d", "00000000cafebabe");
+ try_istri(wot,h,s, "0ddc0ffeebadfeed", "00000000cafebabe");
+}
+
+
+//////////////////////////////////////////////////////////
+// //
// main //
// //
//////////////////////////////////////////////////////////
@@ -2244,5 +2326,6 @@
istri_70();
istri_62();
istri_72();
+ istri_10();
return 0;
}
diff --git a/none/tests/amd64/pcmpstr64.stdout.exp b/none/tests/amd64/pcmpstr64.stdout.exp
index ae006e1..fc37516 100644
--- a/none/tests/amd64/pcmpstr64.stdout.exp
+++ b/none/tests/amd64/pcmpstr64.stdout.exp
@@ -524,3 +524,25 @@
istri 72 0000abcdabcdabcd 00000000000baba0 -> 08c1000b 08c1000b
istri 72 0ddc0ffeebadf00d 00000000cafebabe -> 08c10000 08c10000
istri 72 0ddc0ffeebadfeed 00000000cafebabe -> 08c10004 08c10004
+istri 10 abcdacbdabcdabcd 000000000000000a -> 08810000 08810000
+istri 10 abcdabcdabcdabcd 000000000000000b -> 08810000 08810000
+istri 10 abcdabcdabcdabcd 00000000000000ab -> 08810000 08810000
+istri 10 abcdabc0abcdabcd 000000000000abcd -> 00c10008 00c10008
+istri 10 abcdabcdabcdabcd 000000000000abcd -> 00800010 00800010
+istri 10 0bcdabcdabcdabcd 000000000000abcd -> 00c1000f 00c1000f
+istri 10 abcdabcdabcda0cd 000000000000abcd -> 00c10002 00c10002
+istri 10 abcdabcdabcdab0d 000000000000abcd -> 00c10001 00c10001
+istri 10 abcdabcdabcdabc0 000000000000abcd -> 08c10000 08c10000
+istri 10 abcdabcdabcdabcd 000000000000abcd -> 00800010 00800010
+istri 10 abcdabcdabcdabcd 000000000000a0cd -> 00810002 00810002
+istri 10 abcdabcdabcdabcd 000000000000ab0d -> 00810001 00810001
+istri 10 abcdabcdabcdabcd 000000000000abc0 -> 08810000 08810000
+istri 10 0000000000000000 0000000000000000 -> 08c10000 08c10000
+istri 10 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00000010 00000010
+istri 10 0000abcdabcdabcd 000000000000abcd -> 00c1000c 00c1000c
+istri 10 0000abcdabcdabcd 000000000000dcba -> 00c1000c 00c1000c
+istri 10 0000abcdabcdabcd 000000000000bbbb -> 08c10000 08c10000
+istri 10 0000abcdabcdabcd 000000000000baba -> 08c10000 08c10000
+istri 10 0000abcdabcdabcd 00000000000baba0 -> 08c10000 08c10000
+istri 10 0ddc0ffeebadf00d 00000000cafebabe -> 08c10000 08c10000
+istri 10 0ddc0ffeebadfeed 00000000cafebabe -> 08c10000 08c10000
diff --git a/none/tests/arm/Makefile.am b/none/tests/arm/Makefile.am
index 7b10de8..4776ea7 100644
--- a/none/tests/arm/Makefile.am
+++ b/none/tests/arm/Makefile.am
@@ -14,6 +14,8 @@
v6media.stdout.exp v6media.stderr.exp v6media.vgtest \
v8crypto_a.stdout.exp v8crypto_a.stderr.exp v8crypto_a.vgtest \
v8crypto_t.stdout.exp v8crypto_t.stderr.exp v8crypto_t.vgtest \
+ v8fpsimd_a.stdout.exp v8fpsimd_a.stderr.exp v8fpsimd_a.vgtest \
+ v8fpsimd_t.stdout.exp v8fpsimd_t.stderr.exp v8fpsimd_t.vgtest \
v8memory_a.stdout.exp v8memory_a.stderr.exp v8memory_a.vgtest \
v8memory_t.stdout.exp v8memory_t.stderr.exp v8memory_t.vgtest \
vcvt_fixed_float_VFP.stdout.exp vcvt_fixed_float_VFP.stderr.exp \
@@ -33,6 +35,8 @@
v6media \
v8crypto_a \
v8crypto_t \
+ v8fpsimd_a \
+ v8fpsimd_t \
v8memory_a \
v8memory_t \
vcvt_fixed_float_VFP \
@@ -60,6 +64,9 @@
v8crypto_a_CFLAGS = $(AM_CFLAGS) -g -O0 -mfpu=crypto-neon-fp-armv8 -marm
v8crypto_t_CFLAGS = $(AM_CFLAGS) -g -O0 -mfpu=crypto-neon-fp-armv8 -mthumb
+v8fpsimd_a_CFLAGS = $(AM_CFLAGS) -g -O0 -mfpu=crypto-neon-fp-armv8 -marm
+v8fpsimd_t_CFLAGS = $(AM_CFLAGS) -g -O0 -mfpu=crypto-neon-fp-armv8 -mthumb
+
v8memory_a_CFLAGS = $(AM_CFLAGS) -g -O0 \
-march=armv8-a -mfpu=crypto-neon-fp-armv8 -marm
v8memory_t_CFLAGS = $(AM_CFLAGS) -g -O0 \
diff --git a/none/tests/arm/Makefile.in b/none/tests/arm/Makefile.in
index 86754f2..8820af7 100644
--- a/none/tests/arm/Makefile.in
+++ b/none/tests/arm/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -123,9 +123,9 @@
check_PROGRAMS = allexec$(EXEEXT) intdiv$(EXEEXT) ldrt$(EXEEXT) \
ldrt_arm$(EXEEXT) neon128$(EXEEXT) neon64$(EXEEXT) \
v6intARM$(EXEEXT) v6intThumb$(EXEEXT) v6media$(EXEEXT) \
- v8crypto_a$(EXEEXT) v8crypto_t$(EXEEXT) v8memory_a$(EXEEXT) \
- v8memory_t$(EXEEXT) vcvt_fixed_float_VFP$(EXEEXT) vfp$(EXEEXT) \
- vfpv4_fma$(EXEEXT)
+ v8crypto_a$(EXEEXT) v8crypto_t$(EXEEXT) v8fpsimd_a$(EXEEXT) \
+ v8fpsimd_t$(EXEEXT) v8memory_a$(EXEEXT) v8memory_t$(EXEEXT) \
+ vcvt_fixed_float_VFP$(EXEEXT) vfp$(EXEEXT) vfpv4_fma$(EXEEXT)
subdir = none/tests/arm
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/configure.ac
@@ -192,6 +192,16 @@
v8crypto_t_LDADD = $(LDADD)
v8crypto_t_LINK = $(CCLD) $(v8crypto_t_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
$(LDFLAGS) -o $@
+v8fpsimd_a_SOURCES = v8fpsimd_a.c
+v8fpsimd_a_OBJECTS = v8fpsimd_a-v8fpsimd_a.$(OBJEXT)
+v8fpsimd_a_LDADD = $(LDADD)
+v8fpsimd_a_LINK = $(CCLD) $(v8fpsimd_a_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+v8fpsimd_t_SOURCES = v8fpsimd_t.c
+v8fpsimd_t_OBJECTS = v8fpsimd_t-v8fpsimd_t.$(OBJEXT)
+v8fpsimd_t_LDADD = $(LDADD)
+v8fpsimd_t_LINK = $(CCLD) $(v8fpsimd_t_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
v8memory_a_SOURCES = v8memory_a.c
v8memory_a_OBJECTS = v8memory_a-v8memory_a.$(OBJEXT)
v8memory_a_LDADD = $(LDADD)
@@ -250,12 +260,12 @@
am__v_CCLD_1 =
SOURCES = allexec.c intdiv.c ldrt.c ldrt_arm.c neon128.c neon64.c \
v6intARM.c v6intThumb.c v6media.c v8crypto_a.c v8crypto_t.c \
- v8memory_a.c v8memory_t.c vcvt_fixed_float_VFP.c vfp.c \
- vfpv4_fma.c
+ v8fpsimd_a.c v8fpsimd_t.c v8memory_a.c v8memory_t.c \
+ vcvt_fixed_float_VFP.c vfp.c vfpv4_fma.c
DIST_SOURCES = allexec.c intdiv.c ldrt.c ldrt_arm.c neon128.c neon64.c \
v6intARM.c v6intThumb.c v6media.c v8crypto_a.c v8crypto_t.c \
- v8memory_a.c v8memory_t.c vcvt_fixed_float_VFP.c vfp.c \
- vfpv4_fma.c
+ v8fpsimd_a.c v8fpsimd_t.c v8memory_a.c v8memory_t.c \
+ vcvt_fixed_float_VFP.c vfp.c vfpv4_fma.c
am__can_run_installinfo = \
case $$AM_UPDATE_INFO_DIR in \
n|no|NO) false;; \
@@ -327,6 +337,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -497,6 +508,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -507,6 +519,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -581,8 +594,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -627,7 +638,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
@@ -661,6 +671,8 @@
v6media.stdout.exp v6media.stderr.exp v6media.vgtest \
v8crypto_a.stdout.exp v8crypto_a.stderr.exp v8crypto_a.vgtest \
v8crypto_t.stdout.exp v8crypto_t.stderr.exp v8crypto_t.vgtest \
+ v8fpsimd_a.stdout.exp v8fpsimd_a.stderr.exp v8fpsimd_a.vgtest \
+ v8fpsimd_t.stdout.exp v8fpsimd_t.stderr.exp v8fpsimd_t.vgtest \
v8memory_a.stdout.exp v8memory_a.stderr.exp v8memory_a.vgtest \
v8memory_t.stdout.exp v8memory_t.stderr.exp v8memory_t.vgtest \
vcvt_fixed_float_VFP.stdout.exp vcvt_fixed_float_VFP.stderr.exp \
@@ -682,6 +694,8 @@
v6media_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 -mthumb
v8crypto_a_CFLAGS = $(AM_CFLAGS) -g -O0 -mfpu=crypto-neon-fp-armv8 -marm
v8crypto_t_CFLAGS = $(AM_CFLAGS) -g -O0 -mfpu=crypto-neon-fp-armv8 -mthumb
+v8fpsimd_a_CFLAGS = $(AM_CFLAGS) -g -O0 -mfpu=crypto-neon-fp-armv8 -marm
+v8fpsimd_t_CFLAGS = $(AM_CFLAGS) -g -O0 -mfpu=crypto-neon-fp-armv8 -mthumb
v8memory_a_CFLAGS = $(AM_CFLAGS) -g -O0 \
-march=armv8-a -mfpu=crypto-neon-fp-armv8 -marm
@@ -786,6 +800,14 @@
@rm -f v8crypto_t$(EXEEXT)
$(AM_V_CCLD)$(v8crypto_t_LINK) $(v8crypto_t_OBJECTS) $(v8crypto_t_LDADD) $(LIBS)
+v8fpsimd_a$(EXEEXT): $(v8fpsimd_a_OBJECTS) $(v8fpsimd_a_DEPENDENCIES) $(EXTRA_v8fpsimd_a_DEPENDENCIES)
+ @rm -f v8fpsimd_a$(EXEEXT)
+ $(AM_V_CCLD)$(v8fpsimd_a_LINK) $(v8fpsimd_a_OBJECTS) $(v8fpsimd_a_LDADD) $(LIBS)
+
+v8fpsimd_t$(EXEEXT): $(v8fpsimd_t_OBJECTS) $(v8fpsimd_t_DEPENDENCIES) $(EXTRA_v8fpsimd_t_DEPENDENCIES)
+ @rm -f v8fpsimd_t$(EXEEXT)
+ $(AM_V_CCLD)$(v8fpsimd_t_LINK) $(v8fpsimd_t_OBJECTS) $(v8fpsimd_t_LDADD) $(LIBS)
+
v8memory_a$(EXEEXT): $(v8memory_a_OBJECTS) $(v8memory_a_DEPENDENCIES) $(EXTRA_v8memory_a_DEPENDENCIES)
@rm -f v8memory_a$(EXEEXT)
$(AM_V_CCLD)$(v8memory_a_LINK) $(v8memory_a_OBJECTS) $(v8memory_a_LDADD) $(LIBS)
@@ -823,6 +845,8 @@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/v6media-v6media.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/v8crypto_a-v8crypto_a.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/v8crypto_t-v8crypto_t.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/v8fpsimd_a-v8fpsimd_a.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/v8fpsimd_t-v8fpsimd_t.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/v8memory_a-v8memory_a.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/v8memory_t-v8memory_t.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vcvt_fixed_float_VFP.Po@am__quote@
@@ -999,6 +1023,34 @@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v8crypto_t_CFLAGS) $(CFLAGS) -c -o v8crypto_t-v8crypto_t.obj `if test -f 'v8crypto_t.c'; then $(CYGPATH_W) 'v8crypto_t.c'; else $(CYGPATH_W) '$(srcdir)/v8crypto_t.c'; fi`
+v8fpsimd_a-v8fpsimd_a.o: v8fpsimd_a.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v8fpsimd_a_CFLAGS) $(CFLAGS) -MT v8fpsimd_a-v8fpsimd_a.o -MD -MP -MF $(DEPDIR)/v8fpsimd_a-v8fpsimd_a.Tpo -c -o v8fpsimd_a-v8fpsimd_a.o `test -f 'v8fpsimd_a.c' || echo '$(srcdir)/'`v8fpsimd_a.c
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/v8fpsimd_a-v8fpsimd_a.Tpo $(DEPDIR)/v8fpsimd_a-v8fpsimd_a.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='v8fpsimd_a.c' object='v8fpsimd_a-v8fpsimd_a.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v8fpsimd_a_CFLAGS) $(CFLAGS) -c -o v8fpsimd_a-v8fpsimd_a.o `test -f 'v8fpsimd_a.c' || echo '$(srcdir)/'`v8fpsimd_a.c
+
+v8fpsimd_a-v8fpsimd_a.obj: v8fpsimd_a.c
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+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/v8fpsimd_a-v8fpsimd_a.Tpo $(DEPDIR)/v8fpsimd_a-v8fpsimd_a.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='v8fpsimd_a.c' object='v8fpsimd_a-v8fpsimd_a.obj' libtool=no @AMDEPBACKSLASH@
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+
+v8fpsimd_t-v8fpsimd_t.o: v8fpsimd_t.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v8fpsimd_t_CFLAGS) $(CFLAGS) -MT v8fpsimd_t-v8fpsimd_t.o -MD -MP -MF $(DEPDIR)/v8fpsimd_t-v8fpsimd_t.Tpo -c -o v8fpsimd_t-v8fpsimd_t.o `test -f 'v8fpsimd_t.c' || echo '$(srcdir)/'`v8fpsimd_t.c
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/v8fpsimd_t-v8fpsimd_t.Tpo $(DEPDIR)/v8fpsimd_t-v8fpsimd_t.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='v8fpsimd_t.c' object='v8fpsimd_t-v8fpsimd_t.o' libtool=no @AMDEPBACKSLASH@
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+
+v8fpsimd_t-v8fpsimd_t.obj: v8fpsimd_t.c
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+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/v8fpsimd_t-v8fpsimd_t.Tpo $(DEPDIR)/v8fpsimd_t-v8fpsimd_t.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='v8fpsimd_t.c' object='v8fpsimd_t-v8fpsimd_t.obj' libtool=no @AMDEPBACKSLASH@
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+
v8memory_a-v8memory_a.o: v8memory_a.c
@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v8memory_a_CFLAGS) $(CFLAGS) -MT v8memory_a-v8memory_a.o -MD -MP -MF $(DEPDIR)/v8memory_a-v8memory_a.Tpo -c -o v8memory_a-v8memory_a.o `test -f 'v8memory_a.c' || echo '$(srcdir)/'`v8memory_a.c
@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/v8memory_a-v8memory_a.Tpo $(DEPDIR)/v8memory_a-v8memory_a.Po
diff --git a/none/tests/arm/v8fpsimd_a.c b/none/tests/arm/v8fpsimd_a.c
new file mode 100644
index 0000000..ee7eeb2
--- /dev/null
+++ b/none/tests/arm/v8fpsimd_a.c
@@ -0,0 +1,553 @@
+
+/*
+gcc -o v8fpsimd_a v8fpsimd_a.c -march=armv8-a -mfpu=crypto-neon-fp-armv8 \
+ -I../../.. -Wall -g -marm
+
+gcc -o v8fpsimd_t v8fpsimd_a.c -march=armv8-a -mfpu=crypto-neon-fp-armv8 \
+ -I../../.. -Wall -g
+*/
+
+#include <stdio.h>
+#include <assert.h>
+#include <malloc.h> // memalign
+#include <string.h> // memset
+#include "tests/malloc.h"
+#include <math.h> // isnormal
+
+typedef unsigned char UChar;
+typedef unsigned short int UShort;
+typedef unsigned int UInt;
+typedef signed int Int;
+typedef unsigned char UChar;
+typedef unsigned long long int ULong;
+typedef signed long long int Long;
+typedef double Double;
+typedef float Float;
+
+typedef unsigned char Bool;
+#define False ((Bool)0)
+#define True ((Bool)1)
+
+
+#define ITERS 1
+
+typedef
+ enum { TyHF=1234, TySF, TyDF, TyB, TyH, TyS, TyD, TyNONE }
+ LaneTy;
+
+union _V128 {
+ UChar u8[16];
+ UShort u16[8];
+ UInt u32[4];
+ ULong u64[2];
+ Float f32[4];
+ Double f64[2];
+};
+typedef union _V128 V128;
+
+static inline UChar randUChar ( void )
+{
+ static UInt seed = 80021;
+ seed = 1103515245 * seed + 12345;
+ return (seed >> 17) & 0xFF;
+}
+
+//static ULong randULong ( LaneTy ty )
+//{
+// Int i;
+// ULong r = 0;
+// for (i = 0; i < 8; i++) {
+// r = (r << 8) | (ULong)(0xFF & randUChar());
+// }
+// return r;
+//}
+
+/* Generates a random V128. Ensures that that it contains normalised
+ FP numbers when viewed as either F32x4 or F64x2, so that it is
+ reasonable to use in FP test cases. */
+static void randV128 ( /*OUT*/V128* v, LaneTy ty )
+{
+ static UInt nCalls = 0, nIters = 0;
+ Int i;
+ nCalls++;
+ while (1) {
+ nIters++;
+ for (i = 0; i < 16; i++) {
+ v->u8[i] = randUChar();
+ }
+ if (randUChar() < 32) {
+ /* once every 8 times, clone one of the lanes */
+ switch (ty) {
+ case TySF: case TyS: {
+ UInt l1, l2;
+ while (1) {
+ l1 = randUChar() & 3;
+ l2 = randUChar() & 3;
+ if (l1 != l2) break;
+ }
+ assert(l1 < 4 && l2 < 4);
+ v->u32[l1] = v->u32[l2];
+ printf("randV128: doing v->u32[%u] = v->u32[%u]\n", l1, l2);
+ break;
+ }
+ case TyDF: case TyD: {
+ UInt l1, l2;
+ while (1) {
+ l1 = randUChar() & 1;
+ l2 = randUChar() & 1;
+ if (l1 != l2) break;
+ }
+ assert(l1 < 2 && l2 < 2);
+ printf("randV128: doing v->u64[%u] = v->u64[%u]\n", l1, l2);
+ v->u64[l1] = v->u64[l2];
+ break;
+ }
+ default:
+ break;
+ }
+ }
+ if (isnormal(v->f32[0]) && isnormal(v->f32[1]) && isnormal(v->f32[2])
+ && isnormal(v->f32[3]) && isnormal(v->f64[0]) && isnormal(v->f64[1]))
+ break;
+ }
+ if (0 == (nCalls & 0xFF))
+ printf("randV128: %u calls, %u iters\n", nCalls, nIters);
+}
+
+static void showV128 ( V128* v )
+{
+ Int i;
+ for (i = 15; i >= 0; i--)
+ printf("%02x", (Int)v->u8[i]);
+}
+
+//static void showBlock ( const char* msg, V128* block, Int nBlock )
+//{
+// Int i;
+// printf("%s\n", msg);
+// for (i = 0; i < nBlock; i++) {
+// printf(" ");
+// showV128(&block[i]);
+// printf("\n");
+// }
+//}
+
+
+/* ---------------------------------------------------------------- */
+/* -- Parameterisable test macros -- */
+/* ---------------------------------------------------------------- */
+
+#define DO50(_action) \
+ do { \
+ Int _qq; for (_qq = 0; _qq < 50; _qq++) { _action ; } \
+ } while (0)
+
+
+/* Are we compiling for thumb or arm encodings? This has a bearing
+ on the inline assembly syntax needed below. */
+
+#if defined(__thumb__) || defined(__thumb2__)
+# define IT_EQ "it eq ; "
+# define IT_NE "it ne ; "
+# define IT_AL /* */
+#else
+# define IT_EQ /* */
+# define IT_NE /* */
+# define IT_AL /* */
+#endif
+
+
+/* Generate a test that involves two vector regs,
+ with no bias as towards which is input or output.
+ It's OK to use r8 as scratch.
+
+ Note that the insn doesn't *have* to use Q (128 bit) registers --
+ it can instead mention D (64 bit) and S (32-bit) registers.
+ However, in that case callers of this macro must be very careful to
+ specify QVECREG1NO and QVECREG2NO in such a way as to cover all of
+ the mentioned D and S registers, using the relations
+
+ D<n> == S<2n+1> and S<2n>
+ Q<n> == D<2n+1> and D<2n>
+
+ Failing to do so correctly will make the test meaningless, because
+ it will potentially load test data into the wrong registers before
+ the test, and/or show the values of the wrong registers after the
+ test. The allowed register values are:
+ S: 0 .. 31
+ D: 0 .. 31
+ Q: 0 .. 15
+ Note that Q[15..0] == D[31..0] but S[31..0] only overlaps Q[0..7],
+ so a Q value of 8 or above is definitely invalid for a S register.
+ None of this is checked, though, so be careful when creating the
+ Q numbers.
+
+ It would be clearer and easier to write the Q numbers using integer
+ division. For example, in
+
+ GEN_TWOVEC_QDS_TEST(vcvtn_s32_f64, "vcvtn.s32.f64 s27, d5", 6,2)
+
+ instead of writing "6, 2" at the end, write "(27/4), (5/2)". This
+ would make clear the connection between the register numbers and
+ the Q numbers. Unfortunately those expressions need to expanded to
+ single digits at C-preprocessing time, and cpp won't do that. So
+ we have to do it the hard and error-prone way.
+*/
+#define GEN_TWOVEC_QDS_TEST(TESTNAME,INSN_PRE,INSN, \
+ QVECREG1NO,QVECREG2NO) \
+ __attribute__((noinline)) \
+ static void test_##TESTNAME ( LaneTy ty ) { \
+ Int i; \
+ assert(QVECREG1NO >= 0 && QVECREG1NO <= 15); \
+ assert(QVECREG2NO >= 0 && QVECREG2NO <= 15); \
+ for (i = 0; i < ITERS; i++) { \
+ V128 block[4+1]; \
+ memset(block, 0x55, sizeof(block)); \
+ randV128(&block[0], ty); \
+ randV128(&block[1], ty); \
+ randV128(&block[2], ty); \
+ randV128(&block[3], ty); \
+ __asm__ __volatile__( \
+ "mov r9, #0 ; vmsr fpscr, r9 ; " \
+ "msr apsr_nzcvq, r9 ; " \
+ "add r9, %0, #0 ; vld1.8 { q"#QVECREG1NO" }, [r9] ; " \
+ "add r9, %0, #16 ; vld1.8 { q"#QVECREG2NO" }, [r9] ; " \
+ INSN_PRE INSN " ; " \
+ "add r9, %0, #32 ; vst1.8 { q"#QVECREG1NO" }, [r9] ; " \
+ "add r9, %0, #48 ; vst1.8 { q"#QVECREG2NO" }, [r9] ; " \
+ "vmrs r9, fpscr ; str r9, [%0, #64] " \
+ : : "r"(&block[0]) \
+ : "cc", "memory", "q"#QVECREG1NO, "q"#QVECREG2NO, "r8", "r9" \
+ ); \
+ /* Don't use INSN_PRE in printing, since that differs */ \
+ /* between ARM and Thumb and hence makes their outputs differ. */ \
+ printf(INSN " "); \
+ UInt fpscr = 0xFFFFFFE0 & block[4].u32[0]; \
+ showV128(&block[0]); printf(" "); \
+ showV128(&block[1]); printf(" "); \
+ showV128(&block[2]); printf(" "); \
+ showV128(&block[3]); printf(" fpscr=%08x\n", fpscr); \
+ } \
+ }
+
+
+/* Generate a test that involves three vector regs,
+ with no bias as towards which is input or output. It's also OK
+ to use r8 as scratch. */
+#define GEN_THREEVEC_QDS_TEST(TESTNAME,INSN_PRE, \
+ INSN,QVECREG1NO,QVECREG2NO,QVECREG3NO) \
+ __attribute__((noinline)) \
+ static void test_##TESTNAME ( LaneTy ty ) { \
+ Int i; \
+ assert(QVECREG1NO >= 0 && QVECREG1NO <= 15); \
+ assert(QVECREG2NO >= 0 && QVECREG2NO <= 15); \
+ assert(QVECREG3NO >= 0 && QVECREG3NO <= 15); \
+ for (i = 0; i < ITERS; i++) { \
+ V128 block[6+1]; \
+ memset(block, 0x55, sizeof(block)); \
+ randV128(&block[0], ty); \
+ randV128(&block[1], ty); \
+ randV128(&block[2], ty); \
+ randV128(&block[3], ty); \
+ randV128(&block[4], ty); \
+ randV128(&block[5], ty); \
+ __asm__ __volatile__( \
+ "mov r9, #0 ; vmsr fpscr, r9 ; " \
+ "msr apsr_nzcvq, r9 ; " \
+ "add r9, %0, #0 ; vld1.8 { q"#QVECREG1NO" }, [r9] ; " \
+ "add r9, %0, #16 ; vld1.8 { q"#QVECREG2NO" }, [r9] ; " \
+ "add r9, %0, #32 ; vld1.8 { q"#QVECREG3NO" }, [r9] ; " \
+ INSN_PRE INSN " ; " \
+ "add r9, %0, #48 ; vst1.8 { q"#QVECREG1NO" }, [r9] ; " \
+ "add r9, %0, #64 ; vst1.8 { q"#QVECREG2NO" }, [r9] ; " \
+ "add r9, %0, #80 ; vst1.8 { q"#QVECREG3NO" }, [r9] ; " \
+ "vmrs r9, fpscr ; str r9, [%0, #96] " \
+ : : "r"(&block[0]) \
+ : "cc", "memory", "q"#QVECREG1NO, "q"#QVECREG2NO, "q"#QVECREG3NO, \
+ "r8", "r9" \
+ ); \
+ /* Don't use INSN_PRE in printing, since that differs */ \
+ /* between ARM and Thumb and hence makes their outputs differ. */ \
+ printf(INSN " "); \
+ UInt fpscr = 0xFFFFFFE0 & block[6].u32[0]; \
+ showV128(&block[0]); printf(" "); \
+ showV128(&block[1]); printf(" "); \
+ showV128(&block[2]); printf(" "); \
+ showV128(&block[3]); printf(" "); \
+ showV128(&block[4]); printf(" "); \
+ showV128(&block[5]); printf(" fpscr=%08x\n", fpscr); \
+ } \
+ }
+
+GEN_THREEVEC_QDS_TEST(vselge_f32, IT_AL, "vselge.f32 s15,s16,s20", 3,4,5)
+GEN_THREEVEC_QDS_TEST(vselge_f64, IT_AL, "vselge.f64 d7, d8, d10", 3,4,5)
+
+GEN_THREEVEC_QDS_TEST(vselgt_f32, IT_AL, "vselgt.f32 s15,s16,s20", 3,4,5)
+GEN_THREEVEC_QDS_TEST(vselgt_f64, IT_AL, "vselgt.f64 d7, d8, d10", 3,4,5)
+
+GEN_THREEVEC_QDS_TEST(vseleq_f32, IT_AL, "vseleq.f32 s15,s16,s20", 3,4,5)
+GEN_THREEVEC_QDS_TEST(vseleq_f64, IT_AL, "vseleq.f64 d7, d8, d10", 3,4,5)
+
+GEN_THREEVEC_QDS_TEST(vselvs_f32, IT_AL, "vselvs.f32 s15,s16,s20", 3,4,5)
+GEN_THREEVEC_QDS_TEST(vselvs_f64, IT_AL, "vselvs.f64 d7, d8, d10", 3,4,5)
+
+GEN_THREEVEC_QDS_TEST(vmaxnm_f32, IT_AL, "vmaxnm.f32 s15,s16,s20", 3,4,5)
+GEN_THREEVEC_QDS_TEST(vmaxnm_f64, IT_AL, "vmaxnm.f64 d7, d8, d10", 3,4,5)
+
+GEN_THREEVEC_QDS_TEST(vminnm_f32, IT_AL, "vminnm.f32 s15,s16,s20", 3,4,5)
+GEN_THREEVEC_QDS_TEST(vminnm_f64, IT_AL, "vminnm.f64 d7, d8, d10", 3,4,5)
+
+GEN_TWOVEC_QDS_TEST(vcvtn_s32_f64, IT_AL, "vcvtn.s32.f64 s27, d5", 6,2)
+GEN_TWOVEC_QDS_TEST(vcvta_s32_f64, IT_AL, "vcvta.s32.f64 s4, d20", 1,10)
+GEN_TWOVEC_QDS_TEST(vcvtp_s32_f64, IT_AL, "vcvtp.s32.f64 s7, d31", 1,15)
+GEN_TWOVEC_QDS_TEST(vcvtm_s32_f64, IT_AL, "vcvtm.s32.f64 s1, d0", 0,0)
+
+GEN_TWOVEC_QDS_TEST(vcvtn_s32_f32, IT_AL, "vcvtn.s32.f32 s27, s5", 6,1)
+GEN_TWOVEC_QDS_TEST(vcvta_s32_f32, IT_AL, "vcvta.s32.f32 s4, s20", 1,5)
+GEN_TWOVEC_QDS_TEST(vcvtp_s32_f32, IT_AL, "vcvtp.s32.f32 s7, s31", 1,7)
+GEN_TWOVEC_QDS_TEST(vcvtm_s32_f32, IT_AL, "vcvtm.s32.f32 s1, s0", 0,0)
+
+GEN_TWOVEC_QDS_TEST(vcvtn_u32_f64, IT_AL, "vcvtn.u32.f64 s27, d5", 6,2)
+GEN_TWOVEC_QDS_TEST(vcvta_u32_f64, IT_AL, "vcvta.u32.f64 s4, d20", 1,10)
+GEN_TWOVEC_QDS_TEST(vcvtp_u32_f64, IT_AL, "vcvtp.u32.f64 s7, d31", 1,15)
+GEN_TWOVEC_QDS_TEST(vcvtm_u32_f64, IT_AL, "vcvtm.u32.f64 s1, d0", 0,0)
+
+GEN_TWOVEC_QDS_TEST(vcvtn_u32_f32, IT_AL, "vcvtn.u32.f32 s27, s5", 6,1)
+GEN_TWOVEC_QDS_TEST(vcvta_u32_f32, IT_AL, "vcvta.u32.f32 s4, s20", 1,5)
+GEN_TWOVEC_QDS_TEST(vcvtp_u32_f32, IT_AL, "vcvtp.u32.f32 s7, s31", 1,7)
+GEN_TWOVEC_QDS_TEST(vcvtm_u32_f32, IT_AL, "vcvtm.u32.f32 s1, s0", 0,0)
+
+GEN_TWOVEC_QDS_TEST(vcvtb_f64_f16, IT_AL, "vcvtb.f64.f16 d27, s18", 13, 4)
+GEN_TWOVEC_QDS_TEST(vcvtt_f64_f16, IT_AL, "vcvtt.f64.f16 d28, s17", 14, 4)
+
+GEN_TWOVEC_QDS_TEST(vcvtb_f16_f64, IT_AL, "vcvtb.f16.f64 s9, d17", 2, 8)
+GEN_TWOVEC_QDS_TEST(vcvtt_f16_f64, IT_AL, "vcvtt.f16.f64 s8, d27", 2, 13)
+
+GEN_TWOVEC_QDS_TEST(vrintzeq_f64_f64, IT_EQ, "vrintzeq.f64.f64 d0, d9", 0, 4)
+GEN_TWOVEC_QDS_TEST(vrintzne_f64_f64, IT_NE, "vrintzne.f64.f64 d1, d10", 0, 5)
+GEN_TWOVEC_QDS_TEST(vrintzal_f64_f64, IT_AL, "vrintz.f64.f64 d2, d11", 1, 5)
+
+GEN_TWOVEC_QDS_TEST(vrintreq_f64_f64, IT_EQ, "vrintreq.f64.f64 d3, d12", 1, 6)
+GEN_TWOVEC_QDS_TEST(vrintrne_f64_f64, IT_NE, "vrintrne.f64.f64 d4, d13", 2, 6)
+GEN_TWOVEC_QDS_TEST(vrintral_f64_f64, IT_AL, "vrintr.f64.f64 d5, d14", 2, 7)
+
+GEN_TWOVEC_QDS_TEST(vrintxeq_f64_f64, IT_EQ, "vrintxeq.f64.f64 d6, d15", 3, 7)
+GEN_TWOVEC_QDS_TEST(vrintxne_f64_f64, IT_NE, "vrintxne.f64.f64 d7, d16", 3, 8)
+GEN_TWOVEC_QDS_TEST(vrintxal_f64_f64, IT_AL, "vrintx.f64.f64 d8, d8", 4, 4)
+
+GEN_TWOVEC_QDS_TEST(vrintzeq_f32_f32, IT_EQ, "vrintzeq.f32.f32 s0, s9", 0, 2)
+GEN_TWOVEC_QDS_TEST(vrintzne_f32_f32, IT_NE, "vrintzne.f32.f32 s1, s10", 0, 2)
+GEN_TWOVEC_QDS_TEST(vrintzal_f32_f32, IT_AL, "vrintz.f32.f32 s2, s11", 0, 2)
+
+GEN_TWOVEC_QDS_TEST(vrintreq_f32_f32, IT_EQ, "vrintreq.f32.f32 s3, s12", 0, 3)
+GEN_TWOVEC_QDS_TEST(vrintrne_f32_f32, IT_NE, "vrintrne.f32.f32 s4, s13", 1, 3)
+GEN_TWOVEC_QDS_TEST(vrintral_f32_f32, IT_AL, "vrintr.f32.f32 s5, s14", 1, 3)
+
+GEN_TWOVEC_QDS_TEST(vrintxeq_f32_f32, IT_EQ, "vrintxeq.f32.f32 s6, s15", 1, 3)
+GEN_TWOVEC_QDS_TEST(vrintxne_f32_f32, IT_NE, "vrintxne.f32.f32 s7, s16", 1, 4)
+GEN_TWOVEC_QDS_TEST(vrintxal_f32_f32, IT_AL, "vrintx.f32.f32 s8, s8", 2, 2)
+
+GEN_TWOVEC_QDS_TEST(vrintn_f64_f64, IT_AL, "vrintn.f64.f64 d3, d15", 1, 7)
+GEN_TWOVEC_QDS_TEST(vrinta_f64_f64, IT_AL, "vrinta.f64.f64 d6, d18", 3, 9)
+GEN_TWOVEC_QDS_TEST(vrintp_f64_f64, IT_AL, "vrintp.f64.f64 d9, d21", 4, 10)
+GEN_TWOVEC_QDS_TEST(vrintm_f64_f64, IT_AL, "vrintm.f64.f64 d12, d12", 6, 6)
+
+GEN_TWOVEC_QDS_TEST(vrintn_f32_f32, IT_AL, "vrintn.f32.f32 s3, s15", 0, 3)
+GEN_TWOVEC_QDS_TEST(vrinta_f32_f32, IT_AL, "vrinta.f32.f32 s6, s18", 1, 4)
+GEN_TWOVEC_QDS_TEST(vrintp_f32_f32, IT_AL, "vrintp.f32.f32 s9, s21", 2, 5)
+GEN_TWOVEC_QDS_TEST(vrintm_f32_f32, IT_AL, "vrintm.f32.f32 s12, s12", 3, 3)
+
+GEN_THREEVEC_QDS_TEST(vmaxnm_f32_vec64,
+ IT_AL, "vmaxnm.f32 d15,d16,d20", 7,8,10)
+GEN_THREEVEC_QDS_TEST(vmaxnm_f32_vec128,
+ IT_AL, "vmaxnm.f32 q7, q8, q10", 7,8,10)
+
+GEN_THREEVEC_QDS_TEST(vminnm_f32_vec64,
+ IT_AL, "vminnm.f32 d15,d16,d20", 7,8,10)
+GEN_THREEVEC_QDS_TEST(vminnm_f32_vec128,
+ IT_AL, "vminnm.f32 q7, q8, q10", 7,8,10)
+
+GEN_TWOVEC_QDS_TEST(vcvtn_s32_f32_vec64,
+ IT_AL, "vcvtn.s32.f32 d0, d20", 0, 10)
+GEN_TWOVEC_QDS_TEST(vcvta_s32_f32_vec64,
+ IT_AL, "vcvta.s32.f32 d5, d25", 2, 12)
+GEN_TWOVEC_QDS_TEST(vcvtp_s32_f32_vec64,
+ IT_AL, "vcvtp.s32.f32 d10, d30", 5, 15)
+GEN_TWOVEC_QDS_TEST(vcvtm_s32_f32_vec64,
+ IT_AL, "vcvtm.s32.f32 d15, d15", 7, 7)
+
+GEN_TWOVEC_QDS_TEST(vcvtn_s32_f32_vec128,
+ IT_AL, "vcvtn.s32.f32 q15, q0", 15, 0)
+GEN_TWOVEC_QDS_TEST(vcvta_s32_f32_vec128,
+ IT_AL, "vcvta.s32.f32 q14, q1", 14, 1)
+GEN_TWOVEC_QDS_TEST(vcvtp_s32_f32_vec128,
+ IT_AL, "vcvtp.s32.f32 q13, q2", 13, 2)
+GEN_TWOVEC_QDS_TEST(vcvtm_s32_f32_vec128,
+ IT_AL, "vcvtm.s32.f32 q12, q3", 12, 3)
+
+GEN_TWOVEC_QDS_TEST(vcvtn_u32_f32_vec64,
+ IT_AL, "vcvtn.u32.f32 d0, d20", 0, 10)
+GEN_TWOVEC_QDS_TEST(vcvta_u32_f32_vec64,
+ IT_AL, "vcvta.u32.f32 d5, d25", 2, 12)
+GEN_TWOVEC_QDS_TEST(vcvtp_u32_f32_vec64,
+ IT_AL, "vcvtp.u32.f32 d10, d30", 5, 15)
+GEN_TWOVEC_QDS_TEST(vcvtm_u32_f32_vec64,
+ IT_AL, "vcvtm.u32.f32 d15, d15", 7, 7)
+
+GEN_TWOVEC_QDS_TEST(vcvtn_u32_f32_vec128,
+ IT_AL, "vcvtn.u32.f32 q15, q0", 15, 0)
+GEN_TWOVEC_QDS_TEST(vcvta_u32_f32_vec128,
+ IT_AL, "vcvta.u32.f32 q14, q1", 14, 1)
+GEN_TWOVEC_QDS_TEST(vcvtp_u32_f32_vec128,
+ IT_AL, "vcvtp.u32.f32 q13, q2", 13, 2)
+GEN_TWOVEC_QDS_TEST(vcvtm_u32_f32_vec128,
+ IT_AL, "vcvtm.u32.f32 q12, q3", 12, 3)
+
+GEN_TWOVEC_QDS_TEST(vrintn_f32_f32_vec64,
+ IT_AL, "vrintn.f32.f32 d0, d18", 0, 9)
+GEN_TWOVEC_QDS_TEST(vrinta_f32_f32_vec64,
+ IT_AL, "vrinta.f32.f32 d3, d21", 1, 10)
+GEN_TWOVEC_QDS_TEST(vrintp_f32_f32_vec64,
+ IT_AL, "vrintp.f32.f32 d6, d24", 3, 12)
+GEN_TWOVEC_QDS_TEST(vrintm_f32_f32_vec64,
+ IT_AL, "vrintm.f32.f32 d9, d27", 4, 13)
+GEN_TWOVEC_QDS_TEST(vrintz_f32_f32_vec64,
+ IT_AL, "vrintz.f32.f32 d12, d30", 6, 15)
+GEN_TWOVEC_QDS_TEST(vrintx_f32_f32_vec64,
+ IT_AL, "vrintx.f32.f32 d15, d15", 7, 7)
+
+GEN_TWOVEC_QDS_TEST(vrintn_f32_f32_vec128,
+ IT_AL, "vrintn.f32.f32 q0, q2", 0, 2)
+GEN_TWOVEC_QDS_TEST(vrinta_f32_f32_vec128,
+ IT_AL, "vrinta.f32.f32 q3, q5", 3, 5)
+GEN_TWOVEC_QDS_TEST(vrintp_f32_f32_vec128,
+ IT_AL, "vrintp.f32.f32 q6, q8", 6, 8)
+GEN_TWOVEC_QDS_TEST(vrintm_f32_f32_vec128,
+ IT_AL, "vrintm.f32.f32 q9, q11", 9, 11)
+GEN_TWOVEC_QDS_TEST(vrintz_f32_f32_vec128,
+ IT_AL, "vrintz.f32.f32 q12, q14", 12, 14)
+GEN_TWOVEC_QDS_TEST(vrintx_f32_f32_vec128,
+ IT_AL, "vrintx.f32.f32 q15, q15", 15, 15)
+
+int main ( void )
+{
+ if (1) DO50( test_vselge_f32(TySF) );
+ if (1) DO50( test_vselge_f64(TyDF) );
+
+ if (1) DO50( test_vselgt_f32(TySF) );
+ if (1) DO50( test_vselgt_f64(TyDF) );
+
+ if (1) DO50( test_vseleq_f32(TySF) );
+ if (1) DO50( test_vseleq_f64(TyDF) );
+
+ if (1) DO50( test_vselvs_f32(TySF) );
+ if (1) DO50( test_vselvs_f64(TyDF) );
+
+ if (1) DO50( test_vmaxnm_f32(TySF) );
+ if (1) DO50( test_vmaxnm_f64(TyDF) );
+
+ if (1) DO50( test_vminnm_f32(TySF) );
+ if (1) DO50( test_vminnm_f64(TyDF) );
+
+ if (1) DO50( test_vcvtn_s32_f64(TyDF) );
+ if (1) DO50( test_vcvta_s32_f64(TyDF) );
+ if (1) DO50( test_vcvtp_s32_f64(TyDF) );
+ if (1) DO50( test_vcvtm_s32_f64(TyDF) );
+
+ if (1) DO50( test_vcvtn_s32_f32(TySF) );
+ if (1) DO50( test_vcvta_s32_f32(TySF) );
+ if (1) DO50( test_vcvtp_s32_f32(TySF) );
+ if (1) DO50( test_vcvtm_s32_f32(TySF) );
+
+ if (1) DO50( test_vcvtn_u32_f64(TyDF) );
+ if (1) DO50( test_vcvta_u32_f64(TyDF) );
+ if (1) DO50( test_vcvtp_u32_f64(TyDF) );
+ if (1) DO50( test_vcvtm_u32_f64(TyDF) );
+
+ if (1) DO50( test_vcvtn_u32_f32(TySF) );
+ if (1) DO50( test_vcvta_u32_f32(TySF) );
+ if (1) DO50( test_vcvtp_u32_f32(TySF) );
+ if (1) DO50( test_vcvtm_u32_f32(TySF) );
+
+ if (0) DO50( test_vcvtb_f64_f16(TyDF) );
+ if (0) DO50( test_vcvtt_f64_f16(TyDF) );
+
+ if (0) DO50( test_vcvtb_f16_f64(TyHF) );
+ if (0) DO50( test_vcvtt_f16_f64(TyHF) );
+
+ if (1) DO50( test_vrintzeq_f64_f64(TyDF) );
+ if (1) DO50( test_vrintzne_f64_f64(TyDF) );
+ if (1) DO50( test_vrintzal_f64_f64(TyDF) );
+
+ if (1) DO50( test_vrintreq_f64_f64(TyDF) );
+ if (1) DO50( test_vrintrne_f64_f64(TyDF) );
+ if (1) DO50( test_vrintral_f64_f64(TyDF) );
+
+ if (1) DO50( test_vrintxeq_f64_f64(TyDF) );
+ if (1) DO50( test_vrintxne_f64_f64(TyDF) );
+ if (1) DO50( test_vrintxal_f64_f64(TyDF) );
+
+ if (1) DO50( test_vrintzeq_f32_f32(TySF) );
+ if (1) DO50( test_vrintzne_f32_f32(TySF) );
+ if (1) DO50( test_vrintzal_f32_f32(TySF) );
+
+ if (1) DO50( test_vrintreq_f32_f32(TySF) );
+ if (1) DO50( test_vrintrne_f32_f32(TySF) );
+ if (1) DO50( test_vrintral_f32_f32(TySF) );
+
+ if (1) DO50( test_vrintxeq_f32_f32(TySF) );
+ if (1) DO50( test_vrintxne_f32_f32(TySF) );
+ if (1) DO50( test_vrintxal_f32_f32(TySF) );
+
+ if (1) DO50( test_vrintn_f64_f64(TyDF) );
+ if (1) DO50( test_vrinta_f64_f64(TyDF) );
+ if (1) DO50( test_vrintp_f64_f64(TyDF) );
+ if (1) DO50( test_vrintm_f64_f64(TyDF) );
+
+ if (1) DO50( test_vrintn_f32_f32(TySF) );
+ if (1) DO50( test_vrinta_f32_f32(TySF) );
+ if (1) DO50( test_vrintp_f32_f32(TySF) );
+ if (1) DO50( test_vrintm_f32_f32(TySF) );
+
+ if (1) DO50( test_vmaxnm_f32_vec64(TySF) );
+ if (1) DO50( test_vmaxnm_f32_vec128(TySF) );
+
+ if (1) DO50( test_vminnm_f32_vec64(TySF) );
+ if (1) DO50( test_vminnm_f32_vec128(TySF) );
+
+ if (1) DO50( test_vcvtn_s32_f32_vec64(TySF) );
+ if (1) DO50( test_vcvta_s32_f32_vec64(TySF) );
+ if (1) DO50( test_vcvtp_s32_f32_vec64(TySF) );
+ if (1) DO50( test_vcvtm_s32_f32_vec64(TySF) );
+
+ if (1) DO50( test_vcvtn_s32_f32_vec128(TySF) );
+ if (1) DO50( test_vcvta_s32_f32_vec128(TySF) );
+ if (1) DO50( test_vcvtp_s32_f32_vec128(TySF) );
+ if (1) DO50( test_vcvtm_s32_f32_vec128(TySF) );
+
+ if (1) DO50( test_vcvtn_u32_f32_vec64(TySF) );
+ if (1) DO50( test_vcvta_u32_f32_vec64(TySF) );
+ if (1) DO50( test_vcvtp_u32_f32_vec64(TySF) );
+ if (1) DO50( test_vcvtm_u32_f32_vec64(TySF) );
+
+ if (1) DO50( test_vcvtn_u32_f32_vec128(TySF) );
+ if (1) DO50( test_vcvta_u32_f32_vec128(TySF) );
+ if (1) DO50( test_vcvtp_u32_f32_vec128(TySF) );
+ if (1) DO50( test_vcvtm_u32_f32_vec128(TySF) );
+
+ if (1) DO50( test_vrintn_f32_f32_vec64(TySF) );
+ if (1) DO50( test_vrinta_f32_f32_vec64(TySF) );
+ if (1) DO50( test_vrintp_f32_f32_vec64(TySF) );
+ if (1) DO50( test_vrintm_f32_f32_vec64(TySF) );
+ if (1) DO50( test_vrintz_f32_f32_vec64(TySF) );
+ if (1) DO50( test_vrintx_f32_f32_vec64(TySF) );
+
+ if (1) DO50( test_vrintn_f32_f32_vec128(TySF) );
+ if (1) DO50( test_vrinta_f32_f32_vec128(TySF) );
+ if (1) DO50( test_vrintp_f32_f32_vec128(TySF) );
+ if (1) DO50( test_vrintm_f32_f32_vec128(TySF) );
+ if (1) DO50( test_vrintz_f32_f32_vec128(TySF) );
+ if (1) DO50( test_vrintx_f32_f32_vec128(TySF) );
+
+ return 0;
+}
diff --git a/none/tests/arm/v8fpsimd_a.stderr.exp b/none/tests/arm/v8fpsimd_a.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/arm/v8fpsimd_a.stderr.exp
diff --git a/none/tests/arm/v8fpsimd_a.stdout.exp b/none/tests/arm/v8fpsimd_a.stdout.exp
new file mode 100644
index 0000000..b7ea1b3
--- /dev/null
+++ b/none/tests/arm/v8fpsimd_a.stdout.exp
@@ -0,0 +1,6763 @@
+randV128: doing v->u32[3] = v->u32[2]
+vselge.f32 s15,s16,s20 5175e39d19c9ca1e98f24a4984175700 c5fa956ac5fa956a0d69c3e9a6af27d1 56a044b260b160857d45c48447b8d8c0 a6af27d119c9ca1e98f24a4984175700 c5fa956ac5fa956a0d69c3e9a6af27d1 56a044b260b160857d45c48447b8d8c0 fpscr=00000000
+vselge.f32 s15,s16,s20 d740b80eb7839b97d89998df5035ed36 db56b01a12b0ca1583cb509970b8136c 191fd3a727d1a705f65df9dd4a29f8c0 70b8136cb7839b97d89998df5035ed36 db56b01a12b0ca1583cb509970b8136c 191fd3a727d1a705f65df9dd4a29f8c0 fpscr=00000000
+vselge.f32 s15,s16,s20 b536bbe4da8a369dab4f9465b86ed182 7b8d9035449b06f4e06e2205236eb768 95264321bf3b68b255c2b9e2c95c9810 236eb768da8a369dab4f9465b86ed182 7b8d9035449b06f4e06e2205236eb768 95264321bf3b68b255c2b9e2c95c9810 fpscr=00000000
+vselge.f32 s15,s16,s20 e13dfe910a3e0f7c75cb0842b95ed64d fcb0ebfe6ee98ebd1ca893312a54cae7 5b2d5a70a7920a5f45c55f1c9202b76d 2a54cae70a3e0f7c75cb0842b95ed64d fcb0ebfe6ee98ebd1ca893312a54cae7 5b2d5a70a7920a5f45c55f1c9202b76d fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vselge.f32 s15,s16,s20 a86aacf29b0f395c98b463483da65c8c c3ec352e2dac0350f6fd1ca81b6e33c5 e9bf6f37c9e25f72d82e582b73a8f718 1b6e33c59b0f395c98b463483da65c8c c3ec352e2dac0350f6fd1ca81b6e33c5 e9bf6f37c9e25f72d82e582b73a8f718 fpscr=00000000
+vselge.f32 s15,s16,s20 36da9dbf68bc3026343700a654eb2ddd 810e6dc1a1833d8404eb7f0cf4ca6fee b39925ba7d9d67bcff6f850f2c57ea2a f4ca6fee68bc3026343700a654eb2ddd 810e6dc1a1833d8404eb7f0cf4ca6fee b39925ba7d9d67bcff6f850f2c57ea2a fpscr=00000000
+vselge.f32 s15,s16,s20 01737fd22bfa8f668c8b14f436b2a38d 097df30b8daa927a03090dfc6df078b6 6d498492e7e796df010bf4b23b845743 6df078b62bfa8f668c8b14f436b2a38d 097df30b8daa927a03090dfc6df078b6 6d498492e7e796df010bf4b23b845743 fpscr=00000000
+vselge.f32 s15,s16,s20 985e6d08ed19fa045f841810cd8c109e 7bc0131c4a678450562685769ab818a5 8afcb3dfb984aed62671e865e6f21d40 9ab818a5ed19fa045f841810cd8c109e 7bc0131c4a678450562685769ab818a5 8afcb3dfb984aed62671e865e6f21d40 fpscr=00000000
+vselge.f32 s15,s16,s20 c51cdd8f87e12ab4acb722146c6cbfa9 63d7568e3e8a3ac80e048612e51a468e bdf58de2b4a9d799ff5f0c05cb6ebd12 e51a468e87e12ab4acb722146c6cbfa9 63d7568e3e8a3ac80e048612e51a468e bdf58de2b4a9d799ff5f0c05cb6ebd12 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vselge.f32 s15,s16,s20 fd8f4d8698c2cb9dfb4ea5d187136489 575775bc3a12029d8e66ea903a12029d e85ef9754842f9c9ba28f82a63b15c68 3a12029d98c2cb9dfb4ea5d187136489 575775bc3a12029d8e66ea903a12029d e85ef9754842f9c9ba28f82a63b15c68 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vselge.f32 s15,s16,s20 964fbba0b8d508aebee85fda964fbba0 6809217c310baca0c3837be65197abe2 c0f55f706da71bf2425f9605e2b252c1 5197abe2b8d508aebee85fda964fbba0 6809217c310baca0c3837be65197abe2 c0f55f706da71bf2425f9605e2b252c1 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vselge.f32 s15,s16,s20 0c65c22b4ab8778d9ed6d9eb46ea8ca3 82c1007a7d3cd8f54b130cdaa89cef0e 627bb6e12d1f6d4651ef145cb9b83843 a89cef0e4ab8778d9ed6d9eb46ea8ca3 82c1007a7d3cd8f54b130cdaa89cef0e 627bb6e12d1f6d4651ef145cb9b83843 fpscr=00000000
+vselge.f32 s15,s16,s20 3b25bca27a9c69505d14b27d9d16f25b fbbab6a7f19faff0f1798fe3c1699cf0 9f7301c1392d8087d4ba52a206ff21b1 c1699cf07a9c69505d14b27d9d16f25b fbbab6a7f19faff0f1798fe3c1699cf0 9f7301c1392d8087d4ba52a206ff21b1 fpscr=00000000
+vselge.f32 s15,s16,s20 0352a3d92d460a61a5dd0f6f47086cc3 2e9360315bf0177599dbe14b4616559e 3e9e2b92eef2c569453ccd1b0fc40784 4616559e2d460a61a5dd0f6f47086cc3 2e9360315bf0177599dbe14b4616559e 3e9e2b92eef2c569453ccd1b0fc40784 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselge.f32 s15,s16,s20 0facd2b3c4044ef23fb2e22093a48a9d fac555adddf0eb4808f06704c857e949 812abdb289fba268812abdb21e4a9e09 c857e949c4044ef23fb2e22093a48a9d fac555adddf0eb4808f06704c857e949 812abdb289fba268812abdb21e4a9e09 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vselge.f32 s15,s16,s20 835e3ede9a220dce0e75e07acb193b9a 3ea20cc00420edac31a0d5992573776d 1e6559138591810713013cc685918107 2573776d9a220dce0e75e07acb193b9a 3ea20cc00420edac31a0d5992573776d 1e6559138591810713013cc685918107 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[0]
+vselge.f32 s15,s16,s20 16ee9afa99500fef6024ba39dce32c23 49e54740570037914d04ab3d57003791 16257132a9f8030aa0dc273ba9f8030a 5700379199500fef6024ba39dce32c23 49e54740570037914d04ab3d57003791 16257132a9f8030aa0dc273ba9f8030a fpscr=00000000
+vselge.f32 s15,s16,s20 865de41295f2db8f44cbbf37e2bc70c3 15ff8f2e73a3a0fae06860b606c7e8c7 4428d9c8833f5b78fb29445f3bc8d7fc 06c7e8c795f2db8f44cbbf37e2bc70c3 15ff8f2e73a3a0fae06860b606c7e8c7 4428d9c8833f5b78fb29445f3bc8d7fc fpscr=00000000
+vselge.f32 s15,s16,s20 f5d7c0f9da7f07e00794eb00b0940ba5 8e212ab7be625608d5abd787f5c90ee7 861576e44fac8dd5bbc503330eb9dd5d f5c90ee7da7f07e00794eb00b0940ba5 8e212ab7be625608d5abd787f5c90ee7 861576e44fac8dd5bbc503330eb9dd5d fpscr=00000000
+vselge.f32 s15,s16,s20 d33d431279cce48fce3d3cc0784c2f85 b1ef0b40d58cb22d00b1125934a781e4 e7467c38bb69a6e1e9a617d4d14e5927 34a781e479cce48fce3d3cc0784c2f85 b1ef0b40d58cb22d00b1125934a781e4 e7467c38bb69a6e1e9a617d4d14e5927 fpscr=00000000
+vselge.f32 s15,s16,s20 b9433f079dacacabeb000208c9029669 20162517609f0f22a1a7a4c9c0a51f6b f763e279a20368bc8bdb3b370954bcbf c0a51f6b9dacacabeb000208c9029669 20162517609f0f22a1a7a4c9c0a51f6b f763e279a20368bc8bdb3b370954bcbf fpscr=00000000
+vselge.f32 s15,s16,s20 60926235021b445ef059e641a1ccb097 136b941e54ffe81c9c7740ef19345795 6930e0fad3ba39c483bd1e68fb03f57b 19345795021b445ef059e641a1ccb097 136b941e54ffe81c9c7740ef19345795 6930e0fad3ba39c483bd1e68fb03f57b fpscr=00000000
+vselge.f32 s15,s16,s20 677f96a350623139cb7207e36cbf75aa 5f927f2b383caf8484c5f3078d2aded7 31aa6a1e5e366d4c1cd56194c94a4e2c 8d2aded750623139cb7207e36cbf75aa 5f927f2b383caf8484c5f3078d2aded7 31aa6a1e5e366d4c1cd56194c94a4e2c fpscr=00000000
+vselge.f32 s15,s16,s20 ed4f4db5a9377eb31749ef710cf75788 924816791f1030333fb8fa4b2feb05cb 99bb3fa4c2385e4166df2141ad63a876 2feb05cba9377eb31749ef710cf75788 924816791f1030333fb8fa4b2feb05cb 99bb3fa4c2385e4166df2141ad63a876 fpscr=00000000
+vselge.f32 s15,s16,s20 8f1ee978efa4b054d2bc36ca100a4a3a b4e706a17746411ab40c9f043af6a1ae 88ae0d34fa174f9ce927c476f140aa41 3af6a1aeefa4b054d2bc36ca100a4a3a b4e706a17746411ab40c9f043af6a1ae 88ae0d34fa174f9ce927c476f140aa41 fpscr=00000000
+vselge.f32 s15,s16,s20 cd123e19cf1e2bb001f1161e946f5ca7 d5f13a9ab645e140698bec649583f5aa 5a5e86033374552e23ce8e2455e0205c 9583f5aacf1e2bb001f1161e946f5ca7 d5f13a9ab645e140698bec649583f5aa 5a5e86033374552e23ce8e2455e0205c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vselge.f32 s15,s16,s20 cf82c7aff819714a711ce1284318b884 a88e7b2818210760c299b42e1fdcc2e9 2ef114ddd37570e82d39fd95a9f5a45d 1fdcc2e9f819714a711ce1284318b884 a88e7b2818210760c299b42e1fdcc2e9 2ef114ddd37570e82d39fd95a9f5a45d fpscr=00000000
+vselge.f32 s15,s16,s20 0a9c61f55fce335d68e1a25652a804a7 1dd493f59184345437d5e366d0e20c30 81c50f1401e45b82d3086a7a39a1e621 d0e20c305fce335d68e1a25652a804a7 1dd493f59184345437d5e366d0e20c30 81c50f1401e45b82d3086a7a39a1e621 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[0]
+vselge.f32 s15,s16,s20 370813738219ffced22c62cba0822c4c 7c7642a20df9d4ec68f21f468712f7b8 bba1a11cc04c89478209dbbd84d92508 8712f7b88219ffced22c62cba0822c4c 7c7642a20df9d4ec68f21f468712f7b8 bba1a11cc04c89478209dbbd84d92508 fpscr=00000000
+vselge.f32 s15,s16,s20 291541139c8b1cd0d1a11d81326f4e78 44c930c9028972f8733d11f7fa4450de b8ddd8a1cd852d9cd970502d146432e6 fa4450de9c8b1cd0d1a11d81326f4e78 44c930c9028972f8733d11f7fa4450de b8ddd8a1cd852d9cd970502d146432e6 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vselge.f32 s15,s16,s20 470887bfdd3daf94d7265949ca62b46a d3a0a41fce854ae735e7926e777aa43f b3ef9f8c927c405d2fb2ed4ecc1e172d 777aa43fdd3daf94d7265949ca62b46a d3a0a41fce854ae735e7926e777aa43f b3ef9f8c927c405d2fb2ed4ecc1e172d fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+vselge.f32 s15,s16,s20 cdc14f0bcdc14f0bf7ba2283e22a3104 4e0cf0fdf0aee1dda4e888e2774acbc1 61e618f30110c432a534d0478d5d7e05 774acbc1cdc14f0bf7ba2283e22a3104 4e0cf0fdf0aee1dda4e888e2774acbc1 61e618f30110c432a534d0478d5d7e05 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[3]
+vselge.f32 s15,s16,s20 57805ff098ce3ed14b62bbc77143b71e 0d2c018b8415100484151004ff355bf0 11edd5a106e2d655f9b97953917f469f ff355bf098ce3ed14b62bbc77143b71e 0d2c018b8415100484151004ff355bf0 11edd5a106e2d655f9b97953917f469f fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vselge.f32 s15,s16,s20 d5da99d2eec5040fc700120f62ee9b23 bc58f8b23fcabf6982b029b396ea4f1e 7d2c86fa7c09a37b813bf15120fbc868 96ea4f1eeec5040fc700120f62ee9b23 bc58f8b23fcabf6982b029b396ea4f1e 7d2c86fa7c09a37b813bf15120fbc868 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[1]
+vselge.f32 s15,s16,s20 c997070e67232e66c997070e860c39c5 5073109cfa471afbe686e2ede96f8809 4df8929c4e1bb03ba56adb474e1bb03b e96f880967232e66c997070e860c39c5 5073109cfa471afbe686e2ede96f8809 4df8929c4e1bb03ba56adb474e1bb03b fpscr=00000000
+vselge.f32 s15,s16,s20 59f634f791559ff8d881612a1f00ed91 1add7938e3067d74917c37833edb866b b3448c8c9a654f1c8c8db3b639e1fba1 3edb866b91559ff8d881612a1f00ed91 1add7938e3067d74917c37833edb866b b3448c8c9a654f1c8c8db3b639e1fba1 fpscr=00000000
+vselge.f32 s15,s16,s20 4cb8e76fcc086aeb0414a9cd126c0869 7b85bbd973ba438b80fdb556878af3ad a6cb98bf6fa194a173e020c0ede3baf2 878af3adcc086aeb0414a9cd126c0869 7b85bbd973ba438b80fdb556878af3ad a6cb98bf6fa194a173e020c0ede3baf2 fpscr=00000000
+vselge.f32 s15,s16,s20 65b86284a1cb27a371a4885bc70f501c 2468a718ec4422710c95a6e59e2a7fab bfaf26fbc229d962e2d7a20cab554a62 9e2a7faba1cb27a371a4885bc70f501c 2468a718ec4422710c95a6e59e2a7fab bfaf26fbc229d962e2d7a20cab554a62 fpscr=00000000
+vselge.f32 s15,s16,s20 ad8f313a964967940f284cfce9a33028 738ec585d726b8f4ecb95e02f1d179e3 af5de4ddb013d258a082f55bbf17ae91 f1d179e3964967940f284cfce9a33028 738ec585d726b8f4ecb95e02f1d179e3 af5de4ddb013d258a082f55bbf17ae91 fpscr=00000000
+vselge.f32 s15,s16,s20 d04c2dd1910bd9cf5599014e9dc435b3 95b85f1c30562ca02ba32b169299fd64 09cb539549408a57d0e8a18b5417adc6 9299fd64910bd9cf5599014e9dc435b3 95b85f1c30562ca02ba32b169299fd64 09cb539549408a57d0e8a18b5417adc6 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselge.f32 s15,s16,s20 4954977124406c74e81e7aa9430469f9 d9438203e383314ed9438203c8655800 aaba95edd88623fc68d5d5d393ccbadd c865580024406c74e81e7aa9430469f9 d9438203e383314ed9438203c8655800 aaba95edd88623fc68d5d5d393ccbadd fpscr=00000000
+vselge.f32 s15,s16,s20 7d1161203b947b8f0a536415b779aada f56dfe15b7e82632fc79b30f1483e79b b34432fe82493fa5c4d84771e518605a 1483e79b3b947b8f0a536415b779aada f56dfe15b7e82632fc79b30f1483e79b b34432fe82493fa5c4d84771e518605a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: 256 calls, 265 iters
+vselge.f32 s15,s16,s20 36ba0ab0c81fb7053f6b55d4eaedef93 29b247cac4e8bba2bda130508cf3c5a6 9e8fbc053bc4d999db7390839e8fbc05 8cf3c5a6c81fb7053f6b55d4eaedef93 29b247cac4e8bba2bda130508cf3c5a6 9e8fbc053bc4d999db7390839e8fbc05 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vselge.f32 s15,s16,s20 8dbd4545a92ebc1d99f6f68da34afe4e f4dd02230b0b9f6018e987aeba97106b 2f35968b0a9d5fe4af824eabd8f8f577 ba97106ba92ebc1d99f6f68da34afe4e f4dd02230b0b9f6018e987aeba97106b 2f35968b0a9d5fe4af824eabd8f8f577 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselge.f32 s15,s16,s20 3951f70edbe25a9a3951f70e8dc88216 5ee9b286181efe1783322bd1f4a0a92e d4a3445ee5f0714d6ed9d5a9ea9b3880 f4a0a92edbe25a9a3951f70e8dc88216 5ee9b286181efe1783322bd1f4a0a92e d4a3445ee5f0714d6ed9d5a9ea9b3880 fpscr=00000000
+vselge.f32 s15,s16,s20 0c4e5ddd66c8f02281b3c8f26eeb8d90 d9407ecd6355d7239077cddd8edc2316 ddf6d8b991ce01deaf4923243fc0b6d3 8edc231666c8f02281b3c8f26eeb8d90 d9407ecd6355d7239077cddd8edc2316 ddf6d8b991ce01deaf4923243fc0b6d3 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vselge.f32 s15,s16,s20 fa6db7a39486894259f1290efa6db7a3 e3a4469f24fe98dc158b24fec4bafee7 451c6eb3e447d1587d7aa579647d6dc0 c4bafee79486894259f1290efa6db7a3 e3a4469f24fe98dc158b24fec4bafee7 451c6eb3e447d1587d7aa579647d6dc0 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[3]
+vselge.f32 s15,s16,s20 1fc8f3fa1382738f705b685c54d57186 75f5144ccc5e105c99661df92e3cc13e 8597b02c9c423a147ae28aed9c423a14 2e3cc13e1382738f705b685c54d57186 75f5144ccc5e105c99661df92e3cc13e 8597b02c9c423a147ae28aed9c423a14 fpscr=00000000
+vselge.f32 s15,s16,s20 406068505c979f40cdc58392364fbbe2 6feefdf8d22d16a827667197b8d187cb d8c318f5aa57d04b750405c33deba68d b8d187cb5c979f40cdc58392364fbbe2 6feefdf8d22d16a827667197b8d187cb d8c318f5aa57d04b750405c33deba68d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vselge.f32 s15,s16,s20 9f8c3175b6b243e17860dbd798f8ac48 e87ea00ccf8549bf47029a37d75b1941 02f1b3c72ff97f68cd517cb92b46de01 d75b1941b6b243e17860dbd798f8ac48 e87ea00ccf8549bf47029a37d75b1941 02f1b3c72ff97f68cd517cb92b46de01 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 7dea6f8ae74d5f797dea6f8ae74d5f79 4d15989216cc2891c94f65dfccc66f9e 312d32f1bb069e61ab09c2f3335970be c94f65dfccc66f9e7dea6f8ae74d5f79 4d15989216cc2891c94f65dfccc66f9e 312d32f1bb069e61ab09c2f3335970be fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 20326a7d927f8ecd4a783d658932e026 8b97fa553a6508ac8b97fa553a6508ac 470818041ac5e9b218db305838ff3248 8b97fa553a6508ac4a783d658932e026 8b97fa553a6508ac8b97fa553a6508ac 470818041ac5e9b218db305838ff3248 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 18eb39be527594f68adebded1af4c541 78e95f7a8aed8854faa096b85e32ad5a 699f129680a985484a52397b894a4f49 faa096b85e32ad5a8adebded1af4c541 78e95f7a8aed8854faa096b85e32ad5a 699f129680a985484a52397b894a4f49 fpscr=00000000
+vselge.f64 d7, d8, d10 7c44fda2c4f3ed4e66c03150c383fd2d 1e27c81bff702749760afcca34c46a4a e35ab00b3cdf75747e60035ee161b2dd 760afcca34c46a4a66c03150c383fd2d 1e27c81bff702749760afcca34c46a4a e35ab00b3cdf75747e60035ee161b2dd fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 8f72bc6577b145aeabe876d3472e35c6 28f38b2e093fbce08c1f71338e7c577f 5bc30eedfc43f567c87be936badd6630 8c1f71338e7c577fabe876d3472e35c6 28f38b2e093fbce08c1f71338e7c577f 5bc30eedfc43f567c87be936badd6630 fpscr=00000000
+vselge.f64 d7, d8, d10 95df08065206478d94b3ff795f122865 6c7f80e89ebd80a5e34bca20163ac21e c2e06c5cc8e1357d72cece7967d1f50c e34bca20163ac21e94b3ff795f122865 6c7f80e89ebd80a5e34bca20163ac21e c2e06c5cc8e1357d72cece7967d1f50c fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 ac79a338e2ed6bf4b500d2fe8f552735 244c1dcf60e0190c026f4f4108bb97f1 fce910c815b7b5082a07b97ea580d954 026f4f4108bb97f1b500d2fe8f552735 244c1dcf60e0190c026f4f4108bb97f1 fce910c815b7b5082a07b97ea580d954 fpscr=00000000
+vselge.f64 d7, d8, d10 b164b81a015d181eb0d13422c035a6a7 2b0bfdbeddb488c900901dc5368c3595 cf2d05af86747edec1b4c5c4fa8650fe 00901dc5368c3595b0d13422c035a6a7 2b0bfdbeddb488c900901dc5368c3595 cf2d05af86747edec1b4c5c4fa8650fe fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 1d637d751dfa1352e40c986744421113 a6b7393576df5c23d344e7279f0d2317 a06b4f801c40c9e0a06b4f801c40c9e0 d344e7279f0d2317e40c986744421113 a6b7393576df5c23d344e7279f0d2317 a06b4f801c40c9e0a06b4f801c40c9e0 fpscr=00000000
+vselge.f64 d7, d8, d10 c509a7178875c1b1aa5552bf7b541645 e0332c6ed78e2afc4561d270bed6b68a 313cbec68670df4e1ab8e17b2178e568 4561d270bed6b68aaa5552bf7b541645 e0332c6ed78e2afc4561d270bed6b68a 313cbec68670df4e1ab8e17b2178e568 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 9a9e84669a985ec5f0031343f3185309 4ad64de91c16da21aeefac01e48b55d9 fee0b45668b52a09fee0b45668b52a09 aeefac01e48b55d9f0031343f3185309 4ad64de91c16da21aeefac01e48b55d9 fee0b45668b52a09fee0b45668b52a09 fpscr=00000000
+vselge.f64 d7, d8, d10 1a1256ba10a38a2b40833c5f6109ca65 a98a0320fe506fd007449d8620c34d90 310e98e167b9e8f5f99ff99706c8eb8a 07449d8620c34d9040833c5f6109ca65 a98a0320fe506fd007449d8620c34d90 310e98e167b9e8f5f99ff99706c8eb8a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 8f17393d14b564cbe1d0c0b48a0655b1 d04fb16a4d20867d3a5b4dbd6dd8955f d94d188902284fdfd94d188902284fdf 3a5b4dbd6dd8955fe1d0c0b48a0655b1 d04fb16a4d20867d3a5b4dbd6dd8955f d94d188902284fdfd94d188902284fdf fpscr=00000000
+vselge.f64 d7, d8, d10 442729db00c06ec7a888afd71cbfd9a5 a748e3f1cf4820c03b24f10f9cc602e6 ed8c329e49985ce0a08d4e504c0d1ea8 3b24f10f9cc602e6a888afd71cbfd9a5 a748e3f1cf4820c03b24f10f9cc602e6 ed8c329e49985ce0a08d4e504c0d1ea8 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 4ce7b072a07d2e1c4ce7b072a07d2e1c 224c09e6f9f4b7ac224c09e6f9f4b7ac 30603637c27a144a5b20f8ab9814aff9 224c09e6f9f4b7ac4ce7b072a07d2e1c 224c09e6f9f4b7ac224c09e6f9f4b7ac 30603637c27a144a5b20f8ab9814aff9 fpscr=00000000
+vselge.f64 d7, d8, d10 2f46b6a224a9b26dfb35eb12d4ad50bc f46bdce9dd4c503b8c78011defefc04a c3a1b08243033786b7c84ab17d3be225 8c78011defefc04afb35eb12d4ad50bc f46bdce9dd4c503b8c78011defefc04a c3a1b08243033786b7c84ab17d3be225 fpscr=00000000
+vselge.f64 d7, d8, d10 35623ea06909e69bf4ae69f33c480a53 33f2cc7dd6bb9c2cca197db5feb72438 31b5254262bdc16b771596f6d81f3374 ca197db5feb72438f4ae69f33c480a53 33f2cc7dd6bb9c2cca197db5feb72438 31b5254262bdc16b771596f6d81f3374 fpscr=00000000
+vselge.f64 d7, d8, d10 eb0e45f4f7eae27ec0f14ecb50a5fc04 f684562c36ddb9ea8ea8c8d0e79a950e abba23c025e6d5d2e99c2ac801d7a6e2 8ea8c8d0e79a950ec0f14ecb50a5fc04 f684562c36ddb9ea8ea8c8d0e79a950e abba23c025e6d5d2e99c2ac801d7a6e2 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 2c1b224d3e4395de8b5fc46113474bc4 8283f87c7f421f4912638e4626edfac3 beaf642702c9ac2087e109bc0d20ad2c 12638e4626edfac38b5fc46113474bc4 8283f87c7f421f4912638e4626edfac3 beaf642702c9ac2087e109bc0d20ad2c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 23439e5525914b7f6c80ce6328d14c4f 3b879f7ed58417a23b879f7ed58417a2 4ea3f35b274283763483e142978babb4 3b879f7ed58417a26c80ce6328d14c4f 3b879f7ed58417a23b879f7ed58417a2 4ea3f35b274283763483e142978babb4 fpscr=00000000
+vselge.f64 d7, d8, d10 d5f625fee533c9ac40c2027b6ef50219 26cce3d22e428611c200d10412f69ba3 de0fee83708cf6737d9e7877b9a3b333 c200d10412f69ba340c2027b6ef50219 26cce3d22e428611c200d10412f69ba3 de0fee83708cf6737d9e7877b9a3b333 fpscr=00000000
+vselge.f64 d7, d8, d10 e524262020669f6fdacc5d7113531763 b17d7d8194a0538e824a418418f0b958 2737c8cbeddc2b312ce5ddc92aa7904e 824a418418f0b958dacc5d7113531763 b17d7d8194a0538e824a418418f0b958 2737c8cbeddc2b312ce5ddc92aa7904e fpscr=00000000
+vselge.f64 d7, d8, d10 cd19a8f37bb80620d01d92b83e4c403a 6692a424fc88e808604c7cfc2a781815 38b0aec1474b46a8d94636311f444222 604c7cfc2a781815d01d92b83e4c403a 6692a424fc88e808604c7cfc2a781815 38b0aec1474b46a8d94636311f444222 fpscr=00000000
+vselge.f64 d7, d8, d10 5818643e888b037969929732973d033b 797f021438844d02a38f5943215d8ac5 7b9f006ce9dcecb04919610958335bce a38f5943215d8ac569929732973d033b 797f021438844d02a38f5943215d8ac5 7b9f006ce9dcecb04919610958335bce fpscr=00000000
+vselge.f64 d7, d8, d10 c616893fedf747e7e3b7188215a149fe d247bb0dec2ea57f37c5af844c56a6d2 c282024505efe2bb5e680f8bd808d4a0 37c5af844c56a6d2e3b7188215a149fe d247bb0dec2ea57f37c5af844c56a6d2 c282024505efe2bb5e680f8bd808d4a0 fpscr=00000000
+vselge.f64 d7, d8, d10 20e1106551b53bb68b07cdad1dcc957f 368e1cc3188fca46c4038221f7f38807 ce16f2bacbea6990f0908c45fcf43e06 c4038221f7f388078b07cdad1dcc957f 368e1cc3188fca46c4038221f7f38807 ce16f2bacbea6990f0908c45fcf43e06 fpscr=00000000
+vselge.f64 d7, d8, d10 fcb5b0988ed3ed6fa5a46224d78477c5 debd8d75ea60e0a4508b474b138ad250 4f0c6dd2c295409d0d24fbf1bd35c236 508b474b138ad250a5a46224d78477c5 debd8d75ea60e0a4508b474b138ad250 4f0c6dd2c295409d0d24fbf1bd35c236 fpscr=00000000
+vselge.f64 d7, d8, d10 3bd347680aaab4228a0b10877f5c8727 291397a9ba7f9e19ccd6b6f28eac089f 8eb45934c0c5bf89c26cb8dce73ec9b8 ccd6b6f28eac089f8a0b10877f5c8727 291397a9ba7f9e19ccd6b6f28eac089f 8eb45934c0c5bf89c26cb8dce73ec9b8 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 b10a44033e825486b10a44033e825486 653ab778fcbada2d54bed9dca1146904 9f4d651fe1890b769f4d651fe1890b76 54bed9dca1146904b10a44033e825486 653ab778fcbada2d54bed9dca1146904 9f4d651fe1890b769f4d651fe1890b76 fpscr=00000000
+vselge.f64 d7, d8, d10 c8011cc8a7dc73ed183713208e6e2a22 54ff526986b9c7d9eb61d469d49e0a48 f0846cae958bbf1fe8e9bb56dee959ba eb61d469d49e0a48183713208e6e2a22 54ff526986b9c7d9eb61d469d49e0a48 f0846cae958bbf1fe8e9bb56dee959ba fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 b8782ccb88336084b8782ccb88336084 742ef9b0a22bd197c376de3baf5fdb8c 69c662988b5f5746fb941b276fefe9c6 c376de3baf5fdb8cb8782ccb88336084 742ef9b0a22bd197c376de3baf5fdb8c 69c662988b5f5746fb941b276fefe9c6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 b20c2785c541876db20c2785c541876d 032db762c30b75b069dea946e0b179be 181f0f0b8f5d0353bc2f2ffdc2c55b0f 69dea946e0b179beb20c2785c541876d 032db762c30b75b069dea946e0b179be 181f0f0b8f5d0353bc2f2ffdc2c55b0f fpscr=00000000
+vselge.f64 d7, d8, d10 3c09c110a7a3ccf943504995e94a77e4 d2893ae6ff22b433bbdde4c7ff080c84 f49e747ba1b053546a8f11cbec2196ce bbdde4c7ff080c8443504995e94a77e4 d2893ae6ff22b433bbdde4c7ff080c84 f49e747ba1b053546a8f11cbec2196ce fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 0fa9ad03d399277fd05ca4f26ef8025f 512005ca47f71b72512005ca47f71b72 8f37f9d4b7c27dfe029229e0fac199e9 512005ca47f71b72d05ca4f26ef8025f 512005ca47f71b72512005ca47f71b72 8f37f9d4b7c27dfe029229e0fac199e9 fpscr=00000000
+vselge.f64 d7, d8, d10 fcb4b3e7a908c6d194412d3c5bdb13e5 3155405557892d6649f507b77e997223 aa1a958555027b09baf22fda37cd3760 49f507b77e99722394412d3c5bdb13e5 3155405557892d6649f507b77e997223 aa1a958555027b09baf22fda37cd3760 fpscr=00000000
+randV128: 512 calls, 530 iters
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 d44486b5a6a102107e8ef40422303b1b db5aa202e2121f7aa8d894a9c470d958 326c6c233ef813ba0fe17c5753958e24 a8d894a9c470d9587e8ef40422303b1b db5aa202e2121f7aa8d894a9c470d958 326c6c233ef813ba0fe17c5753958e24 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 d6af490cad91217056d5748db6b4df58 16edd04b278464bc28f0c8ad90647a74 9666b4d4f37549976fb022ffaa75e46d 28f0c8ad90647a7456d5748db6b4df58 16edd04b278464bc28f0c8ad90647a74 9666b4d4f37549976fb022ffaa75e46d fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 ac07cce3ec6d05a4b6a1a4cd9e883257 e901fcadd70937b3956de6fb929444b1 1e83edc02ffa57cb1e83edc02ffa57cb 956de6fb929444b1b6a1a4cd9e883257 e901fcadd70937b3956de6fb929444b1 1e83edc02ffa57cb1e83edc02ffa57cb fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 e04f0d4312973a16fac0656f27a1a7bb 5e17e0b2d6d57a7db0e9535f056177dd b90e2f84fd0f2387b90e2f84fd0f2387 b0e9535f056177ddfac0656f27a1a7bb 5e17e0b2d6d57a7db0e9535f056177dd b90e2f84fd0f2387b90e2f84fd0f2387 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 5e44b0f9e0d5b9fa370241a91527f6b9 011bb2a0f5f10f15717d72120cd2c993 d9dbad27f70c3901ccb48a7230203299 717d72120cd2c993370241a91527f6b9 011bb2a0f5f10f15717d72120cd2c993 d9dbad27f70c3901ccb48a7230203299 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 f7d359b0d13fcfb804169a04d2f81662 6e74cdf571f9829134f3548dd9540466 98627c5eefe64192b7f7857aad810a9a 34f3548dd954046604169a04d2f81662 6e74cdf571f9829134f3548dd9540466 98627c5eefe64192b7f7857aad810a9a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 8d2b6b3e8e322a4ff6b6d1b75f0f9fb4 fe476aa231b0aaf9fe476aa231b0aaf9 fe73fd132e37396917085019174d71f9 fe476aa231b0aaf9f6b6d1b75f0f9fb4 fe476aa231b0aaf9fe476aa231b0aaf9 fe73fd132e37396917085019174d71f9 fpscr=00000000
+vselge.f64 d7, d8, d10 ae6674d2fb42f1655f05df749c5f3646 a78d90ffdc91cea49ae5c06573d83b22 5aaa117e7599eb792f879592071e89e2 9ae5c06573d83b225f05df749c5f3646 a78d90ffdc91cea49ae5c06573d83b22 5aaa117e7599eb792f879592071e89e2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 8de9d387376700458de9d38737670045 5d5cd44e174adb00a0567c2a86afc400 0648ac6426460c1c7493622cfa2597b6 a0567c2a86afc4008de9d38737670045 5d5cd44e174adb00a0567c2a86afc400 0648ac6426460c1c7493622cfa2597b6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 5a9fef0fb2dc303e71375e2906701b0e 403befabe5870936cd45f72008eb890f 08a2f98312aff067d5f03b44cf58f319 cd45f72008eb890f71375e2906701b0e 403befabe5870936cd45f72008eb890f 08a2f98312aff067d5f03b44cf58f319 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 3292b01c28f51c80557c76e23b6d7d67 65ba8b51dadbd02a2efc4a4c3cb79f06 0e442a090e2de0df0e442a090e2de0df 2efc4a4c3cb79f06557c76e23b6d7d67 65ba8b51dadbd02a2efc4a4c3cb79f06 0e442a090e2de0df0e442a090e2de0df fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 018a9ded9a32b2b658bb9dccbe78e080 31d4c3802458c320b8e9ef3655324c69 8bf7d8b25706c5dff7abfe7295d6f441 b8e9ef3655324c6958bb9dccbe78e080 31d4c3802458c320b8e9ef3655324c69 8bf7d8b25706c5dff7abfe7295d6f441 fpscr=00000000
+vselge.f64 d7, d8, d10 dc260bdc0b43237ef922696a0f05c22c f20e1dd4b168dbe16ecc3a09dfbd048c 64b651fc046084577ab57fbffe8986a7 6ecc3a09dfbd048cf922696a0f05c22c f20e1dd4b168dbe16ecc3a09dfbd048c 64b651fc046084577ab57fbffe8986a7 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 de9f39ff175e45afde9f39ff175e45af 1ec7ef10271064461273cbadb462d8dd 5f256ae7f57a25258fdf807367ff0cd7 1273cbadb462d8ddde9f39ff175e45af 1ec7ef10271064461273cbadb462d8dd 5f256ae7f57a25258fdf807367ff0cd7 fpscr=00000000
+vselge.f64 d7, d8, d10 ff3c4b3f064d8c217557cde51027645d 425df6d73059dd837e3e8527449ee9f4 cb297d14227fde7c0f14944c6efdbc0d 7e3e8527449ee9f47557cde51027645d 425df6d73059dd837e3e8527449ee9f4 cb297d14227fde7c0f14944c6efdbc0d fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselgt.f32 s15,s16,s20 1bdf8d327099a8084857c13907f4e2b8 cf8ab30ab9b9dc22f7579b2891a81344 9526bc45f7a76187effcd880ce0be4bb 91a813447099a8084857c13907f4e2b8 cf8ab30ab9b9dc22f7579b2891a81344 9526bc45f7a76187effcd880ce0be4bb fpscr=00000000
+vselgt.f32 s15,s16,s20 c9c0b3124ecb70f79979a7ae01844088 2d3ffa9d1614be74a19641dae470df8a f18c6ed01230ff3e8365b8b6c1363c54 e470df8a4ecb70f79979a7ae01844088 2d3ffa9d1614be74a19641dae470df8a f18c6ed01230ff3e8365b8b6c1363c54 fpscr=00000000
+vselgt.f32 s15,s16,s20 eec0a594220beffe1db4b81f2b597541 085f2ae05c723ca7542a15dacc33b1e8 7bc9cbffb9f9c3f1e39422d258859818 cc33b1e8220beffe1db4b81f2b597541 085f2ae05c723ca7542a15dacc33b1e8 7bc9cbffb9f9c3f1e39422d258859818 fpscr=00000000
+vselgt.f32 s15,s16,s20 2d4071b09e34d197ade8b4986d6b0591 ebd55f51b7352d94362d6f4fc8df6c3a 7f23ae157d67454552a7246adc911c23 c8df6c3a9e34d197ade8b4986d6b0591 ebd55f51b7352d94362d6f4fc8df6c3a 7f23ae157d67454552a7246adc911c23 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[2]
+vselgt.f32 s15,s16,s20 e81f605f6011b79f6011b79f7a8390a6 90a557fdbc7d9bd9764c8b686f3a23b6 0ef0bee102374fafd4e3e2ff7367dd2b 6f3a23b66011b79f6011b79f7a8390a6 90a557fdbc7d9bd9764c8b686f3a23b6 0ef0bee102374fafd4e3e2ff7367dd2b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vselgt.f32 s15,s16,s20 b2aa237461d97084eb06887153eff01a c9cfa6ab4754a2195bd22fb34754a219 895df1dcc89783ffad7ef35a4cf4eb6b 4754a21961d97084eb06887153eff01a c9cfa6ab4754a2195bd22fb34754a219 895df1dcc89783ffad7ef35a4cf4eb6b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[3]
+vselgt.f32 s15,s16,s20 70670d2b81b02e0f0a0edcee4d2cc878 18e8bf66df043a12308c280e5e7c1153 7d4ca4d5e89f7a600a82ee30cd29d94c 5e7c115381b02e0f0a0edcee4d2cc878 18e8bf66df043a12308c280e5e7c1153 7d4ca4d5e89f7a600a82ee30cd29d94c fpscr=00000000
+vselgt.f32 s15,s16,s20 d9bdcc893028e602d73eb2831f4bf609 1a6853f6be84f8bb673f4fc8c387756f 6d6a3f50029353f1b5ac7f6f455b745c c387756f3028e602d73eb2831f4bf609 1a6853f6be84f8bb673f4fc8c387756f 6d6a3f50029353f1b5ac7f6f455b745c fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vselgt.f32 s15,s16,s20 1e876212d6c92a1344cea455fc4eef9f f57b7629851fcfdef394463cd1c7914d f11f910033957a94279b0a97cbc7ac5e d1c7914dd6c92a1344cea455fc4eef9f f57b7629851fcfdef394463cd1c7914d f11f910033957a94279b0a97cbc7ac5e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vselgt.f32 s15,s16,s20 7bcc8918719010b51f8d0a9a7bcc8918 f209e1392f0631401ae5027aa91a00bc 605a3bd8bf3e07b2c2da04a6f33908f3 a91a00bc719010b51f8d0a9a7bcc8918 f209e1392f0631401ae5027aa91a00bc 605a3bd8bf3e07b2c2da04a6f33908f3 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[3]
+vselgt.f32 s15,s16,s20 76795aaf7a3a63326053ff312e26dd2d 1cef651c6c49c9b9c3455d9993e4a5f1 753e762872ee82410613768d72ee8241 93e4a5f17a3a63326053ff312e26dd2d 1cef651c6c49c9b9c3455d9993e4a5f1 753e762872ee82410613768d72ee8241 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vselgt.f32 s15,s16,s20 0f86961d0dfe0e02951a8f772c44efed 22fc2fbc3120de9c6479e10d450f9d06 7879495083fdabe878794950fd4f567a 450f9d060dfe0e02951a8f772c44efed 22fc2fbc3120de9c6479e10d450f9d06 7879495083fdabe878794950fd4f567a fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vselgt.f32 s15,s16,s20 24672c54caa9aa633342e0b5d4f4aeda 19278d62f4b822f982cef9da2674b1f9 c3e2025a96a7091a1f4f5923c556de8f 2674b1f9caa9aa633342e0b5d4f4aeda 19278d62f4b822f982cef9da2674b1f9 c3e2025a96a7091a1f4f5923c556de8f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselgt.f32 s15,s16,s20 015af8db989c4ca73ffe15972ad99232 3038d0cec7409e243038d0ce7b07f98f 1855d89a262a1b0a53270c4dcc860398 7b07f98f989c4ca73ffe15972ad99232 3038d0cec7409e243038d0ce7b07f98f 1855d89a262a1b0a53270c4dcc860398 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vselgt.f32 s15,s16,s20 2dee1843b5e8784c7c8c4889516eeebe 617c8954617c8954a5cbcde8d1860844 0b85da88ee6240d4fab6c9afe737c931 d1860844b5e8784c7c8c4889516eeebe 617c8954617c8954a5cbcde8d1860844 0b85da88ee6240d4fab6c9afe737c931 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vselgt.f32 s15,s16,s20 7908d297e250bfd0beb18ef33bda55a8 c02a0d5fff7bec35055605a42bdaf0c7 3ec6594828ea00ce852ad4015bd9be35 2bdaf0c7e250bfd0beb18ef33bda55a8 c02a0d5fff7bec35055605a42bdaf0c7 3ec6594828ea00ce852ad4015bd9be35 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vselgt.f32 s15,s16,s20 8811bde81e25ab197c2f544bc3a505c0 5b031ff9e7ae8c119c803647a19ed837 c65eabd1c65eabd1fd787344eab396a5 a19ed8371e25ab197c2f544bc3a505c0 5b031ff9e7ae8c119c803647a19ed837 c65eabd1c65eabd1fd787344eab396a5 fpscr=00000000
+vselgt.f32 s15,s16,s20 9a8034e6e3ed64baedc4d347f131748c 173f4b15840aefbd68c882e0ba868812 92595c78dc164f3e6b0b450ee14a3f63 ba868812e3ed64baedc4d347f131748c 173f4b15840aefbd68c882e0ba868812 92595c78dc164f3e6b0b450ee14a3f63 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[0]
+vselgt.f32 s15,s16,s20 c1646445ad3ed3b57d49d58462983027 4114a950baae5dda57a6295a9c342f97 0c48c120052fffdbd7daec0268b166e8 9c342f97ad3ed3b57d49d58462983027 4114a950baae5dda57a6295a9c342f97 0c48c120052fffdbd7daec0268b166e8 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vselgt.f32 s15,s16,s20 4f4243ae39614780efa667b5aedab485 05b02563c9fa6eef4b33b2ee05b02563 fcaee0ded12dca0df26a17d4498d2688 05b0256339614780efa667b5aedab485 05b02563c9fa6eef4b33b2ee05b02563 fcaee0ded12dca0df26a17d4498d2688 fpscr=00000000
+vselgt.f32 s15,s16,s20 de7208c800b715da12557654765782b0 f0d64bb3c491e2964c871592462727ca f3b17280fe8bd0af2574688c737559b2 462727ca00b715da12557654765782b0 f0d64bb3c491e2964c871592462727ca f3b17280fe8bd0af2574688c737559b2 fpscr=00000000
+vselgt.f32 s15,s16,s20 1c44b8009d306bbad4fdc8b28c2e7caa 8a171d1a294d48dac018701d2c9c4cc5 adf8d51b36a1754467de8de308363b05 2c9c4cc59d306bbad4fdc8b28c2e7caa 8a171d1a294d48dac018701d2c9c4cc5 adf8d51b36a1754467de8de308363b05 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vselgt.f32 s15,s16,s20 1a8250dd1a8250ddf0ce0ae3dd1fb618 34ff9e689545c592399af877a2488f5a 912f8374159df2f7085589b343d21f25 a2488f5a1a8250ddf0ce0ae3dd1fb618 34ff9e689545c592399af877a2488f5a 912f8374159df2f7085589b343d21f25 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselgt.f32 s15,s16,s20 e0fab6f1097a591efbe94e37d632c5c5 18b62fb46893080a18b62fb42368e72c b80b650cfe693570ed7e83558122a32f 2368e72c097a591efbe94e37d632c5c5 18b62fb46893080a18b62fb42368e72c b80b650cfe693570ed7e83558122a32f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vselgt.f32 s15,s16,s20 33bddc2fc7a026fecd171aec33bddc2f b1a4ca4f181791f3d454c04f06a53778 c68c6485c6adf116dec9468c558d9860 06a53778c7a026fecd171aec33bddc2f b1a4ca4f181791f3d454c04f06a53778 c68c6485c6adf116dec9468c558d9860 fpscr=00000000
+vselgt.f32 s15,s16,s20 29a983126fa213d785a320168623013c 5683bcd06b852bf92251cb35169b864d 815ea08ffe762184b4b96d2e26a96f0d 169b864d6fa213d785a320168623013c 5683bcd06b852bf92251cb35169b864d 815ea08ffe762184b4b96d2e26a96f0d fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselgt.f32 s15,s16,s20 c1138d54839bd88d84ce1ec208da666e 5c7e82920db77e6cea21645ba286f1eb 54bf2328bcdbe96673dca83ac0d55211 a286f1eb839bd88d84ce1ec208da666e 5c7e82920db77e6cea21645ba286f1eb 54bf2328bcdbe96673dca83ac0d55211 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[1]
+randV128: 768 calls, 799 iters
+vselgt.f32 s15,s16,s20 cf8ff14acf8ff14a5a254e46354122d6 465c83497b47d5b77f61bafe67d20d3b 322ae60a0d6cd20b6d770c50d4ac6c0d 67d20d3bcf8ff14a5a254e46354122d6 465c83497b47d5b77f61bafe67d20d3b 322ae60a0d6cd20b6d770c50d4ac6c0d fpscr=00000000
+vselgt.f32 s15,s16,s20 1fb513253fbf0bbad8c8679e1814cac1 8d162d9b0d5f9d85c79bcbad7f7df9d3 a11e8b73b8f2cb4a028bdedbd8609b86 7f7df9d33fbf0bbad8c8679e1814cac1 8d162d9b0d5f9d85c79bcbad7f7df9d3 a11e8b73b8f2cb4a028bdedbd8609b86 fpscr=00000000
+vselgt.f32 s15,s16,s20 9a660dfbf22d561be6f39a2c0cfb3058 7a7b4e2ba2eb89d3b39f1de9625c24b1 ea603563102a8d410ebd081fb5bb3711 625c24b1f22d561be6f39a2c0cfb3058 7a7b4e2ba2eb89d3b39f1de9625c24b1 ea603563102a8d410ebd081fb5bb3711 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vselgt.f32 s15,s16,s20 56ee33f7ac3926cc5df566ae80e65d3a 20e931e49bb2bad46a21352852c83b9f e4841621bb7f912713317dcabb7f9127 52c83b9fac3926cc5df566ae80e65d3a 20e931e49bb2bad46a21352852c83b9f e4841621bb7f912713317dcabb7f9127 fpscr=00000000
+vselgt.f32 s15,s16,s20 eeda52f02c35e59e0949a14bfd2150e7 408c9b2067aa17b9a984144ef62b496d f81b4f5fe03bec2401c8b1f90f4166de f62b496d2c35e59e0949a14bfd2150e7 408c9b2067aa17b9a984144ef62b496d f81b4f5fe03bec2401c8b1f90f4166de fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[0]
+vselgt.f32 s15,s16,s20 2767dabd36ee9d2036ee9d202debefba 7c7da2b845c144f16c1720c22c991b84 28b1fa34a6deaa2f202ba309356f0684 2c991b8436ee9d2036ee9d202debefba 7c7da2b845c144f16c1720c22c991b84 28b1fa34a6deaa2f202ba309356f0684 fpscr=00000000
+vselgt.f32 s15,s16,s20 e32ad2203fe937d71e545a5fb8b48c3f e604f15032609bb07bb871573e5b1e29 b5f5ec755f52e2ebeaa1e43c6c12f793 3e5b1e293fe937d71e545a5fb8b48c3f e604f15032609bb07bb871573e5b1e29 b5f5ec755f52e2ebeaa1e43c6c12f793 fpscr=00000000
+vselgt.f32 s15,s16,s20 2f9e68b12a89d1a702ab5bb74d390b29 a66de0615ea0d6431181b10449c8c169 dac5cb275692ecb1c505708ac878d540 49c8c1692a89d1a702ab5bb74d390b29 a66de0615ea0d6431181b10449c8c169 dac5cb275692ecb1c505708ac878d540 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vselgt.f32 s15,s16,s20 cac1d1b9d32d0b7e5bc51a46ecf76376 3d66fcd8901008394c881899882591e9 1ee0af201fb673430704090f5eec3703 882591e9d32d0b7e5bc51a46ecf76376 3d66fcd8901008394c881899882591e9 1ee0af201fb673430704090f5eec3703 fpscr=00000000
+vselgt.f32 s15,s16,s20 efd6c9eeee462c3cb59631d8b85d1010 4f537eee9a86447020bf0b56034fb5f3 c1b02de71711f26e5d3d6fa6ce3475da 034fb5f3ee462c3cb59631d8b85d1010 4f537eee9a86447020bf0b56034fb5f3 c1b02de71711f26e5d3d6fa6ce3475da fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vselgt.f32 s15,s16,s20 b5100402bfc81bac17fee204eeb0cb5c f902c9a2df3e3cb7f382b0f6f902c9a2 087be4a6069c87098acb707f5aac4670 f902c9a2bfc81bac17fee204eeb0cb5c f902c9a2df3e3cb7f382b0f6f902c9a2 087be4a6069c87098acb707f5aac4670 fpscr=00000000
+vselgt.f32 s15,s16,s20 21e7c0a58301ba82fc21ccdd8545b41a d05b994fa60d240d51788bb7e1a16f74 81d0e521e29c6658b2fa89dd9a94fc17 e1a16f748301ba82fc21ccdd8545b41a d05b994fa60d240d51788bb7e1a16f74 81d0e521e29c6658b2fa89dd9a94fc17 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vselgt.f32 s15,s16,s20 a724eeacc1578d04928167d0df3f41e1 5f43e64aad74f7bbaf2e023b02afe680 db2e522a3dcd8bb349e538e7dda8ab04 02afe680c1578d04928167d0df3f41e1 5f43e64aad74f7bbaf2e023b02afe680 db2e522a3dcd8bb349e538e7dda8ab04 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[3]
+vselgt.f32 s15,s16,s20 bc17f33bcf2b9d39f9873247ef89ab93 10fd9f5e8e11ad01dcef0d56315a22fb a4727fdaa4727fda492ed6217b98d440 315a22fbcf2b9d39f9873247ef89ab93 10fd9f5e8e11ad01dcef0d56315a22fb a4727fdaa4727fda492ed6217b98d440 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vselgt.f32 s15,s16,s20 deea882120dc114c354a3cedacd46161 5d868c1b95d9e8bc430e287d74b10c3f 56ba6f87ff79947a339de73092581227 74b10c3f20dc114c354a3cedacd46161 5d868c1b95d9e8bc430e287d74b10c3f 56ba6f87ff79947a339de73092581227 fpscr=00000000
+vselgt.f32 s15,s16,s20 273c0d45399c9b122cd84390b7023133 d041932201ece1f76cab44100b00fb70 dd3a9c05382834d243e8102309289f04 0b00fb70399c9b122cd84390b7023133 d041932201ece1f76cab44100b00fb70 dd3a9c05382834d243e8102309289f04 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vselgt.f32 s15,s16,s20 3a753da06a31d380ece50912c7462ffa 1fb72fff96b0fe8e3bae1f8d37e3c323 99ad5ea9a1f602854dcb6e961a321c25 37e3c3236a31d380ece50912c7462ffa 1fb72fff96b0fe8e3bae1f8d37e3c323 99ad5ea9a1f602854dcb6e961a321c25 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vselgt.f32 s15,s16,s20 699bc759eb22cacbec75d26340ffddf6 d4b3e72358437eb891e7c38e901fb05a 3513b9ec899de43c17ad36d3ef68f9d7 901fb05aeb22cacbec75d26340ffddf6 d4b3e72358437eb891e7c38e901fb05a 3513b9ec899de43c17ad36d3ef68f9d7 fpscr=00000000
+vselgt.f32 s15,s16,s20 92a297dec2e9e3f6fb6753d7ab516c02 cba562eeb33a849b04af2e6fd3ee34fd 70577cc5c8b316502f90a52952a5b063 d3ee34fdc2e9e3f6fb6753d7ab516c02 cba562eeb33a849b04af2e6fd3ee34fd 70577cc5c8b316502f90a52952a5b063 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselgt.f32 s15,s16,s20 db7c936146eb0499db7c93615aeed631 0b160f8de8964a92b57b5f1836666691 a45c5cba0e542c3521fc5ae2b449f325 3666669146eb0499db7c93615aeed631 0b160f8de8964a92b57b5f1836666691 a45c5cba0e542c3521fc5ae2b449f325 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vselgt.f32 s15,s16,s20 c84b61ede9902ac1a3cdc80ab45f90eb 6ffff2e82aa56bb5772724df31a64658 1732c074b63b26eb09d0247b4a28d835 31a64658e9902ac1a3cdc80ab45f90eb 6ffff2e82aa56bb5772724df31a64658 1732c074b63b26eb09d0247b4a28d835 fpscr=00000000
+vselgt.f32 s15,s16,s20 8bc2195ff2ebb5a01b5604b6f74470da c5db529dcff48de39d2cd39e879f7672 90f12aa71dfe62fc52c992dd903d2549 879f7672f2ebb5a01b5604b6f74470da c5db529dcff48de39d2cd39e879f7672 90f12aa71dfe62fc52c992dd903d2549 fpscr=00000000
+vselgt.f32 s15,s16,s20 f8ed04aa9b8d23c1c1a6aef520e286d3 d98c7cf36c568aea8a316fe71b5c2e03 b7bdd5efa809001e348f5988c1f6c82a 1b5c2e039b8d23c1c1a6aef520e286d3 d98c7cf36c568aea8a316fe71b5c2e03 b7bdd5efa809001e348f5988c1f6c82a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 3f9c61edeb7496cb5e0437a54d260583 1a75ad5ef068bc8f1a75ad5ef068bc8f c9da1823673a07037584747d9f1860e8 1a75ad5ef068bc8f5e0437a54d260583 1a75ad5ef068bc8f1a75ad5ef068bc8f c9da1823673a07037584747d9f1860e8 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 e6136698d2279aa9136d4ada30fb9e4e ee40784b29393714ee40784b29393714 92147f5309d64b4392147f5309d64b43 ee40784b29393714136d4ada30fb9e4e ee40784b29393714ee40784b29393714 92147f5309d64b4392147f5309d64b43 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 65b43f63357ecd40529f337f2d5dda79 608f00c029de3613dbcdea9a46a0b761 4b4c78162e0a6d233614316bfe51ff7d dbcdea9a46a0b761529f337f2d5dda79 608f00c029de3613dbcdea9a46a0b761 4b4c78162e0a6d233614316bfe51ff7d fpscr=00000000
+vselgt.f64 d7, d8, d10 a5fdd4619ca3fbbaaadd3bcfd967e686 dae1eabc617c99524fccee06be57b0cd b602c7a266815d1ae592158f24400e74 4fccee06be57b0cdaadd3bcfd967e686 dae1eabc617c99524fccee06be57b0cd b602c7a266815d1ae592158f24400e74 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 398be9f9968adddb398be9f9968adddb ea0cca19594c6ff82708f45fa473320d 1527459fc84854711527459fc8485471 2708f45fa473320d398be9f9968adddb ea0cca19594c6ff82708f45fa473320d 1527459fc84854711527459fc8485471 fpscr=00000000
+vselgt.f64 d7, d8, d10 c1c79d7644a6cba105d03730bacf1eab 39d0589dbadedc5fb420fa5ec66b8ee2 9473a371e970cd3de35a4e1617453bcb b420fa5ec66b8ee205d03730bacf1eab 39d0589dbadedc5fb420fa5ec66b8ee2 9473a371e970cd3de35a4e1617453bcb fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 0f071e11dcec3cf9516423533673b907 0a24cae5e8b715cc2073569dc2fd10a6 975d9a3a089cacf06c3025f4e8aca8ea 2073569dc2fd10a6516423533673b907 0a24cae5e8b715cc2073569dc2fd10a6 975d9a3a089cacf06c3025f4e8aca8ea fpscr=00000000
+vselgt.f64 d7, d8, d10 7b78995ea148096c521348c82dc23e60 b171946ef6718b834ce1f0729d0b39dd 37ff19ae21793f3502e53752964117a9 4ce1f0729d0b39dd521348c82dc23e60 b171946ef6718b834ce1f0729d0b39dd 37ff19ae21793f3502e53752964117a9 fpscr=00000000
+vselgt.f64 d7, d8, d10 f8cfe8e7d50668236613bf1f9e155c6e e40b49cae43a978153f481b302330083 60f6f31044959089d1fa1c6ad835ba25 53f481b3023300836613bf1f9e155c6e e40b49cae43a978153f481b302330083 60f6f31044959089d1fa1c6ad835ba25 fpscr=00000000
+vselgt.f64 d7, d8, d10 e014b74b3e2d896242658b6cef5c9847 a5dc8513422b757997b8e3e78709360c e9a3c3904619f63f1c4b1b9f42235e7f 97b8e3e78709360c42658b6cef5c9847 a5dc8513422b757997b8e3e78709360c e9a3c3904619f63f1c4b1b9f42235e7f fpscr=00000000
+vselgt.f64 d7, d8, d10 3223bc404be66e836250454c3b390ef5 2920717443688dbee9625eec89f510d5 de7ec0f6e8e8c80e6e12660f94e0c017 e9625eec89f510d56250454c3b390ef5 2920717443688dbee9625eec89f510d5 de7ec0f6e8e8c80e6e12660f94e0c017 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselgt.f64 d7, d8, d10 cba393991642f0124f764588d0158833 ef6f5df4580476feef6f5df4580476fe d9d62b65994cc8a7e6f3a0a57d8b0bb2 ef6f5df4580476fe4f764588d0158833 ef6f5df4580476feef6f5df4580476fe d9d62b65994cc8a7e6f3a0a57d8b0bb2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselgt.f64 d7, d8, d10 4e2f953af06edcdf4e2f953af06edcdf 298bd0f8923b179aed553385d2a045fc 6a50db4f1b9ccfb00ac9f644af6c35b5 ed553385d2a045fc4e2f953af06edcdf 298bd0f8923b179aed553385d2a045fc 6a50db4f1b9ccfb00ac9f644af6c35b5 fpscr=00000000
+vselgt.f64 d7, d8, d10 4ac240cfc8be0f381ae8e01f521ca43e cbcccaa715e279b7db6a963b13c1e3ca 51b853da308a1146e2e32500cd8fd7cb db6a963b13c1e3ca1ae8e01f521ca43e cbcccaa715e279b7db6a963b13c1e3ca 51b853da308a1146e2e32500cd8fd7cb fpscr=00000000
+vselgt.f64 d7, d8, d10 3726b86f381e19ddf1bb3242f811ed9d 5bbc95f9413a82184f5f247e5d780d4a a50633a077162f6cae00d9a9616fd38c 4f5f247e5d780d4af1bb3242f811ed9d 5bbc95f9413a82184f5f247e5d780d4a a50633a077162f6cae00d9a9616fd38c fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 a00a527c7a3e71272144a3295695755d 9a7dff326017a1e19514df37fbf87121 caac6481b790423fcaac6481b790423f 9514df37fbf871212144a3295695755d 9a7dff326017a1e19514df37fbf87121 caac6481b790423fcaac6481b790423f fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselgt.f64 d7, d8, d10 7e63cc59cccbd0a3b1a06db3c73ae0ca 105015f526edba740e2eb08a2a8571c6 e2dc7727337c2dd90fe42aefa4ee5824 0e2eb08a2a8571c6b1a06db3c73ae0ca 105015f526edba740e2eb08a2a8571c6 e2dc7727337c2dd90fe42aefa4ee5824 fpscr=00000000
+vselgt.f64 d7, d8, d10 6340ab234dd474bfd8d4c662fd870459 c41ba68cab6ca586b60aafceb9d47da8 246ebcbf3251632ec2c358364bdd041f b60aafceb9d47da8d8d4c662fd870459 c41ba68cab6ca586b60aafceb9d47da8 246ebcbf3251632ec2c358364bdd041f fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 57d4be27c1a5174d78728950fadd603a 2b62627b86d0bd834973a67642acd16d 38d8d49260898789ecfa86c5322e33ad 4973a67642acd16d78728950fadd603a 2b62627b86d0bd834973a67642acd16d 38d8d49260898789ecfa86c5322e33ad fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 65838ecb00f2cfa75f72d29952a65385 4888ed9f8dfeec004888ed9f8dfeec00 57a35145a25b79f3c74fd35be6ea59de 4888ed9f8dfeec005f72d29952a65385 4888ed9f8dfeec004888ed9f8dfeec00 57a35145a25b79f3c74fd35be6ea59de fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: 1024 calls, 1064 iters
+vselgt.f64 d7, d8, d10 f73708fe5d15565be8ebcc833e0bdb9b 3f4e8875327705273f4e887532770527 5e1fd2dbeff2b0d603a742d668fbec83 3f4e887532770527e8ebcc833e0bdb9b 3f4e8875327705273f4e887532770527 5e1fd2dbeff2b0d603a742d668fbec83 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselgt.f64 d7, d8, d10 e5349918a6f9c50683e46cdc819cfa68 98305776f15e5cf5c8e20f698a92d77d 82daa912c843a17682daa912c843a176 c8e20f698a92d77d83e46cdc819cfa68 98305776f15e5cf5c8e20f698a92d77d 82daa912c843a17682daa912c843a176 fpscr=00000000
+vselgt.f64 d7, d8, d10 7323e8ea339093584e082524b12c5130 01cb88ac89d491f84d4d934bc2448062 46592dddc3c391a4d67da7770a72bf3d 4d4d934bc24480624e082524b12c5130 01cb88ac89d491f84d4d934bc2448062 46592dddc3c391a4d67da7770a72bf3d fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 9e79ad9453d8d768a855ef96dd4b939b a7ea5ccd5933675fd3bd93203fa5ba14 069ba01413e4b550069ba01413e4b550 d3bd93203fa5ba14a855ef96dd4b939b a7ea5ccd5933675fd3bd93203fa5ba14 069ba01413e4b550069ba01413e4b550 fpscr=00000000
+vselgt.f64 d7, d8, d10 e0aecdb528fb1fc3c84278a4d83ca49b 21d698972394a54142cc6e0151dec49a 3fb20d08ace4ab781ce8746b100c316e 42cc6e0151dec49ac84278a4d83ca49b 21d698972394a54142cc6e0151dec49a 3fb20d08ace4ab781ce8746b100c316e fpscr=00000000
+vselgt.f64 d7, d8, d10 c10abff54f770a20112dfaa1871c6200 43583eca9ac1499f50e117ffbffc9fce fbb76d0b454872abd2b6d05e3da6aec2 50e117ffbffc9fce112dfaa1871c6200 43583eca9ac1499f50e117ffbffc9fce fbb76d0b454872abd2b6d05e3da6aec2 fpscr=00000000
+vselgt.f64 d7, d8, d10 55824ec083b68efd935b3cb06092f214 b24784367524062b5f2442f91082ee85 fe6b68441c3cd4473b05d3739b191eb1 5f2442f91082ee85935b3cb06092f214 b24784367524062b5f2442f91082ee85 fe6b68441c3cd4473b05d3739b191eb1 fpscr=00000000
+vselgt.f64 d7, d8, d10 04ec8007dcd8259eb46706a116fb3594 d6cd91b17366b498ce77a62fd04a04e8 f5428bf658d74321fc004f843c995e19 ce77a62fd04a04e8b46706a116fb3594 d6cd91b17366b498ce77a62fd04a04e8 f5428bf658d74321fc004f843c995e19 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselgt.f64 d7, d8, d10 9982253f796c209a63a01da4fc15ddf7 0517b5e37f453a794f416f41aa1f6327 f5beabf0cf43088f88eb2d9268163c40 4f416f41aa1f632763a01da4fc15ddf7 0517b5e37f453a794f416f41aa1f6327 f5beabf0cf43088f88eb2d9268163c40 fpscr=00000000
+vselgt.f64 d7, d8, d10 193d271dfad342faf8217f803d5d7d1f 043f2c2e6dd27b8f0f27d483ca4b472b 2a9ce0d2064f0c52702884ebd899d8ab 0f27d483ca4b472bf8217f803d5d7d1f 043f2c2e6dd27b8f0f27d483ca4b472b 2a9ce0d2064f0c52702884ebd899d8ab fpscr=00000000
+vselgt.f64 d7, d8, d10 856cf8e6fde3d28de790762347678e7a f82ffe4ce70ef4d4efe07d64463843f2 dbd17c208e78e97e546b8297a6ac08f0 efe07d64463843f2e790762347678e7a f82ffe4ce70ef4d4efe07d64463843f2 dbd17c208e78e97e546b8297a6ac08f0 fpscr=00000000
+vselgt.f64 d7, d8, d10 046a7db02c2b212f4fcf7fd0c67407de 15331e31fe3a99b7b1906b87b46c65c6 d760347e7d32ec11688150cc43fe0f57 b1906b87b46c65c64fcf7fd0c67407de 15331e31fe3a99b7b1906b87b46c65c6 d760347e7d32ec11688150cc43fe0f57 fpscr=00000000
+vselgt.f64 d7, d8, d10 ab982ac5668794dba129791b5aa7b376 5bfd7037ca9edd979b2f27a881724708 de8a4e91eaff7c1a9c5cde179ef79e72 9b2f27a881724708a129791b5aa7b376 5bfd7037ca9edd979b2f27a881724708 de8a4e91eaff7c1a9c5cde179ef79e72 fpscr=00000000
+vselgt.f64 d7, d8, d10 55656554181c3df2324141abf98de883 7992362189c698dc26f0f74603b51746 525a4d9725b55308a2d1130289a02676 26f0f74603b51746324141abf98de883 7992362189c698dc26f0f74603b51746 525a4d9725b55308a2d1130289a02676 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 059c7386ba18e2f9059c7386ba18e2f9 2b6e84f65842f7a22b6e84f65842f7a2 d531965e6ba117763d3801f1069d2d32 2b6e84f65842f7a2059c7386ba18e2f9 2b6e84f65842f7a22b6e84f65842f7a2 d531965e6ba117763d3801f1069d2d32 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 2b346b02d6932174c4ec15b4a1525eba 24a53e153c75ce7a38f9d8685cf863ed 5f9c323a3760db545f9c323a3760db54 38f9d8685cf863edc4ec15b4a1525eba 24a53e153c75ce7a38f9d8685cf863ed 5f9c323a3760db545f9c323a3760db54 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselgt.f64 d7, d8, d10 d200cac69e767dba576370b0bec5daf5 64f0f9ad576c11e2ee5740c884baa187 625e27aef3b33e8b625e27aef3b33e8b ee5740c884baa187576370b0bec5daf5 64f0f9ad576c11e2ee5740c884baa187 625e27aef3b33e8b625e27aef3b33e8b fpscr=00000000
+vselgt.f64 d7, d8, d10 fb0650fe99e00077960d0e17e68462d8 80ad135ca102e2518a639b87f45de2a9 36f0caf8fe5634a37a25a79738a666c1 8a639b87f45de2a9960d0e17e68462d8 80ad135ca102e2518a639b87f45de2a9 36f0caf8fe5634a37a25a79738a666c1 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 4493cb3611bde6fb4493cb3611bde6fb 400ead755366854b7848c9e734cbc93e b81cfda24fbfb946c584c4cb1490405e 7848c9e734cbc93e4493cb3611bde6fb 400ead755366854b7848c9e734cbc93e b81cfda24fbfb946c584c4cb1490405e fpscr=00000000
+vselgt.f64 d7, d8, d10 37acd05b093195d4cc196042f3c4d2b3 d486c05060334f93b036e5cc76f58690 f460f6214260184275dda6294ff45552 b036e5cc76f58690cc196042f3c4d2b3 d486c05060334f93b036e5cc76f58690 f460f6214260184275dda6294ff45552 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 d23c65e0374dacd7d0c927f5ca8e84e4 dfef494e68903106cf285ec202de0303 7c3d35077afe6dcd70a6e690ccee61f6 cf285ec202de0303d0c927f5ca8e84e4 dfef494e68903106cf285ec202de0303 7c3d35077afe6dcd70a6e690ccee61f6 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 c31f59eefee506c3c31f59eefee506c3 d4ffb705e1afce6c8f2e9973c7f1b172 cc6139683c60ba304b49a168cb6a8c59 8f2e9973c7f1b172c31f59eefee506c3 d4ffb705e1afce6c8f2e9973c7f1b172 cc6139683c60ba304b49a168cb6a8c59 fpscr=00000000
+vselgt.f64 d7, d8, d10 0f07ab007ed849a4b42f2c62f6de8259 c8c9868974388f35dbeec777eec8e091 e7599c1d7941859f453ecc281e798668 dbeec777eec8e091b42f2c62f6de8259 c8c9868974388f35dbeec777eec8e091 e7599c1d7941859f453ecc281e798668 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 12ae4c89891b611cb72d1badd1706f6d 33ed6394a4e0fdd833ed6394a4e0fdd8 6d48ba65a049044f0a6ec6b4dfc0b99e 33ed6394a4e0fdd8b72d1badd1706f6d 33ed6394a4e0fdd833ed6394a4e0fdd8 6d48ba65a049044f0a6ec6b4dfc0b99e fpscr=00000000
+vselgt.f64 d7, d8, d10 b477b9e7f18bc6c3580edaccddcf5265 8fce0077d9a66558e02da4604c7f08c3 0f85e6ecc939fc5e6297549b24245209 e02da4604c7f08c3580edaccddcf5265 8fce0077d9a66558e02da4604c7f08c3 0f85e6ecc939fc5e6297549b24245209 fpscr=00000000
+vselgt.f64 d7, d8, d10 fccb1fa9e696df458dcfef3ab5d9369f accf209364f8c75664c64e9312a9df38 770f6e4fec8c7dd3e85ce1c95f9e523e 64c64e9312a9df388dcfef3ab5d9369f accf209364f8c75664c64e9312a9df38 770f6e4fec8c7dd3e85ce1c95f9e523e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 0282cde34cfcd26f0282cde34cfcd26f 3537db92ab191fd44d29f26f8d054574 d69677db647e10777a689d4468d096e9 4d29f26f8d0545740282cde34cfcd26f 3537db92ab191fd44d29f26f8d054574 d69677db647e10777a689d4468d096e9 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 00b3af3be3bd6611a42ecb216f22d818 546f267de84418ad1bee699375639b51 2b58e9fde83fe3f22b58e9fde83fe3f2 1bee699375639b51a42ecb216f22d818 546f267de84418ad1bee699375639b51 2b58e9fde83fe3f22b58e9fde83fe3f2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselgt.f64 d7, d8, d10 10e8927696ec55e2380329874e749e64 83c10380fea42b07395f10c1d376077a d09d8a5ac2fdb52fd3f7f22009bd1333 395f10c1d376077a380329874e749e64 83c10380fea42b07395f10c1d376077a d09d8a5ac2fdb52fd3f7f22009bd1333 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 527dae5149384fd86c205830e0157e2c ff2b5b221d444be6c3e7231053ca4553 e90fc207f5504bfada812af5642cc57f c3e7231053ca45536c205830e0157e2c ff2b5b221d444be6c3e7231053ca4553 e90fc207f5504bfada812af5642cc57f fpscr=00000000
+vseleq.f32 s15,s16,s20 2a442f7f3f29c72589d06df375f67db0 4ef5d56ceea1424e573c1461d21119cc f5b8fcab8605407346035a66572f9608 572f96083f29c72589d06df375f67db0 4ef5d56ceea1424e573c1461d21119cc f5b8fcab8605407346035a66572f9608 fpscr=00000000
+vseleq.f32 s15,s16,s20 e2c18409b920238bd18b730c72200055 041b20f49f05d205e056a7eaabf2fc5a f159e6804a208c3aef5c7d239c335778 9c335778b920238bd18b730c72200055 041b20f49f05d205e056a7eaabf2fc5a f159e6804a208c3aef5c7d239c335778 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vseleq.f32 s15,s16,s20 341fc0b0da11db6eb000a274a69bab7a d126249134f10473a47ba276512cbad6 7abc1e3f1f44a40d833548a11bad0962 1bad0962da11db6eb000a274a69bab7a d126249134f10473a47ba276512cbad6 7abc1e3f1f44a40d833548a11bad0962 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vseleq.f32 s15,s16,s20 66fa978a94423df7150f41089f081300 8d87596f8d87596f5995551c61781273 3a827ce46ded373e3d4d236c40560f95 40560f9594423df7150f41089f081300 8d87596f8d87596f5995551c61781273 3a827ce46ded373e3d4d236c40560f95 fpscr=00000000
+vseleq.f32 s15,s16,s20 f85523d79f9f0c7202154e95a2d3fe26 6380f154c19c1eb005b8c1eecab4c0be 2fe3d2a90bbf9e845e7b26ad220e47f3 220e47f39f9f0c7202154e95a2d3fe26 6380f154c19c1eb005b8c1eecab4c0be 2fe3d2a90bbf9e845e7b26ad220e47f3 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[1]
+vseleq.f32 s15,s16,s20 175da80b0a99d02a56b0dc4dc8f82dab 092de5e052d63dfd0158dc0142ab5ad3 6be226f5a384cc8b8c5092f134a93a24 34a93a240a99d02a56b0dc4dc8f82dab 092de5e052d63dfd0158dc0142ab5ad3 6be226f5a384cc8b8c5092f134a93a24 fpscr=00000000
+vseleq.f32 s15,s16,s20 a0d38bbad477182f3a52cc65df7154eb 104228ad24ae708daa8f6e6aaf719aae 28c508326540315023ce08b43c76375b 3c76375bd477182f3a52cc65df7154eb 104228ad24ae708daa8f6e6aaf719aae 28c508326540315023ce08b43c76375b fpscr=00000000
+vseleq.f32 s15,s16,s20 3ddfbe20ee62ed7bd14f57939b37f0b7 500e5bbebe48a67944424c4eaafcc2da de65816c1d3993c9015e3a1038765fba 38765fbaee62ed7bd14f57939b37f0b7 500e5bbebe48a67944424c4eaafcc2da de65816c1d3993c9015e3a1038765fba fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vseleq.f32 s15,s16,s20 5a2d2a208fa40aea8b37bb14690d0d90 879ff2e1ca394c0019fa007080b4b833 73e1918197b055d12912b29397b055d1 97b055d18fa40aea8b37bb14690d0d90 879ff2e1ca394c0019fa007080b4b833 73e1918197b055d12912b29397b055d1 fpscr=00000000
+vseleq.f32 s15,s16,s20 b1760ed37897654c15cdbb77b19c3542 8277ef56ae879d8e99ac994bb2d53a76 4164cf16b87e90aeee6c793d9640e208 9640e2087897654c15cdbb77b19c3542 8277ef56ae879d8e99ac994bb2d53a76 4164cf16b87e90aeee6c793d9640e208 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vseleq.f32 s15,s16,s20 442679afd4eda67346d348f7bc0cc35d 858ea70e5e5a3030a0f7f71cd8d73ba2 ee554afcbea9746b76a881358221d9c4 8221d9c4d4eda67346d348f7bc0cc35d 858ea70e5e5a3030a0f7f71cd8d73ba2 ee554afcbea9746b76a881358221d9c4 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[3]
+vseleq.f32 s15,s16,s20 9bbe97940e60c5b76dd928407deb9d4c 8319ddaa8319ddaa2dbeac5c7eac91a2 11069ac92e3c1e1611069ac9e197e4d5 e197e4d50e60c5b76dd928407deb9d4c 8319ddaa8319ddaa2dbeac5c7eac91a2 11069ac92e3c1e1611069ac9e197e4d5 fpscr=00000000
+vseleq.f32 s15,s16,s20 94bfe4da62c58c85ff520796ac20e992 f846d7e992fb614308eca488666fef2d 58df37d48349089d0edb61e6ccfdcd36 ccfdcd3662c58c85ff520796ac20e992 f846d7e992fb614308eca488666fef2d 58df37d48349089d0edb61e6ccfdcd36 fpscr=00000000
+randV128: 1280 calls, 1328 iters
+vseleq.f32 s15,s16,s20 b5f645db4a1e113763d81166622b730f bdde4a74f34bca9fd48fa5817f3e85e8 29a73642fea1590558474991d06a543b d06a543b4a1e113763d81166622b730f bdde4a74f34bca9fd48fa5817f3e85e8 29a73642fea1590558474991d06a543b fpscr=00000000
+vseleq.f32 s15,s16,s20 8d21b3d932dcba00d91125ece990acad 3f29605bf5c82079527e413731851f3b 6460d033a91fe9feddd1560c2411c369 2411c36932dcba00d91125ece990acad 3f29605bf5c82079527e413731851f3b 6460d033a91fe9feddd1560c2411c369 fpscr=00000000
+vseleq.f32 s15,s16,s20 b7e38909edb6a49feaa8da5aa184ced6 5c1414ab14a7d6623bed80734cd7c5bd ff2c8f9c4e2364608cb1cee2eacd5bdf eacd5bdfedb6a49feaa8da5aa184ced6 5c1414ab14a7d6623bed80734cd7c5bd ff2c8f9c4e2364608cb1cee2eacd5bdf fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vseleq.f32 s15,s16,s20 9d6799bdcdac0b328733f75f3759982f c081c5adc081c5ad24f43c6b291eb00c 4818d1194dd24462b1304608d35f2a2b d35f2a2bcdac0b328733f75f3759982f c081c5adc081c5ad24f43c6b291eb00c 4818d1194dd24462b1304608d35f2a2b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vseleq.f32 s15,s16,s20 e802f1c1e802f1c17ae72bc22e8f641e 7bdf1613f1beedcd2b896e509d357f78 7cb07d22cb4f3562ed6b1695236578ff 236578ffe802f1c17ae72bc22e8f641e 7bdf1613f1beedcd2b896e509d357f78 7cb07d22cb4f3562ed6b1695236578ff fpscr=00000000
+vseleq.f32 s15,s16,s20 c3504f080ead048d0bb4e834ca63e560 4bf498d4ce3cb40a749200c4309e084f d6cfb2e265f4d3df0f462c1d9d4bb3d5 9d4bb3d50ead048d0bb4e834ca63e560 4bf498d4ce3cb40a749200c4309e084f d6cfb2e265f4d3df0f462c1d9d4bb3d5 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vseleq.f32 s15,s16,s20 38d02a97a4326cfb19614c73775ff989 e32d1c61ec623ca54dff9473a96c852e 6ff669b0d2e063009660b1fd2ed965ff 2ed965ffa4326cfb19614c73775ff989 e32d1c61ec623ca54dff9473a96c852e 6ff669b0d2e063009660b1fd2ed965ff fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vseleq.f32 s15,s16,s20 c4275e212ad52c94c1f9fcdd3eaf5055 7e4677bc0ce53d760fbe5d13b05fde15 1324c00be6bb07206095e039b8abd1e9 b8abd1e92ad52c94c1f9fcdd3eaf5055 7e4677bc0ce53d760fbe5d13b05fde15 1324c00be6bb07206095e039b8abd1e9 fpscr=00000000
+vseleq.f32 s15,s16,s20 65f0bc6583d6f95db8e972df9787befa f6db7bd4ddf32d6b43b7c8ef3ae223cd a353739d03d6e8979b96acbbae82c2fb ae82c2fb83d6f95db8e972df9787befa f6db7bd4ddf32d6b43b7c8ef3ae223cd a353739d03d6e8979b96acbbae82c2fb fpscr=00000000
+vseleq.f32 s15,s16,s20 3d29b0d58bac37ba5050a0c705c0703f ca8f419b68669a6f5a18ba9d71c4b19a 9785fc301f7d5670e5028d706c8e8648 6c8e86488bac37ba5050a0c705c0703f ca8f419b68669a6f5a18ba9d71c4b19a 9785fc301f7d5670e5028d706c8e8648 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vseleq.f32 s15,s16,s20 a45857cd827a199ba578e424469fc3b3 ee5aae8a3df59efdb9e88be508aeba7a 411bb7cf5f266815af1733225facf1cd 5facf1cd827a199ba578e424469fc3b3 ee5aae8a3df59efdb9e88be508aeba7a 411bb7cf5f266815af1733225facf1cd fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vseleq.f32 s15,s16,s20 6aaffd8950c2ad7eee86dc86d89a02a4 72e132dbe8f38aabe32895889c597a7a 4eeda00065310174e1400c74661d014c 661d014c50c2ad7eee86dc86d89a02a4 72e132dbe8f38aabe32895889c597a7a 4eeda00065310174e1400c74661d014c fpscr=00000000
+vseleq.f32 s15,s16,s20 20aac7fba7035a204ce72d85dc4d808b edd9afb7e282d4fe0105456ef2468f27 1309051d4eacc4888ad6fb96068abf0c 068abf0ca7035a204ce72d85dc4d808b edd9afb7e282d4fe0105456ef2468f27 1309051d4eacc4888ad6fb96068abf0c fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vseleq.f32 s15,s16,s20 7980d06f7980d06fed6f2adb29971626 7aba1f33118f2529149b127bc394c1ea 2c2f3a49c56f31c8eaefee667eda2b42 7eda2b427980d06fed6f2adb29971626 7aba1f33118f2529149b127bc394c1ea 2c2f3a49c56f31c8eaefee667eda2b42 fpscr=00000000
+vseleq.f32 s15,s16,s20 8863eb170745f4639e63f81cb5cf2a2a 10044db5fdf63e525d3feba342c69747 a8ad0a908c9297293a6069a4d27e0618 d27e06180745f4639e63f81cb5cf2a2a 10044db5fdf63e525d3feba342c69747 a8ad0a908c9297293a6069a4d27e0618 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vseleq.f32 s15,s16,s20 30e8d05bcf5cb2663ddbe9c2a6f6e512 8635167e67ac5eb5aa17bb4e8635167e 158a0ccb99f6f56acd5650670442a34d 0442a34dcf5cb2663ddbe9c2a6f6e512 8635167e67ac5eb5aa17bb4e8635167e 158a0ccb99f6f56acd5650670442a34d fpscr=00000000
+vseleq.f32 s15,s16,s20 04802eb5d90d46256a9a5a4429cccc71 d26511e4ff0ce20a688d0961c2679665 2941597cf59bf63369468aca91e7bf5f 91e7bf5fd90d46256a9a5a4429cccc71 d26511e4ff0ce20a688d0961c2679665 2941597cf59bf63369468aca91e7bf5f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vseleq.f32 s15,s16,s20 c80ba6fbe7af32522831b206e8cd84de 01eda3c60b54746301eda3c6d6ae3f0e ea38cae3d86d22b459ca6ec48bb888ca 8bb888cae7af32522831b206e8cd84de 01eda3c60b54746301eda3c6d6ae3f0e ea38cae3d86d22b459ca6ec48bb888ca fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vseleq.f32 s15,s16,s20 549ca745513e432fc4285cd1c4285cd1 b4b3c7ac513e135cbf752caec4db9ebb c8e0abdeea179a30f3a2b7169958524e 9958524e513e432fc4285cd1c4285cd1 b4b3c7ac513e135cbf752caec4db9ebb c8e0abdeea179a30f3a2b7169958524e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vseleq.f32 s15,s16,s20 56eced5d2bed0a55ac5022f544895d65 646045ea0855a4db8aecc98cd29a05d8 464ff864464ff8642b9dcfe6f0e76a64 f0e76a642bed0a55ac5022f544895d65 646045ea0855a4db8aecc98cd29a05d8 464ff864464ff8642b9dcfe6f0e76a64 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vseleq.f32 s15,s16,s20 df85e6cbcd8274a02a159c8a2a159c8a 98a137169ed08fa2a2ad51411adc27c8 e6f2e4af9be86dd5d64c0ceb13c5d1ea 13c5d1eacd8274a02a159c8a2a159c8a 98a137169ed08fa2a2ad51411adc27c8 e6f2e4af9be86dd5d64c0ceb13c5d1ea fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vseleq.f32 s15,s16,s20 50b91eeffb24a85e19eac1c246587c4b ad51a4afa3951fc0ad51a4afebf0811f 7cf52d7adbda73576afadc07d461c5be d461c5befb24a85e19eac1c246587c4b ad51a4afa3951fc0ad51a4afebf0811f 7cf52d7adbda73576afadc07d461c5be fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[0]
+vseleq.f32 s15,s16,s20 155c00bfbffcb478a107a4a5bffcb478 a31d8010d7c5b28d562b256781909d84 90c25e5a46460db99b03be371a30d4ea 1a30d4eabffcb478a107a4a5bffcb478 a31d8010d7c5b28d562b256781909d84 90c25e5a46460db99b03be371a30d4ea fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vseleq.f32 s15,s16,s20 5bccaf0399e017716fda6d353c80d92e c7fd0aa5779e84ad615eec0be2d4069a 908de6d4beab8dbd606ef04866847d5c 66847d5c99e017716fda6d353c80d92e c7fd0aa5779e84ad615eec0be2d4069a 908de6d4beab8dbd606ef04866847d5c fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vseleq.f32 s15,s16,s20 f83ab7522c93e35c4a9ed0c18140ba1e 0a34096f4b1fa2cd6f5bf05bf25c2697 d93ddc870bec459f189a3bda2be719de 2be719de2c93e35c4a9ed0c18140ba1e 0a34096f4b1fa2cd6f5bf05bf25c2697 d93ddc870bec459f189a3bda2be719de fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vseleq.f32 s15,s16,s20 4a1c07014a17513d78586477b968384e fc97b59316ecfd5a6c1467c1654c1e90 e3680e1a99f0229f6064465260644652 606446524a17513d78586477b968384e fc97b59316ecfd5a6c1467c1654c1e90 e3680e1a99f0229f6064465260644652 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vseleq.f32 s15,s16,s20 55b67f0687e52afa6beb3f0c6beb3f0c a7e7c4465daaf8f65719a83e389ae908 842d0d22b7e5c00773cff78a6127c486 6127c48687e52afa6beb3f0c6beb3f0c a7e7c4465daaf8f65719a83e389ae908 842d0d22b7e5c00773cff78a6127c486 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vseleq.f32 s15,s16,s20 7438e5177180bc53b94bcd6155097fc4 d0a0fbea55a502d2d0a0fbeaa9a95a58 8a89d0e8fb196c32bd3d7a4b24a470f9 24a470f97180bc53b94bcd6155097fc4 d0a0fbea55a502d2d0a0fbeaa9a95a58 8a89d0e8fb196c32bd3d7a4b24a470f9 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vseleq.f32 s15,s16,s20 85fc1880a367493e9caa7d8817532c0e fea9c4fcc3e38a989f18b2dab4190ec0 edec575cae5beffa32ff73ebae5beffa ae5beffaa367493e9caa7d8817532c0e fea9c4fcc3e38a989f18b2dab4190ec0 edec575cae5beffa32ff73ebae5beffa fpscr=00000000
+vseleq.f32 s15,s16,s20 593892176f9b2e730a6477f66c8a09b0 e29887d09eee2923bd176f271d15f672 82db5771c6a6c0162d8e43a9cdb03e91 cdb03e916f9b2e730a6477f66c8a09b0 e29887d09eee2923bd176f271d15f672 82db5771c6a6c0162d8e43a9cdb03e91 fpscr=00000000
+vseleq.f32 s15,s16,s20 a35552ae5a03aa438878d134f064c3c8 989af7366f888734b026abafebc33787 6fd4375d04e57a2a97d5eef5aa4e0cd7 aa4e0cd75a03aa438878d134f064c3c8 989af7366f888734b026abafebc33787 6fd4375d04e57a2a97d5eef5aa4e0cd7 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vseleq.f32 s15,s16,s20 e7b14f54ab7185049b337ce7f5b461a0 0700975da04de2f3b3706a364da1adc6 ae0f307db8d9980db637fefbb637fefb b637fefbab7185049b337ce7f5b461a0 0700975da04de2f3b3706a364da1adc6 ae0f307db8d9980db637fefbb637fefb fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[3]
+vseleq.f32 s15,s16,s20 92c9db4f0768629292c9db4f6ac68aca e527e38fbfe9db5a360ff7af360ff7af 1406d41b64516599ff275af8518d666b 518d666b0768629292c9db4f6ac68aca e527e38fbfe9db5a360ff7af360ff7af 1406d41b64516599ff275af8518d666b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vseleq.f32 s15,s16,s20 ba868b5c4fdc104504b1e38195d7d957 0a40fde54650557bb0e5631d3720ea00 aae28ebe327427bc5ff800963a1f4020 3a1f40204fdc104504b1e38195d7d957 0a40fde54650557bb0e5631d3720ea00 aae28ebe327427bc5ff800963a1f4020 fpscr=00000000
+vseleq.f32 s15,s16,s20 2317928286b6ce8ad0166cde42c04b59 3e915188fb20e315c8fb07e70dd889d1 66aeb4e3b94723be200657ae56e61ddd 56e61ddd86b6ce8ad0166cde42c04b59 3e915188fb20e315c8fb07e70dd889d1 66aeb4e3b94723be200657ae56e61ddd fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[2]
+vseleq.f32 s15,s16,s20 84816d3c4cc655bb0f7b5edb5f59ede0 f35aa3766b2d140bf35aa3762c1746f4 b9c2430170a98b5f9282753b7f3f95a2 7f3f95a24cc655bb0f7b5edb5f59ede0 f35aa3766b2d140bf35aa3762c1746f4 b9c2430170a98b5f9282753b7f3f95a2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[1]
+vseleq.f32 s15,s16,s20 dd197c89fba99b25dd197c89e263dfb6 2e8cc2d8281af14681b732c523c2326d 550d50719989722807d7da346f2f6074 6f2f6074fba99b25dd197c89e263dfb6 2e8cc2d8281af14681b732c523c2326d 550d50719989722807d7da346f2f6074 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 e8e1c927addada11a6c73bdf5e7fbd85 cb96f09c2fc9268c6b7e9b93d19b5bba 9e1f821146911981b72983da1ddfa47d b72983da1ddfa47da6c73bdf5e7fbd85 cb96f09c2fc9268c6b7e9b93d19b5bba 9e1f821146911981b72983da1ddfa47d fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 b53c235c46486e774b773bc5de6d4be1 3f1b397d79033a03d712d082d1736ceb 5d722a864227fcd05d722a864227fcd0 5d722a864227fcd04b773bc5de6d4be1 3f1b397d79033a03d712d082d1736ceb 5d722a864227fcd05d722a864227fcd0 fpscr=00000000
+vseleq.f64 d7, d8, d10 09b5794d843f0c10d6262add1d7e702d da88fe1cfa0828d9015823c90739a0c5 e0cb80cf05611bff619065358cc061dc 619065358cc061dcd6262add1d7e702d da88fe1cfa0828d9015823c90739a0c5 e0cb80cf05611bff619065358cc061dc fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 9e66898026b4ad61be52ab5e419ed198 a6f557065fc07cb7a6f557065fc07cb7 ed4db65183a2bd306af5bb9081277c34 6af5bb9081277c34be52ab5e419ed198 a6f557065fc07cb7a6f557065fc07cb7 ed4db65183a2bd306af5bb9081277c34 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 2db581639913155b012a564eec402108 08fce825a42f83af9081814ecedcf17b c80d0d8d0892c2b18ac0326f92f544c1 8ac0326f92f544c1012a564eec402108 08fce825a42f83af9081814ecedcf17b c80d0d8d0892c2b18ac0326f92f544c1 fpscr=00000000
+randV128: 1536 calls, 1595 iters
+vseleq.f64 d7, d8, d10 b4923838ce1803aed8154112b81f1215 ed12f64a2fdf7940402282f316476c55 05eab7412d7368e76cfd35f721892d34 6cfd35f721892d34d8154112b81f1215 ed12f64a2fdf7940402282f316476c55 05eab7412d7368e76cfd35f721892d34 fpscr=00000000
+vseleq.f64 d7, d8, d10 971938f5ebed65cc4d7f293d9d790543 d73aef07be63fded627d1bce4ce0351c f4eff2fc7239a39c99d73f4ec6e5335d 99d73f4ec6e5335d4d7f293d9d790543 d73aef07be63fded627d1bce4ce0351c f4eff2fc7239a39c99d73f4ec6e5335d fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 435d66fee065aa82435d66fee065aa82 bb46e63d38e37ebd40f3bad5aedd625c 6878a7d79e993d19864acdc81e9d8711 864acdc81e9d8711435d66fee065aa82 bb46e63d38e37ebd40f3bad5aedd625c 6878a7d79e993d19864acdc81e9d8711 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 1dbf63c6e0948eecf363f7cefcda2d6b e36d1f5407c8246527734c8517ad2557 c2a877b6f6c0e32dc2a877b6f6c0e32d c2a877b6f6c0e32df363f7cefcda2d6b e36d1f5407c8246527734c8517ad2557 c2a877b6f6c0e32dc2a877b6f6c0e32d fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 56f63f9ef45df5b356f63f9ef45df5b3 ed522c046a4d330e65e03223557cced0 e9f57daed1254c33a14ac880f3b84c3c a14ac880f3b84c3c56f63f9ef45df5b3 ed522c046a4d330e65e03223557cced0 e9f57daed1254c33a14ac880f3b84c3c fpscr=00000000
+vseleq.f64 d7, d8, d10 8513a41c82218811983fe514d246fd45 3e1050271b8f4c06c1c6d81e6d774ce2 53d158a6d3399bb9470c4c8a595a8210 470c4c8a595a8210983fe514d246fd45 3e1050271b8f4c06c1c6d81e6d774ce2 53d158a6d3399bb9470c4c8a595a8210 fpscr=00000000
+vseleq.f64 d7, d8, d10 a55fa8df6641d52e6ea2e2dc54a10fc7 3262d882703fd813522b13c9de7de242 cda8c815645ddfc3969d32a6a75f7a73 969d32a6a75f7a736ea2e2dc54a10fc7 3262d882703fd813522b13c9de7de242 cda8c815645ddfc3969d32a6a75f7a73 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 4a371c043d62073e26324ee8587a8117 3d11797b59556e8ce0247e79413e93fd cc4704a7fd7539a6cc4704a7fd7539a6 cc4704a7fd7539a626324ee8587a8117 3d11797b59556e8ce0247e79413e93fd cc4704a7fd7539a6cc4704a7fd7539a6 fpscr=00000000
+vseleq.f64 d7, d8, d10 ed4ee26dd6e7401916eb479a7926673e 9e20d8eec432c40db1dd9cae316c95fa a64fb757cf0d76ca3c3107b68984d4db 3c3107b68984d4db16eb479a7926673e 9e20d8eec432c40db1dd9cae316c95fa a64fb757cf0d76ca3c3107b68984d4db fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 776f3ff8d06060f45e502021988f328d 91d1f8609c23e1fd91d1f8609c23e1fd 036ab43b0d56205ba781d781d92b430e a781d781d92b430e5e502021988f328d 91d1f8609c23e1fd91d1f8609c23e1fd 036ab43b0d56205ba781d781d92b430e fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 df996abe5602a84d3a8792ed33410284 f226f070a8a60a04ca3943a33c6069de e2eeb2b7639ccfa08f7aab0a3b944097 8f7aab0a3b9440973a8792ed33410284 f226f070a8a60a04ca3943a33c6069de e2eeb2b7639ccfa08f7aab0a3b944097 fpscr=00000000
+vseleq.f64 d7, d8, d10 e76006f725db600f146a48c1c8566bfc f68a0b8459738887cd96c3a8bc9a5043 8b34c676e83d0aef0c8d6baabc3d734f 0c8d6baabc3d734f146a48c1c8566bfc f68a0b8459738887cd96c3a8bc9a5043 8b34c676e83d0aef0c8d6baabc3d734f fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 b4daf384361edcd960966ec844c65dcc 33748cb804f98d51ad92770e6b8c2d6a 131b454345e79e7e98a8b3cc19fd2f10 98a8b3cc19fd2f1060966ec844c65dcc 33748cb804f98d51ad92770e6b8c2d6a 131b454345e79e7e98a8b3cc19fd2f10 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 951b9b03782bd2c751f9b52ed37a1d4e d7679e5829ccc78138adcc66eddbf4ea da3cc0fe83f6f8a2da3cc0fe83f6f8a2 da3cc0fe83f6f8a251f9b52ed37a1d4e d7679e5829ccc78138adcc66eddbf4ea da3cc0fe83f6f8a2da3cc0fe83f6f8a2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 b9b475c74a9ac7e4f0024fea1ce9d44a 43599078aa14a9e2bc2aa0ee8306fb8a 2f691e58a67fb94603f4c5b10d41c54a 03f4c5b10d41c54af0024fea1ce9d44a 43599078aa14a9e2bc2aa0ee8306fb8a 2f691e58a67fb94603f4c5b10d41c54a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 c12915c64a63fe5ac12915c64a63fe5a e7fbe6108175a0a2d27c2885fdb529ff 2502b2739e67a54957fdd600e1d1592a 57fdd600e1d1592ac12915c64a63fe5a e7fbe6108175a0a2d27c2885fdb529ff 2502b2739e67a54957fdd600e1d1592a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 9ac39034ba3be9269fd30f8a03b282f7 d82f6a47ac22b0c4bfd1b2202a1a0faf 07dc3d60ae9fe86f753d505c0ab09ee1 753d505c0ab09ee19fd30f8a03b282f7 d82f6a47ac22b0c4bfd1b2202a1a0faf 07dc3d60ae9fe86f753d505c0ab09ee1 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 8e361a535a0e6be515814afcc8ac5227 c1b66eb008c0e757c1b66eb008c0e757 511826a6ea51a34e28271b5982bbadd4 28271b5982bbadd415814afcc8ac5227 c1b66eb008c0e757c1b66eb008c0e757 511826a6ea51a34e28271b5982bbadd4 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 b1504a38ccad3e07b6f04851f13bc773 75478330a1b498178e86f1ef9dc577e5 978548d16d6bf9832414c3af14ec53a3 2414c3af14ec53a3b6f04851f13bc773 75478330a1b498178e86f1ef9dc577e5 978548d16d6bf9832414c3af14ec53a3 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 d1f79073408676e6544da1105bccb169 8df370c44ca3c52de54632e74945f33b 719783eca8c17c9c179d7439f1dc0f5e 179d7439f1dc0f5e544da1105bccb169 8df370c44ca3c52de54632e74945f33b 719783eca8c17c9c179d7439f1dc0f5e fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 e49d48367703dd30953c90570c5d2a68 98b7359f05ab12e36c26fabc992a39f4 fab1f066f1c39b72fab1f066f1c39b72 fab1f066f1c39b72953c90570c5d2a68 98b7359f05ab12e36c26fabc992a39f4 fab1f066f1c39b72fab1f066f1c39b72 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 7ebd46c72a43c1ae00ad05ca0aeeb1c6 7820294273b14b6b7820294273b14b6b fa8a8f2701ab82af6115d46a8a9ea689 6115d46a8a9ea68900ad05ca0aeeb1c6 7820294273b14b6b7820294273b14b6b fa8a8f2701ab82af6115d46a8a9ea689 fpscr=00000000
+vseleq.f64 d7, d8, d10 5ff02707e2ffe81e3d616f6e5273703c e927bc1914a613af65dfc93d02731cbf 6745cdd370da388f06c97f2c531b1d67 06c97f2c531b1d673d616f6e5273703c e927bc1914a613af65dfc93d02731cbf 6745cdd370da388f06c97f2c531b1d67 fpscr=00000000
+vseleq.f64 d7, d8, d10 6f3a14e08a109ffc5653bc8638c0a49b d783625f1c9a65acf9bfde9d8ef03331 4c5bcdde2b857f35bcdaead22207c663 bcdaead22207c6635653bc8638c0a49b d783625f1c9a65acf9bfde9d8ef03331 4c5bcdde2b857f35bcdaead22207c663 fpscr=00000000
+vseleq.f64 d7, d8, d10 7f3e2cfaabc8640652ae595ea822c0ef 67352a0efd872b24e2bb9047ad98a58e e637d7a002b3a67396639a49b7b93025 96639a49b7b9302552ae595ea822c0ef 67352a0efd872b24e2bb9047ad98a58e e637d7a002b3a67396639a49b7b93025 fpscr=00000000
+vseleq.f64 d7, d8, d10 c762f25c38b87c653cb33a082cc900a5 9586f1c2542df0398ae50eaa17ce92ad 3ea7a83efbd0ea437cc59350230a289a 7cc59350230a289a3cb33a082cc900a5 9586f1c2542df0398ae50eaa17ce92ad 3ea7a83efbd0ea437cc59350230a289a fpscr=00000000
+vseleq.f64 d7, d8, d10 6d5471551e91c3d406769835f7a68289 9dc79a349e40d527781e1631a8850d52 f17ce243e19344a0160660602c934a5f 160660602c934a5f06769835f7a68289 9dc79a349e40d527781e1631a8850d52 f17ce243e19344a0160660602c934a5f fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 5c2200532db7a21160731b00026318af cd6a13aef9b38be308a1abc507c0e8be d07d9db9f252e24845a8060da389b305 45a8060da389b30560731b00026318af cd6a13aef9b38be308a1abc507c0e8be d07d9db9f252e24845a8060da389b305 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 5cee19087455e09f1596c60a31728d51 d741906c4a29d78ad741906c4a29d78a 5914e7e42a7a71ba50823ba4cc670369 50823ba4cc6703691596c60a31728d51 d741906c4a29d78ad741906c4a29d78a 5914e7e42a7a71ba50823ba4cc670369 fpscr=00000000
+vseleq.f64 d7, d8, d10 86fa5b0decf3c4036f990f4eb131f511 b169e9ce39f9a86d69613a927548f5f7 d0f436d919b5e68b1cfefea5afe9cdab 1cfefea5afe9cdab6f990f4eb131f511 b169e9ce39f9a86d69613a927548f5f7 d0f436d919b5e68b1cfefea5afe9cdab fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 c148387a3e593261c148387a3e593261 c9dff1ee88dc4f64754589366d561fb3 bf61ae782ec58267befd9728bbf004eb befd9728bbf004ebc148387a3e593261 c9dff1ee88dc4f64754589366d561fb3 bf61ae782ec58267befd9728bbf004eb fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 f846be4fd0ff83ec73d785a097a85aa0 9769aa9589a2e3129769aa9589a2e312 856ce7a918818bc86f50750417a5246f 6f50750417a5246f73d785a097a85aa0 9769aa9589a2e3129769aa9589a2e312 856ce7a918818bc86f50750417a5246f fpscr=00000000
+vseleq.f64 d7, d8, d10 2fc9948aee3b876871c92bffd4630379 0f99f383f262aea5b7065cf0c4d8ee9a 27614e3cf98d83090455c14f5674321d 0455c14f5674321d71c92bffd4630379 0f99f383f262aea5b7065cf0c4d8ee9a 27614e3cf98d83090455c14f5674321d fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 3ad150fc5b6908ce67c9ea6076576649 3656908bdc978df88444a5cc0db4fa55 41d638e93e7dd97cbc65c8ba53e043a3 bc65c8ba53e043a367c9ea6076576649 3656908bdc978df88444a5cc0db4fa55 41d638e93e7dd97cbc65c8ba53e043a3 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 33a228f9830807118bae4dffa1bb7379 389c1a4d568d8d3620104d79833ef33c 5c8eed6608a6b8d1064a9e3ad001994e 064a9e3ad001994e8bae4dffa1bb7379 389c1a4d568d8d3620104d79833ef33c 5c8eed6608a6b8d1064a9e3ad001994e fpscr=00000000
+vseleq.f64 d7, d8, d10 5aa4fd3d875a96a2792c8b7887b6f63e 10089529bb688260dce41f2ca1e10920 b9a0e3baf114e44ce600c387e6361aaa e600c387e6361aaa792c8b7887b6f63e 10089529bb688260dce41f2ca1e10920 b9a0e3baf114e44ce600c387e6361aaa fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 926059f806150662aaf06cf17ca10c09 88a94f4d9eb476a39d49c4c2cdb29686 e87e9c1ccb21f126194c298c8f7cf9fc 194c298c8f7cf9fcaaf06cf17ca10c09 88a94f4d9eb476a39d49c4c2cdb29686 e87e9c1ccb21f126194c298c8f7cf9fc fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 649fb91444a85759339688bf5cb26baa 7579ad460d8ac8fd0c07f6e50f3640c3 20f1e0b3c777e933db0c79edca0d1445 db0c79edca0d1445339688bf5cb26baa 7579ad460d8ac8fd0c07f6e50f3640c3 20f1e0b3c777e933db0c79edca0d1445 fpscr=00000000
+vseleq.f64 d7, d8, d10 b12f76631b32bd41aed1633909582ad6 4683e5ef0298c3535817fa1ee38ba609 9a3854c43cfe7135756cb774e96fbc0a 756cb774e96fbc0aaed1633909582ad6 4683e5ef0298c3535817fa1ee38ba609 9a3854c43cfe7135756cb774e96fbc0a fpscr=00000000
+vseleq.f64 d7, d8, d10 29e1f2dc792e5efd93fcd510e4255ade 3c2d75b22e70d36c09cf62f062ff1935 09f35fa9ca8f3ffb7e371c361bff130b 7e371c361bff130b93fcd510e4255ade 3c2d75b22e70d36c09cf62f062ff1935 09f35fa9ca8f3ffb7e371c361bff130b fpscr=00000000
+vseleq.f64 d7, d8, d10 90e87bdd082b7dedb2ad2214c064d23f e48c664ff3f48fa86ec0e2ba54e85cfe f07391b940ecebff5d41fa31b8b99aef 5d41fa31b8b99aefb2ad2214c064d23f e48c664ff3f48fa86ec0e2ba54e85cfe f07391b940ecebff5d41fa31b8b99aef fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 1f6fade310f6ec181ac7c4162ce9bf5d 1ed9165cf1666d362c7c47c2f06c3ed9 197064f462da0b21ed360fd1dfa911f6 ed360fd1dfa911f61ac7c4162ce9bf5d 1ed9165cf1666d362c7c47c2f06c3ed9 197064f462da0b21ed360fd1dfa911f6 fpscr=00000000
+vseleq.f64 d7, d8, d10 d1191ea440d149950b2a9a77b77841f8 adec3a4fe88117d57f6eeda0a2a392a6 8b0100f58a3193ea534c3f4d54fb0298 534c3f4d54fb02980b2a9a77b77841f8 adec3a4fe88117d57f6eeda0a2a392a6 8b0100f58a3193ea534c3f4d54fb0298 fpscr=00000000
+randV128: 1792 calls, 1855 iters
+vseleq.f64 d7, d8, d10 07b6daba274efad39c88103d8ff70513 eddcc28943c51e6768628f085cafcca9 3f3939b0613776619e0d5aca932d5ae1 9e0d5aca932d5ae19c88103d8ff70513 eddcc28943c51e6768628f085cafcca9 3f3939b0613776619e0d5aca932d5ae1 fpscr=00000000
+vseleq.f64 d7, d8, d10 748050fab4847bfc238293494f21fca6 ba3e6dfec5d1afe74928eca0b8b4a90c 83ea5fdcf80d6c15a4c5b707f9173435 a4c5b707f9173435238293494f21fca6 ba3e6dfec5d1afe74928eca0b8b4a90c 83ea5fdcf80d6c15a4c5b707f9173435 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vselvs.f32 s15,s16,s20 810f3770134ee8b63b1f72984149219d 6617b826e12955b7ddc20e4d86b96483 98c3cc7c9f6f4580deec6f1698c3cc7c 98c3cc7c134ee8b63b1f72984149219d 6617b826e12955b7ddc20e4d86b96483 98c3cc7c9f6f4580deec6f1698c3cc7c fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vselvs.f32 s15,s16,s20 22b22bcec66697e83d076bb653313a0e e395fee086a639f6e395fee0d8d885af 297b6ee70b1f49a19d3374c4a97c5d61 a97c5d61c66697e83d076bb653313a0e e395fee086a639f6e395fee0d8d885af 297b6ee70b1f49a19d3374c4a97c5d61 fpscr=00000000
+vselvs.f32 s15,s16,s20 6421d3a4370cad9550dea420bd1b2043 9de3b8cec11ccb19d2b368a946d06f7c 3dd1d155c1f48af22d1951e72f690496 2f690496370cad9550dea420bd1b2043 9de3b8cec11ccb19d2b368a946d06f7c 3dd1d155c1f48af22d1951e72f690496 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vselvs.f32 s15,s16,s20 3dfac3e6fc4a5cb707ea41e60b86ce74 725cbb44f589641ca1722a9e37e8d7e6 c23c0389e954d394e954d3943dec40a7 3dec40a7fc4a5cb707ea41e60b86ce74 725cbb44f589641ca1722a9e37e8d7e6 c23c0389e954d394e954d3943dec40a7 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[2]
+vselvs.f32 s15,s16,s20 970aee52e18b4aae3cff0bce3cff0bce 3545f68ff4093549fd0b0600f4093549 eea5a8b334dd79461453861ef4365dab f4365dabe18b4aae3cff0bce3cff0bce 3545f68ff4093549fd0b0600f4093549 eea5a8b334dd79461453861ef4365dab fpscr=00000000
+vselvs.f32 s15,s16,s20 f1a8f12219c85df7728a9ac8e5ebeb5d 017b120053c576502975eb08ee5e72b0 9f273c8da890a0c6e3e5659ff188e73a f188e73a19c85df7728a9ac8e5ebeb5d 017b120053c576502975eb08ee5e72b0 9f273c8da890a0c6e3e5659ff188e73a fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vselvs.f32 s15,s16,s20 421e57b476b35703f8f0f1eb3fc28fd0 26a08e658377d12725708809765a4348 883ac891f0494293aa7d9ea5883ac891 883ac89176b35703f8f0f1eb3fc28fd0 26a08e658377d12725708809765a4348 883ac891f0494293aa7d9ea5883ac891 fpscr=00000000
+vselvs.f32 s15,s16,s20 b5705464e08e18c566ca2d32e224225d bfe71c46956bf33b64ddb3f7729d601a d08752515fa192d8b248ad4c876c1ef5 876c1ef5e08e18c566ca2d32e224225d bfe71c46956bf33b64ddb3f7729d601a d08752515fa192d8b248ad4c876c1ef5 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[2]
+vselvs.f32 s15,s16,s20 f21753b9b18a8066d462a96eb18a8066 4f89b7e24b491dd6061815404b491dd6 391d0e3a673b3de33d9c62d11814680f 1814680fb18a8066d462a96eb18a8066 4f89b7e24b491dd6061815404b491dd6 391d0e3a673b3de33d9c62d11814680f fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vselvs.f32 s15,s16,s20 37ae26b044b2de6fb568e08d6d2a278b 6c5d2f39036958cea0229efd40fea670 058e83ee9da4beb1403017f803ae36d7 03ae36d744b2de6fb568e08d6d2a278b 6c5d2f39036958cea0229efd40fea670 058e83ee9da4beb1403017f803ae36d7 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vselvs.f32 s15,s16,s20 3216c9f795f7e5504112e6a2fc92f0f4 7031a787e098bc6058a089ac3738e6b7 698e5e5ad5fd87ba1f1d003a1f1d003a 1f1d003a95f7e5504112e6a2fc92f0f4 7031a787e098bc6058a089ac3738e6b7 698e5e5ad5fd87ba1f1d003a1f1d003a fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vselvs.f32 s15,s16,s20 c85515a2ead61e19a1d1d58123a97b9e 93dd1f32479c31822c6aaac4ded2c45b f7e0cbf647faaee22eadf7ba7b32a72d 7b32a72dead61e19a1d1d58123a97b9e 93dd1f32479c31822c6aaac4ded2c45b f7e0cbf647faaee22eadf7ba7b32a72d fpscr=00000000
+vselvs.f32 s15,s16,s20 a81e08ddd658afaea746f211f5a901ee 74553975c77e5cd1fb79c0c865410bfd 12331df72e6e1d71c3eab80ee22731fc e22731fcd658afaea746f211f5a901ee 74553975c77e5cd1fb79c0c865410bfd 12331df72e6e1d71c3eab80ee22731fc fpscr=00000000
+vselvs.f32 s15,s16,s20 c24ee87b05bcbd7e79f33cc7c8a8ad19 74f0a5944207a687dbec3ad63c068b79 2f00b64006ecdbbd2143173fcc9bb102 cc9bb10205bcbd7e79f33cc7c8a8ad19 74f0a5944207a687dbec3ad63c068b79 2f00b64006ecdbbd2143173fcc9bb102 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vselvs.f32 s15,s16,s20 e3518329d34af5a644852d511c8e6c46 59ce50d50df06b44198bb8a0a8016332 e4a5841b7103f964b9701c46a1bdeb2b a1bdeb2bd34af5a644852d511c8e6c46 59ce50d50df06b44198bb8a0a8016332 e4a5841b7103f964b9701c46a1bdeb2b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vselvs.f32 s15,s16,s20 c9611cde37959b4cd91e5db77abc3411 40d8eaf997f07414df561343ef2337b3 2f36f140109e6891175645ee51690d13 51690d1337959b4cd91e5db77abc3411 40d8eaf997f07414df561343ef2337b3 2f36f140109e6891175645ee51690d13 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vselvs.f32 s15,s16,s20 9a69108c551c107004420fac9e347c33 5dde29fdf15e518c52eedb75afa3e0d1 37b1a3d08f37b0c2eef2a7fb13d1dcf3 13d1dcf3551c107004420fac9e347c33 5dde29fdf15e518c52eedb75afa3e0d1 37b1a3d08f37b0c2eef2a7fb13d1dcf3 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vselvs.f32 s15,s16,s20 044c111eab69783527c0ccd64ec77b5e 6b0c1b499efdcc70738adf8451897de0 99eb8fbdb138d3fcf484296aa20c8585 a20c8585ab69783527c0ccd64ec77b5e 6b0c1b499efdcc70738adf8451897de0 99eb8fbdb138d3fcf484296aa20c8585 fpscr=00000000
+vselvs.f32 s15,s16,s20 98d573ff6be909f2878aa1d2f6b72d29 9b8fb02408800f5ea17a225c568a2d61 fd1e492774a4ac989061f4b8a0ce54b5 a0ce54b56be909f2878aa1d2f6b72d29 9b8fb02408800f5ea17a225c568a2d61 fd1e492774a4ac989061f4b8a0ce54b5 fpscr=00000000
+vselvs.f32 s15,s16,s20 b34620abd5a9c9ddebe1c6769134480e 4d459aa838986faf397cae705c2d71a9 31cb9419678908e2d05ad9cf563e036f 563e036fd5a9c9ddebe1c6769134480e 4d459aa838986faf397cae705c2d71a9 31cb9419678908e2d05ad9cf563e036f fpscr=00000000
+vselvs.f32 s15,s16,s20 a77805d7a2c5e48fbd1ceb54765047a9 ed6589ed7adfec53c663c42adecbe286 c9f3b0d9cbbec136cb89846993654ee2 93654ee2a2c5e48fbd1ceb54765047a9 ed6589ed7adfec53c663c42adecbe286 c9f3b0d9cbbec136cb89846993654ee2 fpscr=00000000
+vselvs.f32 s15,s16,s20 a14a546f95a359e7fcb85a3bc4d61585 ed300d3884f7200dfd646657db9df537 144c77bbe4b39739b22b5fa50ce74d81 0ce74d8195a359e7fcb85a3bc4d61585 ed300d3884f7200dfd646657db9df537 144c77bbe4b39739b22b5fa50ce74d81 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vselvs.f32 s15,s16,s20 bf5cf8ccbfa4fe3bbfa4fe3bba2c25f9 8080370720eda75818743c0305578e82 a05c76e7f08b4e067870ccdd4368dbff 4368dbffbfa4fe3bbfa4fe3bba2c25f9 8080370720eda75818743c0305578e82 a05c76e7f08b4e067870ccdd4368dbff fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselvs.f32 s15,s16,s20 2227b25bf76e44710db537edfcca8dad 59a42780692c5b4359a427809e79eff3 e2429bf8c354fb8fafbae8da0f0132c9 0f0132c9f76e44710db537edfcca8dad 59a42780692c5b4359a427809e79eff3 e2429bf8c354fb8fafbae8da0f0132c9 fpscr=00000000
+vselvs.f32 s15,s16,s20 bcedd93fd90bac7641c309b05daaa174 39ccf4498e895c2d01c639eb9e139c0b 4e48a5da3966e6885381e90d77828792 77828792d90bac7641c309b05daaa174 39ccf4498e895c2d01c639eb9e139c0b 4e48a5da3966e6885381e90d77828792 fpscr=00000000
+vselvs.f32 s15,s16,s20 45ac8b1e1c7efdc1a32a1df9e4e67692 72d8bd4d4ec708b369bfcfe220740e6a a13133149277221a62b7395deb0774bd eb0774bd1c7efdc1a32a1df9e4e67692 72d8bd4d4ec708b369bfcfe220740e6a a13133149277221a62b7395deb0774bd fpscr=00000000
+vselvs.f32 s15,s16,s20 6364a981b685610d6ec97c34a902f4c8 37d830b415b4ad60d4cfaf59b95e672b f4beabb126f02ced78d65b3b276b244e 276b244eb685610d6ec97c34a902f4c8 37d830b415b4ad60d4cfaf59b95e672b f4beabb126f02ced78d65b3b276b244e fpscr=00000000
+vselvs.f32 s15,s16,s20 2b95cbb202622d87cb606a24c50eefdb 8232057ea27bbe83c5e63781fdd60aa4 8c2a31b24491216180864a1acaebd2b5 caebd2b502622d87cb606a24c50eefdb 8232057ea27bbe83c5e63781fdd60aa4 8c2a31b24491216180864a1acaebd2b5 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vselvs.f32 s15,s16,s20 cff69ed2926562d07f602846855c7f5f a180c0a3244fa1681cf5c6b9e7319bb1 c6d6f7eb407ec935e689d848e9634eaa e9634eaa926562d07f602846855c7f5f a180c0a3244fa1681cf5c6b9e7319bb1 c6d6f7eb407ec935e689d848e9634eaa fpscr=00000000
+vselvs.f32 s15,s16,s20 0ccd90a52685b6a9a32c1c9f5c63219d b061d02fb95af08f3752014f9702ecec 134f450c2b4ff97ee836bf722d4ccf39 2d4ccf392685b6a9a32c1c9f5c63219d b061d02fb95af08f3752014f9702ecec 134f450c2b4ff97ee836bf722d4ccf39 fpscr=00000000
+vselvs.f32 s15,s16,s20 3c828bb6e28f48cde4eca7589b610033 a7000f618b3259663ed955e62cf79143 a8973c52e84ae21aab46db179ab174b7 9ab174b7e28f48cde4eca7589b610033 a7000f618b3259663ed955e62cf79143 a8973c52e84ae21aab46db179ab174b7 fpscr=00000000
+vselvs.f32 s15,s16,s20 383368625812cd5aaf536f542dd899b0 57773d100ef41c1d3d437f11b869a7ca 932245eccf703b2d36cb314054bae5e8 54bae5e85812cd5aaf536f542dd899b0 57773d100ef41c1d3d437f11b869a7ca 932245eccf703b2d36cb314054bae5e8 fpscr=00000000
+vselvs.f32 s15,s16,s20 f003ee1de53592d88760940b65923018 7a8b6278062605d3f45fef6967e74939 56e7cf6f45df458beb8330f9a2c60320 a2c60320e53592d88760940b65923018 7a8b6278062605d3f45fef6967e74939 56e7cf6f45df458beb8330f9a2c60320 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[2]
+vselvs.f32 s15,s16,s20 201ac4a77ab50f5f7ab50f5f3af0f73d 296e9ee0f609c5664cae47e7b48914f1 b4ade50b9522975bb44591b5f1c05114 f1c051147ab50f5f7ab50f5f3af0f73d 296e9ee0f609c5664cae47e7b48914f1 b4ade50b9522975bb44591b5f1c05114 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vselvs.f32 s15,s16,s20 de9db706de9db706a81e1ccb16cb716a bf9a5ca70a53339db0a5b22d13fa51aa de00125bbfb9ae8901dbcf3ee3eac664 e3eac664de9db706a81e1ccb16cb716a bf9a5ca70a53339db0a5b22d13fa51aa de00125bbfb9ae8901dbcf3ee3eac664 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vselvs.f32 s15,s16,s20 120bf46a4cd0e40541986c103e26886f 130ca9ed1340d9cc8136a1f04c0b5442 f67f6d2986355d0796d53a13cc0d9649 cc0d96494cd0e40541986c103e26886f 130ca9ed1340d9cc8136a1f04c0b5442 f67f6d2986355d0796d53a13cc0d9649 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[2]
+vselvs.f32 s15,s16,s20 c03cd1d780f264bac03cd1d7511e4895 3760fe183760fe18f06e0104ff0dc3f1 b1191a95eacf7c4e7dd3260a4c984bfe 4c984bfe80f264bac03cd1d7511e4895 3760fe183760fe18f06e0104ff0dc3f1 b1191a95eacf7c4e7dd3260a4c984bfe fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vselvs.f32 s15,s16,s20 b8785d05b8785d05241e65812ead38ae 511859461d757c25d15289792f07f3d1 6e464ad1e015fec92b83601163a667ed 63a667edb8785d05241e65812ead38ae 511859461d757c25d15289792f07f3d1 6e464ad1e015fec92b83601163a667ed fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vselvs.f32 s15,s16,s20 e2c82e6f24a15c422525dfaf3cae565b 0294017cf850c98b69f834aa4b45fb76 df29f4aafdbbf039919dea22e6d79f9a e6d79f9a24a15c422525dfaf3cae565b 0294017cf850c98b69f834aa4b45fb76 df29f4aafdbbf039919dea22e6d79f9a fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[3]
+vselvs.f32 s15,s16,s20 f2b39b0e8e489d94d3b85825a6728fab d825397a581b21ad280e3f64c5d5316f c13ecf3e9c1de9e4097df99b7b3d684c 7b3d684c8e489d94d3b85825a6728fab d825397a581b21ad280e3f64c5d5316f c13ecf3e9c1de9e4097df99b7b3d684c fpscr=00000000
+vselvs.f32 s15,s16,s20 4f85935a48c3ee9937e0630fefd90988 c818d74d074cde5c1f27c25e0c050ff0 ed5b398f1d7abd2c2cea7212710dd87e 710dd87e48c3ee9937e0630fefd90988 c818d74d074cde5c1f27c25e0c050ff0 ed5b398f1d7abd2c2cea7212710dd87e fpscr=00000000
+randV128: 2048 calls, 2118 iters
+randV128: doing v->u32[2] = v->u32[0]
+vselvs.f32 s15,s16,s20 f7b9a82658c78dcf891722f3b0aea5fc 65a3c7477082ee00bcb93d29bf6d6fed fb7a7b1946c3e1522f6ad441c6bd9af3 c6bd9af358c78dcf891722f3b0aea5fc 65a3c7477082ee00bcb93d29bf6d6fed fb7a7b1946c3e1522f6ad441c6bd9af3 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vselvs.f32 s15,s16,s20 dfbcd8f2615bd4d0c04dc6893eada9f3 f92cdd8cfa0726faad40b1e1696cdbf9 709ec90187543a71614a0a57614a0a57 614a0a57615bd4d0c04dc6893eada9f3 f92cdd8cfa0726faad40b1e1696cdbf9 709ec90187543a71614a0a57614a0a57 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vselvs.f32 s15,s16,s20 a30f8f112418ba6b1dd395061dd39506 f68901ca54ee98af528ba4a14225422a a1bf07455e33b3d399a8c6936b8bfa95 6b8bfa952418ba6b1dd395061dd39506 f68901ca54ee98af528ba4a14225422a a1bf07455e33b3d399a8c6936b8bfa95 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vselvs.f32 s15,s16,s20 8793c51817c923b6a187046d3f09b720 9dcdc6913b40380353c44ea1af66a717 d5ab9305e9de68b2b802a210e9de68b2 e9de68b217c923b6a187046d3f09b720 9dcdc6913b40380353c44ea1af66a717 d5ab9305e9de68b2b802a210e9de68b2 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vselvs.f32 s15,s16,s20 3bb4bb0bd15f33f4d15f33f49f01e200 99b635e3c6f037d64c09a1108241d982 763a059e8865b3b5c9c5b9e346af3ec9 46af3ec9d15f33f4d15f33f49f01e200 99b635e3c6f037d64c09a1108241d982 763a059e8865b3b5c9c5b9e346af3ec9 fpscr=00000000
+vselvs.f32 s15,s16,s20 5ae533f3abd6061fcd1b68ac1d7ed21d ca716738a729301ab3274a7683b9aad2 3c0d069049bf701dc3713976571942db 571942dbabd6061fcd1b68ac1d7ed21d ca716738a729301ab3274a7683b9aad2 3c0d069049bf701dc3713976571942db fpscr=00000000
+vselvs.f32 s15,s16,s20 cfd0896c4232967f24d6c5f776893610 084d791cf74bf8a46710e7cc79be9c0f 4f62003f9a70f695d27c81182dc283c6 2dc283c64232967f24d6c5f776893610 084d791cf74bf8a46710e7cc79be9c0f 4f62003f9a70f695d27c81182dc283c6 fpscr=00000000
+vselvs.f32 s15,s16,s20 4bc673b0459cc802f3c4faa60d4b99f6 896ce90b159ce838ac75679848997803 4ccff40eebf552c6f74f134d62cd65d5 62cd65d5459cc802f3c4faa60d4b99f6 896ce90b159ce838ac75679848997803 4ccff40eebf552c6f74f134d62cd65d5 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[1]
+vselvs.f32 s15,s16,s20 678ef34b163a0a8bfe44ed82fe44ed82 c6d3cb3fb356aec68a64518ba891071f b59cbb6fb197b60aab9f4b87ab9f4b87 ab9f4b87163a0a8bfe44ed82fe44ed82 c6d3cb3fb356aec68a64518ba891071f b59cbb6fb197b60aab9f4b87ab9f4b87 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselvs.f64 d7, d8, d10 066423e65f1b4bfc066423e65f1b4bfc 7a6f179963b6abce9e56d1cd73eedd3a c61864a30205d7ed82c673a4f8bbca13 82c673a4f8bbca13066423e65f1b4bfc 7a6f179963b6abce9e56d1cd73eedd3a c61864a30205d7ed82c673a4f8bbca13 fpscr=00000000
+vselvs.f64 d7, d8, d10 0f3713b847c6e605a7b6266f62bb7b92 ef259ad76d76b28452a768e79fdcd204 ad344d45fc98443f6008eed40d7bf867 6008eed40d7bf867a7b6266f62bb7b92 ef259ad76d76b28452a768e79fdcd204 ad344d45fc98443f6008eed40d7bf867 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vselvs.f64 d7, d8, d10 1b49cb4664f720ee1b49cb4664f720ee cbd1fbd82150ef655363d81fd6191d11 1b07784a3b5f9f7374ee2b37b8a50252 74ee2b37b8a502521b49cb4664f720ee cbd1fbd82150ef655363d81fd6191d11 1b07784a3b5f9f7374ee2b37b8a50252 fpscr=00000000
+vselvs.f64 d7, d8, d10 4d0e1cd683ae3ed371fb6e988531163d 6de483c38fffda73d1384b5b1283dcb5 4579b9b774ac6b6a4f92c07dfa124f5b 4f92c07dfa124f5b71fb6e988531163d 6de483c38fffda73d1384b5b1283dcb5 4579b9b774ac6b6a4f92c07dfa124f5b fpscr=00000000
+vselvs.f64 d7, d8, d10 cc40b1017c9f68b29120097cdb5b8e14 3f36095990f0284bf41409b6f393929e b487060e50271b50e11dce1778694f3d e11dce1778694f3d9120097cdb5b8e14 3f36095990f0284bf41409b6f393929e b487060e50271b50e11dce1778694f3d fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselvs.f64 d7, d8, d10 5c2425f2f77a00508f614e0d2688d1d9 e77017f986d44cfee77017f986d44cfe 8c47dcaeae4779bb5cb4381ce60dd9ef 5cb4381ce60dd9ef8f614e0d2688d1d9 e77017f986d44cfee77017f986d44cfe 8c47dcaeae4779bb5cb4381ce60dd9ef fpscr=00000000
+vselvs.f64 d7, d8, d10 49f44feaf351d63e25ef3dd438e2cae5 3a1ce012ba06078c80edb10386d68173 ce99a35e15e8da786ab0000da6fce7ee 6ab0000da6fce7ee25ef3dd438e2cae5 3a1ce012ba06078c80edb10386d68173 ce99a35e15e8da786ab0000da6fce7ee fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vselvs.f64 d7, d8, d10 deecca881ce9982adeecca881ce9982a ba651ec8ef4979070ea5a25915eb1398 6281c9b66c34a4f38749ec252a61af04 8749ec252a61af04deecca881ce9982a ba651ec8ef4979070ea5a25915eb1398 6281c9b66c34a4f38749ec252a61af04 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselvs.f64 d7, d8, d10 4c3c365744634c8988f334ccd603cc2f 17a9599af590737eb1f5f010fef57a77 52378f82f910870160c85b034cc6ab63 60c85b034cc6ab6388f334ccd603cc2f 17a9599af590737eb1f5f010fef57a77 52378f82f910870160c85b034cc6ab63 fpscr=00000000
+vselvs.f64 d7, d8, d10 bc42987735313f7f6393406783056509 4cfe6ea89a67fd7573fd89076c62d3db 4d81883376d90b61be77d16b255e01d8 be77d16b255e01d86393406783056509 4cfe6ea89a67fd7573fd89076c62d3db 4d81883376d90b61be77d16b255e01d8 fpscr=00000000
+vselvs.f64 d7, d8, d10 7626f8c29ff6db7b95720a3abce303aa 29d968b64711207df29c6c50e2df479a 86ea28ac939577469bec4e03ec7a332e 9bec4e03ec7a332e95720a3abce303aa 29d968b64711207df29c6c50e2df479a 86ea28ac939577469bec4e03ec7a332e fpscr=00000000
+vselvs.f64 d7, d8, d10 39f6fec51c6cc92c10c8702e51203f06 d16c194b73d1b48043ca6264df50198b 64c8a64ee462fdab2f7ea9bf899e80fd 2f7ea9bf899e80fd10c8702e51203f06 d16c194b73d1b48043ca6264df50198b 64c8a64ee462fdab2f7ea9bf899e80fd fpscr=00000000
+vselvs.f64 d7, d8, d10 86eeeba6ca4f57c0e4cf7764d4215de6 ae19ebab2aae68bfc3182b3950ed94f1 94a5c9c49523d0045371f57848f48bcb 5371f57848f48bcbe4cf7764d4215de6 ae19ebab2aae68bfc3182b3950ed94f1 94a5c9c49523d0045371f57848f48bcb fpscr=00000000
+vselvs.f64 d7, d8, d10 2d40f5fde1ab0bb1c25daca8dec2a64b 4c5c080f37dd67b9929137dfea19fbaf 342e20a3a42d43d102a07e30fbf124f9 02a07e30fbf124f9c25daca8dec2a64b 4c5c080f37dd67b9929137dfea19fbaf 342e20a3a42d43d102a07e30fbf124f9 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselvs.f64 d7, d8, d10 d47ead462484a0ca6b254ce0878c4a01 173ab64f69d3c02e2b906764eefef7a5 380e4eb9d25486be66a8fc46ab610d60 66a8fc46ab610d606b254ce0878c4a01 173ab64f69d3c02e2b906764eefef7a5 380e4eb9d25486be66a8fc46ab610d60 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselvs.f64 d7, d8, d10 e0740646c8b9b1a1e1fe78467d7e5b02 e878ef228526b91af6334c7d59806848 2b07639c0feee4772b07639c0feee477 2b07639c0feee477e1fe78467d7e5b02 e878ef228526b91af6334c7d59806848 2b07639c0feee4772b07639c0feee477 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselvs.f64 d7, d8, d10 118342517d13311b118342517d13311b 1f8d764eac16369a295bda72d449fba7 a18cc59986bdd8da06422bcf0cc7c63d 06422bcf0cc7c63d118342517d13311b 1f8d764eac16369a295bda72d449fba7 a18cc59986bdd8da06422bcf0cc7c63d fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vselvs.f64 d7, d8, d10 c77564f51ed504b7c77564f51ed504b7 be29117bca4b9c62be29117bca4b9c62 970f5f16c5d267f2970f5f16c5d267f2 970f5f16c5d267f2c77564f51ed504b7 be29117bca4b9c62be29117bca4b9c62 970f5f16c5d267f2970f5f16c5d267f2 fpscr=00000000
+vselvs.f64 d7, d8, d10 44fc53a050c571e3d36ada29a17f5c56 b03f1fe02b93b0c12f6d403ba8e31ff9 2d15067147eb9fba09db33632640bb99 09db33632640bb99d36ada29a17f5c56 b03f1fe02b93b0c12f6d403ba8e31ff9 2d15067147eb9fba09db33632640bb99 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselvs.f64 d7, d8, d10 1212814c474d1a105196d13ad18353b5 c8d287c746672a29586e78f22276a078 c087ce02711245acc4f3ffec8cff1aaa c4f3ffec8cff1aaa5196d13ad18353b5 c8d287c746672a29586e78f22276a078 c087ce02711245acc4f3ffec8cff1aaa fpscr=00000000
+vselvs.f64 d7, d8, d10 05b61e37ab2fc7c09f4bbdd3bd7ff355 0c92a3543b3bc556ad1742e2f2677f4d fe75c73a5de282a93dd6aa1bcaa48703 3dd6aa1bcaa487039f4bbdd3bd7ff355 0c92a3543b3bc556ad1742e2f2677f4d fe75c73a5de282a93dd6aa1bcaa48703 fpscr=00000000
+vselvs.f64 d7, d8, d10 3c97eabcb12367a844f11b64f87d8205 973e19c4764bd3da4edb7b8089e1b943 226e5acfe73f89e25d0b460d759b1445 5d0b460d759b144544f11b64f87d8205 973e19c4764bd3da4edb7b8089e1b943 226e5acfe73f89e25d0b460d759b1445 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselvs.f64 d7, d8, d10 524e1115e21c1e695fd2563b5253bfba 034b7a76c48f92bf9a89f0a2dae0007d 1c8374db220d68b11c8374db220d68b1 1c8374db220d68b15fd2563b5253bfba 034b7a76c48f92bf9a89f0a2dae0007d 1c8374db220d68b11c8374db220d68b1 fpscr=00000000
+vselvs.f64 d7, d8, d10 63dff2dad906c495680e5cb53427cab7 63b5099455a3c02d6aaa815cf7875c46 d58241ea69c72072d90cb15bd7d8e6b6 d90cb15bd7d8e6b6680e5cb53427cab7 63b5099455a3c02d6aaa815cf7875c46 d58241ea69c72072d90cb15bd7d8e6b6 fpscr=00000000
+vselvs.f64 d7, d8, d10 d21eae5369bf2852798eb94a177836cb 6542ea56010d4ef77b69f877810d6ee9 18aab3e48bd147f649286a1fa2ae18a5 49286a1fa2ae18a5798eb94a177836cb 6542ea56010d4ef77b69f877810d6ee9 18aab3e48bd147f649286a1fa2ae18a5 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselvs.f64 d7, d8, d10 f5b4288ce7ec14ac4475c42322c0fa6a db6489b856578f3f7f0be47b63e4753c 503352218b3b9fcb503352218b3b9fcb 503352218b3b9fcb4475c42322c0fa6a db6489b856578f3f7f0be47b63e4753c 503352218b3b9fcb503352218b3b9fcb fpscr=00000000
+vselvs.f64 d7, d8, d10 88746b95c1ccb38421ece0386a3047d5 4004ef9686803aa2ae6a971b94df2cf3 7af70845084c054f5a7c2b42aabe952f 5a7c2b42aabe952f21ece0386a3047d5 4004ef9686803aa2ae6a971b94df2cf3 7af70845084c054f5a7c2b42aabe952f fpscr=00000000
+vselvs.f64 d7, d8, d10 d897c0c02777a4f2f93d8b38b71f4db7 b5b02bf6e66958a9b467b1e76e4e38ee 76cd837e98d9ec6804012d0b214440d2 04012d0b214440d2f93d8b38b71f4db7 b5b02bf6e66958a9b467b1e76e4e38ee 76cd837e98d9ec6804012d0b214440d2 fpscr=00000000
+vselvs.f64 d7, d8, d10 84b9ee8e3ef877b6b4e30911c707c511 2228803eef79843ca3228d5a41385cb9 3e3991217ce7384db8e02fecda21e496 b8e02fecda21e496b4e30911c707c511 2228803eef79843ca3228d5a41385cb9 3e3991217ce7384db8e02fecda21e496 fpscr=00000000
+vselvs.f64 d7, d8, d10 d758d8854ea5162c03fe20f5b46b0ec2 a7204e72014898e1d8beadb04f92d7b1 7aa9fe1bf784d29fc7e87514c8df66a5 c7e87514c8df66a503fe20f5b46b0ec2 a7204e72014898e1d8beadb04f92d7b1 7aa9fe1bf784d29fc7e87514c8df66a5 fpscr=00000000
+vselvs.f64 d7, d8, d10 0a19482b197433c2bcb23cb8920a602e 8cd986212f79ce1514e3c6b451429294 405532dcdc6327d2b8fe1a7a1bafe387 b8fe1a7a1bafe387bcb23cb8920a602e 8cd986212f79ce1514e3c6b451429294 405532dcdc6327d2b8fe1a7a1bafe387 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselvs.f64 d7, d8, d10 262b4bd841e7f321477de313250a966b d4c868449c61c062d4c868449c61c062 60e434b4fc2ccd4a7a8767ccc2f24502 7a8767ccc2f24502477de313250a966b d4c868449c61c062d4c868449c61c062 60e434b4fc2ccd4a7a8767ccc2f24502 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselvs.f64 d7, d8, d10 f43e6857d94d196d6d330a17599a5a0a daa199a08cfd8bbfb6c2ed5ec72bb84b 43aa9c3837bde03643aa9c3837bde036 43aa9c3837bde0366d330a17599a5a0a daa199a08cfd8bbfb6c2ed5ec72bb84b 43aa9c3837bde03643aa9c3837bde036 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: 2304 calls, 2382 iters
+vselvs.f64 d7, d8, d10 883b0be6874517490d23c03d85afc010 b2129c897ce6a222e54219c8bcb4f8f2 eedd299e8fd6c7680a88d4fff792a096 0a88d4fff792a0960d23c03d85afc010 b2129c897ce6a222e54219c8bcb4f8f2 eedd299e8fd6c7680a88d4fff792a096 fpscr=00000000
+vselvs.f64 d7, d8, d10 379ac9cc4c116e7a25b323838d489b72 b501f16cc1c0185dd4ed4a5291a82220 a904502fd23e8093a059a674949154e6 a059a674949154e625b323838d489b72 b501f16cc1c0185dd4ed4a5291a82220 a904502fd23e8093a059a674949154e6 fpscr=00000000
+vselvs.f64 d7, d8, d10 505e10fccb2f69b8bc56b8964600c89c 1b11dd190366aaf7e5e0e14e4d1492c3 ca77691484b75d02a0c3145575afb3a0 a0c3145575afb3a0bc56b8964600c89c 1b11dd190366aaf7e5e0e14e4d1492c3 ca77691484b75d02a0c3145575afb3a0 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselvs.f64 d7, d8, d10 0e0608069f0d2bb30ca0edbef2a63615 2e79e631c3a4d4b9778ec0eb37832068 ebe095c53869a5024cf4d866e37f4495 4cf4d866e37f44950ca0edbef2a63615 2e79e631c3a4d4b9778ec0eb37832068 ebe095c53869a5024cf4d866e37f4495 fpscr=00000000
+vselvs.f64 d7, d8, d10 e8a3694198e7d977b34acd93f5fd38b4 8caf914f5f2fe7d26c413eaf251d64e1 3f35aee70cca5d9cbcc204a92a32771a bcc204a92a32771ab34acd93f5fd38b4 8caf914f5f2fe7d26c413eaf251d64e1 3f35aee70cca5d9cbcc204a92a32771a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselvs.f64 d7, d8, d10 bf2c828ddd265b2df2ac2a7c0635f31b 08be4467cd1294bc08be4467cd1294bc 6b911e0e9e3bf25978c070b67d085f42 78c070b67d085f42f2ac2a7c0635f31b 08be4467cd1294bc08be4467cd1294bc 6b911e0e9e3bf25978c070b67d085f42 fpscr=00000000
+vselvs.f64 d7, d8, d10 ab2c0a5200c881e7603b5a18216605cc 5a05b5a28f1e89947b565c5ddb7eb0a2 cabf5d35cf2bc46b9fc58fdaedf74f0b 9fc58fdaedf74f0b603b5a18216605cc 5a05b5a28f1e89947b565c5ddb7eb0a2 cabf5d35cf2bc46b9fc58fdaedf74f0b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselvs.f64 d7, d8, d10 1ca81cd5cafd47811ade4ff0758bf1de da735c3e6a4a1ba6da735c3e6a4a1ba6 50e99e1a59bf41ec52079a9c244dea46 52079a9c244dea461ade4ff0758bf1de da735c3e6a4a1ba6da735c3e6a4a1ba6 50e99e1a59bf41ec52079a9c244dea46 fpscr=00000000
+vselvs.f64 d7, d8, d10 87a9d9dac159f8c421b04378d038512f 4d7c63889d602d3e20f06839a81f0036 cc4642d893723ea7a0a2b44d6003ff3c a0a2b44d6003ff3c21b04378d038512f 4d7c63889d602d3e20f06839a81f0036 cc4642d893723ea7a0a2b44d6003ff3c fpscr=00000000
+vselvs.f64 d7, d8, d10 d6f00acc07efe3609ef4c0079650034c e74d88115ec0e8923130a60e28d0119b 892b2ee0c0c4456aa2f207571dd27e17 a2f207571dd27e179ef4c0079650034c e74d88115ec0e8923130a60e28d0119b 892b2ee0c0c4456aa2f207571dd27e17 fpscr=00000000
+vselvs.f64 d7, d8, d10 2b732286ff3edaec506a7e9b16be5e8b d5afec72fd1c7497d00530648ea4a40a ce941aa059d45e15478082cf1048a42f 478082cf1048a42f506a7e9b16be5e8b d5afec72fd1c7497d00530648ea4a40a ce941aa059d45e15478082cf1048a42f fpscr=00000000
+vselvs.f64 d7, d8, d10 48d3152fda6eda42b99300ed8a70968d 9c3172ab036c411a29016922e982ae7e 1fad93c2817438a5026f7afc1b257744 026f7afc1b257744b99300ed8a70968d 9c3172ab036c411a29016922e982ae7e 1fad93c2817438a5026f7afc1b257744 fpscr=00000000
+vselvs.f64 d7, d8, d10 903853f620b36f4b4b4664d540cb184c 2ca54d03024cdfab7d1de0e5ee82bcaf e1646eeaca5bd72a99de800c4945adb2 99de800c4945adb24b4664d540cb184c 2ca54d03024cdfab7d1de0e5ee82bcaf e1646eeaca5bd72a99de800c4945adb2 fpscr=00000000
+vselvs.f64 d7, d8, d10 923109daff2348574c7d90ccde8aa85e 21c3c93d9f1c78df832d8b9c4c83fd5c 09328164607884e41c4b6eb4e9af929c 1c4b6eb4e9af929c4c7d90ccde8aa85e 21c3c93d9f1c78df832d8b9c4c83fd5c 09328164607884e41c4b6eb4e9af929c fpscr=00000000
+vselvs.f64 d7, d8, d10 bcf7f08492bd266b84d867a6f3afba3b 3871e38d4815bd23169b4b127b83456c 96f0fd3b6bc3c18cc4585914c2fd867f c4585914c2fd867f84d867a6f3afba3b 3871e38d4815bd23169b4b127b83456c 96f0fd3b6bc3c18cc4585914c2fd867f fpscr=00000000
+vselvs.f64 d7, d8, d10 5a4854cd408746a7a07052c39006cba1 4a1ea6457875c2f481177cadd3f7532c c107b874e724f832c5291376ad03f7e0 c5291376ad03f7e0a07052c39006cba1 4a1ea6457875c2f481177cadd3f7532c c107b874e724f832c5291376ad03f7e0 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselvs.f64 d7, d8, d10 52af21fc6aa2856f6a98bb82269d745d d5d4667d0b64df7bd5d4667d0b64df7b c78e1d09b82808ab8b84f639acd7528d 8b84f639acd7528d6a98bb82269d745d d5d4667d0b64df7bd5d4667d0b64df7b c78e1d09b82808ab8b84f639acd7528d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vmaxnm.f32 s15,s16,s20 0d0cf248b99e7a44642798b515d5aa56 33734573699a60011c37e4ca19cd9b37 197585aa1ffd475b8d3a335b6b9c6bb6 6b9c6bb6b99e7a44642798b515d5aa56 33734573699a60011c37e4ca19cd9b37 197585aa1ffd475b8d3a335b6b9c6bb6 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vmaxnm.f32 s15,s16,s20 1aa623805856adb208d208e7167927b1 8ad458dfe704c70e1a41415e9cc2d51d 28e57938b6fb4fd6d8c7cbf5bcf48ff3 9cc2d51d5856adb208d208e7167927b1 8ad458dfe704c70e1a41415e9cc2d51d 28e57938b6fb4fd6d8c7cbf5bcf48ff3 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[2]
+vmaxnm.f32 s15,s16,s20 94ff1b3a69e3a776792073ff94ff1b3a c1abef6929a58c959aba9e4f29a58c95 da6b9c4eed19ea4aa650eaec94e2d40c 29a58c9569e3a776792073ff94ff1b3a c1abef6929a58c959aba9e4f29a58c95 da6b9c4eed19ea4aa650eaec94e2d40c fpscr=00000000
+vmaxnm.f32 s15,s16,s20 1f1957bf4b1b369a3b3dc0f6e29783ce bfdfcd9b48dd0b824ae51294caeeaa4c 6cc0f9b4ee4bd229392cabb3ae3f996f ae3f996f4b1b369a3b3dc0f6e29783ce bfdfcd9b48dd0b824ae51294caeeaa4c 6cc0f9b4ee4bd229392cabb3ae3f996f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[3]
+vmaxnm.f32 s15,s16,s20 b2d07befdd1f1edc4881f01e63ff35db f7467621f0fafd76f746762173396921 f38eb07bce82ac0fb5b540e2eebbbe59 73396921dd1f1edc4881f01e63ff35db f7467621f0fafd76f746762173396921 f38eb07bce82ac0fb5b540e2eebbbe59 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vmaxnm.f32 s15,s16,s20 740914307d51fe9ff319398681bb7dc2 725350b83918423e52c5fe50c7fda019 cc459ebaddb471cfe090bd3fe090bd3f c7fda0197d51fe9ff319398681bb7dc2 725350b83918423e52c5fe50c7fda019 cc459ebaddb471cfe090bd3fe090bd3f fpscr=00000000
+vmaxnm.f32 s15,s16,s20 56f00e5bc147b5d2fc04c0cf6200de4f ef5821aa214a553677e7b4e97b912973 8bed0b3ca6dffbf9c4744815321df7ac 7b912973c147b5d2fc04c0cf6200de4f ef5821aa214a553677e7b4e97b912973 8bed0b3ca6dffbf9c4744815321df7ac fpscr=00000000
+vmaxnm.f32 s15,s16,s20 22352ea34be582b563082dfbb2fe54bb c9965db7c9a784423d5169d5656eb741 a654213be9f6ccce5c5adf66bd43691d 656eb7414be582b563082dfbb2fe54bb c9965db7c9a784423d5169d5656eb741 a654213be9f6ccce5c5adf66bd43691d fpscr=00000000
+vmaxnm.f32 s15,s16,s20 e284d226a4b0091af2442c850ba27202 f7d8099f3390a8ad25b4bcbaf8404ef7 6eff117e4af554134aacd837e28bf8bc e28bf8bca4b0091af2442c850ba27202 f7d8099f3390a8ad25b4bcbaf8404ef7 6eff117e4af554134aacd837e28bf8bc fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vmaxnm.f32 s15,s16,s20 debe16a841dfe2a044b953f041dfe2a0 399e0f3099a2b6c9c4d05f4aaab7891c 93224057caeb1b0bf82d45079ee6bbe1 9ee6bbe141dfe2a044b953f041dfe2a0 399e0f3099a2b6c9c4d05f4aaab7891c 93224057caeb1b0bf82d45079ee6bbe1 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vmaxnm.f32 s15,s16,s20 4e76e43e85247770794b88a0d690953a 2231ea1f92d7964012196a1d9bc20228 f84113b7f4fa59e8f84113b7094ad76a 094ad76a85247770794b88a0d690953a 2231ea1f92d7964012196a1d9bc20228 f84113b7f4fa59e8f84113b7094ad76a fpscr=00000000
+vmaxnm.f32 s15,s16,s20 02742fbfede4640b8e8c5d9b8fc24459 98033944972dea54e3e8f5c4f98476c2 2cd62c2339477e579c40ff26cef74a90 cef74a90ede4640b8e8c5d9b8fc24459 98033944972dea54e3e8f5c4f98476c2 2cd62c2339477e579c40ff26cef74a90 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vmaxnm.f32 s15,s16,s20 eeeafa8e27e84f2a9b776e9f0989f0df 35a30d0acd4ff0fce58e4521e0385da5 887f18c6e23350ef22ba0b98887f18c6 887f18c627e84f2a9b776e9f0989f0df 35a30d0acd4ff0fce58e4521e0385da5 887f18c6e23350ef22ba0b98887f18c6 fpscr=00000000
+vmaxnm.f32 s15,s16,s20 aca8d4815ea64cf1e13add9274e46400 eee7ec50cc2a25e372b8103e55f4dd63 5d60577b24346a8406179648470307ca 55f4dd635ea64cf1e13add9274e46400 eee7ec50cc2a25e372b8103e55f4dd63 5d60577b24346a8406179648470307ca fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vmaxnm.f32 s15,s16,s20 89da9bf39c8c63156c004ad1c3cae1bc 994aaf56fc2e32919827681a06b2cf4f 0f56cacf3646b9c0dd53bbd1b6379f8f 06b2cf4f9c8c63156c004ad1c3cae1bc 994aaf56fc2e32919827681a06b2cf4f 0f56cacf3646b9c0dd53bbd1b6379f8f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[3]
+vmaxnm.f32 s15,s16,s20 cef0cc342b4a9a42ad2a8f1048c60b6f ea411a0c3c793d37d9428c8eea411a0c 8629296b73f6fef7b64890d3a3f26c14 a3f26c142b4a9a42ad2a8f1048c60b6f ea411a0c3c793d37d9428c8eea411a0c 8629296b73f6fef7b64890d3a3f26c14 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vmaxnm.f32 s15,s16,s20 b1ebf8f5b769cbb6aaba60476365e007 92fafa2e92fafa2ebcdbfb87c449aa36 192765eccca0896753dd632ce4d0bf0a c449aa36b769cbb6aaba60476365e007 92fafa2e92fafa2ebcdbfb87c449aa36 192765eccca0896753dd632ce4d0bf0a fpscr=00000000
+vmaxnm.f32 s15,s16,s20 69bd3204894f728df3b8f2a969dff965 1f8f1e128e01ecc81e3fc6730a1636bf 4226bdeeeee480b1e9e2d853e2f13b24 0a1636bf894f728df3b8f2a969dff965 1f8f1e128e01ecc81e3fc6730a1636bf 4226bdeeeee480b1e9e2d853e2f13b24 fpscr=00000000
+vmaxnm.f32 s15,s16,s20 372f677c0d3624de71ba485eb101df34 b23135dd520f958ec92ed55a99547a3e 01e49496215fed6710d6512972619bc2 72619bc20d3624de71ba485eb101df34 b23135dd520f958ec92ed55a99547a3e 01e49496215fed6710d6512972619bc2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[3]
+vmaxnm.f32 s15,s16,s20 1d033de5326d3fd48e801d0772d1083a 54156cffa0b8b0b908dc1ce6224543d9 86537c53c8877971a5239975056dc00d 224543d9326d3fd48e801d0772d1083a 54156cffa0b8b0b908dc1ce6224543d9 86537c53c8877971a5239975056dc00d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vmaxnm.f32 s15,s16,s20 cfa9a117388fcc33cfa9a117069b9054 cc4372a3a16138364c9c069a91fe5ad1 5d1a79f51118c4f44daa98ee2354a95c 2354a95c388fcc33cfa9a117069b9054 cc4372a3a16138364c9c069a91fe5ad1 5d1a79f51118c4f44daa98ee2354a95c fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vmaxnm.f32 s15,s16,s20 f69e85f7306677bcf2e4e4415d8e19cb c5615c3126b07d4d6fe69a47c82871ba 2af9f9bea5b12e7fa97bc8585a0a10ee 5a0a10ee306677bcf2e4e4415d8e19cb c5615c3126b07d4d6fe69a47c82871ba 2af9f9bea5b12e7fa97bc8585a0a10ee fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[1]
+vmaxnm.f32 s15,s16,s20 9f04d32c0da68815fb713b76a392e04e 3a357f25fb245850f3c6dfb7192899ee 4eac425d5cbd59566fc5321b6fc5321b 6fc5321b0da68815fb713b76a392e04e 3a357f25fb245850f3c6dfb7192899ee 4eac425d5cbd59566fc5321b6fc5321b fpscr=00000000
+vmaxnm.f32 s15,s16,s20 3eebccdac5a38f5886a438c7c524da0b 20466dd37204ee4b12778e29164bd2f9 925e4b4ffc2cbef1012fdc3fb94dddab 164bd2f9c5a38f5886a438c7c524da0b 20466dd37204ee4b12778e29164bd2f9 925e4b4ffc2cbef1012fdc3fb94dddab fpscr=00000000
+vmaxnm.f32 s15,s16,s20 a2f2fe93a90012abcddfd26a0c080021 5b2816dfdfcf9e06853c661923ad1d61 3f80e208bc12760a5efe02b1809661b7 23ad1d61a90012abcddfd26a0c080021 5b2816dfdfcf9e06853c661923ad1d61 3f80e208bc12760a5efe02b1809661b7 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vmaxnm.f32 s15,s16,s20 53861d4f343ce3f1281abab6889aea48 0f2e725eeae49e082175fc1cf7016807 fbb3a9294d27a4b69908861bfef2daba f7016807343ce3f1281abab6889aea48 0f2e725eeae49e082175fc1cf7016807 fbb3a9294d27a4b69908861bfef2daba fpscr=00000000
+randV128: 2560 calls, 2645 iters
+vmaxnm.f32 s15,s16,s20 1f9acd70f3a9b3ae3f5b04eacb306de6 a64a62de08d4b2d323b3be0ad40a3e65 ad843851abf02c9e10b15821a44ddae7 a44ddae7f3a9b3ae3f5b04eacb306de6 a64a62de08d4b2d323b3be0ad40a3e65 ad843851abf02c9e10b15821a44ddae7 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vmaxnm.f32 s15,s16,s20 27cadf6fc35ac3ad24dd81fc45b34116 7c244d044602f5eddd5c22ef99738374 9e4282c40c89d7c20c89d7c2f51fb6a8 99738374c35ac3ad24dd81fc45b34116 7c244d044602f5eddd5c22ef99738374 9e4282c40c89d7c20c89d7c2f51fb6a8 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vmaxnm.f32 s15,s16,s20 bb11d02492c1d5777b1f8564a5b14329 255bf88aac917a47ac917a4709bd0b53 30f7801d9a7014081cd9bc9030f7801d 30f7801d92c1d5777b1f8564a5b14329 255bf88aac917a47ac917a4709bd0b53 30f7801d9a7014081cd9bc9030f7801d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vmaxnm.f32 s15,s16,s20 db5deeaa26c4f92286b52c121b7a678e 3da6cd1951ab4eed3c6a566848931d00 ca41b652827579ee3f7b9b446e107618 6e10761826c4f92286b52c121b7a678e 3da6cd1951ab4eed3c6a566848931d00 ca41b652827579ee3f7b9b446e107618 fpscr=00000000
+vmaxnm.f32 s15,s16,s20 4f66d2966174abecf5d2e6cc78011eea 58b7624ae2255326b83e3dec17cba321 9c2bbced489f9da43ae011f6ae305d02 17cba3216174abecf5d2e6cc78011eea 58b7624ae2255326b83e3dec17cba321 9c2bbced489f9da43ae011f6ae305d02 fpscr=00000000
+vmaxnm.f32 s15,s16,s20 e51b9a1b9a30ee089a9f30e644e20b7f 7d2c4fed70b08bade9f2d6121d8a772f 411fbb3f172e94506c336d6ebe103648 1d8a772f9a30ee089a9f30e644e20b7f 7d2c4fed70b08bade9f2d6121d8a772f 411fbb3f172e94506c336d6ebe103648 fpscr=00000000
+vmaxnm.f32 s15,s16,s20 30ba3e1d2f0996c18b7bac277cc0d446 28ce45901d20ec92369dfc1938af5d7a c6e11dc7dd71c26792f8bbce4136c7bb 4136c7bb2f0996c18b7bac277cc0d446 28ce45901d20ec92369dfc1938af5d7a c6e11dc7dd71c26792f8bbce4136c7bb fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vmaxnm.f32 s15,s16,s20 be84f142f6af736e164ef06e946d1288 07f800010935b0c1871c043e467349e1 a7b4d142a7b4d1421520292e41b09283 467349e1f6af736e164ef06e946d1288 07f800010935b0c1871c043e467349e1 a7b4d142a7b4d1421520292e41b09283 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[2]
+vmaxnm.f32 s15,s16,s20 795dd07d62eb2e7ef292a91b795dd07d bc21400ba772ff4f43af9c0dd24da3ff d93c4840a458eab26ac8e9fea458eab2 a458eab262eb2e7ef292a91b795dd07d bc21400ba772ff4f43af9c0dd24da3ff d93c4840a458eab26ac8e9fea458eab2 fpscr=00000000
+vmaxnm.f32 s15,s16,s20 e650d3d0e00ad4be20431c9628cef582 378393952e183e2633386c557f08575d 7d2cb205a9a75c2feec973381773e35e 7f08575de00ad4be20431c9628cef582 378393952e183e2633386c557f08575d 7d2cb205a9a75c2feec973381773e35e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vmaxnm.f32 s15,s16,s20 db5ab9bd50f68be99e1feec5c60b7545 74d518d4ae89cb8a410a8e1cfd988b4b b7202d388aeffa0b8aeffa0bbbcd7d1c bbcd7d1c50f68be99e1feec5c60b7545 74d518d4ae89cb8a410a8e1cfd988b4b b7202d388aeffa0b8aeffa0bbbcd7d1c fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vmaxnm.f32 s15,s16,s20 2628ec6aaaa84ff472dc3735bcb1132a f3340a846e9a1af13ab1ea70a54ae670 e3bba56f7e6cfa9ccadfcc19cadfcc19 a54ae670aaa84ff472dc3735bcb1132a f3340a846e9a1af13ab1ea70a54ae670 e3bba56f7e6cfa9ccadfcc19cadfcc19 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vmaxnm.f32 s15,s16,s20 808d6c4845eeabfc3d20bd07716e39d9 700b94c79186b8970cfda1ed9559a82a e4d5f6143868cee43868cee422378f22 22378f2245eeabfc3d20bd07716e39d9 700b94c79186b8970cfda1ed9559a82a e4d5f6143868cee43868cee422378f22 fpscr=00000000
+vmaxnm.f32 s15,s16,s20 6762e7b7e2488145c18fa93608bd4e2b 43033319de920bb98f1c360716eb8a33 68077751b9e821981e6c3290b577db84 16eb8a33e2488145c18fa93608bd4e2b 43033319de920bb98f1c360716eb8a33 68077751b9e821981e6c3290b577db84 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vmaxnm.f32 s15,s16,s20 9eae9f6b57217bb59d71f1399cc2dd3b 5d51967dba7ccc006fbaf54acb0ac224 51f78a001b23e93d86a208811a835629 1a83562957217bb59d71f1399cc2dd3b 5d51967dba7ccc006fbaf54acb0ac224 51f78a001b23e93d86a208811a835629 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[3]
+vmaxnm.f32 s15,s16,s20 1c5b22389fa7c23c9fa7c23ccb9871f0 1e2abcd615356fb2ca4bcf80fd8de15f 2ad80f11f15cfd8119b022ec2ad80f11 2ad80f119fa7c23c9fa7c23ccb9871f0 1e2abcd615356fb2ca4bcf80fd8de15f 2ad80f11f15cfd8119b022ec2ad80f11 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[2]
+vmaxnm.f32 s15,s16,s20 4068bf5e9eb166dcd46016ba257024ce fc985a9437b4856a538ff52e5a56e0cb 5e484ff45e484ff49011dd909d31ea6d 5a56e0cb9eb166dcd46016ba257024ce fc985a9437b4856a538ff52e5a56e0cb 5e484ff45e484ff49011dd909d31ea6d fpscr=00000000
+vmaxnm.f32 s15,s16,s20 3ac9e1baee8b38b67a4c95a41ec2fe16 6b7e8f46f09c6c8f0d5e525640ca9014 d66ebd3ba08c11b7a87d614b05bd9d81 40ca9014ee8b38b67a4c95a41ec2fe16 6b7e8f46f09c6c8f0d5e525640ca9014 d66ebd3ba08c11b7a87d614b05bd9d81 fpscr=00000000
+vmaxnm.f32 s15,s16,s20 8e4df20d9af11c1cbff1d858734a7e25 d8c1ae188632b0dbf4a68f3cb9d9d126 bb365dfb0a895330f263579bf42486e9 b9d9d1269af11c1cbff1d858734a7e25 d8c1ae188632b0dbf4a68f3cb9d9d126 bb365dfb0a895330f263579bf42486e9 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vmaxnm.f32 s15,s16,s20 6ff72261c932bb1d5238231e5238231e 9f8f0ef789c1387d16f018fe4fe09c7a c72d670b469ce8933a8d83a8be612d6f 4fe09c7ac932bb1d5238231e5238231e 9f8f0ef789c1387d16f018fe4fe09c7a c72d670b469ce8933a8d83a8be612d6f fpscr=00000000
+vmaxnm.f32 s15,s16,s20 a00000b26fae24d708ca20c0db185072 c87ee898af7fd53c28ee880e6c6c6a06 8a901920ee09c1e2fcca6aaa4a540320 6c6c6a066fae24d708ca20c0db185072 c87ee898af7fd53c28ee880e6c6c6a06 8a901920ee09c1e2fcca6aaa4a540320 fpscr=00000000
+vmaxnm.f32 s15,s16,s20 21890c38756454bec877cecc2a09dbd7 7c4f96ac53f01d9d40c77400e7522cae 607066b0d5917fa72963213e190f332d 190f332d756454bec877cecc2a09dbd7 7c4f96ac53f01d9d40c77400e7522cae 607066b0d5917fa72963213e190f332d fpscr=00000000
+vmaxnm.f32 s15,s16,s20 a11a798f3107b8ac5bc78a1e6d708fef e15bb2cebd97baa0dd69acd4e91d8945 22c597156743250a77fd39104017be2f 4017be2f3107b8ac5bc78a1e6d708fef e15bb2cebd97baa0dd69acd4e91d8945 22c597156743250a77fd39104017be2f fpscr=00000000
+vmaxnm.f32 s15,s16,s20 b57c2f57575bffa12275602a0114a7e9 723343fe1eef6d56b25a9a57bf29797e b600c2056a380663092ac72cbfbf2292 bf29797e575bffa12275602a0114a7e9 723343fe1eef6d56b25a9a57bf29797e b600c2056a380663092ac72cbfbf2292 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 3aa56a33357d0742794eec38c42b3b5f 1472620b229e4bbfa0ac85b3158e21bb 3cc5541f922515e2182e65fb7abc0d9c 182e65fb7abc0d9c794eec38c42b3b5f 1472620b229e4bbfa0ac85b3158e21bb 3cc5541f922515e2182e65fb7abc0d9c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vmaxnm.f64 d7, d8, d10 e60e8614d50c843f06be92e630adc0c4 57a30427809bef82c8d462a92f47a18c 539b87769f8cc67db35daa1ec67d1079 b35daa1ec67d107906be92e630adc0c4 57a30427809bef82c8d462a92f47a18c 539b87769f8cc67db35daa1ec67d1079 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vmaxnm.f64 d7, d8, d10 33c42305f3b22eba6209ab8cc39f8c89 5b29bf4dd9cd660d5ad6a1a46fdcead8 1e37aefcb7c7600b1e37aefcb7c7600b 5ad6a1a46fdcead86209ab8cc39f8c89 5b29bf4dd9cd660d5ad6a1a46fdcead8 1e37aefcb7c7600b1e37aefcb7c7600b fpscr=00000000
+vmaxnm.f64 d7, d8, d10 fc6e41ba1887448d6b1b839945b2cc64 3a0358af797ea6a3b45f81546c3e5435 b119945e245c3eac27f4c136bf3ca26b 27f4c136bf3ca26b6b1b839945b2cc64 3a0358af797ea6a3b45f81546c3e5435 b119945e245c3eac27f4c136bf3ca26b fpscr=00000000
+vmaxnm.f64 d7, d8, d10 414088e43050a90078ca48d40e0c4fca 7cf8b9b0de72aa45cc4564794b1cc468 457f0444d82ecbbffcea030f858ea8b4 cc4564794b1cc46878ca48d40e0c4fca 7cf8b9b0de72aa45cc4564794b1cc468 457f0444d82ecbbffcea030f858ea8b4 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vmaxnm.f64 d7, d8, d10 8b89bd6151de7e50d58e382d53ff93e0 e328a7a8edc57d77814648e42eabacf6 a71a47c2b44c58284dd0d95ea0252e61 4dd0d95ea0252e61d58e382d53ff93e0 e328a7a8edc57d77814648e42eabacf6 a71a47c2b44c58284dd0d95ea0252e61 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 7e670a5ffd58986d8488d7930c9d007d bf96090e9732e18e36f52d4c2babb4d6 dd67667deaabaacefd7ec8f603e304fb 36f52d4c2babb4d68488d7930c9d007d bf96090e9732e18e36f52d4c2babb4d6 dd67667deaabaacefd7ec8f603e304fb fpscr=00000000
+vmaxnm.f64 d7, d8, d10 154d341d758053409fd5c2bd7182b569 e82bc2b1ba923722c2198f86857fdd90 2b374929aac3de997164cd69c52e58ad 7164cd69c52e58ad9fd5c2bd7182b569 e82bc2b1ba923722c2198f86857fdd90 2b374929aac3de997164cd69c52e58ad fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vmaxnm.f64 d7, d8, d10 9fa766ca4772a542c83c876b39dfaa5f 773c3ace1f7746e0903e9d838535d0a0 d237a8bb7001df2f253609079e5efaae 253609079e5efaaec83c876b39dfaa5f 773c3ace1f7746e0903e9d838535d0a0 d237a8bb7001df2f253609079e5efaae fpscr=00000000
+vmaxnm.f64 d7, d8, d10 1385c44a8e6348842fb8319b13064687 50ebdbace45eb4f807237102aa442d3b cc59440b9d04ef3e98524e1070e0fb56 07237102aa442d3b2fb8319b13064687 50ebdbace45eb4f807237102aa442d3b cc59440b9d04ef3e98524e1070e0fb56 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vmaxnm.f64 d7, d8, d10 9fa17f9486d0091f9fa17f9486d0091f 393ece27f135453e7ea87c73716d1be8 45bc7b29dee075c71532bdaca0bcc688 7ea87c73716d1be89fa17f9486d0091f 393ece27f135453e7ea87c73716d1be8 45bc7b29dee075c71532bdaca0bcc688 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vmaxnm.f64 d7, d8, d10 e332271dd1b819c0960640a82b21ce86 b34991b79127566569c647aeae2ea08e 1e153cd39018929ee88f4ac7893918e2 69c647aeae2ea08e960640a82b21ce86 b34991b79127566569c647aeae2ea08e 1e153cd39018929ee88f4ac7893918e2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vmaxnm.f64 d7, d8, d10 6b91ea0d2a3c76ed6b91ea0d2a3c76ed affc7c8b24cff2b54cb78fed4c46f6d6 05b21d5160531f4462b396dd41a739d9 62b396dd41a739d96b91ea0d2a3c76ed affc7c8b24cff2b54cb78fed4c46f6d6 05b21d5160531f4462b396dd41a739d9 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vmaxnm.f64 d7, d8, d10 ad72b15f98cbda73b1bec0016dec9a94 137795641df2baa4b9c35294fd8ed858 69973984fe5b14a44c11a45f04bd5a27 4c11a45f04bd5a27b1bec0016dec9a94 137795641df2baa4b9c35294fd8ed858 69973984fe5b14a44c11a45f04bd5a27 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vmaxnm.f64 d7, d8, d10 7566bb50e85a5e2b8c975c402f1bafb5 7237bfb3ba4920806ae32f7556111204 53104b8e6570b17f995bea914662e531 6ae32f75561112048c975c402f1bafb5 7237bfb3ba4920806ae32f7556111204 53104b8e6570b17f995bea914662e531 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 880bcffa810b40ed26752ade08a76d53 d36c0dfed13dae48a89f870e3174713a 10a012a51275d47e36eac32d1e64af22 36eac32d1e64af2226752ade08a76d53 d36c0dfed13dae48a89f870e3174713a 10a012a51275d47e36eac32d1e64af22 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 fa151eefa74e6bbbd87c05fa7d4e5a91 354d8423ff5db2c18c891cde6e5ee660 c2ce0bfc72c9c1acd22f323ffc7c266c 8c891cde6e5ee660d87c05fa7d4e5a91 354d8423ff5db2c18c891cde6e5ee660 c2ce0bfc72c9c1acd22f323ffc7c266c fpscr=00000000
+vmaxnm.f64 d7, d8, d10 8ec55e61fe9f5b5a8a6e6c4390d5f250 d6e8df46c844bcd8c350eb39adeda24d 59f192397c0c7165700967b055337ffe 700967b055337ffe8a6e6c4390d5f250 d6e8df46c844bcd8c350eb39adeda24d 59f192397c0c7165700967b055337ffe fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vmaxnm.f64 d7, d8, d10 9677f5e2ac1710086d4dfc1714f4fec0 0771e71ea76fb05dfcba3354d5a11579 141011b36f28ca3aa2dd979bacfc7a68 a2dd979bacfc7a686d4dfc1714f4fec0 0771e71ea76fb05dfcba3354d5a11579 141011b36f28ca3aa2dd979bacfc7a68 fpscr=00000000
+randV128: 2816 calls, 2907 iters
+vmaxnm.f64 d7, d8, d10 a7e09f948d6ee43e19c6dde20bae288b dcf18af8a60d0cf0a2b87db2bc55401d 6dc25048d31ff865328ffe55694f0737 328ffe55694f073719c6dde20bae288b dcf18af8a60d0cf0a2b87db2bc55401d 6dc25048d31ff865328ffe55694f0737 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 40d244faedb33004a90d80c3d44e654c 6bf3a5735d0c8bad0ed9790de90b56ce ee3098ff39fd3681c011e46875604134 0ed9790de90b56cea90d80c3d44e654c 6bf3a5735d0c8bad0ed9790de90b56ce ee3098ff39fd3681c011e46875604134 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 5df465f7581ecc7da15392f47ad3f553 db294685d47ba910bf731eee3eef5bd2 714e10121f5cfb3b40c4edddbe12fc41 40c4edddbe12fc41a15392f47ad3f553 db294685d47ba910bf731eee3eef5bd2 714e10121f5cfb3b40c4edddbe12fc41 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vmaxnm.f64 d7, d8, d10 9e48dca568e6e31f4357f9915951d0bd 4bcbc8290bd58df80c434353c2c52f6b 0912777773bf59af0912777773bf59af 0c434353c2c52f6b4357f9915951d0bd 4bcbc8290bd58df80c434353c2c52f6b 0912777773bf59af0912777773bf59af fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vmaxnm.f64 d7, d8, d10 20f769a5be90c6a4bd546d6c158abf46 9187cd7b1d8dd0088b9f9fa4b39df093 6f2bd95751b333ca74899d9551c77d03 74899d9551c77d03bd546d6c158abf46 9187cd7b1d8dd0088b9f9fa4b39df093 6f2bd95751b333ca74899d9551c77d03 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vmaxnm.f64 d7, d8, d10 efdd88875a804da280f4e341a2f97704 d30c57fa47bf45e085da3f819b91c680 b08f40d1b9f5cfc428e186abe57832e7 28e186abe57832e780f4e341a2f97704 d30c57fa47bf45e085da3f819b91c680 b08f40d1b9f5cfc428e186abe57832e7 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 3221aa6deaa3241afbf3fbb1d1d1d173 fdef3ce12fdcdbe5d42bffb9fc517600 710b899dc5e5614640237c9864b8f692 40237c9864b8f692fbf3fbb1d1d1d173 fdef3ce12fdcdbe5d42bffb9fc517600 710b899dc5e5614640237c9864b8f692 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 3098372a759955c618c91c7cd94b05b6 a7cec28691c0f4d8606a0eb4b91e8140 446e4f1f6b1bdfb5e2eba9ecf9062da0 606a0eb4b91e814018c91c7cd94b05b6 a7cec28691c0f4d8606a0eb4b91e8140 446e4f1f6b1bdfb5e2eba9ecf9062da0 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vmaxnm.f64 d7, d8, d10 3f9531cd8e5205d075f5a2a20583f2e1 c6845566380568a3c6845566380568a3 94285538a259ef1a94285538a259ef1a 94285538a259ef1a75f5a2a20583f2e1 c6845566380568a3c6845566380568a3 94285538a259ef1a94285538a259ef1a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vmaxnm.f64 d7, d8, d10 7077f472cf3f3aaab00f008304ac59a6 d329d26217ab61c576f79645ddae27c5 f69abe86b228dcb6f69abe86b228dcb6 76f79645ddae27c5b00f008304ac59a6 d329d26217ab61c576f79645ddae27c5 f69abe86b228dcb6f69abe86b228dcb6 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 d85ba9a3021d0a1846cff08ada7c5d7c 03f74c12a06ae867b93dd78f31ee73d0 e627fa4515dcfd795c887ccf2a36dc13 5c887ccf2a36dc1346cff08ada7c5d7c 03f74c12a06ae867b93dd78f31ee73d0 e627fa4515dcfd795c887ccf2a36dc13 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 ca84887fa6ddb16f3ec4d40453c24248 3871392b5ccd7500b09b46ac876dc16d 07144c4b5bcf28ef5d26532c482bd1c3 5d26532c482bd1c33ec4d40453c24248 3871392b5ccd7500b09b46ac876dc16d 07144c4b5bcf28ef5d26532c482bd1c3 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vmaxnm.f64 d7, d8, d10 ddcf2a3453a67e7f37cd8f8c1406da2e 79e2dafac3661c1f86a5d8714b4f36a7 0d5684ec9d584612cd9d48aaaf4ed61b 86a5d8714b4f36a737cd8f8c1406da2e 79e2dafac3661c1f86a5d8714b4f36a7 0d5684ec9d584612cd9d48aaaf4ed61b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vmaxnm.f64 d7, d8, d10 ab9514699818c6b1bb4a1b2a0eb1ecf5 73a387779a707ed831495c1c41bbc17d f27a04ef088b46f5f27a04ef088b46f5 31495c1c41bbc17dbb4a1b2a0eb1ecf5 73a387779a707ed831495c1c41bbc17d f27a04ef088b46f5f27a04ef088b46f5 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vmaxnm.f64 d7, d8, d10 412ff561b9522baa9eca2e0a3fb7c89a 533e0013bf8e1a6e533e0013bf8e1a6e b751b0e63ec5cd09b6044d4cd2e2ef79 533e0013bf8e1a6e9eca2e0a3fb7c89a 533e0013bf8e1a6e533e0013bf8e1a6e b751b0e63ec5cd09b6044d4cd2e2ef79 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 8b034c20fa11853470c19b439cc0a5d7 1831928b73f0e342add592e6c08c6613 1756bd2e1ecb4bb18fde5fbf89aebde2 8fde5fbf89aebde270c19b439cc0a5d7 1831928b73f0e342add592e6c08c6613 1756bd2e1ecb4bb18fde5fbf89aebde2 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 84f74b8967796a074979dbae9017b139 4c3e3525e830d8bf98d84cb8277a9e2b d5507df378e72c2d9e4f99545123fffe 98d84cb8277a9e2b4979dbae9017b139 4c3e3525e830d8bf98d84cb8277a9e2b d5507df378e72c2d9e4f99545123fffe fpscr=00000000
+vmaxnm.f64 d7, d8, d10 a84c8755241d00ce61e31a360d901daf 07bcedd3e83e6e800264da3bb0af78ec d379126df08b82c88187549abce30021 0264da3bb0af78ec61e31a360d901daf 07bcedd3e83e6e800264da3bb0af78ec d379126df08b82c88187549abce30021 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 c8c536b7d92bb4953f757526efa94437 341c9a172740c67f52e043642ae379ed caa0d66ef99af12624b59e80c270d4eb 52e043642ae379ed3f757526efa94437 341c9a172740c67f52e043642ae379ed caa0d66ef99af12624b59e80c270d4eb fpscr=00000000
+vmaxnm.f64 d7, d8, d10 f483fafe34922a3a88d9b5f9ce4876a2 0f4b4b0a8359789f7817e693779196f9 c734b027a697f97ae7b60bcf59a941d3 7817e693779196f988d9b5f9ce4876a2 0f4b4b0a8359789f7817e693779196f9 c734b027a697f97ae7b60bcf59a941d3 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 56fce3fdf3d5a27e5bf5aee1b534d862 971fe85d0a1edbcf5db8b36a2a9aa133 d48a2c88ac43c94990ca5c91d6783e8e 5db8b36a2a9aa1335bf5aee1b534d862 971fe85d0a1edbcf5db8b36a2a9aa133 d48a2c88ac43c94990ca5c91d6783e8e fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vmaxnm.f64 d7, d8, d10 1e0e6038a09e9e3a6bcba155221f99c1 2dd55f2e1b957557c66c9f988903ac70 9dab748020a584a3323698261b457dbf 323698261b457dbf6bcba155221f99c1 2dd55f2e1b957557c66c9f988903ac70 9dab748020a584a3323698261b457dbf fpscr=00000000
+vmaxnm.f64 d7, d8, d10 73ee152662d4a8bc9b3ac76aebe84661 07752e2ccea92091cc2d0a88cf6af10c a3bb01476078a47a3c9b5813bb3446f4 3c9b5813bb3446f49b3ac76aebe84661 07752e2ccea92091cc2d0a88cf6af10c a3bb01476078a47a3c9b5813bb3446f4 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 25da09f42be1a9866ded34ee22184a0b c3e94c210fb62bdaad2e31d475018351 9722ebed6e0d95237b0628e9bcd4ed0d 7b0628e9bcd4ed0d6ded34ee22184a0b c3e94c210fb62bdaad2e31d475018351 9722ebed6e0d95237b0628e9bcd4ed0d fpscr=00000000
+vmaxnm.f64 d7, d8, d10 0b6a3c0da0b038b3272be06369c07300 f29fc278d91e66ba5978932b36e8a44b 8250a46c961b1b61b73eb34839b83c94 5978932b36e8a44b272be06369c07300 f29fc278d91e66ba5978932b36e8a44b 8250a46c961b1b61b73eb34839b83c94 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 d94bd39899f04441180ecc1353be375a 67e29d7874ec754289b1a2c101c1bdbf 72e05305e3be725e852cba4cb9ad688c 852cba4cb9ad688c180ecc1353be375a 67e29d7874ec754289b1a2c101c1bdbf 72e05305e3be725e852cba4cb9ad688c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vmaxnm.f64 d7, d8, d10 d39894dd6aea118ed39894dd6aea118e 315780ee24250a92315780ee24250a92 8e78a050f7a567cc268753cbbc2cf47b 315780ee24250a92d39894dd6aea118e 315780ee24250a92315780ee24250a92 8e78a050f7a567cc268753cbbc2cf47b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vmaxnm.f64 d7, d8, d10 47ac0fab0848137d47ac0fab0848137d 17487c8df2258fade0404426352df9b0 f39c5f1a7de554e704812ac0beb7a43b 04812ac0beb7a43b47ac0fab0848137d 17487c8df2258fade0404426352df9b0 f39c5f1a7de554e704812ac0beb7a43b fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vmaxnm.f64 d7, d8, d10 0ffb4cf9188ad20d71f64a98c5cc4af3 1e86b85f1b863d198f52c376c607839b ce5d8d36c1a9adfd16a6bc67777fe97a 16a6bc67777fe97a71f64a98c5cc4af3 1e86b85f1b863d198f52c376c607839b ce5d8d36c1a9adfd16a6bc67777fe97a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vmaxnm.f64 d7, d8, d10 f4be7a39201c34401e2a2b35d9cefd1c bff4ab553c70fb05bff4ab553c70fb05 841241f73a7436aa841241f73a7436aa 841241f73a7436aa1e2a2b35d9cefd1c bff4ab553c70fb05bff4ab553c70fb05 841241f73a7436aa841241f73a7436aa fpscr=00000000
+vmaxnm.f64 d7, d8, d10 adba48e671347ef6d850ab7bf82b9e27 7e1cd581cfeabbff13cfcbc1664913f8 1605b6ad71505d657c21e6bbfe57d4d1 7c21e6bbfe57d4d1d850ab7bf82b9e27 7e1cd581cfeabbff13cfcbc1664913f8 1605b6ad71505d657c21e6bbfe57d4d1 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vminnm.f32 s15,s16,s20 f552c89d503515ebdd4c507af761f4cd eaa4cca4eaa4cca437cf733689aa054c 267067e5d1ed8dd9456c82ad7897f057 89aa054c503515ebdd4c507af761f4cd eaa4cca4eaa4cca437cf733689aa054c 267067e5d1ed8dd9456c82ad7897f057 fpscr=00000000
+vminnm.f32 s15,s16,s20 46949f260b97cdeac1bcc8d0fa2694a5 52eff8f507b59a2d68689c8c181a2034 0e03b74b81044b8b30bd2da9d68292e1 d68292e10b97cdeac1bcc8d0fa2694a5 52eff8f507b59a2d68689c8c181a2034 0e03b74b81044b8b30bd2da9d68292e1 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 s15,s16,s20 9013293df9d40c65a9a804bf94aec958 d2504361d8e9f1fba9f18a9eda8a08ed 4a9488c101752289497f88655537ad45 da8a08edf9d40c65a9a804bf94aec958 d2504361d8e9f1fba9f18a9eda8a08ed 4a9488c101752289497f88655537ad45 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vminnm.f32 s15,s16,s20 0dddc0dc0dddc0dc67f2ea61699ed720 1f5e4c7ea1ed2ff7aa5b54df19276920 d28c4908c6ea9ab25438dbf029359f3d 192769200dddc0dc67f2ea61699ed720 1f5e4c7ea1ed2ff7aa5b54df19276920 d28c4908c6ea9ab25438dbf029359f3d fpscr=00000000
+vminnm.f32 s15,s16,s20 3f65287c65e0d607b843f1495252bb0e 021373ed0bea31219f43e098e4d580b9 7b74e71f24c2571542d95cf984236aaa e4d580b965e0d607b843f1495252bb0e 021373ed0bea31219f43e098e4d580b9 7b74e71f24c2571542d95cf984236aaa fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[2]
+vminnm.f32 s15,s16,s20 f6a852ac4b76345185d0b9d7c7ea8bdc a06acc5a061971f0deecd4ce7c7f3444 9161e2704c48d07e9161e270617c5981 617c59814b76345185d0b9d7c7ea8bdc a06acc5a061971f0deecd4ce7c7f3444 9161e2704c48d07e9161e270617c5981 fpscr=00000000
+vminnm.f32 s15,s16,s20 175c4ad6c651d75d10f67aacbed49949 8c2f6ca7c5d20279c486081b939acbc4 7701e9afd36df24d4703a1efb3d4e84a b3d4e84ac651d75d10f67aacbed49949 8c2f6ca7c5d20279c486081b939acbc4 7701e9afd36df24d4703a1efb3d4e84a fpscr=00000000
+vminnm.f32 s15,s16,s20 f556b472464063d004536cde86ffa4ba 8b9efbc668c8176ba4f520fd2ceec445 338b28525e2c1f39c2b3c27f4e9ff231 2ceec445464063d004536cde86ffa4ba 8b9efbc668c8176ba4f520fd2ceec445 338b28525e2c1f39c2b3c27f4e9ff231 fpscr=00000000
+vminnm.f32 s15,s16,s20 d882ccb15c381eda4a1ae38aaba3d529 2058271ca1abc117bc8466fd2e6c8ea8 c392fee16a956edffadde40665da0eea 2e6c8ea85c381eda4a1ae38aaba3d529 2058271ca1abc117bc8466fd2e6c8ea8 c392fee16a956edffadde40665da0eea fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 s15,s16,s20 ae123d938e7521296a222c5aae123d93 ba52edfc33fc43ab5a179d5c839beaed d6e81f5bca4b7d10572374cb65c5af65 839beaed8e7521296a222c5aae123d93 ba52edfc33fc43ab5a179d5c839beaed d6e81f5bca4b7d10572374cb65c5af65 fpscr=00000000
+vminnm.f32 s15,s16,s20 37eb0dfb645a48251d11c7c46b24fc55 f6d2e8d8115bba4c96e8d9ef32bf82ae 4f0106c3659a209cce60acd4d7bdcdf0 d7bdcdf0645a48251d11c7c46b24fc55 f6d2e8d8115bba4c96e8d9ef32bf82ae 4f0106c3659a209cce60acd4d7bdcdf0 fpscr=00000000
+randV128: 3072 calls, 3167 iters
+vminnm.f32 s15,s16,s20 4d2b44eb412531ede7e7c0de974f1105 6bc272e94c5e953314ced573b474b52f d97426ae33c3e9352736e9ccbc5732ba bc5732ba412531ede7e7c0de974f1105 6bc272e94c5e953314ced573b474b52f d97426ae33c3e9352736e9ccbc5732ba fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vminnm.f32 s15,s16,s20 297970fdd25d78a3fdeaf59fce9d0ba2 c9ececef1b44a6a0dd0c5c74dd0c5c74 5ecf5ae4b6a0041dc100a477b92ac94d dd0c5c74d25d78a3fdeaf59fce9d0ba2 c9ececef1b44a6a0dd0c5c74dd0c5c74 5ecf5ae4b6a0041dc100a477b92ac94d fpscr=00000000
+vminnm.f32 s15,s16,s20 0117d7c42403e202e3d4b07ac2dfe424 0fa7c5695a91a4c7a6594d9886f62faa d1a6841a4a15146c82d0febba49844af a49844af2403e202e3d4b07ac2dfe424 0fa7c5695a91a4c7a6594d9886f62faa d1a6841a4a15146c82d0febba49844af fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[1]
+vminnm.f32 s15,s16,s20 8cf61cf68cf61cf6c949cb06d7383990 89f2750905596d9275a7d96b4adaf152 121d62016b2b04826b2b0482ad64a9b0 ad64a9b08cf61cf6c949cb06d7383990 89f2750905596d9275a7d96b4adaf152 121d62016b2b04826b2b0482ad64a9b0 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vminnm.f32 s15,s16,s20 0f2f26fc07dfefa44217e41657461128 a9e66383d3af1b0b706d1168dc84e680 aef61d5401b50ba337ff9f1f3ae32736 dc84e68007dfefa44217e41657461128 a9e66383d3af1b0b706d1168dc84e680 aef61d5401b50ba337ff9f1f3ae32736 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[0]
+vminnm.f32 s15,s16,s20 1a9790cb8624bc923db70609989b727c aaf3cb1c529b8a43aaf3cb1c6362b0aa 610c3b7221483f6efa4ec995610c3b72 610c3b728624bc923db70609989b727c aaf3cb1c529b8a43aaf3cb1c6362b0aa 610c3b7221483f6efa4ec995610c3b72 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vminnm.f32 s15,s16,s20 6f49bde934ed27b26783ba2b53e76076 7785b23dae62e763a5b310186ed40ec5 592a134bc5eab6bf065c418f7d373f3f 6ed40ec534ed27b26783ba2b53e76076 7785b23dae62e763a5b310186ed40ec5 592a134bc5eab6bf065c418f7d373f3f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vminnm.f32 s15,s16,s20 5cb94f0e2f5eaabefe9db86a19f2c9e6 ddce4299da9efbc70dca38332c040778 01de75b301de75b39f07bc445a80f22b 2c0407782f5eaabefe9db86a19f2c9e6 ddce4299da9efbc70dca38332c040778 01de75b301de75b39f07bc445a80f22b fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vminnm.f32 s15,s16,s20 80f644ff526df492fd18e34ff216f2f5 be026ee74338aee969701cc7e980fa12 9c60d63a7400db835feca847ae4b9892 e980fa12526df492fd18e34ff216f2f5 be026ee74338aee969701cc7e980fa12 9c60d63a7400db835feca847ae4b9892 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vminnm.f32 s15,s16,s20 9d5e0127e49c2fa1ccf84829d1f5456c 68afa93600e39cbfc3f423ea6d93f9b1 9d216f5702b9cee02fffa58b64a9f7ea 64a9f7eae49c2fa1ccf84829d1f5456c 68afa93600e39cbfc3f423ea6d93f9b1 9d216f5702b9cee02fffa58b64a9f7ea fpscr=00000000
+vminnm.f32 s15,s16,s20 23a4ecea19e59ee55ce65fe74fa079c4 fdda20f6a54ce76148e5630849e0773d d36f9fc3c268bc0876ba27bdb596144e b596144e19e59ee55ce65fe74fa079c4 fdda20f6a54ce76148e5630849e0773d d36f9fc3c268bc0876ba27bdb596144e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vminnm.f32 s15,s16,s20 a96980535b0686c55b87c7cf8ef500ee 273e4b824e374e33273e4b82dd4e20f8 a058c97ce373af800587ea815640a7cb dd4e20f85b0686c55b87c7cf8ef500ee 273e4b824e374e33273e4b82dd4e20f8 a058c97ce373af800587ea815640a7cb fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vminnm.f32 s15,s16,s20 ef415ab0f2f70465854feb39f16f7c89 af539d813169024c32c53c9a5e52dacd 510cc51516d8a9f6666b253816d8a9f6 16d8a9f6f2f70465854feb39f16f7c89 af539d813169024c32c53c9a5e52dacd 510cc51516d8a9f6666b253816d8a9f6 fpscr=00000000
+vminnm.f32 s15,s16,s20 3b78f8411aad4fac99229cc4f25e5844 ca5777992cab2ef9a4544ad3a9972c53 c22982db4a24e5a7d1ebe204b436e6cc b436e6cc1aad4fac99229cc4f25e5844 ca5777992cab2ef9a4544ad3a9972c53 c22982db4a24e5a7d1ebe204b436e6cc fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 s15,s16,s20 6a00924363014f93d37d9f97c43f2616 313ef11845eece99ded8fa77313ef118 88a79996daaa09c04df3cdbf420d06e5 313ef11863014f93d37d9f97c43f2616 313ef11845eece99ded8fa77313ef118 88a79996daaa09c04df3cdbf420d06e5 fpscr=00000000
+vminnm.f32 s15,s16,s20 c8cf2731c2428fc5e2af41169474a0e2 76759387d4333770880548ecf6fd1eb4 b495898c55e80ffc04c6a3d26ff12002 f6fd1eb4c2428fc5e2af41169474a0e2 76759387d4333770880548ecf6fd1eb4 b495898c55e80ffc04c6a3d26ff12002 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vminnm.f32 s15,s16,s20 19481c7c7800fa3079155f059f264862 a633a7af8f51368c3c0ebf414011c739 d70b7d8c81a2f521a3efa5a3daac7c1d daac7c1d7800fa3079155f059f264862 a633a7af8f51368c3c0ebf414011c739 d70b7d8c81a2f521a3efa5a3daac7c1d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vminnm.f32 s15,s16,s20 32b6279ec91203a485ac4b53ed97ba82 9325c32f769c8f093ea4afb0769c8f09 2daea5c392a7d7a7b398d9e0ddb81a4a ddb81a4ac91203a485ac4b53ed97ba82 9325c32f769c8f093ea4afb0769c8f09 2daea5c392a7d7a7b398d9e0ddb81a4a fpscr=00000000
+vminnm.f32 s15,s16,s20 3081dba51d6d8317987b5a9dae0f4d07 4b8047ab907a0d775c7801417513748c 7c80e9c66cfbb4263c89f7f62562f817 2562f8171d6d8317987b5a9dae0f4d07 4b8047ab907a0d775c7801417513748c 7c80e9c66cfbb4263c89f7f62562f817 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vminnm.f32 s15,s16,s20 ed6019131a95d39639982a06705ab709 397bea57f0e7e6992f1c3fcd142a2121 6fc8c4685c2441d6bcba6db842446311 142a21211a95d39639982a06705ab709 397bea57f0e7e6992f1c3fcd142a2121 6fc8c4685c2441d6bcba6db842446311 fpscr=00000000
+vminnm.f32 s15,s16,s20 02bd9f4f7307555b4796eedae7a342f3 a112684dcd6c8052f4ed23c2683654db 53921dd36717a828a51aea947497e086 683654db7307555b4796eedae7a342f3 a112684dcd6c8052f4ed23c2683654db 53921dd36717a828a51aea947497e086 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vminnm.f32 s15,s16,s20 2fc42639fb1cf16c6381a531487f63fb 3b4ae22d322e80ee704883aef8b1ad8f 846a2cdb24c3e522a2c6ce3ae57154be f8b1ad8ffb1cf16c6381a531487f63fb 3b4ae22d322e80ee704883aef8b1ad8f 846a2cdb24c3e522a2c6ce3ae57154be fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[3]
+vminnm.f32 s15,s16,s20 915f616012933094686132b36c7f45c3 7c3660e5fc1354c39f1bc21e903f8c19 5ee03fdceafb37575ee03fdced53bd5b ed53bd5b12933094686132b36c7f45c3 7c3660e5fc1354c39f1bc21e903f8c19 5ee03fdceafb37575ee03fdced53bd5b fpscr=00000000
+vminnm.f32 s15,s16,s20 b252463e996553cde79e2fad58829af4 e493fdb1a1fe0a2b6ae31cae0483477f 577822a406954cc379fad28375916014 0483477f996553cde79e2fad58829af4 e493fdb1a1fe0a2b6ae31cae0483477f 577822a406954cc379fad28375916014 fpscr=00000000
+vminnm.f32 s15,s16,s20 bb4836da98ebf94e1d5497e5f6339773 dbc59beef911d0a7796d14dcbb85c7ff 7554f1093e3a374acaffa187efdafd75 efdafd7598ebf94e1d5497e5f6339773 dbc59beef911d0a7796d14dcbb85c7ff 7554f1093e3a374acaffa187efdafd75 fpscr=00000000
+vminnm.f32 s15,s16,s20 961e43d9be283a1e36a5606f44d5caf0 7e10d704de0c60e7d6bbeaac6b1f92b0 64fa09fbc9bcc820c4cadd49e10d2412 e10d2412be283a1e36a5606f44d5caf0 7e10d704de0c60e7d6bbeaac6b1f92b0 64fa09fbc9bcc820c4cadd49e10d2412 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 s15,s16,s20 f5b7407122876596a9d7366a51434dea bde0b00b2c20a34e07ecfae7d1d3cb68 b7a4a65e0277ecab61398755ab38324c d1d3cb6822876596a9d7366a51434dea bde0b00b2c20a34e07ecfae7d1d3cb68 b7a4a65e0277ecab61398755ab38324c fpscr=00000000
+vminnm.f32 s15,s16,s20 b40aa2422f83b1db84c4dedffac071bc c24369f5bcb86f0c756b85c290a41aff 62b319471814b7bc04885bc586e3f06e 90a41aff2f83b1db84c4dedffac071bc c24369f5bcb86f0c756b85c290a41aff 62b319471814b7bc04885bc586e3f06e fpscr=00000000
+vminnm.f32 s15,s16,s20 da3fc9c9ee8c9aa16f023dac024c8824 380e67bf427b823e7abe4c7e88e7bed0 70f81bbb52cb9e3c97e2dda85bb775e8 88e7bed0ee8c9aa16f023dac024c8824 380e67bf427b823e7abe4c7e88e7bed0 70f81bbb52cb9e3c97e2dda85bb775e8 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[2]
+vminnm.f32 s15,s16,s20 858aa09865569ad6a5ef6d0788a08031 ab56ed19fcaa61a6e098dc738b2d425d 81935fe2639131c2900e67e9c43bf474 c43bf47465569ad6a5ef6d0788a08031 ab56ed19fcaa61a6e098dc738b2d425d 81935fe2639131c2900e67e9c43bf474 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vminnm.f32 s15,s16,s20 fc0779d0294ddb42d39459223ca0dad4 37ae109fefe184d89fd6d6fb81f01dfd 671157272565e1299934a00dc42e38dd c42e38dd294ddb42d39459223ca0dad4 37ae109fefe184d89fd6d6fb81f01dfd 671157272565e1299934a00dc42e38dd fpscr=00000000
+vminnm.f32 s15,s16,s20 922cb7ad3c2c137252ce3d3c04fa276c cb13fa53f5311d99efbc86fc6254014f 2b0de085e64ef8b08d426aac601768c8 601768c83c2c137252ce3d3c04fa276c cb13fa53f5311d99efbc86fc6254014f 2b0de085e64ef8b08d426aac601768c8 fpscr=00000000
+vminnm.f32 s15,s16,s20 5b6a53c49ca37b9ad5b34dfe515d7d5a 827cf5aad2998502c5646d5f85d2ff2e 4a826162d20d677140ae4d10dea0d5c0 dea0d5c09ca37b9ad5b34dfe515d7d5a 827cf5aad2998502c5646d5f85d2ff2e 4a826162d20d677140ae4d10dea0d5c0 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vminnm.f32 s15,s16,s20 d4fb64aad9776f0b743133ccd4fb64aa 20075dfa8335cebc4e2a023bac4b24bf 9a50b16c6a1df2cbc4092f5490e56a71 ac4b24bfd9776f0b743133ccd4fb64aa 20075dfa8335cebc4e2a023bac4b24bf 9a50b16c6a1df2cbc4092f5490e56a71 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vminnm.f32 s15,s16,s20 afbaba6ea187d67ea5614334903aed4b 90e097a6d12efe48b8603da0b2a3b221 30ab4bc2527345592ad6425b3d92e831 b2a3b221a187d67ea5614334903aed4b 90e097a6d12efe48b8603da0b2a3b221 30ab4bc2527345592ad6425b3d92e831 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vminnm.f32 s15,s16,s20 24b20aaf785513bc9a605826fac6a020 aae6bbc6e8879b711a54879156636c43 35954ca5cc5e7e9f9efe46cdfeed83b8 feed83b8785513bc9a605826fac6a020 aae6bbc6e8879b711a54879156636c43 35954ca5cc5e7e9f9efe46cdfeed83b8 fpscr=00000000
+vminnm.f32 s15,s16,s20 81199ec2318f2daa5ac5670910d8b570 3927a0ca85a892d96a6a1f801278ed4c d49652f482195a01ec693acb781f1420 1278ed4c318f2daa5ac5670910d8b570 3927a0ca85a892d96a6a1f801278ed4c d49652f482195a01ec693acb781f1420 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[3]
+vminnm.f32 s15,s16,s20 5f528ccbe925fcb142dbed8a3a4a165c bf07eddcb3f25f849f2bff099f2bff09 a1d011233588b38f2fabce6b555ecdf7 9f2bff09e925fcb142dbed8a3a4a165c bf07eddcb3f25f849f2bff099f2bff09 a1d011233588b38f2fabce6b555ecdf7 fpscr=00000000
+vminnm.f32 s15,s16,s20 f02d931ff9448bbf628658ed9ad7fcb0 c60717aefe9ef52ae9d2676d0cabfb3f 6edccbae02a30ffb040f7b09de34d1b3 de34d1b3f9448bbf628658ed9ad7fcb0 c60717aefe9ef52ae9d2676d0cabfb3f 6edccbae02a30ffb040f7b09de34d1b3 fpscr=00000000
+vminnm.f64 d7, d8, d10 9ec1549c947ffeb078a9cd64475cfe51 ec90ec5637aeea905e01bf2020199da2 10d4263a635e43544e09b843ec70cbf2 4e09b843ec70cbf278a9cd64475cfe51 ec90ec5637aeea905e01bf2020199da2 10d4263a635e43544e09b843ec70cbf2 fpscr=00000000
+vminnm.f64 d7, d8, d10 a79b82a3915f8f4eab3ba580448a4d62 fe1dfc2afeccb03ff219be3a1cffa2c2 bab0d1f8c4709b93a9025dae0f6fe389 f219be3a1cffa2c2ab3ba580448a4d62 fe1dfc2afeccb03ff219be3a1cffa2c2 bab0d1f8c4709b93a9025dae0f6fe389 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vminnm.f64 d7, d8, d10 2c88331f90dd96f5c257b6db39e08ceb 6aef1b4fcb55517e8d16e95cb5fddb54 a9f14a4a6e9b540588086c5d7c7f5178 8d16e95cb5fddb54c257b6db39e08ceb 6aef1b4fcb55517e8d16e95cb5fddb54 a9f14a4a6e9b540588086c5d7c7f5178 fpscr=00000000
+vminnm.f64 d7, d8, d10 a312d8adcf70f7b073807b60a2968434 7541ec0d5d931043f218d534f5cc01e0 99c86c2e0bbf93dc7e9eff0ae76a330e f218d534f5cc01e073807b60a2968434 7541ec0d5d931043f218d534f5cc01e0 99c86c2e0bbf93dc7e9eff0ae76a330e fpscr=00000000
+randV128: 3328 calls, 3433 iters
+vminnm.f64 d7, d8, d10 f54010b5626ae4b563444de1631da251 8685da542b592a4b3c3d4e8ac50e41f5 eaaae575264f4936aa98e06fdc7298e5 aa98e06fdc7298e563444de1631da251 8685da542b592a4b3c3d4e8ac50e41f5 eaaae575264f4936aa98e06fdc7298e5 fpscr=00000000
+vminnm.f64 d7, d8, d10 e6b2955a9d7dd5b11d793dd305c9dae2 e2e02e55b46637c94ed58869966c4c1f ede7d25073f573b32d70940120dbb390 2d70940120dbb3901d793dd305c9dae2 e2e02e55b46637c94ed58869966c4c1f ede7d25073f573b32d70940120dbb390 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 5d2f676fd7d22aebbe30546279fcf7e3 34802b4c69984b222399fdfff45679b9 b7c7bc615c094af02cdf03077754c581 2399fdfff45679b9be30546279fcf7e3 34802b4c69984b222399fdfff45679b9 b7c7bc615c094af02cdf03077754c581 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 48b6e18fd00f054e996900f989cddb83 2b65c73a61505bdf2b65c73a61505bdf 90e329eeaf1d3cb617b2edbeee77c7c8 17b2edbeee77c7c8996900f989cddb83 2b65c73a61505bdf2b65c73a61505bdf 90e329eeaf1d3cb617b2edbeee77c7c8 fpscr=00000000
+vminnm.f64 d7, d8, d10 6e98400f51d1730d46d250dcdcc6bce0 8b971e805f3b112d467b2701af72b3c6 750958ad7f069d73549c4f572252b1f0 467b2701af72b3c646d250dcdcc6bce0 8b971e805f3b112d467b2701af72b3c6 750958ad7f069d73549c4f572252b1f0 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vminnm.f64 d7, d8, d10 21846857892877452184685789287745 1d6ee545100c3ea4c31cc94c221790dd 9e2d0d30e832c9b1d6891db29d833f51 d6891db29d833f512184685789287745 1d6ee545100c3ea4c31cc94c221790dd 9e2d0d30e832c9b1d6891db29d833f51 fpscr=00000000
+vminnm.f64 d7, d8, d10 ed6365f4b13d579ca65c0cac279a331e ad464d99b21283efbaeac4cc502dfbe0 282451202d689b5f952fa2ddadea6bb6 baeac4cc502dfbe0a65c0cac279a331e ad464d99b21283efbaeac4cc502dfbe0 282451202d689b5f952fa2ddadea6bb6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 95dadac549fc28794a712e41e3990e63 e0a1f93b23bd1340b9d0caade3b8ca53 6924c4d04588fad5b38ef7bf6ef9cba8 b9d0caade3b8ca534a712e41e3990e63 e0a1f93b23bd1340b9d0caade3b8ca53 6924c4d04588fad5b38ef7bf6ef9cba8 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 07cccb52ab09c66007cccb52ab09c660 625e408720980f918e0a10489248665f 98b073c1ae20aabc53c826337d114419 8e0a10489248665f07cccb52ab09c660 625e408720980f918e0a10489248665f 98b073c1ae20aabc53c826337d114419 fpscr=00000000
+vminnm.f64 d7, d8, d10 4769971114ed35c462edefe2ad6b86f0 51136e1b417d3f188a01bda0b5cbd541 0c69ee4f94c12f0ae997c81eed953889 e997c81eed95388962edefe2ad6b86f0 51136e1b417d3f188a01bda0b5cbd541 0c69ee4f94c12f0ae997c81eed953889 fpscr=00000000
+vminnm.f64 d7, d8, d10 08ff5f717f4541312bb93e4ab70c0661 2be8005b5d11522a9acd93f6e1a4bf89 32ce8629633b3f7244e55dfb09a5e826 9acd93f6e1a4bf892bb93e4ab70c0661 2be8005b5d11522a9acd93f6e1a4bf89 32ce8629633b3f7244e55dfb09a5e826 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 70bbc633447d5501305708f3da9f09f3 11a138c608674b5e11a138c608674b5e 2a0582bf8a507918c95a802b06e03ca6 c95a802b06e03ca6305708f3da9f09f3 11a138c608674b5e11a138c608674b5e 2a0582bf8a507918c95a802b06e03ca6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 11748cc0a04110dbee0e004a6d33d40a 814fc161cc3b86874baac00e25156ad3 39fee40d03b52d8399fd0182db9686c8 99fd0182db9686c8ee0e004a6d33d40a 814fc161cc3b86874baac00e25156ad3 39fee40d03b52d8399fd0182db9686c8 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vminnm.f64 d7, d8, d10 f8f5eb2bd4cc3278d9c28987088ebb74 687b6874ac69c54e687b6874ac69c54e e04ff3c0cc9e57382541d9c33ad50b54 2541d9c33ad50b54d9c28987088ebb74 687b6874ac69c54e687b6874ac69c54e e04ff3c0cc9e57382541d9c33ad50b54 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 0de3d32e7cd9086c0de3d32e7cd9086c 6bc9774a7e25fc8bb01edfacdf8ac25f 326cd2fe3712125c212178108f417431 b01edfacdf8ac25f0de3d32e7cd9086c 6bc9774a7e25fc8bb01edfacdf8ac25f 326cd2fe3712125c212178108f417431 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vminnm.f64 d7, d8, d10 8a81c5fd311b604c8a81c5fd311b604c 1a37d2a98af6b0475ed1beed6a5711bc f51a2c0783f303c0f51a2c0783f303c0 f51a2c0783f303c08a81c5fd311b604c 1a37d2a98af6b0475ed1beed6a5711bc f51a2c0783f303c0f51a2c0783f303c0 fpscr=00000000
+vminnm.f64 d7, d8, d10 220b085975c7a3c660b975f0383bffd6 8ab5d33be766a2af6e820706ee7650b5 c184f01a4634642b2590198ea9cc39a8 2590198ea9cc39a860b975f0383bffd6 8ab5d33be766a2af6e820706ee7650b5 c184f01a4634642b2590198ea9cc39a8 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 6d9cd02f0271d0516d9cd02f0271d051 2c11278ef5961e958ce66de3b273bdbe cd910de5eada647caef734dd13660347 aef734dd136603476d9cd02f0271d051 2c11278ef5961e958ce66de3b273bdbe cd910de5eada647caef734dd13660347 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 d1d0240f9bbf5022d1d0240f9bbf5022 788db58718eb1fb8e14e997675c86db4 c81b0e070b8af4476523ba552d182cc6 e14e997675c86db4d1d0240f9bbf5022 788db58718eb1fb8e14e997675c86db4 c81b0e070b8af4476523ba552d182cc6 fpscr=00000000
+vminnm.f64 d7, d8, d10 76682dcdaa5f3b2009ac97e33c494d2a a5266625a1458c0d9da583c5958459b8 4f428d6b1b442e5cbe1c042de1a001a2 be1c042de1a001a209ac97e33c494d2a a5266625a1458c0d9da583c5958459b8 4f428d6b1b442e5cbe1c042de1a001a2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 f4eb9b3491cb064491bc2b888e1301c7 f9719f065bfe66ec13ab103abfc21302 cd8da1b2b6bd34179f3291145c50d2e5 9f3291145c50d2e591bc2b888e1301c7 f9719f065bfe66ec13ab103abfc21302 cd8da1b2b6bd34179f3291145c50d2e5 fpscr=00000000
+vminnm.f64 d7, d8, d10 92b5cc13407b10facd4630f5eb58184d 9275a105fbdcc61fb4f968a7cf7f7c73 a34bb754b1d2a092bfd4c56b483ef726 bfd4c56b483ef726cd4630f5eb58184d 9275a105fbdcc61fb4f968a7cf7f7c73 a34bb754b1d2a092bfd4c56b483ef726 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 198403cbb09aad37b18c1a38458da3c8 594955ac5535cf9c594955ac5535cf9c 45173c9854dd5623c418f6d184202c9f c418f6d184202c9fb18c1a38458da3c8 594955ac5535cf9c594955ac5535cf9c 45173c9854dd5623c418f6d184202c9f fpscr=00000000
+vminnm.f64 d7, d8, d10 9a8a255fcb043fea90fe9f3796fcd137 5a98438632fd60ad9fed876786a02dd9 7c4e0f9638646d144b1b4a608dcb8a7b 9fed876786a02dd990fe9f3796fcd137 5a98438632fd60ad9fed876786a02dd9 7c4e0f9638646d144b1b4a608dcb8a7b fpscr=00000000
+vminnm.f64 d7, d8, d10 584cc0eab93691a24040ae322b196167 51ea76b695b9598113dfc32e1d376be0 7049997b8d3de13226de28643c1e87f2 13dfc32e1d376be04040ae322b196167 51ea76b695b9598113dfc32e1d376be0 7049997b8d3de13226de28643c1e87f2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 6bc945ee0c4749a7e6d717df1c551bef 4dfef88be36457b1c60f6e50928e9f9b 01f5aef560f270e701f5aef560f270e7 c60f6e50928e9f9be6d717df1c551bef 4dfef88be36457b1c60f6e50928e9f9b 01f5aef560f270e701f5aef560f270e7 fpscr=00000000
+vminnm.f64 d7, d8, d10 29584bb3638541f81767cfd581e50028 d1079eaec96aec6598074be49b3dc0f3 567ed59aaae490d7d98443038dac0e9f d98443038dac0e9f1767cfd581e50028 d1079eaec96aec6598074be49b3dc0f3 567ed59aaae490d7d98443038dac0e9f fpscr=00000000
+vminnm.f64 d7, d8, d10 1c205b3b940310d30932c82b2605cad6 57043d12b557bd2b51db45f1d02f59b9 91eb19720583927a0be916c41d24d422 0be916c41d24d4220932c82b2605cad6 57043d12b557bd2b51db45f1d02f59b9 91eb19720583927a0be916c41d24d422 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vminnm.f64 d7, d8, d10 4bd09af378c7960d4bd09af378c7960d 2d0308627cc2a7cbfdf97f8b140a4707 351d130e5ad47fce351d130e5ad47fce fdf97f8b140a47074bd09af378c7960d 2d0308627cc2a7cbfdf97f8b140a4707 351d130e5ad47fce351d130e5ad47fce fpscr=00000000
+vminnm.f64 d7, d8, d10 1fbb00ebaf8a95bbde0452f075634264 25984cab1808a12165e9f2a72383e102 34363a26516ccef4f4eb9c1d14c70acc f4eb9c1d14c70accde0452f075634264 25984cab1808a12165e9f2a72383e102 34363a26516ccef4f4eb9c1d14c70acc fpscr=00000000
+vminnm.f64 d7, d8, d10 79cf50c81b4db67658e0a64ac3e5927f c03de1a887567130f3aa58b47815d64a 7547867ba4f72828ad55e70c78af8c69 f3aa58b47815d64a58e0a64ac3e5927f c03de1a887567130f3aa58b47815d64a 7547867ba4f72828ad55e70c78af8c69 fpscr=00000000
+vminnm.f64 d7, d8, d10 a213907a5bb89395228cf23e515dc116 f4173bd6da5a3f17ed5d7872c34e0a9a 32f0e426df8d5673d1991992c7c44e9a ed5d7872c34e0a9a228cf23e515dc116 f4173bd6da5a3f17ed5d7872c34e0a9a 32f0e426df8d5673d1991992c7c44e9a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 bf2cd9d50af025e3bf2cd9d50af025e3 3e28769e676205e7a9ca7fbe9441b358 1e7251f658653e5c42aa5ca5227a50ab a9ca7fbe9441b358bf2cd9d50af025e3 3e28769e676205e7a9ca7fbe9441b358 1e7251f658653e5c42aa5ca5227a50ab fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vminnm.f64 d7, d8, d10 eac12e3944df9ab1eac12e3944df9ab1 314e17b383e9c115ddeccbb00ace9061 c46c7499b555a62a814baf3edb687f3a ddeccbb00ace9061eac12e3944df9ab1 314e17b383e9c115ddeccbb00ace9061 c46c7499b555a62a814baf3edb687f3a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vminnm.f64 d7, d8, d10 4437d397b9743eea4437d397b9743eea bf4ee30eaeb2ad9f2d14266dfe745df2 92487395bc490dba92487395bc490dba 92487395bc490dba4437d397b9743eea bf4ee30eaeb2ad9f2d14266dfe745df2 92487395bc490dba92487395bc490dba fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vminnm.f64 d7, d8, d10 4fc8fb3982ea9f3064fd20fc984d5ed2 2598a727cc12ff703dd79fad3dbe0bbf debde6a1833566913adc2a38aa6e5fed 3adc2a38aa6e5fed64fd20fc984d5ed2 2598a727cc12ff703dd79fad3dbe0bbf debde6a1833566913adc2a38aa6e5fed fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 47b319f62681891fc1eb8e49616fd615 61ede562bb7457843a9f257a4069babf 214495377475bea9214495377475bea9 214495377475bea9c1eb8e49616fd615 61ede562bb7457843a9f257a4069babf 214495377475bea9214495377475bea9 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 0b62c3a128c627570b62c3a128c62757 043680eec62a1940043680eec62a1940 a0113f7b3d00a487a0113f7b3d00a487 a0113f7b3d00a4870b62c3a128c62757 043680eec62a1940043680eec62a1940 a0113f7b3d00a487a0113f7b3d00a487 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 5c976443bd0713296f502ff8cf3da17e 020ef55a1b770c1047ed85af80c2ee92 5f577d08a074403e8732e10f789f4ae9 8732e10f789f4ae96f502ff8cf3da17e 020ef55a1b770c1047ed85af80c2ee92 5f577d08a074403e8732e10f789f4ae9 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 1229f40ae22f3e8d889328a80ea09247 8bef9baa8612f9c48bef9baa8612f9c4 67658674cd858f09bbe927e48a25cc63 bbe927e48a25cc63889328a80ea09247 8bef9baa8612f9c48bef9baa8612f9c4 67658674cd858f09bbe927e48a25cc63 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 438cf3a264405cb511e011eceabc8a97 2a12da48681ccb058e8c08f86319432c 4883bf5d84f4ceec4822b2555087d8cd 8e8c08f86319432c11e011eceabc8a97 2a12da48681ccb058e8c08f86319432c 4883bf5d84f4ceec4822b2555087d8cd fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vminnm.f64 d7, d8, d10 7eaa866be2dbff6faa3a512df4ab3ca2 1e59fbb636c5e7f71e59fbb636c5e7f7 50c798a9ca7d199220ebcf7e719230be 1e59fbb636c5e7f7aa3a512df4ab3ca2 1e59fbb636c5e7f71e59fbb636c5e7f7 50c798a9ca7d199220ebcf7e719230be fpscr=00000000
+vminnm.f64 d7, d8, d10 9cb2a35dbc82efac3b6487d679d2f1d4 11007afcf516e6650ae4b1b472a991ef a3c37c58d9837c5fb33a00cfec660ef7 b33a00cfec660ef73b6487d679d2f1d4 11007afcf516e6650ae4b1b472a991ef a3c37c58d9837c5fb33a00cfec660ef7 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: 3584 calls, 3696 iters
+randV128: doing v->u64[1] = v->u64[0]
+vminnm.f64 d7, d8, d10 6e94ba9741a454786e94ba9741a45478 316c3ccd0e18c9f5316c3ccd0e18c9f5 fc7177d43296dc4073fed4fda03d6415 316c3ccd0e18c9f56e94ba9741a45478 316c3ccd0e18c9f5316c3ccd0e18c9f5 fc7177d43296dc4073fed4fda03d6415 fpscr=00000000
+vminnm.f64 d7, d8, d10 0bcff263998f4a44b80ade780f0c9e89 5cf7cb9fb7996e611418f17ccdef0ae7 9d8feb5aaa9f1219a6c0aca13a182f34 a6c0aca13a182f34b80ade780f0c9e89 5cf7cb9fb7996e611418f17ccdef0ae7 9d8feb5aaa9f1219a6c0aca13a182f34 fpscr=00000000
+vminnm.f64 d7, d8, d10 2799d86db51d6d4557c89bbd15daa663 66b74276c49ba036af846d8cb0513b5d 1f8cef3da97dcf61057d84ce222fe110 af846d8cb0513b5d57c89bbd15daa663 66b74276c49ba036af846d8cb0513b5d 1f8cef3da97dcf61057d84ce222fe110 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.s32.f64 s27, d5 90fee8100cd5fcdbfb0aea5fd18f9878 349118e0e476089d5786937ece260dc4 000000000cd5fcdbfb0aea5fd18f9878 349118e0e476089d5786937ece260dc4 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.s32.f64 s27, d5 af52f88010a1793c4b4aae2d69481892 d62d843b7acd102936bf8ffb940bac20 8000000010a1793c4b4aae2d69481892 d62d843b7acd102936bf8ffb940bac20 fpscr=00000000
+vcvtn.s32.f64 s27, d5 e30cba8ce8afc882522bfa6d8669f89b c2275295a08361c6675a9b121522ed9e 80000000e8afc882522bfa6d8669f89b c2275295a08361c6675a9b121522ed9e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.s32.f64 s27, d5 921ada5bbda3e60c68ef7cd8025a8409 77bcd4719ae52216159738cc7552a745 7fffffffbda3e60c68ef7cd8025a8409 77bcd4719ae52216159738cc7552a745 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.s32.f64 s27, d5 a5c00450bfb1e4d0f8e4ea27ed4d999f b93cc92492ee1f0fb93cc92492ee1f0f 00000000bfb1e4d0f8e4ea27ed4d999f b93cc92492ee1f0fb93cc92492ee1f0f fpscr=00000000
+vcvtn.s32.f64 s27, d5 8adcff12cc476b2c0fa34a206d600ec6 2b18d2f46017574cdf80d9867b0013c5 00000000cc476b2c0fa34a206d600ec6 2b18d2f46017574cdf80d9867b0013c5 fpscr=00000000
+vcvtn.s32.f64 s27, d5 45e2f407a8e7b531a498925b2d57e73a 2287e87d55169baab785e8a6b3824560 00000000a8e7b531a498925b2d57e73a 2287e87d55169baab785e8a6b3824560 fpscr=00000000
+vcvtn.s32.f64 s27, d5 444d138025981175b654865a0f041c81 8f896e8cfb86188b9604074926c1ef13 0000000025981175b654865a0f041c81 8f896e8cfb86188b9604074926c1ef13 fpscr=00000000
+vcvtn.s32.f64 s27, d5 a00af8661f02febe49299f5a69a53e71 e6ac0a57f619128eab499c753e98083c 800000001f02febe49299f5a69a53e71 e6ac0a57f619128eab499c753e98083c fpscr=00000000
+vcvtn.s32.f64 s27, d5 ee74fa61eaa2c16d702647584cfb649e a9b1fbf67030bce1ce369d456f835a70 00000000eaa2c16d702647584cfb649e a9b1fbf67030bce1ce369d456f835a70 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.s32.f64 s27, d5 7526c9d91d40b0df7526c9d91d40b0df dcd8d1e40cba09fcdcd8d1e40cba09fc 800000001d40b0df7526c9d91d40b0df dcd8d1e40cba09fcdcd8d1e40cba09fc fpscr=00000000
+vcvtn.s32.f64 s27, d5 6ed57af105c9428f5a2f2ec6bad1f340 180d52b6c85c932554087f47d75cfe58 0000000005c9428f5a2f2ec6bad1f340 180d52b6c85c932554087f47d75cfe58 fpscr=00000000
+vcvtn.s32.f64 s27, d5 27fe4e5e1b6502b9b3b8e8e5fa247f43 534cc88b9bd6934c2fd755f5081e4216 7fffffff1b6502b9b3b8e8e5fa247f43 534cc88b9bd6934c2fd755f5081e4216 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.s32.f64 s27, d5 d4b9ca25543b9c4ed4b9ca25543b9c4e 339503f95c5b9382339503f95c5b9382 00000000543b9c4ed4b9ca25543b9c4e 339503f95c5b9382339503f95c5b9382 fpscr=00000000
+vcvtn.s32.f64 s27, d5 16bb7db339a7e7d66cc60944430fc315 7bcd89a7ab73a93bcfbe054d75703757 7fffffff39a7e7d66cc60944430fc315 7bcd89a7ab73a93bcfbe054d75703757 fpscr=00000000
+vcvtn.s32.f64 s27, d5 f2bf73fac3191a5251773b54d4909e42 aae3bfaff628bd76a93f9713ee95cbad 00000000c3191a5251773b54d4909e42 aae3bfaff628bd76a93f9713ee95cbad fpscr=00000000
+vcvtn.s32.f64 s27, d5 d85b0553f12cc975ded512d0aa80ee7b ed6d047cc9bcac96fe6aa8591e439480 80000000f12cc975ded512d0aa80ee7b ed6d047cc9bcac96fe6aa8591e439480 fpscr=00000000
+vcvtn.s32.f64 s27, d5 600362d1651635444cdd39c6474f478e 03e37934c6b981954beab5d0f372a830 00000000651635444cdd39c6474f478e 03e37934c6b981954beab5d0f372a830 fpscr=00000000
+vcvtn.s32.f64 s27, d5 2220dbef76419b551e5c1d60e532a34c e2b40d5113d3d32539a7e01e904d3a3b 8000000076419b551e5c1d60e532a34c e2b40d5113d3d32539a7e01e904d3a3b fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.s32.f64 s27, d5 54933584a61881f654933584a61881f6 1ef40d031757e33797b9c7193ecdc31c 00000000a61881f654933584a61881f6 1ef40d031757e33797b9c7193ecdc31c fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.s32.f64 s27, d5 dccc7cdf8428f17fd41a8b4ed0d1fbab 874da009a8082ae4874da009a8082ae4 000000008428f17fd41a8b4ed0d1fbab 874da009a8082ae4874da009a8082ae4 fpscr=00000000
+vcvtn.s32.f64 s27, d5 59f12c596b0028738dfb98fa71191355 4df5833cb320c969ac5bc6e41d4ca807 7fffffff6b0028738dfb98fa71191355 4df5833cb320c969ac5bc6e41d4ca807 fpscr=00000000
+vcvtn.s32.f64 s27, d5 3ae119d05f9cdbf20a95119ef82c3bcb 2160ae3c91cc95781ef87ff43fdf2bf6 000000005f9cdbf20a95119ef82c3bcb 2160ae3c91cc95781ef87ff43fdf2bf6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.s32.f64 s27, d5 d61eefa23c9164d1fb08f455a19577ae 590cd09503797b30bd708097ab8039f4 7fffffff3c9164d1fb08f455a19577ae 590cd09503797b30bd708097ab8039f4 fpscr=00000000
+vcvtn.s32.f64 s27, d5 d2533fb73531c2a57abb985649fb1efe c58f064e0bdab348e6dde8ff7034132b 800000003531c2a57abb985649fb1efe c58f064e0bdab348e6dde8ff7034132b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.s32.f64 s27, d5 f6d956f7a846dc7db41577aa0e19f428 e1f83b72a8250702e1f83b72a8250702 80000000a846dc7db41577aa0e19f428 e1f83b72a8250702e1f83b72a8250702 fpscr=00000000
+vcvtn.s32.f64 s27, d5 8a7c4af8c6c5074b2d476f58f4826ae6 9b57c96a018d2b71b7ffc205a9a3ef57 00000000c6c5074b2d476f58f4826ae6 9b57c96a018d2b71b7ffc205a9a3ef57 fpscr=00000000
+vcvtn.s32.f64 s27, d5 f345f2050f21d1eb70985743bb00657d 088ebbb8658d83735757f51f90172d6e 000000000f21d1eb70985743bb00657d 088ebbb8658d83735757f51f90172d6e fpscr=00000000
+vcvtn.s32.f64 s27, d5 1edb8be1f468b449e87dd22eef6c5244 978034cf287f804e7ece8cedd52fd9f0 00000000f468b449e87dd22eef6c5244 978034cf287f804e7ece8cedd52fd9f0 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.s32.f64 s27, d5 f436c3caf52d3dd788b87ce3f5f12b22 ece91f25bd7e8ee17c3a8b6445fb45b8 80000000f52d3dd788b87ce3f5f12b22 ece91f25bd7e8ee17c3a8b6445fb45b8 fpscr=00000000
+vcvtn.s32.f64 s27, d5 60659f3bd81af30db3ca886c79ea7c81 ab1ad7a1d8718f543c12bc531b7f5ce4 00000000d81af30db3ca886c79ea7c81 ab1ad7a1d8718f543c12bc531b7f5ce4 fpscr=00000000
+vcvtn.s32.f64 s27, d5 14d692722d428ef08c5d9844bf02c9db e74efc9b79b479f5beff0576cf3daca3 800000002d428ef08c5d9844bf02c9db e74efc9b79b479f5beff0576cf3daca3 fpscr=00000000
+vcvtn.s32.f64 s27, d5 521db966c38b67be2674e70b5e6fc94b ba2bbe9be0f0f66d3a7346ec2123a1dd 00000000c38b67be2674e70b5e6fc94b ba2bbe9be0f0f66d3a7346ec2123a1dd fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.s32.f64 s27, d5 bfc467892f6e74766eda45c52c5989ec e46d6f626c56ef630404e3004f37a064 800000002f6e74766eda45c52c5989ec e46d6f626c56ef630404e3004f37a064 fpscr=00000000
+vcvtn.s32.f64 s27, d5 6b223317e0e73ee0b2cef672b500b6f7 e05ef38a602746b2a0c08904dd2137e9 80000000e0e73ee0b2cef672b500b6f7 e05ef38a602746b2a0c08904dd2137e9 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.s32.f64 s27, d5 6df80d460613e5f24e7959fbdb1d68e1 2ad595fd3f30c890a041336112c34142 000000000613e5f24e7959fbdb1d68e1 2ad595fd3f30c890a041336112c34142 fpscr=00000000
+vcvtn.s32.f64 s27, d5 6a9954f8fc7e1b92af25b316f74161b9 87a99dbbdba8d9758b61008d07adeaf8 00000000fc7e1b92af25b316f74161b9 87a99dbbdba8d9758b61008d07adeaf8 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.s32.f64 s27, d5 126d0964aeae528c126d0964aeae528c f017af13c070a20c9cbd66215ee8ff4e 80000000aeae528c126d0964aeae528c f017af13c070a20c9cbd66215ee8ff4e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.s32.f64 s27, d5 4ff81cfd4109cb254ff81cfd4109cb25 40dc0f269c976ad9bd7541025d1d4d5d 0000703d4109cb254ff81cfd4109cb25 40dc0f269c976ad9bd7541025d1d4d5d fpscr=00000000
+vcvtn.s32.f64 s27, d5 0964b1f33ddd90244704f9ab858d06be 00a35c7f7e9df161dd82eb9d1fb4b13a 000000003ddd90244704f9ab858d06be 00a35c7f7e9df161dd82eb9d1fb4b13a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.s32.f64 s27, d5 5985a4650b064e552ae602b08f3874dc 64c95ed7eecf5c91ae082e688955c1c6 7fffffff0b064e552ae602b08f3874dc 64c95ed7eecf5c91ae082e688955c1c6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.s32.f64 s27, d5 42915857d1727e7df33ea69a95f1e7a2 3c529920280185733c52992028018573 00000000d1727e7df33ea69a95f1e7a2 3c529920280185733c52992028018573 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.s32.f64 s27, d5 efee5fc6feb274876dcd7cf8df800569 af1013836ac7e496af1013836ac7e496 00000000feb274876dcd7cf8df800569 af1013836ac7e496af1013836ac7e496 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.s32.f64 s27, d5 faf6f2d9bfcc57d4f47238e723cb7070 4afe5e1590aedf954afe5e1590aedf95 7fffffffbfcc57d4f47238e723cb7070 4afe5e1590aedf954afe5e1590aedf95 fpscr=00000000
+vcvtn.s32.f64 s27, d5 10cfb8612d1f4b652f5d9aecc7658fce 0aee4fd5f3f0120f665b74592cc42e19 000000002d1f4b652f5d9aecc7658fce 0aee4fd5f3f0120f665b74592cc42e19 fpscr=00000000
+vcvtn.s32.f64 s27, d5 e7bb24273932e67bea3e510df77288b6 f1203ab706cab0deade6bf72a97b9fff 800000003932e67bea3e510df77288b6 f1203ab706cab0deade6bf72a97b9fff fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.s32.f64 s27, d5 3121e28650ebf0573121e28650ebf057 f28d3c301d770f5b899afeb34ef199cd 8000000050ebf0573121e28650ebf057 f28d3c301d770f5b899afeb34ef199cd fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.s32.f64 s27, d5 07a2561d84bab44dac60ca4fbd618bf2 f4af9c4a973475e6f4af9c4a973475e6 8000000084bab44dac60ca4fbd618bf2 f4af9c4a973475e6f4af9c4a973475e6 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.s32.f64 s27, d5 72e6d24ae307e0dc5b03c5e9e3ce4cec 7477951d11aa5121c8c1dd4af79c4eb5 7fffffffe307e0dc5b03c5e9e3ce4cec 7477951d11aa5121c8c1dd4af79c4eb5 fpscr=00000000
+vcvtn.s32.f64 s27, d5 e8f322a8fc299eafe9faf4c338164d9b 715e8d0c83aa81ed1598959f39541589 7ffffffffc299eafe9faf4c338164d9b 715e8d0c83aa81ed1598959f39541589 fpscr=00000000
+vcvta.s32.f64 s4, d20 0bbc664c856b28631ba9138a130b7924 682f52705f91f731b2a643c3207d30a0 0bbc664c856b28631ba9138a00000000 682f52705f91f731b2a643c3207d30a0 fpscr=00000000
+vcvta.s32.f64 s4, d20 6f35416b040a850f337b75cd19b39b5b 8e6ebe2f88e618298cf1ef31d28c829e 6f35416b040a850f337b75cd00000000 8e6ebe2f88e618298cf1ef31d28c829e fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.s32.f64 s4, d20 ad03ad8fae9155f4f502099bcf7be641 29b82782fc08311a89675e8542090b73 ad03ad8fae9155f4f502099b00000000 29b82782fc08311a89675e8542090b73 fpscr=00000000
+vcvta.s32.f64 s4, d20 4b5e40f641f2bf2b49798fcfd8401b77 8eb35c674704542221a51bbddf2de515 4b5e40f641f2bf2b49798fcf00000000 8eb35c674704542221a51bbddf2de515 fpscr=00000000
+vcvta.s32.f64 s4, d20 48fdd0475b4076107a19a25c535df34f 169af45191d8dea8826c4654fb6d4c6c 48fdd0475b4076107a19a25c00000000 169af45191d8dea8826c4654fb6d4c6c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.s32.f64 s4, d20 bceef7694a3078abbceef7694a3078ab 56ff0f65bfb898fa56ff0f65bfb898fa bceef7694a3078abbceef7697fffffff 56ff0f65bfb898fa56ff0f65bfb898fa fpscr=00000000
+vcvta.s32.f64 s4, d20 6bce17b8793952bc28f90e0d260093d1 58f6c71be48b630a08a348e720c0c19a 6bce17b8793952bc28f90e0d00000000 58f6c71be48b630a08a348e720c0c19a fpscr=00000000
+vcvta.s32.f64 s4, d20 9742dc845a0e09f508d95aa41353f41c 5092a1a458e829fd9c653ef66299505d 9742dc845a0e09f508d95aa400000000 5092a1a458e829fd9c653ef66299505d fpscr=00000000
+vcvta.s32.f64 s4, d20 c9ce429dcaa25f1fa7f8eea4d74ce698 651ce7516d2f7852686f4c491f37855e c9ce429dcaa25f1fa7f8eea47fffffff 651ce7516d2f7852686f4c491f37855e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: 3840 calls, 3963 iters
+vcvta.s32.f64 s4, d20 c330376cc0b05ea3c330376cc0b05ea3 bcdd1f808deb40edc8b8a375ace71733 c330376cc0b05ea3c330376c80000000 bcdd1f808deb40edc8b8a375ace71733 fpscr=00000000
+vcvta.s32.f64 s4, d20 5359da301f1f5b7f93b31fb99875239d ee58ac322cfd8e072a805fa2d5aa5c7f 5359da301f1f5b7f93b31fb900000000 ee58ac322cfd8e072a805fa2d5aa5c7f fpscr=00000000
+vcvta.s32.f64 s4, d20 1c3b0cfe6071fc1a1318897aa7852a1b ca66450d6647b2df265a0643311b3915 1c3b0cfe6071fc1a1318897a00000000 ca66450d6647b2df265a0643311b3915 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.s32.f64 s4, d20 b0faa406a244bd8ab0faa406a244bd8a 469441e2410f0f385a37341cbdb4c8f8 b0faa406a244bd8ab0faa4067fffffff 469441e2410f0f385a37341cbdb4c8f8 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.s32.f64 s4, d20 0ff336666fafa084ad619d56f4d58366 8437c3602556381ff0561857b2fe3a38 0ff336666fafa084ad619d5680000000 8437c3602556381ff0561857b2fe3a38 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.s32.f64 s4, d20 6ffe11c7222cc356fa5d538774101ee6 925393b565d1ee932572ba338c058361 6ffe11c7222cc356fa5d538700000000 925393b565d1ee932572ba338c058361 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.s32.f64 s4, d20 2c1726f7e1fbc334ba95b6a8a4d735b3 07887aef75de8e8a07887aef75de8e8a 2c1726f7e1fbc334ba95b6a800000000 07887aef75de8e8a07887aef75de8e8a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.s32.f64 s4, d20 188c03531b96cf79188c03531b96cf79 f16f16ed66f82551938286f577ddacb9 188c03531b96cf79188c035300000000 f16f16ed66f82551938286f577ddacb9 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.s32.f64 s4, d20 1a48699ad92a6c9427f085d58fd1a329 3c2d024ce96ff1ef4c50ba8938cd74e6 1a48699ad92a6c9427f085d57fffffff 3c2d024ce96ff1ef4c50ba8938cd74e6 fpscr=00000000
+vcvta.s32.f64 s4, d20 aea822055609942f3e4860b7cae1540e 06293083997a532993dba4f1512fd116 aea822055609942f3e4860b700000000 06293083997a532993dba4f1512fd116 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.s32.f64 s4, d20 98f2c24ae690a2efcbb26b8c41d5a463 8d35a509a903ce31e86609ce28e12c9a 98f2c24ae690a2efcbb26b8c80000000 8d35a509a903ce31e86609ce28e12c9a fpscr=00000000
+vcvta.s32.f64 s4, d20 5736101e5e4b170bb55b1dfb28f78ab3 fd4a855044607252b827cf4157418525 5736101e5e4b170bb55b1dfb00000000 fd4a855044607252b827cf4157418525 fpscr=00000000
+vcvta.s32.f64 s4, d20 d6fc759e240c3081eb216db9bd8b7170 97b109300399fddfa2b8030c58bb2da6 d6fc759e240c3081eb216db900000000 97b109300399fddfa2b8030c58bb2da6 fpscr=00000000
+vcvta.s32.f64 s4, d20 890179a0c75206bf4f8c4356b9ca4773 63b49fb3198c566c197e36daca080043 890179a0c75206bf4f8c435600000000 63b49fb3198c566c197e36daca080043 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.s32.f64 s4, d20 f3e8b878b71529fdf3e8b878b71529fd 5be1eece46028465ed73b25a7bc19fd9 f3e8b878b71529fdf3e8b87880000000 5be1eece46028465ed73b25a7bc19fd9 fpscr=00000000
+vcvta.s32.f64 s4, d20 0ff68a6c90fa10bda7135388ebe33c1d 32ba4d322687e54f649d214987dbc2fd 0ff68a6c90fa10bda71353887fffffff 32ba4d322687e54f649d214987dbc2fd fpscr=00000000
+vcvta.s32.f64 s4, d20 c9a753ca367d71290bc2883c95850efc ab36c8474ab2c709eab01e20a54d9b3e c9a753ca367d71290bc2883c80000000 ab36c8474ab2c709eab01e20a54d9b3e fpscr=00000000
+vcvta.s32.f64 s4, d20 f25125241ec33eb516946d2771d477a6 12c9da0bb3b0486af15baa2e083bfa20 f25125241ec33eb516946d2780000000 12c9da0bb3b0486af15baa2e083bfa20 fpscr=00000000
+vcvta.s32.f64 s4, d20 0ad831116ba4dee7ba769cf78f9c60c7 91bd9d4ad1f31abb40e9b7b888955581 0ad831116ba4dee7ba769cf70000cdbe 91bd9d4ad1f31abb40e9b7b888955581 fpscr=00000000
+vcvta.s32.f64 s4, d20 3f28e2d0fc1831fc99f348777d1f4ef0 707c8cc257a2edf96cc92f55b3c07512 3f28e2d0fc1831fc99f348777fffffff 707c8cc257a2edf96cc92f55b3c07512 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.s32.f64 s4, d20 17e158043b83303af01b018a5d9e4535 a2c5ac2070e731efae025730432d79b9 17e158043b83303af01b018a00000000 a2c5ac2070e731efae025730432d79b9 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.s32.f64 s4, d20 cfb4fd57c7c8cc5b6aa967c74d7dc740 cd89c4b20edc581d4138187a9622f7bd cfb4fd57c7c8cc5b6aa967c70018187b cd89c4b20edc581d4138187a9622f7bd fpscr=00000000
+vcvta.s32.f64 s4, d20 171b3b91b3fbb6211a295f2ac14327be 2f20a3a46baebaf54fdee5192b2c9cb4 171b3b91b3fbb6211a295f2a7fffffff 2f20a3a46baebaf54fdee5192b2c9cb4 fpscr=00000000
+vcvta.s32.f64 s4, d20 d21d73de9c211adcc4f4c5ea644f61f2 9a5fd110df3af097f2f03941ce2ee7f8 d21d73de9c211adcc4f4c5ea80000000 9a5fd110df3af097f2f03941ce2ee7f8 fpscr=00000000
+vcvta.s32.f64 s4, d20 837659a9ef2557bceb079f39cf88db6e 146229542ea5d28fee16f568a2a6ab4d 837659a9ef2557bceb079f3980000000 146229542ea5d28fee16f568a2a6ab4d fpscr=00000000
+vcvta.s32.f64 s4, d20 ae6ef824bdf21c1462143ec1e22ea907 77b16956a59067b217b910cbbc9213f7 ae6ef824bdf21c1462143ec100000000 77b16956a59067b217b910cbbc9213f7 fpscr=00000000
+vcvta.s32.f64 s4, d20 850b037ea3640315e17bc88bb67ceea2 8eca746fdbe570f1efce7be8a2d90d0b 850b037ea3640315e17bc88b80000000 8eca746fdbe570f1efce7be8a2d90d0b fpscr=00000000
+vcvta.s32.f64 s4, d20 828d3dafd19d0e2b30a207eb2903afbd 3eeaa3c5b35b778e199afb86bef866f6 828d3dafd19d0e2b30a207eb00000000 3eeaa3c5b35b778e199afb86bef866f6 fpscr=00000000
+vcvta.s32.f64 s4, d20 24c5c12bb8f526c894672a6e7f4ad6b9 631bcf221bf3cf32a4fbaa952428693e 24c5c12bb8f526c894672a6e00000000 631bcf221bf3cf32a4fbaa952428693e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.s32.f64 s4, d20 f09b794cb579a8fbdb2425d52f4ab627 56d2aaa909e4d31782003b0d400aefe4 f09b794cb579a8fbdb2425d500000000 56d2aaa909e4d31782003b0d400aefe4 fpscr=00000000
+vcvta.s32.f64 s4, d20 b769e924dc25516f96cb08610bfc4cf9 388ffb1c875de32911f6d70704615273 b769e924dc25516f96cb086100000000 388ffb1c875de32911f6d70704615273 fpscr=00000000
+vcvta.s32.f64 s4, d20 5f6dab4e90fdf72adcdaabc6f59a7f5f dcaca5378c4a7eb59cc6179074ddace6 5f6dab4e90fdf72adcdaabc600000000 dcaca5378c4a7eb59cc6179074ddace6 fpscr=00000000
+vcvta.s32.f64 s4, d20 be6ae06d71b109b6f6de95e144dd5f7f 9722d086bd0af70e37eb04765a70d069 be6ae06d71b109b6f6de95e100000000 9722d086bd0af70e37eb04765a70d069 fpscr=00000000
+vcvta.s32.f64 s4, d20 baf014aaf9ef5664f800ecdd4bea2229 9947bee6eaac7a3a63b58b8118d36ebe baf014aaf9ef5664f800ecdd7fffffff 9947bee6eaac7a3a63b58b8118d36ebe fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.s32.f64 s4, d20 619ced510455f03d619ced510455f03d f20d776cf8687ef8d71e4f478460ad0c 619ced510455f03d619ced5180000000 f20d776cf8687ef8d71e4f478460ad0c fpscr=00000000
+vcvta.s32.f64 s4, d20 5b7d6ff8c000f56e634aafe05d4b00d2 058dbeebad612f19062fa4e24ffea655 5b7d6ff8c000f56e634aafe000000000 058dbeebad612f19062fa4e24ffea655 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.s32.f64 s4, d20 e8d1363988b23f92e8d1363988b23f92 e2e68223618ceae7879d828b35845036 e8d1363988b23f92e8d1363900000000 e2e68223618ceae7879d828b35845036 fpscr=00000000
+vcvta.s32.f64 s4, d20 0eb6dc33dfd83baf48a3492bdbedf443 1cea865a0545bfa056e2876c8cf451ea 0eb6dc33dfd83baf48a3492b7fffffff 1cea865a0545bfa056e2876c8cf451ea fpscr=00000000
+vcvta.s32.f64 s4, d20 4ef9dfb01617815bb2a9581fedecfdc9 3c472cbb306939fe01d533fe5723bc7c 4ef9dfb01617815bb2a9581f00000000 3c472cbb306939fe01d533fe5723bc7c fpscr=00000000
+vcvta.s32.f64 s4, d20 ae6977ce0d5cc9e3fd5586453d589e03 35d949c6562640d1aa1e809ab5f6bd9d ae6977ce0d5cc9e3fd55864500000000 35d949c6562640d1aa1e809ab5f6bd9d fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.s32.f64 s4, d20 915808e6214e4bcf915808e6214e4bcf 7732c7290947c970563f44a226556b6a 915808e6214e4bcf915808e67fffffff 7732c7290947c970563f44a226556b6a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.s32.f64 s7, d31 a653ab4b37ca6891205923a9b08339cf 3618806a53fbe71a3618806a53fbe71a 0000000137ca6891205923a9b08339cf 3618806a53fbe71a3618806a53fbe71a fpscr=00000000
+vcvtp.s32.f64 s7, d31 26215a20eee72442448ef9e9799dc444 043897ef95bbaff2e354519097ea5263 00000001eee72442448ef9e9799dc444 043897ef95bbaff2e354519097ea5263 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.s32.f64 s7, d31 3980cca2c41673721b022a50fda80026 2e85fc21492f2cfd2e85fc21492f2cfd 00000001c41673721b022a50fda80026 2e85fc21492f2cfd2e85fc21492f2cfd fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.s32.f64 s7, d31 0c5de3a056da2a8ff25dbfce97f0ed3d c4eb66b1a1ce7690a0a6a8c3f3ed0aa6 8000000056da2a8ff25dbfce97f0ed3d c4eb66b1a1ce7690a0a6a8c3f3ed0aa6 fpscr=00000000
+vcvtp.s32.f64 s7, d31 4babb6d9eb2698ee2e3bf321041ddec9 a0e01ebd96d2c2e285ec1d8f9740b6e6 00000000eb2698ee2e3bf321041ddec9 a0e01ebd96d2c2e285ec1d8f9740b6e6 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.s32.f64 s7, d31 355ea65def5cb330355ea65def5cb330 6c87415b461dcaa27ca96d5824949a17 7fffffffef5cb330355ea65def5cb330 6c87415b461dcaa27ca96d5824949a17 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.s32.f64 s7, d31 bc4adf05100e8356c26be03b925367d2 fea77cd8d46beb616fef5acb962f84ec 80000000100e8356c26be03b925367d2 fea77cd8d46beb616fef5acb962f84ec fpscr=00000000
+vcvtp.s32.f64 s7, d31 4f636797685cdc95a524b84477b454ca d598361c0afa5572577f100a608f54fd 80000000685cdc95a524b84477b454ca d598361c0afa5572577f100a608f54fd fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.s32.f64 s7, d31 f15163d389922914fb359964c45aef79 00946f7b3da3cc6c59c650d18eb879b0 0000000189922914fb359964c45aef79 00946f7b3da3cc6c59c650d18eb879b0 fpscr=00000000
+vcvtp.s32.f64 s7, d31 a58262703cac67c502f85982575c8679 619415e58328472200c38d7b3b9fca42 7fffffff3cac67c502f85982575c8679 619415e58328472200c38d7b3b9fca42 fpscr=00000000
+vcvtp.s32.f64 s7, d31 96be4eafce925f559044d111ba8d9f93 a6de44d23a4e73b992f8fb5b011d2502 00000000ce925f559044d111ba8d9f93 a6de44d23a4e73b992f8fb5b011d2502 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.s32.f64 s7, d31 676616262f94cad32c1e8d868a530e94 e897a10f1e4b8adc6e3426f706e77e21 800000002f94cad32c1e8d868a530e94 e897a10f1e4b8adc6e3426f706e77e21 fpscr=00000000
+vcvtp.s32.f64 s7, d31 268d7e3fd52f52cf82af98614bac951b cb35dc5af4b548c2b2019450a6b26aef 80000000d52f52cf82af98614bac951b cb35dc5af4b548c2b2019450a6b26aef fpscr=00000000
+vcvtp.s32.f64 s7, d31 f544ea690608309ea26fd05e4e6068f6 60a4cf27bc0be3590b050325a315c616 7fffffff0608309ea26fd05e4e6068f6 60a4cf27bc0be3590b050325a315c616 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.s32.f64 s7, d31 b199436cf278acf0b199436cf278acf0 3c041305b05caf3b914ec0a6379abf8b 00000001f278acf0b199436cf278acf0 3c041305b05caf3b914ec0a6379abf8b fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.s32.f64 s7, d31 fd7129aa777cb56cb5698b6716520cbc 7b6104c0e3d36c7f2bc347e566d538e6 7fffffff777cb56cb5698b6716520cbc 7b6104c0e3d36c7f2bc347e566d538e6 fpscr=00000000
+vcvtp.s32.f64 s7, d31 878882ad9d83ab446180bd58262403a0 6ced33cb0dbbb231d209da5de9fea43a 7fffffff9d83ab446180bd58262403a0 6ced33cb0dbbb231d209da5de9fea43a fpscr=00000000
+vcvtp.s32.f64 s7, d31 651c16288ad3f2c68402d4bca84c286b 2a6ab7fb0462cf1b525d9d2f6dcb8449 000000018ad3f2c68402d4bca84c286b 2a6ab7fb0462cf1b525d9d2f6dcb8449 fpscr=00000000
+vcvtp.s32.f64 s7, d31 87656390e733f36caa8814126a144302 ff03f4d66bc675f26d2dec9522b6b269 80000000e733f36caa8814126a144302 ff03f4d66bc675f26d2dec9522b6b269 fpscr=00000000
+vcvtp.s32.f64 s7, d31 a854c1f01cda8df16649b108c805caf0 c42f5523cb52be0e83d7cac3062eec1a 800000001cda8df16649b108c805caf0 c42f5523cb52be0e83d7cac3062eec1a fpscr=00000000
+vcvtp.s32.f64 s7, d31 442c8adf12e015986c45a531c0bf2f5c 9adc2ea71129bbb2d39396add17b174d 0000000012e015986c45a531c0bf2f5c 9adc2ea71129bbb2d39396add17b174d fpscr=00000000
+vcvtp.s32.f64 s7, d31 94bb7049510ec58ed3b8460455068daf 93ee75f0d6c8c7006134051578a6da93 00000000510ec58ed3b8460455068daf 93ee75f0d6c8c7006134051578a6da93 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.s32.f64 s7, d31 411415043b28b99e411415043b28b99e 48e6b61df06bac5a48e6b61df06bac5a 7fffffff3b28b99e411415043b28b99e 48e6b61df06bac5a48e6b61df06bac5a fpscr=00000000
+randV128: 4096 calls, 4223 iters
+vcvtp.s32.f64 s7, d31 967f65c91b16a8a969b1cb61da7e71b5 e7c4c7a46d07dc5f40d03261df6690fa 800000001b16a8a969b1cb61da7e71b5 e7c4c7a46d07dc5f40d03261df6690fa fpscr=00000000
+vcvtp.s32.f64 s7, d31 7c1726373050c19f52b96f7b73ef42ae 9d631e6fc8892ce27eddbf9606c395ef 000000003050c19f52b96f7b73ef42ae 9d631e6fc8892ce27eddbf9606c395ef fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.s32.f64 s7, d31 55f876e0fc51859d5d65e936a712fcb0 617acec489e8d1ec617acec489e8d1ec 7ffffffffc51859d5d65e936a712fcb0 617acec489e8d1ec617acec489e8d1ec fpscr=00000000
+vcvtp.s32.f64 s7, d31 f68cab6d89f1c0c5e73d556d441d76e3 c066e0274f6fc866a6beca9cc795cc9e ffffff4989f1c0c5e73d556d441d76e3 c066e0274f6fc866a6beca9cc795cc9e fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.s32.f64 s7, d31 1f01727fd742ecd81f01727fd742ecd8 d80df47204ebc7bd3d54b96896929f32 80000000d742ecd81f01727fd742ecd8 d80df47204ebc7bd3d54b96896929f32 fpscr=00000000
+vcvtp.s32.f64 s7, d31 4c2099c162bbffa12504e547ce25f73b 02e455c5e09e52215be56eeba3a12d37 0000000162bbffa12504e547ce25f73b 02e455c5e09e52215be56eeba3a12d37 fpscr=00000000
+vcvtp.s32.f64 s7, d31 9f407cbc74609d945f7f0c2cbbe65259 f871565aeafc7ccf23bd6b84cea94a13 8000000074609d945f7f0c2cbbe65259 f871565aeafc7ccf23bd6b84cea94a13 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.s32.f64 s7, d31 1b77c364165584854034fefa894a71eb 2487970eee16170a5a50300d30220294 00000001165584854034fefa894a71eb 2487970eee16170a5a50300d30220294 fpscr=00000000
+vcvtp.s32.f64 s7, d31 ab3333323e52e0e72cf9b4589dd45c0a 907ef51ee33603dd0eb0010b954c9b08 000000003e52e0e72cf9b4589dd45c0a 907ef51ee33603dd0eb0010b954c9b08 fpscr=00000000
+vcvtp.s32.f64 s7, d31 18a923cc928a375228c0a7283c2e412e e04f36988ec84590c87dc0e93470914b 80000000928a375228c0a7283c2e412e e04f36988ec84590c87dc0e93470914b fpscr=00000000
+vcvtp.s32.f64 s7, d31 adb8b2824b9fbe732afc769a6e5bc3d3 368f0e261d5c01ba8adc29948db9a120 000000014b9fbe732afc769a6e5bc3d3 368f0e261d5c01ba8adc29948db9a120 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.s32.f64 s7, d31 4787e447c8569ebe4787e447c8569ebe 53a35bb3b26c2450144c35c88e946419 7fffffffc8569ebe4787e447c8569ebe 53a35bb3b26c2450144c35c88e946419 fpscr=00000000
+vcvtp.s32.f64 s7, d31 86fcdf28d336895295f3204b72fe69c7 d098b6e53cf79a41b11fab67eab009f3 80000000d336895295f3204b72fe69c7 d098b6e53cf79a41b11fab67eab009f3 fpscr=00000000
+vcvtp.s32.f64 s7, d31 b27a3d6af2328f05cedadfe291e01576 16215038f908f7dfd056117b6df6ac32 00000001f2328f05cedadfe291e01576 16215038f908f7dfd056117b6df6ac32 fpscr=00000000
+vcvtp.s32.f64 s7, d31 51081381b366077935e688f4dcdea817 c5feab3e98b82e217c29ed39ee1fa1bf 80000000b366077935e688f4dcdea817 c5feab3e98b82e217c29ed39ee1fa1bf fpscr=00000000
+vcvtp.s32.f64 s7, d31 b3286f9c909d6a0312adb1c9b1f82bd5 f7d583ff357d91e101052081375a7955 80000000909d6a0312adb1c9b1f82bd5 f7d583ff357d91e101052081375a7955 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.s32.f64 s7, d31 144c96d42f319939144c96d42f319939 10c414766c4e4a148accfa19ca713169 000000012f319939144c96d42f319939 10c414766c4e4a148accfa19ca713169 fpscr=00000000
+vcvtp.s32.f64 s7, d31 4f0744bf28d86dd3514cb99e913e3df4 0d9a7b82517f7ac33cbc3f36025df432 0000000128d86dd3514cb99e913e3df4 0d9a7b82517f7ac33cbc3f36025df432 fpscr=00000000
+vcvtp.s32.f64 s7, d31 110327b0da64f42d2e7e0f60f156ec4c 83cf126fd07f45ffff6bb1187a23b79a 00000000da64f42d2e7e0f60f156ec4c 83cf126fd07f45ffff6bb1187a23b79a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.s32.f64 s7, d31 7228dc2e2cdd41047228dc2e2cdd4104 8c05c7de04bab4f179468d77be8aee0b 000000002cdd41047228dc2e2cdd4104 8c05c7de04bab4f179468d77be8aee0b fpscr=00000000
+vcvtp.s32.f64 s7, d31 1a56051d4f125bc05eafaac963df255e 93e28a3e4f6a7fbdecb10d723839d6f2 000000004f125bc05eafaac963df255e 93e28a3e4f6a7fbdecb10d723839d6f2 fpscr=00000000
+vcvtp.s32.f64 s7, d31 07cc42968f5c4e4e08fc0988f2f015c0 7c28ecc1314003b1d6b6a09d1ada01ad 7fffffff8f5c4e4e08fc0988f2f015c0 7c28ecc1314003b1d6b6a09d1ada01ad fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.s32.f64 s7, d31 9471028c104ec7414ae2446b7136403e b8110c713fdf4d59d2fb732b014a0adc 00000000104ec7414ae2446b7136403e b8110c713fdf4d59d2fb732b014a0adc fpscr=00000000
+vcvtp.s32.f64 s7, d31 c9125e5473ba0ab0859ddcc8403bd2e2 da5f74d267f672e0bbc960d47688d8d6 8000000073ba0ab0859ddcc8403bd2e2 da5f74d267f672e0bbc960d47688d8d6 fpscr=00000000
+vcvtp.s32.f64 s7, d31 68566e05471d2f9909b8b0c3c738fd08 a4784e7130e14a9d5e82698eb9cc5923 00000000471d2f9909b8b0c3c738fd08 a4784e7130e14a9d5e82698eb9cc5923 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.s32.f64 s7, d31 ce32cb2d126898c8b94c2d7f1c4d7d19 e4aa2cec61a32f771eee3e6d30a46ebb 80000000126898c8b94c2d7f1c4d7d19 e4aa2cec61a32f771eee3e6d30a46ebb fpscr=00000000
+vcvtp.s32.f64 s7, d31 e72ea1bcbb63c78a30cd2be5e5ecb54a 3a7d925f9216c2ba04e3d222340ffbc7 00000001bb63c78a30cd2be5e5ecb54a 3a7d925f9216c2ba04e3d222340ffbc7 fpscr=00000000
+vcvtm.s32.f64 s1, d0 1d92c1412bfc99e12726111c5108a45b 034104484033928fe107846a99731047 034104484033928f8000000099731047 034104484033928f8000000099731047 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.s32.f64 s1, d0 bac8bd9a2cd4c6361a86b6804999f94b 82fc2929ba1fdc46372c46bce2c56d11 82fc2929ba1fdc4600000000e2c56d11 82fc2929ba1fdc4600000000e2c56d11 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.s32.f64 s1, d0 606a225e77b607fdc88f4574b15c0e9d 64ef986763d8316319b43147fee2e680 64ef986763d8316300000000fee2e680 64ef986763d8316300000000fee2e680 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.s32.f64 s1, d0 b4078322ed417946d3dd04d1a973ea73 b6576ec32cd92b6eb2e5f1ea6c8e5285 b6576ec32cd92b6effffffff6c8e5285 b6576ec32cd92b6effffffff6c8e5285 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.s32.f64 s1, d0 e2548e5b96ae828baf2ab3d0fedbdfba cce882de3aeef708cce882de3aeef708 cce882de3aeef708800000003aeef708 cce882de3aeef708800000003aeef708 fpscr=00000000
+vcvtm.s32.f64 s1, d0 c19ae7f1e98861b3b3eaf3cc9f78b2b1 15bd22b41c0586f2a4e1e393fe12e2da 15bd22b41c0586f2fffffffffe12e2da 15bd22b41c0586f2fffffffffe12e2da fpscr=00000000
+vcvtm.s32.f64 s1, d0 ff1adba464bd8cc4415f3cf59e6829a8 b90f20256bc54eaa89567e7e131330d3 b90f20256bc54eaaffffffff131330d3 b90f20256bc54eaaffffffff131330d3 fpscr=00000000
+vcvtm.s32.f64 s1, d0 8c13863d8543d33dd28a88e375fab08c f63949bf19962cbd7c117dafda7d11db f63949bf19962cbd7fffffffda7d11db f63949bf19962cbd7fffffffda7d11db fpscr=00000000
+vcvtm.s32.f64 s1, d0 58a1eb972ced8dbf83bca0d7ea62bdad 71fb16e9c12e78aec88e6063a5800fa5 71fb16e9c12e78ae80000000a5800fa5 71fb16e9c12e78ae80000000a5800fa5 fpscr=00000000
+vcvtm.s32.f64 s1, d0 f1626aa5c88d8d6ed31ec859dae523d3 73aa5b9e304ce032d2a2548926d61df7 73aa5b9e304ce0328000000026d61df7 73aa5b9e304ce0328000000026d61df7 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.s32.f64 s1, d0 50c258c445d9dfe0ad36a0d26004176a 1e7e10873422d1728b093f2588744030 1e7e10873422d172ffffffff88744030 1e7e10873422d172ffffffff88744030 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.s32.f64 s1, d0 1392a24485998372daaf687a5dd1e47f 715ad6dd03c076fcd6a8372547d5218e 715ad6dd03c076fc8000000047d5218e 715ad6dd03c076fc8000000047d5218e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.s32.f64 s1, d0 c3a891f6bade890ca3abd2924a3a8965 19afb02ba1433daf19afb02ba1433daf 19afb02ba1433daf00000000a1433daf 19afb02ba1433daf00000000a1433daf fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.s32.f64 s1, d0 ec234511393f641359ea68b23c6149dd d9642bfb91844a8c7a8b35348692a2bf d9642bfb91844a8c7fffffff8692a2bf d9642bfb91844a8c7fffffff8692a2bf fpscr=00000000
+vcvtm.s32.f64 s1, d0 c8742673f74843d21010352299033ed4 4b1759a0ab4e2e4c556bdf315622b5c9 4b1759a0ab4e2e4c7fffffff5622b5c9 4b1759a0ab4e2e4c7fffffff5622b5c9 fpscr=00000000
+vcvtm.s32.f64 s1, d0 1edab9963b197ed634c0a3a0fc46ff99 af8583dc6f0b88a29e6dc2a362919c76 af8583dc6f0b88a2ffffffff62919c76 af8583dc6f0b88a2ffffffff62919c76 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.s32.f64 s1, d0 eb7115ffd06033abc6ca73becc4d926d c08cc57a2f0770e4c08cc57a2f0770e4 c08cc57a2f0770e4fffffc672f0770e4 c08cc57a2f0770e4fffffc672f0770e4 fpscr=00000000
+vcvtm.s32.f64 s1, d0 45f940d245de59bdec3c18a8198a49e6 3a4313a17b5f9e122efb975838cf5f43 3a4313a17b5f9e120000000038cf5f43 3a4313a17b5f9e120000000038cf5f43 fpscr=00000000
+vcvtm.s32.f64 s1, d0 7eeb476aa621b50e510ebbe1dce9d612 51b45789eb3489ede2e7eb44078c4756 51b45789eb3489ed80000000078c4756 51b45789eb3489ed80000000078c4756 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.s32.f64 s1, d0 0ea0e3d2cf59bb673cc55b9803b5f03c 7c0d227a20d9358cf85253a2ad8e0601 7c0d227a20d9358c80000000ad8e0601 7c0d227a20d9358c80000000ad8e0601 fpscr=00000000
+vcvtm.s32.f64 s1, d0 7dd2a23f344f2b866101dd66a3097f87 a21a27dc09c20e181eaf2c3301f8ac96 a21a27dc09c20e180000000001f8ac96 a21a27dc09c20e180000000001f8ac96 fpscr=00000000
+vcvtm.s32.f64 s1, d0 f31f89a39565ccf5b927a0ec65cb2553 e81010046b28475378ca6073e7fa7671 e81010046b2847537fffffffe7fa7671 e81010046b2847537fffffffe7fa7671 fpscr=00000000
+vcvtm.s32.f64 s1, d0 65713e4d8f5f6a2347fbb20c8508f9b3 8e51a10114353f62b15dcf0a42003d57 8e51a10114353f62ffffffff42003d57 8e51a10114353f62ffffffff42003d57 fpscr=00000000
+vcvtm.s32.f64 s1, d0 26f0e70407618731f546914a7ce82b95 5903ba41c4873c565990f18fe22ce8e2 5903ba41c4873c567fffffffe22ce8e2 5903ba41c4873c567fffffffe22ce8e2 fpscr=00000000
+vcvtm.s32.f64 s1, d0 9f5915d4582ae35193e8a5706c194dfc 2fe2c1b5fe94c60295eca0de84cf0311 2fe2c1b5fe94c602ffffffff84cf0311 2fe2c1b5fe94c602ffffffff84cf0311 fpscr=00000000
+vcvtm.s32.f64 s1, d0 bd4f579ca22d9d5fdb51a5b41447dc21 d122b24b267ccd8d97afd701d5fd7376 d122b24b267ccd8dffffffffd5fd7376 d122b24b267ccd8dffffffffd5fd7376 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.s32.f64 s1, d0 9916ff1338343f9d15c55a6691c60f8d 563e359285344e1f563e359285344e1f 563e359285344e1f7fffffff85344e1f 563e359285344e1f7fffffff85344e1f fpscr=00000000
+vcvtm.s32.f64 s1, d0 a427038b3c1fa2e859372112aae0d880 09127dc8b80053df38010b4b783d2107 09127dc8b80053df00000000783d2107 09127dc8b80053df00000000783d2107 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.s32.f64 s1, d0 8fe6b996a3ddfbec38eaf64a64c4584a 2599e47cedc77fce923e58d9bc13d938 2599e47cedc77fceffffffffbc13d938 2599e47cedc77fceffffffffbc13d938 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.s32.f64 s1, d0 b7c8ae468c049b06324f6e08fdd3f3a3 a78d5b1afc8797ff511ae441ce1609b4 a78d5b1afc8797ff7fffffffce1609b4 a78d5b1afc8797ff7fffffffce1609b4 fpscr=00000000
+vcvtm.s32.f64 s1, d0 184f60c97f7e409659bbb2b5256442e0 8129df1a84fd7a6b5ab30753d2d45378 8129df1a84fd7a6b7fffffffd2d45378 8129df1a84fd7a6b7fffffffd2d45378 fpscr=00000000
+vcvtm.s32.f64 s1, d0 80b7e4c2568d04d0eb50c38e9ff5fe83 bd38e23a062ab15a956dd3b76b3592cd bd38e23a062ab15affffffff6b3592cd bd38e23a062ab15affffffff6b3592cd fpscr=00000000
+vcvtm.s32.f64 s1, d0 f25d68866a252387b4ff0c4439e01eed f165851470546118b6034ef6ebf50052 f165851470546118ffffffffebf50052 f165851470546118ffffffffebf50052 fpscr=00000000
+vcvtm.s32.f64 s1, d0 78641c28ccc7042471fc157e12045a84 1f3e4cd2fdd9568bf4c66221f09417d0 1f3e4cd2fdd9568b80000000f09417d0 1f3e4cd2fdd9568b80000000f09417d0 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.s32.f64 s1, d0 a131801b769d9907a131801b769d9907 86de1769502951a966145979e000bedb 86de1769502951a97fffffffe000bedb 86de1769502951a97fffffffe000bedb fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.s32.f64 s1, d0 bc1ee4ec2b6735845dabba48eb4abcde 4544809bd5049acdc91b2b96e9dc7387 4544809bd5049acd80000000e9dc7387 4544809bd5049acd80000000e9dc7387 fpscr=00000000
+vcvtm.s32.f64 s1, d0 75441ce7590976fbdca8ebd58521de2c e946b819759bba74cda1f1a3cc3eed58 e946b819759bba7480000000cc3eed58 e946b819759bba7480000000cc3eed58 fpscr=00000000
+randV128: 4352 calls, 4482 iters
+vcvtm.s32.f64 s1, d0 512db92b40210de8d025c250584e6e43 dd9035c25444e5f965fbdc2f4572eb0e dd9035c25444e5f97fffffff4572eb0e dd9035c25444e5f97fffffff4572eb0e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.s32.f64 s1, d0 c19465b1b6f609fac19465b1b6f609fa ca8b039537dad3a4873050bd2c6291e7 ca8b039537dad3a4ffffffff2c6291e7 ca8b039537dad3a4ffffffff2c6291e7 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.s32.f64 s1, d0 3257401ee364704b880c4ba727a2bd83 3f20c5802168fd26494370e199a43e91 3f20c5802168fd267fffffff99a43e91 3f20c5802168fd267fffffff99a43e91 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.s32.f64 s1, d0 26cbfe7da08a4a1926cbfe7da08a4a19 ff01db84810106df88c949fde5744406 ff01db84810106dfffffffffe5744406 ff01db84810106dfffffffffe5744406 fpscr=00000000
+vcvtm.s32.f64 s1, d0 8d9446ab4d1f2020557e1e6dca618937 a68a785e23d1bab966054053f465e5ba a68a785e23d1bab97ffffffff465e5ba a68a785e23d1bab97ffffffff465e5ba fpscr=00000000
+vcvtm.s32.f64 s1, d0 7373365eac70081da3a454f34c11e46f b435723ec0e47ec33c8f78c9aac932a5 b435723ec0e47ec300000000aac932a5 b435723ec0e47ec300000000aac932a5 fpscr=00000000
+vcvtm.s32.f64 s1, d0 2f3db5a8d4545379af382ccd50108ded d711950d04d65e75261b48c3aa1d7496 d711950d04d65e7500000000aa1d7496 d711950d04d65e7500000000aa1d7496 fpscr=00000000
+vcvtm.s32.f64 s1, d0 590efed015c063af68e7efa6764d921b ed424ec4126bceddbb697ce25362fa82 ed424ec4126bceddffffffff5362fa82 ed424ec4126bceddffffffff5362fa82 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.s32.f64 s1, d0 412d553408f8b66c412d553408f8b66c f5a3ce1dbe451a4341aa156048b03a68 f5a3ce1dbe451a430d0ab02448b03a68 f5a3ce1dbe451a430d0ab02448b03a68 fpscr=00000000
+vcvtm.s32.f64 s1, d0 05d6dc0676276a84e2d6f56f430a3712 15e08537189cf9314e675a513fb73a0a 15e08537189cf9317fffffff3fb73a0a 15e08537189cf9317fffffff3fb73a0a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.s32.f64 s1, d0 c99f23f8ca8498c1a332418488d2a91f 287e1851aec1de64f39e2735143700c5 287e1851aec1de6480000000143700c5 287e1851aec1de6480000000143700c5 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.s32.f64 s1, d0 c17da8a3e85b1bcc874e0cf67c793006 ae0f9b872040e3f8ae0f9b872040e3f8 ae0f9b872040e3f8ffffffff2040e3f8 ae0f9b872040e3f8ffffffff2040e3f8 fpscr=00000000
+vcvtm.s32.f64 s1, d0 13851ba938320db269030efc174d4c0d 2fdc34116d0084a6e5a259edf816ae46 2fdc34116d0084a680000000f816ae46 2fdc34116d0084a680000000f816ae46 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtn.s32.f32 s27, s5 8defe539621f9f1863b0f900e8ed86f0 37a27e97159492d5836eb1d620b43465 00000000621f9f1863b0f900e8ed86f0 37a27e97159492d5836eb1d620b43465 fpscr=00000000
+vcvtn.s32.f32 s27, s5 be8f2f957eab9b1088813bdb40cb2a6d 97e3350e4683a435fe703a92b45cf7fe 800000007eab9b1088813bdb40cb2a6d 97e3350e4683a435fe703a92b45cf7fe fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.s32.f32 s27, s5 d1856c45aa21c423d1856c45636b0051 a07a0416110534706050381697d5314f 7fffffffaa21c423d1856c45636b0051 a07a0416110534706050381697d5314f fpscr=00000000
+vcvtn.s32.f32 s27, s5 ed0352190d614eac9d1262bd6104d799 73aacf702477dfd80f212e415fc8de29 000000000d614eac9d1262bd6104d799 73aacf702477dfd80f212e415fc8de29 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtn.s32.f32 s27, s5 4ff7c62025bba7d64ff7c620c2691f99 8dfe8e3ef40ade7ea41223a95aa7ba2e 0000000025bba7d64ff7c620c2691f99 8dfe8e3ef40ade7ea41223a95aa7ba2e fpscr=00000000
+vcvtn.s32.f32 s27, s5 697578b920499a626b38c5f2de39aead d92e89a3b8e6d8b8b1cfd058b6d175aa 0000000020499a626b38c5f2de39aead d92e89a3b8e6d8b8b1cfd058b6d175aa fpscr=00000000
+vcvtn.s32.f32 s27, s5 4aa5d5601df01425c229e32656aa0e77 5b8692565d16e774e132db275e739e92 800000001df01425c229e32656aa0e77 5b8692565d16e774e132db275e739e92 fpscr=00000000
+vcvtn.s32.f32 s27, s5 55298bfcda938aef240a6476516b6941 e5542363d2c4d3bcaca89c90e64279eb 00000000da938aef240a6476516b6941 e5542363d2c4d3bcaca89c90e64279eb fpscr=00000000
+vcvtn.s32.f32 s27, s5 77906503d54fa4f0e31f28b1dda5c88c f6834ff786930382c152e923a6458957 fffffff3d54fa4f0e31f28b1dda5c88c f6834ff786930382c152e923a6458957 fpscr=00000000
+vcvtn.s32.f32 s27, s5 4c8f2a073101f4bd53f13c45c5290f86 ae84865378255a3a2d2817b90a90b5eb 000000003101f4bd53f13c45c5290f86 ae84865378255a3a2d2817b90a90b5eb fpscr=00000000
+vcvtn.s32.f32 s27, s5 df17751b1e8c68e3ceacf8e530efb3db 948f2d2523fff4cb6e82d60bbc743f67 7fffffff1e8c68e3ceacf8e530efb3db 948f2d2523fff4cb6e82d60bbc743f67 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtn.s32.f32 s27, s5 d65aed259eef21551961711c1961711c 914983cd4a4f223b50d1c6e85cfcf2a6 7fffffff9eef21551961711c1961711c 914983cd4a4f223b50d1c6e85cfcf2a6 fpscr=00000000
+vcvtn.s32.f32 s27, s5 dc604538f3a5d50eae4aaab82e1d4dba 33e53f0e19e5139bbc1c19c5fcbcec44 00000000f3a5d50eae4aaab82e1d4dba 33e53f0e19e5139bbc1c19c5fcbcec44 fpscr=00000000
+vcvtn.s32.f32 s27, s5 af809995fe1e07cdc6b78e925deefe24 e1cecdf55d4fc4f8ae36ed2e2c177d7e 00000000fe1e07cdc6b78e925deefe24 e1cecdf55d4fc4f8ae36ed2e2c177d7e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtn.s32.f32 s27, s5 a12cc7a70a624855c30b4c57d5bb547c 4d175e8ad62b258961b330fd309bf0e7 7fffffff0a624855c30b4c57d5bb547c 4d175e8ad62b258961b330fd309bf0e7 fpscr=00000000
+vcvtn.s32.f32 s27, s5 7e7e75fe25881907ff662e72b0598a09 739deabf51c9d6e1573d5428e3ee2171 7fffffff25881907ff662e72b0598a09 739deabf51c9d6e1573d5428e3ee2171 fpscr=00000000
+vcvtn.s32.f32 s27, s5 857bea41da7a23f54935dfee86957a90 2a9ad69bed8e4c298655755214d73b25 00000000da7a23f54935dfee86957a90 2a9ad69bed8e4c298655755214d73b25 fpscr=00000000
+vcvtn.s32.f32 s27, s5 b96b8312ad507ea5710205b6b16154c1 c9d8aa9a01f5b5eca654339fbc3e0cca 00000000ad507ea5710205b6b16154c1 c9d8aa9a01f5b5eca654339fbc3e0cca fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtn.s32.f32 s27, s5 e479a85a42c3a142c7808c71a4f77c21 3ca32a6c6209e890155a670f7f4c7e82 0000000042c3a142c7808c71a4f77c21 3ca32a6c6209e890155a670f7f4c7e82 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtn.s32.f32 s27, s5 6558d80e32afa89d4ca3d225df5832eb ed483065ce874addc79917da277d4729 fffecdd032afa89d4ca3d225df5832eb ed483065ce874addc79917da277d4729 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtn.s32.f32 s27, s5 ab47c377c0c34d1057c40d2be958162f 55ea02bc317d348b9400c7b432ad7244 00000000c0c34d1057c40d2be958162f 55ea02bc317d348b9400c7b432ad7244 fpscr=00000000
+vcvtn.s32.f32 s27, s5 196f87bd46d3720dce53db27c186812d 43be33f113ccdf684510ab716e0fda57 0000090b46d3720dce53db27c186812d 43be33f113ccdf684510ab716e0fda57 fpscr=00000000
+vcvtn.s32.f32 s27, s5 5378d36352a359919d0f8c76969ccaa8 bb7a6503de1830b498dac4872dbf754f 0000000052a359919d0f8c76969ccaa8 bb7a6503de1830b498dac4872dbf754f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtn.s32.f32 s27, s5 6394e4f0e7ed500b950ed62118c45c8e f218d2eaf28a71cf9cd41cbbd2e55b73 00000000e7ed500b950ed62118c45c8e f218d2eaf28a71cf9cd41cbbd2e55b73 fpscr=00000000
+vcvtn.s32.f32 s27, s5 66a24d838d525fe591c62b172f3d4291 e285157623b99480841b7a216c155c53 000000008d525fe591c62b172f3d4291 e285157623b99480841b7a216c155c53 fpscr=00000000
+vcvtn.s32.f32 s27, s5 34fff44414e6701e344e104bb5d580d7 9585c82f6d13f1105d7396f6025c32a1 7fffffff14e6701e344e104bb5d580d7 9585c82f6d13f1105d7396f6025c32a1 fpscr=00000000
+vcvtn.s32.f32 s27, s5 0dfb6aab8d661840257fb00ac812d8a5 f35e71605afb8a6a409c1a9e2031d6db 000000058d661840257fb00ac812d8a5 f35e71605afb8a6a409c1a9e2031d6db fpscr=00000000
+vcvtn.s32.f32 s27, s5 55358ee18db6daaf7f6f1dacfa4d6d29 d09566d01f1082a2e52367df3b817081 800000008db6daaf7f6f1dacfa4d6d29 d09566d01f1082a2e52367df3b817081 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtn.s32.f32 s27, s5 20d317c63e936f033c4153216afb6668 4a79fe736e8a5cc46e8a5cc4155b3eef 7fffffff3e936f033c4153216afb6668 4a79fe736e8a5cc46e8a5cc4155b3eef fpscr=00000000
+vcvtn.s32.f32 s27, s5 2cdf27cc06f1fa28dc23c3674dd0df70 492d53fb65717c51e11a44aa4ce68fbe 8000000006f1fa28dc23c3674dd0df70 492d53fb65717c51e11a44aa4ce68fbe fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtn.s32.f32 s27, s5 4a85eff954eb2ae8815e5eda1240e213 925be8738cb7dccd8cb7dccdf9ce4f2e 0000000054eb2ae8815e5eda1240e213 925be8738cb7dccd8cb7dccdf9ce4f2e fpscr=00000000
+vcvtn.s32.f32 s27, s5 4770f6ff5ed0ac93c6f464602d4a2e66 5ba1073dc5aef06b864b4bc0c67794b8 000000005ed0ac93c6f464602d4a2e66 5ba1073dc5aef06b864b4bc0c67794b8 fpscr=00000000
+vcvtn.s32.f32 s27, s5 5a49aaaabe27f1349a256b97a393bc1e 4e75eb00cfebc10cd63588f1938166a8 80000000be27f1349a256b97a393bc1e 4e75eb00cfebc10cd63588f1938166a8 fpscr=00000000
+vcvtn.s32.f32 s27, s5 75bdd03dd53ba58a08fe20cd435be872 263dbed7bd3d504c8f6053a744003a4c 00000000d53ba58a08fe20cd435be872 263dbed7bd3d504c8f6053a744003a4c fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[1]
+vcvtn.s32.f32 s27, s5 6fe6dc798830978a494b091c83d5e2ac 25d60a1a48af0b4525d60a1a795f9d6d 000000008830978a494b091c83d5e2ac 25d60a1a48af0b4525d60a1a795f9d6d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[3]
+vcvtn.s32.f32 s27, s5 4a669ffb0113199ebeb6e36c0113199e 5bff3a5ef94a26d7c2fd81ab34c95d11 ffffff810113199ebeb6e36c0113199e 5bff3a5ef94a26d7c2fd81ab34c95d11 fpscr=00000000
+vcvtn.s32.f32 s27, s5 c133028e99ff75a04760f802b94e7dd8 188ff1fa57040f6286983ceed567477b 0000000099ff75a04760f802b94e7dd8 188ff1fa57040f6286983ceed567477b fpscr=00000000
+vcvtn.s32.f32 s27, s5 b010fb66bb06d6918e5589a89bf342fe 1ece11398920f53dd14382b3fec10f5b 80000000bb06d6918e5589a89bf342fe 1ece11398920f53dd14382b3fec10f5b fpscr=00000000
+vcvtn.s32.f32 s27, s5 3954f09d12fcdd50f88fa74650d29404 586fc755308670aba38da55435679452 0000000012fcdd50f88fa74650d29404 586fc755308670aba38da55435679452 fpscr=00000000
+vcvtn.s32.f32 s27, s5 d124a0f261ea0e75eeea820bd9acd48d 0d86707495814c3c67cf4a374436e39f 7fffffff61ea0e75eeea820bd9acd48d 0d86707495814c3c67cf4a374436e39f fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtn.s32.f32 s27, s5 798d7f3be014fc2e98b0141ca3bb4975 32cec9c8d26d836b573bfae3a40a7f3e 7fffffffe014fc2e98b0141ca3bb4975 32cec9c8d26d836b573bfae3a40a7f3e fpscr=00000000
+vcvtn.s32.f32 s27, s5 aac796ef1f9eb884539df542c7163e87 0fd302fdd97688ab4e205a724c287dfd 28169c801f9eb884539df542c7163e87 0fd302fdd97688ab4e205a724c287dfd fpscr=00000000
+vcvtn.s32.f32 s27, s5 0ce6254ff2afd37a3a1753a87c696f8f f7687e7bc4e17ff61597bd7bf8a483f5 00000000f2afd37a3a1753a87c696f8f f7687e7bc4e17ff61597bd7bf8a483f5 fpscr=00000000
+vcvtn.s32.f32 s27, s5 2c99cb76774a271c39a9da18c5abb39f ee97411ab5f00b0ef62d114a6e579381 80000000774a271c39a9da18c5abb39f ee97411ab5f00b0ef62d114a6e579381 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtn.s32.f32 s27, s5 95fd52358391782c95fd523585075d75 638ccd747cab3007e1b008fdf0c1ebb2 800000008391782c95fd523585075d75 638ccd747cab3007e1b008fdf0c1ebb2 fpscr=00000000
+vcvtn.s32.f32 s27, s5 534e255948e6b840c65f5b41acf04231 9099b35166958d37327009ce79ea3bcc 0000000048e6b840c65f5b41acf04231 9099b35166958d37327009ce79ea3bcc fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtn.s32.f32 s27, s5 5838e180949d48f628aedfc5fe18d685 15f56df902dd901fb2ff738b634f69d2 00000000949d48f628aedfc5fe18d685 15f56df902dd901fb2ff738b634f69d2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtn.s32.f32 s27, s5 d0efa931702f5bdf9be7e3b87ac3f143 414f8d605d54fc64c14b4b87f1942629 fffffff3702f5bdf9be7e3b87ac3f143 414f8d605d54fc64c14b4b87f1942629 fpscr=00000000
+vcvtn.s32.f32 s27, s5 f7b610a4733167b6dd410b0d52105b8c 0cd729b4cd7430494d01324c299fd8bb 081324c0733167b6dd410b0d52105b8c 0cd729b4cd7430494d01324c299fd8bb fpscr=00000000
+vcvtn.s32.f32 s27, s5 0790a8e28dbef40a3ec9b0984c790018 847186b6944e557008c61c0da136e737 000000008dbef40a3ec9b0984c790018 847186b6944e557008c61c0da136e737 fpscr=00000000
+vcvta.s32.f32 s4, s20 5c5c76d0fbca73f0aaeb9f39e9060974 174121ce178f63270aa45e8c05d0e6fa 5c5c76d0fbca73f0aaeb9f3900000000 174121ce178f63270aa45e8c05d0e6fa fpscr=00000000
+randV128: 4608 calls, 4743 iters
+vcvta.s32.f32 s4, s20 f36e7080d570680bdb667b54ad1b7112 5391642370c5500b8671dbee4f372267 f36e7080d570680bdb667b547fffffff 5391642370c5500b8671dbee4f372267 fpscr=00000000
+vcvta.s32.f32 s4, s20 482455c8ec3194cc7454b8f5b278cc69 8915ec12e996b7a8b53c4765952bc912 482455c8ec3194cc7454b8f500000000 8915ec12e996b7a8b53c4765952bc912 fpscr=00000000
+vcvta.s32.f32 s4, s20 96bc76513aec2361df827ad6024d37e9 469029844994204006395a5e2758111d 96bc76513aec2361df827ad600000000 469029844994204006395a5e2758111d fpscr=00000000
+vcvta.s32.f32 s4, s20 57fe85c5766c4da4136904710ae2f6a2 ef17ac0d40094ffaae71623a330ee6e3 57fe85c5766c4da41369047100000000 ef17ac0d40094ffaae71623a330ee6e3 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvta.s32.f32 s4, s20 fccf5413913533dc35ce69fa198e13e0 9906c22ed6ed7a25d5c53b37ce5c035d fccf5413913533dc35ce69fac8ff28c0 9906c22ed6ed7a25d5c53b37ce5c035d fpscr=00000000
+vcvta.s32.f32 s4, s20 e793a53cadc6e8e12ea127ae4e2adaa3 d191bffa187e033fafd770bd042d6754 e793a53cadc6e8e12ea127ae00000000 d191bffa187e033fafd770bd042d6754 fpscr=00000000
+vcvta.s32.f32 s4, s20 9db18b84cf07069af5faffd3dc708a41 b91fb0a7b8b8aa31f5391c7b9801c8aa 9db18b84cf07069af5faffd300000000 b91fb0a7b8b8aa31f5391c7b9801c8aa fpscr=00000000
+vcvta.s32.f32 s4, s20 1bb1602ac83fc47c994f04c9ab76ad38 dca2ba4e92c67958665b63dddc79f4a5 1bb1602ac83fc47c994f04c980000000 dca2ba4e92c67958665b63dddc79f4a5 fpscr=00000000
+vcvta.s32.f32 s4, s20 9e6a1dcf840b3ee10bf05f63a74dfeab 057b6dcd539e4b5db09fddc3bcd9c95d 9e6a1dcf840b3ee10bf05f6300000000 057b6dcd539e4b5db09fddc3bcd9c95d fpscr=00000000
+vcvta.s32.f32 s4, s20 ca4dd6b095e64d766ee225cdf409bd48 a343637f0de8b7e0e740691ff9793234 ca4dd6b095e64d766ee225cd80000000 a343637f0de8b7e0e740691ff9793234 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvta.s32.f32 s4, s20 275970189de70be5080e04860dcd28fd 0b0babec63d1698964d6bd18a7137d87 275970189de70be5080e048600000000 0b0babec63d1698964d6bd18a7137d87 fpscr=00000000
+vcvta.s32.f32 s4, s20 c0a4009c3972b082a532af169bcf60be 95aafa8f4ac35acbcb978f24df02d341 c0a4009c3972b082a532af1680000000 95aafa8f4ac35acbcb978f24df02d341 fpscr=00000000
+vcvta.s32.f32 s4, s20 0179c920e62813192acf852e8083e4f4 e249856f18eaab2fc6590813e8f90e4c 0179c920e62813192acf852e80000000 e249856f18eaab2fc6590813e8f90e4c fpscr=00000000
+vcvta.s32.f32 s4, s20 b5ef157c83138d8d1a145d2913e5eaf1 20c1eb8e88cb58c9c5503b5e8e7f67c3 b5ef157c83138d8d1a145d2900000000 20c1eb8e88cb58c9c5503b5e8e7f67c3 fpscr=00000000
+vcvta.s32.f32 s4, s20 94573cec2a14e173e983eeccba463ead 81523a53a8740c92f5c9f8987b3b897b 94573cec2a14e173e983eecc7fffffff 81523a53a8740c92f5c9f8987b3b897b fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.s32.f32 s4, s20 92a74bbdf8b8dd93b95c105992a74bbd 93063e8af04b970992e57557c7500aa2 92a74bbdf8b8dd93b95c1059ffff2ff5 93063e8af04b970992e57557c7500aa2 fpscr=00000000
+vcvta.s32.f32 s4, s20 cdfd28a7b61e128521e4006e0c690728 31f0a2b05e400ab15e6107a7510733d8 cdfd28a7b61e128521e4006e7fffffff 31f0a2b05e400ab15e6107a7510733d8 fpscr=00000000
+vcvta.s32.f32 s4, s20 adfc8b61338e7bad66647e99dcaf2826 150465274fe2f558b0f5e7c95ff4f56a adfc8b61338e7bad66647e997fffffff 150465274fe2f558b0f5e7c95ff4f56a fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.s32.f32 s4, s20 a59af3305bcf5f40eb5aa8f911f7de37 205d4cc1623255ea8a3dfb33023e08ad a59af3305bcf5f40eb5aa8f900000000 205d4cc1623255ea8a3dfb33023e08ad fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvta.s32.f32 s4, s20 a0347b4fbe88d3d6a2166f8ab2e55541 5efa315a5efa315ab992ac602605c362 a0347b4fbe88d3d6a2166f8a00000000 5efa315a5efa315ab992ac602605c362 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvta.s32.f32 s4, s20 edb7d8dab09fff260a9a5b6fdf89d81f 7722926319b1a8dad25e2602fb4c1440 edb7d8dab09fff260a9a5b6f80000000 7722926319b1a8dad25e2602fb4c1440 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.s32.f32 s4, s20 cd60933f2db239eac4af87fdb1b74dca eef04722eef0472287bc00fa86d8bf2d cd60933f2db239eac4af87fd00000000 eef04722eef0472287bc00fa86d8bf2d fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvta.s32.f32 s4, s20 440ee0e3a82bbd3e9018b830a49d2822 bdbe8058475439b0477bde7111cff665 440ee0e3a82bbd3e9018b83000000000 bdbe8058475439b0477bde7111cff665 fpscr=00000000
+vcvta.s32.f32 s4, s20 d13c19bdbe31f022521f2d293176a280 2054fa535581401161dcfc3c19ccd801 d13c19bdbe31f022521f2d2900000000 2054fa535581401161dcfc3c19ccd801 fpscr=00000000
+vcvta.s32.f32 s4, s20 a5dc15f2e87bdabd283a5da18e531ea4 e6ba1df7626f90713f56923d25826127 a5dc15f2e87bdabd283a5da100000000 e6ba1df7626f90713f56923d25826127 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.s32.f32 s4, s20 ab5675189a3116b715ae73d702b9eb6a 01c67cc3397491a3e3f9d3fe397491a3 ab5675189a3116b715ae73d700000000 01c67cc3397491a3e3f9d3fe397491a3 fpscr=00000000
+vcvta.s32.f32 s4, s20 5b24391ea2d7b6bb86f70bb96522b8b5 cd9e255ede913f81b025071460348351 5b24391ea2d7b6bb86f70bb97fffffff cd9e255ede913f81b025071460348351 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.s32.f32 s4, s20 ca22d7dce7e007199a840370bbeb5952 eb5ed66dd81777d6d81777d6ec41bba0 ca22d7dce7e007199a84037080000000 eb5ed66dd81777d6d81777d6ec41bba0 fpscr=00000000
+vcvta.s32.f32 s4, s20 250f7a5c40cc86a0ec62034d3e63ec93 96d5bf9f796dc312173c22f3640d570e 250f7a5c40cc86a0ec62034d7fffffff 96d5bf9f796dc312173c22f3640d570e fpscr=00000000
+vcvta.s32.f32 s4, s20 a53dd659cffb2dca5520c7ddef150d4b 5635ec203e4c4f111526dd638e52b239 a53dd659cffb2dca5520c7dd00000000 5635ec203e4c4f111526dd638e52b239 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.s32.f32 s4, s20 0e0666c73e5eedb9338ebce43e5eedb9 db34d8545cd1f1b54cf6f9d63ff5568b 0e0666c73e5eedb9338ebce400000002 db34d8545cd1f1b54cf6f9d63ff5568b fpscr=00000000
+vcvta.s32.f32 s4, s20 6d0974a7d270ae1cfc565ea2d0fedaf6 bfc596f59de8d0c00a6c9ce7a6af1016 6d0974a7d270ae1cfc565ea200000000 bfc596f59de8d0c00a6c9ce7a6af1016 fpscr=00000000
+vcvta.s32.f32 s4, s20 c9009bcabd05fc28a0c09946da76c8fe d3a28f811fa2440f3d221b5749ac776f c9009bcabd05fc28a0c0994600158eee d3a28f811fa2440f3d221b5749ac776f fpscr=00000000
+vcvta.s32.f32 s4, s20 5d14f6bbf578b58c784f47a909e61e1a 0a8faefafddc16c26b5d157c2c0fe29d 5d14f6bbf578b58c784f47a900000000 0a8faefafddc16c26b5d157c2c0fe29d fpscr=00000000
+vcvta.s32.f32 s4, s20 53c2515d78c59ea29f258e2eaa2d8125 b68432e5822a5de93ef28fdbf220a666 53c2515d78c59ea29f258e2e80000000 b68432e5822a5de93ef28fdbf220a666 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvta.s32.f32 s4, s20 949f9e0cf94535b087b23896949f9e0c 1c1070c5d727b8efd4c715b22003a5e7 949f9e0cf94535b087b2389600000000 1c1070c5d727b8efd4c715b22003a5e7 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.s32.f32 s4, s20 26919b8dd20e99610462e3ca28e76c3c a9ef1002e53f7009f2bb8c14d1722306 26919b8dd20e99610462e3ca80000000 a9ef1002e53f7009f2bb8c14d1722306 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.s32.f32 s4, s20 d488c40d08643462eed16f640f4b78d1 f179b83d558cf1bacac8543258b60d95 d488c40d08643462eed16f647fffffff f179b83d558cf1bacac8543258b60d95 fpscr=00000000
+vcvta.s32.f32 s4, s20 c988ac89952710599e3396a40b79bfc4 cd9aaacd18293a3ec7ec28f84686e184 c988ac89952710599e3396a400004371 cd9aaacd18293a3ec7ec28f84686e184 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.s32.f32 s4, s20 35b517a535b517a59baea6a5e0f39279 ac4e49f2afc259e9aa51ac948dd6a8bb 35b517a535b517a59baea6a500000000 ac4e49f2afc259e9aa51ac948dd6a8bb fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.s32.f32 s4, s20 20bc8ac9e094a5a76147623df2228787 b06b7e104a31d0169704045449d5371c 20bc8ac9e094a5a76147623d001aa6e4 b06b7e104a31d0169704045449d5371c fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvta.s32.f32 s4, s20 1b4db7163b1ba2cffe6239561b4db716 49633be1b0a68ab8ebe2b71800ea7330 1b4db7163b1ba2cffe62395600000000 49633be1b0a68ab8ebe2b71800ea7330 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvta.s32.f32 s4, s20 3b872c4ccb889635fde561b7067e4efb 990c1aa8990c1aa8c6325fe95c6000b0 3b872c4ccb889635fde561b77fffffff 990c1aa8990c1aa8c6325fe95c6000b0 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.s32.f32 s4, s20 b4bed5ea1342e5e706001c50a67afba3 e71f9da7249848ff967f868767b67332 b4bed5ea1342e5e706001c507fffffff e71f9da7249848ff967f868767b67332 fpscr=00000000
+vcvta.s32.f32 s4, s20 b481eb16866ff7701fd521c3c6f39cd9 a1812fdbfa03379b4b09df3cc2e2ab3f b481eb16866ff7701fd521c3ffffff8f a1812fdbfa03379b4b09df3cc2e2ab3f fpscr=00000000
+vcvta.s32.f32 s4, s20 946494b472c9270f0e6994d31f21baae 8c54617b0da72fbb1d5a8c0d99f4ea4a 946494b472c9270f0e6994d300000000 8c54617b0da72fbb1d5a8c0d99f4ea4a fpscr=00000000
+vcvta.s32.f32 s4, s20 b39fdd1d388cd2bbfd7758cbd49e4667 0fb29b763b49af9d854b6cfbe8e9459f b39fdd1d388cd2bbfd7758cb80000000 0fb29b763b49af9d854b6cfbe8e9459f fpscr=00000000
+vcvta.s32.f32 s4, s20 3e63396d9339c145b2d5eaebe951c5b1 b29f94ab1b8192fe9d6ffd5243bb6b58 3e63396d9339c145b2d5eaeb00000177 b29f94ab1b8192fe9d6ffd5243bb6b58 fpscr=00000000
+vcvta.s32.f32 s4, s20 580d3280b9c53945f29a568865465c47 3b57a404fa3b5ac507a8874e91282bfa 580d3280b9c53945f29a568800000000 3b57a404fa3b5ac507a8874e91282bfa fpscr=00000000
+vcvtp.s32.f32 s7, s31 d418f60c8130ea0fbb4a01e533a1fdc6 79a2a4459feaaba232b6fb3eb5875bc8 7fffffff8130ea0fbb4a01e533a1fdc6 79a2a4459feaaba232b6fb3eb5875bc8 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.s32.f32 s7, s31 7f35889a0ce9b3eb8c80df424b95386f 913498ddf2c13f055dce1ecae7e22e1e 000000000ce9b3eb8c80df424b95386f 913498ddf2c13f055dce1ecae7e22e1e fpscr=00000000
+vcvtp.s32.f32 s7, s31 1e330ad2f354134f8560973fad66dcbd f7475480bb8fe360621345406bb0ceb1 80000000f354134f8560973fad66dcbd f7475480bb8fe360621345406bb0ceb1 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[0]
+vcvtp.s32.f32 s7, s31 61212ddceb66fdfe9a89f6b4b43707fd 727013547dbcc13f7dbcc13f5b53c37d 7fffffffeb66fdfe9a89f6b4b43707fd 727013547dbcc13f7dbcc13f5b53c37d fpscr=00000000
+vcvtp.s32.f32 s7, s31 e8e83a3b601c9d2dc2781e402b26d7e1 c49fb86cb91a634d64308a1d98dbd35d fffffb03601c9d2dc2781e402b26d7e1 c49fb86cb91a634d64308a1d98dbd35d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtp.s32.f32 s7, s31 84ebbbd1a76151651bad81a1b33264c1 fbaa6128cd5c0c211c6452cc3038fc33 80000000a76151651bad81a1b33264c1 fbaa6128cd5c0c211c6452cc3038fc33 fpscr=00000000
+vcvtp.s32.f32 s7, s31 663668c9760b966737f5f2aa583765d8 25dd861476667adaa677fb5cc8c0ff73 00000001760b966737f5f2aa583765d8 25dd861476667adaa677fb5cc8c0ff73 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtp.s32.f32 s7, s31 27c229a4fad79f52c623f3aab247a822 6e406f276a5b45818df5868cc83db081 7ffffffffad79f52c623f3aab247a822 6e406f276a5b45818df5868cc83db081 fpscr=00000000
+vcvtp.s32.f32 s7, s31 a028594ba9f537c565c76a72bff6034f 9bf23182fbae2116aa27392c568d5768 00000000a9f537c565c76a72bff6034f 9bf23182fbae2116aa27392c568d5768 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtp.s32.f32 s7, s31 1a349fc3f626ad2db527d069b527d069 42c6538bb254ba5c052fc606f46c5dc4 00000064f626ad2db527d069b527d069 42c6538bb254ba5c052fc606f46c5dc4 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtp.s32.f32 s7, s31 23e8e0f247ee06857cb46d2117b58540 8190aec1a50ce4028190aec1ee6a8eda 0000000047ee06857cb46d2117b58540 8190aec1a50ce4028190aec1ee6a8eda fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.s32.f32 s7, s31 1c4d14b50a771bac5a9c513632a9deb2 e32a061c9bf76af327b5c9be9bf76af3 800000000a771bac5a9c513632a9deb2 e32a061c9bf76af327b5c9be9bf76af3 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtp.s32.f32 s7, s31 34081150aeb033810d9b76e834081150 dd6a4c029b76fe83c7cb9e73c7c4296f 80000000aeb033810d9b76e834081150 dd6a4c029b76fe83c7cb9e73c7c4296f fpscr=00000000
+vcvtp.s32.f32 s7, s31 6620e4cadfd5e2d6b7e9c62144ea349e 1af21a7172a2c21f85d61625289d8472 00000001dfd5e2d6b7e9c62144ea349e 1af21a7172a2c21f85d61625289d8472 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtp.s32.f32 s7, s31 8117f7e2bbae32b4d47d14d04ea3fa95 3f3b7e62b18652dc0f4831bfb18652dc 00000001bbae32b4d47d14d04ea3fa95 3f3b7e62b18652dc0f4831bfb18652dc fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[2]
+randV128: 4864 calls, 5008 iters
+vcvtp.s32.f32 s7, s31 c180651287de57b7e391a534392ee066 8fe0143cf1398f91903333688fe0143c 0000000087de57b7e391a534392ee066 8fe0143cf1398f91903333688fe0143c fpscr=00000000
+vcvtp.s32.f32 s7, s31 c3f5768101e25e7c075155b408f3ffc5 33012022bed81664d12fcafd6c2a52f0 0000000101e25e7c075155b408f3ffc5 33012022bed81664d12fcafd6c2a52f0 fpscr=00000000
+vcvtp.s32.f32 s7, s31 c7ea39a6f1058fc392d88e187084349b 45927bef98a25b9193a13efa024bcd4c 00001250f1058fc392d88e187084349b 45927bef98a25b9193a13efa024bcd4c fpscr=00000000
+vcvtp.s32.f32 s7, s31 e3eb2253f2b74d699fc494b37557ac2d c2c88b8f849a5bf75c3a9ca4aeb2c5b7 ffffff9cf2b74d699fc494b37557ac2d c2c88b8f849a5bf75c3a9ca4aeb2c5b7 fpscr=00000000
+vcvtp.s32.f32 s7, s31 ed0d7978d583608089180ad1ab9164b3 579a578041bcb95af708a8e2dca9443b 7fffffffd583608089180ad1ab9164b3 579a578041bcb95af708a8e2dca9443b fpscr=00000000
+vcvtp.s32.f32 s7, s31 cfb2353b3176207d01f5e6a86d6d503e b50a0226e23beec52a621925fcbac18e 000000003176207d01f5e6a86d6d503e b50a0226e23beec52a621925fcbac18e fpscr=00000000
+vcvtp.s32.f32 s7, s31 9207dc958c47746d5d5f8e3349a1942b 0dadd927df37f7086dbdde07db9c0bcf 000000018c47746d5d5f8e3349a1942b 0dadd927df37f7086dbdde07db9c0bcf fpscr=00000000
+vcvtp.s32.f32 s7, s31 48ef3a426ed9ac8ec061d6665228a2fb e321b3ad8e46551bfe54cac756ff8627 800000006ed9ac8ec061d6665228a2fb e321b3ad8e46551bfe54cac756ff8627 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.s32.f32 s7, s31 e347051b472645434b633d864b633d86 28374355bc80f9e076535abb95a8723f 00000001472645434b633d864b633d86 28374355bc80f9e076535abb95a8723f fpscr=00000000
+vcvtp.s32.f32 s7, s31 b09cd98d57c847808169790fcf56b5a2 122b5ab8970713b47a86104a4230d1ed 0000000157c847808169790fcf56b5a2 122b5ab8970713b47a86104a4230d1ed fpscr=00000000
+vcvtp.s32.f32 s7, s31 2554bce311db033be9100c927a00be0b 7d986949e3254dcf5c0bf96de943893f 7fffffff11db033be9100c927a00be0b 7d986949e3254dcf5c0bf96de943893f fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtp.s32.f32 s7, s31 95c29e7b124208b1ac909b48d73812db a3e71e8328f691afa3e71e83d723585e 00000000124208b1ac909b48d73812db a3e71e8328f691afa3e71e83d723585e fpscr=00000000
+vcvtp.s32.f32 s7, s31 94692f8d68575d1e49a7d7fbb1c36119 6c282ff2472f166f912b56e41c6a1b50 7fffffff68575d1e49a7d7fbb1c36119 6c282ff2472f166f912b56e41c6a1b50 fpscr=00000000
+vcvtp.s32.f32 s7, s31 2156406bea0a2cda814b30859d776642 a1fa7b711111ab50f48380b3cfd74f3a 00000000ea0a2cda814b30859d776642 a1fa7b711111ab50f48380b3cfd74f3a fpscr=00000000
+vcvtp.s32.f32 s7, s31 aae9d412ba5bc1342eea572dea38540a 5b61d3288b61fe267075161ef5373cff 7fffffffba5bc1342eea572dea38540a 5b61d3288b61fe267075161ef5373cff fpscr=00000000
+vcvtp.s32.f32 s7, s31 13a18bdbee5d696f704d562896a911cd 7f339dbaa890e972147c66c83116d7d2 7fffffffee5d696f704d562896a911cd 7f339dbaa890e972147c66c83116d7d2 fpscr=00000000
+vcvtp.s32.f32 s7, s31 0e6b4354f477883693a9326e1eab93b6 37746cb7b35458afb9ccfba01ef6a50d 00000001f477883693a9326e1eab93b6 37746cb7b35458afb9ccfba01ef6a50d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.s32.f32 s7, s31 2b0243cabed66376e539d48afb0b8e7d 194687c2ab7779afab7779af2ab7fe6c 00000001bed66376e539d48afb0b8e7d 194687c2ab7779afab7779af2ab7fe6c fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtp.s32.f32 s7, s31 e7ac39c3a3fd57cba3fd57cbf2f632dc 07c1dfb6a1ae7a9557a34a4f5cfab63b 00000001a3fd57cba3fd57cbf2f632dc 07c1dfb6a1ae7a9557a34a4f5cfab63b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.s32.f32 s7, s31 c710b81fd883389f2faa24fc5b6006f0 92fdf21229fb44e8d62638d418907031 00000000d883389f2faa24fc5b6006f0 92fdf21229fb44e8d62638d418907031 fpscr=00000000
+vcvtp.s32.f32 s7, s31 2b8fb7baec5947f3c6b6db5ad72b8261 1f89d40d6c9fee66824c1b6a19c2790c 00000001ec5947f3c6b6db5ad72b8261 1f89d40d6c9fee66824c1b6a19c2790c fpscr=00000000
+vcvtp.s32.f32 s7, s31 f4dd009a9edf1ba099667358d70a866c 730ce15eeefab1fd59d3e25225e50ac1 7fffffff9edf1ba099667358d70a866c 730ce15eeefab1fd59d3e25225e50ac1 fpscr=00000000
+vcvtp.s32.f32 s7, s31 a71df7e473d1a5e85f89e32776f794fa 10fdbf1cdab0778afdf200c940eff32a 0000000173d1a5e85f89e32776f794fa 10fdbf1cdab0778afdf200c940eff32a fpscr=00000000
+vcvtp.s32.f32 s7, s31 d27ed00a74b6ec7f1db4daff4eeceeb1 6564d8aae18e694b8838953fad4f214f 7fffffff74b6ec7f1db4daff4eeceeb1 6564d8aae18e694b8838953fad4f214f fpscr=00000000
+vcvtp.s32.f32 s7, s31 f273717d5de5230b2a358068d3e6813e 9bf46e15874d94225e420f92dc849a5d 000000005de5230b2a358068d3e6813e 9bf46e15874d94225e420f92dc849a5d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtp.s32.f32 s7, s31 74e7c36ebc560d9470880241aaf99200 3b8458e9e8f814cf1b752520e8f814cf 00000001bc560d9470880241aaf99200 3b8458e9e8f814cf1b752520e8f814cf fpscr=00000000
+vcvtp.s32.f32 s7, s31 83dd8fd5e3f7e8da533f8b2b0425ecc5 9c93356f12d6ed6cb51ed39d25b481bd 00000000e3f7e8da533f8b2b0425ecc5 9c93356f12d6ed6cb51ed39d25b481bd fpscr=00000000
+vcvtp.s32.f32 s7, s31 a01a053f2aa0e9b4ae7ec0d6ec313f51 49d8afa78f206dbbc4cc6eda9734d1c4 001b15f52aa0e9b4ae7ec0d6ec313f51 49d8afa78f206dbbc4cc6eda9734d1c4 fpscr=00000000
+vcvtp.s32.f32 s7, s31 ae3bbaa854c98c645d1732e2d2ec0a6f b3a800f8ab74aa1f3ac8c084e40bd01f 0000000054c98c645d1732e2d2ec0a6f b3a800f8ab74aa1f3ac8c084e40bd01f fpscr=00000000
+vcvtp.s32.f32 s7, s31 58989ace205e406f69421d6e6fe597c3 9ffcfe4f1196ac0a5b68093a16f30889 00000000205e406f69421d6e6fe597c3 9ffcfe4f1196ac0a5b68093a16f30889 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.s32.f32 s7, s31 02242bdae919b72de919b72d208658d1 8e96ca440934cdcd3a406add9a74e8e3 00000000e919b72de919b72d208658d1 8e96ca440934cdcd3a406add9a74e8e3 fpscr=00000000
+vcvtp.s32.f32 s7, s31 a296e624de70d6dd54f5c97099ddb3d4 704d0beee0f3429353f606f1bf6a75b9 7fffffffde70d6dd54f5c97099ddb3d4 704d0beee0f3429353f606f1bf6a75b9 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtp.s32.f32 s7, s31 d9fe44b07e9570fe1f3718881f371888 b160bdf1e85671efff54398158e136fc 000000007e9570fe1f3718881f371888 b160bdf1e85671efff54398158e136fc fpscr=00000000
+vcvtp.s32.f32 s7, s31 c184e05f8c003607ede7ddfd6ac4e3a6 ed762249783ec6ca0e83bc63120390d6 800000008c003607ede7ddfd6ac4e3a6 ed762249783ec6ca0e83bc63120390d6 fpscr=00000000
+vcvtp.s32.f32 s7, s31 b9ef4a3af20c9ee12080178a060ee5f5 78fb2125ed8a24f53fb0146ff7cdbe9d 7ffffffff20c9ee12080178a060ee5f5 78fb2125ed8a24f53fb0146ff7cdbe9d fpscr=00000000
+vcvtm.s32.f32 s1, s0 9457fd43d7383f63d4b0978b102d4d77 bb299941d772be21eb68ba33e6158841 bb299941d772be2180000000e6158841 bb299941d772be2180000000e6158841 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.s32.f32 s1, s0 ce009f8d3967e422bc491433c84f293d 11471dd6ebf491e011471dd6c76fc263 11471dd6ebf491e0ffff103dc76fc263 11471dd6ebf491e0ffff103dc76fc263 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtm.s32.f32 s1, s0 dd1ca2613a5de9fb3a5de9fb1bcdb204 175dbc7b753aac882d29404cf0aab414 175dbc7b753aac8880000000f0aab414 175dbc7b753aac8880000000f0aab414 fpscr=00000000
+vcvtm.s32.f32 s1, s0 9bf7eacf3a99919de79979ab1bdab97f f03622b304980837f1056ecbf3421930 f03622b30498083780000000f3421930 f03622b30498083780000000f3421930 fpscr=00000000
+vcvtm.s32.f32 s1, s0 c50b1e291095d5d4b5a7c57e054f3c4c da7c1def7d935852f8298809c57fe670 da7c1def7d935852fffff001c57fe670 da7c1def7d935852fffff001c57fe670 fpscr=00000000
+vcvtm.s32.f32 s1, s0 0af4d6ff13f47811696c35488e11d9a0 03048499afbb33cb2cea7ab3d082ac0f 03048499afbb33cb80000000d082ac0f 03048499afbb33cb80000000d082ac0f fpscr=00000000
+vcvtm.s32.f32 s1, s0 20a7e64a66a71a3b1fec617ad6e3fb99 3d865449752b7baceb9b440c1b517e05 3d865449752b7bac000000001b517e05 3d865449752b7bac000000001b517e05 fpscr=00000000
+vcvtm.s32.f32 s1, s0 e5d7c1bedd6f4a709eceec73c748bb35 79510b96705567a34d3af385d9969075 79510b96705567a380000000d9969075 79510b96705567a380000000d9969075 fpscr=00000000
+vcvtm.s32.f32 s1, s0 8c76e66b86e3c6ad996719c5a7fd2ca5 877b9bb1c792113c8bcded22d0603065 877b9bb1c792113c80000000d0603065 877b9bb1c792113c80000000d0603065 fpscr=00000000
+vcvtm.s32.f32 s1, s0 70b775e4d49f9203d474792ecc3a81a2 cae50ad6a2488d92a8a589aba318ab73 cae50ad6a2488d92ffffffffa318ab73 cae50ad6a2488d92ffffffffa318ab73 fpscr=00000000
+vcvtm.s32.f32 s1, s0 19186216a0befd8b1944db086e3df36d 4b25e31435dccca39416297ec063bf3f 4b25e31435dccca3fffffffcc063bf3f 4b25e31435dccca3fffffffcc063bf3f fpscr=00000000
+vcvtm.s32.f32 s1, s0 2d9157222f1450834f265db0a7fc356e aa6cd67b91af8ed8d4e9e7213b4651d4 aa6cd67b91af8ed8000000003b4651d4 aa6cd67b91af8ed8000000003b4651d4 fpscr=00000000
+vcvtm.s32.f32 s1, s0 37e4f41862df5448bb7f9c4cddcff632 7d580d01039bfff848c72053876f3caf 7d580d01039bfff8ffffffff876f3caf 7d580d01039bfff8ffffffff876f3caf fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.s32.f32 s1, s0 cba9ad2b49c13f18628b95881c39a651 ec2d7d91b042a80eec2d7d9152cd78e4 ec2d7d91b042a80e7fffffff52cd78e4 ec2d7d91b042a80e7fffffff52cd78e4 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtm.s32.f32 s1, s0 8330a68d1f78eba85f0f7b34ddca15d0 5792d578824f1ebc12c83fb171c5e7fd 5792d578824f1ebc7fffffff71c5e7fd 5792d578824f1ebc7fffffff71c5e7fd fpscr=00000000
+vcvtm.s32.f32 s1, s0 a3a141a72eeefcf798da1ffec9d68a4e 507c0d67db4f2ea6a419124e1e8ab617 507c0d67db4f2ea6000000001e8ab617 507c0d67db4f2ea6000000001e8ab617 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtm.s32.f32 s1, s0 5ee937795cb6ffbaa88d9e6fd2ec55a9 75b5bf3adb8960df01d8d7ab75b5bf3a 75b5bf3adb8960df7fffffff75b5bf3a 75b5bf3adb8960df7fffffff75b5bf3a fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vcvtm.s32.f32 s1, s0 2ffb347fa72b6a633c832d7219068a1b 525e6ff7525e6ff7218a86172bf51194 525e6ff7525e6ff7000000002bf51194 525e6ff7525e6ff7000000002bf51194 fpscr=00000000
+vcvtm.s32.f32 s1, s0 0d8256b006ce896a639f13244988977e 65dc1f17a142da0873167bce1430b627 65dc1f17a142da08000000001430b627 65dc1f17a142da08000000001430b627 fpscr=00000000
+vcvtm.s32.f32 s1, s0 e6569c986f417eb936aa7a6d257f3720 8cb75b086725cde962dd6b74ef806e35 8cb75b086725cde980000000ef806e35 8cb75b086725cde980000000ef806e35 fpscr=00000000
+vcvtm.s32.f32 s1, s0 348c74fff83a2b2420bee202871eaa79 a0e9c86fb95c5721583491aff9916c56 a0e9c86fb95c572180000000f9916c56 a0e9c86fb95c572180000000f9916c56 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.s32.f32 s1, s0 3e3e8dab14356a0648c2b3e5ff5a62ea f818ac6f6ebf4ac7a936cf6b95ebcb48 f818ac6f6ebf4ac7ffffffff95ebcb48 f818ac6f6ebf4ac7ffffffff95ebcb48 fpscr=00000000
+vcvtm.s32.f32 s1, s0 2424c78028dc962ec440fbabfec7f998 536c855f7dc17f5f432f618d36160e6f 536c855f7dc17f5f0000000036160e6f 536c855f7dc17f5f0000000036160e6f fpscr=00000000
+vcvtm.s32.f32 s1, s0 d174465508b51579cc23778c02d27fed 84ac5df62ac7ec2de84aea391df77ff9 84ac5df62ac7ec2d000000001df77ff9 84ac5df62ac7ec2d000000001df77ff9 fpscr=00000000
+vcvtm.s32.f32 s1, s0 50659331cfdd2ed0c0e335deb700cc41 daf5df37dbe53d957df0c804d892443e daf5df37dbe53d9580000000d892443e daf5df37dbe53d9580000000d892443e fpscr=00000000
+vcvtm.s32.f32 s1, s0 78ed4f011a733b24f0a9058e2e0d0711 b6d7e9cf87f61e4564b9d8dbabc678c5 b6d7e9cf87f61e45ffffffffabc678c5 b6d7e9cf87f61e45ffffffffabc678c5 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[2]
+vcvtm.s32.f32 s1, s0 285c50c8de444cc9de444cc91337acef 9454bb5f0759d127c2da7a40be797f09 9454bb5f0759d127ffffffffbe797f09 9454bb5f0759d127ffffffffbe797f09 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtm.s32.f32 s1, s0 4e026915b21eb38ab3bddf19f7d58588 85be6f6c31ae2dd92a085a1706046cbb 85be6f6c31ae2dd90000000006046cbb 85be6f6c31ae2dd90000000006046cbb fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[0]
+vcvtm.s32.f32 s1, s0 4a9487dd956a6651dae4ef9de0a02c08 ecfd5554195fd216ecfd5554221d7195 ecfd5554195fd21600000000221d7195 ecfd5554195fd21600000000221d7195 fpscr=00000000
+randV128: 5120 calls, 5270 iters
+vcvtm.s32.f32 s1, s0 d752cbc22852cff27a0b25f740e44f74 823d85e85789c82c390a874daa721efc 823d85e85789c82cffffffffaa721efc 823d85e85789c82cffffffffaa721efc fpscr=00000000
+vcvtm.s32.f32 s1, s0 f8b3ae2a8302101bf8e63b694f76dbb9 1b16184dee8f7fbf8994bc891d65014d 1b16184dee8f7fbf000000001d65014d 1b16184dee8f7fbf000000001d65014d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtm.s32.f32 s1, s0 0812c23316395797fa5daebfa53f4036 1aa79a93e076c1d613247ba59f734db8 1aa79a93e076c1d6ffffffff9f734db8 1aa79a93e076c1d6ffffffff9f734db8 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtm.s32.f32 s1, s0 7bf808d9988cd1188adbae0fd5071cc1 e6a9f4c1d5b39a053683f447926c52dc e6a9f4c1d5b39a05ffffffff926c52dc e6a9f4c1d5b39a05ffffffff926c52dc fpscr=00000000
+vcvtm.s32.f32 s1, s0 68ecf10a96fa22f431c30bd7a0768699 20ce496ec2c9ee36b80bdd0d60e2805f 20ce496ec2c9ee367fffffff60e2805f 20ce496ec2c9ee367fffffff60e2805f fpscr=00000000
+vcvtm.s32.f32 s1, s0 1dd8078bbb2e449b333d78f4cf68f0b0 0fbf656b76072c57d8ca712b18c17911 0fbf656b76072c570000000018c17911 0fbf656b76072c570000000018c17911 fpscr=00000000
+vcvtm.s32.f32 s1, s0 8cf1e44670d41ffcd34a2f254006ce68 877d999aff54e2392b166c46ab3e8324 877d999aff54e239ffffffffab3e8324 877d999aff54e239ffffffffab3e8324 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtm.s32.f32 s1, s0 138bc20e79a8259b4f80fed29775b3ba 209726ce271c9559c82784084ba4cafc 209726ce271c9559014995f84ba4cafc 209726ce271c9559014995f84ba4cafc fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtm.s32.f32 s1, s0 b7771cd225ab56beecf819f9b7771cd2 33436e3f481df16dc918de05222f9658 33436e3f481df16d00000000222f9658 33436e3f481df16d00000000222f9658 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtm.s32.f32 s1, s0 14465fceb25510bbaffd8a342eb73a25 4aaa315255b9b47588e0b1d435904e31 4aaa315255b9b4750000000035904e31 4aaa315255b9b4750000000035904e31 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.s32.f32 s1, s0 acc916d780a2ea3a1abea25e90f596e0 34bb46482d458b6f15f54b18df4a17af 34bb46482d458b6f80000000df4a17af 34bb46482d458b6f80000000df4a17af fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.s32.f32 s1, s0 267541509e546a7fd4e68adad1568fd2 790021611f52bb989d93ecda5d42e6bb 790021611f52bb987fffffff5d42e6bb 790021611f52bb987fffffff5d42e6bb fpscr=00000000
+vcvtm.s32.f32 s1, s0 9452727f9abc6fefc3341466509ff14d 18a3939f94cb7236f9f34ce2cde86165 18a3939f94cb7236e2f3d360cde86165 18a3939f94cb7236e2f3d360cde86165 fpscr=00000000
+vcvtm.s32.f32 s1, s0 34cd95c69dd8f0f22d6c6ba5ade77182 90e78d037189c8396b5790f70d2c4424 90e78d037189c839000000000d2c4424 90e78d037189c839000000000d2c4424 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.s32.f32 s1, s0 17600a4617600a4690df3416db578fb7 c9b23055a0b6a0a967bb009cc95156d2 c9b23055a0b6a0a9fff2ea92c95156d2 c9b23055a0b6a0a9fff2ea92c95156d2 fpscr=00000000
+vcvtm.s32.f32 s1, s0 da9c48d309e2f96feb176e097079a28d 398abc76ab0c8619ae557ab2347e5110 398abc76ab0c861900000000347e5110 398abc76ab0c861900000000347e5110 fpscr=00000000
+vcvtm.s32.f32 s1, s0 0fe140f803fb7c26eed7f97d32b4366d 94d0fc949f37487d2f31863508d01956 94d0fc949f37487d0000000008d01956 94d0fc949f37487d0000000008d01956 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[2]
+vcvtm.s32.f32 s1, s0 08dc732e4f0f0d8fadd24d62add24d62 03505564bb248807699abd5c2459b401 03505564bb248807000000002459b401 03505564bb248807000000002459b401 fpscr=00000000
+vcvtm.s32.f32 s1, s0 dab0eb9b5b06f31edd23ea1c1e3c55a5 1e78f89a03c449f487db6bb4a9452cd4 1e78f89a03c449f4ffffffffa9452cd4 1e78f89a03c449f4ffffffffa9452cd4 fpscr=00000000
+vcvtm.s32.f32 s1, s0 69a6229e924d13432146569a2f4e9b7e 593bfed3e7d9c0cb2a8fb348bdc7d6b7 593bfed3e7d9c0cbffffffffbdc7d6b7 593bfed3e7d9c0cbffffffffbdc7d6b7 fpscr=00000000
+vcvtm.s32.f32 s1, s0 085e0bf555366421625bb10c31b091e1 afcedebc20a3aae41f4ad1a98b1d9e2c afcedebc20a3aae4ffffffff8b1d9e2c afcedebc20a3aae4ffffffff8b1d9e2c fpscr=00000000
+vcvtn.u32.f64 s27, d5 4f6c80b37e6392dee73c79dc2b38a557 2a10e0481ccc09514c2a258227ac8915 000000007e6392dee73c79dc2b38a557 2a10e0481ccc09514c2a258227ac8915 fpscr=00000000
+vcvtn.u32.f64 s27, d5 df4af078027c243309442a750119432e ce658dbd6b10b83344d7e7313db0cf8b 00000000027c243309442a750119432e ce658dbd6b10b83344d7e7313db0cf8b fpscr=00000000
+vcvtn.u32.f64 s27, d5 1506e125c37418c5192ff7368861b419 2fded8acf89038dc1deb8a0687cfdb3a 00000000c37418c5192ff7368861b419 2fded8acf89038dc1deb8a0687cfdb3a fpscr=00000000
+vcvtn.u32.f64 s27, d5 93424ef0392c62da38666dcb73e4db1d 644da0d29bfcd0cba9448360a180b7a0 ffffffff392c62da38666dcb73e4db1d 644da0d29bfcd0cba9448360a180b7a0 fpscr=00000000
+vcvtn.u32.f64 s27, d5 b09ee2df057e4b71fca1efe01d80d1eb 62319ad813a4188d05316fae4161ce2b ffffffff057e4b71fca1efe01d80d1eb 62319ad813a4188d05316fae4161ce2b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 ae8495eb5b66d977ae8495eb5b66d977 cfb006185cc94b8267b355b84b944dc9 000000005b66d977ae8495eb5b66d977 cfb006185cc94b8267b355b84b944dc9 fpscr=00000000
+vcvtn.u32.f64 s27, d5 b663dc61766721425e7858455e6eea36 871aff9c3238a9dbbd87629234083df5 00000000766721425e7858455e6eea36 871aff9c3238a9dbbd87629234083df5 fpscr=00000000
+vcvtn.u32.f64 s27, d5 dd4fbcf704b693750f1afc9cad6c14be 6be6bfb1da119c04c70cf214f27d7273 ffffffff04b693750f1afc9cad6c14be 6be6bfb1da119c04c70cf214f27d7273 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 03c1d781342509547d2c4e476f8ec324 6a38e8b66cd6e3552ca4dcfe3c9189b8 ffffffff342509547d2c4e476f8ec324 6a38e8b66cd6e3552ca4dcfe3c9189b8 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 a3a08651367adc526a4b94c93782c26d d99a4849e7f0a939d99a4849e7f0a939 00000000367adc526a4b94c93782c26d d99a4849e7f0a939d99a4849e7f0a939 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 9ea3c8364a1a8fb49ea3c8364a1a8fb4 18be694a03332affe378bc8c0412a0fd 000000004a1a8fb49ea3c8364a1a8fb4 18be694a03332affe378bc8c0412a0fd fpscr=00000000
+vcvtn.u32.f64 s27, d5 7a65723edcc94303aaf72badbecedc56 1ab9c6cfaf3021605be36865235cd2f9 00000000dcc94303aaf72badbecedc56 1ab9c6cfaf3021605be36865235cd2f9 fpscr=00000000
+vcvtn.u32.f64 s27, d5 19cb88f8e69fa45e615c228fcc3cce33 dfccc7530aa93bfe529f16b1e422688a 00000000e69fa45e615c228fcc3cce33 dfccc7530aa93bfe529f16b1e422688a fpscr=00000000
+vcvtn.u32.f64 s27, d5 30b1e8631f16f1d7434cb713b8648f16 175d9032deb4ff2561e7a02cf28f23a2 000000001f16f1d7434cb713b8648f16 175d9032deb4ff2561e7a02cf28f23a2 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.u32.f64 s27, d5 20ad2a15816130f3705ba4bba46e8484 ca74ab00e312598e3499ff894a05f87e 00000000816130f3705ba4bba46e8484 ca74ab00e312598e3499ff894a05f87e fpscr=00000000
+vcvtn.u32.f64 s27, d5 6025e3a4d51733152947f7d9406366b2 82bdbfeadf848d6af9a88ea482ac445c 00000000d51733152947f7d9406366b2 82bdbfeadf848d6af9a88ea482ac445c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.u32.f64 s27, d5 6a6bdddd8b536003115da8ba7f5f7079 958b1239a76739c3958b1239a76739c3 000000008b536003115da8ba7f5f7079 958b1239a76739c3958b1239a76739c3 fpscr=00000000
+vcvtn.u32.f64 s27, d5 d360a1c005f543feda72a90bfc7ae833 b452b492427917bc56776486f7a2cdbb 0000000005f543feda72a90bfc7ae833 b452b492427917bc56776486f7a2cdbb fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 c2549babfb02abf06963f7833ff94a84 bf9c8dedb4f3b77e1a37f91fb20e4ad9 00000000fb02abf06963f7833ff94a84 bf9c8dedb4f3b77e1a37f91fb20e4ad9 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.u32.f64 s27, d5 666969c4b9a76533779de6631b0f3205 13d2424bab49c429d09a957dd644bedf 00000000b9a76533779de6631b0f3205 13d2424bab49c429d09a957dd644bedf fpscr=00000000
+vcvtn.u32.f64 s27, d5 d07b25299560e8c679ed58db0a49a107 27f8d626de80526b0a1930f8edb02a45 000000009560e8c679ed58db0a49a107 27f8d626de80526b0a1930f8edb02a45 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.u32.f64 s27, d5 272b7eb1c7027656808e9b71318dca47 702b7fc977020c465b33e66e37058432 ffffffffc7027656808e9b71318dca47 702b7fc977020c465b33e66e37058432 fpscr=00000000
+vcvtn.u32.f64 s27, d5 6ed906dd6e94f32dba29f007d90e6f35 aca84c4317cbbb3d9d0f74d7bcada302 000000006e94f32dba29f007d90e6f35 aca84c4317cbbb3d9d0f74d7bcada302 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 c6fd82a69aace6a87de8a08a3141ba17 83c795fd1698ca8457c83520c5138463 000000009aace6a87de8a08a3141ba17 83c795fd1698ca8457c83520c5138463 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 44c2c83a59312799c2df8b7a2b5180ce 50322c993c7b3c057d0f18c3f92632f8 ffffffff59312799c2df8b7a2b5180ce 50322c993c7b3c057d0f18c3f92632f8 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.u32.f64 s27, d5 155bc1dc015182a8155bc1dc015182a8 b911c2f3074e42201299a90a102ed5b0 00000000015182a8155bc1dc015182a8 b911c2f3074e42201299a90a102ed5b0 fpscr=00000000
+vcvtn.u32.f64 s27, d5 1be4cacdf3fb52a89b3ef9c83d97e789 14472e95166a0bbeb4057968e7bd896f 00000000f3fb52a89b3ef9c83d97e789 14472e95166a0bbeb4057968e7bd896f fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 f4697434e67611f55b99c9b2c98c0bae b76c014881a995085be299e2422213f5 00000000e67611f55b99c9b2c98c0bae b76c014881a995085be299e2422213f5 fpscr=00000000
+vcvtn.u32.f64 s27, d5 239aec17f5e0201b5f67e0be29b2d6c0 cf96cb06d89ed0c8391b32edd031a956 00000000f5e0201b5f67e0be29b2d6c0 cf96cb06d89ed0c8391b32edd031a956 fpscr=00000000
+vcvtn.u32.f64 s27, d5 c85c44fb99ef597319c7b4c2ca837d20 065989bafb2b6cc6dda0acaade3a632a 0000000099ef597319c7b4c2ca837d20 065989bafb2b6cc6dda0acaade3a632a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 46f6a50047135a4350c937aa38956356 8fdfc12d6b289499c7d9cb0f36f3273f 0000000047135a4350c937aa38956356 8fdfc12d6b289499c7d9cb0f36f3273f fpscr=00000000
+vcvtn.u32.f64 s27, d5 42c1fa23e7b79dcbbefb0baff713a70a d6ead07c88d0cad169dc7e953b9614ff 00000000e7b79dcbbefb0baff713a70a d6ead07c88d0cad169dc7e953b9614ff fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.u32.f64 s27, d5 0d12459853885e102e27a2476ba02000 f376ba58b2903bf3f376ba58b2903bf3 0000000053885e102e27a2476ba02000 f376ba58b2903bf3f376ba58b2903bf3 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 c5f7070dde81abd1f5e5604466e7566f f85eb26692014099c1c58f7753d19409 00000000de81abd1f5e5604466e7566f f85eb26692014099c1c58f7753d19409 fpscr=00000000
+vcvtn.u32.f64 s27, d5 0c325a6c8a06a4970b847db42960d28f 332bc686522d9ad48aba17385e542c32 000000008a06a4970b847db42960d28f 332bc686522d9ad48aba17385e542c32 fpscr=00000000
+vcvtn.u32.f64 s27, d5 2f662a9e91ba71ddafb3f3fb44774e35 90b622b015c8dfe4b8e57772be3bf1d9 0000000091ba71ddafb3f3fb44774e35 90b622b015c8dfe4b8e57772be3bf1d9 fpscr=00000000
+vcvtn.u32.f64 s27, d5 c97fc32908cf8fbce74af64755a29182 71b7f030395a6d03be2dd9e73098ee18 ffffffff08cf8fbce74af64755a29182 71b7f030395a6d03be2dd9e73098ee18 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 c0c53f69ee42c90bc0c53f69ee42c90b b476ac9f287f21e8de521f559e598e3b 00000000ee42c90bc0c53f69ee42c90b b476ac9f287f21e8de521f559e598e3b fpscr=00000000
+vcvtn.u32.f64 s27, d5 dd19b5a2861693e6d2ec60d36e2afb3c 4b327dcfd3af4460ec9e1de2aa4141f9 ffffffff861693e6d2ec60d36e2afb3c 4b327dcfd3af4460ec9e1de2aa4141f9 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 f66cd41b78003b23cf349125d2c695bf 2653a7bc7e719620c24823e2e4d35ecc 0000000078003b23cf349125d2c695bf 2653a7bc7e719620c24823e2e4d35ecc fpscr=00000000
+vcvtn.u32.f64 s27, d5 3b084831f1121022d9991c2d93ab2750 d4b0773972b8a018e352f957f0604d91 00000000f1121022d9991c2d93ab2750 d4b0773972b8a018e352f957f0604d91 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 3afcb016fd032dab3afcb016fd032dab 5c619fa42b9e520c060ec3540d5a193a fffffffffd032dab3afcb016fd032dab 5c619fa42b9e520c060ec3540d5a193a fpscr=00000000
+vcvtn.u32.f64 s27, d5 a51ff6b6f025917a90dc1bf235d34a1e 6bb3a5dc6b90fc33939bc23a573b9a3d fffffffff025917a90dc1bf235d34a1e 6bb3a5dc6b90fc33939bc23a573b9a3d fpscr=00000000
+randV128: 5376 calls, 5535 iters
+vcvtn.u32.f64 s27, d5 97de57f7f893acf472c2b3efc3ce3455 30aaa20f9730585f755a617d084b7c2d 00000000f893acf472c2b3efc3ce3455 30aaa20f9730585f755a617d084b7c2d fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 9f8e25f1618e979b6cec9053591eade2 9dc909671e9738179dc909671e973817 00000000618e979b6cec9053591eade2 9dc909671e9738179dc909671e973817 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 746a7a20c8b93cac18dfcab970aeca49 62ea68c49c1d9fd241ad23998c7c1b5f ffffffffc8b93cac18dfcab970aeca49 62ea68c49c1d9fd241ad23998c7c1b5f fpscr=00000000
+vcvtn.u32.f64 s27, d5 29dd5d8e1bd7cd7c465e210b7e762ccb dea75feb3a9203c51c00d641ad78fd4d 000000001bd7cd7c465e210b7e762ccb dea75feb3a9203c51c00d641ad78fd4d fpscr=00000000
+vcvtn.u32.f64 s27, d5 9b9e27cc288d9ae018948338050fbb30 9010cb35facd3d12833ab53690a7db5d 00000000288d9ae018948338050fbb30 9010cb35facd3d12833ab53690a7db5d fpscr=00000000
+vcvtn.u32.f64 s27, d5 980a516a1b831b3176fc137236e978fd 6124f102666208f203ba322da3fbd71d ffffffff1b831b3176fc137236e978fd 6124f102666208f203ba322da3fbd71d fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 b5ca5a3eb4c3fddad70c09cbf288a7a3 b5dba8456876c44fb5dba8456876c44f 00000000b4c3fddad70c09cbf288a7a3 b5dba8456876c44fb5dba8456876c44f fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.u32.f64 s4, d20 ecbd8457e35d67dfbeeb48edcc37dc67 f725c93fbfa8684bf725c93fbfa8684b ecbd8457e35d67dfbeeb48ed00000000 f725c93fbfa8684bf725c93fbfa8684b fpscr=00000000
+vcvta.u32.f64 s4, d20 a5d3936d543d59c28391b8fd1529d66f 6e9a42a5cdb276b134ee9a58166c8f57 a5d3936d543d59c28391b8fd00000000 6e9a42a5cdb276b134ee9a58166c8f57 fpscr=00000000
+vcvta.u32.f64 s4, d20 66d358f274c5f4454dfabe75b63be780 5bcbab1d03ca3a6b912159a07e826a97 66d358f274c5f4454dfabe7500000000 5bcbab1d03ca3a6b912159a07e826a97 fpscr=00000000
+vcvta.u32.f64 s4, d20 5f4de967d3bb0596cb7c788102889e08 3269659dbeb3b87cf20fc130d10f9c68 5f4de967d3bb0596cb7c788100000000 3269659dbeb3b87cf20fc130d10f9c68 fpscr=00000000
+vcvta.u32.f64 s4, d20 dc20686be623ac7f1329be3b7f290261 14967b92d269e375190741c01bcab753 dc20686be623ac7f1329be3b00000000 14967b92d269e375190741c01bcab753 fpscr=00000000
+vcvta.u32.f64 s4, d20 5afc3444e9c500cf76cc43b786fbe4c3 61ae16004ef183b7e88bab774c272848 5afc3444e9c500cf76cc43b700000000 61ae16004ef183b7e88bab774c272848 fpscr=00000000
+vcvta.u32.f64 s4, d20 714c749b1f703438956a90506f280cef 71468e0a5ff0609e5c8484ac532d9f03 714c749b1f703438956a9050ffffffff 71468e0a5ff0609e5c8484ac532d9f03 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.u32.f64 s4, d20 b19d79ba478ca5b279f2b22841f179cf 347d5ad90d9e510370df32131daf5ed2 b19d79ba478ca5b279f2b228ffffffff 347d5ad90d9e510370df32131daf5ed2 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.u32.f64 s4, d20 89ad77863bb509ca89ad77863bb509ca a5c05d38d6ab2cbeb1b3daded4212924 89ad77863bb509ca89ad778600000000 a5c05d38d6ab2cbeb1b3daded4212924 fpscr=00000000
+vcvta.u32.f64 s4, d20 33ab362a37575ab8629f087c2a4187e8 0600f213a64deba11b446179c612c561 33ab362a37575ab8629f087c00000000 0600f213a64deba11b446179c612c561 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.u32.f64 s4, d20 ed35b6ae75b81ea972c9030cd7798389 1a3c685411379a0d1a3c685411379a0d ed35b6ae75b81ea972c9030c00000000 1a3c685411379a0d1a3c685411379a0d fpscr=00000000
+vcvta.u32.f64 s4, d20 3cce4648ab414b3b6cec5472dd568142 a6cec120fa871fffb037b15f53ccecfa 3cce4648ab414b3b6cec547200000000 a6cec120fa871fffb037b15f53ccecfa fpscr=00000000
+vcvta.u32.f64 s4, d20 9e47b98bf35cbf51c21e06de6e4b1bf6 ae2b46777b40bb6d2519da3a056e388b 9e47b98bf35cbf51c21e06de00000000 ae2b46777b40bb6d2519da3a056e388b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.u32.f64 s4, d20 c15fb8028e0b2c67aa7e7d269a187849 3694e58ba7c57441db6ae1f8f4a5caa5 c15fb8028e0b2c67aa7e7d2600000000 3694e58ba7c57441db6ae1f8f4a5caa5 fpscr=00000000
+vcvta.u32.f64 s4, d20 71265756c774b8b4de744bacd0968316 5b2f0bfd14417549d77e9b37769339e9 71265756c774b8b4de744bac00000000 5b2f0bfd14417549d77e9b37769339e9 fpscr=00000000
+vcvta.u32.f64 s4, d20 98c8d9874ef0ce355f859fa3bce9a786 4e0abe1244ec95732b70c6626b41c7d0 98c8d9874ef0ce355f859fa300000000 4e0abe1244ec95732b70c6626b41c7d0 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.u32.f64 s4, d20 f21f594d648582302ecb28e89468f4d9 e531d61401f069f9e904e6650f122001 f21f594d648582302ecb28e800000000 e531d61401f069f9e904e6650f122001 fpscr=00000000
+vcvta.u32.f64 s4, d20 1128d6e0329f896486b0f28332725a4f a02d84c5daeade6ad0d2091b503f1dd7 1128d6e0329f896486b0f28300000000 a02d84c5daeade6ad0d2091b503f1dd7 fpscr=00000000
+vcvta.u32.f64 s4, d20 b2821d72bae2c2613abc357250209fd3 fa5dd757a44a88aff1619ae9945c240b b2821d72bae2c2613abc357200000000 fa5dd757a44a88aff1619ae9945c240b fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.u32.f64 s4, d20 a4166210cc0f248f54f7294ade47752a e5705f6b270abbd5e5705f6b270abbd5 a4166210cc0f248f54f7294a00000000 e5705f6b270abbd5e5705f6b270abbd5 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.u32.f64 s4, d20 5a5c47208da009bf7f16eda64c924047 935341023d8c44ff935341023d8c44ff 5a5c47208da009bf7f16eda600000000 935341023d8c44ff935341023d8c44ff fpscr=00000000
+vcvta.u32.f64 s4, d20 a3d2fba25805db7277aa72aaebffc35f c4bf32e6afad476795b5eb03dc7e03b7 a3d2fba25805db7277aa72aa00000000 c4bf32e6afad476795b5eb03dc7e03b7 fpscr=00000000
+vcvta.u32.f64 s4, d20 2463fa78a42722ddda944e48fb39e335 11bb9452575653a2c488dfce0d2cf6de 2463fa78a42722ddda944e4800000000 11bb9452575653a2c488dfce0d2cf6de fpscr=00000000
+vcvta.u32.f64 s4, d20 efde7e5320917abd641e62d6e67714bd daef733503fb81fa5e450d4fd00540e0 efde7e5320917abd641e62d6ffffffff daef733503fb81fa5e450d4fd00540e0 fpscr=00000000
+vcvta.u32.f64 s4, d20 99ea3f59a32703c9a7089597b9ec3f4c 17b8c1ea9b4573731f6aeb94f34f1d77 99ea3f59a32703c9a708959700000000 17b8c1ea9b4573731f6aeb94f34f1d77 fpscr=00000000
+vcvta.u32.f64 s4, d20 7ea0f3f24171a5f13d0327badc43b08c 74694fe7e07e75fbdb86d677ed47607c 7ea0f3f24171a5f13d0327ba00000000 74694fe7e07e75fbdb86d677ed47607c fpscr=00000000
+vcvta.u32.f64 s4, d20 ce7ac2437932a11bb6d1edab86e1c066 712881df7eaa243c6a4a1b67942ed5e9 ce7ac2437932a11bb6d1edabffffffff 712881df7eaa243c6a4a1b67942ed5e9 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.u32.f64 s4, d20 1ecfa7a7df99486020335f8cda6bf8e8 e507e8fb0d1f51bf4e4f009a15fc120e 1ecfa7a7df99486020335f8cffffffff e507e8fb0d1f51bf4e4f009a15fc120e fpscr=00000000
+vcvta.u32.f64 s4, d20 b79f36453744e04074bad0f735249253 562405a09ec69816e03f6f91799c332c b79f36453744e04074bad0f700000000 562405a09ec69816e03f6f91799c332c fpscr=00000000
+vcvta.u32.f64 s4, d20 f0d26228d1c924c2444fef4b91748c60 7cae02e0d4e2d6f653ae14f34ae9bc37 f0d26228d1c924c2444fef4bffffffff 7cae02e0d4e2d6f653ae14f34ae9bc37 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.u32.f64 s4, d20 519330d8e5247d694d3168255481a796 82bf9dd861bda0301739fc1b47534f70 519330d8e5247d694d31682500000000 82bf9dd861bda0301739fc1b47534f70 fpscr=00000000
+vcvta.u32.f64 s4, d20 f0d993aa6ec857525c6359895df50b37 52ac2c5de9d282cfa6bc4f05e93c7e0b f0d993aa6ec857525c63598900000000 52ac2c5de9d282cfa6bc4f05e93c7e0b fpscr=00000000
+vcvta.u32.f64 s4, d20 e56936c9536a4f84cd9bda5c9b012e62 d8383a0d787e530be2a53395112aa864 e56936c9536a4f84cd9bda5c00000000 d8383a0d787e530be2a53395112aa864 fpscr=00000000
+vcvta.u32.f64 s4, d20 04ccbbfe0b389b2f2559673d6da7bc0e 6517528a52f849c42b3730cd52b0f4f1 04ccbbfe0b389b2f2559673d00000000 6517528a52f849c42b3730cd52b0f4f1 fpscr=00000000
+vcvta.u32.f64 s4, d20 d425c38a281aea898d4c1a6b4606ba36 e8b144684ab921622f0d75cccbb62483 d425c38a281aea898d4c1a6b00000000 e8b144684ab921622f0d75cccbb62483 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.u32.f64 s4, d20 c8fed3aad0571e06c8fed3aad0571e06 e54f3caa255e07ebd3a405eea5a08faa c8fed3aad0571e06c8fed3aa00000000 e54f3caa255e07ebd3a405eea5a08faa fpscr=00000000
+vcvta.u32.f64 s4, d20 5c6e15190fa77d7fbe10afee06173fc6 91489181c386e540498eb2b1a932d2b3 5c6e15190fa77d7fbe10afeeffffffff 91489181c386e540498eb2b1a932d2b3 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.u32.f64 s4, d20 fb4f4498a23405eefb4f4498a23405ee 5461a1ddce258d27799528b9c898315e fb4f4498a23405eefb4f4498ffffffff 5461a1ddce258d27799528b9c898315e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.u32.f64 s4, d20 1b62f57b58fabe9d1b62f57b58fabe9d 95eef97dc392ddbd86bdcf7d29a8943d 1b62f57b58fabe9d1b62f57b00000000 95eef97dc392ddbd86bdcf7d29a8943d fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.u32.f64 s4, d20 6e1a5a83b03f8581d2b60504b2c7f2b7 95a758875c43bcf595a758875c43bcf5 6e1a5a83b03f8581d2b6050400000000 95a758875c43bcf595a758875c43bcf5 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.u32.f64 s4, d20 f890d9757e6f1d6d51f990869a68447b 6f45987dc55d3d3e29af6e33dd4bd450 f890d9757e6f1d6d51f9908600000000 6f45987dc55d3d3e29af6e33dd4bd450 fpscr=00000000
+vcvta.u32.f64 s4, d20 ef39bcc36d4bfb60ed2c6d03dcda753b 1db937ec6ec344b2585383ebe6b4a8af ef39bcc36d4bfb60ed2c6d03ffffffff 1db937ec6ec344b2585383ebe6b4a8af fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.u32.f64 s4, d20 c7378decfb812b15b6c93a2bc0a12d1d df84a7e827ae2732865cfb0c6dbf3aad c7378decfb812b15b6c93a2b00000000 df84a7e827ae2732865cfb0c6dbf3aad fpscr=00000000
+vcvta.u32.f64 s4, d20 e9018f15eb8420b7a572730b7c6cb747 e3fa04b0923e33ae973dcfb7c56d4627 e9018f15eb8420b7a572730b00000000 e3fa04b0923e33ae973dcfb7c56d4627 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.u32.f64 s4, d20 46bffd3415d85564aba321cae5d61399 b074f39ee45d520d126dcaf9c5baa32c 46bffd3415d85564aba321ca00000000 b074f39ee45d520d126dcaf9c5baa32c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.u32.f64 s4, d20 e501c48290d9e867a0e27f7b47463e70 6fa8366b97decf36c5f4ea929d613ac5 e501c48290d9e867a0e27f7b00000000 6fa8366b97decf36c5f4ea929d613ac5 fpscr=00000000
+vcvta.u32.f64 s4, d20 b432f2d3731c1c5fe537bb3e293868b9 b551b66488dc09bf85abf22b6cb47ee4 b432f2d3731c1c5fe537bb3e00000000 b551b66488dc09bf85abf22b6cb47ee4 fpscr=00000000
+vcvta.u32.f64 s4, d20 c66db381b18425dba532d9d7c62b8961 476e7d4cec811a377c894a10dfc8843a c66db381b18425dba532d9d7ffffffff 476e7d4cec811a377c894a10dfc8843a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.u32.f64 s4, d20 df4b78b1f3fb83a3cd400b16d7dbda1b f407fe34faeeb79ef407fe34faeeb79e df4b78b1f3fb83a3cd400b1600000000 f407fe34faeeb79ef407fe34faeeb79e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.u32.f64 s4, d20 7b2cc2c43c63eaaf48e0cfa8c5e11d88 8d56cb5830cc4f2c9eb702941e06beb1 7b2cc2c43c63eaaf48e0cfa800000000 8d56cb5830cc4f2c9eb702941e06beb1 fpscr=00000000
+vcvtp.u32.f64 s7, d31 250bf11c598af09c899bc082b8f494cc 86d779cc9b78ee7b1d6db8bd0d9c9e92 00000000598af09c899bc082b8f494cc 86d779cc9b78ee7b1d6db8bd0d9c9e92 fpscr=00000000
+vcvtp.u32.f64 s7, d31 733afab7c1cac77ccfad1e88520f435d 4a679181a32f30d953df40e013132870 ffffffffc1cac77ccfad1e88520f435d 4a679181a32f30d953df40e013132870 fpscr=00000000
+vcvtp.u32.f64 s7, d31 69fe98cb1c6607ddf221a18de7f26630 95700c1119383ffdb635a24f6fea8a8a 000000001c6607ddf221a18de7f26630 95700c1119383ffdb635a24f6fea8a8a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.u32.f64 s7, d31 e78978250a2c0704e78978250a2c0704 a94a60d3ee4fe758c3594e6274d2e448 000000000a2c0704e78978250a2c0704 a94a60d3ee4fe758c3594e6274d2e448 fpscr=00000000
+vcvtp.u32.f64 s7, d31 ccca3f516562b4b118ecd3956832ddc1 57b35c7494e552114cefa54c5315c960 ffffffff6562b4b118ecd3956832ddc1 57b35c7494e552114cefa54c5315c960 fpscr=00000000
+vcvtp.u32.f64 s7, d31 07fd844cd520a5dbec5f0162dc95fac8 efab063f3de34e7e48552662f0379aed 00000000d520a5dbec5f0162dc95fac8 efab063f3de34e7e48552662f0379aed fpscr=00000000
+vcvtp.u32.f64 s7, d31 0aab93f88f4127d4dd5863633befe1f2 15680d566907d819d8ab19b933a6069d 000000018f4127d4dd5863633befe1f2 15680d566907d819d8ab19b933a6069d fpscr=00000000
+randV128: 5632 calls, 5803 iters
+vcvtp.u32.f64 s7, d31 38d024dfc8ba9df20c73a9394550d9c9 555fd3c6d980d541d470122906699d85 ffffffffc8ba9df20c73a9394550d9c9 555fd3c6d980d541d470122906699d85 fpscr=00000000
+vcvtp.u32.f64 s7, d31 35a68946acca0618ae7c73c7104792d0 29cba957c68701319a5872e32a6f8519 00000001acca0618ae7c73c7104792d0 29cba957c68701319a5872e32a6f8519 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.u32.f64 s7, d31 8d0cd5e0d360d8cd114e5bcc72bbc54a d8bf28f145ff361dbf935b7b5ecb61de 00000000d360d8cd114e5bcc72bbc54a d8bf28f145ff361dbf935b7b5ecb61de fpscr=00000000
+vcvtp.u32.f64 s7, d31 3f3cc68b65f175d70f3f5dca77dd644c b7f7f5848a2daadd345668d70b2c17c4 0000000065f175d70f3f5dca77dd644c b7f7f5848a2daadd345668d70b2c17c4 fpscr=00000000
+vcvtp.u32.f64 s7, d31 6331fb225e9529515a030749a9aeb343 031816689e5824b4d638e7dcfe92f133 000000015e9529515a030749a9aeb343 031816689e5824b4d638e7dcfe92f133 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.u32.f64 s7, d31 8540f20aa46a1850b8c8d4129b0923bf f06c84e4b487f29ef06c84e4b487f29e 00000000a46a1850b8c8d4129b0923bf f06c84e4b487f29ef06c84e4b487f29e fpscr=00000000
+vcvtp.u32.f64 s7, d31 f487fc2801490fb5f6f5cd24fa302c36 70653d475e99cd7506840bb4c0580a12 ffffffff01490fb5f6f5cd24fa302c36 70653d475e99cd7506840bb4c0580a12 fpscr=00000000
+vcvtp.u32.f64 s7, d31 2d4f2b5dc4ac75ebe68b10b11da7c0be 2d4bfd28c958d6bc0be2759ffa47ee34 00000001c4ac75ebe68b10b11da7c0be 2d4bfd28c958d6bc0be2759ffa47ee34 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.u32.f64 s7, d31 2906791eec71bc94cda2bb0e7dc47297 d7ccf2a7d76ad73403fe8d534ef97b5e 00000000ec71bc94cda2bb0e7dc47297 d7ccf2a7d76ad73403fe8d534ef97b5e fpscr=00000000
+vcvtp.u32.f64 s7, d31 04ef45502dc7df79ede8f91b82fafb6c c01b8cb301b2029962800a71705c2cb5 000000002dc7df79ede8f91b82fafb6c c01b8cb301b2029962800a71705c2cb5 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.u32.f64 s7, d31 c1d3876c4ddf4fe4abd52109aa4d1f64 a2b8e26ba011a7e5bb3770391af7bbc3 000000004ddf4fe4abd52109aa4d1f64 a2b8e26ba011a7e5bb3770391af7bbc3 fpscr=00000000
+vcvtp.u32.f64 s7, d31 584b6e7b13cc250d35aa427c6fb17b27 b06bbc149cecab9c9defe00786f91d90 0000000013cc250d35aa427c6fb17b27 b06bbc149cecab9c9defe00786f91d90 fpscr=00000000
+vcvtp.u32.f64 s7, d31 32ce174774749765351bf4ee18934639 5f4c309f5f65b201ec3ed59efb2de8c3 ffffffff74749765351bf4ee18934639 5f4c309f5f65b201ec3ed59efb2de8c3 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.u32.f64 s7, d31 d3d800e41c9ad7d9ebc915babc89925b 2b104934c532eea6ee53cd1bde0d96c7 000000011c9ad7d9ebc915babc89925b 2b104934c532eea6ee53cd1bde0d96c7 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.u32.f64 s7, d31 93edc152b9cd766440911d1b18613273 4e6e4f3109411e9e4e6e4f3109411e9e ffffffffb9cd766440911d1b18613273 4e6e4f3109411e9e4e6e4f3109411e9e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.u32.f64 s7, d31 8bf7450bd9a1e92b87f25328a35c0b2e 5b4bbab030647bde5b4bbab030647bde ffffffffd9a1e92b87f25328a35c0b2e 5b4bbab030647bde5b4bbab030647bde fpscr=00000000
+vcvtp.u32.f64 s7, d31 df273d10cea6c81fd2ab5b57e6998fbc 018c6b484f1d8f8fddc25aaf69be13e7 00000001cea6c81fd2ab5b57e6998fbc 018c6b484f1d8f8fddc25aaf69be13e7 fpscr=00000000
+vcvtp.u32.f64 s7, d31 0aec5e399c2c303d119c84a838c92620 c2f2b990363109ef6b76f7ea5a843a5c 000000009c2c303d119c84a838c92620 c2f2b990363109ef6b76f7ea5a843a5c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.u32.f64 s7, d31 57b0cac51fbe40c857b0cac51fbe40c8 5ffe45c8eb122bb1fbace0931a246d86 ffffffff1fbe40c857b0cac51fbe40c8 5ffe45c8eb122bb1fbace0931a246d86 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.u32.f64 s7, d31 4637ace365dd9a9c59f45f66edb523c4 20036df61fdd358e98b957f3cd2bdf11 0000000165dd9a9c59f45f66edb523c4 20036df61fdd358e98b957f3cd2bdf11 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.u32.f64 s7, d31 0b11b6a8482646a40b11b6a8482646a4 d4713e8a1bf44560c0100380c0df4435 00000000482646a40b11b6a8482646a4 d4713e8a1bf44560c0100380c0df4435 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.u32.f64 s7, d31 33b12c36462268c633b12c36462268c6 ad529eae364043d3a3b29b942c67debe 00000000462268c633b12c36462268c6 ad529eae364043d3a3b29b942c67debe fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.u32.f64 s7, d31 01c47598dfd6679c01c47598dfd6679c 8e8b67641a87f91489e7aaa3047e895e 00000000dfd6679c01c47598dfd6679c 8e8b67641a87f91489e7aaa3047e895e fpscr=00000000
+vcvtp.u32.f64 s7, d31 3563168028dd3b30e50884bbe5428805 6ed9fb74f9a0c03adf3afa5b66c3a5ac ffffffff28dd3b30e50884bbe5428805 6ed9fb74f9a0c03adf3afa5b66c3a5ac fpscr=00000000
+vcvtp.u32.f64 s7, d31 23f9cabdebb84d90d16ad110085519d0 cf59828c4166820abc66cf712f5812ac 00000000ebb84d90d16ad110085519d0 cf59828c4166820abc66cf712f5812ac fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.u32.f64 s7, d31 412269d768875e50ff6863e1b15411e3 fba81d17b83c746afba81d17b83c746a 0000000068875e50ff6863e1b15411e3 fba81d17b83c746afba81d17b83c746a fpscr=00000000
+vcvtp.u32.f64 s7, d31 ff13b97b01acfbcd828f85ef540af22b cdfd52297790487a0fee6e002055981f 0000000001acfbcd828f85ef540af22b cdfd52297790487a0fee6e002055981f fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.u32.f64 s7, d31 0bd9fc215cb614a3d00f17db9800201f 9ee225edf0c04506d3147322f620988b 000000005cb614a3d00f17db9800201f 9ee225edf0c04506d3147322f620988b fpscr=00000000
+vcvtp.u32.f64 s7, d31 3882a82ec609faae5a2f0f6f0569fd91 86b4931f71c7dafbdd23b40e12e33cd6 00000000c609faae5a2f0f6f0569fd91 86b4931f71c7dafbdd23b40e12e33cd6 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.u32.f64 s7, d31 de3cdb3dc4e8706807eb6217fc14edbb dc590213d90c87df6dc3e206cd87cf91 00000000c4e8706807eb6217fc14edbb dc590213d90c87df6dc3e206cd87cf91 fpscr=00000000
+vcvtp.u32.f64 s7, d31 97468b51e66c33035a27c559bd6136fa 173c1a968773c07c6f51f1b1bd3ca104 00000001e66c33035a27c559bd6136fa 173c1a968773c07c6f51f1b1bd3ca104 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.u32.f64 s7, d31 97ebec7e10288f1897ebec7e10288f18 343f2fd3bfc23ebdf65ecbeeb18183d4 0000000110288f1897ebec7e10288f18 343f2fd3bfc23ebdf65ecbeeb18183d4 fpscr=00000000
+vcvtp.u32.f64 s7, d31 a5dddfa15a4786f05f6e4f2ddbd2d153 9938b063c6fb7e6b1daa1b7b80e5db7f 000000005a4786f05f6e4f2ddbd2d153 9938b063c6fb7e6b1daa1b7b80e5db7f fpscr=00000000
+vcvtp.u32.f64 s7, d31 2a2750826174f35ed4733d9629a9c545 77ee6d69f581fa08a2e1a5ced8d6120f ffffffff6174f35ed4733d9629a9c545 77ee6d69f581fa08a2e1a5ced8d6120f fpscr=00000000
+vcvtp.u32.f64 s7, d31 a602d8608e8ec07c162970ce819f8882 67c5d4ca56f1efc04a9b9a2faa51845d ffffffff8e8ec07c162970ce819f8882 67c5d4ca56f1efc04a9b9a2faa51845d fpscr=00000000
+vcvtp.u32.f64 s7, d31 acfb77e47bcd377770f2305623ddb7d0 1e242bfffe6298bdbbc924af78e56f37 000000017bcd377770f2305623ddb7d0 1e242bfffe6298bdbbc924af78e56f37 fpscr=00000000
+vcvtp.u32.f64 s7, d31 bf5b81b951ea7df5b4528b7c3031fff2 3ebe2f6c0153ea1e893b4ebd87d8ee94 0000000151ea7df5b4528b7c3031fff2 3ebe2f6c0153ea1e893b4ebd87d8ee94 fpscr=00000000
+vcvtp.u32.f64 s7, d31 7e2bd1de8a3c6b81a030cee3b1703451 fe34971a3eec314f2784ba21eab1d62b 000000008a3c6b81a030cee3b1703451 fe34971a3eec314f2784ba21eab1d62b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.u32.f64 s7, d31 231066d41abcc6d7a5f358f4faaeca8f c12068c40da490bbb042414a6f177967 000000001abcc6d7a5f358f4faaeca8f c12068c40da490bbb042414a6f177967 fpscr=00000000
+vcvtp.u32.f64 s7, d31 bfbb6d0850a9f1dbcf150c81d2287161 c1ae7a763f58cb4c5be79bc3750c7320 0000000050a9f1dbcf150c81d2287161 c1ae7a763f58cb4c5be79bc3750c7320 fpscr=00000000
+vcvtp.u32.f64 s7, d31 6c66e70a0de9e5473dc87c19c43db55a f401034f63c24c6e5de4430df8af87f0 000000000de9e5473dc87c19c43db55a f401034f63c24c6e5de4430df8af87f0 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.u32.f64 s7, d31 7db28c823b6af7847db28c823b6af784 8c2fd5104309ce2c2617eb275940c36c 000000003b6af7847db28c823b6af784 8c2fd5104309ce2c2617eb275940c36c fpscr=00000000
+vcvtp.u32.f64 s7, d31 4c5050f8ccb0b0fdf66bda60af8bb66e 8c4e84f243d4038ce0feedbd3360393d 00000000ccb0b0fdf66bda60af8bb66e 8c4e84f243d4038ce0feedbd3360393d fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 892d65a4f3e6eff6892d65a4f3e6eff6 18dfed002a791892cf9f0006b3e4f479 18dfed002a79189200000000b3e4f479 18dfed002a79189200000000b3e4f479 fpscr=00000000
+vcvtm.u32.f64 s1, d0 07810bec72e8b020e83df729baffa125 5b99fa2acf60035baedb734811bfee65 5b99fa2acf60035b0000000011bfee65 5b99fa2acf60035b0000000011bfee65 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 7dc577ffee0a85fc6811f5b943eb0972 882f111930e2201b9e10339accc1ea92 882f111930e2201b00000000ccc1ea92 882f111930e2201b00000000ccc1ea92 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 c83ae7439f777e71bd96ea61bc7413c3 2420c4b672f6327b170c3cee0d58bfdf 2420c4b672f6327b000000000d58bfdf 2420c4b672f6327b000000000d58bfdf fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.u32.f64 s1, d0 e9234cf1c432425f5795e1cd5a11437c 3c2201955a60b8eedf35a2989d4750a4 3c2201955a60b8ee000000009d4750a4 3c2201955a60b8ee000000009d4750a4 fpscr=00000000
+vcvtm.u32.f64 s1, d0 82e87ec008860e06f8c9baabe4ee9360 6d8e515d40cf0f4c82cfb67b212b60af 6d8e515d40cf0f4c00000000212b60af 6d8e515d40cf0f4c00000000212b60af fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 ff086dd456b47ae2ff086dd456b47ae2 19377cc8b5f9d277e4ef1dff7456f62d 19377cc8b5f9d277000000007456f62d 19377cc8b5f9d277000000007456f62d fpscr=00000000
+vcvtm.u32.f64 s1, d0 2582e062985a26bb5bf69720305e23a2 b58052df59e12edef2ad125a0118b2d2 b58052df59e12ede000000000118b2d2 b58052df59e12ede000000000118b2d2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 e9f2d3c71a47e71ee9f2d3c71a47e71e 62f8b963423caeec09d72018081dd321 62f8b963423caeec00000000081dd321 62f8b963423caeec00000000081dd321 fpscr=00000000
+vcvtm.u32.f64 s1, d0 542b331bba5d78950a07d5e81a439997 c9979d0006b3a68a903c67a8d50f2c9c c9979d0006b3a68a00000000d50f2c9c c9979d0006b3a68a00000000d50f2c9c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 344fd0f849e5ccef344fd0f849e5ccef 1045592d21459ecda406ff99adba81bc 1045592d21459ecd00000000adba81bc 1045592d21459ecd00000000adba81bc fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.u32.f64 s1, d0 6d3b8eec070db5666d3b8eec070db566 f81cc36b265d9629ce2ed4eea76916ef f81cc36b265d962900000000a76916ef f81cc36b265d962900000000a76916ef fpscr=00000000
+vcvtm.u32.f64 s1, d0 4956998acb4f88bb16d188b26f655079 945ccf68430880f007ec132cace3ba97 945ccf68430880f000000000ace3ba97 945ccf68430880f000000000ace3ba97 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 2b3220d24fc1e5dbd5a9e4c2b02034de 1530d4173fa68c202204bb70e75be92c 1530d4173fa68c2000000000e75be92c 1530d4173fa68c2000000000e75be92c fpscr=00000000
+vcvtm.u32.f64 s1, d0 eed5cd278c770a25e59d68b559b9b40a 167c53c3b309029252fb23fbfb039658 167c53c3b3090292fffffffffb039658 167c53c3b3090292fffffffffb039658 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 d76bf686a1733ab3f0fb3d818bffbbc6 2fc3eae0c27528be3e4c180921be0ee5 2fc3eae0c27528be0000000021be0ee5 2fc3eae0c27528be0000000021be0ee5 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 de9fa8fe9b1b3183eef591ed9dd26ea1 7d6ab3df1dfd29a97d6ab3df1dfd29a9 7d6ab3df1dfd29a9ffffffff1dfd29a9 7d6ab3df1dfd29a9ffffffff1dfd29a9 fpscr=00000000
+vcvtm.u32.f64 s1, d0 1f8d8cdcd6b9778eff562077cfc8f12c cb3e8a0132957fea83ce4d17f950c640 cb3e8a0132957fea00000000f950c640 cb3e8a0132957fea00000000f950c640 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.u32.f64 s1, d0 8175757c10e82a0800c340e005a3717f 74ebf60c77eea16b74ebf60c77eea16b 74ebf60c77eea16bffffffff77eea16b 74ebf60c77eea16bffffffff77eea16b fpscr=00000000
+vcvtm.u32.f64 s1, d0 0d2f4a22d659c6e1d20afb8edb8bc381 51b77a1606ac007981ed7270b0fddadc 51b77a1606ac007900000000b0fddadc 51b77a1606ac007900000000b0fddadc fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.u32.f64 s1, d0 e3548943a46532bae3548943a46532ba 113201188121f85a113201188121f85a 113201188121f85a000000008121f85a 113201188121f85a000000008121f85a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: 5888 calls, 6066 iters
+vcvtm.u32.f64 s1, d0 9b000ae7ed5e3ce19b000ae7ed5e3ce1 49ec35e51be3327af30e5b5a2e51cf09 49ec35e51be3327a000000002e51cf09 49ec35e51be3327a000000002e51cf09 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 6679e7a289ffa61c6679e7a289ffa61c b35b58f8f94a1228ec73b29efd9cdcd8 b35b58f8f94a122800000000fd9cdcd8 b35b58f8f94a122800000000fd9cdcd8 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.u32.f64 s1, d0 616f0b7dfabe909b616f0b7dfabe909b 3c64469fa1d882b5bc9b5d080cc5ec3f 3c64469fa1d882b5000000000cc5ec3f 3c64469fa1d882b5000000000cc5ec3f fpscr=00000000
+vcvtm.u32.f64 s1, d0 16d08d0d22f3c63cce9e6f2d2586d884 f1478fe367db84d41bc55d07363548a0 f1478fe367db84d400000000363548a0 f1478fe367db84d400000000363548a0 fpscr=00000000
+vcvtm.u32.f64 s1, d0 e0ccc6ecb2db4f1851cd6d7ab8d775b9 a42c78bc3806e718c4eb8936c582b889 a42c78bc3806e71800000000c582b889 a42c78bc3806e71800000000c582b889 fpscr=00000000
+vcvtm.u32.f64 s1, d0 7db70441bb6f09c44fdf308c34d8144c 0b0d3a71819d7ad8b5be10a3a1251850 0b0d3a71819d7ad800000000a1251850 0b0d3a71819d7ad800000000a1251850 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 6a9202fc94bb5a77a590479acc3b0eca 7351aa78ae67c6800b9652a9cb4f6963 7351aa78ae67c68000000000cb4f6963 7351aa78ae67c68000000000cb4f6963 fpscr=00000000
+vcvtm.u32.f64 s1, d0 f5600dd799523a619a562c49a9236aa2 921931e76d48ecc11227b833d4b68e81 921931e76d48ecc100000000d4b68e81 921931e76d48ecc100000000d4b68e81 fpscr=00000000
+vcvtm.u32.f64 s1, d0 d9f254a79b04e53c7b2c060295c4ade1 071b7dc7e1dc1230a56ce96e6b40c8fd 071b7dc7e1dc1230000000006b40c8fd 071b7dc7e1dc1230000000006b40c8fd fpscr=00000000
+vcvtm.u32.f64 s1, d0 7b3ab82bb153d879689f1157d756a9a6 56846c7e841c24fc153d41842e010e29 56846c7e841c24fc000000002e010e29 56846c7e841c24fc000000002e010e29 fpscr=00000000
+vcvtm.u32.f64 s1, d0 e6bcd2caba6f421b1f10ef793c90718a ca1d8e77afae88ef3ca9fffa8f1e1fc4 ca1d8e77afae88ef000000008f1e1fc4 ca1d8e77afae88ef000000008f1e1fc4 fpscr=00000000
+vcvtm.u32.f64 s1, d0 5d0bd0acfd52488fdbc67c0f018a7805 bfe05eed941ac584fa331fc890a46fa2 bfe05eed941ac5840000000090a46fa2 bfe05eed941ac5840000000090a46fa2 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.u32.f64 s1, d0 ebd3d4d3dc66876324306c8ebfa04666 9509c4c4d4f9abe265211c7796f390e9 9509c4c4d4f9abe2ffffffff96f390e9 9509c4c4d4f9abe2ffffffff96f390e9 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 10f430e3ce3b32895f8c6f5d798fcbe9 375987b309fdfd4d7603d9bd66a91f1c 375987b309fdfd4dffffffff66a91f1c 375987b309fdfd4dffffffff66a91f1c fpscr=00000000
+vcvtm.u32.f64 s1, d0 38d6d018799ec9ac8e42a48183efe0f9 810a7bd9d120e81edfde3bfca012a902 810a7bd9d120e81e00000000a012a902 810a7bd9d120e81e00000000a012a902 fpscr=00000000
+vcvtm.u32.f64 s1, d0 7890e60715834ef9dac52aa5731254c1 2d14393350022777825658854ec7f74f 2d14393350022777000000004ec7f74f 2d14393350022777000000004ec7f74f fpscr=00000000
+vcvtm.u32.f64 s1, d0 4e9cd43e5d8b8fe134cd021f2074143e f5cff071790d5848447488c4d127e86c f5cff071790d5848ffffffffd127e86c f5cff071790d5848ffffffffd127e86c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 74f7b4f7538a6cf974f7b4f7538a6cf9 9458e4384e1ffa93efcc72568a3a156b 9458e4384e1ffa93000000008a3a156b 9458e4384e1ffa93000000008a3a156b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 4bcd55082881d5bf4e441a4f4fe2c073 bf40230a2c07c6cbc5e9b072da0e90af bf40230a2c07c6cb00000000da0e90af bf40230a2c07c6cb00000000da0e90af fpscr=00000000
+vcvtm.u32.f64 s1, d0 c070c0be51039448c1d11adfcea9b37c 79fa9bf9956561e73ace0cb1f452c6b9 79fa9bf9956561e700000000f452c6b9 79fa9bf9956561e700000000f452c6b9 fpscr=00000000
+vcvtm.u32.f64 s1, d0 2e31edbadc9340dd9aa47766100acf72 05bb4a9a602074ec4bc0c93f6ccd14b7 05bb4a9a602074ecffffffff6ccd14b7 05bb4a9a602074ecffffffff6ccd14b7 fpscr=00000000
+vcvtm.u32.f64 s1, d0 652477b7bee5e8cd2621f1cdecb35407 1fd13b00ab3f5474becd70a7cafbd7a9 1fd13b00ab3f547400000000cafbd7a9 1fd13b00ab3f547400000000cafbd7a9 fpscr=00000000
+vcvtm.u32.f64 s1, d0 5739c22488da1f0236afc08c7260708a e8dc7b6cda0c2e746a056a698381cf6b e8dc7b6cda0c2e74ffffffff8381cf6b e8dc7b6cda0c2e74ffffffff8381cf6b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 c6919bcec564b894c6919bcec564b894 81bba4ccc84e75a4b6de2f6279c5ab6c 81bba4ccc84e75a40000000079c5ab6c 81bba4ccc84e75a40000000079c5ab6c fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 088c23ae3ed6fa689a1c45b099514758 ee09f8d98b208700ee09f8d98b208700 ee09f8d98b208700000000008b208700 ee09f8d98b208700000000008b208700 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 39387fee4994b24239387fee4994b242 8d88561f3f617cbb71dc485b240f5e77 8d88561f3f617cbbffffffff240f5e77 8d88561f3f617cbbffffffff240f5e77 fpscr=00000000
+vcvtm.u32.f64 s1, d0 51f4908912f3897b54a5be94773e38b8 e14c6440c6c49039a4275b34e931f627 e14c6440c6c4903900000000e931f627 e14c6440c6c4903900000000e931f627 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.u32.f64 s1, d0 6ad6b3c15370b696a2213e5d8cf6786c b55025cfbac313bea4daf4c1f6eebc77 b55025cfbac313be00000000f6eebc77 b55025cfbac313be00000000f6eebc77 fpscr=00000000
+vcvtm.u32.f64 s1, d0 45e2bcd8c59aee7c3dfec01badaba048 57f99a5c2f8b1ce96b631a5f89046297 57f99a5c2f8b1ce9ffffffff89046297 57f99a5c2f8b1ce9ffffffff89046297 fpscr=00000000
+vcvtn.u32.f32 s27, s5 f361d94ea4c8730f01619b46a6ca7a56 07613c35a97ab6bf4cbd70e4ee4f60fe 05eb8720a4c8730f01619b46a6ca7a56 07613c35a97ab6bf4cbd70e4ee4f60fe fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[1]
+vcvtn.u32.f32 s27, s5 71ed814b6b008206bd09f1c171ed814b d558ee7fe8088c57aa9ae42d84a27db4 000000006b008206bd09f1c171ed814b d558ee7fe8088c57aa9ae42d84a27db4 fpscr=00000000
+vcvtn.u32.f32 s27, s5 f365e620505c7f2cab20c8574c9f70ef 34bb15d0277193c2bb491c1391adf07d 00000000505c7f2cab20c8574c9f70ef 34bb15d0277193c2bb491c1391adf07d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtn.u32.f32 s27, s5 446fbd95acb8699771b4e0a7db59b3aa 0d5c51e20d5c51e2726e3566fc82ae7a ffffffffacb8699771b4e0a7db59b3aa 0d5c51e20d5c51e2726e3566fc82ae7a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtn.u32.f32 s27, s5 c81c24130afe1c99fc863ccc37dd0c42 09d572be21acfdd14037b5d323488cb4 000000030afe1c99fc863ccc37dd0c42 09d572be21acfdd14037b5d323488cb4 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtn.u32.f32 s27, s5 1a2dde68caca5ea8dc5fc16ddb5db496 a91722ce4106f4b6adf7aafacb69aa0b 00000000caca5ea8dc5fc16ddb5db496 a91722ce4106f4b6adf7aafacb69aa0b fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtn.u32.f32 s27, s5 ce6eb6abb84f97187f2d789712376e41 68656e571ec58105959df98d03abc543 00000000b84f97187f2d789712376e41 68656e571ec58105959df98d03abc543 fpscr=00000000
+vcvtn.u32.f32 s27, s5 2fc3a22f79ebdd442df05474c14061cf 232a576e7d487fa8e4f8849b2c63c171 0000000079ebdd442df05474c14061cf 232a576e7d487fa8e4f8849b2c63c171 fpscr=00000000
+vcvtn.u32.f32 s27, s5 851833d0c300af1fd871d8e3dab478b4 2008f48ced0bb9b91bcb4b333d38a67a 00000000c300af1fd871d8e3dab478b4 2008f48ced0bb9b91bcb4b333d38a67a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtn.u32.f32 s27, s5 1e8c4213a7b527db11e698bb0be2b921 fd9146dbfd9146dbcaff7b785efa38bc 00000000a7b527db11e698bb0be2b921 fd9146dbfd9146dbcaff7b785efa38bc fpscr=00000000
+vcvtn.u32.f32 s27, s5 0a253528a2150a1650032a79ac617953 62e3e468aa8ae1839c021b53f5d49a65 00000000a2150a1650032a79ac617953 62e3e468aa8ae1839c021b53f5d49a65 fpscr=00000000
+vcvtn.u32.f32 s27, s5 d53d9da0d052ddf946535d24061d6d41 4197b833b6434424687d5cd9db421e8f ffffffffd052ddf946535d24061d6d41 4197b833b6434424687d5cd9db421e8f fpscr=00000000
+vcvtn.u32.f32 s27, s5 fac3aadc64ab98b854f1a320be430e29 53bb5810d4057c16be78cb2c06c5d0dd 0000000064ab98b854f1a320be430e29 53bb5810d4057c16be78cb2c06c5d0dd fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtn.u32.f32 s27, s5 1ff168b265ff9e44102110504199bd53 9c67ac4476e6f9156fe1397c08fe7548 ffffffff65ff9e44102110504199bd53 9c67ac4476e6f9156fe1397c08fe7548 fpscr=00000000
+vcvtn.u32.f32 s27, s5 45f5b4a25a386b1f5abf64334b3dd1d9 ebd32f0b0d95a9b2cc9b285e29cb730b 000000005a386b1f5abf64334b3dd1d9 ebd32f0b0d95a9b2cc9b285e29cb730b fpscr=00000000
+vcvtn.u32.f32 s27, s5 123f632051e479b3408c89bb9462d8be 82a22227b99a1507766c2a0872b1c801 ffffffff51e479b3408c89bb9462d8be 82a22227b99a1507766c2a0872b1c801 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtn.u32.f32 s27, s5 66b6b0b9ca33c90a7f352e07dcdc5924 a468b3480411c773b7fdb6acbaef8047 00000000ca33c90a7f352e07dcdc5924 a468b3480411c773b7fdb6acbaef8047 fpscr=00000000
+vcvtn.u32.f32 s27, s5 d839ff0b50cf99534bd7d2af1d6db149 aa8a5512cfe8f5065371cec9cde548da ffffffff50cf99534bd7d2af1d6db149 aa8a5512cfe8f5065371cec9cde548da fpscr=00000000
+vcvtn.u32.f32 s27, s5 5dc912a76c547d2a03452cfeb2050b14 ec0237faf52b36e55a49037b591d3eaa ffffffff6c547d2a03452cfeb2050b14 ec0237faf52b36e55a49037b591d3eaa fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.u32.f32 s27, s5 2eb7937abb9c85b8486a473d40c0fd18 7c9439b7b16b2fa773ccaafeb16b2fa7 ffffffffbb9c85b8486a473d40c0fd18 7c9439b7b16b2fa773ccaafeb16b2fa7 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtn.u32.f32 s27, s5 0b0274a08648b6c74f0df25f6ff56d67 13b067be1d55745aba8d0c2bbc520083 000000008648b6c74f0df25f6ff56d67 13b067be1d55745aba8d0c2bbc520083 fpscr=00000000
+vcvtn.u32.f32 s27, s5 9ab04df1c694c1a6e31fc031e3690161 c4d75a3c4f9873301c86566fcf7464cd 00000000c694c1a6e31fc031e3690161 c4d75a3c4f9873301c86566fcf7464cd fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtn.u32.f32 s27, s5 fa54a3bd603c39d7a99922a19d7abeb5 1664374e46f2a8cb96b316b2e0326326 00000000603c39d7a99922a19d7abeb5 1664374e46f2a8cb96b316b2e0326326 fpscr=00000000
+vcvtn.u32.f32 s27, s5 d6f469b35b0e249b632fd45c6682eae7 c9a1fb8fb0217f13e3dbe1fc9f48ffa8 000000005b0e249b632fd45c6682eae7 c9a1fb8fb0217f13e3dbe1fc9f48ffa8 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtn.u32.f32 s27, s5 c788c93b0b02558d52bcfd170dbf4e76 a37263ce589f878f78368020a0b034c3 ffffffff0b02558d52bcfd170dbf4e76 a37263ce589f878f78368020a0b034c3 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtn.u32.f32 s27, s5 10195cec0f4f6ed1f0c89a8ba803b7fd 4399f070a08937bf4399f070e5af74b1 000001340f4f6ed1f0c89a8ba803b7fd 4399f070a08937bf4399f070e5af74b1 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[1]
+vcvtn.u32.f32 s27, s5 82f1f476cf03702882f1f476bf821f3b 7d910a60b1351f51c9d358eac9d358ea 00000000cf03702882f1f476bf821f3b 7d910a60b1351f51c9d358eac9d358ea fpscr=00000000
+vcvtn.u32.f32 s27, s5 bcd169747bae3c9f3b4c6abc0a99cf85 df2a41411bc500ac2f1278693d5b5ebc 000000007bae3c9f3b4c6abc0a99cf85 df2a41411bc500ac2f1278693d5b5ebc fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.u32.f32 s27, s5 6ce79e70a1aea1cca1aea1cc2b362fb0 1d0a3759027c438abeab202573e9d94d 00000000a1aea1cca1aea1cc2b362fb0 1d0a3759027c438abeab202573e9d94d fpscr=00000000
+vcvtn.u32.f32 s27, s5 cc7d9ada21659e79481ad905634f747a ae756c8373766f409d93173f89bfd8e7 0000000021659e79481ad905634f747a ae756c8373766f409d93173f89bfd8e7 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[2]
+vcvtn.u32.f32 s27, s5 6da48ae99a7d9f926da48ae9cf584b45 e068c91f84ffb47a901840f0d83be984 000000009a7d9f926da48ae9cf584b45 e068c91f84ffb47a901840f0d83be984 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[1]
+vcvtn.u32.f32 s27, s5 49ed52ecb6164fc876412660543d6fd3 ac0e51fc2ac9b9dd2ac9b9dd8421b639 00000000b6164fc876412660543d6fd3 ac0e51fc2ac9b9dd2ac9b9dd8421b639 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[2]
+vcvtn.u32.f32 s27, s5 dc8a28e97283ba547283ba54b5e89125 019d6d2b8ab49b4f87f518f9376b27fc 000000007283ba547283ba54b5e89125 019d6d2b8ab49b4f87f518f9376b27fc fpscr=00000000
+vcvtn.u32.f32 s27, s5 8f898f4a4826e314b707fabc3556c142 1834fd46eb2d769acd00cd3811c9341b 000000004826e314b707fabc3556c142 1834fd46eb2d769acd00cd3811c9341b fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtn.u32.f32 s27, s5 48d1a6017208c0a3da7b438139a136ad 34028be834028be8a464245041576366 000000007208c0a3da7b438139a136ad 34028be834028be8a464245041576366 fpscr=00000000
+randV128: 6144 calls, 6328 iters
+vcvtn.u32.f32 s27, s5 c66d8b22067087c136d7d66567829198 f022b699a7fca58fd65bb4890e783c76 00000000067087c136d7d66567829198 f022b699a7fca58fd65bb4890e783c76 fpscr=00000000
+vcvtn.u32.f32 s27, s5 d81144ffdeb27d6af9eb6566ab9a9cff 81fcee6f2c3da8dda1afab084685f9ab 00000000deb27d6af9eb6566ab9a9cff 81fcee6f2c3da8dda1afab084685f9ab fpscr=00000000
+vcvtn.u32.f32 s27, s5 6b614674e686aeec766f0d9c1f18c41d de621b46ab8121941fd0eaf79c0dbcba 00000000e686aeec766f0d9c1f18c41d de621b46ab8121941fd0eaf79c0dbcba fpscr=00000000
+vcvtn.u32.f32 s27, s5 f6378388ee4f3b1783f894586f041a17 eeb2eccba607f0d5020daaec2abdddc8 00000000ee4f3b1783f894586f041a17 eeb2eccba607f0d5020daaec2abdddc8 fpscr=00000000
+vcvtn.u32.f32 s27, s5 e2e02e17497d441aed206a2f8fc9d6a3 5bb4dca50c8bdbfd722182d5e77fea57 ffffffff497d441aed206a2f8fc9d6a3 5bb4dca50c8bdbfd722182d5e77fea57 fpscr=00000000
+vcvtn.u32.f32 s27, s5 a24bd6efe914d34162274dbfa2903028 d6b916c1c8a1de05eac0492320105169 00000000e914d34162274dbfa2903028 d6b916c1c8a1de05eac0492320105169 fpscr=00000000
+vcvtn.u32.f32 s27, s5 93fd399b84a0972b4764716b5266a1f1 baf5308c47a47eccfab206f51a66dc66 0000000084a0972b4764716b5266a1f1 baf5308c47a47eccfab206f51a66dc66 fpscr=00000000
+vcvtn.u32.f32 s27, s5 1c6a44aad0b6bef92bf486d2d4851804 5fec30c9770067453a6b5d5e4f8af6c5 00000000d0b6bef92bf486d2d4851804 5fec30c9770067453a6b5d5e4f8af6c5 fpscr=00000000
+vcvtn.u32.f32 s27, s5 898fd54e44d21cda2a5c5780f82704c6 22523845c0ff3b57d5bf83ea8f7093d7 0000000044d21cda2a5c5780f82704c6 22523845c0ff3b57d5bf83ea8f7093d7 fpscr=00000000
+vcvtn.u32.f32 s27, s5 13ff95e610b186103ef54fd3fecf6512 4463ef6debba5745bffc7897b29264dc 0000000010b186103ef54fd3fecf6512 4463ef6debba5745bffc7897b29264dc fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtn.u32.f32 s27, s5 d8e97adeb383fae77e3c381869b43c73 285615568831835330a1d71d88318353 00000000b383fae77e3c381869b43c73 285615568831835330a1d71d88318353 fpscr=00000000
+vcvtn.u32.f32 s27, s5 67982e16320bae6df1f42599b0fd668c 82870b447138ee1f28c37cca06758697 00000000320bae6df1f42599b0fd668c 82870b447138ee1f28c37cca06758697 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[2]
+vcvtn.u32.f32 s27, s5 8ed899ae6d7ad72e2b20460a3d643b35 a73a48d5a73a48d5b39829702e0a15f7 000000006d7ad72e2b20460a3d643b35 a73a48d5a73a48d5b39829702e0a15f7 fpscr=00000000
+vcvtn.u32.f32 s27, s5 b35ec515b16446153ba3c22bd2b71514 8e12c0008174823ab70380ad9b1dd5a1 00000000b16446153ba3c22bd2b71514 8e12c0008174823ab70380ad9b1dd5a1 fpscr=00000000
+vcvtn.u32.f32 s27, s5 49276c8639e7ed7f38989f3ebc53a295 ca16ca0bd30653b8d4f9441ee80b194d 0000000039e7ed7f38989f3ebc53a295 ca16ca0bd30653b8d4f9441ee80b194d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.u32.f32 s4, s20 facddafffacddaff0cfec6510d265b0a ec345b3df19253fa3a77fefe0e186705 facddafffacddaff0cfec65100000000 ec345b3df19253fa3a77fefe0e186705 fpscr=00000000
+vcvta.u32.f32 s4, s20 019b767b5899b2fc3430009c7f560a05 607133e9b488ae99df1a2720471b70db 019b767b5899b2fc3430009c00009b71 607133e9b488ae99df1a2720471b70db fpscr=00000000
+vcvta.u32.f32 s4, s20 d5887b7953d02db16dd911073a354a7f a43c45c4c2784ed4c5ef14554047a868 d5887b7953d02db16dd9110700000003 a43c45c4c2784ed4c5ef14554047a868 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvta.u32.f32 s4, s20 f936b1ba86a6bfe9ee640b78fe33f84e a7108efbd9af5d4f52c6a43a6cc12db0 f936b1ba86a6bfe9ee640b78ffffffff a7108efbd9af5d4f52c6a43a6cc12db0 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.u32.f32 s4, s20 3a6706966e1c586de801567e72ff8429 207e2fb63b0fb7de0c1bfe644616a239 3a6706966e1c586de801567e000025a9 207e2fb63b0fb7de0c1bfe644616a239 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvta.u32.f32 s4, s20 334e5ed0334e5ed06fcdde227d898814 68c8e285c4ebe959e323e822a7332545 334e5ed0334e5ed06fcdde2200000000 68c8e285c4ebe959e323e822a7332545 fpscr=00000000
+vcvta.u32.f32 s4, s20 b1fb7ac38b2564391ce0127b9c1e98d1 43e9a56f88ad43410670686a8170e0b5 b1fb7ac38b2564391ce0127b00000000 43e9a56f88ad43410670686a8170e0b5 fpscr=00000000
+vcvta.u32.f32 s4, s20 14be4c6ad8113401a2a3124890bf379e 3b3737c58195b2ae31e6f79cfbdad3dd 14be4c6ad8113401a2a3124800000000 3b3737c58195b2ae31e6f79cfbdad3dd fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.u32.f32 s4, s20 098b92d4eee3c76789c8551089c85510 78d5c454388bc451044cdfc2388bc451 098b92d4eee3c76789c8551000000000 78d5c454388bc451044cdfc2388bc451 fpscr=00000000
+vcvta.u32.f32 s4, s20 acd04fbc5097e6a0cfd6b37fddef694a 6237c0f5920b496ec2856c5b7c0cac8a acd04fbc5097e6a0cfd6b37fffffffff 6237c0f5920b496ec2856c5b7c0cac8a fpscr=00000000
+vcvta.u32.f32 s4, s20 8389ea5408cf98bec5055561815e2ad9 5b162088f01e75208648557c4486c98f 8389ea5408cf98bec505556100000436 5b162088f01e75208648557c4486c98f fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvta.u32.f32 s4, s20 be2ab989846dc1d49b2d877bd018d2ca 51fc85e6b14e546d079c10ecd3c7c9bb be2ab989846dc1d49b2d877b00000000 51fc85e6b14e546d079c10ecd3c7c9bb fpscr=00000000
+vcvta.u32.f32 s4, s20 96870ada29659ee18ec21d222fe2b5a6 b11654c96eb2a9d104bb6f03f0df701c 96870ada29659ee18ec21d2200000000 b11654c96eb2a9d104bb6f03f0df701c fpscr=00000000
+vcvta.u32.f32 s4, s20 19cd481d378f8e855c6ee33a729ab0f9 8c00dc75bdd98336d140a3643cab5a00 19cd481d378f8e855c6ee33a00000000 8c00dc75bdd98336d140a3643cab5a00 fpscr=00000000
+vcvta.u32.f32 s4, s20 59cf4f2bf4dd596b39d56916929fd1d3 a688b07cdf76b83a8d370871738a5c97 59cf4f2bf4dd596b39d56916ffffffff a688b07cdf76b83a8d370871738a5c97 fpscr=00000000
+vcvta.u32.f32 s4, s20 71354c56a52cd1a44e002f067cb97aed a215c38df55fd8363c2340bc820e425b 71354c56a52cd1a44e002f0600000000 a215c38df55fd8363c2340bc820e425b fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvta.u32.f32 s4, s20 3f91d4f2d38d61f86fd466300997aa4d 208887b5f7e9ba95f3eb607b03e8d2db 3f91d4f2d38d61f86fd4663000000000 208887b5f7e9ba95f3eb607b03e8d2db fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvta.u32.f32 s4, s20 90c4b7d1a6d07759aa55bc8f90c4b7d1 f250e1130aa3a6fee4713dc4180402d1 90c4b7d1a6d07759aa55bc8f00000000 f250e1130aa3a6fee4713dc4180402d1 fpscr=00000000
+vcvta.u32.f32 s4, s20 1924ac6e3181a51525503b9a6ffb2fef 4ac2ce646ccbe46c8d9b63bc7f7c7753 1924ac6e3181a51525503b9affffffff 4ac2ce646ccbe46c8d9b63bc7f7c7753 fpscr=00000000
+vcvta.u32.f32 s4, s20 bc2e1362d6bd5ceb84d193024a96878e 570d5071d8f35b1bb6388e52a93603ea bc2e1362d6bd5ceb84d1930200000000 570d5071d8f35b1bb6388e52a93603ea fpscr=00000000
+vcvta.u32.f32 s4, s20 54e5676011c0e5db192cbfffaf51b6d0 ca8c65fd0162610b2b23163f2f7542a6 54e5676011c0e5db192cbfff00000000 ca8c65fd0162610b2b23163f2f7542a6 fpscr=00000000
+vcvta.u32.f32 s4, s20 625d482dd56a15655a90a961c3d1b70b ab02adfb1e518a2ac6a386cea43260ae 625d482dd56a15655a90a96100000000 ab02adfb1e518a2ac6a386cea43260ae fpscr=00000000
+vcvta.u32.f32 s4, s20 0098492fe141185599f1d24e79fb3f55 f6be90891e406a7943d0081e07b2209b 0098492fe141185599f1d24e00000000 f6be90891e406a7943d0081e07b2209b fpscr=00000000
+vcvta.u32.f32 s4, s20 87b0c4d3411dc10678e7283d9aeb41bb 6e01e2626c0bb5ad4e36a970705fb622 87b0c4d3411dc10678e7283dffffffff 6e01e2626c0bb5ad4e36a970705fb622 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvta.u32.f32 s4, s20 7a5533cf0c56faca0c56faca1ad74528 e0c6312baf966adae56326fb94bd6be8 7a5533cf0c56faca0c56faca00000000 e0c6312baf966adae56326fb94bd6be8 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.u32.f32 s4, s20 8bc4da8442db9fc61668c5629da251a0 502c48ede90524a2b3c4a5e752c34549 8bc4da8442db9fc61668c562ffffffff 502c48ede90524a2b3c4a5e752c34549 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvta.u32.f32 s4, s20 144c2a5f19a03125a49c1b9b15997c3e ed3ba49c12d289d4c8832e7892771af6 144c2a5f19a03125a49c1b9b00000000 ed3ba49c12d289d4c8832e7892771af6 fpscr=00000000
+vcvta.u32.f32 s4, s20 e9ee00cb51216a3ea9d8463b877b7686 f5ec03b48b06cd6eb3e3a2d037b5f196 e9ee00cb51216a3ea9d8463b00000000 f5ec03b48b06cd6eb3e3a2d037b5f196 fpscr=00000000
+vcvta.u32.f32 s4, s20 d13a8d06906ba092b03de12ac9018ece cca90eb4fd9b448b17114a5b8b2901e4 d13a8d06906ba092b03de12a00000000 cca90eb4fd9b448b17114a5b8b2901e4 fpscr=00000000
+vcvta.u32.f32 s4, s20 822445b98ab9cb5ebd70dfc0e013b3dd a8bf34224238e6dba26906da4105fafa 822445b98ab9cb5ebd70dfc000000008 a8bf34224238e6dba26906da4105fafa fpscr=00000000
+vcvta.u32.f32 s4, s20 42bdac9c4fed523d4150af7ad3dd2033 4da48df8eb0821e211de4dffc2b72a01 42bdac9c4fed523d4150af7a00000000 4da48df8eb0821e211de4dffc2b72a01 fpscr=00000000
+vcvta.u32.f32 s4, s20 e58e61ee2873d094ef3b6cc255dd993a dd7621a3cd04eb3026bc8b851af82382 e58e61ee2873d094ef3b6cc200000000 dd7621a3cd04eb3026bc8b851af82382 fpscr=00000000
+vcvta.u32.f32 s4, s20 e848c4f55112593218fcc6acc3edf12a b8941a27f7320928c3859392393b526d e848c4f55112593218fcc6ac00000000 b8941a27f7320928c3859392393b526d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.u32.f32 s4, s20 e656f95ae656f95a5d984a937237efc4 6e443692d0a796364425e425ea7e0e88 e656f95ae656f95a5d984a9300000000 6e443692d0a796364425e425ea7e0e88 fpscr=00000000
+vcvta.u32.f32 s4, s20 04906c4555671c768a50c8fe019869ff 3ce6478fba4cb24a73008685f5fa86af 04906c4555671c768a50c8fe00000000 3ce6478fba4cb24a73008685f5fa86af fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvta.u32.f32 s4, s20 05bb31171a28910e7f0178507f017850 450a889ef2eb3888c79469f75d860b95 05bb31171a28910e7f017850ffffffff 450a889ef2eb3888c79469f75d860b95 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvta.u32.f32 s4, s20 a577c71cab6da7640a2221b5a577c71c 0ef5949b748db05e44bc4bd9c5f17552 a577c71cab6da7640a2221b500000000 0ef5949b748db05e44bc4bd9c5f17552 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.u32.f32 s4, s20 84312a6fb3c40798f58242f33e629aa7 0c30a043fd410697fd4106979f28b016 84312a6fb3c40798f58242f300000000 0c30a043fd410697fd4106979f28b016 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.u32.f32 s4, s20 51aa57f5441d8a54441d8a54e84119cd 98e034df62db756abf864d6ae008b9cd 51aa57f5441d8a54441d8a5400000000 98e034df62db756abf864d6ae008b9cd fpscr=00000000
+vcvta.u32.f32 s4, s20 1fa1d98801e9e90ee899b15e29549ad6 8c1058c92005415e972dd0974af86886 1fa1d98801e9e90ee899b15e007c3443 8c1058c92005415e972dd0974af86886 fpscr=00000000
+vcvta.u32.f32 s4, s20 64b9d1675128e6bbd10e3c4a7f1b4f93 088c240fbd1d86f17880ce0956375502 64b9d1675128e6bbd10e3c4affffffff 088c240fbd1d86f17880ce0956375502 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.u32.f32 s4, s20 d86689ad80aed34780aed3479ffb2118 fc81e4cb0478c48b5e78c5dd4bf20131 d86689ad80aed34780aed34701e40262 fc81e4cb0478c48b5e78c5dd4bf20131 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvta.u32.f32 s4, s20 ac1bf7ee5ef4f263ac1bf7ee73e78a94 210809f741bb4bc72275da37bc7ca647 ac1bf7ee5ef4f263ac1bf7ee00000000 210809f741bb4bc72275da37bc7ca647 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvta.u32.f32 s4, s20 3f5a5dd8fa1cfe25b440c99263ab6fa2 e86fc0fa3240f28b6e585550623094ca 3f5a5dd8fa1cfe25b440c992ffffffff e86fc0fa3240f28b6e585550623094ca fpscr=00000000
+vcvta.u32.f32 s4, s20 0277fb04da9112e2b4dc9aa316e7ca7f 58859be0011cd699bf93a4cb91842a90 0277fb04da9112e2b4dc9aa300000000 58859be0011cd699bf93a4cb91842a90 fpscr=00000000
+vcvta.u32.f32 s4, s20 b412e5a19b13aa695432f0cfbb8cdec4 a347e2b8ff7da47a4e7e3e96ca81ce1c b412e5a19b13aa695432f0cf00000000 a347e2b8ff7da47a4e7e3e96ca81ce1c fpscr=00000000
+vcvta.u32.f32 s4, s20 199dcbbbb0096c6702883bf07ed54279 e2a0daaa5ac95c25667a9f6f14474201 199dcbbbb0096c6702883bf000000000 e2a0daaa5ac95c25667a9f6f14474201 fpscr=00000000
+vcvta.u32.f32 s4, s20 5841b8fe3b72ba46586f037516378ff9 3d31e3f2fbe79f33d7afdd9ced5ceb9f 5841b8fe3b72ba46586f037500000000 3d31e3f2fbe79f33d7afdd9ced5ceb9f fpscr=00000000
+vcvta.u32.f32 s4, s20 14c4baf51e27745c3fd1e1537ad8c6fb 78174a67ef434289d5e97acd0f065fcb 14c4baf51e27745c3fd1e15300000000 78174a67ef434289d5e97acd0f065fcb fpscr=00000000
+randV128: 6400 calls, 6595 iters
+vcvta.u32.f32 s4, s20 a9c92c159be09c64f2dd57cb103c01ea 389aa0b779333fa3660a9a61c024c9d3 a9c92c159be09c64f2dd57cb00000000 389aa0b779333fa3660a9a61c024c9d3 fpscr=00000000
+vcvtp.u32.f32 s7, s31 23b12e5d8aee4dec3bb908271732ef1f 55f3da6105a1870612402b7fa87b4b84 ffffffff8aee4dec3bb908271732ef1f 55f3da6105a1870612402b7fa87b4b84 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.u32.f32 s7, s31 f733520d47143f1a09af8c43532f5d1c 3fede8f3c4e75ecff99fc20cc4e75ecf 0000000247143f1a09af8c43532f5d1c 3fede8f3c4e75ecff99fc20cc4e75ecf fpscr=00000000
+vcvtp.u32.f32 s7, s31 f3312a90ab639d0ddd332b2fefd06566 78935ff8f1bbd40485e4612fc9377369 ffffffffab639d0ddd332b2fefd06566 78935ff8f1bbd40485e4612fc9377369 fpscr=00000000
+vcvtp.u32.f32 s7, s31 a246bd589ea23aea7f4429c4adff8b6e cce07f8fb8737563b552ac3565df802b 000000009ea23aea7f4429c4adff8b6e cce07f8fb8737563b552ac3565df802b fpscr=00000000
+vcvtp.u32.f32 s7, s31 6674fa9341fdaed80420c14c1d152cbd 4e6dc8dc84cc7a66e833a5e7f18fb6c7 3b72370041fdaed80420c14c1d152cbd 4e6dc8dc84cc7a66e833a5e7f18fb6c7 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtp.u32.f32 s7, s31 b6411ec408a2f2490c0808bd886cd37d c124f962d180bc5130dea2de958afcb0 0000000008a2f2490c0808bd886cd37d c124f962d180bc5130dea2de958afcb0 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.u32.f32 s7, s31 d82058d99cffa5ac1cdea46bf2bae4c8 1a6184e202ff9de1c3ec7f07a3852ef4 000000019cffa5ac1cdea46bf2bae4c8 1a6184e202ff9de1c3ec7f07a3852ef4 fpscr=00000000
+vcvtp.u32.f32 s7, s31 34b5e0dc5ae0eff634e87c9c8d923d58 741a1740fc2a34dabc980ae75684383e ffffffff5ae0eff634e87c9c8d923d58 741a1740fc2a34dabc980ae75684383e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.u32.f32 s7, s31 a4f21c0119d5ecc7aea6afe3d24dd8a6 336609b8d40a8003336609b8834a469b 0000000119d5ecc7aea6afe3d24dd8a6 336609b8d40a8003336609b8834a469b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtp.u32.f32 s7, s31 91924fce91924fce402c5b347d3e0bc4 4c18f86704dab7a49ec2baf4626ae4b0 0263e19c91924fce402c5b347d3e0bc4 4c18f86704dab7a49ec2baf4626ae4b0 fpscr=00000000
+vcvtp.u32.f32 s7, s31 5605ecd70c87c8b255fe9a5e91883846 a4ca39c957d7a58fde7a273ab15bf896 000000000c87c8b255fe9a5e91883846 a4ca39c957d7a58fde7a273ab15bf896 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtp.u32.f32 s7, s31 ba4c2cda5a969e841035d79db772f9fa 96059222016fcebb9c59d5471b6fb323 000000005a969e841035d79db772f9fa 96059222016fcebb9c59d5471b6fb323 fpscr=00000000
+vcvtp.u32.f32 s7, s31 6f1c99bb3dffc11696b957f8a6b3406e 4c4cceb342c22601d0132c050a3b7a7e 03333acc3dffc11696b957f8a6b3406e 4c4cceb342c22601d0132c050a3b7a7e fpscr=00000000
+vcvtp.u32.f32 s7, s31 2951263be640d7a069fa4eb7b32f2d8a 935c1dd1680b9a7225357bfb3e71876c 00000000e640d7a069fa4eb7b32f2d8a 935c1dd1680b9a7225357bfb3e71876c fpscr=00000000
+vcvtp.u32.f32 s7, s31 1a7284fd658231318ee70bc18702428e 1c9aaebec28fb49f7eb1811e1cd3f6d4 00000001658231318ee70bc18702428e 1c9aaebec28fb49f7eb1811e1cd3f6d4 fpscr=00000000
+vcvtp.u32.f32 s7, s31 7af66b24ef4c2d73cf6c7f2a4572137f 06049a6bd90e83a691271b29ee20e497 00000001ef4c2d73cf6c7f2a4572137f 06049a6bd90e83a691271b29ee20e497 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.u32.f32 s7, s31 3621bcc80bdba25c4770ef864770ef86 d9ab4680de69825368153c453ff76005 000000000bdba25c4770ef864770ef86 d9ab4680de69825368153c453ff76005 fpscr=00000000
+vcvtp.u32.f32 s7, s31 91900adeec5fd49b6f3c670658439d4e 7afbec7fb7d4c9f306fa0ba393b5a520 ffffffffec5fd49b6f3c670658439d4e 7afbec7fb7d4c9f306fa0ba393b5a520 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtp.u32.f32 s7, s31 2c757eee538014fae61edab08e456cd6 dab0c6754e2333ed9ecf1f8660ef00d6 00000000538014fae61edab08e456cd6 dab0c6754e2333ed9ecf1f8660ef00d6 fpscr=00000000
+vcvtp.u32.f32 s7, s31 194e2ac1ca815a0b41a01f9003671bb9 a5b084e36a3cd6d76524c14b737aee7e 00000000ca815a0b41a01f9003671bb9 a5b084e36a3cd6d76524c14b737aee7e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtp.u32.f32 s7, s31 0408bfc18c2f89ae0408bfc148b9d321 2b5be864f5d39b4e01072abd680c82ce 000000018c2f89ae0408bfc148b9d321 2b5be864f5d39b4e01072abd680c82ce fpscr=00000000
+vcvtp.u32.f32 s7, s31 317d54051f5b6c4b74cdbf64ed287865 265becbbd4300de7d1cfdb646a274ef9 000000011f5b6c4b74cdbf64ed287865 265becbbd4300de7d1cfdb646a274ef9 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtp.u32.f32 s7, s31 2437cecb24b7979624b797967b2c914c 483cc146697a874d8dffd49f235f4f96 0002f30624b7979624b797967b2c914c 483cc146697a874d8dffd49f235f4f96 fpscr=00000000
+vcvtp.u32.f32 s7, s31 adce08ba767dde431e5dc68f754777a5 b0f91d5b36e32b2b862bb56624978b87 00000000767dde431e5dc68f754777a5 b0f91d5b36e32b2b862bb56624978b87 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.u32.f32 s7, s31 635ac79f34e735d534e735d5c704f766 1edbff30bd659a4de566e75937a4ff6d 0000000134e735d534e735d5c704f766 1edbff30bd659a4de566e75937a4ff6d fpscr=00000000
+vcvtp.u32.f32 s7, s31 7f47923522f98db443a040c64c516c43 52a62fd869779967e7a8a0076c708753 ffffffff22f98db443a040c64c516c43 52a62fd869779967e7a8a0076c708753 fpscr=00000000
+vcvtp.u32.f32 s7, s31 4061031035bad58728d05a6e16bed25d a1d6400a3fb39a2b89d51a313eccf2bb 0000000035bad58728d05a6e16bed25d a1d6400a3fb39a2b89d51a313eccf2bb fpscr=00000000
+vcvtp.u32.f32 s7, s31 7b145f499fd556485bf14d5561f3cf9f 11071036b53b69b166e860abfd9dff1a 000000019fd556485bf14d5561f3cf9f 11071036b53b69b166e860abfd9dff1a fpscr=00000000
+vcvtp.u32.f32 s7, s31 b67d8cf007d1ac7aa945a4522825e238 b98cf9a8ec9f73fd93cbe0353e464fc3 0000000007d1ac7aa945a4522825e238 b98cf9a8ec9f73fd93cbe0353e464fc3 fpscr=00000000
+vcvtp.u32.f32 s7, s31 550e98561e181db0d64c140a857675cc 89e1fe2ce9b16bf5eed6b66c1e939eb6 000000001e181db0d64c140a857675cc 89e1fe2ce9b16bf5eed6b66c1e939eb6 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtp.u32.f32 s7, s31 709751359ed67d903fc8bc6d70975135 d2cfc4ecbc88087dd9ccca8cec9b5e0d 000000009ed67d903fc8bc6d70975135 d2cfc4ecbc88087dd9ccca8cec9b5e0d fpscr=00000000
+vcvtp.u32.f32 s7, s31 56588e1753bb035114663621c346945d 9b26ace0e09edd66e4be6abd26b7e6bb 0000000053bb035114663621c346945d 9b26ace0e09edd66e4be6abd26b7e6bb fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtp.u32.f32 s7, s31 1d6a865aa4fbb41a2e12e1faa97722a5 c5d47a87dee0fc9fc5d47a8735b4d2ee 00000000a4fbb41a2e12e1faa97722a5 c5d47a87dee0fc9fc5d47a8735b4d2ee fpscr=00000000
+vcvtp.u32.f32 s7, s31 af8eca2071b15d364c94e727e05b7815 dd9d4e5e1eee6fe5377867680e7a61d0 0000000071b15d364c94e727e05b7815 dd9d4e5e1eee6fe5377867680e7a61d0 fpscr=00000000
+vcvtp.u32.f32 s7, s31 d494f3bf3ed16134a6afd82a6dfb7fbe 97dd4d774506667c869ede25a78f141b 000000003ed16134a6afd82a6dfb7fbe 97dd4d774506667c869ede25a78f141b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.u32.f32 s7, s31 fac65bf90a3e9c2795dcd8edeba7ed26 6cfd84e271ba5f5889ce3e52cc77c157 ffffffff0a3e9c2795dcd8edeba7ed26 6cfd84e271ba5f5889ce3e52cc77c157 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtp.u32.f32 s7, s31 41d0d9f6dca8185d88917e3f2b941490 bf3285e7cdef58674f11e4ec41788a55 00000000dca8185d88917e3f2b941490 bf3285e7cdef58674f11e4ec41788a55 fpscr=00000000
+vcvtp.u32.f32 s7, s31 d4d13626fbb2a872255e13f949b9006b b6b29d74a76d359e317cec8a7b7cd764 00000000fbb2a872255e13f949b9006b b6b29d74a76d359e317cec8a7b7cd764 fpscr=00000000
+vcvtp.u32.f32 s7, s31 2bca4ea717e32ac7b1b203ba9372978f c8e38f3f8684560b3f3e2275a6f7de94 0000000017e32ac7b1b203ba9372978f c8e38f3f8684560b3f3e2275a6f7de94 fpscr=00000000
+vcvtp.u32.f32 s7, s31 f716af304f108aa2e9a29fd1cf6e0ae7 666fcb4188a7a9122af5433426e8ec17 ffffffff4f108aa2e9a29fd1cf6e0ae7 666fcb4188a7a9122af5433426e8ec17 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtp.u32.f32 s7, s31 978bfa9a0be2fb1014b1d6355ef2fd3d 67df2d5067df2d507b68b951595fe57b ffffffff0be2fb1014b1d6355ef2fd3d 67df2d5067df2d507b68b951595fe57b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.u32.f32 s7, s31 83adf6283f636d6f45a325a53a64e164 12113144381b8155f533c2d97b6d02bb 000000013f636d6f45a325a53a64e164 12113144381b8155f533c2d97b6d02bb fpscr=00000000
+vcvtp.u32.f32 s7, s31 7622f23011fb0059090719ede144c976 8d89e0bfc618b005e50a865161238baa 0000000011fb0059090719ede144c976 8d89e0bfc618b005e50a865161238baa fpscr=00000000
+vcvtp.u32.f32 s7, s31 81633df7782224a33e4898a842452814 52c50ed02f3a24ddcc36fc680f4fb822 ffffffff782224a33e4898a842452814 52c50ed02f3a24ddcc36fc680f4fb822 fpscr=00000000
+vcvtp.u32.f32 s7, s31 40a7185f93ea6ef29aa3ceb455c7e278 95fa89fc30b44c0024a2e04ca757f3d6 0000000093ea6ef29aa3ceb455c7e278 95fa89fc30b44c0024a2e04ca757f3d6 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtp.u32.f32 s7, s31 d874aeec3b3392f6bc009e693b855043 4cabfb3f70d83b4a4cabfb3fc3b919d1 055fd9f83b3392f6bc009e693b855043 4cabfb3f70d83b4a4cabfb3fc3b919d1 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[3]
+vcvtp.u32.f32 s7, s31 a784ceed886cef6171ce2bb8dafd817a 223f945580f6487143957cda43957cda 00000001886cef6171ce2bb8dafd817a 223f945580f6487143957cda43957cda fpscr=00000000
+vcvtp.u32.f32 s7, s31 1ddc266224380ded3473d7b38f3051cf aaa24e40833402846e33d449f6941ede 0000000024380ded3473d7b38f3051cf aaa24e40833402846e33d449f6941ede fpscr=00000000
+vcvtp.u32.f32 s7, s31 1723ae018f26d282961043ca695a25b1 cc9c38574ee894dde9a34f7fe80503ea 000000008f26d282961043ca695a25b1 cc9c38574ee894dde9a34f7fe80503ea fpscr=00000000
+vcvtp.u32.f32 s7, s31 5910018dbdf0477ea682793d0fa2845c d7c9e56e939ff63daa0c03ee41d1f07f 00000000bdf0477ea682793d0fa2845c d7c9e56e939ff63daa0c03ee41d1f07f fpscr=00000000
+vcvtm.u32.f32 s1, s0 a04464e00f5a708367e5893c444ffaf3 79bf10594bda6d3d995d73c51feefb51 79bf10594bda6d3d000000001feefb51 79bf10594bda6d3d000000001feefb51 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.u32.f32 s1, s0 6edde749eeab0e1ff561549af561549a afc3139589b1ba60dbb0e465abbc3db7 afc3139589b1ba6000000000abbc3db7 afc3139589b1ba6000000000abbc3db7 fpscr=00000000
+vcvtm.u32.f32 s1, s0 c9e08d2c36d16c0890b99c865d0a2126 15afdee06a203655960a6519b2a3014b 15afdee06a20365500000000b2a3014b 15afdee06a20365500000000b2a3014b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.u32.f32 s1, s0 38627091aa914d3c3862709164cddbca 0d0f869b2fe75515829320b723f15e05 0d0f869b2fe755150000000023f15e05 0d0f869b2fe755150000000023f15e05 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtm.u32.f32 s1, s0 f5f317eb0bf7a6b218414ed32c3bd38c 951959d5cf15f5488f721e93ef4129b5 951959d5cf15f54800000000ef4129b5 951959d5cf15f54800000000ef4129b5 fpscr=00000000
+vcvtm.u32.f32 s1, s0 94f3d3eea6eb03b3e605aba62ad3ba55 89f35a1f2828b6daf1f5f06bf8bcc0a5 89f35a1f2828b6da00000000f8bcc0a5 89f35a1f2828b6da00000000f8bcc0a5 fpscr=00000000
+vcvtm.u32.f32 s1, s0 caf8936349402bb2c6834044bd8d45d8 981a42af30dc3d9777eafc6251f5b6d1 981a42af30dc3d97ffffffff51f5b6d1 981a42af30dc3d97ffffffff51f5b6d1 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.u32.f32 s1, s0 3603aaced2199c7912b8a75573660d86 9f31b11113d88f1ebcb1824c1d924511 9f31b11113d88f1e000000001d924511 9f31b11113d88f1e000000001d924511 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.u32.f32 s1, s0 5361340148ec17b553613401205c5039 f0c8e31a45a5735e2e61a0bdc0495da0 f0c8e31a45a5735e00000000c0495da0 f0c8e31a45a5735e00000000c0495da0 fpscr=00000000
+vcvtm.u32.f32 s1, s0 cb8a9602a1b2eeec166366e7f8ae2e90 57b43f014a88189849baa8f51e6a0db4 57b43f014a881898000000001e6a0db4 57b43f014a881898000000001e6a0db4 fpscr=00000000
+vcvtm.u32.f32 s1, s0 abd75333c0f75f7d7b5c9bd7b1f8cc2b 5e4d6f05f1fc2f1e212d868cbc2e396c 5e4d6f05f1fc2f1e00000000bc2e396c 5e4d6f05f1fc2f1e00000000bc2e396c fpscr=00000000
+vcvtm.u32.f32 s1, s0 7f28553c53f36a7fd76ff70654160e55 67334fe992cc78c152c0087d0b283c6a 67334fe992cc78c1000000000b283c6a 67334fe992cc78c1000000000b283c6a fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtm.u32.f32 s1, s0 63faed5a865897b8416abb7be76d771a 126a76f4a46f33f39b9409ca3d061f9e 126a76f4a46f33f3000000003d061f9e 126a76f4a46f33f3000000003d061f9e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: 6656 calls, 6860 iters
+vcvtm.u32.f32 s1, s0 4221cf780eaab39382c2155d8ecb0811 843f792aeed95b7a4e11a7aa466ad32c 843f792aeed95b7a00003ab4466ad32c 843f792aeed95b7a00003ab4466ad32c fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtm.u32.f32 s1, s0 57cec4e62c9a75a6075ffb74af8ef76a 996e95813a1b1663483a5c5a49b9bf77 996e95813a1b1663001737ee49b9bf77 996e95813a1b1663001737ee49b9bf77 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtm.u32.f32 s1, s0 4e71fa56409aa77b9c751a514e71fa56 a42884c8cf4af550e0c46d439e835395 a42884c8cf4af550000000009e835395 a42884c8cf4af550000000009e835395 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtm.u32.f32 s1, s0 bb0dbf2477e17e1043f6c96faf59b7cf 285d8b822dbc963f1b26b72775707ee0 285d8b822dbc963fffffffff75707ee0 285d8b822dbc963fffffffff75707ee0 fpscr=00000000
+vcvtm.u32.f32 s1, s0 f17d5c62020df526e072ab0188d5106d feceb68b1f676f1aa9ec14ac88f79e5f feceb68b1f676f1a0000000088f79e5f feceb68b1f676f1a0000000088f79e5f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtm.u32.f32 s1, s0 d0bbd7958e576879883710fbd92763c9 aa7bf3d5aa7bf3d5e302fbf19da4b9d8 aa7bf3d5aa7bf3d5000000009da4b9d8 aa7bf3d5aa7bf3d5000000009da4b9d8 fpscr=00000000
+vcvtm.u32.f32 s1, s0 c1c78c7d1f89a9cf6c72dd647424532d 630b103a787861b06c548972cc51d1d9 630b103a787861b000000000cc51d1d9 630b103a787861b000000000cc51d1d9 fpscr=00000000
+vcvtm.u32.f32 s1, s0 a84bce606c8583bf6358643cff19c003 98cfab205faf637fb18dafbe160af264 98cfab205faf637f00000000160af264 98cfab205faf637f00000000160af264 fpscr=00000000
+vcvtm.u32.f32 s1, s0 d69b418c76b1bff9d13968e08287df61 6722df41266f2a8b9845c42b2037f585 6722df41266f2a8b000000002037f585 6722df41266f2a8b000000002037f585 fpscr=00000000
+vcvtm.u32.f32 s1, s0 5492e47c97e6e93c9d628d57cf431d3f 73b7b27cf5042147b71e8dcc6ead911e 73b7b27cf5042147ffffffff6ead911e 73b7b27cf5042147ffffffff6ead911e fpscr=00000000
+vcvtm.u32.f32 s1, s0 c72d3821c5e6bdf72e323cf5fbbe18d9 5597e3294490b3ceabf47c6fabbe33c1 5597e3294490b3ce00000000abbe33c1 5597e3294490b3ce00000000abbe33c1 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.u32.f32 s1, s0 2d7d4b6e72f559736a52ee227cdf191a 025c5ca5e26a6597ead1519bead1519b 025c5ca5e26a659700000000ead1519b 025c5ca5e26a659700000000ead1519b fpscr=00000000
+vcvtm.u32.f32 s1, s0 44117d00a9394cca4a59904b617c2335 9219904e0cc4595a49fd02e78e6350e6 9219904e0cc4595a000000008e6350e6 9219904e0cc4595a000000008e6350e6 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[2]
+vcvtm.u32.f32 s1, s0 6e4b23532880d6e77a93fb7a9e60ff8e a7b761671c1cb9b6d1b18ba01c1cb9b6 a7b761671c1cb9b6000000001c1cb9b6 a7b761671c1cb9b6000000001c1cb9b6 fpscr=00000000
+vcvtm.u32.f32 s1, s0 b9f80d7472815f4e9815ec52fe98be68 a07b9139eff5a22a8234b5660e0961e4 a07b9139eff5a22a000000000e0961e4 a07b9139eff5a22a000000000e0961e4 fpscr=00000000
+vcvtm.u32.f32 s1, s0 beebb7cfbcff8373509f1aa6c10e2080 67db792d3be83664fb9134ba3b289088 67db792d3be83664000000003b289088 67db792d3be83664000000003b289088 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[2]
+vcvtm.u32.f32 s1, s0 7251aea71cb411c89900e18d1ad1fe24 8fd7fba3d07efacb60a72d2ebb12b2ac 8fd7fba3d07efacb00000000bb12b2ac 8fd7fba3d07efacb00000000bb12b2ac fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtm.u32.f32 s1, s0 99d6798f587de0c4f459b90f031ed093 c5da39caba01052d79316b7959a3f306 c5da39caba01052dffffffff59a3f306 c5da39caba01052dffffffff59a3f306 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.u32.f32 s1, s0 4e781adacb6128c4c0c59e9123d543f4 de539a572bddfaf84c78fd8f307ffc90 de539a572bddfaf800000000307ffc90 de539a572bddfaf800000000307ffc90 fpscr=00000000
+vcvtm.u32.f32 s1, s0 aef22caa9c3caaec72a77948eeced8c5 0303cf00aab22c80db1666b518aa8b8a 0303cf00aab22c800000000018aa8b8a 0303cf00aab22c800000000018aa8b8a fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.u32.f32 s1, s0 743a121219deb1241932636f1932636f ad3478aa2815366bbdaef52d96fe099b ad3478aa2815366b0000000096fe099b ad3478aa2815366b0000000096fe099b fpscr=00000000
+vcvtm.u32.f32 s1, s0 ae85c880203b37b9f0afae54eec9aa84 abc827416adc728603eb02768dcc04dd abc827416adc7286000000008dcc04dd abc827416adc7286000000008dcc04dd fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtm.u32.f32 s1, s0 e62fc704ec522ae156ef9b33e62fc704 61e5726fb51a22817e217d4da798a8c2 61e5726fb51a228100000000a798a8c2 61e5726fb51a228100000000a798a8c2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.u32.f32 s1, s0 33cd0eb0834d3f6838c041065360cf4e 60b6ce15db4d4d2fb5b47bc881753349 60b6ce15db4d4d2f0000000081753349 60b6ce15db4d4d2f0000000081753349 fpscr=00000000
+vcvtm.u32.f32 s1, s0 602d72e2f97ec265987b5c42b0301590 d9f56aa86a957bee71f3e0824fb07f24 d9f56aa86a957beeffffffff4fb07f24 d9f56aa86a957beeffffffff4fb07f24 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtm.u32.f32 s1, s0 1ad9008f7a3a8ded970d7a487a3a8ded f136adf7ccdaedfc237bdb6dd653f399 f136adf7ccdaedfc00000000d653f399 f136adf7ccdaedfc00000000d653f399 fpscr=00000000
+vcvtm.u32.f32 s1, s0 c6425072f3945f15feac625217e7c383 ea1228ab7a448d812cd8699f48e2f6ec ea1228ab7a448d81000717b748e2f6ec ea1228ab7a448d81000717b748e2f6ec fpscr=00000000
+vcvtm.u32.f32 s1, s0 3d9b6f8aa73d7564e9ccdc147e5949f4 1bc3e0203ea621ab0c73535cc7b02d3d 1bc3e0203ea621ab00000000c7b02d3d 1bc3e0203ea621ab00000000c7b02d3d fpscr=00000000
+vcvtm.u32.f32 s1, s0 c3193659ecaa58a257c46a478691f3b6 1a76d5ce008f0cd129615d138621dfe8 1a76d5ce008f0cd1000000008621dfe8 1a76d5ce008f0cd1000000008621dfe8 fpscr=00000000
+vcvtm.u32.f32 s1, s0 b110862d6f0deb05500206b936b68efb 7af10de7b540fd11ebe7ba608ba2be42 7af10de7b540fd11000000008ba2be42 7af10de7b540fd11000000008ba2be42 fpscr=00000000
+vcvtm.u32.f32 s1, s0 c92298b580c895b917e8bb9ec885daaf 743c160f2bf789a2a25dc607ba2bca2c 743c160f2bf789a200000000ba2bca2c 743c160f2bf789a200000000ba2bca2c fpscr=00000000
+vcvtm.u32.f32 s1, s0 bc1c9533376a762bf0e576ff188c0704 79a56170bc92aa8e5d76a346c22c0e10 79a56170bc92aa8e00000000c22c0e10 79a56170bc92aa8e00000000c22c0e10 fpscr=00000000
+vcvtm.u32.f32 s1, s0 0eb68d86f990fc3a4b763b08604887e0 a1268232d69420c593e7ba8bf1ce3a33 a1268232d69420c500000000f1ce3a33 a1268232d69420c500000000f1ce3a33 fpscr=00000000
+vcvtm.u32.f32 s1, s0 5e30c91b629fdd444206c0376526472f f42c4a516f8ead96b068198fd99a2669 f42c4a516f8ead9600000000d99a2669 f42c4a516f8ead9600000000d99a2669 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[0]
+vcvtm.u32.f32 s1, s0 0bce86b98663691488a76166f85d420b 4ce130824ce130828720b0c5e7802c2f 4ce130824ce1308200000000e7802c2f 4ce130824ce1308200000000e7802c2f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtm.u32.f32 s1, s0 3c6b205b3c3904329b9142afa6b573bf aece18b9f1f6325936e9a9759d676c35 aece18b9f1f63259000000009d676c35 aece18b9f1f63259000000009d676c35 fpscr=00000000
+vcvtm.u32.f32 s1, s0 afc71dddc91943bd06ebfd206f04a951 7559fb8bd1986a068421047f125857ee 7559fb8bd1986a0600000000125857ee 7559fb8bd1986a0600000000125857ee fpscr=00000000
+vrintzeq.f64.f64 d0, d9 65e02960e1a963659e529488d87822c0 7cb9b60d9207675c414d89e1200c0b44 65e02960e1a963659e529488d87822c0 7cb9b60d9207675c414d89e1200c0b44 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 dbe8a688deaffaf96a259ae215568faa c3bd0178d8bde25bdca564f6debbebbe dbe8a688deaffaf96a259ae215568faa c3bd0178d8bde25bdca564f6debbebbe fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vrintzeq.f64.f64 d0, d9 3608b2eacd3ffa5c1da6acf83192d2b8 f7abee35b074ad7c1ff1d4a45062edb7 3608b2eacd3ffa5c1da6acf83192d2b8 f7abee35b074ad7c1ff1d4a45062edb7 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 a0de02e340e1cf0f220565a07770bd84 24bc58ac5673b759557421e5a99e9c7e a0de02e340e1cf0f220565a07770bd84 24bc58ac5673b759557421e5a99e9c7e fpscr=00000000
+vrintzeq.f64.f64 d0, d9 866337f680b1a1318eca98772ac8ca8b f9a64cba9adb8dd047bc359ba9b4c228 866337f680b1a1318eca98772ac8ca8b f9a64cba9adb8dd047bc359ba9b4c228 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 21b8d5c28cf97ce171d544de5e52b257 0eecdbcf81ff6c3578e342b9e920ed05 21b8d5c28cf97ce171d544de5e52b257 0eecdbcf81ff6c3578e342b9e920ed05 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 7f4077c49b62cbc691be2cfb33015585 f462aa778724f99be5ce13d31db5d749 7f4077c49b62cbc691be2cfb33015585 f462aa778724f99be5ce13d31db5d749 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzeq.f64.f64 d0, d9 2fac5ec2b88dd04a0220ecf0751028a5 adb85527447ded3db34104c987f5a076 2fac5ec2b88dd04a0220ecf0751028a5 adb85527447ded3db34104c987f5a076 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 39c75274fc3d3222dab8ad35f24b3552 a575c72719bb22f85a1f7ecbe283f223 39c75274fc3d3222dab8ad35f24b3552 a575c72719bb22f85a1f7ecbe283f223 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 2aa5a95eca04c7ee46789e999be03c97 7c64c7fddbd272ec548916993794012c 2aa5a95eca04c7ee46789e999be03c97 7c64c7fddbd272ec548916993794012c fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzeq.f64.f64 d0, d9 682e8064102bb56d5e9e326e34fa536f f4699220edb3e97bf4699220edb3e97b 682e8064102bb56d5e9e326e34fa536f f4699220edb3e97bf4699220edb3e97b fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzeq.f64.f64 d0, d9 1a88a34419fc7efb7964a7b016e525e9 5ea9667c1df6f604e82e52d6c18fc6aa 1a88a34419fc7efb7964a7b016e525e9 5ea9667c1df6f604e82e52d6c18fc6aa fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vrintzeq.f64.f64 d0, d9 54ba9aae82a2a90354ba9aae82a2a903 a052d8c66f45cde5d0958e84b1110fe3 54ba9aae82a2a90354ba9aae82a2a903 a052d8c66f45cde5d0958e84b1110fe3 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 141ce1bf9b3097c4c33098734a5b4a74 aa9166db76a38f52c9b0cdae6b461f93 141ce1bf9b3097c4c33098734a5b4a74 aa9166db76a38f52c9b0cdae6b461f93 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzeq.f64.f64 d0, d9 9caa83450abd44670c7c7db0aa27e1fb ed4d5894fc39627013d5c066dedc4c2d 9caa83450abd44670c7c7db0aa27e1fb ed4d5894fc39627013d5c066dedc4c2d fpscr=00000000
+vrintzeq.f64.f64 d0, d9 5f08de972718b1a245cdd906dfbeaf28 1a70111e64a1b2a7e1cefbe4f6f738e4 5f08de972718b1a245cdd906dfbeaf28 1a70111e64a1b2a7e1cefbe4f6f738e4 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 2422dabc5978107edca1e96a6fb018be 2cee659f4290f56cdcbcd7750fb41c8b 2422dabc5978107edca1e96a6fb018be 2cee659f4290f56cdcbcd7750fb41c8b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzeq.f64.f64 d0, d9 a73e904457ae1838b20ed5dfacb15dbe 73de451857faeeeeabe9386447493c16 a73e904457ae1838b20ed5dfacb15dbe 73de451857faeeeeabe9386447493c16 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 e13e9176f28bdfdf4538d1c5b27b35da da56e7e875b606410c009980327f4cb5 e13e9176f28bdfdf4538d1c5b27b35da da56e7e875b606410c009980327f4cb5 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzeq.f64.f64 d0, d9 baa0da1ea991590b6a7787853f8f7aad fb14b97b84d72ae624cf1cb3e1fbac3f baa0da1ea991590b6a7787853f8f7aad fb14b97b84d72ae624cf1cb3e1fbac3f fpscr=00000000
+vrintzeq.f64.f64 d0, d9 3b93086c8697a88bd9dda8c62c8b7aee fc11d374e649a682c94b36c666671537 3b93086c8697a88bd9dda8c62c8b7aee fc11d374e649a682c94b36c666671537 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vrintzeq.f64.f64 d0, d9 4e9864983845d733661bde3c68cc5003 a74386d8a99a8838a74386d8a99a8838 4e9864983845d733661bde3c68cc5003 a74386d8a99a8838a74386d8a99a8838 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintzeq.f64.f64 d0, d9 59355852126d6419b4ae5b3ab237f047 0b06697d7100ac17739e7b16b4f8d934 59355852126d6419b4ae5b3ab237f047 0b06697d7100ac17739e7b16b4f8d934 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 2138012201cf2f43267d1dac23e56b34 64eee9a2cd3d3de8663227bc0481647f 2138012201cf2f43267d1dac23e56b34 64eee9a2cd3d3de8663227bc0481647f fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzeq.f64.f64 d0, d9 e199f546a020ca129d80f2c5c661d906 bb15f6746d5c7b22298e692490e54e8c e199f546a020ca129d80f2c5c661d906 bb15f6746d5c7b22298e692490e54e8c fpscr=00000000
+vrintzeq.f64.f64 d0, d9 ce3eff35e371f20d4e126545292e3992 4bc8487f542538e55436688f3b90f004 ce3eff35e371f20d4e126545292e3992 4bc8487f542538e55436688f3b90f004 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 f9a1abe0f09d19754fe0d4e9547fd5d3 f2bc144dc2f083761c22713c6393a685 f9a1abe0f09d19754fe0d4e9547fd5d3 f2bc144dc2f083761c22713c6393a685 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: 6912 calls, 7126 iters
+vrintzeq.f64.f64 d0, d9 bac422d35ded595c1fb07d7ab97d21f4 29dbc0711ac93ef08b1d4af0c29731b8 bac422d35ded595c1fb07d7ab97d21f4 29dbc0711ac93ef08b1d4af0c29731b8 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 caa563d83736892244199b33f0f33bd7 40a74610c2aaef2f1518cb2ab934082f caa563d83736892244199b33f0f33bd7 40a74610c2aaef2f1518cb2ab934082f fpscr=00000000
+vrintzeq.f64.f64 d0, d9 f79906fde72565c49abbe121cd3095d4 b48e3b7bda975d2b5819d505e35d66bd f79906fde72565c49abbe121cd3095d4 b48e3b7bda975d2b5819d505e35d66bd fpscr=00000000
+vrintzeq.f64.f64 d0, d9 204a63281b9d82a926a37f57c127a221 0e826ee370fd7bdbf8e189d5eb043a3b 204a63281b9d82a926a37f57c127a221 0e826ee370fd7bdbf8e189d5eb043a3b fpscr=00000000
+vrintzeq.f64.f64 d0, d9 4b7eb26940d8fcdb7e748361677e8ff1 6ed5ed0262dd35e4f76326b8fb652aee 4b7eb26940d8fcdb7e748361677e8ff1 6ed5ed0262dd35e4f76326b8fb652aee fpscr=00000000
+vrintzeq.f64.f64 d0, d9 03a1568ecd024ae09f6f6760017ee886 af1508b0257a80bd27ae1d2fa8a19cf1 03a1568ecd024ae09f6f6760017ee886 af1508b0257a80bd27ae1d2fa8a19cf1 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzeq.f64.f64 d0, d9 973e682d9b4eec5c6c25e24f1b6f8618 55cb41f84b2ef0de52f24a71bbd587a6 973e682d9b4eec5c6c25e24f1b6f8618 55cb41f84b2ef0de52f24a71bbd587a6 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzeq.f64.f64 d0, d9 fe8032d22709246bfc1d0d8f92aa0647 f643ca18a7fd6c32b0cdc3598692561f fe8032d22709246bfc1d0d8f92aa0647 f643ca18a7fd6c32b0cdc3598692561f fpscr=00000000
+vrintzeq.f64.f64 d0, d9 762aad90df0443d6a45e93792a848c71 ee5a3ca00c308cd26b33d30f26c8a298 762aad90df0443d6a45e93792a848c71 ee5a3ca00c308cd26b33d30f26c8a298 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzeq.f64.f64 d0, d9 6f7837c7653a0f6013b4221b0d8cca93 8e5df439adc0971f19d511f2d47bb864 6f7837c7653a0f6013b4221b0d8cca93 8e5df439adc0971f19d511f2d47bb864 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 85e58265d2b7db0005918c1406189827 5585126929e0b1933c223db54010d73d 85e58265d2b7db0005918c1406189827 5585126929e0b1933c223db54010d73d fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzeq.f64.f64 d0, d9 2b5dd97e2169647e2b5dd97e2169647e 8892e737e3af79c9a1ef80390b8397f9 2b5dd97e2169647e2b5dd97e2169647e 8892e737e3af79c9a1ef80390b8397f9 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 2c6dba4725e13563ef88d59788fc7680 0746786d21940c44eb607ce754dd9633 2c6dba4725e13563ef88d59788fc7680 0746786d21940c44eb607ce754dd9633 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzeq.f64.f64 d0, d9 2eb43572bb95b66522fcf8b33cb90f1d 184ca7c8b93143a2eb96c595bfd49dbc 2eb43572bb95b66522fcf8b33cb90f1d 184ca7c8b93143a2eb96c595bfd49dbc fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzeq.f64.f64 d0, d9 78720bc0e93b286dc43821b6106fcdbc 2cee6ea7383e9ed6d84645c8c41ad86b 78720bc0e93b286dc43821b6106fcdbc 2cee6ea7383e9ed6d84645c8c41ad86b fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzeq.f64.f64 d0, d9 8a87e196a6981a71864d80b70a937d84 39ae5c966226fe0639ae5c966226fe06 8a87e196a6981a71864d80b70a937d84 39ae5c966226fe0639ae5c966226fe06 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 1f22496021170a017e9617e3ac095ccf 64ba85005731ed0722e2504836f37117 1f22496021170a017e9617e3ac095ccf 64ba85005731ed0722e2504836f37117 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzeq.f64.f64 d0, d9 3c7fc973d39ef910eb5703a82035b051 9e42b5e2e85ee9b6761c8256b1b1e79c 3c7fc973d39ef910eb5703a82035b051 9e42b5e2e85ee9b6761c8256b1b1e79c fpscr=00000000
+vrintzeq.f64.f64 d0, d9 522c30d079afff913dd92bae0552e19e 9d6520886f994828ac91cd9f32247c6f 522c30d079afff913dd92bae0552e19e 9d6520886f994828ac91cd9f32247c6f fpscr=00000000
+vrintzeq.f64.f64 d0, d9 d767b03a0f50d6cfc0d548148a9369b8 0ee404a16abab7c8e83e4565d92a7920 d767b03a0f50d6cfc0d548148a9369b8 0ee404a16abab7c8e83e4565d92a7920 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzeq.f64.f64 d0, d9 7756a146d01eb2c61b7cc7a7891b8647 ddd21ba3652935d76c3f6b2501e53bbf 7756a146d01eb2c61b7cc7a7891b8647 ddd21ba3652935d76c3f6b2501e53bbf fpscr=00000000
+vrintzeq.f64.f64 d0, d9 7e1a6d8917cf56c6020ded0256cfbecf 74752b02839b3e01e7af498a6be704d3 7e1a6d8917cf56c6020ded0256cfbecf 74752b02839b3e01e7af498a6be704d3 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vrintzeq.f64.f64 d0, d9 b09155b0b292b58fb09155b0b292b58f e5420ab303a19358cdc67a071474fad6 b09155b0b292b58fb09155b0b292b58f e5420ab303a19358cdc67a071474fad6 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzne.f64.f64 d1, d10 d84be620422a322401bd0e3124641473 23738d678ae6d4698536e5459e45e3d3 800000000000000001bd0e3124641473 23738d678ae6d4698536e5459e45e3d3 fpscr=00000000
+vrintzne.f64.f64 d1, d10 84eb9d1adb29d9eee8f69215cf78acfd 6f9e81d32a8e1fa657554353b97fcfd5 57554353b97fcfd5e8f69215cf78acfd 6f9e81d32a8e1fa657554353b97fcfd5 fpscr=00000000
+vrintzne.f64.f64 d1, d10 09be2fce748bc02884303ee01f65e2f6 7664cb9c53fd6ad425a38d71912c510b 000000000000000084303ee01f65e2f6 7664cb9c53fd6ad425a38d71912c510b fpscr=00000000
+vrintzne.f64.f64 d1, d10 70f36d16f3bd55579413b00f0f5952d6 b0a3fc774ff0e4c8df8413db121276a5 df8413db121276a59413b00f0f5952d6 b0a3fc774ff0e4c8df8413db121276a5 fpscr=00000000
+vrintzne.f64.f64 d1, d10 bb391f380289599d1b292650c6e34f30 f30359a49f4296084633c3587315dcc8 4633c3587315dcc81b292650c6e34f30 f30359a49f4296084633c3587315dcc8 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 c749668c1efadd8381065c3bbb0dc82b 152f58a904f7033969fba5b608c387fd 69fba5b608c387fd81065c3bbb0dc82b 152f58a904f7033969fba5b608c387fd fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 f3207b018140ba19af3272635223b7d0 8c1ca226c9bb323973070425f4222ba5 73070425f4222ba5af3272635223b7d0 8c1ca226c9bb323973070425f4222ba5 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 56f9f4b0b6469a0df5d3884944906c89 b4791370b34ba4f6b4791370b34ba4f6 8000000000000000f5d3884944906c89 b4791370b34ba4f6b4791370b34ba4f6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 a9ae33e0f1d05953374fef2238e06a0b b3dbf1d9dea0e10db3dbf1d9dea0e10d 8000000000000000374fef2238e06a0b b3dbf1d9dea0e10db3dbf1d9dea0e10d fpscr=00000000
+vrintzne.f64.f64 d1, d10 8bb6e6beb71a303535c22a4550b549a8 e00620a04fa5f75779c544e781323d30 79c544e781323d3035c22a4550b549a8 e00620a04fa5f75779c544e781323d30 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 2f130b0ba3cdf11fc6a6a8b6bd890fb2 0f086e75eafd0c2b9edfb7261f93ff40 8000000000000000c6a6a8b6bd890fb2 0f086e75eafd0c2b9edfb7261f93ff40 fpscr=00000000
+vrintzne.f64.f64 d1, d10 9ef3eb72dabe3ec88643cf48f59ed0ed 203e3599ba2303be3e15cc92dfb390ed 00000000000000008643cf48f59ed0ed 203e3599ba2303be3e15cc92dfb390ed fpscr=00000000
+vrintzne.f64.f64 d1, d10 c93bc68591429cdb4bf3ac0be6e6e509 b78543dee5b167af86b09dc471d3145a 80000000000000004bf3ac0be6e6e509 b78543dee5b167af86b09dc471d3145a fpscr=00000000
+vrintzne.f64.f64 d1, d10 7ec031a1374059e3f882f52a42f9e850 edd41d793476282f43503d48084c88b9 43503d48084c88b9f882f52a42f9e850 edd41d793476282f43503d48084c88b9 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzne.f64.f64 d1, d10 e848fb25335f20e7e848fb25335f20e7 7b193937966a4c8f2a02190fab6c8323 0000000000000000e848fb25335f20e7 7b193937966a4c8f2a02190fab6c8323 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 a6036a620ad1d4a776fba089052466d2 9ebdfac81bb7c4f6b174e1bc3c442cb3 800000000000000076fba089052466d2 9ebdfac81bb7c4f6b174e1bc3c442cb3 fpscr=00000000
+vrintzne.f64.f64 d1, d10 df542a86a02805142c7653c27afacc2d 5efbf9a7ab17cc097ed42d952239d880 7ed42d952239d8802c7653c27afacc2d 5efbf9a7ab17cc097ed42d952239d880 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 e26c6d83d9d39488b6d76a174905044d 8c745c92ac36e805965292920cb31193 8000000000000000b6d76a174905044d 8c745c92ac36e805965292920cb31193 fpscr=00000000
+vrintzne.f64.f64 d1, d10 1f7d937437bd68f6717962fb74ee76b5 4a223cb6acbf025b9e05e6b4b6e076f7 8000000000000000717962fb74ee76b5 4a223cb6acbf025b9e05e6b4b6e076f7 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 560e5e594cc5963b560e5e594cc5963b ac267c87814f475510d4882a700533ac 0000000000000000560e5e594cc5963b ac267c87814f475510d4882a700533ac fpscr=00000000
+vrintzne.f64.f64 d1, d10 e30729b5d1dcf18d43a9509c01c18773 a74ee29a2597b80fca88570e96cdef56 ca88570e96cdef5643a9509c01c18773 a74ee29a2597b80fca88570e96cdef56 fpscr=00000000
+vrintzne.f64.f64 d1, d10 3a600955af0695f709d04dd5de4b2dff b6c9ed29f36dff8027a85b68cd1a3043 000000000000000009d04dd5de4b2dff b6c9ed29f36dff8027a85b68cd1a3043 fpscr=00000000
+vrintzne.f64.f64 d1, d10 67b052e87cbca0c5ca1150ab69d2c23f 38ad25541bc785295632e04e92b943f3 5632e04e92b943f3ca1150ab69d2c23f 38ad25541bc785295632e04e92b943f3 fpscr=00000000
+vrintzne.f64.f64 d1, d10 062799745ad282cd06d22086b1fd6564 67b1566cd2f5da3578c69005a3f2c6a2 78c69005a3f2c6a206d22086b1fd6564 67b1566cd2f5da3578c69005a3f2c6a2 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzne.f64.f64 d1, d10 50c9ff7a55499ca150c9ff7a55499ca1 0159db9593813ca95c162c57fc4b7ded 5c162c57fc4b7ded50c9ff7a55499ca1 0159db9593813ca95c162c57fc4b7ded fpscr=00000000
+vrintzne.f64.f64 d1, d10 cbaa5dd44a66efca85a937db8b32a890 16c62800ef04c809fdf89bdc8874d398 fdf89bdc8874d39885a937db8b32a890 16c62800ef04c809fdf89bdc8874d398 fpscr=00000000
+vrintzne.f64.f64 d1, d10 abaa0f3556c2652347283b0ef4a80cdf bf6bc84babffb26100c4928e15f7d1c2 000000000000000047283b0ef4a80cdf bf6bc84babffb26100c4928e15f7d1c2 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 5c3d3d069a119b03cd24e45e424e4047 989bddf194789805989bddf194789805 8000000000000000cd24e45e424e4047 989bddf194789805989bddf194789805 fpscr=00000000
+vrintzne.f64.f64 d1, d10 6df5e3407a0b920c023b4ecd08402b18 c077bdc1a630650f414d054f5aba952b 414d054f00000000023b4ecd08402b18 c077bdc1a630650f414d054f5aba952b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 a2a315542819d4007b9c22c740da482e c9a9bf7449a95158c9a9bf7449a95158 c9a9bf7449a951587b9c22c740da482e c9a9bf7449a95158c9a9bf7449a95158 fpscr=00000000
+vrintzne.f64.f64 d1, d10 1552a7046d25095eebb934c4b23a80ef 0f66500be338913a3e97192346156396 0000000000000000ebb934c4b23a80ef 0f66500be338913a3e97192346156396 fpscr=00000000
+vrintzne.f64.f64 d1, d10 d87b61f4449488310b52ce298d2e7058 e708e6a6196218013d4416a2233f91c7 00000000000000000b52ce298d2e7058 e708e6a6196218013d4416a2233f91c7 fpscr=00000000
+vrintzne.f64.f64 d1, d10 4b1174d081e56603bbd1b5533384d261 f5e86dc02c8e7465565e733c6311b9c1 565e733c6311b9c1bbd1b5533384d261 f5e86dc02c8e7465565e733c6311b9c1 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 d33b2c89671becebc911cab8253ac19d b1de3a37e1a442afe12f584f3875fe36 e12f584f3875fe36c911cab8253ac19d b1de3a37e1a442afe12f584f3875fe36 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vrintzne.f64.f64 d1, d10 90deb72bcbd61e7290deb72bcbd61e72 8c47c047fd44dba58c47c047fd44dba5 800000000000000090deb72bcbd61e72 8c47c047fd44dba58c47c047fd44dba5 fpscr=00000000
+vrintzne.f64.f64 d1, d10 8ad7d1d1c33d4d18c56079e8f2e7f4c5 9f3b4b47e617eae8b504d813487e1bfa 8000000000000000c56079e8f2e7f4c5 9f3b4b47e617eae8b504d813487e1bfa fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 2fdde04d966ff4602fdde04d966ff460 b4e5ff1bf701e6dc973ae4ddb870aff2 80000000000000002fdde04d966ff460 b4e5ff1bf701e6dc973ae4ddb870aff2 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzne.f64.f64 d1, d10 4f1b1a0bdabf139c4f1b1a0bdabf139c 8fe443ab470dc8f37c17c2a73979520e 7c17c2a73979520e4f1b1a0bdabf139c 8fe443ab470dc8f37c17c2a73979520e fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzne.f64.f64 d1, d10 5db6f757b301be8de54a63e41bae09da 109e43a55c692f1ca1fc8bbb052971fa 8000000000000000e54a63e41bae09da 109e43a55c692f1ca1fc8bbb052971fa fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzne.f64.f64 d1, d10 b2bcc2177494b28af0441e98020a1bab cc8dd741aeda7c94cc8dd741aeda7c94 cc8dd741aeda7c94f0441e98020a1bab cc8dd741aeda7c94cc8dd741aeda7c94 fpscr=00000000
+vrintzne.f64.f64 d1, d10 6de3dd1c6c1589dbdbd6425fb08310b9 b51f999bfd05c80451b57daae126ffcd 51b57daae126ffcddbd6425fb08310b9 b51f999bfd05c80451b57daae126ffcd fpscr=00000000
+randV128: 7168 calls, 7393 iters
+vrintzne.f64.f64 d1, d10 537784c1daa995aff0dfdb6aa5d80ef4 1f8c7c8dcbaf679546ae15369f7fb70c 46ae15369f7fb70cf0dfdb6aa5d80ef4 1f8c7c8dcbaf679546ae15369f7fb70c fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzne.f64.f64 d1, d10 c5bfe29406ae295d370116702dec2f08 c5c7be2ff6281ec1c5c7be2ff6281ec1 c5c7be2ff6281ec1370116702dec2f08 c5c7be2ff6281ec1c5c7be2ff6281ec1 fpscr=00000000
+vrintzne.f64.f64 d1, d10 9b891076a383c67ec9ebd4c10772e674 45615e5f60c2c335ef9111b6d6f33e14 ef9111b6d6f33e14c9ebd4c10772e674 45615e5f60c2c335ef9111b6d6f33e14 fpscr=00000000
+vrintzne.f64.f64 d1, d10 5118debc4ed1ae7687e50c87c40611df 3250b285c11ea98428bf61cd25cb1967 000000000000000087e50c87c40611df 3250b285c11ea98428bf61cd25cb1967 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzne.f64.f64 d1, d10 9d5e20798112db006efa0a4cd2cbfab8 b7f380100d6c27ae99200e7d3f7a3ba3 80000000000000006efa0a4cd2cbfab8 b7f380100d6c27ae99200e7d3f7a3ba3 fpscr=00000000
+vrintzne.f64.f64 d1, d10 ad85543119d367c24466e40c6c8a5ae5 4aa8ba44e58beaa24e5c12125403afc7 4e5c12125403afc74466e40c6c8a5ae5 4aa8ba44e58beaa24e5c12125403afc7 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzne.f64.f64 d1, d10 8f0c8a2330e7d9e58f0c8a2330e7d9e5 b4590c0c33befc81dd1328fff582518a dd1328fff582518a8f0c8a2330e7d9e5 b4590c0c33befc81dd1328fff582518a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 c0063b9f153d9a715ceda0676718006b bc986f66e849f5a7bc986f66e849f5a7 80000000000000005ceda0676718006b bc986f66e849f5a7bc986f66e849f5a7 fpscr=00000000
+vrintzne.f64.f64 d1, d10 ccf5ea603cd76ac81f4aeb27b92437ba f2e087a50cb268a28eb68cc46da8d47b 80000000000000001f4aeb27b92437ba f2e087a50cb268a28eb68cc46da8d47b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vrintz.f64.f64 d2, d11 4126e58b04e2117a4126e58b04e2117a 1d66fb90508d9b554cc88bd9417c3fde 4126e58b04e2117a0000000000000000 1d66fb90508d9b554cc88bd9417c3fde fpscr=00000000
+vrintz.f64.f64 d2, d11 1385230615cca44486d82cc5b652778e d1255cee5b7ff5a32c6188ced8f5a82f 1385230615cca444d1255cee5b7ff5a3 d1255cee5b7ff5a32c6188ced8f5a82f fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintz.f64.f64 d2, d11 6458cc3f2583a0d06458cc3f2583a0d0 a91030fb0fd6ad847a846bf8526da307 6458cc3f2583a0d08000000000000000 a91030fb0fd6ad847a846bf8526da307 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintz.f64.f64 d2, d11 533c9abbf1a2346d1898f8c916c78127 9896321a24700fe09896321a24700fe0 533c9abbf1a2346d8000000000000000 9896321a24700fe09896321a24700fe0 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintz.f64.f64 d2, d11 9d12483f33fd3e0b25adea9aa46156bb a7fecb16241b16507dd0dc4674f12d8e 9d12483f33fd3e0b8000000000000000 a7fecb16241b16507dd0dc4674f12d8e fpscr=00000000
+vrintz.f64.f64 d2, d11 dac42e831264fa33fa5f00e572723e87 bab9b5f090842789429a24ea168e8d2b dac42e831264fa338000000000000000 bab9b5f090842789429a24ea168e8d2b fpscr=00000000
+vrintz.f64.f64 d2, d11 be2881a7924ab2b2b41304878a5e399f 21183d7fc6677aae46a1db9de0e287f5 be2881a7924ab2b20000000000000000 21183d7fc6677aae46a1db9de0e287f5 fpscr=00000000
+vrintz.f64.f64 d2, d11 b554185c8b4730acd9cfb260b79b8c24 d72008703993a3364f35887e2724737d b554185c8b4730acd72008703993a336 d72008703993a3364f35887e2724737d fpscr=00000000
+vrintz.f64.f64 d2, d11 85cc1d8d0b3fee53b96b0882c7ba66a6 36c38a63566430f164401ff0290e2a14 85cc1d8d0b3fee530000000000000000 36c38a63566430f164401ff0290e2a14 fpscr=00000000
+vrintz.f64.f64 d2, d11 9aacd059be2f5244bbfa914cd7e9e89e 7f19fcc8135a26c603d67447d299c6b7 9aacd059be2f52447f19fcc8135a26c6 7f19fcc8135a26c603d67447d299c6b7 fpscr=00000000
+vrintz.f64.f64 d2, d11 7180b390457862f68a0104a6e5420ee2 3014f06070ef160a5109910dac15f7f6 7180b390457862f60000000000000000 3014f06070ef160a5109910dac15f7f6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintz.f64.f64 d2, d11 32a317fb088eb4fb32a317fb088eb4fb f35fe8b24c04913cf35fe8b24c04913c 32a317fb088eb4fbf35fe8b24c04913c f35fe8b24c04913cf35fe8b24c04913c fpscr=00000000
+vrintz.f64.f64 d2, d11 7bd77e115984f311f14e8dca281210d2 00e6c0f1df8d62ff1c80fb6c7103fb48 7bd77e115984f3110000000000000000 00e6c0f1df8d62ff1c80fb6c7103fb48 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintz.f64.f64 d2, d11 5a12390957466abb5a12390957466abb 03de4dd629b91eb970437d5fed910e6b 5a12390957466abb0000000000000000 03de4dd629b91eb970437d5fed910e6b fpscr=00000000
+vrintz.f64.f64 d2, d11 28668669a2b9eeb2691d4dc035f32bb1 e71de82ab385857cd60fd9c13b46d171 28668669a2b9eeb2e71de82ab385857c e71de82ab385857cd60fd9c13b46d171 fpscr=00000000
+vrintz.f64.f64 d2, d11 e1648c1992ddd5a36b908b2ecde06c46 4f91e03b46b21ae4c170d7f7d223d009 e1648c1992ddd5a34f91e03b46b21ae4 4f91e03b46b21ae4c170d7f7d223d009 fpscr=00000000
+vrintz.f64.f64 d2, d11 56e2f0137514104c2d54b72101284560 f345a626574a3b29d1d103ca0cff23a7 56e2f0137514104cf345a626574a3b29 f345a626574a3b29d1d103ca0cff23a7 fpscr=00000000
+vrintz.f64.f64 d2, d11 9348ed3707f1d7e161c25e115baa8cc4 9ac2a2053bad464b3833ccf866db853b 9348ed3707f1d7e18000000000000000 9ac2a2053bad464b3833ccf866db853b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintz.f64.f64 d2, d11 07f5fae7381a73aceb4b7a68d2ac7208 a734c38f3c9f5aa31f2300494155eaae 07f5fae7381a73ac8000000000000000 a734c38f3c9f5aa31f2300494155eaae fpscr=00000000
+vrintz.f64.f64 d2, d11 618ac9772a2770959500ac0e16c1e17f e008f5ed33ff4d999ba0ed42bdbe7e36 618ac9772a277095e008f5ed33ff4d99 e008f5ed33ff4d999ba0ed42bdbe7e36 fpscr=00000000
+vrintz.f64.f64 d2, d11 c2c3e7308522ae2cb5a9fb971f5dd4ff 041ebfb18a42e0c9d9b025982d597a93 c2c3e7308522ae2c0000000000000000 041ebfb18a42e0c9d9b025982d597a93 fpscr=00000000
+vrintz.f64.f64 d2, d11 9a437060904c189e956ae36a2ea58a5c f51a19be44a1098c3a2013ede0878f12 9a437060904c189ef51a19be44a1098c f51a19be44a1098c3a2013ede0878f12 fpscr=00000000
+vrintz.f64.f64 d2, d11 64e9e70044a6bb5f087ca71a71c14a90 28abb5bf7210839ef007103e5182ec3b 64e9e70044a6bb5f0000000000000000 28abb5bf7210839ef007103e5182ec3b fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintz.f64.f64 d2, d11 48ce928e2795f701340652530ab07605 7675d65f965c25c82b412e11f097a5aa 48ce928e2795f7017675d65f965c25c8 7675d65f965c25c82b412e11f097a5aa fpscr=00000000
+vrintz.f64.f64 d2, d11 48e522971eef5ebfce191b1b56d0f4ee 6234dbd360878142d79e1f36761095bf 48e522971eef5ebf6234dbd360878142 6234dbd360878142d79e1f36761095bf fpscr=00000000
+vrintz.f64.f64 d2, d11 e1e9179fc5babdee4527958a6948813a 1a1b57374cbc19cd1db80a139d59ffc8 e1e9179fc5babdee0000000000000000 1a1b57374cbc19cd1db80a139d59ffc8 fpscr=00000000
+vrintz.f64.f64 d2, d11 b0b1c88948b0c6183186fa1016b81832 2f30f438a37f4e7bc70b85821deba4c8 b0b1c88948b0c6180000000000000000 2f30f438a37f4e7bc70b85821deba4c8 fpscr=00000000
+vrintz.f64.f64 d2, d11 dd949e723328dbefc60b409ec367190e 7ed8353860809954ef33f256ddf389dd dd949e723328dbef7ed8353860809954 7ed8353860809954ef33f256ddf389dd fpscr=00000000
+vrintz.f64.f64 d2, d11 f26266f9856e5bc7844afd027c1ea31b 7da0dada6b38f74938251841c52f8d92 f26266f9856e5bc77da0dada6b38f749 7da0dada6b38f74938251841c52f8d92 fpscr=00000000
+vrintz.f64.f64 d2, d11 2b8c8246d46c77c8cebb0584e895f472 527c16bfdf6264db9f7f10384e28fc72 2b8c8246d46c77c8527c16bfdf6264db 527c16bfdf6264db9f7f10384e28fc72 fpscr=00000000
+vrintz.f64.f64 d2, d11 31c254b0164fb13dfe700d8787be3d49 4eaf6d86beb75b248b54f54a78f103a6 31c254b0164fb13d4eaf6d86beb75b24 4eaf6d86beb75b248b54f54a78f103a6 fpscr=00000000
+vrintz.f64.f64 d2, d11 d0ef974f8aab4c9113bf680bdd0b7c76 0ea749bc778f3e3dde3c658765b3b58a d0ef974f8aab4c910000000000000000 0ea749bc778f3e3dde3c658765b3b58a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintz.f64.f64 d2, d11 5d057ba5fd35eb12131739b0023c850f 14c6a2d3190a34149a562ae212ea95c9 5d057ba5fd35eb120000000000000000 14c6a2d3190a34149a562ae212ea95c9 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintz.f64.f64 d2, d11 54baa34ac9253344fdb8583482d8ab67 1cd4c5d4f02617e61cd4c5d4f02617e6 54baa34ac92533440000000000000000 1cd4c5d4f02617e61cd4c5d4f02617e6 fpscr=00000000
+vrintz.f64.f64 d2, d11 3e71e3ded34f1dd5723845e469ca15d2 d5e9ce20207b88975b45c938261e8df2 3e71e3ded34f1dd5d5e9ce20207b8897 d5e9ce20207b88975b45c938261e8df2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vrintz.f64.f64 d2, d11 67a40e26f17e185dfba2dc531ee9b1c4 8cfcb7084e499ac2936d586cc70fcfda 67a40e26f17e185d8000000000000000 8cfcb7084e499ac2936d586cc70fcfda fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vrintz.f64.f64 d2, d11 8720ad75cc4b53ce8720ad75cc4b53ce 08797ff851c4b2e197d888dd251c07ca 8720ad75cc4b53ce0000000000000000 08797ff851c4b2e197d888dd251c07ca fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintz.f64.f64 d2, d11 11b9edb14c5f4c5a11b9edb14c5f4c5a f771c49cf094a5a3f46e2cfefa3368da 11b9edb14c5f4c5af771c49cf094a5a3 f771c49cf094a5a3f46e2cfefa3368da fpscr=00000000
+vrintz.f64.f64 d2, d11 73a81ecc3ac47977bdd260ea993c6486 318fbb3ae6e0f3edb1bd641115f5e788 73a81ecc3ac479770000000000000000 318fbb3ae6e0f3edb1bd641115f5e788 fpscr=00000000
+vrintz.f64.f64 d2, d11 83fa7e97e92e65589242542f195baae2 96020adc013bee6768c4be80ed93d3bf 83fa7e97e92e65588000000000000000 96020adc013bee6768c4be80ed93d3bf fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintz.f64.f64 d2, d11 b026f31cb2724501ba7d28b15dc9b4a7 818fa179dc003e27818fa179dc003e27 b026f31cb27245018000000000000000 818fa179dc003e27818fa179dc003e27 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintz.f64.f64 d2, d11 733e104de1303e05733e104de1303e05 43e7908b771e1325102b71f09b537c8e 733e104de1303e0543e7908b771e1325 43e7908b771e1325102b71f09b537c8e fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintz.f64.f64 d2, d11 75b38269e502f923ed08e20cb82a6969 bc51395e556bdb02e8d569805d5de542 75b38269e502f9238000000000000000 bc51395e556bdb02e8d569805d5de542 fpscr=00000000
+vrintz.f64.f64 d2, d11 b697a706d47369fc5526b6708c5040ff 11730405849497c9ea7b5b1ca6b72715 b697a706d47369fc0000000000000000 11730405849497c9ea7b5b1ca6b72715 fpscr=00000000
+vrintz.f64.f64 d2, d11 348764ae0e5f2ee798194a935096371a 0aa922648fa3385b4f0d49a285cdedcc 348764ae0e5f2ee70000000000000000 0aa922648fa3385b4f0d49a285cdedcc fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintz.f64.f64 d2, d11 1eade9e382ef21302da68406dec165d9 bb8f22cb4b06f4a01fce07b9d693afc5 1eade9e382ef21308000000000000000 bb8f22cb4b06f4a01fce07b9d693afc5 fpscr=00000000
+vrintz.f64.f64 d2, d11 fe780629116b4efc512881bf2c0caf8f 2f0609a81cd9b901abd9b30d056120d3 fe780629116b4efc0000000000000000 2f0609a81cd9b901abd9b30d056120d3 fpscr=00000000
+vrintz.f64.f64 d2, d11 88f394f40c96461868763d39e55d1158 de184f45a03864962f7555ab7bcba39c 88f394f40c964618de184f45a0386496 de184f45a03864962f7555ab7bcba39c fpscr=00000000
+vrintz.f64.f64 d2, d11 817a9369f6f7efd2c18f32dba866cbc4 35c01f52f73aaf7224cb3328ee33ee6b 817a9369f6f7efd20000000000000000 35c01f52f73aaf7224cb3328ee33ee6b fpscr=00000000
+vrintz.f64.f64 d2, d11 f2e4236ddb99d47c898cc5cafec3abd2 10a94f03ca568fc049bab7921a9dd540 f2e4236ddb99d47c0000000000000000 10a94f03ca568fc049bab7921a9dd540 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vrintreq.f64.f64 d3, d12 8faabdf19497b150b95e3e4f2212f63d 1e273d4f3377c9851e273d4f3377c985 8faabdf19497b150b95e3e4f2212f63d 1e273d4f3377c9851e273d4f3377c985 fpscr=00000000
+vrintreq.f64.f64 d3, d12 5c28d090158bdf1653442add81137ef6 f2973ab32647b3c3967cb3c4f187a0b1 5c28d090158bdf1653442add81137ef6 f2973ab32647b3c3967cb3c4f187a0b1 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vrintreq.f64.f64 d3, d12 44581cab0d45dc8044581cab0d45dc80 558c3575f7fbfdc26b8e8d82ff078ef8 44581cab0d45dc8044581cab0d45dc80 558c3575f7fbfdc26b8e8d82ff078ef8 fpscr=00000000
+vrintreq.f64.f64 d3, d12 a5b2fb345d44dea9d02a524304178900 1bc750c664ecd959da25773f7e58f178 a5b2fb345d44dea9d02a524304178900 1bc750c664ecd959da25773f7e58f178 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintreq.f64.f64 d3, d12 ef4d9f5c013190559328cc55595d95de 2a53d417f8dec693dc12ea7e908ba7b2 ef4d9f5c013190559328cc55595d95de 2a53d417f8dec693dc12ea7e908ba7b2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: 7424 calls, 7662 iters
+vrintreq.f64.f64 d3, d12 e6d18d2b9025312df6d1d5557f1216b9 e3ee24e455a606bdbd1209330791f707 e6d18d2b9025312df6d1d5557f1216b9 e3ee24e455a606bdbd1209330791f707 fpscr=00000000
+vrintreq.f64.f64 d3, d12 75a7be4303bf46eb660c13529c5c4fdd c5eacdb8df2aa0add332b69436b6961a 75a7be4303bf46eb660c13529c5c4fdd c5eacdb8df2aa0add332b69436b6961a fpscr=00000000
+vrintreq.f64.f64 d3, d12 33174bf5bd39460967ea149ae992f68d 7e219d65f216aac2ba9b90d0ee63d559 33174bf5bd39460967ea149ae992f68d 7e219d65f216aac2ba9b90d0ee63d559 fpscr=00000000
+vrintreq.f64.f64 d3, d12 5511d528139f846ceb1c09a913102e3d f836e455636d667c1861f07fc80b1439 5511d528139f846ceb1c09a913102e3d f836e455636d667c1861f07fc80b1439 fpscr=00000000
+vrintreq.f64.f64 d3, d12 5c8cc6e9eacae8aa388fa662dfb0e683 5486b37f5e362b59c6b62e7496a900ce 5c8cc6e9eacae8aa388fa662dfb0e683 5486b37f5e362b59c6b62e7496a900ce fpscr=00000000
+vrintreq.f64.f64 d3, d12 a7296ddf9af9314d28f0684b08da562c 673a3b43536de399d9fbc17d59b8982a a7296ddf9af9314d28f0684b08da562c 673a3b43536de399d9fbc17d59b8982a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintreq.f64.f64 d3, d12 1ffa00c523e061348bc5fbf9b643fb0d 467f78553642be14467f78553642be14 1ffa00c523e061348bc5fbf9b643fb0d 467f78553642be14467f78553642be14 fpscr=00000000
+vrintreq.f64.f64 d3, d12 f3fc5449856d78007bb08e1bef6c5634 eab545a9d2deeb480d1ed55113a077b3 f3fc5449856d78007bb08e1bef6c5634 eab545a9d2deeb480d1ed55113a077b3 fpscr=00000000
+vrintreq.f64.f64 d3, d12 708971742a50f6f024ae096e2f9a32c9 98dad91a6e530094191c93d4073e1f7b 708971742a50f6f024ae096e2f9a32c9 98dad91a6e530094191c93d4073e1f7b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintreq.f64.f64 d3, d12 badfa5a78fb3d0b74d6c2319cdede505 1aa77712d4b4c92d1aa77712d4b4c92d badfa5a78fb3d0b74d6c2319cdede505 1aa77712d4b4c92d1aa77712d4b4c92d fpscr=00000000
+vrintreq.f64.f64 d3, d12 8b4b8eed2bcc2c126dee24eb90adada5 b960588477e22088f793cfbe185231e7 8b4b8eed2bcc2c126dee24eb90adada5 b960588477e22088f793cfbe185231e7 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintreq.f64.f64 d3, d12 d0f29ecff2fe5e7f5fc34f36b724e895 2f7bc25255d727bfe51a29d76a8da565 d0f29ecff2fe5e7f5fc34f36b724e895 2f7bc25255d727bfe51a29d76a8da565 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintreq.f64.f64 d3, d12 e0d27759e9fe106c33d3cba4ee659846 ca1da99bded6e9065041323840723f50 e0d27759e9fe106c33d3cba4ee659846 ca1da99bded6e9065041323840723f50 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintreq.f64.f64 d3, d12 27b164047ce462c7828f2f4c2860f0fd 7d7dd94364572c1174292b927858fa29 27b164047ce462c7828f2f4c2860f0fd 7d7dd94364572c1174292b927858fa29 fpscr=00000000
+vrintreq.f64.f64 d3, d12 b0082dc3c69ee2313bd1be34311d9e02 bd41af714d68879068ef6cdac64b1ae7 b0082dc3c69ee2313bd1be34311d9e02 bd41af714d68879068ef6cdac64b1ae7 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vrintreq.f64.f64 d3, d12 bb1d53139c0a1990bb1d53139c0a1990 649f8f54194d2db6649f8f54194d2db6 bb1d53139c0a1990bb1d53139c0a1990 649f8f54194d2db6649f8f54194d2db6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vrintreq.f64.f64 d3, d12 0c895c8d0d67d7200c895c8d0d67d720 07fce33ab8bc7465339ae49f2f6958d3 0c895c8d0d67d7200c895c8d0d67d720 07fce33ab8bc7465339ae49f2f6958d3 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintreq.f64.f64 d3, d12 a74e60526388d207a25f63e551506609 c650c10d513c2c67488e717eaabfc3f0 a74e60526388d207a25f63e551506609 c650c10d513c2c67488e717eaabfc3f0 fpscr=00000000
+vrintreq.f64.f64 d3, d12 f55e123863d3f97419dba241a82e2c66 a516a1fde031ec9149ac27de727705ee f55e123863d3f97419dba241a82e2c66 a516a1fde031ec9149ac27de727705ee fpscr=00000000
+vrintreq.f64.f64 d3, d12 6ef61084faa0f51ffdae1af25eee35ed 03f1397c09a98e5c92f8d11e01f01500 6ef61084faa0f51ffdae1af25eee35ed 03f1397c09a98e5c92f8d11e01f01500 fpscr=00000000
+vrintreq.f64.f64 d3, d12 ad43c8600dce5809960ed1cabb92180f f9b5add039e9a41968adc8587b453160 ad43c8600dce5809960ed1cabb92180f f9b5add039e9a41968adc8587b453160 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintreq.f64.f64 d3, d12 6a0feb007cd1028f58c89ca6d84094de e5e770d032c046060c676acc55af7ed4 6a0feb007cd1028f58c89ca6d84094de e5e770d032c046060c676acc55af7ed4 fpscr=00000000
+vrintreq.f64.f64 d3, d12 f5b11090304ec84a1f7cbe9f1042afc3 0831b515057d5b7aa6fed596d7a85cc8 f5b11090304ec84a1f7cbe9f1042afc3 0831b515057d5b7aa6fed596d7a85cc8 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintreq.f64.f64 d3, d12 16096e82f35c30ddcaf9bec45dcbd38e 9604a38c2a133ffb34e6e97d524ec496 16096e82f35c30ddcaf9bec45dcbd38e 9604a38c2a133ffb34e6e97d524ec496 fpscr=00000000
+vrintreq.f64.f64 d3, d12 426f5738877051541edd2061aef3b994 a1728ac66c7b51cf385e263e98079746 426f5738877051541edd2061aef3b994 a1728ac66c7b51cf385e263e98079746 fpscr=00000000
+vrintreq.f64.f64 d3, d12 2d9fdde41f278af0bfd0558bd001951a 9517bd5ecf292e45e418c206a0573864 2d9fdde41f278af0bfd0558bd001951a 9517bd5ecf292e45e418c206a0573864 fpscr=00000000
+vrintreq.f64.f64 d3, d12 aaad2c6cd69db03c0a45f33befe8e9d9 6e74c63d9680b3882706b153a745e4a6 aaad2c6cd69db03c0a45f33befe8e9d9 6e74c63d9680b3882706b153a745e4a6 fpscr=00000000
+vrintreq.f64.f64 d3, d12 61960e3ab665f7fd636f206661aaf2fa 1484a7dc9b634050acb2bc5ec0d0b4ed 61960e3ab665f7fd636f206661aaf2fa 1484a7dc9b634050acb2bc5ec0d0b4ed fpscr=00000000
+vrintreq.f64.f64 d3, d12 5964c04d5c373d7ad8b8487dce25e597 ee3667d58a999eac03b096f08ebf1234 5964c04d5c373d7ad8b8487dce25e597 ee3667d58a999eac03b096f08ebf1234 fpscr=00000000
+vrintreq.f64.f64 d3, d12 0c3b8f29e3718b49d1fc611bd784d114 b83cd26bf285ba285e0a74bda45a9582 0c3b8f29e3718b49d1fc611bd784d114 b83cd26bf285ba285e0a74bda45a9582 fpscr=00000000
+vrintreq.f64.f64 d3, d12 439ee80b79984ecf503c2cabca69ad7d 654579bf8be41a7e3bece3caf0b78aef 439ee80b79984ecf503c2cabca69ad7d 654579bf8be41a7e3bece3caf0b78aef fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintreq.f64.f64 d3, d12 df2058a73b75d5afe8448ecf294e419b 0b53741332f3fdef86326295a59724a1 df2058a73b75d5afe8448ecf294e419b 0b53741332f3fdef86326295a59724a1 fpscr=00000000
+vrintreq.f64.f64 d3, d12 56d4919969d945f7cb4e42dc12aa303b 76dfd463a0a526c5cbabaaed54342feb 56d4919969d945f7cb4e42dc12aa303b 76dfd463a0a526c5cbabaaed54342feb fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vrintreq.f64.f64 d3, d12 d23b47349af9c7003eaee16136adda59 c62d20c66dd3d34fc62d20c66dd3d34f d23b47349af9c7003eaee16136adda59 c62d20c66dd3d34fc62d20c66dd3d34f fpscr=00000000
+vrintreq.f64.f64 d3, d12 3ad8b53bea8c7acc298aa5c4c2f39a39 ca1850321439cd76090d78e043188995 3ad8b53bea8c7acc298aa5c4c2f39a39 ca1850321439cd76090d78e043188995 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintreq.f64.f64 d3, d12 a5fa129d6284935b70b1d4926e81819a f6897c938d7b590dfcad3fcdb4c99997 a5fa129d6284935b70b1d4926e81819a f6897c938d7b590dfcad3fcdb4c99997 fpscr=00000000
+vrintreq.f64.f64 d3, d12 57437d906598e26441a1713e13ba7cfc 9987f1510be55ba698d67298d4b13519 57437d906598e26441a1713e13ba7cfc 9987f1510be55ba698d67298d4b13519 fpscr=00000000
+vrintreq.f64.f64 d3, d12 2c21cf2cf04988211e143a37bedb5db6 c3a97fcf517f3dbfea0164b0fd72187f 2c21cf2cf04988211e143a37bedb5db6 c3a97fcf517f3dbfea0164b0fd72187f fpscr=00000000
+vrintreq.f64.f64 d3, d12 39481e46e3b180b5b86cb051d789af75 d99ebf25fbeb0042571dff0101163e0f 39481e46e3b180b5b86cb051d789af75 d99ebf25fbeb0042571dff0101163e0f fpscr=00000000
+vrintreq.f64.f64 d3, d12 0448a5ac0c635520b8460bd48f0fd480 16caeb8168de0b7457425dc60a4398f6 0448a5ac0c635520b8460bd48f0fd480 16caeb8168de0b7457425dc60a4398f6 fpscr=00000000
+vrintreq.f64.f64 d3, d12 cf677f55abe251b5c9c803e5893f4fe8 ac46d12b38f911155181faf4378df63c cf677f55abe251b5c9c803e5893f4fe8 ac46d12b38f911155181faf4378df63c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintreq.f64.f64 d3, d12 ae2b84f8a2cd7d52ea6df26051d70af6 3977d2dd6476b3d83977d2dd6476b3d8 ae2b84f8a2cd7d52ea6df26051d70af6 3977d2dd6476b3d83977d2dd6476b3d8 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintreq.f64.f64 d3, d12 ec15a7af6f3e0300835d7ef39c29ce07 04a2c27ba1735002afb58bc60145e391 ec15a7af6f3e0300835d7ef39c29ce07 04a2c27ba1735002afb58bc60145e391 fpscr=00000000
+vrintreq.f64.f64 d3, d12 aa8d78607f7779e492c236bc6eb364e4 8ab7f6cd19d0638cdf56622f3f5469d7 aa8d78607f7779e492c236bc6eb364e4 8ab7f6cd19d0638cdf56622f3f5469d7 fpscr=00000000
+vrintreq.f64.f64 d3, d12 2fd139573c4556adb6f8d66c3fafa7dc 908463a9294b4338acded0167f652a65 2fd139573c4556adb6f8d66c3fafa7dc 908463a9294b4338acded0167f652a65 fpscr=00000000
+vrintrne.f64.f64 d4, d13 2bb8000c125a817c09d77cf53b6dbdfa 808dd0d93bc51a8d3192c3a3d2300a63 2bb8000c125a817c8000000000000000 808dd0d93bc51a8d3192c3a3d2300a63 fpscr=00000000
+vrintrne.f64.f64 d4, d13 a76f5178886ddf5edf638f52f1a3ca99 8b6b8904ca5be55be6e62a6f036bd5ee a76f5178886ddf5e8000000000000000 8b6b8904ca5be55be6e62a6f036bd5ee fpscr=00000000
+vrintrne.f64.f64 d4, d13 b8d9f9582361c1915ca8e177744c423a 32b965542ba325970917d9b9f0c9f32f b8d9f9582361c1910000000000000000 32b965542ba325970917d9b9f0c9f32f fpscr=00000000
+vrintrne.f64.f64 d4, d13 4cd3ad825730a378844093e786c9e7b7 846690916818489917b985c59da30ad4 4cd3ad825730a3788000000000000000 846690916818489917b985c59da30ad4 fpscr=00000000
+vrintrne.f64.f64 d4, d13 dddb8aa1502cc9f02939ceabaa6aa7da ade3ad2274666f379f223517ae8b0a6c dddb8aa1502cc9f08000000000000000 ade3ad2274666f379f223517ae8b0a6c fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vrintrne.f64.f64 d4, d13 fa136d46a6a9bc09b65e63a70e555852 7abefd9338b68cac7abefd9338b68cac fa136d46a6a9bc097abefd9338b68cac 7abefd9338b68cac7abefd9338b68cac fpscr=00000000
+vrintrne.f64.f64 d4, d13 7ef94f9c8592b6ad395fe501a81bded6 1ed9069d1f3ff5c32305363409f6613a 7ef94f9c8592b6ad0000000000000000 1ed9069d1f3ff5c32305363409f6613a fpscr=00000000
+vrintrne.f64.f64 d4, d13 55f09fe02a4ef9abed0d01f99e382e33 7358285c6dd59168b268880b7093e28f 55f09fe02a4ef9ab7358285c6dd59168 7358285c6dd59168b268880b7093e28f fpscr=00000000
+vrintrne.f64.f64 d4, d13 91501f1ae5cbac08a9db9c8bab0a76d0 3dd48ec36077c5dd8a5cea24ed1eb4f6 91501f1ae5cbac080000000000000000 3dd48ec36077c5dd8a5cea24ed1eb4f6 fpscr=00000000
+vrintrne.f64.f64 d4, d13 42da6412dfe2c43d87543f07ddff189b 2333e930f6e9476801e1295dd55073b1 42da6412dfe2c43d0000000000000000 2333e930f6e9476801e1295dd55073b1 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintrne.f64.f64 d4, d13 8f8cefdbb45835275cf85d9c1beb393c abe51dfab674b1bcabe51dfab674b1bc 8f8cefdbb45835278000000000000000 abe51dfab674b1bcabe51dfab674b1bc fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintrne.f64.f64 d4, d13 59e012c0da77fa94be4f5490493eeaf0 00897e8997ab532e00897e8997ab532e 59e012c0da77fa940000000000000000 00897e8997ab532e00897e8997ab532e fpscr=00000000
+vrintrne.f64.f64 d4, d13 337e56e4b2dec726c2fa384ef35b147b 31fb003f08ade43bb1ff81fa1a4107e4 337e56e4b2dec7260000000000000000 31fb003f08ade43bb1ff81fa1a4107e4 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintrne.f64.f64 d4, d13 403684a4f5ab034bdecc686f57f1fe14 5e4aa7b008b4d9e02992ba2f7de8d48b 403684a4f5ab034b5e4aa7b008b4d9e0 5e4aa7b008b4d9e02992ba2f7de8d48b fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintrne.f64.f64 d4, d13 4e219d84604815b3e2cdf7f948ef138e b4323e355621ccc3c395d344caf3c099 4e219d84604815b38000000000000000 b4323e355621ccc3c395d344caf3c099 fpscr=00000000
+vrintrne.f64.f64 d4, d13 f0710cb4d5ad2028f77d7d70d9e61f60 3e7744e2e570c4a636f53b3f0dcb6b89 f0710cb4d5ad20280000000000000000 3e7744e2e570c4a636f53b3f0dcb6b89 fpscr=00000000
+vrintrne.f64.f64 d4, d13 501cfdd122c46c76e8d0897f8b71e87a 5f66910535b517667976d7163bfa886c 501cfdd122c46c765f66910535b51766 5f66910535b517667976d7163bfa886c fpscr=00000000
+vrintrne.f64.f64 d4, d13 a2041c9913bf7f828aaac2f28c0834c1 b18265a0d83ef4380b82357abee438e0 a2041c9913bf7f828000000000000000 b18265a0d83ef4380b82357abee438e0 fpscr=00000000
+vrintrne.f64.f64 d4, d13 1bc7634e4c91b02f71346d7a88047007 a01230a0d7e4e94b1e8a60f1a03d7f7d 1bc7634e4c91b02f8000000000000000 a01230a0d7e4e94b1e8a60f1a03d7f7d fpscr=00000000
+randV128: 7680 calls, 7927 iters
+vrintrne.f64.f64 d4, d13 46d5cfdb7a63001b580d8779cc5b2a99 0d826f0b5ee27312980014d210acb690 46d5cfdb7a63001b0000000000000000 0d826f0b5ee27312980014d210acb690 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintrne.f64.f64 d4, d13 01d77486fe17d17262ee15ec27590158 56f08c97ebfcff786513dc15d436c795 01d77486fe17d17256f08c97ebfcff78 56f08c97ebfcff786513dc15d436c795 fpscr=00000000
+vrintrne.f64.f64 d4, d13 044b0a6be7e2f27ceba1fd97c425e23b 07dfc60c440b9b9d5806c4789fdd138c 044b0a6be7e2f27c0000000000000000 07dfc60c440b9b9d5806c4789fdd138c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintrne.f64.f64 d4, d13 848aa7cd15a0503d848aa7cd15a0503d 389464c2f8f35d8a220add60f775cfc4 848aa7cd15a0503d0000000000000000 389464c2f8f35d8a220add60f775cfc4 fpscr=00000000
+vrintrne.f64.f64 d4, d13 a8ee0f4b7f0cf658f30c524629efa7bb 7883c11e6adad5e2bfbd10f8c2259439 a8ee0f4b7f0cf6587883c11e6adad5e2 7883c11e6adad5e2bfbd10f8c2259439 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintrne.f64.f64 d4, d13 a00bca34047f4cd33c7d91764d85a625 a941cff4e0b9dacf150c42673f7db245 a00bca34047f4cd38000000000000000 a941cff4e0b9dacf150c42673f7db245 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintrne.f64.f64 d4, d13 8fbe2a17898cb15a9322d074db2374ff b18e0bf13047ca63b18e0bf13047ca63 8fbe2a17898cb15a8000000000000000 b18e0bf13047ca63b18e0bf13047ca63 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintrne.f64.f64 d4, d13 9052b1941fee5d419052b1941fee5d41 78885bbe0d7260926a150ae3f4914cc5 9052b1941fee5d4178885bbe0d726092 78885bbe0d7260926a150ae3f4914cc5 fpscr=00000000
+vrintrne.f64.f64 d4, d13 0a3b54f24252878eccb7d6d7f2f6cf41 f2f97dd98cb58ae5db2679a0fd9e7c01 0a3b54f24252878ef2f97dd98cb58ae5 f2f97dd98cb58ae5db2679a0fd9e7c01 fpscr=00000000
+vrintrne.f64.f64 d4, d13 a256ba2e16d4887afb3f935e5ffe1021 b1d357f39cf2432678493db4d19a97a0 a256ba2e16d4887a8000000000000000 b1d357f39cf2432678493db4d19a97a0 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintrne.f64.f64 d4, d13 aa52b691549fbe858ab7cb901aa3538a f68ab21956b50fea8491c2821e134e2b aa52b691549fbe85f68ab21956b50fea f68ab21956b50fea8491c2821e134e2b fpscr=00000000
+vrintrne.f64.f64 d4, d13 68859814bc2f29ebe86d548f89fd050a 06abc0ad581d207accdbcb99d5ba495c 68859814bc2f29eb0000000000000000 06abc0ad581d207accdbcb99d5ba495c fpscr=00000000
+vrintrne.f64.f64 d4, d13 aacd45b23dae67ff55ee04e1e742d0b6 f7a75f3dedb9486eaf3dee9f98e57530 aacd45b23dae67fff7a75f3dedb9486e f7a75f3dedb9486eaf3dee9f98e57530 fpscr=00000000
+vrintrne.f64.f64 d4, d13 870fbcf765fb8709ee9ad13fbcec9a96 d6e8fc1410802fc7b69d6d0174a35337 870fbcf765fb8709d6e8fc1410802fc7 d6e8fc1410802fc7b69d6d0174a35337 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintrne.f64.f64 d4, d13 cb34000d5cabb435cb34000d5cabb435 cd108f59527580861e3de18f437b6141 cb34000d5cabb435cd108f5952758086 cd108f59527580861e3de18f437b6141 fpscr=00000000
+vrintrne.f64.f64 d4, d13 7a568c74620b1dc5c35f438b1793371f 84de9f29455d2a188c161e8516e24ff7 7a568c74620b1dc58000000000000000 84de9f29455d2a188c161e8516e24ff7 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintrne.f64.f64 d4, d13 044565123ec677f5044565123ec677f5 4d5eb546485a8e234d5eb546485a8e23 044565123ec677f54d5eb546485a8e23 4d5eb546485a8e234d5eb546485a8e23 fpscr=00000000
+vrintrne.f64.f64 d4, d13 0d5f0deaa327a3681f7e714f53e5c994 77b05bec059012f1cead9f5201e15a14 0d5f0deaa327a36877b05bec059012f1 77b05bec059012f1cead9f5201e15a14 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintrne.f64.f64 d4, d13 518d0e3ebcf785f83e92acd253f7cd99 c221fd898874baf9cedd83b66e67730b 518d0e3ebcf785f8c221fd8988740000 c221fd898874baf9cedd83b66e67730b fpscr=00000000
+vrintrne.f64.f64 d4, d13 b030c2f9fad2e4c09ce73c6226d44682 4bae058dc7320df8ca32636e2f6f0c07 b030c2f9fad2e4c04bae058dc7320df8 4bae058dc7320df8ca32636e2f6f0c07 fpscr=00000000
+vrintrne.f64.f64 d4, d13 879bc0440fa1b72920018d3bae9d6209 fea88f1cfbcb9c44261baab3b7c464ee 879bc0440fa1b729fea88f1cfbcb9c44 fea88f1cfbcb9c44261baab3b7c464ee fpscr=00000000
+vrintrne.f64.f64 d4, d13 0170a7405c4ff2641cb04979c8a9d4a0 683fcad0a6671370780f2a4f3d7e9744 0170a7405c4ff264683fcad0a6671370 683fcad0a6671370780f2a4f3d7e9744 fpscr=00000000
+vrintrne.f64.f64 d4, d13 39358bf5c9e6772ace877e9ab8be5648 7d6ee9b05fd55119f1bbf356235a0e8e 39358bf5c9e6772a7d6ee9b05fd55119 7d6ee9b05fd55119f1bbf356235a0e8e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintrne.f64.f64 d4, d13 8ba9e1102de36806fb273f7fbda44446 a668315b7f4c02d52f4dfc12408490ad 8ba9e1102de368068000000000000000 a668315b7f4c02d52f4dfc12408490ad fpscr=00000000
+vrintrne.f64.f64 d4, d13 a93988289bf3a2495680845a288c3a01 a8f73cea65c63a27fd64351d3fb2f03a a93988289bf3a2498000000000000000 a8f73cea65c63a27fd64351d3fb2f03a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintrne.f64.f64 d4, d13 9468f57e32f223819468f57e32f22381 569887088f658df7c31f54db238eff42 9468f57e32f22381569887088f658df7 569887088f658df7c31f54db238eff42 fpscr=00000000
+vrintrne.f64.f64 d4, d13 5d806ae803e5c525e3a1c97fd978c788 1865b9cf9a622125fc220836beec7ec8 5d806ae803e5c5250000000000000000 1865b9cf9a622125fc220836beec7ec8 fpscr=00000000
+vrintrne.f64.f64 d4, d13 401990cf151c7f4da2c476be7da12afa ec8869e8e1097b1aca8ef99a4fe2aa1e 401990cf151c7f4dec8869e8e1097b1a ec8869e8e1097b1aca8ef99a4fe2aa1e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintrne.f64.f64 d4, d13 86d48fd6f985127d943461254a29e745 70bd5f21d73e984470bd5f21d73e9844 86d48fd6f985127d70bd5f21d73e9844 70bd5f21d73e984470bd5f21d73e9844 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintrne.f64.f64 d4, d13 0829eee569b2f8230829eee569b2f823 ee58238e8d54116de6834db0f029a9b0 0829eee569b2f823ee58238e8d54116d ee58238e8d54116de6834db0f029a9b0 fpscr=00000000
+vrintrne.f64.f64 d4, d13 f1d28096033415e976b518a51db2c16f 234303ce9f64bf98a05b41c3a69823b2 f1d28096033415e90000000000000000 234303ce9f64bf98a05b41c3a69823b2 fpscr=00000000
+vrintr.f64.f64 d5, d14 c7cf036df53b712ad2604abc5a05b647 0f250b4007a9ba23c0e67cecde3a3c76 c0e67ce000000000d2604abc5a05b647 0f250b4007a9ba23c0e67cecde3a3c76 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintr.f64.f64 d5, d14 d1636652f0b18328144363b7c0f531c0 84168ffba70f689661e3a970b2beba6b 61e3a970b2beba6b144363b7c0f531c0 84168ffba70f689661e3a970b2beba6b fpscr=00000000
+vrintr.f64.f64 d5, d14 95d4ccdaf659001572fff3271262304b cca93dc66d36685ec38a1c0c737492d0 c38a1c0c737492d072fff3271262304b cca93dc66d36685ec38a1c0c737492d0 fpscr=00000000
+vrintr.f64.f64 d5, d14 b8f952ad7486ef3c6b56a6b27b10af93 035d89fbc7117bd2ae91efd57a0ecdfa 80000000000000006b56a6b27b10af93 035d89fbc7117bd2ae91efd57a0ecdfa fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintr.f64.f64 d5, d14 ec29093fabfea59bec29093fabfea59b 9fab4a3e48f1134503a1b00a810ca82f 0000000000000000ec29093fabfea59b 9fab4a3e48f1134503a1b00a810ca82f fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintr.f64.f64 d5, d14 53bbef63d4f373652b65f5ea900fdc1c a2c603e15a9198b3185209cccb52ea73 00000000000000002b65f5ea900fdc1c a2c603e15a9198b3185209cccb52ea73 fpscr=00000000
+vrintr.f64.f64 d5, d14 d142efd22e668948b3111b74160b2fe5 544388650be1629a3ed0300021b61c7d 0000000000000000b3111b74160b2fe5 544388650be1629a3ed0300021b61c7d fpscr=00000000
+vrintr.f64.f64 d5, d14 25b5522436c757ca19058daf59e112f9 bbda94f04d0ae894c6f4e274691a7fd6 c6f4e274691a7fd619058daf59e112f9 bbda94f04d0ae894c6f4e274691a7fd6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintr.f64.f64 d5, d14 9faaf466e142b109d9bb6c3216ec3e4e 7196fb59b964e5b463880e2688108234 63880e2688108234d9bb6c3216ec3e4e 7196fb59b964e5b463880e2688108234 fpscr=00000000
+vrintr.f64.f64 d5, d14 9baa14631bf69d5bfdb214a3b9153f0e e4d140e502acde9ef977706a31b89b27 f977706a31b89b27fdb214a3b9153f0e e4d140e502acde9ef977706a31b89b27 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintr.f64.f64 d5, d14 f0ee2c429eefc86cf0ee2c429eefc86c 3051d7286469671f791bb4b7b856b6b7 791bb4b7b856b6b7f0ee2c429eefc86c 3051d7286469671f791bb4b7b856b6b7 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintr.f64.f64 d5, d14 a32f5d61564ee0f3400ae6cb833141e7 e419853ca193083c74280d6807322ff4 74280d6807322ff4400ae6cb833141e7 e419853ca193083c74280d6807322ff4 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintr.f64.f64 d5, d14 7c0348b78eb37c7b7c0348b78eb37c7b dea0ce85e9db944a5d4d32bddffc2fa4 5d4d32bddffc2fa47c0348b78eb37c7b dea0ce85e9db944a5d4d32bddffc2fa4 fpscr=00000000
+vrintr.f64.f64 d5, d14 6cac401bf0a95a8640a3f76654edf5ba dbd57e02c16248aac136d4907a173bd0 c136d4900000000040a3f76654edf5ba dbd57e02c16248aac136d4907a173bd0 fpscr=00000000
+vrintr.f64.f64 d5, d14 55015443c3dff071b960c438f85c7c4c 45ef59dd67b1f649b454aa9c72733786 8000000000000000b960c438f85c7c4c 45ef59dd67b1f649b454aa9c72733786 fpscr=00000000
+vrintr.f64.f64 d5, d14 731d0c1de8e32b29e029949e9b88a40b 400eb0ffc092090bf7cbdd3d1758543d f7cbdd3d1758543de029949e9b88a40b 400eb0ffc092090bf7cbdd3d1758543d fpscr=00000000
+vrintr.f64.f64 d5, d14 89f7b7bb7905670397620da3ed0492bd b76dd6dd3d3a5b8c2d6ebd8d10327c24 000000000000000097620da3ed0492bd b76dd6dd3d3a5b8c2d6ebd8d10327c24 fpscr=00000000
+vrintr.f64.f64 d5, d14 37ae4e266cca7801e458763bafce187a f3592ca24df6f39660c70e83aabf9668 60c70e83aabf9668e458763bafce187a f3592ca24df6f39660c70e83aabf9668 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintr.f64.f64 d5, d14 3c351c902cc58863dde6ba3c4900e43d 4b438b040737889bb1293e9c083e2671 8000000000000000dde6ba3c4900e43d 4b438b040737889bb1293e9c083e2671 fpscr=00000000
+vrintr.f64.f64 d5, d14 1b018c410a4ff07f8dd09a92713eeb22 a905062f6f7f5cb8a05f17c7b1bb0bb1 80000000000000008dd09a92713eeb22 a905062f6f7f5cb8a05f17c7b1bb0bb1 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vrintr.f64.f64 d5, d14 e2bb6b5bf2ab8fbce2bb6b5bf2ab8fbc 366ecb91520d88ce4242917130fd5750 4242917130fd8000e2bb6b5bf2ab8fbc 366ecb91520d88ce4242917130fd5750 fpscr=00000000
+vrintr.f64.f64 d5, d14 4526f212b5ac7cebf0223aec026528f9 5e027e651cf114e102e4bd3376c76724 0000000000000000f0223aec026528f9 5e027e651cf114e102e4bd3376c76724 fpscr=00000000
+vrintr.f64.f64 d5, d14 d2d4b3c3dc9f77306ff161bcc49ffd54 977fbc50f1354e01f27be8de3d759706 f27be8de3d7597066ff161bcc49ffd54 977fbc50f1354e01f27be8de3d759706 fpscr=00000000
+vrintr.f64.f64 d5, d14 253f6500cdead09216f96c125db279db c51286743711e334358259c524320f44 000000000000000016f96c125db279db c51286743711e334358259c524320f44 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintr.f64.f64 d5, d14 99085c5bd397b11799085c5bd397b117 ccb784a19f830c0cbfad9e6deabe8bcb 800000000000000099085c5bd397b117 ccb784a19f830c0cbfad9e6deabe8bcb fpscr=00000000
+vrintr.f64.f64 d5, d14 cd52ef9d4419a6dbd0d062794548168f 87248dfee158b2885ceb905ddee92c71 5ceb905ddee92c71d0d062794548168f 87248dfee158b2885ceb905ddee92c71 fpscr=00000000
+vrintr.f64.f64 d5, d14 0942fe1a43ebcd96c09c2440b4e1afcd 5d3f68b77e96e9b6a878f4346495b1e4 8000000000000000c09c2440b4e1afcd 5d3f68b77e96e9b6a878f4346495b1e4 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintr.f64.f64 d5, d14 feb4464ae3fb4f79feb4464ae3fb4f79 4ad3187a1b1b534787c2aa279e624e86 8000000000000000feb4464ae3fb4f79 4ad3187a1b1b534787c2aa279e624e86 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintr.f64.f64 d5, d14 4e55d3dc3fceb9315adb2e4c18627584 3f8381041239787db70d9f9809a0556b 80000000000000005adb2e4c18627584 3f8381041239787db70d9f9809a0556b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintr.f64.f64 d5, d14 581f5b2f0361cdbe581f5b2f0361cdbe 6da282fdb8db1b2e1610a860ac5ee2f3 0000000000000000581f5b2f0361cdbe 6da282fdb8db1b2e1610a860ac5ee2f3 fpscr=00000000
+vrintr.f64.f64 d5, d14 14bd5cacd566c416ebb1e76368ee2846 8305908645ae9ccea6ce98443b36b193 8000000000000000ebb1e76368ee2846 8305908645ae9ccea6ce98443b36b193 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintr.f64.f64 d5, d14 6e684ccf7d309eda9fb2ab1515d08f9c 28de38244daee7592728af22d612386e 00000000000000009fb2ab1515d08f9c 28de38244daee7592728af22d612386e fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintr.f64.f64 d5, d14 6c027b9999997f3f6c027b9999997f3f 29527c1d7cd2cc7c347c3b876f29a4a3 00000000000000006c027b9999997f3f 29527c1d7cd2cc7c347c3b876f29a4a3 fpscr=00000000
+randV128: 7936 calls, 8186 iters
+vrintr.f64.f64 d5, d14 edebc5a4f182e642d37e09628252945e ded85716faa6e741200819b713e1c33a 0000000000000000d37e09628252945e ded85716faa6e741200819b713e1c33a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintr.f64.f64 d5, d14 f21fd8cc4f7ff2c977bcea82efb57dac 893a008268ad1699b26252abf5d82099 800000000000000077bcea82efb57dac 893a008268ad1699b26252abf5d82099 fpscr=00000000
+vrintr.f64.f64 d5, d14 681e3b5b234103c291af3fb331c20b9d c8cd8173235543b52cb7a4de4f79dbc0 000000000000000091af3fb331c20b9d c8cd8173235543b52cb7a4de4f79dbc0 fpscr=00000000
+vrintr.f64.f64 d5, d14 1c076b5897aad1b3c9ddd5539cd4503f 224bcf549761646e45fd74140298b51d 45fd74140298b51dc9ddd5539cd4503f 224bcf549761646e45fd74140298b51d fpscr=00000000
+vrintr.f64.f64 d5, d14 bf931db576f97906ce564d5caa53efdf 61d323b2da9eca4f06f64086d258d873 0000000000000000ce564d5caa53efdf 61d323b2da9eca4f06f64086d258d873 fpscr=00000000
+vrintr.f64.f64 d5, d14 45ceb2ca0a9cbff56711cc1cef838fb6 c46400c75ae3ff3f27ff4345756c749c 00000000000000006711cc1cef838fb6 c46400c75ae3ff3f27ff4345756c749c fpscr=00000000
+vrintr.f64.f64 d5, d14 a26091a7a6b6b17a5a32e311cfb042f9 b06ed98edc0c1ca83fef3f876a509a18 3ff00000000000005a32e311cfb042f9 b06ed98edc0c1ca83fef3f876a509a18 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vrintr.f64.f64 d5, d14 6f30a6d0796542af6f30a6d0796542af 1cf74d043dc1ac491cf74d043dc1ac49 00000000000000006f30a6d0796542af 1cf74d043dc1ac491cf74d043dc1ac49 fpscr=00000000
+vrintr.f64.f64 d5, d14 a5609c8d6d519db3534a7e6cc4503d64 28061d843bfb0fbb46d377e655b43849 46d377e655b43849534a7e6cc4503d64 28061d843bfb0fbb46d377e655b43849 fpscr=00000000
+vrintr.f64.f64 d5, d14 034f9479bd2b4840fd6e45eedd30c119 90dbab155efeec62c1dc1372d315ff4b c1dc1372d3000000fd6e45eedd30c119 90dbab155efeec62c1dc1372d315ff4b fpscr=00000000
+vrintr.f64.f64 d5, d14 078b253cc3f4c778e96d2e02234b59f4 f001b246d7bbe2cca2c1cb702f8bf00b 8000000000000000e96d2e02234b59f4 f001b246d7bbe2cca2c1cb702f8bf00b fpscr=00000000
+vrintr.f64.f64 d5, d14 477f15f9b9da998514251fc255311a8f bb0a7c06540b6675a13a63e6fe70fa82 800000000000000014251fc255311a8f bb0a7c06540b6675a13a63e6fe70fa82 fpscr=00000000
+vrintr.f64.f64 d5, d14 3bec53b1f7707a4cbddbdbf1a4f9c1d8 24d165d2b8810227591424ed93279590 591424ed93279590bddbdbf1a4f9c1d8 24d165d2b8810227591424ed93279590 fpscr=00000000
+vrintr.f64.f64 d5, d14 a04818c58d01eb628807f1995be4d96a e15de7046b9c961b75b06571d010a1b9 75b06571d010a1b98807f1995be4d96a e15de7046b9c961b75b06571d010a1b9 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintr.f64.f64 d5, d14 5dbf3867055dddbac51aaabb5823d9c2 82a58423d4f8864482a58423d4f88644 8000000000000000c51aaabb5823d9c2 82a58423d4f8864482a58423d4f88644 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintr.f64.f64 d5, d14 4c0d4bb3b84401975e5ccb07b7b33fe7 e86c92c537ec535c93afba3d3fd0c240 80000000000000005e5ccb07b7b33fe7 e86c92c537ec535c93afba3d3fd0c240 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintr.f64.f64 d5, d14 623d6493fb6cebe8c9cb2ba1120313bd 5ad5a24e88f0fbb15ad5a24e88f0fbb1 5ad5a24e88f0fbb1c9cb2ba1120313bd 5ad5a24e88f0fbb15ad5a24e88f0fbb1 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 9fdddfc98cedc34cf26cbdd053636547 5603d7762626b1389e5067719c25e928 9fdddfc98cedc34cf26cbdd053636547 5603d7762626b1389e5067719c25e928 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 7e73d5fe512a26007e73d5fe512a2600 6528daa4530293262a4854ebaeb9b199 7e73d5fe512a26007e73d5fe512a2600 6528daa4530293262a4854ebaeb9b199 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 5c00f87c073ca5df7e24f28de955c9e2 a5bcbbb92b4cf1dbaaeffe9d12f7310d 5c00f87c073ca5df7e24f28de955c9e2 a5bcbbb92b4cf1dbaaeffe9d12f7310d fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 f53f350dcb8118b1f53f350dcb8118b1 cdb58e6f81a4f30bdbb176a17af6fc41 f53f350dcb8118b1f53f350dcb8118b1 cdb58e6f81a4f30bdbb176a17af6fc41 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 f825348ce754d8295a79ed75cc2978c3 67db9e19f6d44c36abffb6129a3ff778 f825348ce754d8295a79ed75cc2978c3 67db9e19f6d44c36abffb6129a3ff778 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 2f679302f7fff43f4076020a62b1bf41 dd308b502ea0a8bbbe42164c46828732 2f679302f7fff43f4076020a62b1bf41 dd308b502ea0a8bbbe42164c46828732 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 12318e45cc60e2a752b5526ce1f9efcc 704a5927204d2d4a325681997ca3045e 12318e45cc60e2a752b5526ce1f9efcc 704a5927204d2d4a325681997ca3045e fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 27fa30aa884ee74e82d24027b79714dd f34baa4d361af822dd3cc3c6d8df41f8 27fa30aa884ee74e82d24027b79714dd f34baa4d361af822dd3cc3c6d8df41f8 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 90be4e98954fa902c38e207b2b7bbe0c d1767539330f0ed158503525e4016972 90be4e98954fa902c38e207b2b7bbe0c d1767539330f0ed158503525e4016972 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxeq.f64.f64 d6, d15 48df279b0bbff81748df279b0bbff817 da7b95b68c15f9e2342da868efbd4f83 48df279b0bbff81748df279b0bbff817 da7b95b68c15f9e2342da868efbd4f83 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 bf94c2782dd80f67561dbe8f98bb3b9d 4a806ee10f3fca677b53c497750d4d8a bf94c2782dd80f67561dbe8f98bb3b9d 4a806ee10f3fca677b53c497750d4d8a fpscr=00000000
+vrintxeq.f64.f64 d6, d15 7645fe8674beeeabc83cadbe8b04940a 1f1d052540408ccfdd58ce5627523165 7645fe8674beeeabc83cadbe8b04940a 1f1d052540408ccfdd58ce5627523165 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 6f1eab11c97024213cad662001d691f9 521716f18779a76e6fad67e1262782e3 6f1eab11c97024213cad662001d691f9 521716f18779a76e6fad67e1262782e3 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 0bc46f310c6cca2b65ae5c1d78408ab7 55afbf8ec79397aca437d523b524df77 0bc46f310c6cca2b65ae5c1d78408ab7 55afbf8ec79397aca437d523b524df77 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 07d4f1a46475595089fb20a4abdf0758 d39c8da5421417275086517857b66ea1 07d4f1a46475595089fb20a4abdf0758 d39c8da5421417275086517857b66ea1 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxeq.f64.f64 d6, d15 56514a09b626b09a937501aa44ab105a 53636a20525c313c826835d6cd5024b4 56514a09b626b09a937501aa44ab105a 53636a20525c313c826835d6cd5024b4 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 fb1d52f0c1ff78607dd790b4148af8a3 02c4ad076a760af42eed41e00a4ff308 fb1d52f0c1ff78607dd790b4148af8a3 02c4ad076a760af42eed41e00a4ff308 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxeq.f64.f64 d6, d15 3f765647f722ec95feb37b799b3cf560 d6bf70247b4db14560262f7e75fc8087 3f765647f722ec95feb37b799b3cf560 d6bf70247b4db14560262f7e75fc8087 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxeq.f64.f64 d6, d15 3fa2621faeeeb1da3fa2621faeeeb1da 1f13af32de563d860642900504bffd56 3fa2621faeeeb1da3fa2621faeeeb1da 1f13af32de563d860642900504bffd56 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxeq.f64.f64 d6, d15 3734504153f58d1109d9b8e3c5ea687e 92c6a7c92b31f16bf839d3e10ae6629c 3734504153f58d1109d9b8e3c5ea687e 92c6a7c92b31f16bf839d3e10ae6629c fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 4a165e7933af8a6d4a165e7933af8a6d 3dc6babb215621d5cab9427bafc67d2d 4a165e7933af8a6d4a165e7933af8a6d 3dc6babb215621d5cab9427bafc67d2d fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 c49ca98e742dbacdc49ca98e742dbacd 234c08fd75f8b2254c9162e9222503df c49ca98e742dbacdc49ca98e742dbacd 234c08fd75f8b2254c9162e9222503df fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 632173feee3c645b632173feee3c645b 644336f1f89ebfc73a4ca59d47f71131 632173feee3c645b632173feee3c645b 644336f1f89ebfc73a4ca59d47f71131 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 bbcf152b991da773bbcf152b991da773 9aedea40996f50d29aedea40996f50d2 bbcf152b991da773bbcf152b991da773 9aedea40996f50d29aedea40996f50d2 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 17da099240ecf3df6509aa6414257d45 4a976e0b5f48cbe084e614a5b9e2e3db 17da099240ecf3df6509aa6414257d45 4a976e0b5f48cbe084e614a5b9e2e3db fpscr=00000000
+vrintxeq.f64.f64 d6, d15 575ac7f98349fb67aae06e334208d0fe 589c263d76ed21bc5b74ee1e45d5854b 575ac7f98349fb67aae06e334208d0fe 589c263d76ed21bc5b74ee1e45d5854b fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 9af79c8e037c70516a6e9cdaaff469ff 9ef4a3944df3c9d49ef4a3944df3c9d4 9af79c8e037c70516a6e9cdaaff469ff 9ef4a3944df3c9d49ef4a3944df3c9d4 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 7395a6bbe31716cb78e8c8aab62daaa8 ab5052451e0d74e776296d47a2f8228e 7395a6bbe31716cb78e8c8aab62daaa8 ab5052451e0d74e776296d47a2f8228e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vrintxeq.f64.f64 d6, d15 35df52dd395b5564e43fb140cab5fb34 523e46b870bec885523e46b870bec885 35df52dd395b5564e43fb140cab5fb34 523e46b870bec885523e46b870bec885 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 026ca90693fc6583dc4ba1f9e4a13d51 469676575afcde6353320bf3ab4a56e7 026ca90693fc6583dc4ba1f9e4a13d51 469676575afcde6353320bf3ab4a56e7 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 498b43c7c3a7f4130bc7a4df785044b4 47526f4aade6a2828b4c7e29034a825b 498b43c7c3a7f4130bc7a4df785044b4 47526f4aade6a2828b4c7e29034a825b fpscr=00000000
+vrintxeq.f64.f64 d6, d15 8b6db5dd9cc52b456259c5434a5ac3e0 c5c18507a358e55ccf2bbc8b97fcdfa7 8b6db5dd9cc52b456259c5434a5ac3e0 c5c18507a358e55ccf2bbc8b97fcdfa7 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 6be03ddd55aa6275a2e4ff253e627c77 19508a18e4bd02bf56aa38328ac5a5d3 6be03ddd55aa6275a2e4ff253e627c77 19508a18e4bd02bf56aa38328ac5a5d3 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 153eb9c3fa624dc7091ac18dbbc82047 368dcb81b766872cd8ba2a8242a8482d 153eb9c3fa624dc7091ac18dbbc82047 368dcb81b766872cd8ba2a8242a8482d fpscr=00000000
+vrintxeq.f64.f64 d6, d15 b0f5ac4f7a659ea30845342f069d3306 6c172942df2661fc8993ddf18218ddaf b0f5ac4f7a659ea30845342f069d3306 6c172942df2661fc8993ddf18218ddaf fpscr=00000000
+vrintxeq.f64.f64 d6, d15 38fba740241f101855fbe1dff56954f4 00feff415845ede6f94dde2e6f376dc6 38fba740241f101855fbe1dff56954f4 00feff415845ede6f94dde2e6f376dc6 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 b2150b787a63c91364a6b8fb05e0e257 af6ef38ff6d6e5e5d4d706a666612176 b2150b787a63c91364a6b8fb05e0e257 af6ef38ff6d6e5e5d4d706a666612176 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 3cf6759ece6904d83cf6759ece6904d8 2e1258560acfa50be56e2d807b486e6b 3cf6759ece6904d83cf6759ece6904d8 2e1258560acfa50be56e2d807b486e6b fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 b47a33fba3b7fbb4d27dc958b03067c6 41059e1db1323b6d0138836d869d3879 b47a33fba3b7fbb4d27dc958b03067c6 41059e1db1323b6d0138836d869d3879 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 de9ca56d372c772fd0a71c6d0b9823c7 fb3b5eb50b0cdfe8fb3b5eb50b0cdfe8 de9ca56d372c772fd0a71c6d0b9823c7 fb3b5eb50b0cdfe8fb3b5eb50b0cdfe8 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 94b24979c2d04c4097e399a4554c5c16 db721b8ed5700e78ab59218e159731d0 94b24979c2d04c4097e399a4554c5c16 db721b8ed5700e78ab59218e159731d0 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 b5880f61fedd20425c5543e8c7936b85 5307fb644310e267befa0eba8f6c446c b5880f61fedd20425c5543e8c7936b85 5307fb644310e267befa0eba8f6c446c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxeq.f64.f64 d6, d15 fd4a84aa423eaacaa94054b3e94c7a63 2e7d81d1653b606922e6bad669efd9f5 fd4a84aa423eaacaa94054b3e94c7a63 2e7d81d1653b606922e6bad669efd9f5 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 7e57ef5abda44c6436db62d8d503bb36 e1a082289b9dff1de1a082289b9dff1d 7e57ef5abda44c6436db62d8d503bb36 e1a082289b9dff1de1a082289b9dff1d fpscr=00000000
+vrintxeq.f64.f64 d6, d15 3d96deb3906a9e6fda4a3243fab1d7cc 425762ffef7ae5c0019f5f8976908972 3d96deb3906a9e6fda4a3243fab1d7cc 425762ffef7ae5c0019f5f8976908972 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 3e25e79c36592546e9193ca251e28a22 a1d0a7d64b462ca55d7e51971a1f5611 3e25e79c36592546e9193ca251e28a22 a1d0a7d64b462ca55d7e51971a1f5611 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 f2ec4d6bd823991353cb02104eff712c 99c93dd4c3ed00c62274b20a6d9b7bf8 f2ec4d6bd823991353cb02104eff712c 99c93dd4c3ed00c62274b20a6d9b7bf8 fpscr=00000000
+randV128: 8192 calls, 8449 iters
+vrintxeq.f64.f64 d6, d15 3043412377039d9dbf63e8c0b7216563 9621bc486f32a787a12dd36ca840d48f 3043412377039d9dbf63e8c0b7216563 9621bc486f32a787a12dd36ca840d48f fpscr=00000000
+vrintxeq.f64.f64 d6, d15 0b7293ee9e89d5d40f79607452c53585 659338cb7aecc4bccf0528461cf30127 0b7293ee9e89d5d40f79607452c53585 659338cb7aecc4bccf0528461cf30127 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxeq.f64.f64 d6, d15 9c685842346c76209c685842346c7620 88ee453421d5502a5be597c762f29ba2 9c685842346c76209c685842346c7620 88ee453421d5502a5be597c762f29ba2 fpscr=00000000
+vrintxne.f64.f64 d7, d16 49b16af265688ae95e141ba29973810e bcdccf6002b5acbaabc002d873d6cd12 80000000000000005e141ba29973810e bcdccf6002b5acbaabc002d873d6cd12 fpscr=00000000
+vrintxne.f64.f64 d7, d16 8d96c7fe1ee4860cec4048bc67f75afc e9ca67a7f85bfd5ae80ae4905125e8ff e80ae4905125e8ffec4048bc67f75afc e9ca67a7f85bfd5ae80ae4905125e8ff fpscr=00000000
+vrintxne.f64.f64 d7, d16 baa8cb25ecbbe07eeee5c0fa26eef99b 6b49ae52d3d7d78fa069cc5f1e0bba41 8000000000000000eee5c0fa26eef99b 6b49ae52d3d7d78fa069cc5f1e0bba41 fpscr=00000000
+vrintxne.f64.f64 d7, d16 f3abde207a8c76fa986faa650c405d8b 1e1c6703e8d6cbffa3e96e2088fe0c40 8000000000000000986faa650c405d8b 1e1c6703e8d6cbffa3e96e2088fe0c40 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxne.f64.f64 d7, d16 f81ddbd8a4184905f81ddbd8a4184905 1d9fc6b5613bb6b1d2dcb2a585e4bade d2dcb2a585e4badef81ddbd8a4184905 1d9fc6b5613bb6b1d2dcb2a585e4bade fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxne.f64.f64 d7, d16 df779793bd9b3960111dfc6061bff646 027e25ce9c17766a027e25ce9c17766a 0000000000000000111dfc6061bff646 027e25ce9c17766a027e25ce9c17766a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxne.f64.f64 d7, d16 dc615cab8952d23af4e089849f34c37d 0445d96206c45df9c127fad05f7cc7be c127fad000000000f4e089849f34c37d 0445d96206c45df9c127fad05f7cc7be fpscr=00000000
+vrintxne.f64.f64 d7, d16 c31cbc98a9e0cdd84c6d3145c49a5d25 73866d7cacfd3aa9b5ed9fd5aa1e9794 80000000000000004c6d3145c49a5d25 73866d7cacfd3aa9b5ed9fd5aa1e9794 fpscr=00000000
+vrintxne.f64.f64 d7, d16 16cd5df4bc956cd5845a3b538d8f86bd 0e964d4d9595c587107358421905c51d 0000000000000000845a3b538d8f86bd 0e964d4d9595c587107358421905c51d fpscr=00000000
+vrintxne.f64.f64 d7, d16 28d4fd2d2c0601f0c38c1911402ca796 02f7c22f576e8f2a652cf2450cc2a710 652cf2450cc2a710c38c1911402ca796 02f7c22f576e8f2a652cf2450cc2a710 fpscr=00000000
+vrintxne.f64.f64 d7, d16 ca87f5e4362e559f3ea55fe1ba61a1ad 3dd94ef0a72be697243a0df943295698 00000000000000003ea55fe1ba61a1ad 3dd94ef0a72be697243a0df943295698 fpscr=00000000
+vrintxne.f64.f64 d7, d16 6d515e486a56cf0c0f33045d2d075627 08056454dc3bc12b06a20c10d3dc289a 00000000000000000f33045d2d075627 08056454dc3bc12b06a20c10d3dc289a fpscr=00000000
+vrintxne.f64.f64 d7, d16 323eeda6d842784a847780359341ebc6 796c6d7403856a16ca0d5c737f3b9478 ca0d5c737f3b9478847780359341ebc6 796c6d7403856a16ca0d5c737f3b9478 fpscr=00000000
+vrintxne.f64.f64 d7, d16 d8dfb05d1db2d2eb4a89c663f647e6c0 48932df957f87ec043831ec4683180aa 43831ec4683180aa4a89c663f647e6c0 48932df957f87ec043831ec4683180aa fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxne.f64.f64 d7, d16 7de128bea28728f37de128bea28728f3 5a1b186606e28c3e18f65a00d1f024b6 00000000000000007de128bea28728f3 5a1b186606e28c3e18f65a00d1f024b6 fpscr=00000000
+vrintxne.f64.f64 d7, d16 35be36127d106331ebe06141993b10f4 3683eceab5d2bb4abda7da3f3a94614f 8000000000000000ebe06141993b10f4 3683eceab5d2bb4abda7da3f3a94614f fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxne.f64.f64 d7, d16 4da2c617a7ad20624da2c617a7ad2062 ce180ae8dfbc29bc05a479dcbcfbb7b1 00000000000000004da2c617a7ad2062 ce180ae8dfbc29bc05a479dcbcfbb7b1 fpscr=00000000
+vrintxne.f64.f64 d7, d16 780efa43e5d4bdc2cb5672f2017e45a2 4d60b36fea0553d0f6c0f6753d013350 f6c0f6753d013350cb5672f2017e45a2 4d60b36fea0553d0f6c0f6753d013350 fpscr=00000000
+vrintxne.f64.f64 d7, d16 b13e6323da51a536010b0ccfea446548 fc5f4cdbe6b7b8b55cc1d973cc64dbec 5cc1d973cc64dbec010b0ccfea446548 fc5f4cdbe6b7b8b55cc1d973cc64dbec fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintxne.f64.f64 d7, d16 893901aa94fdf7c301e192c653873f64 1f4fc515b0b92d021f4fc515b0b92d02 000000000000000001e192c653873f64 1f4fc515b0b92d021f4fc515b0b92d02 fpscr=00000000
+vrintxne.f64.f64 d7, d16 81730899abc69f7940797a9090bf2722 425fffadcad311238aae0a664a7a78d0 800000000000000040797a9090bf2722 425fffadcad311238aae0a664a7a78d0 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxne.f64.f64 d7, d16 e036df19023efb7cd69df0907634a723 99c628398b953fee99c628398b953fee 8000000000000000d69df0907634a723 99c628398b953fee99c628398b953fee fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxne.f64.f64 d7, d16 6777120d0cd8c98b97e1b66077e106d1 d399bbcb4fe2482ed399bbcb4fe2482e d399bbcb4fe2482e97e1b66077e106d1 d399bbcb4fe2482ed399bbcb4fe2482e fpscr=00000000
+vrintxne.f64.f64 d7, d16 187487fe5123690c4da5d27097608e72 47f628ed49aef1c736395a7f240f9adb 00000000000000004da5d27097608e72 47f628ed49aef1c736395a7f240f9adb fpscr=00000000
+vrintxne.f64.f64 d7, d16 4e72cf1414e81d11838612c33924fbbc 7c30dd06df527dd2bbd9f74c08dcf616 8000000000000000838612c33924fbbc 7c30dd06df527dd2bbd9f74c08dcf616 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxne.f64.f64 d7, d16 d6f8672776585cdb337bc51aaac07015 55db5155ab05154466fcab4678818ce8 66fcab4678818ce8337bc51aaac07015 55db5155ab05154466fcab4678818ce8 fpscr=00000000
+vrintxne.f64.f64 d7, d16 b11065f24e9b3a1e6e97d8d317dbd2d5 5b5d6cc3aec098422e32a9cc522c2383 00000000000000006e97d8d317dbd2d5 5b5d6cc3aec098422e32a9cc522c2383 fpscr=00000000
+vrintxne.f64.f64 d7, d16 02e72354d08d90099f05a10f05b1c8e0 612d730a26cea390e8fa9b5d0edf355b e8fa9b5d0edf355b9f05a10f05b1c8e0 612d730a26cea390e8fa9b5d0edf355b fpscr=00000000
+vrintxne.f64.f64 d7, d16 43d4618ce941857cba03269dd5a87d6f 1fa62a10c3bf566bd361896096ef1006 d361896096ef1006ba03269dd5a87d6f 1fa62a10c3bf566bd361896096ef1006 fpscr=00000000
+vrintxne.f64.f64 d7, d16 01d69c62bd683fde401109eece50888e 5f347396a9bc0d233799e6064377ff93 0000000000000000401109eece50888e 5f347396a9bc0d233799e6064377ff93 fpscr=00000000
+vrintxne.f64.f64 d7, d16 6fe58ad090ce8097add0532968370d8c 21bd62a99f68fa3c52a17d059b1c043a 52a17d059b1c043aadd0532968370d8c 21bd62a99f68fa3c52a17d059b1c043a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxne.f64.f64 d7, d16 a79067eca91aa31dfbd8115274eb004d e66c5b79823f5eebe66c5b79823f5eeb e66c5b79823f5eebfbd8115274eb004d e66c5b79823f5eebe66c5b79823f5eeb fpscr=00000000
+vrintxne.f64.f64 d7, d16 48264ec838815680b6b69a6aeee58580 8b3f911a5301e2d210909361abe5bfbb 0000000000000000b6b69a6aeee58580 8b3f911a5301e2d210909361abe5bfbb fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxne.f64.f64 d7, d16 22b692ef212cc0cd4ec7e6d3462d5672 5e68a2b5819bc9f65e68a2b5819bc9f6 5e68a2b5819bc9f64ec7e6d3462d5672 5e68a2b5819bc9f65e68a2b5819bc9f6 fpscr=00000000
+vrintxne.f64.f64 d7, d16 f1dbaf7fec31e8c99edcf1990d5f2072 c2349b046fe01bd5849cd9c2bfd37fd0 80000000000000009edcf1990d5f2072 c2349b046fe01bd5849cd9c2bfd37fd0 fpscr=00000000
+vrintxne.f64.f64 d7, d16 87f0cb9fe4e306e7c17bbdbe6d100802 d07558761ab72e82059f5c556e25c6c0 0000000000000000c17bbdbe6d100802 d07558761ab72e82059f5c556e25c6c0 fpscr=00000000
+vrintxne.f64.f64 d7, d16 24d40a63132c23bcefc0ac0ed205b34b 99ddec2c78ea26a08f8db0c6b25175ee 8000000000000000efc0ac0ed205b34b 99ddec2c78ea26a08f8db0c6b25175ee fpscr=00000000
+vrintxne.f64.f64 d7, d16 d8c480f279647ed45794b87df5d28152 cea53c9cdfea6bd603cfb8fe81947eb2 00000000000000005794b87df5d28152 cea53c9cdfea6bd603cfb8fe81947eb2 fpscr=00000000
+vrintxne.f64.f64 d7, d16 adfa24cf13aceb4d04d5fd3033876943 f6bdc312d46049d82d65e403d0036d72 000000000000000004d5fd3033876943 f6bdc312d46049d82d65e403d0036d72 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxne.f64.f64 d7, d16 68a5db59b884fdffe18a0f39a48867d6 d3030b431687ff106966e4c5e32eb693 6966e4c5e32eb693e18a0f39a48867d6 d3030b431687ff106966e4c5e32eb693 fpscr=00000000
+vrintxne.f64.f64 d7, d16 986f4262254166b2dcc118ff957a1dc6 b016fab92b6880b9fc6e3f31ab5bc0cd fc6e3f31ab5bc0cddcc118ff957a1dc6 b016fab92b6880b9fc6e3f31ab5bc0cd fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintxne.f64.f64 d7, d16 1a6728bed649310a1a6728bed649310a 4530b29683b38f1dc9e7e7461045d006 c9e7e7461045d0061a6728bed649310a 4530b29683b38f1dc9e7e7461045d006 fpscr=00000000
+vrintxne.f64.f64 d7, d16 5fbcd60391328198a0566d5337855215 ddfa2fd659288e5dd7afe760612f560a d7afe760612f560aa0566d5337855215 ddfa2fd659288e5dd7afe760612f560a fpscr=00000000
+vrintxne.f64.f64 d7, d16 833667aff8dd8fcea9f041f2a8f306c3 987462b14b2bcd12cd92df35bb1be23f cd92df35bb1be23fa9f041f2a8f306c3 987462b14b2bcd12cd92df35bb1be23f fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintxne.f64.f64 d7, d16 b5764c93c54cd5ba47f50e30b1be648a 90762c0bdb61e64f90762c0bdb61e64f 800000000000000047f50e30b1be648a 90762c0bdb61e64f90762c0bdb61e64f fpscr=00000000
+vrintxne.f64.f64 d7, d16 28b8e1e22460e460589391b22537e28c 093a87fee536969b4782c22a73fb8eab 4782c22a73fb8eab589391b22537e28c 093a87fee536969b4782c22a73fb8eab fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxne.f64.f64 d7, d16 e22da3faf3b11cddd2e2ce82bba699f6 6de19dfb5b5949be6de19dfb5b5949be 6de19dfb5b5949bed2e2ce82bba699f6 6de19dfb5b5949be6de19dfb5b5949be fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vrintxne.f64.f64 d7, d16 70424d142aff413a70424d142aff413a 86f1439befff1f920d379e41130f36e3 000000000000000070424d142aff413a 86f1439befff1f920d379e41130f36e3 fpscr=00000000
+vrintxne.f64.f64 d7, d16 fa4672afc17bcacde325047f295230bb 40fba23a53272c49830fc1d06f871244 8000000000000000e325047f295230bb 40fba23a53272c49830fc1d06f871244 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintxne.f64.f64 d7, d16 53d485794e47af5f43505e44bed446f1 95b68f21913cd08f95b68f21913cd08f 800000000000000043505e44bed446f1 95b68f21913cd08f95b68f21913cd08f fpscr=00000000
+vrintx.f64.f64 d8, d8 441b58e61151b4c1976b8d1d2853604a f48b9d03ab878310eed12ed64f651a8b f48b9d03ab878310eed12ed64f651a8b f48b9d03ab878310eed12ed64f651a8b fpscr=00000000
+vrintx.f64.f64 d8, d8 4da1b86d9dc4d8f18f4f856b7e897280 8276e559e8be88c43ebfd5f04e498ccf 8276e559e8be88c40000000000000000 8276e559e8be88c40000000000000000 fpscr=00000000
+vrintx.f64.f64 d8, d8 55e181a24c69d0b96f595462c64246f2 571ac88bbe1d4d177d20f67b0ee83438 571ac88bbe1d4d177d20f67b0ee83438 571ac88bbe1d4d177d20f67b0ee83438 fpscr=00000000
+vrintx.f64.f64 d8, d8 e301c610d68dcc8440d3b3b09839ad96 c8e0ac00c00a4816c3f26e1815934806 c8e0ac00c00a4816c3f26e1815934806 c8e0ac00c00a4816c3f26e1815934806 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vrintx.f64.f64 d8, d8 aaf08fb60b3e41b1aaf08fb60b3e41b1 d27e23e5c84b773da94a78061913f0d5 d27e23e5c84b773d8000000000000000 d27e23e5c84b773d8000000000000000 fpscr=00000000
+vrintx.f64.f64 d8, d8 ee9861a6a55c62cc27151ca9ce6236ac b7efcf717a15f490c7ffc8415a63ea13 b7efcf717a15f490c7ffc8415a63ea13 b7efcf717a15f490c7ffc8415a63ea13 fpscr=00000000
+vrintx.f64.f64 d8, d8 33d23a52a227df4444ea6bac0951662b 33946081a7bf8e3347182600fb56828e 33946081a7bf8e3347182600fb56828e 33946081a7bf8e3347182600fb56828e fpscr=00000000
+vrintx.f64.f64 d8, d8 fd50c38a7187b1389bc7fa4518656aa5 a59c2e23fc3e5314615dd8cdd2669e07 a59c2e23fc3e5314615dd8cdd2669e07 a59c2e23fc3e5314615dd8cdd2669e07 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintx.f64.f64 d8, d8 0d13d85136feecec8da80cd097a87b9c 1586268ba970c7a7e3ed203d2a791d66 1586268ba970c7a7e3ed203d2a791d66 1586268ba970c7a7e3ed203d2a791d66 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintx.f64.f64 d8, d8 00a65be1733f5f6c6d66d238616c6753 9f0d3310e93a84500e7a54de988fd716 9f0d3310e93a84500000000000000000 9f0d3310e93a84500000000000000000 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintx.f64.f64 d8, d8 d3525940d186d7c7ce68ac1c173be477 0d88852b62cf51dd0d88852b62cf51dd 0d88852b62cf51dd0000000000000000 0d88852b62cf51dd0000000000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: 8448 calls, 8713 iters
+vrintx.f64.f64 d8, d8 ef16d5aa9470c9b72ce03804d361f79d ef3992c5d807de0e3fb8c3ffb9a9f94d ef3992c5d807de0e0000000000000000 ef3992c5d807de0e0000000000000000 fpscr=00000000
+vrintx.f64.f64 d8, d8 d3b5d147ff0d9c3d8b0e7a2021a76b98 e324bbd3f7ba2f91593f2c809e0dfd08 e324bbd3f7ba2f91593f2c809e0dfd08 e324bbd3f7ba2f91593f2c809e0dfd08 fpscr=00000000
+vrintx.f64.f64 d8, d8 e59d7ad6aa26b6063f66fe78b8aa7065 c58c2d11241b056e964ccdf9ecc9b2e1 c58c2d11241b056e8000000000000000 c58c2d11241b056e8000000000000000 fpscr=00000000
+vrintx.f64.f64 d8, d8 c3488a67f7006f46e4ecb7186c8777a7 bfcef9a18ffb2c5dab0d9bfdbfe4aace bfcef9a18ffb2c5d8000000000000000 bfcef9a18ffb2c5d8000000000000000 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintx.f64.f64 d8, d8 e1a672f58bcfdc30a2064627e1e7345b 757fc7d9400917041f1c45e45b5b5ee0 757fc7d9400917040000000000000000 757fc7d9400917040000000000000000 fpscr=00000000
+vrintx.f64.f64 d8, d8 9bd2d4fe3c3ca7220c0de40cfe47554d ab18fd38ac71b6fecc358d358ff85432 ab18fd38ac71b6fecc358d358ff85432 ab18fd38ac71b6fecc358d358ff85432 fpscr=00000000
+vrintx.f64.f64 d8, d8 4d0fb2c2ec6361482fb43b02a9298d37 b9ac53262ba999df4298306e6bb23972 b9ac53262ba999df4298306e6bb23800 b9ac53262ba999df4298306e6bb23800 fpscr=00000000
+vrintx.f64.f64 d8, d8 de834a152342d0fa70a66da6e779117f 5771447a92fd8b4eace540bf837ccf57 5771447a92fd8b4e8000000000000000 5771447a92fd8b4e8000000000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintx.f64.f64 d8, d8 fdf29a2899cc9ee75b4d6c7b07fcda76 68861137f59b23c083a8732c8eac51b6 68861137f59b23c08000000000000000 68861137f59b23c08000000000000000 fpscr=00000000
+vrintx.f64.f64 d8, d8 a032dd2da588fbfa1706c3734e99d391 968b3987e19ada1e59061fabb81aeb8b 968b3987e19ada1e59061fabb81aeb8b 968b3987e19ada1e59061fabb81aeb8b fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintx.f64.f64 d8, d8 682b87d58af85a336c0b5546aeba3cd8 6a7406f71cd469626a7406f71cd46962 6a7406f71cd469626a7406f71cd46962 6a7406f71cd469626a7406f71cd46962 fpscr=00000000
+vrintx.f64.f64 d8, d8 a0c6dacb0adf97f5fbe8176e8b1ed2e9 c9bba7eaba4b75b2d070ca287010db4d c9bba7eaba4b75b2d070ca287010db4d c9bba7eaba4b75b2d070ca287010db4d fpscr=00000000
+vrintx.f64.f64 d8, d8 4d47c1ec047d957777515c0bee473494 766eb5db356d5d597c59f29a132e78ee 766eb5db356d5d597c59f29a132e78ee 766eb5db356d5d597c59f29a132e78ee fpscr=00000000
+vrintx.f64.f64 d8, d8 13cff5bffb8d2f4a8320644c0aa2b06c bf46985265871d7f41d2f7b49fa4c669 bf46985265871d7f41d2f7b49fc00000 bf46985265871d7f41d2f7b49fc00000 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintx.f64.f64 d8, d8 8cd07d8680af9c908cd07d8680af9c90 2ce3c5ded81bf613f5c8f28ab8d5cc4b 2ce3c5ded81bf613f5c8f28ab8d5cc4b 2ce3c5ded81bf613f5c8f28ab8d5cc4b fpscr=00000000
+vrintx.f64.f64 d8, d8 3eb73659b08a72f13875d4f843a62b2b 69d0cbcf14aa57728ad6a960b316fdd6 69d0cbcf14aa57728000000000000000 69d0cbcf14aa57728000000000000000 fpscr=00000000
+vrintx.f64.f64 d8, d8 9d65cc0719e2f6e21113b50afa08708a a4815483727ff9627954237cabf0b88d a4815483727ff9627954237cabf0b88d a4815483727ff9627954237cabf0b88d fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintx.f64.f64 d8, d8 c903f9d2bc0ccb7bc903f9d2bc0ccb7b c55362dbad5b37ea2171e7ed6dd3c558 c55362dbad5b37ea0000000000000000 c55362dbad5b37ea0000000000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintx.f64.f64 d8, d8 a544bbbd4a39d6e96fb9bf6904f3d4d0 23cdeef7a486ab1e0eab6c3f6223232a 23cdeef7a486ab1e0000000000000000 23cdeef7a486ab1e0000000000000000 fpscr=00000000
+vrintx.f64.f64 d8, d8 a9296b566c38978158cd09135f556ea3 37a3b90ce2319f4b3907a536d2dd083e 37a3b90ce2319f4b0000000000000000 37a3b90ce2319f4b0000000000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintx.f64.f64 d8, d8 b85b9ae7b54ccddfad06943b4d41a1e1 da568ebcdce1815322afb6939c9bbf18 da568ebcdce181530000000000000000 da568ebcdce181530000000000000000 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintx.f64.f64 d8, d8 1c5ea42ce81bfc9f7582931d2db6c5db eaefef6166e8e1f2eaefef6166e8e1f2 eaefef6166e8e1f2eaefef6166e8e1f2 eaefef6166e8e1f2eaefef6166e8e1f2 fpscr=00000000
+vrintx.f64.f64 d8, d8 5e224c2e0c06d877ddcb4f9b42fe765f a564798c153279adb243f7068a7e188d a564798c153279ad8000000000000000 a564798c153279ad8000000000000000 fpscr=00000000
+vrintx.f64.f64 d8, d8 360637a8d6d29bf083eaaa55581616f1 2cbe6946132fc6a7494a061b59c9c1dd 2cbe6946132fc6a7494a061b59c9c1dd 2cbe6946132fc6a7494a061b59c9c1dd fpscr=00000000
+vrintx.f64.f64 d8, d8 7023f314c1c601b66b82945baac56053 8f7f1dc807e8158b4d5858dc53b151c4 8f7f1dc807e8158b4d5858dc53b151c4 8f7f1dc807e8158b4d5858dc53b151c4 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintx.f64.f64 d8, d8 47bb8ac6187e2647feb9cb5744fe50e4 643e4b88b1be8f0b643e4b88b1be8f0b 643e4b88b1be8f0b643e4b88b1be8f0b 643e4b88b1be8f0b643e4b88b1be8f0b fpscr=00000000
+vrintx.f64.f64 d8, d8 9e6c1ca240c91467eba34c4ba1305744 be53480286ccc2167027d954b14c2f79 be53480286ccc2167027d954b14c2f79 be53480286ccc2167027d954b14c2f79 fpscr=00000000
+vrintx.f64.f64 d8, d8 c44d85a7cb75fae1045ff912f1dd83ed de54f99186183d166201342ce310188e de54f99186183d166201342ce310188e de54f99186183d166201342ce310188e fpscr=00000000
+vrintx.f64.f64 d8, d8 540925f2123798401b9eb271fc711cdb b1ad508646d077d947feb864c00c2a76 b1ad508646d077d947feb864c00c2a76 b1ad508646d077d947feb864c00c2a76 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintx.f64.f64 d8, d8 96de54eb60390f9296de54eb60390f92 303f98e6d9384961dae495491a7bc6f0 303f98e6d9384961dae495491a7bc6f0 303f98e6d9384961dae495491a7bc6f0 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintx.f64.f64 d8, d8 947ef2242dc2eb8a9d1e50a36fa1b375 c4c02e467a4395a5b67b56d2d5d0cb77 c4c02e467a4395a58000000000000000 c4c02e467a4395a58000000000000000 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintx.f64.f64 d8, d8 5f22a9c7bc7c8550649b93c4690eb1ad eee839ec02267fa6e0fb718154e52321 eee839ec02267fa6e0fb718154e52321 eee839ec02267fa6e0fb718154e52321 fpscr=00000000
+vrintx.f64.f64 d8, d8 58b608008b4f68a2d06b77faad1aa768 34fdec19937f4d570895da96c55a8359 34fdec19937f4d570000000000000000 34fdec19937f4d570000000000000000 fpscr=00000000
+vrintx.f64.f64 d8, d8 3ff7bfea289b6d2d18fb4e33a495092d 6fa23573265b5d8647f4b97b2003b134 6fa23573265b5d8647f4b97b2003b134 6fa23573265b5d8647f4b97b2003b134 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintx.f64.f64 d8, d8 97676176b21c8e2b52e37589289b70b6 98996bb894b9e1039d2aa8ede28412b3 98996bb894b9e1038000000000000000 98996bb894b9e1038000000000000000 fpscr=00000000
+vrintx.f64.f64 d8, d8 caafaf46903760afb0dc7ca015d2259a 284ae2f3b849f196aac21be59c561633 284ae2f3b849f1968000000000000000 284ae2f3b849f1968000000000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintx.f64.f64 d8, d8 dcb4639e9c502b51770ae1e5aeefe6d6 9cdc0c0180f8d5942086ea94dee9e1b9 9cdc0c0180f8d5940000000000000000 9cdc0c0180f8d5940000000000000000 fpscr=00000000
+vrintx.f64.f64 d8, d8 9d136d9f94d8a89bf4e7ff6cc1e49969 44f317ecb1f9c87aa050364ebba8c896 44f317ecb1f9c87a8000000000000000 44f317ecb1f9c87a8000000000000000 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintx.f64.f64 d8, d8 8f90da4a132baf33d5cc1cab453654e3 57568aee3bcbea4c062a2f56553929ae 57568aee3bcbea4c0000000000000000 57568aee3bcbea4c0000000000000000 fpscr=00000000
+vrintzeq.f32.f32 s0, s9 bbb66909e2ea5a3304096e47b7e1897a 1ba52a7cf514a2aef5a25175319fe6fe bbb66909e2ea5a3304096e47b7e1897a 1ba52a7cf514a2aef5a25175319fe6fe fpscr=00000000
+vrintzeq.f32.f32 s0, s9 40a5dfbc0cb0537f133e68f917afbfc8 f8493741ac3709f71ef6bd2aedce7948 40a5dfbc0cb0537f133e68f917afbfc8 f8493741ac3709f71ef6bd2aedce7948 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintzeq.f32.f32 s0, s9 29250fffd27127b7f1a2f5865bd3620a 5d5adf28535a766ecc147823af263209 29250fffd27127b7f1a2f5865bd3620a 5d5adf28535a766ecc147823af263209 fpscr=00000000
+vrintzeq.f32.f32 s0, s9 e00984602a2495b3ac2036abb6494beb 4efe40b9402a717c463423763a5ada1d e00984602a2495b3ac2036abb6494beb 4efe40b9402a717c463423763a5ada1d fpscr=00000000
+vrintzeq.f32.f32 s0, s9 e43732830e8bf0a76f24f086fd3e4bb2 c14cbf548e63f38b1d22404788eec77b e43732830e8bf0a76f24f086fd3e4bb2 c14cbf548e63f38b1d22404788eec77b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[2]
+vrintzeq.f32.f32 s0, s9 349f4ad2ee4133e0ee4133e0b6e61bfb 5d05d104a604b0404d631611a604b040 349f4ad2ee4133e0ee4133e0b6e61bfb 5d05d104a604b0404d631611a604b040 fpscr=00000000
+vrintzeq.f32.f32 s0, s9 e7db81ea638d531ee80cc366565a004c b6f9983ba9b3a2dbfd030028254cc47a e7db81ea638d531ee80cc366565a004c b6f9983ba9b3a2dbfd030028254cc47a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintzeq.f32.f32 s0, s9 0d3f3dbc1dd80bf894648293225c2512 b7f89b477397f084d3b07d8ab7f89b47 0d3f3dbc1dd80bf894648293225c2512 b7f89b477397f084d3b07d8ab7f89b47 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintzeq.f32.f32 s0, s9 710467b3cdbec4fee108e3cc21fd348f 71ae57b0cc4f8ce9c389bceeac2f947b 710467b3cdbec4fee108e3cc21fd348f 71ae57b0cc4f8ce9c389bceeac2f947b fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintzeq.f32.f32 s0, s9 aa1662e89a69e732c2f9bba665b5e136 8fe70a5b2f3457a864ca12758fe70a5b aa1662e89a69e732c2f9bba665b5e136 8fe70a5b2f3457a864ca12758fe70a5b fpscr=00000000
+vrintzeq.f32.f32 s0, s9 2bc635c6f43a232d1d1e656f0d5cccab 4d01e6b0f3a37ef8ddb354cda483eba9 2bc635c6f43a232d1d1e656f0d5cccab 4d01e6b0f3a37ef8ddb354cda483eba9 fpscr=00000000
+vrintzeq.f32.f32 s0, s9 c60c71939e0df818f06f5d38194a9bf1 5159e333be70d1a5100e04f36b67b56a c60c71939e0df818f06f5d38194a9bf1 5159e333be70d1a5100e04f36b67b56a fpscr=00000000
+vrintzeq.f32.f32 s0, s9 fa57406eb220ab3ae4d9c86c4b9a9de5 40d56a4fe03f1f00274a397f67eff74c fa57406eb220ab3ae4d9c86c4b9a9de5 40d56a4fe03f1f00274a397f67eff74c fpscr=00000000
+vrintzeq.f32.f32 s0, s9 a53a637acd1aae3fa807b7005d0904a1 5733846c487710cbe347a5f868effd9d a53a637acd1aae3fa807b7005d0904a1 5733846c487710cbe347a5f868effd9d fpscr=00000000
+vrintzeq.f32.f32 s0, s9 c0ff5f4390ac99bc3fde152e08a0f6c5 ce66690b031a4cc02350af163dcf577a c0ff5f4390ac99bc3fde152e08a0f6c5 ce66690b031a4cc02350af163dcf577a fpscr=00000000
+vrintzeq.f32.f32 s0, s9 3913e7f21c1d2688112d4dfab082d41c 77ee70b4f8c48a1ac1af9bebb3c02792 3913e7f21c1d2688112d4dfab082d41c 77ee70b4f8c48a1ac1af9bebb3c02792 fpscr=00000000
+vrintzeq.f32.f32 s0, s9 28589f72e5ba9efb64395186879cdf13 388bd93a85f97d7552a59f657152524c 28589f72e5ba9efb64395186879cdf13 388bd93a85f97d7552a59f657152524c fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintzeq.f32.f32 s0, s9 614f436de7219c0e312cff5bf631411f a98910dea66ac575a29e3247bed23ad6 614f436de7219c0e312cff5bf631411f a98910dea66ac575a29e3247bed23ad6 fpscr=00000000
+vrintzeq.f32.f32 s0, s9 31bb43416e734f69784993137b685bce a62ff141a47e38ed9d69448d46f05ec3 31bb43416e734f69784993137b685bce a62ff141a47e38ed9d69448d46f05ec3 fpscr=00000000
+vrintzeq.f32.f32 s0, s9 fe87dc3ee8e69066cfe5014c3dab8660 aaf0d3f463a003e24c33076943742f59 fe87dc3ee8e69066cfe5014c3dab8660 aaf0d3f463a003e24c33076943742f59 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[0]
+vrintzeq.f32.f32 s0, s9 5569e3145569e314a9e4afab63bd2010 0486ad668881d1cdc072963261adccb4 5569e3145569e314a9e4afab63bd2010 0486ad668881d1cdc072963261adccb4 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintzeq.f32.f32 s0, s9 46e90204609b8fbd609b8fbd391b36dd b7563d8ee64a59b5371c69390708cbe1 46e90204609b8fbd609b8fbd391b36dd b7563d8ee64a59b5371c69390708cbe1 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintzeq.f32.f32 s0, s9 667a8c6540de3b7c40de3b7cf9511749 92e340a4447a47c8ec8b27fc81ae7f8d 667a8c6540de3b7c40de3b7cf9511749 92e340a4447a47c8ec8b27fc81ae7f8d fpscr=00000000
+vrintzeq.f32.f32 s0, s9 2abb3cf5467bfabc2fdd4fb271facc1b 9201b9c21123d29dbed988a3e9e1cb4f 2abb3cf5467bfabc2fdd4fb271facc1b 9201b9c21123d29dbed988a3e9e1cb4f fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintzeq.f32.f32 s0, s9 f0b1a5428acd8686412f2572f0b1a542 39c09f4405f744b0ea48f1787bfb99e8 f0b1a5428acd8686412f2572f0b1a542 39c09f4405f744b0ea48f1787bfb99e8 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: 8704 calls, 8981 iters
+vrintzeq.f32.f32 s0, s9 080b9213b916c69c114d18bb5e9b2d93 bf3323aedc60e7b6bf3323aee710f8cb 080b9213b916c69c114d18bb5e9b2d93 bf3323aedc60e7b6bf3323aee710f8cb fpscr=00000000
+vrintzeq.f32.f32 s0, s9 3d5ff3885ae5494782819db414306573 8677650d8b922a53a4887507d36ec2d0 3d5ff3885ae5494782819db414306573 8677650d8b922a53a4887507d36ec2d0 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintzeq.f32.f32 s0, s9 a6a3bf8435027a3f4f41a855f875e513 2e52fba832c176d4fa2750a0cfa65e4f a6a3bf8435027a3f4f41a855f875e513 2e52fba832c176d4fa2750a0cfa65e4f fpscr=00000000
+vrintzeq.f32.f32 s0, s9 70d8af9faf18a50b917003f841a41384 db3d4546af7ae96c4ad583791533229e 70d8af9faf18a50b917003f841a41384 db3d4546af7ae96c4ad583791533229e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintzeq.f32.f32 s0, s9 9d35ade95ce492761db2a17343b5ceb6 38a78d049365d3da9b77b07ce3a42787 9d35ade95ce492761db2a17343b5ceb6 38a78d049365d3da9b77b07ce3a42787 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[3]
+vrintzeq.f32.f32 s0, s9 683cff6f24c520d1c25a860f2bf1925c 8b0aeabcb5a51aae8b0aeabcafc2e862 683cff6f24c520d1c25a860f2bf1925c 8b0aeabcb5a51aae8b0aeabcafc2e862 fpscr=00000000
+vrintzeq.f32.f32 s0, s9 85456b088e581d3fd28142c149488adf e36bdcaea1d2aad875524d73cc9ccd64 85456b088e581d3fd28142c149488adf e36bdcaea1d2aad875524d73cc9ccd64 fpscr=00000000
+vrintzeq.f32.f32 s0, s9 c84e23f18e9986ce3cad4d8127e86a52 e58b56bd650f42af8495e644748f26c6 c84e23f18e9986ce3cad4d8127e86a52 e58b56bd650f42af8495e644748f26c6 fpscr=00000000
+vrintzeq.f32.f32 s0, s9 2bf71f3e3c1743a52868bb1d268fb28c 6387c63cec8f8d5b465d9b22a82da6bc 2bf71f3e3c1743a52868bb1d268fb28c 6387c63cec8f8d5b465d9b22a82da6bc fpscr=00000000
+vrintzeq.f32.f32 s0, s9 f7cca157839edf4d560a235fb4926bd3 7bc5458cc1beedac2fd3e59364b4c767 f7cca157839edf4d560a235fb4926bd3 7bc5458cc1beedac2fd3e59364b4c767 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintzeq.f32.f32 s0, s9 74a6df2d553652fbf9fc65bf790624ff 4b3c35da30277c38192a443b8eb63ec2 74a6df2d553652fbf9fc65bf790624ff 4b3c35da30277c38192a443b8eb63ec2 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintzeq.f32.f32 s0, s9 2caa48e898784adbfe17e950a6c53041 87d31a25f0ac89e3674777c07e14cfe7 2caa48e898784adbfe17e950a6c53041 87d31a25f0ac89e3674777c07e14cfe7 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintzeq.f32.f32 s0, s9 f044ec20fc3623fe341fda728af3b1fc 8fcdd2bb9c326436f51f71c58ff89a93 f044ec20fc3623fe341fda728af3b1fc 8fcdd2bb9c326436f51f71c58ff89a93 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintzeq.f32.f32 s0, s9 352efec2819aca61104dd4bb6f225e11 16426ee6215da3493950fb42130717af 352efec2819aca61104dd4bb6f225e11 16426ee6215da3493950fb42130717af fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[3]
+vrintzeq.f32.f32 s0, s9 4f74a56036ad5c454f74a560afb7e037 9c86a9ab6e1475b386d6be38381bdb27 4f74a56036ad5c454f74a560afb7e037 9c86a9ab6e1475b386d6be38381bdb27 fpscr=00000000
+vrintzeq.f32.f32 s0, s9 1a60113d5315c8b5a6b8b86771b01329 a1e1a5ce996b291ba9ca7232485ad17d 1a60113d5315c8b5a6b8b86771b01329 a1e1a5ce996b291ba9ca7232485ad17d fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintzeq.f32.f32 s0, s9 0202aa1e4eb75f310202aa1e1eaaa94e 122362547744f5b1da44b90cbdcd277e 0202aa1e4eb75f310202aa1e1eaaa94e 122362547744f5b1da44b90cbdcd277e fpscr=00000000
+vrintzeq.f32.f32 s0, s9 c2b240fe399a61caa37c609421b551ea baf02abb4ec0b0fb0e92f76e38232cb7 c2b240fe399a61caa37c609421b551ea baf02abb4ec0b0fb0e92f76e38232cb7 fpscr=00000000
+vrintzeq.f32.f32 s0, s9 e4f7609d4bcfe26a6f5a3728cfdcb5d9 09828f4b1a709c62ed7aae7964e4b468 e4f7609d4bcfe26a6f5a3728cfdcb5d9 09828f4b1a709c62ed7aae7964e4b468 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintzeq.f32.f32 s0, s9 3246953f54bcf142280be54cca32bab6 20d2e56f20d2e56fe4a7056f42c76050 3246953f54bcf142280be54cca32bab6 20d2e56f20d2e56fe4a7056f42c76050 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintzeq.f32.f32 s0, s9 5bdc97b07ea8f8e6c40eee1f5852ffa2 0486073822781e43b9abf4ad65866312 5bdc97b07ea8f8e6c40eee1f5852ffa2 0486073822781e43b9abf4ad65866312 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintzeq.f32.f32 s0, s9 21d459b994b3a2236fe2a17ff0fd6c21 39995e07e4593275134cf35639995e07 21d459b994b3a2236fe2a17ff0fd6c21 39995e07e4593275134cf35639995e07 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[0]
+vrintzeq.f32.f32 s0, s9 07a2142e468dcb7d07a2142ee0cc0cd5 743b2e313014c9ea47d77d782219fb5f 07a2142e468dcb7d07a2142ee0cc0cd5 743b2e313014c9ea47d77d782219fb5f fpscr=00000000
+vrintzeq.f32.f32 s0, s9 a7373f48f0eb571da87a6a6281aa0ad0 5f8752d52ab9daf82b1e8a7f0aebbb82 a7373f48f0eb571da87a6a6281aa0ad0 5f8752d52ab9daf82b1e8a7f0aebbb82 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[3]
+vrintzeq.f32.f32 s0, s9 3d4e3c40479241ae479241ae4574971d 45960d315e9f4faf2124191d45960d31 3d4e3c40479241ae479241ae4574971d 45960d315e9f4faf2124191d45960d31 fpscr=00000000
+vrintzne.f32.f32 s1, s10 472c8ee6d1b2519d09f15e3624a1eb3d 94903517526e6d330a56c3834db94d06 472c8ee6d1b2519d526e6d3324a1eb3d 94903517526e6d330a56c3834db94d06 fpscr=00000000
+vrintzne.f32.f32 s1, s10 b4874fa305bb220162152b734d807c90 513e2ebe598680743827ef33aaaaab5c b4874fa305bb2201598680744d807c90 513e2ebe598680743827ef33aaaaab5c fpscr=00000000
+vrintzne.f32.f32 s1, s10 0f77095e812ddf9a38a14e0de819d0f4 621de13e15039feb0ca8bb61e70e2a75 0f77095e812ddf9a00000000e819d0f4 621de13e15039feb0ca8bb61e70e2a75 fpscr=00000000
+vrintzne.f32.f32 s1, s10 84293ffe7620a048aeb1f6b60dd745c0 f0e72970f1452d25b66707475687e610 84293ffe7620a048f1452d250dd745c0 f0e72970f1452d25b66707475687e610 fpscr=00000000
+vrintzne.f32.f32 s1, s10 fa4eb4682ceafad2a4ab9ae07c299201 0c843cbcbc4f561f8ff1cd0d6c88b523 fa4eb4682ceafad2800000007c299201 0c843cbcbc4f561f8ff1cd0d6c88b523 fpscr=00000000
+vrintzne.f32.f32 s1, s10 1644bc18d23a00b095b1a7014d9e30e4 089054678e64d3072379201cf5d11d45 1644bc18d23a00b0800000004d9e30e4 089054678e64d3072379201cf5d11d45 fpscr=00000000
+vrintzne.f32.f32 s1, s10 8c91b826f1e827dd543617c496474bf8 4e4eb993e485d86df8775a9d5ec27e90 8c91b826f1e827dde485d86d96474bf8 4e4eb993e485d86df8775a9d5ec27e90 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vrintzne.f32.f32 s1, s10 e40c3a6c52f0c2a47981455f9f9c8f18 0f10b6e6c2824ab7e49039850f10b6e6 e40c3a6c52f0c2a4c28200009f9c8f18 0f10b6e6c2824ab7e49039850f10b6e6 fpscr=00000000
+vrintzne.f32.f32 s1, s10 0b6890d68f331049c4fabf2af95a0499 38f918b6b0f6cd8584e4063b19e38e19 0b6890d68f33104980000000f95a0499 38f918b6b0f6cd8584e4063b19e38e19 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintzne.f32.f32 s1, s10 b915f2b16ecf64106bc55773151b3239 088c4ae0088c4ae09889e9292ae63c2f b915f2b16ecf641000000000151b3239 088c4ae0088c4ae09889e9292ae63c2f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintzne.f32.f32 s1, s10 6b1ef3c195269db4ef49c179ed46f924 c3c0dea4c4e0e8d05aebf0a7ab056c4d 6b1ef3c195269db4c4e0e000ed46f924 c3c0dea4c4e0e8d05aebf0a7ab056c4d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintzne.f32.f32 s1, s10 66ca08c95265252d7299e29eff4645bb 75a57e6575a57e65932246d03b7bf665 66ca08c95265252d75a57e65ff4645bb 75a57e6575a57e65932246d03b7bf665 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[1]
+vrintzne.f32.f32 s1, s10 00afbed100afbed13f8ac3842ab0fe24 b878608979589ff1dc6278080a71ddb0 00afbed100afbed179589ff12ab0fe24 b878608979589ff1dc6278080a71ddb0 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintzne.f32.f32 s1, s10 d5dda871c8cab9e0cf24f9c9d468bb48 ed43a379a326823215ff09b842476ea9 d5dda871c8cab9e080000000d468bb48 ed43a379a326823215ff09b842476ea9 fpscr=00000000
+vrintzne.f32.f32 s1, s10 cfa6806e892110ded53dca28d2c17e0c a98ef2018cb45a18ed6592cd83a89c86 cfa6806e892110de80000000d2c17e0c a98ef2018cb45a18ed6592cd83a89c86 fpscr=00000000
+vrintzne.f32.f32 s1, s10 04473a6439131786b7e763fcfc3de337 22a2adf60e009f4fc966ff290cc42825 04473a643913178600000000fc3de337 22a2adf60e009f4fc966ff290cc42825 fpscr=00000000
+vrintzne.f32.f32 s1, s10 f033888b1ee01b953548dc5727afc5fe 72db71f87977d934fafbed02d8d2ff03 f033888b1ee01b957977d93427afc5fe 72db71f87977d934fafbed02d8d2ff03 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[2]
+vrintzne.f32.f32 s1, s10 a2a5ae42c812d438d8c70715a2a5ae42 d103bea8a121bd5ad103bea8ab36cd5f a2a5ae42c812d43880000000a2a5ae42 d103bea8a121bd5ad103bea8ab36cd5f fpscr=00000000
+vrintzne.f32.f32 s1, s10 5d338d804783dce70cea1ae95c8d8dca 37cb7067bad25749bcf3be0e037473bf 5d338d804783dce7800000005c8d8dca 37cb7067bad25749bcf3be0e037473bf fpscr=00000000
+vrintzne.f32.f32 s1, s10 12187d2dc6873bf001c205a9e1593fab 459f3fa4b4c8a650c8cd076767ed4458 12187d2dc6873bf080000000e1593fab 459f3fa4b4c8a650c8cd076767ed4458 fpscr=00000000
+vrintzne.f32.f32 s1, s10 e9c3bf0864ee3b1273a7aa7d72c79372 78890b6c260959945d0181330cf7d5a0 e9c3bf0864ee3b120000000072c79372 78890b6c260959945d0181330cf7d5a0 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintzne.f32.f32 s1, s10 3021d6fac69a24894957d8ea45f4bb87 994c650dc0389f74e87d5e1d91585fef 3021d6fac69a2489c000000045f4bb87 994c650dc0389f74e87d5e1d91585fef fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintzne.f32.f32 s1, s10 1eb1aba266b2574be7a363296733a0b3 eab369a0c391ebdc5e2800a1c391ebdc 1eb1aba266b2574bc39180006733a0b3 eab369a0c391ebdc5e2800a1c391ebdc fpscr=00000000
+vrintzne.f32.f32 s1, s10 70edb797a3d8a59006a6761cdbaa76d6 85cc2e48c5731c76f214451405c2bca9 70edb797a3d8a590c5731000dbaa76d6 85cc2e48c5731c76f214451405c2bca9 fpscr=00000000
+vrintzne.f32.f32 s1, s10 9ab854304c739ae51d3d8e36dbaa0732 9bdce719ddfd081341e73c38273f0266 9ab854304c739ae5ddfd0813dbaa0732 9bdce719ddfd081341e73c38273f0266 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintzne.f32.f32 s1, s10 6c828769061092932e4fb14bf0532d3e e4b5e5f2a7281eff7aac91ca6babe5e7 6c8287690610929380000000f0532d3e e4b5e5f2a7281eff7aac91ca6babe5e7 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+vrintzne.f32.f32 s1, s10 4ca5a176655e7d2458f0e7254282f8e2 1edf424edf3bb2e9df3bb2e9e88ebcbb 4ca5a176655e7d24df3bb2e94282f8e2 1edf424edf3bb2e9df3bb2e9e88ebcbb fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintzne.f32.f32 s1, s10 7b4fa74fa603082e7b4fa74f90205048 9419b925f28e676805b2d60cc6f4f2f5 7b4fa74fa603082ef28e676890205048 9419b925f28e676805b2d60cc6f4f2f5 fpscr=00000000
+vrintzne.f32.f32 s1, s10 828574a1e1ba3aed1bbb29b0740236c8 304abf01e0143642e60796097af0b47c 828574a1e1ba3aede0143642740236c8 304abf01e0143642e60796097af0b47c fpscr=00000000
+vrintzne.f32.f32 s1, s10 a6191164d9f89a83660ae1a65b83f622 a42be55e546f91b45582a41f2c85522b a6191164d9f89a83546f91b45b83f622 a42be55e546f91b45582a41f2c85522b fpscr=00000000
+vrintzne.f32.f32 s1, s10 e8fbaf5db364a93fd9ab45d6c556717a 0c6d839df218c18a37347c245444659b e8fbaf5db364a93ff218c18ac556717a 0c6d839df218c18a37347c245444659b fpscr=00000000
+vrintzne.f32.f32 s1, s10 38d8983410ef758bf6f625a162ff57fa 99893e65fdc15277f6b43b52397adf31 38d8983410ef758bfdc1527762ff57fa 99893e65fdc15277f6b43b52397adf31 fpscr=00000000
+vrintzne.f32.f32 s1, s10 211abd6d3f5ef4b5dd915cb5512e65ea c30bccba2cc07f4cfab2a5aa0fdfb396 211abd6d3f5ef4b500000000512e65ea c30bccba2cc07f4cfab2a5aa0fdfb396 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintzne.f32.f32 s1, s10 798a361d098ea747395690092e3e463d e3bd1cffdb5ef51e7f618b2b6220dd17 798a361d098ea747db5ef51e2e3e463d e3bd1cffdb5ef51e7f618b2b6220dd17 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintzne.f32.f32 s1, s10 e296ea599e01622012bd129ace2b0520 c2fc25bcdcd2ab05f83ccbca8ef8f54e e296ea599e016220dcd2ab05ce2b0520 c2fc25bcdcd2ab05f83ccbca8ef8f54e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintzne.f32.f32 s1, s10 2ff828eb658151f4f2791f9a7ad409fe b7378c07e55e5ccc6e4eec14c0f34a4e 2ff828eb658151f4e55e5ccc7ad409fe b7378c07e55e5ccc6e4eec14c0f34a4e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintzne.f32.f32 s1, s10 6883697313b06d928dc3872c58de169e 20be760f9cbb5b06d91d84ee38ecdaf4 6883697313b06d928000000058de169e 20be760f9cbb5b06d91d84ee38ecdaf4 fpscr=00000000
+vrintzne.f32.f32 s1, s10 e1b73bc99002ae5445d26d6663bc09dd 6089e589f53d1f84b9d0200c8d868f81 e1b73bc99002ae54f53d1f8463bc09dd 6089e589f53d1f84b9d0200c8d868f81 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintzne.f32.f32 s1, s10 970c132f16389b9c00c7c69168c83a73 b8ea2c3590fbde9f90fbde9f8150928a 970c132f16389b9c8000000068c83a73 b8ea2c3590fbde9f90fbde9f8150928a fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: 8960 calls, 9246 iters
+vrintzne.f32.f32 s1, s10 0c2f6f52132019b3b3fa6f1beab22689 d75dad5b54f1bca3043bf007915e26ac 0c2f6f52132019b354f1bca3eab22689 d75dad5b54f1bca3043bf007915e26ac fpscr=00000000
+vrintzne.f32.f32 s1, s10 8e5ea4e7c65790210cc18841ebe1413f ed2f2b6d646b68d6a0e4457408a53b68 8e5ea4e7c6579021646b68d6ebe1413f ed2f2b6d646b68d6a0e4457408a53b68 fpscr=00000000
+vrintzne.f32.f32 s1, s10 cf3499c670a652444d68bdba093ec871 adf969bd9c1308a806c8643151439d7b cf3499c670a6524480000000093ec871 adf969bd9c1308a806c8643151439d7b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintzne.f32.f32 s1, s10 59bbe5f5034cb1fb034cb1fb216d7357 9949e6cfb7b26889b071b4aa18e33c6b 59bbe5f5034cb1fb80000000216d7357 9949e6cfb7b26889b071b4aa18e33c6b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintzne.f32.f32 s1, s10 fd6532230b6a060094561fe58fe2c524 76e9c94a61f240ed5c0422fb502496d3 fd6532230b6a060061f240ed8fe2c524 76e9c94a61f240ed5c0422fb502496d3 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[0]
+vrintzne.f32.f32 s1, s10 2ea9b4a16f4ed8e2fea54b9329cb667f dd195df9da053ea77ad28d56da053ea7 2ea9b4a16f4ed8e2da053ea729cb667f dd195df9da053ea77ad28d56da053ea7 fpscr=00000000
+vrintzne.f32.f32 s1, s10 bc75377d5333d5a11d15011902365f35 95d22b73f109e17899ef25ef7a991fb4 bc75377d5333d5a1f109e17802365f35 95d22b73f109e17899ef25ef7a991fb4 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[1]
+vrintzne.f32.f32 s1, s10 0f670e2e0a1d5992cb8d5f02a30e5502 92a5e81b0c20ddc016e2d77992a5e81b 0f670e2e0a1d599200000000a30e5502 92a5e81b0c20ddc016e2d77992a5e81b fpscr=00000000
+vrintzne.f32.f32 s1, s10 4cfa812da33be7073c0ff2156fcf182b 980c79d0bd5bf0df8421780d453e31a1 4cfa812da33be707800000006fcf182b 980c79d0bd5bf0df8421780d453e31a1 fpscr=00000000
+vrintzne.f32.f32 s1, s10 0c89f7d529ab70592bc9c836fe7942c6 195e03d7cb08bd442d7a1bea5e6ce1e3 0c89f7d529ab7059cb08bd44fe7942c6 195e03d7cb08bd442d7a1bea5e6ce1e3 fpscr=00000000
+vrintzne.f32.f32 s1, s10 64847b7d6a44a22f5749259ba72fc2d5 9dc415bc8e13b692f48e05f60c46b505 64847b7d6a44a22f80000000a72fc2d5 9dc415bc8e13b692f48e05f60c46b505 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintz.f32.f32 s2, s11 9e1f114beac0b63d38c38206b7358253 8994edc2b950064a3eefc47a707eb3c7 9e1f114b8000000038c38206b7358253 8994edc2b950064a3eefc47a707eb3c7 fpscr=00000000
+vrintz.f32.f32 s2, s11 6fa1b726979461b8ee1edff5743f5665 810f738ff9ff0705d16eb58309d488d4 6fa1b72680000000ee1edff5743f5665 810f738ff9ff0705d16eb58309d488d4 fpscr=00000000
+vrintz.f32.f32 s2, s11 39cca17351e61bbf46fe70e17c592184 2b8001a2cc67c4c0cab16c7adcc3f23b 39cca1730000000046fe70e17c592184 2b8001a2cc67c4c0cab16c7adcc3f23b fpscr=00000000
+vrintz.f32.f32 s2, s11 a2cf5ac2586a35d400a088ddb456acf8 3c17388074b9ad1c2b846233399916d4 a2cf5ac20000000000a088ddb456acf8 3c17388074b9ad1c2b846233399916d4 fpscr=00000000
+vrintz.f32.f32 s2, s11 9967f1e9e8acbe3912c371105b2edfe0 76581b212f533d5806056cf5fc45acc8 9967f1e976581b2112c371105b2edfe0 76581b212f533d5806056cf5fc45acc8 fpscr=00000000
+vrintz.f32.f32 s2, s11 8c025f6e8fbfb2ab78ea484147373687 f7c3b32386d74bde02d0798f41449d0e 8c025f6ef7c3b32378ea484147373687 f7c3b32386d74bde02d0798f41449d0e fpscr=00000000
+vrintz.f32.f32 s2, s11 56a0477a37c5d7f45c7df61431e8d83b 10387705bbc218976ba539d6136e4e03 56a0477a000000005c7df61431e8d83b 10387705bbc218976ba539d6136e4e03 fpscr=00000000
+vrintz.f32.f32 s2, s11 0c1c96351bd680e628541198e0019f84 7d4c0f45a8d4b030abff210485a246eb 0c1c96357d4c0f4528541198e0019f84 7d4c0f45a8d4b030abff210485a246eb fpscr=00000000
+vrintz.f32.f32 s2, s11 aed1fb758c4226ac729e99453d10eeb9 f7777d61ec5fb238217bd4f426582f4c aed1fb75f7777d61729e99453d10eeb9 f7777d61ec5fb238217bd4f426582f4c fpscr=00000000
+vrintz.f32.f32 s2, s11 afa14ed9a83be885cc20944d3c5871f8 2f1c9fb188787518532be640db0d4230 afa14ed900000000cc20944d3c5871f8 2f1c9fb188787518532be640db0d4230 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintz.f32.f32 s2, s11 6a5bc33fe2d8e9d471e29054ae17c078 1f7d1928d2028df687c0034211900a3f 6a5bc33f0000000071e29054ae17c078 1f7d1928d2028df687c0034211900a3f fpscr=00000000
+vrintz.f32.f32 s2, s11 c0866d7e1394727d8f9cd233fe84ea29 35d7c48899f0cb9bb574b99c78ed532f c0866d7e000000008f9cd233fe84ea29 35d7c48899f0cb9bb574b99c78ed532f fpscr=00000000
+vrintz.f32.f32 s2, s11 764da5637213a3a29d53050b72055f12 616d31807de9d56f104af1bb149144cb 764da563616d31809d53050b72055f12 616d31807de9d56f104af1bb149144cb fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintz.f32.f32 s2, s11 5dd26fc370d302f5381713d7bdd30262 c85d0993db07cae17073f0bf7073f0bf 5dd26fc3c85d0980381713d7bdd30262 c85d0993db07cae17073f0bf7073f0bf fpscr=00000000
+vrintz.f32.f32 s2, s11 b11849298598b9c368e3bd48259df1f3 0f3e87504f41e390721c492b69829850 b11849290000000068e3bd48259df1f3 0f3e87504f41e390721c492b69829850 fpscr=00000000
+vrintz.f32.f32 s2, s11 412b66e6cb69aefbee7e857896803b09 650a657ba2afa93b577e38eb36d20bb9 412b66e6650a657bee7e857896803b09 650a657ba2afa93b577e38eb36d20bb9 fpscr=00000000
+vrintz.f32.f32 s2, s11 47d85580cfd2492bfceaabcc6fb6284e e8daf14f7e8313cc366df0003827b742 47d85580e8daf14ffceaabcc6fb6284e e8daf14f7e8313cc366df0003827b742 fpscr=00000000
+vrintz.f32.f32 s2, s11 1deb612ac87e6dcf76f213de7dcdeee2 c6c7d913bb678b2968a8d4e73eb7583a 1deb612ac6c7d80076f213de7dcdeee2 c6c7d913bb678b2968a8d4e73eb7583a fpscr=00000000
+vrintz.f32.f32 s2, s11 7cfb586cc9afb809c5a0e227cc8343a0 06b3ff1cc049c16f6e936cde4da7951e 7cfb586c00000000c5a0e227cc8343a0 06b3ff1cc049c16f6e936cde4da7951e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintz.f32.f32 s2, s11 3e7a4b634dc3d69482f92269e7e3d6a9 ea51916c41a40c0bfa9332265fae9134 3e7a4b63ea51916c82f92269e7e3d6a9 ea51916c41a40c0bfa9332265fae9134 fpscr=00000000
+vrintz.f32.f32 s2, s11 c17379baff5e48ec5f2732028cccd104 101f035150c486bad5448a61282a1dab c17379ba000000005f2732028cccd104 101f035150c486bad5448a61282a1dab fpscr=00000000
+vrintz.f32.f32 s2, s11 5b8970ff1e0ad4461fe1a34b39020b19 73c220cb71987143143518ad1f5b42c9 5b8970ff73c220cb1fe1a34b39020b19 73c220cb71987143143518ad1f5b42c9 fpscr=00000000
+vrintz.f32.f32 s2, s11 92c8be0e7c9cc31c1e839f9674e131f7 69d0b763c1fac564832c1a5d34d2fd0a 92c8be0e69d0b7631e839f9674e131f7 69d0b763c1fac564832c1a5d34d2fd0a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintz.f32.f32 s2, s11 6eb98433c77c1e986eb98433a13eb909 c3eb6e906b2c3dd04eb1d6fb4aa4a7ba 6eb98433c3eb00006eb98433a13eb909 c3eb6e906b2c3dd04eb1d6fb4aa4a7ba fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintz.f32.f32 s2, s11 6a3c249a8805124581dcdbbf6a3c249a 83e3f23b745e1a35f5610add650a4f27 6a3c249a8000000081dcdbbf6a3c249a 83e3f23b745e1a35f5610add650a4f27 fpscr=00000000
+vrintz.f32.f32 s2, s11 2affb48e3ad6d97695a248315a767668 3312da54b0e5d7ab6906c4b3db58b9ef 2affb48e0000000095a248315a767668 3312da54b0e5d7ab6906c4b3db58b9ef fpscr=00000000
+vrintz.f32.f32 s2, s11 aedca69f6cac59f9348174dc063a0883 60559a865820f649da633b7c372cb744 aedca69f60559a86348174dc063a0883 60559a865820f649da633b7c372cb744 fpscr=00000000
+vrintz.f32.f32 s2, s11 af54c83c44d2e29fafb6f469d27359a3 d85d8ca35eae245e626786ad633d7e8e af54c83cd85d8ca3afb6f469d27359a3 d85d8ca35eae245e626786ad633d7e8e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintz.f32.f32 s2, s11 5301c1db71fa1e79fafc820ad57d6640 835144998351449986df7992b0c8ec60 5301c1db80000000fafc820ad57d6640 835144998351449986df7992b0c8ec60 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[2]
+vrintz.f32.f32 s2, s11 c8fa04a2228742108523f571500928e7 06079193c7090907d3879afd0e0e65e8 c8fa04a2000000008523f571500928e7 06079193c7090907d3879afd0e0e65e8 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintz.f32.f32 s2, s11 a44d935ec701f7206ecb9a1b984c83fd 9ac449a64501f4367729a83f9ac449a6 a44d935e800000006ecb9a1b984c83fd 9ac449a64501f4367729a83f9ac449a6 fpscr=00000000
+vrintz.f32.f32 s2, s11 d638b970901895e9ebd1dad9a8080eff 616f362291247576bd81131b227eb64a d638b970616f3622ebd1dad9a8080eff 616f362291247576bd81131b227eb64a fpscr=00000000
+vrintz.f32.f32 s2, s11 fdb0334348b3a4015c63db92b51bfe90 e2654cff78e4cb1a06ee2e9f6c9bd891 fdb03343e2654cff5c63db92b51bfe90 e2654cff78e4cb1a06ee2e9f6c9bd891 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[1]
+vrintz.f32.f32 s2, s11 b3b3ae9063131c63eac94939045af525 2dd00af52dd00af50da27324dc2c8c76 b3b3ae9000000000eac94939045af525 2dd00af52dd00af50da27324dc2c8c76 fpscr=00000000
+vrintz.f32.f32 s2, s11 033d58ff0a0ea1f13d6e580f2885d2cd 0f6026fd616d07c0528eacccc38c65f1 033d58ff000000003d6e580f2885d2cd 0f6026fd616d07c0528eacccc38c65f1 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintz.f32.f32 s2, s11 1c0fab6c00f73a307b7cf12682b6a7c4 d9598a9525ed83ab84b0d5bbc2be48bd 1c0fab6cd9598a957b7cf12682b6a7c4 d9598a9525ed83ab84b0d5bbc2be48bd fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintz.f32.f32 s2, s11 40ea1a20521ce3e784fd9db2137e559d a654bb5bd8ea84dc794c10b1d92afd73 40ea1a208000000084fd9db2137e559d a654bb5bd8ea84dc794c10b1d92afd73 fpscr=00000000
+vrintz.f32.f32 s2, s11 0c08d9ab18d0b0aa0116eca03ecfdb8a 746686edf6145735d404908c410cefda 0c08d9ab746686ed0116eca03ecfdb8a 746686edf6145735d404908c410cefda fpscr=00000000
+vrintz.f32.f32 s2, s11 c852808ddf7537f8e31a6bb91c303c6a 9ee80bb80237c3ff9ce0c8037150f356 c852808d80000000e31a6bb91c303c6a 9ee80bb80237c3ff9ce0c8037150f356 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintz.f32.f32 s2, s11 a01b886540c741a4757479cbfdd9c13f f1adfba4ab2690b32cabfdc0086a45d6 a01b8865f1adfba4757479cbfdd9c13f f1adfba4ab2690b32cabfdc0086a45d6 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[3]
+vrintz.f32.f32 s2, s11 a10917c343a6971d66a2a321a10917c3 8ef0afe3bcf801fa8ef0afe38cfeb102 a10917c38000000066a2a321a10917c3 8ef0afe3bcf801fa8ef0afe38cfeb102 fpscr=00000000
+vrintz.f32.f32 s2, s11 cf324e97e9d416aa5f258cc7180d9e95 9d83ffbf9f44c64ef1d34739dda623ba cf324e97800000005f258cc7180d9e95 9d83ffbf9f44c64ef1d34739dda623ba fpscr=00000000
+vrintz.f32.f32 s2, s11 73c8879edb35e295a575447ed866b067 b49339eff5e0946b2764c6c2279bebeb 73c8879e80000000a575447ed866b067 b49339eff5e0946b2764c6c2279bebeb fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintz.f32.f32 s2, s11 9a886cd6c297e00411741a8e96458f6e 9695dfc6d491fe21bd015e93e2d26cac 9a886cd68000000011741a8e96458f6e 9695dfc6d491fe21bd015e93e2d26cac fpscr=00000000
+vrintz.f32.f32 s2, s11 98aeed9a6dee30fe1eb4f2712203d4d1 f20a3b019919ec167280b7fd5d198ae1 98aeed9af20a3b011eb4f2712203d4d1 f20a3b019919ec167280b7fd5d198ae1 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintz.f32.f32 s2, s11 87c0282ecc7c1f11e7d8dd1bcc7c1f11 b5cf216142d8df4cdf8cec148245df80 87c0282e80000000e7d8dd1bcc7c1f11 b5cf216142d8df4cdf8cec148245df80 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintz.f32.f32 s2, s11 58d408f5089ab15036b1e40867311fe2 6ec30a3773c42c24604ce053ce59dd47 58d408f56ec30a3736b1e40867311fe2 6ec30a3773c42c24604ce053ce59dd47 fpscr=00000000
+vrintz.f32.f32 s2, s11 ff6a47cb90e22fb0f9e48653759bed0f cee4f6ae8db3f25edf9d093780fa911f ff6a47cbcee4f6aef9e48653759bed0f cee4f6ae8db3f25edf9d093780fa911f fpscr=00000000
+vrintz.f32.f32 s2, s11 c334329b2f133816d16baad432342a9d 37f84b83e9f0e8e29efcd4559344d807 c334329b00000000d16baad432342a9d 37f84b83e9f0e8e29efcd4559344d807 fpscr=00000000
+vrintz.f32.f32 s2, s11 0c3f16855fa96515c5280a1ee85ba99f 218c42518f73ec71cf5a1f3085937488 0c3f168500000000c5280a1ee85ba99f 218c42518f73ec71cf5a1f3085937488 fpscr=00000000
+vrintreq.f32.f32 s3, s12 5a33d61ad59f42f5ae5198239f099f44 2017a5485b70c72869191817e101fa78 5a33d61ad59f42f5ae5198239f099f44 2017a5485b70c72869191817e101fa78 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintreq.f32.f32 s3, s12 c4da9a53307021ac7f576c2f8f8bab25 5e22bc9326fc98252c2c7c3524cb2d55 c4da9a53307021ac7f576c2f8f8bab25 5e22bc9326fc98252c2c7c3524cb2d55 fpscr=00000000
+vrintreq.f32.f32 s3, s12 5720678d0a07851e75faf48b479ee9c7 1212f12f3615c11c60603947c295f5a2 5720678d0a07851e75faf48b479ee9c7 1212f12f3615c11c60603947c295f5a2 fpscr=00000000
+randV128: 9216 calls, 9508 iters
+vrintreq.f32.f32 s3, s12 7915b1f770bece9818db2227ebf788e5 b8278e8c6b0b46b3e26b07eca1ffbad9 7915b1f770bece9818db2227ebf788e5 b8278e8c6b0b46b3e26b07eca1ffbad9 fpscr=00000000
+vrintreq.f32.f32 s3, s12 4f08923ab2ec387d5e5de0ad5d5a7c54 4606a3030387d24dec11b55bf1b19070 4f08923ab2ec387d5e5de0ad5d5a7c54 4606a3030387d24dec11b55bf1b19070 fpscr=00000000
+vrintreq.f32.f32 s3, s12 c8bc8977328452471edb18b3025e7c2c e138cc5ffdd099cffdd3c65ff6069c05 c8bc8977328452471edb18b3025e7c2c e138cc5ffdd099cffdd3c65ff6069c05 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintreq.f32.f32 s3, s12 c85e93b48eec17cd878df80a9d4132fa d2f8a7e6149d5c06494434fa05ebc9a1 c85e93b48eec17cd878df80a9d4132fa d2f8a7e6149d5c06494434fa05ebc9a1 fpscr=00000000
+vrintreq.f32.f32 s3, s12 f98942d5657cae3bf4223958e32ae47f 4c22d08595dda82c0c9c85363f12214a f98942d5657cae3bf4223958e32ae47f 4c22d08595dda82c0c9c85363f12214a fpscr=00000000
+vrintreq.f32.f32 s3, s12 58681fcd191da9dbeec1fe7d390537ec 4e43f1bc68c8c14aa379377201b8b93b 58681fcd191da9dbeec1fe7d390537ec 4e43f1bc68c8c14aa379377201b8b93b fpscr=00000000
+vrintreq.f32.f32 s3, s12 9ccde6e39a4afb6f46665ba67634b9ee 965d37e97cae300ed8733e918f8c4ddb 9ccde6e39a4afb6f46665ba67634b9ee 965d37e97cae300ed8733e918f8c4ddb fpscr=00000000
+vrintreq.f32.f32 s3, s12 db3a7aa7c3ef021e336cc2fffb03a73a 792161ace75fa572c75e8de1df131b08 db3a7aa7c3ef021e336cc2fffb03a73a 792161ace75fa572c75e8de1df131b08 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintreq.f32.f32 s3, s12 6ddcd878b873e5840e0246f0d45d0671 a0520243d95ad1963e7173fce48876c8 6ddcd878b873e5840e0246f0d45d0671 a0520243d95ad1963e7173fce48876c8 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vrintreq.f32.f32 s3, s12 35b714ea1b00d33a2c10aa3b4fddd976 4b701fed423fcbc1423fcbc148d6c99b 35b714ea1b00d33a2c10aa3b4fddd976 4b701fed423fcbc1423fcbc148d6c99b fpscr=00000000
+vrintreq.f32.f32 s3, s12 f82eb5a6cd683cfb7f2061c83794a415 8784c74fad4c550b9425d0f9e5237ae4 f82eb5a6cd683cfb7f2061c83794a415 8784c74fad4c550b9425d0f9e5237ae4 fpscr=00000000
+vrintreq.f32.f32 s3, s12 b83fcd9961e8949b8fb6f778ee232f3f 34be464f2408c103b4c0ad428ff6d88a b83fcd9961e8949b8fb6f778ee232f3f 34be464f2408c103b4c0ad428ff6d88a fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintreq.f32.f32 s3, s12 7bac317f9f90a50bdf5b532874c87065 54c021567678f66344a819944cc4a1e8 7bac317f9f90a50bdf5b532874c87065 54c021567678f66344a819944cc4a1e8 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintreq.f32.f32 s3, s12 ddb6af8aa1472aeb34ca1fa2ef11139a ef7d8bf65e6c49a71c238d2128d313ed ddb6af8aa1472aeb34ca1fa2ef11139a ef7d8bf65e6c49a71c238d2128d313ed fpscr=00000000
+vrintreq.f32.f32 s3, s12 f81385e5412dfabd6ce1a16d4c81d106 4cb3aa91c8cb834b80aa7f092cb90780 f81385e5412dfabd6ce1a16d4c81d106 4cb3aa91c8cb834b80aa7f092cb90780 fpscr=00000000
+vrintreq.f32.f32 s3, s12 d7424f73dd185b1a86ecccc0db05c88a 23e37875c43e845a0cbef2c549498544 d7424f73dd185b1a86ecccc0db05c88a 23e37875c43e845a0cbef2c549498544 fpscr=00000000
+vrintreq.f32.f32 s3, s12 b1d1ff3de12b6f02af9633119a4f341f 5ff88e26c53bcc039defef9e6a3a9ccd b1d1ff3de12b6f02af9633119a4f341f 5ff88e26c53bcc039defef9e6a3a9ccd fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintreq.f32.f32 s3, s12 1de241d8c3c2182bb724bf7a50edef2a 3188c7ff1d78d7e2ce16c8bb3188c7ff 1de241d8c3c2182bb724bf7a50edef2a 3188c7ff1d78d7e2ce16c8bb3188c7ff fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintreq.f32.f32 s3, s12 7cef43fa17f64823025e5eb97188388d a9ada46cf9ab123826cfa7b93e559d56 7cef43fa17f64823025e5eb97188388d a9ada46cf9ab123826cfa7b93e559d56 fpscr=00000000
+vrintreq.f32.f32 s3, s12 9c235f93d9362529a6590ce39ac0f039 f41506a54347acec25e494d285c878c3 9c235f93d9362529a6590ce39ac0f039 f41506a54347acec25e494d285c878c3 fpscr=00000000
+vrintreq.f32.f32 s3, s12 171ebca102e4df0f81689743aecafc6b b78ba8e421dd2e4eb88b0feb5e39586b 171ebca102e4df0f81689743aecafc6b b78ba8e421dd2e4eb88b0feb5e39586b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintreq.f32.f32 s3, s12 4ca557a207779ad0c9e3b7712cc1b29e b1dca6333a560cb61240acc76b8a318c 4ca557a207779ad0c9e3b7712cc1b29e b1dca6333a560cb61240acc76b8a318c fpscr=00000000
+vrintreq.f32.f32 s3, s12 1cdfeebc2573ad7afddc760c76e33d4c 54540777163e03924158e6cac8581d45 1cdfeebc2573ad7afddc760c76e33d4c 54540777163e03924158e6cac8581d45 fpscr=00000000
+vrintreq.f32.f32 s3, s12 723871c25227a40c3c342f1c2b5da889 1c775c5d1764435cbd07a347808987ec 723871c25227a40c3c342f1c2b5da889 1c775c5d1764435cbd07a347808987ec fpscr=00000000
+vrintreq.f32.f32 s3, s12 50ea798385bf1a41c2e4c9baafd4f2f7 e84738b1c83a5d6095e60d2819e4ba35 50ea798385bf1a41c2e4c9baafd4f2f7 e84738b1c83a5d6095e60d2819e4ba35 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintreq.f32.f32 s3, s12 b5a93c908d6e50706f121f044c773d26 f78dc1b86b8514c6f78dc1b830b9c4ba b5a93c908d6e50706f121f044c773d26 f78dc1b86b8514c6f78dc1b830b9c4ba fpscr=00000000
+vrintreq.f32.f32 s3, s12 4448bec9f4755acf3c21207452e71090 7db0ea7635f9105eace39750897e0850 4448bec9f4755acf3c21207452e71090 7db0ea7635f9105eace39750897e0850 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintreq.f32.f32 s3, s12 b95b6334e63cd57bb435b28c15e2e85b c1c05fe630929c9402e65cb60e0dcb89 b95b6334e63cd57bb435b28c15e2e85b c1c05fe630929c9402e65cb60e0dcb89 fpscr=00000000
+vrintreq.f32.f32 s3, s12 ddf3b2375b00e86710bf5751a5027d6c 89c47dace912164b8084aee235e8fe61 ddf3b2375b00e86710bf5751a5027d6c 89c47dace912164b8084aee235e8fe61 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintreq.f32.f32 s3, s12 b147fd9d2f6b3c002be154ccc5403749 74ed0004e75c84f14440b2b6fe286dbe b147fd9d2f6b3c002be154ccc5403749 74ed0004e75c84f14440b2b6fe286dbe fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintreq.f32.f32 s3, s12 8a7c115d364e226c45ac6bc766170711 25e09d54b0e0033bfbf2f215894d4632 8a7c115d364e226c45ac6bc766170711 25e09d54b0e0033bfbf2f215894d4632 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintreq.f32.f32 s3, s12 d1eba14f20de285320de28531bcd1af0 11f0536652886f31402abb50a41c05c9 d1eba14f20de285320de28531bcd1af0 11f0536652886f31402abb50a41c05c9 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintreq.f32.f32 s3, s12 2ad977cb3f8e6e0bcbbee271ecfa3550 3e5db93f3e5db93f10f34e3f9b947189 2ad977cb3f8e6e0bcbbee271ecfa3550 3e5db93f3e5db93f10f34e3f9b947189 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[2]
+vrintreq.f32.f32 s3, s12 8d4c69958d4c6995ece025605cdece48 664ac83b664ac83bf3c9d36d17fb9706 8d4c69958d4c6995ece025605cdece48 664ac83b664ac83bf3c9d36d17fb9706 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[3]
+vrintreq.f32.f32 s3, s12 7cf84b3485e3d8126cae58c1c05bb7c1 57113deca5c9bd99ed262544a5c9bd99 7cf84b3485e3d8126cae58c1c05bb7c1 57113deca5c9bd99ed262544a5c9bd99 fpscr=00000000
+vrintreq.f32.f32 s3, s12 7204c2681229b69ff93c8f2dd375efa1 1159376f58f8f0421c7a4409b6148f49 7204c2681229b69ff93c8f2dd375efa1 1159376f58f8f0421c7a4409b6148f49 fpscr=00000000
+vrintreq.f32.f32 s3, s12 6f735bf5029b5ee1d507bd994e7b96d2 a3ff282d2c8dd8a06649f3a637380ee9 6f735bf5029b5ee1d507bd994e7b96d2 a3ff282d2c8dd8a06649f3a637380ee9 fpscr=00000000
+vrintreq.f32.f32 s3, s12 c836f55bcf15290b9889a75168bc4ed7 0bd32b3a5bcfc6c5fe87b97404ed297b c836f55bcf15290b9889a75168bc4ed7 0bd32b3a5bcfc6c5fe87b97404ed297b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintreq.f32.f32 s3, s12 00bdac85222a36f4222a36f4b383f11e 937dc68ac64198508160d4092f553bfe 00bdac85222a36f4222a36f4b383f11e 937dc68ac64198508160d4092f553bfe fpscr=00000000
+vrintreq.f32.f32 s3, s12 bd43d286aa00620f195a8b9008e34811 222bd04ef46e538b9f4ffde547fa6e8f bd43d286aa00620f195a8b9008e34811 222bd04ef46e538b9f4ffde547fa6e8f fpscr=00000000
+vrintreq.f32.f32 s3, s12 eb8a3fdfdd77e333cc1ef280a1cf7e82 c563548659ec2e29d2922d32ee329973 eb8a3fdfdd77e333cc1ef280a1cf7e82 c563548659ec2e29d2922d32ee329973 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintreq.f32.f32 s3, s12 c9ccd9a51287fae6953610e5953610e5 a21dc48d5ca5807a59efd2fdaf188cc7 c9ccd9a51287fae6953610e5953610e5 a21dc48d5ca5807a59efd2fdaf188cc7 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintreq.f32.f32 s3, s12 fd82ee4bf670f3f7f9fc4ec5a038c5e1 6c249aa4e9d784ef438ea2dfb6bbee3d fd82ee4bf670f3f7f9fc4ec5a038c5e1 6c249aa4e9d784ef438ea2dfb6bbee3d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintreq.f32.f32 s3, s12 088d72cdc90c8e9bd2629179d2629179 6232591d107c8fcc61776c8e1b94b650 088d72cdc90c8e9bd2629179d2629179 6232591d107c8fcc61776c8e1b94b650 fpscr=00000000
+vrintreq.f32.f32 s3, s12 37b0713bca62527f94c395f1f16647a5 6758b9f6259b8f90e8e70e5e77bf0ef3 37b0713bca62527f94c395f1f16647a5 6758b9f6259b8f90e8e70e5e77bf0ef3 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintreq.f32.f32 s3, s12 e79bf7371589a9fc3836922a79312d91 e5e8b23c45bf16352fa21ea1408be8e8 e79bf7371589a9fc3836922a79312d91 e5e8b23c45bf16352fa21ea1408be8e8 fpscr=00000000
+vrintreq.f32.f32 s3, s12 488867eaf2b9c7ff7c1de2472f5e5f45 7d1e878c116b0d4765f2424e59207f6b 488867eaf2b9c7ff7c1de2472f5e5f45 7d1e878c116b0d4765f2424e59207f6b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintrne.f32.f32 s4, s13 2ef7bcfe92104bd2e233fb357a0d0ef2 ae946f3bafe4e50e1242e2e18599c93f 2ef7bcfe92104bd2e233fb3500000000 ae946f3bafe4e50e1242e2e18599c93f fpscr=00000000
+vrintrne.f32.f32 s4, s13 abdb215b19aec98b104970a6adb5d18e c57ea78d9ef2beb08557f457cb67c8b0 abdb215b19aec98b104970a680000000 c57ea78d9ef2beb08557f457cb67c8b0 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[2]
+vrintrne.f32.f32 s4, s13 0546ead80546ead83e1d4e1dc94d442c bb68fe8fada9b563fb3601a0fe5091b1 0546ead80546ead83e1d4e1dfb3601a0 bb68fe8fada9b563fb3601a0fe5091b1 fpscr=00000000
+vrintrne.f32.f32 s4, s13 66c3cec2ab7d7be0ee321a7b36117d98 0d48392167a74acaa2c4559ef025bddb 66c3cec2ab7d7be0ee321a7b80000000 0d48392167a74acaa2c4559ef025bddb fpscr=00000000
+vrintrne.f32.f32 s4, s13 4ec4d1b6e3a67cf8a8f5243e7d22939c 0941b0a0b9d601ecb38bfe31e8c5706d 4ec4d1b6e3a67cf8a8f5243e80000000 0941b0a0b9d601ecb38bfe31e8c5706d fpscr=00000000
+vrintrne.f32.f32 s4, s13 be91e0a0c02ced58daa4b26933a297e1 aa172089952096e80e573cf7d2f4be9a be91e0a0c02ced58daa4b26900000000 aa172089952096e80e573cf7d2f4be9a fpscr=00000000
+vrintrne.f32.f32 s4, s13 c1ebe4ec8d19d7435a540feb2c1b5076 d46568e8e96658b46120166f6dab4a22 c1ebe4ec8d19d7435a540feb6120166f d46568e8e96658b46120166f6dab4a22 fpscr=00000000
+vrintrne.f32.f32 s4, s13 b2894d0ad4e4f06a136732edfe9d17d0 ff0b368abe435ca85de5affacc208d13 b2894d0ad4e4f06a136732ed5de5affa ff0b368abe435ca85de5affacc208d13 fpscr=00000000
+vrintrne.f32.f32 s4, s13 025db5c74b5b58e40b0a9f6530dbd0ff 6c7ec81c1275e4c0333f53426773843d 025db5c74b5b58e40b0a9f6500000000 6c7ec81c1275e4c0333f53426773843d fpscr=00000000
+vrintrne.f32.f32 s4, s13 ef375b00a5e535825720231047bccf3e bbf014270d2c25b667c9dc6d9437b095 ef375b00a5e535825720231067c9dc6d bbf014270d2c25b667c9dc6d9437b095 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintrne.f32.f32 s4, s13 0cd083ba3b29358ae88673c7b7378df0 e26450f4943a6d045de87f735de87f73 0cd083ba3b29358ae88673c75de87f73 e26450f4943a6d045de87f735de87f73 fpscr=00000000
+vrintrne.f32.f32 s4, s13 34b43211ad54b22bb0979e15eac435b9 ab07d095477e819bd5434321a5bd3aab 34b43211ad54b22bb0979e15d5434321 ab07d095477e819bd5434321a5bd3aab fpscr=00000000
+vrintrne.f32.f32 s4, s13 180d2361987b4a60c9ac064305facdde 6293b9ce3d4b9cde68ebc1fd3e514772 180d2361987b4a60c9ac064368ebc1fd 6293b9ce3d4b9cde68ebc1fd3e514772 fpscr=00000000
+vrintrne.f32.f32 s4, s13 0f4f38c4e46e81bc10b99bbf7bc6c624 0fdcb534c67facb1dd5b77597225da43 0f4f38c4e46e81bc10b99bbfdd5b7759 0fdcb534c67facb1dd5b77597225da43 fpscr=00000000
+vrintrne.f32.f32 s4, s13 0e2d4bd75dba534e03bca72e7bcf058e 6ea96a68b481185f1ef5a4d4eb17c1e4 0e2d4bd75dba534e03bca72e00000000 6ea96a68b481185f1ef5a4d4eb17c1e4 fpscr=00000000
+vrintrne.f32.f32 s4, s13 5edb60bf8419f6c71be9a35453587317 e55015adba260b66934ed6b7cbd50215 5edb60bf8419f6c71be9a35480000000 e55015adba260b66934ed6b7cbd50215 fpscr=00000000
+vrintrne.f32.f32 s4, s13 ff2655d41224adc268fe24f9283b0737 0993241993b2a9c9e648be600d23501c ff2655d41224adc268fe24f9e648be60 0993241993b2a9c9e648be600d23501c fpscr=00000000
+randV128: 9472 calls, 9772 iters
+vrintrne.f32.f32 s4, s13 dfe56ea1526e746d11fdab2e9a3db5ce 835d2aa08bb4a53b2717658e52f1e235 dfe56ea1526e746d11fdab2e00000000 835d2aa08bb4a53b2717658e52f1e235 fpscr=00000000
+vrintrne.f32.f32 s4, s13 556135015fc6392c5817c4930260a7dc 2d50f33f0807776bbf5948939e8148e0 556135015fc6392c5817c493bf800000 2d50f33f0807776bbf5948939e8148e0 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[3]
+vrintrne.f32.f32 s4, s13 8399839a892a77bdd39be003d39be003 700bd9b003fb8ca13e2233f10ba855c5 8399839a892a77bdd39be00300000000 700bd9b003fb8ca13e2233f10ba855c5 fpscr=00000000
+vrintrne.f32.f32 s4, s13 a697516816a29d0de3460687f650636c 55f8bb08d8af4c56ef3f9a7424031fc7 a697516816a29d0de3460687ef3f9a74 55f8bb08d8af4c56ef3f9a7424031fc7 fpscr=00000000
+vrintrne.f32.f32 s4, s13 d6768dac85fbc6d7ab06324b012fc795 9e85c4d3f498080e1a9c7990cbe325c5 d6768dac85fbc6d7ab06324b00000000 9e85c4d3f498080e1a9c7990cbe325c5 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintrne.f32.f32 s4, s13 76b546d32143290a361bc5d79105d916 b42587c8040826df0724c550a4c70cb6 76b546d32143290a361bc5d700000000 b42587c8040826df0724c550a4c70cb6 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintrne.f32.f32 s4, s13 e3781390af012db4d9177509fd3bfbe1 2abc26a06fcf6327e8c853ebd5b1c575 e3781390af012db4d9177509e8c853eb 2abc26a06fcf6327e8c853ebd5b1c575 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintrne.f32.f32 s4, s13 77c408f4a0595f694c29d2f5c340b7eb c895843109b267243c0fd37f4f7f2fcd 77c408f4a0595f694c29d2f500000000 c895843109b267243c0fd37f4f7f2fcd fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintrne.f32.f32 s4, s13 0d66438471d90fbdb5c78c54c6f5877a 7b35161723ebcd72e0dd676723ebcd72 0d66438471d90fbdb5c78c54e0dd6767 7b35161723ebcd72e0dd676723ebcd72 fpscr=00000000
+vrintrne.f32.f32 s4, s13 8d859a9a23da455855021ce1855fb5f1 97665306fb2bf01938082f14c47d3037 8d859a9a23da455855021ce100000000 97665306fb2bf01938082f14c47d3037 fpscr=00000000
+vrintrne.f32.f32 s4, s13 161a1d2899820e4ab8910bccdd73794a b22c9714591c07e6603b2086c0d3b38e 161a1d2899820e4ab8910bcc603b2086 b22c9714591c07e6603b2086c0d3b38e fpscr=00000000
+vrintrne.f32.f32 s4, s13 760265f0c9da51b9e0bfa3928c51a312 f2ab39190268bba731c693de35c1713f 760265f0c9da51b9e0bfa39200000000 f2ab39190268bba731c693de35c1713f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintrne.f32.f32 s4, s13 9c4422aed17d78cc76cfb569449b39d2 08679eb708679eb7ced62ce27f4356cf 9c4422aed17d78cc76cfb569ced62ce2 08679eb708679eb7ced62ce27f4356cf fpscr=00000000
+vrintrne.f32.f32 s4, s13 a3a475b098b1aef810d5c483a9adfd5a 35bd2c98e2756709cf8a6073266a7756 a3a475b098b1aef810d5c483cf8a6073 35bd2c98e2756709cf8a6073266a7756 fpscr=00000000
+vrintrne.f32.f32 s4, s13 115cc978cbff3a021b17d6ede9462f75 c462c8c9d4caab55b0815819a4495bae 115cc978cbff3a021b17d6ed80000000 c462c8c9d4caab55b0815819a4495bae fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[2]
+vrintrne.f32.f32 s4, s13 4a58fa208ede0c113af073ab376ef384 6a013dd98a4ef8c46e1e12576e1e1257 4a58fa208ede0c113af073ab6e1e1257 6a013dd98a4ef8c46e1e12576e1e1257 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[2]
+vrintrne.f32.f32 s4, s13 aa0200d6337b2bf5a3da6fb73552bf5c 07e6372007e6372075b6a7da6c842ce8 aa0200d6337b2bf5a3da6fb775b6a7da 07e6372007e6372075b6a7da6c842ce8 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[1]
+vrintrne.f32.f32 s4, s13 f4e43c4646e88e752db5b60a0e345950 f0e405e3ad16548a1761811aad16548a f4e43c4646e88e752db5b60a00000000 f0e405e3ad16548a1761811aad16548a fpscr=00000000
+vrintrne.f32.f32 s4, s13 11da416c7f0d11939f38aed5fd1c6c35 ad8af7ea172a4d04db100a8a8ee941db 11da416c7f0d11939f38aed5db100a8a ad8af7ea172a4d04db100a8a8ee941db fpscr=00000000
+vrintrne.f32.f32 s4, s13 06c43b96746668be2e9259bd0152856b 3756558e0b4406846da4cc00fb6b2d4c 06c43b96746668be2e9259bd6da4cc00 3756558e0b4406846da4cc00fb6b2d4c fpscr=00000000
+vrintrne.f32.f32 s4, s13 d4ce0b3c04a0995469846e0301444364 a5a5ef4ccc672ecf4a0a00b54e3c50d5 d4ce0b3c04a0995469846e034a0a00b4 a5a5ef4ccc672ecf4a0a00b54e3c50d5 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintrne.f32.f32 s4, s13 d194359c2d4da5f1c234d63bd194359c 054605bd035cbc847d3159309825caba d194359c2d4da5f1c234d63b7d315930 054605bd035cbc847d3159309825caba fpscr=00000000
+vrintrne.f32.f32 s4, s13 72ec3532613242e58e5c540bfc6722e1 0fbab5bf95918f61e8af41aaa2893d93 72ec3532613242e58e5c540be8af41aa 0fbab5bf95918f61e8af41aaa2893d93 fpscr=00000000
+vrintrne.f32.f32 s4, s13 35d86e9b940f5b2b9af570b632122a67 bf870f78b4f4a77b88cb5cb9c9b493f7 35d86e9b940f5b2b9af570b680000000 bf870f78b4f4a77b88cb5cb9c9b493f7 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintrne.f32.f32 s4, s13 4b124b2e6c940b8e6c940b8eebc43b0b 4e115535880e1d47c7dee11d13393dd5 4b124b2e6c940b8e6c940b8ec7dee100 4e115535880e1d47c7dee11d13393dd5 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintrne.f32.f32 s4, s13 db148f410800531f865509b51061dada 2313ccbc218b455d28cd89d38e74f714 db148f410800531f865509b500000000 2313ccbc218b455d28cd89d38e74f714 fpscr=00000000
+vrintrne.f32.f32 s4, s13 0bc41c56b8d73f6dd918bf16ad198893 094627f8a2a23f53bd5df052290fcccb 0bc41c56b8d73f6dd918bf1680000000 094627f8a2a23f53bd5df052290fcccb fpscr=00000000
+vrintrne.f32.f32 s4, s13 2bd6e80ccecab45ceaef46a993b3aba8 0e5940f9fcffdf68fadb0cade9251b46 2bd6e80ccecab45ceaef46a9fadb0cad 0e5940f9fcffdf68fadb0cade9251b46 fpscr=00000000
+vrintrne.f32.f32 s4, s13 f601474e91a504e4feff1d6c8a01d027 2d661b4a2f542fa076dd5fa032baeb03 f601474e91a504e4feff1d6c76dd5fa0 2d661b4a2f542fa076dd5fa032baeb03 fpscr=00000000
+vrintrne.f32.f32 s4, s13 1e3b346faf023550209aff4979c437e3 b453800ea34b82ae3cb15c9dd6be0781 1e3b346faf023550209aff4900000000 b453800ea34b82ae3cb15c9dd6be0781 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintrne.f32.f32 s4, s13 8335ebc3e95d1f892f7ff0c5b914b99d 8f6a09231c59a513cbb1fcd7965027d2 8335ebc3e95d1f892f7ff0c5cbb1fcd7 8f6a09231c59a513cbb1fcd7965027d2 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintrne.f32.f32 s4, s13 2b0676eabeddf9b01dca0c4bbeddf9b0 98c16a189dd1d3a252bc37d05c3798eb 2b0676eabeddf9b01dca0c4b52bc37d0 98c16a189dd1d3a252bc37d05c3798eb fpscr=00000000
+vrintrne.f32.f32 s4, s13 3773d079055e3a0b9d59e8512f42a39b 20f0ddf00755bb14cda21c59884b9b67 3773d079055e3a0b9d59e851cda21c59 20f0ddf00755bb14cda21c59884b9b67 fpscr=00000000
+vrintr.f32.f32 s5, s14 c4044c8ca87a0d46e4712d49c8b9c85c 5ba802b295bdf421b6764fdec88f65cb c4044c8ca87a0d4680000000c8b9c85c 5ba802b295bdf421b6764fdec88f65cb fpscr=00000000
+vrintr.f32.f32 s5, s14 5e1d0179b99f7feb9054810c92daa0b1 4b7a07483603ec672959962255407041 5e1d0179b99f7feb0000000092daa0b1 4b7a07483603ec672959962255407041 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintr.f32.f32 s5, s14 a2810252f89397891e1321e1bc24a552 fa216c76a75e5f8e72f2f470fa216c76 a2810252f893978980000000bc24a552 fa216c76a75e5f8e72f2f470fa216c76 fpscr=00000000
+vrintr.f32.f32 s5, s14 5c66c23e54cb4a7d16ae7fa60fe5f337 af445da7b3cc9be9f340d8c4ab9c27bb 5c66c23e54cb4a7d800000000fe5f337 af445da7b3cc9be9f340d8c4ab9c27bb fpscr=00000000
+vrintr.f32.f32 s5, s14 3bdf35a81626c9754edff07d4ac39d64 bbf1dff955eb7fcf6e4d85fa5df158fd 3bdf35a81626c97555eb7fcf4ac39d64 bbf1dff955eb7fcf6e4d85fa5df158fd fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[3]
+vrintr.f32.f32 s5, s14 518e97de44aeb941b1c1eac8518e97de 2e2e064c2e2e064ca7cce8a090ee3425 518e97de44aeb94100000000518e97de 2e2e064c2e2e064ca7cce8a090ee3425 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintr.f32.f32 s5, s14 29d2cadb2877c9a04940ae5b07d8b2d5 fc5e036f1e08aa3b1cf52bef1cf52bef 29d2cadb2877c9a00000000007d8b2d5 fc5e036f1e08aa3b1cf52bef1cf52bef fpscr=00000000
+vrintr.f32.f32 s5, s14 3e6cf017afd55687ae5d3c0948e85745 4c795d6e8ddb0736d4be2a46fa5187e8 3e6cf017afd556878000000048e85745 4c795d6e8ddb0736d4be2a46fa5187e8 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintr.f32.f32 s5, s14 8cde6bb706ebebff8cde6bb715aa861d 37014f45105abe46ca30c42901129b51 8cde6bb706ebebff0000000015aa861d 37014f45105abe46ca30c42901129b51 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintr.f32.f32 s5, s14 c9c2a52c7a613928afa1d3d204c53377 88e36ec0a9e5717acdc01b0f88e36ec0 c9c2a52c7a6139288000000004c53377 88e36ec0a9e5717acdc01b0f88e36ec0 fpscr=00000000
+vrintr.f32.f32 s5, s14 b530c37173f13ca899a2c13239c3933e ed2a9667de4b459903f70cbe337a357f b530c37173f13ca8de4b459939c3933e ed2a9667de4b459903f70cbe337a357f fpscr=00000000
+vrintr.f32.f32 s5, s14 25a6751819ea54a82ea64bae0e90a6ed 20ef8a5e8bf79f99f1bdf9a250a8bf6e 25a6751819ea54a8800000000e90a6ed 20ef8a5e8bf79f99f1bdf9a250a8bf6e fpscr=00000000
+vrintr.f32.f32 s5, s14 b123d31d5b83837819283ef47959d633 832af8af6d72f765cd59065d323603df b123d31d5b8383786d72f7657959d633 832af8af6d72f765cd59065d323603df fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintr.f32.f32 s5, s14 95c4308f954b62b6fc298943954b62b6 a030e0ee86d93bd5577293d9881c1230 95c4308f954b62b680000000954b62b6 a030e0ee86d93bd5577293d9881c1230 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintr.f32.f32 s5, s14 63ba5c671abbbc9b74414f7b3f0ce7fa b6c202f108c0428f70bd5869fbc5c93b 63ba5c671abbbc9b000000003f0ce7fa b6c202f108c0428f70bd5869fbc5c93b fpscr=00000000
+vrintr.f32.f32 s5, s14 53c0a60f29af65b32abe8ed791d3bb0e 59c18663fe60072c05a377fd68e345c9 53c0a60f29af65b3fe60072c91d3bb0e 59c18663fe60072c05a377fd68e345c9 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintr.f32.f32 s5, s14 2174e4aa044d67fb290924c12174e4aa d121ea41b5d1eae36f626004f673cb89 2174e4aa044d67fb800000002174e4aa d121ea41b5d1eae36f626004f673cb89 fpscr=00000000
+vrintr.f32.f32 s5, s14 0fe3382a5f457e1a8133d567dc83696c 1dfb0265cea5f7791a7eee6d42c4dbbc 0fe3382a5f457e1acea5f779dc83696c 1dfb0265cea5f7791a7eee6d42c4dbbc fpscr=00000000
+vrintr.f32.f32 s5, s14 b67d2ba6fc4a83aa03d4c1d6fadfa095 5387cedca1eb4edbbad4f6d16c2b6bc4 b67d2ba6fc4a83aa80000000fadfa095 5387cedca1eb4edbbad4f6d16c2b6bc4 fpscr=00000000
+vrintr.f32.f32 s5, s14 fd97f47b121b7b0c90fb9059510f28b7 c857d8cd7dc3725edbcfe6f5bbdad25a fd97f47b121b7b0c7dc3725e510f28b7 c857d8cd7dc3725edbcfe6f5bbdad25a fpscr=00000000
+vrintr.f32.f32 s5, s14 90b258bb42500a6e82320583ba6d08d3 0a1b0e6243bb2368b5cb2510fd8257f3 90b258bb42500a6e43bb0000ba6d08d3 0a1b0e6243bb2368b5cb2510fd8257f3 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vrintr.f32.f32 s5, s14 e201b384d6f5ab5dd8f6e878e61fa76a 561c94beb4a97443b4a974435b7f47d3 e201b384d6f5ab5d80000000e61fa76a 561c94beb4a97443b4a974435b7f47d3 fpscr=00000000
+vrintr.f32.f32 s5, s14 a2ba118e74be7ddf5678012a3cd0be39 bef21083ff3b12976721285d1e23932e a2ba118e74be7ddfff3b12973cd0be39 bef21083ff3b12976721285d1e23932e fpscr=00000000
+vrintr.f32.f32 s5, s14 a6d98895f7feab9826d04a31f3f1a2a5 0b26850edb53f3eadd1682d8863cd595 a6d98895f7feab98db53f3eaf3f1a2a5 0b26850edb53f3eadd1682d8863cd595 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintr.f32.f32 s5, s14 5d70dbe9b756ef0fb756ef0f454444ba d0b20d64c881e555a3007bbfa8ebf41b 5d70dbe9b756ef0fc881e560454444ba d0b20d64c881e555a3007bbfa8ebf41b fpscr=00000000
+vrintr.f32.f32 s5, s14 a401f59a468a68a1da186fc91d0cb2d9 4669cd1ee1dc649f4bd7560277d534b3 a401f59a468a68a1e1dc649f1d0cb2d9 4669cd1ee1dc649f4bd7560277d534b3 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintr.f32.f32 s5, s14 8951ce39cad568b6301747b0937e1654 4ed6b0d48fa15310f1399f4bf1399f4b 8951ce39cad568b680000000937e1654 4ed6b0d48fa15310f1399f4bf1399f4b fpscr=00000000
+vrintr.f32.f32 s5, s14 03ff27ad8fe4ddcb360180019908f3f1 668cf64b62743e159e65db2228518dc0 03ff27ad8fe4ddcb62743e159908f3f1 668cf64b62743e159e65db2228518dc0 fpscr=00000000
+vrintr.f32.f32 s5, s14 192c11ec2a8d0ac246c51438c339d85b f108bd36f71620f6aae1ede66808a1a5 192c11ec2a8d0ac2f71620f6c339d85b f108bd36f71620f6aae1ede66808a1a5 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintr.f32.f32 s5, s14 ca2ab02cd4176c6df979b6c6481bc3ef c5fa91b974ee5fffd8add460fb14cb19 ca2ab02cd4176c6d74ee5fff481bc3ef c5fa91b974ee5fffd8add460fb14cb19 fpscr=00000000
+vrintr.f32.f32 s5, s14 743ee21ac6ad8d1a38c7b9d1e21a6173 5ee8422b6c76b9fd84cd5b4d9db5a3e7 743ee21ac6ad8d1a6c76b9fde21a6173 5ee8422b6c76b9fd84cd5b4d9db5a3e7 fpscr=00000000
+randV128: 9728 calls, 10041 iters
+vrintr.f32.f32 s5, s14 5dd83f7d2d7a2558eb525e274bc9549f 12f11cedd66f222dd83f23deccf33b23 5dd83f7d2d7a2558d66f222d4bc9549f 12f11cedd66f222dd83f23deccf33b23 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintr.f32.f32 s5, s14 bfdfe09f0554c9b6a15d4442e4e014d2 da4909ef7e80cc53610962a1e8b4aebd bfdfe09f0554c9b67e80cc53e4e014d2 da4909ef7e80cc53610962a1e8b4aebd fpscr=00000000
+vrintr.f32.f32 s5, s14 ea7e363cf97f9127e59e0ef5e46a30c8 9720a029966678b40dc42a48d961df15 ea7e363cf97f912780000000e46a30c8 9720a029966678b40dc42a48d961df15 fpscr=00000000
+vrintr.f32.f32 s5, s14 792ff382657824abf3accaf390c6d79c f7f0b9393247af79c17e64dd4dd9f6a8 792ff382657824ab0000000090c6d79c f7f0b9393247af79c17e64dd4dd9f6a8 fpscr=00000000
+vrintr.f32.f32 s5, s14 26fe284f4b1b540d849afb6ee6cb8025 c20681c1181401cecd5831c776a43e5b 26fe284f4b1b540d00000000e6cb8025 c20681c1181401cecd5831c776a43e5b fpscr=00000000
+vrintr.f32.f32 s5, s14 9cb5d49e4f302a3dd527facc6f786366 52fb351c4c709854b94ed4e2bd5c91b2 9cb5d49e4f302a3d4c7098546f786366 52fb351c4c709854b94ed4e2bd5c91b2 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintr.f32.f32 s5, s14 8f7492348639b4910c5ae5bb74748bd5 a376fdf026652ce163253e98c3d60159 8f7492348639b4910000000074748bd5 a376fdf026652ce163253e98c3d60159 fpscr=00000000
+vrintr.f32.f32 s5, s14 6d958ce712e5d33b46cd422bdb1a3edb da912ad775b7b0719b156dd8a8646906 6d958ce712e5d33b75b7b071db1a3edb da912ad775b7b0719b156dd8a8646906 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintr.f32.f32 s5, s14 87bef3baefdc0645efdc0645af63b0ea 819e9bd05555848b530e55010a487713 87bef3baefdc06455555848baf63b0ea 819e9bd05555848b530e55010a487713 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintr.f32.f32 s5, s14 53583dcb45da5db029c1cc4e4911015f a7f58adfe5daffecfce10a7212d4e151 53583dcb45da5db0e5daffec4911015f a7f58adfe5daffecfce10a7212d4e151 fpscr=00000000
+vrintr.f32.f32 s5, s14 dd79c32da747b9b4cf1b10be2efc29d2 eeb668fd17348a5d7bfe7b7cd0eb6044 dd79c32da747b9b4000000002efc29d2 eeb668fd17348a5d7bfe7b7cd0eb6044 fpscr=00000000
+vrintr.f32.f32 s5, s14 2e30b7f6a8719752b30cd7789f1da562 e517da6c66b99e9f6f8afda13625f74a 2e30b7f6a871975266b99e9f9f1da562 e517da6c66b99e9f6f8afda13625f74a fpscr=00000000
+vrintr.f32.f32 s5, s14 b62103b6ca7dc417e227c687a7e2ec25 e995b58af73ae1ce96a9e60cb87bb638 b62103b6ca7dc417f73ae1cea7e2ec25 e995b58af73ae1ce96a9e60cb87bb638 fpscr=00000000
+vrintr.f32.f32 s5, s14 fc84111c92c2a783ca85c728f9ba537e 97bc0af8f7bae809fe9bda3d2dcfc371 fc84111c92c2a783f7bae809f9ba537e 97bc0af8f7bae809fe9bda3d2dcfc371 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vrintr.f32.f32 s5, s14 8b132d5419bc972c19bc972c8e261f07 d74a5a1f3b2d73513b2d73512a6ad997 8b132d5419bc972c000000008e261f07 d74a5a1f3b2d73513b2d73512a6ad997 fpscr=00000000
+vrintr.f32.f32 s5, s14 0e6174bb6d5c0f699022c4103eb7a168 b5bd26a291e4c1bec2470356f467070d 0e6174bb6d5c0f69800000003eb7a168 b5bd26a291e4c1bec2470356f467070d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[1]
+vrintr.f32.f32 s5, s14 5dbf9d5d54023831b95f588fb95f588f 1456fb1ab51842cc25d3f418aacf07ba 5dbf9d5d5402383180000000b95f588f 1456fb1ab51842cc25d3f418aacf07ba fpscr=00000000
+vrintr.f32.f32 s5, s14 f6b1c7fb7bbac2999f8461433c2c8270 bbf3429b7269b894a22695b9be39f79b f6b1c7fb7bbac2997269b8943c2c8270 bbf3429b7269b894a22695b9be39f79b fpscr=00000000
+vrintr.f32.f32 s5, s14 63b68a156aa9509422b9bec39c3ad373 3179177c020b74d210ae4515f113e61e 63b68a156aa95094000000009c3ad373 3179177c020b74d210ae4515f113e61e fpscr=00000000
+vrintxeq.f32.f32 s6, s15 7dceaaddf35dfac68fbb145524e50f57 8e333c704723d4b347eb389b8de6f7c1 7dceaaddf35dfac68fbb145524e50f57 8e333c704723d4b347eb389b8de6f7c1 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 72aefa55c52dbcb34bcd4a1dc6c9711d abe575e8e56143fb382c51a36af57056 72aefa55c52dbcb34bcd4a1dc6c9711d abe575e8e56143fb382c51a36af57056 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 89fa64a9b14a202a4ae2b48ccbe7dbf9 ff0a6e42e3b0854fd5e419c3e5f470aa 89fa64a9b14a202a4ae2b48ccbe7dbf9 ff0a6e42e3b0854fd5e419c3e5f470aa fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintxeq.f32.f32 s6, s15 dc0f2aca06b7240603ab91416ccff349 a306038ec91123a5532652db3f1d9f2b dc0f2aca06b7240603ab91416ccff349 a306038ec91123a5532652db3f1d9f2b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintxeq.f32.f32 s6, s15 eb046bb390f3420f83c7cc87f7c3c9b1 a88d29b972b79acbb60448786274dca8 eb046bb390f3420f83c7cc87f7c3c9b1 a88d29b972b79acbb60448786274dca8 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintxeq.f32.f32 s6, s15 a10d0c5c95a3e0022e36541489501421 d8513d775d7c6902b9091ca9a509a38a a10d0c5c95a3e0022e36541489501421 d8513d775d7c6902b9091ca9a509a38a fpscr=00000000
+vrintxeq.f32.f32 s6, s15 b2a41da880e8eb03cfb44de7191ac708 9c252da5b6e993c07baf4e77b482fd75 b2a41da880e8eb03cfb44de7191ac708 9c252da5b6e993c07baf4e77b482fd75 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vrintxeq.f32.f32 s6, s15 3cba7d2d1021b7403cba7d2d46634fd4 79f7e2b9861fab196cf50258861fab19 3cba7d2d1021b7403cba7d2d46634fd4 79f7e2b9861fab196cf50258861fab19 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[1]
+vrintxeq.f32.f32 s6, s15 8f5925edb5988521b59885215b83bd48 e94e481317270cc50c5264d68bfb9f1e 8f5925edb5988521b59885215b83bd48 e94e481317270cc50c5264d68bfb9f1e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[2]
+vrintxeq.f32.f32 s6, s15 1f02550600e4d0bb1f02550676f46810 d9a6c051a773d2019436a659353d2ee2 1f02550600e4d0bb1f02550676f46810 d9a6c051a773d2019436a659353d2ee2 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 43d6052773d139b2f24b57b56460aa63 183d8255ec977b56f12c86326d81074f 43d6052773d139b2f24b57b56460aa63 183d8255ec977b56f12c86326d81074f fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintxeq.f32.f32 s6, s15 2e80be9e43d17dd566e8db794e1c0ac9 9aa0fc5c8dc32d206bf11fc9f1abf94d 2e80be9e43d17dd566e8db794e1c0ac9 9aa0fc5c8dc32d206bf11fc9f1abf94d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintxeq.f32.f32 s6, s15 5ea12de1253869e1e4c7bc0406191a69 c8b63bc1b511d8ed6247cf580ad4b724 5ea12de1253869e1e4c7bc0406191a69 c8b63bc1b511d8ed6247cf580ad4b724 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintxeq.f32.f32 s6, s15 5cf7d1b291f175e1121e192991091fe5 16e255b4e2e46ee5521e8254a040069f 5cf7d1b291f175e1121e192991091fe5 16e255b4e2e46ee5521e8254a040069f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintxeq.f32.f32 s6, s15 ead2f7c9c63730d5753a97de6f91ba90 b21ef5bd73c505e88b2af1202f4e90d6 ead2f7c9c63730d5753a97de6f91ba90 b21ef5bd73c505e88b2af1202f4e90d6 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 80a56cea52d74a83354d758b1b1c3384 a08a7b92edd19478b71d86da403d18b6 80a56cea52d74a83354d758b1b1c3384 a08a7b92edd19478b71d86da403d18b6 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 9c30ac3017e02a815006d97794f3172c 66748822cc1839bba50470eda1097935 9c30ac3017e02a815006d97794f3172c 66748822cc1839bba50470eda1097935 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 7beba304d9c290007a1e96ce90ebcb75 9acaa5103b4d8bf21419371c662d6faf 7beba304d9c290007a1e96ce90ebcb75 9acaa5103b4d8bf21419371c662d6faf fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintxeq.f32.f32 s6, s15 d2aab42e98822582fb475d9993230fda 6899e9abc1eba0ec9ea008c06899e9ab d2aab42e98822582fb475d9993230fda 6899e9abc1eba0ec9ea008c06899e9ab fpscr=00000000
+vrintxeq.f32.f32 s6, s15 9e8929cd220f50c9dcddb5916030215e d794348be5758411e8914fa8075dab98 9e8929cd220f50c9dcddb5916030215e d794348be5758411e8914fa8075dab98 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintxeq.f32.f32 s6, s15 c2429600e95629c1e1f807aa871c35f5 3d9b94b5cd137ee5f9ed7ca6e5132560 c2429600e95629c1e1f807aa871c35f5 3d9b94b5cd137ee5f9ed7ca6e5132560 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 ecfdd022739c7c43f83a03aff7a64970 47f9c3fdb262e4f132605ab70da7f5e6 ecfdd022739c7c43f83a03aff7a64970 47f9c3fdb262e4f132605ab70da7f5e6 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 30bbbf9e440f2728428aea8e21734b73 84c41b22b7643ff26d3f90d352e95de2 30bbbf9e440f2728428aea8e21734b73 84c41b22b7643ff26d3f90d352e95de2 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 afb8f376e029d9870dfd78162c656c02 b241a0b14efecff3e5580f38c7cf21a1 afb8f376e029d9870dfd78162c656c02 b241a0b14efecff3e5580f38c7cf21a1 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintxeq.f32.f32 s6, s15 7277bc98124a4b10182093d6a7a523cb 5711e39809fb0b71b456033cb0361132 7277bc98124a4b10182093d6a7a523cb 5711e39809fb0b71b456033cb0361132 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 5dfa5d263ddc8972837e73f2496e3780 adb9564a1a709c248291bbca0430962e 5dfa5d263ddc8972837e73f2496e3780 adb9564a1a709c248291bbca0430962e fpscr=00000000
+vrintxeq.f32.f32 s6, s15 4dd4e66eb7a22e2ebb5673f156653191 9320f4aa6e47f8134a82d9a29e6ea60f 4dd4e66eb7a22e2ebb5673f156653191 9320f4aa6e47f8134a82d9a29e6ea60f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+vrintxeq.f32.f32 s6, s15 284edc65284edc65a98708080bf091d6 4f31046dae3029c2506f484710ffc4be 284edc65284edc65a98708080bf091d6 4f31046dae3029c2506f484710ffc4be fpscr=00000000
+vrintxeq.f32.f32 s6, s15 1f97af341d723650fd0fc4a3ee7b65da 410d3d98bafb1082e9ace9f4252c5163 1f97af341d723650fd0fc4a3ee7b65da 410d3d98bafb1082e9ace9f4252c5163 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 46251313c2906c67f107d4b3fb1198b6 a09650331f5e8124160e73ec937112c9 46251313c2906c67f107d4b3fb1198b6 a09650331f5e8124160e73ec937112c9 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 1e588b5c8a1da2ddb119da0313f6d5b7 051788d951a781c5e3b3ed59b3a64731 1e588b5c8a1da2ddb119da0313f6d5b7 051788d951a781c5e3b3ed59b3a64731 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintxeq.f32.f32 s6, s15 a5ed303692181975d79bf095cd91d966 7142f649117147d54ffa4f8deeecdf17 a5ed303692181975d79bf095cd91d966 7142f649117147d54ffa4f8deeecdf17 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintxeq.f32.f32 s6, s15 caefaeb43e2de9c3caefaeb455630eff f8e845e4ea12d8e1d6fbe8752f2a7977 caefaeb43e2de9c3caefaeb455630eff f8e845e4ea12d8e1d6fbe8752f2a7977 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 237e9eb0e54443568adbaecb532cdfc2 849dab0c7922b4437aae0a3e73128494 237e9eb0e54443568adbaecb532cdfc2 849dab0c7922b4437aae0a3e73128494 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 662986243cb629d33e2af074afa44729 0e630b1f93f1d0ec3d76f9f1c9877cbb 662986243cb629d33e2af074afa44729 0e630b1f93f1d0ec3d76f9f1c9877cbb fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintxeq.f32.f32 s6, s15 7c8d3ad5d9372ab95582fac2582e5458 43c81db2e100029c2cfd2009a7c373ce 7c8d3ad5d9372ab95582fac2582e5458 43c81db2e100029c2cfd2009a7c373ce fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintxeq.f32.f32 s6, s15 4215eb83b9206c9d9a5b490f62e14e42 1b2d4a559d3b64caeca5e4d3db23b0a1 4215eb83b9206c9d9a5b490f62e14e42 1b2d4a559d3b64caeca5e4d3db23b0a1 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 bbf6957ebdc179e7cd8894ea390dba9a 8c17fec3b2513b1efca88f1cbc60b351 bbf6957ebdc179e7cd8894ea390dba9a 8c17fec3b2513b1efca88f1cbc60b351 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 6bd195fb9ab2d2f630d38c7d48e23df2 dbd2fa2fb356f19d4c8d3fe34bcded44 6bd195fb9ab2d2f630d38c7d48e23df2 dbd2fa2fb356f19d4c8d3fe34bcded44 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 a4199390c9a753cf4e6fba79dc905c38 b1ac5c99d5d8bca502a3fd9b48b9865e a4199390c9a753cf4e6fba79dc905c38 b1ac5c99d5d8bca502a3fd9b48b9865e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[0]
+vrintxeq.f32.f32 s6, s15 b6706d3d0d73e9cb0d73e9cbb88d2d66 46f7dfd0128fa030f67cb07c7cca2e6d b6706d3d0d73e9cb0d73e9cbb88d2d66 46f7dfd0128fa030f67cb07c7cca2e6d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintxeq.f32.f32 s6, s15 0091c86174cb27164497b35a6d4dd0f6 b821770180b4b527bda2bbd480b4b527 0091c86174cb27164497b35a6d4dd0f6 b821770180b4b527bda2bbd480b4b527 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 7c179b2cf96e6f2c5f890034281bfa99 866c38b77d0f55c74be10c7f502f9f7b 7c179b2cf96e6f2c5f890034281bfa99 866c38b77d0f55c74be10c7f502f9f7b fpscr=00000000
+vrintxeq.f32.f32 s6, s15 f87e1ec5b78f76c9f8ba5b5d1cf4f285 bbc9fc55e4c21a6d1e20cc012e3f5c0a f87e1ec5b78f76c9f8ba5b5d1cf4f285 bbc9fc55e4c21a6d1e20cc012e3f5c0a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintxeq.f32.f32 s6, s15 7b87f5de793bea87e5c7a36a83872506 9d23dfb2ae6013fb2d63750fbb95fd31 7b87f5de793bea87e5c7a36a83872506 9d23dfb2ae6013fb2d63750fbb95fd31 fpscr=00000000
+randV128: 9984 calls, 10305 iters
+vrintxeq.f32.f32 s6, s15 fc35cec7b7a0f66fa02613b63f9b659e ac56febd78457c44080b3ae7204141af fc35cec7b7a0f66fa02613b63f9b659e ac56febd78457c44080b3ae7204141af fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintxeq.f32.f32 s6, s15 8a000512946c2c0bf1ef10f2f1ef10f2 b4f83a29fcf36f01d738a06a5e5c825c 8a000512946c2c0bf1ef10f2f1ef10f2 b4f83a29fcf36f01d738a06a5e5c825c fpscr=00000000
+vrintxeq.f32.f32 s6, s15 a08fca36439b459d334ac51438400ea9 60106840856409c426c40653d3bed675 a08fca36439b459d334ac51438400ea9 60106840856409c426c40653d3bed675 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 46813bbf7283effbe332ddcc9eff4f0e 4eb47e7ca9b420ea21e008471d6e81c7 46813bbf7283effbe332ddcc9eff4f0e 4eb47e7ca9b420ea21e008471d6e81c7 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintxeq.f32.f32 s6, s15 52bebdb933811efa313d2ab459e1e571 961bf0bd20d9cf6d7c5d17016acc1912 52bebdb933811efa313d2ab459e1e571 961bf0bd20d9cf6d7c5d17016acc1912 fpscr=00000000
+vrintxne.f32.f32 s7, s16 e73f871a86f6cf9e9664e2b67e673e9f 246edc11d0c60f8d64c51a584cb2b96c 4cb2b96c86f6cf9e9664e2b67e673e9f 246edc11d0c60f8d64c51a584cb2b96c fpscr=00000000
+vrintxne.f32.f32 s7, s16 ac3f4143fb7f71ec02974501b25eb500 2298339404650a86b1ac2f11d2681c93 d2681c93fb7f71ec02974501b25eb500 2298339404650a86b1ac2f11d2681c93 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[0]
+vrintxne.f32.f32 s7, s16 0505e94ce68615c79e0bea6fe68615c7 413ce5f9d6c64ff3f1063a423d223bd1 00000000e68615c79e0bea6fe68615c7 413ce5f9d6c64ff3f1063a423d223bd1 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintxne.f32.f32 s7, s16 5149001ff61f59a3c946433eacd64199 c0396961c0396961c432fcfe284070b5 00000000f61f59a3c946433eacd64199 c0396961c0396961c432fcfe284070b5 fpscr=00000000
+vrintxne.f32.f32 s7, s16 1fbc82eef0bd3ec4d5aa54e30ad0ce99 5c2936e8e377c51625ed6109cb064ffa cb064ffaf0bd3ec4d5aa54e30ad0ce99 5c2936e8e377c51625ed6109cb064ffa fpscr=00000000
+vrintxne.f32.f32 s7, s16 e3ea5827ab19bbd8a72765b419930e87 eae30ccd523b3d920749ee0fe298b9ed e298b9edab19bbd8a72765b419930e87 eae30ccd523b3d920749ee0fe298b9ed fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintxne.f32.f32 s7, s16 0927c557d9f52c3e81a1cc8ebcd5a67a 03f80334129f73738894ffe3cb531f54 cb531f54d9f52c3e81a1cc8ebcd5a67a 03f80334129f73738894ffe3cb531f54 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintxne.f32.f32 s7, s16 3e842d83bc8225361c8f8603d1844886 b42cfb6524756cbba358bc0753fab112 53fab112bc8225361c8f8603d1844886 b42cfb6524756cbba358bc0753fab112 fpscr=00000000
+vrintxne.f32.f32 s7, s16 37fb637fa08f3445c3f4d9d8a5c223ae 0c4ecd81eba6a47f30c913c6575ab902 575ab902a08f3445c3f4d9d8a5c223ae 0c4ecd81eba6a47f30c913c6575ab902 fpscr=00000000
+vrintxne.f32.f32 s7, s16 3727925a8f4c0bd4a03025ed74520a57 2d688cc7b2ee23a14491e62506e0e703 000000008f4c0bd4a03025ed74520a57 2d688cc7b2ee23a14491e62506e0e703 fpscr=00000000
+vrintxne.f32.f32 s7, s16 0a808d33b2cc69106e26548e728b6f5e 6723355c0ff8cac7f3aefa393b665b7d 00000000b2cc69106e26548e728b6f5e 6723355c0ff8cac7f3aefa393b665b7d fpscr=00000000
+vrintxne.f32.f32 s7, s16 84e3e810a8bdc3e42a87e68934699d8e cf87ac4be77dd7854b9e96c4b0ed32a9 80000000a8bdc3e42a87e68934699d8e cf87ac4be77dd7854b9e96c4b0ed32a9 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintxne.f32.f32 s7, s16 0bab52824c5ec50619800596ff3969a6 d741cc0e5c080f7b5c080f7bc1bad120 c1b800004c5ec50619800596ff3969a6 d741cc0e5c080f7b5c080f7bc1bad120 fpscr=00000000
+vrintxne.f32.f32 s7, s16 e251ab5b3b1d694593931dac741bbea8 976230408ebcce2d091c5faabcd6afd2 800000003b1d694593931dac741bbea8 976230408ebcce2d091c5faabcd6afd2 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[3]
+vrintxne.f32.f32 s7, s16 bbb78e2ad7dbd113738e66e0cdc157ac 266780a71a88bb223ffbb7ce3ffbb7ce 40000000d7dbd113738e66e0cdc157ac 266780a71a88bb223ffbb7ce3ffbb7ce fpscr=00000000
+vrintxne.f32.f32 s7, s16 c1170c4e0a46d3788b57d500d13f8ddb fae3d53e04370826b7a979b0b28a58b2 800000000a46d3788b57d500d13f8ddb fae3d53e04370826b7a979b0b28a58b2 fpscr=00000000
+vrintxne.f32.f32 s7, s16 c8e74f71e52abf16a9eb1946a56e08d2 907237b0dc6c1fae95a1d58cab8ca13c 80000000e52abf16a9eb1946a56e08d2 907237b0dc6c1fae95a1d58cab8ca13c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintxne.f32.f32 s7, s16 72daaca0a2485a75a0b0c976398501df ae79fc5fa23b8f857de3960db6d4d0ab 80000000a2485a75a0b0c976398501df ae79fc5fa23b8f857de3960db6d4d0ab fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintxne.f32.f32 s7, s16 bb492fd9e43bbb025fb6795be43bbb02 2d899a33dcee40f5647dfbd1d4c260d8 d4c260d8e43bbb025fb6795be43bbb02 2d899a33dcee40f5647dfbd1d4c260d8 fpscr=00000000
+vrintxne.f32.f32 s7, s16 60aba9de3f7b1c86192d13d09697c6fa aa5c45d76ec9836a98b79222391cc344 000000003f7b1c86192d13d09697c6fa aa5c45d76ec9836a98b79222391cc344 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintxne.f32.f32 s7, s16 9a640f949a640f94e5999fc08641df94 b40acaf6c1843e1c136992c74307d827 430800009a640f94e5999fc08641df94 b40acaf6c1843e1c136992c74307d827 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintxne.f32.f32 s7, s16 6a7c9e931dd58f44f809cf6969d48ff5 717ffeb8d58667fbd979d26f26c777e2 000000001dd58f44f809cf6969d48ff5 717ffeb8d58667fbd979d26f26c777e2 fpscr=00000000
+vrintxne.f32.f32 s7, s16 b55f52fe7ac8f3637c00aa5b22bdf940 087af15f95c5935d54563144504fac19 504fac197ac8f3637c00aa5b22bdf940 087af15f95c5935d54563144504fac19 fpscr=00000000
+vrintxne.f32.f32 s7, s16 227ebeeb07b5f43d6c47ddb171069ce9 15c73add7f2ba51206f28e6f43b71e54 43b7000007b5f43d6c47ddb171069ce9 15c73add7f2ba51206f28e6f43b71e54 fpscr=00000000
+vrintxne.f32.f32 s7, s16 2173ad24981bb6fef8d9249b74d3118d 3b3671457d1653c5881c93f5feddb6ef feddb6ef981bb6fef8d9249b74d3118d 3b3671457d1653c5881c93f5feddb6ef fpscr=00000000
+vrintxne.f32.f32 s7, s16 9dc75512d9d457beb61339efd30072d8 31b8ee41641928814e66b1dd2dc72ab3 00000000d9d457beb61339efd30072d8 31b8ee41641928814e66b1dd2dc72ab3 fpscr=00000000
+vrintxne.f32.f32 s7, s16 8c48acd692a2ff474021afa95df836e2 1357477741c0bfec8502830468153588 6815358892a2ff474021afa95df836e2 1357477741c0bfec8502830468153588 fpscr=00000000
+vrintxne.f32.f32 s7, s16 85bf23c6ccce41761a2750dbb53a17c4 5a9979278f2c5a52b73571557c52622f 7c52622fccce41761a2750dbb53a17c4 5a9979278f2c5a52b73571557c52622f fpscr=00000000
+vrintxne.f32.f32 s7, s16 68a461f6162f107be69cd1629836a5af 862267e2035885f7bd346dc07176e5db 7176e5db162f107be69cd1629836a5af 862267e2035885f7bd346dc07176e5db fpscr=00000000
+vrintxne.f32.f32 s7, s16 e4fcde6fa52bfb2b2765af4b3b92bd7b 0b44b9aacdc0808e2d72add0de730901 de730901a52bfb2b2765af4b3b92bd7b 0b44b9aacdc0808e2d72add0de730901 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintxne.f32.f32 s7, s16 efc9973b4e64f4a9e03b9827d7407754 636f0a99cd1ebe5740eb0ade636f0a99 636f0a994e64f4a9e03b9827d7407754 636f0a99cd1ebe5740eb0ade636f0a99 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintxne.f32.f32 s7, s16 a2d5b7e8cb383633856fcccc4a0553f5 f74826ca74dd18d316d073ce5ed5215d 5ed5215dcb383633856fcccc4a0553f5 f74826ca74dd18d316d073ce5ed5215d fpscr=00000000
+vrintxne.f32.f32 s7, s16 32fb06cff641ba0d1ece993827a8aa4e 7c207b34c21ea288ca6b56c4e75b84f6 e75b84f6f641ba0d1ece993827a8aa4e 7c207b34c21ea288ca6b56c4e75b84f6 fpscr=00000000
+vrintxne.f32.f32 s7, s16 e5b5ece92bf4c9aa96ae065cde651d98 4b8d6d55d03992df17cbfcb41e5dbf99 000000002bf4c9aa96ae065cde651d98 4b8d6d55d03992df17cbfcb41e5dbf99 fpscr=00000000
+vrintxne.f32.f32 s7, s16 7f113b505308937899aafd131cd26622 107f13e2f25eff9ac0bf3e3313d664ac 000000005308937899aafd131cd26622 107f13e2f25eff9ac0bf3e3313d664ac fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[3]
+vrintxne.f32.f32 s7, s16 213b4f54b2ac8cab83ddc86cb2ac8cab cf7899f3535ec8e568421b4b5a87ffe9 5a87ffe9b2ac8cab83ddc86cb2ac8cab cf7899f3535ec8e568421b4b5a87ffe9 fpscr=00000000
+vrintxne.f32.f32 s7, s16 c96884ab4bd5d95bea30006e5152799d 39b68cac9064fc61f5065eda43bd01d8 43bd00004bd5d95bea30006e5152799d 39b68cac9064fc61f5065eda43bd01d8 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintxne.f32.f32 s7, s16 2c6475cbf4629b5c1f99e1a2f4629b5c 39a5f53915022771ed50d3652c8a5a62 00000000f4629b5c1f99e1a2f4629b5c 39a5f53915022771ed50d3652c8a5a62 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintxne.f32.f32 s7, s16 bf9a39605088e553101fab6422d8f57c 29a9a9606b6bcb3f651577a86918d360 6918d3605088e553101fab6422d8f57c 29a9a9606b6bcb3f651577a86918d360 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintxne.f32.f32 s7, s16 eeec7fcdeeec7fcde41ec4609021359d b822ada82e148eb4a6b87abd1dd3711a 00000000eeec7fcde41ec4609021359d b822ada82e148eb4a6b87abd1dd3711a fpscr=00000000
+vrintxne.f32.f32 s7, s16 d4ab938707503f65483ab17fa090da46 35e2dbc73ab0fc4127bc43966685e55a 6685e55a07503f65483ab17fa090da46 35e2dbc73ab0fc4127bc43966685e55a fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintxne.f32.f32 s7, s16 adcb5e1789ab16c389ab16c3724f43ec fe3f9152447945a616987815b25dc88c 8000000089ab16c389ab16c3724f43ec fe3f9152447945a616987815b25dc88c fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintxne.f32.f32 s7, s16 de7066504c1b108baa5dfb3d63d94b75 3120bf064429f8ae728ae9ae1d2ad431 000000004c1b108baa5dfb3d63d94b75 3120bf064429f8ae728ae9ae1d2ad431 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintxne.f32.f32 s7, s16 db515eade4d0a3802867dfcf8e851dff 303d0e13167cb409a79de211279e327b 00000000e4d0a3802867dfcf8e851dff 303d0e13167cb409a79de211279e327b fpscr=00000000
+vrintxne.f32.f32 s7, s16 f638d88000e52b6b0e1114640ef98b57 4b5a5c9abc774ca0ceabf86c730f16cd 730f16cd00e52b6b0e1114640ef98b57 4b5a5c9abc774ca0ceabf86c730f16cd fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintxne.f32.f32 s7, s16 70b64df6efa75b63b6e97c0925bd2c58 4725157541d7f7f0d06c5d0bb8f6a660 80000000efa75b63b6e97c0925bd2c58 4725157541d7f7f0d06c5d0bb8f6a660 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintxne.f32.f32 s7, s16 af4dfe79cd8e80f4691d698e7d2f9ea1 adcbb98edd92cb2c91cbefcce31de50c e31de50ccd8e80f4691d698e7d2f9ea1 adcbb98edd92cb2c91cbefcce31de50c fpscr=00000000
+vrintxne.f32.f32 s7, s16 1b80ff5c37fd6aeea3d0940b203101c3 846ccc42281304bf7bd59c727d3a6555 7d3a655537fd6aeea3d0940b203101c3 846ccc42281304bf7bd59c727d3a6555 fpscr=00000000
+vrintxne.f32.f32 s7, s16 2feef3f0a22d7794cc4c1dfac50c95fd a0f48a78dd9da4c3dfaf7d63419118c5 41900000a22d7794cc4c1dfac50c95fd a0f48a78dd9da4c3dfaf7d63419118c5 fpscr=00000000
+vrintxne.f32.f32 s7, s16 a2b069e8ea8e8503424a65edadc6a8d2 e89cb42df72c47d9a5dec4f1d00d7997 d00d7997ea8e8503424a65edadc6a8d2 e89cb42df72c47d9a5dec4f1d00d7997 fpscr=00000000
+vrintx.f32.f32 s8, s8 0e563b57e8c440614da5ea4edb38a9c8 64448f57e46aee13b384d2c73d108dad 64448f57e46aee13b384d2c700000000 64448f57e46aee13b384d2c700000000 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vrintx.f32.f32 s8, s8 135ed7dd92772e6743b52888135ed7dd dd4334daa539341376929c45dd4334da dd4334daa539341376929c45dd4334da dd4334daa539341376929c45dd4334da fpscr=00000000
+vrintx.f32.f32 s8, s8 0de09cdb0fd3c65bc7974fba793952fa 330c5eaf9acbe865d2485fa876be59b5 330c5eaf9acbe865d2485fa876be59b5 330c5eaf9acbe865d2485fa876be59b5 fpscr=00000000
+vrintx.f32.f32 s8, s8 23959fbea2580007020997a00c99f550 5f0670cb008f399896b9f1d413ccba7c 5f0670cb008f399896b9f1d400000000 5f0670cb008f399896b9f1d400000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 b91696cf248c31e8e3a44d18958d7436 dcbdb6ce3f184c7a40b7c1a390bfa007 dcbdb6ce3f184c7a40b7c1a380000000 dcbdb6ce3f184c7a40b7c1a380000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 bb55deaaefd1d6a59f9e4b4db224646f 1335e980dd60f13bc81d9b69536356b0 1335e980dd60f13bc81d9b69536356b0 1335e980dd60f13bc81d9b69536356b0 fpscr=00000000
+vrintx.f32.f32 s8, s8 75579efb8e7139c14e4d1c6d7529cd4e 2649292b0589b50f1c24c4e55bf5bd78 2649292b0589b50f1c24c4e55bf5bd78 2649292b0589b50f1c24c4e55bf5bd78 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintx.f32.f32 s8, s8 7f108773cb244e2d1853f8dfb5ea4886 cf1a62dd046cf08f2e0ba0b9fbe98fad cf1a62dd046cf08f2e0ba0b9fbe98fad cf1a62dd046cf08f2e0ba0b9fbe98fad fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintx.f32.f32 s8, s8 60da8eb3741d9df660da8eb3a1dd395c 21781d1b8d5b1383160824f76dabbccd 21781d1b8d5b1383160824f76dabbccd 21781d1b8d5b1383160824f76dabbccd fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: 10240 calls, 10568 iters
+vrintx.f32.f32 s8, s8 e8ecc49e1e51e218f590180c2dcf2561 0f7fc9d5417f73e7a1cdc5429ee03089 0f7fc9d5417f73e7a1cdc54280000000 0f7fc9d5417f73e7a1cdc54280000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 f6c883e7726101e156a76dd72015fc84 d69813577c5d20caf690cdcd5f270dd7 d69813577c5d20caf690cdcd5f270dd7 d69813577c5d20caf690cdcd5f270dd7 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintx.f32.f32 s8, s8 bc315b5980f3d0a794add7fa61646bfb b6080a4fc33b0d3b367f76ca1ffd2742 b6080a4fc33b0d3b367f76ca00000000 b6080a4fc33b0d3b367f76ca00000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 716e60a4fcafbe7b846c37fbc17fa9d2 de38d1f48580e70adcb0495c38cb8121 de38d1f48580e70adcb0495c00000000 de38d1f48580e70adcb0495c00000000 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintx.f32.f32 s8, s8 2aceeb52136a6ae66cc4216b5f1e4cae 3b209bed3b209bedbd108ef21024989b 3b209bed3b209bedbd108ef200000000 3b209bed3b209bedbd108ef200000000 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[2]
+vrintx.f32.f32 s8, s8 18b34357ea3d3655777445c9c9442fc6 db315bfbdb315bfbbf5576028486e92a db315bfbdb315bfbbf55760280000000 db315bfbdb315bfbbf55760280000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 d769b3362269ae4d5d24efe42a8cd075 9c30bd68e45028f6f878069a1b48fb9b 9c30bd68e45028f6f878069a00000000 9c30bd68e45028f6f878069a00000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 70485f6c57d8a89520779159f046485f 15105a9d4913a806f17f5a8aa4b8b9d2 15105a9d4913a806f17f5a8a80000000 15105a9d4913a806f17f5a8a80000000 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintx.f32.f32 s8, s8 ebffcb7ee8d6973d9ad2e6630f83e61e eb9535e875b7ab422dc8228f1afada22 eb9535e875b7ab422dc8228f00000000 eb9535e875b7ab422dc8228f00000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 237a2017dedfd4f562b780e647acc7ff 3fdf4d983ce467da61fe28167637e67e 3fdf4d983ce467da61fe28167637e67e 3fdf4d983ce467da61fe28167637e67e fpscr=00000000
+vrintx.f32.f32 s8, s8 dd5595f621f252f11e93d279f86c9756 2813c432bcef3e2bf9cc744c946a0f8c 2813c432bcef3e2bf9cc744c80000000 2813c432bcef3e2bf9cc744c80000000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintx.f32.f32 s8, s8 8d0a79f5925a6e11ea62ef484381456c 85b76e3a6e3411ca2a71f44c2a71f44c 85b76e3a6e3411ca2a71f44c00000000 85b76e3a6e3411ca2a71f44c00000000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintx.f32.f32 s8, s8 9c40d510bdb032c53d6bb9d53d6bb9d5 e4e42550dbf46596cfa85d61224d6cf3 e4e42550dbf46596cfa85d6100000000 e4e42550dbf46596cfa85d6100000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 b1f77c0baf9607066cb17a6a6fc97416 6e4732aac3077531b53bd5a3524bb01e 6e4732aac3077531b53bd5a3524bb01e 6e4732aac3077531b53bd5a3524bb01e fpscr=00000000
+vrintx.f32.f32 s8, s8 a34ca09943ed3423c98d6b4f46a25b3a 6096b5cf743c966d6a0a6a228a1c4d6c 6096b5cf743c966d6a0a6a2280000000 6096b5cf743c966d6a0a6a2280000000 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintx.f32.f32 s8, s8 f7ac505e0f13483364307cec4bd229fb 4c6a4bc113cf096fd118fe5713cf096f 4c6a4bc113cf096fd118fe5700000000 4c6a4bc113cf096fd118fe5700000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 c99331c7baa42cd4b0a8f0e3758c739e 6ba67fb556ff906d17de8b549fac6439 6ba67fb556ff906d17de8b5480000000 6ba67fb556ff906d17de8b5480000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 e70f015b22d516ee20a91ca3eb9fa59d d8c4b16a7f387680b140e783436fa785 d8c4b16a7f387680b140e78343700000 d8c4b16a7f387680b140e78343700000 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintx.f32.f32 s8, s8 bff18e8515639bd1efa9ae846b2b310b 88a3f3228f9667ed47acacd78f9667ed 88a3f3228f9667ed47acacd780000000 88a3f3228f9667ed47acacd780000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 d4048bb3baab93b840ec2a6a4634a991 9be209475700e25ad085c7391a0bc080 9be209475700e25ad085c73900000000 9be209475700e25ad085c73900000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 7f1133b40b8508381d21c111762bc625 db03f55b9d75f6e8bfb2fd26fa9ba28b db03f55b9d75f6e8bfb2fd26fa9ba28b db03f55b9d75f6e8bfb2fd26fa9ba28b fpscr=00000000
+vrintx.f32.f32 s8, s8 97477cf355225f2680b489055ac9c58f 761c96c104607aaa83e70fccf3189dc6 761c96c104607aaa83e70fccf3189dc6 761c96c104607aaa83e70fccf3189dc6 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[3]
+vrintx.f32.f32 s8, s8 4c7c211733052bcc7d862a4bdacf6c10 2b2ec3f793fc4103cf88a9502b2ec3f7 2b2ec3f793fc4103cf88a95000000000 2b2ec3f793fc4103cf88a95000000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 1a9b5be32f9040ee43bb2ff918a4513b 51bf466ff8d165c9b5a246c83fe86854 51bf466ff8d165c9b5a246c840000000 51bf466ff8d165c9b5a246c840000000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[3]
+vrintx.f32.f32 s8, s8 0d5406e8e7c9b9870d5406e8950fa175 5f86c0d9c5680f1d9b1a2ec12ed364ce 5f86c0d9c5680f1d9b1a2ec100000000 5f86c0d9c5680f1d9b1a2ec100000000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintx.f32.f32 s8, s8 60fb52ce6b64f09946b7f0a44ab881f6 074ddae4d8a307d2cdea05bcb649c9a9 074ddae4d8a307d2cdea05bc80000000 074ddae4d8a307d2cdea05bc80000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 20a62231fa618f2b26565b283f3873f1 ddf43ee27b11b91342086d2ab55e49a6 ddf43ee27b11b91342086d2a80000000 ddf43ee27b11b91342086d2a80000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 0893ef34753d8932ee1e2d1f2f597c38 5b8493494f60678f7199a5010659561a 5b8493494f60678f7199a50100000000 5b8493494f60678f7199a50100000000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintx.f32.f32 s8, s8 b7f455a0b10ba3e29bdd5e2c651d1c36 6dd9e9d694f7eeec889570e3791b2cf6 6dd9e9d694f7eeec889570e3791b2cf6 6dd9e9d694f7eeec889570e3791b2cf6 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[1]
+vrintx.f32.f32 s8, s8 74babcf279add41f02a7ba9e3912a41f 72b65f56e9673a02addae8470ac22f92 72b65f56e9673a02addae84700000000 72b65f56e9673a02addae84700000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 cc00a032fb1ec3b71cd0dba4fc3c9189 27fd8b281a2932e129bd7a5ad81277d9 27fd8b281a2932e129bd7a5ad81277d9 27fd8b281a2932e129bd7a5ad81277d9 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintx.f32.f32 s8, s8 4c4e5e9ff7c70b29d12edce56a9fab8e 11e4e72e9e324e3743cab14a43cab14a 11e4e72e9e324e3743cab14a43ca8000 11e4e72e9e324e3743cab14a43ca8000 fpscr=00000000
+vrintx.f32.f32 s8, s8 2264bc6aa5b4e3cfd64d6161fa2da99c f5a584d89a41d07661cedf5f7cc351a5 f5a584d89a41d07661cedf5f7cc351a5 f5a584d89a41d07661cedf5f7cc351a5 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintx.f32.f32 s8, s8 aca39a70497026110cd6b95920cdeb2f a7b58b5aa3ab56240f8bff7efcb84b64 a7b58b5aa3ab56240f8bff7efcb84b64 a7b58b5aa3ab56240f8bff7efcb84b64 fpscr=00000000
+vrintx.f32.f32 s8, s8 44bcceffdc19ce42219ad199896f9e9a e8df53fea9b7cb76dae035e5f28a9e57 e8df53fea9b7cb76dae035e5f28a9e57 e8df53fea9b7cb76dae035e5f28a9e57 fpscr=00000000
+vrintx.f32.f32 s8, s8 cc478bbd1701ea2f6f17ee22764a1494 418e24d15372fd2b0c7b11846ccde729 418e24d15372fd2b0c7b11846ccde729 418e24d15372fd2b0c7b11846ccde729 fpscr=00000000
+vrintx.f32.f32 s8, s8 eb1d63b400fe25127f3cbfef1956f94d ed5ccaa816c1cdd04d523509d78daff5 ed5ccaa816c1cdd04d523509d78daff5 ed5ccaa816c1cdd04d523509d78daff5 fpscr=00000000
+vrintx.f32.f32 s8, s8 cd08a8d8183571cf062106fd5acf2ca0 814a029c1bc03aa660fefb8e355d5d78 814a029c1bc03aa660fefb8e00000000 814a029c1bc03aa660fefb8e00000000 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintx.f32.f32 s8, s8 74d457271b797f71369235e7be120edf ba66a2e9ee7e89a604cd86527e260eea ba66a2e9ee7e89a604cd86527e260eea ba66a2e9ee7e89a604cd86527e260eea fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintx.f32.f32 s8, s8 8ad01767c65077fb58cd239158cd2391 d2adec2706a92f1da2f773c9bcd8a12b d2adec2706a92f1da2f773c980000000 d2adec2706a92f1da2f773c980000000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintx.f32.f32 s8, s8 38aa0b855d3030b7b26500434631e999 5518fa1e65b6d52259f1c63af00cecd2 5518fa1e65b6d52259f1c63af00cecd2 5518fa1e65b6d52259f1c63af00cecd2 fpscr=00000000
+vrintn.f64.f64 d3, d15 0e04846ce3f87e0526dea14e2292d769 eae42dc4f1d1b27ab8322bbf516379fc eae42dc4f1d1b27a26dea14e2292d769 eae42dc4f1d1b27ab8322bbf516379fc fpscr=00000000
+vrintn.f64.f64 d3, d15 c8c4a8ab793e4154de278a125c700dc8 6537073aaa3f48a5b1a168da40da83a8 6537073aaa3f48a5de278a125c700dc8 6537073aaa3f48a5b1a168da40da83a8 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 f4ce5182329cd6ba5bff2103a1363c30 83591b83dbde090c5f8a4261d131d618 80000000000000005bff2103a1363c30 83591b83dbde090c5f8a4261d131d618 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 d9b0635d142b626a99f98160660693a6 c4e79d61d07769a3c4e79d61d07769a3 c4e79d61d07769a399f98160660693a6 c4e79d61d07769a3c4e79d61d07769a3 fpscr=00000000
+vrintn.f64.f64 d3, d15 eb5c5e76820ba1bb5d296b50eeaf155c b77c971b12dcecbf247f7dc593cd3746 80000000000000005d296b50eeaf155c b77c971b12dcecbf247f7dc593cd3746 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 4fd4ccac462a419435837e2a9cfec324 fcbada6cbea7cd8b01c8863efcd8868b fcbada6cbea7cd8b35837e2a9cfec324 fcbada6cbea7cd8b01c8863efcd8868b fpscr=00000000
+vrintn.f64.f64 d3, d15 328fa31d3820e5e88b7136ba8e7be067 20a9cb6d982be2680bd4ae9fdcdf1264 00000000000000008b7136ba8e7be067 20a9cb6d982be2680bd4ae9fdcdf1264 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintn.f64.f64 d3, d15 f5a590267b3fbfa1ab586fd363a69c6c 4f4554dc9983c9614f4554dc9983c961 4f4554dc9983c961ab586fd363a69c6c 4f4554dc9983c9614f4554dc9983c961 fpscr=00000000
+vrintn.f64.f64 d3, d15 2b5aa71bb8c77a06ae1b2ceaf96c0d73 d70778b11b70abbb66d239076d891bbf d70778b11b70abbbae1b2ceaf96c0d73 d70778b11b70abbb66d239076d891bbf fpscr=00000000
+vrintn.f64.f64 d3, d15 9c22663439abf9baf3b01ce2ead418d2 51331a8a5020ec3085fb3d1c8f59b939 51331a8a5020ec30f3b01ce2ead418d2 51331a8a5020ec3085fb3d1c8f59b939 fpscr=00000000
+vrintn.f64.f64 d3, d15 bc3454a89b3e3832268b96e9df020c17 5073e659e229c1a9079046b3162e1002 5073e659e229c1a9268b96e9df020c17 5073e659e229c1a9079046b3162e1002 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintn.f64.f64 d3, d15 ea834f94d90836cf68cd13b7d1595f07 0dc642b03f2a49a087e3b50a5c36e71a 000000000000000068cd13b7d1595f07 0dc642b03f2a49a087e3b50a5c36e71a fpscr=00000000
+vrintn.f64.f64 d3, d15 8dadf42e452f0ff6e1319297c0d1e231 4139a9938f6906605c3777f4bd489f43 4139a99400000000e1319297c0d1e231 4139a9938f6906605c3777f4bd489f43 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintn.f64.f64 d3, d15 2f8a2801115da87b14767cca9960c540 2d15a13638011e502d15a13638011e50 000000000000000014767cca9960c540 2d15a13638011e502d15a13638011e50 fpscr=00000000
+vrintn.f64.f64 d3, d15 3bf6379a3e44415d36a8711a78c9332f 3d0879a41e5ea77212d72b5473e3695c 000000000000000036a8711a78c9332f 3d0879a41e5ea77212d72b5473e3695c fpscr=00000000
+vrintn.f64.f64 d3, d15 bfe9961cddad347e7e9883493d5a00ff 4d83e1111f85d7bc2749650c8151e1ae 4d83e1111f85d7bc7e9883493d5a00ff 4d83e1111f85d7bc2749650c8151e1ae fpscr=00000000
+vrintn.f64.f64 d3, d15 6222263674ffe01d7c6412babcb659c7 ebb10b10b8f24b69d6b5cdac606a04b1 ebb10b10b8f24b697c6412babcb659c7 ebb10b10b8f24b69d6b5cdac606a04b1 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 a0e5427fec4f9a7ee40a19fdf67ab0ae 6153c228c479b9566153c228c479b956 6153c228c479b956e40a19fdf67ab0ae 6153c228c479b9566153c228c479b956 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintn.f64.f64 d3, d15 dfc9f6fc42a586a72e49b2fd99e3cd66 620c62655d9da852620c62655d9da852 620c62655d9da8522e49b2fd99e3cd66 620c62655d9da852620c62655d9da852 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 8808961da7da7b1b10297be66b595bc4 44aebafd2fe6adc944aebafd2fe6adc9 44aebafd2fe6adc910297be66b595bc4 44aebafd2fe6adc944aebafd2fe6adc9 fpscr=00000000
+vrintn.f64.f64 d3, d15 ebea4407091c281fdcabb0a61930faf9 9dfc2379f702cc97bc2af5ae43a64180 8000000000000000dcabb0a61930faf9 9dfc2379f702cc97bc2af5ae43a64180 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 8bb8b986453a4c06a9e894465221864b cfc4338966880c1acfc4338966880c1a cfc4338966880c1aa9e894465221864b cfc4338966880c1acfc4338966880c1a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintn.f64.f64 d3, d15 df17ee436de9aa093ab5ec7ede0a8723 77ded03987b40cc077ded03987b40cc0 77ded03987b40cc03ab5ec7ede0a8723 77ded03987b40cc077ded03987b40cc0 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: 10496 calls, 10828 iters
+vrintn.f64.f64 d3, d15 d5637ddb7f364db378303efb8617e594 9e4cc5f1f1c5ad44ecdb019e0661f5ac 800000000000000078303efb8617e594 9e4cc5f1f1c5ad44ecdb019e0661f5ac fpscr=00000000
+vrintn.f64.f64 d3, d15 b592c43eed070cd1fb77dc5c5b86d38d db68e8a3c26819ca1514ccccdc84e374 db68e8a3c26819cafb77dc5c5b86d38d db68e8a3c26819ca1514ccccdc84e374 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 dc6f72cf4ae28a8d35a3bea7c03e20ca c7a12e5692bf672d7ec426fc36351f85 c7a12e5692bf672d35a3bea7c03e20ca c7a12e5692bf672d7ec426fc36351f85 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vrintn.f64.f64 d3, d15 f534d9628d1dfa5fafaf20fe7b52d155 6b95cb3a406a9e2f6b95cb3a406a9e2f 6b95cb3a406a9e2fafaf20fe7b52d155 6b95cb3a406a9e2f6b95cb3a406a9e2f fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintn.f64.f64 d3, d15 538668456916742c8777a16b1a962544 b512d910383a7e3eb512d910383a7e3e 80000000000000008777a16b1a962544 b512d910383a7e3eb512d910383a7e3e fpscr=00000000
+vrintn.f64.f64 d3, d15 1dfd67967041fc4f9ea8e57e2e068df6 b695dca03bde2c0ccfa33e34d256b47a 80000000000000009ea8e57e2e068df6 b695dca03bde2c0ccfa33e34d256b47a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 a962d8b4c79ac47de6248cbcaf97aa62 726495fb79f99d48af9a3b48296bd6ca 726495fb79f99d48e6248cbcaf97aa62 726495fb79f99d48af9a3b48296bd6ca fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 8df1a313b0ccf92d3ff4c48eb4615233 062a435b12b0e7e2cb06c38864059535 00000000000000003ff4c48eb4615233 062a435b12b0e7e2cb06c38864059535 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 43bff6e353c2894eef2972a8a60a4335 404a44f6cfc54bf6404a44f6cfc54bf6 404a800000000000ef2972a8a60a4335 404a44f6cfc54bf6404a44f6cfc54bf6 fpscr=00000000
+vrintn.f64.f64 d3, d15 59ba94f10c0c629101330d3773c4a9f9 f13ada049adfab01aea537649b03a659 f13ada049adfab0101330d3773c4a9f9 f13ada049adfab01aea537649b03a659 fpscr=00000000
+vrintn.f64.f64 d3, d15 f818b7d8e4b27dbb8424c517083695d2 84cfd9566b3679c257677214dd7269cf 80000000000000008424c517083695d2 84cfd9566b3679c257677214dd7269cf fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 74657f799c76c52cf799df87bf0dcc32 4eadb235dd3585cf2d933e118f0ac162 4eadb235dd3585cff799df87bf0dcc32 4eadb235dd3585cf2d933e118f0ac162 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintn.f64.f64 d3, d15 522226784cc1090b522226784cc1090b 5b36fb47d94639ba8c6fc5e20d02b4ef 5b36fb47d94639ba522226784cc1090b 5b36fb47d94639ba8c6fc5e20d02b4ef fpscr=00000000
+vrintn.f64.f64 d3, d15 9548160eedbae4f01d773136943b2ed3 07f6c79cece388fd616bbdbd0ffe9bad 00000000000000001d773136943b2ed3 07f6c79cece388fd616bbdbd0ffe9bad fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintn.f64.f64 d3, d15 b812f5724f20a5ebab3127d94f9e72d8 30afcf12355182c45fe8147b7b2220b3 0000000000000000ab3127d94f9e72d8 30afcf12355182c45fe8147b7b2220b3 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 891a4b92a57d2309891a4b92a57d2309 aa055169649f13e5de9fa4cf2ccee63b 8000000000000000891a4b92a57d2309 aa055169649f13e5de9fa4cf2ccee63b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintn.f64.f64 d3, d15 037ac39d841f8e128b5a0c533e45cfed 22fe7db8a7f8daf402c2178bc8dd4ef9 00000000000000008b5a0c533e45cfed 22fe7db8a7f8daf402c2178bc8dd4ef9 fpscr=00000000
+vrintn.f64.f64 d3, d15 4885a1b8de641fa954d3cdeb6c53ef1d 36ee8e49dec27cce35a569f92646a309 000000000000000054d3cdeb6c53ef1d 36ee8e49dec27cce35a569f92646a309 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 aabfc54091dc28c2aabfc54091dc28c2 a0694e4ce13b69d1e5ca1782d75e4eef 8000000000000000aabfc54091dc28c2 a0694e4ce13b69d1e5ca1782d75e4eef fpscr=00000000
+vrintn.f64.f64 d3, d15 c6cebe7736a635488242cc7353951fbf db85cb91a381452af8276ed470b0bc25 db85cb91a381452a8242cc7353951fbf db85cb91a381452af8276ed470b0bc25 fpscr=00000000
+vrintn.f64.f64 d3, d15 da2d8926e414f159f16694e5a78c8ab3 10904397079c1aaf469a352779c5a6d7 0000000000000000f16694e5a78c8ab3 10904397079c1aaf469a352779c5a6d7 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintn.f64.f64 d3, d15 f770ba9f29cb8fd9998167a396a7ba34 bbc676d8bda3b288c9c2e7cae9937d21 8000000000000000998167a396a7ba34 bbc676d8bda3b288c9c2e7cae9937d21 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 3480d693c0eb4e7df9359b2c5d047df5 ec52433dad0385db1b90c8b3665e55b3 ec52433dad0385dbf9359b2c5d047df5 ec52433dad0385db1b90c8b3665e55b3 fpscr=00000000
+vrintn.f64.f64 d3, d15 6a013b39a11f798cb97c73aca9968f32 02e3af0229bfbdc1d41ffeb7b539e178 0000000000000000b97c73aca9968f32 02e3af0229bfbdc1d41ffeb7b539e178 fpscr=00000000
+vrintn.f64.f64 d3, d15 11f73625cba650c84bdc394e4c05c18d c7fa0a9e80db4e19c2938ae2322845bf c7fa0a9e80db4e194bdc394e4c05c18d c7fa0a9e80db4e19c2938ae2322845bf fpscr=00000000
+vrintn.f64.f64 d3, d15 38e2fb9c41beab35b8b57e63921d5225 cad298ff52421191af405932e3d3265d cad298ff52421191b8b57e63921d5225 cad298ff52421191af405932e3d3265d fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 ddee26f549b33295ddee26f549b33295 3632c0d88ab4d8973632c0d88ab4d897 0000000000000000ddee26f549b33295 3632c0d88ab4d8973632c0d88ab4d897 fpscr=00000000
+vrinta.f64.f64 d6, d18 750df7e73f1592950d5f0978b2ff1b20 90c97f9f3d4de279ea37dd74eff68b2b 750df7e73f159295ea37dd74eff68b2b 90c97f9f3d4de279ea37dd74eff68b2b fpscr=00000000
+vrinta.f64.f64 d6, d18 15774aa77a78bbbb98ac6a3a04d02db0 b9d7061609e6002aa6612a564c63d3f5 15774aa77a78bbbb8000000000000000 b9d7061609e6002aa6612a564c63d3f5 fpscr=00000000
+vrinta.f64.f64 d6, d18 e3ce029b10daf0e146ad5f36033edbe7 6633c644b4b911345f63416ded9fe625 e3ce029b10daf0e15f63416ded9fe625 6633c644b4b911345f63416ded9fe625 fpscr=00000000
+vrinta.f64.f64 d6, d18 67f4472f16aefb1449947d1e398a4437 4f95a9ca82f21a8048f1ec91709f24c8 67f4472f16aefb1448f1ec91709f24c8 4f95a9ca82f21a8048f1ec91709f24c8 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vrinta.f64.f64 d6, d18 fb879d9518351b70fb879d9518351b70 e241d75c2be056dde241d75c2be056dd fb879d9518351b70e241d75c2be056dd e241d75c2be056dde241d75c2be056dd fpscr=00000000
+vrinta.f64.f64 d6, d18 dc43bfdf6ba52443d2d9c4bfdf8d8646 af91c79efb49100a6cdc35fbad7baef1 dc43bfdf6ba524436cdc35fbad7baef1 af91c79efb49100a6cdc35fbad7baef1 fpscr=00000000
+vrinta.f64.f64 d6, d18 7e5b78958df49918c8d4d0a7b3048d61 ad9d77db769f61e37c65852001b73a44 7e5b78958df499187c65852001b73a44 ad9d77db769f61e37c65852001b73a44 fpscr=00000000
+vrinta.f64.f64 d6, d18 f594a96670d015f815bde3c7464da7e3 984048e84af8a8d5e91d0b71acbabcb9 f594a96670d015f8e91d0b71acbabcb9 984048e84af8a8d5e91d0b71acbabcb9 fpscr=00000000
+vrinta.f64.f64 d6, d18 a99634bbf7238a1daeeb282ed57ffecc 35542a5bfc919f2f51b9f99de769a6a6 a99634bbf7238a1d51b9f99de769a6a6 35542a5bfc919f2f51b9f99de769a6a6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrinta.f64.f64 d6, d18 e512e49492f3f1a01cc748e69a8e1219 b7af8e0e5eca1320b7af8e0e5eca1320 e512e49492f3f1a08000000000000000 b7af8e0e5eca1320b7af8e0e5eca1320 fpscr=00000000
+vrinta.f64.f64 d6, d18 3b1ceb761808f12f8b0dd4b350b4c45f dd04a0b39844945e32760eb1d6dfbbc6 3b1ceb761808f12f0000000000000000 dd04a0b39844945e32760eb1d6dfbbc6 fpscr=00000000
+vrinta.f64.f64 d6, d18 f9d66a72c0a11c628beaecddfab4cfb5 66d27749292de9f5c0ca54935f7e236a f9d66a72c0a11c62c0ca548000000000 66d27749292de9f5c0ca54935f7e236a fpscr=00000000
+vrinta.f64.f64 d6, d18 867e546ecd9ae93c190f33ee4cd836fc 0b1a6e35d1cc971e1a025533fef6d8b0 867e546ecd9ae93c0000000000000000 0b1a6e35d1cc971e1a025533fef6d8b0 fpscr=00000000
+vrinta.f64.f64 d6, d18 280015d4ef00cf02bbe5a394a6478ef9 e3e3decc97425ca42f38f7c690e3c3cf 280015d4ef00cf020000000000000000 e3e3decc97425ca42f38f7c690e3c3cf fpscr=00000000
+vrinta.f64.f64 d6, d18 3112293fc1ac21dc18873bf12498f958 d99fa00cb06dfd414402871c5f7677a2 3112293fc1ac21dc4402871c5f7677a2 d99fa00cb06dfd414402871c5f7677a2 fpscr=00000000
+vrinta.f64.f64 d6, d18 e7f7108a4b24a00220bb34ec62f3f91b 1c88510e05f3a4b9ac143955f2bad1fd e7f7108a4b24a0028000000000000000 1c88510e05f3a4b9ac143955f2bad1fd fpscr=00000000
+vrinta.f64.f64 d6, d18 cb18a8b9ea5773ce92d7945ca60fafe6 706e70e1a2a71c4d4d4c83fcb73a7169 cb18a8b9ea5773ce4d4c83fcb73a7169 706e70e1a2a71c4d4d4c83fcb73a7169 fpscr=00000000
+vrinta.f64.f64 d6, d18 58d855ba0a4def8e13105f7692091c34 8a3c436677f66cc9739923148193917d 58d855ba0a4def8e739923148193917d 8a3c436677f66cc9739923148193917d fpscr=00000000
+vrinta.f64.f64 d6, d18 288b19915fc2679b3e1c65dd4f23f9eb e02f432766a0a9276dab9e5fb9321838 288b19915fc2679b6dab9e5fb9321838 e02f432766a0a9276dab9e5fb9321838 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrinta.f64.f64 d6, d18 8da1cc34ea3bb02d8da1cc34ea3bb02d 2364d62c9400a250bae0bf6428a35df4 8da1cc34ea3bb02d8000000000000000 2364d62c9400a250bae0bf6428a35df4 fpscr=00000000
+vrinta.f64.f64 d6, d18 24c0ada747db94f2ae892e1f4fd346fd d295a14b420ac25c1aebe35acf1e6f6b 24c0ada747db94f20000000000000000 d295a14b420ac25c1aebe35acf1e6f6b fpscr=00000000
+vrinta.f64.f64 d6, d18 cab41cdb053132abefa6f4a451c5c130 b76edd5197d8ed9509d86e9292319fcc cab41cdb053132ab0000000000000000 b76edd5197d8ed9509d86e9292319fcc fpscr=00000000
+vrinta.f64.f64 d6, d18 b235862cc2ed578c2411631ea7b90190 d98782f24134dbf279d2ff44d8b03bae b235862cc2ed578c79d2ff44d8b03bae d98782f24134dbf279d2ff44d8b03bae fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrinta.f64.f64 d6, d18 e77afca362bf1f61e77afca362bf1f61 3198ee95c0054f1598d1bf1f0434d863 e77afca362bf1f618000000000000000 3198ee95c0054f1598d1bf1f0434d863 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrinta.f64.f64 d6, d18 0f047614a80adc6ccc99ee15a16f8f10 00f8d144d1160cd100f8d144d1160cd1 0f047614a80adc6c0000000000000000 00f8d144d1160cd100f8d144d1160cd1 fpscr=00000000
+vrinta.f64.f64 d6, d18 ee5a5fa305b7b4292cd633852ed35e39 5cc5b15a81fc67168fd7bb547c818f33 ee5a5fa305b7b4298000000000000000 5cc5b15a81fc67168fd7bb547c818f33 fpscr=00000000
+vrinta.f64.f64 d6, d18 8b7446c0c14e811ee074a53a271c7c80 327510060806de7814a6bb00a1dc2bad 8b7446c0c14e811e0000000000000000 327510060806de7814a6bb00a1dc2bad fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vrinta.f64.f64 d6, d18 843063c7c260af78ac9a544e1dbd0063 c7d3e1500826085ca0f55b1d95ca11ad 843063c7c260af788000000000000000 c7d3e1500826085ca0f55b1d95ca11ad fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrinta.f64.f64 d6, d18 df74b7887d60c004f40aabe3c84b7c16 67a5a9a2095c29b167a5a9a2095c29b1 df74b7887d60c00467a5a9a2095c29b1 67a5a9a2095c29b167a5a9a2095c29b1 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrinta.f64.f64 d6, d18 53ac2ce014009b71e6531492daf69314 c2424536450d84b5e44a178238a95a76 53ac2ce014009b71e44a178238a95a76 c2424536450d84b5e44a178238a95a76 fpscr=00000000
+vrinta.f64.f64 d6, d18 8f09742261564433fb7199f3bf12485f 2c2a2d8147bfb84be2cd6a4e28de42e3 8f09742261564433e2cd6a4e28de42e3 2c2a2d8147bfb84be2cd6a4e28de42e3 fpscr=00000000
+vrinta.f64.f64 d6, d18 fa60ce40285c1b60d30cfc83aca730e1 ec2438193f2d640f2faa89b43f1c6db8 fa60ce40285c1b600000000000000000 ec2438193f2d640f2faa89b43f1c6db8 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrinta.f64.f64 d6, d18 842eabaa671d6dbcad1100f62bc5db7c 2ff534f2e5d316dc2ff534f2e5d316dc 842eabaa671d6dbc0000000000000000 2ff534f2e5d316dc2ff534f2e5d316dc fpscr=00000000
+vrinta.f64.f64 d6, d18 8b4a9a3f24bd648d8847885b20fd7f08 c2bd1382ac26e9e004eb6ba1a01bdce0 8b4a9a3f24bd648d0000000000000000 c2bd1382ac26e9e004eb6ba1a01bdce0 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vrinta.f64.f64 d6, d18 eb9d1c6aaef7baf8eb9d1c6aaef7baf8 2c68d1c24a0bc0dfb61e834c7cb563b2 eb9d1c6aaef7baf88000000000000000 2c68d1c24a0bc0dfb61e834c7cb563b2 fpscr=00000000
+vrinta.f64.f64 d6, d18 e9489b583b15c86949eda5015da284e5 ce165dc84b43fdcb6209ebdf2f8f4071 e9489b583b15c8696209ebdf2f8f4071 ce165dc84b43fdcb6209ebdf2f8f4071 fpscr=00000000
+vrinta.f64.f64 d6, d18 2c90da4d5e2df1c3e6eaeba162113ef9 448080adbd80236236c590af83b3e1d0 2c90da4d5e2df1c30000000000000000 448080adbd80236236c590af83b3e1d0 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: 10752 calls, 11089 iters
+vrinta.f64.f64 d6, d18 200b3ee41788b9ff200b3ee41788b9ff cab65110b3360f2687edac4137b8daa3 200b3ee41788b9ff8000000000000000 cab65110b3360f2687edac4137b8daa3 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrinta.f64.f64 d6, d18 b14b88e9af066f66b14b88e9af066f66 397a0e48c3c545bbb05796211bae0eae b14b88e9af066f668000000000000000 397a0e48c3c545bbb05796211bae0eae fpscr=00000000
+vrinta.f64.f64 d6, d18 859fcc157ccadb531b60052e1b6bb52c 9e6f35c0ce5b0fb0dfec08d02ee998a3 859fcc157ccadb53dfec08d02ee998a3 9e6f35c0ce5b0fb0dfec08d02ee998a3 fpscr=00000000
+vrinta.f64.f64 d6, d18 b740589f416db4ca02b7dea557814e42 56614e1935ffe6d55df4d30c1a74cad6 b740589f416db4ca5df4d30c1a74cad6 56614e1935ffe6d55df4d30c1a74cad6 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrinta.f64.f64 d6, d18 780c3d4d03311fe45ead402baaa2f99d 2586c4962ff0a01036a6a38670e8acf7 780c3d4d03311fe40000000000000000 2586c4962ff0a01036a6a38670e8acf7 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrinta.f64.f64 d6, d18 1767b1a6b96302afef05ab909caa1814 c7cb3ea69010e8fec7cb3ea69010e8fe 1767b1a6b96302afc7cb3ea69010e8fe c7cb3ea69010e8fec7cb3ea69010e8fe fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrinta.f64.f64 d6, d18 7ec25f5e74b55a05e39129c6fe805680 2c13912baed24b562c13912baed24b56 7ec25f5e74b55a050000000000000000 2c13912baed24b562c13912baed24b56 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrinta.f64.f64 d6, d18 2a67fa4dfbf69f809665e6b7a8735f6d 9c5477320eb264ec1cb3c77d7e39602c 2a67fa4dfbf69f800000000000000000 9c5477320eb264ec1cb3c77d7e39602c fpscr=00000000
+vrinta.f64.f64 d6, d18 54bd7429d4494b8d31745571673fe230 ff12a497f01dccb18c4a8e756eed8e04 54bd7429d4494b8d8000000000000000 ff12a497f01dccb18c4a8e756eed8e04 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrinta.f64.f64 d6, d18 0b9af11cdd5508e5a9139660ec771369 8cf4ffba308c3cf78cf4ffba308c3cf7 0b9af11cdd5508e58000000000000000 8cf4ffba308c3cf78cf4ffba308c3cf7 fpscr=00000000
+vrinta.f64.f64 d6, d18 61558a05f1e2728531a0482857595020 6f42744ba9c4fe297ac26d78c7e53709 61558a05f1e272857ac26d78c7e53709 6f42744ba9c4fe297ac26d78c7e53709 fpscr=00000000
+vrinta.f64.f64 d6, d18 c0f4e64d353b221da7247667dd030516 e77466648aa853c424a219228ac58214 c0f4e64d353b221d0000000000000000 e77466648aa853c424a219228ac58214 fpscr=00000000
+vrinta.f64.f64 d6, d18 7dab2743ac488585d31a25b242a1f0b8 c0fd4ae2aa4b82428930e241133da7a8 7dab2743ac4885858000000000000000 c0fd4ae2aa4b82428930e241133da7a8 fpscr=00000000
+vrintp.f64.f64 d9, d21 f4861b414cc712b6081045099cd0f3a3 551811d4bca9f7417f6a4b5a4a3a0122 551811d4bca9f741081045099cd0f3a3 551811d4bca9f7417f6a4b5a4a3a0122 fpscr=00000000
+vrintp.f64.f64 d9, d21 2790c5cf2898dba691b83322352f87b7 347bdf981631f297d6232f704432a30b 3ff000000000000091b83322352f87b7 347bdf981631f297d6232f704432a30b fpscr=00000000
+vrintp.f64.f64 d9, d21 0268b595566f8c5d37bb4993ad5ced67 702128ae2732c5c7e4ff1c1fefcbd4ce 702128ae2732c5c737bb4993ad5ced67 702128ae2732c5c7e4ff1c1fefcbd4ce fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintp.f64.f64 d9, d21 02c4bc213b7bb9de287dd6e084d0c5e6 cc6baef1bf9af2d7f5e392119fe171cd cc6baef1bf9af2d7287dd6e084d0c5e6 cc6baef1bf9af2d7f5e392119fe171cd fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintp.f64.f64 d9, d21 d27def28d62738cf009e27e098f93bbc 73b8a195f78ec9a95f293d22298896b4 73b8a195f78ec9a9009e27e098f93bbc 73b8a195f78ec9a95f293d22298896b4 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintp.f64.f64 d9, d21 07d5cf96fea0b56507d5cf96fea0b565 42ccc978ecf6d99990ff87d726f69d3f 42ccc978ecf6da0007d5cf96fea0b565 42ccc978ecf6d99990ff87d726f69d3f fpscr=00000000
+vrintp.f64.f64 d9, d21 b025707ddf6b4f0304ec0845e548ce5e 1459f3ae523de656e834a43dd87ca5ee 3ff000000000000004ec0845e548ce5e 1459f3ae523de656e834a43dd87ca5ee fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintp.f64.f64 d9, d21 b7ff45b302eaaa388fe5cdc8a496e39b acd9db0041b689b7acd9db0041b689b7 80000000000000008fe5cdc8a496e39b acd9db0041b689b7acd9db0041b689b7 fpscr=00000000
+vrintp.f64.f64 d9, d21 d4d6dc68663411743b8b4dcd4da6725f c25c064125c24962080c81e839c631ff c25c064125c240003b8b4dcd4da6725f c25c064125c24962080c81e839c631ff fpscr=00000000
+vrintp.f64.f64 d9, d21 041a3426a0bebab3571aedb0cc010d48 7899dd049e0e9723ccd5238f932369ea 7899dd049e0e9723571aedb0cc010d48 7899dd049e0e9723ccd5238f932369ea fpscr=00000000
+vrintp.f64.f64 d9, d21 5aecfdef74111228a29a3cc5d1f87cfe 5f953c99d7bfeb6fe0088c454adf8e37 5f953c99d7bfeb6fa29a3cc5d1f87cfe 5f953c99d7bfeb6fe0088c454adf8e37 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintp.f64.f64 d9, d21 3cc16581c505508d11f0170801ef5d33 0e6126b9a028e1cd72ab0578d974c563 3ff000000000000011f0170801ef5d33 0e6126b9a028e1cd72ab0578d974c563 fpscr=00000000
+vrintp.f64.f64 d9, d21 6f9ecbe5f35ff5a947169140d6e28a94 352b667aeffa4ea7f35d061370ba0280 3ff000000000000047169140d6e28a94 352b667aeffa4ea7f35d061370ba0280 fpscr=00000000
+vrintp.f64.f64 d9, d21 aa7f12ac6c95c6e4e4385ab05d6c1af7 a4eac7c51d1d172fd63faa60563e20e2 8000000000000000e4385ab05d6c1af7 a4eac7c51d1d172fd63faa60563e20e2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintp.f64.f64 d9, d21 6354873d5838e4096354873d5838e409 e4265ff0ad78fc69d11f22261e803e05 e4265ff0ad78fc696354873d5838e409 e4265ff0ad78fc69d11f22261e803e05 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintp.f64.f64 d9, d21 b2bb5d64a7ca9413b2bb5d64a7ca9413 3da1e06407878e2176967638ecca7471 3ff0000000000000b2bb5d64a7ca9413 3da1e06407878e2176967638ecca7471 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintp.f64.f64 d9, d21 c74f476c44ff4c33edeb156e96cb8b4e 4f3f9ab0057fe7f36adc327719d68b8e 4f3f9ab0057fe7f3edeb156e96cb8b4e 4f3f9ab0057fe7f36adc327719d68b8e fpscr=00000000
+vrintp.f64.f64 d9, d21 350a700285d54720599f95c004a91477 5866a9a414fa9a3f23d9f883cd0f18bf 5866a9a414fa9a3f599f95c004a91477 5866a9a414fa9a3f23d9f883cd0f18bf fpscr=00000000
+vrintp.f64.f64 d9, d21 7d00daefbd8636b44babaebb7875f40c 604107f6d36cf90f90caeb8c10bee89b 604107f6d36cf90f4babaebb7875f40c 604107f6d36cf90f90caeb8c10bee89b fpscr=00000000
+vrintp.f64.f64 d9, d21 e7d57f9173c456e48ba709f61c176912 ad33dcabe5080c7601ef0017aeed7da4 80000000000000008ba709f61c176912 ad33dcabe5080c7601ef0017aeed7da4 fpscr=00000000
+vrintp.f64.f64 d9, d21 0281fc3d94cf6485608e7621a22702c9 0812d96741fd6014e03e6f520fb3407d 3ff0000000000000608e7621a22702c9 0812d96741fd6014e03e6f520fb3407d fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintp.f64.f64 d9, d21 98182044eb5774f1a7342c3724bf1a05 74a65f09691b1bdaa1232897b0c3906a 74a65f09691b1bdaa7342c3724bf1a05 74a65f09691b1bdaa1232897b0c3906a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintp.f64.f64 d9, d21 14b577d09d477ee9e17d8760ec38fe67 95b54b4ee7052c8795b54b4ee7052c87 8000000000000000e17d8760ec38fe67 95b54b4ee7052c8795b54b4ee7052c87 fpscr=00000000
+vrintp.f64.f64 d9, d21 96108c9ec74207056b503a8ecd334411 556ee144e53f88bf49adae33f7eba926 556ee144e53f88bf6b503a8ecd334411 556ee144e53f88bf49adae33f7eba926 fpscr=00000000
+vrintp.f64.f64 d9, d21 fa36050ed786d0a818f6c414683b0141 1a02509ef970b88eb8e9921ab8f86fe2 3ff000000000000018f6c414683b0141 1a02509ef970b88eb8e9921ab8f86fe2 fpscr=00000000
+vrintp.f64.f64 d9, d21 b83b166ff9efd3fb20936efaa511c2e0 8cabede730d3a7672513f4aa45ee65f1 800000000000000020936efaa511c2e0 8cabede730d3a7672513f4aa45ee65f1 fpscr=00000000
+vrintp.f64.f64 d9, d21 ac9fe25d5c7b60e95e4ac217bab777f6 6d7220418caa74c81059f7e25aa7a908 6d7220418caa74c85e4ac217bab777f6 6d7220418caa74c81059f7e25aa7a908 fpscr=00000000
+vrintp.f64.f64 d9, d21 f22cdd7ad9b6b9f8b158d54882c7810f c3d8eec738060b1bfbdb9a803586cd1c c3d8eec738060b1bb158d54882c7810f c3d8eec738060b1bfbdb9a803586cd1c fpscr=00000000
+vrintp.f64.f64 d9, d21 026193ab5e47ef15d99fb0c76aa12b64 1841515c9a67574c25e620cd35690552 3ff0000000000000d99fb0c76aa12b64 1841515c9a67574c25e620cd35690552 fpscr=00000000
+vrintp.f64.f64 d9, d21 33151e60ac142612cb5a201a8bbba728 2ff81b9e848362c9a8ef8f2792f0bf37 3ff0000000000000cb5a201a8bbba728 2ff81b9e848362c9a8ef8f2792f0bf37 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vrintp.f64.f64 d9, d21 0549398c1b28c4266645b47819c64ee7 586125036221b7fe9e4b4aea4d4ff837 586125036221b7fe6645b47819c64ee7 586125036221b7fe9e4b4aea4d4ff837 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintp.f64.f64 d9, d21 408f4fc57a689eea408f4fc57a689eea 7182cd86305f99927182cd86305f9992 7182cd86305f9992408f4fc57a689eea 7182cd86305f99927182cd86305f9992 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintp.f64.f64 d9, d21 256ee5ecc09d7670ef6328b23304715a 90b7ac8e076807dc8cc9d3a101f29387 8000000000000000ef6328b23304715a 90b7ac8e076807dc8cc9d3a101f29387 fpscr=00000000
+vrintp.f64.f64 d9, d21 5918d50a3ab9980067262220df5c4f77 4717ae4359235d926179458c986a717c 4717ae4359235d9267262220df5c4f77 4717ae4359235d926179458c986a717c fpscr=00000000
+vrintp.f64.f64 d9, d21 2fb5d867836e8b05f9bd625c9884d4c5 89fb53c1b3d5c88df1ec64e385c2df8f 8000000000000000f9bd625c9884d4c5 89fb53c1b3d5c88df1ec64e385c2df8f fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintp.f64.f64 d9, d21 0d4e6e985f66073869bcb9a2e6fa8509 aa65027ce9b824b4d3af7ab17ad272b0 800000000000000069bcb9a2e6fa8509 aa65027ce9b824b4d3af7ab17ad272b0 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintp.f64.f64 d9, d21 4152fd7131c4d23b4152fd7131c4d23b 6395554a939495259373a6a46faf62d6 6395554a939495254152fd7131c4d23b 6395554a939495259373a6a46faf62d6 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintp.f64.f64 d9, d21 c525a5f35eb1ed19e2e8b1c40a0ba740 165dd6bbfaee6874165dd6bbfaee6874 3ff0000000000000e2e8b1c40a0ba740 165dd6bbfaee6874165dd6bbfaee6874 fpscr=00000000
+vrintp.f64.f64 d9, d21 f17a27b496287b9c59908bee3b09939f c830f7f1e3b0846b69da5e8c7658d7e2 c830f7f1e3b0846b59908bee3b09939f c830f7f1e3b0846b69da5e8c7658d7e2 fpscr=00000000
+vrintp.f64.f64 d9, d21 753604f6a872fee9ebe1b027d27afac8 aeecc4eeaea23412a2fde0b418bf624e 8000000000000000ebe1b027d27afac8 aeecc4eeaea23412a2fde0b418bf624e fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vrintp.f64.f64 d9, d21 41ea6a6d2294a195c042526753ab4525 ac6e22eac1d4a614ac6e22eac1d4a614 8000000000000000c042526753ab4525 ac6e22eac1d4a614ac6e22eac1d4a614 fpscr=00000000
+vrintp.f64.f64 d9, d21 89e3a021721f57a217366cf64057c0e8 083039a6caced193ecf5bfdcf70ffa99 3ff000000000000017366cf64057c0e8 083039a6caced193ecf5bfdcf70ffa99 fpscr=00000000
+vrintp.f64.f64 d9, d21 0492e69dc8d8765ae4a35dddbd101ded 378403345d9abf3f631f2e0e86045abc 3ff0000000000000e4a35dddbd101ded 378403345d9abf3f631f2e0e86045abc fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintp.f64.f64 d9, d21 10bd300dd91e57a4a0652d910c26e348 3be18d206604aae9b7dedbe77a6b8b69 3ff0000000000000a0652d910c26e348 3be18d206604aae9b7dedbe77a6b8b69 fpscr=00000000
+vrintp.f64.f64 d9, d21 7d6f94468622fa4a16d46efccd38facf 56142d72203b3b6533cee0fb3c9c75db 56142d72203b3b6516d46efccd38facf 56142d72203b3b6533cee0fb3c9c75db fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintp.f64.f64 d9, d21 2bf77352e3a378c22bf77352e3a378c2 dda37e01a63e1982601fc1f947d98a7c dda37e01a63e19822bf77352e3a378c2 dda37e01a63e1982601fc1f947d98a7c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintp.f64.f64 d9, d21 93ab366b30c46b34d2a3779e846ef775 4819b367988c163b4e472c789712f903 4819b367988c163bd2a3779e846ef775 4819b367988c163b4e472c789712f903 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintp.f64.f64 d9, d21 032a965e15bf81e4485b366f1acd7138 65853eedbe771c67712bdc632877b91f 65853eedbe771c67485b366f1acd7138 65853eedbe771c67712bdc632877b91f fpscr=00000000
+vrintp.f64.f64 d9, d21 51fff75e1cf7fe1e0483c374fe803e1f 02632d98f10733580576f9fdd7fe91b7 3ff00000000000000483c374fe803e1f 02632d98f10733580576f9fdd7fe91b7 fpscr=00000000
+vrintp.f64.f64 d9, d21 c1158e89be9f399c43e69303bea2ceb1 9d6e8f800340aafee95ca70bf834be78 800000000000000043e69303bea2ceb1 9d6e8f800340aafee95ca70bf834be78 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintm.f64.f64 d12, d12 1f25711cabdccdd61f25711cabdccdd6 ea67c1d95d7ca5229fb93bf83b58e675 ea67c1d95d7ca522bff0000000000000 ea67c1d95d7ca522bff0000000000000 fpscr=00000000
+randV128: 11008 calls, 11357 iters
+vrintm.f64.f64 d12, d12 8f89627e84711d0eab2e960e46811bc8 d17f79839d98462694eabe83ebf5c961 d17f79839d984626bff0000000000000 d17f79839d984626bff0000000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 8725080685ce689566c149c25830f959 aa78114056240076476b961e22a3b4a8 aa78114056240076476b961e22a3b4a8 aa78114056240076476b961e22a3b4a8 fpscr=00000000
+vrintm.f64.f64 d12, d12 1fe80767f232ce304de59b93e64a3144 ef67453e9accab9bd3842f8001b9c63f ef67453e9accab9bd3842f8001b9c63f ef67453e9accab9bd3842f8001b9c63f fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 adfb75178cc777b7c0ec2aca90402fb9 4cc23feb9b1e3cf44cc23feb9b1e3cf4 4cc23feb9b1e3cf44cc23feb9b1e3cf4 4cc23feb9b1e3cf44cc23feb9b1e3cf4 fpscr=00000000
+vrintm.f64.f64 d12, d12 7445c94b6f5ddfecb1c66c07c29d5284 2f10162eb715fad0a2151fff7885a3e4 2f10162eb715fad0bff0000000000000 2f10162eb715fad0bff0000000000000 fpscr=00000000
+vrintm.f64.f64 d12, d12 27ba9def449c94c2d672a29725078443 d3317995fced05e36b589f07ae4d606e d3317995fced05e36b589f07ae4d606e d3317995fced05e36b589f07ae4d606e fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 2c2f770eac4118a08f25addfb35a9c3b 012810b982e64ee1f51f5efe3d6ad00e 012810b982e64ee1f51f5efe3d6ad00e 012810b982e64ee1f51f5efe3d6ad00e fpscr=00000000
+vrintm.f64.f64 d12, d12 e8fb0400df0eab6c4479156c7aad7318 a732c60b9b155e7f2e0cde79cbc92d35 a732c60b9b155e7f0000000000000000 a732c60b9b155e7f0000000000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 e4be79540af865f7e4be79540af865f7 900200c3ea3ddafa6f5275935189bdf5 900200c3ea3ddafa6f5275935189bdf5 900200c3ea3ddafa6f5275935189bdf5 fpscr=00000000
+vrintm.f64.f64 d12, d12 d82f64733db49cf3227fa8ad6da36f2d 22bcc9b1dcc32459852e8cd5dde490ae 22bcc9b1dcc32459bff0000000000000 22bcc9b1dcc32459bff0000000000000 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintm.f64.f64 d12, d12 24cec7bbce65bceb6fa120ce80b4201a 47cf610cb37383c18a5dc63832319e24 47cf610cb37383c1bff0000000000000 47cf610cb37383c1bff0000000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 c1d1a7f046886f0e3df2cb3f5aac02b4 a409b38899b0782fa409b38899b0782f a409b38899b0782fbff0000000000000 a409b38899b0782fbff0000000000000 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintm.f64.f64 d12, d12 5bebdf86990353445bebdf8699035344 db506e3363007094a2f8a62016c50bbf db506e3363007094bff0000000000000 db506e3363007094bff0000000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 71d9fd58e27f4d58ad96fb5e4e6a6ad4 336f9668735342446a355adc681ce3de 336f9668735342446a355adc681ce3de 336f9668735342446a355adc681ce3de fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 40897e0cbdc27a8740897e0cbdc27a87 7b9f4983c99e0c0309a983f31d049e2a 7b9f4983c99e0c030000000000000000 7b9f4983c99e0c030000000000000000 fpscr=00000000
+vrintm.f64.f64 d12, d12 45a4000e6664bab9c2604775c59b5c75 ec44a6fdbaf5d3ae145395f4425fcf96 ec44a6fdbaf5d3ae0000000000000000 ec44a6fdbaf5d3ae0000000000000000 fpscr=00000000
+vrintm.f64.f64 d12, d12 0fe672eba580ff24071b1d27ee69fb38 ccec2b5a42a23ef406ee7a40ba897aa4 ccec2b5a42a23ef40000000000000000 ccec2b5a42a23ef40000000000000000 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintm.f64.f64 d12, d12 a5ffa3350f6e76a11f7f6029eb867d47 7f2ff5e4a1fe6a0fdf3070a5fac2cda6 7f2ff5e4a1fe6a0fdf3070a5fac2cda6 7f2ff5e4a1fe6a0fdf3070a5fac2cda6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 7077d1ae40a206037077d1ae40a20603 349407aaf5d7f86c7d11f4884e106493 349407aaf5d7f86c7d11f4884e106493 349407aaf5d7f86c7d11f4884e106493 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintm.f64.f64 d12, d12 829823feaea9a91658a2fb696225b65b da69a12c8c6b90bce43e9d58a23482c8 da69a12c8c6b90bce43e9d58a23482c8 da69a12c8c6b90bce43e9d58a23482c8 fpscr=00000000
+vrintm.f64.f64 d12, d12 fd6cfabe565f86808b716aa58577615c b267aa73d646bdf1d50e329d0521b187 b267aa73d646bdf1d50e329d0521b187 b267aa73d646bdf1d50e329d0521b187 fpscr=00000000
+vrintm.f64.f64 d12, d12 0479d0abfb348a8e76307d8d1e85a438 70854dadbce2d404f5c2390427f3b265 70854dadbce2d404f5c2390427f3b265 70854dadbce2d404f5c2390427f3b265 fpscr=00000000
+vrintm.f64.f64 d12, d12 3deb22fbc51e77e4b1da43d088c0c89f b8f176d41a2407288ddee0070d52baf7 b8f176d41a240728bff0000000000000 b8f176d41a240728bff0000000000000 fpscr=00000000
+vrintm.f64.f64 d12, d12 ff415e850c7f2b48fb80aafb38fc7e9e 40b12e04a1d752a34d003a36604b1a8f 40b12e04a1d752a34d003a36604b1a8f 40b12e04a1d752a34d003a36604b1a8f fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 1920c79499ca62383bb9b4a6c27c9cd9 b25cb3a8a9eee892b25cb3a8a9eee892 b25cb3a8a9eee892bff0000000000000 b25cb3a8a9eee892bff0000000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 2d6f6005c4ce81732d6f6005c4ce8173 bcd0483e722ed4082aaf0fd1942c99fb bcd0483e722ed4080000000000000000 bcd0483e722ed4080000000000000000 fpscr=00000000
+vrintm.f64.f64 d12, d12 53d6b4d675eb2eb96d77387240e33846 c0ceeeb62d44c8bb40e795e295e66eb1 c0ceeeb62d44c8bb40e795e000000000 c0ceeeb62d44c8bb40e795e000000000 fpscr=00000000
+vrintm.f64.f64 d12, d12 49093684b1428c01390917f2fecbd9e2 3a1408e4a4c2511ff148b5ae76e00c8e 3a1408e4a4c2511ff148b5ae76e00c8e 3a1408e4a4c2511ff148b5ae76e00c8e fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 eaf0f2ead31365b33f2efa796c319387 f2d233550b81dc91f2d233550b81dc91 f2d233550b81dc91f2d233550b81dc91 f2d233550b81dc91f2d233550b81dc91 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintm.f64.f64 d12, d12 de211341b6c4315347560b396ab20793 02276311eab7a9f1f07eeb9650df609e 02276311eab7a9f1f07eeb9650df609e 02276311eab7a9f1f07eeb9650df609e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintm.f64.f64 d12, d12 e1275facadc8ed83e1275facadc8ed83 bff20659339abb469b470409ed82e196 bff20659339abb46bff0000000000000 bff20659339abb46bff0000000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 e3bffc3c77cce1458d90c3bcaa1e854b c640debb1e03c1b5a0119290e48bd9a4 c640debb1e03c1b5bff0000000000000 c640debb1e03c1b5bff0000000000000 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintm.f64.f64 d12, d12 766350d31a70a8767b81f3461f88fa9e cab2a72f144af361cab2a72f144af361 cab2a72f144af361cab2a72f144af361 cab2a72f144af361cab2a72f144af361 fpscr=00000000
+vrintm.f64.f64 d12, d12 ab8270b3aa067e2ab9065e579a7bab67 95c48cab90d0ab8b1330dedb740e0f98 95c48cab90d0ab8b0000000000000000 95c48cab90d0ab8b0000000000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 c5a455d372304e609d1f6ab6ee7e2eda 2b3df8ebc7d38d1373b5db08e55ae9db 2b3df8ebc7d38d1373b5db08e55ae9db 2b3df8ebc7d38d1373b5db08e55ae9db fpscr=00000000
+vrintm.f64.f64 d12, d12 e3091bcffd72babe59d17cc005027962 02f356bdb8676b16f6b232434d090033 02f356bdb8676b16f6b232434d090033 02f356bdb8676b16f6b232434d090033 fpscr=00000000
+vrintm.f64.f64 d12, d12 39e651fdca5e5da7c0fde8f29ea391ea 34510650cedd585142ea82dff6ab86b5 34510650cedd585142ea82dff6ab86a0 34510650cedd585142ea82dff6ab86a0 fpscr=00000000
+vrintm.f64.f64 d12, d12 61ffa0d3176a0b7a322b3c69b73a9739 428c3cb4eea649c45141aabbcd18a3e0 428c3cb4eea649c45141aabbcd18a3e0 428c3cb4eea649c45141aabbcd18a3e0 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 d12efa58b4fce50684ed4176fbd09a74 1301a7969a012193d502e36cecfdacdb 1301a7969a012193d502e36cecfdacdb 1301a7969a012193d502e36cecfdacdb fpscr=00000000
+vrintm.f64.f64 d12, d12 e34a453228fef2bf9168f5830b7a84de b2ff6dce70e55179c09dc1aaa618f6eb b2ff6dce70e55179c09dc40000000000 b2ff6dce70e55179c09dc40000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vrintm.f64.f64 d12, d12 2ab62a8186ac4e98d8e80043bd376303 c1df48203ef979d472e46fa8c689a717 c1df48203ef979d472e46fa8c689a717 c1df48203ef979d472e46fa8c689a717 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vrintm.f64.f64 d12, d12 6c1efc469f0f15706c1efc469f0f1570 f7baa102cd24a19df7baa102cd24a19d f7baa102cd24a19df7baa102cd24a19d f7baa102cd24a19df7baa102cd24a19d fpscr=00000000
+vrintm.f64.f64 d12, d12 b424d02366a58231f836d96f19a84b2a 7f08a4261823d4105e71802fc42d3041 7f08a4261823d4105e71802fc42d3041 7f08a4261823d4105e71802fc42d3041 fpscr=00000000
+vrintm.f64.f64 d12, d12 428a2b868f84c7e3facbdaafd0a47020 8500e4c59114f715c2fbb9909e78b133 8500e4c59114f715c2fbb9909e78b140 8500e4c59114f715c2fbb9909e78b140 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 365c8821588f1fc715a1e31e42a0d2c8 9264fe011ea0c5069264fe011ea0c506 9264fe011ea0c506bff0000000000000 9264fe011ea0c506bff0000000000000 fpscr=00000000
+vrintm.f64.f64 d12, d12 e263589a490b72d8d2f80c5f8e70d01e 30423a32499324352290fc4826dc57c4 30423a32499324350000000000000000 30423a32499324350000000000000000 fpscr=00000000
+vrintm.f64.f64 d12, d12 0583866c94d31a48324e63e861172ff2 2b2743ce28a8184d891605eb157b88ad 2b2743ce28a8184dbff0000000000000 2b2743ce28a8184dbff0000000000000 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintm.f64.f64 d12, d12 53308a9fda85f0fb3340425a68fd2c9f fb4a5ec360d9f4541a40f23af99af89a fb4a5ec360d9f4540000000000000000 fb4a5ec360d9f4540000000000000000 fpscr=00000000
+vrintm.f64.f64 d12, d12 065d4418ea62c2ffabfa9908203bede6 9defdfe4b0056faa0e08956dfed9d66c 9defdfe4b0056faa0000000000000000 9defdfe4b0056faa0000000000000000 fpscr=00000000
+vrintn.f32.f32 s3, s15 3bbb0abc9313f2c4bc25a854ef1d206b 1f44fab0afde49ce867bd8f89b2829c1 000000009313f2c4bc25a854ef1d206b 1f44fab0afde49ce867bd8f89b2829c1 fpscr=00000000
+vrintn.f32.f32 s3, s15 047cb79b5b29fb6dbf7d855cf025e58f b1e3fabe27379ae16c26ff95208a9616 800000005b29fb6dbf7d855cf025e58f b1e3fabe27379ae16c26ff95208a9616 fpscr=00000000
+vrintn.f32.f32 s3, s15 140ae2d17cee2dee198120d06cfbdd41 98dacca69f7019312e737963fbb3585f 800000007cee2dee198120d06cfbdd41 98dacca69f7019312e737963fbb3585f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[1]
+vrintn.f32.f32 s3, s15 b628ed6c89fc6866597b04f9877d3d24 c1b217662acec7cdf6dc5fc72acec7cd c1b0000089fc6866597b04f9877d3d24 c1b217662acec7cdf6dc5fc72acec7cd fpscr=00000000
+vrintn.f32.f32 s3, s15 023ebbab56716c5612e410c6dba87fa4 4179130bbcfcff9b29a1794a7c97b6d7 4180000056716c5612e410c6dba87fa4 4179130bbcfcff9b29a1794a7c97b6d7 fpscr=00000000
+vrintn.f32.f32 s3, s15 569d44e9d4d61da03e2e81949fae8c61 2dd59c326d5050decb577b4ac62692e4 00000000d4d61da03e2e81949fae8c61 2dd59c326d5050decb577b4ac62692e4 fpscr=00000000
+vrintn.f32.f32 s3, s15 2c712f834fac0d33fad8e5b3f57864c2 a9bbae056f54e8b1bd522f2e71d83a61 800000004fac0d33fad8e5b3f57864c2 a9bbae056f54e8b1bd522f2e71d83a61 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintn.f32.f32 s3, s15 e01e3f9a12f68c8ee3c2918ad52372c5 044d163185c07fb525c6f48212e1905c 0000000012f68c8ee3c2918ad52372c5 044d163185c07fb525c6f48212e1905c fpscr=00000000
+vrintn.f32.f32 s3, s15 bd48df92a98a188b52ff01de0eef2d89 b817ab3521df91b26a205402325d4af0 80000000a98a188b52ff01de0eef2d89 b817ab3521df91b26a205402325d4af0 fpscr=00000000
+vrintn.f32.f32 s3, s15 5576a3de7c84caf38229db6929edfe74 ba72786f8c16318ad3590c2c46f1883a 800000007c84caf38229db6929edfe74 ba72786f8c16318ad3590c2c46f1883a fpscr=00000000
+vrintn.f32.f32 s3, s15 f6d4cc990203e1e252cc52dab4dd2d44 c0ba1e66d9b02dfa21e55b75e165b5ac c0c000000203e1e252cc52dab4dd2d44 c0ba1e66d9b02dfa21e55b75e165b5ac fpscr=00000000
+vrintn.f32.f32 s3, s15 e2eb14610f9796b5455289b1207f57a4 cd92e6ae2dabbe99e0bbbb68d96487d4 cd92e6ae0f9796b5455289b1207f57a4 cd92e6ae2dabbe99e0bbbb68d96487d4 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[1]
+vrintn.f32.f32 s3, s15 73188893731888931c327941fec37daa 256904f007a2c2f9f31a0847cdde2f75 00000000731888931c327941fec37daa 256904f007a2c2f9f31a0847cdde2f75 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintn.f32.f32 s3, s15 70ac1327bce46e31f26b70f6b37f18d5 4ac29f36683a7cd051be2ad30cc966a4 4ac29f36bce46e31f26b70f6b37f18d5 4ac29f36683a7cd051be2ad30cc966a4 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintn.f32.f32 s3, s15 c590c1e22d8b04ba1927713ec590c1e2 674cc96b17dcea2b0545384bd16ee333 674cc96b2d8b04ba1927713ec590c1e2 674cc96b17dcea2b0545384bd16ee333 fpscr=00000000
+randV128: 11264 calls, 11622 iters
+vrintn.f32.f32 s3, s15 27bc711951033c1c28fc95f1e558d08f 39390c163d77694c752ec1d6a6cbf909 0000000051033c1c28fc95f1e558d08f 39390c163d77694c752ec1d6a6cbf909 fpscr=00000000
+vrintn.f32.f32 s3, s15 354151c547676954d67933a377dfbc46 98cdc30812d5f969c7211df220c234b7 8000000047676954d67933a377dfbc46 98cdc30812d5f969c7211df220c234b7 fpscr=00000000
+vrintn.f32.f32 s3, s15 78a5b01c6370000fac43fc4a04cad8fe a9e980d6e77fabedc3ee31ce622b433c 800000006370000fac43fc4a04cad8fe a9e980d6e77fabedc3ee31ce622b433c fpscr=00000000
+vrintn.f32.f32 s3, s15 763e0cda2f739fb035e6f9ba37b00a5b 9b6c300d16a4d48e948d7213ad661125 800000002f739fb035e6f9ba37b00a5b 9b6c300d16a4d48e948d7213ad661125 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintn.f32.f32 s3, s15 1bfb5051e06b41aac9fe65ab8b041b25 7159f6a067518ad6c879fe94c879fe94 7159f6a0e06b41aac9fe65ab8b041b25 7159f6a067518ad6c879fe94c879fe94 fpscr=00000000
+vrintn.f32.f32 s3, s15 ca893d1fa2aaef4e2e634a2cba4624a7 e53b25cd5d34d0967395bdee0fdb1f48 e53b25cda2aaef4e2e634a2cba4624a7 e53b25cd5d34d0967395bdee0fdb1f48 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintn.f32.f32 s3, s15 0f919ec40f919ec4ca7dc06b9e0893e0 e072944b32e3ee4fa4800130600ad196 e072944b0f919ec4ca7dc06b9e0893e0 e072944b32e3ee4fa4800130600ad196 fpscr=00000000
+vrintn.f32.f32 s3, s15 94708189d01a1d38533c4278dcc9b408 818022347470296511f704c959c79de4 80000000d01a1d38533c4278dcc9b408 818022347470296511f704c959c79de4 fpscr=00000000
+vrintn.f32.f32 s3, s15 8390329113b137bed46119bc4f7b459c 747ef5b674a0dac80b7da2538ddd888a 747ef5b613b137bed46119bc4f7b459c 747ef5b674a0dac80b7da2538ddd888a fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintn.f32.f32 s3, s15 75d972e668f398fe68f398fe1053d264 300a2b4cb3552c060b75cd7591cdab7f 0000000068f398fe68f398fe1053d264 300a2b4cb3552c060b75cd7591cdab7f fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintn.f32.f32 s3, s15 e9f638c148bd2fd99e57617fd5fc1804 9de38bc3937e12646626e5c24f585386 8000000048bd2fd99e57617fd5fc1804 9de38bc3937e12646626e5c24f585386 fpscr=00000000
+vrintn.f32.f32 s3, s15 dca307e9c7c2d31bd49fc520dc6a3a63 fccee7c47de88b23f583715a95eaada1 fccee7c4c7c2d31bd49fc520dc6a3a63 fccee7c47de88b23f583715a95eaada1 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintn.f32.f32 s3, s15 bce8a5a71a986a781a986a7834ffd2e6 0e94ed35e64310825b1d5dd99a49b07e 000000001a986a781a986a7834ffd2e6 0e94ed35e64310825b1d5dd99a49b07e fpscr=00000000
+vrintn.f32.f32 s3, s15 351c941bc9ecbb771470aef448c45d15 81fda2cac65dbc7a91cfa1cdf6baa4b3 80000000c9ecbb771470aef448c45d15 81fda2cac65dbc7a91cfa1cdf6baa4b3 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintn.f32.f32 s3, s15 7ab35798cdfe25b21d81c7bbcdfe25b2 0d76f1b25a1f501bb3c471e6dfc4c9dd 00000000cdfe25b21d81c7bbcdfe25b2 0d76f1b25a1f501bb3c471e6dfc4c9dd fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintn.f32.f32 s3, s15 f3ee4dbca71e3eeaa347de8990305931 320b75d6786f890a993136f74e116e0e 00000000a71e3eeaa347de8990305931 320b75d6786f890a993136f74e116e0e fpscr=00000000
+vrintn.f32.f32 s3, s15 71d2921db69ee75fff05f76be7a87897 492636a672cfff2bc09c9717bffef7c3 492636a0b69ee75fff05f76be7a87897 492636a672cfff2bc09c9717bffef7c3 fpscr=00000000
+vrintn.f32.f32 s3, s15 6ed5b6cd699f25debffb807cd24c5d60 663854925e606568ef62d8e88fbbcd4e 66385492699f25debffb807cd24c5d60 663854925e606568ef62d8e88fbbcd4e fpscr=00000000
+vrintn.f32.f32 s3, s15 1477f4873a93ea3dbe15aa12072b9da5 6d19a35be7aec8318330559637ed1c22 6d19a35b3a93ea3dbe15aa12072b9da5 6d19a35be7aec8318330559637ed1c22 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintn.f32.f32 s3, s15 502bb83b87f7e9d8428f3f4552950319 597512dd7d1688af7f1814e91876660f 597512dd87f7e9d8428f3f4552950319 597512dd7d1688af7f1814e91876660f fpscr=00000000
+vrintn.f32.f32 s3, s15 9a7d12f9b2a56b668cd7f4ac0d48662c 9356b1adb92e2ff1363b0944b9a98e55 80000000b2a56b668cd7f4ac0d48662c 9356b1adb92e2ff1363b0944b9a98e55 fpscr=00000000
+vrintn.f32.f32 s3, s15 2b7347b12413e46d608b1e2c7c783af7 32b42a599271fa2ff44a47bc7ead7284 000000002413e46d608b1e2c7c783af7 32b42a599271fa2ff44a47bc7ead7284 fpscr=00000000
+vrintn.f32.f32 s3, s15 1517b684138eccc3673acb22f9bc48dd 8cd5b3a791816ad7213dabff89c802b8 80000000138eccc3673acb22f9bc48dd 8cd5b3a791816ad7213dabff89c802b8 fpscr=00000000
+vrintn.f32.f32 s3, s15 8abfc3f95159bade423fc52c4251a979 bfb1d3931382a362750d98809f9925fd bf8000005159bade423fc52c4251a979 bfb1d3931382a362750d98809f9925fd fpscr=00000000
+vrintn.f32.f32 s3, s15 67c7093f6fdebfeb4397700598e7124c ff64770cbc4ac2fd75db67073e381535 ff64770c6fdebfeb4397700598e7124c ff64770cbc4ac2fd75db67073e381535 fpscr=00000000
+vrintn.f32.f32 s3, s15 e13fd6e986f2021f56c08a80c931b85a 335c13eda7b2aba44a5dccf012c25f77 0000000086f2021f56c08a80c931b85a 335c13eda7b2aba44a5dccf012c25f77 fpscr=00000000
+vrintn.f32.f32 s3, s15 c4407e98c2f7a829ec5f85f3a1e671e1 4a101514fb7d0b4365b1ba2a8f39a25a 4a101514c2f7a829ec5f85f3a1e671e1 4a101514fb7d0b4365b1ba2a8f39a25a fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[0]
+vrintn.f32.f32 s3, s15 04bfd4fd1d55b8d77ed8c20b6e766237 64425adeb38bd599eaba27f5a60d7821 64425ade1d55b8d77ed8c20b6e766237 64425adeb38bd599eaba27f5a60d7821 fpscr=00000000
+vrintn.f32.f32 s3, s15 32b609f12dbe1ecdf29105bf59b60ff7 595ccc96befc3a1035a970b4e1915f56 595ccc962dbe1ecdf29105bf59b60ff7 595ccc96befc3a1035a970b4e1915f56 fpscr=00000000
+vrintn.f32.f32 s3, s15 b690a641c0236b16c8406d6dbf7ce573 95f0ecfe85617ac74b1758f5923b1c73 80000000c0236b16c8406d6dbf7ce573 95f0ecfe85617ac74b1758f5923b1c73 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintn.f32.f32 s3, s15 0f8c5e79ed0a9bd32c80bcfd1b3716a9 cb47193a3e0ac4ea2234de83c0b0ee82 cb47193aed0a9bd32c80bcfd1b3716a9 cb47193a3e0ac4ea2234de83c0b0ee82 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintn.f32.f32 s3, s15 0ed66d7aa7613d605f36c36d5cbb3213 8c2e59a25fd3fce78c2e59a2085b4545 80000000a7613d605f36c36d5cbb3213 8c2e59a25fd3fce78c2e59a2085b4545 fpscr=00000000
+vrintn.f32.f32 s3, s15 d00e37324e6716cf647a3bdac713a12c 4af93d5abb99590cba412ccee49a765c 4af93d5a4e6716cf647a3bdac713a12c 4af93d5abb99590cba412ccee49a765c fpscr=00000000
+vrintn.f32.f32 s3, s15 4238a21f74365d4a2f2c7b0d75501e11 e24cf597695e7c7fd4a3f183905be68f e24cf59774365d4a2f2c7b0d75501e11 e24cf597695e7c7fd4a3f183905be68f fpscr=00000000
+vrintn.f32.f32 s3, s15 a8eef856be31e18b6edeaeecc81d1def cc8913204bd0bbf02f505446d01d4b2f cc891320be31e18b6edeaeecc81d1def cc8913204bd0bbf02f505446d01d4b2f fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrinta.f32.f32 s6, s18 e7c9ef1206a2e7a1edc1f927edc1f927 c033c5300afb79aea2fce2bfb019feb0 e7c9ef1200000000edc1f927edc1f927 c033c5300afb79aea2fce2bfb019feb0 fpscr=00000000
+vrinta.f32.f32 s6, s18 f3365e503cefe0cba57d56653d22b149 27ad2df4d02346a8cba93afe57b708fb f3365e50d02346a8a57d56653d22b149 27ad2df4d02346a8cba93afe57b708fb fpscr=00000000
+vrinta.f32.f32 s6, s18 311c62a85d363a342cd2eaaf2f847895 53b92cb516d7067eb1cf20e907247057 311c62a8000000002cd2eaaf2f847895 53b92cb516d7067eb1cf20e907247057 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrinta.f32.f32 s6, s18 4b7a9ab04a7fd56c3f17e3d73f17e3d7 d80b8de0e308375edbc539feec6adf4f 4b7a9ab0e308375e3f17e3d73f17e3d7 d80b8de0e308375edbc539feec6adf4f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrinta.f32.f32 s6, s18 e70217d0c8c6b0d6faa5641b09e1c0c7 1bc60591c528546f1b147251e5b940ff e70217d0c5285000faa5641b09e1c0c7 1bc60591c528546f1b147251e5b940ff fpscr=00000000
+vrinta.f32.f32 s6, s18 9aa0004c922785ba99a79174398a1992 2a3eb21993f7cb8e52c6272118ff92f1 9aa0004c8000000099a79174398a1992 2a3eb21993f7cb8e52c6272118ff92f1 fpscr=00000000
+vrinta.f32.f32 s6, s18 746abdb920f937555a6792a563a5dbc4 6685a79afdf40d0cb39e66c2d8355055 746abdb9fdf40d0c5a6792a563a5dbc4 6685a79afdf40d0cb39e66c2d8355055 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrinta.f32.f32 s6, s18 d4ae6a74d4da14dea92d026da1a49f70 c1a525c2475670b3e4867aac475670b3 d4ae6a7447567100a92d026da1a49f70 c1a525c2475670b3e4867aac475670b3 fpscr=00000000
+vrinta.f32.f32 s6, s18 54d95966d097504e0323c1927ec25601 67225d3ee63b8182a19fc2388ac9684f 54d95966e63b81820323c1927ec25601 67225d3ee63b8182a19fc2388ac9684f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrinta.f32.f32 s6, s18 1bed6affbe0a74ba1bed6aff238db87b 252f71ab0845c87b8623d742c7f11362 1bed6aff000000001bed6aff238db87b 252f71ab0845c87b8623d742c7f11362 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrinta.f32.f32 s6, s18 b0f64d65afbb186992d925edafbb1869 5706d227c1b8a44d0f93afb8d7a898ed b0f64d65c1b8000092d925edafbb1869 5706d227c1b8a44d0f93afb8d7a898ed fpscr=00000000
+vrinta.f32.f32 s6, s18 0974fd759b571d2ac12c7167b331f8d4 5f5b390b91cd5eff637449fc2795de67 0974fd7580000000c12c7167b331f8d4 5f5b390b91cd5eff637449fc2795de67 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrinta.f32.f32 s6, s18 09c92ef67e7d2c19a1fa6d7f2ff1f49c 658c4cee8e1e3f430933aab8dca8905e 09c92ef680000000a1fa6d7f2ff1f49c 658c4cee8e1e3f430933aab8dca8905e fpscr=00000000
+vrinta.f32.f32 s6, s18 58651a9ccbff714e9159e16be24368ed 7f062b07f8aa248b9405348d68eb6a32 58651a9cf8aa248b9159e16be24368ed 7f062b07f8aa248b9405348d68eb6a32 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrinta.f32.f32 s6, s18 6e6141a0f3ec6d0136de6b65d5b06a86 12670d832f7431ad9a37c4959a37c495 6e6141a00000000036de6b65d5b06a86 12670d832f7431ad9a37c4959a37c495 fpscr=00000000
+vrinta.f32.f32 s6, s18 77903ce9ab1543d5a54717752f0cccdb 54877799ca7cb669c04d34c62c538876 77903ce9ca7cb668a54717752f0cccdb 54877799ca7cb669c04d34c62c538876 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrinta.f32.f32 s6, s18 16ed2ec84304cccd1f5ca59d2c0d3500 856d3f6a022bf28cd8a027a0a0ca9529 16ed2ec8000000001f5ca59d2c0d3500 856d3f6a022bf28cd8a027a0a0ca9529 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrinta.f32.f32 s6, s18 4fa8712da26c9d394fa8712dc008852a 39dd21ecf37c9190f8b88400894eb692 4fa8712df37c91904fa8712dc008852a 39dd21ecf37c9190f8b88400894eb692 fpscr=00000000
+vrinta.f32.f32 s6, s18 cf248b8ce6c2dcc409ae12e6c8cdb9e7 b9c4390ba0a3ac29d6601209ca5fa8d7 cf248b8c8000000009ae12e6c8cdb9e7 b9c4390ba0a3ac29d6601209ca5fa8d7 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrinta.f32.f32 s6, s18 420ccf9f8d9b57f1c9aca1c98b2659c5 eac6c25a5ef501b7314102c3fd5e69d1 420ccf9f5ef501b7c9aca1c98b2659c5 eac6c25a5ef501b7314102c3fd5e69d1 fpscr=00000000
+vrinta.f32.f32 s6, s18 978499c855f5c809400fc8ee697bd589 b6a3be415e415051f79f6c6ed27b4b8d 978499c85e415051400fc8ee697bd589 b6a3be415e415051f79f6c6ed27b4b8d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrinta.f32.f32 s6, s18 38766e5285918d982717cd363b11a196 397603ddad6a0d77b5ccc665db2bad5b 38766e52800000002717cd363b11a196 397603ddad6a0d77b5ccc665db2bad5b fpscr=00000000
+vrinta.f32.f32 s6, s18 4949e1f54be601ad0be23aa2ea8a7dcc 3984146c6975a6a7baf10f4e4761e0a1 4949e1f56975a6a70be23aa2ea8a7dcc 3984146c6975a6a7baf10f4e4761e0a1 fpscr=00000000
+vrinta.f32.f32 s6, s18 6796a17a983aa3a5e0763fd2d3f0d19c 872e4abad84b4f4b56790b27039ad403 6796a17ad84b4f4be0763fd2d3f0d19c 872e4abad84b4f4b56790b27039ad403 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrinta.f32.f32 s6, s18 51b2dbe15e8f55a799f88c4cc8bdf748 b0b7652a155373964bfb6fc84bfb6fc8 51b2dbe10000000099f88c4cc8bdf748 b0b7652a155373964bfb6fc84bfb6fc8 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrinta.f32.f32 s6, s18 c57b8523596df50ab5a2242b9e302be4 a84c962b724772ba2bf0be00d700f275 c57b8523724772bab5a2242b9e302be4 a84c962b724772ba2bf0be00d700f275 fpscr=00000000
+vrinta.f32.f32 s6, s18 15d7d62e99e020744d96cc4f683c7285 b15d3afd2e638cca297968a0f5c3e111 15d7d62e000000004d96cc4f683c7285 b15d3afd2e638cca297968a0f5c3e111 fpscr=00000000
+vrinta.f32.f32 s6, s18 b2e96ddd72d2f95e47f1badac1784f7a 587f4ff25cbfd3aee2368dff822b6503 b2e96ddd5cbfd3ae47f1badac1784f7a 587f4ff25cbfd3aee2368dff822b6503 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrinta.f32.f32 s6, s18 66a2e41566a2e415f72849e35e67740f b3582612657a0f0e43c9c41a99005f85 66a2e415657a0f0ef72849e35e67740f b3582612657a0f0e43c9c41a99005f85 fpscr=00000000
+randV128: 11520 calls, 11887 iters
+vrinta.f32.f32 s6, s18 98f367908a3368fde3b0eb2fe6f062b6 c4e9d1ec65693546326b1a752ea5b277 98f3679065693546e3b0eb2fe6f062b6 c4e9d1ec65693546326b1a752ea5b277 fpscr=00000000
+vrinta.f32.f32 s6, s18 ceaa101165ef86c425a7ffb8a0a188f2 8577540f1018d63d8cfc9221ab4ecd40 ceaa10110000000025a7ffb8a0a188f2 8577540f1018d63d8cfc9221ab4ecd40 fpscr=00000000
+vrinta.f32.f32 s6, s18 28d4c2b24777aa293d2450b5e5954c21 6a5f001de615d074f64cbb1994cac160 28d4c2b2e615d0743d2450b5e5954c21 6a5f001de615d074f64cbb1994cac160 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[1]
+vrinta.f32.f32 s6, s18 1b8ba9c5814f90e9c5688edbf0fd9108 5744740643bc2157057f3f5e6d9aaa13 1b8ba9c543bc0000c5688edbf0fd9108 5744740643bc2157057f3f5e6d9aaa13 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrinta.f32.f32 s6, s18 d43ca1564355a24135c2d073b5bffc32 3764948a35c9faff35c9faffe2f6e6bd d43ca1560000000035c2d073b5bffc32 3764948a35c9faff35c9faffe2f6e6bd fpscr=00000000
+vrinta.f32.f32 s6, s18 06b9b519e5005895bc68e244909c5c16 06178afb6605189f6263587969e9e05f 06b9b5196605189fbc68e244909c5c16 06178afb6605189f6263587969e9e05f fpscr=00000000
+vrinta.f32.f32 s6, s18 70e9352b2b04225d40313ec412b3be90 5bee5c24b85a0bf6e8559f65db1c1060 70e9352b8000000040313ec412b3be90 5bee5c24b85a0bf6e8559f65db1c1060 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrinta.f32.f32 s6, s18 a24d9753a4edb016bdef2ba44f91866a 616b90b2616b90b28808c62f17759eee a24d9753616b90b2bdef2ba44f91866a 616b90b2616b90b28808c62f17759eee fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrinta.f32.f32 s6, s18 a2bccd012b33021b83896e64a2f2f636 0a32ebb18924f5c29dd89fa55df5adf8 a2bccd018000000083896e64a2f2f636 0a32ebb18924f5c29dd89fa55df5adf8 fpscr=00000000
+vrinta.f32.f32 s6, s18 448aa73372862d6dc2e9c3c0f1e8eb3f 88697a9e03e3f1f6be48d8d5b6200032 448aa73300000000c2e9c3c0f1e8eb3f 88697a9e03e3f1f6be48d8d5b6200032 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[1]
+vrinta.f32.f32 s6, s18 34b494c31bc7ef7b5865b08934b494c3 e2efcbce9919f1eae2efcbcefa6a9454 34b494c3800000005865b08934b494c3 e2efcbce9919f1eae2efcbcefa6a9454 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrinta.f32.f32 s6, s18 edcb7d866ecdb50c6c41704902e40b74 03bea473b2700e033464d5c6e64bca7b edcb7d86800000006c41704902e40b74 03bea473b2700e033464d5c6e64bca7b fpscr=00000000
+vrinta.f32.f32 s6, s18 6d010871fdeb7a65cef4e2ca4bb012cb 224ac38ae1918fe43b0aa92d0c6f805f 6d010871e1918fe4cef4e2ca4bb012cb 224ac38ae1918fe43b0aa92d0c6f805f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrinta.f32.f32 s6, s18 85a9921354b7077da15e378a54b7077d 6aa99b4becab5c4e9be29ceed564be0e 85a99213ecab5c4ea15e378a54b7077d 6aa99b4becab5c4e9be29ceed564be0e fpscr=00000000
+vrinta.f32.f32 s6, s18 f68e4f03fb8f2bab4eb7b28a2b691b3a 8f5c440dc058b7bf667f5e30add04491 f68e4f03c04000004eb7b28a2b691b3a 8f5c440dc058b7bf667f5e30add04491 fpscr=00000000
+vrinta.f32.f32 s6, s18 739cd2cfa8e00964a2de85ca2a8a1d43 1e77f1a9d554d08ceb087e3d18001e35 739cd2cfd554d08ca2de85ca2a8a1d43 1e77f1a9d554d08ceb087e3d18001e35 fpscr=00000000
+vrinta.f32.f32 s6, s18 8b7ac01f2b821296d9929c429240f14a 534bf150dd23063f4e64b6bccc19d025 8b7ac01fdd23063fd9929c429240f14a 534bf150dd23063f4e64b6bccc19d025 fpscr=00000000
+vrinta.f32.f32 s6, s18 ec8cd7a582522e4058d7b0b9e985677f 66961019c6bc24bf0f5d028cdaebd4fb ec8cd7a5c6bc240058d7b0b9e985677f 66961019c6bc24bf0f5d028cdaebd4fb fpscr=00000000
+vrinta.f32.f32 s6, s18 4a0bac30e094b43f4588e1795b7b0c18 0436654354e25637c990ac4a9284c4ef 4a0bac3054e256374588e1795b7b0c18 0436654354e25637c990ac4a9284c4ef fpscr=00000000
+vrinta.f32.f32 s6, s18 f92ec8b0e03b2c7356c61b9133fb39ad ab41fedea0d9ee5ecfc73e383c286951 f92ec8b08000000056c61b9133fb39ad ab41fedea0d9ee5ecfc73e383c286951 fpscr=00000000
+vrinta.f32.f32 s6, s18 e33b350f1b1e78b80d44ddebad036d7a ee7a73d27a7e1b1aa9ab4882b8a5a97b e33b350f7a7e1b1a0d44ddebad036d7a ee7a73d27a7e1b1aa9ab4882b8a5a97b fpscr=00000000
+vrintp.f32.f32 s9, s21 dd7661f1210155c84a755e5532061f7a 8f284e41a0b9728872df17e5fd0d530f dd7661f1210155c872df17e532061f7a 8f284e41a0b9728872df17e5fd0d530f fpscr=00000000
+vrintp.f32.f32 s9, s21 5eef6454ce8749f4439d1253e713da65 7e4b5d51e3575a6119723db374c6d29e 5eef6454ce8749f43f800000e713da65 7e4b5d51e3575a6119723db374c6d29e fpscr=00000000
+vrintp.f32.f32 s9, s21 932ca509fefce1c7d9bb93e6a8edcb8f b631df51203e61c07cb7013b3a07b6b2 932ca509fefce1c77cb7013ba8edcb8f b631df51203e61c07cb7013b3a07b6b2 fpscr=00000000
+vrintp.f32.f32 s9, s21 d8bbe517a5045b814e59e7285df1a0a8 fd70933b220362496678ad8e3ba8232f d8bbe517a5045b816678ad8e5df1a0a8 fd70933b220362496678ad8e3ba8232f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintp.f32.f32 s9, s21 8aa09ef58aa09ef55c3c1fc5ade8d456 d7518138a2a25be29baf7093bda8305a 8aa09ef58aa09ef580000000ade8d456 d7518138a2a25be29baf7093bda8305a fpscr=00000000
+vrintp.f32.f32 s9, s21 cd5e43a2cdabbe58e74eaaed696118b2 7ba3530a73ef880f9499b9e7e9ef7f40 cd5e43a2cdabbe5880000000696118b2 7ba3530a73ef880f9499b9e7e9ef7f40 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[0]
+vrintp.f32.f32 s9, s21 150fcccf530f2874150fcccf1822f7df aa68eb50b4b851cb8c981b47c10a3344 150fcccf530f2874800000001822f7df aa68eb50b4b851cb8c981b47c10a3344 fpscr=00000000
+vrintp.f32.f32 s9, s21 03211377023a745fc44e0973e2bd1b59 404b438a209b2dcc64428ea5d493a6a6 03211377023a745f64428ea5e2bd1b59 404b438a209b2dcc64428ea5d493a6a6 fpscr=00000000
+vrintp.f32.f32 s9, s21 2d2efbe332d8b4acb5ff3e78bdd9d99a 65ebc080ecaa8f2d38ef6974df434a68 2d2efbe332d8b4ac3f800000bdd9d99a 65ebc080ecaa8f2d38ef6974df434a68 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintp.f32.f32 s9, s21 344bdf1079837789b546cf313ec5b29c e6152a4087a63851e6152a407850be3f 344bdf1079837789e6152a403ec5b29c e6152a4087a63851e6152a407850be3f fpscr=00000000
+vrintp.f32.f32 s9, s21 a541a08d0c5cf6eeeb885706fa856ccc 56539287a37c8749b4b6de2bf5a08f6c a541a08d0c5cf6ee80000000fa856ccc 56539287a37c8749b4b6de2bf5a08f6c fpscr=00000000
+vrintp.f32.f32 s9, s21 4f468fcf3af2be35bc1e67956cbda616 b0c5040af390a4fb915049197a0fc95a 4f468fcf3af2be35800000006cbda616 b0c5040af390a4fb915049197a0fc95a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintp.f32.f32 s9, s21 b5a813be3c6c5e98e1eb89173062689f c803af3dc80ddcd697d5d655d05fe531 b5a813be3c6c5e98800000003062689f c803af3dc80ddcd697d5d655d05fe531 fpscr=00000000
+vrintp.f32.f32 s9, s21 75c089bc705a88db368b4860b831788d 08a015d99e0bc549d9a35596303540a9 75c089bc705a88dbd9a35596b831788d 08a015d99e0bc549d9a35596303540a9 fpscr=00000000
+vrintp.f32.f32 s9, s21 f350ed38fdbc9cf28edd413bdb3fd042 8fa2a9e858e80287744da56333a9baaf f350ed38fdbc9cf2744da563db3fd042 8fa2a9e858e80287744da56333a9baaf fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintp.f32.f32 s9, s21 73ba1d7cef1df09e08ccbb536ffa5c3e 6bee80cd9b85f7da4020e4d71539dcc9 73ba1d7cef1df09e404000006ffa5c3e 6bee80cd9b85f7da4020e4d71539dcc9 fpscr=00000000
+vrintp.f32.f32 s9, s21 2861304cdb5e623341b8898513848b7a 52fc7b7d7ac5096ddb0dce5d9983a2a8 2861304cdb5e6233db0dce5d13848b7a 52fc7b7d7ac5096ddb0dce5d9983a2a8 fpscr=00000000
+vrintp.f32.f32 s9, s21 445ce00bdb3791d3f7efd5067a832269 4f7329b39116dfaf3b033c48c77b088d 445ce00bdb3791d33f8000007a832269 4f7329b39116dfaf3b033c48c77b088d fpscr=00000000
+vrintp.f32.f32 s9, s21 b6aa190551c8c5279d092605ab45e5e0 68c93aac46ce24f7fca6f71295aa2b45 b6aa190551c8c527fca6f712ab45e5e0 68c93aac46ce24f7fca6f71295aa2b45 fpscr=00000000
+vrintp.f32.f32 s9, s21 bdf3b85110095b66fda2bc57a6cbdc80 fcde961b5313c4b9949fe1e9d3616c58 bdf3b85110095b6680000000a6cbdc80 fcde961b5313c4b9949fe1e9d3616c58 fpscr=00000000
+vrintp.f32.f32 s9, s21 e480b556bb0e92dadf5ad1ad76b4294e ca17f543bb411a69115337606b72831a e480b556bb0e92da3f80000076b4294e ca17f543bb411a69115337606b72831a fpscr=00000000
+vrintp.f32.f32 s9, s21 d4e4becf36a08b5ad4a031caee961a93 645992fe93eaf368cbff00050b5a6585 d4e4becf36a08b5acbff0005ee961a93 645992fe93eaf368cbff00050b5a6585 fpscr=00000000
+vrintp.f32.f32 s9, s21 75aef41b3b5aa6ef5d094c91160f8240 5ca27e8ff621e031a0b191d5911cd3b0 75aef41b3b5aa6ef80000000160f8240 5ca27e8ff621e031a0b191d5911cd3b0 fpscr=00000000
+vrintp.f32.f32 s9, s21 b7ef6e6af06a08bf5210d7fadc2da588 720f2175906876870c4344f3acf4aea4 b7ef6e6af06a08bf3f800000dc2da588 720f2175906876870c4344f3acf4aea4 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[1]
+vrintp.f32.f32 s9, s21 93aab306afb41f95abf9a070afb41f95 1f8d8f2607e9be421f8d8f26d9fc079f 93aab306afb41f953f800000afb41f95 1f8d8f2607e9be421f8d8f26d9fc079f fpscr=00000000
+vrintp.f32.f32 s9, s21 bc07cd4615cda43e6ee6e275e683a392 eee60eb932dd01457370523c7aeb40f1 bc07cd4615cda43e7370523ce683a392 eee60eb932dd01457370523c7aeb40f1 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintp.f32.f32 s9, s21 eae17f6b85b1538585b1538565c113dd e7a1357242b0e8e21bd5bd2e3b551211 eae17f6b85b153853f80000065c113dd e7a1357242b0e8e21bd5bd2e3b551211 fpscr=00000000
+vrintp.f32.f32 s9, s21 13397f35d2f05695c5edadc31f641809 3d624b3e14ab1e6b4a35a6584c7bc8f5 13397f35d2f056954a35a6581f641809 3d624b3e14ab1e6b4a35a6584c7bc8f5 fpscr=00000000
+vrintp.f32.f32 s9, s21 6e2b1efb02e3e2e1c7cb8a47defe8a11 5c5da2ed4f0ff5d957e02b43e105f47f 6e2b1efb02e3e2e157e02b43defe8a11 5c5da2ed4f0ff5d957e02b43e105f47f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vrintp.f32.f32 s9, s21 fa41f90bd66cfc55ba851b400d1ebeda 6250d6e75fae363b30f84cab1b96263f fa41f90bd66cfc553f8000000d1ebeda 6250d6e75fae363b30f84cab1b96263f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[0]
+vrintp.f32.f32 s9, s21 c44682d550c18858b85fd82b50c18858 8cbe6a27f6cd565c787fb490787fb490 c44682d550c18858787fb49050c18858 8cbe6a27f6cd565c787fb490787fb490 fpscr=00000000
+vrintp.f32.f32 s9, s21 ab76f64aaaa7b2cd02802c15b173def9 dbaf866aba6aee485af9f30b32f9a36b ab76f64aaaa7b2cd5af9f30bb173def9 dbaf866aba6aee485af9f30b32f9a36b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintp.f32.f32 s9, s21 db6845ba47afad015c4d4c6812da09ba c8e75cfc3111a1f0c8e75cfc94f4c814 db6845ba47afad01c8e75ce012da09ba c8e75cfc3111a1f0c8e75cfc94f4c814 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintp.f32.f32 s9, s21 20f97b5549e061275560010503b90610 91ade7b987a847de5c082de991ade7b9 20f97b5549e061275c082de903b90610 91ade7b987a847de5c082de991ade7b9 fpscr=00000000
+vrintp.f32.f32 s9, s21 9835015379582e6aeb790973ecc0f915 0b12844168fa172c9499456adcb16ec1 9835015379582e6a80000000ecc0f915 0b12844168fa172c9499456adcb16ec1 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintp.f32.f32 s9, s21 c072879b7d6c4d77c9d17ec5a616b402 ff4667da5a9c338a9655f9db545e32af c072879b7d6c4d7780000000a616b402 ff4667da5a9c338a9655f9db545e32af fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vrintp.f32.f32 s9, s21 43582530d8c46b48bbccf81743582530 759c1ec003333a41e0cc4ca14d207518 43582530d8c46b48e0cc4ca143582530 759c1ec003333a41e0cc4ca14d207518 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[3]
+vrintp.f32.f32 s9, s21 9471db94bd08140ddb5aea303fd83a45 567bfb5dc325e1fc89f328fc89f328fc 9471db94bd08140d800000003fd83a45 567bfb5dc325e1fc89f328fc89f328fc fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[0]
+vrintp.f32.f32 s9, s21 196518081965180834074d37c20af3f1 4847669dd875a6c8b190a5c32f12c9de 196518081965180880000000c20af3f1 4847669dd875a6c8b190a5c32f12c9de fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintp.f32.f32 s9, s21 a4f119ffefc9cbf94088331689e7e94c 7b795c93a184d944dd0fb55350d546cb a4f119ffefc9cbf9dd0fb55389e7e94c 7b795c93a184d944dd0fb55350d546cb fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintp.f32.f32 s9, s21 62468851d95e7e84d95e7e8497081db2 b73a5378629cf7d1f64d1ea98aa130f1 62468851d95e7e84f64d1ea997081db2 b73a5378629cf7d1f64d1ea98aa130f1 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+vrintp.f32.f32 s9, s21 cfb0aeecc3f4c6947d6372cbc3f4c694 968c9d940de060bb0de060bb2822a70c cfb0aeecc3f4c6943f800000c3f4c694 968c9d940de060bb0de060bb2822a70c fpscr=00000000
+vrintp.f32.f32 s9, s21 17b15a5bf2ee28136e0c6517245c4e67 06ffd511230d17a368df696f4993ac35 17b15a5bf2ee281368df696f245c4e67 06ffd511230d17a368df696f4993ac35 fpscr=00000000
+randV128: 11776 calls, 12159 iters
+vrintp.f32.f32 s9, s21 2d10d5621071d7f36033a881df22770b 75797043bbcfed77071c1a32d213594f 2d10d5621071d7f33f800000df22770b 75797043bbcfed77071c1a32d213594f fpscr=00000000
+vrintp.f32.f32 s9, s21 905c40d9391822260747fb4fb5e12834 ee027c1df8029d42cab494db67aa7d99 905c40d939182226cab494dab5e12834 ee027c1df8029d42cab494db67aa7d99 fpscr=00000000
+vrintp.f32.f32 s9, s21 92b8040baea21a9474f64725130eaa9e f1091f21ecccc7fe8f6b77f55bd5676d 92b8040baea21a9480000000130eaa9e f1091f21ecccc7fe8f6b77f55bd5676d fpscr=00000000
+vrintp.f32.f32 s9, s21 c1fb3113ecb42cd0e4630236c7b54d4d 499724b5d633d0eab5422065b367888e c1fb3113ecb42cd080000000c7b54d4d 499724b5d633d0eab5422065b367888e fpscr=00000000
+vrintp.f32.f32 s9, s21 d35d5c58e0dc9b511ae74d6670a61662 3a22a43f2cc5481489e850a52546126e d35d5c58e0dc9b518000000070a61662 3a22a43f2cc5481489e850a52546126e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintp.f32.f32 s9, s21 b8fdfa018f553ef1106b8d66fbb1472c 4a2543a24a2543a2c23d31726a0aff30 b8fdfa018f553ef1c23c0000fbb1472c 4a2543a24a2543a2c23d31726a0aff30 fpscr=00000000
+vrintp.f32.f32 s9, s21 de40afda773d6c807842e8eb7ad016c6 1583992e7989af8e322359b0550ffff2 de40afda773d6c803f8000007ad016c6 1583992e7989af8e322359b0550ffff2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintm.f32.f32 s12, s12 c1350f8d8ad4ab38106b382a66401ad8 353fd41d99b4fd24aac0d79a353fd41d 353fd41d99b4fd24aac0d79a00000000 353fd41d99b4fd24aac0d79a00000000 fpscr=00000000
+vrintm.f32.f32 s12, s12 0f38a18125d81c47d8811f4e46e4b5e8 033542abcb1c6217d98ec9075f3281bb 033542abcb1c6217d98ec9075f3281bb 033542abcb1c6217d98ec9075f3281bb fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintm.f32.f32 s12, s12 365e5a3fcd9c29bfa912fe95a912fe95 607f64f2fcedeb602560bd29d9ced4c3 607f64f2fcedeb602560bd29d9ced4c3 607f64f2fcedeb602560bd29d9ced4c3 fpscr=00000000
+vrintm.f32.f32 s12, s12 a5035cae929b11a27c3eb4c0b7ef87c5 3bba4a932b31bf4ef04413aca052b809 3bba4a932b31bf4ef04413acbf800000 3bba4a932b31bf4ef04413acbf800000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintm.f32.f32 s12, s12 621c9b9e7cc53b237cc53b230344a304 485461e1edb83a04103d9add4fd803b7 485461e1edb83a04103d9add4fd803b7 485461e1edb83a04103d9add4fd803b7 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintm.f32.f32 s12, s12 729425a026e0714ac1ac337a3ec5254c 440f31524d952ad29cad24e6440f3152 440f31524d952ad29cad24e6440f0000 440f31524d952ad29cad24e6440f0000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintm.f32.f32 s12, s12 3f9dc9e6a28ffa0470c615645da159ad 16932442ed45cc1eb0e74a8f83d98c8d 16932442ed45cc1eb0e74a8fbf800000 16932442ed45cc1eb0e74a8fbf800000 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintm.f32.f32 s12, s12 22cdd51e3836f1256a827c0052b276ac 84fea6491e15c1481e15c148c174c4ef 84fea6491e15c1481e15c148c1800000 84fea6491e15c1481e15c148c1800000 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintm.f32.f32 s12, s12 fd83f1cf4ba92d67a7b18e1fda58c843 3c87600fd49f1ff2766087d92f068ab0 3c87600fd49f1ff2766087d900000000 3c87600fd49f1ff2766087d900000000 fpscr=00000000
+vrintm.f32.f32 s12, s12 47be2209922b59b24adac4039bf924d9 d829381bb7a6836717a744390f2f5c04 d829381bb7a6836717a7443900000000 d829381bb7a6836717a7443900000000 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintm.f32.f32 s12, s12 261ebea9eefb5d3e99349c5c2ab2d3f3 4459663aabe799e1ae03d9b158330920 4459663aabe799e1ae03d9b158330920 4459663aabe799e1ae03d9b158330920 fpscr=00000000
+vrintm.f32.f32 s12, s12 2e5721325f52c6df377c7e9e19105891 5aff7150324311ea1a82819473cb8b12 5aff7150324311ea1a82819473cb8b12 5aff7150324311ea1a82819473cb8b12 fpscr=00000000
+vrintm.f32.f32 s12, s12 ebc6df674f83504934a356e305be33ac a33a2f40c8b99f809091764995a2c11b a33a2f40c8b99f8090917649bf800000 a33a2f40c8b99f8090917649bf800000 fpscr=00000000
+vrintm.f32.f32 s12, s12 55f95c9c2141966ee89b7bc4c2e9d6c5 789b51210ad8095cd9a351a62cd1e80f 789b51210ad8095cd9a351a600000000 789b51210ad8095cd9a351a600000000 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintm.f32.f32 s12, s12 e3c81c8d7c8836e84c5e181fd8fe8403 5b7ff0cfbcf275fc3aa39dbcec9ce6a0 5b7ff0cfbcf275fc3aa39dbcec9ce6a0 5b7ff0cfbcf275fc3aa39dbcec9ce6a0 fpscr=00000000
+vrintm.f32.f32 s12, s12 3f6186be5097a77550cbf7ce88854d7c 8af1cbf0f14895b2bf584e55e848937d 8af1cbf0f14895b2bf584e55e848937d 8af1cbf0f14895b2bf584e55e848937d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vrintm.f32.f32 s12, s12 e5734572c4993f399427fc4fe5734572 9857a2610acade22aa50f56c03afd45f 9857a2610acade22aa50f56c00000000 9857a2610acade22aa50f56c00000000 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[0]
+vrintm.f32.f32 s12, s12 fe06568ec6debf3db23cda722cf3a8b8 23ae0418feea42b817d534b623ae0418 23ae0418feea42b817d534b600000000 23ae0418feea42b817d534b600000000 fpscr=00000000
+vrintm.f32.f32 s12, s12 537e88ba7538282edcfd874e6b9c86de f73c3f475ccc1cd92fb80a0f6eeab27d f73c3f475ccc1cd92fb80a0f6eeab27d f73c3f475ccc1cd92fb80a0f6eeab27d fpscr=00000000
+vrintm.f32.f32 s12, s12 81488577b949200357a76023e7492273 29f3c9dcb37791332020518e1a0972c7 29f3c9dcb37791332020518e00000000 29f3c9dcb37791332020518e00000000 fpscr=00000000
+vrintm.f32.f32 s12, s12 5f6601268f65b222e8f45d5c33af9fd4 7166ba5a9a691fe5cf749bfd0de67703 7166ba5a9a691fe5cf749bfd00000000 7166ba5a9a691fe5cf749bfd00000000 fpscr=00000000
+vrintm.f32.f32 s12, s12 f6afa0b7aed59cd261aeb2a9aa11be85 765021d9a385631df6277cee024a821c 765021d9a385631df6277cee00000000 765021d9a385631df6277cee00000000 fpscr=00000000
+vrintm.f32.f32 s12, s12 cb1bbc6b9fb32f1f9801a3c3dca3e509 19ac85023f483be28cf83ab4c9bf675f 19ac85023f483be28cf83ab4c9bf6760 19ac85023f483be28cf83ab4c9bf6760 fpscr=00000000
+vrintm.f32.f32 s12, s12 8459276a640e0d51a941289e8cca2f0e fb3c731b47c928a5f5ba57ac440fa5a7 fb3c731b47c928a5f5ba57ac440f8000 fb3c731b47c928a5f5ba57ac440f8000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintm.f32.f32 s12, s12 28855704d732a44b74396dcd753bec15 f463d8fa71a1505d71a1505d7a065699 f463d8fa71a1505d71a1505d7a065699 f463d8fa71a1505d71a1505d7a065699 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintm.f32.f32 s12, s12 ad7f7e5fad7f7e5fc3589d14710c6d0e 61c85d204931f9ed00f9407ca8caa205 61c85d204931f9ed00f9407cbf800000 61c85d204931f9ed00f9407cbf800000 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintm.f32.f32 s12, s12 c2ec4c677062551dacadb1372d50b9a8 518f073e8f6387b080f48e488f6387b0 518f073e8f6387b080f48e48bf800000 518f073e8f6387b080f48e48bf800000 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[2]
+vrintm.f32.f32 s12, s12 131777db159db432a307c0c3159db432 f1512819f15128191518b3ce62201e88 f1512819f15128191518b3ce62201e88 f1512819f15128191518b3ce62201e88 fpscr=00000000
+vrintm.f32.f32 s12, s12 a2e5feb98f375e4e3195f117366d9c41 abc15b3e5fa3fc5eef80de95e87fe406 abc15b3e5fa3fc5eef80de95e87fe406 abc15b3e5fa3fc5eef80de95e87fe406 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintm.f32.f32 s12, s12 38a0e70b011ad91b35fbf1f7713cdcbc 18d647fa89789eeffa8a0a5ce9626136 18d647fa89789eeffa8a0a5ce9626136 18d647fa89789eeffa8a0a5ce9626136 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintm.f32.f32 s12, s12 ee3fd612df862574205e16af3fe7f4cb b58abcc0fc3f3fe260a4f01e5ba25841 b58abcc0fc3f3fe260a4f01e5ba25841 b58abcc0fc3f3fe260a4f01e5ba25841 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintm.f32.f32 s12, s12 92f138d8a871f552bb506f3626bf92c2 0895b8b6a3c80ae905050c9374bb8880 0895b8b6a3c80ae905050c9374bb8880 0895b8b6a3c80ae905050c9374bb8880 fpscr=00000000
+vrintm.f32.f32 s12, s12 271840206cd6b3c192db9f895181f37b 071117d642e258c5652b7d565a9542d4 071117d642e258c5652b7d565a9542d4 071117d642e258c5652b7d565a9542d4 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintm.f32.f32 s12, s12 4916622ad98a51864916622a8ebf0665 55c91ab47f49cb16141d9cd629bac3ba 55c91ab47f49cb16141d9cd600000000 55c91ab47f49cb16141d9cd600000000 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintm.f32.f32 s12, s12 56334540c96c541a8fdd8a2acd1cf75e 337dd953a13c8e5839a26b929787bd94 337dd953a13c8e5839a26b92bf800000 337dd953a13c8e5839a26b92bf800000 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintm.f32.f32 s12, s12 5c496500f505facc7714aae96fee2774 170822eb13bc095edce3e59a13bc095e 170822eb13bc095edce3e59a00000000 170822eb13bc095edce3e59a00000000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintm.f32.f32 s12, s12 ecb79f44371a6497371a6497f98afde7 a7282a4c5bab80f5b636745bbe50cc4d a7282a4c5bab80f5b636745bbf800000 a7282a4c5bab80f5b636745bbf800000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintm.f32.f32 s12, s12 7dd85c6ac8530df4c8530df43580da3f 8ed9edbdfc14c3fb75cf5852bf54a59b 8ed9edbdfc14c3fb75cf5852bf800000 8ed9edbdfc14c3fb75cf5852bf800000 fpscr=00000000
+vrintm.f32.f32 s12, s12 35d2af9c919d65eb206461f8e2232e2d b8864dd69489332910cf8e232df23b64 b8864dd69489332910cf8e2300000000 b8864dd69489332910cf8e2300000000 fpscr=00000000
+vrintm.f32.f32 s12, s12 842ebe324fc344924420f73236725b0c f7de7e6a973e1903e034c689ae9098ba f7de7e6a973e1903e034c689bf800000 f7de7e6a973e1903e034c689bf800000 fpscr=00000000
+vrintm.f32.f32 s12, s12 b6c21f81e612c1d00356bcf8bbd805aa bf86755dddf239bd3ca8006b553a863e bf86755dddf239bd3ca8006b553a863e bf86755dddf239bd3ca8006b553a863e fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintm.f32.f32 s12, s12 fc53a608a1eab2dc77c7ccdcb16c76ae cded29c6cded29c6e6cebdf28622e26c cded29c6cded29c6e6cebdf2bf800000 cded29c6cded29c6e6cebdf2bf800000 fpscr=00000000
+vrintm.f32.f32 s12, s12 66570e9e6936d90d2483b2f1d483982d 598fc69a7ccc5e30594fefdb31b0f3d2 598fc69a7ccc5e30594fefdb00000000 598fc69a7ccc5e30594fefdb00000000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintm.f32.f32 s12, s12 12e45ca17b8dcc16bf633294150848b6 7733b7e70cf3395b4e257ac14e257ac1 7733b7e70cf3395b4e257ac14e257ac1 7733b7e70cf3395b4e257ac14e257ac1 fpscr=00000000
+vrintm.f32.f32 s12, s12 86d0785c6d15dfbdb0d2202f2a65b1a7 77239f28b78f34140c831cec4908c361 77239f28b78f34140c831cec4908c360 77239f28b78f34140c831cec4908c360 fpscr=00000000
+vrintm.f32.f32 s12, s12 1130e069bac1f3b5df9cb6a5049d75a4 a129d0241d888a7d9093481123c2ddec a129d0241d888a7d9093481100000000 a129d0241d888a7d9093481100000000 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintm.f32.f32 s12, s12 f576068d90bea9d0c67eca526bf9dc4b f4dac128bf2836ac467dd82785e849d6 f4dac128bf2836ac467dd827bf800000 f4dac128bf2836ac467dd827bf800000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintm.f32.f32 s12, s12 d651e2e906f6709841f3fc46183864ce e4fedc9748d6bfd727624ca91e1384b5 e4fedc9748d6bfd727624ca900000000 e4fedc9748d6bfd727624ca900000000 fpscr=00000000
+vrintm.f32.f32 s12, s12 e3aacf52b02d839e971efa440994346d 283db81f212f6a3631d3648a4bf8bd01 283db81f212f6a3631d3648a4bf8bd01 283db81f212f6a3631d3648a4bf8bd01 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintm.f32.f32 s12, s12 43797fe769c63c89fa7f928e7cd7e2ce d8fac5b6f7e9761318ae614a18ae614a d8fac5b6f7e9761318ae614a00000000 d8fac5b6f7e9761318ae614a00000000 fpscr=00000000
+vmaxnm.f32 d15,d16,d20 9429182ae250990097babcea1cd03a88 9886929a9c6e483612844b6ad8d38bae 2ba9aff5af5bd454521218ff58f4a0dd 521218ff58f4a0dd97babcea1cd03a88 9886929a9c6e483612844b6ad8d38bae 2ba9aff5af5bd454521218ff58f4a0dd fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vmaxnm.f32 d15,d16,d20 8d11418bc55da54110ae660c90a95a06 97935a052a97593c38208726ed1791ab 95d3b3c8767d85b0ee506dc8dcc33763 38208726dcc3376310ae660c90a95a06 97935a052a97593c38208726ed1791ab 95d3b3c8767d85b0ee506dc8dcc33763 fpscr=00000000
+vmaxnm.f32 d15,d16,d20 1bd65ad797754ddf6143662b17b4f2dd a3219d5dd4a4f91fd8de70d05ecb74a4 6e7b920237d03500dbbcb6fb44ef8e01 d8de70d05ecb74a46143662b17b4f2dd a3219d5dd4a4f91fd8de70d05ecb74a4 6e7b920237d03500dbbcb6fb44ef8e01 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vmaxnm.f32 d15,d16,d20 a14fe66dc8329a2516714cbba14fe66d 5d78c087b055d5be60d531d9b858f81e 0ff1fd02f9086031d18ae2b50ff1fd02 60d531d90ff1fd0216714cbba14fe66d 5d78c087b055d5be60d531d9b858f81e 0ff1fd02f9086031d18ae2b50ff1fd02 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vmaxnm.f32 d15,d16,d20 d7f374e27e0bae2fae3881cb7a98c692 991ceaf53cf40d67ac65acf0787d06f3 25bd24bc4786ed156b0c9dcab3025cd7 6b0c9dca787d06f3ae3881cb7a98c692 991ceaf53cf40d67ac65acf0787d06f3 25bd24bc4786ed156b0c9dcab3025cd7 fpscr=00000000
+randV128: 12032 calls, 12424 iters
+randV128: doing v->u32[0] = v->u32[1]
+vmaxnm.f32 d15,d16,d20 32c414ad795aa32c596443350875a2ba e3ab30d70fab55cdcc7627fe960f64ef f8d3e4381b5cf17d670ff9db670ff9db 670ff9db670ff9db596443350875a2ba e3ab30d70fab55cdcc7627fe960f64ef f8d3e4381b5cf17d670ff9db670ff9db fpscr=00000000
+vmaxnm.f32 d15,d16,d20 21ed3ce3404dbde2930b87b1bd942384 6f3f5b270440b990b5abddf791bf6f0d cfc0533fbc64a010f0c24902e52e4aa0 b5abddf791bf6f0d930b87b1bd942384 6f3f5b270440b990b5abddf791bf6f0d cfc0533fbc64a010f0c24902e52e4aa0 fpscr=00000000
+vmaxnm.f32 d15,d16,d20 a9ed0eea3e3054c3c4077d0ba6113c87 ac6fffdc5a000229c0a12ddeda362651 77ed80fb0d0a637fdb8c4402335c9fd7 c0a12dde335c9fd7c4077d0ba6113c87 ac6fffdc5a000229c0a12ddeda362651 77ed80fb0d0a637fdb8c4402335c9fd7 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[2]
+vmaxnm.f32 d15,d16,d20 b98a57db51167f870a88b5a8412baae6 a7c22fd9b551394c341a6e00ebed8de7 8ac7e7000882bdbd0882bdbd59dad998 341a6e0059dad9980a88b5a8412baae6 a7c22fd9b551394c341a6e00ebed8de7 8ac7e7000882bdbd0882bdbd59dad998 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+vmaxnm.f32 d15,d16,d20 5dae0f3178a0e74fbd470dc478a0e74f bd521d4c8a552b13c305f582e698373f 3eb797e326f98e713e9ad5ae798ee349 3e9ad5ae798ee349bd470dc478a0e74f bd521d4c8a552b13c305f582e698373f 3eb797e326f98e713e9ad5ae798ee349 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vmaxnm.f32 d15,d16,d20 f822baf50afa8a96a0723b5d090e4e59 db0aecc9ec1da68c0091fc5dd0d95933 1e6204d410bc321e89693d572f4dda70 0091fc5d2f4dda70a0723b5d090e4e59 db0aecc9ec1da68c0091fc5dd0d95933 1e6204d410bc321e89693d572f4dda70 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vmaxnm.f32 d15,d16,d20 8c02fc3f182ecea363ddccfda45a73a7 e90fb36af91d836da05ad169f9f1df98 2ebef630dc9373f58aa8ee4baacfa509 8aa8ee4baacfa50963ddccfda45a73a7 e90fb36af91d836da05ad169f9f1df98 2ebef630dc9373f58aa8ee4baacfa509 fpscr=00000000
+vmaxnm.f32 d15,d16,d20 f424534fce111a1bee8a4ca9111c8aa4 7185e05991a2e3fce4a96d68fae2c489 c02d7f16d40c8a9563f1d5665e36daa6 63f1d5665e36daa6ee8a4ca9111c8aa4 7185e05991a2e3fce4a96d68fae2c489 c02d7f16d40c8a9563f1d5665e36daa6 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vmaxnm.f32 d15,d16,d20 3ef850850ea6ad7ec9992199c2c85237 245272db78efbfd99bec679dae761184 d1a6c03f48b87d0be8ee15a215913182 9bec679d15913182c9992199c2c85237 245272db78efbfd99bec679dae761184 d1a6c03f48b87d0be8ee15a215913182 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[1]
+vmaxnm.f32 d15,d16,d20 d299613d37c638b725e3bcf2c6f3232e f75012201e8c3b5bcc3d58d204f8f581 4af863b224b08d08eaafdf775171f92f cc3d58d25171f92f25e3bcf2c6f3232e f75012201e8c3b5bcc3d58d204f8f581 4af863b224b08d08eaafdf775171f92f fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vmaxnm.f32 d15,d16,d20 e18c253f8b0a46d84cfbc5e9d16f9097 8fdda124a6ea567cd688843c8fdda124 86a10e3e0dee6e820d18c8cd57362328 0d18c8cd573623284cfbc5e9d16f9097 8fdda124a6ea567cd688843c8fdda124 86a10e3e0dee6e820d18c8cd57362328 fpscr=00000000
+vmaxnm.f32 d15,d16,d20 d89c42c60812524c0f7f663b1bc471b6 b240803cda9573ac730696154abe769b 27bba58b8b1f1f0252fbde9accae2440 730696154abe769b0f7f663b1bc471b6 b240803cda9573ac730696154abe769b 27bba58b8b1f1f0252fbde9accae2440 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[2]
+vmaxnm.f32 d15,d16,d20 b6234b6f0aca4525b6234b6fb60d5a16 9cb3ce95a4bdb65d78bd7b18fc385ca1 2cecb47e840ca8acca03cdab2cecb47e 78bd7b182cecb47eb6234b6fb60d5a16 9cb3ce95a4bdb65d78bd7b18fc385ca1 2cecb47e840ca8acca03cdab2cecb47e fpscr=00000000
+vmaxnm.f32 d15,d16,d20 04eb23b1eda89eb80d7a68ccd8029ad3 d7dbf8067078e6d0bc1a29cda619d2fa c6e9a4e176356485753e4cab71343af7 753e4cab71343af70d7a68ccd8029ad3 d7dbf8067078e6d0bc1a29cda619d2fa c6e9a4e176356485753e4cab71343af7 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vmaxnm.f32 d15,d16,d20 2ef255a3e553788ee553788e28db04af 2c95fb469d2b6afbb67100619e1495d0 19443419731d349210fbc4bb0f1a2a4c 10fbc4bb0f1a2a4ce553788e28db04af 2c95fb469d2b6afbb67100619e1495d0 19443419731d349210fbc4bb0f1a2a4c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+vmaxnm.f32 d15,d16,d20 fec024cc1d51ec593d346ad61d51ec59 13c0733071afd05171afd051d98c6d1d 0b25cee1393bd63e6d22b28c9cfd1ad8 71afd0519cfd1ad83d346ad61d51ec59 13c0733071afd05171afd051d98c6d1d 0b25cee1393bd63e6d22b28c9cfd1ad8 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vmaxnm.f32 d15,d16,d20 df01369d6192b282d192020b6192b282 bcc85d8ecaa17a098329a55c5cfecf99 3bbd27fd813db871cf3fbd97743fae14 8329a55c743fae14d192020b6192b282 bcc85d8ecaa17a098329a55c5cfecf99 3bbd27fd813db871cf3fbd97743fae14 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vmaxnm.f32 d15,d16,d20 5bca9b084ab7d4d1675f979dad6f2056 384a161d02b1613fab5053abb54649c0 eab271415a8e503f5adfc4be4cadb5eb 5adfc4be4cadb5eb675f979dad6f2056 384a161d02b1613fab5053abb54649c0 eab271415a8e503f5adfc4be4cadb5eb fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vmaxnm.f32 d15,d16,d20 246ddd3e14083a0883122e6f52cf5fd3 f111dd8d14c4beea3a7d15463e5527fa 24b8c458e02adc89370899e4370899e4 3a7d15463e5527fa83122e6f52cf5fd3 f111dd8d14c4beea3a7d15463e5527fa 24b8c458e02adc89370899e4370899e4 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vmaxnm.f32 d15,d16,d20 d38f4dfad38f4dfa50ebdac87854f9c1 33e59695b099d0009686812325ab6f1f 4c8b2821e6264b41165816504951550a 165816504951550a50ebdac87854f9c1 33e59695b099d0009686812325ab6f1f 4c8b2821e6264b41165816504951550a fpscr=00000000
+vmaxnm.f32 d15,d16,d20 8371d547a6366729c62e0fd9576b3161 3cc640ed916c2d33a16a1f355aaefcae 7677092eae282d6914568959713828d8 14568959713828d8c62e0fd9576b3161 3cc640ed916c2d33a16a1f355aaefcae 7677092eae282d6914568959713828d8 fpscr=00000000
+vmaxnm.f32 d15,d16,d20 c52d6e6dfcbee08177d0c050cdcb3c18 ece528697dad25aab9dc3de134ccdf49 b294eac5fc5c85a4bb6fc80f63a9f11b b9dc3de163a9f11b77d0c050cdcb3c18 ece528697dad25aab9dc3de134ccdf49 b294eac5fc5c85a4bb6fc80f63a9f11b fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vmaxnm.f32 d15,d16,d20 2404668f9033dd433808fa6d4f5cec42 4e4b43308d6b1f739da90a6593977084 3ecac70ae125fd44e3415f1c9de90133 9da90a65939770843808fa6d4f5cec42 4e4b43308d6b1f739da90a6593977084 3ecac70ae125fd44e3415f1c9de90133 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[2]
+vmaxnm.f32 d15,d16,d20 8879c7c6637e46848879c7c651bafd0a 412033bd4d78c69df786127d56ca7832 7cf82a7639440d894aab654eb1c6e692 4aab654e56ca78328879c7c651bafd0a 412033bd4d78c69df786127d56ca7832 7cf82a7639440d894aab654eb1c6e692 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vmaxnm.f32 d15,d16,d20 f70b0e084e62b670537b5d91133d2660 bfcc58cedc80ee971a5c7e551a5c7e55 9aa2e6d65ae322c034c23beea5d8c4a3 34c23bee1a5c7e55537b5d91133d2660 bfcc58cedc80ee971a5c7e551a5c7e55 9aa2e6d65ae322c034c23beea5d8c4a3 fpscr=00000000
+vmaxnm.f32 d15,d16,d20 943166b359ebd1d3e262a64c4745fb9e 88e1a8887e9e80d4d4a732b83035f9a3 a4769097e234f188823e9e00ee588ce0 823e9e003035f9a3e262a64c4745fb9e 88e1a8887e9e80d4d4a732b83035f9a3 a4769097e234f188823e9e00ee588ce0 fpscr=00000000
+vmaxnm.f32 d15,d16,d20 2df82b1fad56fd9aa251cd5d38bb83e5 25ebe2dde927e1443a7b1c30760169ce dd0adc48c44a0bbb062fbe262a0e9584 3a7b1c30760169cea251cd5d38bb83e5 25ebe2dde927e1443a7b1c30760169ce dd0adc48c44a0bbb062fbe262a0e9584 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[3]
+vmaxnm.f32 d15,d16,d20 74524332448d91a728b5d9bcbaeb0ae9 0f8b09c4d2ea2e27d2ea2e272c52a281 a6c52a73947448f535676fee0a6da110 35676fee2c52a28128b5d9bcbaeb0ae9 0f8b09c4d2ea2e27d2ea2e272c52a281 a6c52a73947448f535676fee0a6da110 fpscr=00000000
+vmaxnm.f32 d15,d16,d20 b27ac3da0b9c7705b49f8ef37e73ace8 b189c58e22216b076f88abf83ec3e057 cedff95d485c6905dea2cf7bbaf701aa 6f88abf83ec3e057b49f8ef37e73ace8 b189c58e22216b076f88abf83ec3e057 cedff95d485c6905dea2cf7bbaf701aa fpscr=00000000
+vmaxnm.f32 d15,d16,d20 7cdeb58ed1ab0492a592f5b549c2f16c 39ac84ff7c8918b46dead156357ea5e6 d1a9d4357eee765b1e9b163efb3564be 6dead156357ea5e6a592f5b549c2f16c 39ac84ff7c8918b46dead156357ea5e6 d1a9d4357eee765b1e9b163efb3564be fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[3]
+vmaxnm.f32 d15,d16,d20 74bf3262de7d0dfd5c57f9a35c57f9a3 c203551ba3dd2faf41017e07dd3f7e6c b3b7d340547e43d75a1f86672a067d63 5a1f86672a067d635c57f9a35c57f9a3 c203551ba3dd2faf41017e07dd3f7e6c b3b7d340547e43d75a1f86672a067d63 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vmaxnm.f32 d15,d16,d20 0e4914c93cfbffc222b65513bc56de7d f69821ad33f5892ae027ccc78611352d d27847579b2005ba9b2005ba0a12b92c 9b2005ba0a12b92c22b65513bc56de7d f69821ad33f5892ae027ccc78611352d d27847579b2005ba9b2005ba0a12b92c fpscr=00000000
+vmaxnm.f32 d15,d16,d20 b869929d4471940abc62a003e20dc91e f61ce2c29d5aa3e5919fb6ef17a4b063 084953889bd616f9891e10d6df7a9494 891e10d617a4b063bc62a003e20dc91e f61ce2c29d5aa3e5919fb6ef17a4b063 084953889bd616f9891e10d6df7a9494 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[0]
+vmaxnm.f32 d15,d16,d20 43ff18eeb8a6740eddb9a19fb5eba9cb c32f0f4021800bbb21800bbb394cc51c 5fed098da2df78129b6111ee6d1cf3b5 21800bbb6d1cf3b5ddb9a19fb5eba9cb c32f0f4021800bbb21800bbb394cc51c 5fed098da2df78129b6111ee6d1cf3b5 fpscr=00000000
+vmaxnm.f32 d15,d16,d20 8a6851cdf14be812df82f606d313cd21 3b6a727913a9ccef57abd1ec21ec71fb b60b9b58364158fa361c08af532fc76e 57abd1ec532fc76edf82f606d313cd21 3b6a727913a9ccef57abd1ec21ec71fb b60b9b58364158fa361c08af532fc76e fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vmaxnm.f32 d15,d16,d20 3fba6d6eb3a7c0546f895160f6c43d3f 21b674ffc393b603dcc9f9ebc9340c5a ac22b90b20674d3987599b3c96a4f5eb 87599b3c96a4f5eb6f895160f6c43d3f 21b674ffc393b603dcc9f9ebc9340c5a ac22b90b20674d3987599b3c96a4f5eb fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vmaxnm.f32 d15,d16,d20 ba6bef434207a9ba612bcf6f9b3eef5a 4db2d14ab02942d08f7dbb0a567498fd 8bb7d515238dcb463c81f8d51234c2ba 3c81f8d5567498fd612bcf6f9b3eef5a 4db2d14ab02942d08f7dbb0a567498fd 8bb7d515238dcb463c81f8d51234c2ba fpscr=00000000
+vmaxnm.f32 d15,d16,d20 a9aaf2286533169145c6e6eeec484204 e5e9899ff0579c78b13349d8a137d72e b536444a0f4ac0878f98881e964c0fd5 8f98881e964c0fd545c6e6eeec484204 e5e9899ff0579c78b13349d8a137d72e b536444a0f4ac0878f98881e964c0fd5 fpscr=00000000
+vmaxnm.f32 d15,d16,d20 2e4b577c8f7d3cd444b197a7efda9a9b 394d7c040a81e0c52e29848b490c7745 ccdd3fb74184bb95b236b3afad6bae4e 2e29848b490c774544b197a7efda9a9b 394d7c040a81e0c52e29848b490c7745 ccdd3fb74184bb95b236b3afad6bae4e fpscr=00000000
+vmaxnm.f32 d15,d16,d20 afcfe17ee0c6d8042db32e3dcce0170a 1f21553545365b1ed9863fe12d14433b 49b054a8bda186f3b89cc7d34d0489a1 b89cc7d34d0489a12db32e3dcce0170a 1f21553545365b1ed9863fe12d14433b 49b054a8bda186f3b89cc7d34d0489a1 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vmaxnm.f32 d15,d16,d20 c9bf1a9c78eacac25d3cc6eefbff3e90 244d750d5ec75021db87f16ed82d9618 5ae74aba276ff27233fcf8ee276ff272 33fcf8ee276ff2725d3cc6eefbff3e90 244d750d5ec75021db87f16ed82d9618 5ae74aba276ff27233fcf8ee276ff272 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vmaxnm.f32 d15,d16,d20 0ac4ec069fe93ff81f8a1b0e8424deb6 2e08e267f05b988a8ca1de82417ef4b1 2bc31b41cf70530b7aa24c961951f606 7aa24c96417ef4b11f8a1b0e8424deb6 2e08e267f05b988a8ca1de82417ef4b1 2bc31b41cf70530b7aa24c961951f606 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: 12288 calls, 12689 iters
+vmaxnm.f32 d15,d16,d20 2b322c1f30bfd4062034743630bfd406 91dff5eb9bb7bcf91fe6d153f0157fce b520d40cb2b08c2a36819c0eebe24d0a 36819c0eebe24d0a2034743630bfd406 91dff5eb9bb7bcf91fe6d153f0157fce b520d40cb2b08c2a36819c0eebe24d0a fpscr=00000000
+vmaxnm.f32 d15,d16,d20 3b8c4833302e08edd0664fcb7e678fd5 8c7e0f851764cf0cf40abd4383a072c1 5b9f156203011bead0d83ed6cad91744 d0d83ed683a072c1d0664fcb7e678fd5 8c7e0f851764cf0cf40abd4383a072c1 5b9f156203011bead0d83ed6cad91744 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vmaxnm.f32 d15,d16,d20 027a8eb24fb9252ac361a716b70e746c cb32c6c4d34fd139d34fd139fb86b38f 7828904f3045661c41a53254de6aa03e 41a53254de6aa03ec361a716b70e746c cb32c6c4d34fd139d34fd139fb86b38f 7828904f3045661c41a53254de6aa03e fpscr=00000000
+vmaxnm.f32 q7, q8, q10 34dcde47d1475c29397668959126753e 38b1bc6a51338d198306c6e3e2987180 76cd23f4226ad0e9fedc2c55eb5c88b4 76cd23f451338d198306c6e3e2987180 38b1bc6a51338d198306c6e3e2987180 76cd23f4226ad0e9fedc2c55eb5c88b4 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 182430ffb768323bbce770c2565a2a4b da8c2e35606782404c9d57a39f30f28c c27cc265d7a7da4d6be169f9a9efe45e c27cc265606782406be169f99f30f28c da8c2e35606782404c9d57a39f30f28c c27cc265d7a7da4d6be169f9a9efe45e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vmaxnm.f32 q7, q8, q10 419b3f0d074c054f1c11424efb5ee111 ce864d28c9dca7ecc9dca7eca64f6d5c 8c77dd9de32dc8a22cc3f6af51cc5ea4 8c77dd9dc9dca7ec2cc3f6af51cc5ea4 ce864d28c9dca7ecc9dca7eca64f6d5c 8c77dd9de32dc8a22cc3f6af51cc5ea4 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[2]
+vmaxnm.f32 q7, q8, q10 d0e08219a273cb0a929528c7ba7b5015 d1cfe56648e2ad131bec16acd1cfe566 536ef05e77d94eb693dd8f153763d88e 536ef05e77d94eb61bec16ac3763d88e d1cfe56648e2ad131bec16acd1cfe566 536ef05e77d94eb693dd8f153763d88e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vmaxnm.f32 q7, q8, q10 bd145f60552c496a7a16c6db814dfeb3 9821d8ee08f20a33a4bc7f558456ac99 00971f74ced838021c001a7f00971f74 00971f7408f20a331c001a7f00971f74 9821d8ee08f20a33a4bc7f558456ac99 00971f74ced838021c001a7f00971f74 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[0]
+vmaxnm.f32 q7, q8, q10 58e6986ce63f9144529726efe63f9144 24ca7588fdb7198ba423f942fdb7198b f115c77e9ec45198f2e898e2595a56ab 24ca75889ec45198a423f942595a56ab 24ca7588fdb7198ba423f942fdb7198b f115c77e9ec45198f2e898e2595a56ab fpscr=00000000
+vmaxnm.f32 q7, q8, q10 dd9a725f760d93ebd87eeece494d87a8 c3b1d05f0a18e0b074959edb1ab94e8b 92a197cc9c421ac2bbff48b5aaca9ded 92a197cc0a18e0b074959edb1ab94e8b c3b1d05f0a18e0b074959edb1ab94e8b 92a197cc9c421ac2bbff48b5aaca9ded fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[1]
+vmaxnm.f32 q7, q8, q10 594976658ae250d4e11382e88a516b5f 0c24134dd6dec3eadede091e0306dc7d 26e214792dc5124626e214799c11c986 26e214792dc5124626e214790306dc7d 0c24134dd6dec3eadede091e0306dc7d 26e214792dc5124626e214799c11c986 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 fb6b4c9e837b719b3876278abf0447a6 9ade037108c0e145643630995654e6bf bf499cc73581930bcebc05fca5759180 9ade03713581930b643630995654e6bf 9ade037108c0e145643630995654e6bf bf499cc73581930bcebc05fca5759180 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 9fc14a5633e863961c6b42d88b53ccf6 7af7f9305039a0b431ba6a3ed9ab4bee d5e92d48560e01813166f6b3d828dadc 7af7f930560e018131ba6a3ed828dadc 7af7f9305039a0b431ba6a3ed9ab4bee d5e92d48560e01813166f6b3d828dadc fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vmaxnm.f32 q7, q8, q10 a88aac1bef64147b1b59405ba88aac1b 9620330f7eb34717dd31f3cbd27e3da2 3107763b30d670a07a66061eac24c915 3107763b7eb347177a66061eac24c915 9620330f7eb34717dd31f3cbd27e3da2 3107763b30d670a07a66061eac24c915 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vmaxnm.f32 q7, q8, q10 abc6d76bb8dd4d96e540e0e6e540e0e6 34ebdaa4699a49cef173db4d34ebdaa4 11d63b134409e0cfa3b207c581b320e0 34ebdaa4699a49cea3b207c534ebdaa4 34ebdaa4699a49cef173db4d34ebdaa4 11d63b134409e0cfa3b207c581b320e0 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vmaxnm.f32 q7, q8, q10 f13df8be44e80fbcb15ab31e87fd985c c2ce95233ca157e856c409bed2b7ef44 bc5887ad790f6976a4960aa5a4960aa5 bc5887ad790f697656c409bea4960aa5 c2ce95233ca157e856c409bed2b7ef44 bc5887ad790f6976a4960aa5a4960aa5 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 4175fa30b045415166dbaffb9eee7290 f793011a8a30e5cbbfd3135bb060739b 80fc7b81a41c646fd3cb6a18822bb7b6 80fc7b818a30e5cbbfd3135b822bb7b6 f793011a8a30e5cbbfd3135bb060739b 80fc7b81a41c646fd3cb6a18822bb7b6 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vmaxnm.f32 q7, q8, q10 22443ce2edbb41847790accb9bdceae1 e56c81c77e081753cbc3233adda92a3a a555c764f8a34d14e4f4f9d1d7f6a8ac a555c7647e081753cbc3233ad7f6a8ac e56c81c77e081753cbc3233adda92a3a a555c764f8a34d14e4f4f9d1d7f6a8ac fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+vmaxnm.f32 q7, q8, q10 c294ada1a9d330162d3265777dc665d9 c8eafd09368389153c200fba98b3e36c 162ca2b4156f8b9b68514697ae812457 162ca2b4368389156851469798b3e36c c8eafd09368389153c200fba98b3e36c 162ca2b4156f8b9b68514697ae812457 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 2e6a39381562f46a37a9519bd47d4548 0c6da62316cc0282386fa1274d093645 a46f245cb7538a8ed4ad990d86959aa3 0c6da62316cc0282386fa1274d093645 0c6da62316cc0282386fa1274d093645 a46f245cb7538a8ed4ad990d86959aa3 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vmaxnm.f32 q7, q8, q10 c2842a6c3ddec3ba0cd956eedfbb18c8 c20abfb1cd9ccd20e0aa086cd70c65e8 888453c17b667b5737889d9595495740 888453c17b667b5737889d9595495740 c20abfb1cd9ccd20e0aa086cd70c65e8 888453c17b667b5737889d9595495740 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 7b1f97468c355277ef3bcac25e2032f9 e038beeaef82c97963caf7cfb0733274 61910d03dbf9929e85bbd116dda9f4ee 61910d03dbf9929e63caf7cfb0733274 e038beeaef82c97963caf7cfb0733274 61910d03dbf9929e85bbd116dda9f4ee fpscr=00000000
+vmaxnm.f32 q7, q8, q10 90d2021fb9991a24be11ad1cc0b44dc3 2298f7741eb4eb371c5cec260addb55c 2b366fbf7ec3054301879e4c3aa750fb 2b366fbf7ec305431c5cec263aa750fb 2298f7741eb4eb371c5cec260addb55c 2b366fbf7ec3054301879e4c3aa750fb fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[1]
+vmaxnm.f32 q7, q8, q10 7104bd56f967c62b4cd6b263d554362d 0c749a1e754c2adeba611e4324b45c14 7bb8ac544e198e9216e2b6bb6b905ab6 7bb8ac54754c2ade16e2b6bb6b905ab6 0c749a1e754c2adeba611e4324b45c14 7bb8ac544e198e9216e2b6bb6b905ab6 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vmaxnm.f32 q7, q8, q10 453febd4bacd6b3f8ce30f1a1c55e21a 119d29a95991af30dde39898b2847138 e65638c4f68fd22912b6839be65638c4 119d29a95991af3012b6839bb2847138 119d29a95991af30dde39898b2847138 e65638c4f68fd22912b6839be65638c4 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vmaxnm.f32 q7, q8, q10 2042f731b00141a258f520b8437d4f71 6da12c203a3a70a21c5c8f8c98d2f176 06274e3fbc0efde447c11b98175eb4ec 6da12c203a3a70a247c11b98175eb4ec 6da12c203a3a70a21c5c8f8c98d2f176 06274e3fbc0efde447c11b98175eb4ec fpscr=00000000
+vmaxnm.f32 q7, q8, q10 ce5823143cd8634996c9c67d3b1ddebd 52c87c92e87520532a4d8783525ffb1f ab9ef0bbaf5b4cd3885c494ce34745ec 52c87c92af5b4cd32a4d8783525ffb1f 52c87c92e87520532a4d8783525ffb1f ab9ef0bbaf5b4cd3885c494ce34745ec fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vmaxnm.f32 q7, q8, q10 21e91df65b3ff818d23f95b61bd1c93f a5ac3d9cf10bbc4305cba0da1a7b230c 960e77ba960e77ba750b4314e716e1ea 960e77ba960e77ba750b43141a7b230c a5ac3d9cf10bbc4305cba0da1a7b230c 960e77ba960e77ba750b4314e716e1ea fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vmaxnm.f32 q7, q8, q10 c11f6d20c033057e5ef9e446c6b6b58f ab1f444dca6e5cc73b72c693396df2a0 a2299153dcc7ef37a229915354027061 a2299153ca6e5cc73b72c69354027061 ab1f444dca6e5cc73b72c693396df2a0 a2299153dcc7ef37a229915354027061 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 3864cf48db9e77b873a6dbbb26a4e1c0 51a189d468de23143130846d6f268bda dce8274cb4fab05301177e9ca320a665 51a189d468de23143130846d6f268bda 51a189d468de23143130846d6f268bda dce8274cb4fab05301177e9ca320a665 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vmaxnm.f32 q7, q8, q10 c16e8b88e169a1c1d8ea166021bd3d7e ccb3074c1af9daaac80b62bd8e4e6f20 1a4e4ce09667b01d42089b5cd0e1fa92 1a4e4ce01af9daaa42089b5c8e4e6f20 ccb3074c1af9daaac80b62bd8e4e6f20 1a4e4ce09667b01d42089b5cd0e1fa92 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vmaxnm.f32 q7, q8, q10 2d570263aea1492d26b1cdeacfed15d8 5ac37c2aac7febf718fe229604f35be6 ea9bd4ac184e07a7168d4e49110677c0 5ac37c2a184e07a718fe2296110677c0 5ac37c2aac7febf718fe229604f35be6 ea9bd4ac184e07a7168d4e49110677c0 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vmaxnm.f32 q7, q8, q10 92a8308fca9221ce95870b01174b9618 3bc01a1395e03851149814becf131a67 1e99974c6b4ca067e77b5670e5c32387 3bc01a136b4ca067149814becf131a67 3bc01a1395e03851149814becf131a67 1e99974c6b4ca067e77b5670e5c32387 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 27b1045e727f0280ec05c75e6710b81c 2cf38eb7f43f12876962edc5e3182769 e0f08e4327256ee81f47dc0b094e9b8b 2cf38eb727256ee86962edc5094e9b8b 2cf38eb7f43f12876962edc5e3182769 e0f08e4327256ee81f47dc0b094e9b8b fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vmaxnm.f32 q7, q8, q10 d29a892b1cbf6f57436eba166e707878 9493b2379cf43e8743df8af1f360026e 89d06ccb49a69c86e32553a3cc7a0d3e 89d06ccb49a69c8643df8af1cc7a0d3e 9493b2379cf43e8743df8af1f360026e 89d06ccb49a69c86e32553a3cc7a0d3e fpscr=00000000
+vmaxnm.f32 q7, q8, q10 4f23cca734f5ebae7d0e87e96bc81604 76b89c7d43af61cc40b5f698f5099c8f 7723f0dbdfd5dea7499c7ad8b580a5ba 7723f0db43af61cc499c7ad8b580a5ba 76b89c7d43af61cc40b5f698f5099c8f 7723f0dbdfd5dea7499c7ad8b580a5ba fpscr=00000000
+vmaxnm.f32 q7, q8, q10 7a5aaf3bd07a3fb1f34b13f51f3ab783 5d3226c1e25f210d8a0f8667ab492780 9948331506c1d325ff6b65772d361487 5d3226c106c1d3258a0f86672d361487 5d3226c1e25f210d8a0f8667ab492780 9948331506c1d325ff6b65772d361487 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 b15bc802978cc877ecfbf18bd94f58a5 4259fa86eb02542a7e434b6b7d9a5a7f bbd3732e81322c76b75788c3850edd9e 4259fa8681322c767e434b6b7d9a5a7f 4259fa86eb02542a7e434b6b7d9a5a7f bbd3732e81322c76b75788c3850edd9e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vmaxnm.f32 q7, q8, q10 a7b388190eb641a741b96677acb0e78f 2bf250362bf250368e4867aff4ae2181 dd745df50fe87e4aad26b684910db7bd 2bf250362bf250368e4867af910db7bd 2bf250362bf250368e4867aff4ae2181 dd745df50fe87e4aad26b684910db7bd fpscr=00000000
+vmaxnm.f32 q7, q8, q10 acca231f49ae8f15947b5dd6cf6b590a ebd51889f2a8e7a2663a187f8665c5fe aae3dad225501e8dbdd6c9509fe9eb39 aae3dad225501e8d663a187f8665c5fe ebd51889f2a8e7a2663a187f8665c5fe aae3dad225501e8dbdd6c9509fe9eb39 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 92e4d3a1a9cb12a47c8e83bb5dc6d641 d5bfa9f92050578f2847c82f29962ec5 d9e372b191b5d3d033e62853ab01a82c d5bfa9f92050578f33e6285329962ec5 d5bfa9f92050578f2847c82f29962ec5 d9e372b191b5d3d033e62853ab01a82c fpscr=00000000
+vmaxnm.f32 q7, q8, q10 8a8764826ac8c802be5cef6ebd051194 9a5182d3b8616c07092bc51b0f733ddf 0c37c69aa7328aad4a7b4c8139097d55 0c37c69aa7328aad4a7b4c8139097d55 9a5182d3b8616c07092bc51b0f733ddf 0c37c69aa7328aad4a7b4c8139097d55 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[0]
+vmaxnm.f32 q7, q8, q10 61b518d6138d674e0558a15a96afaa79 91be67b58279a0fa983a03f0ebfc68a2 6c8616225ee203f13f4f7917a12d304a 6c8616225ee203f13f4f7917a12d304a 91be67b58279a0fa983a03f0ebfc68a2 6c8616225ee203f13f4f7917a12d304a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: 12544 calls, 12962 iters
+vmaxnm.f32 q7, q8, q10 141365b890733a739c8f4dcda30a3320 033aa6fff771e2498ce8897a86897392 4e70253e82b28130feb979e287a29a00 4e70253e82b281308ce8897a86897392 033aa6fff771e2498ce8897a86897392 4e70253e82b28130feb979e287a29a00 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vmaxnm.f32 q7, q8, q10 98289fde39d478daba217a8a6589b672 fdf82bffb09f75dc69cf164c8ca44b9f 845f81336f87cb770d014ffd0d014ffd 845f81336f87cb7769cf164c0d014ffd fdf82bffb09f75dc69cf164c8ca44b9f 845f81336f87cb770d014ffd0d014ffd fpscr=00000000
+vmaxnm.f32 q7, q8, q10 d44316d7cecca454409260f3da8a20ca 9346e6721dc388f4e43c85b1d182248d bc193e663e0a8f8217fc8e3d384e4ed2 9346e6723e0a8f8217fc8e3d384e4ed2 9346e6721dc388f4e43c85b1d182248d bc193e663e0a8f8217fc8e3d384e4ed2 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[1]
+vmaxnm.f32 q7, q8, q10 d28957f3b1471ad2ce6133eace6133ea 192c47fe4ed86ce1afdd03724ed86ce1 964dab57341f2c209a46113f517dd549 192c47fe4ed86ce19a46113f517dd549 192c47fe4ed86ce1afdd03724ed86ce1 964dab57341f2c209a46113f517dd549 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vmaxnm.f32 q7, q8, q10 91052e7b10bf91cb8a92d43265a2a488 ac595a7a7509bb860faa9253495f1a26 5d598049f6fe6bc7a6a4c6f88fa00c49 5d5980497509bb860faa9253495f1a26 ac595a7a7509bb860faa9253495f1a26 5d598049f6fe6bc7a6a4c6f88fa00c49 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 66bd9dfc4d3a225df53a09e981785f34 eee3f2a588f5651281a35010fbe658b0 2082ac8dad5d1aef94f44a835a393078 2082ac8d88f5651281a350105a393078 eee3f2a588f5651281a35010fbe658b0 2082ac8dad5d1aef94f44a835a393078 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 3d1355856e85c61a8e1a5429914d1fd4 af32d3ae5ea9dfa05561f0da83687173 d90c2ef13fd650c743ea0aded39d24b9 af32d3ae5ea9dfa05561f0da83687173 af32d3ae5ea9dfa05561f0da83687173 d90c2ef13fd650c743ea0aded39d24b9 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 89a765d410fd6af683d95cbb538d6da5 778a6dd4f090e7fb02f446b40e0a855f 25f43f33409d106ffe344d46e0044ffb 778a6dd4409d106f02f446b40e0a855f 778a6dd4f090e7fb02f446b40e0a855f 25f43f33409d106ffe344d46e0044ffb fpscr=00000000
+vmaxnm.f32 q7, q8, q10 5a0b13b185e88f7b408f0d108f325f78 554015caca460802719ac6767ac2b261 adbd0f57ef7319fc604fdd10c2d983ca 554015caca460802719ac6767ac2b261 554015caca460802719ac6767ac2b261 adbd0f57ef7319fc604fdd10c2d983ca fpscr=00000000
+vmaxnm.f32 q7, q8, q10 541574232a5b9deb95caf17262137f7b bf0ba2e3078c894a8e9d1d679d476e12 b3a3d7c97cc1938ced8b17f82daccb1b b3a3d7c97cc1938c8e9d1d672daccb1b bf0ba2e3078c894a8e9d1d679d476e12 b3a3d7c97cc1938ced8b17f82daccb1b fpscr=00000000
+vminnm.f32 d15,d16,d20 909acc2a927b5e3c273945f0505345d5 1cf76bf45bf0ce1f4e30ce4926d2167b cbfa1a6f34e7489b1992c2ebc63ad9d3 1992c2ebc63ad9d3273945f0505345d5 1cf76bf45bf0ce1f4e30ce4926d2167b cbfa1a6f34e7489b1992c2ebc63ad9d3 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vminnm.f32 d15,d16,d20 0870ae4e1a5e536205686ea005686ea0 9877ea3b0ba4d259e10a9c50d40e6131 c8c433b6af2093c7d157f959a74355dd e10a9c50d40e613105686ea005686ea0 9877ea3b0ba4d259e10a9c50d40e6131 c8c433b6af2093c7d157f959a74355dd fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vminnm.f32 d15,d16,d20 faa25148a99d765ee58ebfabafdc2c54 efe33ebdd12d8e275eb0a2e443242cda 8cda13cc4f8a9fc0462cdd8d609e5ecf 462cdd8d43242cdae58ebfabafdc2c54 efe33ebdd12d8e275eb0a2e443242cda 8cda13cc4f8a9fc0462cdd8d609e5ecf fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vminnm.f32 d15,d16,d20 81f7b7262d85e25f5ae36d7d15a522c9 2f0de8f9bdc05ca0c76c84ec5525d15a 53a6d62efbd02d1b3dee81a8c6460ebf c76c84ecc6460ebf5ae36d7d15a522c9 2f0de8f9bdc05ca0c76c84ec5525d15a 53a6d62efbd02d1b3dee81a8c6460ebf fpscr=00000000
+vminnm.f32 d15,d16,d20 288da89490cb473dfecda7f992822321 5cd0ed4773c0bbde51d7a96dc18d12d2 9508275efab4ad14fa2fca0c478f6eac fa2fca0cc18d12d2fecda7f992822321 5cd0ed4773c0bbde51d7a96dc18d12d2 9508275efab4ad14fa2fca0c478f6eac fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vminnm.f32 d15,d16,d20 b0ef9896cf46abbe6350c39e205d3c07 fca5b0cd2925b3e32925b3e335384a30 efaa92b623efbe1bbc86c7fa49c9ffe5 bc86c7fa35384a306350c39e205d3c07 fca5b0cd2925b3e32925b3e335384a30 efaa92b623efbe1bbc86c7fa49c9ffe5 fpscr=00000000
+vminnm.f32 d15,d16,d20 435c3ff467772e1abefc2f2aebe35662 5dd15f482188c7815f23f47f866d23db 16feae8567747f9d0299aaf2e911c726 0299aaf2e911c726befc2f2aebe35662 5dd15f482188c7815f23f47f866d23db 16feae8567747f9d0299aaf2e911c726 fpscr=00000000
+vminnm.f32 d15,d16,d20 4d9431b7bc681d698e3fc4b5ad9d5b4c e7a61879940538bcd639b57b74c2f4ff 72b0b4400f76be2ef95ca400495e1e1b f95ca400495e1e1b8e3fc4b5ad9d5b4c e7a61879940538bcd639b57b74c2f4ff 72b0b4400f76be2ef95ca400495e1e1b fpscr=00000000
+vminnm.f32 d15,d16,d20 07035ece1e8b7df93b6f9ccb174f9269 88721f6b51edc13b03778442216ca496 5a307af641a22fdaf77ee26210993187 f77ee262109931873b6f9ccb174f9269 88721f6b51edc13b03778442216ca496 5a307af641a22fdaf77ee26210993187 fpscr=00000000
+vminnm.f32 d15,d16,d20 99ab463c233b4fa9d80363c552882eff 6213d3b87ac75e1c156c506f74eba764 b6c4c9eac91e3f87082123875f9a4b84 082123875f9a4b84d80363c552882eff 6213d3b87ac75e1c156c506f74eba764 b6c4c9eac91e3f87082123875f9a4b84 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[3]
+vminnm.f32 d15,d16,d20 62f4fad7e5b80d6aae12a4d5779ab5a5 36e6e6f4238c29c971f3a936d96d74a6 45ca8c7a054f8353b9a3e85c054f8353 b9a3e85cd96d74a6ae12a4d5779ab5a5 36e6e6f4238c29c971f3a936d96d74a6 45ca8c7a054f8353b9a3e85c054f8353 fpscr=00000000
+vminnm.f32 d15,d16,d20 37054689934a896f9df4aa35ac689d65 a87800c5c86edd0fbf16c3a7b13632ab 74132093429a90861a05ee7778a30a1b bf16c3a7b13632ab9df4aa35ac689d65 a87800c5c86edd0fbf16c3a7b13632ab 74132093429a90861a05ee7778a30a1b fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vminnm.f32 d15,d16,d20 88f055822cdf6024148da208923bd4c2 84e97e3904d1940896c3d63f96c3d63f 2054f5e57c4b011973bd4f1ec2a7cdc5 96c3d63fc2a7cdc5148da208923bd4c2 84e97e3904d1940896c3d63f96c3d63f 2054f5e57c4b011973bd4f1ec2a7cdc5 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[3]
+vminnm.f32 d15,d16,d20 48fa3d99e61864c86b9595e9b2364962 a3eec96dbfa6e30805c3fffe926bc26e 5a6e5138b7edb3daa5ff3ebb959a0288 a5ff3ebb959a02886b9595e9b2364962 a3eec96dbfa6e30805c3fffe926bc26e 5a6e5138b7edb3daa5ff3ebb959a0288 fpscr=00000000
+vminnm.f32 d15,d16,d20 820dea189e98b5e6adbeb6a82b6f7b6c f41f8f3382f9a2c726f6b8297232c8bd 135b99aa1da93c225080aa90eb123d16 26f6b829eb123d16adbeb6a82b6f7b6c f41f8f3382f9a2c726f6b8297232c8bd 135b99aa1da93c225080aa90eb123d16 fpscr=00000000
+vminnm.f32 d15,d16,d20 d918e1353b95f4b242bf5eea52b3ca77 839e66627195d4e8a83e957204664c74 70a2414332876553d1160d7cf9a11004 d1160d7cf9a1100442bf5eea52b3ca77 839e66627195d4e8a83e957204664c74 70a2414332876553d1160d7cf9a11004 fpscr=00000000
+vminnm.f32 d15,d16,d20 459582ae6bde602e3e59425fe407aee7 cc84dc5421eadbd0a9ec512daf846044 e8cb105974340160ee2712514e64b28d ee271251af8460443e59425fe407aee7 cc84dc5421eadbd0a9ec512daf846044 e8cb105974340160ee2712514e64b28d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vminnm.f32 d15,d16,d20 b9b876c9bfffdc18bfffdc1823290e89 6a4f42f1c1bf24f38e23a8c08ce32ce3 bee4e203240159909f5ea6ab6ffdb945 9f5ea6ab8ce32ce3bfffdc1823290e89 6a4f42f1c1bf24f38e23a8c08ce32ce3 bee4e203240159909f5ea6ab6ffdb945 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vminnm.f32 d15,d16,d20 7df0b2b419d8f7f9710a3cc83df25e24 b6e19465158a6ebba69de5c382afae72 b8b4b865b9cc0bddb9cc0bddb74e6c62 b9cc0bddb74e6c62710a3cc83df25e24 b6e19465158a6ebba69de5c382afae72 b8b4b865b9cc0bddb9cc0bddb74e6c62 fpscr=00000000
+vminnm.f32 d15,d16,d20 b1d5b3e2f4eaf6336f037d34a9409d1b 35646f257e925e2bbef4ce1ee3ff79fd c18cec07d42305ee4555842311bd6d16 bef4ce1ee3ff79fd6f037d34a9409d1b 35646f257e925e2bbef4ce1ee3ff79fd c18cec07d42305ee4555842311bd6d16 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vminnm.f32 d15,d16,d20 99a6f61af79fb7269c6de9184b3f4d15 a227cda51eab8251610c91d1cb17049c dbe8ba329c4780b6d184471f9c3d04f2 d184471fcb17049c9c6de9184b3f4d15 a227cda51eab8251610c91d1cb17049c dbe8ba329c4780b6d184471f9c3d04f2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 d15,d16,d20 65b22bebd319bb4edb5b6d5655ff9235 20e3ecec3cb679a2fa65ded07c200c4d 3edfd82048979fab1597d3d0d0501a8a fa65ded0d0501a8adb5b6d5655ff9235 20e3ecec3cb679a2fa65ded07c200c4d 3edfd82048979fab1597d3d0d0501a8a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 d15,d16,d20 72daeaa3f40335fba59ba62976a8e753 0e1ec1a798a0d25eba1428db0e1ec1a7 9ded261c3caf1c152fc9f28bf77f1f27 ba1428dbf77f1f27a59ba62976a8e753 0e1ec1a798a0d25eba1428db0e1ec1a7 9ded261c3caf1c152fc9f28bf77f1f27 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vminnm.f32 d15,d16,d20 6e34db798fed8af561a5e6d8fa0cbc28 cd6dd50785a8d617c2cce2b264e731c7 08eb2dee9b2f791827dcb49cb74003e0 c2cce2b2b74003e061a5e6d8fa0cbc28 cd6dd50785a8d617c2cce2b264e731c7 08eb2dee9b2f791827dcb49cb74003e0 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vminnm.f32 d15,d16,d20 d41e48f6c24be1f5857762405d2181a0 137d8826297a38a1accf867375040f48 d74fbe2fe6a7b684d74fbe2fa1b2cf57 d74fbe2fa1b2cf57857762405d2181a0 137d8826297a38a1accf867375040f48 d74fbe2fe6a7b684d74fbe2fa1b2cf57 fpscr=00000000
+vminnm.f32 d15,d16,d20 aff8d7bc5e3add705557e99306c562a0 cc2bb71e41f2cec845ac575b12687503 c4be92cf7a57cea10b21f94586e6da26 0b21f94586e6da265557e99306c562a0 cc2bb71e41f2cec845ac575b12687503 c4be92cf7a57cea10b21f94586e6da26 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vminnm.f32 d15,d16,d20 4c419f3b5e4ca28ea81c0d7c0bc26171 8720dfd7561b5002a1d1f555a1d1f555 8d9e59822d9b5b1ea974cf45094197c2 a974cf45a1d1f555a81c0d7c0bc26171 8720dfd7561b5002a1d1f555a1d1f555 8d9e59822d9b5b1ea974cf45094197c2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vminnm.f32 d15,d16,d20 60755588f5a7ef5abf88b86ff113d174 4d00d36dcc43cd15258704e583ed0ba7 f4ca8a12b45e3bb4d200ef6ed788568c d200ef6ed788568cbf88b86ff113d174 4d00d36dcc43cd15258704e583ed0ba7 f4ca8a12b45e3bb4d200ef6ed788568c fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vminnm.f32 d15,d16,d20 63e23dd804a48c646636a59376cfc78f 30d296ebd5c8ba366df94698be535b8e ae3b24f53e0b134e3e0b134e0e2b8255 3e0b134ebe535b8e6636a59376cfc78f 30d296ebd5c8ba366df94698be535b8e ae3b24f53e0b134e3e0b134e0e2b8255 fpscr=00000000
+vminnm.f32 d15,d16,d20 0fef52ee563ee930a22f9fbb043bfef9 8687bd1a34f39932c9ee9b70ef997428 8305f27652568c275b27f64ed771fef7 c9ee9b70ef997428a22f9fbb043bfef9 8687bd1a34f39932c9ee9b70ef997428 8305f27652568c275b27f64ed771fef7 fpscr=00000000
+vminnm.f32 d15,d16,d20 4bcb0d8f521c4761fed011cb4759c7fd 85ab568210944316bb3fee52d500fec7 0e209e1702701d5d52bd811b78ff194d bb3fee52d500fec7fed011cb4759c7fd 85ab568210944316bb3fee52d500fec7 0e209e1702701d5d52bd811b78ff194d fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 d15,d16,d20 635cbb04e0875e5b68de5715a52fffd9 84cbf00ae257ae9daee36a06306244e0 1e44843de01b0456a18cf2e31e44843d aee36a061e44843d68de5715a52fffd9 84cbf00ae257ae9daee36a06306244e0 1e44843de01b0456a18cf2e31e44843d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 d15,d16,d20 65db7e006cec6042ea83890fbe978d95 a679fb2a6c8c8ba91aeddd931aeddd93 85cb67a47b3a75d1c4fcd17f85cb67a4 c4fcd17f85cb67a4ea83890fbe978d95 a679fb2a6c8c8ba91aeddd931aeddd93 85cb67a47b3a75d1c4fcd17f85cb67a4 fpscr=00000000
+randV128: 12800 calls, 13227 iters
+vminnm.f32 d15,d16,d20 690abb6f1a2822266f884d37a0693b47 7adf034d9f30234834c659db8be68a6d a15a6392a284d4ee80dc72d3214c2ce9 80dc72d38be68a6d6f884d37a0693b47 7adf034d9f30234834c659db8be68a6d a15a6392a284d4ee80dc72d3214c2ce9 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vminnm.f32 d15,d16,d20 01358e4cdaa01c3769404a29cd88aba0 5fb230021670466f9c0f4ca51670466f 09bdebfcca541b20b2c22cb7cd38e39c b2c22cb7cd38e39c69404a29cd88aba0 5fb230021670466f9c0f4ca51670466f 09bdebfcca541b20b2c22cb7cd38e39c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vminnm.f32 d15,d16,d20 6268f7c48e0986a90b913216e420dc11 78b75538e8ba1e705eb9177278b75538 52a0bf649f655584091063386452f11c 091063386452f11c0b913216e420dc11 78b75538e8ba1e705eb9177278b75538 52a0bf649f655584091063386452f11c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vminnm.f32 d15,d16,d20 cb08f38fa4bd2667566a1a5bab214fac 076940ac5744188fa8a40c59fc606654 7eaac24c5da22a0edfd577de7eaac24c dfd577defc606654566a1a5bab214fac 076940ac5744188fa8a40c59fc606654 7eaac24c5da22a0edfd577de7eaac24c fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 d15,d16,d20 b065b8d67d5449e0a0923d54b065b8d6 e22f2180d56fc20aba9ef245c6a0e3a4 3823ed0ef5e60f31e96742201f8b8b2a e9674220c6a0e3a4a0923d54b065b8d6 e22f2180d56fc20aba9ef245c6a0e3a4 3823ed0ef5e60f31e96742201f8b8b2a fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[2]
+vminnm.f32 d15,d16,d20 fd772f32d693feefa038d3bca01739b6 c46ea3fbf4eb6fd47c415e6804e4f82b b638078c388ce0ec388ce0ec4980022d 388ce0ec04e4f82ba038d3bca01739b6 c46ea3fbf4eb6fd47c415e6804e4f82b b638078c388ce0ec388ce0ec4980022d fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[0]
+vminnm.f32 d15,d16,d20 beba9e85844effeddeeb95e7beba9e85 933aa7c26cdc070c14d239054ab32810 664c70c1f23dc82aac2b65cef23dc82a ac2b65cef23dc82adeeb95e7beba9e85 933aa7c26cdc070c14d239054ab32810 664c70c1f23dc82aac2b65cef23dc82a fpscr=00000000
+vminnm.f32 d15,d16,d20 809b2345d1ebea66a8c2c6aee06d4a3c 07438a867b3ed8ac3471b4a4498bc0a1 b4b8ddba2e8428f224d63b53d6e0b976 24d63b53d6e0b976a8c2c6aee06d4a3c 07438a867b3ed8ac3471b4a4498bc0a1 b4b8ddba2e8428f224d63b53d6e0b976 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[3]
+vminnm.f32 d15,d16,d20 a4b5aaef8491569033b0ffb873965a54 f1a3b839455f7f4af1a3b83930e11841 a369d662799beb423836aa5ea4f5360e f1a3b839a4f5360e33b0ffb873965a54 f1a3b839455f7f4af1a3b83930e11841 a369d662799beb423836aa5ea4f5360e fpscr=00000000
+vminnm.f32 d15,d16,d20 6e471c996e361a9a9fa9ca126512a590 1b51e6858f5b6e116c8d1d61e4c1dd30 17c4ca0a540fabdec7520b92bffa5627 c7520b92e4c1dd309fa9ca126512a590 1b51e6858f5b6e116c8d1d61e4c1dd30 17c4ca0a540fabdec7520b92bffa5627 fpscr=00000000
+vminnm.f32 d15,d16,d20 f7997a4db0224cc897a4f64c156842fd 881c7682b5807b7758ed7657f0ed5f0a de7dce5479329dec4884a262f8773182 4884a262f877318297a4f64c156842fd 881c7682b5807b7758ed7657f0ed5f0a de7dce5479329dec4884a262f8773182 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vminnm.f32 d15,d16,d20 16125f00f365545d3e015eb0aa03b6d5 02fe905a8ff6e67dc91555430fbfe7b2 977b3e5152970bc61b245ca4cba3e9fd c9155543cba3e9fd3e015eb0aa03b6d5 02fe905a8ff6e67dc91555430fbfe7b2 977b3e5152970bc61b245ca4cba3e9fd fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vminnm.f32 d15,d16,d20 d60785e77f6b9f6ef1c6363e72716d5f 4cb3c4d024a6187f24a6187f6875a7cf ddd69145272ce28027c2d996d4b3be47 24a6187fd4b3be47f1c6363e72716d5f 4cb3c4d024a6187f24a6187f6875a7cf ddd69145272ce28027c2d996d4b3be47 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vminnm.f32 d15,d16,d20 94c4a3a01340d866eafdcd169cd8f6ee 95b6973f04ed747123a3c730ba2cfcde 847e87b3840ab8b5840ab8b5f30b41cf 840ab8b5f30b41cfeafdcd169cd8f6ee 95b6973f04ed747123a3c730ba2cfcde 847e87b3840ab8b5840ab8b5f30b41cf fpscr=00000000
+vminnm.f32 d15,d16,d20 4ee16e42966a36406a48cbca34265a57 cbc2cbb85de7b6254d87b0da626bc002 cb22d4d5a5e39dfb5b98b3a7ca18e35c 4d87b0daca18e35c6a48cbca34265a57 cbc2cbb85de7b6254d87b0da626bc002 cb22d4d5a5e39dfb5b98b3a7ca18e35c fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[3]
+vminnm.f32 d15,d16,d20 92f4774a8828db460f390a6878e1cf58 62c489c23f2fda779eb68bff6bb891ec 6d40aac9487b884bb37bd9e6487b884b b37bd9e6487b884b0f390a6878e1cf58 62c489c23f2fda779eb68bff6bb891ec 6d40aac9487b884bb37bd9e6487b884b fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 d15,d16,d20 7893adfa541fae48440a79457893adfa 70e9e46087bb7d5144824d9cc340e211 cfea81c3992967a93f9668d582bad44e 3f9668d5c340e211440a79457893adfa 70e9e46087bb7d5144824d9cc340e211 cfea81c3992967a93f9668d582bad44e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[3]
+vminnm.f32 q7, q8, q10 af593304cac5f4db3f7a65e17bca6f22 f082e9cb013fa42f013fa42f7c51d4e4 78f8293c697891435d05b3d5df82b2c7 f082e9cb013fa42f013fa42fdf82b2c7 f082e9cb013fa42f013fa42f7c51d4e4 78f8293c697891435d05b3d5df82b2c7 fpscr=00000000
+vminnm.f32 q7, q8, q10 b9b284ad1e04ffb4dbda23c718a8e15a e8b41b551743f6db9000c6b9cccaeaae 0bae0ff1ebe101f176c39fd4bcee1906 e8b41b55ebe101f19000c6b9cccaeaae e8b41b551743f6db9000c6b9cccaeaae 0bae0ff1ebe101f176c39fd4bcee1906 fpscr=00000000
+vminnm.f32 q7, q8, q10 9194616763e47e4417a35c9288715a68 ba0636201bb6ee7771e617b0294e9a44 acfa0a123c52751df0107429ae7e3c88 ba0636201bb6ee77f0107429ae7e3c88 ba0636201bb6ee7771e617b0294e9a44 acfa0a123c52751df0107429ae7e3c88 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[0]
+vminnm.f32 q7, q8, q10 23bb356afbb98d53756fa37723bb356a d9d7103d52311d40028d9a6b23ca658a 4946718d91893cae9ce434f83b852f0d d9d7103d91893cae9ce434f823ca658a d9d7103d52311d40028d9a6b23ca658a 4946718d91893cae9ce434f83b852f0d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vminnm.f32 q7, q8, q10 2f4d09438d8d3a1014b1d11d6ca9ad6c 1d3eaf6ce42a6fc9da735b996929531d 36d9e8fe75ce31a336d9e8fe786b8f04 1d3eaf6ce42a6fc9da735b996929531d 1d3eaf6ce42a6fc9da735b996929531d 36d9e8fe75ce31a336d9e8fe786b8f04 fpscr=00000000
+vminnm.f32 q7, q8, q10 8fd3a8095e5da8bbe5f6a84dd3c315d7 6ec70299b4b65de43291a9644d7c4d77 1e5d09abf7b68befd8ec42b6c7f96ac6 1e5d09abf7b68befd8ec42b6c7f96ac6 6ec70299b4b65de43291a9644d7c4d77 1e5d09abf7b68befd8ec42b6c7f96ac6 fpscr=00000000
+vminnm.f32 q7, q8, q10 46f2acbb9a176e4b0ee8d5d144d973e9 d449ffd56782b7e6689619b54caa98f3 dd6c5aaba55f46f4718c2e268a1858ce dd6c5aaba55f46f4689619b58a1858ce d449ffd56782b7e6689619b54caa98f3 dd6c5aaba55f46f4718c2e268a1858ce fpscr=00000000
+vminnm.f32 q7, q8, q10 8f670bc127b737083ccd153b549870b8 c47b1a19f206ab2014f8998d1302b016 f0dd2263c799c8b16c6421550dd00e43 f0dd2263f206ab2014f8998d0dd00e43 c47b1a19f206ab2014f8998d1302b016 f0dd2263c799c8b16c6421550dd00e43 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vminnm.f32 q7, q8, q10 d4660bde72d544618a81ccf98f6e6c54 8e5b3c1b537d55631b4cbd9ae283937d 6556870b3b6f5932c00e98c031af688d 8e5b3c1b3b6f5932c00e98c0e283937d 8e5b3c1b537d55631b4cbd9ae283937d 6556870b3b6f5932c00e98c031af688d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[0]
+vminnm.f32 q7, q8, q10 dc89569eb93484e1ba546b49ba546b49 57a38630d8c1e2db8f4838986d21b45e b3ce661022ec200422ec20045f56fbc6 b3ce6610d8c1e2db8f4838985f56fbc6 57a38630d8c1e2db8f4838986d21b45e b3ce661022ec200422ec20045f56fbc6 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vminnm.f32 q7, q8, q10 f14ddb1077227b6e58d6920c4d3182a8 15fc16fe2d822740d6950bf3a8ff53a4 399f110fedba28b1639d241676e182bc 15fc16feedba28b1d6950bf3a8ff53a4 15fc16fe2d822740d6950bf3a8ff53a4 399f110fedba28b1639d241676e182bc fpscr=00000000
+vminnm.f32 q7, q8, q10 0b382d7562e1a15bae5b931d3baebfec d1578cc1babf3ee2879d04fa25e31768 9ddd29852f66c1341382a52a4c220fef d1578cc1babf3ee2879d04fa25e31768 d1578cc1babf3ee2879d04fa25e31768 9ddd29852f66c1341382a52a4c220fef fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[3]
+vminnm.f32 q7, q8, q10 5899d153e997f64cf126a024d92f4c56 2c6e79d1a394e9a17b50c3ac7b50c3ac 39b53c8c042e692ed90ebc3c0aacb7b8 2c6e79d1a394e9a1d90ebc3c0aacb7b8 2c6e79d1a394e9a17b50c3ac7b50c3ac 39b53c8c042e692ed90ebc3c0aacb7b8 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[3]
+vminnm.f32 q7, q8, q10 06bef665c2737d2d2ff0b927cd74673a 281f1541292bb5bf11c57718c7376bcd 196df3e28e6a354a9f83ba9d194231d8 196df3e28e6a354a9f83ba9dc7376bcd 281f1541292bb5bf11c57718c7376bcd 196df3e28e6a354a9f83ba9d194231d8 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vminnm.f32 q7, q8, q10 a14023e501e2f0c2a14023e548a8d6d3 c1deeff8bd163e37596260b7d812a116 de5acb5bf30a462ba4242c5aedbb9070 de5acb5bf30a462ba4242c5aedbb9070 c1deeff8bd163e37596260b7d812a116 de5acb5bf30a462ba4242c5aedbb9070 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vminnm.f32 q7, q8, q10 fcfc5fbe422ab89a31194082daf69781 33794f2f4ef03d1c663f90ff9c81e48f 5cc9adb1de4439bf60a1c90debf1a644 33794f2fde4439bf60a1c90debf1a644 33794f2f4ef03d1c663f90ff9c81e48f 5cc9adb1de4439bf60a1c90debf1a644 fpscr=00000000
+vminnm.f32 q7, q8, q10 41a418d5b06307b06aa15c1bee67af09 20b982a3771fcb31065c0084aa1411a6 7a1c2639914cdcfcc2f5946d071f3602 20b982a3914cdcfcc2f5946daa1411a6 20b982a3771fcb31065c0084aa1411a6 7a1c2639914cdcfcc2f5946d071f3602 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[1]
+vminnm.f32 q7, q8, q10 5ecc11480a49c8d8a23de5f13567da1f 1e85a6005f30476d47c20b561a0a23d7 75505d3d0c10bf6bbcf9b20f75505d3d 1e85a6000c10bf6bbcf9b20f1a0a23d7 1e85a6005f30476d47c20b561a0a23d7 75505d3d0c10bf6bbcf9b20f75505d3d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vminnm.f32 q7, q8, q10 cad21082a17e8c2e23f9efe323f9efe3 b262117934d0faca399db34140aa03bd 51e504f7c964858d167891423a2fc026 b2621179c964858d167891423a2fc026 b262117934d0faca399db34140aa03bd 51e504f7c964858d167891423a2fc026 fpscr=00000000
+vminnm.f32 q7, q8, q10 be1749d9214c3e0a42e7e100357ac90a 96a8392b8eea7df670d0b04031017c00 347b2275f04d293f492dea92e63ab09e 96a8392bf04d293f492dea92e63ab09e 96a8392b8eea7df670d0b04031017c00 347b2275f04d293f492dea92e63ab09e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vminnm.f32 q7, q8, q10 b4ee284d0585eab3b2731a96760eed35 4e5aeeda21782661edf1af9c7246af84 caa502cc96995402ff5cd6f1c9516eb0 caa502cc96995402ff5cd6f1c9516eb0 4e5aeeda21782661edf1af9c7246af84 caa502cc96995402ff5cd6f1c9516eb0 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[3]
+vminnm.f32 q7, q8, q10 06ddef1a202594e078e4eb71bc55244f d1dbe1bc0c7127010982b8a50982b8a5 bd70b110f0d9b796e9824df4f0d9b796 d1dbe1bcf0d9b796e9824df4f0d9b796 d1dbe1bc0c7127010982b8a50982b8a5 bd70b110f0d9b796e9824df4f0d9b796 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vminnm.f32 q7, q8, q10 a6265627653622eb347a55fea66c079d 4fdb52a921ed7d1b19472c02f72fc744 0afb87621a33a6c4aad6eb7973c5eef4 0afb87621a33a6c4aad6eb79f72fc744 4fdb52a921ed7d1b19472c02f72fc744 0afb87621a33a6c4aad6eb7973c5eef4 fpscr=00000000
+vminnm.f32 q7, q8, q10 42af77e26e0db08b2d09c6ff00ee1181 977132dc67a7b0aab3d09d91d4338d90 1fe184f99c8d5eb9b972d40d15133ec0 977132dc9c8d5eb9b972d40dd4338d90 977132dc67a7b0aab3d09d91d4338d90 1fe184f99c8d5eb9b972d40d15133ec0 fpscr=00000000
+vminnm.f32 q7, q8, q10 8dd8dd6eb2a0ca0e0ec799f35503c906 a5ca7cdfc2546f8990cbdfb7ec9f977e aa78152b42960fc0a45333ccc2154d51 aa78152bc2546f89a45333ccec9f977e a5ca7cdfc2546f8990cbdfb7ec9f977e aa78152b42960fc0a45333ccc2154d51 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: 13056 calls, 13498 iters
+vminnm.f32 q7, q8, q10 b7d77cf4b7d77cf41897ca4b433b74b5 d767d0f75cf0a158e1d83b8799283ae7 0712b86fa266eb2c2f5532a1a0e8806e d767d0f7a266eb2ce1d83b87a0e8806e d767d0f75cf0a158e1d83b8799283ae7 0712b86fa266eb2c2f5532a1a0e8806e fpscr=00000000
+vminnm.f32 q7, q8, q10 1e3ff117a17c1b9a0cc3e2c495afd522 4182692b24be906b71a317956c3eedd8 4ffa22496d587c04f431210be0e40e44 4182692b24be906bf431210be0e40e44 4182692b24be906b71a317956c3eedd8 4ffa22496d587c04f431210be0e40e44 fpscr=00000000
+vminnm.f32 q7, q8, q10 2589c66b15ba976384770b3bb231f4e9 979334f699b79484b8634ecd12c53402 911f9ff59f225ccb418c97ad76828f71 979334f69f225ccbb8634ecd12c53402 979334f699b79484b8634ecd12c53402 911f9ff59f225ccb418c97ad76828f71 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vminnm.f32 q7, q8, q10 2691b466fef46a67f92b1febff507644 fd9893ec46502d490aa7068a39b24687 19eb9001674d155c33c5331593d34b04 fd9893ec46502d490aa7068a93d34b04 fd9893ec46502d490aa7068a39b24687 19eb9001674d155c33c5331593d34b04 fpscr=00000000
+vminnm.f32 q7, q8, q10 5510ac1202576ca17d12cc680de4b928 8661fc09f634f5ade9953ca012c69157 32fe3b7d61253496a6b0b94b7574271c 8661fc09f634f5ade9953ca012c69157 8661fc09f634f5ade9953ca012c69157 32fe3b7d61253496a6b0b94b7574271c fpscr=00000000
+vminnm.f32 q7, q8, q10 3f39c08811da333b33046730e5128699 461b9c3b25215a5e58d018f1a4421722 c9e424c5976b8d9afc2547a89ea363bc c9e424c5976b8d9afc2547a8a4421722 461b9c3b25215a5e58d018f1a4421722 c9e424c5976b8d9afc2547a89ea363bc fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[3]
+vminnm.f32 q7, q8, q10 74534e2af3655e21760a31f3760a31f3 9d00730c2825b488f7ef29c53a22685e 62bdd8654fe2f5142e1aaaca2e710334 9d00730c2825b488f7ef29c52e710334 9d00730c2825b488f7ef29c53a22685e 62bdd8654fe2f5142e1aaaca2e710334 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vminnm.f32 q7, q8, q10 84813a1f44d19586a5e8b448a3c7bcec a11fbfae7ee9f1156ba16b7467c03b96 e983b1c351991ad67dda8ffb7dda8ffb e983b1c351991ad66ba16b7467c03b96 a11fbfae7ee9f1156ba16b7467c03b96 e983b1c351991ad67dda8ffb7dda8ffb fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[2]
+vminnm.f32 q7, q8, q10 3e74c9a606f5ae8a6d070d983e74c9a6 f3c0263187457f0872477b17088a5492 635fc469b4e52b81237ed708b4e52b81 f3c02631b4e52b81237ed708b4e52b81 f3c0263187457f0872477b17088a5492 635fc469b4e52b81237ed708b4e52b81 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[2]
+vminnm.f32 q7, q8, q10 7d5b63ac260837b97d5b63aceb72ff28 67a90cd35fbefafc5bd4174ec05d25d1 82c80f1bf8a79116f8a79116e84da7fd 82c80f1bf8a79116f8a79116e84da7fd 67a90cd35fbefafc5bd4174ec05d25d1 82c80f1bf8a79116f8a79116e84da7fd fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 q7, q8, q10 5d977e009461885a8315b8ff5445cf39 8af8812669f6d6369d130ef98a734854 af177f40826b7b3ef269cc6140e1adef af177f40826b7b3ef269cc618a734854 8af8812669f6d6369d130ef98a734854 af177f40826b7b3ef269cc6140e1adef fpscr=00000000
+vminnm.f32 q7, q8, q10 17be0e3fd7dc4a37abfa5fb667fb774a b499e8f5d43569d809987bb430de1ca7 ab455f2b8b3104724335aee272ade533 b499e8f5d43569d809987bb430de1ca7 b499e8f5d43569d809987bb430de1ca7 ab455f2b8b3104724335aee272ade533 fpscr=00000000
+vminnm.f32 q7, q8, q10 ebbdf6452c14c25adc6fd4bf578a7ae6 d9896a4d50546afb42213864b80f98e8 a54388a55a365f04d5f4e9d2f1cd2a79 d9896a4d50546afbd5f4e9d2f1cd2a79 d9896a4d50546afb42213864b80f98e8 a54388a55a365f04d5f4e9d2f1cd2a79 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[2]
+vminnm.f32 q7, q8, q10 0d80ee3a7ae13dd49275faf32ac8585e 9ee6a816e6b98b396807b9450f0754b8 188864da60d78b398c32de1a188864da 9ee6a816e6b98b398c32de1a0f0754b8 9ee6a816e6b98b396807b9450f0754b8 188864da60d78b398c32de1a188864da fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 q7, q8, q10 f96966935026d2ffae64046529f4e316 749df956350a551ec096dab8a6bc80bb ab81306a6dfa5de3661a5f842bdb370c ab81306a350a551ec096dab8a6bc80bb 749df956350a551ec096dab8a6bc80bb ab81306a6dfa5de3661a5f842bdb370c fpscr=00000000
+vminnm.f32 q7, q8, q10 ccc83b6bcf4dd7ab3a33bf00aa346e2a f717da6320590803562dbf16a968ee18 f5fb2c5bdedf2a540c85451481f7a460 f717da63dedf2a540c854514a968ee18 f717da6320590803562dbf16a968ee18 f5fb2c5bdedf2a540c85451481f7a460 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vminnm.f32 q7, q8, q10 719d67d7662088ad429c054fa0e27189 36feb82a849183131e2d557acfbe44b2 42ba039e1b0cf2afbc85793c3ddaf63c 36feb82a84918313bc85793ccfbe44b2 36feb82a849183131e2d557acfbe44b2 42ba039e1b0cf2afbc85793c3ddaf63c fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 q7, q8, q10 5e215066e8a29f53bc323b961c61bdce 5709336246fd083994396122d39ea245 e56e48a8c26319d2a4915b1c5e83b35d e56e48a8c26319d2a4915b1cd39ea245 5709336246fd083994396122d39ea245 e56e48a8c26319d2a4915b1c5e83b35d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[2]
+vminnm.f32 q7, q8, q10 00f28517c2d01538a37cca258dd115d3 7d5f9f126d65804be72f14616a4d9cb6 cf3f67f44895ade6d0eef9c6da739fdc cf3f67f44895ade6e72f1461da739fdc 7d5f9f126d65804be72f14616a4d9cb6 cf3f67f44895ade6d0eef9c6da739fdc fpscr=00000000
+vminnm.f32 q7, q8, q10 d032fbff5585b1dfb371961437fd3cff 9a8185284416a7d4d90d2ce5a67db465 9f071e6eba1f8ce3291b768a944ad93e 9f071e6eba1f8ce3d90d2ce5a67db465 9a8185284416a7d4d90d2ce5a67db465 9f071e6eba1f8ce3291b768a944ad93e fpscr=00000000
+vminnm.f32 q7, q8, q10 e380143f474d2f21a6662bd0e8145d47 d8752ad74bb3033b3572ef972a649d68 08e918d038a99f9da1b173e572edb1da d8752ad738a99f9da1b173e52a649d68 d8752ad74bb3033b3572ef972a649d68 08e918d038a99f9da1b173e572edb1da fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[2]
+vminnm.f32 q7, q8, q10 32a79d2f5776ad9d17cfd5022cc237a8 df3d4a7042f5c979df3d4a7083aabd4b ce7ef43a33a96d699fe3e651ea040bce df3d4a7033a96d69df3d4a70ea040bce df3d4a7042f5c979df3d4a7083aabd4b ce7ef43a33a96d699fe3e651ea040bce fpscr=00000000
+vminnm.f32 q7, q8, q10 9755f485f82cee30373758a526535a37 d95ee1198480e4045c48f64a4a7f7d3a 1484e97a0a958449bf0859475b354c05 d95ee1198480e404bf0859474a7f7d3a d95ee1198480e4045c48f64a4a7f7d3a 1484e97a0a958449bf0859475b354c05 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vminnm.f32 q7, q8, q10 59c0717ad5df8ec03e8fac87da585a06 f722c7a943c765a7ebcf73081c3c8bf1 b17b6909323b419c0c067b5b323b419c f722c7a9323b419cebcf73081c3c8bf1 f722c7a943c765a7ebcf73081c3c8bf1 b17b6909323b419c0c067b5b323b419c fpscr=00000000
+vminnm.f32 q7, q8, q10 a968d0aa5a62d7133869247c1ffcfeaf da61a37210752f3815732c37a7a6c643 4df27aafb3731a19a13c06d76fec9ddf da61a372b3731a19a13c06d7a7a6c643 da61a37210752f3815732c37a7a6c643 4df27aafb3731a19a13c06d76fec9ddf fpscr=00000000
+vcvtn.s32.f32 d0, d20 e8d027cee9b2ebd002ba7e4bc6bb618e 9129c3b47d14f066ee78982ffb879866 e8d027cee9b2ebd08000000080000000 9129c3b47d14f066ee78982ffb879866 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtn.s32.f32 d0, d20 1948dae321bfff87368d9619ac2e37e6 a29868da2e7ac852ca1c7c18f4599244 1948dae321bfff87ffd8e0fa80000000 a29868da2e7ac852ca1c7c18f4599244 fpscr=00000000
+vcvtn.s32.f32 d0, d20 bbb98c91e46f896fd3402178b7e59563 61c7bb692aac01ee384ca72b8daaf54e bbb98c91e46f896f0000000000000000 61c7bb692aac01ee384ca72b8daaf54e fpscr=00000000
+vcvtn.s32.f32 d0, d20 19de0aceb11f7375724c36edb4a148d9 3f52d49533087bdc827bf99ad6fddd9b 19de0aceb11f73750000000080000000 3f52d49533087bdc827bf99ad6fddd9b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.s32.f32 d0, d20 4cae2bdb0165af5359046e1e4c6b80a1 665685ffe180a6c3665685ff976f6bfb 4cae2bdb0165af537fffffff00000000 665685ffe180a6c3665685ff976f6bfb fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtn.s32.f32 d0, d20 2449e73771ff9afb3a23c26a9deb1449 f6fc87e3df09f17a046ddc5d046ddc5d 2449e73771ff9afb0000000000000000 f6fc87e3df09f17a046ddc5d046ddc5d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[2]
+vcvtn.s32.f32 d0, d20 4b4aa42b8b8cb9784b4aa42b46a428ac ef769616ef76961693e265132a95763c 4b4aa42b8b8cb9780000000000000000 ef769616ef76961693e265132a95763c fpscr=00000000
+vcvtn.s32.f32 d0, d20 f929f3d4c3fd3dac85bb7783ad9c9a27 e0e4721999f22ef95018b5627c4470b8 f929f3d4c3fd3dac7fffffff7fffffff e0e4721999f22ef95018b5627c4470b8 fpscr=00000000
+vcvtn.s32.f32 d0, d20 facb20922b28fbda1ed9a8e099d79a03 f08cb7e7b388369d949426814dffdb3b facb20922b28fbda000000001ffb6760 f08cb7e7b388369d949426814dffdb3b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[3]
+vcvtn.s32.f32 d0, d20 5d88372a79062efc57c00b9a86695cdb 204b265ee33aaa8bb09eece2e33aaa8b 5d88372a79062efc0000000080000000 204b265ee33aaa8bb09eece2e33aaa8b fpscr=00000000
+vcvtn.s32.f32 d0, d20 07f5c6e5c51af73f111b370da182c1d7 ad4b09db0d549560f6e04af207c604d9 07f5c6e5c51af73f8000000000000000 ad4b09db0d549560f6e04af207c604d9 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtn.s32.f32 d0, d20 342fcfa7fdf51b7615d7a5f5fdf51b76 6aa97cf43643669f281206d02b218225 342fcfa7fdf51b760000000000000000 6aa97cf43643669f281206d02b218225 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.s32.f32 d0, d20 3c23f8ccce9b03334360527eef830a40 e390be3fc2472537e390be3fb1610be9 3c23f8ccce9b03338000000000000000 e390be3fc2472537e390be3fb1610be9 fpscr=00000000
+vcvtn.s32.f32 d0, d20 c705a97b7f46913a3aebd605136e14c2 f17616b37b4823362168cff945b20746 c705a97b7f46913a0000000000001641 f17616b37b4823362168cff945b20746 fpscr=00000000
+vcvtn.s32.f32 d0, d20 4669075a5b83c8b6718a0026cac91aad b77fd4a98688167b08cd7f2e7157f39e 4669075a5b83c8b6000000007fffffff b77fd4a98688167b08cd7f2e7157f39e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[1]
+vcvtn.s32.f32 d0, d20 ee8d186cd39a1fd9ee8d186ca1726947 92e1c992bc5a33a5e139b43df8b35987 ee8d186cd39a1fd98000000080000000 92e1c992bc5a33a5e139b43df8b35987 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtn.s32.f32 d0, d20 bb043da3fb9445656f1cf9c7de9cf637 856a78b503121a87201e02d5856a78b5 bb043da3fb9445650000000000000000 856a78b503121a87201e02d5856a78b5 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[2]
+vcvtn.s32.f32 d0, d20 32d00c12a9a26c30a163235a32d00c12 5dc63fabd0074cbcd0074cbcf9d1662f 32d00c12a9a26c308000000080000000 5dc63fabd0074cbcd0074cbcf9d1662f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtn.s32.f32 d0, d20 61de638fcfc675b1f7ac9f4960437a57 59614594c5d13f0559614594a9ea4000 61de638fcfc675b17fffffff00000000 59614594c5d13f0559614594a9ea4000 fpscr=00000000
+vcvtn.s32.f32 d0, d20 f037cac0beb92ea8979ad41cbb947b72 f2c5f87ee1fbb8cb45a182b5c9e83e07 f037cac0beb92ea800001430ffe2f83f f2c5f87ee1fbb8cb45a182b5c9e83e07 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.s32.f32 d0, d20 dcb96e1b17bd15bd605d6fe12901b9b3 4dfd3e5dd8d52f434dfd3e5d25e15310 dcb96e1b17bd15bd1fa7cba000000000 4dfd3e5dd8d52f434dfd3e5d25e15310 fpscr=00000000
+vcvtn.s32.f32 d0, d20 54cb3818436640aaf687671b2b17471b 8a7f403731c489242f3c8168f66ce45d 54cb3818436640aa0000000080000000 8a7f403731c489242f3c8168f66ce45d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtn.s32.f32 d0, d20 a7bca564a7bca564123bb6f4aeb5cddc e9c73ad9943f3304bc94a7d29417abbb a7bca564a7bca5640000000000000000 e9c73ad9943f3304bc94a7d29417abbb fpscr=00000000
+vcvtn.s32.f32 d0, d20 25ed26d369513433db3ae55b44695ee1 8418e9017d0b161b19337d2c6d60ba0d 25ed26d369513433000000007fffffff 8418e9017d0b161b19337d2c6d60ba0d fpscr=00000000
+vcvtn.s32.f32 d0, d20 b71dab056513223799a245fe510cb3b6 4607aaf431f74bb589e5a1d382f69e0f b71dab05651322370000000000000000 4607aaf431f74bb589e5a1d382f69e0f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.s32.f32 d0, d20 a6e8ecf5994f53f3668fd30b9f6c2660 e727d9e2e727d9e2d9fec3ebe7b4a398 a6e8ecf5994f53f38000000080000000 e727d9e2e727d9e2d9fec3ebe7b4a398 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vcvtn.s32.f32 d0, d20 18b51d93d2fbe430c70460cfc70460cf 93d2bd7a6e84e22b1b2f75896e84e22b 18b51d93d2fbe430000000007fffffff 93d2bd7a6e84e22b1b2f75896e84e22b fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: 13312 calls, 13761 iters
+vcvtn.s32.f32 d0, d20 a24d20f22ca4e460311d699a8ca5b39c cc78987601b70f9f4a19779dd832cf06 a24d20f22ca4e46000265de780000000 cc78987601b70f9f4a19779dd832cf06 fpscr=00000000
+vcvtn.s32.f32 d0, d20 6d325902a9cb8c2e4b32516aa7335334 c4bae7315c46efdc473e1d742c5b2d09 6d325902a9cb8c2e0000be1d00000000 c4bae7315c46efdc473e1d742c5b2d09 fpscr=00000000
+vcvtn.s32.f32 d0, d20 713d4ebca3ab4ec21bff1f9c0f15599f 6a58e85df9f87371126bfabfbcb7546c 713d4ebca3ab4ec20000000000000000 6a58e85df9f87371126bfabfbcb7546c fpscr=00000000
+vcvtn.s32.f32 d0, d20 4286febd435a47de9f2371edbc04ba78 f5e7550f2cf8848ab0147636eb57ce84 4286febd435a47de0000000080000000 f5e7550f2cf8848ab0147636eb57ce84 fpscr=00000000
+vcvtn.s32.f32 d0, d20 6a4b88773e928af230645429bf7a2365 03588d559ace04518d4b04a4c96dcfe3 6a4b88773e928af200000000fff12302 03588d559ace04518d4b04a4c96dcfe3 fpscr=00000000
+vcvtn.s32.f32 d0, d20 6360d58a05512d7e0c5970ee993bd57f 132879da50d49149dd9fe5456fb14809 6360d58a05512d7e800000007fffffff 132879da50d49149dd9fe5456fb14809 fpscr=00000000
+vcvtn.s32.f32 d0, d20 8b321ba157076e0f87c0d2ca0abc1193 cacf17f41b4b31f419cff5159eb9d94c 8b321ba157076e0f0000000000000000 cacf17f41b4b31f419cff5159eb9d94c fpscr=00000000
+vcvtn.s32.f32 d0, d20 7dc0c53138a13a1fa8a50e385178d83c 0997ec02ced0e2dd5de2586c3ea99a1a 7dc0c53138a13a1f7fffffff00000000 0997ec02ced0e2dd5de2586c3ea99a1a fpscr=00000000
+vcvtn.s32.f32 d0, d20 c360b7194a7910d21974c580b61a14e4 f2d74e37583605f9aa9c090ab94fcea2 c360b7194a7910d20000000000000000 f2d74e37583605f9aa9c090ab94fcea2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtn.s32.f32 d0, d20 7c264d937c264d9380e68e738d8d1ca2 e962c28197bec9b7b072fd55497a3e94 7c264d937c264d9300000000000fa3e9 e962c28197bec9b7b072fd55497a3e94 fpscr=00000000
+vcvtn.s32.f32 d0, d20 e66917efb13f2926ca9435ce3a0c80e6 124b8e212c402b8dd9c8532eebddd756 e66917efb13f29268000000080000000 124b8e212c402b8dd9c8532eebddd756 fpscr=00000000
+vcvtn.s32.f32 d0, d20 d8c899d39c0d866eeb2856c87ce84c36 4987e62b72cb43e9655a86a78308729d d8c899d39c0d866e7fffffff00000000 4987e62b72cb43e9655a86a78308729d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtn.s32.f32 d0, d20 de04636bc4ae7cd8fd0840c9e9acd83a 16494db597162d46154d07957211b32d de04636bc4ae7cd8000000007fffffff 16494db597162d46154d07957211b32d fpscr=00000000
+vcvtn.s32.f32 d0, d20 954f50d62ab99b8e422adb1f55cd817a dc20163693b0ea4a967a9cc322f70aff 954f50d62ab99b8e0000000000000000 dc20163693b0ea4a967a9cc322f70aff fpscr=00000000
+vcvtn.s32.f32 d0, d20 e6e12ee56b1ea2365bc5eb57534fef8a 328166eae5b068dccaf1c83f911f2771 e6e12ee56b1ea236ff871be000000000 328166eae5b068dccaf1c83f911f2771 fpscr=00000000
+vcvtn.s32.f32 d0, d20 b7941b107a2e0eb003ef005657405947 190e78985465175763d958a6e599570f b7941b107a2e0eb07fffffff80000000 190e78985465175763d958a6e599570f fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[1]
+vcvtn.s32.f32 d0, d20 8807e6ec63156977dda5400a6239bedf 4b7758cc7668e4fa4b7758cc79a0672f 8807e6ec6315697700f758cc7fffffff 4b7758cc7668e4fa4b7758cc79a0672f fpscr=00000000
+vcvtn.s32.f32 d0, d20 69c9f89102cafa9f29e71eb7eb00a837 983f744d77759a0146c312ca353ecded 69c9f89102cafa9f0000618900000000 983f744d77759a0146c312ca353ecded fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtn.s32.f32 d0, d20 c79bcc5798900aac8bd5049e3ba2506a 40a8b27a6beddcb0e6c72a02c940ef31 c79bcc5798900aac80000000fff3f10d 40a8b27a6beddcb0e6c72a02c940ef31 fpscr=00000000
+vcvtn.s32.f32 d0, d20 7ce9a7fe4c74632ef8d0648f63ab9c69 9c2f61bc0e33b2e83140b74ff3b1f139 7ce9a7fe4c74632e0000000080000000 9c2f61bc0e33b2e83140b74ff3b1f139 fpscr=00000000
+vcvtn.s32.f32 d0, d20 b17829aecf88572078b37365d06b2ea4 8e0e1f65411e028e1fdb3c344d8a5dc7 b17829aecf88572000000000114bb8e0 8e0e1f65411e028e1fdb3c344d8a5dc7 fpscr=00000000
+vcvtn.s32.f32 d0, d20 b93db5ae0f5bfa615985b13517335622 287afd6a491a6cac201e39219c4ebfeb b93db5ae0f5bfa610000000000000000 287afd6a491a6cac201e39219c4ebfeb fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtn.s32.f32 d0, d20 eb196ddc2c3778122b7a0a347dbf141c 959e936970c54051cc3dadcb178ee6d5 eb196ddc2c377812fd0948d400000000 959e936970c54051cc3dadcb178ee6d5 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvta.s32.f32 d5, d25 2107cfe80b56122a1b0e432b70a566b4 a2ca2a31352c3d5fa2ca2a31b586f5d7 00000000000000001b0e432b70a566b4 a2ca2a31352c3d5fa2ca2a31b586f5d7 fpscr=00000000
+vcvta.s32.f32 d5, d25 3c7f303c68a6468a0ed04021225324d4 288326fd977a13196a5c4415deca6862 00000000000000000ed04021225324d4 288326fd977a13196a5c4415deca6862 fpscr=00000000
+vcvta.s32.f32 d5, d25 c2f608fb3a0510b557bdece6f3514170 65bd3d189981e573509ccfa47f7e0f62 7fffffff0000000057bdece6f3514170 65bd3d189981e573509ccfa47f7e0f62 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[2]
+vcvta.s32.f32 d5, d25 8f6b76fa73c7b0be1c618d00b41b29b6 d3fb715d79ab0af7d3fb715d12434a1d 800000007fffffff1c618d00b41b29b6 d3fb715d79ab0af7d3fb715d12434a1d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvta.s32.f32 d5, d25 d772292b53cf041e87c012df0cc3d2cb cc3512ea2b3d7a328ae2731b9bdecf31 fd2bb4580000000087c012df0cc3d2cb cc3512ea2b3d7a328ae2731b9bdecf31 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvta.s32.f32 d5, d25 5de6189d9d4f03242729b79630b0ca78 259eaf116b05ea8858abbd3c4b61a2ee 000000007fffffff2729b79630b0ca78 259eaf116b05ea8858abbd3c4b61a2ee fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvta.s32.f32 d5, d25 e8e6059f1bdfecd87bfe094fdee12927 087e07332014fe95031ed8f5031ed8f5 00000000000000007bfe094fdee12927 087e07332014fe95031ed8f5031ed8f5 fpscr=00000000
+vcvta.s32.f32 d5, d25 0a53bc02e5653c18f74345630cb84732 c135b50071b99bc148b6cce412777f92 fffffff57ffffffff74345630cb84732 c135b50071b99bc148b6cce412777f92 fpscr=00000000
+vcvta.s32.f32 d5, d25 1ed381d99774639bcf27d29a0dfc4cf9 711efc19160da5d0486f299f91f38569 7fffffff00000000cf27d29a0dfc4cf9 711efc19160da5d0486f299f91f38569 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvta.s32.f32 d5, d25 4d2b02f7eb06ffcdb3467381114c0a4b 7ca21255c6233292700c3ee0a5979177 7fffffffffffd733b3467381114c0a4b 7ca21255c6233292700c3ee0a5979177 fpscr=00000000
+vcvta.s32.f32 d5, d25 916791b4aaba219e10893df86becbfa9 c610d60ff7b25975f3475dc69e50ad93 ffffdbca8000000010893df86becbfa9 c610d60ff7b25975f3475dc69e50ad93 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.s32.f32 d5, d25 b5ae01eb436fbc73975ad1bdf2047588 e2ceb7e446e85255470497bb78e51566 8000000000007429975ad1bdf2047588 e2ceb7e446e85255470497bb78e51566 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[2]
+vcvta.s32.f32 d5, d25 d48390d0639c2153639c215378ac9e82 2dfa8f66cbf5fde8e51258aa2dfa8f66 00000000fe140430639c215378ac9e82 2dfa8f66cbf5fde8e51258aa2dfa8f66 fpscr=00000000
+vcvta.s32.f32 d5, d25 1435b0e9a2453e9f61b120f3a66c1ded 9c50471fbf4653d5a23d679f8eae9501 00000000ffffffff61b120f3a66c1ded 9c50471fbf4653d5a23d679f8eae9501 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.s32.f32 d5, d25 0c274fb8352d55cc447ca0682a4e00a7 d11689ea420af7033d8cb420420af703 8000000000000023447ca0682a4e00a7 d11689ea420af7033d8cb420420af703 fpscr=00000000
+vcvta.s32.f32 d5, d25 4eeec21ff2ad6d933347d422fa903eb0 cf2b9ed9e3b6b1802ea25225a04e9403 80000000800000003347d422fa903eb0 cf2b9ed9e3b6b1802ea25225a04e9403 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.s32.f32 d5, d25 a9a40bf7bc84c4bfccc733b80cc652f2 13c1b59ca4b95aa593eb8526c567d731 0000000000000000ccc733b80cc652f2 13c1b59ca4b95aa593eb8526c567d731 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvta.s32.f32 d5, d25 032f682e9aa3d3495b4c029acce570b6 991f03db778f5e5111c81e37a7005973 000000007fffffff5b4c029acce570b6 991f03db778f5e5111c81e37a7005973 fpscr=00000000
+vcvta.s32.f32 d5, d25 fab8617aa3045e8da7499a966cabc46e 02db84042c34f82a09e0c17265fe1b1e 0000000000000000a7499a966cabc46e 02db84042c34f82a09e0c17265fe1b1e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvta.s32.f32 d5, d25 5a11242546b63b9f96845c8043f5c890 2561866c9d6f62cbbd8edf719d19d599 000000000000000096845c8043f5c890 2561866c9d6f62cbbd8edf719d19d599 fpscr=00000000
+vcvta.s32.f32 d5, d25 529de79367d1c4d339817a83eea6abb5 14be9e9b1493aee64d8460c44584a863 000000000000000039817a83eea6abb5 14be9e9b1493aee64d8460c44584a863 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.s32.f32 d5, d25 8ece12c539f59d4039f59d40bdeef6fd 013d6284d48d30b9fa6101d6ed3179a3 000000008000000039f59d40bdeef6fd 013d6284d48d30b9fa6101d6ed3179a3 fpscr=00000000
+vcvta.s32.f32 d5, d25 a3e92ae2309c490efc846864c08d7139 dc9331074c7a057b47fd2ca77a549096 8000000003e815ecfc846864c08d7139 dc9331074c7a057b47fd2ca77a549096 fpscr=00000000
+vcvta.s32.f32 d5, d25 29820855518361865870869b2c5ee8e9 0799d581747837d94821936f613c4997 000000007fffffff5870869b2c5ee8e9 0799d581747837d94821936f613c4997 fpscr=00000000
+vcvta.s32.f32 d5, d25 74c9cdbb87af17ae96b24cc4047dc544 4bb63993ba6a7af991fb0d0635108e41 016c73260000000096b24cc4047dc544 4bb63993ba6a7af991fb0d0635108e41 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[2]
+vcvta.s32.f32 d5, d25 79d9e89857533c67a3019fbd897fd322 f66efc42f66efc42b0ef1c227ca5d887 8000000080000000a3019fbd897fd322 f66efc42f66efc42b0ef1c227ca5d887 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvta.s32.f32 d5, d25 fd0742da99f8beecfbe1d01f1b2a82c2 d5b2c4ca78d0673ab0fab2a29e778517 800000007ffffffffbe1d01f1b2a82c2 d5b2c4ca78d0673ab0fab2a29e778517 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvta.s32.f32 d5, d25 cc3d7a303ac73f42cc3d7a3011541b8d d3ea3c5dd0b77e28acc80299703482a7 8000000080000000cc3d7a3011541b8d d3ea3c5dd0b77e28acc80299703482a7 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvta.s32.f32 d5, d25 4a8450af0e9c70e2a7d073a84a8450af 5228531553a960960f62a44af034038e 7fffffff7fffffffa7d073a84a8450af 5228531553a960960f62a44af034038e fpscr=00000000
+vcvta.s32.f32 d5, d25 dc0dc728e939ec40cfd282820b8653ab c330ff3cde6397ee382655d968bf4aef ffffff4f80000000cfd282820b8653ab c330ff3cde6397ee382655d968bf4aef fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvta.s32.f32 d5, d25 67677fc4e8d0f6954cc7e6d307c26d7f d1d56fbfe59cb4d8d1d56fbfd6345f5e 80000000800000004cc7e6d307c26d7f d1d56fbfe59cb4d8d1d56fbfd6345f5e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvta.s32.f32 d5, d25 debce70d315f83bbbadd5b89debce70d bc3b51e54362b25834edcb96ca49dda4 00000000000000e3badd5b89debce70d bc3b51e54362b25834edcb96ca49dda4 fpscr=00000000
+vcvta.s32.f32 d5, d25 da89a974b76cdd5cc6bc8036ab75178a 1c654903a47347780bae9ba123e41aed 0000000000000000c6bc8036ab75178a 1c654903a47347780bae9ba123e41aed fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.s32.f32 d5, d25 546d05f7bad43230bad43230bdc47ec2 00ed527a06378161aa8356f1bbbabfaa 0000000000000000bad43230bdc47ec2 00ed527a06378161aa8356f1bbbabfaa fpscr=00000000
+vcvta.s32.f32 d5, d25 148f0a3fb53f2caa9da241254780287b ca865796d9ed524893489fb24ef97896 ffbcd435800000009da241254780287b ca865796d9ed524893489fb24ef97896 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvta.s32.f32 d5, d25 8c949e983da1c96b2fba2f03209afee3 deb34758d59f0447ba687307ba687307 80000000800000002fba2f03209afee3 deb34758d59f0447ba687307ba687307 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.s32.f32 d5, d25 c0a73a6297a07adcfbe8cbd256227927 6d3c17e176b1d7d715118335481ef07f 7fffffff7ffffffffbe8cbd256227927 6d3c17e176b1d7d715118335481ef07f fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvta.s32.f32 d5, d25 56b2a9027cc243fc9c391d4bc0e42431 966610f090ae261e86b7769786b77697 00000000000000009c391d4bc0e42431 966610f090ae261e86b7769786b77697 fpscr=00000000
+vcvta.s32.f32 d5, d25 d7f012eb7aa087435a14c1972eb1b852 f663ba43e4d4c2d9bd9fc2c3cf52414b 80000000800000005a14c1972eb1b852 f663ba43e4d4c2d9bd9fc2c3cf52414b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.s32.f32 d5, d25 a67c574ea95d4b50b81d0516a95d4b50 eb79288b373efc154b72d136ab71e304 8000000000000000b81d0516a95d4b50 eb79288b373efc154b72d136ab71e304 fpscr=00000000
+vcvta.s32.f32 d5, d25 8d637e1428d579183b8772353dfd6a3f c31217370a011bbd8740b729670dd5a4 ffffff6e000000003b8772353dfd6a3f c31217370a011bbd8740b729670dd5a4 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[2]
+randV128: 13568 calls, 14026 iters
+vcvta.s32.f32 d5, d25 34ef517fa09363b3104022660f5108fe af2fbd52903a12766f8291e93672aaf2 0000000000000000104022660f5108fe af2fbd52903a12766f8291e93672aaf2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[3]
+vcvta.s32.f32 d5, d25 3c3d2b430b43f4acf46f3946c3400eb5 f44177748823b69b36c02d44da5a6526 8000000000000000f46f3946c3400eb5 f44177748823b69b36c02d44da5a6526 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.s32.f32 d5, d25 caace0b6a04822c76bbd497cb3c38af1 3fd1c1d49821ef2133b613b0899e40e8 00000002000000006bbd497cb3c38af1 3fd1c1d49821ef2133b613b0899e40e8 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvta.s32.f32 d5, d25 6e689051586c9d0b22a4e0c525cca7f1 257284a8acda8435e8bda75fb56bf093 000000000000000022a4e0c525cca7f1 257284a8acda8435e8bda75fb56bf093 fpscr=00000000
+vcvta.s32.f32 d5, d25 c0059b7263e4253313c31c6d2f84deb3 26d8a13a1d1920f06b40298754480ed3 000000000000000013c31c6d2f84deb3 26d8a13a1d1920f06b40298754480ed3 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvta.s32.f32 d5, d25 adec28ea1539d8d9660f62834d39ab45 0952db9d1da76ec79a96cdb7650b7f33 0000000000000000660f62834d39ab45 0952db9d1da76ec79a96cdb7650b7f33 fpscr=00000000
+vcvta.s32.f32 d5, d25 03b1984cb7a96b7a4d8f64ff29cd1bd5 eb3bd2cad7f9087c5401b243cb238930 80000000800000004d8f64ff29cd1bd5 eb3bd2cad7f9087c5401b243cb238930 fpscr=00000000
+vcvta.s32.f32 d5, d25 c26d77614eff34a6b1222db08b90dd3f 24492b7be153a67c5c61dae0a544b623 0000000080000000b1222db08b90dd3f 24492b7be153a67c5c61dae0a544b623 fpscr=00000000
+vcvta.s32.f32 d5, d25 9e50a00715aa85b60a6b0d74af8ac9fb 63602b281909e55ba6596b89a5245180 7fffffff000000000a6b0d74af8ac9fb 63602b281909e55ba6596b89a5245180 fpscr=00000000
+vcvtp.s32.f32 d10, d30 b5473b5d7c1fac6e5e09a785c5636790 82eb3db81435cdb2d38f673f8430cebf b5473b5d7c1fac6e8000000000000000 82eb3db81435cdb2d38f673f8430cebf fpscr=00000000
+vcvtp.s32.f32 d10, d30 51a9e0e2aaf8ebaf39cb17955f46f3c6 689284e91a801f142d40023446a5ff64 51a9e0e2aaf8ebaf0000000100005300 689284e91a801f142d40023446a5ff64 fpscr=00000000
+vcvtp.s32.f32 d10, d30 ac8c2be11cdb4ddd6442f0cf3432415e b43c0ce55a3f400886b2d3de8ce2ab0d ac8c2be11cdb4ddd0000000000000000 b43c0ce55a3f400886b2d3de8ce2ab0d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtp.s32.f32 d10, d30 79a99dd603eff320f245669479a99dd6 ccec7d8a7e23b7d9b2cfc8bd6e4eeb6a 79a99dd603eff320000000007fffffff ccec7d8a7e23b7d9b2cfc8bd6e4eeb6a fpscr=00000000
+vcvtp.s32.f32 d10, d30 20666f5d6a313a9f68da45b30b081de9 d828389de3d59c09573e08c600e9710d 20666f5d6a313a9f7fffffff00000001 d828389de3d59c09573e08c600e9710d fpscr=00000000
+vcvtp.s32.f32 d10, d30 ece9388014917889b19a8b120c1e64c9 e0438d83769c42466651652d906725c2 ece93880149178897fffffff00000000 e0438d83769c42466651652d906725c2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vcvtp.s32.f32 d10, d30 1456cb4d380e9b3d8b4ce4091456cb4d 18618b5b35258f47c1c44fea94ea36c2 1456cb4d380e9b3dffffffe800000000 18618b5b35258f47c1c44fea94ea36c2 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.s32.f32 d10, d30 730dea338874e69d654268912bc2989d a0339c73744cbf52744cbf5227ccbbb7 730dea338874e69d7fffffff00000001 a0339c73744cbf52744cbf5227ccbbb7 fpscr=00000000
+vcvtp.s32.f32 d10, d30 c26e4789315aba32958fa43d027b3a32 d26211d7f1576225f9f4d33c6a4e4eed c26e4789315aba32800000007fffffff d26211d7f1576225f9f4d33c6a4e4eed fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.s32.f32 d10, d30 288cdf8a20206493d78030fb20206493 ca4ebecd391de9d0d87c40b3ccc6a406 288cdf8a2020649380000000f9cadfd0 ca4ebecd391de9d0d87c40b3ccc6a406 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[3]
+vcvtp.s32.f32 d10, d30 1d661e167441dc4e7441dc4e3a411088 ed7f0e990afa9f01f421cd6b0fb9de5d 1d661e167441dc4e8000000000000001 ed7f0e990afa9f01f421cd6b0fb9de5d fpscr=00000000
+vcvtp.s32.f32 d10, d30 72bffdffadcd1d14651abf2935409753 75f8c1fb9abbd5d4ec32a6a9047b95ff 72bffdffadcd1d148000000000000001 75f8c1fb9abbd5d4ec32a6a9047b95ff fpscr=00000000
+vcvtp.s32.f32 d10, d30 a5385164eafc27d611277a2f4390ca07 6f2e65d0159090aab6b7cc5bb2991b3a a5385164eafc27d60000000000000000 6f2e65d0159090aab6b7cc5bb2991b3a fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtp.s32.f32 d10, d30 adca8e945f40f82ab42619c46859f0ba f8b33e5e103f6487a9b26599415f32f2 adca8e945f40f82a000000000000000e f8b33e5e103f6487a9b26599415f32f2 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtp.s32.f32 d10, d30 3e9fa69a92687a774f128580890ad36c 241471406e81e60e4fdfdbcd7439ce57 3e9fa69a92687a777fffffff7fffffff 241471406e81e60e4fdfdbcd7439ce57 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtp.s32.f32 d10, d30 6f8466f7afe30d843a5a7b73b4895fed e7baa8be1676a5e501040f4fc046ad24 6f8466f7afe30d8400000001fffffffd e7baa8be1676a5e501040f4fc046ad24 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtp.s32.f32 d10, d30 64de919424dcce0941cb0252e756b227 b2e4051c6d473b34a5784d4942fc5266 64de919424dcce09000000000000007f b2e4051c6d473b34a5784d4942fc5266 fpscr=00000000
+vcvtp.s32.f32 d10, d30 e3b03e880f56d3d2150218da090f5428 a33a9e6122693a3cff10fc8f8d57d984 e3b03e880f56d3d28000000000000000 a33a9e6122693a3cff10fc8f8d57d984 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.s32.f32 d10, d30 66bbe0066b97847f8892d8222a9c132e c70903cccde0b252c18afe20cde0b252 66bbe0066b97847fffffffefe3e9b5c0 c70903cccde0b252c18afe20cde0b252 fpscr=00000000
+vcvtp.s32.f32 d10, d30 71f1344b7d9d41ad6e8fc057ac9ab2d1 af6feac66b12302a3801b78cb89edb12 71f1344b7d9d41ad0000000100000000 af6feac66b12302a3801b78cb89edb12 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.s32.f32 d10, d30 25cfe1b6e31bc80fe31bc80f0c60c350 b2cc61ece383675be59d9bd260ae743e 25cfe1b6e31bc80f800000007fffffff b2cc61ece383675be59d9bd260ae743e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtp.s32.f32 d10, d30 c479e4ffc479e4ffd7f8136d0d154829 0c62397fb44cc35fbb0e65cfb2bc18f8 c479e4ffc479e4ff0000000000000000 0c62397fb44cc35fbb0e65cfb2bc18f8 fpscr=00000000
+vcvtp.s32.f32 d10, d30 836692a2d9f94558f7417d86e0508e03 a156aadab56e463dc36900034d41adef 836692a2d9f94558ffffff170c1adef0 a156aadab56e463dc36900034d41adef fpscr=00000000
+vcvtp.s32.f32 d10, d30 cb8efff1ea7fd791d729e78f7d46d10b 196eaef91cf561406d5e2798a4f4843d cb8efff1ea7fd7917fffffff00000000 196eaef91cf561406d5e2798a4f4843d fpscr=00000000
+vcvtp.s32.f32 d10, d30 8db92c261b9cc1d5a5ad3a081591bdef 9ef94c0a3eb4c76fcaff94518adf0ac2 8db92c261b9cc1d5ff8035d800000000 9ef94c0a3eb4c76fcaff94518adf0ac2 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtp.s32.f32 d10, d30 4ffece8c8c8a2352c7fc786aa864c623 4b622f55a42991d1f003bf894a6b5664 4ffece8c8c8a235280000000003ad599 4b622f55a42991d1f003bf894a6b5664 fpscr=00000000
+vcvtp.s32.f32 d10, d30 e1eb6f55808192120ddb9e2da093e4bc 73dd892175574f103e40069df06df010 e1eb6f55808192120000000180000000 73dd892175574f103e40069df06df010 fpscr=00000000
+vcvtp.s32.f32 d10, d30 3e203c42da8d6c7205180626e06e7c93 f432e051ddbc86837d867f490557a6b5 3e203c42da8d6c727fffffff00000001 f432e051ddbc86837d867f490557a6b5 fpscr=00000000
+vcvtp.s32.f32 d10, d30 f962d27ba55fe68dd110c18e54430d19 0da3e68b202d6df2fa325c15ba96b96b f962d27ba55fe68d8000000000000000 0da3e68b202d6df2fa325c15ba96b96b fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtp.s32.f32 d10, d30 871c5368871c5368018c6fb52853ce87 7348fc1530ccb54a1aac3e3561c9aba0 871c5368871c5368000000017fffffff 7348fc1530ccb54a1aac3e3561c9aba0 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.s32.f32 d10, d30 36d165124a57dacef06960b298eeb289 4a1ff60f1cbe66ff7ec56cd5226a2eab 36d165124a57dace7fffffff00000001 4a1ff60f1cbe66ff7ec56cd5226a2eab fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[3]
+vcvtp.s32.f32 d10, d30 a3e024d0eefe9a4aeefe9a4ace6912cf 0c741d448b7382ce8157d7380c741d44 a3e024d0eefe9a4a0000000000000001 0c741d448b7382ce8157d7380c741d44 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[2]
+vcvtp.s32.f32 d10, d30 e7c6409b6131abbabbbe3ee7def9373e c169bd6ae49ae989e49ae98976da4654 e7c6409b6131abba800000007fffffff c169bd6ae49ae989e49ae98976da4654 fpscr=00000000
+vcvtp.s32.f32 d10, d30 2d437e6b0d2ecb304571028b6b4da579 7511352cda8b4d0f41fc9192fe04b14e 2d437e6b0d2ecb300000002080000000 7511352cda8b4d0f41fc9192fe04b14e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.s32.f32 d10, d30 9101fdc1c031b92c0134f9c60823ce9b 85e9c88f8de690fd6667ca808b49f57d 9101fdc1c031b92c7fffffff00000000 85e9c88f8de690fd6667ca808b49f57d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[1]
+vcvtp.s32.f32 d10, d30 bccbaf0566cf1d31c81276b5c81276b5 755703750845adda82298fcd82298fcd bccbaf0566cf1d310000000000000000 755703750845adda82298fcd82298fcd fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtp.s32.f32 d10, d30 ff2633322d6e57adff263332597a2702 8cef6726264f4da99ac068b79b5f1900 ff2633322d6e57ad0000000000000000 8cef6726264f4da99ac068b79b5f1900 fpscr=00000000
+vcvtp.s32.f32 d10, d30 ed90abe0f5cb88c29a296253e3632455 d3ade5f1565e79b6d5a1951b7b849675 ed90abe0f5cb88c2800000007fffffff d3ade5f1565e79b6d5a1951b7b849675 fpscr=00000000
+vcvtp.s32.f32 d10, d30 026b0e0750f03b8e208bace3fb90b05a 817c3d99860cc32a36744f2dedf322bf 026b0e0750f03b8e0000000180000000 817c3d99860cc32a36744f2dedf322bf fpscr=00000000
+vcvtp.s32.f32 d10, d30 a6d5f4ec9ac8e2a1e81a11bafa378054 c11b4e88c1122fdcbd77a2c00e91c9eb a6d5f4ec9ac8e2a10000000000000001 c11b4e88c1122fdcbd77a2c00e91c9eb fpscr=00000000
+vcvtp.s32.f32 d10, d30 14c751d7198e1b3dad8d52a714ee8c46 e509fd1870a52b3ad47a41515a4f6414 14c751d7198e1b3d800000007fffffff e509fd1870a52b3ad47a41515a4f6414 fpscr=00000000
+vcvtp.s32.f32 d10, d30 f3e785215d29be6aac2d93c99a9abdfa f68d95ad031b0b06202727559915535a f3e785215d29be6a0000000100000000 f68d95ad031b0b06202727559915535a fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.s32.f32 d10, d30 42455641c40c731dccce93e5c092bc70 2319fe2781f065692fab15f4b002203a 42455641c40c731d0000000100000000 2319fe2781f065692fab15f4b002203a fpscr=00000000
+vcvtp.s32.f32 d10, d30 1afa400296f748bd61f6a64c21b43f8f 4b1d50e60d11e6b9f62c536a08b7f01b 1afa400296f748bd8000000000000001 4b1d50e60d11e6b9f62c536a08b7f01b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.s32.f32 d10, d30 43142335c79b4df4418cdfdcd348a93d c056ac21f5f1b321c2298dc294e9fff9 43142335c79b4df4ffffffd600000000 c056ac21f5f1b321c2298dc294e9fff9 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.s32.f32 d10, d30 ccddb1e4e0cf12d8e0cf12d8786765bf c7b2b9b67e1af850ccd56b3ac4bb6a13 ccddb1e4e0cf12d8f954a630fffffa25 c7b2b9b67e1af850ccd56b3ac4bb6a13 fpscr=00000000
+vcvtp.s32.f32 d10, d30 f64ec2c6405ffdc9205e6df76cb2bd81 937f59a4e993c9c110e512cdde3b01cf f64ec2c6405ffdc90000000180000000 937f59a4e993c9c110e512cdde3b01cf fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtp.s32.f32 d10, d30 294f72a7f92919a4e9f40eb5a4c492a2 376d4b3352648f410ae4bf29418d7851 294f72a7f92919a40000000100000012 376d4b3352648f410ae4bf29418d7851 fpscr=00000000
+vcvtp.s32.f32 d10, d30 77c470b81d6f63929ed33a731cf2a4d1 293501ee00de5bf6d3452d008b42323d 77c470b81d6f63928000000000000000 293501ee00de5bf6d3452d008b42323d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.s32.f32 d10, d30 86c1806c8bf96e331190ca2a35639a8a f2cc49d5479db15d404e72a386fa8733 86c1806c8bf96e330000000400000000 f2cc49d5479db15d404e72a386fa8733 fpscr=00000000
+vcvtm.s32.f32 d15, d15 40727fdd55c630bddd57ee188be3443e 26973ad3a0d30d682dbed31011ad1de3 00000000ffffffff2dbed31011ad1de3 00000000ffffffff2dbed31011ad1de3 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtm.s32.f32 d15, d15 270ce7ec75f74ffbecf3c831dee65b97 43eebd5c0a9e3cdb0a9e3cdb5fa0f311 000001dd000000000a9e3cdb5fa0f311 000001dd000000000a9e3cdb5fa0f311 fpscr=00000000
+vcvtm.s32.f32 d15, d15 c94730b1ad3e21738938dd2ea02c486b 526de5bcafee706429084f2b65e21f26 7fffffffffffffff29084f2b65e21f26 7fffffffffffffff29084f2b65e21f26 fpscr=00000000
+vcvtm.s32.f32 d15, d15 1d404b6610444f6ec5647cb3a8cd5878 d1522d5d92ce164902f8b532456a45d6 80000000ffffffff02f8b532456a45d6 80000000ffffffff02f8b532456a45d6 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtm.s32.f32 d15, d15 62fdec3a51cced2291b7dd89396a182a 498ea9ae498ea9ae8da0d5be0c167139 0011d5350011d5358da0d5be0c167139 0011d5350011d5358da0d5be0c167139 fpscr=00000000
+randV128: 13824 calls, 14294 iters
+vcvtm.s32.f32 d15, d15 fa2c28055a10d0d74c345c23eb212cff f01c445d07d6ea3c198c462a1c2aa5c5 8000000000000000198c462a1c2aa5c5 8000000000000000198c462a1c2aa5c5 fpscr=00000000
+vcvtm.s32.f32 d15, d15 f03a1b7bdcc20ed0727d9431d8b81ea6 7552c4cf2cf34fca1e883279230da44e 7fffffff000000001e883279230da44e 7fffffff000000001e883279230da44e fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtm.s32.f32 d15, d15 1144c219caab8322452fa732641b8e6d de73a405adad337e2ec989a4660b8423 80000000ffffffff2ec989a4660b8423 80000000ffffffff2ec989a4660b8423 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtm.s32.f32 d15, d15 58547e50c93c3f3d1b837887652c9a58 934b731ac64913a06553a09d06a800f4 ffffffffffffcdbb6553a09d06a800f4 ffffffffffffcdbb6553a09d06a800f4 fpscr=00000000
+vcvtm.s32.f32 d15, d15 83c312cf09ad3b00f2061a0204bf419a 6846fd1f71d7efb4f0894e38d4a440a8 7fffffff7ffffffff0894e38d4a440a8 7fffffff7ffffffff0894e38d4a440a8 fpscr=00000000
+vcvtm.s32.f32 d15, d15 111b42f8033a2579cb790892050b7717 7ef41b5ac8d85a4e317ef73e690e7eeb 7ffffffffff93d2d317ef73e690e7eeb 7ffffffffff93d2d317ef73e690e7eeb fpscr=00000000
+vcvtm.s32.f32 d15, d15 8bb3426cc657024efecbbf5e197a9f69 cce4a7c3fe17d646d25d29bdc4ab0bcb f8dac1e880000000d25d29bdc4ab0bcb f8dac1e880000000d25d29bdc4ab0bcb fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtm.s32.f32 d15, d15 78f1bfa73fb8f3d278f1bfa7e5b4ca4c e578055fa1636b44ce5101ebdac7d352 80000000ffffffffce5101ebdac7d352 80000000ffffffffce5101ebdac7d352 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtm.s32.f32 d15, d15 38c6383a5011d593068ae7bb5efd1da0 f9264e05671a06f18e5bd129671a06f1 800000007fffffff8e5bd129671a06f1 800000007fffffff8e5bd129671a06f1 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[2]
+vcvtm.s32.f32 d15, d15 e753989c9b48833ae753989c9b928f2f d30e5990c3a0488473f689fdd53898f6 80000000fffffebf73f689fdd53898f6 80000000fffffebf73f689fdd53898f6 fpscr=00000000
+vcvtm.s32.f32 d15, d15 38479ba2b94e587482ad07cb7d939f1a b634ea050ed0074727f34b460d0f3e2e ffffffff0000000027f34b460d0f3e2e ffffffff0000000027f34b460d0f3e2e fpscr=00000000
+vcvtm.s32.f32 d15, d15 b479bce403a59e41f65d819d7ec8ba22 1e1bb83e533cd785f06664958e9d8a3e 000000007ffffffff06664958e9d8a3e 000000007ffffffff06664958e9d8a3e fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtm.s32.f32 d15, d15 ec7558d9715b0f473703e711cd2753a2 55f22c4271285b146fa59c831b0fd443 7fffffff7fffffff6fa59c831b0fd443 7fffffff7fffffff6fa59c831b0fd443 fpscr=00000000
+vcvtm.s32.f32 d15, d15 4f9adef0abb63217bf6d731b244404f1 9fe4f382370cb63197612e613aa45c46 ffffffff0000000097612e613aa45c46 ffffffff0000000097612e613aa45c46 fpscr=00000000
+vcvtm.s32.f32 d15, d15 6f1bb4a51a3078ce1a6a40f9f8d1711b 5f5a0ed3a992974e261b55baa42e749a 7fffffffffffffff261b55baa42e749a 7fffffffffffffff261b55baa42e749a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.s32.f32 d15, d15 385eccab68f93d7fe6bf2f153b514e6e 1d6494fe2faa0bf6ea390a70975480fb 0000000000000000ea390a70975480fb 0000000000000000ea390a70975480fb fpscr=00000000
+vcvtm.s32.f32 d15, d15 c7e99894d4a15e4dd9137155c35992a6 0824d8d78b6ce38dca85ac82ddcec2b9 00000000ffffffffca85ac82ddcec2b9 00000000ffffffffca85ac82ddcec2b9 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.s32.f32 d15, d15 6e6dd07548facb6cf40e2daa3efd36c0 bc4d0c9409415afd8d2d00bf48bd2f9a ffffffff000000008d2d00bf48bd2f9a ffffffff000000008d2d00bf48bd2f9a fpscr=00000000
+vcvtm.s32.f32 d15, d15 432bfbb09c960a7c8b474ffe77445fbf 04839c3e4051983c39cb9b220ca6208f 000000000000000339cb9b220ca6208f 000000000000000339cb9b220ca6208f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.s32.f32 d15, d15 a3ba0d1ba3ba0d1b8496f597978b8010 9e5120380f7b3cbcd2dd80c1d0e6a408 ffffffff00000000d2dd80c1d0e6a408 ffffffff00000000d2dd80c1d0e6a408 fpscr=00000000
+vcvtm.s32.f32 d15, d15 653daa2dfa8dd846d830d796c170587d 2f83f435711be5d9dd931c6ef3f431e6 000000007fffffffdd931c6ef3f431e6 000000007fffffffdd931c6ef3f431e6 fpscr=00000000
+vcvtm.s32.f32 d15, d15 6e372721d39e639c3f827e4152164a5e d9a736fd985a124af055bbc358e5bfa3 80000000fffffffff055bbc358e5bfa3 80000000fffffffff055bbc358e5bfa3 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtm.s32.f32 d15, d15 d005bac5ac72e5a48da593debb70f592 205a95e8fa5e83546b974e2efa5e8354 00000000800000006b974e2efa5e8354 00000000800000006b974e2efa5e8354 fpscr=00000000
+vcvtm.s32.f32 d15, d15 4171961beed9b4ce13350dc27e39f534 449afa2f428f96cce949c07e49f9889a 000004d700000047e949c07e49f9889a 000004d700000047e949c07e49f9889a fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.s32.f32 d15, d15 e5cec1a3e1335d64f19ef2fa0fd6f106 da04a54820f5e299125391af19a4a0e2 8000000000000000125391af19a4a0e2 8000000000000000125391af19a4a0e2 fpscr=00000000
+vcvtm.s32.f32 d15, d15 b7f363035a47c10f451e6e7b7021143d 379a6108cffb6b50d209ba063497ae8b 0000000080000000d209ba063497ae8b 0000000080000000d209ba063497ae8b fpscr=00000000
+vcvtm.s32.f32 d15, d15 df3e642d1b9a4988ca967c867a5901f3 e1a843d9aee63dcaa69017616fbaf2c0 80000000ffffffffa69017616fbaf2c0 80000000ffffffffa69017616fbaf2c0 fpscr=00000000
+vcvtm.s32.f32 d15, d15 782cd97f2d728437e067c089546e7389 b69a111c4b8f33cb6669763470980345 ffffffff011e67966669763470980345 ffffffff011e67966669763470980345 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.s32.f32 d15, d15 720f5c17a247ae78e22a4c6ba247ae78 acd6c9d7f9865126e81003345ffc3f86 ffffffff80000000e81003345ffc3f86 ffffffff80000000e81003345ffc3f86 fpscr=00000000
+vcvtm.s32.f32 d15, d15 3aebf8a6cc189a83855c7f1b07e29824 c24359b3bf64dff72b5cb1a7b8742856 ffffffcfffffffff2b5cb1a7b8742856 ffffffcfffffffff2b5cb1a7b8742856 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtm.s32.f32 d15, d15 ee1d8b63ee1d8b639bd307162c3f1e07 7d33f60e2f4a66969eecd4b2eda1e1c5 7fffffff000000009eecd4b2eda1e1c5 7fffffff000000009eecd4b2eda1e1c5 fpscr=00000000
+vcvtm.s32.f32 d15, d15 dcad6e8067dd540e24c8acc75b09ca4e 8bb2b97240c1968d9a83fcf74a5b7ef8 ffffffff000000069a83fcf74a5b7ef8 ffffffff000000069a83fcf74a5b7ef8 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.s32.f32 d15, d15 609b9513076eb928170405dc82c6b67c 196ebe756b409bb4465245f0db5964c4 000000007fffffff465245f0db5964c4 000000007fffffff465245f0db5964c4 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtm.s32.f32 d15, d15 96d02b7e60575c0ce9ec8205057bd062 ac2e8a000ed6083f9776bdf68b0f6e46 ffffffff000000009776bdf68b0f6e46 ffffffff000000009776bdf68b0f6e46 fpscr=00000000
+vcvtm.s32.f32 d15, d15 3568e49afb54e05a59292878aeb1551d cd9323ecd15d437f748de15876be5c27 ed9b828080000000748de15876be5c27 ed9b828080000000748de15876be5c27 fpscr=00000000
+vcvtm.s32.f32 d15, d15 4bede7335c1493a8d4732d5944477e80 70ee7415c89ba55f83b4416cccad5e81 7ffffffffffb22d583b4416cccad5e81 7ffffffffffb22d583b4416cccad5e81 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtm.s32.f32 d15, d15 c265ae4d462a1617cb6d7a792e22ddad ed07535a561c2e9f561c2e9f70e68754 800000007fffffff561c2e9f70e68754 800000007fffffff561c2e9f70e68754 fpscr=00000000
+vcvtm.s32.f32 d15, d15 9b7853f497412cd6417710f315ede355 63b3faace0d2840d6135d3702d91b86c 7fffffff800000006135d3702d91b86c 7fffffff800000006135d3702d91b86c fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.s32.f32 d15, d15 4a6df60e227b5a6a961f4a9199a00927 f0aa4a44444e67510bde209ff1eec74b 80000000000003390bde209ff1eec74b 80000000000003390bde209ff1eec74b fpscr=00000000
+vcvtm.s32.f32 d15, d15 1de3e4110c752acbbf681b585bc8b0e9 5e0b5d0236762a13edc5e2732648d59e 7fffffff00000000edc5e2732648d59e 7fffffff00000000edc5e2732648d59e fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vcvtm.s32.f32 d15, d15 f12072e72927e6f1148092b22927e6f1 503024ecafa8d3981914315d503024ec 7fffffffffffffff1914315d503024ec 7fffffffffffffff1914315d503024ec fpscr=00000000
+vcvtm.s32.f32 d15, d15 9fdfd945eb795552a4978fd7d81dacca 09259bc90acd766624fd27d74fd0ce0b 000000000000000024fd27d74fd0ce0b 000000000000000024fd27d74fd0ce0b fpscr=00000000
+vcvtm.s32.f32 d15, d15 caedcd934deb67a15fd122008b5d99ef 6496026a270dc117370e35a1fc1bd916 7fffffff00000000370e35a1fc1bd916 7fffffff00000000370e35a1fc1bd916 fpscr=00000000
+vcvtm.s32.f32 d15, d15 11a3c5e9e558b918c7533815a978adea 3b3b9973acc96a58d5583c81b53cbaf3 00000000ffffffffd5583c81b53cbaf3 00000000ffffffffd5583c81b53cbaf3 fpscr=00000000
+vcvtm.s32.f32 d15, d15 b8e7bb673e6644c782ed2f556cf9af84 3f1a2065e335754e82957528f367ec67 000000008000000082957528f367ec67 000000008000000082957528f367ec67 fpscr=00000000
+vcvtn.s32.f32 q15, q0 99b12a27e19a5abb0201f4db008d902a 33e6dd97c91dc051f65e2231c65a033a 00000000fff623fb80000000ffffc97f 33e6dd97c91dc051f65e2231c65a033a fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtn.s32.f32 q15, q0 79f4effe4e6a29db17b42fa2be563504 07d60c9a4f5b8fec7d463fca4f5b8fec 000000007fffffff7fffffff7fffffff 07d60c9a4f5b8fec7d463fca4f5b8fec fpscr=00000000
+vcvtn.s32.f32 q15, q0 32e0bf6f91185128a6ace7f9c561bb15 5737dcd92a0676abfb49344c0eb53af4 7fffffff000000008000000000000000 5737dcd92a0676abfb49344c0eb53af4 fpscr=00000000
+vcvtn.s32.f32 q15, q0 53e1885ae978b6cfcde6437ebf49c33c 5855de30269849e341f32ab286b2c018 7fffffff000000000000001e00000000 5855de30269849e341f32ab286b2c018 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtn.s32.f32 q15, q0 35d41ff2265260b54efa5c7f91a2add8 fc5f015e6ebcc489ecff5a35a041044a 800000007fffffff8000000000000000 fc5f015e6ebcc489ecff5a35a041044a fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.s32.f32 q15, q0 9f89cdef2e294fe4d4eb3350c2178d6d 60fac6cea3d11abaa383dd738ac6ea8f 7fffffff000000000000000000000000 60fac6cea3d11abaa383dd738ac6ea8f fpscr=00000000
+vcvtn.s32.f32 q15, q0 c272b813c2aa2e17d3dd61e82ebb7eaa c9999f5717abb57f1ea493eb08128998 ffeccc15000000000000000000000000 c9999f5717abb57f1ea493eb08128998 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtn.s32.f32 q15, q0 53d8cd66c999917cb18ffa4384c81c24 a26e60420ca2168b2bb6df9db6e46f86 00000000000000000000000000000000 a26e60420ca2168b2bb6df9db6e46f86 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.s32.f32 q15, q0 72cfde6d73fccd8e9dfb044f86dc0062 21786dea499601dfe384e91b648b1fe8 000000000012c03c800000007fffffff 21786dea499601dfe384e91b648b1fe8 fpscr=00000000
+vcvtn.s32.f32 q15, q0 fb3cc9be73732ad360882643f866a745 cc41ba594147b5f3dc275348d2f231f9 fcf9169c0000000c8000000080000000 cc41ba594147b5f3dc275348d2f231f9 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.s32.f32 q15, q0 063dbeb76b9fda9f2fbe51e521ff6597 f26241ce6099514674295d701564c7af 800000007fffffff7fffffff00000000 f26241ce6099514674295d701564c7af fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtn.s32.f32 q15, q0 c0d3ad3d73d620edcade3c287efc0691 1439ff9310023815adac342947dc9a7d 0000000000000000000000000001b935 1439ff9310023815adac342947dc9a7d fpscr=00000000
+vcvtn.s32.f32 q15, q0 517a7c93a34e44f56394f5aaa1217e2e 7b6c0755c6fb176836ab23a2cd8655c9 7fffffffffff827400000000ef3546e0 7b6c0755c6fb176836ab23a2cd8655c9 fpscr=00000000
+vcvtn.s32.f32 q15, q0 1618851e71cc863efc555b5de5ad9435 5524f078ccf243080a17d2c3aa673077 7ffffffff86de7c00000000000000000 5524f078ccf243080a17d2c3aa673077 fpscr=00000000
+vcvtn.s32.f32 q15, q0 2817e26324d840f5ea1b587de73d65e9 136ac98b762981b2f6a8b49c581e24a9 000000007fffffff800000007fffffff 136ac98b762981b2f6a8b49c581e24a9 fpscr=00000000
+vcvtn.s32.f32 q15, q0 6fef7bc74db7422511735b8c1c48552e 887c476f1a2f9b98ff64a7e4d8ee3c71 00000000000000008000000080000000 887c476f1a2f9b98ff64a7e4d8ee3c71 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtn.s32.f32 q15, q0 25b9e8956a11973236f2f7b53bca35c5 5341754eea59f23ef7913f11ce35406d 7fffffff8000000080000000d2afe4c0 5341754eea59f23ef7913f11ce35406d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[0]
+vcvtn.s32.f32 q15, q0 58c4fd2dad49ac0d6044706c605944a6 94998bf33855c1033855c1038d5088ef 00000000000000000000000000000000 94998bf33855c1033855c1038d5088ef fpscr=00000000
+vcvtn.s32.f32 q15, q0 d7f69af905aea97ccdc01b4e0596e316 c509246e461f4f1fa3c8d53e79f27f4e fffff76e000027d4000000007fffffff c509246e461f4f1fa3c8d53e79f27f4e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: 14080 calls, 14558 iters
+vcvtn.s32.f32 q15, q0 5c9c7d9703a93212407843cc5c9c7d97 085ea38bd7fe986f00c9cd006b099a39 0000000080000000000000007fffffff 085ea38bd7fe986f00c9cd006b099a39 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtn.s32.f32 q15, q0 90cc47b5bcac4507811d8a98279a7b90 6f84b3d667baa346d921cfec638aa2c3 7fffffff7fffffff800000007fffffff 6f84b3d667baa346d921cfec638aa2c3 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vcvtn.s32.f32 q15, q0 491f484018d5f7f17b460634491f4840 ae4ee4797459cec425d5ee51481674cd 000000007fffffff00000000000259d3 ae4ee4797459cec425d5ee51481674cd fpscr=00000000
+vcvtn.s32.f32 q15, q0 8c4e616c1f20c293dfc3c8ba3a9b6893 e14b186626df43c7d62fdcb8e29d3bee 80000000000000008000000080000000 e14b186626df43c7d62fdcb8e29d3bee fpscr=00000000
+vcvtn.s32.f32 q15, q0 55ffb0a838503c3b8118932069a44f58 4c5801993dd8d15f9689adca9be2403e 03600664000000000000000000000000 4c5801993dd8d15f9689adca9be2403e fpscr=00000000
+vcvtn.s32.f32 q15, q0 4673ebe1617aec32bb53c2141abb21d0 04a22638dc8ce90ec373a37a69245a82 0000000080000000ffffff0c7fffffff 04a22638dc8ce90ec373a37a69245a82 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vcvtn.s32.f32 q15, q0 8eabcf793dd29f32a10d806df3b8d357 6ef36452408000f91aac81d31aac81d3 7fffffff000000040000000000000000 6ef36452408000f91aac81d31aac81d3 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtn.s32.f32 q15, q0 9728cac652149ab5a8ff9253a5bf393a 106ca7df11c6976a65ac172d11c6976a 00000000000000007fffffff00000000 106ca7df11c6976a65ac172d11c6976a fpscr=00000000
+vcvtn.s32.f32 q15, q0 54d41a0477202f3ed10556735eee52b6 156a9c421d0cbd42d8c6c999930a36ad 00000000000000008000000000000000 156a9c421d0cbd42d8c6c999930a36ad fpscr=00000000
+vcvtn.s32.f32 q15, q0 7f6c5ba95544111b0f9c915c71950132 6e97020bff16998641e774299fa3d66c 7fffffff800000000000001d00000000 6e97020bff16998641e774299fa3d66c fpscr=00000000
+vcvtn.s32.f32 q15, q0 b37b23f8114b5e4ee9231276dfa3eb99 a6bdde0c3237a7fc696ff0ab953a7829 00000000000000007fffffff00000000 a6bdde0c3237a7fc696ff0ab953a7829 fpscr=00000000
+vcvtn.s32.f32 q15, q0 fcc86630626944442f109ba4e8712c21 f044cce5dac5721752b3ab8c6c18f4d5 80000000800000007fffffff7fffffff f044cce5dac5721752b3ab8c6c18f4d5 fpscr=00000000
+vcvtn.s32.f32 q15, q0 b23db4e070e5ca5e8e1fc7d1e09ef850 37880c391a270b9d5dd855939a3cc93e 00000000000000007fffffff00000000 37880c391a270b9d5dd855939a3cc93e fpscr=00000000
+vcvtn.s32.f32 q15, q0 b460f4f91b282961762f35e2eceda20e bd65289e0798808d79d490d58ed7e85f 00000000000000007fffffff00000000 bd65289e0798808d79d490d58ed7e85f fpscr=00000000
+vcvtn.s32.f32 q15, q0 a18a5d24fad08c433417129ded07861c ac86808cd701dd5a50108e4e6b2bba6b 00000000800000007fffffff7fffffff ac86808cd701dd5a50108e4e6b2bba6b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtn.s32.f32 q15, q0 0cea407a189b6b25ed7ae710dd6950f7 9c40e68c0cfb6c391283e45175d0995d 0000000000000000000000007fffffff 9c40e68c0cfb6c391283e45175d0995d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtn.s32.f32 q15, q0 63d3b8fe988e577f35f61b7c6acf6ebd 167779529146f3a89146f3a8c0d0cdcb 000000000000000000000000fffffff9 167779529146f3a89146f3a8c0d0cdcb fpscr=00000000
+vcvtn.s32.f32 q15, q0 90db2f68b9666fcca71fe07eebd928a1 d5afa4c7cb84736e8f7740ccd7927e91 80000000fef719240000000080000000 d5afa4c7cb84736e8f7740ccd7927e91 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtn.s32.f32 q15, q0 def62593701d37432ca157bf7f5b1482 3abf05ac5923ef94debc59b7f83ba237 000000007fffffff8000000080000000 3abf05ac5923ef94debc59b7f83ba237 fpscr=00000000
+vcvtn.s32.f32 q15, q0 41e6235ffb5a3160f0d07b335ae26992 7e46bad238f71e7d12af6172b29cda87 7fffffff000000000000000000000000 7e46bad238f71e7d12af6172b29cda87 fpscr=00000000
+vcvtn.s32.f32 q15, q0 a5fcc814bba50d8e5f53ac5bf2849cbf fa26231de528078da07dba6126e48329 80000000800000000000000000000000 fa26231de528078da07dba6126e48329 fpscr=00000000
+vcvtn.s32.f32 q15, q0 a78c97c225581940f7cfc0b52fc80c90 c74d76cca3c3289919e4366ab807ca00 ffff3289000000000000000000000000 c74d76cca3c3289919e4366ab807ca00 fpscr=00000000
+vcvtn.s32.f32 q15, q0 f52fbc85575b1b477dccdae254439eb4 eb439de97628c26cf9d03d5dfcd828c9 800000007fffffff8000000080000000 eb439de97628c26cf9d03d5dfcd828c9 fpscr=00000000
+vcvtn.s32.f32 q15, q0 66bd0b78a5c8f59055d215a10c396cda dc51b8fc9203bf4890682edbdbac43ca 80000000000000000000000080000000 dc51b8fc9203bf4890682edbdbac43ca fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[3]
+vcvtn.s32.f32 q15, q0 b71a3f4aeed590e079770aac00cfe6ae 475d6c4a8b882d4859976eac475d6c4a 0000dd6c000000007fffffff0000dd6c 475d6c4a8b882d4859976eac475d6c4a fpscr=00000000
+vcvtn.s32.f32 q15, q0 dbebbe6801580293feb9382d9b6c5a8e 3d9faa076b9eb96f3d31329ee02fdea9 000000007fffffff0000000080000000 3d9faa076b9eb96f3d31329ee02fdea9 fpscr=00000000
+vcvtn.s32.f32 q15, q0 74793c039e7c95681ed8047f613e902c 56943b8d8ff5deca058ed08ad3a01874 7fffffff000000000000000080000000 56943b8d8ff5deca058ed08ad3a01874 fpscr=00000000
+vcvtn.s32.f32 q15, q0 8b7daa55375de243c28011145d561e12 086b358f995941224b641e2a23d8fc34 000000000000000000e41e2a00000000 086b358f995941224b641e2a23d8fc34 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtn.s32.f32 q15, q0 5c9d4d58d2c1213457eb7bf6255712cc 7be59f49a91cf031edb40823d2cac907 7fffffff000000008000000080000000 7be59f49a91cf031edb40823d2cac907 fpscr=00000000
+vcvtn.s32.f32 q15, q0 6e83083f406dfa14b5095445b9abb682 8f211bdb58469acc3bcf60c183ecb285 000000007fffffff0000000000000000 8f211bdb58469acc3bcf60c183ecb285 fpscr=00000000
+vcvtn.s32.f32 q15, q0 a046ac5ae5befee1b75892c14bd7f368 b354dde1684df0f2a40736e523fd8d39 000000007fffffff0000000000000000 b354dde1684df0f2a40736e523fd8d39 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvta.s32.f32 q14, q1 59bfe8bfb93215af3afc075913dcae10 33c394d16576da4eb13d815dd1b7354f 000000007fffffff0000000080000000 33c394d16576da4eb13d815dd1b7354f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.s32.f32 q14, q1 f627a938f627a93807374fc1b6ca660e 1abb5248730d7e409d11962a842e712f 000000007fffffff0000000000000000 1abb5248730d7e409d11962a842e712f fpscr=00000000
+vcvta.s32.f32 q14, q1 6e90b1bab167e944170858378afe14dc 04ae3d0cce21fc8ab5b9fc2349fdd0ca 00000000d780dd8000000000001fba19 04ae3d0cce21fc8ab5b9fc2349fdd0ca fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.s32.f32 q14, q1 e520104ce520104c045297096084eb87 39b2cd5e9cc94e8efaf600d0b9dd57d8 00000000000000008000000000000000 39b2cd5e9cc94e8efaf600d0b9dd57d8 fpscr=00000000
+vcvta.s32.f32 q14, q1 a339cac64ee62c685cb603e816daeab8 2f7cd63b7d58a02bac2ef44df8178f29 000000007fffffff0000000080000000 2f7cd63b7d58a02bac2ef44df8178f29 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvta.s32.f32 q14, q1 d25d8bec3c3befd356972f863c3befd3 326144a1a0e45200538c1e428dcd0b51 00000000000000007fffffff00000000 326144a1a0e45200538c1e428dcd0b51 fpscr=00000000
+vcvta.s32.f32 q14, q1 a49993d3ea3784485621063da8242a0b b349e09dc9663f39f6d99f0e8809fbd0 00000000fff19c0c8000000000000000 b349e09dc9663f39f6d99f0e8809fbd0 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvta.s32.f32 q14, q1 11f66335113553cd88378f31ebea631f 82aff707edca4bd41502130182aff707 00000000800000000000000000000000 82aff707edca4bd41502130182aff707 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvta.s32.f32 q14, q1 96a05923c63a4a9904ed5aaf73c1f2a2 a62518679556846360116b8160116b81 00000000000000007fffffff7fffffff a62518679556846360116b8160116b81 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.s32.f32 q14, q1 823134177f48373681c5a2ba7f483736 313c4bdd54abce24cc0229a53f93cd86 000000007ffffffffdf7596c00000001 313c4bdd54abce24cc0229a53f93cd86 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[0]
+vcvta.s32.f32 q14, q1 e713cf7e649a36ade4c71e763eef2364 1654f595743dcf81b861ed0f6151b874 000000007fffffff000000007fffffff 1654f595743dcf81b861ed0f6151b874 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.s32.f32 q14, q1 4bd640744d33f3bfc4469290d8008ebd b3e7a67e3158dc60aeb947853158dc60 00000000000000000000000000000000 b3e7a67e3158dc60aeb947853158dc60 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvta.s32.f32 q14, q1 6749ee50db06ca6916e7597a81d88948 7ceca994c75566d27ceca9949d526fe0 7fffffffffff2a997fffffff00000000 7ceca994c75566d27ceca9949d526fe0 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvta.s32.f32 q14, q1 378e2a3826dd9a9c5e0c51b03d86f298 9ee6ac445406d682f67148295f89e979 000000007fffffff800000007fffffff 9ee6ac445406d682f67148295f89e979 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvta.s32.f32 q14, q1 e1a9f07c6d8d825d8ac36aebede07e09 40c216ecd996de77d996de77dc542ee2 00000006800000008000000080000000 40c216ecd996de77d996de77dc542ee2 fpscr=00000000
+vcvta.s32.f32 q14, q1 2b39d5245a646b2844c90b9eddb36977 264fbbfd056a43b35bd89aba3830a704 00000000000000007fffffff00000000 264fbbfd056a43b35bd89aba3830a704 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[3]
+vcvta.s32.f32 q14, q1 8f0be6067b290c0e79587dcdf98ad9a5 54ce8a94f7862d23409875d4409875d4 7fffffff800000000000000500000005 54ce8a94f7862d23409875d4409875d4 fpscr=00000000
+vcvta.s32.f32 q14, q1 d3bbf24d8c2a7d4d7a8d7a24eecaac5e 9556bd39437ffabe90d96b0fe237f10d 00000000000001000000000080000000 9556bd39437ffabe90d96b0fe237f10d fpscr=00000000
+vcvta.s32.f32 q14, q1 99de29038663d6ac752b7862e858b4fb 1204904e93a121ee4f2768ad6ec54b38 00000000000000007fffffff7fffffff 1204904e93a121ee4f2768ad6ec54b38 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvta.s32.f32 q14, q1 844b933267ae028f844b93321e3265d1 3ed440c1d2ad80341b46e0aac1e37c67 000000008000000000000000ffffffe4 3ed440c1d2ad80341b46e0aac1e37c67 fpscr=00000000
+vcvta.s32.f32 q14, q1 77aaa0dc0682744b82d1013ff9d27e1f d2202566f2de3b7685e02c09a0735cd2 80000000800000000000000000000000 d2202566f2de3b7685e02c09a0735cd2 fpscr=00000000
+vcvta.s32.f32 q14, q1 36e678340ab831a33179f82a6495c772 0ff5a7225c328734dbca4214d09ef4e1 000000007fffffff8000000080000000 0ff5a7225c328734dbca4214d09ef4e1 fpscr=00000000
+vcvta.s32.f32 q14, q1 48ba1e17ee60fcc7fd887a4985e26dca 28b29b075959e8f6793ca292dbf833fd 000000007fffffff7fffffff80000000 28b29b075959e8f6793ca292dbf833fd fpscr=00000000
+vcvta.s32.f32 q14, q1 c7ef91ad3d5c20cafba8bf17aff8dcab aa03b2e6cb59af80752b6f5f0a9d56e1 00000000ff2650807fffffff00000000 aa03b2e6cb59af80752b6f5f0a9d56e1 fpscr=00000000
+vcvta.s32.f32 q14, q1 f893489ecee2eebd5f4379f642ca1dbf 996764bcdcd7bddf4f434bc89420a112 00000000800000007fffffff00000000 996764bcdcd7bddf4f434bc89420a112 fpscr=00000000
+vcvta.s32.f32 q14, q1 a72814bd31083f00e03b2e57c2d0d7c8 307e3ce31a3e2c02ce5308f3853b4732 0000000000000000cb3dc34000000000 307e3ce31a3e2c02ce5308f3853b4732 fpscr=00000000
+vcvta.s32.f32 q14, q1 0cc6a93513ed7028ca794b30743dbb10 4b060582065116065ebb2a7282d622b6 00860582000000007fffffff00000000 4b060582065116065ebb2a7282d622b6 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.s32.f32 q14, q1 515ae2c71045b37c900dd2a25da89987 6da0a3651e8ef79018c9ea5ed1554581 7fffffff000000000000000080000000 6da0a3651e8ef79018c9ea5ed1554581 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvta.s32.f32 q14, q1 4c536e5c8fcd2591d8d4a6a4b0e73acf 530e6a2ef30e1571bcdcfbff81294844 7fffffff800000000000000000000000 530e6a2ef30e1571bcdcfbff81294844 fpscr=00000000
+vcvta.s32.f32 q14, q1 bb83ad7424ff2fc3664efd23b2a5f755 36db8046076dac5d61342f5377d3eb95 00000000000000007fffffff7fffffff 36db8046076dac5d61342f5377d3eb95 fpscr=00000000
+vcvta.s32.f32 q14, q1 250fee5622dc7d7dc90167029cfc2b1a a980cd45e7e32288424ad71a9fd0dfef 00000000800000000000003300000000 a980cd45e7e32288424ad71a9fd0dfef fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvta.s32.f32 q14, q1 927c55f1c7094a94936df843927c55f1 0baf6244fd5629bdf1f4a352edee7f84 00000000800000008000000080000000 0baf6244fd5629bdf1f4a352edee7f84 fpscr=00000000
+vcvta.s32.f32 q14, q1 20f85924575343e014917a1736b85823 b7867e0ff1094f335c67ebd13ae549a5 00000000800000007fffffff00000000 b7867e0ff1094f335c67ebd13ae549a5 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: 14336 calls, 14823 iters
+vcvta.s32.f32 q14, q1 705b8d43f7cf3e08d68151af914ac929 3a9771d7a436788e5b0b65e2c16a0860 00000000000000007ffffffffffffff1 3a9771d7a436788e5b0b65e2c16a0860 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvta.s32.f32 q14, q1 1583b10cbe60c9e4f7ba69cdd4e69097 0663fc1b5016c34338bc5e38530329d3 000000007fffffff000000007fffffff 0663fc1b5016c34338bc5e38530329d3 fpscr=00000000
+vcvta.s32.f32 q14, q1 c4a54d713f3a858b011cc3d36c05da46 d3c0a9ba77fd7bed1932f6d7e8ec16d4 800000007fffffff0000000080000000 d3c0a9ba77fd7bed1932f6d7e8ec16d4 fpscr=00000000
+vcvta.s32.f32 q14, q1 0b116beb66435fc8de67ccd6f70179c1 848cded0b3abec78ba920add42842b72 00000000000000000000000000000042 848cded0b3abec78ba920add42842b72 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvta.s32.f32 q14, q1 c680c66e754b0496754b04961510da7e aa0d58e65467e0d47972900e2cb26187 000000007fffffff7fffffff00000000 aa0d58e65467e0d47972900e2cb26187 fpscr=00000000
+vcvta.s32.f32 q14, q1 9ed6a39fd0a78025ef548a8ed4ec04f6 273393a4c518139ab469553e7603b025 00000000fffff67f000000007fffffff 273393a4c518139ab469553e7603b025 fpscr=00000000
+vcvta.s32.f32 q14, q1 6473d1001b79c6bc274d947bce9c2a3d 2a9fc1449e5870948d0f7e9f9d5944ac 00000000000000000000000000000000 2a9fc1449e5870948d0f7e9f9d5944ac fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvta.s32.f32 q14, q1 160dfc18753af2550ba9cf8e926ae0e1 68bc70b80b0fa83da927f2e265d2f8d4 7fffffff00000000000000007fffffff 68bc70b80b0fa83da927f2e265d2f8d4 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvta.s32.f32 q14, q1 6faa40e11a87820e0f7d166468c64cc6 cf67c7c768b7bab6cf67c7c78a83a880 800000007fffffff8000000000000000 cf67c7c768b7bab6cf67c7c78a83a880 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.s32.f32 q14, q1 a7c7f6fb42661cbe3b9a52497ba9c5c3 ca7fd03267f241e8015294858d76df30 ffc00bf47fffffff0000000000000000 ca7fd03267f241e8015294858d76df30 fpscr=00000000
+vcvta.s32.f32 q14, q1 1d40db01f54f8fc076034f19c700a182 860269c5e362789c57f06354d3dea526 00000000800000007fffffff80000000 860269c5e362789c57f06354d3dea526 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvta.s32.f32 q14, q1 2a31fea15d34c79495da5ed4e31f86f0 48df1dafa90794752263795991934b18 0006f8ed000000000000000000000000 48df1dafa90794752263795991934b18 fpscr=00000000
+vcvta.s32.f32 q14, q1 95defb801e11ae02ba4326c818f9efc0 2232b8fc72f08cbbd7b7ec8e37c34a97 000000007fffffff8000000000000000 2232b8fc72f08cbbd7b7ec8e37c34a97 fpscr=00000000
+vcvta.s32.f32 q14, q1 8ebbdef2319f0861467c487a3bcc585c f45b8aafa35af42d0563e526903bae75 80000000000000000000000000000000 f45b8aafa35af42d0563e526903bae75 fpscr=00000000
+vcvta.s32.f32 q14, q1 c8b41d415dff1e91ef799cdb7d10b400 ad2494f15fa3f6e066ffb9ea6a788b09 000000007fffffff7fffffff7fffffff ad2494f15fa3f6e066ffb9ea6a788b09 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[0]
+vcvta.s32.f32 q14, q1 4cdb111ce4324ded3619d3bd3619d3bd a2f484feaa77b15ce1d6ac80502d10f6 0000000000000000800000007fffffff a2f484feaa77b15ce1d6ac80502d10f6 fpscr=00000000
+vcvta.s32.f32 q14, q1 0438135dd06938d99c5d674b7783b492 b831475446a7418cde753c0fd463bb8a 00000000000053a18000000080000000 b831475446a7418cde753c0fd463bb8a fpscr=00000000
+vcvtp.s32.f32 q13, q2 98006dfa918ff22decc9e4c0c9f16a00 43b2d52816675c80628be8e045a0186d 00000166000000017fffffff00001404 43b2d52816675c80628be8e045a0186d fpscr=00000000
+vcvtp.s32.f32 q13, q2 df1deff75c92dfb987332b60ab58149b dbcbfbc5c7f04cfe1ddef61e5869764f 80000000fffe1f67000000017fffffff dbcbfbc5c7f04cfe1ddef61e5869764f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[0]
+vcvtp.s32.f32 q13, q2 a2cd3ab9a2cd3ab90e4f410a45051dd6 e46adf3d655a60db7403eae3909e8175 800000007fffffff7fffffff00000000 e46adf3d655a60db7403eae3909e8175 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtp.s32.f32 q13, q2 df9da7477353a0c69ea60c3d2f5695cb ef73c43ca0b0971ac7a74dfb9f96beb4 8000000000000000fffeb16500000000 ef73c43ca0b0971ac7a74dfb9f96beb4 fpscr=00000000
+vcvtp.s32.f32 q13, q2 daf233efa5c14df6d9579ca968a406c3 c322f14d0c887df6731ab382c1129bce ffffff5e000000017ffffffffffffff7 c322f14d0c887df6731ab382c1129bce fpscr=00000000
+vcvtp.s32.f32 q13, q2 50ea6b13cdce7c2fa80a83444bb6b278 cdaba67aa3769097a3c90894d3deeae2 ea8b30c0000000000000000080000000 cdaba67aa3769097a3c90894d3deeae2 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtp.s32.f32 q13, q2 d79d73f536afdbb5b97b1bf1d7dd71be 29fe07ad1045a03351bbd86ed4ad75a3 00000001000000017fffffff80000000 29fe07ad1045a03351bbd86ed4ad75a3 fpscr=00000000
+vcvtp.s32.f32 q13, q2 b3ff1424023ee52d16e3a24b00ee7e58 a65458875f38d84c555819dec85730d2 000000007fffffff7ffffffffffca33d a65458875f38d84c555819dec85730d2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtp.s32.f32 q13, q2 c89d98e04683de769108e7f9abde751d a09d01d4a09d01d49186a286b72c4656 00000000000000000000000000000000 a09d01d4a09d01d49186a286b72c4656 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.s32.f32 q13, q2 8e8d0bf98d2464faf06107c0ebca2fb6 180ca6b90ad6161a80bda74bc72b7dd0 000000010000000100000000ffff5483 180ca6b90ad6161a80bda74bc72b7dd0 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtp.s32.f32 q13, q2 186570b7b9a002d23c93e64df91c3b6c 4bb908611542ac8f36cf5d649ec39e65 017210c2000000010000000100000000 4bb908611542ac8f36cf5d649ec39e65 fpscr=00000000
+vcvtp.s32.f32 q13, q2 93179d4b5d328ca1f36b69006d1d561d 7533f89cb9be8fd931bdeb8d927d678a 7fffffff000000000000000100000000 7533f89cb9be8fd931bdeb8d927d678a fpscr=00000000
+vcvtp.s32.f32 q13, q2 73a2658513cb5240502df4677b5d880b b85c4232d957e5ffb34f19c51c36789e 00000000800000000000000000000001 b85c4232d957e5ffb34f19c51c36789e fpscr=00000000
+vcvtp.s32.f32 q13, q2 2c9cd669cfc5c152449a425d9e55b097 9ce43827a9d27b553a4366f48cd4c7de 00000000000000000000000100000000 9ce43827a9d27b553a4366f48cd4c7de fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtp.s32.f32 q13, q2 ab7a83b9ff36941af3b2fdc48763cc81 bd5160ab8f9e7c5d77a77431795a59dc 00000000000000007fffffff7fffffff bd5160ab8f9e7c5d77a77431795a59dc fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtp.s32.f32 q13, q2 3b0f24763b0f24763612142a112838d0 cdee57ee923147de51de22de51686c7f e2350240000000007fffffff7fffffff cdee57ee923147de51de22de51686c7f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtp.s32.f32 q13, q2 2b3577222b357722ee2a901182190219 7e09eca91d6bf50f4f8031ab1d8f36f0 7fffffff000000017fffffff00000001 7e09eca91d6bf50f4f8031ab1d8f36f0 fpscr=00000000
+vcvtp.s32.f32 q13, q2 f1d2638f6802f89bf3824ca0f7c621a6 fef6eb77481449d96590ae5e4e68043d 80000000000251287fffffff3a010f40 fef6eb77481449d96590ae5e4e68043d fpscr=00000000
+vcvtp.s32.f32 q13, q2 07eb47b5630398f52dde317e531c9c5f 5ef0aaef50d3656bf443560c2270da39 7fffffff7fffffff8000000000000001 5ef0aaef50d3656bf443560c2270da39 fpscr=00000000
+vcvtp.s32.f32 q13, q2 6e5703e0bcc5273645aaeea71b9236be d692fa81c70294c4b2f88c9963f3f3a2 80000000ffff7d6c000000007fffffff d692fa81c70294c4b2f88c9963f3f3a2 fpscr=00000000
+vcvtp.s32.f32 q13, q2 8600fb7be7061934e7743fb0f8a6c683 d7f3dfece572f81a4fe20b6905c64160 80000000800000007fffffff00000001 d7f3dfece572f81a4fe20b6905c64160 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.s32.f32 q13, q2 9c64200a5b5c78d73dc8dd0ee9d6ee03 536cad0ef8d0c250d6f0ed3dd6f0ed3d 7fffffff800000008000000080000000 536cad0ef8d0c250d6f0ed3dd6f0ed3d fpscr=00000000
+vcvtp.s32.f32 q13, q2 fc3c8d1ca1fedbd53a02d3e97927cf7b 753aedc00523af6c54cdf4a78ed10aae 7fffffff000000017fffffff00000000 753aedc00523af6c54cdf4a78ed10aae fpscr=00000000
+vcvtp.s32.f32 q13, q2 cce0cb3005611876f364e2740d3d4d85 e082059db7544c5d3eb1940c615eaad9 8000000000000000000000017fffffff e082059db7544c5d3eb1940c615eaad9 fpscr=00000000
+vcvtp.s32.f32 q13, q2 20fbc55da362bc96f425f1dc963b1121 a337ac8a78aeae0b1a6ac3a13a26e2ac 000000007fffffff0000000100000001 a337ac8a78aeae0b1a6ac3a13a26e2ac fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtp.s32.f32 q13, q2 e279ad2e73c7cb20b672e1c62867792e 95306a25887e420e50afdc8480df30ec 00000000000000007fffffff00000000 95306a25887e420e50afdc8480df30ec fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.s32.f32 q13, q2 6ac710749cfd46396eadb7ef4c4b63ee cbbe13e9f3ce2dfdcf7eacceab6548e2 fe83d82e800000008000000000000000 cbbe13e9f3ce2dfdcf7eacceab6548e2 fpscr=00000000
+vcvtp.s32.f32 q13, q2 87c6ed40a9461cd15f6f1485b2014f12 a0b56dd538fdaeaa106f278ee16935ce 00000000000000010000000180000000 a0b56dd538fdaeaa106f278ee16935ce fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.s32.f32 q13, q2 d47c772c0a7508186342fb7c2b01b151 36b219c002f92c0b7b93af9b02f92c0b 00000001000000017fffffff00000001 36b219c002f92c0b7b93af9b02f92c0b fpscr=00000000
+vcvtp.s32.f32 q13, q2 f077999be81c9f83d849b69616af7143 1bde161bd1874b946b37797ed58c3515 00000001800000007fffffff80000000 1bde161bd1874b946b37797ed58c3515 fpscr=00000000
+vcvtp.s32.f32 q13, q2 b848e28709a1ff9b4363292c5224eb0a 7a72a574686faa441089d4cd579de7a5 7fffffff7fffffff000000017fffffff 7a72a574686faa441089d4cd579de7a5 fpscr=00000000
+vcvtp.s32.f32 q13, q2 552acd68ee925a1e4746194a3c46d355 d0387bef6ee2303669fdf03c7681b1be 800000007fffffff7fffffff7fffffff d0387bef6ee2303669fdf03c7681b1be fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.s32.f32 q13, q2 cfc2c579bc2357118ef5de5209444988 a15124e4d06f404a7e70b455a2bc6aab 00000000800000007fffffff00000000 a15124e4d06f404a7e70b455a2bc6aab fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtp.s32.f32 q13, q2 3faa2047540c6bc6e67a5e165c2a4068 ad84b832d6c73ecd88a7eff58478ceee 00000000800000000000000000000000 ad84b832d6c73ecd88a7eff58478ceee fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[3]
+vcvtp.s32.f32 q13, q2 c3be8e46a73571aed0188695c3be8e46 1a5cd1691a5cd16923cb48fb9ab06c5f 00000001000000010000000100000000 1a5cd1691a5cd16923cb48fb9ab06c5f fpscr=00000000
+vcvtp.s32.f32 q13, q2 b6ecdec2be3f609682781a502cd97190 e0f29713a9ad59385ae88d4e67bea3cb 80000000000000007fffffff7fffffff e0f29713a9ad59385ae88d4e67bea3cb fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtp.s32.f32 q13, q2 b61f9bbe0ae63a27b61f9bbe12625fdf 5004443545510690214a47052adf0a86 7fffffff00000d110000000100000001 5004443545510690214a47052adf0a86 fpscr=00000000
+vcvtp.s32.f32 q13, q2 f400ba6adf33a1e68d700937e2687298 3571156c684db8c2c1ba6f30bc63bbf9 000000017fffffffffffffe900000000 3571156c684db8c2c1ba6f30bc63bbf9 fpscr=00000000
+vcvtp.s32.f32 q13, q2 c0e3ea22d61de5660bdf5b58406611c1 409d629f39b6c62b8ce59d774c3cfa32 00000005000000010000000002f3e8c8 409d629f39b6c62b8ce59d774c3cfa32 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtp.s32.f32 q13, q2 3889f7a0c1a03808e54166964de3c680 dee2d13481663f0b073ff7999c2dd2b5 80000000000000000000000100000000 dee2d13481663f0b073ff7999c2dd2b5 fpscr=00000000
+vcvtp.s32.f32 q13, q2 6f8615788439db0b0efadeaac5d24161 3ec3dd0c496feab2bb3ca65b2bc98a0a 00000001000efeac0000000000000001 3ec3dd0c496feab2bb3ca65b2bc98a0a fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[2]
+vcvtp.s32.f32 q13, q2 2921fe81a35500004ab04900a3550000 873bad6353d365e853d365e841997ee8 000000007fffffff7fffffff00000014 873bad6353d365e853d365e841997ee8 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtp.s32.f32 q13, q2 9980010745e1973445e197343d42b913 7ad157375df9fe30647d83539d782e8b 7fffffff7fffffff7fffffff00000000 7ad157375df9fe30647d83539d782e8b fpscr=00000000
+vcvtp.s32.f32 q13, q2 a97a0abd7745a9884936b4066d5559b6 d9943ff499d3a1f872e0f972b3b01997 80000000000000007fffffff00000000 d9943ff499d3a1f872e0f972b3b01997 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.s32.f32 q13, q2 364e8e20c626c78ae777e139d2ea9407 4ff11fbb81f307af8814a67828dfb23d 7fffffff000000000000000000000001 4ff11fbb81f307af8814a67828dfb23d fpscr=00000000
+vcvtp.s32.f32 q13, q2 f34717605809f22b6e0498193015228f 7ce112303a7afe0b1ccde7e9e6774a20 7fffffff000000010000000180000000 7ce112303a7afe0b1ccde7e9e6774a20 fpscr=00000000
+vcvtp.s32.f32 q13, q2 799fc1c2579561ad85e755ab7413c723 02fac3dc4f538d4714decffd296473ad 000000017fffffff0000000100000001 02fac3dc4f538d4714decffd296473ad fpscr=00000000
+randV128: 14592 calls, 15088 iters
+vcvtp.s32.f32 q13, q2 6cedb65dd30c294a1800c4a30965420b 0216c60ec12be6232a59fc02664cb833 00000001fffffff6000000017fffffff 0216c60ec12be6232a59fc02664cb833 fpscr=00000000
+vcvtp.s32.f32 q13, q2 caea16a337e94f5f8195e2bfa1811b6f 643463e9b97d1abe7baafdf3099eda69 7fffffff000000007fffffff00000001 643463e9b97d1abe7baafdf3099eda69 fpscr=00000000
+vcvtp.s32.f32 q13, q2 03865bb839c38896a5c85825639bcd82 3e7d6ef0683b4d2022fea9969055692e 000000017fffffff0000000100000000 3e7d6ef0683b4d2022fea9969055692e fpscr=00000000
+vcvtm.s32.f32 q12, q3 0c89b3586660ba7879a5678296eab10e 6e15ee16292aabbc330a19fe9c7bd276 7fffffff0000000000000000ffffffff 6e15ee16292aabbc330a19fe9c7bd276 fpscr=00000000
+vcvtm.s32.f32 q12, q3 ea0ffa7680f0ee52512fcf8d25822461 4b65e672fe6cd28dee8c12e13b637b4a 00e5e672800000008000000000000000 4b65e672fe6cd28dee8c12e13b637b4a fpscr=00000000
+vcvtm.s32.f32 q12, q3 7e3905f36afb45aaa5903bd0166b3841 c51c95df3e57e03a9c5a5d7f0ced1293 fffff63600000000ffffffff00000000 c51c95df3e57e03a9c5a5d7f0ced1293 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtm.s32.f32 q12, q3 2589085f24e55f21a258b93a2589085f 76ed9428b76719ead22202ae71f786b3 7fffffffffffffff800000007fffffff 76ed9428b76719ead22202ae71f786b3 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.s32.f32 q12, q3 9694bbce0bef686a9dfaa6162ba2be44 213ec9ea9005da3e3ce47b842096aed3 00000000ffffffff0000000000000000 213ec9ea9005da3e3ce47b842096aed3 fpscr=00000000
+vcvtm.s32.f32 q12, q3 cadc1ca2a581f823536be0db31cbddae 1f78506044cbe3fb7159a56a14dec7a0 000000000000065f7fffffff00000000 1f78506044cbe3fb7159a56a14dec7a0 fpscr=00000000
+vcvtm.s32.f32 q12, q3 e8b77beb9b68923f05bffd955acbe944 54c14a6b88c00e2db1b256d452f015fc 7fffffffffffffffffffffff7fffffff 54c14a6b88c00e2db1b256d452f015fc fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.s32.f32 q12, q3 8f419be53b6c56b8d923d9e4d3f78549 6614c7bbe698e7af41478a8e41478a8e 7fffffff800000000000000c0000000c 6614c7bbe698e7af41478a8e41478a8e fpscr=00000000
+vcvtm.s32.f32 q12, q3 3e4dc05445c92605cd21ef8056954af7 0427051120def925183cb255368bd6f4 00000000000000000000000000000000 0427051120def925183cb255368bd6f4 fpscr=00000000
+vcvtm.s32.f32 q12, q3 0d1cd88f082e87e00a28bc4bcb553a84 eeb45870a14187b462a2530298ffb2a9 80000000ffffffff7fffffffffffffff eeb45870a14187b462a2530298ffb2a9 fpscr=00000000
+vcvtm.s32.f32 q12, q3 72675eb6f97ac85f566863face03d1f1 9e4cd7124232b041d4b79b85abbcdff5 ffffffff0000002c80000000ffffffff 9e4cd7124232b041d4b79b85abbcdff5 fpscr=00000000
+vcvtm.s32.f32 q12, q3 8c806184f6b2d527b0d023ac88dcb583 2792feb119bbeac878d2b7167bea20e3 00000000000000007fffffff7fffffff 2792feb119bbeac878d2b7167bea20e3 fpscr=00000000
+vcvtm.s32.f32 q12, q3 39f72ed17315a3afea736de291fe4a55 634240dd5a562369a672acb871f54e4e 7fffffff7fffffffffffffff7fffffff 634240dd5a562369a672acb871f54e4e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtm.s32.f32 q12, q3 fa554aa70401c66ffa554aa7af8987c9 bbe262934272dcf41978ace8d3ef23d2 ffffffff0000003c0000000080000000 bbe262934272dcf41978ace8d3ef23d2 fpscr=00000000
+vcvtm.s32.f32 q12, q3 a6713ab8c32c41ab69edac1c0c93049a 92ceb5fff7728d62a0f9625a3cd8fda8 ffffffff80000000ffffffff00000000 92ceb5fff7728d62a0f9625a3cd8fda8 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtm.s32.f32 q12, q3 5e2df758eb700ac39fae2a320b289029 106ca066a036bc10b873922be59bd5d4 00000000ffffffffffffffff80000000 106ca066a036bc10b873922be59bd5d4 fpscr=00000000
+vcvtm.s32.f32 q12, q3 46534ff3b915c3df691c34ec2000a3fc 2f62c4bbdf47259aac084a3692264bc2 0000000080000000ffffffffffffffff 2f62c4bbdf47259aac084a3692264bc2 fpscr=00000000
+vcvtm.s32.f32 q12, q3 4762c1c251c2f13f7216b7596aa10aac b393ddbcdca4bc6c50c8dfee65dd46e2 ffffffff800000007fffffff7fffffff b393ddbcdca4bc6c50c8dfee65dd46e2 fpscr=00000000
+vcvtm.s32.f32 q12, q3 a0c26245ddd22f14d1ca113544b8cf25 fd50b3d0b7538415631ebeb3d95d15a2 80000000ffffffff7fffffff80000000 fd50b3d0b7538415631ebeb3d95d15a2 fpscr=00000000
+vcvtm.s32.f32 q12, q3 ca16b3557d143199ae80befe8edc04fd 5e410a46af36e97dd10601875a0de146 7fffffffffffffff800000007fffffff 5e410a46af36e97dd10601875a0de146 fpscr=00000000
+vcvtm.s32.f32 q12, q3 538603ccee430013539b2f0b9cce4ee1 7d681bd5f647a09ddd4e6dd2618eb6f2 7fffffff80000000800000007fffffff 7d681bd5f647a09ddd4e6dd2618eb6f2 fpscr=00000000
+vcvtm.s32.f32 q12, q3 c9023619cf0ccbf4abfb6bd604b83bfb 30ff0041a815e88bd09c5a0ae8799ead 00000000ffffffff8000000080000000 30ff0041a815e88bd09c5a0ae8799ead fpscr=00000000
+vcvtm.s32.f32 q12, q3 95dcef65994633a260d37e67e09fd2fd 84d0cd04724641473c0f0fa44d22976c ffffffff7fffffff000000000a2976c0 84d0cd04724641473c0f0fa44d22976c fpscr=00000000
+vcvtm.s32.f32 q12, q3 b7b8a21383887898dce1c81be83cfc85 217affe195f5836aa2b971de9836ef00 00000000ffffffffffffffffffffffff 217affe195f5836aa2b971de9836ef00 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.s32.f32 q12, q3 6ce87ead3d1c8ef37334d7e47334d7e4 40c1148a5a5052ee53b57c041e6f2038 000000067fffffff7fffffff00000000 40c1148a5a5052ee53b57c041e6f2038 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtm.s32.f32 q12, q3 dc28fa3377b6be9001e037fa77b6be90 4e0de3456085d588da5dc71d81a76417 2378d1407fffffff80000000ffffffff 4e0de3456085d588da5dc71d81a76417 fpscr=00000000
+vcvtm.s32.f32 q12, q3 426fc804fa33fde86d11f632bd0a625b e37803fee3b2f7c8408cc474e3da2233 80000000800000000000000480000000 e37803fee3b2f7c8408cc474e3da2233 fpscr=00000000
+vcvtm.s32.f32 q12, q3 ff12556d3603a5deceb544dfe40236aa 413d71e361c0134d83036f5554217d87 0000000b7fffffffffffffff7fffffff 413d71e361c0134d83036f5554217d87 fpscr=00000000
+vcvtm.s32.f32 q12, q3 3714116e47c94145cfa97e53a9f2988b 53e7dbaa8361999b97e64c10161439e7 7fffffffffffffffffffffff00000000 53e7dbaa8361999b97e64c10161439e7 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.s32.f32 q12, q3 c4b75e80afe8f25d94a7d55cefc032c2 662c9e48e13a6e6c034280f5e5ca0f25 7fffffff800000000000000080000000 662c9e48e13a6e6c034280f5e5ca0f25 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtm.s32.f32 q12, q3 cfac4cba6d92f5499a5968590993c40d 914a7a432973602f13b09407b5dc21be ffffffff0000000000000000ffffffff 914a7a432973602f13b09407b5dc21be fpscr=00000000
+vcvtm.s32.f32 q12, q3 2f13db3db60d0a4c4bb0c83b854e7bde 0f653c8d6ae135f8f78580fec64a94b5 000000007fffffff80000000ffffcd5a 0f653c8d6ae135f8f78580fec64a94b5 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.s32.f32 q12, q3 5d8037e790e549b80a728624a94e1657 1e7bff1b6b175be2d3df52df845d98f4 000000007fffffff80000000ffffffff 1e7bff1b6b175be2d3df52df845d98f4 fpscr=00000000
+vcvtm.s32.f32 q12, q3 df81abd1344f483715470b8d06f29917 1f94738f6c2cf90f088ce31c67fe53d1 000000007fffffff000000007fffffff 1f94738f6c2cf90f088ce31c67fe53d1 fpscr=00000000
+vcvtm.s32.f32 q12, q3 c0499670d84f4f8c9f33eb1a314b7f6a cb8f6f4b97261cacd68db713d532d752 fee1216affffffff8000000080000000 cb8f6f4b97261cacd68db713d532d752 fpscr=00000000
+vcvtm.s32.f32 q12, q3 eca89ac809161032aa4d292816022688 3206480d2c4508053e89cd363971b867 00000000000000000000000000000000 3206480d2c4508053e89cd363971b867 fpscr=00000000
+vcvtm.s32.f32 q12, q3 b85aea389cb5d4dcba191dec35db1805 6a957225e52e2bc7b3da300a749de60e 7fffffff80000000ffffffff7fffffff 6a957225e52e2bc7b3da300a749de60e fpscr=00000000
+vcvtm.s32.f32 q12, q3 42c8146c42ff7e8f205fe05eb1b39ffd 441a61f25e5b8e6f1323838abf2e463b 000002697fffffff00000000ffffffff 441a61f25e5b8e6f1323838abf2e463b fpscr=00000000
+vcvtm.s32.f32 q12, q3 20aa781057d227fbee0701295a059ead e0e2b5e44d669d6d83bb65621dc4af37 800000000e69d6d0ffffffff00000000 e0e2b5e44d669d6d83bb65621dc4af37 fpscr=00000000
+vcvtm.s32.f32 q12, q3 f30faee792bda134be6529049ed05467 a1bdb952173e4a1b9cfc380d399656dc ffffffff00000000ffffffff00000000 a1bdb952173e4a1b9cfc380d399656dc fpscr=00000000
+vcvtm.s32.f32 q12, q3 ccc2be438e04cfc362de966855e0f9e7 87e44e41c72e9aa00b7246d593bb94b3 ffffffffffff516500000000ffffffff 87e44e41c72e9aa00b7246d593bb94b3 fpscr=00000000
+vcvtm.s32.f32 q12, q3 82113fd93d08e82076ed7aa5726e370c e5ce2efc64cf81b081e547b11d5c08f4 800000007fffffffffffffff00000000 e5ce2efc64cf81b081e547b11d5c08f4 fpscr=00000000
+vcvtm.s32.f32 q12, q3 dcf157f7330e9084c9893a578b2b8fec 73d89694a4d43222094c47ff2ec02063 7fffffffffffffff0000000000000000 73d89694a4d43222094c47ff2ec02063 fpscr=00000000
+vcvtm.s32.f32 q12, q3 a0869719d460dd24aceb883f50a4934a c7d9473f06b9be76c29aee26d83d000d fffe4d7100000000ffffffb280000000 c7d9473f06b9be76c29aee26d83d000d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[3]
+vcvtm.s32.f32 q12, q3 2c8aef9347521c30ef6824159f01c3e8 b62ff77d553e33a9c3cd61a4c3cd61a4 ffffffff7ffffffffffffe65fffffe65 b62ff77d553e33a9c3cd61a4c3cd61a4 fpscr=00000000
+vcvtm.s32.f32 q12, q3 7394b28f073667e8d3d8efa737389014 904720ed857d0dd30ce3e4d2b9093a17 ffffffffffffffff00000000ffffffff 904720ed857d0dd30ce3e4d2b9093a17 fpscr=00000000
+vcvtm.s32.f32 q12, q3 5d8174294c8917ee6f128010ed147247 615cb797c9e73670cb5ff6d914035227 7fffffffffe31932ff20092700000000 615cb797c9e73670cb5ff6d914035227 fpscr=00000000
+vcvtm.s32.f32 q12, q3 32f065688aaaf32c28f339bf64d4504c 37d37082b60f44566a23b888bbe63ded 00000000ffffffff7fffffffffffffff 37d37082b60f44566a23b888bbe63ded fpscr=00000000
+vcvtm.s32.f32 q12, q3 73c47068d09fecd4f196f5bd67b277e1 77ce63fff58dfe82f1130cef535a8794 7fffffff80000000800000007fffffff 77ce63fff58dfe82f1130cef535a8794 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtm.s32.f32 q12, q3 ec83f4186569c1733e401acff125d9bf f0d2c92bb8c81b9af6ad7602f6ad7602 80000000ffffffff8000000080000000 f0d2c92bb8c81b9af6ad7602f6ad7602 fpscr=00000000
+vcvtn.u32.f32 d0, d20 bc1c95b662988fcc307c3a8c09461c0d 543f751aedbe7a22e7d97eee51747ba0 bc1c95b662988fcc00000000ffffffff 543f751aedbe7a22e7d97eee51747ba0 fpscr=00000000
+vcvtn.u32.f32 d0, d20 a9a0b5cfc545a59f02c5c785987da382 2c5d5f33fb187272dcd6ab4641f7abbd a9a0b5cfc545a59f000000000000001f 2c5d5f33fb187272dcd6ab4641f7abbd fpscr=00000000
+vcvtn.u32.f32 d0, d20 c7599fed2b07678c13523b114357d0f8 ae0cfae6c9f919fc508f0bea4b667a53 c7599fed2b07678cffffffff00e67a53 ae0cfae6c9f919fc508f0bea4b667a53 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[2]
+vcvtn.u32.f32 d0, d20 cec7a96fa966f5c30823baec0823baec 9b0d7753dcb9beead3f803192dda3405 cec7a96fa966f5c30000000000000000 9b0d7753dcb9beead3f803192dda3405 fpscr=00000000
+vcvtn.u32.f32 d0, d20 93a375ba1d7c2d87d991b72c6f71a801 dcc2f880b3c346ec6172f6db33e94172 93a375ba1d7c2d87ffffffff00000000 dcc2f880b3c346ec6172f6db33e94172 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[2]
+vcvtn.u32.f32 d0, d20 66e35629664bbdcd66e356296b3ecd5e ab375f56ab375f56895a996578b9a28b 66e35629664bbdcd00000000ffffffff ab375f56ab375f56895a996578b9a28b fpscr=00000000
+vcvtn.u32.f32 d0, d20 8559b3d61a36ea4e7bd6213e948285cd 6cda4e0b4d853c12dc8e3cf00ecb64cc 8559b3d61a36ea4e0000000000000000 6cda4e0b4d853c12dc8e3cf00ecb64cc fpscr=00000000
+vcvtn.u32.f32 d0, d20 213601545d02a30e179805c0d26e9938 a646c54a4ae6853979d77f77b152dff7 213601545d02a30effffffff00000000 a646c54a4ae6853979d77f77b152dff7 fpscr=00000000
+vcvtn.u32.f32 d0, d20 1ba9a814fc7911101dc6805a3d20ffc1 a4c81dee01e6b3bb7b936f4c928bff34 1ba9a814fc791110ffffffff00000000 a4c81dee01e6b3bb7b936f4c928bff34 fpscr=00000000
+vcvtn.u32.f32 d0, d20 811c286ec7fbe1d83e8edb25a406291b f50fc3918fc010e5d4248b5f5ebf6c24 811c286ec7fbe1d800000000ffffffff f50fc3918fc010e5d4248b5f5ebf6c24 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtn.u32.f32 d0, d20 4cdda108993732163734839dc5d440f5 114de927f37f580176f61e05114de927 4cdda10899373216ffffffff00000000 114de927f37f580176f61e05114de927 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: 14848 calls, 15355 iters
+vcvtn.u32.f32 d0, d20 0e14e67d6b154dff770060104bb6be04 744eceb8afd9c628bcb1ab6646cca62c 0e14e67d6b154dff0000000000006653 744eceb8afd9c628bcb1ab6646cca62c fpscr=00000000
+vcvtn.u32.f32 d0, d20 6a86849e7806ed30ef87d0b1f3e69a7b 512912178f3cb2e28bc4fad6e0504c26 6a86849e7806ed300000000000000000 512912178f3cb2e28bc4fad6e0504c26 fpscr=00000000
+vcvtn.u32.f32 d0, d20 5a4c5efaebf98a3c3a480445c9e6b778 62fd9f9e1bd0935f22737b463979d26c 5a4c5efaebf98a3c0000000000000000 62fd9f9e1bd0935f22737b463979d26c fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtn.u32.f32 d0, d20 3618fbdda69bba51487d3d62d33db233 71982135ee1136a2ee1136a2b4d8b1d9 3618fbdda69bba510000000000000000 71982135ee1136a2ee1136a2b4d8b1d9 fpscr=00000000
+vcvtn.u32.f32 d0, d20 9f25cc32fbe85cace480951b9a9ce1f3 efa051ace986e83eac84541fb5c1b69a 9f25cc32fbe85cac0000000000000000 efa051ace986e83eac84541fb5c1b69a fpscr=00000000
+vcvtn.u32.f32 d0, d20 5c467d545755aedf0da9496e866686aa 1e1193da73297b613493e8859ca37688 5c467d545755aedf0000000000000000 1e1193da73297b613493e8859ca37688 fpscr=00000000
+vcvtn.u32.f32 d0, d20 f432abe9d284363df424de986fdb603e 71077696299db6ce1aaebdbc438751cd f432abe9d284363d000000000000010f 71077696299db6ce1aaebdbc438751cd fpscr=00000000
+vcvtn.u32.f32 d0, d20 c203742ed669e85f834e22f0d771bd3d 6ec7b36ff99d361174fc5fcec392f51d c203742ed669e85fffffffff00000000 6ec7b36ff99d361174fc5fcec392f51d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.u32.f32 d0, d20 3204e52ca5dedc90aafba03dd085a34d 213f2eb4d9d3f32ec03cca5edf8f6d3b 3204e52ca5dedc900000000000000000 213f2eb4d9d3f32ec03cca5edf8f6d3b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtn.u32.f32 d0, d20 de4ab5bf759af0ca65d8cfc865d8cfc8 ece3f81ebb1b57787e7c21f3ec4b607e de4ab5bf759af0caffffffff00000000 ece3f81ebb1b57787e7c21f3ec4b607e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtn.u32.f32 d0, d20 60e22955f58616eaf095ce36da882b27 84be346e21f0bd716408cd2ebab4fb3d 60e22955f58616eaffffffff00000000 84be346e21f0bd716408cd2ebab4fb3d fpscr=00000000
+vcvtn.u32.f32 d0, d20 cef2508e7c7654403338be461137f4a0 d30e6828a7e1c7c0dd4f0f8e9705f840 cef2508e7c7654400000000000000000 d30e6828a7e1c7c0dd4f0f8e9705f840 fpscr=00000000
+vcvtn.u32.f32 d0, d20 3b572300ba08b0bc1002855bfcbb9ec4 f1a9fb63616cb0c0fefa5159f987951b 3b572300ba08b0bc0000000000000000 f1a9fb63616cb0c0fefa5159f987951b fpscr=00000000
+vcvtn.u32.f32 d0, d20 7795fa0e7261107e51da35635a3c5611 0ca248bfafaf9a4ae00dac5506e002e8 7795fa0e7261107e0000000000000000 0ca248bfafaf9a4ae00dac5506e002e8 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtn.u32.f32 d0, d20 f4bacd0d7ded886a0bf56713f4493e64 edafb53990aed1215c2f3df22e523d47 f4bacd0d7ded886affffffff00000000 edafb53990aed1215c2f3df22e523d47 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtn.u32.f32 d0, d20 6ad688c2be2c9943f4ad945969c5fc7e 722b74385393c90f8f8619e2d919e0c9 6ad688c2be2c99430000000000000000 722b74385393c90f8f8619e2d919e0c9 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtn.u32.f32 d0, d20 1b3b68dc5457fdff1b0a0bba459ebe0c 4001b2caa8eb1d366a687778aeb2fa1e 1b3b68dc5457fdffffffffff00000000 4001b2caa8eb1d366a687778aeb2fa1e fpscr=00000000
+vcvtn.u32.f32 d0, d20 98bbb1920beeb8bc8563ad1338b547f5 5e1667d22045bda7463125f7b0c22749 98bbb1920beeb8bc00002c4900000000 5e1667d22045bda7463125f7b0c22749 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtn.u32.f32 d0, d20 d05736a051d06a37ac581c3cd05736a0 f2351feb6bed7bbbc12df059431abc2b d05736a051d06a37000000000000009b f2351feb6bed7bbbc12df059431abc2b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtn.u32.f32 d0, d20 db1decb2f46cc712db72a00406cc40c9 c151cbb574da982f7611670a77971a95 db1decb2f46cc712ffffffffffffffff c151cbb574da982f7611670a77971a95 fpscr=00000000
+vcvtn.u32.f32 d0, d20 4361b3c3e318e9c04a4a0ef54aa027c1 545db7eb4425fa79c12aa51dad9301ad 4361b3c3e318e9c00000000000000000 545db7eb4425fa79c12aa51dad9301ad fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtn.u32.f32 d0, d20 76ed21fbc55de2cda589a385a6facf42 78fe2fcadf80231618a2d02518a2d025 76ed21fbc55de2cd0000000000000000 78fe2fcadf80231618a2d02518a2d025 fpscr=00000000
+vcvtn.u32.f32 d0, d20 b69bb395ff2b381ace62f14b83163a80 e3df157dc6eb4fb7086b0065f90ae48b b69bb395ff2b381a0000000000000000 e3df157dc6eb4fb7086b0065f90ae48b fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtn.u32.f32 d0, d20 298840d38b3f88125d543a68298840d3 b5c2b3cd6598650c83f6e2d01a47f97e 298840d38b3f88120000000000000000 b5c2b3cd6598650c83f6e2d01a47f97e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtn.u32.f32 d0, d20 0fe36084f367d2e420bf04dd92bfda99 4ba5d4bb5b39359062a21cb622bca62b 0fe36084f367d2e4ffffffff00000000 4ba5d4bb5b39359062a21cb622bca62b fpscr=00000000
+vcvtn.u32.f32 d0, d20 3bd330f05d0b6fa573a75cbe66d88bc9 2e1108f814b01e2968c16ea93a95afcf 3bd330f05d0b6fa5ffffffff00000000 2e1108f814b01e2968c16ea93a95afcf fpscr=00000000
+vcvtn.u32.f32 d0, d20 3d2b7fa8fe76b2a1c5f1c52117df0700 70dd4cc3a7e96b2bea7d3c3dad2fcf73 3d2b7fa8fe76b2a10000000000000000 70dd4cc3a7e96b2bea7d3c3dad2fcf73 fpscr=00000000
+vcvtn.u32.f32 d0, d20 665ef64de7b8133e5ceba099c34b7336 4f1d87f3963fd06eed35d7e47f388640 665ef64de7b8133e00000000ffffffff 4f1d87f3963fd06eed35d7e47f388640 fpscr=00000000
+vcvtn.u32.f32 d0, d20 41dc92cac5fa931af334ea88b7125db8 ac3d368e0dedca65575bfbf5df572d83 41dc92cac5fa931affffffff00000000 ac3d368e0dedca65575bfbf5df572d83 fpscr=00000000
+vcvtn.u32.f32 d0, d20 ac4e6765f91e9461ad85a8ebc2806467 e55bc34a8ab7c6fb141e33689391aeb8 ac4e6765f91e94610000000000000000 e55bc34a8ab7c6fb141e33689391aeb8 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.u32.f32 d0, d20 42c9154b9618f076bf2ca52a7dde989e c3264280e771fb2be771fb2b440fa25d 42c9154b9618f076000000000000023f c3264280e771fb2be771fb2b440fa25d fpscr=00000000
+vcvtn.u32.f32 d0, d20 3f512a7c20f7a3fccd2c6e84746b7ec7 bc05a94d4c2b0e884edf2af72f53f42a 3f512a7c20f7a3fc6f957b8000000000 bc05a94d4c2b0e884edf2af72f53f42a fpscr=00000000
+vcvtn.u32.f32 d0, d20 618fa6ab0d0dac9eb2129ae992b723ea 240db6306f73496803043ebb6d2af262 618fa6ab0d0dac9e00000000ffffffff 240db6306f73496803043ebb6d2af262 fpscr=00000000
+vcvtn.u32.f32 d0, d20 677a1f0cfcad002461ecf68824d2a3d1 19aa7caf919236f011c0c4e37a954b17 677a1f0cfcad002400000000ffffffff 19aa7caf919236f011c0c4e37a954b17 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtn.u32.f32 d0, d20 3f16fce2f7a19062842b97f39bd0681b 5a161462fd057e2cdbdc5106814bfb1e 3f16fce2f7a190620000000000000000 5a161462fd057e2cdbdc5106814bfb1e fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtn.u32.f32 d0, d20 d0a074ce772c617ecbfa3a49157d58ec 4b1f2804b954e34a483b8c6bb954e34a d0a074ce772c617e0002ee3200000000 4b1f2804b954e34a483b8c6bb954e34a fpscr=00000000
+vcvtn.u32.f32 d0, d20 3b0b88873cd3b14e9c1d50265b65e324 d68d1d32502613f3048337865c953174 3b0b88873cd3b14e00000000ffffffff d68d1d32502613f3048337865c953174 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtn.u32.f32 d0, d20 3db06f2ad65527a712fb066b22c80861 4daa95a32011194bcbfd4d55c8b74cb5 3db06f2ad65527a70000000000000000 4daa95a32011194bcbfd4d55c8b74cb5 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtn.u32.f32 d0, d20 a4530254bb4155a58bf99b7791252d3d 6eb4211edfd22d868b172d18a4c79bf0 a4530254bb4155a50000000000000000 6eb4211edfd22d868b172d18a4c79bf0 fpscr=00000000
+vcvta.u32.f32 d5, d25 019e06a05f954184c431f9b93df029f4 17f4a9a06a18fb530714031dfe090e24 00000000ffffffffc431f9b93df029f4 17f4a9a06a18fb530714031dfe090e24 fpscr=00000000
+vcvta.u32.f32 d5, d25 96ff2a102ce969baab648b3c5bc1cf0a 1a432b5a56a7fa6bc422d1b8ec389497 00000000ffffffffab648b3c5bc1cf0a 1a432b5a56a7fa6bc422d1b8ec389497 fpscr=00000000
+vcvta.u32.f32 d5, d25 eb70a0f38a3e8aa6fa6450c83325e25c a8d3757c747920df6f5434510b40d241 00000000fffffffffa6450c83325e25c a8d3757c747920df6f5434510b40d241 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[2]
+vcvta.u32.f32 d5, d25 47aba37f8c7899d747aba37fcaee19ac 0f67b0abd6aba8320453ad15d6aba832 000000000000000047aba37fcaee19ac 0f67b0abd6aba8320453ad15d6aba832 fpscr=00000000
+vcvta.u32.f32 d5, d25 d79e0101969c4ef61bc806046a16a82d f8e29a8a8e461e0ef2fab2f8beb66be8 00000000000000001bc806046a16a82d f8e29a8a8e461e0ef2fab2f8beb66be8 fpscr=00000000
+vcvta.u32.f32 d5, d25 3ee55f34eb970b35581202834fa2cceb 8b13301c455d01bef8f3c9bc78562081 0000000000000dd0581202834fa2cceb 8b13301c455d01bef8f3c9bc78562081 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.u32.f32 d5, d25 fdb8e27efdb8e27e4d4f51a73b20f319 e0d0578f8ea9c5fea237a20a86b77f9f 00000000000000004d4f51a73b20f319 e0d0578f8ea9c5fea237a20a86b77f9f fpscr=00000000
+vcvta.u32.f32 d5, d25 a2448c90c9d49c67d51b1d451d317d36 f6de4206f048d5c16b02dc4bfded93f5 0000000000000000d51b1d451d317d36 f6de4206f048d5c16b02dc4bfded93f5 fpscr=00000000
+vcvta.u32.f32 d5, d25 f3a31b63cfea9cece043121024fc6f0f 1b02e345b53f7d35d702f281e37afb69 0000000000000000e043121024fc6f0f 1b02e345b53f7d35d702f281e37afb69 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.u32.f32 d5, d25 33a0f903f39c5c9033a0f90386fe166a 3e6c8fcc3e6c8fcc09ec598d1aa314a3 000000000000000033a0f90386fe166a 3e6c8fcc3e6c8fcc09ec598d1aa314a3 fpscr=00000000
+vcvta.u32.f32 d5, d25 26f9ad898918d8ae8caa5b2e4e5c198b ab7ae9d77b2bd0bc3774ebb37320aea6 00000000ffffffff8caa5b2e4e5c198b ab7ae9d77b2bd0bc3774ebb37320aea6 fpscr=00000000
+vcvta.u32.f32 d5, d25 9ab3d4d06cf9b51416e12ec1e5faeef5 08c1decd1db2750d1739dd8b3ff5af61 000000000000000016e12ec1e5faeef5 08c1decd1db2750d1739dd8b3ff5af61 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[3]
+vcvta.u32.f32 d5, d25 add2b91587f8d562bffc1a97aa4ecb1d 5c6e3fd90ccf3bb90ccf3bb922a54539 ffffffff00000000bffc1a97aa4ecb1d 5c6e3fd90ccf3bb90ccf3bb922a54539 fpscr=00000000
+vcvta.u32.f32 d5, d25 6d464258301b3a7ccfea27f2ff321a33 87c3c256b1340db3a3956f8f698c920b 0000000000000000cfea27f2ff321a33 87c3c256b1340db3a3956f8f698c920b fpscr=00000000
+vcvta.u32.f32 d5, d25 7b3bbf60629e8ee035f5f00518abb45c 08b8a16f65d2bbcb0469e92542bc8a43 00000000ffffffff35f5f00518abb45c 08b8a16f65d2bbcb0469e92542bc8a43 fpscr=00000000
+vcvta.u32.f32 d5, d25 ba588f4e9a1a5413418d65863fa93c9c a420ea64b8ca700bc62303646c7bd645 0000000000000000418d65863fa93c9c a420ea64b8ca700bc62303646c7bd645 fpscr=00000000
+vcvta.u32.f32 d5, d25 4ef819b755b9846419458d018a177c81 5ea935c5ac390aa92dcd05976c4f2afc ffffffff0000000019458d018a177c81 5ea935c5ac390aa92dcd05976c4f2afc fpscr=00000000
+vcvta.u32.f32 d5, d25 d1d87b5730d0c11cc6404a530b87d8b0 abc377d533b9b23322e5a44d573ee150 0000000000000000c6404a530b87d8b0 abc377d533b9b23322e5a44d573ee150 fpscr=00000000
+vcvta.u32.f32 d5, d25 18bd4f76ee40a34abe7d5367d6151d91 ec1f6588253204597c6ddbc394a7e4b5 0000000000000000be7d5367d6151d91 ec1f6588253204597c6ddbc394a7e4b5 fpscr=00000000
+vcvta.u32.f32 d5, d25 602ac1c13bfa75a586c25278da5faff6 96114a7815ef611a4794041d98a71054 000000000000000086c25278da5faff6 96114a7815ef611a4794041d98a71054 fpscr=00000000
+vcvta.u32.f32 d5, d25 45b2c8f2f0d751c186f7a0c679bf6942 dfc5d5be4262e87c7ee0f5e973c9d701 000000000000003986f7a0c679bf6942 dfc5d5be4262e87c7ee0f5e973c9d701 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvta.u32.f32 d5, d25 2920fd9d2920fd9d374a45c8db14b038 3d958daa823806b57de724e2a39b86d2 0000000000000000374a45c8db14b038 3d958daa823806b57de724e2a39b86d2 fpscr=00000000
+vcvta.u32.f32 d5, d25 b78ea467c2672b72a9a131bbd4c515e4 cd1733c45fa3ad353467b8c12aea9a71 00000000ffffffffa9a131bbd4c515e4 cd1733c45fa3ad353467b8c12aea9a71 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvta.u32.f32 d5, d25 a606eef6aef438048bef18fc2ccb3ee2 b8b1bfd73499b0a3310d55ca310d55ca 00000000000000008bef18fc2ccb3ee2 b8b1bfd73499b0a3310d55ca310d55ca fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvta.u32.f32 d5, d25 3a4d611bb110fdc73a4d611b6cba1201 73f9cca33b2e1384787506714462328e ffffffff000000003a4d611b6cba1201 73f9cca33b2e1384787506714462328e fpscr=00000000
+randV128: 15104 calls, 15614 iters
+vcvta.u32.f32 d5, d25 1425d7120ba7cf16d48b42d3540acd3e fcabc659ad62faea4eeefefb568250e2 0000000000000000d48b42d3540acd3e fcabc659ad62faea4eeefefb568250e2 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.u32.f32 d5, d25 25f6e618cd7054b6544b747b4aa79172 4485c7f436b03df6951db120dbb2ac42 0000042e00000000544b747b4aa79172 4485c7f436b03df6951db120dbb2ac42 fpscr=00000000
+vcvta.u32.f32 d5, d25 2442587c395c3c595b266d70e5d1d7ff edcbbcd9dabd69f460c91715c25e8d08 00000000000000005b266d70e5d1d7ff edcbbcd9dabd69f460c91715c25e8d08 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[1]
+vcvta.u32.f32 d5, d25 73f50537d5e1c1cec044a8d82321d387 c9ed0bbf8d8b395e05db89b0ed28fcb8 0000000000000000c044a8d82321d387 c9ed0bbf8d8b395e05db89b0ed28fcb8 fpscr=00000000
+vcvta.u32.f32 d5, d25 c1428da3ce52a93c16c435c3ae1068fe 0ebf38e3342da351fd74feb3d9fccfae 000000000000000016c435c3ae1068fe 0ebf38e3342da351fd74feb3d9fccfae fpscr=00000000
+vcvta.u32.f32 d5, d25 dc0701ab5d45d257d73a1ac8e8be2690 98f2f64c5a8f1e5ba5e1aee871ff5595 00000000ffffffffd73a1ac8e8be2690 98f2f64c5a8f1e5ba5e1aee871ff5595 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.u32.f32 d5, d25 c96736afd5fdde024ce8caf0ce84c8aa b243837757983fda710a5b1ff25a54d4 00000000ffffffff4ce8caf0ce84c8aa b243837757983fda710a5b1ff25a54d4 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvta.u32.f32 d5, d25 8efcf67376a73215f6eb4691a48ced0a 71c05c1d74121b6aeb3f8e8e5d69338e fffffffffffffffff6eb4691a48ced0a 71c05c1d74121b6aeb3f8e8e5d69338e fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[2]
+vcvta.u32.f32 d5, d25 3431597f3431597f18ec2d28983f3688 098451934154356fb7dd2626877d8be7 000000000000000d18ec2d28983f3688 098451934154356fb7dd2626877d8be7 fpscr=00000000
+vcvta.u32.f32 d5, d25 f1507743f5330572d2adfc64ec0b76e2 1a075caaf8fb6e0bf18e0968be04545a 0000000000000000d2adfc64ec0b76e2 1a075caaf8fb6e0bf18e0968be04545a fpscr=00000000
+vcvta.u32.f32 d5, d25 b482eaaad844da479fd4f072b83380f7 f69752e6cfe08e27da1edd93cd0be6e3 00000000000000009fd4f072b83380f7 f69752e6cfe08e27da1edd93cd0be6e3 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.u32.f32 d5, d25 c2eaba31b81ae0e38dc40b3bf2027415 daa7d4514cf847e51bdf040ca6c212cc 0000000007c23f288dc40b3bf2027415 daa7d4514cf847e51bdf040ca6c212cc fpscr=00000000
+vcvta.u32.f32 d5, d25 f30de7ccfb6bf55656b1a7e5bec0dd65 883df6c5eb9ee1c2852639b79f2e21ad 000000000000000056b1a7e5bec0dd65 883df6c5eb9ee1c2852639b79f2e21ad fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.u32.f32 d5, d25 2338e7de642929076013635877c4e7be f2eebbbad3a3d86b9315f9b0d3a3d86b 00000000000000006013635877c4e7be f2eebbbad3a3d86b9315f9b0d3a3d86b fpscr=00000000
+vcvta.u32.f32 d5, d25 6314492a5722dcfb9105d0b97265ecbb 51c6027ef7df036e027ee4da46f8444a ffffffff000000009105d0b97265ecbb 51c6027ef7df036e027ee4da46f8444a fpscr=00000000
+vcvta.u32.f32 d5, d25 b25e2136668f6dec2378eabf59e74893 4d144bbd8dd92470cb24ba5f6e9f3a01 0944bbd0000000002378eabf59e74893 4d144bbd8dd92470cb24ba5f6e9f3a01 fpscr=00000000
+vcvta.u32.f32 d5, d25 bf58f5c3b83a39b6b2bb2144c11975c4 58df4d23420256e284218ab1c1d94c3f ffffffff00000021b2bb2144c11975c4 58df4d23420256e284218ab1c1d94c3f fpscr=00000000
+vcvta.u32.f32 d5, d25 a9e8154a93553054920d96c11f4a56db 06551dc530f7300f2e8e271a2ec7a744 0000000000000000920d96c11f4a56db 06551dc530f7300f2e8e271a2ec7a744 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvta.u32.f32 d5, d25 ee8b8841b4ac4701babbd1043a6cc3bc ea6d5144c5255eed2e3ab478b1413bba 0000000000000000babbd1043a6cc3bc ea6d5144c5255eed2e3ab478b1413bba fpscr=00000000
+vcvta.u32.f32 d5, d25 0ababfab7a74211cf515de8a597834c5 017626b2a0da8a5d12d3672df8e75e67 0000000000000000f515de8a597834c5 017626b2a0da8a5d12d3672df8e75e67 fpscr=00000000
+vcvta.u32.f32 d5, d25 fcff9517c72243fc99b0af203d24a5ae a733e2681d346af5d28a5af4db523ba0 000000000000000099b0af203d24a5ae a733e2681d346af5d28a5af4db523ba0 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvta.u32.f32 d5, d25 3da3e016175ed68ef51727edb2d8c6ab 1091a0e7dfda58451db9feff0e51bafc 0000000000000000f51727edb2d8c6ab 1091a0e7dfda58451db9feff0e51bafc fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvta.u32.f32 d5, d25 30502f9dd6765b50131d12f3e1be6a7e 919106e4b917ea619fea4d63bf8a6fd0 0000000000000000131d12f3e1be6a7e 919106e4b917ea619fea4d63bf8a6fd0 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvta.u32.f32 d5, d25 ce487ec55c59d31ef437c442b20cdbe5 e7ad171ceef993d3e7ad171cd36187ba 0000000000000000f437c442b20cdbe5 e7ad171ceef993d3e7ad171cd36187ba fpscr=00000000
+vcvta.u32.f32 d5, d25 ce2b72b83915fc53027e3d01c7db7fe7 d5b8e6ba88ea4dd2e0e3206a899fceb6 0000000000000000027e3d01c7db7fe7 d5b8e6ba88ea4dd2e0e3206a899fceb6 fpscr=00000000
+vcvtp.u32.f32 d10, d30 d51add7e0c537590452fcd41f5fb5326 959964003b6b4113327c9d773d66ac09 d51add7e0c5375900000000100000001 959964003b6b4113327c9d773d66ac09 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtp.u32.f32 d10, d30 f1f4b3d3552b0348b5aa4872bf422171 105ff6f0482e163127436335bcb5fd17 f1f4b3d3552b03480000000100000000 105ff6f0482e163127436335bcb5fd17 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtp.u32.f32 d10, d30 018774cf912763574be6fe62089faa91 98c6b58e854e387e3f7ee72505b8f91e 018774cf912763570000000100000001 98c6b58e854e387e3f7ee72505b8f91e fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.u32.f32 d10, d30 5e917712dd7d55f29873c7749e36b06e 4b352c4b9013c997ef6fac1e121e9cd1 5e917712dd7d55f20000000000000001 4b352c4b9013c997ef6fac1e121e9cd1 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.u32.f32 d10, d30 5a7ac901ce1c00ff1d6cc96bb91b4cd1 dcf166cd9296dd219296dd21559b64b1 5a7ac901ce1c00ff00000000ffffffff dcf166cd9296dd219296dd21559b64b1 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.u32.f32 d10, d30 d8547a443b12866efd0b3c4c8a36d45e 66daee2c34ea7791a9fe6d6b34ea7791 d8547a443b12866e0000000000000001 66daee2c34ea7791a9fe6d6b34ea7791 fpscr=00000000
+vcvtp.u32.f32 d10, d30 23719bca3322f2963077f595aa4adbda 985c689f2bd5055d42343fee1ed48cff 23719bca3322f2960000002e00000001 985c689f2bd5055d42343fee1ed48cff fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.u32.f32 d10, d30 bde5d361d2725ec0e609c404d2725ec0 5e18e9480566bb6e5ba4bb66049b903d bde5d361d2725ec0ffffffff00000001 5e18e9480566bb6e5ba4bb66049b903d fpscr=00000000
+vcvtp.u32.f32 d10, d30 04ef28499294c22b6ab42d155c0f5ba3 9bcd755ca9628cda27b5770b182c0d40 04ef28499294c22b0000000100000001 9bcd755ca9628cda27b5770b182c0d40 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.u32.f32 d10, d30 00eecbb4bba776af055309cba364057b f1848019e93b522def934a595e2e5987 00eecbb4bba776af00000000ffffffff f1848019e93b522def934a595e2e5987 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtp.u32.f32 d10, d30 3918ee681622bce21622bce200b98e8d dc8ebaedcd97bbc39cdf57c041ada9b4 3918ee681622bce20000000000000016 dc8ebaedcd97bbc39cdf57c041ada9b4 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.u32.f32 d10, d30 0277efb7f99323b769520b2f2e047fb8 77cbd44184c944d310447027fa12fdeb 0277efb7f99323b70000000100000000 77cbd44184c944d310447027fa12fdeb fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.u32.f32 d10, d30 7a27e6b330705d8dfa1e98cfc525d0d6 8232d5ab9dc88e5f1d2eee341d2eee34 7a27e6b330705d8d0000000100000001 8232d5ab9dc88e5f1d2eee341d2eee34 fpscr=00000000
+vcvtp.u32.f32 d10, d30 664eb0dd63958cb9e0c950895bc1961e 68b814c1bc54bf9c12a15038dd7e307e 664eb0dd63958cb90000000100000000 68b814c1bc54bf9c12a15038dd7e307e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.u32.f32 d10, d30 d66002c7cd0b18c2fec04f70b4b7d034 ec15274c193ad82fcbd02292cc43c5f6 d66002c7cd0b18c20000000000000000 ec15274c193ad82fcbd02292cc43c5f6 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtp.u32.f32 d10, d30 b6cbfc3948c86e11935e4458b6cbfc39 aabdeda4934df81f3088de77ca171d5e b6cbfc3948c86e110000000100000000 aabdeda4934df81f3088de77ca171d5e fpscr=00000000
+vcvtp.u32.f32 d10, d30 200b6643c39d571978661bf670949059 0b81d6d9cc7121e9dde6702a812f0e3a 200b6643c39d57190000000000000000 0b81d6d9cc7121e9dde6702a812f0e3a fpscr=00000000
+vcvtp.u32.f32 d10, d30 fbb9b3a6c7948e22835b14167903ae96 e785559d07a7d9c866772a2fd28a21e0 fbb9b3a6c7948e22ffffffff00000000 e785559d07a7d9c866772a2fd28a21e0 fpscr=00000000
+vcvtp.u32.f32 d10, d30 98e9a2384cbd41fa6d9935621b981a26 8c2989a0737eb29f0a2310ce5a2ce9d6 98e9a2384cbd41fa00000001ffffffff 8c2989a0737eb29f0a2310ce5a2ce9d6 fpscr=00000000
+vcvtp.u32.f32 d10, d30 f23e3f3c70a9cf5e80fb45bd71fabbe3 b29789ffbc6b7ac67432822ff3565a4b f23e3f3c70a9cf5effffffff00000000 b29789ffbc6b7ac67432822ff3565a4b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.u32.f32 d10, d30 9f999fcb2809ca727341c8e2f9531dcf 2b69e1f9d811d561af30fb51ca03a3ac 9f999fcb2809ca720000000000000000 2b69e1f9d811d561af30fb51ca03a3ac fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtp.u32.f32 d10, d30 5c45d7ec9e5551f677fb5eac2b092f2a 21ea686964eb70b1f105b7ddbc12ef32 5c45d7ec9e5551f60000000000000000 21ea686964eb70b1f105b7ddbc12ef32 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtp.u32.f32 d10, d30 11bd7f37d2a2666b0d5a2c44d019de17 689eb0940ef0e3c8a6321c31b382905b 11bd7f37d2a2666b0000000000000000 689eb0940ef0e3c8a6321c31b382905b fpscr=00000000
+vcvtp.u32.f32 d10, d30 cd4d05d8ff5a3ea837b1f3f5325e8d45 a7901b12093557ab2ce091d56d584413 cd4d05d8ff5a3ea800000001ffffffff a7901b12093557ab2ce091d56d584413 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtp.u32.f32 d10, d30 85cc2790eafa4d6de527a2dad3b39ce9 ed8892801e7fac86772ffa6746c8343b 85cc2790eafa4d6dffffffff0000641b ed8892801e7fac86772ffa6746c8343b fpscr=00000000
+vcvtp.u32.f32 d10, d30 82b4b25f2c56034c319d4eb5661b3aae 5044f396e359d3d520d9dc5f5f7dceb5 82b4b25f2c56034c00000001ffffffff 5044f396e359d3d520d9dc5f5f7dceb5 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtp.u32.f32 d10, d30 52be77ec55018fb8907dfee76ffab899 973a281b973a281b898355aa3dcd69d3 52be77ec55018fb80000000000000001 973a281b973a281b898355aa3dcd69d3 fpscr=00000000
+vcvtp.u32.f32 d10, d30 5f00785db0e889f454daf29d3c8f03d4 2efe0c54f8b14464dce1eb23371f571f 5f00785db0e889f40000000000000001 2efe0c54f8b14464dce1eb23371f571f fpscr=00000000
+vcvtp.u32.f32 d10, d30 e3d1eef431135868ad4b40278396a0de e1c60810c4c7f2b356ebc9dc1f2b12ad e3d1eef431135868ffffffff00000001 e1c60810c4c7f2b356ebc9dc1f2b12ad fpscr=00000000
+vcvtp.u32.f32 d10, d30 c0b123bd0c06b229e2029633628c20cc a07edd209d906e80c0c66b086db66596 c0b123bd0c06b22900000000ffffffff a07edd209d906e80c0c66b086db66596 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.u32.f32 d10, d30 71f6f04400a7e3dbd1ae95a0d1ae95a0 70da484ed7eff69f5d932df5a65e035b 71f6f04400a7e3dbffffffff00000000 70da484ed7eff69f5d932df5a65e035b fpscr=00000000
+vcvtp.u32.f32 d10, d30 096de7991a457c5e4ce649d650b60c1d 550332ae19ebea94975b6e23cc497357 096de7991a457c5e0000000000000000 550332ae19ebea94975b6e23cc497357 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[1]
+vcvtp.u32.f32 d10, d30 a24d150ce2dec90ee2dec90e0a14fe1c b52e6e05bb6df896efbdaeacdc634540 a24d150ce2dec90e0000000000000000 b52e6e05bb6df896efbdaeacdc634540 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtp.u32.f32 d10, d30 4e6189ed69fd06cfb7153c02621d45ce 06d47c31871adb710d62a05aad65c201 4e6189ed69fd06cf0000000100000000 06d47c31871adb710d62a05aad65c201 fpscr=00000000
+vcvtp.u32.f32 d10, d30 282b3d3b841f1487bcb63da4f4d752fa 33033f816b0243a8e2cbc246c5194fb5 282b3d3b841f14870000000000000000 33033f816b0243a8e2cbc246c5194fb5 fpscr=00000000
+vcvtp.u32.f32 d10, d30 6291f04c0fc11b275103e289f9ee3b2a 4eb876a398afa64a6440881b3d5c0218 6291f04c0fc11b27ffffffff00000001 4eb876a398afa64a6440881b3d5c0218 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtp.u32.f32 d10, d30 affac8f21fc6ea69fbe37bef956ed452 7f22565592bcde81e85773cee85773ce affac8f21fc6ea690000000000000000 7f22565592bcde81e85773cee85773ce fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[3]
+vcvtp.u32.f32 d10, d30 36262e4d7370a20b36262e4d8539ccf1 fd9422a12d0d67182d0d67181415788b 36262e4d7370a20b0000000100000001 fd9422a12d0d67182d0d67181415788b fpscr=00000000
+vcvtp.u32.f32 d10, d30 e24334eb6d078822ac5f050d24cb1fb8 6e02b07fb70d9fd77489491a1302730d e24334eb6d078822ffffffff00000001 6e02b07fb70d9fd77489491a1302730d fpscr=00000000
+randV128: 15360 calls, 15882 iters
+vcvtp.u32.f32 d10, d30 40680e056c075c0101be50e1f8a80994 4ebb6a5ead74eeb3b9815ad00525782d 40680e056c075c010000000000000001 4ebb6a5ead74eeb3b9815ad00525782d fpscr=00000000
+vcvtp.u32.f32 d10, d30 908222e72f6084e369586bcca9ec51b0 cb69dd8f8948c1ec8190d147c9c125fb 908222e72f6084e30000000000000000 cb69dd8f8948c1ec8190d147c9c125fb fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.u32.f32 d10, d30 10be492570ec1c59f5e287ec70ec1c59 d94f533821bd07b52e7effdf8a196888 10be492570ec1c590000000100000000 d94f533821bd07b52e7effdf8a196888 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[2]
+vcvtp.u32.f32 d10, d30 09592d5a09592d5a44761afa896f5da6 a35f1f63761367d81b64a6ca761367d8 09592d5a09592d5a00000001ffffffff a35f1f63761367d81b64a6ca761367d8 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[2]
+vcvtp.u32.f32 d10, d30 6d354ea12a9a8fce0f0fbde7e4944986 a454ac4654c919376b0dfbc5a454ac46 6d354ea12a9a8fceffffffff00000000 a454ac4654c919376b0dfbc5a454ac46 fpscr=00000000
+vcvtp.u32.f32 d10, d30 4c9f558dd8f3c3894c61a454db96bbf1 82dbb866eb3ffabfb2b576b012571192 4c9f558dd8f3c3890000000000000001 82dbb866eb3ffabfb2b576b012571192 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtp.u32.f32 d10, d30 8458f92afc6bf28e7e9c3076df89abd6 e164ebbf9c4236ea0219f31b8e30a427 8458f92afc6bf28e0000000100000000 e164ebbf9c4236ea0219f31b8e30a427 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtp.u32.f32 d10, d30 699e2f4d699e2f4d4ce1fcbf7e092808 127395a0a809c00f4a7ae2a0fdf11394 699e2f4d699e2f4d003eb8a800000000 127395a0a809c00f4a7ae2a0fdf11394 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtp.u32.f32 d10, d30 aefd542c1f944c58aefd542c3a506ba7 4fb825acee8fc0b7f7a538f921d523a7 aefd542c1f944c580000000000000001 4fb825acee8fc0b7f7a538f921d523a7 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtp.u32.f32 d10, d30 e55201b50b64cd16ab70da2f0afce007 da44c73d09d5d2e13f4d2e6a458a0e52 e55201b50b64cd160000000100001142 da44c73d09d5d2e13f4d2e6a458a0e52 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtp.u32.f32 d10, d30 1a5d01768b2c1aaefe7646afda8e76af 0c743a12d4aef5be75a45901fd128fed 1a5d01768b2c1aaeffffffff00000000 0c743a12d4aef5be75a45901fd128fed fpscr=00000000
+vcvtm.u32.f32 d15, d15 b5f36916f534df9c94c4e20afb3487c6 225b986c5dd95c84c8ac42a66e85292c 00000000ffffffffc8ac42a66e85292c 00000000ffffffffc8ac42a66e85292c fpscr=00000000
+vcvtm.u32.f32 d15, d15 c92fbbd6545b976053b9a3bb90419abd dc349e578b7e6a403556210a2dac8882 00000000000000003556210a2dac8882 00000000000000003556210a2dac8882 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtm.u32.f32 d15, d15 e0aab3f099485cf1c5124091dd8e597a ff46191c4ead2be058c1e196d933f638 000000005695f00058c1e196d933f638 000000005695f00058c1e196d933f638 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.u32.f32 d15, d15 e483b213af8e395d5f573dba4b77d5a6 38d81f0b38d81f0bc09232658bee3107 0000000000000000c09232658bee3107 0000000000000000c09232658bee3107 fpscr=00000000
+vcvtm.u32.f32 d15, d15 3d1f60772e460894b6d74faf98026637 a47a07f5e3f2783f5dde651dd70f70db 00000000000000005dde651dd70f70db 00000000000000005dde651dd70f70db fpscr=00000000
+vcvtm.u32.f32 d15, d15 3089d6d11545188918f5e36b1ea2f7f1 ac5b0f35500571b82fcf5d527d723163 00000000ffffffff2fcf5d527d723163 00000000ffffffff2fcf5d527d723163 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[1]
+vcvtm.u32.f32 d15, d15 01fd8a904f6c654ca3225569a3225569 059c049fb35ff29db3d4e72868998085 0000000000000000b3d4e72868998085 0000000000000000b3d4e72868998085 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.u32.f32 d15, d15 c2497635f64887986d2871524c7866b9 398e021d3b0d2174cf94f491c8f4995d 0000000000000000cf94f491c8f4995d 0000000000000000cf94f491c8f4995d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtm.u32.f32 d15, d15 5d8f4220b153b57630ae000d67539412 cd304fb28a9aa609e04a2d81ab9430fd 0000000000000000e04a2d81ab9430fd 0000000000000000e04a2d81ab9430fd fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+vcvtm.u32.f32 d15, d15 badea1a6badea1a665a8afe9df4ea84c d9c057dacaeea12ecaeea12e216e7575 0000000000000000caeea12e216e7575 0000000000000000caeea12e216e7575 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[3]
+vcvtm.u32.f32 d15, d15 97324607b0c8a1655f862636ab463f6d 0abb7778686721460abb777805bcbd00 00000000ffffffff0abb777805bcbd00 00000000ffffffff0abb777805bcbd00 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[1]
+vcvtm.u32.f32 d15, d15 6da96d9b3ac0adf87d2e08b46da96d9b 5e8c4ab4407df216bdcc8f03975516a9 ffffffff00000003bdcc8f03975516a9 ffffffff00000003bdcc8f03975516a9 fpscr=00000000
+vcvtm.u32.f32 d15, d15 412eb1e4f60775c9eca6cd56d82837e1 3227f3d222d5a34459cdfe27fd9d0a01 000000000000000059cdfe27fd9d0a01 000000000000000059cdfe27fd9d0a01 fpscr=00000000
+vcvtm.u32.f32 d15, d15 40663cc0cbaa70de1ecff64fadef3e85 8f61acc9adf12d99372af8c483dfba08 0000000000000000372af8c483dfba08 0000000000000000372af8c483dfba08 fpscr=00000000
+vcvtm.u32.f32 d15, d15 a2df37c34663a656496221e5aecd0acb 85bf5956c4eb89f243a77b89705eda91 000000000000000043a77b89705eda91 000000000000000043a77b89705eda91 fpscr=00000000
+vcvtm.u32.f32 d15, d15 50ab89e5f6cc948c8f6321d09db7a45a 9b5f72e8e8125fa1cb2fc1e4552b3e84 0000000000000000cb2fc1e4552b3e84 0000000000000000cb2fc1e4552b3e84 fpscr=00000000
+vcvtm.u32.f32 d15, d15 5cd568d4e2cb8ddebbe1ff6ffac68b8d 4303bdfce8247c0233ce6632030fb37d 000000830000000033ce6632030fb37d 000000830000000033ce6632030fb37d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtm.u32.f32 d15, d15 69bf9e6a19a016bef3997d85d07e58cb 24f734d6d95f5c5f92df8dc0c6d2cce9 000000000000000092df8dc0c6d2cce9 000000000000000092df8dc0c6d2cce9 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtm.u32.f32 d15, d15 020000f3a6871e46a6871e466e4d6275 d1739629dce24c256a6e10aca21f68a5 00000000000000006a6e10aca21f68a5 00000000000000006a6e10aca21f68a5 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtm.u32.f32 d15, d15 2540ac7fba40a741373b49920ea7f8ed 2949485a0c759c7b9e36832419971f82 00000000000000009e36832419971f82 00000000000000009e36832419971f82 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtm.u32.f32 d15, d15 219254c0219254c055819aa491ea5603 c3330556af7ed402d5f7deafdc8620c8 0000000000000000d5f7deafdc8620c8 0000000000000000d5f7deafdc8620c8 fpscr=00000000
+vcvtm.u32.f32 d15, d15 8583f2806059fc348353adf37ed68061 029f63797af4e10caab55b1b6ca3d9be 00000000ffffffffaab55b1b6ca3d9be 00000000ffffffffaab55b1b6ca3d9be fpscr=00000000
+vcvtm.u32.f32 d15, d15 2b9966be5424d760f6b995600539c34a 9728593f612c2b20894daeb747b78d8c 00000000ffffffff894daeb747b78d8c 00000000ffffffff894daeb747b78d8c fpscr=00000000
+vcvtm.u32.f32 d15, d15 64c934de707d888fd16358600e91cc74 143eae99ef570d828ee0e91b5020cb39 00000000000000008ee0e91b5020cb39 00000000000000008ee0e91b5020cb39 fpscr=00000000
+vcvtm.u32.f32 d15, d15 4b9870e59c6ff47752e50575dda055df 6cdc9990bb4466d2eb1b1d58e99bfd4a ffffffff00000000eb1b1d58e99bfd4a ffffffff00000000eb1b1d58e99bfd4a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.u32.f32 d15, d15 3cc78d83af763da63edfac7cb131bbd0 3c2c40bb1e29e2a63c2c40bbe954ea9f 00000000000000003c2c40bbe954ea9f 00000000000000003c2c40bbe954ea9f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.u32.f32 d15, d15 344ce2d339a6a5a8c3af2cc580882c7a 669b3f4353c2475a990940887369f5d7 ffffffffffffffff990940887369f5d7 ffffffffffffffff990940887369f5d7 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtm.u32.f32 d15, d15 b8114fcb2c365453b5ce1eddec9ea5dc a054aff7a054aff7610bd0a76335d126 0000000000000000610bd0a76335d126 0000000000000000610bd0a76335d126 fpscr=00000000
+vcvtm.u32.f32 d15, d15 1b1d7f5ec315e3c07a890693dd13e566 8dd0565419dc28f02b810816260456ca 00000000000000002b810816260456ca 00000000000000002b810816260456ca fpscr=00000000
+vcvtm.u32.f32 d15, d15 fdeb3c627c39074346c53618e5cc51cb 4e0e6b007c324d9adef06c4c4924100d 239ac000ffffffffdef06c4c4924100d 239ac000ffffffffdef06c4c4924100d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.u32.f32 d15, d15 3fb6ed8ba9ffc2e128962d5f105a0ff9 b3025708d21c526928b9be9652a24cc6 000000000000000028b9be9652a24cc6 000000000000000028b9be9652a24cc6 fpscr=00000000
+vcvtm.u32.f32 d15, d15 a75553a8c0e632da166a6673ba068216 891e69c40d6625d2bd93e19652de71c4 0000000000000000bd93e19652de71c4 0000000000000000bd93e19652de71c4 fpscr=00000000
+vcvtm.u32.f32 d15, d15 be37b48f2ec7626099265e5be83c9627 bf5a8cccdff1c1c26ff6d0b3b9df5bd9 00000000000000006ff6d0b3b9df5bd9 00000000000000006ff6d0b3b9df5bd9 fpscr=00000000
+vcvtm.u32.f32 d15, d15 4c1f4718695ae8ae89882f54b287221b f8d498d63757411888b1e1d6c55e9504 000000000000000088b1e1d6c55e9504 000000000000000088b1e1d6c55e9504 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.u32.f32 d15, d15 fc5126f23b0e3f9f40bac0c61b781b64 1f182be138727da81f182be162bfa760 00000000000000001f182be162bfa760 00000000000000001f182be162bfa760 fpscr=00000000
+vcvtm.u32.f32 d15, d15 864e7af5c1cc33e778f00b0922bda236 f5fbca6bd13839fb572de609e5bd57fc 0000000000000000572de609e5bd57fc 0000000000000000572de609e5bd57fc fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtm.u32.f32 d15, d15 73bf631e672c42a9583d60365a041cee 4eaf926d61b228a56af3a3a62f9be2fa 57c93680ffffffff6af3a3a62f9be2fa 57c93680ffffffff6af3a3a62f9be2fa fpscr=00000000
+vcvtm.u32.f32 d15, d15 4098d00ca4be2c36aee6e4dc78a48522 06e741de14c398e0c18f9ade8f65c29d 0000000000000000c18f9ade8f65c29d 0000000000000000c18f9ade8f65c29d fpscr=00000000
+vcvtm.u32.f32 d15, d15 0bb996d929712f4468ee489d3c635e3e d7075c65fd63526eb21c7ccb978d7fde 0000000000000000b21c7ccb978d7fde 0000000000000000b21c7ccb978d7fde fpscr=00000000
+vcvtm.u32.f32 d15, d15 c7f212fbf62e3d66c29c156aa42225d5 c4a1acd0e8f2bc8f9826ab5d7606dbd0 00000000000000009826ab5d7606dbd0 00000000000000009826ab5d7606dbd0 fpscr=00000000
+vcvtm.u32.f32 d15, d15 e19550bb9bd1dbc08603f2bf6af7e45d caf5ae4017bc6285da9bf31fb7912e0e 0000000000000000da9bf31fb7912e0e 0000000000000000da9bf31fb7912e0e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtm.u32.f32 d15, d15 04badef00e8aaac96bfd980f1b1615c3 cc9516b016061d886a6a5c078f61e175 00000000000000006a6a5c078f61e175 00000000000000006a6a5c078f61e175 fpscr=00000000
+vcvtm.u32.f32 d15, d15 2920f278839c37c7e00861df1e629d0b 150faa33b357ec032f15d5713d622d0f 00000000000000002f15d5713d622d0f 00000000000000002f15d5713d622d0f fpscr=00000000
+vcvtm.u32.f32 d15, d15 1e2de4750a04eebf67577d596a1989e2 11eefeb7172aee2066c2b69397abbbb4 000000000000000066c2b69397abbbb4 000000000000000066c2b69397abbbb4 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[3]
+vcvtm.u32.f32 d15, d15 da90ec17a5d712e9c7ac835b1b517faa 8774169807934a2dfd19cedf87741698 0000000000000000fd19cedf87741698 0000000000000000fd19cedf87741698 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[0]
+vcvtm.u32.f32 d15, d15 5af89326bdab4f75bdab4f7581b7fa56 f678d46658e556fbbb4e78c65f8d9d1e 00000000ffffffffbb4e78c65f8d9d1e 00000000ffffffffbb4e78c65f8d9d1e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtm.u32.f32 d15, d15 380eb2f9f93050780a9d2569380eb2f9 94e1d2b06d75bf7b4cb968ebc91cb102 00000000ffffffff4cb968ebc91cb102 00000000ffffffff4cb968ebc91cb102 fpscr=00000000
+vcvtm.u32.f32 d15, d15 2d84871a1bfecc49fea131d3b20aedfe 7e34812bca3d6a3281e4023972039c64 ffffffff0000000081e4023972039c64 ffffffff0000000081e4023972039c64 fpscr=00000000
+vcvtm.u32.f32 d15, d15 55efc3e8793154452edfea8988b714e6 977c9aac5ab9dbfd93dfce75b2090b5b 00000000ffffffff93dfce75b2090b5b 00000000ffffffff93dfce75b2090b5b fpscr=00000000
+vcvtm.u32.f32 d15, d15 c43bc03491c3e7d1e01849cc6e13712f 06474af644cc3566fed2c8ae4fa55f5a 0000000000000661fed2c8ae4fa55f5a 0000000000000661fed2c8ae4fa55f5a fpscr=00000000
+vcvtn.u32.f32 q15, q0 707cc1ebf7f149909577b2cc419a450e d39c42ee7823799c51de88fdcd5da820 00000000ffffffffffffffff00000000 d39c42ee7823799c51de88fdcd5da820 fpscr=00000000
+vcvtn.u32.f32 q15, q0 3bda322220858ab4818dd713426c0238 b76420d922c08dd240cde5fd1d90f452 00000000000000000000000600000000 b76420d922c08dd240cde5fd1d90f452 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtn.u32.f32 q15, q0 c3d8446595db951b95db951b4170481e c97c54bc3580816da87e1ca1fd30bc26 00000000000000000000000000000000 c97c54bc3580816da87e1ca1fd30bc26 fpscr=00000000
+randV128: 15616 calls, 16146 iters
+vcvtn.u32.f32 q15, q0 e84e0efa73745794b5ef70b4b442afdd adebce23aa271e040f73ac019a3a221f 00000000000000000000000000000000 adebce23aa271e040f73ac019a3a221f fpscr=00000000
+vcvtn.u32.f32 q15, q0 ee931acadb56656248be2c898423871d 6b9cbb85056e61a140e65f84f9fc99ff ffffffff000000000000000700000000 6b9cbb85056e61a140e65f84f9fc99ff fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtn.u32.f32 q15, q0 fba7493e7acf72e7e6330b8959482216 131189af131189af7a44e3e5ed98781d 0000000000000000ffffffff00000000 131189af131189af7a44e3e5ed98781d fpscr=00000000
+vcvtn.u32.f32 q15, q0 d1111fc7af7d5037bdafbe3707a8ec45 4774db1d78622b6fe10ddd898bd9be95 0000f4dbffffffff0000000000000000 4774db1d78622b6fe10ddd898bd9be95 fpscr=00000000
+vcvtn.u32.f32 q15, q0 76f2a134b6f1cf670cc778fc77026b2a a99679213d6a4586a079f7a65a13965e 000000000000000000000000ffffffff a99679213d6a4586a079f7a65a13965e fpscr=00000000
+vcvtn.u32.f32 q15, q0 8a292eea2e12c1fef2ef646da7b42ec5 ad31d5fe3974d00d959e05d5cdb86b1e 00000000000000000000000000000000 ad31d5fe3974d00d959e05d5cdb86b1e fpscr=00000000
+vcvtn.u32.f32 q15, q0 7d6836bfd3785755620056d2b3ace79f cfcf7de60f3dfdf54a65ec462f70fd6b 000000000000000000397b1200000000 cfcf7de60f3dfdf54a65ec462f70fd6b fpscr=00000000
+vcvtn.u32.f32 q15, q0 3e0ba7b12ace4e6a4d613b69719bbf91 4de1670da7b598e5ee9238ffbacaac2b 1c2ce1a0000000000000000000000000 4de1670da7b598e5ee9238ffbacaac2b fpscr=00000000
+vcvtn.u32.f32 q15, q0 02f21da96b11e9291f7cc73b58c53a04 6a3481ac8f13b5e8da7af41d2c91667a ffffffff000000000000000000000000 6a3481ac8f13b5e8da7af41d2c91667a fpscr=00000000
+vcvtn.u32.f32 q15, q0 9967c93a6e9d7b4854ed9224bb540012 86cb1c6a354c3f6ce91b52814a7f71ed 000000000000000000000000003fdc7b 86cb1c6a354c3f6ce91b52814a7f71ed fpscr=00000000
+vcvtn.u32.f32 q15, q0 23eeb6410a1a490a6d8ca5a95b800184 1f103e200ae667afb88f3bd13e591d39 00000000000000000000000000000000 1f103e200ae667afb88f3bd13e591d39 fpscr=00000000
+vcvtn.u32.f32 q15, q0 2bf86f5dc74dd7d845615dba5fa0fbad b16ecdfe7933f07ec4e2beddd35d5339 00000000ffffffff0000000000000000 b16ecdfe7933f07ec4e2beddd35d5339 fpscr=00000000
+vcvtn.u32.f32 q15, q0 16690655f3c184c1ca6db04da91a6229 6f459e13cbe35d61664c5b6c931fff57 ffffffff00000000ffffffff00000000 6f459e13cbe35d61664c5b6c931fff57 fpscr=00000000
+vcvtn.u32.f32 q15, q0 fe0b7a501b5b98d8105ad6e08c2da280 e63e6233e3fb021cb7c4345ac7be5e4b 00000000000000000000000000000000 e63e6233e3fb021cb7c4345ac7be5e4b fpscr=00000000
+vcvtn.u32.f32 q15, q0 e6db7af4dec1a872cb0a4ed4e3a1c89b 7908753cda2eee9a46f51c225574324a ffffffff0000000000007a8effffffff 7908753cda2eee9a46f51c225574324a fpscr=00000000
+vcvtn.u32.f32 q15, q0 5037906526b05a45200340ad8756882a bd658ebc828dbc2ebc977ec47993ca84 000000000000000000000000ffffffff bd658ebc828dbc2ebc977ec47993ca84 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtn.u32.f32 q15, q0 34eda326ba238d62ddbe4a2c23b0a2df bba848f9bea23e3e572133096bd9f010 0000000000000000ffffffffffffffff bba848f9bea23e3e572133096bd9f010 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[3]
+vcvtn.u32.f32 q15, q0 24bb2dc95525decf3865de1911d6a053 8d8278b20a849554c5e4104349e32e2d 000000000000000000000000001c65c6 8d8278b20a849554c5e4104349e32e2d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtn.u32.f32 q15, q0 34f67b0534f67b05ebe4f735f8b46afd 456c3c8bb32b72ee8aa330a8cf47090f 00000ec4000000000000000000000000 456c3c8bb32b72ee8aa330a8cf47090f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtn.u32.f32 q15, q0 c74a8868299b0da3a28b32b49e700877 1f9ce4b02d233c0f94d6fca38dbdb5a5 00000000000000000000000000000000 1f9ce4b02d233c0f94d6fca38dbdb5a5 fpscr=00000000
+vcvtn.u32.f32 q15, q0 fcc18ffd34334687cf9ccb53300e319f ab15669a34e54b1d90fb0f17a6f28bff 00000000000000000000000000000000 ab15669a34e54b1d90fb0f17a6f28bff fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[1]
+vcvtn.u32.f32 q15, q0 808c6167729760e4729760e498490bf5 3b6c3b3aab1c4056cf46ce9acf46ce9a 00000000000000000000000000000000 3b6c3b3aab1c4056cf46ce9acf46ce9a fpscr=00000000
+vcvtn.u32.f32 q15, q0 55e7f96eda2362de98f7dafec5f77f0e ddf2d8f55b50f13cef61674e782b9485 00000000ffffffff00000000ffffffff ddf2d8f55b50f13cef61674e782b9485 fpscr=00000000
+vcvtn.u32.f32 q15, q0 751636eaf81715603016786c1c2c4b00 87727daac5194da9eace8fdb7d6a4730 000000000000000000000000ffffffff 87727daac5194da9eace8fdb7d6a4730 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtn.u32.f32 q15, q0 36a8a25314b4382c625d242a9e79041b bd643a301e21e904b17f2f09e95d7527 00000000000000000000000000000000 bd643a301e21e904b17f2f09e95d7527 fpscr=00000000
+vcvtn.u32.f32 q15, q0 f4b7dd0402a3a5ec84b6e8ce6cbc7219 526ffe4b039dd2276e2010fdaac70305 ffffffff00000000ffffffff00000000 526ffe4b039dd2276e2010fdaac70305 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.u32.f32 q15, q0 d51a89bf4cb42f9bd51a89bfb63cd0c5 7c134ae2a182f67ed475466cc323f9e4 ffffffff000000000000000000000000 7c134ae2a182f67ed475466cc323f9e4 fpscr=00000000
+vcvtn.u32.f32 q15, q0 30917d04fa88bca80c57ec2def40309a af8e68f1fa20792e37876be33c7eb535 00000000000000000000000000000000 af8e68f1fa20792e37876be33c7eb535 fpscr=00000000
+vcvtn.u32.f32 q15, q0 6bac8765a2fbd026a2cc5ea64e190d89 ff1c32f99f3dd55e2aaebc3f18ce7e80 00000000000000000000000000000000 ff1c32f99f3dd55e2aaebc3f18ce7e80 fpscr=00000000
+vcvtn.u32.f32 q15, q0 378d33401c8a42065a96be03f2ecae78 7e4ca8c0d41189a9686a8bde6d9b72f5 ffffffff00000000ffffffffffffffff 7e4ca8c0d41189a9686a8bde6d9b72f5 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtn.u32.f32 q15, q0 c8fb3041a1fbde9b71b0460838c228fb 4eb02903e37a5cf30862bf9a68f4eb51 581481800000000000000000ffffffff 4eb02903e37a5cf30862bf9a68f4eb51 fpscr=00000000
+vcvtn.u32.f32 q15, q0 ef35ac02bd5497a915b7cf48ee255f5d b2eec08e61f747e68138d2f78cc2e575 00000000ffffffff0000000000000000 b2eec08e61f747e68138d2f78cc2e575 fpscr=00000000
+vcvtn.u32.f32 q15, q0 04a3250b974abf93a32690636207b41b 1f121a6da2f0fc3c980702b63e77a528 00000000000000000000000000000000 1f121a6da2f0fc3c980702b63e77a528 fpscr=00000000
+vcvtn.u32.f32 q15, q0 4f05752b20f6e59a3c5fb27d87c21baf fa7f6505796742bc67a7cfc3ff4e9f91 00000000ffffffffffffffff00000000 fa7f6505796742bc67a7cfc3ff4e9f91 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[1]
+vcvtn.u32.f32 q15, q0 4483d77a0fae77710fae777163f19a02 54ba3dd66744087b99abbad0ac7e5aa0 ffffffffffffffff0000000000000000 54ba3dd66744087b99abbad0ac7e5aa0 fpscr=00000000
+vcvtn.u32.f32 q15, q0 f0bcebf3ef6345b9ce368ea9735092e3 76e448321b45e06b57fa88b8b3f1014a ffffffff00000000ffffffff00000000 76e448321b45e06b57fa88b8b3f1014a fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtn.u32.f32 q15, q0 2110c57ae5b63d2b8d1d0bc482f75ffa 86178159d35540ad064d3005d81ef05e 00000000000000000000000000000000 86178159d35540ad064d3005d81ef05e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtn.u32.f32 q15, q0 e5a3a37d95b86ba77c3d0f7bd5e1d8c3 d5dc425c7cb910df2dfeb4d23985e75c 00000000ffffffff0000000000000000 d5dc425c7cb910df2dfeb4d23985e75c fpscr=00000000
+vcvtn.u32.f32 q15, q0 bc151b9fd19c6d97e810bed330a6cd6d a471a52d9b53c0ccda38b4ed6d79f9d5 000000000000000000000000ffffffff a471a52d9b53c0ccda38b4ed6d79f9d5 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtn.u32.f32 q15, q0 46c5408673b2ce0e0c77fc934d893829 409e525d3c6136163c613616740d098a 000000050000000000000000ffffffff 409e525d3c6136163c613616740d098a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtn.u32.f32 q15, q0 ecef3a5cf11fa5709e3655f1fe146d97 a6b379041739f3196997f156a195f9d9 0000000000000000ffffffff00000000 a6b379041739f3196997f156a195f9d9 fpscr=00000000
+vcvtn.u32.f32 q15, q0 afc5099fb9abdb2a1f8d8134f6dc50ec a6ef0fc3fd81ab733446059f57c068a0 000000000000000000000000ffffffff a6ef0fc3fd81ab733446059f57c068a0 fpscr=00000000
+vcvtn.u32.f32 q15, q0 86b90fc99ed4129145afed161fe924ad cd4e5358a06053a31591ed00a6e75341 00000000000000000000000000000000 cd4e5358a06053a31591ed00a6e75341 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.u32.f32 q15, q0 f9c9f1746e6c6f2f5466ebec1f6b1e2a 57a74efd7eead626767e6b6c12407e99 ffffffffffffffffffffffff00000000 57a74efd7eead626767e6b6c12407e99 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtn.u32.f32 q15, q0 ff556dbc1ed85bc88e095ae29e399e54 7c4a68a9b5cff3395639c001737c8828 ffffffff00000000ffffffffffffffff 7c4a68a9b5cff3395639c001737c8828 fpscr=00000000
+vcvtn.u32.f32 q15, q0 738b3a343f983c3dfa0a6f58efaffa77 defae1d4cb5e49b46998dce535f41e7b 0000000000000000ffffffff00000000 defae1d4cb5e49b46998dce535f41e7b fpscr=00000000
+vcvtn.u32.f32 q15, q0 b706a379207d40dca36d032bc5c56c47 47629fe74621c11f5191e2e0863ecb60 0000e2a000002870ffffffff00000000 47629fe74621c11f5191e2e0863ecb60 fpscr=00000000
+vcvta.u32.f32 q14, q1 7bdf1f31636f91afe8aa6ee03597347e 8bc6af5351630fa978da334acae8a8af 00000000ffffffffffffffff00000000 8bc6af5351630fa978da334acae8a8af fpscr=00000000
+vcvta.u32.f32 q14, q1 44faff9a2f7a01aad9b824f7aa70a49f 02bc950d2a620391bb263749d3079835 00000000000000000000000000000000 02bc950d2a620391bb263749d3079835 fpscr=00000000
+vcvta.u32.f32 q14, q1 864ebf178538b15039fbe74bf7423eb0 b5bfbe6d4eb1561b1fce958ce48978a7 0000000058ab0d800000000000000000 b5bfbe6d4eb1561b1fce958ce48978a7 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvta.u32.f32 q14, q1 6d31a38538b8caaa8bc3a5a47bc3b172 977b4b494ca90bca46643aa2c8e8c522 0000000005485e500000390f00000000 977b4b494ca90bca46643aa2c8e8c522 fpscr=00000000
+vcvta.u32.f32 q14, q1 c4381afe34f6feb33985451dc24048b3 4b78fc2db1387106cfeaefc21ce6537e 00f8fc2d000000000000000000000000 4b78fc2db1387106cfeaefc21ce6537e fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.u32.f32 q14, q1 113126c5d2241b7d308edc243857fffd cb7ec673497c08c0b579a1826a94497b 00000000000fc08c00000000ffffffff cb7ec673497c08c0b579a1826a94497b fpscr=00000000
+vcvta.u32.f32 q14, q1 6c1586526eaabe9f3100fc6309c24219 41db13d73512cfc38b7794749d59f727 0000001b000000000000000000000000 41db13d73512cfc38b7794749d59f727 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[2]
+vcvta.u32.f32 q14, q1 e49d99e99e4886c3d254ee43d254ee43 4783458ff40bda4a1ed38e10fb6e574e 0001068b000000000000000000000000 4783458ff40bda4a1ed38e10fb6e574e fpscr=00000000
+vcvta.u32.f32 q14, q1 59677d7d91d185b6d547c3818437207c d7873cd03e5e749508676ee4c924fcbe 00000000000000000000000000000000 d7873cd03e5e749508676ee4c924fcbe fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[0]
+vcvta.u32.f32 q14, q1 881de94f524f48da153ec7f4153ec7f4 4260d871f5b122efeba3bef6670c76c0 000000380000000000000000ffffffff 4260d871f5b122efeba3bef6670c76c0 fpscr=00000000
+vcvta.u32.f32 q14, q1 80c7f5093a612dbe3fc4912879a70ba0 bb9ea8cca50121bbf02b1cce073b84ec 00000000000000000000000000000000 bb9ea8cca50121bbf02b1cce073b84ec fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvta.u32.f32 q14, q1 0c960c041a1fbb4c0e28a651705dad4c a62b1692c8e4339ba62b169217d23554 00000000000000000000000000000000 a62b1692c8e4339ba62b169217d23554 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvta.u32.f32 q14, q1 743fcdaa5b0cb1bc614e55d2ba69db0a 447554fcb01e165eed05a2b6447554fc 000003d50000000000000000000003d5 447554fcb01e165eed05a2b6447554fc fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvta.u32.f32 q14, q1 ebc92aa3e40a0bc6927fbdfb4e09a500 038ab241b049323f4e2f4eb194c98a9c 00000000000000002bd3ac4000000000 038ab241b049323f4e2f4eb194c98a9c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvta.u32.f32 q14, q1 08547b0a39ead7b444746feba5411766 1ce12e17882697f6902f7f02e60a81bb 00000000000000000000000000000000 1ce12e17882697f6902f7f02e60a81bb fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvta.u32.f32 q14, q1 0a735b3c900ef47d6748c9a7e15eda8a c06ad6ff23367565fa817f56632cb1cf 000000000000000000000000ffffffff c06ad6ff23367565fa817f56632cb1cf fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvta.u32.f32 q14, q1 d21d6e0ae175baa063d9c53ed21d6e0a e04d7a0d5b4fc5dcdbd6bf73ec536128 00000000ffffffff0000000000000000 e04d7a0d5b4fc5dcdbd6bf73ec536128 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: 15872 calls, 16413 iters
+vcvta.u32.f32 q14, q1 231f7bcc159c8074c76979ff159c8074 6c226bc4d66fd5e78930b8427df98a55 ffffffff0000000000000000ffffffff 6c226bc4d66fd5e78930b8427df98a55 fpscr=00000000
+vcvta.u32.f32 q14, q1 6f3dbf6c430fcc9a2a6fd91759bddf2e c67a058b06ce521fed5d08a6518a5e06 000000000000000000000000ffffffff c67a058b06ce521fed5d08a6518a5e06 fpscr=00000000
+vcvta.u32.f32 q14, q1 13b4daedb0c6b0c807c2446456874fbd c24d541809331ec93abd83b3873dc11f 00000000000000000000000000000000 c24d541809331ec93abd83b3873dc11f fpscr=00000000
+vcvta.u32.f32 q14, q1 ed6b40ab35ad90c9b4841c56191d3302 86fd73b3bda4213e7447645cd811d216 0000000000000000ffffffff00000000 86fd73b3bda4213e7447645cd811d216 fpscr=00000000
+vcvta.u32.f32 q14, q1 2a20a73ecce6698d502988f5dc5765f7 b356577845a73e855d0de9fee617b7a3 00000000000014e8ffffffff00000000 b356577845a73e855d0de9fee617b7a3 fpscr=00000000
+vcvta.u32.f32 q14, q1 02f7fed1694dc71b3b12fabdc5082250 164dd411124d07120978b19884e78bb8 00000000000000000000000000000000 164dd411124d07120978b19884e78bb8 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvta.u32.f32 q14, q1 2d39d5246903ceed2d39d52499cf541b da9a414e899d9e31cf45b3e2eef3b0d1 00000000000000000000000000000000 da9a414e899d9e31cf45b3e2eef3b0d1 fpscr=00000000
+vcvta.u32.f32 q14, q1 7a1b1112fee270e19b2eabbd72f2d6c3 da6b0ef9b4f408c6935185896e257674 000000000000000000000000ffffffff da6b0ef9b4f408c6935185896e257674 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvta.u32.f32 q14, q1 113b63df082a99c012dade5485802803 f1d8fa34d7519911cf872de79078acb4 00000000000000000000000000000000 f1d8fa34d7519911cf872de79078acb4 fpscr=00000000
+vcvta.u32.f32 q14, q1 126072f3131d6ae10faafbbcc796e6d8 8086e1b664a64f531cbf23f560690bb2 00000000ffffffff00000000ffffffff 8086e1b664a64f531cbf23f560690bb2 fpscr=00000000
+vcvta.u32.f32 q14, q1 6047d60fa7e39d3a05eb9049d92cb5b3 ba9a1f0faa83bc651e9bea7238809eb8 00000000000000000000000000000000 ba9a1f0faa83bc651e9bea7238809eb8 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.u32.f32 q14, q1 d527f9215665528e04f85c61eadee154 7b3100432acf50880b62a1ff701ca196 ffffffff0000000000000000ffffffff 7b3100432acf50880b62a1ff701ca196 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvta.u32.f32 q14, q1 8371e33989551edd20a019dbac4386ea 31fce6cde95cca911ce800712ffc3991 00000000000000000000000000000000 31fce6cde95cca911ce800712ffc3991 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvta.u32.f32 q14, q1 35a780bc8bee450c725b41e76a27c1e7 8e158f0d15507e769efd53868e158f0d 00000000000000000000000000000000 8e158f0d15507e769efd53868e158f0d fpscr=00000000
+vcvta.u32.f32 q14, q1 1c94d96fff63701a8dda4995d9087a8f 8c3a819c634fa30e18ff9cf9a648486b 00000000ffffffff0000000000000000 8c3a819c634fa30e18ff9cf9a648486b fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvta.u32.f32 q14, q1 efc135852d6c066b9dfdf1186d32cf63 0b85c59fc6e1c76833a3fe3958acde6d 000000000000000000000000ffffffff 0b85c59fc6e1c76833a3fe3958acde6d fpscr=00000000
+vcvta.u32.f32 q14, q1 d8153bffdec80b949c2c5a3ca6e0a0fa c8cf1899de0110897956bb86d2a74098 0000000000000000ffffffff00000000 c8cf1899de0110897956bb86d2a74098 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[3]
+vcvta.u32.f32 q14, q1 6c4d0e77d04af46c2fe8bacd2fe8bacd a114a29655c8634e8a3a030b1443824d 00000000ffffffff0000000000000000 a114a29655c8634e8a3a030b1443824d fpscr=00000000
+vcvta.u32.f32 q14, q1 0578e2ba26fac3561da40c52c259bf6c bce4799a685fa4ea8e6d0e816f4f1f27 00000000ffffffff00000000ffffffff bce4799a685fa4ea8e6d0e816f4f1f27 fpscr=00000000
+vcvta.u32.f32 q14, q1 107908ae50288571871d2b872a49b8f9 fb5e1941ca85282f83653f4ec8851c8c 00000000000000000000000000000000 fb5e1941ca85282f83653f4ec8851c8c fpscr=00000000
+vcvta.u32.f32 q14, q1 655850cbd3e2cd9937aa946e7eb4ea50 24adf5850619b95da59be2495c5906a2 000000000000000000000000ffffffff 24adf5850619b95da59be2495c5906a2 fpscr=00000000
+vcvta.u32.f32 q14, q1 9bd946ce6da22e3ef83bd5381bde7192 e84edafe17662578ac8e02552c858548 00000000000000000000000000000000 e84edafe17662578ac8e02552c858548 fpscr=00000000
+vcvta.u32.f32 q14, q1 a3f28dcd8c98985bfdda84b3e065816c 746c83f04a4127fc53807bfcce1dd288 ffffffff003049ffffffffff00000000 746c83f04a4127fc53807bfcce1dd288 fpscr=00000000
+vcvta.u32.f32 q14, q1 270a57c2560977238b23fa1876dfb50c 63ca52464c8b4773849bf8a0b85ad772 ffffffff045a3b980000000000000000 63ca52464c8b4773849bf8a0b85ad772 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvta.u32.f32 q14, q1 551939000b8a2190fdaa67b8f95acce7 8a01f4e7141c976e6876ce1374bb2d4d 0000000000000000ffffffffffffffff 8a01f4e7141c976e6876ce1374bb2d4d fpscr=00000000
+vcvta.u32.f32 q14, q1 30fb01a5607ccf21b1d22a31478bf9b4 488aa82ed869b60350da5700bc8aa98e 0004554100000000ffffffff00000000 488aa82ed869b60350da5700bc8aa98e fpscr=00000000
+vcvta.u32.f32 q14, q1 f8f032a02bf8ce423b9b2bce3b9fe3e1 825cf2f2952b0f3451b5a2be8af70ed6 0000000000000000ffffffff00000000 825cf2f2952b0f3451b5a2be8af70ed6 fpscr=00000000
+vcvta.u32.f32 q14, q1 9e17ff251a1bc2ac634d82e23e63c602 541c82db21ca51857d21447885c03090 ffffffff00000000ffffffff00000000 541c82db21ca51857d21447885c03090 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.u32.f32 q14, q1 ea3edb182e53da29500a9ffa38d87b66 c4dda62af4f5761af9e36d3cdecd285a 00000000000000000000000000000000 c4dda62af4f5761af9e36d3cdecd285a fpscr=00000000
+vcvta.u32.f32 q14, q1 77998e9b3ba194adff2b07a2c88ef99f fd5b54310bf802a6882b4a30f5c3e808 00000000000000000000000000000000 fd5b54310bf802a6882b4a30f5c3e808 fpscr=00000000
+vcvta.u32.f32 q14, q1 b611c220cdbb9bb4d32553e6a33c362c 10f1ab66a61ccaa40a2e8a2534e3ecff 00000000000000000000000000000000 10f1ab66a61ccaa40a2e8a2534e3ecff fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.u32.f32 q14, q1 b970a17df2373324f2373324636999fe 33aba2ddb8d1b67be2ffe2a5cbd19414 00000000000000000000000000000000 33aba2ddb8d1b67be2ffe2a5cbd19414 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.u32.f32 q14, q1 c91bb65e9de388fbbc699bf587eeb332 3e68dc10148cab0f89e97c2d28b6b280 00000000000000000000000000000000 3e68dc10148cab0f89e97c2d28b6b280 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.u32.f32 q13, q2 b5daa5ff7d267d8eb2e89fc127d00f34 a8c57b7b4129326d4129326d9a8a9480 000000000000000b0000000b00000000 a8c57b7b4129326d4129326d9a8a9480 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.u32.f32 q13, q2 7479d35bb65cd6065c92033a93f52308 4d46e8e4e6d9b746e6d9b74621a63b8c 0c6e8e40000000000000000000000001 4d46e8e4e6d9b746e6d9b74621a63b8c fpscr=00000000
+vcvtp.u32.f32 q13, q2 32f1f90af01c868fc7de100cade2b1c1 59a580639d81ee914022446d995e782d ffffffff000000000000000300000000 59a580639d81ee914022446d995e782d fpscr=00000000
+vcvtp.u32.f32 q13, q2 3e11d73d361afc8fb67202bdc7feee16 03b5ac3cd6ee1b7ab36e919f6704c673 000000010000000000000000ffffffff 03b5ac3cd6ee1b7ab36e919f6704c673 fpscr=00000000
+vcvtp.u32.f32 q13, q2 e8bd36d2ac9038aeb17d10aa3d3349e4 bacdae55b8f5f1211f46e679963418cf 00000000000000000000000100000000 bacdae55b8f5f1211f46e679963418cf fpscr=00000000
+vcvtp.u32.f32 q13, q2 346182a53109157a07d7ae1204f8943b 56e4b650b74e4a43f73b7475140dc3c0 ffffffff000000000000000000000001 56e4b650b74e4a43f73b7475140dc3c0 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtp.u32.f32 q13, q2 a490b047cd4d177c3c8a7153b0c49c4b 3d8599afbb723614dd2913849fe51697 00000001000000000000000000000000 3d8599afbb723614dd2913849fe51697 fpscr=00000000
+vcvtp.u32.f32 q13, q2 7a9256b7e7816a2ea8d45fbceea36b20 e9054070fc0017d64611c712b0730bc0 00000000000000000000247200000000 e9054070fc0017d64611c712b0730bc0 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[3]
+vcvtp.u32.f32 q13, q2 09af4b8e84afeb37c6b9c07d09af4b8e e000b24f5c86625b6a7ebe19f54f9cb2 00000000ffffffffffffffff00000000 e000b24f5c86625b6a7ebe19f54f9cb2 fpscr=00000000
+vcvtp.u32.f32 q13, q2 53a1263f997f54261c505ff2a0fed629 d87f71f45f74df98437b8a1e8386fcb2 00000000ffffffff000000fc00000000 d87f71f45f74df98437b8a1e8386fcb2 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.u32.f32 q13, q2 0d7d0bfbb46830df162845959964c1d0 09c7a31ea4cf4e709ee5e64c94a7d98b 00000001000000000000000000000000 09c7a31ea4cf4e709ee5e64c94a7d98b fpscr=00000000
+vcvtp.u32.f32 q13, q2 96a63ff3f0a311e39e88848d965ed40a 1ea6f73226b289e6c982fc06e200548e 00000001000000010000000000000000 1ea6f73226b289e6c982fc06e200548e fpscr=00000000
+vcvtp.u32.f32 q13, q2 84e2508456d921362db5728d4beaa370 97e5f204292642126b186c580b384303 0000000000000001ffffffff00000001 97e5f204292642126b186c580b384303 fpscr=00000000
+vcvtp.u32.f32 q13, q2 21d6a8acdba70bdc6c8d2f0522f10fdb 6ec97e7fac4584d9db35269593ee1300 ffffffff000000000000000000000000 6ec97e7fac4584d9db35269593ee1300 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtp.u32.f32 q13, q2 14ddbd641b17d3a3e7039f64b72447bd 2094d068878a9a97ef10457e96b1039b 00000001000000000000000000000000 2094d068878a9a97ef10457e96b1039b fpscr=00000000
+vcvtp.u32.f32 q13, q2 d4ba7b3a040a692a6f3b076565d08657 9b0dccb89d7acc68dd11b476da8ec127 00000000000000000000000000000000 9b0dccb89d7acc68dd11b476da8ec127 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.u32.f32 q13, q2 44816ad5baa6732aaf19cf5bf5afc521 a63b5bd456b3915e8be1d3056688566b 00000000ffffffff00000000ffffffff a63b5bd456b3915e8be1d3056688566b fpscr=00000000
+vcvtp.u32.f32 q13, q2 e39349caaccc4b4c988fba6512ba7934 6028964f00c80495ba8314f9f8c2574a ffffffff000000010000000000000000 6028964f00c80495ba8314f9f8c2574a fpscr=00000000
+vcvtp.u32.f32 q13, q2 1a7c5c5a616f15695c76f43d6c4cf4a3 c2e3064544af2f70cdd642b42bc1d4c2 000000000000057a0000000000000001 c2e3064544af2f70cdd642b42bc1d4c2 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtp.u32.f32 q13, q2 d6fa0f739a6274fb39c549a479b547d3 fab150b1fc49c34231099ab1ce4aedb4 00000000000000000000000100000000 fab150b1fc49c34231099ab1ce4aedb4 fpscr=00000000
+vcvtp.u32.f32 q13, q2 f262026477a5a2e6c00b246972ee4bf5 eda4f18b6b4cbcf6c5ced5b0795c8716 00000000ffffffff00000000ffffffff eda4f18b6b4cbcf6c5ced5b0795c8716 fpscr=00000000
+vcvtp.u32.f32 q13, q2 74a7b56813e9e008db6f05f8b40a96f0 71a88590787094ad611b144ab8e6aef8 ffffffffffffffffffffffff00000000 71a88590787094ad611b144ab8e6aef8 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtp.u32.f32 q13, q2 dbe6004d6af0c88bf3c4c238c115df91 de4cbe518c39e86a4eb423cbbba5618c 00000000000000005a11e58000000000 de4cbe518c39e86a4eb423cbbba5618c fpscr=00000000
+vcvtp.u32.f32 q13, q2 c7d9c8039d9a8bdda92c1ec22dff7452 da18493860fed57fa47d98bfec0fcf4f 00000000ffffffff0000000000000000 da18493860fed57fa47d98bfec0fcf4f fpscr=00000000
+vcvtp.u32.f32 q13, q2 5f5a22827f1c665b5e48d7f3d483707e 11daeb8ae97a1cb6d4b5c1054123f41b 0000000100000000000000000000000b 11daeb8ae97a1cb6d4b5c1054123f41b fpscr=00000000
+vcvtp.u32.f32 q13, q2 21012e573a4f0e13d4e35dc8adf49f89 425f697ddf42b2ae9c724bc7767305bf 000000380000000000000000ffffffff 425f697ddf42b2ae9c724bc7767305bf fpscr=00000000
+vcvtp.u32.f32 q13, q2 c68976dd8b3fb12d878e9b8352de374a 7b6fb78d01835fa008fac0a88553b388 ffffffff000000010000000100000000 7b6fb78d01835fa008fac0a88553b388 fpscr=00000000
+vcvtp.u32.f32 q13, q2 f4bb75dccd26ba2d51d6b02ab5f82a2b 6c1fc940131e50b3b19e070512620ba2 ffffffff000000010000000000000001 6c1fc940131e50b3b19e070512620ba2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtp.u32.f32 q13, q2 e9f6597e945df962c05a54f2e491e934 ac3cd2fecb2947c8ac3cd2fe17165bd4 00000000000000000000000000000001 ac3cd2fecb2947c8ac3cd2fe17165bd4 fpscr=00000000
+vcvtp.u32.f32 q13, q2 375b690e636d4e0a82b4f4538275356c 662f840bfdeeb5d02d4374acb04ea915 ffffffff000000000000000100000000 662f840bfdeeb5d02d4374acb04ea915 fpscr=00000000
+vcvtp.u32.f32 q13, q2 b06b871840de7880948e71a7fe3cf3fc 3273fb22f876ae5c1e61c486bbbfc886 00000001000000000000000100000000 3273fb22f876ae5c1e61c486bbbfc886 fpscr=00000000
+randV128: 16128 calls, 16676 iters
+vcvtp.u32.f32 q13, q2 e52599c6cf50749af7ff24124528322e 47eee4e8dcfc31b057e4ce01f64e2311 0001ddca00000000ffffffff00000000 47eee4e8dcfc31b057e4ce01f64e2311 fpscr=00000000
+vcvtp.u32.f32 q13, q2 9332523d97eec3318bbbba333d1f4b23 b93b930560ed3d0c291bc3d0e35944da 00000000ffffffff0000000100000000 b93b930560ed3d0c291bc3d0e35944da fpscr=00000000
+vcvtp.u32.f32 q13, q2 b570c74d115229f0b480e508c4093a40 112c6db7fd229ea552d0badf7aae1261 0000000100000000ffffffffffffffff 112c6db7fd229ea552d0badf7aae1261 fpscr=00000000
+vcvtp.u32.f32 q13, q2 967d4504d7b3a78ca8e376c41b3ddfab c65ded31028b8d28b01af1f27e75b842 000000000000000100000000ffffffff c65ded31028b8d28b01af1f27e75b842 fpscr=00000000
+vcvtp.u32.f32 q13, q2 bd9914a6b2645a59a16d5c023843191a 139d0ad50ec2bb15590a7b253303edcd 0000000100000001ffffffff00000001 139d0ad50ec2bb15590a7b253303edcd fpscr=00000000
+vcvtp.u32.f32 q13, q2 bef1170188bc3741e428815bf1fcc50f 2c3dfd58df73b5ff10343d447687978d 000000010000000000000001ffffffff 2c3dfd58df73b5ff10343d447687978d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtp.u32.f32 q13, q2 e3424127285eae19b6828a5f0b289a6a d54168bd91afaaa61c255a102f93d39c 00000000000000000000000100000001 d54168bd91afaaa61c255a102f93d39c fpscr=00000000
+vcvtp.u32.f32 q13, q2 eac8bfdeff7efddb2258249373ea264a 5d69556adc2f2c1694fb7daaf8592b91 ffffffff000000000000000000000000 5d69556adc2f2c1694fb7daaf8592b91 fpscr=00000000
+vcvtp.u32.f32 q13, q2 526a99146b3d97bd4b2bb7c20ed891f0 9c1ad127bcc8a0e9b7f9810366fd500e 000000000000000000000000ffffffff 9c1ad127bcc8a0e9b7f9810366fd500e fpscr=00000000
+vcvtp.u32.f32 q13, q2 a36abbf5713c1be874edfdd0611df058 d2d0ff62892516f38e66beec9ec433e6 00000000000000000000000000000000 d2d0ff62892516f38e66beec9ec433e6 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtp.u32.f32 q13, q2 72a3a07dcc2c906496fef837e539cf78 d1473b2c82eeaa5c0f6f64910f6f6491 00000000000000000000000100000001 d1473b2c82eeaa5c0f6f64910f6f6491 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtp.u32.f32 q13, q2 588ed61be309e2f50212e13011825af5 b5732c789bfce57667dc091d08df64dd 0000000000000000ffffffff00000001 b5732c789bfce57667dc091d08df64dd fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[1]
+vcvtp.u32.f32 q13, q2 1261443ecc6ba054c3672a4bbbbc3984 678093a91c1a47fffc20ed40d306472c ffffffff000000010000000000000000 678093a91c1a47fffc20ed40d306472c fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtp.u32.f32 q13, q2 9d8f5d5fa766c6da85daccafa766c6da 7b466df81a3d0024e5f679b938fad963 ffffffff000000010000000000000001 7b466df81a3d0024e5f679b938fad963 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.u32.f32 q13, q2 eeeb907578ab294f8862670d8513e03b 58cae80fb1097ad6f7e4c2f547103c0c ffffffff00000000000000000000903d 58cae80fb1097ad6f7e4c2f547103c0c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtp.u32.f32 q13, q2 cd0ac99d5b9872edc7f05b9ac7f05b9a 16f6a2b1dc0f863c8addf0b43bfc964f 00000001000000000000000000000001 16f6a2b1dc0f863c8addf0b43bfc964f fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtp.u32.f32 q13, q2 0c79335269b99865e6b7e7dd4860f8be 39da442cb683a845fa7329a039da442c 00000001000000000000000000000001 39da442cb683a845fa7329a039da442c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.u32.f32 q13, q2 c247e9d3ae6e252feb8fd5c8ae6e252f fa93a8c642e0519ae4c45a8f2edc0c1e 00000000000000710000000000000001 fa93a8c642e0519ae4c45a8f2edc0c1e fpscr=00000000
+vcvtp.u32.f32 q13, q2 60ad9c641a3b03e0ae567044a798d4cc b1eb97ee2dbddfe535cc6f00e5309a7c 00000000000000010000000100000000 b1eb97ee2dbddfe535cc6f00e5309a7c fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.u32.f32 q12, q3 6f6a1d6f6f6a1d6f1e6bc27473b98a18 55a60862be34d1bc167872959edbdb4f ffffffff000000000000000000000000 55a60862be34d1bc167872959edbdb4f fpscr=00000000
+vcvtm.u32.f32 q12, q3 0715ca15bf680b1b766569250435178a 0890d56ace987d101a1f22108b3eaa7a 00000000000000000000000000000000 0890d56ace987d101a1f22108b3eaa7a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.u32.f32 q12, q3 a1b2cd2fc9c49c5ed6aa3b1c42fdafbc 505b64ca110f7491d8532077b80d8348 ffffffff000000000000000000000000 505b64ca110f7491d8532077b80d8348 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtm.u32.f32 q12, q3 075336d0f87a5ed3c3d3ff6dc3d3ff6d f0e92c6d035f05a354b6af17f7804ecd 0000000000000000ffffffff00000000 f0e92c6d035f05a354b6af17f7804ecd fpscr=00000000
+vcvtm.u32.f32 q12, q3 d90214df58b42d1ea26ff23e70f3e166 bda97df0412810fd3e13828a8431367e 000000000000000a0000000000000000 bda97df0412810fd3e13828a8431367e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.u32.f32 q12, q3 e215621bc7600265e215621bf6dcc5e6 e53e843bf37374c3483669cc7835a289 00000000000000000002d9a7ffffffff e53e843bf37374c3483669cc7835a289 fpscr=00000000
+vcvtm.u32.f32 q12, q3 99483744740e1e6e8dd5f45c7cb8a948 160dd94f90418b6a2a8b0438af8e6fa9 00000000000000000000000000000000 160dd94f90418b6a2a8b0438af8e6fa9 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtm.u32.f32 q12, q3 9d8fbc0579bec9531b64349d68b6febb bf8165c9703cff81848076c7848076c7 00000000ffffffff0000000000000000 bf8165c9703cff81848076c7848076c7 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtm.u32.f32 q12, q3 1f21dc8fe29c48a6feb55bb637abe187 b4699247e0b0d4fc3e578752b4699247 00000000000000000000000000000000 b4699247e0b0d4fc3e578752b4699247 fpscr=00000000
+vcvtm.u32.f32 q12, q3 9f33d9f9e0df7d6e096eac741ca213bf 0fb27dc4870381762262516bab9b1478 00000000000000000000000000000000 0fb27dc4870381762262516bab9b1478 fpscr=00000000
+vcvtm.u32.f32 q12, q3 45224440115c088ccd06fb3bb0ea5e7f 6eb61115357447cfd1efa23a2acd9927 ffffffff000000000000000000000000 6eb61115357447cfd1efa23a2acd9927 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[3]
+vcvtm.u32.f32 q12, q3 e996443c59491c9807de4cafb9a9f869 2231f716c95c30cfef93a3082231f716 00000000000000000000000000000000 2231f716c95c30cfef93a3082231f716 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.u32.f32 q12, q3 cf34de4334ade839cf34de4333f00824 af92234fe957cf6804e258427e7e3ff0 000000000000000000000000ffffffff af92234fe957cf6804e258427e7e3ff0 fpscr=00000000
+vcvtm.u32.f32 q12, q3 b257084e4c232fbff018ea4a2325bcd3 abf87b88c729338a1ffa9984d2f876ac 00000000000000000000000000000000 abf87b88c729338a1ffa9984d2f876ac fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[2]
+vcvtm.u32.f32 q12, q3 a5bb5bd9cef0e635f1710b4df1710b4d 6c998ce9b34cd78b656a1b3ba952d5a4 ffffffff00000000ffffffff00000000 6c998ce9b34cd78b656a1b3ba952d5a4 fpscr=00000000
+vcvtm.u32.f32 q12, q3 9d74cbb4ee697fc58d108246c8862d02 e048e8d0ad44190e1d21b84d02585bba 00000000000000000000000000000000 e048e8d0ad44190e1d21b84d02585bba fpscr=00000000
+vcvtm.u32.f32 q12, q3 341ca45870e41949de50faf53e7f24ac 1497d436281e0570f2f38c231886a84a 00000000000000000000000000000000 1497d436281e0570f2f38c231886a84a fpscr=00000000
+vcvtm.u32.f32 q12, q3 a8bdc200be7d2a51c4cd05c600e9f439 40cf01990a98f376276e74e63a4d0971 00000006000000000000000000000000 40cf01990a98f376276e74e63a4d0971 fpscr=00000000
+vcvtm.u32.f32 q12, q3 31f0d6726756936fd7db2cc9798f6e8e 0b0ce06594b083032da068ea3e169213 00000000000000000000000000000000 0b0ce06594b083032da068ea3e169213 fpscr=00000000
+vcvtm.u32.f32 q12, q3 f7c1d54c81a13390a3d49e535f988a20 ded9a90374e23b33ec06c0e0de8f9472 00000000ffffffff0000000000000000 ded9a90374e23b33ec06c0e0de8f9472 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.u32.f32 q12, q3 177a189178f4cbfb177a1891a7b11a0e bca0aa625f4d0d538ea81b687be9fad9 00000000ffffffff00000000ffffffff bca0aa625f4d0d538ea81b687be9fad9 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtm.u32.f32 q12, q3 99d6e7491bf5a6a699d6e749968153b5 705ed2b134da2f0467da8150c68b2397 ffffffff00000000ffffffff00000000 705ed2b134da2f0467da8150c68b2397 fpscr=00000000
+vcvtm.u32.f32 q12, q3 e2d82f35a038026ccfd6baf3368dfb54 25f977a46ba4b817947fcbed6f9345a7 00000000ffffffff00000000ffffffff 25f977a46ba4b817947fcbed6f9345a7 fpscr=00000000
+vcvtm.u32.f32 q12, q3 1e7bbb5f3de4b252c107d2f2152b91c0 cf4bffd09351b3bb8aa8275ff72628f6 00000000000000000000000000000000 cf4bffd09351b3bb8aa8275ff72628f6 fpscr=00000000
+vcvtm.u32.f32 q12, q3 2f7542a1a6629c178f43ece932aca423 d11e58332ad956d39ff7fa231ad4a5c0 00000000000000000000000000000000 d11e58332ad956d39ff7fa231ad4a5c0 fpscr=00000000
+vcvtm.u32.f32 q12, q3 89119b07fb9331a98bdcaad637d63ed8 27f59f9406921daa139b771c2b4c2d39 00000000000000000000000000000000 27f59f9406921daa139b771c2b4c2d39 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtm.u32.f32 q12, q3 af2b5f0c2bc8467ce96024262bc8467c c6300ea7fb38bd97e0f32f8e977f49bd 00000000000000000000000000000000 c6300ea7fb38bd97e0f32f8e977f49bd fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtm.u32.f32 q12, q3 48bdcb0a3d97fe3f81d6f52e0b323da3 7b138b977b138b97f801c172077be7ad ffffffffffffffff0000000000000000 7b138b977b138b97f801c172077be7ad fpscr=00000000
+vcvtm.u32.f32 q12, q3 82b8fb0d3dbff1b94028cc7b256c9a66 b8a8ef8e3d0ff4baaf5bc9a75a43a70d 000000000000000000000000ffffffff b8a8ef8e3d0ff4baaf5bc9a75a43a70d fpscr=00000000
+vcvtm.u32.f32 q12, q3 454c07b66fc83bebab60bb7318dbe6c3 8a68bb97b05f565a7117ae4c1d9730fe 0000000000000000ffffffff00000000 8a68bb97b05f565a7117ae4c1d9730fe fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtm.u32.f32 q12, q3 2ae23103e047d05d17971de2d78bd980 b44f351178adbadf3e8914bf95160aa9 00000000ffffffff0000000000000000 b44f351178adbadf3e8914bf95160aa9 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtm.u32.f32 q12, q3 8777e4875e9a509b1cab63a4864ec307 2bc78eaf2bc78eafd6ec5627f4305c30 00000000000000000000000000000000 2bc78eaf2bc78eafd6ec5627f4305c30 fpscr=00000000
+vcvtm.u32.f32 q12, q3 0ce4245f78f0985e5be184baafb8a7da 7cb8000ef6c68b374146188e02e2557a ffffffff000000000000000c00000000 7cb8000ef6c68b374146188e02e2557a fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.u32.f32 q12, q3 0a6b325b5285957d65f1834c65f1834c 072a478abf671b1f08d1068bed8fcd6b 00000000000000000000000000000000 072a478abf671b1f08d1068bed8fcd6b fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtm.u32.f32 q12, q3 03fa9141738ce6b4eae2e9f75f8c57c2 f6c6094b7d166afdcbd2e6c27d166afd 00000000ffffffff00000000ffffffff f6c6094b7d166afdcbd2e6c27d166afd fpscr=00000000
+vcvtm.u32.f32 q12, q3 83652426816b722597aa72ce558f815c b3e8e382ab60eb07b3a423386e7bc2d5 000000000000000000000000ffffffff b3e8e382ab60eb07b3a423386e7bc2d5 fpscr=00000000
+vcvtm.u32.f32 q12, q3 e5034f7d407a75f67247bdb05fcb4f3a 7e280c130e1f9904271816dd55b7596f ffffffff0000000000000000ffffffff 7e280c130e1f9904271816dd55b7596f fpscr=00000000
+vcvtm.u32.f32 q12, q3 63809d9a18ee220ada545f1b3362c5fa 656e59855cb9d96e4d2cea581117d826 ffffffffffffffff0acea58000000000 656e59855cb9d96e4d2cea581117d826 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtm.u32.f32 q12, q3 3d8fc3fe87f7a082f7e42c433152c3f6 e5d101bac20b0be0546e09bac20b0be0 0000000000000000ffffffff00000000 e5d101bac20b0be0546e09bac20b0be0 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtm.u32.f32 q12, q3 d5f443e2f5ad6a9e94c6051f59cc6144 ca8eaa7095c8844b3cabcffa452ac525 00000000000000000000000000000aac ca8eaa7095c8844b3cabcffa452ac525 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtm.u32.f32 q12, q3 1968420fc00ea01d0e49ff1f7e627905 c823856863de5e3873933131c8238568 00000000ffffffffffffffff00000000 c823856863de5e3873933131c8238568 fpscr=00000000
+vcvtm.u32.f32 q12, q3 24123a3dd0764ad407921da5fba92ecc 46ed24e66100f6712b22c457cc2a3704 00007692ffffffff0000000000000000 46ed24e66100f6712b22c457cc2a3704 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtm.u32.f32 q12, q3 4457a1a881c171c3c5d16be75aaf1d1e fdbb68b7c8e71c6f722a44a9d0bbd6eb 0000000000000000ffffffff00000000 fdbb68b7c8e71c6f722a44a9d0bbd6eb fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtm.u32.f32 q12, q3 aa55fbfa79b866314b422835a677255b 70bac36b6d68de926d68de92f06f0978 ffffffffffffffffffffffff00000000 70bac36b6d68de926d68de92f06f0978 fpscr=00000000
+vcvtm.u32.f32 q12, q3 4102c686cb95551bc18fe3f56f28e1f0 bd56484dfe6a35aa3f752db41008ed6c 00000000000000000000000000000000 bd56484dfe6a35aa3f752db41008ed6c fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: 16384 calls, 16941 iters
+vcvtm.u32.f32 q12, q3 085a1e7a5e094db32b6c1a1a341dd732 fa59d05967258f62e4f4774baafecef5 00000000ffffffff0000000000000000 fa59d05967258f62e4f4774baafecef5 fpscr=00000000
+vcvtm.u32.f32 q12, q3 4e6f28b6c9363bbc3dd5831769a855ea 5edece48eb5d48deea1ae4323632c835 ffffffff000000000000000000000000 5edece48eb5d48deea1ae4323632c835 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.u32.f32 q12, q3 8f932d6bc86c63345fe23915c7ad8d5e 5d2b3ed4faf5f42ef1f27a85b4ddd6fc ffffffff000000000000000000000000 5d2b3ed4faf5f42ef1f27a85b4ddd6fc fpscr=00000000
+vcvtm.u32.f32 q12, q3 af0e051de2b9d9253a631a820e2817d8 66f3d5b154a91f20cc7f417b2c5ca6c1 ffffffffffffffff0000000000000000 66f3d5b154a91f20cc7f417b2c5ca6c1 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtm.u32.f32 q12, q3 33e82905bad8ef994455715dbf2fa391 2c045d5a50eeae2cd8b24a7a79f815d1 00000000ffffffff00000000ffffffff 2c045d5a50eeae2cd8b24a7a79f815d1 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintn.f32.f32 d0, d18 99269f54564d12988a1f09f2fd2a8303 87b725a587b725a54b8936848f62696f 99269f54564d12984b89368480000000 87b725a587b725a54b8936848f62696f fpscr=00000000
+vrintn.f32.f32 d0, d18 29f71457b3e74060deb0d5e06bf75996 7882b53d380704e1f434b2d6e9016555 29f71457b3e74060f434b2d6e9016555 7882b53d380704e1f434b2d6e9016555 fpscr=00000000
+vrintn.f32.f32 d0, d18 69a8bbca8ff74a35add1bd0aa34e774c f02470061c74c0acc481d2fa82c7fd7d 69a8bbca8ff74a35c481e00080000000 f02470061c74c0acc481d2fa82c7fd7d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintn.f32.f32 d0, d18 24436970468713db24b5f23f830f1be1 9aef0fde6433ae114a8b1fc4ca21ccbc 24436970468713db4a8b1fc4ca21ccbc 9aef0fde6433ae114a8b1fc4ca21ccbc fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[2]
+vrintn.f32.f32 d0, d18 469bb931fbf7baffc46c7f46ac23161d 2eec94c06355883857608f5663558838 469bb931fbf7baff57608f5663558838 2eec94c06355883857608f5663558838 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintn.f32.f32 d0, d18 4410908ca9d06cf0b2365b8314962961 03dda891861659aa5846fcbc48775019 4410908ca9d06cf05846fcbc48775000 03dda891861659aa5846fcbc48775019 fpscr=00000000
+vrintn.f32.f32 d0, d18 5076376eff10d948d38c8b3ac55da975 bd10e10ccfa116088275892b24dde209 5076376eff10d9488000000000000000 bd10e10ccfa116088275892b24dde209 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintn.f32.f32 d0, d18 da6e9476db1470abe8b06ac0b3d1555d 19fa0bd919fa0bd9f5a8eb26384923d6 da6e9476db1470abf5a8eb2600000000 19fa0bd919fa0bd9f5a8eb26384923d6 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintn.f32.f32 d0, d18 0160f9d3091fbe57bdfe46aea7371bc2 b6a9d89426d7aca9aaff9d3417fdf32f 0160f9d3091fbe578000000000000000 b6a9d89426d7aca9aaff9d3417fdf32f fpscr=00000000
+vrintn.f32.f32 d0, d18 0f9578796f1b0c54de33165d4352e772 c86d995391e31a189f5eb2befd04fe12 0f9578796f1b0c5480000000fd04fe12 c86d995391e31a189f5eb2befd04fe12 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintn.f32.f32 d0, d18 75e122996874cb7df8da29a83738cfbd 2044ad2b7e32db29d8cd09f17e32db29 75e122996874cb7dd8cd09f17e32db29 2044ad2b7e32db29d8cd09f17e32db29 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintn.f32.f32 d0, d18 163ac4e60eaa5677e58938d676c4b479 b62da0e45979c41cf99c3a06905200b8 163ac4e60eaa5677f99c3a0680000000 b62da0e45979c41cf99c3a06905200b8 fpscr=00000000
+vrintn.f32.f32 d0, d18 7c4418cb0b0d98b54b26388a1c43a356 c567ffe5cdaa304c866138ab07132e9e 7c4418cb0b0d98b58000000000000000 c567ffe5cdaa304c866138ab07132e9e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintn.f32.f32 d0, d18 6a5ef00d45f4b32a9d58ce116b24fdbc ef0f3713ef0f3713f7b1afd9b4076b44 6a5ef00d45f4b32af7b1afd980000000 ef0f3713ef0f3713f7b1afd9b4076b44 fpscr=00000000
+vrintn.f32.f32 d0, d18 2fc254b0d8e5c84a4f1059694db79ad4 c11d3a8f1350f18cd599a6384cb8a7dd 2fc254b0d8e5c84ad599a6384cb8a7dd c11d3a8f1350f18cd599a6384cb8a7dd fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vrintn.f32.f32 d0, d18 b33d0c622f112766461b0f519b279604 ddec642bf7a180e6c2db4ac3c2db4ac3 b33d0c622f112766c2dc0000c2dc0000 ddec642bf7a180e6c2db4ac3c2db4ac3 fpscr=00000000
+vrintn.f32.f32 d0, d18 a37bf3c3e2399090e61a1f57b7005fed 5d4004b6c1a312ab6437e94a4da63edb a37bf3c3e23990906437e94a4da63edb 5d4004b6c1a312ab6437e94a4da63edb fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintn.f32.f32 d0, d18 0cd44e9379acc6378ed57e7e2f9df633 471a9adffc370119f99a17b2c8d2338b 0cd44e9379acc637f99a17b2c8d23380 471a9adffc370119f99a17b2c8d2338b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintn.f32.f32 d0, d18 a50eef221b1221cf19a70a3726ea8c3f 8bd0af64df518022f879c02ff879c02f a50eef221b1221cff879c02ff879c02f 8bd0af64df518022f879c02ff879c02f fpscr=00000000
+vrintn.f32.f32 d0, d18 85515db15b17273ab4a5fbd9c26724bb af7fbbb9e2f6a63097edde5ad2d56499 85515db15b17273a80000000d2d56499 af7fbbb9e2f6a63097edde5ad2d56499 fpscr=00000000
+vrintn.f32.f32 d0, d18 27d5e05fa561a60d20dee22b3f6e5336 baa9792e043011f7d2eabcbbd05f77b5 27d5e05fa561a60dd2eabcbbd05f77b5 baa9792e043011f7d2eabcbbd05f77b5 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintn.f32.f32 d0, d18 8559d5f5cddee8eccddee8ec28f5c131 245c321cc41b950b442f21c10c47bc79 8559d5f5cddee8ec442f400000000000 245c321cc41b950b442f21c10c47bc79 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintn.f32.f32 d0, d18 088202df6449bf661be5b6da5c2c5da9 97641ba297641ba2ded9c8551257e793 088202df6449bf66ded9c85500000000 97641ba297641ba2ded9c8551257e793 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintn.f32.f32 d0, d18 e4c4073605759b02e6ac42486e7ce694 29592e63f01cb56729592e63c8753a35 e4c4073605759b0200000000c8753a40 29592e63f01cb56729592e63c8753a35 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintn.f32.f32 d0, d18 0f1bf4b78db21a3a9eee77a25e1e8422 28b3ddf51ae2fa4f28b3ddf59786d1c6 0f1bf4b78db21a3a0000000080000000 28b3ddf51ae2fa4f28b3ddf59786d1c6 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintn.f32.f32 d0, d18 07d74fb17c6e71f37f3743297c6e71f3 1745e444618513f3c350767e36c59d1f 07d74fb17c6e71f3c350000000000000 1745e444618513f3c350767e36c59d1f fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintn.f32.f32 d0, d18 9f3a31c9b810515ab1542163b1542163 e2c50be2092ae4b6851f5882933dc3d6 9f3a31c9b810515a8000000080000000 e2c50be2092ae4b6851f5882933dc3d6 fpscr=00000000
+vrintn.f32.f32 d0, d18 c4c93b93c2882c141ed17887e9be5fa9 2850ce7fd51dd0392118bcf99a70a0f7 c4c93b93c2882c140000000080000000 2850ce7fd51dd0392118bcf99a70a0f7 fpscr=00000000
+vrintn.f32.f32 d0, d18 969b03c27c05811bab05a43fa0425553 552fc0b13d3b3a0d4bb7e6b34ee3a6ea 969b03c27c05811b4bb7e6b34ee3a6ea 552fc0b13d3b3a0d4bb7e6b34ee3a6ea fpscr=00000000
+vrintn.f32.f32 d0, d18 ea82e937f42b077ec556088edefa0766 2e6fad8abc31c8b2038ff4f324f42cb0 ea82e937f42b077e0000000000000000 2e6fad8abc31c8b2038ff4f324f42cb0 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintn.f32.f32 d0, d18 338191668e305480e72e62d4fd9e31cc 4db8338815409300e221fba259aadc94 338191668e305480e221fba259aadc94 4db8338815409300e221fba259aadc94 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintn.f32.f32 d0, d18 5f3ae121efd24d7ed4c7b5112e908df0 ed3076e06d17e06fbfa9689ca9e6625b 5f3ae121efd24d7ebf80000080000000 ed3076e06d17e06fbfa9689ca9e6625b fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintn.f32.f32 d0, d18 ebc9c1fbfcea4c65d03abbb680bf38dc fa3c5f9977169b202f7a356de2cfacb5 ebc9c1fbfcea4c6500000000e2cfacb5 fa3c5f9977169b202f7a356de2cfacb5 fpscr=00000000
+vrintn.f32.f32 d0, d18 83ea21f43a48d6562f3e428c475cce83 7070f302a1dc2bec437468f520756cbb 83ea21f43a48d6564374000000000000 7070f302a1dc2bec437468f520756cbb fpscr=00000000
+vrintn.f32.f32 d0, d18 920c031fb9d8c3779ab4bc30930b8e6e 0cbd16394755fd081eaa5c306b1b1af1 920c031fb9d8c377000000006b1b1af1 0cbd16394755fd081eaa5c306b1b1af1 fpscr=00000000
+vrintn.f32.f32 d0, d18 ee6e6a2fd4f1b301708b18153548fd38 a2536b3bcfe01fc2fe9306d82d0a6d67 ee6e6a2fd4f1b301fe9306d800000000 a2536b3bcfe01fc2fe9306d82d0a6d67 fpscr=00000000
+vrintn.f32.f32 d0, d18 5c3ef20b4e44c1799df92aac07e57eae 2eec7a3d30dee43882e103aa778aecd1 5c3ef20b4e44c17980000000778aecd1 2eec7a3d30dee43882e103aa778aecd1 fpscr=00000000
+vrintn.f32.f32 d0, d18 9890538501ae30429b7c55194c05c801 00916c29439c05c79b2cf88a0321a351 9890538501ae30428000000000000000 00916c29439c05c79b2cf88a0321a351 fpscr=00000000
+vrintn.f32.f32 d0, d18 00df182b1fd1bf8d589f813e33f686f1 e7c509d1151db9de0357c9fcc49f8592 00df182b1fd1bf8d00000000c49f8000 e7c509d1151db9de0357c9fcc49f8592 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintn.f32.f32 d0, d18 430a92891538b336845abbf44e7ca43d bf9cf128c4de38e8ee5e4d462932acc1 430a92891538b336ee5e4d4600000000 bf9cf128c4de38e8ee5e4d462932acc1 fpscr=00000000
+vrintn.f32.f32 d0, d18 41fd9ffc9e040510833ab5f726bee7ae bf470a3b964c2faa8e88af8a8189dd4b 41fd9ffc9e0405108000000080000000 bf470a3b964c2faa8e88af8a8189dd4b fpscr=00000000
+vrintn.f32.f32 d0, d18 581d4e2bfa9a4dd6512f46d109d5ac50 492867ec1c6f830c2a2ddf095e12f0f1 581d4e2bfa9a4dd6000000005e12f0f1 492867ec1c6f830c2a2ddf095e12f0f1 fpscr=00000000
+vrintn.f32.f32 d0, d18 c9d3d6fe4ea0b9d434fdaccb3e81e3bf 3d1f0c7904beceef5bf0fba751a06f5b c9d3d6fe4ea0b9d45bf0fba751a06f5b 3d1f0c7904beceef5bf0fba751a06f5b fpscr=00000000
+vrintn.f32.f32 d0, d18 05be014b0c39977eca48eb464e051dbb 8692f24b334cd4a1ad3312525a29506b 05be014b0c39977e800000005a29506b 8692f24b334cd4a1ad3312525a29506b fpscr=00000000
+vrintn.f32.f32 d0, d18 7b63b8d6bdae5a293b0096562cf34461 643cb3797215bdaf053d371f26e61174 7b63b8d6bdae5a290000000000000000 643cb3797215bdaf053d371f26e61174 fpscr=00000000
+vrintn.f32.f32 d0, d18 37acb61c4514eff5271dc6ccb7083364 96518506c1cc2fb909a3bfc094531352 37acb61c4514eff50000000080000000 96518506c1cc2fb909a3bfc094531352 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintn.f32.f32 d0, d18 ed499a0387c3779ee7427027a4eca614 6c021b767bf84ea6760b605a2b9bd9db ed499a0387c3779e760b605a00000000 6c021b767bf84ea6760b605a2b9bd9db fpscr=00000000
+vrintn.f32.f32 d0, d18 bdb85eec62696cb9572835361761c2cf decbb06361c06f809d4047542bbd645b bdb85eec62696cb98000000000000000 decbb06361c06f809d4047542bbd645b fpscr=00000000
+vrintn.f32.f32 d0, d18 ac6b1b64418f4bd6b56e2f43ea9ca1e5 783c79b61ca7c592b424c71b70f7d9c7 ac6b1b64418f4bd68000000070f7d9c7 783c79b61ca7c592b424c71b70f7d9c7 fpscr=00000000
+vrintn.f32.f32 d0, d18 fc13b0a1d26bacf74791c27733b196c7 ed28d80b656fd2e2e71c7da3774c5333 fc13b0a1d26bacf7e71c7da3774c5333 ed28d80b656fd2e2e71c7da3774c5333 fpscr=00000000
+vrinta.f32.f32 d3, d21 97f5278caed370f98f446dbf2e9f24b1 cd5361470bf5c557bdd1fc16208ab8f6 cd536147000000008f446dbf2e9f24b1 cd5361470bf5c557bdd1fc16208ab8f6 fpscr=00000000
+vrinta.f32.f32 d3, d21 5256eccc658c57966dfa66e544d6be9e db01a190cf21300e54e6913262c3d7b2 db01a190cf21300e6dfa66e544d6be9e db01a190cf21300e54e6913262c3d7b2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[2]
+vrinta.f32.f32 d3, d21 5293379083ce77168f94e39352933790 17ecfd94fd76fa13fd76fa13c887ae5b 00000000fd76fa138f94e39352933790 17ecfd94fd76fa13fd76fa13c887ae5b fpscr=00000000
+vrinta.f32.f32 d3, d21 18c05207522f5c9edccbc9e7684f686b cf82405b73a5cd121cbc994fe2eea0d5 cf82405b73a5cd12dccbc9e7684f686b cf82405b73a5cd121cbc994fe2eea0d5 fpscr=00000000
+vrinta.f32.f32 d3, d21 40d528730624e858b43f7e5dc5e7eab8 6aa3acb84e6f2a9a3541f7f3ac701cde 6aa3acb84e6f2a9ab43f7e5dc5e7eab8 6aa3acb84e6f2a9a3541f7f3ac701cde fpscr=00000000
+vrinta.f32.f32 d3, d21 136684cd6a23ebdf15d2a881e1ace436 d2ef3befa9011bfe7a96d65b874076f1 d2ef3bef8000000015d2a881e1ace436 d2ef3befa9011bfe7a96d65b874076f1 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrinta.f32.f32 d3, d21 02296ca30256a191cb6a7ea0a6acf262 dd35775f752f7bed752f7bed355625ff dd35775f752f7bedcb6a7ea0a6acf262 dd35775f752f7bed752f7bed355625ff fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrinta.f32.f32 d3, d21 e45d0ff7e65be8f2c3c99fcd9308c38a 2225ae64fc47b64340346419043fac8c 00000000fc47b643c3c99fcd9308c38a 2225ae64fc47b64340346419043fac8c fpscr=00000000
+vrinta.f32.f32 d3, d21 b5470d30798e44d3222c6e9c52b056e1 6e22f7b3b7c5cb859b5c756f766cf61d 6e22f7b380000000222c6e9c52b056e1 6e22f7b3b7c5cb859b5c756f766cf61d fpscr=00000000
+randV128: 16640 calls, 17205 iters
+vrinta.f32.f32 d3, d21 10787b9dd749c9df55016c77eea3f9ee 02d89106959474c2841cfd86ed25a8f2 000000008000000055016c77eea3f9ee 02d89106959474c2841cfd86ed25a8f2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrinta.f32.f32 d3, d21 20762f2f90a8ada8dfead39a80e5bc28 de040777d0ee27f4de040777155a9887 de040777d0ee27f4dfead39a80e5bc28 de040777d0ee27f4de040777155a9887 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrinta.f32.f32 d3, d21 334ae07be943acbf86e74c64137d2c09 5f3833c80862772da145ddd742ee28d1 5f3833c80000000086e74c64137d2c09 5f3833c80862772da145ddd742ee28d1 fpscr=00000000
+vrinta.f32.f32 d3, d21 2c0af4c155555cf354030d880b072a63 ce9c24e621b1a173c18aa09dfa5b1ff6 ce9c24e60000000054030d880b072a63 ce9c24e621b1a173c18aa09dfa5b1ff6 fpscr=00000000
+vrinta.f32.f32 d3, d21 a269c25d7eba441a325ec39151fb2812 c75c10fae785f4139138bd4960512979 c75c1100e785f413325ec39151fb2812 c75c10fae785f4139138bd4960512979 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrinta.f32.f32 d3, d21 95fcbf941f94cb11ecee6d241227777e e52bdfe0044063b4360b316b970b5739 e52bdfe000000000ecee6d241227777e e52bdfe0044063b4360b316b970b5739 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[0]
+vrinta.f32.f32 d3, d21 29ee8ab3acf81b827de830ac596b5c5b 9dd87ce1cf58785010b3799101c4ecdd 80000000cf5878507de830ac596b5c5b 9dd87ce1cf58785010b3799101c4ecdd fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrinta.f32.f32 d3, d21 55008da055008da04046aa907f2569a5 27f529348e4950f486cab5126760596c 00000000800000004046aa907f2569a5 27f529348e4950f486cab5126760596c fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrinta.f32.f32 d3, d21 1e9c13884ac7b683b069841616d357b2 87393b2e6a05f737c5f0069dc5f0069d 800000006a05f737b069841616d357b2 87393b2e6a05f737c5f0069dc5f0069d fpscr=00000000
+vrinta.f32.f32 d3, d21 eebb2ace600972a024c319df94ea0da8 f1d392f6be8a0b95be46cfc6c9af2134 f1d392f68000000024c319df94ea0da8 f1d392f6be8a0b95be46cfc6c9af2134 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrinta.f32.f32 d3, d21 7ce53451a6c7586e3cd23cc58129c0c3 df85d4af9307bbf41307d79f7b20b716 df85d4af800000003cd23cc58129c0c3 df85d4af9307bbf41307d79f7b20b716 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrinta.f32.f32 d3, d21 754c38d19d81d5f77e26661704495945 434f34726dd254199b5ab17d9b5ab17d 434f00006dd254197e26661704495945 434f34726dd254199b5ab17d9b5ab17d fpscr=00000000
+vrinta.f32.f32 d3, d21 7d69acd7738ab4c93e209d8de5139442 f1b962c56d3361dd5b370a1e2770aba5 f1b962c56d3361dd3e209d8de5139442 f1b962c56d3361dd5b370a1e2770aba5 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrinta.f32.f32 d3, d21 ae8a2985325bdd8ab46ca4ae92c9003b 9e5c71f7adbc0d789b5aa714c1811844 8000000080000000b46ca4ae92c9003b 9e5c71f7adbc0d789b5aa714c1811844 fpscr=00000000
+vrinta.f32.f32 d3, d21 d4c832f8251eb5e57a28f2d3cd2d213e 9f12cccc20c754c84a36b50155631065 80000000000000007a28f2d3cd2d213e 9f12cccc20c754c84a36b50155631065 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrinta.f32.f32 d3, d21 642b3427fdcf2809a201631b77a09b31 b47521214cb07bb7cc551c93961a6968 800000004cb07bb7a201631b77a09b31 b47521214cb07bb7cc551c93961a6968 fpscr=00000000
+vrinta.f32.f32 d3, d21 9eb58329d13e5d4ca7236f3744ab99ff 156db91244191d769b10d88f61ff21d6 0000000044190000a7236f3744ab99ff 156db91244191d769b10d88f61ff21d6 fpscr=00000000
+vrinta.f32.f32 d3, d21 86802a65c90750561b9f2cd49ec6095f e91fa1ec4e5377b493df5cc5d33ba48f e91fa1ec4e5377b41b9f2cd49ec6095f e91fa1ec4e5377b493df5cc5d33ba48f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrinta.f32.f32 d3, d21 810f8f582a4931a4f4ed634f271db222 0132c6b8866ed24a11f16192879fd044 0000000080000000f4ed634f271db222 0132c6b8866ed24a11f16192879fd044 fpscr=00000000
+vrinta.f32.f32 d3, d21 8e7e39dad2ffc4797128ccdaca76ffc7 ed39264f830c8d066fad53f3e5b4bf27 ed39264f800000007128ccdaca76ffc7 ed39264f830c8d066fad53f3e5b4bf27 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrinta.f32.f32 d3, d21 08b7d43786db8cd94eb2e24314b04c95 a0fe86dd276ce394ee0f4f6e105bb08d 80000000000000004eb2e24314b04c95 a0fe86dd276ce394ee0f4f6e105bb08d fpscr=00000000
+vrinta.f32.f32 d3, d21 4b08a1fe1e30275adae35bfb7a2d9aa4 c3b6778bf8964e3aca2b45733babc759 c3b68000f8964e3adae35bfb7a2d9aa4 c3b6778bf8964e3aca2b45733babc759 fpscr=00000000
+vrinta.f32.f32 d3, d21 746dcaf67bb7619c8427f106173aed40 3ec85e28a60e93849215149a706aa630 00000000800000008427f106173aed40 3ec85e28a60e93849215149a706aa630 fpscr=00000000
+vrinta.f32.f32 d3, d21 78aa8141cf40429cdf7e79eba07f451e 9f6670250d0aacad38525fcdb38254fc 8000000000000000df7e79eba07f451e 9f6670250d0aacad38525fcdb38254fc fpscr=00000000
+vrinta.f32.f32 d3, d21 bc6d426436b247af9ba1a0f757bcca4a ad49cd436ac3d80371f69f90d8623a48 800000006ac3d8039ba1a0f757bcca4a ad49cd436ac3d80371f69f90d8623a48 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrinta.f32.f32 d3, d21 1e84d310a5c04a72841d6239baefc669 79dacc097900bd270f683b2ec96c97b3 79dacc097900bd27841d6239baefc669 79dacc097900bd270f683b2ec96c97b3 fpscr=00000000
+vrinta.f32.f32 d3, d21 86764cf5f4c3659e4f0a1bacf562424c cb83df0b94eda017985cc57d5e25ee35 cb83df0b800000004f0a1bacf562424c cb83df0b94eda017985cc57d5e25ee35 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[3]
+vrinta.f32.f32 d3, d21 34cf19e7ebd7761934cf19e79c0dff91 e0803f61741a126774cad7b84e792c78 e0803f61741a126734cf19e79c0dff91 e0803f61741a126774cad7b84e792c78 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrinta.f32.f32 d3, d21 dae2dee83d5d4835f4dcc6083d4cc961 e6eea1917812553a3490a66261db159c e6eea1917812553af4dcc6083d4cc961 e6eea1917812553a3490a66261db159c fpscr=00000000
+vrinta.f32.f32 d3, d21 e2de0e0e843f06fdfccf235d20784880 7e79182882b5be7fc913c7fc5cdbca12 7e79182880000000fccf235d20784880 7e79182882b5be7fc913c7fc5cdbca12 fpscr=00000000
+vrinta.f32.f32 d3, d21 2c15f572cc724ba4f04f507dfe20c609 79ee5a65777525c8fac9273ef8eb4afe 79ee5a65777525c8f04f507dfe20c609 79ee5a65777525c8fac9273ef8eb4afe fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrinta.f32.f32 d3, d21 7ae177538ef69a097ae177534199106c 3a7a03df8c3cfbbb84c95493e26be79a 00000000800000007ae177534199106c 3a7a03df8c3cfbbb84c95493e26be79a fpscr=00000000
+vrinta.f32.f32 d3, d21 71298730c3ea1e6cc804614d60eb6062 abad57e87f1d9de027818dd05b66f333 800000007f1d9de0c804614d60eb6062 abad57e87f1d9de027818dd05b66f333 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrinta.f32.f32 d3, d21 9d35b6ec3aa0f090496e3aca50ae03fa 365ae32037c796b72d2655b04d96108e 0000000000000000496e3aca50ae03fa 365ae32037c796b72d2655b04d96108e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrinta.f32.f32 d3, d21 afe0da645494cefa7cf9272b5494cefa 0616c6a38fd69ae0081834edca9be23b 00000000800000007cf9272b5494cefa 0616c6a38fd69ae0081834edca9be23b fpscr=00000000
+vrinta.f32.f32 d3, d21 8c1bd449e8a23bbeae6982b55822e335 cb1f9e3eb6021eea944c26cf5f475fb4 cb1f9e3e80000000ae6982b55822e335 cb1f9e3eb6021eea944c26cf5f475fb4 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrinta.f32.f32 d3, d21 4846d58970ff790361f7b6c870ff7903 64aad6ee02e0f171b449d2efa88cae78 64aad6ee0000000061f7b6c870ff7903 64aad6ee02e0f171b449d2efa88cae78 fpscr=00000000
+vrinta.f32.f32 d3, d21 1254ac282fb9f0207ac7b1753ed3c18b 74a396d014c809653aedc473fce5ab4c 74a396d0000000007ac7b1753ed3c18b 74a396d014c809653aedc473fce5ab4c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrinta.f32.f32 d3, d21 5608b5d1f6f1e6785b80e0493dc3a8e8 3a56dde30d8d7ca320c57d15cfa48ae7 00000000000000005b80e0493dc3a8e8 3a56dde30d8d7ca320c57d15cfa48ae7 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrinta.f32.f32 d3, d21 5da364225da364228bc99866874c2f6f 0d960dc098447e4ddda5b41bc04db034 00000000800000008bc99866874c2f6f 0d960dc098447e4ddda5b41bc04db034 fpscr=00000000
+vrinta.f32.f32 d3, d21 4214e4cbdea89d948d6ea6d430d22e82 8d5f01ba8a59fe66731761893820c7f7 80000000800000008d6ea6d430d22e82 8d5f01ba8a59fe66731761893820c7f7 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintp.f32.f32 d6, d24 b2a06289b84f289c279fa564b2a06289 509c9eaea3d83057baad8b909e57f4e7 b2a06289b84f289c8000000080000000 509c9eaea3d83057baad8b909e57f4e7 fpscr=00000000
+vrintp.f32.f32 d6, d24 894759efb28323bee7317340c7a9a65c 5dee2ef1db4142fe8b09469ff9041b8a 894759efb28323be80000000f9041b8a 5dee2ef1db4142fe8b09469ff9041b8a fpscr=00000000
+vrintp.f32.f32 d6, d24 f8e1cac941236c5bbdc098c0ad1da33b 63adf853f00887d304d01900f24d2132 f8e1cac941236c5b3f800000f24d2132 63adf853f00887d304d01900f24d2132 fpscr=00000000
+vrintp.f32.f32 d6, d24 05a0721deabfb114e168800dfa99c76b 74678a942141408c510986e7f767e9f5 05a0721deabfb114510986e7f767e9f5 74678a942141408c510986e7f767e9f5 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintp.f32.f32 d6, d24 a6a43a4d6f903b9df96343806a193d81 46dd750eb82263cfb83a621046dd750e a6a43a4d6f903b9d8000000046dd7600 46dd750eb82263cfb83a621046dd750e fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintp.f32.f32 d6, d24 5a51a63c4d385a80c9d251ba7978fb4e 31989c2131989c21bc6d7f6da05f6b86 5a51a63c4d385a808000000080000000 31989c2131989c21bc6d7f6da05f6b86 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintp.f32.f32 d6, d24 7489dd28289f249a03ce4cd2433a85e0 51115b874a23e95e8358903f4a23e95e 7489dd28289f249a800000004a23e960 51115b874a23e95e8358903f4a23e95e fpscr=00000000
+vrintp.f32.f32 d6, d24 e43756489c28254fd01333c2fea692d8 9c0914a5b18506402f85bd3474784def e43756489c28254f3f80000074784def 9c0914a5b18506402f85bd3474784def fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintp.f32.f32 d6, d24 26a06d6868a9f211afdd246f26a06d68 be0c1243cb2517b45ed0c2e79d9ffbf6 26a06d6868a9f2115ed0c2e780000000 be0c1243cb2517b45ed0c2e79d9ffbf6 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintp.f32.f32 d6, d24 4291118af3f2ef3b527e7acdf3f2ef3b e1298589e2753e71d17e18fa27292aa7 4291118af3f2ef3bd17e18fa3f800000 e1298589e2753e71d17e18fa27292aa7 fpscr=00000000
+vrintp.f32.f32 d6, d24 6ffdceb1f61ae14ff76c4e2873d22374 6952678a362650ee3de352b2cf94bbfb 6ffdceb1f61ae14f3f800000cf94bbfb 6952678a362650ee3de352b2cf94bbfb fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintp.f32.f32 d6, d24 0808efe9f5a37ae02ad4edf02ad4edf0 b83fecb1ad66979ba1d16f5d90c2f6ad 0808efe9f5a37ae08000000080000000 b83fecb1ad66979ba1d16f5d90c2f6ad fpscr=00000000
+vrintp.f32.f32 d6, d24 e56db278d7d3b95eb5559b7d8a7c3f4b 4ca7ce37bac5c79514cceebca776edae e56db278d7d3b95e3f80000080000000 4ca7ce37bac5c79514cceebca776edae fpscr=00000000
+vrintp.f32.f32 d6, d24 16ba93f1944f83f3f34473cffd5ed195 0c3e150ca2c9c707d58da3a781824544 16ba93f1944f83f3d58da3a780000000 0c3e150ca2c9c707d58da3a781824544 fpscr=00000000
+vrintp.f32.f32 d6, d24 113ec20add2416f90898e3df05c20cb7 8f0158bb480dfed99a8be23f31a4e24f 113ec20add2416f9800000003f800000 8f0158bb480dfed99a8be23f31a4e24f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintp.f32.f32 d6, d24 858a30b5758ef3ca962504fb978dde44 a7e80f3c7f6a938dbef2653da7e80f3c 858a30b5758ef3ca8000000080000000 a7e80f3c7f6a938dbef2653da7e80f3c fpscr=00000000
+vrintp.f32.f32 d6, d24 660187da71384ab89ace40b0dee416a2 ccbf8567b4d30af14c92e770b892e658 660187da71384ab84c92e77080000000 ccbf8567b4d30af14c92e770b892e658 fpscr=00000000
+vrintp.f32.f32 d6, d24 aa211dcd330747a1bc85d3ce6de85003 3d57783876f17db3aa2fd7bedb5a27f5 aa211dcd330747a180000000db5a27f5 3d57783876f17db3aa2fd7bedb5a27f5 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintp.f32.f32 d6, d24 63a0d83eb5ce228e861a0ac7fed8002c d3a890350d4a78c08ba05a3916fa03e7 63a0d83eb5ce228e800000003f800000 d3a890350d4a78c08ba05a3916fa03e7 fpscr=00000000
+vrintp.f32.f32 d6, d24 d95714ee4cf78db1f85f934d47833e99 afbb7fabe3c110756f480088a3206bab d95714ee4cf78db16f48008880000000 afbb7fabe3c110756f480088a3206bab fpscr=00000000
+vrintp.f32.f32 d6, d24 3777f44073cd5cf7cd45b8bb36e924ff f9446488a456b20acb9b843b1db173f0 3777f44073cd5cf7cb9b843b3f800000 f9446488a456b20acb9b843b1db173f0 fpscr=00000000
+vrintp.f32.f32 d6, d24 50c863f8e70e5a0ae6d8b47e4991c41d 5d9630860a4dbdb0760492f0882a8fda 50c863f8e70e5a0a760492f080000000 5d9630860a4dbdb0760492f0882a8fda fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintp.f32.f32 d6, d24 4c92326c045fc1e20f91bc3814d9fae3 7706d5d59773e60abe8699cc9773e60a 4c92326c045fc1e28000000080000000 7706d5d59773e60abe8699cc9773e60a fpscr=00000000
+randV128: 16896 calls, 17470 iters
+vrintp.f32.f32 d6, d24 be2f14dad207e2ec22cbaf97ea778e5e e0647b5f993ebe8c83879a7e55d074ce be2f14dad207e2ec8000000055d074ce e0647b5f993ebe8c83879a7e55d074ce fpscr=00000000
+vrintp.f32.f32 d6, d24 ba8c065c64d636028d88ccfd8c7c2fd0 8b5e971c93b2e8b1a30e541e82a9c597 ba8c065c64d636028000000080000000 8b5e971c93b2e8b1a30e541e82a9c597 fpscr=00000000
+vrintp.f32.f32 d6, d24 1d799ddfa6670f039fd9eb584e5fea26 21a7bc8a7ab6d98b818e89cdf35c989c 1d799ddfa6670f0380000000f35c989c 21a7bc8a7ab6d98b818e89cdf35c989c fpscr=00000000
+vrintp.f32.f32 d6, d24 0aeae6ecc11572bb7664c7ac4f99123a 5f18c6c3e1b27a755b6996630bd6bf93 0aeae6ecc11572bb5b6996633f800000 5f18c6c3e1b27a755b6996630bd6bf93 fpscr=00000000
+vrintp.f32.f32 d6, d24 6be9e3e3f6aadc1976f9f4cf08e30fba 04cdfb8bca1ff976a9c757468d572d81 6be9e3e3f6aadc198000000080000000 04cdfb8bca1ff976a9c757468d572d81 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintp.f32.f32 d6, d24 60fec8702d689d4301395d151d86047d 2c0bf912d7c4b5ddb2bd536ed7c4b5dd 60fec8702d689d4380000000d7c4b5dd 2c0bf912d7c4b5ddb2bd536ed7c4b5dd fpscr=00000000
+vrintp.f32.f32 d6, d24 89cd8af31965646a170cfc9ba0680bf7 55500514f79174b8435684623d3b78d2 89cd8af31965646a435700003f800000 55500514f79174b8435684623d3b78d2 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintp.f32.f32 d6, d24 b67b3df9a9ebfa72dccb42d1dccb42d1 67045bbae4d26cc3eb086dd845b8de3a b67b3df9a9ebfa72eb086dd845b8e000 67045bbae4d26cc3eb086dd845b8de3a fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintp.f32.f32 d6, d24 eb2d9dd18b30731beb2d9dd1f2910402 4a45cb6481dcbb68154b1b8d21d2f17d eb2d9dd18b30731b3f8000003f800000 4a45cb6481dcbb68154b1b8d21d2f17d fpscr=00000000
+vrintp.f32.f32 d6, d24 5d7653211f04318d60f5a7fc52b999b8 3e26b6e0aeaaf09a5eea1b68533567d8 5d7653211f04318d5eea1b68533567d8 3e26b6e0aeaaf09a5eea1b68533567d8 fpscr=00000000
+vrintp.f32.f32 d6, d24 592990e644da6a20e0b26a6063ec47d5 134933b4ff77922222a5d73b04f0e6e4 592990e644da6a203f8000003f800000 134933b4ff77922222a5d73b04f0e6e4 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintp.f32.f32 d6, d24 ce7cbedd97bf98b7677ea2b7de697606 358a1d6b358a1d6bd6bb447e0616df26 ce7cbedd97bf98b7d6bb447e3f800000 358a1d6b358a1d6bd6bb447e0616df26 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[2]
+vrintp.f32.f32 d6, d24 d1badd693c30643ed5e8cf8ccfa6a6c1 9f96e484b6d66fb1667c6ec09a4d8d39 d1badd693c30643e667c6ec080000000 9f96e484b6d66fb1667c6ec09a4d8d39 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintp.f32.f32 d6, d24 4aa46f8a7a3247c62f177087fc72527c a2bdce3b7e2aac7a1270b8a10128e415 4aa46f8a7a3247c63f8000003f800000 a2bdce3b7e2aac7a1270b8a10128e415 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintp.f32.f32 d6, d24 91d5f8637bf4ce4140354846a411f14d b2d23e9d9a3b8bc2c217c420eceaa1a0 91d5f8637bf4ce41c2140000eceaa1a0 b2d23e9d9a3b8bc2c217c420eceaa1a0 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintp.f32.f32 d6, d24 c04d728b14256f4e82e1da5582e1da55 770927f64db49a0b499cb6360619b8b8 c04d728b14256f4e499cb6383f800000 770927f64db49a0b499cb6360619b8b8 fpscr=00000000
+vrintp.f32.f32 d6, d24 67420418f0590d785ffc567aaf832340 c935340e914047aefd585ba89db6f0bc 67420418f0590d78fd585ba880000000 c935340e914047aefd585ba89db6f0bc fpscr=00000000
+vrintp.f32.f32 d6, d24 78efffe88501de85727bc61aa4a87ecc 8f2907b32d22d6f531d309521ac99bb2 78efffe88501de853f8000003f800000 8f2907b32d22d6f531d309521ac99bb2 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintp.f32.f32 d6, d24 661960b16f1c618643c0b0115d51b0bc b35f4267581d8b33644771ad26e8f780 661960b16f1c6186644771ad3f800000 b35f4267581d8b33644771ad26e8f780 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintp.f32.f32 d6, d24 9552deef995b8eb31311fc5941200161 fce0c416fb71b989fce0c416978a5003 9552deef995b8eb3fce0c41680000000 fce0c416fb71b989fce0c416978a5003 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintp.f32.f32 d6, d24 6c0917cfb7110d9415d2fc40a24b2a2c e539eaa068ce32636ead44ddee367099 6c0917cfb7110d946ead44ddee367099 e539eaa068ce32636ead44ddee367099 fpscr=00000000
+vrintp.f32.f32 d6, d24 a9b5b99e62aaa22bba5f80c08b6ef8af 2ee9a824d3c22390bf3fbc2f33edc629 a9b5b99e62aaa22b800000003f800000 2ee9a824d3c22390bf3fbc2f33edc629 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintp.f32.f32 d6, d24 f2c918d875349bbf866ea601796ab42f 31dc702c7b29439859847dfa513c3057 f2c918d875349bbf59847dfa513c3057 31dc702c7b29439859847dfa513c3057 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[3]
+vrintp.f32.f32 d6, d24 e8ef3b01756b9b12505e6744f8fa326d a109f2599c072981cb51ffc8a109f259 e8ef3b01756b9b12cb51ffc880000000 a109f2599c072981cb51ffc8a109f259 fpscr=00000000
+vrintp.f32.f32 d6, d24 fde06265971ca4d3391ea60a3cfa1b90 bceb2896d866fdc41fa5675deeb19f35 fde06265971ca4d33f800000eeb19f35 bceb2896d866fdc41fa5675deeb19f35 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintp.f32.f32 d6, d24 95f00bab22b45f9ede329f89261bc7fe 3848b7e89b27dcec3848b7e8bf696871 95f00bab22b45f9e3f80000080000000 3848b7e89b27dcec3848b7e8bf696871 fpscr=00000000
+vrintp.f32.f32 d6, d24 434038541d699746ba62550857d605a0 e61812921822d2b4368727e965f72f03 434038541d6997463f80000065f72f03 e61812921822d2b4368727e965f72f03 fpscr=00000000
+vrintm.f32.f32 d9, d27 951e761eb402f28a40579500240f7839 33ce7cc02db1f47218561b6dd062c012 000000000000000040579500240f7839 33ce7cc02db1f47218561b6dd062c012 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintm.f32.f32 d9, d27 0ec7827c0ec7827c1a66776abc91707f 482796c9510646d0178e3b788f941a9b 482796c0510646d01a66776abc91707f 482796c9510646d0178e3b788f941a9b fpscr=00000000
+vrintm.f32.f32 d9, d27 da7ecfb63c396d9b19c90e62084656cb 1c75fc4467118f5707b1a8de01cd734d 0000000067118f5719c90e62084656cb 1c75fc4467118f5707b1a8de01cd734d fpscr=00000000
+vrintm.f32.f32 d9, d27 5c32107222a5d3c813c85e9cb76ca876 684d194c37298bafc289bcaf03dcb8d8 684d194c0000000013c85e9cb76ca876 684d194c37298bafc289bcaf03dcb8d8 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintm.f32.f32 d9, d27 65d69e431ddaa0794eee87de6014c02b a64b85ba1375e2f344389382b76d7eb1 bf800000000000004eee87de6014c02b a64b85ba1375e2f344389382b76d7eb1 fpscr=00000000
+vrintm.f32.f32 d9, d27 82769da89e343d4b2d62105ceecbdfba 0db21fc957474914bc2e84e9c7a5cb80 00000000574749142d62105ceecbdfba 0db21fc957474914bc2e84e9c7a5cb80 fpscr=00000000
+vrintm.f32.f32 d9, d27 bf35d2b1e794e0f5fc3e335715bd0d44 83e27d0c5849c24959ab30e751a8a95d bf8000005849c249fc3e335715bd0d44 83e27d0c5849c24959ab30e751a8a95d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintm.f32.f32 d9, d27 9855f4c3a17fcbd2474c2bfd67fd7228 f9230bba9651e651cc525789af14a23c f9230bbabf800000474c2bfd67fd7228 f9230bba9651e651cc525789af14a23c fpscr=00000000
+vrintm.f32.f32 d9, d27 68b86202f371e0e890cd2c0a496481fe 63f3fa5a10e6260ceda968626854caae 63f3fa5a0000000090cd2c0a496481fe 63f3fa5a10e6260ceda968626854caae fpscr=00000000
+vrintm.f32.f32 d9, d27 f5b03dd9c8d575aeecbe5ec00f5d4035 744c262d21e6ba5956b309a36f345af3 744c262d00000000ecbe5ec00f5d4035 744c262d21e6ba5956b309a36f345af3 fpscr=00000000
+vrintm.f32.f32 d9, d27 3bcbe53414e1df8687642d060708f43f abc36659e46d77bf49f086f520d901c9 bf800000e46d77bf87642d060708f43f abc36659e46d77bf49f086f520d901c9 fpscr=00000000
+vrintm.f32.f32 d9, d27 396e5ecc9e1b183f90ba74a586c8696a efd883d938902eb764248abc3bf2bd0e efd883d90000000090ba74a586c8696a efd883d938902eb764248abc3bf2bd0e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintm.f32.f32 d9, d27 ccbf83c1b3b142693dab6ce24b9ddc96 6c271bf8ba9cebdbdb50cc2edb50cc2e 6c271bf8bf8000003dab6ce24b9ddc96 6c271bf8ba9cebdbdb50cc2edb50cc2e fpscr=00000000
+vrintm.f32.f32 d9, d27 9e15d47475005eed3659272a5523f8da aba1d700f53dacd9f2f402919f85f4e5 bf800000f53dacd93659272a5523f8da aba1d700f53dacd9f2f402919f85f4e5 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[0]
+vrintm.f32.f32 d9, d27 b5e42d0fe7068d0bf39188a6f39188a6 52d3740317eebe3b3b2914e830dced06 52d3740300000000f39188a6f39188a6 52d3740317eebe3b3b2914e830dced06 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintm.f32.f32 d9, d27 f6550f6c0d8691704c0a0a74e9875be4 e71dc58d13cd480b163e2182163e2182 e71dc58d000000004c0a0a74e9875be4 e71dc58d13cd480b163e2182163e2182 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintm.f32.f32 d9, d27 42f0629c42f0629c51cde8825c4d2ac6 c9f6430a6b14ed201aa4556925460dd8 c9f643106b14ed2051cde8825c4d2ac6 c9f6430a6b14ed201aa4556925460dd8 fpscr=00000000
+vrintm.f32.f32 d9, d27 a8e191f27a49d3620ed0af59f807ba08 80fd1c1a04a0f7d69df62064c87df550 bf800000000000000ed0af59f807ba08 80fd1c1a04a0f7d69df62064c87df550 fpscr=00000000
+vrintm.f32.f32 d9, d27 7c26b37391f2d665709beb58c6604c9f 83a85843b27b9afe4c4b099ad57c9bf1 bf800000bf800000709beb58c6604c9f 83a85843b27b9afe4c4b099ad57c9bf1 fpscr=00000000
+vrintm.f32.f32 d9, d27 85bca6a681497022e29e896d1092635c e718a20a66a34c12c635f76c41f726ca e718a20a66a34c12e29e896d1092635c e718a20a66a34c12c635f76c41f726ca fpscr=00000000
+vrintm.f32.f32 d9, d27 31e96d823fb8bc8647191ef3edb791d4 4aba3e254864551b1d67fe5310b0c874 4aba3e244864550047191ef3edb791d4 4aba3e254864551b1d67fe5310b0c874 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintm.f32.f32 d9, d27 143109917085a69bebce66437e5efeb7 a79f2dbf2f87bdc32f87bdc3ad5be575 bf80000000000000ebce66437e5efeb7 a79f2dbf2f87bdc32f87bdc3ad5be575 fpscr=00000000
+vrintm.f32.f32 d9, d27 63f6dfe3d9a3c31288c413dcd4a276bf d095bd184cdb4c585fd8b1045dcd7de0 d095bd184cdb4c5888c413dcd4a276bf d095bd184cdb4c585fd8b1045dcd7de0 fpscr=00000000
+vrintm.f32.f32 d9, d27 9413d0275ad854d6ddad1d4a53d47acc c437e7686f21a070e0573313a0d5b364 c43800006f21a070ddad1d4a53d47acc c437e7686f21a070e0573313a0d5b364 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintm.f32.f32 d9, d27 156ac0c229cfb5ea093219a0e46280ba 4e63a5c8bfeef8a31afcf4f082ed3e30 4e63a5c8c0000000093219a0e46280ba 4e63a5c8bfeef8a31afcf4f082ed3e30 fpscr=00000000
+vrintm.f32.f32 d9, d27 f911fb4b10d3f8b778e0ec91f2e1cee5 96dac9210bccf6ced15e84eb878bb187 bf8000000000000078e0ec91f2e1cee5 96dac9210bccf6ced15e84eb878bb187 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintm.f32.f32 d9, d27 8314216eea6fe43c1284df78ed703c3b 3cd05f55132c7d4f1fcd06d56a89f38d 00000000000000001284df78ed703c3b 3cd05f55132c7d4f1fcd06d56a89f38d fpscr=00000000
+vrintm.f32.f32 d9, d27 d751a8ec35a3e8232a54237a05ef97c5 a172ee3fe64fc4e86c39989e17ce6ea9 bf800000e64fc4e82a54237a05ef97c5 a172ee3fe64fc4e86c39989e17ce6ea9 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintm.f32.f32 d9, d27 fed8c0de34641b4f42ef1cbe032b0514 3b5583949ec548cf6724e327bc850791 00000000bf80000042ef1cbe032b0514 3b5583949ec548cf6724e327bc850791 fpscr=00000000
+vrintm.f32.f32 d9, d27 ec31983e647c403d71654d8443fc143a 750f361fccd5cd2ad1625b6ca6eb69d7 750f361fccd5cd2a71654d8443fc143a 750f361fccd5cd2ad1625b6ca6eb69d7 fpscr=00000000
+vrintm.f32.f32 d9, d27 f3cdc76697a9d21e7807f37c1cd58190 6653f373434b426271201d897383b7c6 6653f373434b00007807f37c1cd58190 6653f373434b426271201d897383b7c6 fpscr=00000000
+vrintm.f32.f32 d9, d27 569433f148725489880594872cf97877 101419959a82acd7bf25eac597e30bd1 00000000bf800000880594872cf97877 101419959a82acd7bf25eac597e30bd1 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintm.f32.f32 d9, d27 3cd0149d3cd0149d493adfc421253d59 e5460008ac3927b6e0f16b35c050cafe e5460008bf800000493adfc421253d59 e5460008ac3927b6e0f16b35c050cafe fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintm.f32.f32 d9, d27 3f44358e3f44358e9c08944cc8cf5604 c890f010ef9c001f0ebf3391f0eda821 c890f020ef9c001f9c08944cc8cf5604 c890f010ef9c001f0ebf3391f0eda821 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintm.f32.f32 d9, d27 c275b7364d63a974030d2a4a69cfbe48 4924f0104924f010e0c4285a2c0e7f8b 4924f0104924f010030d2a4a69cfbe48 4924f0104924f010e0c4285a2c0e7f8b fpscr=00000000
+vrintm.f32.f32 d9, d27 0d1e95c454ba196cd7850c4b29d4fc05 a8c13ef3c4c0d12add0ab81d9f74023a bf800000c4c0e000d7850c4b29d4fc05 a8c13ef3c4c0d12add0ab81d9f74023a fpscr=00000000
+vrintm.f32.f32 d9, d27 c1365d4c96c3b3e24eff516ee26c564f 52e0c4686a1623f6736ec7294d46b7e9 52e0c4686a1623f64eff516ee26c564f 52e0c4686a1623f6736ec7294d46b7e9 fpscr=00000000
+randV128: 17152 calls, 17733 iters
+vrintm.f32.f32 d9, d27 25e739a14a5c8d0855fdc9b8d95bca5b 40abedfc463f6a0a0bfa5488d3830b82 40a00000463f680055fdc9b8d95bca5b 40abedfc463f6a0a0bfa5488d3830b82 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintm.f32.f32 d9, d27 617d943506276bf170542b0baaaa3628 0f59d70d9104e307071319336bccb10a 00000000bf80000070542b0baaaa3628 0f59d70d9104e307071319336bccb10a fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintm.f32.f32 d9, d27 406aed1bdc2667fdc06e4a56e2f792fe 3bd6ce46b110a890bdce7e1781ed74bb 00000000bf800000c06e4a56e2f792fe 3bd6ce46b110a890bdce7e1781ed74bb fpscr=00000000
+vrintm.f32.f32 d9, d27 44a80e6f971593e7bb6f5cd8f66b65a9 fe6929230c80942a379814bb8a28c920 fe69292300000000bb6f5cd8f66b65a9 fe6929230c80942a379814bb8a28c920 fpscr=00000000
+vrintm.f32.f32 d9, d27 80db64a7ec36cbd608228bc49990ecbc b68d3752c2a6442649ddce3a764ffb0e bf800000c2a8000008228bc49990ecbc b68d3752c2a6442649ddce3a764ffb0e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintm.f32.f32 d9, d27 ce4568a8f8d3f9a46e0c838a6db989df 5a21ca732635cbca38165fbccc06cb68 5a21ca73000000006e0c838a6db989df 5a21ca732635cbca38165fbccc06cb68 fpscr=00000000
+vrintm.f32.f32 d9, d27 082dfd40837188015826fc8e78355e0c 36347ef1434a255bd6ee013bef50ecc0 00000000434a00005826fc8e78355e0c 36347ef1434a255bd6ee013bef50ecc0 fpscr=00000000
+vrintm.f32.f32 d9, d27 6d794bc7cc559b51ebfdccb0440a0b07 46b2dc1fda9ef01f2ded1190f161f393 46b2dc00da9ef01febfdccb0440a0b07 46b2dc1fda9ef01f2ded1190f161f393 fpscr=00000000
+vrintm.f32.f32 d9, d27 1b7b5fe824f7cb6d5b2790ad304ea9b4 3441e2c7c3aa7d80374a645efb649a97 00000000c3aa80005b2790ad304ea9b4 3441e2c7c3aa7d80374a645efb649a97 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintm.f32.f32 d9, d27 911f4fd0fcfa7f4854c52114fcfa7f48 e40ff630d960edb6f60f8f1346efad1a e40ff630d960edb654c52114fcfa7f48 e40ff630d960edb6f60f8f1346efad1a fpscr=00000000
+vrintm.f32.f32 d9, d27 4b9decd38ac052009a54e4cfd3bedc44 737e236665f57212d892ebabb7430bcc 737e236665f572129a54e4cfd3bedc44 737e236665f57212d892ebabb7430bcc fpscr=00000000
+vrintm.f32.f32 d9, d27 4296b7d27666a28e3878889e5764b25b 73bc2ea94e3f727f5f428a606c6e8efe 73bc2ea94e3f727f3878889e5764b25b 73bc2ea94e3f727f5f428a606c6e8efe fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintm.f32.f32 d9, d27 d43691c6ee90b2544e691acc76941358 0df1f9d3a4a6448449e612d335d69dfb 00000000bf8000004e691acc76941358 0df1f9d3a4a6448449e612d335d69dfb fpscr=00000000
+vrintz.f32.f32 d12, d30 4144930cc3d0a34442d3265a9e7fb405 6b35beabc9dc461e0f97fcd4c047c552 4144930cc3d0a34400000000c0400000 6b35beabc9dc461e0f97fcd4c047c552 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[2]
+vrintz.f32.f32 d12, d30 d32165c6abee5835abee5835f20ec953 6b69403e9d82a1c9c6e5c0300bcd03d2 d32165c6abee5835c6e5c00000000000 6b69403e9d82a1c9c6e5c0300bcd03d2 fpscr=00000000
+vrintz.f32.f32 d12, d30 68bcde34649e7a7008befd9af092057b 256a6f38d9f20092f478b01f60af20be 68bcde34649e7a70f478b01f60af20be 256a6f38d9f20092f478b01f60af20be fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[2]
+vrintz.f32.f32 d12, d30 c82c182a64ba3102c6fbfc40c6fbfc40 84e77f6b600408d387debd533458c834 c82c182a64ba31028000000000000000 84e77f6b600408d387debd533458c834 fpscr=00000000
+vrintz.f32.f32 d12, d30 dfb84365991b50a112fbf44ad15c0664 0873d11a9fbebe9e052212067a88f5d9 dfb84365991b50a1000000007a88f5d9 0873d11a9fbebe9e052212067a88f5d9 fpscr=00000000
+vrintz.f32.f32 d12, d30 3d64b1a8093ecda05d45e8a697f3670d 0e6b452122e731e9f10fec18e94fbd42 3d64b1a8093ecda0f10fec18e94fbd42 0e6b452122e731e9f10fec18e94fbd42 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintz.f32.f32 d12, d30 958590430da1675a265cb6ec32c0e8c7 97b27083b993998fa493663cfb40770d 958590430da1675a80000000fb40770d 97b27083b993998fa493663cfb40770d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[2]
+vrintz.f32.f32 d12, d30 f523408ef523408e77f5c04ee141bfab f6189bf3f6189bf3e009266022e1fcf5 f523408ef523408ee009266000000000 f6189bf3f6189bf3e009266022e1fcf5 fpscr=00000000
+vrintz.f32.f32 d12, d30 ae238b17ad3778f08ac160aebc2e7590 0292c9d4592464c812c4fbf365c05029 ae238b17ad3778f00000000065c05029 0292c9d4592464c812c4fbf365c05029 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintz.f32.f32 d12, d30 487febbbbaad898406fd5785295d2826 e6b2d4c486718511d19776dba83f559c 487febbbbaad8984d19776db80000000 e6b2d4c486718511d19776dba83f559c fpscr=00000000
+vrintz.f32.f32 d12, d30 ab633465f4136cce2d8a6421b9a3ded7 e96d815b4cb2cb10aa825a2542f95443 ab633465f4136cce8000000042f80000 e96d815b4cb2cb10aa825a2542f95443 fpscr=00000000
+vrintz.f32.f32 d12, d30 6c4106fc18a2838adcb80c9cd0328bde 169aa2ddd37c28c4a60806a29698df8f 6c4106fc18a2838a8000000080000000 169aa2ddd37c28c4a60806a29698df8f fpscr=00000000
+vrintz.f32.f32 d12, d30 e7738f4049f8c13002c60d2532bb0849 7254e57d767e8389c1008c9e8d45f748 e7738f4049f8c130c100000080000000 7254e57d767e8389c1008c9e8d45f748 fpscr=00000000
+vrintz.f32.f32 d12, d30 48ffe1365079054172da542f492eaf94 9a1c52f8625eed330e24e7c512d90ccb 48ffe136507905410000000000000000 9a1c52f8625eed330e24e7c512d90ccb fpscr=00000000
+vrintz.f32.f32 d12, d30 e7082983f37e4fa9b04ed1c4c5479f5a 7e1b6cdefebc45ee22589e77406d2d70 e7082983f37e4fa90000000040400000 7e1b6cdefebc45ee22589e77406d2d70 fpscr=00000000
+vrintz.f32.f32 d12, d30 39b56c5f09e1995224d270b3ea54d328 2d8c8fd25ebe4396285a664f1123572a 39b56c5f09e199520000000000000000 2d8c8fd25ebe4396285a664f1123572a fpscr=00000000
+vrintz.f32.f32 d12, d30 9f782af068e0981a21f6fb2ebc5e26b5 1112baa4177fd9fc594d2e7876d716fc 9f782af068e0981a594d2e7876d716fc 1112baa4177fd9fc594d2e7876d716fc fpscr=00000000
+vrintz.f32.f32 d12, d30 12b4d6fdac62582fd90dd3b90da82f78 83dbb6557a5efd00d22c7defcfaa8e63 12b4d6fdac62582fd22c7defcfaa8e63 83dbb6557a5efd00d22c7defcfaa8e63 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintz.f32.f32 d12, d30 b4c23804eda1bbbb297493866e9cfe9b c3b999f02529cd90ca1340a3bf75dc89 b4c23804eda1bbbbca1340a080000000 c3b999f02529cd90ca1340a3bf75dc89 fpscr=00000000
+vrintz.f32.f32 d12, d30 6b3d3856abaf4a2ad703473b8c27f80f fd714b08ad4bff2e1685246deb6f6110 6b3d3856abaf4a2a00000000eb6f6110 fd714b08ad4bff2e1685246deb6f6110 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[3]
+vrintz.f32.f32 d12, d30 d2a0374839ad564a35d74d2720a7ffe5 4d69857fb8a38628b8a38628fefbe188 d2a0374839ad564a80000000fefbe188 4d69857fb8a38628b8a38628fefbe188 fpscr=00000000
+vrintz.f32.f32 d12, d30 faf3796f26b434bb5ab998e667cded6e 0b671fd1ca78ba56e5e09f1c8c0c6cf4 faf3796f26b434bbe5e09f1c80000000 0b671fd1ca78ba56e5e09f1c8c0c6cf4 fpscr=00000000
+vrintz.f32.f32 d12, d30 7a7842986041706469950e12c329a394 4f395273fa9d48f35b806e1c4bb970ca 7a784298604170645b806e1c4bb970ca 4f395273fa9d48f35b806e1c4bb970ca fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintz.f32.f32 d12, d30 822055f9a83c6e2f388127adb1036a47 d884869b8c72ebba2abdbc8cd884869b 822055f9a83c6e2f00000000d884869b d884869b8c72ebba2abdbc8cd884869b fpscr=00000000
+vrintz.f32.f32 d12, d30 a8db7e9f6562b556190e9b1e7819584f 31cecaeaa8613152278bb0e4204575f6 a8db7e9f6562b5560000000000000000 31cecaeaa8613152278bb0e4204575f6 fpscr=00000000
+vrintz.f32.f32 d12, d30 904f09cf3d03a713046348bc5f9a7d62 cef6b465d4faed15262942462948fb80 904f09cf3d03a7130000000000000000 cef6b465d4faed15262942462948fb80 fpscr=00000000
+vrintz.f32.f32 d12, d30 0c9c50ce35dad1045e97e9913fe83537 bbea973f36cc117eef28d10f4686b0cd 0c9c50ce35dad104ef28d10f4686b000 bbea973f36cc117eef28d10f4686b0cd fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[0]
+vrintz.f32.f32 d12, d30 f7b7ea4c0a1a34baadd25764e53ad8b9 961b0383736799f2961b03837c1b0e1d f7b7ea4c0a1a34ba800000007c1b0e1d 961b0383736799f2961b03837c1b0e1d fpscr=00000000
+vrintz.f32.f32 d12, d30 cd7b9c2e92f6aa1eb7e62c38c81b3aab b74146b743f75b2daac28efc115d52d8 cd7b9c2e92f6aa1e8000000000000000 b74146b743f75b2daac28efc115d52d8 fpscr=00000000
+vrintz.f32.f32 d12, d30 cba9ed799ebfaab0864567573347a248 aa4c811a5ce00117c3bf678c24ce8b5c cba9ed799ebfaab0c3bf000000000000 aa4c811a5ce00117c3bf678c24ce8b5c fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintz.f32.f32 d12, d30 c5d235d53764bbff5de193913c4c02b9 b8dccdc09bb15c9a0ee6f20a3b3f0402 c5d235d53764bbff0000000000000000 b8dccdc09bb15c9a0ee6f20a3b3f0402 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintz.f32.f32 d12, d30 710a59916d3c87c465787fe424dbeb42 38b8077073958c7b20f970ecd3ec2e34 710a59916d3c87c400000000d3ec2e34 38b8077073958c7b20f970ecd3ec2e34 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintz.f32.f32 d12, d30 db47f01ba7f72d91eb6eae9af4bfcec6 cc23d5cb76ff0b5bbafb0bae793ed523 db47f01ba7f72d9180000000793ed523 cc23d5cb76ff0b5bbafb0bae793ed523 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintz.f32.f32 d12, d30 b6e0034d1c435f18863622cc1c2ed7fb 520b5cb1eefd0f888308ca468bea1dd8 b6e0034d1c435f188000000080000000 520b5cb1eefd0f888308ca468bea1dd8 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintz.f32.f32 d12, d30 ed1b448fe5348c20ace7c50258a48ddd 44610e0d7958bc37e27d8805ee59c6ef ed1b448fe5348c20e27d8805ee59c6ef 44610e0d7958bc37e27d8805ee59c6ef fpscr=00000000
+vrintz.f32.f32 d12, d30 55c877fd60c4d2184b7003860f9a1704 71d6d9a39ab8f4a1be1235164749b984 55c877fd60c4d218800000004749b900 71d6d9a39ab8f4a1be1235164749b984 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintz.f32.f32 d12, d30 2141a6abcdfdc2893b29d6e4de21137f 29046ebfe5cb043442b02178945a59bc 2141a6abcdfdc28942b0000080000000 29046ebfe5cb043442b02178945a59bc fpscr=00000000
+vrintz.f32.f32 d12, d30 c6f1c7442c3d9fdbc3f44cee1ac95f53 b1f03bca0107740e9bc54b8083ca762a c6f1c7442c3d9fdb8000000080000000 b1f03bca0107740e9bc54b8083ca762a fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[1]
+vrintz.f32.f32 d12, d30 459606746b3537564468a2e6ba37b4fa 29d07d0bb7760fce1ce4d6d6511f04d4 459606746b35375600000000511f04d4 29d07d0bb7760fce1ce4d6d6511f04d4 fpscr=00000000
+vrintz.f32.f32 d12, d30 8e7fa4ccbd6213ec523cc43c73aa816e 1f7e387a70773a5629c2c5641265bf8c 8e7fa4ccbd6213ec0000000000000000 1f7e387a70773a5629c2c5641265bf8c fpscr=00000000
+vrintz.f32.f32 d12, d30 6bf093df66b135f208314cab87458fc7 55325a178ddc1c5e6729966121197098 6bf093df66b135f26729966100000000 55325a178ddc1c5e6729966121197098 fpscr=00000000
+vrintz.f32.f32 d12, d30 739087cdfe095001b71cd6af136a5062 e1bd33ba0bd8789ac749302a2bb4d68e 739087cdfe095001c749300000000000 e1bd33ba0bd8789ac749302a2bb4d68e fpscr=00000000
+vrintz.f32.f32 d12, d30 79d83d01300593357ee92416dea0e7e0 2ce20353f0f238144b82d48aac25553e 79d83d01300593354b82d48a80000000 2ce20353f0f238144b82d48aac25553e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintz.f32.f32 d12, d30 d16cfb9ed77dcfa9d16cfb9e4b6f6f00 67ae2affafb5b2757c5427826ac2f492 d16cfb9ed77dcfa97c5427826ac2f492 67ae2affafb5b2757c5427826ac2f492 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintz.f32.f32 d12, d30 25e867c936fbac53c00c2ea5a3a1546e 2bd43fa3ecbe36a5e524df1aeff065ce 25e867c936fbac53e524df1aeff065ce 2bd43fa3ecbe36a5e524df1aeff065ce fpscr=00000000
+vrintz.f32.f32 d12, d30 303e868c35d59d056222b22517ebedc8 c9579060f47f4dd7aa56c7b44573c4d2 303e868c35d59d05800000004573c000 c9579060f47f4dd7aa56c7b44573c4d2 fpscr=00000000
+vrintz.f32.f32 d12, d30 c82c21aa1847777a18cd882de23a1c7a 5b9554779ec133de47df342756a6daf1 c82c21aa1847777a47df340056a6daf1 5b9554779ec133de47df342756a6daf1 fpscr=00000000
+vrintz.f32.f32 d12, d30 f403d4ef04fd710830ec2211d673483e c4ce9d3cd6ca9a6ef176e96ffbb3c023 f403d4ef04fd7108f176e96ffbb3c023 c4ce9d3cd6ca9a6ef176e96ffbb3c023 fpscr=00000000
+vrintz.f32.f32 d12, d30 5ad02bf69f24bd4a8717208cdb0be72f f74089d9d840c67eadde219ca1d39272 5ad02bf69f24bd4a8000000080000000 f74089d9d840c67eadde219ca1d39272 fpscr=00000000
+vrintz.f32.f32 d12, d30 3a0e47013546a0a8081b0d29b25a9016 035d9ae3c587d36f06873e7ebf32c964 3a0e47013546a0a80000000080000000 035d9ae3c587d36f06873e7ebf32c964 fpscr=00000000
+vrintx.f32.f32 d15, d15 2572239c0a3c4f14a300e11c8ec9236b 18fe0423ba96206e4bf85aab2e03e59d 00000000800000004bf85aab2e03e59d 00000000800000004bf85aab2e03e59d fpscr=00000000
+randV128: 17408 calls, 17995 iters
+vrintx.f32.f32 d15, d15 159b3a1918fb3ba6a4fee90704df4f33 6100dfbbd530a138a7b1b2e468f6fdeb 6100dfbbd530a138a7b1b2e468f6fdeb 6100dfbbd530a138a7b1b2e468f6fdeb fpscr=00000000
+vrintx.f32.f32 d15, d15 de9d8feb1c3fb61f6a460b8e673275b9 c0302da90e730a452558f7dda90e2ea4 c0400000000000002558f7dda90e2ea4 c0400000000000002558f7dda90e2ea4 fpscr=00000000
+vrintx.f32.f32 d15, d15 0b750eec121bf74178b270e17b31f434 74abd2b1f7d6dd498c547c65e9d8e673 74abd2b1f7d6dd498c547c65e9d8e673 74abd2b1f7d6dd498c547c65e9d8e673 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintx.f32.f32 d15, d15 104d59700b668311f1558410f1558410 fd9d8f8d5aa15b7a5a1f1dbf41e6bd02 fd9d8f8d5aa15b7a5a1f1dbf41e6bd02 fd9d8f8d5aa15b7a5a1f1dbf41e6bd02 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintx.f32.f32 d15, d15 df80ddb5e94d5f0df0f46be3624edc2c 083d560aaaf7bbe14c0a30c2e450134c 00000000800000004c0a30c2e450134c 00000000800000004c0a30c2e450134c fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintx.f32.f32 d15, d15 e352a3badba895b4463b0dad2507970e 39451d5a39451d5aaa06b55fb3446e5c 0000000000000000aa06b55fb3446e5c 0000000000000000aa06b55fb3446e5c fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[1]
+vrintx.f32.f32 d15, d15 365617a1365617a178efcf6b673b9c89 03def0ba8c804132583d29c70ece6289 0000000080000000583d29c70ece6289 0000000080000000583d29c70ece6289 fpscr=00000000
+vrintx.f32.f32 d15, d15 6fc315627ecf6c69db86b8c539013255 b14f184809f9a84d6caab2d43cc63de6 80000000000000006caab2d43cc63de6 80000000000000006caab2d43cc63de6 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintx.f32.f32 d15, d15 3ac8a171b17f176f276197d13ac8a171 3d62b97b0251fdef4a1794d6cf985f20 00000000000000004a1794d6cf985f20 00000000000000004a1794d6cf985f20 fpscr=00000000
+vrintx.f32.f32 d15, d15 21a97c49346eeed8cd6ded243468e41c 905c65045fee2ca717699be01b9b04a0 800000005fee2ca717699be01b9b04a0 800000005fee2ca717699be01b9b04a0 fpscr=00000000
+vrintx.f32.f32 d15, d15 3139b52348291f7aff64434eca258490 1705b508ae997ecf1c9a1f4bca6a6c85 00000000800000001c9a1f4bca6a6c85 00000000800000001c9a1f4bca6a6c85 fpscr=00000000
+vrintx.f32.f32 d15, d15 b4503b1e3b1378106bc1686fb1c3990b a921505194caf3bc26eb269955c573c7 800000008000000026eb269955c573c7 800000008000000026eb269955c573c7 fpscr=00000000
+vrintx.f32.f32 d15, d15 cf087c89a727640f187146feed4fb708 7820d01bf2ce0fcd08fcae55d8b33dc1 7820d01bf2ce0fcd08fcae55d8b33dc1 7820d01bf2ce0fcd08fcae55d8b33dc1 fpscr=00000000
+vrintx.f32.f32 d15, d15 50a3a7ba19bec956a4d15f20283581cf f2afed3ceaf82936b19c187454f8c632 f2afed3ceaf82936b19c187454f8c632 f2afed3ceaf82936b19c187454f8c632 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintx.f32.f32 d15, d15 201ab36a2238aca702750f400b2d8d31 1d4d22646abc9560838b6a03d7723622 000000006abc9560838b6a03d7723622 000000006abc9560838b6a03d7723622 fpscr=00000000
+vrintx.f32.f32 d15, d15 54326503ef937f00d24e9d7c4b17adb4 c9ba4e89e7718fb6270771fa2363e66e c9ba4e88e7718fb6270771fa2363e66e c9ba4e88e7718fb6270771fa2363e66e fpscr=00000000
+vrintx.f32.f32 d15, d15 5799cf31d4395e727276350423ecb428 65fa7a4450bc440682c7a3ab38725b45 65fa7a4450bc440682c7a3ab38725b45 65fa7a4450bc440682c7a3ab38725b45 fpscr=00000000
+vrintx.f32.f32 d15, d15 16f04da4c401df6ff060d85994421dbc 48f21c9dc849fe4bcc12f2fb6ef4b84b 48f21ca0c849fe40cc12f2fb6ef4b84b 48f21ca0c849fe40cc12f2fb6ef4b84b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[3]
+vrintx.f32.f32 d15, d15 d62f76d8d62f76d88b7e7fac8806b418 475b17d9bb129fe6dee48729b059a09c 475b180080000000dee48729b059a09c 475b180080000000dee48729b059a09c fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintx.f32.f32 d15, d15 7cee4e29849d14374e670b27849d1437 890169ca782893d3857fa08cef5a72ae 80000000782893d3857fa08cef5a72ae 80000000782893d3857fa08cef5a72ae fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[3]
+vrintx.f32.f32 d15, d15 88630c14becdb19bcc0671d5cc0671d5 3f209c65f72e9c0c0b6b5fa4ea0b42e0 3f800000f72e9c0c0b6b5fa4ea0b42e0 3f800000f72e9c0c0b6b5fa4ea0b42e0 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintx.f32.f32 d15, d15 091e0940e323580496facc51051909aa 7ce1f9570d942d052704abc8100e3f18 7ce1f957000000002704abc8100e3f18 7ce1f957000000002704abc8100e3f18 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[1]
+vrintx.f32.f32 d15, d15 e262da48a3532dbaa9535ddd393feeb2 a5eff80da78f89540ecd7f7ffc915350 80000000800000000ecd7f7ffc915350 80000000800000000ecd7f7ffc915350 fpscr=00000000
+vrintx.f32.f32 d15, d15 b12a44afe3962df2f5425dc95446db86 a199acd4c69765913ca9193e6a2e0ef3 80000000c69766003ca9193e6a2e0ef3 80000000c69766003ca9193e6a2e0ef3 fpscr=00000000
+vrintx.f32.f32 d15, d15 1d6a93519e0cb41e5852c0f9a6bdfeca b10f4093eec1d08e9f5dc200fa598e27 80000000eec1d08e9f5dc200fa598e27 80000000eec1d08e9f5dc200fa598e27 fpscr=00000000
+vrintx.f32.f32 d15, d15 5f37273cbc7b9553f706302a5368688f 86bb443db7c1e2bb3dabc3ec0d7fb29d 80000000800000003dabc3ec0d7fb29d 80000000800000003dabc3ec0d7fb29d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintx.f32.f32 d15, d15 5e14c76b1cf49e0a6c2258bf19f817b3 bce49c5ef6fcd991ef5c51be70b7664d 80000000f6fcd991ef5c51be70b7664d 80000000f6fcd991ef5c51be70b7664d fpscr=00000000
+vrintx.f32.f32 d15, d15 3f6ff9654599112859c7deddeea5ecf1 64f59fd945ea7e6d44ede760a5ac1955 64f59fd945ea800044ede760a5ac1955 64f59fd945ea800044ede760a5ac1955 fpscr=00000000
+vrintx.f32.f32 d15, d15 2ae6e870cb1acefdb63c9895d0ac42f7 d817c1e8b41291a3718b70c4f94b9cc7 d817c1e880000000718b70c4f94b9cc7 d817c1e880000000718b70c4f94b9cc7 fpscr=00000000
+vrintx.f32.f32 d15, d15 5d9af340d61eaa7a5f339d18692e4317 560fac1c70a6e835ce0f297f97c66ad7 560fac1c70a6e835ce0f297f97c66ad7 560fac1c70a6e835ce0f297f97c66ad7 fpscr=00000000
+vrintx.f32.f32 d15, d15 fb4b056a83c345ec11a3fb355c9ac596 90151a18bb81e2e65e1b12a9904c46cc 80000000800000005e1b12a9904c46cc 80000000800000005e1b12a9904c46cc fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintx.f32.f32 d15, d15 2ac9ea558bf5afe51ef51c573a533c81 f3bc90faa6f2e900e540594e84d720a5 f3bc90fa80000000e540594e84d720a5 f3bc90fa80000000e540594e84d720a5 fpscr=00000000
+vrintx.f32.f32 d15, d15 abf3b3c039f2888f09933aacd546340e 99c2bdab5798d710dc020ea5cfe1175a 800000005798d710dc020ea5cfe1175a 800000005798d710dc020ea5cfe1175a fpscr=00000000
+vrintx.f32.f32 d15, d15 43858907228f75f4a168b38c47821b7f 2ca3656889435cf35319898c067feafa 00000000800000005319898c067feafa 00000000800000005319898c067feafa fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintx.f32.f32 d15, d15 960357d97813eabf060cf4fe706285b1 a95cb910bac36ef6d60915119e597746 8000000080000000d60915119e597746 8000000080000000d60915119e597746 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintx.f32.f32 d15, d15 6418b781a19da43b1f7bdea1dfbdb64c da493a28da493a285b00746d2faf5f74 da493a28da493a285b00746d2faf5f74 da493a28da493a285b00746d2faf5f74 fpscr=00000000
+vrintx.f32.f32 d15, d15 d2380287f306e2554da09386faca0b70 70215759009514c0e046917b71c4d074 7021575900000000e046917b71c4d074 7021575900000000e046917b71c4d074 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintx.f32.f32 d15, d15 13892820e6e7e15822a9b59b2b184d68 71b1ecedc6946c42215eb2b3d8504f04 71b1ecedc6946c00215eb2b3d8504f04 71b1ecedc6946c00215eb2b3d8504f04 fpscr=00000000
+vrintx.f32.f32 d15, d15 43a2c85423bcbadacd049b616a819d29 9250ec96850800ed3f7549c0c32d530b 80000000800000003f7549c0c32d530b 80000000800000003f7549c0c32d530b fpscr=00000000
+vrintx.f32.f32 d15, d15 7a74fb4bcf1e0d80396f19a5c2bd5186 2e5a6c35a2e2d7fd06729b780325db06 000000008000000006729b780325db06 000000008000000006729b780325db06 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintx.f32.f32 d15, d15 8a658e088a658e08b72b7fb3a5568fc8 2310b1ca4e97571104503ea98caa058b 000000004e97571104503ea98caa058b 000000004e97571104503ea98caa058b fpscr=00000000
+vrintx.f32.f32 d15, d15 fc64b275fd5d7fa85d1cbc0625395cab bb92864cbc9d9e4df274db4304074703 8000000080000000f274db4304074703 8000000080000000f274db4304074703 fpscr=00000000
+vrintx.f32.f32 d15, d15 b99e53d454014873b6b3e8a42f3f7037 0c4057f68a9a7e94b83193ef7ca39a4f 0000000080000000b83193ef7ca39a4f 0000000080000000b83193ef7ca39a4f fpscr=00000000
+vrintx.f32.f32 d15, d15 847496bcc621f62711bdacfe3ffafa2d cd87fb36f84321b5fa1f0d02f92d7212 cd87fb36f84321b5fa1f0d02f92d7212 cd87fb36f84321b5fa1f0d02f92d7212 fpscr=00000000
+vrintx.f32.f32 d15, d15 f01915c1754977348fb14ec393783ef4 5ee343124f0cb934a59aef01ec8213f7 5ee343124f0cb934a59aef01ec8213f7 5ee343124f0cb934a59aef01ec8213f7 fpscr=00000000
+vrintx.f32.f32 d15, d15 2270d3c5da69593dd8f85293732dba8a 23fba9d35ad6588d8f1acb85f2a4a23a 000000005ad6588d8f1acb85f2a4a23a 000000005ad6588d8f1acb85f2a4a23a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[3]
+vrintx.f32.f32 d15, d15 c11abfd65f03f4124c423c1e0d6387bb f2e9ee80cc0e95ddf2e9ee806d120f88 f2e9ee80cc0e95ddf2e9ee806d120f88 f2e9ee80cc0e95ddf2e9ee806d120f88 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintx.f32.f32 d15, d15 e5067be54bc853669eea5236e5067be5 2a24d9f71c74412dd987626139d63be3 0000000000000000d987626139d63be3 0000000000000000d987626139d63be3 fpscr=00000000
+vrintx.f32.f32 d15, d15 3a2c7f2694ddb00cd6fa4c76ec1d4f82 08b00623ca5631ffab5f1282f3af061a 00000000ca563200ab5f1282f3af061a 00000000ca563200ab5f1282f3af061a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintn.f32.f32 q0, q2 bf6945adbf6945add7f8bc634a337222 1e297ed2c37a942bc560f2cdc06afaeb 00000000c37b0000c560f000c0800000 1e297ed2c37a942bc560f2cdc06afaeb fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintn.f32.f32 q0, q2 949a44bfc39d5de8949a44bf3d17c6d0 25361d780affd60c88f0a03af6d1feaf 000000000000000080000000f6d1feaf 25361d780affd60c88f0a03af6d1feaf fpscr=00000000
+vrintn.f32.f32 q0, q2 56d36232125133fd008ac0b640c230ad f9848c1293bcc27535330d2fff6b0c67 f9848c128000000000000000ff6b0c67 f9848c1293bcc27535330d2fff6b0c67 fpscr=00000000
+vrintn.f32.f32 q0, q2 faa1ba396af5a50258853b400faabfa2 693aa3c38c1293b7aa83ece33c612b6f 693aa3c3800000008000000000000000 693aa3c38c1293b7aa83ece33c612b6f fpscr=00000000
+vrintn.f32.f32 q0, q2 ea122994fe4092096c42d76366e7fdc5 57b71d6688a2c86c57e77ee44aea7c22 57b71d668000000057e77ee44aea7c22 57b71d6688a2c86c57e77ee44aea7c22 fpscr=00000000
+vrintn.f32.f32 q0, q2 5153935a2da0bf71d6ca4f77bc9b5835 3e1459aec5e0c8124cb60f1238622df8 00000000c5e0c8004cb60f1200000000 3e1459aec5e0c8124cb60f1238622df8 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[1]
+vrintn.f32.f32 q0, q2 e38053a5194f9531e38053a5e21d5265 184be1cae1e1fd5b8264267b8264267b 00000000e1e1fd5b8000000080000000 184be1cae1e1fd5b8264267b8264267b fpscr=00000000
+vrintn.f32.f32 q0, q2 e8be44426382d5c0cb57561fa1518963 d46a408cdeb9beea1162ec0cdd3ae823 d46a408cdeb9beea00000000dd3ae823 d46a408cdeb9beea1162ec0cdd3ae823 fpscr=00000000
+vrintn.f32.f32 q0, q2 116d4b4088c98a35bd6eb326799260a3 1e57292d128dbed59c0c5ebe701912d7 000000000000000080000000701912d7 1e57292d128dbed59c0c5ebe701912d7 fpscr=00000000
+vrintn.f32.f32 q0, q2 4e35a27f41ef3dbabab4c34c42fc0e23 d0746f70f3848da05b9ad4ab7864d828 d0746f70f3848da05b9ad4ab7864d828 d0746f70f3848da05b9ad4ab7864d828 fpscr=00000000
+vrintn.f32.f32 q0, q2 200b873a6233cc012a4f58a6de5e5068 42d1523191180dabe2613118133e5962 42d2000080000000e261311800000000 42d1523191180dabe2613118133e5962 fpscr=00000000
+vrintn.f32.f32 q0, q2 5afd90b155f8822ddd4f74c8a7f078aa 8f50e46057e9789f145f02d70fc90269 8000000057e9789f0000000000000000 8f50e46057e9789f145f02d70fc90269 fpscr=00000000
+vrintn.f32.f32 q0, q2 a1fbc8469a04ae72f2ad2b332efe84d8 225a99d80b037aae48ad73f77c44450f 000000000000000048ad74007c44450f 225a99d80b037aae48ad73f77c44450f fpscr=00000000
+vrintn.f32.f32 q0, q2 a93733b7cb7d15e6dccd9dd723bf6667 4f8ad4233972e48319322a8375ffa319 4f8ad423000000000000000075ffa319 4f8ad4233972e48319322a8375ffa319 fpscr=00000000
+vrintn.f32.f32 q0, q2 bd66e57d6c3723f225e72f6002b83b3f 12de08997b706f99f7b4ef3417bb55c0 000000007b706f99f7b4ef3400000000 12de08997b706f99f7b4ef3417bb55c0 fpscr=00000000
+randV128: 17664 calls, 18256 iters
+vrintn.f32.f32 q0, q2 7e5a45ffc81f3bd66fa6be9d9199f712 5f9d9b1c73774414c40dd072bcfe1acb 5f9d9b1c73774414c40dc00080000000 5f9d9b1c73774414c40dd072bcfe1acb fpscr=00000000
+vrintn.f32.f32 q0, q2 df2b2eb41c2de085c735ad328a415890 5e0419ba46ea2dfddded63bf487762bd 5e0419ba46ea2e00dded63bf487762c0 5e0419ba46ea2dfddded63bf487762bd fpscr=00000000
+vrintn.f32.f32 q0, q2 01b5431284355983023117af6ff8a2d1 b731444dc63fee7af0293828aa89a21e 80000000c63ff000f029382880000000 b731444dc63fee7af0293828aa89a21e fpscr=00000000
+vrintn.f32.f32 q0, q2 70be42e7e0d8082be8df9d107187a179 3f9880babd542538a1d25b2b8f0a0efe 3f800000800000008000000080000000 3f9880babd542538a1d25b2b8f0a0efe fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintn.f32.f32 q0, q2 ec8fde2b0298897e75a96be00298897e 4672b20c7e0c5df544d275452d1ad01d 4672b4007e0c5df544d2800000000000 4672b20c7e0c5df544d275452d1ad01d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintn.f32.f32 q0, q2 52337f81de30309a289fa00e566e1f09 a54b7ebe77b7edf757684af49c47be64 8000000077b7edf757684af480000000 a54b7ebe77b7edf757684af49c47be64 fpscr=00000000
+vrintn.f32.f32 q0, q2 f769777a103141aa58f9a0f135113c0b 4453ff622958df3e4df4d8e4f7bb14e6 44540000000000004df4d8e4f7bb14e6 4453ff622958df3e4df4d8e4f7bb14e6 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintn.f32.f32 q0, q2 d558e539d558e5394e5c58a0c7994b59 34407d91cbb1466634f2e4332dadbf4b 00000000cbb146660000000000000000 34407d91cbb1466634f2e4332dadbf4b fpscr=00000000
+vrintn.f32.f32 q0, q2 18f908d78d32e1651bcbf4eb106ddcc5 1d9ec32cf41033f153599e4fa3572fdf 00000000f41033f153599e4f80000000 1d9ec32cf41033f153599e4fa3572fdf fpscr=00000000
+vrintn.f32.f32 q0, q2 c1070d6dfabae886504193834cf86720 7e2d3403d2e9bde814a0a12f0473e9f8 7e2d3403d2e9bde80000000000000000 7e2d3403d2e9bde814a0a12f0473e9f8 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintn.f32.f32 q0, q2 e18540dc10cb9db93261cd5cbc91ca12 c2459f4e40b0fb6edc02f56040b0fb6e c244000040c00000dc02f56040c00000 c2459f4e40b0fb6edc02f56040b0fb6e fpscr=00000000
+vrintn.f32.f32 q0, q2 cacb75f28427c56281d5096524dc6fa2 b0e4ce143a7583c22f9d51e9aef0e654 80000000000000000000000080000000 b0e4ce143a7583c22f9d51e9aef0e654 fpscr=00000000
+vrintn.f32.f32 q0, q2 cd559371229f057097feddcf34363162 e94de78fb9aa3a96d7fb371dfd806f9c e94de78f80000000d7fb371dfd806f9c e94de78fb9aa3a96d7fb371dfd806f9c fpscr=00000000
+vrintn.f32.f32 q0, q2 cd56470a27a80cbce8d2f0cdeb0e52e6 6fdead8b87417a5a50575b2cebbafc0d 6fdead8b8000000050575b2cebbafc0d 6fdead8b87417a5a50575b2cebbafc0d fpscr=00000000
+vrintn.f32.f32 q0, q2 9231733f6668cabadd409fdcfcc4186a 6e3d32ddb7f440b7898a2a76d4ca93b6 6e3d32dd8000000080000000d4ca93b6 6e3d32ddb7f440b7898a2a76d4ca93b6 fpscr=00000000
+vrintn.f32.f32 q0, q2 e54113f963372e7129040594d17d2c31 4d0a55aedea7121199adb6534d0857c4 4d0a55aedea71211800000004d0857c4 4d0a55aedea7121199adb6534d0857c4 fpscr=00000000
+vrintn.f32.f32 q0, q2 9a5f242586c625b40d6d2085f78bd8fb 206bcddd2718a6007de2fbb375e96f3f 00000000000000007de2fbb375e96f3f 206bcddd2718a6007de2fbb375e96f3f fpscr=00000000
+vrintn.f32.f32 q0, q2 88c95aa022a576b18e81ca65703328db 7c7b8f3bcb6ae9af2505869dacce4da3 7c7b8f3bcb6ae9af0000000080000000 7c7b8f3bcb6ae9af2505869dacce4da3 fpscr=00000000
+vrintn.f32.f32 q0, q2 4b67c198692686ef7e869aabddd3e36e b2998ea6e798631df237788aaab05466 80000000e798631df237788a80000000 b2998ea6e798631df237788aaab05466 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintn.f32.f32 q0, q2 fb703b3738a9ed9f9064707290647072 82d2c0c46093e90cb2be01388451f2a7 800000006093e90c8000000080000000 82d2c0c46093e90cb2be01388451f2a7 fpscr=00000000
+vrintn.f32.f32 q0, q2 849bba31b775dfc2c53bfc5477740620 6c30bfd66db76c48104736dbf92bd5f0 6c30bfd66db76c4800000000f92bd5f0 6c30bfd66db76c48104736dbf92bd5f0 fpscr=00000000
+vrintn.f32.f32 q0, q2 c269aed212bf340a2aa11816ed148980 39a6655557c078dd8b0085af7cd2ea2e 0000000057c078dd800000007cd2ea2e 39a6655557c078dd8b0085af7cd2ea2e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintn.f32.f32 q0, q2 621d5243621d5243dbbdf6deeac3db70 7db65cf59764f0a34995ab0264e43d8f 7db65cf5800000004995ab0064e43d8f 7db65cf59764f0a34995ab0264e43d8f fpscr=00000000
+vrintn.f32.f32 q0, q2 cae3427ca10ded05df3cea52bc65bff6 b6c9c575616b723f9803a78185d3c9d8 80000000616b723f8000000080000000 b6c9c575616b723f9803a78185d3c9d8 fpscr=00000000
+vrintn.f32.f32 q0, q2 ef10205371dbfa1aedf23d2cfe613b67 b477b8815a53f2e9a9db7d78787dbd1f 800000005a53f2e980000000787dbd1f b477b8815a53f2e9a9db7d78787dbd1f fpscr=00000000
+vrintn.f32.f32 q0, q2 b3925f86c9e1bc16b88797a49b14e339 84f900c86ea439dca8346a3ab5e4dd7f 800000006ea439dc8000000080000000 84f900c86ea439dca8346a3ab5e4dd7f fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[3]
+vrintn.f32.f32 q0, q2 ccda5da0a8598fcb85683e6d7ab6378c 7a00fe9d90b587f03ca4a99d5dda9f95 7a00fe9d80000000000000005dda9f95 7a00fe9d90b587f03ca4a99d5dda9f95 fpscr=00000000
+vrintn.f32.f32 q0, q2 4ea2fe8a4a3f0c0a808b8eb0aaa1875e 1999e5fdac476e52a8561b355cbf2e25 0000000080000000800000005cbf2e25 1999e5fdac476e52a8561b355cbf2e25 fpscr=00000000
+vrintn.f32.f32 q0, q2 3531fd63e1252c1c00e5d990b97c8aa6 bb33aaf6e0fa4b39700eb40aa9bba013 80000000e0fa4b39700eb40a80000000 bb33aaf6e0fa4b39700eb40aa9bba013 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintn.f32.f32 q0, q2 4c6295b8e063f26513a852cb1f3fd716 7f62fc3128da330a7c93aa448a57264c 7f62fc31000000007c93aa4480000000 7f62fc3128da330a7c93aa448a57264c fpscr=00000000
+vrintn.f32.f32 q0, q2 80da81a279b368401cbc20a36762440d 8a0034a62f366980ddffa62f42f5cbc4 8000000000000000ddffa62f42f60000 8a0034a62f366980ddffa62f42f5cbc4 fpscr=00000000
+vrintn.f32.f32 q0, q2 16afebd24d3fec09f07b6f1b077b56d3 3a24c1bf84d70271fcb68221b20b1691 0000000080000000fcb6822180000000 3a24c1bf84d70271fcb68221b20b1691 fpscr=00000000
+vrintn.f32.f32 q0, q2 b2586175cd066a5c099bf93b119cc2d4 d9467fc5d4d848d30e77fef50b39aca6 d9467fc5d4d848d30000000000000000 d9467fc5d4d848d30e77fef50b39aca6 fpscr=00000000
+vrintn.f32.f32 q0, q2 1fc56ebc564cfe597bb1a15e16cc0718 1ce57b9e20f0e2850ddadb360a3f0892 00000000000000000000000000000000 1ce57b9e20f0e2850ddadb360a3f0892 fpscr=00000000
+vrintn.f32.f32 q0, q2 bf4391d1fd340b91f5ce108ac48b5a49 83b44ea230a85234cc3fea1f38446633 8000000000000000cc3fea1f00000000 83b44ea230a85234cc3fea1f38446633 fpscr=00000000
+vrinta.f32.f32 q3, q5 e55f7dfd60db0b5b01c3d13cbf2fa615 1266af0b6a50fbe023fa6fbf0c80d5a0 000000006a50fbe00000000000000000 1266af0b6a50fbe023fa6fbf0c80d5a0 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrinta.f32.f32 q3, q5 ebfec532eb33e2410de67479eb33e241 3a86e50c09b0ca418df8ee522424a1ef 00000000000000008000000000000000 3a86e50c09b0ca418df8ee522424a1ef fpscr=00000000
+vrinta.f32.f32 q3, q5 90202eea830bd494e243ef8527c0cdba 0ded32a6a943e67df269d2731b38b470 0000000080000000f269d27300000000 0ded32a6a943e67df269d2731b38b470 fpscr=00000000
+vrinta.f32.f32 q3, q5 86e1c495f258fd7f79491e9cc5867d93 65d26957470d334166584a910ba6cee1 65d26957470d330066584a9100000000 65d26957470d334166584a910ba6cee1 fpscr=00000000
+vrinta.f32.f32 q3, q5 c5a0ecea4056ae0bac28bd09115212fb 92247d50ae577afead1cc4a45127f0a7 8000000080000000800000005127f0a7 92247d50ae577afead1cc4a45127f0a7 fpscr=00000000
+vrinta.f32.f32 q3, q5 d01516c25937ac1de0c22af31f7ac72f 3271cc824ff7f103c3b7f8238aa0d91a 000000004ff7f103c3b8000080000000 3271cc824ff7f103c3b7f8238aa0d91a fpscr=00000000
+vrinta.f32.f32 q3, q5 4c52dc9e95644e65a885671fdc725897 d8eb2e394da30e846e5c2ddd18e9e87c d8eb2e394da30e846e5c2ddd00000000 d8eb2e394da30e846e5c2ddd18e9e87c fpscr=00000000
+vrinta.f32.f32 q3, q5 fc95acbd7b72c8bb60a5e1815f6f90b4 455bed46968eb7ca01125a5861e09d1b 455bf000800000000000000061e09d1b 455bed46968eb7ca01125a5861e09d1b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrinta.f32.f32 q3, q5 64a09e69d26093500f99bdf81137af78 f49f63d20d24ef660d24ef66ae9f10e0 f49f63d2000000000000000080000000 f49f63d20d24ef660d24ef66ae9f10e0 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[3]
+vrinta.f32.f32 q3, q5 ceb32b8efa3dc796110ae728110ae728 83523496f373dd2cc66d357fdac68594 80000000f373dd2cc66d3400dac68594 83523496f373dd2cc66d357fdac68594 fpscr=00000000
+vrinta.f32.f32 q3, q5 0222d095d2c30a73d115c6375e41e4b4 caa8f2573d115022c5331ac241985004 caa8f25800000000c533200041980000 caa8f2573d115022c5331ac241985004 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[1]
+vrinta.f32.f32 q3, q5 b28dadb2bd1b3ef578ee2808bd1b3ef5 67b24f2db35da93a5a7354415a735441 67b24f2d800000005a7354415a735441 67b24f2db35da93a5a7354415a735441 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrinta.f32.f32 q3, q5 635557fea45b96bc3603e6eeb8cabbc8 d849f92f6df06ceca8319df6c8382fa8 d849f92f6df06cec80000000c8382fc0 d849f92f6df06ceca8319df6c8382fa8 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrinta.f32.f32 q3, q5 50572d3d51128721511287219f170dd9 d81963f4ba8478c85982b98afd09b61f d81963f4800000005982b98afd09b61f d81963f4ba8478c85982b98afd09b61f fpscr=00000000
+vrinta.f32.f32 q3, q5 8985fae5b18c9b419db396224096b2a8 e44618e6f010410ba6897b533f275ca3 e44618e6f010410b800000003f800000 e44618e6f010410ba6897b533f275ca3 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrinta.f32.f32 q3, q5 98c0d983cfb8dca071eb3866e771d67e df6e8e7afb95368909003e8c44c17e71 df6e8e7afb9536890000000044c18000 df6e8e7afb95368909003e8c44c17e71 fpscr=00000000
+vrinta.f32.f32 q3, q5 62512c024838d5768b6182b836c68c38 c12e09b044d1748e05513f60f2dd7f3c c130000044d1800000000000f2dd7f3c c12e09b044d1748e05513f60f2dd7f3c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[3]
+vrinta.f32.f32 q3, q5 b12bf3350e472ebd4810481a4810481a 0336aed70336aed74a880aa6679bf241 00000000000000004a880aa6679bf241 0336aed70336aed74a880aa6679bf241 fpscr=00000000
+vrinta.f32.f32 q3, q5 6c4f49a9dca2dcf04a70ff18f7faef18 d8445e95e24a298ccea878073e39feb8 d8445e95e24a298ccea8780700000000 d8445e95e24a298ccea878073e39feb8 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrinta.f32.f32 q3, q5 8bed8f8ae9553513dae94025a2759965 bf70ee2fd66f39e32e3145fdf16cc143 bf800000d66f39e300000000f16cc143 bf70ee2fd66f39e32e3145fdf16cc143 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrinta.f32.f32 q3, q5 188dcaf6f508dd4aa877ab8d4aeff90b 32a9318d3b0e03018537ba19c5c09c06 000000000000000080000000c5c0a000 32a9318d3b0e03018537ba19c5c09c06 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vrinta.f32.f32 q3, q5 d5ed875b5950ff955950ff95ebe421f5 ddc5d70914ab490fee4e37e814ab490f ddc5d70900000000ee4e37e800000000 ddc5d70914ab490fee4e37e814ab490f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrinta.f32.f32 q3, q5 2ae659f86194911a6cdf26a92ae659f8 bbede7d77ee142befcbcda23e6705e48 800000007ee142befcbcda23e6705e48 bbede7d77ee142befcbcda23e6705e48 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vrinta.f32.f32 q3, q5 b04a659190296ff5bd74a971f3466260 5f49645b72b8042ac6ed98975f49645b 5f49645b72b8042ac6ed98005f49645b 5f49645b72b8042ac6ed98975f49645b fpscr=00000000
+vrinta.f32.f32 q3, q5 ad5f1817379f0f305a37cdd6156fab2c 974680a9068f0d611f84b1734372f6f5 80000000000000000000000043730000 974680a9068f0d611f84b1734372f6f5 fpscr=00000000
+vrinta.f32.f32 q3, q5 b92a73ee46e2eb82dd672668e8a5e995 eebc00091dbc00ac0636b818cfef8098 eebc00090000000000000000cfef8098 eebc00091dbc00ac0636b818cfef8098 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrinta.f32.f32 q3, q5 7eb1ae68b45aa237065c12a5fb8113a3 be53eac3129f36a889d0cebb554e8dde 800000000000000080000000554e8dde be53eac3129f36a889d0cebb554e8dde fpscr=00000000
+vrinta.f32.f32 q3, q5 b654b6e992dc0fa5933f44e664aecd2c 037442853f722e90864f7210a1113964 000000003f8000008000000080000000 037442853f722e90864f7210a1113964 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrinta.f32.f32 q3, q5 249056d67d62502e13f884bb281a492f 0882c6fee88193c6e54a90289b436ced 00000000e88193c6e54a902880000000 0882c6fee88193c6e54a90289b436ced fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: 17920 calls, 18522 iters
+vrinta.f32.f32 q3, q5 0843fb8b7f631793c1eb87d0f0e0fabc ebe28c3595f1ec103f04d28a95f1ec10 ebe28c35800000003f80000080000000 ebe28c3595f1ec103f04d28a95f1ec10 fpscr=00000000
+vrinta.f32.f32 q3, q5 ad67a6ab42f28ca7e9b6e3b46edac8ac b16157c8fe13b9ba6b95ef7ce243a229 80000000fe13b9ba6b95ef7ce243a229 b16157c8fe13b9ba6b95ef7ce243a229 fpscr=00000000
+vrinta.f32.f32 q3, q5 e592cfc247c07e323d19b51dd27b4fc1 8c5f46a3be64e87cf6dc40707567d11d 8000000080000000f6dc40707567d11d 8c5f46a3be64e87cf6dc40707567d11d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[3]
+vrinta.f32.f32 q3, q5 8d065dcb6c6fd76637ff5be16c6fd766 7b75e0df0629251a24862035b8edae45 7b75e0df000000000000000080000000 7b75e0df0629251a24862035b8edae45 fpscr=00000000
+vrinta.f32.f32 q3, q5 b527f9842ff5f683e5ed1e2cb89820a8 617dd01682ee9791a5ef50bc6b9227e3 617dd01680000000800000006b9227e3 617dd01682ee9791a5ef50bc6b9227e3 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrinta.f32.f32 q3, q5 f5b546f5c3fbd390f7ad6463cc8a0567 ccc66351be81d8b7be81d8b7a2040299 ccc66351800000008000000080000000 ccc66351be81d8b7be81d8b7a2040299 fpscr=00000000
+vrinta.f32.f32 q3, q5 04136b0e428c6ae1f237b2608d1ee3a4 8b23de8eb07f7f1c2773a08341355ffc 80000000800000000000000041300000 8b23de8eb07f7f1c2773a08341355ffc fpscr=00000000
+vrinta.f32.f32 q3, q5 22b174ac54310cdc6db04462bacc8e8b a1db82b79b6d4a4cdac27a6d38890c89 8000000080000000dac27a6d00000000 a1db82b79b6d4a4cdac27a6d38890c89 fpscr=00000000
+vrinta.f32.f32 q3, q5 f4e2f5b1dd8ebc4e4dde464d7b44e018 5dfd0e47fb61d63295367dbc1f3f9d19 5dfd0e47fb61d6328000000000000000 5dfd0e47fb61d63295367dbc1f3f9d19 fpscr=00000000
+vrinta.f32.f32 q3, q5 57c781c113012677c6d833c14ef87941 22fa1e0ba6d04319cc6d4d7457e1563c 0000000080000000cc6d4d7457e1563c 22fa1e0ba6d04319cc6d4d7457e1563c fpscr=00000000
+vrinta.f32.f32 q3, q5 cbb42f7969da04f9464b7d1b3e6d3ae5 304137ec5e42dd75d48fda28f45fc8dd 000000005e42dd75d48fda28f45fc8dd 304137ec5e42dd75d48fda28f45fc8dd fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrinta.f32.f32 q3, q5 9828ceb65679f24ed6b403feee9e597f 4fde45a2a19bb833cd3c1cf1c79bb3d4 4fde45a280000000cd3c1cf1c79bb400 4fde45a2a19bb833cd3c1cf1c79bb3d4 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrinta.f32.f32 q3, q5 1dda5f85f8cf55be2c7373ceb7c34f49 2455825ebefd30e113ace71f9588b2e7 00000000800000000000000080000000 2455825ebefd30e113ace71f9588b2e7 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrinta.f32.f32 q3, q5 5d751f25c3f7ff715d751f25cafc6f24 2c396edef18b375060e893b1cc4f0afd 00000000f18b375060e893b1cc4f0afd 2c396edef18b375060e893b1cc4f0afd fpscr=00000000
+vrinta.f32.f32 q3, q5 f2d1df02f90cb4c52cb9eb74b9d3ade7 98ce7f030c6ae196049823b51f0b0759 80000000000000000000000000000000 98ce7f030c6ae196049823b51f0b0759 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrinta.f32.f32 q3, q5 9e3f369fc8e6697c6e4204e68fcf3d7b 614f56b625739641ba26243f25739641 614f56b6000000008000000000000000 614f56b625739641ba26243f25739641 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrinta.f32.f32 q3, q5 b9843c2648a3819a2823afa879cb9610 8da9c06eb4a3cb38b4a3cb38727e964f 800000008000000080000000727e964f 8da9c06eb4a3cb38b4a3cb38727e964f fpscr=00000000
+vrinta.f32.f32 q3, q5 c8554268572eb2db2d7cb115310af707 255e7ca132d9c0cc52bc0229e71655f6 000000000000000052bc0229e71655f6 255e7ca132d9c0cc52bc0229e71655f6 fpscr=00000000
+vrinta.f32.f32 q3, q5 24138e0db6bd59fe422c5d963bef7f41 b380a1ca6ba7770fa02e8a994a59f23b 800000006ba7770f800000004a59f23c b380a1ca6ba7770fa02e8a994a59f23b fpscr=00000000
+vrinta.f32.f32 q3, q5 ce6096074331994c52476eaad4eef0ba c9df25f0fcdbcad14e74cd929d80d0e5 c9df25f0fcdbcad14e74cd9280000000 c9df25f0fcdbcad14e74cd929d80d0e5 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrinta.f32.f32 q3, q5 3172103df9d2e04ed5907710f9d2e04e dfba52098b114ec2ebeeb001eb43ae26 dfba520980000000ebeeb001eb43ae26 dfba52098b114ec2ebeeb001eb43ae26 fpscr=00000000
+vrintp.f32.f32 q6, q8 5fa2884d916ceb3f4b4bec15270dae51 f6580922bf09cdd58e1b26b8cc779146 f65809228000000080000000cc779146 f6580922bf09cdd58e1b26b8cc779146 fpscr=00000000
+vrintp.f32.f32 q6, q8 0161e59cf0758c58756c2cecdebb8338 06c8ecb21af96b2e6f7c8f8a2fb66468 3f8000003f8000006f7c8f8a3f800000 06c8ecb21af96b2e6f7c8f8a2fb66468 fpscr=00000000
+vrintp.f32.f32 q6, q8 bed1e9d2f92b0713d26ba53f6c19f36e 8ed37f32b7fe83a0d8a18947d43a163e 8000000080000000d8a18947d43a163e 8ed37f32b7fe83a0d8a18947d43a163e fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintp.f32.f32 q6, q8 22c3d15c11cd1bc23f4d8c2be4e4b362 1848b395e68c5e2ba7bb8b689032c24c 3f800000e68c5e2b8000000080000000 1848b395e68c5e2ba7bb8b689032c24c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintp.f32.f32 q6, q8 eca38a771f3b13f523a890b9de7ab329 9bc6a302038cea3f36628529c5ae38dd 800000003f8000003f800000c5ae3800 9bc6a302038cea3f36628529c5ae38dd fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintp.f32.f32 q6, q8 8a1398c945700a708a079ffdee0c1442 db6b2e0ce781c176d59f29726858b545 db6b2e0ce781c176d59f29726858b545 db6b2e0ce781c176d59f29726858b545 fpscr=00000000
+vrintp.f32.f32 q6, q8 dcf272931f168fa8ccbbd40ca35713d2 ec3cd0f8d001ff6cd42dd8bb91197a7c ec3cd0f8d001ff6cd42dd8bb80000000 ec3cd0f8d001ff6cd42dd8bb91197a7c fpscr=00000000
+vrintp.f32.f32 q6, q8 8ff2794eace96f2dd0c718e5296d6899 b929c608056069f0c9b2e1a9ba6f6134 800000003f800000c9b2e1a880000000 b929c608056069f0c9b2e1a9ba6f6134 fpscr=00000000
+vrintp.f32.f32 q6, q8 b1e3caacb79b760ec0ad2de53840052a 0c3aa35be42a73f848c0a7e1f793e202 3f800000e42a73f848c0a800f793e202 0c3aa35be42a73f848c0a7e1f793e202 fpscr=00000000
+vrintp.f32.f32 q6, q8 836156c4d5bc5eb873d753c1fa9c8d1a e225aaad50f1fa51f1350a7f183ee8ad e225aaad50f1fa51f1350a7f3f800000 e225aaad50f1fa51f1350a7f183ee8ad fpscr=00000000
+vrintp.f32.f32 q6, q8 b88e337361be87a7b94fd0eda106f0c8 298ff997870a96a78a61e15e402bed7f 3f800000800000008000000040400000 298ff997870a96a78a61e15e402bed7f fpscr=00000000
+vrintp.f32.f32 q6, q8 ec79d6d80ff952820f5a734b3ff900ab 1cf8744c20981b609a3718151d6ab960 3f8000003f800000800000003f800000 1cf8744c20981b609a3718151d6ab960 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintp.f32.f32 q6, q8 ebe13821581066892488eb466b95fb0d 5c563adb5d7a845d5c563adb7a8991d8 5c563adb5d7a845d5c563adb7a8991d8 5c563adb5d7a845d5c563adb7a8991d8 fpscr=00000000
+vrintp.f32.f32 q6, q8 e888e360cdc7c5bac7734f110d46d59b 042011d75775de1a359516fe573d3aaa 3f8000005775de1a3f800000573d3aaa 042011d75775de1a359516fe573d3aaa fpscr=00000000
+vrintp.f32.f32 q6, q8 cd1c72ed662224e6d79fd9a3eb87b0dc fc1f483eb23ebe1da197d3d749c1aa66 fc1f483e800000008000000049c1aa68 fc1f483eb23ebe1da197d3d749c1aa66 fpscr=00000000
+vrintp.f32.f32 q6, q8 9c7690c4ed618f4137ab2c82d54f05fc 6104e2858b1605eb54e671a15a6537a4 6104e2858000000054e671a15a6537a4 6104e2858b1605eb54e671a15a6537a4 fpscr=00000000
+vrintp.f32.f32 q6, q8 3845bc0f37f27d2655341ec54af78944 171f66d191f9b367f64db595f3575366 3f80000080000000f64db595f3575366 171f66d191f9b367f64db595f3575366 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintp.f32.f32 q6, q8 b6c4e4131038eaeeed872ac1b95bf2ac 1bdc83bdedf0f530fdcf94673c8fd0b7 3f800000edf0f530fdcf94673f800000 1bdc83bdedf0f530fdcf94673c8fd0b7 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintp.f32.f32 q6, q8 bc33f0d4ce303f7501979f16ce303f75 d3f72e45075f7bd2eea1d9eaf1f691ff d3f72e453f800000eea1d9eaf1f691ff d3f72e45075f7bd2eea1d9eaf1f691ff fpscr=00000000
+vrintp.f32.f32 q6, q8 e5e4ac278b972270639f69c7743199ac b55c99fdb47bf6700edcbe3cbc2d541c 80000000800000003f80000080000000 b55c99fdb47bf6700edcbe3cbc2d541c fpscr=00000000
+vrintp.f32.f32 q6, q8 c56cd21be9c6588a4885612b1f7dc162 7a27338dd055a900c917184bcbb98c10 7a27338dd055a900c9171840cbb98c10 7a27338dd055a900c917184bcbb98c10 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintp.f32.f32 q6, q8 c8016d98c8016d9863176249e5b4d743 999619d588cb09a422285edba1b8f22a 80000000800000003f80000080000000 999619d588cb09a422285edba1b8f22a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintp.f32.f32 q6, q8 870e15e593e71848773796f24c2db1b7 9ba4fe046eb5e2ed49d5288566df3d4e 800000006eb5e2ed49d5288866df3d4e 9ba4fe046eb5e2ed49d5288566df3d4e fpscr=00000000
+vrintp.f32.f32 q6, q8 28de134f0ec5ccff3651c0065af6cba4 c6bbe5dc698ab51e3633337d3a9eadc2 c6bbe400698ab51e3f8000003f800000 c6bbe5dc698ab51e3633337d3a9eadc2 fpscr=00000000
+vrintp.f32.f32 q6, q8 4894f196ef6c22727cb2e8a3f0961d5b 7f01e68daceab3aa9312cec6db91c94d 7f01e68d8000000080000000db91c94d 7f01e68daceab3aa9312cec6db91c94d fpscr=00000000
+vrintp.f32.f32 q6, q8 7f1086124cddc3a439ef6f87f8053adc 75746ea5492ab43e79346e8ce8c0c6fd 75746ea5492ab44079346e8ce8c0c6fd 75746ea5492ab43e79346e8ce8c0c6fd fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[0]
+vrintp.f32.f32 q6, q8 f37d22e75be88653096a97c36746576e 96dcdcddf00b45bf78253c4a78253c4a 80000000f00b45bf78253c4a78253c4a 96dcdcddf00b45bf78253c4a78253c4a fpscr=00000000
+vrintp.f32.f32 q6, q8 515f104c9a2a0e8f0bd2950f8830b0a1 b452151cb8e8323b5b9c653b2e8a84da 80000000800000005b9c653b3f800000 b452151cb8e8323b5b9c653b2e8a84da fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintp.f32.f32 q6, q8 0efdf0110efdf01177ec6da169a7b723 375f9bb037f72c314b7b3c83fcfa1232 3f8000003f8000004b7b3c83fcfa1232 375f9bb037f72c314b7b3c83fcfa1232 fpscr=00000000
+vrintp.f32.f32 q6, q8 aa8cb0570fcd963a6b75bfbf8f2abcf7 ebb442a390e1802ace32868822cd01bd ebb442a380000000ce3286883f800000 ebb442a390e1802ace32868822cd01bd fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[3]
+vrintp.f32.f32 q6, q8 25075fd970daef7725075fd9938cfb7e ebb34c111dc7fd6eebb34c113d8652e3 ebb34c113f800000ebb34c113f800000 ebb34c111dc7fd6eebb34c113d8652e3 fpscr=00000000
+vrintp.f32.f32 q6, q8 baf2774c166e8e2a2cd9fb9bad33c1c7 791dc138d45906f17eb58983f030c3f9 791dc138d45906f17eb58983f030c3f9 791dc138d45906f17eb58983f030c3f9 fpscr=00000000
+vrintp.f32.f32 q6, q8 65e7fd815f947c6f6fddb7f91427f79d 02825f233328d94ac5ea7815b3809e7f 3f8000003f800000c5ea780080000000 02825f233328d94ac5ea7815b3809e7f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[0]
+vrintp.f32.f32 q6, q8 6810e1761c8b588f6c46b6a7f8182080 9e542db5d52259b35b51fc5d8c1d2cff 80000000d52259b35b51fc5d80000000 9e542db5d52259b35b51fc5d8c1d2cff fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintp.f32.f32 q6, q8 2ed5b54a4288fd86cf3589c3de3ab5de c0c7e2dc8aed850af75e06a73f64b63d c0c0000080000000f75e06a73f800000 c0c7e2dc8aed850af75e06a73f64b63d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintp.f32.f32 q6, q8 6eadd0c7793034f390693d2ae6b553c3 23262fb70c7505238656428623262fb7 3f8000003f800000800000003f800000 23262fb70c7505238656428623262fb7 fpscr=00000000
+vrintp.f32.f32 q6, q8 543ee8357bb6001826aa1ed8e2e3c186 d1025b9ad678676a98e88d543b2e11de d1025b9ad678676a800000003f800000 d1025b9ad678676a98e88d543b2e11de fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintp.f32.f32 q6, q8 eab7a1d27dcd47b494bf5f0e4a7d6c0d 8384d140a9213016725942d5447ff7b3 8000000080000000725942d544800000 8384d140a9213016725942d5447ff7b3 fpscr=00000000
+vrintp.f32.f32 q6, q8 c615de2bf2d8b858fe3662695b7c72c6 df1411d817deb1e55bba42940a1e9018 df1411d83f8000005bba42943f800000 df1411d817deb1e55bba42940a1e9018 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintp.f32.f32 q6, q8 1210143c9de965077100f7d3558162f2 854d9e64687c7968854d9e6438877bba 80000000687c7968800000003f800000 854d9e64687c7968854d9e6438877bba fpscr=00000000
+vrintp.f32.f32 q6, q8 c426a3490633f34d53d2ad1cbba1726c 68ab601c414f8f28356873d3a0827d16 68ab601c415000003f80000080000000 68ab601c414f8f28356873d3a0827d16 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintp.f32.f32 q6, q8 87fd445ecb2ec16c984ba07640b64412 4c6d8b175e90aa9b949c33508207a258 4c6d8b175e90aa9b8000000080000000 4c6d8b175e90aa9b949c33508207a258 fpscr=00000000
+vrintp.f32.f32 q6, q8 8d4d8269151369bf10db8d858adb51b4 fa3ef5d5705c7a788d4f2a320ef0683d fa3ef5d5705c7a78800000003f800000 fa3ef5d5705c7a788d4f2a320ef0683d fpscr=00000000
+randV128: 18176 calls, 18788 iters
+vrintp.f32.f32 q6, q8 8661c49aa9ff3b4921474c278a77d5ea d53df7b0d5311e1f9f40d9d812997a1c d53df7b0d5311e1f800000003f800000 d53df7b0d5311e1f9f40d9d812997a1c fpscr=00000000
+vrintp.f32.f32 q6, q8 6f9af687aaf3ed40357329a560c9d705 8f34c60ab7e8beadea4ca295218d9d57 8000000080000000ea4ca2953f800000 8f34c60ab7e8beadea4ca295218d9d57 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintp.f32.f32 q6, q8 2526d6e6b0e9a1a03c7e9928110b2bde 1bc52ed933a3e004793897a49a6fe218 3f8000003f800000793897a480000000 1bc52ed933a3e004793897a49a6fe218 fpscr=00000000
+vrintp.f32.f32 q6, q8 0fe17744793d87a3e6d532f53dc8fd22 b7b075ca83ba24f1f3d495b9bd1721a8 8000000080000000f3d495b980000000 b7b075ca83ba24f1f3d495b9bd1721a8 fpscr=00000000
+vrintp.f32.f32 q6, q8 6eead41e4bfd04494c14c463b2094ef4 fa8af40c29a913f115f2781b16249acf fa8af40c3f8000003f8000003f800000 fa8af40c29a913f115f2781b16249acf fpscr=00000000
+vrintp.f32.f32 q6, q8 979cfd05899a69c2ce492d08c6c6aef7 9fbf83b872699d16741ffc2bba8940eb 8000000072699d16741ffc2b80000000 9fbf83b872699d16741ffc2bba8940eb fpscr=00000000
+vrintp.f32.f32 q6, q8 60db40c30cfb2182489246c57628d0e1 e6829e2ac577a8e548a32661f7f48d58 e6829e2ac577a00048a32680f7f48d58 e6829e2ac577a8e548a32661f7f48d58 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintm.f32.f32 q9, q11 062858ba57aaf90c57aaf90c8b304d89 9d96e223f825fb34d8b83049a361dc1a bf800000f825fb34d8b83049bf800000 9d96e223f825fb34d8b83049a361dc1a fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintm.f32.f32 q9, q11 0b8fad553a25372d0ad64e0bf8217b51 b7a29d10ab1e1afe652f9a9e3e824015 bf800000bf800000652f9a9e00000000 b7a29d10ab1e1afe652f9a9e3e824015 fpscr=00000000
+vrintm.f32.f32 q9, q11 a02f6a53bb99c5c03bbb889165fa5084 c02ac530a2b5d16a8531507e830eb444 c0400000bf800000bf800000bf800000 c02ac530a2b5d16a8531507e830eb444 fpscr=00000000
+vrintm.f32.f32 q9, q11 354545f8190c4ecb1a546dcfa68196b6 db101a05de357b4f7a06f899a3e5ed98 db101a05de357b4f7a06f899bf800000 db101a05de357b4f7a06f899a3e5ed98 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintm.f32.f32 q9, q11 0de14b6651770f76eb340f081464e51d ef288d0fe80d03eefe4f1542ef288d0f ef288d0fe80d03eefe4f1542ef288d0f ef288d0fe80d03eefe4f1542ef288d0f fpscr=00000000
+vrintm.f32.f32 q9, q11 eb60fdefac02898c76a144aa85fff407 2f4975f42f36a990c7141d1806fa805a 0000000000000000c7141e0000000000 2f4975f42f36a990c7141d1806fa805a fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vrintm.f32.f32 q9, q11 08c53472282d647f5004394ffa8bec3e 8b3062f577a760438ecada108ecada10 bf80000077a76043bf800000bf800000 8b3062f577a760438ecada108ecada10 fpscr=00000000
+vrintm.f32.f32 q9, q11 86081e5b71e03be8f6937b65b080d7d7 51fd9a8b57f590d99d2de92cb142b867 51fd9a8b57f590d9bf800000bf800000 51fd9a8b57f590d99d2de92cb142b867 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintm.f32.f32 q9, q11 181faa92181faa928854bc9d44fd83ac 6a2df7bfafed21c7c901d49a88814216 6a2df7bfbf800000c901d4a0bf800000 6a2df7bfafed21c7c901d49a88814216 fpscr=00000000
+vrintm.f32.f32 q9, q11 ca6496cafcdbd807b36fc0452875cc1c 8e8cc8a90e1bd8945e8ab9238a564565 bf800000000000005e8ab923bf800000 8e8cc8a90e1bd8945e8ab9238a564565 fpscr=00000000
+vrintm.f32.f32 q9, q11 6c08345e95648cd4a96b60cf615e669b 0dc20a00a93aae4991e4192ac5057bf3 00000000bf800000bf800000c5058000 0dc20a00a93aae4991e4192ac5057bf3 fpscr=00000000
+vrintm.f32.f32 q9, q11 3ec71543227fe8fbc2a1dac45a2291d8 82c8b6ef5fd20c298983e9b752691960 bf8000005fd20c29bf80000052691960 82c8b6ef5fd20c298983e9b752691960 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[0]
+vrintm.f32.f32 q9, q11 8b39173d15fc6afc570a61e5317b5ffb ff35b1d1bfe9753cff35b1d18d45dad4 ff35b1d1c0000000ff35b1d1bf800000 ff35b1d1bfe9753cff35b1d18d45dad4 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintm.f32.f32 q9, q11 7b74901561e0810f28d82f0d697ad2c6 40417001951d5c663304af9dadc19413 40400000bf80000000000000bf800000 40417001951d5c663304af9dadc19413 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintm.f32.f32 q9, q11 a1aa2e755611d3998f82b75b9ccb2056 47c35efe8fda82048fda820464a81ee7 47c35e80bf800000bf80000064a81ee7 47c35efe8fda82048fda820464a81ee7 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintm.f32.f32 q9, q11 3e59b01ebe71be191077e3cc038aea33 532f038ed7ec89c10f62ecb7d7ec89c1 532f038ed7ec89c100000000d7ec89c1 532f038ed7ec89c10f62ecb7d7ec89c1 fpscr=00000000
+vrintm.f32.f32 q9, q11 4bde568a223c3eeac872035f99b16953 c6b8605f416b4d38e2d54e46f5f2ced8 c6b8620041600000e2d54e46f5f2ced8 c6b8605f416b4d38e2d54e46f5f2ced8 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintm.f32.f32 q9, q11 1b89f5ed115d95ef15df5ca33182fa09 68b9236ac63c060dbb62dfeba0d25fdc 68b9236ac63c0800bf800000bf800000 68b9236ac63c060dbb62dfeba0d25fdc fpscr=00000000
+vrintm.f32.f32 q9, q11 7a226ac5421eff05b2b0b974ce074971 7c914bd6f41882208dabb6b74e86e0b2 7c914bd6f4188220bf8000004e86e0b2 7c914bd6f41882208dabb6b74e86e0b2 fpscr=00000000
+vrintm.f32.f32 q9, q11 aa0f3946c6c97be156f07f9ff1ebff74 a93ae96e8f8782c92c2293daae65f607 bf800000bf80000000000000bf800000 a93ae96e8f8782c92c2293daae65f607 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintm.f32.f32 q9, q11 77e60d4259a8d8dbaff4e612f9c17bb9 341a27fabb7654464512154d9134fac8 00000000bf80000045121000bf800000 341a27fabb7654464512154d9134fac8 fpscr=00000000
+vrintm.f32.f32 q9, q11 44842d18ca97c2e7a9ae720b6fdb1504 affab653f987010e539ea695e1ceff12 bf800000f987010e539ea695e1ceff12 affab653f987010e539ea695e1ceff12 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintm.f32.f32 q9, q11 e61c67d18c64ed4cbf1f2658bb3bd799 9ecdb6d26919c190494d3d13c7f0cb78 bf8000006919c190494d3d10c7f0cb80 9ecdb6d26919c190494d3d13c7f0cb78 fpscr=00000000
+vrintm.f32.f32 q9, q11 09e4d189fde26efdf1b9079253f689de 5085b75d80b400e4a7e478a330eb689f 5085b75dbf800000bf80000000000000 5085b75d80b400e4a7e478a330eb689f fpscr=00000000
+vrintm.f32.f32 q9, q11 45b65c84d1091f4005174601907e936d f920d68f569b856a8407fb0253033b77 f920d68f569b856abf80000053033b77 f920d68f569b856a8407fb0253033b77 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintm.f32.f32 q9, q11 0f1274c07e91654f7e91654f6fed4d88 64693bbf64900cdb2c7e835a94fcfa36 64693bbf64900cdb00000000bf800000 64693bbf64900cdb2c7e835a94fcfa36 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[1]
+vrintm.f32.f32 q9, q11 f5421f42d75ce75e7ca1765b9b0951ed b16144c3c85138a2141dbdcec85138a2 bf800000c85138c000000000c85138c0 b16144c3c85138a2141dbdcec85138a2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintm.f32.f32 q9, q11 cc6ad70be8d453f233bba44d4e7a6d7e 0bc772280bc772280794585932302ff1 00000000000000000000000000000000 0bc772280bc772280794585932302ff1 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[0]
+vrintm.f32.f32 q9, q11 2416e2950337e2d97d76d75523b84d02 3c9d3f46ad7ee78f9ed76e32ad7ee78f 00000000bf800000bf800000bf800000 3c9d3f46ad7ee78f9ed76e32ad7ee78f fpscr=00000000
+vrintm.f32.f32 q9, q11 fd95e5158a0e709b17bdf3dc3ecbf671 00fe2f53c7e111b9a5c6b0de5782feb2 00000000c7e11200bf8000005782feb2 00fe2f53c7e111b9a5c6b0de5782feb2 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintm.f32.f32 q9, q11 e8e9186d6430edf1118d7feea0dddf0d 0a0d47687baf7adce0feeea19f6af475 000000007baf7adce0feeea1bf800000 0a0d47687baf7adce0feeea19f6af475 fpscr=00000000
+vrintm.f32.f32 q9, q11 3e30e769426c59bf15cae7d0cf63a68a a673076860030dac0e3f1a75a277a6a2 bf80000060030dac00000000bf800000 a673076860030dac0e3f1a75a277a6a2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintm.f32.f32 q9, q11 2428b5df6eb91d6f2428b5df8b1267d4 2dbcaa44d79d745bcde7b08e69ad7845 00000000d79d745bcde7b08e69ad7845 2dbcaa44d79d745bcde7b08e69ad7845 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[1]
+vrintm.f32.f32 q9, q11 efb27d66cb7c181a620c3170cb7c181a 4b8e3b6c044933b86c4fc7611993f6e7 4b8e3b6c000000006c4fc76100000000 4b8e3b6c044933b86c4fc7611993f6e7 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintm.f32.f32 q9, q11 738ddb9b3f9a7af8738ddb9b43e95bda 7b3096fa587f12ee0a04f928dd4bb14c 7b3096fa587f12ee00000000dd4bb14c 7b3096fa587f12ee0a04f928dd4bb14c fpscr=00000000
+vrintm.f32.f32 q9, q11 d450c2972917da45f0918606dd5b0d0b 0927d3c790e6ca509b7c120320f3e7fa 00000000bf800000bf80000000000000 0927d3c790e6ca509b7c120320f3e7fa fpscr=00000000
+vrintm.f32.f32 q9, q11 22f5641a66c30b097f139266249fe863 aa039f1f79cbe5fb7d685aeaf84d61d6 bf80000079cbe5fb7d685aeaf84d61d6 aa039f1f79cbe5fb7d685aeaf84d61d6 fpscr=00000000
+vrintm.f32.f32 q9, q11 337e0a05fa0731632334e4d5445ad2a5 bbc7cf43c0612b2512c7e8f0871a7f39 bf800000c080000000000000bf800000 bbc7cf43c0612b2512c7e8f0871a7f39 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintm.f32.f32 q9, q11 bc1c9bc83cf0964d2e826238ce60310b cd92df742604d6efb79b520bb79b520b cd92df7400000000bf800000bf800000 cd92df742604d6efb79b520bb79b520b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintm.f32.f32 q9, q11 90d6fa80fa8b4be490d6fa803fd8bcf3 2188367fe3e0e053269cf220dfbe7eef 00000000e3e0e05300000000dfbe7eef 2188367fe3e0e053269cf220dfbe7eef fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintm.f32.f32 q9, q11 3f0ded072a3f2de2cd848decfce8c24d 4e9568fe1ab8e097b56e293110459a64 4e9568fe00000000bf80000000000000 4e9568fe1ab8e097b56e293110459a64 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[3]
+vrintm.f32.f32 q9, q11 efe0e29f5523c45b78acc01f5d2245ba 83f385c3034ee0dba030f8a4dccb5ef4 bf80000000000000bf800000dccb5ef4 83f385c3034ee0dba030f8a4dccb5ef4 fpscr=00000000
+vrintm.f32.f32 q9, q11 b5e411429fca1a1cff4406dd3e3fc34d b94701e31565278e35614864dddb5106 bf8000000000000000000000dddb5106 b94701e31565278e35614864dddb5106 fpscr=00000000
+vrintm.f32.f32 q9, q11 e40bfc6d1827316d45643da90ae52f40 38caa3c8830d3d7106690ff6a81d4440 00000000bf80000000000000bf800000 38caa3c8830d3d7106690ff6a81d4440 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[1]
+vrintm.f32.f32 q9, q11 57d743e253ad73e12d858cc1462bb5a0 a9d8e77fa9d8e77f4b9d0d91d7601c89 bf800000bf8000004b9d0d91d7601c89 a9d8e77fa9d8e77f4b9d0d91d7601c89 fpscr=00000000
+vrintm.f32.f32 q9, q11 7cf1564fa367ab2ea9526de0ccab8a18 af78ecaa3e6394a6c468e2955a40a5ba bf80000000000000c46900005a40a5ba af78ecaa3e6394a6c468e2955a40a5ba fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintm.f32.f32 q9, q11 4005222c4b5598e40898a925b64ac141 c8f7e5050c74221d13d3dff0ef77b6a7 c8f7e5200000000000000000ef77b6a7 c8f7e5050c74221d13d3dff0ef77b6a7 fpscr=00000000
+vrintm.f32.f32 q9, q11 e5d7aa036f8bde01a8869257c4ad1f48 36e85fe500c4afd41b12e1c02f93934e 00000000000000000000000000000000 36e85fe500c4afd41b12e1c02f93934e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintm.f32.f32 q9, q11 699e33fee65c61aa4c0a7b79ae41b1d7 6c4df2920b0b8605c0d69d07853710bc 6c4df29200000000c0e00000bf800000 6c4df2920b0b8605c0d69d07853710bc fpscr=00000000
+vrintm.f32.f32 q9, q11 f103d377c9490113e391525efc8b9ff8 afe53f586a18cc656d6b8f3122e0f375 bf8000006a18cc656d6b8f3100000000 afe53f586a18cc656d6b8f3122e0f375 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintz.f32.f32 q12, q14 d877010dd877010d4617bad4bdfc89bd e8cf05b47328c70181808b99dbb5acc7 e8cf05b47328c70180000000dbb5acc7 e8cf05b47328c70181808b99dbb5acc7 fpscr=00000000
+vrintz.f32.f32 q12, q14 9f8d052606394d2ddb5067baf270943a 53c13b95fb2bb34f3944feec4f789dc1 53c13b95fb2bb34f000000004f789dc1 53c13b95fb2bb34f3944feec4f789dc1 fpscr=00000000
+vrintz.f32.f32 q12, q14 9f80f28183f185fa76749ef66119b4b3 fa4cb2111bf2eadd16436e9d49263406 fa4cb211000000000000000049263400 fa4cb2111bf2eadd16436e9d49263406 fpscr=00000000
+vrintz.f32.f32 q12, q14 2c49ad0e56148cd9bfb7a8fe6aa32bb0 cd037e1b65658d2c6a94751f18761601 cd037e1b65658d2c6a94751f00000000 cd037e1b65658d2c6a94751f18761601 fpscr=00000000
+vrintz.f32.f32 q12, q14 258ad8c5b81d43bffc39ee5fb5c1cd11 c7ff7092965f4c83b406f1e71e07babc c7ff7080800000008000000000000000 c7ff7092965f4c83b406f1e71e07babc fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[1]
+vrintz.f32.f32 q12, q14 ac9b1355ac9b13552a90287cf1cf78f3 a5c8ba1a8834072b569f787a81b93292 8000000080000000569f787a80000000 a5c8ba1a8834072b569f787a81b93292 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vrintz.f32.f32 q12, q14 6e6d700ebe38e2f6be38e2f6844f745a 05cbfcf7b7b40093d8283db5d51eecda 0000000080000000d8283db5d51eecda 05cbfcf7b7b40093d8283db5d51eecda fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: 18432 calls, 19051 iters
+vrintz.f32.f32 q12, q14 c8e1e85f11a45b14b9f6cf3ce5c124b9 4e2d77fe1a365f81010734c0010734c0 4e2d77fe000000000000000000000000 4e2d77fe1a365f81010734c0010734c0 fpscr=00000000
+vrintz.f32.f32 q12, q14 a1458f960bd1078514076d0e0f03f32c d76ee389dbbfb213374f6cfc21b9111b d76ee389dbbfb2130000000000000000 d76ee389dbbfb213374f6cfc21b9111b fpscr=00000000
+vrintz.f32.f32 q12, q14 da0be4e4cd63ad08d458450b98ad930c 78ddd3f03921bafb5b3fcb90d0d0f5a3 78ddd3f0000000005b3fcb90d0d0f5a3 78ddd3f03921bafb5b3fcb90d0d0f5a3 fpscr=00000000
+vrintz.f32.f32 q12, q14 e1948ba6467d99015d3ac0687bbae352 93058d37d592d67e8f12837a42f57705 80000000d592d67e8000000042f40000 93058d37d592d67e8f12837a42f57705 fpscr=00000000
+vrintz.f32.f32 q12, q14 4197d10ce32815295d4699fab1ac2898 937974d5bf2a0278764ae8f0bb9e1e67 8000000080000000764ae8f080000000 937974d5bf2a0278764ae8f0bb9e1e67 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintz.f32.f32 q12, q14 276b21c5840b54703592a0577e4744b0 08c240f77d5110c55c7784d33a65eba5 000000007d5110c55c7784d300000000 08c240f77d5110c55c7784d33a65eba5 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintz.f32.f32 q12, q14 a60042bdfd100c4a08211eb3ef2c37b2 8d0616c43cf89dc50658e5d79865494d 80000000000000000000000080000000 8d0616c43cf89dc50658e5d79865494d fpscr=00000000
+vrintz.f32.f32 q12, q14 6bec14680b3454a9413f59faae9a7d64 92671b15c788623823035db49f5d7660 80000000c78862000000000080000000 92671b15c788623823035db49f5d7660 fpscr=00000000
+vrintz.f32.f32 q12, q14 e9706cb36deb329711203a16c2511939 8f249227335c584ed6071dbc6b1cc66b 8000000000000000d6071dbc6b1cc66b 8f249227335c584ed6071dbc6b1cc66b fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[2]
+vrintz.f32.f32 q12, q14 70577e6bcad4ded83e7720b7c09aba25 cd079df2916054a26b78daefcd079df2 cd079df2800000006b78daefcd079df2 cd079df2916054a26b78daefcd079df2 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintz.f32.f32 q12, q14 1a7f578de7c4382c1a7f578d5f8215fc 1ad904fdb83ba5a4862c2766d15f9829 000000008000000080000000d15f9829 1ad904fdb83ba5a4862c2766d15f9829 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintz.f32.f32 q12, q14 da6d2a55da6d2a553613133b37cf0104 e8c9837a5888b999ac263a54c1472185 e8c9837a5888b99980000000c1400000 e8c9837a5888b999ac263a54c1472185 fpscr=00000000
+vrintz.f32.f32 q12, q14 129c71218f8e383e0db9c70decd5d3e4 afe607fb438adb35e685a9d99c18061c 80000000438a8000e685a9d980000000 afe607fb438adb35e685a9d99c18061c fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintz.f32.f32 q12, q14 3e9b28018b030b153e9b28017d8abba9 418c07906549367ef961fc41e7ac5981 418800006549367ef961fc41e7ac5981 418c07906549367ef961fc41e7ac5981 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintz.f32.f32 q12, q14 8eddbf532e016b01f9dadb401236b53b 960ee53b2733f46ca57022c81a43742e 80000000000000008000000000000000 960ee53b2733f46ca57022c81a43742e fpscr=00000000
+vrintz.f32.f32 q12, q14 30f2eb51228990474ef29b297d37a8a3 416ea9d94aa348bf6b2dbf0de1dc2963 416000004aa348be6b2dbf0de1dc2963 416ea9d94aa348bf6b2dbf0de1dc2963 fpscr=00000000
+vrintz.f32.f32 q12, q14 40d383211561ba727d4813778eac4179 568233dbfce209898fd8dcc9f0e9eb79 568233dbfce2098980000000f0e9eb79 568233dbfce209898fd8dcc9f0e9eb79 fpscr=00000000
+vrintz.f32.f32 q12, q14 ce89d73af6812ff3d8470fb6a0cf764c 1bcdef8a45ec1db1724b5716af6c308b 0000000045ec1800724b571680000000 1bcdef8a45ec1db1724b5716af6c308b fpscr=00000000
+vrintz.f32.f32 q12, q14 bf2666723c7a88666014c727d8844afe 2afdedb20e6d20478da2e44b810975e2 00000000000000008000000080000000 2afdedb20e6d20478da2e44b810975e2 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintz.f32.f32 q12, q14 7d414c03949feb13949feb13de6cac9d b7c9b6ddbb95dcf6de0ad60efc0d0c03 8000000080000000de0ad60efc0d0c03 b7c9b6ddbb95dcf6de0ad60efc0d0c03 fpscr=00000000
+vrintz.f32.f32 q12, q14 3fa3708a4dee069cb5f72373e56b35d6 ee514f507b74b39b8594c20728125410 ee514f507b74b39b8000000000000000 ee514f507b74b39b8594c20728125410 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintz.f32.f32 q12, q14 2b68d4343a334827750b04667c47f58b 455d7ba3c576cfe2b3dc22e6364abc8f 455d7000c576c0008000000000000000 455d7ba3c576cfe2b3dc22e6364abc8f fpscr=00000000
+vrintz.f32.f32 q12, q14 1eae16aaef48b5f2ba51609aeb22e142 4d107f39354483ea451f601ddfd74060 4d107f3900000000451f6000dfd74060 4d107f39354483ea451f601ddfd74060 fpscr=00000000
+vrintz.f32.f32 q12, q14 900160d4a3cc586b86dd0ed2209810b8 933002a54fd892f07f27b11e9d359da7 800000004fd892f07f27b11e80000000 933002a54fd892f07f27b11e9d359da7 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintz.f32.f32 q12, q14 455d742f6cd83dd8d67171e1b44a98e7 4ddf4d3ea9b45980a9b45980343ab05c 4ddf4d3e800000008000000000000000 4ddf4d3ea9b45980a9b45980343ab05c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintz.f32.f32 q12, q14 4936dd600178ae7fe22ecba456ce177e a08accc7404457ad34cca8539d6f1018 80000000404000000000000080000000 a08accc7404457ad34cca8539d6f1018 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[0]
+vrintz.f32.f32 q12, q14 6daed38f5045ab636fa16fb9d0e5533e c74dd5b58f824bbe9754c00bc74dd5b5 c74dd5008000000080000000c74dd500 c74dd5b58f824bbe9754c00bc74dd5b5 fpscr=00000000
+vrintz.f32.f32 q12, q14 c8a9d27e1d1258dd636b0bf96e935c9c 039dccadfc9135a3fd8e7e03b6880c99 00000000fc9135a3fd8e7e0380000000 039dccadfc9135a3fd8e7e03b6880c99 fpscr=00000000
+vrintz.f32.f32 q12, q14 ebc47b5984dafa5a80c915d395b6772c 177a4df9b2e96b5405a6769ec86ea684 000000008000000000000000c86ea680 177a4df9b2e96b5405a6769ec86ea684 fpscr=00000000
+vrintz.f32.f32 q12, q14 2da007de9d795df29c752a934bc58a6b af9a7b977e6941629b6335a8ccd596bc 800000007e69416280000000ccd596bc af9a7b977e6941629b6335a8ccd596bc fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vrintz.f32.f32 q12, q14 e487da088b4aa6921dad9c08a3a0ebcb 7253776dcc19ce7f7253776d10430784 7253776dcc19ce7f7253776d00000000 7253776dcc19ce7f7253776d10430784 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintz.f32.f32 q12, q14 7d217dcf935cd87039b6285a0376817f 2ce0b55b910c860b7d087208d1c42be8 00000000800000007d087208d1c42be8 2ce0b55b910c860b7d087208d1c42be8 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintz.f32.f32 q12, q14 bfda0b857d2de740709d82fbbfda0b85 747561927cb8867e0f307438260bc79f 747561927cb8867e0000000000000000 747561927cb8867e0f307438260bc79f fpscr=00000000
+vrintz.f32.f32 q12, q14 024eeed29b41f8a8070b3cf27a31f51d 00818bf9e75649fcc400d09eba28afbd 00000000e75649fcc400c00080000000 00818bf9e75649fcc400d09eba28afbd fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[1]
+vrintz.f32.f32 q12, q14 bba5ebeda7a9269a60e51084bf647b79 444d7dd2f3af1a03584fd72af3af1a03 444d4000f3af1a03584fd72af3af1a03 444d7dd2f3af1a03584fd72af3af1a03 fpscr=00000000
+vrintz.f32.f32 q12, q14 3e6bfc69a8c58e03c9b6a079d83828a8 47ed0f14b582787d24a48b1d219b4566 47ed0f00800000000000000000000000 47ed0f14b582787d24a48b1d219b4566 fpscr=00000000
+vrintz.f32.f32 q12, q14 d01500b104665287ca301f623240bda1 2d25f37071f37a5ebcc9fa320ecf6c87 0000000071f37a5e8000000000000000 2d25f37071f37a5ebcc9fa320ecf6c87 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintz.f32.f32 q12, q14 ad7ef10f49b15b5a81270bacf4bb9612 46d49855b22a4a3fd02904c462117506 46d4980080000000d02904c462117506 46d49855b22a4a3fd02904c462117506 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintz.f32.f32 q12, q14 6e0c25073948d77e1d233ac3e77a5981 216edfc7045febe1a4d5d98ac24da4e7 000000000000000080000000c24c0000 216edfc7045febe1a4d5d98ac24da4e7 fpscr=00000000
+vrintz.f32.f32 q12, q14 37bd6c634aafa1f3630c23d386c401bb 0f978c74fcae37e8940ea0130c6b43c0 00000000fcae37e88000000000000000 0f978c74fcae37e8940ea0130c6b43c0 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintz.f32.f32 q12, q14 ea8476993b0468e7ea8476995cd1ad77 b8a5bf376dc7a6a405627894bba9e0ca 800000006dc7a6a40000000080000000 b8a5bf376dc7a6a405627894bba9e0ca fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[0]
+vrintz.f32.f32 q12, q14 9121d93d287e3fc6218fbde3218fbde3 8bf14e1bdc643e7e067c9064dc643e7e 80000000dc643e7e00000000dc643e7e 8bf14e1bdc643e7e067c9064dc643e7e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintz.f32.f32 q12, q14 375c6f20375c6f203ec4558a80ba1cff f49727aea83ade82ee653533119dd8a1 f49727ae80000000ee65353300000000 f49727aea83ade82ee653533119dd8a1 fpscr=00000000
+vrintx.f32.f32 q15, q15 1836bb9e0eacb60d6aaed33aec83eb55 d28faf6da28b0097967a4842cc41b8b9 d28faf6d8000000080000000cc41b8b9 d28faf6d8000000080000000cc41b8b9 fpscr=00000000
+vrintx.f32.f32 q15, q15 65368b931c9a145f68b209e3010b339a 293bd0c4517ac32116e4e088a5a0033d 00000000517ac3210000000080000000 00000000517ac3210000000080000000 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintx.f32.f32 q15, q15 8c6f5376b00f8a228b638def4f874c60 e1049f09e1049f09fc06546cb1812762 e1049f09e1049f09fc06546c80000000 e1049f09e1049f09fc06546c80000000 fpscr=00000000
+vrintx.f32.f32 q15, q15 7a8280d56c399d8e1b32c6438c8dc253 b07352cb31e21547b95ccb70203277b3 80000000000000008000000000000000 80000000000000008000000000000000 fpscr=00000000
+vrintx.f32.f32 q15, q15 3abad55aa0cdebce0491dca0010e6190 ccb44bc4c552463aa961ef754d70793c ccb44bc4c5524000800000004d70793c ccb44bc4c5524000800000004d70793c fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintx.f32.f32 q15, q15 416bc65c1a40481b902ded7648d61d5a fc22bfe08e3708ee87c72ce9fc22bfe0 fc22bfe08000000080000000fc22bfe0 fc22bfe08000000080000000fc22bfe0 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[0]
+vrintx.f32.f32 q15, q15 896055f6d1f26a8fd1f26a8f1416ef64 0e2c10dfa3591529bceca35f12f3be22 00000000800000008000000000000000 00000000800000008000000000000000 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintx.f32.f32 q15, q15 3086a123bda7326bd369e63d3086a123 d2ae1069a882341672afa696058d76bd d2ae10698000000072afa69600000000 d2ae10698000000072afa69600000000 fpscr=00000000
+vrintx.f32.f32 q15, q15 789db5eb54a6234c5cfaa080ecc9a778 1f6cc3ed6f03101a928e6c7e69760810 000000006f03101a8000000069760810 000000006f03101a8000000069760810 fpscr=00000000
+vrintx.f32.f32 q15, q15 62972b80faeaf0eef5b7bdc4c940aab4 cfcba3316a9fb10c0a3a69c9442c38c6 cfcba3316a9fb10c00000000442c4000 cfcba3316a9fb10c00000000442c4000 fpscr=00000000
+vrintx.f32.f32 q15, q15 3ef5cd9153b2c85af3be50b85faafe4c f53897af80b9a832aac07d0805327a56 f53897af800000008000000000000000 f53897af800000008000000000000000 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[0]
+vrintx.f32.f32 q15, q15 caa4a186a205758229b9c7714379b3a9 2f71dc807d8371cc7d8371cc3fb088bf 000000007d8371cc7d8371cc3f800000 000000007d8371cc7d8371cc3f800000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintx.f32.f32 q15, q15 0a5fe18a50321299e3468ad539c79c86 4e52822738b722594fc64333a4ab59ec 4e528227000000004fc6433380000000 4e528227000000004fc6433380000000 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintx.f32.f32 q15, q15 9c5e45a9bed92ed14fea7ed9e1f25dc1 3d99b2555bb1e3d81c6f8d1420da8773 000000005bb1e3d80000000000000000 000000005bb1e3d80000000000000000 fpscr=00000000
+vrintx.f32.f32 q15, q15 286f58d56f3659829bd949c389f8cf28 9707f4c9744a38c450616d1f5f2c7cd3 80000000744a38c450616d1f5f2c7cd3 80000000744a38c450616d1f5f2c7cd3 fpscr=00000000
+vrintx.f32.f32 q15, q15 377823e6343e62a0f8bd591a10759908 09d3a28418a9ae101b623324abd660ad 00000000000000000000000080000000 00000000000000000000000080000000 fpscr=00000000
+vrintx.f32.f32 q15, q15 d9eddd4eb238a8d5715a14e1547b5083 536770f6a19c3251eeb6cd769107fe76 536770f680000000eeb6cd7680000000 536770f680000000eeb6cd7680000000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintx.f32.f32 q15, q15 17f898bb4b7490fa7d1b41a1c0244cf9 435711f1c95604b5d46e7c2b770db1db 43570000c95604b0d46e7c2b770db1db 43570000c95604b0d46e7c2b770db1db fpscr=00000000
+vrintx.f32.f32 q15, q15 f2168dbb1f6874826b300a54a5477781 44093282caf7b059becb7ecc094f0128 44094000caf7b0588000000000000000 44094000caf7b0588000000000000000 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[2]
+vrintx.f32.f32 q15, q15 a389a9c48628184a2289fcfbce6cf6ed 1d1aeed3634b6852eab5643feab5643f 00000000634b6852eab5643feab5643f 00000000634b6852eab5643feab5643f fpscr=00000000
+vrintx.f32.f32 q15, q15 324c440689bee90dfa2ac8e792cbd281 105d0164ed06dcc4a3ce01da80dbd6d9 00000000ed06dcc48000000080000000 00000000ed06dcc48000000080000000 fpscr=00000000
+randV128: 18688 calls, 19312 iters
+vrintx.f32.f32 q15, q15 8e301f5c9d3b3781541e376f0fe10f80 e1760db50a65fa5bed9a554e5610f70d e1760db500000000ed9a554e5610f70d e1760db500000000ed9a554e5610f70d fpscr=00000000
+vrintx.f32.f32 q15, q15 73857fa2155c85f66e970db8f7e50979 3bd1aa4b099c2596cfca386cc37d8c14 0000000000000000cfca386cc37e0000 0000000000000000cfca386cc37e0000 fpscr=00000000
+vrintx.f32.f32 q15, q15 8fe2f6dbd60c0e224fbbeb2383bfa40d 2117910534101645b1edc72fc06c1a77 000000000000000080000000c0800000 000000000000000080000000c0800000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vrintx.f32.f32 q15, q15 2cfefdbdd506dc342cfefdbd3b4a5460 084947b8ca242595dbddc673084947b8 00000000ca242594dbddc67300000000 00000000ca242594dbddc67300000000 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintx.f32.f32 q15, q15 e33b8a07e33b8a072eb4680d985c5df8 6480f7aa5c384b23e2a18fee78e5754a 6480f7aa5c384b23e2a18fee78e5754a 6480f7aa5c384b23e2a18fee78e5754a fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[2]
+vrintx.f32.f32 q15, q15 1bce841017696b4c81d1c72b6d11123e 09dc14068611d5048611d5048e7bd02a 00000000800000008000000080000000 00000000800000008000000080000000 fpscr=00000000
+vrintx.f32.f32 q15, q15 f4c56f19eaa617d410b8421a2511a329 4776a02c765a3beb8aa887c697a2958e 4776a000765a3beb8000000080000000 4776a000765a3beb8000000080000000 fpscr=00000000
+vrintx.f32.f32 q15, q15 7418736607b28df5249cbc95c02896ce 34e43772d162895a3f93ddc355154c47 00000000d162895a3f80000055154c47 00000000d162895a3f80000055154c47 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintx.f32.f32 q15, q15 5431fc21b37c163f812352f91e9851b1 16079155073929694cb23212918151fe 00000000000000004cb2321280000000 00000000000000004cb2321280000000 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintx.f32.f32 q15, q15 adc507c02728804fd160084bf0aab4d5 939fd67f5e6d396520cefd0cdfc43fd2 800000005e6d396500000000dfc43fd2 800000005e6d396500000000dfc43fd2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintx.f32.f32 q15, q15 665f853d7857fc90665f853db3af41b7 05b8b5a1e9b6d1931d6dc6b0f0bc5546 00000000e9b6d19300000000f0bc5546 00000000e9b6d19300000000f0bc5546 fpscr=00000000
+vrintx.f32.f32 q15, q15 59cb89648fb2d03f908c850bde537d8e 0a42952ed8efd136cdd431c536884590 00000000d8efd136cdd431c500000000 00000000d8efd136cdd431c500000000 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintx.f32.f32 q15, q15 ceb402ad24fa10da983281a9c1a7d956 01b11916667c823006ef689726fd16b6 00000000667c82300000000000000000 00000000667c82300000000000000000 fpscr=00000000
+vrintx.f32.f32 q15, q15 6e35105e6ef6c199aa70c3fba0ceee96 6f0564a7f6f93fa9748d57cb14aef212 6f0564a7f6f93fa9748d57cb00000000 6f0564a7f6f93fa9748d57cb00000000 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintx.f32.f32 q15, q15 51d392710aeec670be30882582127fa0 27fbf669f6b53ae68b50c108bb37a747 00000000f6b53ae68000000080000000 00000000f6b53ae68000000080000000 fpscr=00000000
+vrintx.f32.f32 q15, q15 253f1f175b75fd88e4d5d90de863cc40 6fdf94bf69112938cb2755316d6a3a7c 6fdf94bf69112938cb2755316d6a3a7c 6fdf94bf69112938cb2755316d6a3a7c fpscr=00000000
+vrintx.f32.f32 q15, q15 93e2dd9161dfa88967e212f069383c70 1208a2b545ba4d2e368381f7ca6f6cd7 0000000045ba500000000000ca6f6cd8 0000000045ba500000000000ca6f6cd8 fpscr=00000000
+vrintx.f32.f32 q15, q15 b5d018d721fd1e40a26abb34dc250e97 3a93815115b0c5be6503f50df18faea8 00000000000000006503f50df18faea8 00000000000000006503f50df18faea8 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[2]
+vrintx.f32.f32 q15, q15 8c2bcdac6032a7478c2bcdac70ac0106 6a8a25bca41f9e8a18e52399a41f9e8a 6a8a25bc800000000000000080000000 6a8a25bc800000000000000080000000 fpscr=00000000
+vrintx.f32.f32 q15, q15 0a2f0b0148c8b4dd70ddd39a578b2806 76a47b20c8f8e500f482d9cd42050bf3 76a47b20c8f8e500f482d9cd42040000 76a47b20c8f8e500f482d9cd42040000 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintx.f32.f32 q15, q15 c91114caee0a979fa6412764bcfeb3c8 e065ea1444c43b1e7304ef73e065ea14 e065ea1444c440007304ef73e065ea14 e065ea1444c440007304ef73e065ea14 fpscr=00000000
+vrintx.f32.f32 q15, q15 45e6eb4612e6370aa78da56b2f4061b1 fc8e08526e449b0c4a7b0a4f78015785 fc8e08526e449b0c4a7b0a5078015785 fc8e08526e449b0c4a7b0a5078015785 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintx.f32.f32 q15, q15 2855dc30d6c94f3e0c708f300c708f30 54f62fcd7ebbe3250dc589e9ccd4f60c 54f62fcd7ebbe32500000000ccd4f60c 54f62fcd7ebbe32500000000ccd4f60c fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintx.f32.f32 q15, q15 1ecc27fe27e8f34c682784c75237b980 e0e4cd51ca215049f8837032e66f9d5d e0e4cd51ca215048f8837032e66f9d5d e0e4cd51ca215048f8837032e66f9d5d fpscr=00000000
+vrintx.f32.f32 q15, q15 1672b08a020f49ad2dec34dcc31e8a2c 2b65a4f3a7840d96dc48917086a083f9 0000000080000000dc48917080000000 0000000080000000dc48917080000000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintx.f32.f32 q15, q15 35007c003092e93038e2b5797d512dcc 59e4fb074b647c694b647c694de28843 59e4fb074b647c694b647c694de28843 59e4fb074b647c694b647c694de28843 fpscr=00000000
+vrintx.f32.f32 q15, q15 02a0dd5830849ee2156d8983c2422a51 ef5918a22b9cadcc7b5d4795c62b6d93 ef5918a2000000007b5d4795c62b6c00 ef5918a2000000007b5d4795c62b6c00 fpscr=00000000
+vrintx.f32.f32 q15, q15 5935442528a7c5bb0eb8e9703a9665f6 ad686658d603d8bff52e3ce9ae604518 80000000d603d8bff52e3ce980000000 80000000d603d8bff52e3ce980000000 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintx.f32.f32 q15, q15 a21820b1885beb51f2f5f67d117eaf19 2517c0ee339b13c81b08771df61e75f8 000000000000000000000000f61e75f8 000000000000000000000000f61e75f8 fpscr=00000000
diff --git a/none/tests/arm/v8fpsimd_a.vgtest b/none/tests/arm/v8fpsimd_a.vgtest
new file mode 100644
index 0000000..360c897
--- /dev/null
+++ b/none/tests/arm/v8fpsimd_a.vgtest
@@ -0,0 +1,2 @@
+prog: v8fpsimd_a
+vgopts: -q
diff --git a/none/tests/arm/v8fpsimd_t.c b/none/tests/arm/v8fpsimd_t.c
new file mode 100644
index 0000000..ee7eeb2
--- /dev/null
+++ b/none/tests/arm/v8fpsimd_t.c
@@ -0,0 +1,553 @@
+
+/*
+gcc -o v8fpsimd_a v8fpsimd_a.c -march=armv8-a -mfpu=crypto-neon-fp-armv8 \
+ -I../../.. -Wall -g -marm
+
+gcc -o v8fpsimd_t v8fpsimd_a.c -march=armv8-a -mfpu=crypto-neon-fp-armv8 \
+ -I../../.. -Wall -g
+*/
+
+#include <stdio.h>
+#include <assert.h>
+#include <malloc.h> // memalign
+#include <string.h> // memset
+#include "tests/malloc.h"
+#include <math.h> // isnormal
+
+typedef unsigned char UChar;
+typedef unsigned short int UShort;
+typedef unsigned int UInt;
+typedef signed int Int;
+typedef unsigned char UChar;
+typedef unsigned long long int ULong;
+typedef signed long long int Long;
+typedef double Double;
+typedef float Float;
+
+typedef unsigned char Bool;
+#define False ((Bool)0)
+#define True ((Bool)1)
+
+
+#define ITERS 1
+
+typedef
+ enum { TyHF=1234, TySF, TyDF, TyB, TyH, TyS, TyD, TyNONE }
+ LaneTy;
+
+union _V128 {
+ UChar u8[16];
+ UShort u16[8];
+ UInt u32[4];
+ ULong u64[2];
+ Float f32[4];
+ Double f64[2];
+};
+typedef union _V128 V128;
+
+static inline UChar randUChar ( void )
+{
+ static UInt seed = 80021;
+ seed = 1103515245 * seed + 12345;
+ return (seed >> 17) & 0xFF;
+}
+
+//static ULong randULong ( LaneTy ty )
+//{
+// Int i;
+// ULong r = 0;
+// for (i = 0; i < 8; i++) {
+// r = (r << 8) | (ULong)(0xFF & randUChar());
+// }
+// return r;
+//}
+
+/* Generates a random V128. Ensures that that it contains normalised
+ FP numbers when viewed as either F32x4 or F64x2, so that it is
+ reasonable to use in FP test cases. */
+static void randV128 ( /*OUT*/V128* v, LaneTy ty )
+{
+ static UInt nCalls = 0, nIters = 0;
+ Int i;
+ nCalls++;
+ while (1) {
+ nIters++;
+ for (i = 0; i < 16; i++) {
+ v->u8[i] = randUChar();
+ }
+ if (randUChar() < 32) {
+ /* once every 8 times, clone one of the lanes */
+ switch (ty) {
+ case TySF: case TyS: {
+ UInt l1, l2;
+ while (1) {
+ l1 = randUChar() & 3;
+ l2 = randUChar() & 3;
+ if (l1 != l2) break;
+ }
+ assert(l1 < 4 && l2 < 4);
+ v->u32[l1] = v->u32[l2];
+ printf("randV128: doing v->u32[%u] = v->u32[%u]\n", l1, l2);
+ break;
+ }
+ case TyDF: case TyD: {
+ UInt l1, l2;
+ while (1) {
+ l1 = randUChar() & 1;
+ l2 = randUChar() & 1;
+ if (l1 != l2) break;
+ }
+ assert(l1 < 2 && l2 < 2);
+ printf("randV128: doing v->u64[%u] = v->u64[%u]\n", l1, l2);
+ v->u64[l1] = v->u64[l2];
+ break;
+ }
+ default:
+ break;
+ }
+ }
+ if (isnormal(v->f32[0]) && isnormal(v->f32[1]) && isnormal(v->f32[2])
+ && isnormal(v->f32[3]) && isnormal(v->f64[0]) && isnormal(v->f64[1]))
+ break;
+ }
+ if (0 == (nCalls & 0xFF))
+ printf("randV128: %u calls, %u iters\n", nCalls, nIters);
+}
+
+static void showV128 ( V128* v )
+{
+ Int i;
+ for (i = 15; i >= 0; i--)
+ printf("%02x", (Int)v->u8[i]);
+}
+
+//static void showBlock ( const char* msg, V128* block, Int nBlock )
+//{
+// Int i;
+// printf("%s\n", msg);
+// for (i = 0; i < nBlock; i++) {
+// printf(" ");
+// showV128(&block[i]);
+// printf("\n");
+// }
+//}
+
+
+/* ---------------------------------------------------------------- */
+/* -- Parameterisable test macros -- */
+/* ---------------------------------------------------------------- */
+
+#define DO50(_action) \
+ do { \
+ Int _qq; for (_qq = 0; _qq < 50; _qq++) { _action ; } \
+ } while (0)
+
+
+/* Are we compiling for thumb or arm encodings? This has a bearing
+ on the inline assembly syntax needed below. */
+
+#if defined(__thumb__) || defined(__thumb2__)
+# define IT_EQ "it eq ; "
+# define IT_NE "it ne ; "
+# define IT_AL /* */
+#else
+# define IT_EQ /* */
+# define IT_NE /* */
+# define IT_AL /* */
+#endif
+
+
+/* Generate a test that involves two vector regs,
+ with no bias as towards which is input or output.
+ It's OK to use r8 as scratch.
+
+ Note that the insn doesn't *have* to use Q (128 bit) registers --
+ it can instead mention D (64 bit) and S (32-bit) registers.
+ However, in that case callers of this macro must be very careful to
+ specify QVECREG1NO and QVECREG2NO in such a way as to cover all of
+ the mentioned D and S registers, using the relations
+
+ D<n> == S<2n+1> and S<2n>
+ Q<n> == D<2n+1> and D<2n>
+
+ Failing to do so correctly will make the test meaningless, because
+ it will potentially load test data into the wrong registers before
+ the test, and/or show the values of the wrong registers after the
+ test. The allowed register values are:
+ S: 0 .. 31
+ D: 0 .. 31
+ Q: 0 .. 15
+ Note that Q[15..0] == D[31..0] but S[31..0] only overlaps Q[0..7],
+ so a Q value of 8 or above is definitely invalid for a S register.
+ None of this is checked, though, so be careful when creating the
+ Q numbers.
+
+ It would be clearer and easier to write the Q numbers using integer
+ division. For example, in
+
+ GEN_TWOVEC_QDS_TEST(vcvtn_s32_f64, "vcvtn.s32.f64 s27, d5", 6,2)
+
+ instead of writing "6, 2" at the end, write "(27/4), (5/2)". This
+ would make clear the connection between the register numbers and
+ the Q numbers. Unfortunately those expressions need to expanded to
+ single digits at C-preprocessing time, and cpp won't do that. So
+ we have to do it the hard and error-prone way.
+*/
+#define GEN_TWOVEC_QDS_TEST(TESTNAME,INSN_PRE,INSN, \
+ QVECREG1NO,QVECREG2NO) \
+ __attribute__((noinline)) \
+ static void test_##TESTNAME ( LaneTy ty ) { \
+ Int i; \
+ assert(QVECREG1NO >= 0 && QVECREG1NO <= 15); \
+ assert(QVECREG2NO >= 0 && QVECREG2NO <= 15); \
+ for (i = 0; i < ITERS; i++) { \
+ V128 block[4+1]; \
+ memset(block, 0x55, sizeof(block)); \
+ randV128(&block[0], ty); \
+ randV128(&block[1], ty); \
+ randV128(&block[2], ty); \
+ randV128(&block[3], ty); \
+ __asm__ __volatile__( \
+ "mov r9, #0 ; vmsr fpscr, r9 ; " \
+ "msr apsr_nzcvq, r9 ; " \
+ "add r9, %0, #0 ; vld1.8 { q"#QVECREG1NO" }, [r9] ; " \
+ "add r9, %0, #16 ; vld1.8 { q"#QVECREG2NO" }, [r9] ; " \
+ INSN_PRE INSN " ; " \
+ "add r9, %0, #32 ; vst1.8 { q"#QVECREG1NO" }, [r9] ; " \
+ "add r9, %0, #48 ; vst1.8 { q"#QVECREG2NO" }, [r9] ; " \
+ "vmrs r9, fpscr ; str r9, [%0, #64] " \
+ : : "r"(&block[0]) \
+ : "cc", "memory", "q"#QVECREG1NO, "q"#QVECREG2NO, "r8", "r9" \
+ ); \
+ /* Don't use INSN_PRE in printing, since that differs */ \
+ /* between ARM and Thumb and hence makes their outputs differ. */ \
+ printf(INSN " "); \
+ UInt fpscr = 0xFFFFFFE0 & block[4].u32[0]; \
+ showV128(&block[0]); printf(" "); \
+ showV128(&block[1]); printf(" "); \
+ showV128(&block[2]); printf(" "); \
+ showV128(&block[3]); printf(" fpscr=%08x\n", fpscr); \
+ } \
+ }
+
+
+/* Generate a test that involves three vector regs,
+ with no bias as towards which is input or output. It's also OK
+ to use r8 as scratch. */
+#define GEN_THREEVEC_QDS_TEST(TESTNAME,INSN_PRE, \
+ INSN,QVECREG1NO,QVECREG2NO,QVECREG3NO) \
+ __attribute__((noinline)) \
+ static void test_##TESTNAME ( LaneTy ty ) { \
+ Int i; \
+ assert(QVECREG1NO >= 0 && QVECREG1NO <= 15); \
+ assert(QVECREG2NO >= 0 && QVECREG2NO <= 15); \
+ assert(QVECREG3NO >= 0 && QVECREG3NO <= 15); \
+ for (i = 0; i < ITERS; i++) { \
+ V128 block[6+1]; \
+ memset(block, 0x55, sizeof(block)); \
+ randV128(&block[0], ty); \
+ randV128(&block[1], ty); \
+ randV128(&block[2], ty); \
+ randV128(&block[3], ty); \
+ randV128(&block[4], ty); \
+ randV128(&block[5], ty); \
+ __asm__ __volatile__( \
+ "mov r9, #0 ; vmsr fpscr, r9 ; " \
+ "msr apsr_nzcvq, r9 ; " \
+ "add r9, %0, #0 ; vld1.8 { q"#QVECREG1NO" }, [r9] ; " \
+ "add r9, %0, #16 ; vld1.8 { q"#QVECREG2NO" }, [r9] ; " \
+ "add r9, %0, #32 ; vld1.8 { q"#QVECREG3NO" }, [r9] ; " \
+ INSN_PRE INSN " ; " \
+ "add r9, %0, #48 ; vst1.8 { q"#QVECREG1NO" }, [r9] ; " \
+ "add r9, %0, #64 ; vst1.8 { q"#QVECREG2NO" }, [r9] ; " \
+ "add r9, %0, #80 ; vst1.8 { q"#QVECREG3NO" }, [r9] ; " \
+ "vmrs r9, fpscr ; str r9, [%0, #96] " \
+ : : "r"(&block[0]) \
+ : "cc", "memory", "q"#QVECREG1NO, "q"#QVECREG2NO, "q"#QVECREG3NO, \
+ "r8", "r9" \
+ ); \
+ /* Don't use INSN_PRE in printing, since that differs */ \
+ /* between ARM and Thumb and hence makes their outputs differ. */ \
+ printf(INSN " "); \
+ UInt fpscr = 0xFFFFFFE0 & block[6].u32[0]; \
+ showV128(&block[0]); printf(" "); \
+ showV128(&block[1]); printf(" "); \
+ showV128(&block[2]); printf(" "); \
+ showV128(&block[3]); printf(" "); \
+ showV128(&block[4]); printf(" "); \
+ showV128(&block[5]); printf(" fpscr=%08x\n", fpscr); \
+ } \
+ }
+
+GEN_THREEVEC_QDS_TEST(vselge_f32, IT_AL, "vselge.f32 s15,s16,s20", 3,4,5)
+GEN_THREEVEC_QDS_TEST(vselge_f64, IT_AL, "vselge.f64 d7, d8, d10", 3,4,5)
+
+GEN_THREEVEC_QDS_TEST(vselgt_f32, IT_AL, "vselgt.f32 s15,s16,s20", 3,4,5)
+GEN_THREEVEC_QDS_TEST(vselgt_f64, IT_AL, "vselgt.f64 d7, d8, d10", 3,4,5)
+
+GEN_THREEVEC_QDS_TEST(vseleq_f32, IT_AL, "vseleq.f32 s15,s16,s20", 3,4,5)
+GEN_THREEVEC_QDS_TEST(vseleq_f64, IT_AL, "vseleq.f64 d7, d8, d10", 3,4,5)
+
+GEN_THREEVEC_QDS_TEST(vselvs_f32, IT_AL, "vselvs.f32 s15,s16,s20", 3,4,5)
+GEN_THREEVEC_QDS_TEST(vselvs_f64, IT_AL, "vselvs.f64 d7, d8, d10", 3,4,5)
+
+GEN_THREEVEC_QDS_TEST(vmaxnm_f32, IT_AL, "vmaxnm.f32 s15,s16,s20", 3,4,5)
+GEN_THREEVEC_QDS_TEST(vmaxnm_f64, IT_AL, "vmaxnm.f64 d7, d8, d10", 3,4,5)
+
+GEN_THREEVEC_QDS_TEST(vminnm_f32, IT_AL, "vminnm.f32 s15,s16,s20", 3,4,5)
+GEN_THREEVEC_QDS_TEST(vminnm_f64, IT_AL, "vminnm.f64 d7, d8, d10", 3,4,5)
+
+GEN_TWOVEC_QDS_TEST(vcvtn_s32_f64, IT_AL, "vcvtn.s32.f64 s27, d5", 6,2)
+GEN_TWOVEC_QDS_TEST(vcvta_s32_f64, IT_AL, "vcvta.s32.f64 s4, d20", 1,10)
+GEN_TWOVEC_QDS_TEST(vcvtp_s32_f64, IT_AL, "vcvtp.s32.f64 s7, d31", 1,15)
+GEN_TWOVEC_QDS_TEST(vcvtm_s32_f64, IT_AL, "vcvtm.s32.f64 s1, d0", 0,0)
+
+GEN_TWOVEC_QDS_TEST(vcvtn_s32_f32, IT_AL, "vcvtn.s32.f32 s27, s5", 6,1)
+GEN_TWOVEC_QDS_TEST(vcvta_s32_f32, IT_AL, "vcvta.s32.f32 s4, s20", 1,5)
+GEN_TWOVEC_QDS_TEST(vcvtp_s32_f32, IT_AL, "vcvtp.s32.f32 s7, s31", 1,7)
+GEN_TWOVEC_QDS_TEST(vcvtm_s32_f32, IT_AL, "vcvtm.s32.f32 s1, s0", 0,0)
+
+GEN_TWOVEC_QDS_TEST(vcvtn_u32_f64, IT_AL, "vcvtn.u32.f64 s27, d5", 6,2)
+GEN_TWOVEC_QDS_TEST(vcvta_u32_f64, IT_AL, "vcvta.u32.f64 s4, d20", 1,10)
+GEN_TWOVEC_QDS_TEST(vcvtp_u32_f64, IT_AL, "vcvtp.u32.f64 s7, d31", 1,15)
+GEN_TWOVEC_QDS_TEST(vcvtm_u32_f64, IT_AL, "vcvtm.u32.f64 s1, d0", 0,0)
+
+GEN_TWOVEC_QDS_TEST(vcvtn_u32_f32, IT_AL, "vcvtn.u32.f32 s27, s5", 6,1)
+GEN_TWOVEC_QDS_TEST(vcvta_u32_f32, IT_AL, "vcvta.u32.f32 s4, s20", 1,5)
+GEN_TWOVEC_QDS_TEST(vcvtp_u32_f32, IT_AL, "vcvtp.u32.f32 s7, s31", 1,7)
+GEN_TWOVEC_QDS_TEST(vcvtm_u32_f32, IT_AL, "vcvtm.u32.f32 s1, s0", 0,0)
+
+GEN_TWOVEC_QDS_TEST(vcvtb_f64_f16, IT_AL, "vcvtb.f64.f16 d27, s18", 13, 4)
+GEN_TWOVEC_QDS_TEST(vcvtt_f64_f16, IT_AL, "vcvtt.f64.f16 d28, s17", 14, 4)
+
+GEN_TWOVEC_QDS_TEST(vcvtb_f16_f64, IT_AL, "vcvtb.f16.f64 s9, d17", 2, 8)
+GEN_TWOVEC_QDS_TEST(vcvtt_f16_f64, IT_AL, "vcvtt.f16.f64 s8, d27", 2, 13)
+
+GEN_TWOVEC_QDS_TEST(vrintzeq_f64_f64, IT_EQ, "vrintzeq.f64.f64 d0, d9", 0, 4)
+GEN_TWOVEC_QDS_TEST(vrintzne_f64_f64, IT_NE, "vrintzne.f64.f64 d1, d10", 0, 5)
+GEN_TWOVEC_QDS_TEST(vrintzal_f64_f64, IT_AL, "vrintz.f64.f64 d2, d11", 1, 5)
+
+GEN_TWOVEC_QDS_TEST(vrintreq_f64_f64, IT_EQ, "vrintreq.f64.f64 d3, d12", 1, 6)
+GEN_TWOVEC_QDS_TEST(vrintrne_f64_f64, IT_NE, "vrintrne.f64.f64 d4, d13", 2, 6)
+GEN_TWOVEC_QDS_TEST(vrintral_f64_f64, IT_AL, "vrintr.f64.f64 d5, d14", 2, 7)
+
+GEN_TWOVEC_QDS_TEST(vrintxeq_f64_f64, IT_EQ, "vrintxeq.f64.f64 d6, d15", 3, 7)
+GEN_TWOVEC_QDS_TEST(vrintxne_f64_f64, IT_NE, "vrintxne.f64.f64 d7, d16", 3, 8)
+GEN_TWOVEC_QDS_TEST(vrintxal_f64_f64, IT_AL, "vrintx.f64.f64 d8, d8", 4, 4)
+
+GEN_TWOVEC_QDS_TEST(vrintzeq_f32_f32, IT_EQ, "vrintzeq.f32.f32 s0, s9", 0, 2)
+GEN_TWOVEC_QDS_TEST(vrintzne_f32_f32, IT_NE, "vrintzne.f32.f32 s1, s10", 0, 2)
+GEN_TWOVEC_QDS_TEST(vrintzal_f32_f32, IT_AL, "vrintz.f32.f32 s2, s11", 0, 2)
+
+GEN_TWOVEC_QDS_TEST(vrintreq_f32_f32, IT_EQ, "vrintreq.f32.f32 s3, s12", 0, 3)
+GEN_TWOVEC_QDS_TEST(vrintrne_f32_f32, IT_NE, "vrintrne.f32.f32 s4, s13", 1, 3)
+GEN_TWOVEC_QDS_TEST(vrintral_f32_f32, IT_AL, "vrintr.f32.f32 s5, s14", 1, 3)
+
+GEN_TWOVEC_QDS_TEST(vrintxeq_f32_f32, IT_EQ, "vrintxeq.f32.f32 s6, s15", 1, 3)
+GEN_TWOVEC_QDS_TEST(vrintxne_f32_f32, IT_NE, "vrintxne.f32.f32 s7, s16", 1, 4)
+GEN_TWOVEC_QDS_TEST(vrintxal_f32_f32, IT_AL, "vrintx.f32.f32 s8, s8", 2, 2)
+
+GEN_TWOVEC_QDS_TEST(vrintn_f64_f64, IT_AL, "vrintn.f64.f64 d3, d15", 1, 7)
+GEN_TWOVEC_QDS_TEST(vrinta_f64_f64, IT_AL, "vrinta.f64.f64 d6, d18", 3, 9)
+GEN_TWOVEC_QDS_TEST(vrintp_f64_f64, IT_AL, "vrintp.f64.f64 d9, d21", 4, 10)
+GEN_TWOVEC_QDS_TEST(vrintm_f64_f64, IT_AL, "vrintm.f64.f64 d12, d12", 6, 6)
+
+GEN_TWOVEC_QDS_TEST(vrintn_f32_f32, IT_AL, "vrintn.f32.f32 s3, s15", 0, 3)
+GEN_TWOVEC_QDS_TEST(vrinta_f32_f32, IT_AL, "vrinta.f32.f32 s6, s18", 1, 4)
+GEN_TWOVEC_QDS_TEST(vrintp_f32_f32, IT_AL, "vrintp.f32.f32 s9, s21", 2, 5)
+GEN_TWOVEC_QDS_TEST(vrintm_f32_f32, IT_AL, "vrintm.f32.f32 s12, s12", 3, 3)
+
+GEN_THREEVEC_QDS_TEST(vmaxnm_f32_vec64,
+ IT_AL, "vmaxnm.f32 d15,d16,d20", 7,8,10)
+GEN_THREEVEC_QDS_TEST(vmaxnm_f32_vec128,
+ IT_AL, "vmaxnm.f32 q7, q8, q10", 7,8,10)
+
+GEN_THREEVEC_QDS_TEST(vminnm_f32_vec64,
+ IT_AL, "vminnm.f32 d15,d16,d20", 7,8,10)
+GEN_THREEVEC_QDS_TEST(vminnm_f32_vec128,
+ IT_AL, "vminnm.f32 q7, q8, q10", 7,8,10)
+
+GEN_TWOVEC_QDS_TEST(vcvtn_s32_f32_vec64,
+ IT_AL, "vcvtn.s32.f32 d0, d20", 0, 10)
+GEN_TWOVEC_QDS_TEST(vcvta_s32_f32_vec64,
+ IT_AL, "vcvta.s32.f32 d5, d25", 2, 12)
+GEN_TWOVEC_QDS_TEST(vcvtp_s32_f32_vec64,
+ IT_AL, "vcvtp.s32.f32 d10, d30", 5, 15)
+GEN_TWOVEC_QDS_TEST(vcvtm_s32_f32_vec64,
+ IT_AL, "vcvtm.s32.f32 d15, d15", 7, 7)
+
+GEN_TWOVEC_QDS_TEST(vcvtn_s32_f32_vec128,
+ IT_AL, "vcvtn.s32.f32 q15, q0", 15, 0)
+GEN_TWOVEC_QDS_TEST(vcvta_s32_f32_vec128,
+ IT_AL, "vcvta.s32.f32 q14, q1", 14, 1)
+GEN_TWOVEC_QDS_TEST(vcvtp_s32_f32_vec128,
+ IT_AL, "vcvtp.s32.f32 q13, q2", 13, 2)
+GEN_TWOVEC_QDS_TEST(vcvtm_s32_f32_vec128,
+ IT_AL, "vcvtm.s32.f32 q12, q3", 12, 3)
+
+GEN_TWOVEC_QDS_TEST(vcvtn_u32_f32_vec64,
+ IT_AL, "vcvtn.u32.f32 d0, d20", 0, 10)
+GEN_TWOVEC_QDS_TEST(vcvta_u32_f32_vec64,
+ IT_AL, "vcvta.u32.f32 d5, d25", 2, 12)
+GEN_TWOVEC_QDS_TEST(vcvtp_u32_f32_vec64,
+ IT_AL, "vcvtp.u32.f32 d10, d30", 5, 15)
+GEN_TWOVEC_QDS_TEST(vcvtm_u32_f32_vec64,
+ IT_AL, "vcvtm.u32.f32 d15, d15", 7, 7)
+
+GEN_TWOVEC_QDS_TEST(vcvtn_u32_f32_vec128,
+ IT_AL, "vcvtn.u32.f32 q15, q0", 15, 0)
+GEN_TWOVEC_QDS_TEST(vcvta_u32_f32_vec128,
+ IT_AL, "vcvta.u32.f32 q14, q1", 14, 1)
+GEN_TWOVEC_QDS_TEST(vcvtp_u32_f32_vec128,
+ IT_AL, "vcvtp.u32.f32 q13, q2", 13, 2)
+GEN_TWOVEC_QDS_TEST(vcvtm_u32_f32_vec128,
+ IT_AL, "vcvtm.u32.f32 q12, q3", 12, 3)
+
+GEN_TWOVEC_QDS_TEST(vrintn_f32_f32_vec64,
+ IT_AL, "vrintn.f32.f32 d0, d18", 0, 9)
+GEN_TWOVEC_QDS_TEST(vrinta_f32_f32_vec64,
+ IT_AL, "vrinta.f32.f32 d3, d21", 1, 10)
+GEN_TWOVEC_QDS_TEST(vrintp_f32_f32_vec64,
+ IT_AL, "vrintp.f32.f32 d6, d24", 3, 12)
+GEN_TWOVEC_QDS_TEST(vrintm_f32_f32_vec64,
+ IT_AL, "vrintm.f32.f32 d9, d27", 4, 13)
+GEN_TWOVEC_QDS_TEST(vrintz_f32_f32_vec64,
+ IT_AL, "vrintz.f32.f32 d12, d30", 6, 15)
+GEN_TWOVEC_QDS_TEST(vrintx_f32_f32_vec64,
+ IT_AL, "vrintx.f32.f32 d15, d15", 7, 7)
+
+GEN_TWOVEC_QDS_TEST(vrintn_f32_f32_vec128,
+ IT_AL, "vrintn.f32.f32 q0, q2", 0, 2)
+GEN_TWOVEC_QDS_TEST(vrinta_f32_f32_vec128,
+ IT_AL, "vrinta.f32.f32 q3, q5", 3, 5)
+GEN_TWOVEC_QDS_TEST(vrintp_f32_f32_vec128,
+ IT_AL, "vrintp.f32.f32 q6, q8", 6, 8)
+GEN_TWOVEC_QDS_TEST(vrintm_f32_f32_vec128,
+ IT_AL, "vrintm.f32.f32 q9, q11", 9, 11)
+GEN_TWOVEC_QDS_TEST(vrintz_f32_f32_vec128,
+ IT_AL, "vrintz.f32.f32 q12, q14", 12, 14)
+GEN_TWOVEC_QDS_TEST(vrintx_f32_f32_vec128,
+ IT_AL, "vrintx.f32.f32 q15, q15", 15, 15)
+
+int main ( void )
+{
+ if (1) DO50( test_vselge_f32(TySF) );
+ if (1) DO50( test_vselge_f64(TyDF) );
+
+ if (1) DO50( test_vselgt_f32(TySF) );
+ if (1) DO50( test_vselgt_f64(TyDF) );
+
+ if (1) DO50( test_vseleq_f32(TySF) );
+ if (1) DO50( test_vseleq_f64(TyDF) );
+
+ if (1) DO50( test_vselvs_f32(TySF) );
+ if (1) DO50( test_vselvs_f64(TyDF) );
+
+ if (1) DO50( test_vmaxnm_f32(TySF) );
+ if (1) DO50( test_vmaxnm_f64(TyDF) );
+
+ if (1) DO50( test_vminnm_f32(TySF) );
+ if (1) DO50( test_vminnm_f64(TyDF) );
+
+ if (1) DO50( test_vcvtn_s32_f64(TyDF) );
+ if (1) DO50( test_vcvta_s32_f64(TyDF) );
+ if (1) DO50( test_vcvtp_s32_f64(TyDF) );
+ if (1) DO50( test_vcvtm_s32_f64(TyDF) );
+
+ if (1) DO50( test_vcvtn_s32_f32(TySF) );
+ if (1) DO50( test_vcvta_s32_f32(TySF) );
+ if (1) DO50( test_vcvtp_s32_f32(TySF) );
+ if (1) DO50( test_vcvtm_s32_f32(TySF) );
+
+ if (1) DO50( test_vcvtn_u32_f64(TyDF) );
+ if (1) DO50( test_vcvta_u32_f64(TyDF) );
+ if (1) DO50( test_vcvtp_u32_f64(TyDF) );
+ if (1) DO50( test_vcvtm_u32_f64(TyDF) );
+
+ if (1) DO50( test_vcvtn_u32_f32(TySF) );
+ if (1) DO50( test_vcvta_u32_f32(TySF) );
+ if (1) DO50( test_vcvtp_u32_f32(TySF) );
+ if (1) DO50( test_vcvtm_u32_f32(TySF) );
+
+ if (0) DO50( test_vcvtb_f64_f16(TyDF) );
+ if (0) DO50( test_vcvtt_f64_f16(TyDF) );
+
+ if (0) DO50( test_vcvtb_f16_f64(TyHF) );
+ if (0) DO50( test_vcvtt_f16_f64(TyHF) );
+
+ if (1) DO50( test_vrintzeq_f64_f64(TyDF) );
+ if (1) DO50( test_vrintzne_f64_f64(TyDF) );
+ if (1) DO50( test_vrintzal_f64_f64(TyDF) );
+
+ if (1) DO50( test_vrintreq_f64_f64(TyDF) );
+ if (1) DO50( test_vrintrne_f64_f64(TyDF) );
+ if (1) DO50( test_vrintral_f64_f64(TyDF) );
+
+ if (1) DO50( test_vrintxeq_f64_f64(TyDF) );
+ if (1) DO50( test_vrintxne_f64_f64(TyDF) );
+ if (1) DO50( test_vrintxal_f64_f64(TyDF) );
+
+ if (1) DO50( test_vrintzeq_f32_f32(TySF) );
+ if (1) DO50( test_vrintzne_f32_f32(TySF) );
+ if (1) DO50( test_vrintzal_f32_f32(TySF) );
+
+ if (1) DO50( test_vrintreq_f32_f32(TySF) );
+ if (1) DO50( test_vrintrne_f32_f32(TySF) );
+ if (1) DO50( test_vrintral_f32_f32(TySF) );
+
+ if (1) DO50( test_vrintxeq_f32_f32(TySF) );
+ if (1) DO50( test_vrintxne_f32_f32(TySF) );
+ if (1) DO50( test_vrintxal_f32_f32(TySF) );
+
+ if (1) DO50( test_vrintn_f64_f64(TyDF) );
+ if (1) DO50( test_vrinta_f64_f64(TyDF) );
+ if (1) DO50( test_vrintp_f64_f64(TyDF) );
+ if (1) DO50( test_vrintm_f64_f64(TyDF) );
+
+ if (1) DO50( test_vrintn_f32_f32(TySF) );
+ if (1) DO50( test_vrinta_f32_f32(TySF) );
+ if (1) DO50( test_vrintp_f32_f32(TySF) );
+ if (1) DO50( test_vrintm_f32_f32(TySF) );
+
+ if (1) DO50( test_vmaxnm_f32_vec64(TySF) );
+ if (1) DO50( test_vmaxnm_f32_vec128(TySF) );
+
+ if (1) DO50( test_vminnm_f32_vec64(TySF) );
+ if (1) DO50( test_vminnm_f32_vec128(TySF) );
+
+ if (1) DO50( test_vcvtn_s32_f32_vec64(TySF) );
+ if (1) DO50( test_vcvta_s32_f32_vec64(TySF) );
+ if (1) DO50( test_vcvtp_s32_f32_vec64(TySF) );
+ if (1) DO50( test_vcvtm_s32_f32_vec64(TySF) );
+
+ if (1) DO50( test_vcvtn_s32_f32_vec128(TySF) );
+ if (1) DO50( test_vcvta_s32_f32_vec128(TySF) );
+ if (1) DO50( test_vcvtp_s32_f32_vec128(TySF) );
+ if (1) DO50( test_vcvtm_s32_f32_vec128(TySF) );
+
+ if (1) DO50( test_vcvtn_u32_f32_vec64(TySF) );
+ if (1) DO50( test_vcvta_u32_f32_vec64(TySF) );
+ if (1) DO50( test_vcvtp_u32_f32_vec64(TySF) );
+ if (1) DO50( test_vcvtm_u32_f32_vec64(TySF) );
+
+ if (1) DO50( test_vcvtn_u32_f32_vec128(TySF) );
+ if (1) DO50( test_vcvta_u32_f32_vec128(TySF) );
+ if (1) DO50( test_vcvtp_u32_f32_vec128(TySF) );
+ if (1) DO50( test_vcvtm_u32_f32_vec128(TySF) );
+
+ if (1) DO50( test_vrintn_f32_f32_vec64(TySF) );
+ if (1) DO50( test_vrinta_f32_f32_vec64(TySF) );
+ if (1) DO50( test_vrintp_f32_f32_vec64(TySF) );
+ if (1) DO50( test_vrintm_f32_f32_vec64(TySF) );
+ if (1) DO50( test_vrintz_f32_f32_vec64(TySF) );
+ if (1) DO50( test_vrintx_f32_f32_vec64(TySF) );
+
+ if (1) DO50( test_vrintn_f32_f32_vec128(TySF) );
+ if (1) DO50( test_vrinta_f32_f32_vec128(TySF) );
+ if (1) DO50( test_vrintp_f32_f32_vec128(TySF) );
+ if (1) DO50( test_vrintm_f32_f32_vec128(TySF) );
+ if (1) DO50( test_vrintz_f32_f32_vec128(TySF) );
+ if (1) DO50( test_vrintx_f32_f32_vec128(TySF) );
+
+ return 0;
+}
diff --git a/none/tests/arm/v8fpsimd_t.stderr.exp b/none/tests/arm/v8fpsimd_t.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/arm/v8fpsimd_t.stderr.exp
diff --git a/none/tests/arm/v8fpsimd_t.stdout.exp b/none/tests/arm/v8fpsimd_t.stdout.exp
new file mode 100644
index 0000000..b7ea1b3
--- /dev/null
+++ b/none/tests/arm/v8fpsimd_t.stdout.exp
@@ -0,0 +1,6763 @@
+randV128: doing v->u32[3] = v->u32[2]
+vselge.f32 s15,s16,s20 5175e39d19c9ca1e98f24a4984175700 c5fa956ac5fa956a0d69c3e9a6af27d1 56a044b260b160857d45c48447b8d8c0 a6af27d119c9ca1e98f24a4984175700 c5fa956ac5fa956a0d69c3e9a6af27d1 56a044b260b160857d45c48447b8d8c0 fpscr=00000000
+vselge.f32 s15,s16,s20 d740b80eb7839b97d89998df5035ed36 db56b01a12b0ca1583cb509970b8136c 191fd3a727d1a705f65df9dd4a29f8c0 70b8136cb7839b97d89998df5035ed36 db56b01a12b0ca1583cb509970b8136c 191fd3a727d1a705f65df9dd4a29f8c0 fpscr=00000000
+vselge.f32 s15,s16,s20 b536bbe4da8a369dab4f9465b86ed182 7b8d9035449b06f4e06e2205236eb768 95264321bf3b68b255c2b9e2c95c9810 236eb768da8a369dab4f9465b86ed182 7b8d9035449b06f4e06e2205236eb768 95264321bf3b68b255c2b9e2c95c9810 fpscr=00000000
+vselge.f32 s15,s16,s20 e13dfe910a3e0f7c75cb0842b95ed64d fcb0ebfe6ee98ebd1ca893312a54cae7 5b2d5a70a7920a5f45c55f1c9202b76d 2a54cae70a3e0f7c75cb0842b95ed64d fcb0ebfe6ee98ebd1ca893312a54cae7 5b2d5a70a7920a5f45c55f1c9202b76d fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vselge.f32 s15,s16,s20 a86aacf29b0f395c98b463483da65c8c c3ec352e2dac0350f6fd1ca81b6e33c5 e9bf6f37c9e25f72d82e582b73a8f718 1b6e33c59b0f395c98b463483da65c8c c3ec352e2dac0350f6fd1ca81b6e33c5 e9bf6f37c9e25f72d82e582b73a8f718 fpscr=00000000
+vselge.f32 s15,s16,s20 36da9dbf68bc3026343700a654eb2ddd 810e6dc1a1833d8404eb7f0cf4ca6fee b39925ba7d9d67bcff6f850f2c57ea2a f4ca6fee68bc3026343700a654eb2ddd 810e6dc1a1833d8404eb7f0cf4ca6fee b39925ba7d9d67bcff6f850f2c57ea2a fpscr=00000000
+vselge.f32 s15,s16,s20 01737fd22bfa8f668c8b14f436b2a38d 097df30b8daa927a03090dfc6df078b6 6d498492e7e796df010bf4b23b845743 6df078b62bfa8f668c8b14f436b2a38d 097df30b8daa927a03090dfc6df078b6 6d498492e7e796df010bf4b23b845743 fpscr=00000000
+vselge.f32 s15,s16,s20 985e6d08ed19fa045f841810cd8c109e 7bc0131c4a678450562685769ab818a5 8afcb3dfb984aed62671e865e6f21d40 9ab818a5ed19fa045f841810cd8c109e 7bc0131c4a678450562685769ab818a5 8afcb3dfb984aed62671e865e6f21d40 fpscr=00000000
+vselge.f32 s15,s16,s20 c51cdd8f87e12ab4acb722146c6cbfa9 63d7568e3e8a3ac80e048612e51a468e bdf58de2b4a9d799ff5f0c05cb6ebd12 e51a468e87e12ab4acb722146c6cbfa9 63d7568e3e8a3ac80e048612e51a468e bdf58de2b4a9d799ff5f0c05cb6ebd12 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vselge.f32 s15,s16,s20 fd8f4d8698c2cb9dfb4ea5d187136489 575775bc3a12029d8e66ea903a12029d e85ef9754842f9c9ba28f82a63b15c68 3a12029d98c2cb9dfb4ea5d187136489 575775bc3a12029d8e66ea903a12029d e85ef9754842f9c9ba28f82a63b15c68 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vselge.f32 s15,s16,s20 964fbba0b8d508aebee85fda964fbba0 6809217c310baca0c3837be65197abe2 c0f55f706da71bf2425f9605e2b252c1 5197abe2b8d508aebee85fda964fbba0 6809217c310baca0c3837be65197abe2 c0f55f706da71bf2425f9605e2b252c1 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vselge.f32 s15,s16,s20 0c65c22b4ab8778d9ed6d9eb46ea8ca3 82c1007a7d3cd8f54b130cdaa89cef0e 627bb6e12d1f6d4651ef145cb9b83843 a89cef0e4ab8778d9ed6d9eb46ea8ca3 82c1007a7d3cd8f54b130cdaa89cef0e 627bb6e12d1f6d4651ef145cb9b83843 fpscr=00000000
+vselge.f32 s15,s16,s20 3b25bca27a9c69505d14b27d9d16f25b fbbab6a7f19faff0f1798fe3c1699cf0 9f7301c1392d8087d4ba52a206ff21b1 c1699cf07a9c69505d14b27d9d16f25b fbbab6a7f19faff0f1798fe3c1699cf0 9f7301c1392d8087d4ba52a206ff21b1 fpscr=00000000
+vselge.f32 s15,s16,s20 0352a3d92d460a61a5dd0f6f47086cc3 2e9360315bf0177599dbe14b4616559e 3e9e2b92eef2c569453ccd1b0fc40784 4616559e2d460a61a5dd0f6f47086cc3 2e9360315bf0177599dbe14b4616559e 3e9e2b92eef2c569453ccd1b0fc40784 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselge.f32 s15,s16,s20 0facd2b3c4044ef23fb2e22093a48a9d fac555adddf0eb4808f06704c857e949 812abdb289fba268812abdb21e4a9e09 c857e949c4044ef23fb2e22093a48a9d fac555adddf0eb4808f06704c857e949 812abdb289fba268812abdb21e4a9e09 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vselge.f32 s15,s16,s20 835e3ede9a220dce0e75e07acb193b9a 3ea20cc00420edac31a0d5992573776d 1e6559138591810713013cc685918107 2573776d9a220dce0e75e07acb193b9a 3ea20cc00420edac31a0d5992573776d 1e6559138591810713013cc685918107 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[0]
+vselge.f32 s15,s16,s20 16ee9afa99500fef6024ba39dce32c23 49e54740570037914d04ab3d57003791 16257132a9f8030aa0dc273ba9f8030a 5700379199500fef6024ba39dce32c23 49e54740570037914d04ab3d57003791 16257132a9f8030aa0dc273ba9f8030a fpscr=00000000
+vselge.f32 s15,s16,s20 865de41295f2db8f44cbbf37e2bc70c3 15ff8f2e73a3a0fae06860b606c7e8c7 4428d9c8833f5b78fb29445f3bc8d7fc 06c7e8c795f2db8f44cbbf37e2bc70c3 15ff8f2e73a3a0fae06860b606c7e8c7 4428d9c8833f5b78fb29445f3bc8d7fc fpscr=00000000
+vselge.f32 s15,s16,s20 f5d7c0f9da7f07e00794eb00b0940ba5 8e212ab7be625608d5abd787f5c90ee7 861576e44fac8dd5bbc503330eb9dd5d f5c90ee7da7f07e00794eb00b0940ba5 8e212ab7be625608d5abd787f5c90ee7 861576e44fac8dd5bbc503330eb9dd5d fpscr=00000000
+vselge.f32 s15,s16,s20 d33d431279cce48fce3d3cc0784c2f85 b1ef0b40d58cb22d00b1125934a781e4 e7467c38bb69a6e1e9a617d4d14e5927 34a781e479cce48fce3d3cc0784c2f85 b1ef0b40d58cb22d00b1125934a781e4 e7467c38bb69a6e1e9a617d4d14e5927 fpscr=00000000
+vselge.f32 s15,s16,s20 b9433f079dacacabeb000208c9029669 20162517609f0f22a1a7a4c9c0a51f6b f763e279a20368bc8bdb3b370954bcbf c0a51f6b9dacacabeb000208c9029669 20162517609f0f22a1a7a4c9c0a51f6b f763e279a20368bc8bdb3b370954bcbf fpscr=00000000
+vselge.f32 s15,s16,s20 60926235021b445ef059e641a1ccb097 136b941e54ffe81c9c7740ef19345795 6930e0fad3ba39c483bd1e68fb03f57b 19345795021b445ef059e641a1ccb097 136b941e54ffe81c9c7740ef19345795 6930e0fad3ba39c483bd1e68fb03f57b fpscr=00000000
+vselge.f32 s15,s16,s20 677f96a350623139cb7207e36cbf75aa 5f927f2b383caf8484c5f3078d2aded7 31aa6a1e5e366d4c1cd56194c94a4e2c 8d2aded750623139cb7207e36cbf75aa 5f927f2b383caf8484c5f3078d2aded7 31aa6a1e5e366d4c1cd56194c94a4e2c fpscr=00000000
+vselge.f32 s15,s16,s20 ed4f4db5a9377eb31749ef710cf75788 924816791f1030333fb8fa4b2feb05cb 99bb3fa4c2385e4166df2141ad63a876 2feb05cba9377eb31749ef710cf75788 924816791f1030333fb8fa4b2feb05cb 99bb3fa4c2385e4166df2141ad63a876 fpscr=00000000
+vselge.f32 s15,s16,s20 8f1ee978efa4b054d2bc36ca100a4a3a b4e706a17746411ab40c9f043af6a1ae 88ae0d34fa174f9ce927c476f140aa41 3af6a1aeefa4b054d2bc36ca100a4a3a b4e706a17746411ab40c9f043af6a1ae 88ae0d34fa174f9ce927c476f140aa41 fpscr=00000000
+vselge.f32 s15,s16,s20 cd123e19cf1e2bb001f1161e946f5ca7 d5f13a9ab645e140698bec649583f5aa 5a5e86033374552e23ce8e2455e0205c 9583f5aacf1e2bb001f1161e946f5ca7 d5f13a9ab645e140698bec649583f5aa 5a5e86033374552e23ce8e2455e0205c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vselge.f32 s15,s16,s20 cf82c7aff819714a711ce1284318b884 a88e7b2818210760c299b42e1fdcc2e9 2ef114ddd37570e82d39fd95a9f5a45d 1fdcc2e9f819714a711ce1284318b884 a88e7b2818210760c299b42e1fdcc2e9 2ef114ddd37570e82d39fd95a9f5a45d fpscr=00000000
+vselge.f32 s15,s16,s20 0a9c61f55fce335d68e1a25652a804a7 1dd493f59184345437d5e366d0e20c30 81c50f1401e45b82d3086a7a39a1e621 d0e20c305fce335d68e1a25652a804a7 1dd493f59184345437d5e366d0e20c30 81c50f1401e45b82d3086a7a39a1e621 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[0]
+vselge.f32 s15,s16,s20 370813738219ffced22c62cba0822c4c 7c7642a20df9d4ec68f21f468712f7b8 bba1a11cc04c89478209dbbd84d92508 8712f7b88219ffced22c62cba0822c4c 7c7642a20df9d4ec68f21f468712f7b8 bba1a11cc04c89478209dbbd84d92508 fpscr=00000000
+vselge.f32 s15,s16,s20 291541139c8b1cd0d1a11d81326f4e78 44c930c9028972f8733d11f7fa4450de b8ddd8a1cd852d9cd970502d146432e6 fa4450de9c8b1cd0d1a11d81326f4e78 44c930c9028972f8733d11f7fa4450de b8ddd8a1cd852d9cd970502d146432e6 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vselge.f32 s15,s16,s20 470887bfdd3daf94d7265949ca62b46a d3a0a41fce854ae735e7926e777aa43f b3ef9f8c927c405d2fb2ed4ecc1e172d 777aa43fdd3daf94d7265949ca62b46a d3a0a41fce854ae735e7926e777aa43f b3ef9f8c927c405d2fb2ed4ecc1e172d fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+vselge.f32 s15,s16,s20 cdc14f0bcdc14f0bf7ba2283e22a3104 4e0cf0fdf0aee1dda4e888e2774acbc1 61e618f30110c432a534d0478d5d7e05 774acbc1cdc14f0bf7ba2283e22a3104 4e0cf0fdf0aee1dda4e888e2774acbc1 61e618f30110c432a534d0478d5d7e05 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[3]
+vselge.f32 s15,s16,s20 57805ff098ce3ed14b62bbc77143b71e 0d2c018b8415100484151004ff355bf0 11edd5a106e2d655f9b97953917f469f ff355bf098ce3ed14b62bbc77143b71e 0d2c018b8415100484151004ff355bf0 11edd5a106e2d655f9b97953917f469f fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vselge.f32 s15,s16,s20 d5da99d2eec5040fc700120f62ee9b23 bc58f8b23fcabf6982b029b396ea4f1e 7d2c86fa7c09a37b813bf15120fbc868 96ea4f1eeec5040fc700120f62ee9b23 bc58f8b23fcabf6982b029b396ea4f1e 7d2c86fa7c09a37b813bf15120fbc868 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[1]
+vselge.f32 s15,s16,s20 c997070e67232e66c997070e860c39c5 5073109cfa471afbe686e2ede96f8809 4df8929c4e1bb03ba56adb474e1bb03b e96f880967232e66c997070e860c39c5 5073109cfa471afbe686e2ede96f8809 4df8929c4e1bb03ba56adb474e1bb03b fpscr=00000000
+vselge.f32 s15,s16,s20 59f634f791559ff8d881612a1f00ed91 1add7938e3067d74917c37833edb866b b3448c8c9a654f1c8c8db3b639e1fba1 3edb866b91559ff8d881612a1f00ed91 1add7938e3067d74917c37833edb866b b3448c8c9a654f1c8c8db3b639e1fba1 fpscr=00000000
+vselge.f32 s15,s16,s20 4cb8e76fcc086aeb0414a9cd126c0869 7b85bbd973ba438b80fdb556878af3ad a6cb98bf6fa194a173e020c0ede3baf2 878af3adcc086aeb0414a9cd126c0869 7b85bbd973ba438b80fdb556878af3ad a6cb98bf6fa194a173e020c0ede3baf2 fpscr=00000000
+vselge.f32 s15,s16,s20 65b86284a1cb27a371a4885bc70f501c 2468a718ec4422710c95a6e59e2a7fab bfaf26fbc229d962e2d7a20cab554a62 9e2a7faba1cb27a371a4885bc70f501c 2468a718ec4422710c95a6e59e2a7fab bfaf26fbc229d962e2d7a20cab554a62 fpscr=00000000
+vselge.f32 s15,s16,s20 ad8f313a964967940f284cfce9a33028 738ec585d726b8f4ecb95e02f1d179e3 af5de4ddb013d258a082f55bbf17ae91 f1d179e3964967940f284cfce9a33028 738ec585d726b8f4ecb95e02f1d179e3 af5de4ddb013d258a082f55bbf17ae91 fpscr=00000000
+vselge.f32 s15,s16,s20 d04c2dd1910bd9cf5599014e9dc435b3 95b85f1c30562ca02ba32b169299fd64 09cb539549408a57d0e8a18b5417adc6 9299fd64910bd9cf5599014e9dc435b3 95b85f1c30562ca02ba32b169299fd64 09cb539549408a57d0e8a18b5417adc6 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselge.f32 s15,s16,s20 4954977124406c74e81e7aa9430469f9 d9438203e383314ed9438203c8655800 aaba95edd88623fc68d5d5d393ccbadd c865580024406c74e81e7aa9430469f9 d9438203e383314ed9438203c8655800 aaba95edd88623fc68d5d5d393ccbadd fpscr=00000000
+vselge.f32 s15,s16,s20 7d1161203b947b8f0a536415b779aada f56dfe15b7e82632fc79b30f1483e79b b34432fe82493fa5c4d84771e518605a 1483e79b3b947b8f0a536415b779aada f56dfe15b7e82632fc79b30f1483e79b b34432fe82493fa5c4d84771e518605a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: 256 calls, 265 iters
+vselge.f32 s15,s16,s20 36ba0ab0c81fb7053f6b55d4eaedef93 29b247cac4e8bba2bda130508cf3c5a6 9e8fbc053bc4d999db7390839e8fbc05 8cf3c5a6c81fb7053f6b55d4eaedef93 29b247cac4e8bba2bda130508cf3c5a6 9e8fbc053bc4d999db7390839e8fbc05 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vselge.f32 s15,s16,s20 8dbd4545a92ebc1d99f6f68da34afe4e f4dd02230b0b9f6018e987aeba97106b 2f35968b0a9d5fe4af824eabd8f8f577 ba97106ba92ebc1d99f6f68da34afe4e f4dd02230b0b9f6018e987aeba97106b 2f35968b0a9d5fe4af824eabd8f8f577 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselge.f32 s15,s16,s20 3951f70edbe25a9a3951f70e8dc88216 5ee9b286181efe1783322bd1f4a0a92e d4a3445ee5f0714d6ed9d5a9ea9b3880 f4a0a92edbe25a9a3951f70e8dc88216 5ee9b286181efe1783322bd1f4a0a92e d4a3445ee5f0714d6ed9d5a9ea9b3880 fpscr=00000000
+vselge.f32 s15,s16,s20 0c4e5ddd66c8f02281b3c8f26eeb8d90 d9407ecd6355d7239077cddd8edc2316 ddf6d8b991ce01deaf4923243fc0b6d3 8edc231666c8f02281b3c8f26eeb8d90 d9407ecd6355d7239077cddd8edc2316 ddf6d8b991ce01deaf4923243fc0b6d3 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vselge.f32 s15,s16,s20 fa6db7a39486894259f1290efa6db7a3 e3a4469f24fe98dc158b24fec4bafee7 451c6eb3e447d1587d7aa579647d6dc0 c4bafee79486894259f1290efa6db7a3 e3a4469f24fe98dc158b24fec4bafee7 451c6eb3e447d1587d7aa579647d6dc0 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[3]
+vselge.f32 s15,s16,s20 1fc8f3fa1382738f705b685c54d57186 75f5144ccc5e105c99661df92e3cc13e 8597b02c9c423a147ae28aed9c423a14 2e3cc13e1382738f705b685c54d57186 75f5144ccc5e105c99661df92e3cc13e 8597b02c9c423a147ae28aed9c423a14 fpscr=00000000
+vselge.f32 s15,s16,s20 406068505c979f40cdc58392364fbbe2 6feefdf8d22d16a827667197b8d187cb d8c318f5aa57d04b750405c33deba68d b8d187cb5c979f40cdc58392364fbbe2 6feefdf8d22d16a827667197b8d187cb d8c318f5aa57d04b750405c33deba68d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vselge.f32 s15,s16,s20 9f8c3175b6b243e17860dbd798f8ac48 e87ea00ccf8549bf47029a37d75b1941 02f1b3c72ff97f68cd517cb92b46de01 d75b1941b6b243e17860dbd798f8ac48 e87ea00ccf8549bf47029a37d75b1941 02f1b3c72ff97f68cd517cb92b46de01 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 7dea6f8ae74d5f797dea6f8ae74d5f79 4d15989216cc2891c94f65dfccc66f9e 312d32f1bb069e61ab09c2f3335970be c94f65dfccc66f9e7dea6f8ae74d5f79 4d15989216cc2891c94f65dfccc66f9e 312d32f1bb069e61ab09c2f3335970be fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 20326a7d927f8ecd4a783d658932e026 8b97fa553a6508ac8b97fa553a6508ac 470818041ac5e9b218db305838ff3248 8b97fa553a6508ac4a783d658932e026 8b97fa553a6508ac8b97fa553a6508ac 470818041ac5e9b218db305838ff3248 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 18eb39be527594f68adebded1af4c541 78e95f7a8aed8854faa096b85e32ad5a 699f129680a985484a52397b894a4f49 faa096b85e32ad5a8adebded1af4c541 78e95f7a8aed8854faa096b85e32ad5a 699f129680a985484a52397b894a4f49 fpscr=00000000
+vselge.f64 d7, d8, d10 7c44fda2c4f3ed4e66c03150c383fd2d 1e27c81bff702749760afcca34c46a4a e35ab00b3cdf75747e60035ee161b2dd 760afcca34c46a4a66c03150c383fd2d 1e27c81bff702749760afcca34c46a4a e35ab00b3cdf75747e60035ee161b2dd fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 8f72bc6577b145aeabe876d3472e35c6 28f38b2e093fbce08c1f71338e7c577f 5bc30eedfc43f567c87be936badd6630 8c1f71338e7c577fabe876d3472e35c6 28f38b2e093fbce08c1f71338e7c577f 5bc30eedfc43f567c87be936badd6630 fpscr=00000000
+vselge.f64 d7, d8, d10 95df08065206478d94b3ff795f122865 6c7f80e89ebd80a5e34bca20163ac21e c2e06c5cc8e1357d72cece7967d1f50c e34bca20163ac21e94b3ff795f122865 6c7f80e89ebd80a5e34bca20163ac21e c2e06c5cc8e1357d72cece7967d1f50c fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 ac79a338e2ed6bf4b500d2fe8f552735 244c1dcf60e0190c026f4f4108bb97f1 fce910c815b7b5082a07b97ea580d954 026f4f4108bb97f1b500d2fe8f552735 244c1dcf60e0190c026f4f4108bb97f1 fce910c815b7b5082a07b97ea580d954 fpscr=00000000
+vselge.f64 d7, d8, d10 b164b81a015d181eb0d13422c035a6a7 2b0bfdbeddb488c900901dc5368c3595 cf2d05af86747edec1b4c5c4fa8650fe 00901dc5368c3595b0d13422c035a6a7 2b0bfdbeddb488c900901dc5368c3595 cf2d05af86747edec1b4c5c4fa8650fe fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 1d637d751dfa1352e40c986744421113 a6b7393576df5c23d344e7279f0d2317 a06b4f801c40c9e0a06b4f801c40c9e0 d344e7279f0d2317e40c986744421113 a6b7393576df5c23d344e7279f0d2317 a06b4f801c40c9e0a06b4f801c40c9e0 fpscr=00000000
+vselge.f64 d7, d8, d10 c509a7178875c1b1aa5552bf7b541645 e0332c6ed78e2afc4561d270bed6b68a 313cbec68670df4e1ab8e17b2178e568 4561d270bed6b68aaa5552bf7b541645 e0332c6ed78e2afc4561d270bed6b68a 313cbec68670df4e1ab8e17b2178e568 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 9a9e84669a985ec5f0031343f3185309 4ad64de91c16da21aeefac01e48b55d9 fee0b45668b52a09fee0b45668b52a09 aeefac01e48b55d9f0031343f3185309 4ad64de91c16da21aeefac01e48b55d9 fee0b45668b52a09fee0b45668b52a09 fpscr=00000000
+vselge.f64 d7, d8, d10 1a1256ba10a38a2b40833c5f6109ca65 a98a0320fe506fd007449d8620c34d90 310e98e167b9e8f5f99ff99706c8eb8a 07449d8620c34d9040833c5f6109ca65 a98a0320fe506fd007449d8620c34d90 310e98e167b9e8f5f99ff99706c8eb8a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 8f17393d14b564cbe1d0c0b48a0655b1 d04fb16a4d20867d3a5b4dbd6dd8955f d94d188902284fdfd94d188902284fdf 3a5b4dbd6dd8955fe1d0c0b48a0655b1 d04fb16a4d20867d3a5b4dbd6dd8955f d94d188902284fdfd94d188902284fdf fpscr=00000000
+vselge.f64 d7, d8, d10 442729db00c06ec7a888afd71cbfd9a5 a748e3f1cf4820c03b24f10f9cc602e6 ed8c329e49985ce0a08d4e504c0d1ea8 3b24f10f9cc602e6a888afd71cbfd9a5 a748e3f1cf4820c03b24f10f9cc602e6 ed8c329e49985ce0a08d4e504c0d1ea8 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 4ce7b072a07d2e1c4ce7b072a07d2e1c 224c09e6f9f4b7ac224c09e6f9f4b7ac 30603637c27a144a5b20f8ab9814aff9 224c09e6f9f4b7ac4ce7b072a07d2e1c 224c09e6f9f4b7ac224c09e6f9f4b7ac 30603637c27a144a5b20f8ab9814aff9 fpscr=00000000
+vselge.f64 d7, d8, d10 2f46b6a224a9b26dfb35eb12d4ad50bc f46bdce9dd4c503b8c78011defefc04a c3a1b08243033786b7c84ab17d3be225 8c78011defefc04afb35eb12d4ad50bc f46bdce9dd4c503b8c78011defefc04a c3a1b08243033786b7c84ab17d3be225 fpscr=00000000
+vselge.f64 d7, d8, d10 35623ea06909e69bf4ae69f33c480a53 33f2cc7dd6bb9c2cca197db5feb72438 31b5254262bdc16b771596f6d81f3374 ca197db5feb72438f4ae69f33c480a53 33f2cc7dd6bb9c2cca197db5feb72438 31b5254262bdc16b771596f6d81f3374 fpscr=00000000
+vselge.f64 d7, d8, d10 eb0e45f4f7eae27ec0f14ecb50a5fc04 f684562c36ddb9ea8ea8c8d0e79a950e abba23c025e6d5d2e99c2ac801d7a6e2 8ea8c8d0e79a950ec0f14ecb50a5fc04 f684562c36ddb9ea8ea8c8d0e79a950e abba23c025e6d5d2e99c2ac801d7a6e2 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 2c1b224d3e4395de8b5fc46113474bc4 8283f87c7f421f4912638e4626edfac3 beaf642702c9ac2087e109bc0d20ad2c 12638e4626edfac38b5fc46113474bc4 8283f87c7f421f4912638e4626edfac3 beaf642702c9ac2087e109bc0d20ad2c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 23439e5525914b7f6c80ce6328d14c4f 3b879f7ed58417a23b879f7ed58417a2 4ea3f35b274283763483e142978babb4 3b879f7ed58417a26c80ce6328d14c4f 3b879f7ed58417a23b879f7ed58417a2 4ea3f35b274283763483e142978babb4 fpscr=00000000
+vselge.f64 d7, d8, d10 d5f625fee533c9ac40c2027b6ef50219 26cce3d22e428611c200d10412f69ba3 de0fee83708cf6737d9e7877b9a3b333 c200d10412f69ba340c2027b6ef50219 26cce3d22e428611c200d10412f69ba3 de0fee83708cf6737d9e7877b9a3b333 fpscr=00000000
+vselge.f64 d7, d8, d10 e524262020669f6fdacc5d7113531763 b17d7d8194a0538e824a418418f0b958 2737c8cbeddc2b312ce5ddc92aa7904e 824a418418f0b958dacc5d7113531763 b17d7d8194a0538e824a418418f0b958 2737c8cbeddc2b312ce5ddc92aa7904e fpscr=00000000
+vselge.f64 d7, d8, d10 cd19a8f37bb80620d01d92b83e4c403a 6692a424fc88e808604c7cfc2a781815 38b0aec1474b46a8d94636311f444222 604c7cfc2a781815d01d92b83e4c403a 6692a424fc88e808604c7cfc2a781815 38b0aec1474b46a8d94636311f444222 fpscr=00000000
+vselge.f64 d7, d8, d10 5818643e888b037969929732973d033b 797f021438844d02a38f5943215d8ac5 7b9f006ce9dcecb04919610958335bce a38f5943215d8ac569929732973d033b 797f021438844d02a38f5943215d8ac5 7b9f006ce9dcecb04919610958335bce fpscr=00000000
+vselge.f64 d7, d8, d10 c616893fedf747e7e3b7188215a149fe d247bb0dec2ea57f37c5af844c56a6d2 c282024505efe2bb5e680f8bd808d4a0 37c5af844c56a6d2e3b7188215a149fe d247bb0dec2ea57f37c5af844c56a6d2 c282024505efe2bb5e680f8bd808d4a0 fpscr=00000000
+vselge.f64 d7, d8, d10 20e1106551b53bb68b07cdad1dcc957f 368e1cc3188fca46c4038221f7f38807 ce16f2bacbea6990f0908c45fcf43e06 c4038221f7f388078b07cdad1dcc957f 368e1cc3188fca46c4038221f7f38807 ce16f2bacbea6990f0908c45fcf43e06 fpscr=00000000
+vselge.f64 d7, d8, d10 fcb5b0988ed3ed6fa5a46224d78477c5 debd8d75ea60e0a4508b474b138ad250 4f0c6dd2c295409d0d24fbf1bd35c236 508b474b138ad250a5a46224d78477c5 debd8d75ea60e0a4508b474b138ad250 4f0c6dd2c295409d0d24fbf1bd35c236 fpscr=00000000
+vselge.f64 d7, d8, d10 3bd347680aaab4228a0b10877f5c8727 291397a9ba7f9e19ccd6b6f28eac089f 8eb45934c0c5bf89c26cb8dce73ec9b8 ccd6b6f28eac089f8a0b10877f5c8727 291397a9ba7f9e19ccd6b6f28eac089f 8eb45934c0c5bf89c26cb8dce73ec9b8 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 b10a44033e825486b10a44033e825486 653ab778fcbada2d54bed9dca1146904 9f4d651fe1890b769f4d651fe1890b76 54bed9dca1146904b10a44033e825486 653ab778fcbada2d54bed9dca1146904 9f4d651fe1890b769f4d651fe1890b76 fpscr=00000000
+vselge.f64 d7, d8, d10 c8011cc8a7dc73ed183713208e6e2a22 54ff526986b9c7d9eb61d469d49e0a48 f0846cae958bbf1fe8e9bb56dee959ba eb61d469d49e0a48183713208e6e2a22 54ff526986b9c7d9eb61d469d49e0a48 f0846cae958bbf1fe8e9bb56dee959ba fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 b8782ccb88336084b8782ccb88336084 742ef9b0a22bd197c376de3baf5fdb8c 69c662988b5f5746fb941b276fefe9c6 c376de3baf5fdb8cb8782ccb88336084 742ef9b0a22bd197c376de3baf5fdb8c 69c662988b5f5746fb941b276fefe9c6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 b20c2785c541876db20c2785c541876d 032db762c30b75b069dea946e0b179be 181f0f0b8f5d0353bc2f2ffdc2c55b0f 69dea946e0b179beb20c2785c541876d 032db762c30b75b069dea946e0b179be 181f0f0b8f5d0353bc2f2ffdc2c55b0f fpscr=00000000
+vselge.f64 d7, d8, d10 3c09c110a7a3ccf943504995e94a77e4 d2893ae6ff22b433bbdde4c7ff080c84 f49e747ba1b053546a8f11cbec2196ce bbdde4c7ff080c8443504995e94a77e4 d2893ae6ff22b433bbdde4c7ff080c84 f49e747ba1b053546a8f11cbec2196ce fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 0fa9ad03d399277fd05ca4f26ef8025f 512005ca47f71b72512005ca47f71b72 8f37f9d4b7c27dfe029229e0fac199e9 512005ca47f71b72d05ca4f26ef8025f 512005ca47f71b72512005ca47f71b72 8f37f9d4b7c27dfe029229e0fac199e9 fpscr=00000000
+vselge.f64 d7, d8, d10 fcb4b3e7a908c6d194412d3c5bdb13e5 3155405557892d6649f507b77e997223 aa1a958555027b09baf22fda37cd3760 49f507b77e99722394412d3c5bdb13e5 3155405557892d6649f507b77e997223 aa1a958555027b09baf22fda37cd3760 fpscr=00000000
+randV128: 512 calls, 530 iters
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 d44486b5a6a102107e8ef40422303b1b db5aa202e2121f7aa8d894a9c470d958 326c6c233ef813ba0fe17c5753958e24 a8d894a9c470d9587e8ef40422303b1b db5aa202e2121f7aa8d894a9c470d958 326c6c233ef813ba0fe17c5753958e24 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 d6af490cad91217056d5748db6b4df58 16edd04b278464bc28f0c8ad90647a74 9666b4d4f37549976fb022ffaa75e46d 28f0c8ad90647a7456d5748db6b4df58 16edd04b278464bc28f0c8ad90647a74 9666b4d4f37549976fb022ffaa75e46d fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 ac07cce3ec6d05a4b6a1a4cd9e883257 e901fcadd70937b3956de6fb929444b1 1e83edc02ffa57cb1e83edc02ffa57cb 956de6fb929444b1b6a1a4cd9e883257 e901fcadd70937b3956de6fb929444b1 1e83edc02ffa57cb1e83edc02ffa57cb fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 e04f0d4312973a16fac0656f27a1a7bb 5e17e0b2d6d57a7db0e9535f056177dd b90e2f84fd0f2387b90e2f84fd0f2387 b0e9535f056177ddfac0656f27a1a7bb 5e17e0b2d6d57a7db0e9535f056177dd b90e2f84fd0f2387b90e2f84fd0f2387 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 5e44b0f9e0d5b9fa370241a91527f6b9 011bb2a0f5f10f15717d72120cd2c993 d9dbad27f70c3901ccb48a7230203299 717d72120cd2c993370241a91527f6b9 011bb2a0f5f10f15717d72120cd2c993 d9dbad27f70c3901ccb48a7230203299 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 f7d359b0d13fcfb804169a04d2f81662 6e74cdf571f9829134f3548dd9540466 98627c5eefe64192b7f7857aad810a9a 34f3548dd954046604169a04d2f81662 6e74cdf571f9829134f3548dd9540466 98627c5eefe64192b7f7857aad810a9a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 8d2b6b3e8e322a4ff6b6d1b75f0f9fb4 fe476aa231b0aaf9fe476aa231b0aaf9 fe73fd132e37396917085019174d71f9 fe476aa231b0aaf9f6b6d1b75f0f9fb4 fe476aa231b0aaf9fe476aa231b0aaf9 fe73fd132e37396917085019174d71f9 fpscr=00000000
+vselge.f64 d7, d8, d10 ae6674d2fb42f1655f05df749c5f3646 a78d90ffdc91cea49ae5c06573d83b22 5aaa117e7599eb792f879592071e89e2 9ae5c06573d83b225f05df749c5f3646 a78d90ffdc91cea49ae5c06573d83b22 5aaa117e7599eb792f879592071e89e2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 8de9d387376700458de9d38737670045 5d5cd44e174adb00a0567c2a86afc400 0648ac6426460c1c7493622cfa2597b6 a0567c2a86afc4008de9d38737670045 5d5cd44e174adb00a0567c2a86afc400 0648ac6426460c1c7493622cfa2597b6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 5a9fef0fb2dc303e71375e2906701b0e 403befabe5870936cd45f72008eb890f 08a2f98312aff067d5f03b44cf58f319 cd45f72008eb890f71375e2906701b0e 403befabe5870936cd45f72008eb890f 08a2f98312aff067d5f03b44cf58f319 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 3292b01c28f51c80557c76e23b6d7d67 65ba8b51dadbd02a2efc4a4c3cb79f06 0e442a090e2de0df0e442a090e2de0df 2efc4a4c3cb79f06557c76e23b6d7d67 65ba8b51dadbd02a2efc4a4c3cb79f06 0e442a090e2de0df0e442a090e2de0df fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 018a9ded9a32b2b658bb9dccbe78e080 31d4c3802458c320b8e9ef3655324c69 8bf7d8b25706c5dff7abfe7295d6f441 b8e9ef3655324c6958bb9dccbe78e080 31d4c3802458c320b8e9ef3655324c69 8bf7d8b25706c5dff7abfe7295d6f441 fpscr=00000000
+vselge.f64 d7, d8, d10 dc260bdc0b43237ef922696a0f05c22c f20e1dd4b168dbe16ecc3a09dfbd048c 64b651fc046084577ab57fbffe8986a7 6ecc3a09dfbd048cf922696a0f05c22c f20e1dd4b168dbe16ecc3a09dfbd048c 64b651fc046084577ab57fbffe8986a7 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 de9f39ff175e45afde9f39ff175e45af 1ec7ef10271064461273cbadb462d8dd 5f256ae7f57a25258fdf807367ff0cd7 1273cbadb462d8ddde9f39ff175e45af 1ec7ef10271064461273cbadb462d8dd 5f256ae7f57a25258fdf807367ff0cd7 fpscr=00000000
+vselge.f64 d7, d8, d10 ff3c4b3f064d8c217557cde51027645d 425df6d73059dd837e3e8527449ee9f4 cb297d14227fde7c0f14944c6efdbc0d 7e3e8527449ee9f47557cde51027645d 425df6d73059dd837e3e8527449ee9f4 cb297d14227fde7c0f14944c6efdbc0d fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselgt.f32 s15,s16,s20 1bdf8d327099a8084857c13907f4e2b8 cf8ab30ab9b9dc22f7579b2891a81344 9526bc45f7a76187effcd880ce0be4bb 91a813447099a8084857c13907f4e2b8 cf8ab30ab9b9dc22f7579b2891a81344 9526bc45f7a76187effcd880ce0be4bb fpscr=00000000
+vselgt.f32 s15,s16,s20 c9c0b3124ecb70f79979a7ae01844088 2d3ffa9d1614be74a19641dae470df8a f18c6ed01230ff3e8365b8b6c1363c54 e470df8a4ecb70f79979a7ae01844088 2d3ffa9d1614be74a19641dae470df8a f18c6ed01230ff3e8365b8b6c1363c54 fpscr=00000000
+vselgt.f32 s15,s16,s20 eec0a594220beffe1db4b81f2b597541 085f2ae05c723ca7542a15dacc33b1e8 7bc9cbffb9f9c3f1e39422d258859818 cc33b1e8220beffe1db4b81f2b597541 085f2ae05c723ca7542a15dacc33b1e8 7bc9cbffb9f9c3f1e39422d258859818 fpscr=00000000
+vselgt.f32 s15,s16,s20 2d4071b09e34d197ade8b4986d6b0591 ebd55f51b7352d94362d6f4fc8df6c3a 7f23ae157d67454552a7246adc911c23 c8df6c3a9e34d197ade8b4986d6b0591 ebd55f51b7352d94362d6f4fc8df6c3a 7f23ae157d67454552a7246adc911c23 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[2]
+vselgt.f32 s15,s16,s20 e81f605f6011b79f6011b79f7a8390a6 90a557fdbc7d9bd9764c8b686f3a23b6 0ef0bee102374fafd4e3e2ff7367dd2b 6f3a23b66011b79f6011b79f7a8390a6 90a557fdbc7d9bd9764c8b686f3a23b6 0ef0bee102374fafd4e3e2ff7367dd2b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vselgt.f32 s15,s16,s20 b2aa237461d97084eb06887153eff01a c9cfa6ab4754a2195bd22fb34754a219 895df1dcc89783ffad7ef35a4cf4eb6b 4754a21961d97084eb06887153eff01a c9cfa6ab4754a2195bd22fb34754a219 895df1dcc89783ffad7ef35a4cf4eb6b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[3]
+vselgt.f32 s15,s16,s20 70670d2b81b02e0f0a0edcee4d2cc878 18e8bf66df043a12308c280e5e7c1153 7d4ca4d5e89f7a600a82ee30cd29d94c 5e7c115381b02e0f0a0edcee4d2cc878 18e8bf66df043a12308c280e5e7c1153 7d4ca4d5e89f7a600a82ee30cd29d94c fpscr=00000000
+vselgt.f32 s15,s16,s20 d9bdcc893028e602d73eb2831f4bf609 1a6853f6be84f8bb673f4fc8c387756f 6d6a3f50029353f1b5ac7f6f455b745c c387756f3028e602d73eb2831f4bf609 1a6853f6be84f8bb673f4fc8c387756f 6d6a3f50029353f1b5ac7f6f455b745c fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vselgt.f32 s15,s16,s20 1e876212d6c92a1344cea455fc4eef9f f57b7629851fcfdef394463cd1c7914d f11f910033957a94279b0a97cbc7ac5e d1c7914dd6c92a1344cea455fc4eef9f f57b7629851fcfdef394463cd1c7914d f11f910033957a94279b0a97cbc7ac5e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vselgt.f32 s15,s16,s20 7bcc8918719010b51f8d0a9a7bcc8918 f209e1392f0631401ae5027aa91a00bc 605a3bd8bf3e07b2c2da04a6f33908f3 a91a00bc719010b51f8d0a9a7bcc8918 f209e1392f0631401ae5027aa91a00bc 605a3bd8bf3e07b2c2da04a6f33908f3 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[3]
+vselgt.f32 s15,s16,s20 76795aaf7a3a63326053ff312e26dd2d 1cef651c6c49c9b9c3455d9993e4a5f1 753e762872ee82410613768d72ee8241 93e4a5f17a3a63326053ff312e26dd2d 1cef651c6c49c9b9c3455d9993e4a5f1 753e762872ee82410613768d72ee8241 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vselgt.f32 s15,s16,s20 0f86961d0dfe0e02951a8f772c44efed 22fc2fbc3120de9c6479e10d450f9d06 7879495083fdabe878794950fd4f567a 450f9d060dfe0e02951a8f772c44efed 22fc2fbc3120de9c6479e10d450f9d06 7879495083fdabe878794950fd4f567a fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vselgt.f32 s15,s16,s20 24672c54caa9aa633342e0b5d4f4aeda 19278d62f4b822f982cef9da2674b1f9 c3e2025a96a7091a1f4f5923c556de8f 2674b1f9caa9aa633342e0b5d4f4aeda 19278d62f4b822f982cef9da2674b1f9 c3e2025a96a7091a1f4f5923c556de8f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselgt.f32 s15,s16,s20 015af8db989c4ca73ffe15972ad99232 3038d0cec7409e243038d0ce7b07f98f 1855d89a262a1b0a53270c4dcc860398 7b07f98f989c4ca73ffe15972ad99232 3038d0cec7409e243038d0ce7b07f98f 1855d89a262a1b0a53270c4dcc860398 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vselgt.f32 s15,s16,s20 2dee1843b5e8784c7c8c4889516eeebe 617c8954617c8954a5cbcde8d1860844 0b85da88ee6240d4fab6c9afe737c931 d1860844b5e8784c7c8c4889516eeebe 617c8954617c8954a5cbcde8d1860844 0b85da88ee6240d4fab6c9afe737c931 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vselgt.f32 s15,s16,s20 7908d297e250bfd0beb18ef33bda55a8 c02a0d5fff7bec35055605a42bdaf0c7 3ec6594828ea00ce852ad4015bd9be35 2bdaf0c7e250bfd0beb18ef33bda55a8 c02a0d5fff7bec35055605a42bdaf0c7 3ec6594828ea00ce852ad4015bd9be35 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vselgt.f32 s15,s16,s20 8811bde81e25ab197c2f544bc3a505c0 5b031ff9e7ae8c119c803647a19ed837 c65eabd1c65eabd1fd787344eab396a5 a19ed8371e25ab197c2f544bc3a505c0 5b031ff9e7ae8c119c803647a19ed837 c65eabd1c65eabd1fd787344eab396a5 fpscr=00000000
+vselgt.f32 s15,s16,s20 9a8034e6e3ed64baedc4d347f131748c 173f4b15840aefbd68c882e0ba868812 92595c78dc164f3e6b0b450ee14a3f63 ba868812e3ed64baedc4d347f131748c 173f4b15840aefbd68c882e0ba868812 92595c78dc164f3e6b0b450ee14a3f63 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[0]
+vselgt.f32 s15,s16,s20 c1646445ad3ed3b57d49d58462983027 4114a950baae5dda57a6295a9c342f97 0c48c120052fffdbd7daec0268b166e8 9c342f97ad3ed3b57d49d58462983027 4114a950baae5dda57a6295a9c342f97 0c48c120052fffdbd7daec0268b166e8 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vselgt.f32 s15,s16,s20 4f4243ae39614780efa667b5aedab485 05b02563c9fa6eef4b33b2ee05b02563 fcaee0ded12dca0df26a17d4498d2688 05b0256339614780efa667b5aedab485 05b02563c9fa6eef4b33b2ee05b02563 fcaee0ded12dca0df26a17d4498d2688 fpscr=00000000
+vselgt.f32 s15,s16,s20 de7208c800b715da12557654765782b0 f0d64bb3c491e2964c871592462727ca f3b17280fe8bd0af2574688c737559b2 462727ca00b715da12557654765782b0 f0d64bb3c491e2964c871592462727ca f3b17280fe8bd0af2574688c737559b2 fpscr=00000000
+vselgt.f32 s15,s16,s20 1c44b8009d306bbad4fdc8b28c2e7caa 8a171d1a294d48dac018701d2c9c4cc5 adf8d51b36a1754467de8de308363b05 2c9c4cc59d306bbad4fdc8b28c2e7caa 8a171d1a294d48dac018701d2c9c4cc5 adf8d51b36a1754467de8de308363b05 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vselgt.f32 s15,s16,s20 1a8250dd1a8250ddf0ce0ae3dd1fb618 34ff9e689545c592399af877a2488f5a 912f8374159df2f7085589b343d21f25 a2488f5a1a8250ddf0ce0ae3dd1fb618 34ff9e689545c592399af877a2488f5a 912f8374159df2f7085589b343d21f25 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselgt.f32 s15,s16,s20 e0fab6f1097a591efbe94e37d632c5c5 18b62fb46893080a18b62fb42368e72c b80b650cfe693570ed7e83558122a32f 2368e72c097a591efbe94e37d632c5c5 18b62fb46893080a18b62fb42368e72c b80b650cfe693570ed7e83558122a32f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vselgt.f32 s15,s16,s20 33bddc2fc7a026fecd171aec33bddc2f b1a4ca4f181791f3d454c04f06a53778 c68c6485c6adf116dec9468c558d9860 06a53778c7a026fecd171aec33bddc2f b1a4ca4f181791f3d454c04f06a53778 c68c6485c6adf116dec9468c558d9860 fpscr=00000000
+vselgt.f32 s15,s16,s20 29a983126fa213d785a320168623013c 5683bcd06b852bf92251cb35169b864d 815ea08ffe762184b4b96d2e26a96f0d 169b864d6fa213d785a320168623013c 5683bcd06b852bf92251cb35169b864d 815ea08ffe762184b4b96d2e26a96f0d fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselgt.f32 s15,s16,s20 c1138d54839bd88d84ce1ec208da666e 5c7e82920db77e6cea21645ba286f1eb 54bf2328bcdbe96673dca83ac0d55211 a286f1eb839bd88d84ce1ec208da666e 5c7e82920db77e6cea21645ba286f1eb 54bf2328bcdbe96673dca83ac0d55211 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[1]
+randV128: 768 calls, 799 iters
+vselgt.f32 s15,s16,s20 cf8ff14acf8ff14a5a254e46354122d6 465c83497b47d5b77f61bafe67d20d3b 322ae60a0d6cd20b6d770c50d4ac6c0d 67d20d3bcf8ff14a5a254e46354122d6 465c83497b47d5b77f61bafe67d20d3b 322ae60a0d6cd20b6d770c50d4ac6c0d fpscr=00000000
+vselgt.f32 s15,s16,s20 1fb513253fbf0bbad8c8679e1814cac1 8d162d9b0d5f9d85c79bcbad7f7df9d3 a11e8b73b8f2cb4a028bdedbd8609b86 7f7df9d33fbf0bbad8c8679e1814cac1 8d162d9b0d5f9d85c79bcbad7f7df9d3 a11e8b73b8f2cb4a028bdedbd8609b86 fpscr=00000000
+vselgt.f32 s15,s16,s20 9a660dfbf22d561be6f39a2c0cfb3058 7a7b4e2ba2eb89d3b39f1de9625c24b1 ea603563102a8d410ebd081fb5bb3711 625c24b1f22d561be6f39a2c0cfb3058 7a7b4e2ba2eb89d3b39f1de9625c24b1 ea603563102a8d410ebd081fb5bb3711 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vselgt.f32 s15,s16,s20 56ee33f7ac3926cc5df566ae80e65d3a 20e931e49bb2bad46a21352852c83b9f e4841621bb7f912713317dcabb7f9127 52c83b9fac3926cc5df566ae80e65d3a 20e931e49bb2bad46a21352852c83b9f e4841621bb7f912713317dcabb7f9127 fpscr=00000000
+vselgt.f32 s15,s16,s20 eeda52f02c35e59e0949a14bfd2150e7 408c9b2067aa17b9a984144ef62b496d f81b4f5fe03bec2401c8b1f90f4166de f62b496d2c35e59e0949a14bfd2150e7 408c9b2067aa17b9a984144ef62b496d f81b4f5fe03bec2401c8b1f90f4166de fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[0]
+vselgt.f32 s15,s16,s20 2767dabd36ee9d2036ee9d202debefba 7c7da2b845c144f16c1720c22c991b84 28b1fa34a6deaa2f202ba309356f0684 2c991b8436ee9d2036ee9d202debefba 7c7da2b845c144f16c1720c22c991b84 28b1fa34a6deaa2f202ba309356f0684 fpscr=00000000
+vselgt.f32 s15,s16,s20 e32ad2203fe937d71e545a5fb8b48c3f e604f15032609bb07bb871573e5b1e29 b5f5ec755f52e2ebeaa1e43c6c12f793 3e5b1e293fe937d71e545a5fb8b48c3f e604f15032609bb07bb871573e5b1e29 b5f5ec755f52e2ebeaa1e43c6c12f793 fpscr=00000000
+vselgt.f32 s15,s16,s20 2f9e68b12a89d1a702ab5bb74d390b29 a66de0615ea0d6431181b10449c8c169 dac5cb275692ecb1c505708ac878d540 49c8c1692a89d1a702ab5bb74d390b29 a66de0615ea0d6431181b10449c8c169 dac5cb275692ecb1c505708ac878d540 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vselgt.f32 s15,s16,s20 cac1d1b9d32d0b7e5bc51a46ecf76376 3d66fcd8901008394c881899882591e9 1ee0af201fb673430704090f5eec3703 882591e9d32d0b7e5bc51a46ecf76376 3d66fcd8901008394c881899882591e9 1ee0af201fb673430704090f5eec3703 fpscr=00000000
+vselgt.f32 s15,s16,s20 efd6c9eeee462c3cb59631d8b85d1010 4f537eee9a86447020bf0b56034fb5f3 c1b02de71711f26e5d3d6fa6ce3475da 034fb5f3ee462c3cb59631d8b85d1010 4f537eee9a86447020bf0b56034fb5f3 c1b02de71711f26e5d3d6fa6ce3475da fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vselgt.f32 s15,s16,s20 b5100402bfc81bac17fee204eeb0cb5c f902c9a2df3e3cb7f382b0f6f902c9a2 087be4a6069c87098acb707f5aac4670 f902c9a2bfc81bac17fee204eeb0cb5c f902c9a2df3e3cb7f382b0f6f902c9a2 087be4a6069c87098acb707f5aac4670 fpscr=00000000
+vselgt.f32 s15,s16,s20 21e7c0a58301ba82fc21ccdd8545b41a d05b994fa60d240d51788bb7e1a16f74 81d0e521e29c6658b2fa89dd9a94fc17 e1a16f748301ba82fc21ccdd8545b41a d05b994fa60d240d51788bb7e1a16f74 81d0e521e29c6658b2fa89dd9a94fc17 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vselgt.f32 s15,s16,s20 a724eeacc1578d04928167d0df3f41e1 5f43e64aad74f7bbaf2e023b02afe680 db2e522a3dcd8bb349e538e7dda8ab04 02afe680c1578d04928167d0df3f41e1 5f43e64aad74f7bbaf2e023b02afe680 db2e522a3dcd8bb349e538e7dda8ab04 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[3]
+vselgt.f32 s15,s16,s20 bc17f33bcf2b9d39f9873247ef89ab93 10fd9f5e8e11ad01dcef0d56315a22fb a4727fdaa4727fda492ed6217b98d440 315a22fbcf2b9d39f9873247ef89ab93 10fd9f5e8e11ad01dcef0d56315a22fb a4727fdaa4727fda492ed6217b98d440 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vselgt.f32 s15,s16,s20 deea882120dc114c354a3cedacd46161 5d868c1b95d9e8bc430e287d74b10c3f 56ba6f87ff79947a339de73092581227 74b10c3f20dc114c354a3cedacd46161 5d868c1b95d9e8bc430e287d74b10c3f 56ba6f87ff79947a339de73092581227 fpscr=00000000
+vselgt.f32 s15,s16,s20 273c0d45399c9b122cd84390b7023133 d041932201ece1f76cab44100b00fb70 dd3a9c05382834d243e8102309289f04 0b00fb70399c9b122cd84390b7023133 d041932201ece1f76cab44100b00fb70 dd3a9c05382834d243e8102309289f04 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vselgt.f32 s15,s16,s20 3a753da06a31d380ece50912c7462ffa 1fb72fff96b0fe8e3bae1f8d37e3c323 99ad5ea9a1f602854dcb6e961a321c25 37e3c3236a31d380ece50912c7462ffa 1fb72fff96b0fe8e3bae1f8d37e3c323 99ad5ea9a1f602854dcb6e961a321c25 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vselgt.f32 s15,s16,s20 699bc759eb22cacbec75d26340ffddf6 d4b3e72358437eb891e7c38e901fb05a 3513b9ec899de43c17ad36d3ef68f9d7 901fb05aeb22cacbec75d26340ffddf6 d4b3e72358437eb891e7c38e901fb05a 3513b9ec899de43c17ad36d3ef68f9d7 fpscr=00000000
+vselgt.f32 s15,s16,s20 92a297dec2e9e3f6fb6753d7ab516c02 cba562eeb33a849b04af2e6fd3ee34fd 70577cc5c8b316502f90a52952a5b063 d3ee34fdc2e9e3f6fb6753d7ab516c02 cba562eeb33a849b04af2e6fd3ee34fd 70577cc5c8b316502f90a52952a5b063 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselgt.f32 s15,s16,s20 db7c936146eb0499db7c93615aeed631 0b160f8de8964a92b57b5f1836666691 a45c5cba0e542c3521fc5ae2b449f325 3666669146eb0499db7c93615aeed631 0b160f8de8964a92b57b5f1836666691 a45c5cba0e542c3521fc5ae2b449f325 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vselgt.f32 s15,s16,s20 c84b61ede9902ac1a3cdc80ab45f90eb 6ffff2e82aa56bb5772724df31a64658 1732c074b63b26eb09d0247b4a28d835 31a64658e9902ac1a3cdc80ab45f90eb 6ffff2e82aa56bb5772724df31a64658 1732c074b63b26eb09d0247b4a28d835 fpscr=00000000
+vselgt.f32 s15,s16,s20 8bc2195ff2ebb5a01b5604b6f74470da c5db529dcff48de39d2cd39e879f7672 90f12aa71dfe62fc52c992dd903d2549 879f7672f2ebb5a01b5604b6f74470da c5db529dcff48de39d2cd39e879f7672 90f12aa71dfe62fc52c992dd903d2549 fpscr=00000000
+vselgt.f32 s15,s16,s20 f8ed04aa9b8d23c1c1a6aef520e286d3 d98c7cf36c568aea8a316fe71b5c2e03 b7bdd5efa809001e348f5988c1f6c82a 1b5c2e039b8d23c1c1a6aef520e286d3 d98c7cf36c568aea8a316fe71b5c2e03 b7bdd5efa809001e348f5988c1f6c82a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 3f9c61edeb7496cb5e0437a54d260583 1a75ad5ef068bc8f1a75ad5ef068bc8f c9da1823673a07037584747d9f1860e8 1a75ad5ef068bc8f5e0437a54d260583 1a75ad5ef068bc8f1a75ad5ef068bc8f c9da1823673a07037584747d9f1860e8 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 e6136698d2279aa9136d4ada30fb9e4e ee40784b29393714ee40784b29393714 92147f5309d64b4392147f5309d64b43 ee40784b29393714136d4ada30fb9e4e ee40784b29393714ee40784b29393714 92147f5309d64b4392147f5309d64b43 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 65b43f63357ecd40529f337f2d5dda79 608f00c029de3613dbcdea9a46a0b761 4b4c78162e0a6d233614316bfe51ff7d dbcdea9a46a0b761529f337f2d5dda79 608f00c029de3613dbcdea9a46a0b761 4b4c78162e0a6d233614316bfe51ff7d fpscr=00000000
+vselgt.f64 d7, d8, d10 a5fdd4619ca3fbbaaadd3bcfd967e686 dae1eabc617c99524fccee06be57b0cd b602c7a266815d1ae592158f24400e74 4fccee06be57b0cdaadd3bcfd967e686 dae1eabc617c99524fccee06be57b0cd b602c7a266815d1ae592158f24400e74 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 398be9f9968adddb398be9f9968adddb ea0cca19594c6ff82708f45fa473320d 1527459fc84854711527459fc8485471 2708f45fa473320d398be9f9968adddb ea0cca19594c6ff82708f45fa473320d 1527459fc84854711527459fc8485471 fpscr=00000000
+vselgt.f64 d7, d8, d10 c1c79d7644a6cba105d03730bacf1eab 39d0589dbadedc5fb420fa5ec66b8ee2 9473a371e970cd3de35a4e1617453bcb b420fa5ec66b8ee205d03730bacf1eab 39d0589dbadedc5fb420fa5ec66b8ee2 9473a371e970cd3de35a4e1617453bcb fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 0f071e11dcec3cf9516423533673b907 0a24cae5e8b715cc2073569dc2fd10a6 975d9a3a089cacf06c3025f4e8aca8ea 2073569dc2fd10a6516423533673b907 0a24cae5e8b715cc2073569dc2fd10a6 975d9a3a089cacf06c3025f4e8aca8ea fpscr=00000000
+vselgt.f64 d7, d8, d10 7b78995ea148096c521348c82dc23e60 b171946ef6718b834ce1f0729d0b39dd 37ff19ae21793f3502e53752964117a9 4ce1f0729d0b39dd521348c82dc23e60 b171946ef6718b834ce1f0729d0b39dd 37ff19ae21793f3502e53752964117a9 fpscr=00000000
+vselgt.f64 d7, d8, d10 f8cfe8e7d50668236613bf1f9e155c6e e40b49cae43a978153f481b302330083 60f6f31044959089d1fa1c6ad835ba25 53f481b3023300836613bf1f9e155c6e e40b49cae43a978153f481b302330083 60f6f31044959089d1fa1c6ad835ba25 fpscr=00000000
+vselgt.f64 d7, d8, d10 e014b74b3e2d896242658b6cef5c9847 a5dc8513422b757997b8e3e78709360c e9a3c3904619f63f1c4b1b9f42235e7f 97b8e3e78709360c42658b6cef5c9847 a5dc8513422b757997b8e3e78709360c e9a3c3904619f63f1c4b1b9f42235e7f fpscr=00000000
+vselgt.f64 d7, d8, d10 3223bc404be66e836250454c3b390ef5 2920717443688dbee9625eec89f510d5 de7ec0f6e8e8c80e6e12660f94e0c017 e9625eec89f510d56250454c3b390ef5 2920717443688dbee9625eec89f510d5 de7ec0f6e8e8c80e6e12660f94e0c017 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselgt.f64 d7, d8, d10 cba393991642f0124f764588d0158833 ef6f5df4580476feef6f5df4580476fe d9d62b65994cc8a7e6f3a0a57d8b0bb2 ef6f5df4580476fe4f764588d0158833 ef6f5df4580476feef6f5df4580476fe d9d62b65994cc8a7e6f3a0a57d8b0bb2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselgt.f64 d7, d8, d10 4e2f953af06edcdf4e2f953af06edcdf 298bd0f8923b179aed553385d2a045fc 6a50db4f1b9ccfb00ac9f644af6c35b5 ed553385d2a045fc4e2f953af06edcdf 298bd0f8923b179aed553385d2a045fc 6a50db4f1b9ccfb00ac9f644af6c35b5 fpscr=00000000
+vselgt.f64 d7, d8, d10 4ac240cfc8be0f381ae8e01f521ca43e cbcccaa715e279b7db6a963b13c1e3ca 51b853da308a1146e2e32500cd8fd7cb db6a963b13c1e3ca1ae8e01f521ca43e cbcccaa715e279b7db6a963b13c1e3ca 51b853da308a1146e2e32500cd8fd7cb fpscr=00000000
+vselgt.f64 d7, d8, d10 3726b86f381e19ddf1bb3242f811ed9d 5bbc95f9413a82184f5f247e5d780d4a a50633a077162f6cae00d9a9616fd38c 4f5f247e5d780d4af1bb3242f811ed9d 5bbc95f9413a82184f5f247e5d780d4a a50633a077162f6cae00d9a9616fd38c fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 a00a527c7a3e71272144a3295695755d 9a7dff326017a1e19514df37fbf87121 caac6481b790423fcaac6481b790423f 9514df37fbf871212144a3295695755d 9a7dff326017a1e19514df37fbf87121 caac6481b790423fcaac6481b790423f fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselgt.f64 d7, d8, d10 7e63cc59cccbd0a3b1a06db3c73ae0ca 105015f526edba740e2eb08a2a8571c6 e2dc7727337c2dd90fe42aefa4ee5824 0e2eb08a2a8571c6b1a06db3c73ae0ca 105015f526edba740e2eb08a2a8571c6 e2dc7727337c2dd90fe42aefa4ee5824 fpscr=00000000
+vselgt.f64 d7, d8, d10 6340ab234dd474bfd8d4c662fd870459 c41ba68cab6ca586b60aafceb9d47da8 246ebcbf3251632ec2c358364bdd041f b60aafceb9d47da8d8d4c662fd870459 c41ba68cab6ca586b60aafceb9d47da8 246ebcbf3251632ec2c358364bdd041f fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 57d4be27c1a5174d78728950fadd603a 2b62627b86d0bd834973a67642acd16d 38d8d49260898789ecfa86c5322e33ad 4973a67642acd16d78728950fadd603a 2b62627b86d0bd834973a67642acd16d 38d8d49260898789ecfa86c5322e33ad fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 65838ecb00f2cfa75f72d29952a65385 4888ed9f8dfeec004888ed9f8dfeec00 57a35145a25b79f3c74fd35be6ea59de 4888ed9f8dfeec005f72d29952a65385 4888ed9f8dfeec004888ed9f8dfeec00 57a35145a25b79f3c74fd35be6ea59de fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: 1024 calls, 1064 iters
+vselgt.f64 d7, d8, d10 f73708fe5d15565be8ebcc833e0bdb9b 3f4e8875327705273f4e887532770527 5e1fd2dbeff2b0d603a742d668fbec83 3f4e887532770527e8ebcc833e0bdb9b 3f4e8875327705273f4e887532770527 5e1fd2dbeff2b0d603a742d668fbec83 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselgt.f64 d7, d8, d10 e5349918a6f9c50683e46cdc819cfa68 98305776f15e5cf5c8e20f698a92d77d 82daa912c843a17682daa912c843a176 c8e20f698a92d77d83e46cdc819cfa68 98305776f15e5cf5c8e20f698a92d77d 82daa912c843a17682daa912c843a176 fpscr=00000000
+vselgt.f64 d7, d8, d10 7323e8ea339093584e082524b12c5130 01cb88ac89d491f84d4d934bc2448062 46592dddc3c391a4d67da7770a72bf3d 4d4d934bc24480624e082524b12c5130 01cb88ac89d491f84d4d934bc2448062 46592dddc3c391a4d67da7770a72bf3d fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 9e79ad9453d8d768a855ef96dd4b939b a7ea5ccd5933675fd3bd93203fa5ba14 069ba01413e4b550069ba01413e4b550 d3bd93203fa5ba14a855ef96dd4b939b a7ea5ccd5933675fd3bd93203fa5ba14 069ba01413e4b550069ba01413e4b550 fpscr=00000000
+vselgt.f64 d7, d8, d10 e0aecdb528fb1fc3c84278a4d83ca49b 21d698972394a54142cc6e0151dec49a 3fb20d08ace4ab781ce8746b100c316e 42cc6e0151dec49ac84278a4d83ca49b 21d698972394a54142cc6e0151dec49a 3fb20d08ace4ab781ce8746b100c316e fpscr=00000000
+vselgt.f64 d7, d8, d10 c10abff54f770a20112dfaa1871c6200 43583eca9ac1499f50e117ffbffc9fce fbb76d0b454872abd2b6d05e3da6aec2 50e117ffbffc9fce112dfaa1871c6200 43583eca9ac1499f50e117ffbffc9fce fbb76d0b454872abd2b6d05e3da6aec2 fpscr=00000000
+vselgt.f64 d7, d8, d10 55824ec083b68efd935b3cb06092f214 b24784367524062b5f2442f91082ee85 fe6b68441c3cd4473b05d3739b191eb1 5f2442f91082ee85935b3cb06092f214 b24784367524062b5f2442f91082ee85 fe6b68441c3cd4473b05d3739b191eb1 fpscr=00000000
+vselgt.f64 d7, d8, d10 04ec8007dcd8259eb46706a116fb3594 d6cd91b17366b498ce77a62fd04a04e8 f5428bf658d74321fc004f843c995e19 ce77a62fd04a04e8b46706a116fb3594 d6cd91b17366b498ce77a62fd04a04e8 f5428bf658d74321fc004f843c995e19 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselgt.f64 d7, d8, d10 9982253f796c209a63a01da4fc15ddf7 0517b5e37f453a794f416f41aa1f6327 f5beabf0cf43088f88eb2d9268163c40 4f416f41aa1f632763a01da4fc15ddf7 0517b5e37f453a794f416f41aa1f6327 f5beabf0cf43088f88eb2d9268163c40 fpscr=00000000
+vselgt.f64 d7, d8, d10 193d271dfad342faf8217f803d5d7d1f 043f2c2e6dd27b8f0f27d483ca4b472b 2a9ce0d2064f0c52702884ebd899d8ab 0f27d483ca4b472bf8217f803d5d7d1f 043f2c2e6dd27b8f0f27d483ca4b472b 2a9ce0d2064f0c52702884ebd899d8ab fpscr=00000000
+vselgt.f64 d7, d8, d10 856cf8e6fde3d28de790762347678e7a f82ffe4ce70ef4d4efe07d64463843f2 dbd17c208e78e97e546b8297a6ac08f0 efe07d64463843f2e790762347678e7a f82ffe4ce70ef4d4efe07d64463843f2 dbd17c208e78e97e546b8297a6ac08f0 fpscr=00000000
+vselgt.f64 d7, d8, d10 046a7db02c2b212f4fcf7fd0c67407de 15331e31fe3a99b7b1906b87b46c65c6 d760347e7d32ec11688150cc43fe0f57 b1906b87b46c65c64fcf7fd0c67407de 15331e31fe3a99b7b1906b87b46c65c6 d760347e7d32ec11688150cc43fe0f57 fpscr=00000000
+vselgt.f64 d7, d8, d10 ab982ac5668794dba129791b5aa7b376 5bfd7037ca9edd979b2f27a881724708 de8a4e91eaff7c1a9c5cde179ef79e72 9b2f27a881724708a129791b5aa7b376 5bfd7037ca9edd979b2f27a881724708 de8a4e91eaff7c1a9c5cde179ef79e72 fpscr=00000000
+vselgt.f64 d7, d8, d10 55656554181c3df2324141abf98de883 7992362189c698dc26f0f74603b51746 525a4d9725b55308a2d1130289a02676 26f0f74603b51746324141abf98de883 7992362189c698dc26f0f74603b51746 525a4d9725b55308a2d1130289a02676 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 059c7386ba18e2f9059c7386ba18e2f9 2b6e84f65842f7a22b6e84f65842f7a2 d531965e6ba117763d3801f1069d2d32 2b6e84f65842f7a2059c7386ba18e2f9 2b6e84f65842f7a22b6e84f65842f7a2 d531965e6ba117763d3801f1069d2d32 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 2b346b02d6932174c4ec15b4a1525eba 24a53e153c75ce7a38f9d8685cf863ed 5f9c323a3760db545f9c323a3760db54 38f9d8685cf863edc4ec15b4a1525eba 24a53e153c75ce7a38f9d8685cf863ed 5f9c323a3760db545f9c323a3760db54 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselgt.f64 d7, d8, d10 d200cac69e767dba576370b0bec5daf5 64f0f9ad576c11e2ee5740c884baa187 625e27aef3b33e8b625e27aef3b33e8b ee5740c884baa187576370b0bec5daf5 64f0f9ad576c11e2ee5740c884baa187 625e27aef3b33e8b625e27aef3b33e8b fpscr=00000000
+vselgt.f64 d7, d8, d10 fb0650fe99e00077960d0e17e68462d8 80ad135ca102e2518a639b87f45de2a9 36f0caf8fe5634a37a25a79738a666c1 8a639b87f45de2a9960d0e17e68462d8 80ad135ca102e2518a639b87f45de2a9 36f0caf8fe5634a37a25a79738a666c1 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 4493cb3611bde6fb4493cb3611bde6fb 400ead755366854b7848c9e734cbc93e b81cfda24fbfb946c584c4cb1490405e 7848c9e734cbc93e4493cb3611bde6fb 400ead755366854b7848c9e734cbc93e b81cfda24fbfb946c584c4cb1490405e fpscr=00000000
+vselgt.f64 d7, d8, d10 37acd05b093195d4cc196042f3c4d2b3 d486c05060334f93b036e5cc76f58690 f460f6214260184275dda6294ff45552 b036e5cc76f58690cc196042f3c4d2b3 d486c05060334f93b036e5cc76f58690 f460f6214260184275dda6294ff45552 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 d23c65e0374dacd7d0c927f5ca8e84e4 dfef494e68903106cf285ec202de0303 7c3d35077afe6dcd70a6e690ccee61f6 cf285ec202de0303d0c927f5ca8e84e4 dfef494e68903106cf285ec202de0303 7c3d35077afe6dcd70a6e690ccee61f6 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 c31f59eefee506c3c31f59eefee506c3 d4ffb705e1afce6c8f2e9973c7f1b172 cc6139683c60ba304b49a168cb6a8c59 8f2e9973c7f1b172c31f59eefee506c3 d4ffb705e1afce6c8f2e9973c7f1b172 cc6139683c60ba304b49a168cb6a8c59 fpscr=00000000
+vselgt.f64 d7, d8, d10 0f07ab007ed849a4b42f2c62f6de8259 c8c9868974388f35dbeec777eec8e091 e7599c1d7941859f453ecc281e798668 dbeec777eec8e091b42f2c62f6de8259 c8c9868974388f35dbeec777eec8e091 e7599c1d7941859f453ecc281e798668 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 12ae4c89891b611cb72d1badd1706f6d 33ed6394a4e0fdd833ed6394a4e0fdd8 6d48ba65a049044f0a6ec6b4dfc0b99e 33ed6394a4e0fdd8b72d1badd1706f6d 33ed6394a4e0fdd833ed6394a4e0fdd8 6d48ba65a049044f0a6ec6b4dfc0b99e fpscr=00000000
+vselgt.f64 d7, d8, d10 b477b9e7f18bc6c3580edaccddcf5265 8fce0077d9a66558e02da4604c7f08c3 0f85e6ecc939fc5e6297549b24245209 e02da4604c7f08c3580edaccddcf5265 8fce0077d9a66558e02da4604c7f08c3 0f85e6ecc939fc5e6297549b24245209 fpscr=00000000
+vselgt.f64 d7, d8, d10 fccb1fa9e696df458dcfef3ab5d9369f accf209364f8c75664c64e9312a9df38 770f6e4fec8c7dd3e85ce1c95f9e523e 64c64e9312a9df388dcfef3ab5d9369f accf209364f8c75664c64e9312a9df38 770f6e4fec8c7dd3e85ce1c95f9e523e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 0282cde34cfcd26f0282cde34cfcd26f 3537db92ab191fd44d29f26f8d054574 d69677db647e10777a689d4468d096e9 4d29f26f8d0545740282cde34cfcd26f 3537db92ab191fd44d29f26f8d054574 d69677db647e10777a689d4468d096e9 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 00b3af3be3bd6611a42ecb216f22d818 546f267de84418ad1bee699375639b51 2b58e9fde83fe3f22b58e9fde83fe3f2 1bee699375639b51a42ecb216f22d818 546f267de84418ad1bee699375639b51 2b58e9fde83fe3f22b58e9fde83fe3f2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselgt.f64 d7, d8, d10 10e8927696ec55e2380329874e749e64 83c10380fea42b07395f10c1d376077a d09d8a5ac2fdb52fd3f7f22009bd1333 395f10c1d376077a380329874e749e64 83c10380fea42b07395f10c1d376077a d09d8a5ac2fdb52fd3f7f22009bd1333 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 527dae5149384fd86c205830e0157e2c ff2b5b221d444be6c3e7231053ca4553 e90fc207f5504bfada812af5642cc57f c3e7231053ca45536c205830e0157e2c ff2b5b221d444be6c3e7231053ca4553 e90fc207f5504bfada812af5642cc57f fpscr=00000000
+vseleq.f32 s15,s16,s20 2a442f7f3f29c72589d06df375f67db0 4ef5d56ceea1424e573c1461d21119cc f5b8fcab8605407346035a66572f9608 572f96083f29c72589d06df375f67db0 4ef5d56ceea1424e573c1461d21119cc f5b8fcab8605407346035a66572f9608 fpscr=00000000
+vseleq.f32 s15,s16,s20 e2c18409b920238bd18b730c72200055 041b20f49f05d205e056a7eaabf2fc5a f159e6804a208c3aef5c7d239c335778 9c335778b920238bd18b730c72200055 041b20f49f05d205e056a7eaabf2fc5a f159e6804a208c3aef5c7d239c335778 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vseleq.f32 s15,s16,s20 341fc0b0da11db6eb000a274a69bab7a d126249134f10473a47ba276512cbad6 7abc1e3f1f44a40d833548a11bad0962 1bad0962da11db6eb000a274a69bab7a d126249134f10473a47ba276512cbad6 7abc1e3f1f44a40d833548a11bad0962 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vseleq.f32 s15,s16,s20 66fa978a94423df7150f41089f081300 8d87596f8d87596f5995551c61781273 3a827ce46ded373e3d4d236c40560f95 40560f9594423df7150f41089f081300 8d87596f8d87596f5995551c61781273 3a827ce46ded373e3d4d236c40560f95 fpscr=00000000
+vseleq.f32 s15,s16,s20 f85523d79f9f0c7202154e95a2d3fe26 6380f154c19c1eb005b8c1eecab4c0be 2fe3d2a90bbf9e845e7b26ad220e47f3 220e47f39f9f0c7202154e95a2d3fe26 6380f154c19c1eb005b8c1eecab4c0be 2fe3d2a90bbf9e845e7b26ad220e47f3 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[1]
+vseleq.f32 s15,s16,s20 175da80b0a99d02a56b0dc4dc8f82dab 092de5e052d63dfd0158dc0142ab5ad3 6be226f5a384cc8b8c5092f134a93a24 34a93a240a99d02a56b0dc4dc8f82dab 092de5e052d63dfd0158dc0142ab5ad3 6be226f5a384cc8b8c5092f134a93a24 fpscr=00000000
+vseleq.f32 s15,s16,s20 a0d38bbad477182f3a52cc65df7154eb 104228ad24ae708daa8f6e6aaf719aae 28c508326540315023ce08b43c76375b 3c76375bd477182f3a52cc65df7154eb 104228ad24ae708daa8f6e6aaf719aae 28c508326540315023ce08b43c76375b fpscr=00000000
+vseleq.f32 s15,s16,s20 3ddfbe20ee62ed7bd14f57939b37f0b7 500e5bbebe48a67944424c4eaafcc2da de65816c1d3993c9015e3a1038765fba 38765fbaee62ed7bd14f57939b37f0b7 500e5bbebe48a67944424c4eaafcc2da de65816c1d3993c9015e3a1038765fba fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vseleq.f32 s15,s16,s20 5a2d2a208fa40aea8b37bb14690d0d90 879ff2e1ca394c0019fa007080b4b833 73e1918197b055d12912b29397b055d1 97b055d18fa40aea8b37bb14690d0d90 879ff2e1ca394c0019fa007080b4b833 73e1918197b055d12912b29397b055d1 fpscr=00000000
+vseleq.f32 s15,s16,s20 b1760ed37897654c15cdbb77b19c3542 8277ef56ae879d8e99ac994bb2d53a76 4164cf16b87e90aeee6c793d9640e208 9640e2087897654c15cdbb77b19c3542 8277ef56ae879d8e99ac994bb2d53a76 4164cf16b87e90aeee6c793d9640e208 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vseleq.f32 s15,s16,s20 442679afd4eda67346d348f7bc0cc35d 858ea70e5e5a3030a0f7f71cd8d73ba2 ee554afcbea9746b76a881358221d9c4 8221d9c4d4eda67346d348f7bc0cc35d 858ea70e5e5a3030a0f7f71cd8d73ba2 ee554afcbea9746b76a881358221d9c4 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[3]
+vseleq.f32 s15,s16,s20 9bbe97940e60c5b76dd928407deb9d4c 8319ddaa8319ddaa2dbeac5c7eac91a2 11069ac92e3c1e1611069ac9e197e4d5 e197e4d50e60c5b76dd928407deb9d4c 8319ddaa8319ddaa2dbeac5c7eac91a2 11069ac92e3c1e1611069ac9e197e4d5 fpscr=00000000
+vseleq.f32 s15,s16,s20 94bfe4da62c58c85ff520796ac20e992 f846d7e992fb614308eca488666fef2d 58df37d48349089d0edb61e6ccfdcd36 ccfdcd3662c58c85ff520796ac20e992 f846d7e992fb614308eca488666fef2d 58df37d48349089d0edb61e6ccfdcd36 fpscr=00000000
+randV128: 1280 calls, 1328 iters
+vseleq.f32 s15,s16,s20 b5f645db4a1e113763d81166622b730f bdde4a74f34bca9fd48fa5817f3e85e8 29a73642fea1590558474991d06a543b d06a543b4a1e113763d81166622b730f bdde4a74f34bca9fd48fa5817f3e85e8 29a73642fea1590558474991d06a543b fpscr=00000000
+vseleq.f32 s15,s16,s20 8d21b3d932dcba00d91125ece990acad 3f29605bf5c82079527e413731851f3b 6460d033a91fe9feddd1560c2411c369 2411c36932dcba00d91125ece990acad 3f29605bf5c82079527e413731851f3b 6460d033a91fe9feddd1560c2411c369 fpscr=00000000
+vseleq.f32 s15,s16,s20 b7e38909edb6a49feaa8da5aa184ced6 5c1414ab14a7d6623bed80734cd7c5bd ff2c8f9c4e2364608cb1cee2eacd5bdf eacd5bdfedb6a49feaa8da5aa184ced6 5c1414ab14a7d6623bed80734cd7c5bd ff2c8f9c4e2364608cb1cee2eacd5bdf fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vseleq.f32 s15,s16,s20 9d6799bdcdac0b328733f75f3759982f c081c5adc081c5ad24f43c6b291eb00c 4818d1194dd24462b1304608d35f2a2b d35f2a2bcdac0b328733f75f3759982f c081c5adc081c5ad24f43c6b291eb00c 4818d1194dd24462b1304608d35f2a2b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vseleq.f32 s15,s16,s20 e802f1c1e802f1c17ae72bc22e8f641e 7bdf1613f1beedcd2b896e509d357f78 7cb07d22cb4f3562ed6b1695236578ff 236578ffe802f1c17ae72bc22e8f641e 7bdf1613f1beedcd2b896e509d357f78 7cb07d22cb4f3562ed6b1695236578ff fpscr=00000000
+vseleq.f32 s15,s16,s20 c3504f080ead048d0bb4e834ca63e560 4bf498d4ce3cb40a749200c4309e084f d6cfb2e265f4d3df0f462c1d9d4bb3d5 9d4bb3d50ead048d0bb4e834ca63e560 4bf498d4ce3cb40a749200c4309e084f d6cfb2e265f4d3df0f462c1d9d4bb3d5 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vseleq.f32 s15,s16,s20 38d02a97a4326cfb19614c73775ff989 e32d1c61ec623ca54dff9473a96c852e 6ff669b0d2e063009660b1fd2ed965ff 2ed965ffa4326cfb19614c73775ff989 e32d1c61ec623ca54dff9473a96c852e 6ff669b0d2e063009660b1fd2ed965ff fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vseleq.f32 s15,s16,s20 c4275e212ad52c94c1f9fcdd3eaf5055 7e4677bc0ce53d760fbe5d13b05fde15 1324c00be6bb07206095e039b8abd1e9 b8abd1e92ad52c94c1f9fcdd3eaf5055 7e4677bc0ce53d760fbe5d13b05fde15 1324c00be6bb07206095e039b8abd1e9 fpscr=00000000
+vseleq.f32 s15,s16,s20 65f0bc6583d6f95db8e972df9787befa f6db7bd4ddf32d6b43b7c8ef3ae223cd a353739d03d6e8979b96acbbae82c2fb ae82c2fb83d6f95db8e972df9787befa f6db7bd4ddf32d6b43b7c8ef3ae223cd a353739d03d6e8979b96acbbae82c2fb fpscr=00000000
+vseleq.f32 s15,s16,s20 3d29b0d58bac37ba5050a0c705c0703f ca8f419b68669a6f5a18ba9d71c4b19a 9785fc301f7d5670e5028d706c8e8648 6c8e86488bac37ba5050a0c705c0703f ca8f419b68669a6f5a18ba9d71c4b19a 9785fc301f7d5670e5028d706c8e8648 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vseleq.f32 s15,s16,s20 a45857cd827a199ba578e424469fc3b3 ee5aae8a3df59efdb9e88be508aeba7a 411bb7cf5f266815af1733225facf1cd 5facf1cd827a199ba578e424469fc3b3 ee5aae8a3df59efdb9e88be508aeba7a 411bb7cf5f266815af1733225facf1cd fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vseleq.f32 s15,s16,s20 6aaffd8950c2ad7eee86dc86d89a02a4 72e132dbe8f38aabe32895889c597a7a 4eeda00065310174e1400c74661d014c 661d014c50c2ad7eee86dc86d89a02a4 72e132dbe8f38aabe32895889c597a7a 4eeda00065310174e1400c74661d014c fpscr=00000000
+vseleq.f32 s15,s16,s20 20aac7fba7035a204ce72d85dc4d808b edd9afb7e282d4fe0105456ef2468f27 1309051d4eacc4888ad6fb96068abf0c 068abf0ca7035a204ce72d85dc4d808b edd9afb7e282d4fe0105456ef2468f27 1309051d4eacc4888ad6fb96068abf0c fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vseleq.f32 s15,s16,s20 7980d06f7980d06fed6f2adb29971626 7aba1f33118f2529149b127bc394c1ea 2c2f3a49c56f31c8eaefee667eda2b42 7eda2b427980d06fed6f2adb29971626 7aba1f33118f2529149b127bc394c1ea 2c2f3a49c56f31c8eaefee667eda2b42 fpscr=00000000
+vseleq.f32 s15,s16,s20 8863eb170745f4639e63f81cb5cf2a2a 10044db5fdf63e525d3feba342c69747 a8ad0a908c9297293a6069a4d27e0618 d27e06180745f4639e63f81cb5cf2a2a 10044db5fdf63e525d3feba342c69747 a8ad0a908c9297293a6069a4d27e0618 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vseleq.f32 s15,s16,s20 30e8d05bcf5cb2663ddbe9c2a6f6e512 8635167e67ac5eb5aa17bb4e8635167e 158a0ccb99f6f56acd5650670442a34d 0442a34dcf5cb2663ddbe9c2a6f6e512 8635167e67ac5eb5aa17bb4e8635167e 158a0ccb99f6f56acd5650670442a34d fpscr=00000000
+vseleq.f32 s15,s16,s20 04802eb5d90d46256a9a5a4429cccc71 d26511e4ff0ce20a688d0961c2679665 2941597cf59bf63369468aca91e7bf5f 91e7bf5fd90d46256a9a5a4429cccc71 d26511e4ff0ce20a688d0961c2679665 2941597cf59bf63369468aca91e7bf5f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vseleq.f32 s15,s16,s20 c80ba6fbe7af32522831b206e8cd84de 01eda3c60b54746301eda3c6d6ae3f0e ea38cae3d86d22b459ca6ec48bb888ca 8bb888cae7af32522831b206e8cd84de 01eda3c60b54746301eda3c6d6ae3f0e ea38cae3d86d22b459ca6ec48bb888ca fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vseleq.f32 s15,s16,s20 549ca745513e432fc4285cd1c4285cd1 b4b3c7ac513e135cbf752caec4db9ebb c8e0abdeea179a30f3a2b7169958524e 9958524e513e432fc4285cd1c4285cd1 b4b3c7ac513e135cbf752caec4db9ebb c8e0abdeea179a30f3a2b7169958524e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vseleq.f32 s15,s16,s20 56eced5d2bed0a55ac5022f544895d65 646045ea0855a4db8aecc98cd29a05d8 464ff864464ff8642b9dcfe6f0e76a64 f0e76a642bed0a55ac5022f544895d65 646045ea0855a4db8aecc98cd29a05d8 464ff864464ff8642b9dcfe6f0e76a64 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vseleq.f32 s15,s16,s20 df85e6cbcd8274a02a159c8a2a159c8a 98a137169ed08fa2a2ad51411adc27c8 e6f2e4af9be86dd5d64c0ceb13c5d1ea 13c5d1eacd8274a02a159c8a2a159c8a 98a137169ed08fa2a2ad51411adc27c8 e6f2e4af9be86dd5d64c0ceb13c5d1ea fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vseleq.f32 s15,s16,s20 50b91eeffb24a85e19eac1c246587c4b ad51a4afa3951fc0ad51a4afebf0811f 7cf52d7adbda73576afadc07d461c5be d461c5befb24a85e19eac1c246587c4b ad51a4afa3951fc0ad51a4afebf0811f 7cf52d7adbda73576afadc07d461c5be fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[0]
+vseleq.f32 s15,s16,s20 155c00bfbffcb478a107a4a5bffcb478 a31d8010d7c5b28d562b256781909d84 90c25e5a46460db99b03be371a30d4ea 1a30d4eabffcb478a107a4a5bffcb478 a31d8010d7c5b28d562b256781909d84 90c25e5a46460db99b03be371a30d4ea fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vseleq.f32 s15,s16,s20 5bccaf0399e017716fda6d353c80d92e c7fd0aa5779e84ad615eec0be2d4069a 908de6d4beab8dbd606ef04866847d5c 66847d5c99e017716fda6d353c80d92e c7fd0aa5779e84ad615eec0be2d4069a 908de6d4beab8dbd606ef04866847d5c fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vseleq.f32 s15,s16,s20 f83ab7522c93e35c4a9ed0c18140ba1e 0a34096f4b1fa2cd6f5bf05bf25c2697 d93ddc870bec459f189a3bda2be719de 2be719de2c93e35c4a9ed0c18140ba1e 0a34096f4b1fa2cd6f5bf05bf25c2697 d93ddc870bec459f189a3bda2be719de fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vseleq.f32 s15,s16,s20 4a1c07014a17513d78586477b968384e fc97b59316ecfd5a6c1467c1654c1e90 e3680e1a99f0229f6064465260644652 606446524a17513d78586477b968384e fc97b59316ecfd5a6c1467c1654c1e90 e3680e1a99f0229f6064465260644652 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vseleq.f32 s15,s16,s20 55b67f0687e52afa6beb3f0c6beb3f0c a7e7c4465daaf8f65719a83e389ae908 842d0d22b7e5c00773cff78a6127c486 6127c48687e52afa6beb3f0c6beb3f0c a7e7c4465daaf8f65719a83e389ae908 842d0d22b7e5c00773cff78a6127c486 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vseleq.f32 s15,s16,s20 7438e5177180bc53b94bcd6155097fc4 d0a0fbea55a502d2d0a0fbeaa9a95a58 8a89d0e8fb196c32bd3d7a4b24a470f9 24a470f97180bc53b94bcd6155097fc4 d0a0fbea55a502d2d0a0fbeaa9a95a58 8a89d0e8fb196c32bd3d7a4b24a470f9 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vseleq.f32 s15,s16,s20 85fc1880a367493e9caa7d8817532c0e fea9c4fcc3e38a989f18b2dab4190ec0 edec575cae5beffa32ff73ebae5beffa ae5beffaa367493e9caa7d8817532c0e fea9c4fcc3e38a989f18b2dab4190ec0 edec575cae5beffa32ff73ebae5beffa fpscr=00000000
+vseleq.f32 s15,s16,s20 593892176f9b2e730a6477f66c8a09b0 e29887d09eee2923bd176f271d15f672 82db5771c6a6c0162d8e43a9cdb03e91 cdb03e916f9b2e730a6477f66c8a09b0 e29887d09eee2923bd176f271d15f672 82db5771c6a6c0162d8e43a9cdb03e91 fpscr=00000000
+vseleq.f32 s15,s16,s20 a35552ae5a03aa438878d134f064c3c8 989af7366f888734b026abafebc33787 6fd4375d04e57a2a97d5eef5aa4e0cd7 aa4e0cd75a03aa438878d134f064c3c8 989af7366f888734b026abafebc33787 6fd4375d04e57a2a97d5eef5aa4e0cd7 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vseleq.f32 s15,s16,s20 e7b14f54ab7185049b337ce7f5b461a0 0700975da04de2f3b3706a364da1adc6 ae0f307db8d9980db637fefbb637fefb b637fefbab7185049b337ce7f5b461a0 0700975da04de2f3b3706a364da1adc6 ae0f307db8d9980db637fefbb637fefb fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[3]
+vseleq.f32 s15,s16,s20 92c9db4f0768629292c9db4f6ac68aca e527e38fbfe9db5a360ff7af360ff7af 1406d41b64516599ff275af8518d666b 518d666b0768629292c9db4f6ac68aca e527e38fbfe9db5a360ff7af360ff7af 1406d41b64516599ff275af8518d666b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vseleq.f32 s15,s16,s20 ba868b5c4fdc104504b1e38195d7d957 0a40fde54650557bb0e5631d3720ea00 aae28ebe327427bc5ff800963a1f4020 3a1f40204fdc104504b1e38195d7d957 0a40fde54650557bb0e5631d3720ea00 aae28ebe327427bc5ff800963a1f4020 fpscr=00000000
+vseleq.f32 s15,s16,s20 2317928286b6ce8ad0166cde42c04b59 3e915188fb20e315c8fb07e70dd889d1 66aeb4e3b94723be200657ae56e61ddd 56e61ddd86b6ce8ad0166cde42c04b59 3e915188fb20e315c8fb07e70dd889d1 66aeb4e3b94723be200657ae56e61ddd fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[2]
+vseleq.f32 s15,s16,s20 84816d3c4cc655bb0f7b5edb5f59ede0 f35aa3766b2d140bf35aa3762c1746f4 b9c2430170a98b5f9282753b7f3f95a2 7f3f95a24cc655bb0f7b5edb5f59ede0 f35aa3766b2d140bf35aa3762c1746f4 b9c2430170a98b5f9282753b7f3f95a2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[1]
+vseleq.f32 s15,s16,s20 dd197c89fba99b25dd197c89e263dfb6 2e8cc2d8281af14681b732c523c2326d 550d50719989722807d7da346f2f6074 6f2f6074fba99b25dd197c89e263dfb6 2e8cc2d8281af14681b732c523c2326d 550d50719989722807d7da346f2f6074 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 e8e1c927addada11a6c73bdf5e7fbd85 cb96f09c2fc9268c6b7e9b93d19b5bba 9e1f821146911981b72983da1ddfa47d b72983da1ddfa47da6c73bdf5e7fbd85 cb96f09c2fc9268c6b7e9b93d19b5bba 9e1f821146911981b72983da1ddfa47d fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 b53c235c46486e774b773bc5de6d4be1 3f1b397d79033a03d712d082d1736ceb 5d722a864227fcd05d722a864227fcd0 5d722a864227fcd04b773bc5de6d4be1 3f1b397d79033a03d712d082d1736ceb 5d722a864227fcd05d722a864227fcd0 fpscr=00000000
+vseleq.f64 d7, d8, d10 09b5794d843f0c10d6262add1d7e702d da88fe1cfa0828d9015823c90739a0c5 e0cb80cf05611bff619065358cc061dc 619065358cc061dcd6262add1d7e702d da88fe1cfa0828d9015823c90739a0c5 e0cb80cf05611bff619065358cc061dc fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 9e66898026b4ad61be52ab5e419ed198 a6f557065fc07cb7a6f557065fc07cb7 ed4db65183a2bd306af5bb9081277c34 6af5bb9081277c34be52ab5e419ed198 a6f557065fc07cb7a6f557065fc07cb7 ed4db65183a2bd306af5bb9081277c34 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 2db581639913155b012a564eec402108 08fce825a42f83af9081814ecedcf17b c80d0d8d0892c2b18ac0326f92f544c1 8ac0326f92f544c1012a564eec402108 08fce825a42f83af9081814ecedcf17b c80d0d8d0892c2b18ac0326f92f544c1 fpscr=00000000
+randV128: 1536 calls, 1595 iters
+vseleq.f64 d7, d8, d10 b4923838ce1803aed8154112b81f1215 ed12f64a2fdf7940402282f316476c55 05eab7412d7368e76cfd35f721892d34 6cfd35f721892d34d8154112b81f1215 ed12f64a2fdf7940402282f316476c55 05eab7412d7368e76cfd35f721892d34 fpscr=00000000
+vseleq.f64 d7, d8, d10 971938f5ebed65cc4d7f293d9d790543 d73aef07be63fded627d1bce4ce0351c f4eff2fc7239a39c99d73f4ec6e5335d 99d73f4ec6e5335d4d7f293d9d790543 d73aef07be63fded627d1bce4ce0351c f4eff2fc7239a39c99d73f4ec6e5335d fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 435d66fee065aa82435d66fee065aa82 bb46e63d38e37ebd40f3bad5aedd625c 6878a7d79e993d19864acdc81e9d8711 864acdc81e9d8711435d66fee065aa82 bb46e63d38e37ebd40f3bad5aedd625c 6878a7d79e993d19864acdc81e9d8711 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 1dbf63c6e0948eecf363f7cefcda2d6b e36d1f5407c8246527734c8517ad2557 c2a877b6f6c0e32dc2a877b6f6c0e32d c2a877b6f6c0e32df363f7cefcda2d6b e36d1f5407c8246527734c8517ad2557 c2a877b6f6c0e32dc2a877b6f6c0e32d fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 56f63f9ef45df5b356f63f9ef45df5b3 ed522c046a4d330e65e03223557cced0 e9f57daed1254c33a14ac880f3b84c3c a14ac880f3b84c3c56f63f9ef45df5b3 ed522c046a4d330e65e03223557cced0 e9f57daed1254c33a14ac880f3b84c3c fpscr=00000000
+vseleq.f64 d7, d8, d10 8513a41c82218811983fe514d246fd45 3e1050271b8f4c06c1c6d81e6d774ce2 53d158a6d3399bb9470c4c8a595a8210 470c4c8a595a8210983fe514d246fd45 3e1050271b8f4c06c1c6d81e6d774ce2 53d158a6d3399bb9470c4c8a595a8210 fpscr=00000000
+vseleq.f64 d7, d8, d10 a55fa8df6641d52e6ea2e2dc54a10fc7 3262d882703fd813522b13c9de7de242 cda8c815645ddfc3969d32a6a75f7a73 969d32a6a75f7a736ea2e2dc54a10fc7 3262d882703fd813522b13c9de7de242 cda8c815645ddfc3969d32a6a75f7a73 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 4a371c043d62073e26324ee8587a8117 3d11797b59556e8ce0247e79413e93fd cc4704a7fd7539a6cc4704a7fd7539a6 cc4704a7fd7539a626324ee8587a8117 3d11797b59556e8ce0247e79413e93fd cc4704a7fd7539a6cc4704a7fd7539a6 fpscr=00000000
+vseleq.f64 d7, d8, d10 ed4ee26dd6e7401916eb479a7926673e 9e20d8eec432c40db1dd9cae316c95fa a64fb757cf0d76ca3c3107b68984d4db 3c3107b68984d4db16eb479a7926673e 9e20d8eec432c40db1dd9cae316c95fa a64fb757cf0d76ca3c3107b68984d4db fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 776f3ff8d06060f45e502021988f328d 91d1f8609c23e1fd91d1f8609c23e1fd 036ab43b0d56205ba781d781d92b430e a781d781d92b430e5e502021988f328d 91d1f8609c23e1fd91d1f8609c23e1fd 036ab43b0d56205ba781d781d92b430e fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 df996abe5602a84d3a8792ed33410284 f226f070a8a60a04ca3943a33c6069de e2eeb2b7639ccfa08f7aab0a3b944097 8f7aab0a3b9440973a8792ed33410284 f226f070a8a60a04ca3943a33c6069de e2eeb2b7639ccfa08f7aab0a3b944097 fpscr=00000000
+vseleq.f64 d7, d8, d10 e76006f725db600f146a48c1c8566bfc f68a0b8459738887cd96c3a8bc9a5043 8b34c676e83d0aef0c8d6baabc3d734f 0c8d6baabc3d734f146a48c1c8566bfc f68a0b8459738887cd96c3a8bc9a5043 8b34c676e83d0aef0c8d6baabc3d734f fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 b4daf384361edcd960966ec844c65dcc 33748cb804f98d51ad92770e6b8c2d6a 131b454345e79e7e98a8b3cc19fd2f10 98a8b3cc19fd2f1060966ec844c65dcc 33748cb804f98d51ad92770e6b8c2d6a 131b454345e79e7e98a8b3cc19fd2f10 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 951b9b03782bd2c751f9b52ed37a1d4e d7679e5829ccc78138adcc66eddbf4ea da3cc0fe83f6f8a2da3cc0fe83f6f8a2 da3cc0fe83f6f8a251f9b52ed37a1d4e d7679e5829ccc78138adcc66eddbf4ea da3cc0fe83f6f8a2da3cc0fe83f6f8a2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 b9b475c74a9ac7e4f0024fea1ce9d44a 43599078aa14a9e2bc2aa0ee8306fb8a 2f691e58a67fb94603f4c5b10d41c54a 03f4c5b10d41c54af0024fea1ce9d44a 43599078aa14a9e2bc2aa0ee8306fb8a 2f691e58a67fb94603f4c5b10d41c54a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 c12915c64a63fe5ac12915c64a63fe5a e7fbe6108175a0a2d27c2885fdb529ff 2502b2739e67a54957fdd600e1d1592a 57fdd600e1d1592ac12915c64a63fe5a e7fbe6108175a0a2d27c2885fdb529ff 2502b2739e67a54957fdd600e1d1592a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 9ac39034ba3be9269fd30f8a03b282f7 d82f6a47ac22b0c4bfd1b2202a1a0faf 07dc3d60ae9fe86f753d505c0ab09ee1 753d505c0ab09ee19fd30f8a03b282f7 d82f6a47ac22b0c4bfd1b2202a1a0faf 07dc3d60ae9fe86f753d505c0ab09ee1 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 8e361a535a0e6be515814afcc8ac5227 c1b66eb008c0e757c1b66eb008c0e757 511826a6ea51a34e28271b5982bbadd4 28271b5982bbadd415814afcc8ac5227 c1b66eb008c0e757c1b66eb008c0e757 511826a6ea51a34e28271b5982bbadd4 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 b1504a38ccad3e07b6f04851f13bc773 75478330a1b498178e86f1ef9dc577e5 978548d16d6bf9832414c3af14ec53a3 2414c3af14ec53a3b6f04851f13bc773 75478330a1b498178e86f1ef9dc577e5 978548d16d6bf9832414c3af14ec53a3 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 d1f79073408676e6544da1105bccb169 8df370c44ca3c52de54632e74945f33b 719783eca8c17c9c179d7439f1dc0f5e 179d7439f1dc0f5e544da1105bccb169 8df370c44ca3c52de54632e74945f33b 719783eca8c17c9c179d7439f1dc0f5e fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 e49d48367703dd30953c90570c5d2a68 98b7359f05ab12e36c26fabc992a39f4 fab1f066f1c39b72fab1f066f1c39b72 fab1f066f1c39b72953c90570c5d2a68 98b7359f05ab12e36c26fabc992a39f4 fab1f066f1c39b72fab1f066f1c39b72 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 7ebd46c72a43c1ae00ad05ca0aeeb1c6 7820294273b14b6b7820294273b14b6b fa8a8f2701ab82af6115d46a8a9ea689 6115d46a8a9ea68900ad05ca0aeeb1c6 7820294273b14b6b7820294273b14b6b fa8a8f2701ab82af6115d46a8a9ea689 fpscr=00000000
+vseleq.f64 d7, d8, d10 5ff02707e2ffe81e3d616f6e5273703c e927bc1914a613af65dfc93d02731cbf 6745cdd370da388f06c97f2c531b1d67 06c97f2c531b1d673d616f6e5273703c e927bc1914a613af65dfc93d02731cbf 6745cdd370da388f06c97f2c531b1d67 fpscr=00000000
+vseleq.f64 d7, d8, d10 6f3a14e08a109ffc5653bc8638c0a49b d783625f1c9a65acf9bfde9d8ef03331 4c5bcdde2b857f35bcdaead22207c663 bcdaead22207c6635653bc8638c0a49b d783625f1c9a65acf9bfde9d8ef03331 4c5bcdde2b857f35bcdaead22207c663 fpscr=00000000
+vseleq.f64 d7, d8, d10 7f3e2cfaabc8640652ae595ea822c0ef 67352a0efd872b24e2bb9047ad98a58e e637d7a002b3a67396639a49b7b93025 96639a49b7b9302552ae595ea822c0ef 67352a0efd872b24e2bb9047ad98a58e e637d7a002b3a67396639a49b7b93025 fpscr=00000000
+vseleq.f64 d7, d8, d10 c762f25c38b87c653cb33a082cc900a5 9586f1c2542df0398ae50eaa17ce92ad 3ea7a83efbd0ea437cc59350230a289a 7cc59350230a289a3cb33a082cc900a5 9586f1c2542df0398ae50eaa17ce92ad 3ea7a83efbd0ea437cc59350230a289a fpscr=00000000
+vseleq.f64 d7, d8, d10 6d5471551e91c3d406769835f7a68289 9dc79a349e40d527781e1631a8850d52 f17ce243e19344a0160660602c934a5f 160660602c934a5f06769835f7a68289 9dc79a349e40d527781e1631a8850d52 f17ce243e19344a0160660602c934a5f fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 5c2200532db7a21160731b00026318af cd6a13aef9b38be308a1abc507c0e8be d07d9db9f252e24845a8060da389b305 45a8060da389b30560731b00026318af cd6a13aef9b38be308a1abc507c0e8be d07d9db9f252e24845a8060da389b305 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 5cee19087455e09f1596c60a31728d51 d741906c4a29d78ad741906c4a29d78a 5914e7e42a7a71ba50823ba4cc670369 50823ba4cc6703691596c60a31728d51 d741906c4a29d78ad741906c4a29d78a 5914e7e42a7a71ba50823ba4cc670369 fpscr=00000000
+vseleq.f64 d7, d8, d10 86fa5b0decf3c4036f990f4eb131f511 b169e9ce39f9a86d69613a927548f5f7 d0f436d919b5e68b1cfefea5afe9cdab 1cfefea5afe9cdab6f990f4eb131f511 b169e9ce39f9a86d69613a927548f5f7 d0f436d919b5e68b1cfefea5afe9cdab fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 c148387a3e593261c148387a3e593261 c9dff1ee88dc4f64754589366d561fb3 bf61ae782ec58267befd9728bbf004eb befd9728bbf004ebc148387a3e593261 c9dff1ee88dc4f64754589366d561fb3 bf61ae782ec58267befd9728bbf004eb fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 f846be4fd0ff83ec73d785a097a85aa0 9769aa9589a2e3129769aa9589a2e312 856ce7a918818bc86f50750417a5246f 6f50750417a5246f73d785a097a85aa0 9769aa9589a2e3129769aa9589a2e312 856ce7a918818bc86f50750417a5246f fpscr=00000000
+vseleq.f64 d7, d8, d10 2fc9948aee3b876871c92bffd4630379 0f99f383f262aea5b7065cf0c4d8ee9a 27614e3cf98d83090455c14f5674321d 0455c14f5674321d71c92bffd4630379 0f99f383f262aea5b7065cf0c4d8ee9a 27614e3cf98d83090455c14f5674321d fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 3ad150fc5b6908ce67c9ea6076576649 3656908bdc978df88444a5cc0db4fa55 41d638e93e7dd97cbc65c8ba53e043a3 bc65c8ba53e043a367c9ea6076576649 3656908bdc978df88444a5cc0db4fa55 41d638e93e7dd97cbc65c8ba53e043a3 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 33a228f9830807118bae4dffa1bb7379 389c1a4d568d8d3620104d79833ef33c 5c8eed6608a6b8d1064a9e3ad001994e 064a9e3ad001994e8bae4dffa1bb7379 389c1a4d568d8d3620104d79833ef33c 5c8eed6608a6b8d1064a9e3ad001994e fpscr=00000000
+vseleq.f64 d7, d8, d10 5aa4fd3d875a96a2792c8b7887b6f63e 10089529bb688260dce41f2ca1e10920 b9a0e3baf114e44ce600c387e6361aaa e600c387e6361aaa792c8b7887b6f63e 10089529bb688260dce41f2ca1e10920 b9a0e3baf114e44ce600c387e6361aaa fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 926059f806150662aaf06cf17ca10c09 88a94f4d9eb476a39d49c4c2cdb29686 e87e9c1ccb21f126194c298c8f7cf9fc 194c298c8f7cf9fcaaf06cf17ca10c09 88a94f4d9eb476a39d49c4c2cdb29686 e87e9c1ccb21f126194c298c8f7cf9fc fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vseleq.f64 d7, d8, d10 649fb91444a85759339688bf5cb26baa 7579ad460d8ac8fd0c07f6e50f3640c3 20f1e0b3c777e933db0c79edca0d1445 db0c79edca0d1445339688bf5cb26baa 7579ad460d8ac8fd0c07f6e50f3640c3 20f1e0b3c777e933db0c79edca0d1445 fpscr=00000000
+vseleq.f64 d7, d8, d10 b12f76631b32bd41aed1633909582ad6 4683e5ef0298c3535817fa1ee38ba609 9a3854c43cfe7135756cb774e96fbc0a 756cb774e96fbc0aaed1633909582ad6 4683e5ef0298c3535817fa1ee38ba609 9a3854c43cfe7135756cb774e96fbc0a fpscr=00000000
+vseleq.f64 d7, d8, d10 29e1f2dc792e5efd93fcd510e4255ade 3c2d75b22e70d36c09cf62f062ff1935 09f35fa9ca8f3ffb7e371c361bff130b 7e371c361bff130b93fcd510e4255ade 3c2d75b22e70d36c09cf62f062ff1935 09f35fa9ca8f3ffb7e371c361bff130b fpscr=00000000
+vseleq.f64 d7, d8, d10 90e87bdd082b7dedb2ad2214c064d23f e48c664ff3f48fa86ec0e2ba54e85cfe f07391b940ecebff5d41fa31b8b99aef 5d41fa31b8b99aefb2ad2214c064d23f e48c664ff3f48fa86ec0e2ba54e85cfe f07391b940ecebff5d41fa31b8b99aef fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vseleq.f64 d7, d8, d10 1f6fade310f6ec181ac7c4162ce9bf5d 1ed9165cf1666d362c7c47c2f06c3ed9 197064f462da0b21ed360fd1dfa911f6 ed360fd1dfa911f61ac7c4162ce9bf5d 1ed9165cf1666d362c7c47c2f06c3ed9 197064f462da0b21ed360fd1dfa911f6 fpscr=00000000
+vseleq.f64 d7, d8, d10 d1191ea440d149950b2a9a77b77841f8 adec3a4fe88117d57f6eeda0a2a392a6 8b0100f58a3193ea534c3f4d54fb0298 534c3f4d54fb02980b2a9a77b77841f8 adec3a4fe88117d57f6eeda0a2a392a6 8b0100f58a3193ea534c3f4d54fb0298 fpscr=00000000
+randV128: 1792 calls, 1855 iters
+vseleq.f64 d7, d8, d10 07b6daba274efad39c88103d8ff70513 eddcc28943c51e6768628f085cafcca9 3f3939b0613776619e0d5aca932d5ae1 9e0d5aca932d5ae19c88103d8ff70513 eddcc28943c51e6768628f085cafcca9 3f3939b0613776619e0d5aca932d5ae1 fpscr=00000000
+vseleq.f64 d7, d8, d10 748050fab4847bfc238293494f21fca6 ba3e6dfec5d1afe74928eca0b8b4a90c 83ea5fdcf80d6c15a4c5b707f9173435 a4c5b707f9173435238293494f21fca6 ba3e6dfec5d1afe74928eca0b8b4a90c 83ea5fdcf80d6c15a4c5b707f9173435 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vselvs.f32 s15,s16,s20 810f3770134ee8b63b1f72984149219d 6617b826e12955b7ddc20e4d86b96483 98c3cc7c9f6f4580deec6f1698c3cc7c 98c3cc7c134ee8b63b1f72984149219d 6617b826e12955b7ddc20e4d86b96483 98c3cc7c9f6f4580deec6f1698c3cc7c fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vselvs.f32 s15,s16,s20 22b22bcec66697e83d076bb653313a0e e395fee086a639f6e395fee0d8d885af 297b6ee70b1f49a19d3374c4a97c5d61 a97c5d61c66697e83d076bb653313a0e e395fee086a639f6e395fee0d8d885af 297b6ee70b1f49a19d3374c4a97c5d61 fpscr=00000000
+vselvs.f32 s15,s16,s20 6421d3a4370cad9550dea420bd1b2043 9de3b8cec11ccb19d2b368a946d06f7c 3dd1d155c1f48af22d1951e72f690496 2f690496370cad9550dea420bd1b2043 9de3b8cec11ccb19d2b368a946d06f7c 3dd1d155c1f48af22d1951e72f690496 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vselvs.f32 s15,s16,s20 3dfac3e6fc4a5cb707ea41e60b86ce74 725cbb44f589641ca1722a9e37e8d7e6 c23c0389e954d394e954d3943dec40a7 3dec40a7fc4a5cb707ea41e60b86ce74 725cbb44f589641ca1722a9e37e8d7e6 c23c0389e954d394e954d3943dec40a7 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[2]
+vselvs.f32 s15,s16,s20 970aee52e18b4aae3cff0bce3cff0bce 3545f68ff4093549fd0b0600f4093549 eea5a8b334dd79461453861ef4365dab f4365dabe18b4aae3cff0bce3cff0bce 3545f68ff4093549fd0b0600f4093549 eea5a8b334dd79461453861ef4365dab fpscr=00000000
+vselvs.f32 s15,s16,s20 f1a8f12219c85df7728a9ac8e5ebeb5d 017b120053c576502975eb08ee5e72b0 9f273c8da890a0c6e3e5659ff188e73a f188e73a19c85df7728a9ac8e5ebeb5d 017b120053c576502975eb08ee5e72b0 9f273c8da890a0c6e3e5659ff188e73a fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vselvs.f32 s15,s16,s20 421e57b476b35703f8f0f1eb3fc28fd0 26a08e658377d12725708809765a4348 883ac891f0494293aa7d9ea5883ac891 883ac89176b35703f8f0f1eb3fc28fd0 26a08e658377d12725708809765a4348 883ac891f0494293aa7d9ea5883ac891 fpscr=00000000
+vselvs.f32 s15,s16,s20 b5705464e08e18c566ca2d32e224225d bfe71c46956bf33b64ddb3f7729d601a d08752515fa192d8b248ad4c876c1ef5 876c1ef5e08e18c566ca2d32e224225d bfe71c46956bf33b64ddb3f7729d601a d08752515fa192d8b248ad4c876c1ef5 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[2]
+vselvs.f32 s15,s16,s20 f21753b9b18a8066d462a96eb18a8066 4f89b7e24b491dd6061815404b491dd6 391d0e3a673b3de33d9c62d11814680f 1814680fb18a8066d462a96eb18a8066 4f89b7e24b491dd6061815404b491dd6 391d0e3a673b3de33d9c62d11814680f fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vselvs.f32 s15,s16,s20 37ae26b044b2de6fb568e08d6d2a278b 6c5d2f39036958cea0229efd40fea670 058e83ee9da4beb1403017f803ae36d7 03ae36d744b2de6fb568e08d6d2a278b 6c5d2f39036958cea0229efd40fea670 058e83ee9da4beb1403017f803ae36d7 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vselvs.f32 s15,s16,s20 3216c9f795f7e5504112e6a2fc92f0f4 7031a787e098bc6058a089ac3738e6b7 698e5e5ad5fd87ba1f1d003a1f1d003a 1f1d003a95f7e5504112e6a2fc92f0f4 7031a787e098bc6058a089ac3738e6b7 698e5e5ad5fd87ba1f1d003a1f1d003a fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vselvs.f32 s15,s16,s20 c85515a2ead61e19a1d1d58123a97b9e 93dd1f32479c31822c6aaac4ded2c45b f7e0cbf647faaee22eadf7ba7b32a72d 7b32a72dead61e19a1d1d58123a97b9e 93dd1f32479c31822c6aaac4ded2c45b f7e0cbf647faaee22eadf7ba7b32a72d fpscr=00000000
+vselvs.f32 s15,s16,s20 a81e08ddd658afaea746f211f5a901ee 74553975c77e5cd1fb79c0c865410bfd 12331df72e6e1d71c3eab80ee22731fc e22731fcd658afaea746f211f5a901ee 74553975c77e5cd1fb79c0c865410bfd 12331df72e6e1d71c3eab80ee22731fc fpscr=00000000
+vselvs.f32 s15,s16,s20 c24ee87b05bcbd7e79f33cc7c8a8ad19 74f0a5944207a687dbec3ad63c068b79 2f00b64006ecdbbd2143173fcc9bb102 cc9bb10205bcbd7e79f33cc7c8a8ad19 74f0a5944207a687dbec3ad63c068b79 2f00b64006ecdbbd2143173fcc9bb102 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vselvs.f32 s15,s16,s20 e3518329d34af5a644852d511c8e6c46 59ce50d50df06b44198bb8a0a8016332 e4a5841b7103f964b9701c46a1bdeb2b a1bdeb2bd34af5a644852d511c8e6c46 59ce50d50df06b44198bb8a0a8016332 e4a5841b7103f964b9701c46a1bdeb2b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vselvs.f32 s15,s16,s20 c9611cde37959b4cd91e5db77abc3411 40d8eaf997f07414df561343ef2337b3 2f36f140109e6891175645ee51690d13 51690d1337959b4cd91e5db77abc3411 40d8eaf997f07414df561343ef2337b3 2f36f140109e6891175645ee51690d13 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vselvs.f32 s15,s16,s20 9a69108c551c107004420fac9e347c33 5dde29fdf15e518c52eedb75afa3e0d1 37b1a3d08f37b0c2eef2a7fb13d1dcf3 13d1dcf3551c107004420fac9e347c33 5dde29fdf15e518c52eedb75afa3e0d1 37b1a3d08f37b0c2eef2a7fb13d1dcf3 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vselvs.f32 s15,s16,s20 044c111eab69783527c0ccd64ec77b5e 6b0c1b499efdcc70738adf8451897de0 99eb8fbdb138d3fcf484296aa20c8585 a20c8585ab69783527c0ccd64ec77b5e 6b0c1b499efdcc70738adf8451897de0 99eb8fbdb138d3fcf484296aa20c8585 fpscr=00000000
+vselvs.f32 s15,s16,s20 98d573ff6be909f2878aa1d2f6b72d29 9b8fb02408800f5ea17a225c568a2d61 fd1e492774a4ac989061f4b8a0ce54b5 a0ce54b56be909f2878aa1d2f6b72d29 9b8fb02408800f5ea17a225c568a2d61 fd1e492774a4ac989061f4b8a0ce54b5 fpscr=00000000
+vselvs.f32 s15,s16,s20 b34620abd5a9c9ddebe1c6769134480e 4d459aa838986faf397cae705c2d71a9 31cb9419678908e2d05ad9cf563e036f 563e036fd5a9c9ddebe1c6769134480e 4d459aa838986faf397cae705c2d71a9 31cb9419678908e2d05ad9cf563e036f fpscr=00000000
+vselvs.f32 s15,s16,s20 a77805d7a2c5e48fbd1ceb54765047a9 ed6589ed7adfec53c663c42adecbe286 c9f3b0d9cbbec136cb89846993654ee2 93654ee2a2c5e48fbd1ceb54765047a9 ed6589ed7adfec53c663c42adecbe286 c9f3b0d9cbbec136cb89846993654ee2 fpscr=00000000
+vselvs.f32 s15,s16,s20 a14a546f95a359e7fcb85a3bc4d61585 ed300d3884f7200dfd646657db9df537 144c77bbe4b39739b22b5fa50ce74d81 0ce74d8195a359e7fcb85a3bc4d61585 ed300d3884f7200dfd646657db9df537 144c77bbe4b39739b22b5fa50ce74d81 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vselvs.f32 s15,s16,s20 bf5cf8ccbfa4fe3bbfa4fe3bba2c25f9 8080370720eda75818743c0305578e82 a05c76e7f08b4e067870ccdd4368dbff 4368dbffbfa4fe3bbfa4fe3bba2c25f9 8080370720eda75818743c0305578e82 a05c76e7f08b4e067870ccdd4368dbff fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselvs.f32 s15,s16,s20 2227b25bf76e44710db537edfcca8dad 59a42780692c5b4359a427809e79eff3 e2429bf8c354fb8fafbae8da0f0132c9 0f0132c9f76e44710db537edfcca8dad 59a42780692c5b4359a427809e79eff3 e2429bf8c354fb8fafbae8da0f0132c9 fpscr=00000000
+vselvs.f32 s15,s16,s20 bcedd93fd90bac7641c309b05daaa174 39ccf4498e895c2d01c639eb9e139c0b 4e48a5da3966e6885381e90d77828792 77828792d90bac7641c309b05daaa174 39ccf4498e895c2d01c639eb9e139c0b 4e48a5da3966e6885381e90d77828792 fpscr=00000000
+vselvs.f32 s15,s16,s20 45ac8b1e1c7efdc1a32a1df9e4e67692 72d8bd4d4ec708b369bfcfe220740e6a a13133149277221a62b7395deb0774bd eb0774bd1c7efdc1a32a1df9e4e67692 72d8bd4d4ec708b369bfcfe220740e6a a13133149277221a62b7395deb0774bd fpscr=00000000
+vselvs.f32 s15,s16,s20 6364a981b685610d6ec97c34a902f4c8 37d830b415b4ad60d4cfaf59b95e672b f4beabb126f02ced78d65b3b276b244e 276b244eb685610d6ec97c34a902f4c8 37d830b415b4ad60d4cfaf59b95e672b f4beabb126f02ced78d65b3b276b244e fpscr=00000000
+vselvs.f32 s15,s16,s20 2b95cbb202622d87cb606a24c50eefdb 8232057ea27bbe83c5e63781fdd60aa4 8c2a31b24491216180864a1acaebd2b5 caebd2b502622d87cb606a24c50eefdb 8232057ea27bbe83c5e63781fdd60aa4 8c2a31b24491216180864a1acaebd2b5 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vselvs.f32 s15,s16,s20 cff69ed2926562d07f602846855c7f5f a180c0a3244fa1681cf5c6b9e7319bb1 c6d6f7eb407ec935e689d848e9634eaa e9634eaa926562d07f602846855c7f5f a180c0a3244fa1681cf5c6b9e7319bb1 c6d6f7eb407ec935e689d848e9634eaa fpscr=00000000
+vselvs.f32 s15,s16,s20 0ccd90a52685b6a9a32c1c9f5c63219d b061d02fb95af08f3752014f9702ecec 134f450c2b4ff97ee836bf722d4ccf39 2d4ccf392685b6a9a32c1c9f5c63219d b061d02fb95af08f3752014f9702ecec 134f450c2b4ff97ee836bf722d4ccf39 fpscr=00000000
+vselvs.f32 s15,s16,s20 3c828bb6e28f48cde4eca7589b610033 a7000f618b3259663ed955e62cf79143 a8973c52e84ae21aab46db179ab174b7 9ab174b7e28f48cde4eca7589b610033 a7000f618b3259663ed955e62cf79143 a8973c52e84ae21aab46db179ab174b7 fpscr=00000000
+vselvs.f32 s15,s16,s20 383368625812cd5aaf536f542dd899b0 57773d100ef41c1d3d437f11b869a7ca 932245eccf703b2d36cb314054bae5e8 54bae5e85812cd5aaf536f542dd899b0 57773d100ef41c1d3d437f11b869a7ca 932245eccf703b2d36cb314054bae5e8 fpscr=00000000
+vselvs.f32 s15,s16,s20 f003ee1de53592d88760940b65923018 7a8b6278062605d3f45fef6967e74939 56e7cf6f45df458beb8330f9a2c60320 a2c60320e53592d88760940b65923018 7a8b6278062605d3f45fef6967e74939 56e7cf6f45df458beb8330f9a2c60320 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[2]
+vselvs.f32 s15,s16,s20 201ac4a77ab50f5f7ab50f5f3af0f73d 296e9ee0f609c5664cae47e7b48914f1 b4ade50b9522975bb44591b5f1c05114 f1c051147ab50f5f7ab50f5f3af0f73d 296e9ee0f609c5664cae47e7b48914f1 b4ade50b9522975bb44591b5f1c05114 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vselvs.f32 s15,s16,s20 de9db706de9db706a81e1ccb16cb716a bf9a5ca70a53339db0a5b22d13fa51aa de00125bbfb9ae8901dbcf3ee3eac664 e3eac664de9db706a81e1ccb16cb716a bf9a5ca70a53339db0a5b22d13fa51aa de00125bbfb9ae8901dbcf3ee3eac664 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vselvs.f32 s15,s16,s20 120bf46a4cd0e40541986c103e26886f 130ca9ed1340d9cc8136a1f04c0b5442 f67f6d2986355d0796d53a13cc0d9649 cc0d96494cd0e40541986c103e26886f 130ca9ed1340d9cc8136a1f04c0b5442 f67f6d2986355d0796d53a13cc0d9649 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[2]
+vselvs.f32 s15,s16,s20 c03cd1d780f264bac03cd1d7511e4895 3760fe183760fe18f06e0104ff0dc3f1 b1191a95eacf7c4e7dd3260a4c984bfe 4c984bfe80f264bac03cd1d7511e4895 3760fe183760fe18f06e0104ff0dc3f1 b1191a95eacf7c4e7dd3260a4c984bfe fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vselvs.f32 s15,s16,s20 b8785d05b8785d05241e65812ead38ae 511859461d757c25d15289792f07f3d1 6e464ad1e015fec92b83601163a667ed 63a667edb8785d05241e65812ead38ae 511859461d757c25d15289792f07f3d1 6e464ad1e015fec92b83601163a667ed fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vselvs.f32 s15,s16,s20 e2c82e6f24a15c422525dfaf3cae565b 0294017cf850c98b69f834aa4b45fb76 df29f4aafdbbf039919dea22e6d79f9a e6d79f9a24a15c422525dfaf3cae565b 0294017cf850c98b69f834aa4b45fb76 df29f4aafdbbf039919dea22e6d79f9a fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[3]
+vselvs.f32 s15,s16,s20 f2b39b0e8e489d94d3b85825a6728fab d825397a581b21ad280e3f64c5d5316f c13ecf3e9c1de9e4097df99b7b3d684c 7b3d684c8e489d94d3b85825a6728fab d825397a581b21ad280e3f64c5d5316f c13ecf3e9c1de9e4097df99b7b3d684c fpscr=00000000
+vselvs.f32 s15,s16,s20 4f85935a48c3ee9937e0630fefd90988 c818d74d074cde5c1f27c25e0c050ff0 ed5b398f1d7abd2c2cea7212710dd87e 710dd87e48c3ee9937e0630fefd90988 c818d74d074cde5c1f27c25e0c050ff0 ed5b398f1d7abd2c2cea7212710dd87e fpscr=00000000
+randV128: 2048 calls, 2118 iters
+randV128: doing v->u32[2] = v->u32[0]
+vselvs.f32 s15,s16,s20 f7b9a82658c78dcf891722f3b0aea5fc 65a3c7477082ee00bcb93d29bf6d6fed fb7a7b1946c3e1522f6ad441c6bd9af3 c6bd9af358c78dcf891722f3b0aea5fc 65a3c7477082ee00bcb93d29bf6d6fed fb7a7b1946c3e1522f6ad441c6bd9af3 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vselvs.f32 s15,s16,s20 dfbcd8f2615bd4d0c04dc6893eada9f3 f92cdd8cfa0726faad40b1e1696cdbf9 709ec90187543a71614a0a57614a0a57 614a0a57615bd4d0c04dc6893eada9f3 f92cdd8cfa0726faad40b1e1696cdbf9 709ec90187543a71614a0a57614a0a57 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vselvs.f32 s15,s16,s20 a30f8f112418ba6b1dd395061dd39506 f68901ca54ee98af528ba4a14225422a a1bf07455e33b3d399a8c6936b8bfa95 6b8bfa952418ba6b1dd395061dd39506 f68901ca54ee98af528ba4a14225422a a1bf07455e33b3d399a8c6936b8bfa95 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vselvs.f32 s15,s16,s20 8793c51817c923b6a187046d3f09b720 9dcdc6913b40380353c44ea1af66a717 d5ab9305e9de68b2b802a210e9de68b2 e9de68b217c923b6a187046d3f09b720 9dcdc6913b40380353c44ea1af66a717 d5ab9305e9de68b2b802a210e9de68b2 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vselvs.f32 s15,s16,s20 3bb4bb0bd15f33f4d15f33f49f01e200 99b635e3c6f037d64c09a1108241d982 763a059e8865b3b5c9c5b9e346af3ec9 46af3ec9d15f33f4d15f33f49f01e200 99b635e3c6f037d64c09a1108241d982 763a059e8865b3b5c9c5b9e346af3ec9 fpscr=00000000
+vselvs.f32 s15,s16,s20 5ae533f3abd6061fcd1b68ac1d7ed21d ca716738a729301ab3274a7683b9aad2 3c0d069049bf701dc3713976571942db 571942dbabd6061fcd1b68ac1d7ed21d ca716738a729301ab3274a7683b9aad2 3c0d069049bf701dc3713976571942db fpscr=00000000
+vselvs.f32 s15,s16,s20 cfd0896c4232967f24d6c5f776893610 084d791cf74bf8a46710e7cc79be9c0f 4f62003f9a70f695d27c81182dc283c6 2dc283c64232967f24d6c5f776893610 084d791cf74bf8a46710e7cc79be9c0f 4f62003f9a70f695d27c81182dc283c6 fpscr=00000000
+vselvs.f32 s15,s16,s20 4bc673b0459cc802f3c4faa60d4b99f6 896ce90b159ce838ac75679848997803 4ccff40eebf552c6f74f134d62cd65d5 62cd65d5459cc802f3c4faa60d4b99f6 896ce90b159ce838ac75679848997803 4ccff40eebf552c6f74f134d62cd65d5 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[1]
+vselvs.f32 s15,s16,s20 678ef34b163a0a8bfe44ed82fe44ed82 c6d3cb3fb356aec68a64518ba891071f b59cbb6fb197b60aab9f4b87ab9f4b87 ab9f4b87163a0a8bfe44ed82fe44ed82 c6d3cb3fb356aec68a64518ba891071f b59cbb6fb197b60aab9f4b87ab9f4b87 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselvs.f64 d7, d8, d10 066423e65f1b4bfc066423e65f1b4bfc 7a6f179963b6abce9e56d1cd73eedd3a c61864a30205d7ed82c673a4f8bbca13 82c673a4f8bbca13066423e65f1b4bfc 7a6f179963b6abce9e56d1cd73eedd3a c61864a30205d7ed82c673a4f8bbca13 fpscr=00000000
+vselvs.f64 d7, d8, d10 0f3713b847c6e605a7b6266f62bb7b92 ef259ad76d76b28452a768e79fdcd204 ad344d45fc98443f6008eed40d7bf867 6008eed40d7bf867a7b6266f62bb7b92 ef259ad76d76b28452a768e79fdcd204 ad344d45fc98443f6008eed40d7bf867 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vselvs.f64 d7, d8, d10 1b49cb4664f720ee1b49cb4664f720ee cbd1fbd82150ef655363d81fd6191d11 1b07784a3b5f9f7374ee2b37b8a50252 74ee2b37b8a502521b49cb4664f720ee cbd1fbd82150ef655363d81fd6191d11 1b07784a3b5f9f7374ee2b37b8a50252 fpscr=00000000
+vselvs.f64 d7, d8, d10 4d0e1cd683ae3ed371fb6e988531163d 6de483c38fffda73d1384b5b1283dcb5 4579b9b774ac6b6a4f92c07dfa124f5b 4f92c07dfa124f5b71fb6e988531163d 6de483c38fffda73d1384b5b1283dcb5 4579b9b774ac6b6a4f92c07dfa124f5b fpscr=00000000
+vselvs.f64 d7, d8, d10 cc40b1017c9f68b29120097cdb5b8e14 3f36095990f0284bf41409b6f393929e b487060e50271b50e11dce1778694f3d e11dce1778694f3d9120097cdb5b8e14 3f36095990f0284bf41409b6f393929e b487060e50271b50e11dce1778694f3d fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselvs.f64 d7, d8, d10 5c2425f2f77a00508f614e0d2688d1d9 e77017f986d44cfee77017f986d44cfe 8c47dcaeae4779bb5cb4381ce60dd9ef 5cb4381ce60dd9ef8f614e0d2688d1d9 e77017f986d44cfee77017f986d44cfe 8c47dcaeae4779bb5cb4381ce60dd9ef fpscr=00000000
+vselvs.f64 d7, d8, d10 49f44feaf351d63e25ef3dd438e2cae5 3a1ce012ba06078c80edb10386d68173 ce99a35e15e8da786ab0000da6fce7ee 6ab0000da6fce7ee25ef3dd438e2cae5 3a1ce012ba06078c80edb10386d68173 ce99a35e15e8da786ab0000da6fce7ee fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vselvs.f64 d7, d8, d10 deecca881ce9982adeecca881ce9982a ba651ec8ef4979070ea5a25915eb1398 6281c9b66c34a4f38749ec252a61af04 8749ec252a61af04deecca881ce9982a ba651ec8ef4979070ea5a25915eb1398 6281c9b66c34a4f38749ec252a61af04 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselvs.f64 d7, d8, d10 4c3c365744634c8988f334ccd603cc2f 17a9599af590737eb1f5f010fef57a77 52378f82f910870160c85b034cc6ab63 60c85b034cc6ab6388f334ccd603cc2f 17a9599af590737eb1f5f010fef57a77 52378f82f910870160c85b034cc6ab63 fpscr=00000000
+vselvs.f64 d7, d8, d10 bc42987735313f7f6393406783056509 4cfe6ea89a67fd7573fd89076c62d3db 4d81883376d90b61be77d16b255e01d8 be77d16b255e01d86393406783056509 4cfe6ea89a67fd7573fd89076c62d3db 4d81883376d90b61be77d16b255e01d8 fpscr=00000000
+vselvs.f64 d7, d8, d10 7626f8c29ff6db7b95720a3abce303aa 29d968b64711207df29c6c50e2df479a 86ea28ac939577469bec4e03ec7a332e 9bec4e03ec7a332e95720a3abce303aa 29d968b64711207df29c6c50e2df479a 86ea28ac939577469bec4e03ec7a332e fpscr=00000000
+vselvs.f64 d7, d8, d10 39f6fec51c6cc92c10c8702e51203f06 d16c194b73d1b48043ca6264df50198b 64c8a64ee462fdab2f7ea9bf899e80fd 2f7ea9bf899e80fd10c8702e51203f06 d16c194b73d1b48043ca6264df50198b 64c8a64ee462fdab2f7ea9bf899e80fd fpscr=00000000
+vselvs.f64 d7, d8, d10 86eeeba6ca4f57c0e4cf7764d4215de6 ae19ebab2aae68bfc3182b3950ed94f1 94a5c9c49523d0045371f57848f48bcb 5371f57848f48bcbe4cf7764d4215de6 ae19ebab2aae68bfc3182b3950ed94f1 94a5c9c49523d0045371f57848f48bcb fpscr=00000000
+vselvs.f64 d7, d8, d10 2d40f5fde1ab0bb1c25daca8dec2a64b 4c5c080f37dd67b9929137dfea19fbaf 342e20a3a42d43d102a07e30fbf124f9 02a07e30fbf124f9c25daca8dec2a64b 4c5c080f37dd67b9929137dfea19fbaf 342e20a3a42d43d102a07e30fbf124f9 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselvs.f64 d7, d8, d10 d47ead462484a0ca6b254ce0878c4a01 173ab64f69d3c02e2b906764eefef7a5 380e4eb9d25486be66a8fc46ab610d60 66a8fc46ab610d606b254ce0878c4a01 173ab64f69d3c02e2b906764eefef7a5 380e4eb9d25486be66a8fc46ab610d60 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselvs.f64 d7, d8, d10 e0740646c8b9b1a1e1fe78467d7e5b02 e878ef228526b91af6334c7d59806848 2b07639c0feee4772b07639c0feee477 2b07639c0feee477e1fe78467d7e5b02 e878ef228526b91af6334c7d59806848 2b07639c0feee4772b07639c0feee477 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselvs.f64 d7, d8, d10 118342517d13311b118342517d13311b 1f8d764eac16369a295bda72d449fba7 a18cc59986bdd8da06422bcf0cc7c63d 06422bcf0cc7c63d118342517d13311b 1f8d764eac16369a295bda72d449fba7 a18cc59986bdd8da06422bcf0cc7c63d fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vselvs.f64 d7, d8, d10 c77564f51ed504b7c77564f51ed504b7 be29117bca4b9c62be29117bca4b9c62 970f5f16c5d267f2970f5f16c5d267f2 970f5f16c5d267f2c77564f51ed504b7 be29117bca4b9c62be29117bca4b9c62 970f5f16c5d267f2970f5f16c5d267f2 fpscr=00000000
+vselvs.f64 d7, d8, d10 44fc53a050c571e3d36ada29a17f5c56 b03f1fe02b93b0c12f6d403ba8e31ff9 2d15067147eb9fba09db33632640bb99 09db33632640bb99d36ada29a17f5c56 b03f1fe02b93b0c12f6d403ba8e31ff9 2d15067147eb9fba09db33632640bb99 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselvs.f64 d7, d8, d10 1212814c474d1a105196d13ad18353b5 c8d287c746672a29586e78f22276a078 c087ce02711245acc4f3ffec8cff1aaa c4f3ffec8cff1aaa5196d13ad18353b5 c8d287c746672a29586e78f22276a078 c087ce02711245acc4f3ffec8cff1aaa fpscr=00000000
+vselvs.f64 d7, d8, d10 05b61e37ab2fc7c09f4bbdd3bd7ff355 0c92a3543b3bc556ad1742e2f2677f4d fe75c73a5de282a93dd6aa1bcaa48703 3dd6aa1bcaa487039f4bbdd3bd7ff355 0c92a3543b3bc556ad1742e2f2677f4d fe75c73a5de282a93dd6aa1bcaa48703 fpscr=00000000
+vselvs.f64 d7, d8, d10 3c97eabcb12367a844f11b64f87d8205 973e19c4764bd3da4edb7b8089e1b943 226e5acfe73f89e25d0b460d759b1445 5d0b460d759b144544f11b64f87d8205 973e19c4764bd3da4edb7b8089e1b943 226e5acfe73f89e25d0b460d759b1445 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselvs.f64 d7, d8, d10 524e1115e21c1e695fd2563b5253bfba 034b7a76c48f92bf9a89f0a2dae0007d 1c8374db220d68b11c8374db220d68b1 1c8374db220d68b15fd2563b5253bfba 034b7a76c48f92bf9a89f0a2dae0007d 1c8374db220d68b11c8374db220d68b1 fpscr=00000000
+vselvs.f64 d7, d8, d10 63dff2dad906c495680e5cb53427cab7 63b5099455a3c02d6aaa815cf7875c46 d58241ea69c72072d90cb15bd7d8e6b6 d90cb15bd7d8e6b6680e5cb53427cab7 63b5099455a3c02d6aaa815cf7875c46 d58241ea69c72072d90cb15bd7d8e6b6 fpscr=00000000
+vselvs.f64 d7, d8, d10 d21eae5369bf2852798eb94a177836cb 6542ea56010d4ef77b69f877810d6ee9 18aab3e48bd147f649286a1fa2ae18a5 49286a1fa2ae18a5798eb94a177836cb 6542ea56010d4ef77b69f877810d6ee9 18aab3e48bd147f649286a1fa2ae18a5 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselvs.f64 d7, d8, d10 f5b4288ce7ec14ac4475c42322c0fa6a db6489b856578f3f7f0be47b63e4753c 503352218b3b9fcb503352218b3b9fcb 503352218b3b9fcb4475c42322c0fa6a db6489b856578f3f7f0be47b63e4753c 503352218b3b9fcb503352218b3b9fcb fpscr=00000000
+vselvs.f64 d7, d8, d10 88746b95c1ccb38421ece0386a3047d5 4004ef9686803aa2ae6a971b94df2cf3 7af70845084c054f5a7c2b42aabe952f 5a7c2b42aabe952f21ece0386a3047d5 4004ef9686803aa2ae6a971b94df2cf3 7af70845084c054f5a7c2b42aabe952f fpscr=00000000
+vselvs.f64 d7, d8, d10 d897c0c02777a4f2f93d8b38b71f4db7 b5b02bf6e66958a9b467b1e76e4e38ee 76cd837e98d9ec6804012d0b214440d2 04012d0b214440d2f93d8b38b71f4db7 b5b02bf6e66958a9b467b1e76e4e38ee 76cd837e98d9ec6804012d0b214440d2 fpscr=00000000
+vselvs.f64 d7, d8, d10 84b9ee8e3ef877b6b4e30911c707c511 2228803eef79843ca3228d5a41385cb9 3e3991217ce7384db8e02fecda21e496 b8e02fecda21e496b4e30911c707c511 2228803eef79843ca3228d5a41385cb9 3e3991217ce7384db8e02fecda21e496 fpscr=00000000
+vselvs.f64 d7, d8, d10 d758d8854ea5162c03fe20f5b46b0ec2 a7204e72014898e1d8beadb04f92d7b1 7aa9fe1bf784d29fc7e87514c8df66a5 c7e87514c8df66a503fe20f5b46b0ec2 a7204e72014898e1d8beadb04f92d7b1 7aa9fe1bf784d29fc7e87514c8df66a5 fpscr=00000000
+vselvs.f64 d7, d8, d10 0a19482b197433c2bcb23cb8920a602e 8cd986212f79ce1514e3c6b451429294 405532dcdc6327d2b8fe1a7a1bafe387 b8fe1a7a1bafe387bcb23cb8920a602e 8cd986212f79ce1514e3c6b451429294 405532dcdc6327d2b8fe1a7a1bafe387 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselvs.f64 d7, d8, d10 262b4bd841e7f321477de313250a966b d4c868449c61c062d4c868449c61c062 60e434b4fc2ccd4a7a8767ccc2f24502 7a8767ccc2f24502477de313250a966b d4c868449c61c062d4c868449c61c062 60e434b4fc2ccd4a7a8767ccc2f24502 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselvs.f64 d7, d8, d10 f43e6857d94d196d6d330a17599a5a0a daa199a08cfd8bbfb6c2ed5ec72bb84b 43aa9c3837bde03643aa9c3837bde036 43aa9c3837bde0366d330a17599a5a0a daa199a08cfd8bbfb6c2ed5ec72bb84b 43aa9c3837bde03643aa9c3837bde036 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: 2304 calls, 2382 iters
+vselvs.f64 d7, d8, d10 883b0be6874517490d23c03d85afc010 b2129c897ce6a222e54219c8bcb4f8f2 eedd299e8fd6c7680a88d4fff792a096 0a88d4fff792a0960d23c03d85afc010 b2129c897ce6a222e54219c8bcb4f8f2 eedd299e8fd6c7680a88d4fff792a096 fpscr=00000000
+vselvs.f64 d7, d8, d10 379ac9cc4c116e7a25b323838d489b72 b501f16cc1c0185dd4ed4a5291a82220 a904502fd23e8093a059a674949154e6 a059a674949154e625b323838d489b72 b501f16cc1c0185dd4ed4a5291a82220 a904502fd23e8093a059a674949154e6 fpscr=00000000
+vselvs.f64 d7, d8, d10 505e10fccb2f69b8bc56b8964600c89c 1b11dd190366aaf7e5e0e14e4d1492c3 ca77691484b75d02a0c3145575afb3a0 a0c3145575afb3a0bc56b8964600c89c 1b11dd190366aaf7e5e0e14e4d1492c3 ca77691484b75d02a0c3145575afb3a0 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselvs.f64 d7, d8, d10 0e0608069f0d2bb30ca0edbef2a63615 2e79e631c3a4d4b9778ec0eb37832068 ebe095c53869a5024cf4d866e37f4495 4cf4d866e37f44950ca0edbef2a63615 2e79e631c3a4d4b9778ec0eb37832068 ebe095c53869a5024cf4d866e37f4495 fpscr=00000000
+vselvs.f64 d7, d8, d10 e8a3694198e7d977b34acd93f5fd38b4 8caf914f5f2fe7d26c413eaf251d64e1 3f35aee70cca5d9cbcc204a92a32771a bcc204a92a32771ab34acd93f5fd38b4 8caf914f5f2fe7d26c413eaf251d64e1 3f35aee70cca5d9cbcc204a92a32771a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselvs.f64 d7, d8, d10 bf2c828ddd265b2df2ac2a7c0635f31b 08be4467cd1294bc08be4467cd1294bc 6b911e0e9e3bf25978c070b67d085f42 78c070b67d085f42f2ac2a7c0635f31b 08be4467cd1294bc08be4467cd1294bc 6b911e0e9e3bf25978c070b67d085f42 fpscr=00000000
+vselvs.f64 d7, d8, d10 ab2c0a5200c881e7603b5a18216605cc 5a05b5a28f1e89947b565c5ddb7eb0a2 cabf5d35cf2bc46b9fc58fdaedf74f0b 9fc58fdaedf74f0b603b5a18216605cc 5a05b5a28f1e89947b565c5ddb7eb0a2 cabf5d35cf2bc46b9fc58fdaedf74f0b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselvs.f64 d7, d8, d10 1ca81cd5cafd47811ade4ff0758bf1de da735c3e6a4a1ba6da735c3e6a4a1ba6 50e99e1a59bf41ec52079a9c244dea46 52079a9c244dea461ade4ff0758bf1de da735c3e6a4a1ba6da735c3e6a4a1ba6 50e99e1a59bf41ec52079a9c244dea46 fpscr=00000000
+vselvs.f64 d7, d8, d10 87a9d9dac159f8c421b04378d038512f 4d7c63889d602d3e20f06839a81f0036 cc4642d893723ea7a0a2b44d6003ff3c a0a2b44d6003ff3c21b04378d038512f 4d7c63889d602d3e20f06839a81f0036 cc4642d893723ea7a0a2b44d6003ff3c fpscr=00000000
+vselvs.f64 d7, d8, d10 d6f00acc07efe3609ef4c0079650034c e74d88115ec0e8923130a60e28d0119b 892b2ee0c0c4456aa2f207571dd27e17 a2f207571dd27e179ef4c0079650034c e74d88115ec0e8923130a60e28d0119b 892b2ee0c0c4456aa2f207571dd27e17 fpscr=00000000
+vselvs.f64 d7, d8, d10 2b732286ff3edaec506a7e9b16be5e8b d5afec72fd1c7497d00530648ea4a40a ce941aa059d45e15478082cf1048a42f 478082cf1048a42f506a7e9b16be5e8b d5afec72fd1c7497d00530648ea4a40a ce941aa059d45e15478082cf1048a42f fpscr=00000000
+vselvs.f64 d7, d8, d10 48d3152fda6eda42b99300ed8a70968d 9c3172ab036c411a29016922e982ae7e 1fad93c2817438a5026f7afc1b257744 026f7afc1b257744b99300ed8a70968d 9c3172ab036c411a29016922e982ae7e 1fad93c2817438a5026f7afc1b257744 fpscr=00000000
+vselvs.f64 d7, d8, d10 903853f620b36f4b4b4664d540cb184c 2ca54d03024cdfab7d1de0e5ee82bcaf e1646eeaca5bd72a99de800c4945adb2 99de800c4945adb24b4664d540cb184c 2ca54d03024cdfab7d1de0e5ee82bcaf e1646eeaca5bd72a99de800c4945adb2 fpscr=00000000
+vselvs.f64 d7, d8, d10 923109daff2348574c7d90ccde8aa85e 21c3c93d9f1c78df832d8b9c4c83fd5c 09328164607884e41c4b6eb4e9af929c 1c4b6eb4e9af929c4c7d90ccde8aa85e 21c3c93d9f1c78df832d8b9c4c83fd5c 09328164607884e41c4b6eb4e9af929c fpscr=00000000
+vselvs.f64 d7, d8, d10 bcf7f08492bd266b84d867a6f3afba3b 3871e38d4815bd23169b4b127b83456c 96f0fd3b6bc3c18cc4585914c2fd867f c4585914c2fd867f84d867a6f3afba3b 3871e38d4815bd23169b4b127b83456c 96f0fd3b6bc3c18cc4585914c2fd867f fpscr=00000000
+vselvs.f64 d7, d8, d10 5a4854cd408746a7a07052c39006cba1 4a1ea6457875c2f481177cadd3f7532c c107b874e724f832c5291376ad03f7e0 c5291376ad03f7e0a07052c39006cba1 4a1ea6457875c2f481177cadd3f7532c c107b874e724f832c5291376ad03f7e0 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselvs.f64 d7, d8, d10 52af21fc6aa2856f6a98bb82269d745d d5d4667d0b64df7bd5d4667d0b64df7b c78e1d09b82808ab8b84f639acd7528d 8b84f639acd7528d6a98bb82269d745d d5d4667d0b64df7bd5d4667d0b64df7b c78e1d09b82808ab8b84f639acd7528d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vmaxnm.f32 s15,s16,s20 0d0cf248b99e7a44642798b515d5aa56 33734573699a60011c37e4ca19cd9b37 197585aa1ffd475b8d3a335b6b9c6bb6 6b9c6bb6b99e7a44642798b515d5aa56 33734573699a60011c37e4ca19cd9b37 197585aa1ffd475b8d3a335b6b9c6bb6 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vmaxnm.f32 s15,s16,s20 1aa623805856adb208d208e7167927b1 8ad458dfe704c70e1a41415e9cc2d51d 28e57938b6fb4fd6d8c7cbf5bcf48ff3 9cc2d51d5856adb208d208e7167927b1 8ad458dfe704c70e1a41415e9cc2d51d 28e57938b6fb4fd6d8c7cbf5bcf48ff3 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[2]
+vmaxnm.f32 s15,s16,s20 94ff1b3a69e3a776792073ff94ff1b3a c1abef6929a58c959aba9e4f29a58c95 da6b9c4eed19ea4aa650eaec94e2d40c 29a58c9569e3a776792073ff94ff1b3a c1abef6929a58c959aba9e4f29a58c95 da6b9c4eed19ea4aa650eaec94e2d40c fpscr=00000000
+vmaxnm.f32 s15,s16,s20 1f1957bf4b1b369a3b3dc0f6e29783ce bfdfcd9b48dd0b824ae51294caeeaa4c 6cc0f9b4ee4bd229392cabb3ae3f996f ae3f996f4b1b369a3b3dc0f6e29783ce bfdfcd9b48dd0b824ae51294caeeaa4c 6cc0f9b4ee4bd229392cabb3ae3f996f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[3]
+vmaxnm.f32 s15,s16,s20 b2d07befdd1f1edc4881f01e63ff35db f7467621f0fafd76f746762173396921 f38eb07bce82ac0fb5b540e2eebbbe59 73396921dd1f1edc4881f01e63ff35db f7467621f0fafd76f746762173396921 f38eb07bce82ac0fb5b540e2eebbbe59 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vmaxnm.f32 s15,s16,s20 740914307d51fe9ff319398681bb7dc2 725350b83918423e52c5fe50c7fda019 cc459ebaddb471cfe090bd3fe090bd3f c7fda0197d51fe9ff319398681bb7dc2 725350b83918423e52c5fe50c7fda019 cc459ebaddb471cfe090bd3fe090bd3f fpscr=00000000
+vmaxnm.f32 s15,s16,s20 56f00e5bc147b5d2fc04c0cf6200de4f ef5821aa214a553677e7b4e97b912973 8bed0b3ca6dffbf9c4744815321df7ac 7b912973c147b5d2fc04c0cf6200de4f ef5821aa214a553677e7b4e97b912973 8bed0b3ca6dffbf9c4744815321df7ac fpscr=00000000
+vmaxnm.f32 s15,s16,s20 22352ea34be582b563082dfbb2fe54bb c9965db7c9a784423d5169d5656eb741 a654213be9f6ccce5c5adf66bd43691d 656eb7414be582b563082dfbb2fe54bb c9965db7c9a784423d5169d5656eb741 a654213be9f6ccce5c5adf66bd43691d fpscr=00000000
+vmaxnm.f32 s15,s16,s20 e284d226a4b0091af2442c850ba27202 f7d8099f3390a8ad25b4bcbaf8404ef7 6eff117e4af554134aacd837e28bf8bc e28bf8bca4b0091af2442c850ba27202 f7d8099f3390a8ad25b4bcbaf8404ef7 6eff117e4af554134aacd837e28bf8bc fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vmaxnm.f32 s15,s16,s20 debe16a841dfe2a044b953f041dfe2a0 399e0f3099a2b6c9c4d05f4aaab7891c 93224057caeb1b0bf82d45079ee6bbe1 9ee6bbe141dfe2a044b953f041dfe2a0 399e0f3099a2b6c9c4d05f4aaab7891c 93224057caeb1b0bf82d45079ee6bbe1 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vmaxnm.f32 s15,s16,s20 4e76e43e85247770794b88a0d690953a 2231ea1f92d7964012196a1d9bc20228 f84113b7f4fa59e8f84113b7094ad76a 094ad76a85247770794b88a0d690953a 2231ea1f92d7964012196a1d9bc20228 f84113b7f4fa59e8f84113b7094ad76a fpscr=00000000
+vmaxnm.f32 s15,s16,s20 02742fbfede4640b8e8c5d9b8fc24459 98033944972dea54e3e8f5c4f98476c2 2cd62c2339477e579c40ff26cef74a90 cef74a90ede4640b8e8c5d9b8fc24459 98033944972dea54e3e8f5c4f98476c2 2cd62c2339477e579c40ff26cef74a90 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vmaxnm.f32 s15,s16,s20 eeeafa8e27e84f2a9b776e9f0989f0df 35a30d0acd4ff0fce58e4521e0385da5 887f18c6e23350ef22ba0b98887f18c6 887f18c627e84f2a9b776e9f0989f0df 35a30d0acd4ff0fce58e4521e0385da5 887f18c6e23350ef22ba0b98887f18c6 fpscr=00000000
+vmaxnm.f32 s15,s16,s20 aca8d4815ea64cf1e13add9274e46400 eee7ec50cc2a25e372b8103e55f4dd63 5d60577b24346a8406179648470307ca 55f4dd635ea64cf1e13add9274e46400 eee7ec50cc2a25e372b8103e55f4dd63 5d60577b24346a8406179648470307ca fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vmaxnm.f32 s15,s16,s20 89da9bf39c8c63156c004ad1c3cae1bc 994aaf56fc2e32919827681a06b2cf4f 0f56cacf3646b9c0dd53bbd1b6379f8f 06b2cf4f9c8c63156c004ad1c3cae1bc 994aaf56fc2e32919827681a06b2cf4f 0f56cacf3646b9c0dd53bbd1b6379f8f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[3]
+vmaxnm.f32 s15,s16,s20 cef0cc342b4a9a42ad2a8f1048c60b6f ea411a0c3c793d37d9428c8eea411a0c 8629296b73f6fef7b64890d3a3f26c14 a3f26c142b4a9a42ad2a8f1048c60b6f ea411a0c3c793d37d9428c8eea411a0c 8629296b73f6fef7b64890d3a3f26c14 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vmaxnm.f32 s15,s16,s20 b1ebf8f5b769cbb6aaba60476365e007 92fafa2e92fafa2ebcdbfb87c449aa36 192765eccca0896753dd632ce4d0bf0a c449aa36b769cbb6aaba60476365e007 92fafa2e92fafa2ebcdbfb87c449aa36 192765eccca0896753dd632ce4d0bf0a fpscr=00000000
+vmaxnm.f32 s15,s16,s20 69bd3204894f728df3b8f2a969dff965 1f8f1e128e01ecc81e3fc6730a1636bf 4226bdeeeee480b1e9e2d853e2f13b24 0a1636bf894f728df3b8f2a969dff965 1f8f1e128e01ecc81e3fc6730a1636bf 4226bdeeeee480b1e9e2d853e2f13b24 fpscr=00000000
+vmaxnm.f32 s15,s16,s20 372f677c0d3624de71ba485eb101df34 b23135dd520f958ec92ed55a99547a3e 01e49496215fed6710d6512972619bc2 72619bc20d3624de71ba485eb101df34 b23135dd520f958ec92ed55a99547a3e 01e49496215fed6710d6512972619bc2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[3]
+vmaxnm.f32 s15,s16,s20 1d033de5326d3fd48e801d0772d1083a 54156cffa0b8b0b908dc1ce6224543d9 86537c53c8877971a5239975056dc00d 224543d9326d3fd48e801d0772d1083a 54156cffa0b8b0b908dc1ce6224543d9 86537c53c8877971a5239975056dc00d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vmaxnm.f32 s15,s16,s20 cfa9a117388fcc33cfa9a117069b9054 cc4372a3a16138364c9c069a91fe5ad1 5d1a79f51118c4f44daa98ee2354a95c 2354a95c388fcc33cfa9a117069b9054 cc4372a3a16138364c9c069a91fe5ad1 5d1a79f51118c4f44daa98ee2354a95c fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vmaxnm.f32 s15,s16,s20 f69e85f7306677bcf2e4e4415d8e19cb c5615c3126b07d4d6fe69a47c82871ba 2af9f9bea5b12e7fa97bc8585a0a10ee 5a0a10ee306677bcf2e4e4415d8e19cb c5615c3126b07d4d6fe69a47c82871ba 2af9f9bea5b12e7fa97bc8585a0a10ee fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[1]
+vmaxnm.f32 s15,s16,s20 9f04d32c0da68815fb713b76a392e04e 3a357f25fb245850f3c6dfb7192899ee 4eac425d5cbd59566fc5321b6fc5321b 6fc5321b0da68815fb713b76a392e04e 3a357f25fb245850f3c6dfb7192899ee 4eac425d5cbd59566fc5321b6fc5321b fpscr=00000000
+vmaxnm.f32 s15,s16,s20 3eebccdac5a38f5886a438c7c524da0b 20466dd37204ee4b12778e29164bd2f9 925e4b4ffc2cbef1012fdc3fb94dddab 164bd2f9c5a38f5886a438c7c524da0b 20466dd37204ee4b12778e29164bd2f9 925e4b4ffc2cbef1012fdc3fb94dddab fpscr=00000000
+vmaxnm.f32 s15,s16,s20 a2f2fe93a90012abcddfd26a0c080021 5b2816dfdfcf9e06853c661923ad1d61 3f80e208bc12760a5efe02b1809661b7 23ad1d61a90012abcddfd26a0c080021 5b2816dfdfcf9e06853c661923ad1d61 3f80e208bc12760a5efe02b1809661b7 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vmaxnm.f32 s15,s16,s20 53861d4f343ce3f1281abab6889aea48 0f2e725eeae49e082175fc1cf7016807 fbb3a9294d27a4b69908861bfef2daba f7016807343ce3f1281abab6889aea48 0f2e725eeae49e082175fc1cf7016807 fbb3a9294d27a4b69908861bfef2daba fpscr=00000000
+randV128: 2560 calls, 2645 iters
+vmaxnm.f32 s15,s16,s20 1f9acd70f3a9b3ae3f5b04eacb306de6 a64a62de08d4b2d323b3be0ad40a3e65 ad843851abf02c9e10b15821a44ddae7 a44ddae7f3a9b3ae3f5b04eacb306de6 a64a62de08d4b2d323b3be0ad40a3e65 ad843851abf02c9e10b15821a44ddae7 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vmaxnm.f32 s15,s16,s20 27cadf6fc35ac3ad24dd81fc45b34116 7c244d044602f5eddd5c22ef99738374 9e4282c40c89d7c20c89d7c2f51fb6a8 99738374c35ac3ad24dd81fc45b34116 7c244d044602f5eddd5c22ef99738374 9e4282c40c89d7c20c89d7c2f51fb6a8 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vmaxnm.f32 s15,s16,s20 bb11d02492c1d5777b1f8564a5b14329 255bf88aac917a47ac917a4709bd0b53 30f7801d9a7014081cd9bc9030f7801d 30f7801d92c1d5777b1f8564a5b14329 255bf88aac917a47ac917a4709bd0b53 30f7801d9a7014081cd9bc9030f7801d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vmaxnm.f32 s15,s16,s20 db5deeaa26c4f92286b52c121b7a678e 3da6cd1951ab4eed3c6a566848931d00 ca41b652827579ee3f7b9b446e107618 6e10761826c4f92286b52c121b7a678e 3da6cd1951ab4eed3c6a566848931d00 ca41b652827579ee3f7b9b446e107618 fpscr=00000000
+vmaxnm.f32 s15,s16,s20 4f66d2966174abecf5d2e6cc78011eea 58b7624ae2255326b83e3dec17cba321 9c2bbced489f9da43ae011f6ae305d02 17cba3216174abecf5d2e6cc78011eea 58b7624ae2255326b83e3dec17cba321 9c2bbced489f9da43ae011f6ae305d02 fpscr=00000000
+vmaxnm.f32 s15,s16,s20 e51b9a1b9a30ee089a9f30e644e20b7f 7d2c4fed70b08bade9f2d6121d8a772f 411fbb3f172e94506c336d6ebe103648 1d8a772f9a30ee089a9f30e644e20b7f 7d2c4fed70b08bade9f2d6121d8a772f 411fbb3f172e94506c336d6ebe103648 fpscr=00000000
+vmaxnm.f32 s15,s16,s20 30ba3e1d2f0996c18b7bac277cc0d446 28ce45901d20ec92369dfc1938af5d7a c6e11dc7dd71c26792f8bbce4136c7bb 4136c7bb2f0996c18b7bac277cc0d446 28ce45901d20ec92369dfc1938af5d7a c6e11dc7dd71c26792f8bbce4136c7bb fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vmaxnm.f32 s15,s16,s20 be84f142f6af736e164ef06e946d1288 07f800010935b0c1871c043e467349e1 a7b4d142a7b4d1421520292e41b09283 467349e1f6af736e164ef06e946d1288 07f800010935b0c1871c043e467349e1 a7b4d142a7b4d1421520292e41b09283 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[2]
+vmaxnm.f32 s15,s16,s20 795dd07d62eb2e7ef292a91b795dd07d bc21400ba772ff4f43af9c0dd24da3ff d93c4840a458eab26ac8e9fea458eab2 a458eab262eb2e7ef292a91b795dd07d bc21400ba772ff4f43af9c0dd24da3ff d93c4840a458eab26ac8e9fea458eab2 fpscr=00000000
+vmaxnm.f32 s15,s16,s20 e650d3d0e00ad4be20431c9628cef582 378393952e183e2633386c557f08575d 7d2cb205a9a75c2feec973381773e35e 7f08575de00ad4be20431c9628cef582 378393952e183e2633386c557f08575d 7d2cb205a9a75c2feec973381773e35e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vmaxnm.f32 s15,s16,s20 db5ab9bd50f68be99e1feec5c60b7545 74d518d4ae89cb8a410a8e1cfd988b4b b7202d388aeffa0b8aeffa0bbbcd7d1c bbcd7d1c50f68be99e1feec5c60b7545 74d518d4ae89cb8a410a8e1cfd988b4b b7202d388aeffa0b8aeffa0bbbcd7d1c fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vmaxnm.f32 s15,s16,s20 2628ec6aaaa84ff472dc3735bcb1132a f3340a846e9a1af13ab1ea70a54ae670 e3bba56f7e6cfa9ccadfcc19cadfcc19 a54ae670aaa84ff472dc3735bcb1132a f3340a846e9a1af13ab1ea70a54ae670 e3bba56f7e6cfa9ccadfcc19cadfcc19 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vmaxnm.f32 s15,s16,s20 808d6c4845eeabfc3d20bd07716e39d9 700b94c79186b8970cfda1ed9559a82a e4d5f6143868cee43868cee422378f22 22378f2245eeabfc3d20bd07716e39d9 700b94c79186b8970cfda1ed9559a82a e4d5f6143868cee43868cee422378f22 fpscr=00000000
+vmaxnm.f32 s15,s16,s20 6762e7b7e2488145c18fa93608bd4e2b 43033319de920bb98f1c360716eb8a33 68077751b9e821981e6c3290b577db84 16eb8a33e2488145c18fa93608bd4e2b 43033319de920bb98f1c360716eb8a33 68077751b9e821981e6c3290b577db84 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vmaxnm.f32 s15,s16,s20 9eae9f6b57217bb59d71f1399cc2dd3b 5d51967dba7ccc006fbaf54acb0ac224 51f78a001b23e93d86a208811a835629 1a83562957217bb59d71f1399cc2dd3b 5d51967dba7ccc006fbaf54acb0ac224 51f78a001b23e93d86a208811a835629 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[3]
+vmaxnm.f32 s15,s16,s20 1c5b22389fa7c23c9fa7c23ccb9871f0 1e2abcd615356fb2ca4bcf80fd8de15f 2ad80f11f15cfd8119b022ec2ad80f11 2ad80f119fa7c23c9fa7c23ccb9871f0 1e2abcd615356fb2ca4bcf80fd8de15f 2ad80f11f15cfd8119b022ec2ad80f11 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[2]
+vmaxnm.f32 s15,s16,s20 4068bf5e9eb166dcd46016ba257024ce fc985a9437b4856a538ff52e5a56e0cb 5e484ff45e484ff49011dd909d31ea6d 5a56e0cb9eb166dcd46016ba257024ce fc985a9437b4856a538ff52e5a56e0cb 5e484ff45e484ff49011dd909d31ea6d fpscr=00000000
+vmaxnm.f32 s15,s16,s20 3ac9e1baee8b38b67a4c95a41ec2fe16 6b7e8f46f09c6c8f0d5e525640ca9014 d66ebd3ba08c11b7a87d614b05bd9d81 40ca9014ee8b38b67a4c95a41ec2fe16 6b7e8f46f09c6c8f0d5e525640ca9014 d66ebd3ba08c11b7a87d614b05bd9d81 fpscr=00000000
+vmaxnm.f32 s15,s16,s20 8e4df20d9af11c1cbff1d858734a7e25 d8c1ae188632b0dbf4a68f3cb9d9d126 bb365dfb0a895330f263579bf42486e9 b9d9d1269af11c1cbff1d858734a7e25 d8c1ae188632b0dbf4a68f3cb9d9d126 bb365dfb0a895330f263579bf42486e9 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vmaxnm.f32 s15,s16,s20 6ff72261c932bb1d5238231e5238231e 9f8f0ef789c1387d16f018fe4fe09c7a c72d670b469ce8933a8d83a8be612d6f 4fe09c7ac932bb1d5238231e5238231e 9f8f0ef789c1387d16f018fe4fe09c7a c72d670b469ce8933a8d83a8be612d6f fpscr=00000000
+vmaxnm.f32 s15,s16,s20 a00000b26fae24d708ca20c0db185072 c87ee898af7fd53c28ee880e6c6c6a06 8a901920ee09c1e2fcca6aaa4a540320 6c6c6a066fae24d708ca20c0db185072 c87ee898af7fd53c28ee880e6c6c6a06 8a901920ee09c1e2fcca6aaa4a540320 fpscr=00000000
+vmaxnm.f32 s15,s16,s20 21890c38756454bec877cecc2a09dbd7 7c4f96ac53f01d9d40c77400e7522cae 607066b0d5917fa72963213e190f332d 190f332d756454bec877cecc2a09dbd7 7c4f96ac53f01d9d40c77400e7522cae 607066b0d5917fa72963213e190f332d fpscr=00000000
+vmaxnm.f32 s15,s16,s20 a11a798f3107b8ac5bc78a1e6d708fef e15bb2cebd97baa0dd69acd4e91d8945 22c597156743250a77fd39104017be2f 4017be2f3107b8ac5bc78a1e6d708fef e15bb2cebd97baa0dd69acd4e91d8945 22c597156743250a77fd39104017be2f fpscr=00000000
+vmaxnm.f32 s15,s16,s20 b57c2f57575bffa12275602a0114a7e9 723343fe1eef6d56b25a9a57bf29797e b600c2056a380663092ac72cbfbf2292 bf29797e575bffa12275602a0114a7e9 723343fe1eef6d56b25a9a57bf29797e b600c2056a380663092ac72cbfbf2292 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 3aa56a33357d0742794eec38c42b3b5f 1472620b229e4bbfa0ac85b3158e21bb 3cc5541f922515e2182e65fb7abc0d9c 182e65fb7abc0d9c794eec38c42b3b5f 1472620b229e4bbfa0ac85b3158e21bb 3cc5541f922515e2182e65fb7abc0d9c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vmaxnm.f64 d7, d8, d10 e60e8614d50c843f06be92e630adc0c4 57a30427809bef82c8d462a92f47a18c 539b87769f8cc67db35daa1ec67d1079 b35daa1ec67d107906be92e630adc0c4 57a30427809bef82c8d462a92f47a18c 539b87769f8cc67db35daa1ec67d1079 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vmaxnm.f64 d7, d8, d10 33c42305f3b22eba6209ab8cc39f8c89 5b29bf4dd9cd660d5ad6a1a46fdcead8 1e37aefcb7c7600b1e37aefcb7c7600b 5ad6a1a46fdcead86209ab8cc39f8c89 5b29bf4dd9cd660d5ad6a1a46fdcead8 1e37aefcb7c7600b1e37aefcb7c7600b fpscr=00000000
+vmaxnm.f64 d7, d8, d10 fc6e41ba1887448d6b1b839945b2cc64 3a0358af797ea6a3b45f81546c3e5435 b119945e245c3eac27f4c136bf3ca26b 27f4c136bf3ca26b6b1b839945b2cc64 3a0358af797ea6a3b45f81546c3e5435 b119945e245c3eac27f4c136bf3ca26b fpscr=00000000
+vmaxnm.f64 d7, d8, d10 414088e43050a90078ca48d40e0c4fca 7cf8b9b0de72aa45cc4564794b1cc468 457f0444d82ecbbffcea030f858ea8b4 cc4564794b1cc46878ca48d40e0c4fca 7cf8b9b0de72aa45cc4564794b1cc468 457f0444d82ecbbffcea030f858ea8b4 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vmaxnm.f64 d7, d8, d10 8b89bd6151de7e50d58e382d53ff93e0 e328a7a8edc57d77814648e42eabacf6 a71a47c2b44c58284dd0d95ea0252e61 4dd0d95ea0252e61d58e382d53ff93e0 e328a7a8edc57d77814648e42eabacf6 a71a47c2b44c58284dd0d95ea0252e61 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 7e670a5ffd58986d8488d7930c9d007d bf96090e9732e18e36f52d4c2babb4d6 dd67667deaabaacefd7ec8f603e304fb 36f52d4c2babb4d68488d7930c9d007d bf96090e9732e18e36f52d4c2babb4d6 dd67667deaabaacefd7ec8f603e304fb fpscr=00000000
+vmaxnm.f64 d7, d8, d10 154d341d758053409fd5c2bd7182b569 e82bc2b1ba923722c2198f86857fdd90 2b374929aac3de997164cd69c52e58ad 7164cd69c52e58ad9fd5c2bd7182b569 e82bc2b1ba923722c2198f86857fdd90 2b374929aac3de997164cd69c52e58ad fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vmaxnm.f64 d7, d8, d10 9fa766ca4772a542c83c876b39dfaa5f 773c3ace1f7746e0903e9d838535d0a0 d237a8bb7001df2f253609079e5efaae 253609079e5efaaec83c876b39dfaa5f 773c3ace1f7746e0903e9d838535d0a0 d237a8bb7001df2f253609079e5efaae fpscr=00000000
+vmaxnm.f64 d7, d8, d10 1385c44a8e6348842fb8319b13064687 50ebdbace45eb4f807237102aa442d3b cc59440b9d04ef3e98524e1070e0fb56 07237102aa442d3b2fb8319b13064687 50ebdbace45eb4f807237102aa442d3b cc59440b9d04ef3e98524e1070e0fb56 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vmaxnm.f64 d7, d8, d10 9fa17f9486d0091f9fa17f9486d0091f 393ece27f135453e7ea87c73716d1be8 45bc7b29dee075c71532bdaca0bcc688 7ea87c73716d1be89fa17f9486d0091f 393ece27f135453e7ea87c73716d1be8 45bc7b29dee075c71532bdaca0bcc688 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vmaxnm.f64 d7, d8, d10 e332271dd1b819c0960640a82b21ce86 b34991b79127566569c647aeae2ea08e 1e153cd39018929ee88f4ac7893918e2 69c647aeae2ea08e960640a82b21ce86 b34991b79127566569c647aeae2ea08e 1e153cd39018929ee88f4ac7893918e2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vmaxnm.f64 d7, d8, d10 6b91ea0d2a3c76ed6b91ea0d2a3c76ed affc7c8b24cff2b54cb78fed4c46f6d6 05b21d5160531f4462b396dd41a739d9 62b396dd41a739d96b91ea0d2a3c76ed affc7c8b24cff2b54cb78fed4c46f6d6 05b21d5160531f4462b396dd41a739d9 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vmaxnm.f64 d7, d8, d10 ad72b15f98cbda73b1bec0016dec9a94 137795641df2baa4b9c35294fd8ed858 69973984fe5b14a44c11a45f04bd5a27 4c11a45f04bd5a27b1bec0016dec9a94 137795641df2baa4b9c35294fd8ed858 69973984fe5b14a44c11a45f04bd5a27 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vmaxnm.f64 d7, d8, d10 7566bb50e85a5e2b8c975c402f1bafb5 7237bfb3ba4920806ae32f7556111204 53104b8e6570b17f995bea914662e531 6ae32f75561112048c975c402f1bafb5 7237bfb3ba4920806ae32f7556111204 53104b8e6570b17f995bea914662e531 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 880bcffa810b40ed26752ade08a76d53 d36c0dfed13dae48a89f870e3174713a 10a012a51275d47e36eac32d1e64af22 36eac32d1e64af2226752ade08a76d53 d36c0dfed13dae48a89f870e3174713a 10a012a51275d47e36eac32d1e64af22 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 fa151eefa74e6bbbd87c05fa7d4e5a91 354d8423ff5db2c18c891cde6e5ee660 c2ce0bfc72c9c1acd22f323ffc7c266c 8c891cde6e5ee660d87c05fa7d4e5a91 354d8423ff5db2c18c891cde6e5ee660 c2ce0bfc72c9c1acd22f323ffc7c266c fpscr=00000000
+vmaxnm.f64 d7, d8, d10 8ec55e61fe9f5b5a8a6e6c4390d5f250 d6e8df46c844bcd8c350eb39adeda24d 59f192397c0c7165700967b055337ffe 700967b055337ffe8a6e6c4390d5f250 d6e8df46c844bcd8c350eb39adeda24d 59f192397c0c7165700967b055337ffe fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vmaxnm.f64 d7, d8, d10 9677f5e2ac1710086d4dfc1714f4fec0 0771e71ea76fb05dfcba3354d5a11579 141011b36f28ca3aa2dd979bacfc7a68 a2dd979bacfc7a686d4dfc1714f4fec0 0771e71ea76fb05dfcba3354d5a11579 141011b36f28ca3aa2dd979bacfc7a68 fpscr=00000000
+randV128: 2816 calls, 2907 iters
+vmaxnm.f64 d7, d8, d10 a7e09f948d6ee43e19c6dde20bae288b dcf18af8a60d0cf0a2b87db2bc55401d 6dc25048d31ff865328ffe55694f0737 328ffe55694f073719c6dde20bae288b dcf18af8a60d0cf0a2b87db2bc55401d 6dc25048d31ff865328ffe55694f0737 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 40d244faedb33004a90d80c3d44e654c 6bf3a5735d0c8bad0ed9790de90b56ce ee3098ff39fd3681c011e46875604134 0ed9790de90b56cea90d80c3d44e654c 6bf3a5735d0c8bad0ed9790de90b56ce ee3098ff39fd3681c011e46875604134 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 5df465f7581ecc7da15392f47ad3f553 db294685d47ba910bf731eee3eef5bd2 714e10121f5cfb3b40c4edddbe12fc41 40c4edddbe12fc41a15392f47ad3f553 db294685d47ba910bf731eee3eef5bd2 714e10121f5cfb3b40c4edddbe12fc41 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vmaxnm.f64 d7, d8, d10 9e48dca568e6e31f4357f9915951d0bd 4bcbc8290bd58df80c434353c2c52f6b 0912777773bf59af0912777773bf59af 0c434353c2c52f6b4357f9915951d0bd 4bcbc8290bd58df80c434353c2c52f6b 0912777773bf59af0912777773bf59af fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vmaxnm.f64 d7, d8, d10 20f769a5be90c6a4bd546d6c158abf46 9187cd7b1d8dd0088b9f9fa4b39df093 6f2bd95751b333ca74899d9551c77d03 74899d9551c77d03bd546d6c158abf46 9187cd7b1d8dd0088b9f9fa4b39df093 6f2bd95751b333ca74899d9551c77d03 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vmaxnm.f64 d7, d8, d10 efdd88875a804da280f4e341a2f97704 d30c57fa47bf45e085da3f819b91c680 b08f40d1b9f5cfc428e186abe57832e7 28e186abe57832e780f4e341a2f97704 d30c57fa47bf45e085da3f819b91c680 b08f40d1b9f5cfc428e186abe57832e7 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 3221aa6deaa3241afbf3fbb1d1d1d173 fdef3ce12fdcdbe5d42bffb9fc517600 710b899dc5e5614640237c9864b8f692 40237c9864b8f692fbf3fbb1d1d1d173 fdef3ce12fdcdbe5d42bffb9fc517600 710b899dc5e5614640237c9864b8f692 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 3098372a759955c618c91c7cd94b05b6 a7cec28691c0f4d8606a0eb4b91e8140 446e4f1f6b1bdfb5e2eba9ecf9062da0 606a0eb4b91e814018c91c7cd94b05b6 a7cec28691c0f4d8606a0eb4b91e8140 446e4f1f6b1bdfb5e2eba9ecf9062da0 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vmaxnm.f64 d7, d8, d10 3f9531cd8e5205d075f5a2a20583f2e1 c6845566380568a3c6845566380568a3 94285538a259ef1a94285538a259ef1a 94285538a259ef1a75f5a2a20583f2e1 c6845566380568a3c6845566380568a3 94285538a259ef1a94285538a259ef1a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vmaxnm.f64 d7, d8, d10 7077f472cf3f3aaab00f008304ac59a6 d329d26217ab61c576f79645ddae27c5 f69abe86b228dcb6f69abe86b228dcb6 76f79645ddae27c5b00f008304ac59a6 d329d26217ab61c576f79645ddae27c5 f69abe86b228dcb6f69abe86b228dcb6 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 d85ba9a3021d0a1846cff08ada7c5d7c 03f74c12a06ae867b93dd78f31ee73d0 e627fa4515dcfd795c887ccf2a36dc13 5c887ccf2a36dc1346cff08ada7c5d7c 03f74c12a06ae867b93dd78f31ee73d0 e627fa4515dcfd795c887ccf2a36dc13 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 ca84887fa6ddb16f3ec4d40453c24248 3871392b5ccd7500b09b46ac876dc16d 07144c4b5bcf28ef5d26532c482bd1c3 5d26532c482bd1c33ec4d40453c24248 3871392b5ccd7500b09b46ac876dc16d 07144c4b5bcf28ef5d26532c482bd1c3 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vmaxnm.f64 d7, d8, d10 ddcf2a3453a67e7f37cd8f8c1406da2e 79e2dafac3661c1f86a5d8714b4f36a7 0d5684ec9d584612cd9d48aaaf4ed61b 86a5d8714b4f36a737cd8f8c1406da2e 79e2dafac3661c1f86a5d8714b4f36a7 0d5684ec9d584612cd9d48aaaf4ed61b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vmaxnm.f64 d7, d8, d10 ab9514699818c6b1bb4a1b2a0eb1ecf5 73a387779a707ed831495c1c41bbc17d f27a04ef088b46f5f27a04ef088b46f5 31495c1c41bbc17dbb4a1b2a0eb1ecf5 73a387779a707ed831495c1c41bbc17d f27a04ef088b46f5f27a04ef088b46f5 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vmaxnm.f64 d7, d8, d10 412ff561b9522baa9eca2e0a3fb7c89a 533e0013bf8e1a6e533e0013bf8e1a6e b751b0e63ec5cd09b6044d4cd2e2ef79 533e0013bf8e1a6e9eca2e0a3fb7c89a 533e0013bf8e1a6e533e0013bf8e1a6e b751b0e63ec5cd09b6044d4cd2e2ef79 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 8b034c20fa11853470c19b439cc0a5d7 1831928b73f0e342add592e6c08c6613 1756bd2e1ecb4bb18fde5fbf89aebde2 8fde5fbf89aebde270c19b439cc0a5d7 1831928b73f0e342add592e6c08c6613 1756bd2e1ecb4bb18fde5fbf89aebde2 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 84f74b8967796a074979dbae9017b139 4c3e3525e830d8bf98d84cb8277a9e2b d5507df378e72c2d9e4f99545123fffe 98d84cb8277a9e2b4979dbae9017b139 4c3e3525e830d8bf98d84cb8277a9e2b d5507df378e72c2d9e4f99545123fffe fpscr=00000000
+vmaxnm.f64 d7, d8, d10 a84c8755241d00ce61e31a360d901daf 07bcedd3e83e6e800264da3bb0af78ec d379126df08b82c88187549abce30021 0264da3bb0af78ec61e31a360d901daf 07bcedd3e83e6e800264da3bb0af78ec d379126df08b82c88187549abce30021 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 c8c536b7d92bb4953f757526efa94437 341c9a172740c67f52e043642ae379ed caa0d66ef99af12624b59e80c270d4eb 52e043642ae379ed3f757526efa94437 341c9a172740c67f52e043642ae379ed caa0d66ef99af12624b59e80c270d4eb fpscr=00000000
+vmaxnm.f64 d7, d8, d10 f483fafe34922a3a88d9b5f9ce4876a2 0f4b4b0a8359789f7817e693779196f9 c734b027a697f97ae7b60bcf59a941d3 7817e693779196f988d9b5f9ce4876a2 0f4b4b0a8359789f7817e693779196f9 c734b027a697f97ae7b60bcf59a941d3 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 56fce3fdf3d5a27e5bf5aee1b534d862 971fe85d0a1edbcf5db8b36a2a9aa133 d48a2c88ac43c94990ca5c91d6783e8e 5db8b36a2a9aa1335bf5aee1b534d862 971fe85d0a1edbcf5db8b36a2a9aa133 d48a2c88ac43c94990ca5c91d6783e8e fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vmaxnm.f64 d7, d8, d10 1e0e6038a09e9e3a6bcba155221f99c1 2dd55f2e1b957557c66c9f988903ac70 9dab748020a584a3323698261b457dbf 323698261b457dbf6bcba155221f99c1 2dd55f2e1b957557c66c9f988903ac70 9dab748020a584a3323698261b457dbf fpscr=00000000
+vmaxnm.f64 d7, d8, d10 73ee152662d4a8bc9b3ac76aebe84661 07752e2ccea92091cc2d0a88cf6af10c a3bb01476078a47a3c9b5813bb3446f4 3c9b5813bb3446f49b3ac76aebe84661 07752e2ccea92091cc2d0a88cf6af10c a3bb01476078a47a3c9b5813bb3446f4 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 25da09f42be1a9866ded34ee22184a0b c3e94c210fb62bdaad2e31d475018351 9722ebed6e0d95237b0628e9bcd4ed0d 7b0628e9bcd4ed0d6ded34ee22184a0b c3e94c210fb62bdaad2e31d475018351 9722ebed6e0d95237b0628e9bcd4ed0d fpscr=00000000
+vmaxnm.f64 d7, d8, d10 0b6a3c0da0b038b3272be06369c07300 f29fc278d91e66ba5978932b36e8a44b 8250a46c961b1b61b73eb34839b83c94 5978932b36e8a44b272be06369c07300 f29fc278d91e66ba5978932b36e8a44b 8250a46c961b1b61b73eb34839b83c94 fpscr=00000000
+vmaxnm.f64 d7, d8, d10 d94bd39899f04441180ecc1353be375a 67e29d7874ec754289b1a2c101c1bdbf 72e05305e3be725e852cba4cb9ad688c 852cba4cb9ad688c180ecc1353be375a 67e29d7874ec754289b1a2c101c1bdbf 72e05305e3be725e852cba4cb9ad688c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vmaxnm.f64 d7, d8, d10 d39894dd6aea118ed39894dd6aea118e 315780ee24250a92315780ee24250a92 8e78a050f7a567cc268753cbbc2cf47b 315780ee24250a92d39894dd6aea118e 315780ee24250a92315780ee24250a92 8e78a050f7a567cc268753cbbc2cf47b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vmaxnm.f64 d7, d8, d10 47ac0fab0848137d47ac0fab0848137d 17487c8df2258fade0404426352df9b0 f39c5f1a7de554e704812ac0beb7a43b 04812ac0beb7a43b47ac0fab0848137d 17487c8df2258fade0404426352df9b0 f39c5f1a7de554e704812ac0beb7a43b fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vmaxnm.f64 d7, d8, d10 0ffb4cf9188ad20d71f64a98c5cc4af3 1e86b85f1b863d198f52c376c607839b ce5d8d36c1a9adfd16a6bc67777fe97a 16a6bc67777fe97a71f64a98c5cc4af3 1e86b85f1b863d198f52c376c607839b ce5d8d36c1a9adfd16a6bc67777fe97a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vmaxnm.f64 d7, d8, d10 f4be7a39201c34401e2a2b35d9cefd1c bff4ab553c70fb05bff4ab553c70fb05 841241f73a7436aa841241f73a7436aa 841241f73a7436aa1e2a2b35d9cefd1c bff4ab553c70fb05bff4ab553c70fb05 841241f73a7436aa841241f73a7436aa fpscr=00000000
+vmaxnm.f64 d7, d8, d10 adba48e671347ef6d850ab7bf82b9e27 7e1cd581cfeabbff13cfcbc1664913f8 1605b6ad71505d657c21e6bbfe57d4d1 7c21e6bbfe57d4d1d850ab7bf82b9e27 7e1cd581cfeabbff13cfcbc1664913f8 1605b6ad71505d657c21e6bbfe57d4d1 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vminnm.f32 s15,s16,s20 f552c89d503515ebdd4c507af761f4cd eaa4cca4eaa4cca437cf733689aa054c 267067e5d1ed8dd9456c82ad7897f057 89aa054c503515ebdd4c507af761f4cd eaa4cca4eaa4cca437cf733689aa054c 267067e5d1ed8dd9456c82ad7897f057 fpscr=00000000
+vminnm.f32 s15,s16,s20 46949f260b97cdeac1bcc8d0fa2694a5 52eff8f507b59a2d68689c8c181a2034 0e03b74b81044b8b30bd2da9d68292e1 d68292e10b97cdeac1bcc8d0fa2694a5 52eff8f507b59a2d68689c8c181a2034 0e03b74b81044b8b30bd2da9d68292e1 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 s15,s16,s20 9013293df9d40c65a9a804bf94aec958 d2504361d8e9f1fba9f18a9eda8a08ed 4a9488c101752289497f88655537ad45 da8a08edf9d40c65a9a804bf94aec958 d2504361d8e9f1fba9f18a9eda8a08ed 4a9488c101752289497f88655537ad45 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vminnm.f32 s15,s16,s20 0dddc0dc0dddc0dc67f2ea61699ed720 1f5e4c7ea1ed2ff7aa5b54df19276920 d28c4908c6ea9ab25438dbf029359f3d 192769200dddc0dc67f2ea61699ed720 1f5e4c7ea1ed2ff7aa5b54df19276920 d28c4908c6ea9ab25438dbf029359f3d fpscr=00000000
+vminnm.f32 s15,s16,s20 3f65287c65e0d607b843f1495252bb0e 021373ed0bea31219f43e098e4d580b9 7b74e71f24c2571542d95cf984236aaa e4d580b965e0d607b843f1495252bb0e 021373ed0bea31219f43e098e4d580b9 7b74e71f24c2571542d95cf984236aaa fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[2]
+vminnm.f32 s15,s16,s20 f6a852ac4b76345185d0b9d7c7ea8bdc a06acc5a061971f0deecd4ce7c7f3444 9161e2704c48d07e9161e270617c5981 617c59814b76345185d0b9d7c7ea8bdc a06acc5a061971f0deecd4ce7c7f3444 9161e2704c48d07e9161e270617c5981 fpscr=00000000
+vminnm.f32 s15,s16,s20 175c4ad6c651d75d10f67aacbed49949 8c2f6ca7c5d20279c486081b939acbc4 7701e9afd36df24d4703a1efb3d4e84a b3d4e84ac651d75d10f67aacbed49949 8c2f6ca7c5d20279c486081b939acbc4 7701e9afd36df24d4703a1efb3d4e84a fpscr=00000000
+vminnm.f32 s15,s16,s20 f556b472464063d004536cde86ffa4ba 8b9efbc668c8176ba4f520fd2ceec445 338b28525e2c1f39c2b3c27f4e9ff231 2ceec445464063d004536cde86ffa4ba 8b9efbc668c8176ba4f520fd2ceec445 338b28525e2c1f39c2b3c27f4e9ff231 fpscr=00000000
+vminnm.f32 s15,s16,s20 d882ccb15c381eda4a1ae38aaba3d529 2058271ca1abc117bc8466fd2e6c8ea8 c392fee16a956edffadde40665da0eea 2e6c8ea85c381eda4a1ae38aaba3d529 2058271ca1abc117bc8466fd2e6c8ea8 c392fee16a956edffadde40665da0eea fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 s15,s16,s20 ae123d938e7521296a222c5aae123d93 ba52edfc33fc43ab5a179d5c839beaed d6e81f5bca4b7d10572374cb65c5af65 839beaed8e7521296a222c5aae123d93 ba52edfc33fc43ab5a179d5c839beaed d6e81f5bca4b7d10572374cb65c5af65 fpscr=00000000
+vminnm.f32 s15,s16,s20 37eb0dfb645a48251d11c7c46b24fc55 f6d2e8d8115bba4c96e8d9ef32bf82ae 4f0106c3659a209cce60acd4d7bdcdf0 d7bdcdf0645a48251d11c7c46b24fc55 f6d2e8d8115bba4c96e8d9ef32bf82ae 4f0106c3659a209cce60acd4d7bdcdf0 fpscr=00000000
+randV128: 3072 calls, 3167 iters
+vminnm.f32 s15,s16,s20 4d2b44eb412531ede7e7c0de974f1105 6bc272e94c5e953314ced573b474b52f d97426ae33c3e9352736e9ccbc5732ba bc5732ba412531ede7e7c0de974f1105 6bc272e94c5e953314ced573b474b52f d97426ae33c3e9352736e9ccbc5732ba fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vminnm.f32 s15,s16,s20 297970fdd25d78a3fdeaf59fce9d0ba2 c9ececef1b44a6a0dd0c5c74dd0c5c74 5ecf5ae4b6a0041dc100a477b92ac94d dd0c5c74d25d78a3fdeaf59fce9d0ba2 c9ececef1b44a6a0dd0c5c74dd0c5c74 5ecf5ae4b6a0041dc100a477b92ac94d fpscr=00000000
+vminnm.f32 s15,s16,s20 0117d7c42403e202e3d4b07ac2dfe424 0fa7c5695a91a4c7a6594d9886f62faa d1a6841a4a15146c82d0febba49844af a49844af2403e202e3d4b07ac2dfe424 0fa7c5695a91a4c7a6594d9886f62faa d1a6841a4a15146c82d0febba49844af fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[1]
+vminnm.f32 s15,s16,s20 8cf61cf68cf61cf6c949cb06d7383990 89f2750905596d9275a7d96b4adaf152 121d62016b2b04826b2b0482ad64a9b0 ad64a9b08cf61cf6c949cb06d7383990 89f2750905596d9275a7d96b4adaf152 121d62016b2b04826b2b0482ad64a9b0 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vminnm.f32 s15,s16,s20 0f2f26fc07dfefa44217e41657461128 a9e66383d3af1b0b706d1168dc84e680 aef61d5401b50ba337ff9f1f3ae32736 dc84e68007dfefa44217e41657461128 a9e66383d3af1b0b706d1168dc84e680 aef61d5401b50ba337ff9f1f3ae32736 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[0]
+vminnm.f32 s15,s16,s20 1a9790cb8624bc923db70609989b727c aaf3cb1c529b8a43aaf3cb1c6362b0aa 610c3b7221483f6efa4ec995610c3b72 610c3b728624bc923db70609989b727c aaf3cb1c529b8a43aaf3cb1c6362b0aa 610c3b7221483f6efa4ec995610c3b72 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vminnm.f32 s15,s16,s20 6f49bde934ed27b26783ba2b53e76076 7785b23dae62e763a5b310186ed40ec5 592a134bc5eab6bf065c418f7d373f3f 6ed40ec534ed27b26783ba2b53e76076 7785b23dae62e763a5b310186ed40ec5 592a134bc5eab6bf065c418f7d373f3f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vminnm.f32 s15,s16,s20 5cb94f0e2f5eaabefe9db86a19f2c9e6 ddce4299da9efbc70dca38332c040778 01de75b301de75b39f07bc445a80f22b 2c0407782f5eaabefe9db86a19f2c9e6 ddce4299da9efbc70dca38332c040778 01de75b301de75b39f07bc445a80f22b fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vminnm.f32 s15,s16,s20 80f644ff526df492fd18e34ff216f2f5 be026ee74338aee969701cc7e980fa12 9c60d63a7400db835feca847ae4b9892 e980fa12526df492fd18e34ff216f2f5 be026ee74338aee969701cc7e980fa12 9c60d63a7400db835feca847ae4b9892 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vminnm.f32 s15,s16,s20 9d5e0127e49c2fa1ccf84829d1f5456c 68afa93600e39cbfc3f423ea6d93f9b1 9d216f5702b9cee02fffa58b64a9f7ea 64a9f7eae49c2fa1ccf84829d1f5456c 68afa93600e39cbfc3f423ea6d93f9b1 9d216f5702b9cee02fffa58b64a9f7ea fpscr=00000000
+vminnm.f32 s15,s16,s20 23a4ecea19e59ee55ce65fe74fa079c4 fdda20f6a54ce76148e5630849e0773d d36f9fc3c268bc0876ba27bdb596144e b596144e19e59ee55ce65fe74fa079c4 fdda20f6a54ce76148e5630849e0773d d36f9fc3c268bc0876ba27bdb596144e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vminnm.f32 s15,s16,s20 a96980535b0686c55b87c7cf8ef500ee 273e4b824e374e33273e4b82dd4e20f8 a058c97ce373af800587ea815640a7cb dd4e20f85b0686c55b87c7cf8ef500ee 273e4b824e374e33273e4b82dd4e20f8 a058c97ce373af800587ea815640a7cb fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vminnm.f32 s15,s16,s20 ef415ab0f2f70465854feb39f16f7c89 af539d813169024c32c53c9a5e52dacd 510cc51516d8a9f6666b253816d8a9f6 16d8a9f6f2f70465854feb39f16f7c89 af539d813169024c32c53c9a5e52dacd 510cc51516d8a9f6666b253816d8a9f6 fpscr=00000000
+vminnm.f32 s15,s16,s20 3b78f8411aad4fac99229cc4f25e5844 ca5777992cab2ef9a4544ad3a9972c53 c22982db4a24e5a7d1ebe204b436e6cc b436e6cc1aad4fac99229cc4f25e5844 ca5777992cab2ef9a4544ad3a9972c53 c22982db4a24e5a7d1ebe204b436e6cc fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 s15,s16,s20 6a00924363014f93d37d9f97c43f2616 313ef11845eece99ded8fa77313ef118 88a79996daaa09c04df3cdbf420d06e5 313ef11863014f93d37d9f97c43f2616 313ef11845eece99ded8fa77313ef118 88a79996daaa09c04df3cdbf420d06e5 fpscr=00000000
+vminnm.f32 s15,s16,s20 c8cf2731c2428fc5e2af41169474a0e2 76759387d4333770880548ecf6fd1eb4 b495898c55e80ffc04c6a3d26ff12002 f6fd1eb4c2428fc5e2af41169474a0e2 76759387d4333770880548ecf6fd1eb4 b495898c55e80ffc04c6a3d26ff12002 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vminnm.f32 s15,s16,s20 19481c7c7800fa3079155f059f264862 a633a7af8f51368c3c0ebf414011c739 d70b7d8c81a2f521a3efa5a3daac7c1d daac7c1d7800fa3079155f059f264862 a633a7af8f51368c3c0ebf414011c739 d70b7d8c81a2f521a3efa5a3daac7c1d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vminnm.f32 s15,s16,s20 32b6279ec91203a485ac4b53ed97ba82 9325c32f769c8f093ea4afb0769c8f09 2daea5c392a7d7a7b398d9e0ddb81a4a ddb81a4ac91203a485ac4b53ed97ba82 9325c32f769c8f093ea4afb0769c8f09 2daea5c392a7d7a7b398d9e0ddb81a4a fpscr=00000000
+vminnm.f32 s15,s16,s20 3081dba51d6d8317987b5a9dae0f4d07 4b8047ab907a0d775c7801417513748c 7c80e9c66cfbb4263c89f7f62562f817 2562f8171d6d8317987b5a9dae0f4d07 4b8047ab907a0d775c7801417513748c 7c80e9c66cfbb4263c89f7f62562f817 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vminnm.f32 s15,s16,s20 ed6019131a95d39639982a06705ab709 397bea57f0e7e6992f1c3fcd142a2121 6fc8c4685c2441d6bcba6db842446311 142a21211a95d39639982a06705ab709 397bea57f0e7e6992f1c3fcd142a2121 6fc8c4685c2441d6bcba6db842446311 fpscr=00000000
+vminnm.f32 s15,s16,s20 02bd9f4f7307555b4796eedae7a342f3 a112684dcd6c8052f4ed23c2683654db 53921dd36717a828a51aea947497e086 683654db7307555b4796eedae7a342f3 a112684dcd6c8052f4ed23c2683654db 53921dd36717a828a51aea947497e086 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vminnm.f32 s15,s16,s20 2fc42639fb1cf16c6381a531487f63fb 3b4ae22d322e80ee704883aef8b1ad8f 846a2cdb24c3e522a2c6ce3ae57154be f8b1ad8ffb1cf16c6381a531487f63fb 3b4ae22d322e80ee704883aef8b1ad8f 846a2cdb24c3e522a2c6ce3ae57154be fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[3]
+vminnm.f32 s15,s16,s20 915f616012933094686132b36c7f45c3 7c3660e5fc1354c39f1bc21e903f8c19 5ee03fdceafb37575ee03fdced53bd5b ed53bd5b12933094686132b36c7f45c3 7c3660e5fc1354c39f1bc21e903f8c19 5ee03fdceafb37575ee03fdced53bd5b fpscr=00000000
+vminnm.f32 s15,s16,s20 b252463e996553cde79e2fad58829af4 e493fdb1a1fe0a2b6ae31cae0483477f 577822a406954cc379fad28375916014 0483477f996553cde79e2fad58829af4 e493fdb1a1fe0a2b6ae31cae0483477f 577822a406954cc379fad28375916014 fpscr=00000000
+vminnm.f32 s15,s16,s20 bb4836da98ebf94e1d5497e5f6339773 dbc59beef911d0a7796d14dcbb85c7ff 7554f1093e3a374acaffa187efdafd75 efdafd7598ebf94e1d5497e5f6339773 dbc59beef911d0a7796d14dcbb85c7ff 7554f1093e3a374acaffa187efdafd75 fpscr=00000000
+vminnm.f32 s15,s16,s20 961e43d9be283a1e36a5606f44d5caf0 7e10d704de0c60e7d6bbeaac6b1f92b0 64fa09fbc9bcc820c4cadd49e10d2412 e10d2412be283a1e36a5606f44d5caf0 7e10d704de0c60e7d6bbeaac6b1f92b0 64fa09fbc9bcc820c4cadd49e10d2412 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 s15,s16,s20 f5b7407122876596a9d7366a51434dea bde0b00b2c20a34e07ecfae7d1d3cb68 b7a4a65e0277ecab61398755ab38324c d1d3cb6822876596a9d7366a51434dea bde0b00b2c20a34e07ecfae7d1d3cb68 b7a4a65e0277ecab61398755ab38324c fpscr=00000000
+vminnm.f32 s15,s16,s20 b40aa2422f83b1db84c4dedffac071bc c24369f5bcb86f0c756b85c290a41aff 62b319471814b7bc04885bc586e3f06e 90a41aff2f83b1db84c4dedffac071bc c24369f5bcb86f0c756b85c290a41aff 62b319471814b7bc04885bc586e3f06e fpscr=00000000
+vminnm.f32 s15,s16,s20 da3fc9c9ee8c9aa16f023dac024c8824 380e67bf427b823e7abe4c7e88e7bed0 70f81bbb52cb9e3c97e2dda85bb775e8 88e7bed0ee8c9aa16f023dac024c8824 380e67bf427b823e7abe4c7e88e7bed0 70f81bbb52cb9e3c97e2dda85bb775e8 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[2]
+vminnm.f32 s15,s16,s20 858aa09865569ad6a5ef6d0788a08031 ab56ed19fcaa61a6e098dc738b2d425d 81935fe2639131c2900e67e9c43bf474 c43bf47465569ad6a5ef6d0788a08031 ab56ed19fcaa61a6e098dc738b2d425d 81935fe2639131c2900e67e9c43bf474 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vminnm.f32 s15,s16,s20 fc0779d0294ddb42d39459223ca0dad4 37ae109fefe184d89fd6d6fb81f01dfd 671157272565e1299934a00dc42e38dd c42e38dd294ddb42d39459223ca0dad4 37ae109fefe184d89fd6d6fb81f01dfd 671157272565e1299934a00dc42e38dd fpscr=00000000
+vminnm.f32 s15,s16,s20 922cb7ad3c2c137252ce3d3c04fa276c cb13fa53f5311d99efbc86fc6254014f 2b0de085e64ef8b08d426aac601768c8 601768c83c2c137252ce3d3c04fa276c cb13fa53f5311d99efbc86fc6254014f 2b0de085e64ef8b08d426aac601768c8 fpscr=00000000
+vminnm.f32 s15,s16,s20 5b6a53c49ca37b9ad5b34dfe515d7d5a 827cf5aad2998502c5646d5f85d2ff2e 4a826162d20d677140ae4d10dea0d5c0 dea0d5c09ca37b9ad5b34dfe515d7d5a 827cf5aad2998502c5646d5f85d2ff2e 4a826162d20d677140ae4d10dea0d5c0 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vminnm.f32 s15,s16,s20 d4fb64aad9776f0b743133ccd4fb64aa 20075dfa8335cebc4e2a023bac4b24bf 9a50b16c6a1df2cbc4092f5490e56a71 ac4b24bfd9776f0b743133ccd4fb64aa 20075dfa8335cebc4e2a023bac4b24bf 9a50b16c6a1df2cbc4092f5490e56a71 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vminnm.f32 s15,s16,s20 afbaba6ea187d67ea5614334903aed4b 90e097a6d12efe48b8603da0b2a3b221 30ab4bc2527345592ad6425b3d92e831 b2a3b221a187d67ea5614334903aed4b 90e097a6d12efe48b8603da0b2a3b221 30ab4bc2527345592ad6425b3d92e831 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vminnm.f32 s15,s16,s20 24b20aaf785513bc9a605826fac6a020 aae6bbc6e8879b711a54879156636c43 35954ca5cc5e7e9f9efe46cdfeed83b8 feed83b8785513bc9a605826fac6a020 aae6bbc6e8879b711a54879156636c43 35954ca5cc5e7e9f9efe46cdfeed83b8 fpscr=00000000
+vminnm.f32 s15,s16,s20 81199ec2318f2daa5ac5670910d8b570 3927a0ca85a892d96a6a1f801278ed4c d49652f482195a01ec693acb781f1420 1278ed4c318f2daa5ac5670910d8b570 3927a0ca85a892d96a6a1f801278ed4c d49652f482195a01ec693acb781f1420 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[3]
+vminnm.f32 s15,s16,s20 5f528ccbe925fcb142dbed8a3a4a165c bf07eddcb3f25f849f2bff099f2bff09 a1d011233588b38f2fabce6b555ecdf7 9f2bff09e925fcb142dbed8a3a4a165c bf07eddcb3f25f849f2bff099f2bff09 a1d011233588b38f2fabce6b555ecdf7 fpscr=00000000
+vminnm.f32 s15,s16,s20 f02d931ff9448bbf628658ed9ad7fcb0 c60717aefe9ef52ae9d2676d0cabfb3f 6edccbae02a30ffb040f7b09de34d1b3 de34d1b3f9448bbf628658ed9ad7fcb0 c60717aefe9ef52ae9d2676d0cabfb3f 6edccbae02a30ffb040f7b09de34d1b3 fpscr=00000000
+vminnm.f64 d7, d8, d10 9ec1549c947ffeb078a9cd64475cfe51 ec90ec5637aeea905e01bf2020199da2 10d4263a635e43544e09b843ec70cbf2 4e09b843ec70cbf278a9cd64475cfe51 ec90ec5637aeea905e01bf2020199da2 10d4263a635e43544e09b843ec70cbf2 fpscr=00000000
+vminnm.f64 d7, d8, d10 a79b82a3915f8f4eab3ba580448a4d62 fe1dfc2afeccb03ff219be3a1cffa2c2 bab0d1f8c4709b93a9025dae0f6fe389 f219be3a1cffa2c2ab3ba580448a4d62 fe1dfc2afeccb03ff219be3a1cffa2c2 bab0d1f8c4709b93a9025dae0f6fe389 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vminnm.f64 d7, d8, d10 2c88331f90dd96f5c257b6db39e08ceb 6aef1b4fcb55517e8d16e95cb5fddb54 a9f14a4a6e9b540588086c5d7c7f5178 8d16e95cb5fddb54c257b6db39e08ceb 6aef1b4fcb55517e8d16e95cb5fddb54 a9f14a4a6e9b540588086c5d7c7f5178 fpscr=00000000
+vminnm.f64 d7, d8, d10 a312d8adcf70f7b073807b60a2968434 7541ec0d5d931043f218d534f5cc01e0 99c86c2e0bbf93dc7e9eff0ae76a330e f218d534f5cc01e073807b60a2968434 7541ec0d5d931043f218d534f5cc01e0 99c86c2e0bbf93dc7e9eff0ae76a330e fpscr=00000000
+randV128: 3328 calls, 3433 iters
+vminnm.f64 d7, d8, d10 f54010b5626ae4b563444de1631da251 8685da542b592a4b3c3d4e8ac50e41f5 eaaae575264f4936aa98e06fdc7298e5 aa98e06fdc7298e563444de1631da251 8685da542b592a4b3c3d4e8ac50e41f5 eaaae575264f4936aa98e06fdc7298e5 fpscr=00000000
+vminnm.f64 d7, d8, d10 e6b2955a9d7dd5b11d793dd305c9dae2 e2e02e55b46637c94ed58869966c4c1f ede7d25073f573b32d70940120dbb390 2d70940120dbb3901d793dd305c9dae2 e2e02e55b46637c94ed58869966c4c1f ede7d25073f573b32d70940120dbb390 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 5d2f676fd7d22aebbe30546279fcf7e3 34802b4c69984b222399fdfff45679b9 b7c7bc615c094af02cdf03077754c581 2399fdfff45679b9be30546279fcf7e3 34802b4c69984b222399fdfff45679b9 b7c7bc615c094af02cdf03077754c581 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 48b6e18fd00f054e996900f989cddb83 2b65c73a61505bdf2b65c73a61505bdf 90e329eeaf1d3cb617b2edbeee77c7c8 17b2edbeee77c7c8996900f989cddb83 2b65c73a61505bdf2b65c73a61505bdf 90e329eeaf1d3cb617b2edbeee77c7c8 fpscr=00000000
+vminnm.f64 d7, d8, d10 6e98400f51d1730d46d250dcdcc6bce0 8b971e805f3b112d467b2701af72b3c6 750958ad7f069d73549c4f572252b1f0 467b2701af72b3c646d250dcdcc6bce0 8b971e805f3b112d467b2701af72b3c6 750958ad7f069d73549c4f572252b1f0 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vminnm.f64 d7, d8, d10 21846857892877452184685789287745 1d6ee545100c3ea4c31cc94c221790dd 9e2d0d30e832c9b1d6891db29d833f51 d6891db29d833f512184685789287745 1d6ee545100c3ea4c31cc94c221790dd 9e2d0d30e832c9b1d6891db29d833f51 fpscr=00000000
+vminnm.f64 d7, d8, d10 ed6365f4b13d579ca65c0cac279a331e ad464d99b21283efbaeac4cc502dfbe0 282451202d689b5f952fa2ddadea6bb6 baeac4cc502dfbe0a65c0cac279a331e ad464d99b21283efbaeac4cc502dfbe0 282451202d689b5f952fa2ddadea6bb6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 95dadac549fc28794a712e41e3990e63 e0a1f93b23bd1340b9d0caade3b8ca53 6924c4d04588fad5b38ef7bf6ef9cba8 b9d0caade3b8ca534a712e41e3990e63 e0a1f93b23bd1340b9d0caade3b8ca53 6924c4d04588fad5b38ef7bf6ef9cba8 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 07cccb52ab09c66007cccb52ab09c660 625e408720980f918e0a10489248665f 98b073c1ae20aabc53c826337d114419 8e0a10489248665f07cccb52ab09c660 625e408720980f918e0a10489248665f 98b073c1ae20aabc53c826337d114419 fpscr=00000000
+vminnm.f64 d7, d8, d10 4769971114ed35c462edefe2ad6b86f0 51136e1b417d3f188a01bda0b5cbd541 0c69ee4f94c12f0ae997c81eed953889 e997c81eed95388962edefe2ad6b86f0 51136e1b417d3f188a01bda0b5cbd541 0c69ee4f94c12f0ae997c81eed953889 fpscr=00000000
+vminnm.f64 d7, d8, d10 08ff5f717f4541312bb93e4ab70c0661 2be8005b5d11522a9acd93f6e1a4bf89 32ce8629633b3f7244e55dfb09a5e826 9acd93f6e1a4bf892bb93e4ab70c0661 2be8005b5d11522a9acd93f6e1a4bf89 32ce8629633b3f7244e55dfb09a5e826 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 70bbc633447d5501305708f3da9f09f3 11a138c608674b5e11a138c608674b5e 2a0582bf8a507918c95a802b06e03ca6 c95a802b06e03ca6305708f3da9f09f3 11a138c608674b5e11a138c608674b5e 2a0582bf8a507918c95a802b06e03ca6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 11748cc0a04110dbee0e004a6d33d40a 814fc161cc3b86874baac00e25156ad3 39fee40d03b52d8399fd0182db9686c8 99fd0182db9686c8ee0e004a6d33d40a 814fc161cc3b86874baac00e25156ad3 39fee40d03b52d8399fd0182db9686c8 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vminnm.f64 d7, d8, d10 f8f5eb2bd4cc3278d9c28987088ebb74 687b6874ac69c54e687b6874ac69c54e e04ff3c0cc9e57382541d9c33ad50b54 2541d9c33ad50b54d9c28987088ebb74 687b6874ac69c54e687b6874ac69c54e e04ff3c0cc9e57382541d9c33ad50b54 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 0de3d32e7cd9086c0de3d32e7cd9086c 6bc9774a7e25fc8bb01edfacdf8ac25f 326cd2fe3712125c212178108f417431 b01edfacdf8ac25f0de3d32e7cd9086c 6bc9774a7e25fc8bb01edfacdf8ac25f 326cd2fe3712125c212178108f417431 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vminnm.f64 d7, d8, d10 8a81c5fd311b604c8a81c5fd311b604c 1a37d2a98af6b0475ed1beed6a5711bc f51a2c0783f303c0f51a2c0783f303c0 f51a2c0783f303c08a81c5fd311b604c 1a37d2a98af6b0475ed1beed6a5711bc f51a2c0783f303c0f51a2c0783f303c0 fpscr=00000000
+vminnm.f64 d7, d8, d10 220b085975c7a3c660b975f0383bffd6 8ab5d33be766a2af6e820706ee7650b5 c184f01a4634642b2590198ea9cc39a8 2590198ea9cc39a860b975f0383bffd6 8ab5d33be766a2af6e820706ee7650b5 c184f01a4634642b2590198ea9cc39a8 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 6d9cd02f0271d0516d9cd02f0271d051 2c11278ef5961e958ce66de3b273bdbe cd910de5eada647caef734dd13660347 aef734dd136603476d9cd02f0271d051 2c11278ef5961e958ce66de3b273bdbe cd910de5eada647caef734dd13660347 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 d1d0240f9bbf5022d1d0240f9bbf5022 788db58718eb1fb8e14e997675c86db4 c81b0e070b8af4476523ba552d182cc6 e14e997675c86db4d1d0240f9bbf5022 788db58718eb1fb8e14e997675c86db4 c81b0e070b8af4476523ba552d182cc6 fpscr=00000000
+vminnm.f64 d7, d8, d10 76682dcdaa5f3b2009ac97e33c494d2a a5266625a1458c0d9da583c5958459b8 4f428d6b1b442e5cbe1c042de1a001a2 be1c042de1a001a209ac97e33c494d2a a5266625a1458c0d9da583c5958459b8 4f428d6b1b442e5cbe1c042de1a001a2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 f4eb9b3491cb064491bc2b888e1301c7 f9719f065bfe66ec13ab103abfc21302 cd8da1b2b6bd34179f3291145c50d2e5 9f3291145c50d2e591bc2b888e1301c7 f9719f065bfe66ec13ab103abfc21302 cd8da1b2b6bd34179f3291145c50d2e5 fpscr=00000000
+vminnm.f64 d7, d8, d10 92b5cc13407b10facd4630f5eb58184d 9275a105fbdcc61fb4f968a7cf7f7c73 a34bb754b1d2a092bfd4c56b483ef726 bfd4c56b483ef726cd4630f5eb58184d 9275a105fbdcc61fb4f968a7cf7f7c73 a34bb754b1d2a092bfd4c56b483ef726 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 198403cbb09aad37b18c1a38458da3c8 594955ac5535cf9c594955ac5535cf9c 45173c9854dd5623c418f6d184202c9f c418f6d184202c9fb18c1a38458da3c8 594955ac5535cf9c594955ac5535cf9c 45173c9854dd5623c418f6d184202c9f fpscr=00000000
+vminnm.f64 d7, d8, d10 9a8a255fcb043fea90fe9f3796fcd137 5a98438632fd60ad9fed876786a02dd9 7c4e0f9638646d144b1b4a608dcb8a7b 9fed876786a02dd990fe9f3796fcd137 5a98438632fd60ad9fed876786a02dd9 7c4e0f9638646d144b1b4a608dcb8a7b fpscr=00000000
+vminnm.f64 d7, d8, d10 584cc0eab93691a24040ae322b196167 51ea76b695b9598113dfc32e1d376be0 7049997b8d3de13226de28643c1e87f2 13dfc32e1d376be04040ae322b196167 51ea76b695b9598113dfc32e1d376be0 7049997b8d3de13226de28643c1e87f2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 6bc945ee0c4749a7e6d717df1c551bef 4dfef88be36457b1c60f6e50928e9f9b 01f5aef560f270e701f5aef560f270e7 c60f6e50928e9f9be6d717df1c551bef 4dfef88be36457b1c60f6e50928e9f9b 01f5aef560f270e701f5aef560f270e7 fpscr=00000000
+vminnm.f64 d7, d8, d10 29584bb3638541f81767cfd581e50028 d1079eaec96aec6598074be49b3dc0f3 567ed59aaae490d7d98443038dac0e9f d98443038dac0e9f1767cfd581e50028 d1079eaec96aec6598074be49b3dc0f3 567ed59aaae490d7d98443038dac0e9f fpscr=00000000
+vminnm.f64 d7, d8, d10 1c205b3b940310d30932c82b2605cad6 57043d12b557bd2b51db45f1d02f59b9 91eb19720583927a0be916c41d24d422 0be916c41d24d4220932c82b2605cad6 57043d12b557bd2b51db45f1d02f59b9 91eb19720583927a0be916c41d24d422 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vminnm.f64 d7, d8, d10 4bd09af378c7960d4bd09af378c7960d 2d0308627cc2a7cbfdf97f8b140a4707 351d130e5ad47fce351d130e5ad47fce fdf97f8b140a47074bd09af378c7960d 2d0308627cc2a7cbfdf97f8b140a4707 351d130e5ad47fce351d130e5ad47fce fpscr=00000000
+vminnm.f64 d7, d8, d10 1fbb00ebaf8a95bbde0452f075634264 25984cab1808a12165e9f2a72383e102 34363a26516ccef4f4eb9c1d14c70acc f4eb9c1d14c70accde0452f075634264 25984cab1808a12165e9f2a72383e102 34363a26516ccef4f4eb9c1d14c70acc fpscr=00000000
+vminnm.f64 d7, d8, d10 79cf50c81b4db67658e0a64ac3e5927f c03de1a887567130f3aa58b47815d64a 7547867ba4f72828ad55e70c78af8c69 f3aa58b47815d64a58e0a64ac3e5927f c03de1a887567130f3aa58b47815d64a 7547867ba4f72828ad55e70c78af8c69 fpscr=00000000
+vminnm.f64 d7, d8, d10 a213907a5bb89395228cf23e515dc116 f4173bd6da5a3f17ed5d7872c34e0a9a 32f0e426df8d5673d1991992c7c44e9a ed5d7872c34e0a9a228cf23e515dc116 f4173bd6da5a3f17ed5d7872c34e0a9a 32f0e426df8d5673d1991992c7c44e9a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 bf2cd9d50af025e3bf2cd9d50af025e3 3e28769e676205e7a9ca7fbe9441b358 1e7251f658653e5c42aa5ca5227a50ab a9ca7fbe9441b358bf2cd9d50af025e3 3e28769e676205e7a9ca7fbe9441b358 1e7251f658653e5c42aa5ca5227a50ab fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vminnm.f64 d7, d8, d10 eac12e3944df9ab1eac12e3944df9ab1 314e17b383e9c115ddeccbb00ace9061 c46c7499b555a62a814baf3edb687f3a ddeccbb00ace9061eac12e3944df9ab1 314e17b383e9c115ddeccbb00ace9061 c46c7499b555a62a814baf3edb687f3a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vminnm.f64 d7, d8, d10 4437d397b9743eea4437d397b9743eea bf4ee30eaeb2ad9f2d14266dfe745df2 92487395bc490dba92487395bc490dba 92487395bc490dba4437d397b9743eea bf4ee30eaeb2ad9f2d14266dfe745df2 92487395bc490dba92487395bc490dba fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vminnm.f64 d7, d8, d10 4fc8fb3982ea9f3064fd20fc984d5ed2 2598a727cc12ff703dd79fad3dbe0bbf debde6a1833566913adc2a38aa6e5fed 3adc2a38aa6e5fed64fd20fc984d5ed2 2598a727cc12ff703dd79fad3dbe0bbf debde6a1833566913adc2a38aa6e5fed fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 47b319f62681891fc1eb8e49616fd615 61ede562bb7457843a9f257a4069babf 214495377475bea9214495377475bea9 214495377475bea9c1eb8e49616fd615 61ede562bb7457843a9f257a4069babf 214495377475bea9214495377475bea9 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 0b62c3a128c627570b62c3a128c62757 043680eec62a1940043680eec62a1940 a0113f7b3d00a487a0113f7b3d00a487 a0113f7b3d00a4870b62c3a128c62757 043680eec62a1940043680eec62a1940 a0113f7b3d00a487a0113f7b3d00a487 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 5c976443bd0713296f502ff8cf3da17e 020ef55a1b770c1047ed85af80c2ee92 5f577d08a074403e8732e10f789f4ae9 8732e10f789f4ae96f502ff8cf3da17e 020ef55a1b770c1047ed85af80c2ee92 5f577d08a074403e8732e10f789f4ae9 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 1229f40ae22f3e8d889328a80ea09247 8bef9baa8612f9c48bef9baa8612f9c4 67658674cd858f09bbe927e48a25cc63 bbe927e48a25cc63889328a80ea09247 8bef9baa8612f9c48bef9baa8612f9c4 67658674cd858f09bbe927e48a25cc63 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vminnm.f64 d7, d8, d10 438cf3a264405cb511e011eceabc8a97 2a12da48681ccb058e8c08f86319432c 4883bf5d84f4ceec4822b2555087d8cd 8e8c08f86319432c11e011eceabc8a97 2a12da48681ccb058e8c08f86319432c 4883bf5d84f4ceec4822b2555087d8cd fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vminnm.f64 d7, d8, d10 7eaa866be2dbff6faa3a512df4ab3ca2 1e59fbb636c5e7f71e59fbb636c5e7f7 50c798a9ca7d199220ebcf7e719230be 1e59fbb636c5e7f7aa3a512df4ab3ca2 1e59fbb636c5e7f71e59fbb636c5e7f7 50c798a9ca7d199220ebcf7e719230be fpscr=00000000
+vminnm.f64 d7, d8, d10 9cb2a35dbc82efac3b6487d679d2f1d4 11007afcf516e6650ae4b1b472a991ef a3c37c58d9837c5fb33a00cfec660ef7 b33a00cfec660ef73b6487d679d2f1d4 11007afcf516e6650ae4b1b472a991ef a3c37c58d9837c5fb33a00cfec660ef7 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: 3584 calls, 3696 iters
+randV128: doing v->u64[1] = v->u64[0]
+vminnm.f64 d7, d8, d10 6e94ba9741a454786e94ba9741a45478 316c3ccd0e18c9f5316c3ccd0e18c9f5 fc7177d43296dc4073fed4fda03d6415 316c3ccd0e18c9f56e94ba9741a45478 316c3ccd0e18c9f5316c3ccd0e18c9f5 fc7177d43296dc4073fed4fda03d6415 fpscr=00000000
+vminnm.f64 d7, d8, d10 0bcff263998f4a44b80ade780f0c9e89 5cf7cb9fb7996e611418f17ccdef0ae7 9d8feb5aaa9f1219a6c0aca13a182f34 a6c0aca13a182f34b80ade780f0c9e89 5cf7cb9fb7996e611418f17ccdef0ae7 9d8feb5aaa9f1219a6c0aca13a182f34 fpscr=00000000
+vminnm.f64 d7, d8, d10 2799d86db51d6d4557c89bbd15daa663 66b74276c49ba036af846d8cb0513b5d 1f8cef3da97dcf61057d84ce222fe110 af846d8cb0513b5d57c89bbd15daa663 66b74276c49ba036af846d8cb0513b5d 1f8cef3da97dcf61057d84ce222fe110 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.s32.f64 s27, d5 90fee8100cd5fcdbfb0aea5fd18f9878 349118e0e476089d5786937ece260dc4 000000000cd5fcdbfb0aea5fd18f9878 349118e0e476089d5786937ece260dc4 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.s32.f64 s27, d5 af52f88010a1793c4b4aae2d69481892 d62d843b7acd102936bf8ffb940bac20 8000000010a1793c4b4aae2d69481892 d62d843b7acd102936bf8ffb940bac20 fpscr=00000000
+vcvtn.s32.f64 s27, d5 e30cba8ce8afc882522bfa6d8669f89b c2275295a08361c6675a9b121522ed9e 80000000e8afc882522bfa6d8669f89b c2275295a08361c6675a9b121522ed9e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.s32.f64 s27, d5 921ada5bbda3e60c68ef7cd8025a8409 77bcd4719ae52216159738cc7552a745 7fffffffbda3e60c68ef7cd8025a8409 77bcd4719ae52216159738cc7552a745 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.s32.f64 s27, d5 a5c00450bfb1e4d0f8e4ea27ed4d999f b93cc92492ee1f0fb93cc92492ee1f0f 00000000bfb1e4d0f8e4ea27ed4d999f b93cc92492ee1f0fb93cc92492ee1f0f fpscr=00000000
+vcvtn.s32.f64 s27, d5 8adcff12cc476b2c0fa34a206d600ec6 2b18d2f46017574cdf80d9867b0013c5 00000000cc476b2c0fa34a206d600ec6 2b18d2f46017574cdf80d9867b0013c5 fpscr=00000000
+vcvtn.s32.f64 s27, d5 45e2f407a8e7b531a498925b2d57e73a 2287e87d55169baab785e8a6b3824560 00000000a8e7b531a498925b2d57e73a 2287e87d55169baab785e8a6b3824560 fpscr=00000000
+vcvtn.s32.f64 s27, d5 444d138025981175b654865a0f041c81 8f896e8cfb86188b9604074926c1ef13 0000000025981175b654865a0f041c81 8f896e8cfb86188b9604074926c1ef13 fpscr=00000000
+vcvtn.s32.f64 s27, d5 a00af8661f02febe49299f5a69a53e71 e6ac0a57f619128eab499c753e98083c 800000001f02febe49299f5a69a53e71 e6ac0a57f619128eab499c753e98083c fpscr=00000000
+vcvtn.s32.f64 s27, d5 ee74fa61eaa2c16d702647584cfb649e a9b1fbf67030bce1ce369d456f835a70 00000000eaa2c16d702647584cfb649e a9b1fbf67030bce1ce369d456f835a70 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.s32.f64 s27, d5 7526c9d91d40b0df7526c9d91d40b0df dcd8d1e40cba09fcdcd8d1e40cba09fc 800000001d40b0df7526c9d91d40b0df dcd8d1e40cba09fcdcd8d1e40cba09fc fpscr=00000000
+vcvtn.s32.f64 s27, d5 6ed57af105c9428f5a2f2ec6bad1f340 180d52b6c85c932554087f47d75cfe58 0000000005c9428f5a2f2ec6bad1f340 180d52b6c85c932554087f47d75cfe58 fpscr=00000000
+vcvtn.s32.f64 s27, d5 27fe4e5e1b6502b9b3b8e8e5fa247f43 534cc88b9bd6934c2fd755f5081e4216 7fffffff1b6502b9b3b8e8e5fa247f43 534cc88b9bd6934c2fd755f5081e4216 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.s32.f64 s27, d5 d4b9ca25543b9c4ed4b9ca25543b9c4e 339503f95c5b9382339503f95c5b9382 00000000543b9c4ed4b9ca25543b9c4e 339503f95c5b9382339503f95c5b9382 fpscr=00000000
+vcvtn.s32.f64 s27, d5 16bb7db339a7e7d66cc60944430fc315 7bcd89a7ab73a93bcfbe054d75703757 7fffffff39a7e7d66cc60944430fc315 7bcd89a7ab73a93bcfbe054d75703757 fpscr=00000000
+vcvtn.s32.f64 s27, d5 f2bf73fac3191a5251773b54d4909e42 aae3bfaff628bd76a93f9713ee95cbad 00000000c3191a5251773b54d4909e42 aae3bfaff628bd76a93f9713ee95cbad fpscr=00000000
+vcvtn.s32.f64 s27, d5 d85b0553f12cc975ded512d0aa80ee7b ed6d047cc9bcac96fe6aa8591e439480 80000000f12cc975ded512d0aa80ee7b ed6d047cc9bcac96fe6aa8591e439480 fpscr=00000000
+vcvtn.s32.f64 s27, d5 600362d1651635444cdd39c6474f478e 03e37934c6b981954beab5d0f372a830 00000000651635444cdd39c6474f478e 03e37934c6b981954beab5d0f372a830 fpscr=00000000
+vcvtn.s32.f64 s27, d5 2220dbef76419b551e5c1d60e532a34c e2b40d5113d3d32539a7e01e904d3a3b 8000000076419b551e5c1d60e532a34c e2b40d5113d3d32539a7e01e904d3a3b fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.s32.f64 s27, d5 54933584a61881f654933584a61881f6 1ef40d031757e33797b9c7193ecdc31c 00000000a61881f654933584a61881f6 1ef40d031757e33797b9c7193ecdc31c fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.s32.f64 s27, d5 dccc7cdf8428f17fd41a8b4ed0d1fbab 874da009a8082ae4874da009a8082ae4 000000008428f17fd41a8b4ed0d1fbab 874da009a8082ae4874da009a8082ae4 fpscr=00000000
+vcvtn.s32.f64 s27, d5 59f12c596b0028738dfb98fa71191355 4df5833cb320c969ac5bc6e41d4ca807 7fffffff6b0028738dfb98fa71191355 4df5833cb320c969ac5bc6e41d4ca807 fpscr=00000000
+vcvtn.s32.f64 s27, d5 3ae119d05f9cdbf20a95119ef82c3bcb 2160ae3c91cc95781ef87ff43fdf2bf6 000000005f9cdbf20a95119ef82c3bcb 2160ae3c91cc95781ef87ff43fdf2bf6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.s32.f64 s27, d5 d61eefa23c9164d1fb08f455a19577ae 590cd09503797b30bd708097ab8039f4 7fffffff3c9164d1fb08f455a19577ae 590cd09503797b30bd708097ab8039f4 fpscr=00000000
+vcvtn.s32.f64 s27, d5 d2533fb73531c2a57abb985649fb1efe c58f064e0bdab348e6dde8ff7034132b 800000003531c2a57abb985649fb1efe c58f064e0bdab348e6dde8ff7034132b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.s32.f64 s27, d5 f6d956f7a846dc7db41577aa0e19f428 e1f83b72a8250702e1f83b72a8250702 80000000a846dc7db41577aa0e19f428 e1f83b72a8250702e1f83b72a8250702 fpscr=00000000
+vcvtn.s32.f64 s27, d5 8a7c4af8c6c5074b2d476f58f4826ae6 9b57c96a018d2b71b7ffc205a9a3ef57 00000000c6c5074b2d476f58f4826ae6 9b57c96a018d2b71b7ffc205a9a3ef57 fpscr=00000000
+vcvtn.s32.f64 s27, d5 f345f2050f21d1eb70985743bb00657d 088ebbb8658d83735757f51f90172d6e 000000000f21d1eb70985743bb00657d 088ebbb8658d83735757f51f90172d6e fpscr=00000000
+vcvtn.s32.f64 s27, d5 1edb8be1f468b449e87dd22eef6c5244 978034cf287f804e7ece8cedd52fd9f0 00000000f468b449e87dd22eef6c5244 978034cf287f804e7ece8cedd52fd9f0 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.s32.f64 s27, d5 f436c3caf52d3dd788b87ce3f5f12b22 ece91f25bd7e8ee17c3a8b6445fb45b8 80000000f52d3dd788b87ce3f5f12b22 ece91f25bd7e8ee17c3a8b6445fb45b8 fpscr=00000000
+vcvtn.s32.f64 s27, d5 60659f3bd81af30db3ca886c79ea7c81 ab1ad7a1d8718f543c12bc531b7f5ce4 00000000d81af30db3ca886c79ea7c81 ab1ad7a1d8718f543c12bc531b7f5ce4 fpscr=00000000
+vcvtn.s32.f64 s27, d5 14d692722d428ef08c5d9844bf02c9db e74efc9b79b479f5beff0576cf3daca3 800000002d428ef08c5d9844bf02c9db e74efc9b79b479f5beff0576cf3daca3 fpscr=00000000
+vcvtn.s32.f64 s27, d5 521db966c38b67be2674e70b5e6fc94b ba2bbe9be0f0f66d3a7346ec2123a1dd 00000000c38b67be2674e70b5e6fc94b ba2bbe9be0f0f66d3a7346ec2123a1dd fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.s32.f64 s27, d5 bfc467892f6e74766eda45c52c5989ec e46d6f626c56ef630404e3004f37a064 800000002f6e74766eda45c52c5989ec e46d6f626c56ef630404e3004f37a064 fpscr=00000000
+vcvtn.s32.f64 s27, d5 6b223317e0e73ee0b2cef672b500b6f7 e05ef38a602746b2a0c08904dd2137e9 80000000e0e73ee0b2cef672b500b6f7 e05ef38a602746b2a0c08904dd2137e9 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.s32.f64 s27, d5 6df80d460613e5f24e7959fbdb1d68e1 2ad595fd3f30c890a041336112c34142 000000000613e5f24e7959fbdb1d68e1 2ad595fd3f30c890a041336112c34142 fpscr=00000000
+vcvtn.s32.f64 s27, d5 6a9954f8fc7e1b92af25b316f74161b9 87a99dbbdba8d9758b61008d07adeaf8 00000000fc7e1b92af25b316f74161b9 87a99dbbdba8d9758b61008d07adeaf8 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.s32.f64 s27, d5 126d0964aeae528c126d0964aeae528c f017af13c070a20c9cbd66215ee8ff4e 80000000aeae528c126d0964aeae528c f017af13c070a20c9cbd66215ee8ff4e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.s32.f64 s27, d5 4ff81cfd4109cb254ff81cfd4109cb25 40dc0f269c976ad9bd7541025d1d4d5d 0000703d4109cb254ff81cfd4109cb25 40dc0f269c976ad9bd7541025d1d4d5d fpscr=00000000
+vcvtn.s32.f64 s27, d5 0964b1f33ddd90244704f9ab858d06be 00a35c7f7e9df161dd82eb9d1fb4b13a 000000003ddd90244704f9ab858d06be 00a35c7f7e9df161dd82eb9d1fb4b13a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.s32.f64 s27, d5 5985a4650b064e552ae602b08f3874dc 64c95ed7eecf5c91ae082e688955c1c6 7fffffff0b064e552ae602b08f3874dc 64c95ed7eecf5c91ae082e688955c1c6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.s32.f64 s27, d5 42915857d1727e7df33ea69a95f1e7a2 3c529920280185733c52992028018573 00000000d1727e7df33ea69a95f1e7a2 3c529920280185733c52992028018573 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.s32.f64 s27, d5 efee5fc6feb274876dcd7cf8df800569 af1013836ac7e496af1013836ac7e496 00000000feb274876dcd7cf8df800569 af1013836ac7e496af1013836ac7e496 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.s32.f64 s27, d5 faf6f2d9bfcc57d4f47238e723cb7070 4afe5e1590aedf954afe5e1590aedf95 7fffffffbfcc57d4f47238e723cb7070 4afe5e1590aedf954afe5e1590aedf95 fpscr=00000000
+vcvtn.s32.f64 s27, d5 10cfb8612d1f4b652f5d9aecc7658fce 0aee4fd5f3f0120f665b74592cc42e19 000000002d1f4b652f5d9aecc7658fce 0aee4fd5f3f0120f665b74592cc42e19 fpscr=00000000
+vcvtn.s32.f64 s27, d5 e7bb24273932e67bea3e510df77288b6 f1203ab706cab0deade6bf72a97b9fff 800000003932e67bea3e510df77288b6 f1203ab706cab0deade6bf72a97b9fff fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.s32.f64 s27, d5 3121e28650ebf0573121e28650ebf057 f28d3c301d770f5b899afeb34ef199cd 8000000050ebf0573121e28650ebf057 f28d3c301d770f5b899afeb34ef199cd fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.s32.f64 s27, d5 07a2561d84bab44dac60ca4fbd618bf2 f4af9c4a973475e6f4af9c4a973475e6 8000000084bab44dac60ca4fbd618bf2 f4af9c4a973475e6f4af9c4a973475e6 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.s32.f64 s27, d5 72e6d24ae307e0dc5b03c5e9e3ce4cec 7477951d11aa5121c8c1dd4af79c4eb5 7fffffffe307e0dc5b03c5e9e3ce4cec 7477951d11aa5121c8c1dd4af79c4eb5 fpscr=00000000
+vcvtn.s32.f64 s27, d5 e8f322a8fc299eafe9faf4c338164d9b 715e8d0c83aa81ed1598959f39541589 7ffffffffc299eafe9faf4c338164d9b 715e8d0c83aa81ed1598959f39541589 fpscr=00000000
+vcvta.s32.f64 s4, d20 0bbc664c856b28631ba9138a130b7924 682f52705f91f731b2a643c3207d30a0 0bbc664c856b28631ba9138a00000000 682f52705f91f731b2a643c3207d30a0 fpscr=00000000
+vcvta.s32.f64 s4, d20 6f35416b040a850f337b75cd19b39b5b 8e6ebe2f88e618298cf1ef31d28c829e 6f35416b040a850f337b75cd00000000 8e6ebe2f88e618298cf1ef31d28c829e fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.s32.f64 s4, d20 ad03ad8fae9155f4f502099bcf7be641 29b82782fc08311a89675e8542090b73 ad03ad8fae9155f4f502099b00000000 29b82782fc08311a89675e8542090b73 fpscr=00000000
+vcvta.s32.f64 s4, d20 4b5e40f641f2bf2b49798fcfd8401b77 8eb35c674704542221a51bbddf2de515 4b5e40f641f2bf2b49798fcf00000000 8eb35c674704542221a51bbddf2de515 fpscr=00000000
+vcvta.s32.f64 s4, d20 48fdd0475b4076107a19a25c535df34f 169af45191d8dea8826c4654fb6d4c6c 48fdd0475b4076107a19a25c00000000 169af45191d8dea8826c4654fb6d4c6c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.s32.f64 s4, d20 bceef7694a3078abbceef7694a3078ab 56ff0f65bfb898fa56ff0f65bfb898fa bceef7694a3078abbceef7697fffffff 56ff0f65bfb898fa56ff0f65bfb898fa fpscr=00000000
+vcvta.s32.f64 s4, d20 6bce17b8793952bc28f90e0d260093d1 58f6c71be48b630a08a348e720c0c19a 6bce17b8793952bc28f90e0d00000000 58f6c71be48b630a08a348e720c0c19a fpscr=00000000
+vcvta.s32.f64 s4, d20 9742dc845a0e09f508d95aa41353f41c 5092a1a458e829fd9c653ef66299505d 9742dc845a0e09f508d95aa400000000 5092a1a458e829fd9c653ef66299505d fpscr=00000000
+vcvta.s32.f64 s4, d20 c9ce429dcaa25f1fa7f8eea4d74ce698 651ce7516d2f7852686f4c491f37855e c9ce429dcaa25f1fa7f8eea47fffffff 651ce7516d2f7852686f4c491f37855e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: 3840 calls, 3963 iters
+vcvta.s32.f64 s4, d20 c330376cc0b05ea3c330376cc0b05ea3 bcdd1f808deb40edc8b8a375ace71733 c330376cc0b05ea3c330376c80000000 bcdd1f808deb40edc8b8a375ace71733 fpscr=00000000
+vcvta.s32.f64 s4, d20 5359da301f1f5b7f93b31fb99875239d ee58ac322cfd8e072a805fa2d5aa5c7f 5359da301f1f5b7f93b31fb900000000 ee58ac322cfd8e072a805fa2d5aa5c7f fpscr=00000000
+vcvta.s32.f64 s4, d20 1c3b0cfe6071fc1a1318897aa7852a1b ca66450d6647b2df265a0643311b3915 1c3b0cfe6071fc1a1318897a00000000 ca66450d6647b2df265a0643311b3915 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.s32.f64 s4, d20 b0faa406a244bd8ab0faa406a244bd8a 469441e2410f0f385a37341cbdb4c8f8 b0faa406a244bd8ab0faa4067fffffff 469441e2410f0f385a37341cbdb4c8f8 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.s32.f64 s4, d20 0ff336666fafa084ad619d56f4d58366 8437c3602556381ff0561857b2fe3a38 0ff336666fafa084ad619d5680000000 8437c3602556381ff0561857b2fe3a38 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.s32.f64 s4, d20 6ffe11c7222cc356fa5d538774101ee6 925393b565d1ee932572ba338c058361 6ffe11c7222cc356fa5d538700000000 925393b565d1ee932572ba338c058361 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.s32.f64 s4, d20 2c1726f7e1fbc334ba95b6a8a4d735b3 07887aef75de8e8a07887aef75de8e8a 2c1726f7e1fbc334ba95b6a800000000 07887aef75de8e8a07887aef75de8e8a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.s32.f64 s4, d20 188c03531b96cf79188c03531b96cf79 f16f16ed66f82551938286f577ddacb9 188c03531b96cf79188c035300000000 f16f16ed66f82551938286f577ddacb9 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.s32.f64 s4, d20 1a48699ad92a6c9427f085d58fd1a329 3c2d024ce96ff1ef4c50ba8938cd74e6 1a48699ad92a6c9427f085d57fffffff 3c2d024ce96ff1ef4c50ba8938cd74e6 fpscr=00000000
+vcvta.s32.f64 s4, d20 aea822055609942f3e4860b7cae1540e 06293083997a532993dba4f1512fd116 aea822055609942f3e4860b700000000 06293083997a532993dba4f1512fd116 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.s32.f64 s4, d20 98f2c24ae690a2efcbb26b8c41d5a463 8d35a509a903ce31e86609ce28e12c9a 98f2c24ae690a2efcbb26b8c80000000 8d35a509a903ce31e86609ce28e12c9a fpscr=00000000
+vcvta.s32.f64 s4, d20 5736101e5e4b170bb55b1dfb28f78ab3 fd4a855044607252b827cf4157418525 5736101e5e4b170bb55b1dfb00000000 fd4a855044607252b827cf4157418525 fpscr=00000000
+vcvta.s32.f64 s4, d20 d6fc759e240c3081eb216db9bd8b7170 97b109300399fddfa2b8030c58bb2da6 d6fc759e240c3081eb216db900000000 97b109300399fddfa2b8030c58bb2da6 fpscr=00000000
+vcvta.s32.f64 s4, d20 890179a0c75206bf4f8c4356b9ca4773 63b49fb3198c566c197e36daca080043 890179a0c75206bf4f8c435600000000 63b49fb3198c566c197e36daca080043 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.s32.f64 s4, d20 f3e8b878b71529fdf3e8b878b71529fd 5be1eece46028465ed73b25a7bc19fd9 f3e8b878b71529fdf3e8b87880000000 5be1eece46028465ed73b25a7bc19fd9 fpscr=00000000
+vcvta.s32.f64 s4, d20 0ff68a6c90fa10bda7135388ebe33c1d 32ba4d322687e54f649d214987dbc2fd 0ff68a6c90fa10bda71353887fffffff 32ba4d322687e54f649d214987dbc2fd fpscr=00000000
+vcvta.s32.f64 s4, d20 c9a753ca367d71290bc2883c95850efc ab36c8474ab2c709eab01e20a54d9b3e c9a753ca367d71290bc2883c80000000 ab36c8474ab2c709eab01e20a54d9b3e fpscr=00000000
+vcvta.s32.f64 s4, d20 f25125241ec33eb516946d2771d477a6 12c9da0bb3b0486af15baa2e083bfa20 f25125241ec33eb516946d2780000000 12c9da0bb3b0486af15baa2e083bfa20 fpscr=00000000
+vcvta.s32.f64 s4, d20 0ad831116ba4dee7ba769cf78f9c60c7 91bd9d4ad1f31abb40e9b7b888955581 0ad831116ba4dee7ba769cf70000cdbe 91bd9d4ad1f31abb40e9b7b888955581 fpscr=00000000
+vcvta.s32.f64 s4, d20 3f28e2d0fc1831fc99f348777d1f4ef0 707c8cc257a2edf96cc92f55b3c07512 3f28e2d0fc1831fc99f348777fffffff 707c8cc257a2edf96cc92f55b3c07512 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.s32.f64 s4, d20 17e158043b83303af01b018a5d9e4535 a2c5ac2070e731efae025730432d79b9 17e158043b83303af01b018a00000000 a2c5ac2070e731efae025730432d79b9 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.s32.f64 s4, d20 cfb4fd57c7c8cc5b6aa967c74d7dc740 cd89c4b20edc581d4138187a9622f7bd cfb4fd57c7c8cc5b6aa967c70018187b cd89c4b20edc581d4138187a9622f7bd fpscr=00000000
+vcvta.s32.f64 s4, d20 171b3b91b3fbb6211a295f2ac14327be 2f20a3a46baebaf54fdee5192b2c9cb4 171b3b91b3fbb6211a295f2a7fffffff 2f20a3a46baebaf54fdee5192b2c9cb4 fpscr=00000000
+vcvta.s32.f64 s4, d20 d21d73de9c211adcc4f4c5ea644f61f2 9a5fd110df3af097f2f03941ce2ee7f8 d21d73de9c211adcc4f4c5ea80000000 9a5fd110df3af097f2f03941ce2ee7f8 fpscr=00000000
+vcvta.s32.f64 s4, d20 837659a9ef2557bceb079f39cf88db6e 146229542ea5d28fee16f568a2a6ab4d 837659a9ef2557bceb079f3980000000 146229542ea5d28fee16f568a2a6ab4d fpscr=00000000
+vcvta.s32.f64 s4, d20 ae6ef824bdf21c1462143ec1e22ea907 77b16956a59067b217b910cbbc9213f7 ae6ef824bdf21c1462143ec100000000 77b16956a59067b217b910cbbc9213f7 fpscr=00000000
+vcvta.s32.f64 s4, d20 850b037ea3640315e17bc88bb67ceea2 8eca746fdbe570f1efce7be8a2d90d0b 850b037ea3640315e17bc88b80000000 8eca746fdbe570f1efce7be8a2d90d0b fpscr=00000000
+vcvta.s32.f64 s4, d20 828d3dafd19d0e2b30a207eb2903afbd 3eeaa3c5b35b778e199afb86bef866f6 828d3dafd19d0e2b30a207eb00000000 3eeaa3c5b35b778e199afb86bef866f6 fpscr=00000000
+vcvta.s32.f64 s4, d20 24c5c12bb8f526c894672a6e7f4ad6b9 631bcf221bf3cf32a4fbaa952428693e 24c5c12bb8f526c894672a6e00000000 631bcf221bf3cf32a4fbaa952428693e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.s32.f64 s4, d20 f09b794cb579a8fbdb2425d52f4ab627 56d2aaa909e4d31782003b0d400aefe4 f09b794cb579a8fbdb2425d500000000 56d2aaa909e4d31782003b0d400aefe4 fpscr=00000000
+vcvta.s32.f64 s4, d20 b769e924dc25516f96cb08610bfc4cf9 388ffb1c875de32911f6d70704615273 b769e924dc25516f96cb086100000000 388ffb1c875de32911f6d70704615273 fpscr=00000000
+vcvta.s32.f64 s4, d20 5f6dab4e90fdf72adcdaabc6f59a7f5f dcaca5378c4a7eb59cc6179074ddace6 5f6dab4e90fdf72adcdaabc600000000 dcaca5378c4a7eb59cc6179074ddace6 fpscr=00000000
+vcvta.s32.f64 s4, d20 be6ae06d71b109b6f6de95e144dd5f7f 9722d086bd0af70e37eb04765a70d069 be6ae06d71b109b6f6de95e100000000 9722d086bd0af70e37eb04765a70d069 fpscr=00000000
+vcvta.s32.f64 s4, d20 baf014aaf9ef5664f800ecdd4bea2229 9947bee6eaac7a3a63b58b8118d36ebe baf014aaf9ef5664f800ecdd7fffffff 9947bee6eaac7a3a63b58b8118d36ebe fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.s32.f64 s4, d20 619ced510455f03d619ced510455f03d f20d776cf8687ef8d71e4f478460ad0c 619ced510455f03d619ced5180000000 f20d776cf8687ef8d71e4f478460ad0c fpscr=00000000
+vcvta.s32.f64 s4, d20 5b7d6ff8c000f56e634aafe05d4b00d2 058dbeebad612f19062fa4e24ffea655 5b7d6ff8c000f56e634aafe000000000 058dbeebad612f19062fa4e24ffea655 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.s32.f64 s4, d20 e8d1363988b23f92e8d1363988b23f92 e2e68223618ceae7879d828b35845036 e8d1363988b23f92e8d1363900000000 e2e68223618ceae7879d828b35845036 fpscr=00000000
+vcvta.s32.f64 s4, d20 0eb6dc33dfd83baf48a3492bdbedf443 1cea865a0545bfa056e2876c8cf451ea 0eb6dc33dfd83baf48a3492b7fffffff 1cea865a0545bfa056e2876c8cf451ea fpscr=00000000
+vcvta.s32.f64 s4, d20 4ef9dfb01617815bb2a9581fedecfdc9 3c472cbb306939fe01d533fe5723bc7c 4ef9dfb01617815bb2a9581f00000000 3c472cbb306939fe01d533fe5723bc7c fpscr=00000000
+vcvta.s32.f64 s4, d20 ae6977ce0d5cc9e3fd5586453d589e03 35d949c6562640d1aa1e809ab5f6bd9d ae6977ce0d5cc9e3fd55864500000000 35d949c6562640d1aa1e809ab5f6bd9d fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.s32.f64 s4, d20 915808e6214e4bcf915808e6214e4bcf 7732c7290947c970563f44a226556b6a 915808e6214e4bcf915808e67fffffff 7732c7290947c970563f44a226556b6a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.s32.f64 s7, d31 a653ab4b37ca6891205923a9b08339cf 3618806a53fbe71a3618806a53fbe71a 0000000137ca6891205923a9b08339cf 3618806a53fbe71a3618806a53fbe71a fpscr=00000000
+vcvtp.s32.f64 s7, d31 26215a20eee72442448ef9e9799dc444 043897ef95bbaff2e354519097ea5263 00000001eee72442448ef9e9799dc444 043897ef95bbaff2e354519097ea5263 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.s32.f64 s7, d31 3980cca2c41673721b022a50fda80026 2e85fc21492f2cfd2e85fc21492f2cfd 00000001c41673721b022a50fda80026 2e85fc21492f2cfd2e85fc21492f2cfd fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.s32.f64 s7, d31 0c5de3a056da2a8ff25dbfce97f0ed3d c4eb66b1a1ce7690a0a6a8c3f3ed0aa6 8000000056da2a8ff25dbfce97f0ed3d c4eb66b1a1ce7690a0a6a8c3f3ed0aa6 fpscr=00000000
+vcvtp.s32.f64 s7, d31 4babb6d9eb2698ee2e3bf321041ddec9 a0e01ebd96d2c2e285ec1d8f9740b6e6 00000000eb2698ee2e3bf321041ddec9 a0e01ebd96d2c2e285ec1d8f9740b6e6 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.s32.f64 s7, d31 355ea65def5cb330355ea65def5cb330 6c87415b461dcaa27ca96d5824949a17 7fffffffef5cb330355ea65def5cb330 6c87415b461dcaa27ca96d5824949a17 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.s32.f64 s7, d31 bc4adf05100e8356c26be03b925367d2 fea77cd8d46beb616fef5acb962f84ec 80000000100e8356c26be03b925367d2 fea77cd8d46beb616fef5acb962f84ec fpscr=00000000
+vcvtp.s32.f64 s7, d31 4f636797685cdc95a524b84477b454ca d598361c0afa5572577f100a608f54fd 80000000685cdc95a524b84477b454ca d598361c0afa5572577f100a608f54fd fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.s32.f64 s7, d31 f15163d389922914fb359964c45aef79 00946f7b3da3cc6c59c650d18eb879b0 0000000189922914fb359964c45aef79 00946f7b3da3cc6c59c650d18eb879b0 fpscr=00000000
+vcvtp.s32.f64 s7, d31 a58262703cac67c502f85982575c8679 619415e58328472200c38d7b3b9fca42 7fffffff3cac67c502f85982575c8679 619415e58328472200c38d7b3b9fca42 fpscr=00000000
+vcvtp.s32.f64 s7, d31 96be4eafce925f559044d111ba8d9f93 a6de44d23a4e73b992f8fb5b011d2502 00000000ce925f559044d111ba8d9f93 a6de44d23a4e73b992f8fb5b011d2502 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.s32.f64 s7, d31 676616262f94cad32c1e8d868a530e94 e897a10f1e4b8adc6e3426f706e77e21 800000002f94cad32c1e8d868a530e94 e897a10f1e4b8adc6e3426f706e77e21 fpscr=00000000
+vcvtp.s32.f64 s7, d31 268d7e3fd52f52cf82af98614bac951b cb35dc5af4b548c2b2019450a6b26aef 80000000d52f52cf82af98614bac951b cb35dc5af4b548c2b2019450a6b26aef fpscr=00000000
+vcvtp.s32.f64 s7, d31 f544ea690608309ea26fd05e4e6068f6 60a4cf27bc0be3590b050325a315c616 7fffffff0608309ea26fd05e4e6068f6 60a4cf27bc0be3590b050325a315c616 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.s32.f64 s7, d31 b199436cf278acf0b199436cf278acf0 3c041305b05caf3b914ec0a6379abf8b 00000001f278acf0b199436cf278acf0 3c041305b05caf3b914ec0a6379abf8b fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.s32.f64 s7, d31 fd7129aa777cb56cb5698b6716520cbc 7b6104c0e3d36c7f2bc347e566d538e6 7fffffff777cb56cb5698b6716520cbc 7b6104c0e3d36c7f2bc347e566d538e6 fpscr=00000000
+vcvtp.s32.f64 s7, d31 878882ad9d83ab446180bd58262403a0 6ced33cb0dbbb231d209da5de9fea43a 7fffffff9d83ab446180bd58262403a0 6ced33cb0dbbb231d209da5de9fea43a fpscr=00000000
+vcvtp.s32.f64 s7, d31 651c16288ad3f2c68402d4bca84c286b 2a6ab7fb0462cf1b525d9d2f6dcb8449 000000018ad3f2c68402d4bca84c286b 2a6ab7fb0462cf1b525d9d2f6dcb8449 fpscr=00000000
+vcvtp.s32.f64 s7, d31 87656390e733f36caa8814126a144302 ff03f4d66bc675f26d2dec9522b6b269 80000000e733f36caa8814126a144302 ff03f4d66bc675f26d2dec9522b6b269 fpscr=00000000
+vcvtp.s32.f64 s7, d31 a854c1f01cda8df16649b108c805caf0 c42f5523cb52be0e83d7cac3062eec1a 800000001cda8df16649b108c805caf0 c42f5523cb52be0e83d7cac3062eec1a fpscr=00000000
+vcvtp.s32.f64 s7, d31 442c8adf12e015986c45a531c0bf2f5c 9adc2ea71129bbb2d39396add17b174d 0000000012e015986c45a531c0bf2f5c 9adc2ea71129bbb2d39396add17b174d fpscr=00000000
+vcvtp.s32.f64 s7, d31 94bb7049510ec58ed3b8460455068daf 93ee75f0d6c8c7006134051578a6da93 00000000510ec58ed3b8460455068daf 93ee75f0d6c8c7006134051578a6da93 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.s32.f64 s7, d31 411415043b28b99e411415043b28b99e 48e6b61df06bac5a48e6b61df06bac5a 7fffffff3b28b99e411415043b28b99e 48e6b61df06bac5a48e6b61df06bac5a fpscr=00000000
+randV128: 4096 calls, 4223 iters
+vcvtp.s32.f64 s7, d31 967f65c91b16a8a969b1cb61da7e71b5 e7c4c7a46d07dc5f40d03261df6690fa 800000001b16a8a969b1cb61da7e71b5 e7c4c7a46d07dc5f40d03261df6690fa fpscr=00000000
+vcvtp.s32.f64 s7, d31 7c1726373050c19f52b96f7b73ef42ae 9d631e6fc8892ce27eddbf9606c395ef 000000003050c19f52b96f7b73ef42ae 9d631e6fc8892ce27eddbf9606c395ef fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.s32.f64 s7, d31 55f876e0fc51859d5d65e936a712fcb0 617acec489e8d1ec617acec489e8d1ec 7ffffffffc51859d5d65e936a712fcb0 617acec489e8d1ec617acec489e8d1ec fpscr=00000000
+vcvtp.s32.f64 s7, d31 f68cab6d89f1c0c5e73d556d441d76e3 c066e0274f6fc866a6beca9cc795cc9e ffffff4989f1c0c5e73d556d441d76e3 c066e0274f6fc866a6beca9cc795cc9e fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.s32.f64 s7, d31 1f01727fd742ecd81f01727fd742ecd8 d80df47204ebc7bd3d54b96896929f32 80000000d742ecd81f01727fd742ecd8 d80df47204ebc7bd3d54b96896929f32 fpscr=00000000
+vcvtp.s32.f64 s7, d31 4c2099c162bbffa12504e547ce25f73b 02e455c5e09e52215be56eeba3a12d37 0000000162bbffa12504e547ce25f73b 02e455c5e09e52215be56eeba3a12d37 fpscr=00000000
+vcvtp.s32.f64 s7, d31 9f407cbc74609d945f7f0c2cbbe65259 f871565aeafc7ccf23bd6b84cea94a13 8000000074609d945f7f0c2cbbe65259 f871565aeafc7ccf23bd6b84cea94a13 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.s32.f64 s7, d31 1b77c364165584854034fefa894a71eb 2487970eee16170a5a50300d30220294 00000001165584854034fefa894a71eb 2487970eee16170a5a50300d30220294 fpscr=00000000
+vcvtp.s32.f64 s7, d31 ab3333323e52e0e72cf9b4589dd45c0a 907ef51ee33603dd0eb0010b954c9b08 000000003e52e0e72cf9b4589dd45c0a 907ef51ee33603dd0eb0010b954c9b08 fpscr=00000000
+vcvtp.s32.f64 s7, d31 18a923cc928a375228c0a7283c2e412e e04f36988ec84590c87dc0e93470914b 80000000928a375228c0a7283c2e412e e04f36988ec84590c87dc0e93470914b fpscr=00000000
+vcvtp.s32.f64 s7, d31 adb8b2824b9fbe732afc769a6e5bc3d3 368f0e261d5c01ba8adc29948db9a120 000000014b9fbe732afc769a6e5bc3d3 368f0e261d5c01ba8adc29948db9a120 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.s32.f64 s7, d31 4787e447c8569ebe4787e447c8569ebe 53a35bb3b26c2450144c35c88e946419 7fffffffc8569ebe4787e447c8569ebe 53a35bb3b26c2450144c35c88e946419 fpscr=00000000
+vcvtp.s32.f64 s7, d31 86fcdf28d336895295f3204b72fe69c7 d098b6e53cf79a41b11fab67eab009f3 80000000d336895295f3204b72fe69c7 d098b6e53cf79a41b11fab67eab009f3 fpscr=00000000
+vcvtp.s32.f64 s7, d31 b27a3d6af2328f05cedadfe291e01576 16215038f908f7dfd056117b6df6ac32 00000001f2328f05cedadfe291e01576 16215038f908f7dfd056117b6df6ac32 fpscr=00000000
+vcvtp.s32.f64 s7, d31 51081381b366077935e688f4dcdea817 c5feab3e98b82e217c29ed39ee1fa1bf 80000000b366077935e688f4dcdea817 c5feab3e98b82e217c29ed39ee1fa1bf fpscr=00000000
+vcvtp.s32.f64 s7, d31 b3286f9c909d6a0312adb1c9b1f82bd5 f7d583ff357d91e101052081375a7955 80000000909d6a0312adb1c9b1f82bd5 f7d583ff357d91e101052081375a7955 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.s32.f64 s7, d31 144c96d42f319939144c96d42f319939 10c414766c4e4a148accfa19ca713169 000000012f319939144c96d42f319939 10c414766c4e4a148accfa19ca713169 fpscr=00000000
+vcvtp.s32.f64 s7, d31 4f0744bf28d86dd3514cb99e913e3df4 0d9a7b82517f7ac33cbc3f36025df432 0000000128d86dd3514cb99e913e3df4 0d9a7b82517f7ac33cbc3f36025df432 fpscr=00000000
+vcvtp.s32.f64 s7, d31 110327b0da64f42d2e7e0f60f156ec4c 83cf126fd07f45ffff6bb1187a23b79a 00000000da64f42d2e7e0f60f156ec4c 83cf126fd07f45ffff6bb1187a23b79a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.s32.f64 s7, d31 7228dc2e2cdd41047228dc2e2cdd4104 8c05c7de04bab4f179468d77be8aee0b 000000002cdd41047228dc2e2cdd4104 8c05c7de04bab4f179468d77be8aee0b fpscr=00000000
+vcvtp.s32.f64 s7, d31 1a56051d4f125bc05eafaac963df255e 93e28a3e4f6a7fbdecb10d723839d6f2 000000004f125bc05eafaac963df255e 93e28a3e4f6a7fbdecb10d723839d6f2 fpscr=00000000
+vcvtp.s32.f64 s7, d31 07cc42968f5c4e4e08fc0988f2f015c0 7c28ecc1314003b1d6b6a09d1ada01ad 7fffffff8f5c4e4e08fc0988f2f015c0 7c28ecc1314003b1d6b6a09d1ada01ad fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.s32.f64 s7, d31 9471028c104ec7414ae2446b7136403e b8110c713fdf4d59d2fb732b014a0adc 00000000104ec7414ae2446b7136403e b8110c713fdf4d59d2fb732b014a0adc fpscr=00000000
+vcvtp.s32.f64 s7, d31 c9125e5473ba0ab0859ddcc8403bd2e2 da5f74d267f672e0bbc960d47688d8d6 8000000073ba0ab0859ddcc8403bd2e2 da5f74d267f672e0bbc960d47688d8d6 fpscr=00000000
+vcvtp.s32.f64 s7, d31 68566e05471d2f9909b8b0c3c738fd08 a4784e7130e14a9d5e82698eb9cc5923 00000000471d2f9909b8b0c3c738fd08 a4784e7130e14a9d5e82698eb9cc5923 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.s32.f64 s7, d31 ce32cb2d126898c8b94c2d7f1c4d7d19 e4aa2cec61a32f771eee3e6d30a46ebb 80000000126898c8b94c2d7f1c4d7d19 e4aa2cec61a32f771eee3e6d30a46ebb fpscr=00000000
+vcvtp.s32.f64 s7, d31 e72ea1bcbb63c78a30cd2be5e5ecb54a 3a7d925f9216c2ba04e3d222340ffbc7 00000001bb63c78a30cd2be5e5ecb54a 3a7d925f9216c2ba04e3d222340ffbc7 fpscr=00000000
+vcvtm.s32.f64 s1, d0 1d92c1412bfc99e12726111c5108a45b 034104484033928fe107846a99731047 034104484033928f8000000099731047 034104484033928f8000000099731047 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.s32.f64 s1, d0 bac8bd9a2cd4c6361a86b6804999f94b 82fc2929ba1fdc46372c46bce2c56d11 82fc2929ba1fdc4600000000e2c56d11 82fc2929ba1fdc4600000000e2c56d11 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.s32.f64 s1, d0 606a225e77b607fdc88f4574b15c0e9d 64ef986763d8316319b43147fee2e680 64ef986763d8316300000000fee2e680 64ef986763d8316300000000fee2e680 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.s32.f64 s1, d0 b4078322ed417946d3dd04d1a973ea73 b6576ec32cd92b6eb2e5f1ea6c8e5285 b6576ec32cd92b6effffffff6c8e5285 b6576ec32cd92b6effffffff6c8e5285 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.s32.f64 s1, d0 e2548e5b96ae828baf2ab3d0fedbdfba cce882de3aeef708cce882de3aeef708 cce882de3aeef708800000003aeef708 cce882de3aeef708800000003aeef708 fpscr=00000000
+vcvtm.s32.f64 s1, d0 c19ae7f1e98861b3b3eaf3cc9f78b2b1 15bd22b41c0586f2a4e1e393fe12e2da 15bd22b41c0586f2fffffffffe12e2da 15bd22b41c0586f2fffffffffe12e2da fpscr=00000000
+vcvtm.s32.f64 s1, d0 ff1adba464bd8cc4415f3cf59e6829a8 b90f20256bc54eaa89567e7e131330d3 b90f20256bc54eaaffffffff131330d3 b90f20256bc54eaaffffffff131330d3 fpscr=00000000
+vcvtm.s32.f64 s1, d0 8c13863d8543d33dd28a88e375fab08c f63949bf19962cbd7c117dafda7d11db f63949bf19962cbd7fffffffda7d11db f63949bf19962cbd7fffffffda7d11db fpscr=00000000
+vcvtm.s32.f64 s1, d0 58a1eb972ced8dbf83bca0d7ea62bdad 71fb16e9c12e78aec88e6063a5800fa5 71fb16e9c12e78ae80000000a5800fa5 71fb16e9c12e78ae80000000a5800fa5 fpscr=00000000
+vcvtm.s32.f64 s1, d0 f1626aa5c88d8d6ed31ec859dae523d3 73aa5b9e304ce032d2a2548926d61df7 73aa5b9e304ce0328000000026d61df7 73aa5b9e304ce0328000000026d61df7 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.s32.f64 s1, d0 50c258c445d9dfe0ad36a0d26004176a 1e7e10873422d1728b093f2588744030 1e7e10873422d172ffffffff88744030 1e7e10873422d172ffffffff88744030 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.s32.f64 s1, d0 1392a24485998372daaf687a5dd1e47f 715ad6dd03c076fcd6a8372547d5218e 715ad6dd03c076fc8000000047d5218e 715ad6dd03c076fc8000000047d5218e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.s32.f64 s1, d0 c3a891f6bade890ca3abd2924a3a8965 19afb02ba1433daf19afb02ba1433daf 19afb02ba1433daf00000000a1433daf 19afb02ba1433daf00000000a1433daf fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.s32.f64 s1, d0 ec234511393f641359ea68b23c6149dd d9642bfb91844a8c7a8b35348692a2bf d9642bfb91844a8c7fffffff8692a2bf d9642bfb91844a8c7fffffff8692a2bf fpscr=00000000
+vcvtm.s32.f64 s1, d0 c8742673f74843d21010352299033ed4 4b1759a0ab4e2e4c556bdf315622b5c9 4b1759a0ab4e2e4c7fffffff5622b5c9 4b1759a0ab4e2e4c7fffffff5622b5c9 fpscr=00000000
+vcvtm.s32.f64 s1, d0 1edab9963b197ed634c0a3a0fc46ff99 af8583dc6f0b88a29e6dc2a362919c76 af8583dc6f0b88a2ffffffff62919c76 af8583dc6f0b88a2ffffffff62919c76 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.s32.f64 s1, d0 eb7115ffd06033abc6ca73becc4d926d c08cc57a2f0770e4c08cc57a2f0770e4 c08cc57a2f0770e4fffffc672f0770e4 c08cc57a2f0770e4fffffc672f0770e4 fpscr=00000000
+vcvtm.s32.f64 s1, d0 45f940d245de59bdec3c18a8198a49e6 3a4313a17b5f9e122efb975838cf5f43 3a4313a17b5f9e120000000038cf5f43 3a4313a17b5f9e120000000038cf5f43 fpscr=00000000
+vcvtm.s32.f64 s1, d0 7eeb476aa621b50e510ebbe1dce9d612 51b45789eb3489ede2e7eb44078c4756 51b45789eb3489ed80000000078c4756 51b45789eb3489ed80000000078c4756 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.s32.f64 s1, d0 0ea0e3d2cf59bb673cc55b9803b5f03c 7c0d227a20d9358cf85253a2ad8e0601 7c0d227a20d9358c80000000ad8e0601 7c0d227a20d9358c80000000ad8e0601 fpscr=00000000
+vcvtm.s32.f64 s1, d0 7dd2a23f344f2b866101dd66a3097f87 a21a27dc09c20e181eaf2c3301f8ac96 a21a27dc09c20e180000000001f8ac96 a21a27dc09c20e180000000001f8ac96 fpscr=00000000
+vcvtm.s32.f64 s1, d0 f31f89a39565ccf5b927a0ec65cb2553 e81010046b28475378ca6073e7fa7671 e81010046b2847537fffffffe7fa7671 e81010046b2847537fffffffe7fa7671 fpscr=00000000
+vcvtm.s32.f64 s1, d0 65713e4d8f5f6a2347fbb20c8508f9b3 8e51a10114353f62b15dcf0a42003d57 8e51a10114353f62ffffffff42003d57 8e51a10114353f62ffffffff42003d57 fpscr=00000000
+vcvtm.s32.f64 s1, d0 26f0e70407618731f546914a7ce82b95 5903ba41c4873c565990f18fe22ce8e2 5903ba41c4873c567fffffffe22ce8e2 5903ba41c4873c567fffffffe22ce8e2 fpscr=00000000
+vcvtm.s32.f64 s1, d0 9f5915d4582ae35193e8a5706c194dfc 2fe2c1b5fe94c60295eca0de84cf0311 2fe2c1b5fe94c602ffffffff84cf0311 2fe2c1b5fe94c602ffffffff84cf0311 fpscr=00000000
+vcvtm.s32.f64 s1, d0 bd4f579ca22d9d5fdb51a5b41447dc21 d122b24b267ccd8d97afd701d5fd7376 d122b24b267ccd8dffffffffd5fd7376 d122b24b267ccd8dffffffffd5fd7376 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.s32.f64 s1, d0 9916ff1338343f9d15c55a6691c60f8d 563e359285344e1f563e359285344e1f 563e359285344e1f7fffffff85344e1f 563e359285344e1f7fffffff85344e1f fpscr=00000000
+vcvtm.s32.f64 s1, d0 a427038b3c1fa2e859372112aae0d880 09127dc8b80053df38010b4b783d2107 09127dc8b80053df00000000783d2107 09127dc8b80053df00000000783d2107 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.s32.f64 s1, d0 8fe6b996a3ddfbec38eaf64a64c4584a 2599e47cedc77fce923e58d9bc13d938 2599e47cedc77fceffffffffbc13d938 2599e47cedc77fceffffffffbc13d938 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.s32.f64 s1, d0 b7c8ae468c049b06324f6e08fdd3f3a3 a78d5b1afc8797ff511ae441ce1609b4 a78d5b1afc8797ff7fffffffce1609b4 a78d5b1afc8797ff7fffffffce1609b4 fpscr=00000000
+vcvtm.s32.f64 s1, d0 184f60c97f7e409659bbb2b5256442e0 8129df1a84fd7a6b5ab30753d2d45378 8129df1a84fd7a6b7fffffffd2d45378 8129df1a84fd7a6b7fffffffd2d45378 fpscr=00000000
+vcvtm.s32.f64 s1, d0 80b7e4c2568d04d0eb50c38e9ff5fe83 bd38e23a062ab15a956dd3b76b3592cd bd38e23a062ab15affffffff6b3592cd bd38e23a062ab15affffffff6b3592cd fpscr=00000000
+vcvtm.s32.f64 s1, d0 f25d68866a252387b4ff0c4439e01eed f165851470546118b6034ef6ebf50052 f165851470546118ffffffffebf50052 f165851470546118ffffffffebf50052 fpscr=00000000
+vcvtm.s32.f64 s1, d0 78641c28ccc7042471fc157e12045a84 1f3e4cd2fdd9568bf4c66221f09417d0 1f3e4cd2fdd9568b80000000f09417d0 1f3e4cd2fdd9568b80000000f09417d0 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.s32.f64 s1, d0 a131801b769d9907a131801b769d9907 86de1769502951a966145979e000bedb 86de1769502951a97fffffffe000bedb 86de1769502951a97fffffffe000bedb fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.s32.f64 s1, d0 bc1ee4ec2b6735845dabba48eb4abcde 4544809bd5049acdc91b2b96e9dc7387 4544809bd5049acd80000000e9dc7387 4544809bd5049acd80000000e9dc7387 fpscr=00000000
+vcvtm.s32.f64 s1, d0 75441ce7590976fbdca8ebd58521de2c e946b819759bba74cda1f1a3cc3eed58 e946b819759bba7480000000cc3eed58 e946b819759bba7480000000cc3eed58 fpscr=00000000
+randV128: 4352 calls, 4482 iters
+vcvtm.s32.f64 s1, d0 512db92b40210de8d025c250584e6e43 dd9035c25444e5f965fbdc2f4572eb0e dd9035c25444e5f97fffffff4572eb0e dd9035c25444e5f97fffffff4572eb0e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.s32.f64 s1, d0 c19465b1b6f609fac19465b1b6f609fa ca8b039537dad3a4873050bd2c6291e7 ca8b039537dad3a4ffffffff2c6291e7 ca8b039537dad3a4ffffffff2c6291e7 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.s32.f64 s1, d0 3257401ee364704b880c4ba727a2bd83 3f20c5802168fd26494370e199a43e91 3f20c5802168fd267fffffff99a43e91 3f20c5802168fd267fffffff99a43e91 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.s32.f64 s1, d0 26cbfe7da08a4a1926cbfe7da08a4a19 ff01db84810106df88c949fde5744406 ff01db84810106dfffffffffe5744406 ff01db84810106dfffffffffe5744406 fpscr=00000000
+vcvtm.s32.f64 s1, d0 8d9446ab4d1f2020557e1e6dca618937 a68a785e23d1bab966054053f465e5ba a68a785e23d1bab97ffffffff465e5ba a68a785e23d1bab97ffffffff465e5ba fpscr=00000000
+vcvtm.s32.f64 s1, d0 7373365eac70081da3a454f34c11e46f b435723ec0e47ec33c8f78c9aac932a5 b435723ec0e47ec300000000aac932a5 b435723ec0e47ec300000000aac932a5 fpscr=00000000
+vcvtm.s32.f64 s1, d0 2f3db5a8d4545379af382ccd50108ded d711950d04d65e75261b48c3aa1d7496 d711950d04d65e7500000000aa1d7496 d711950d04d65e7500000000aa1d7496 fpscr=00000000
+vcvtm.s32.f64 s1, d0 590efed015c063af68e7efa6764d921b ed424ec4126bceddbb697ce25362fa82 ed424ec4126bceddffffffff5362fa82 ed424ec4126bceddffffffff5362fa82 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.s32.f64 s1, d0 412d553408f8b66c412d553408f8b66c f5a3ce1dbe451a4341aa156048b03a68 f5a3ce1dbe451a430d0ab02448b03a68 f5a3ce1dbe451a430d0ab02448b03a68 fpscr=00000000
+vcvtm.s32.f64 s1, d0 05d6dc0676276a84e2d6f56f430a3712 15e08537189cf9314e675a513fb73a0a 15e08537189cf9317fffffff3fb73a0a 15e08537189cf9317fffffff3fb73a0a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.s32.f64 s1, d0 c99f23f8ca8498c1a332418488d2a91f 287e1851aec1de64f39e2735143700c5 287e1851aec1de6480000000143700c5 287e1851aec1de6480000000143700c5 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.s32.f64 s1, d0 c17da8a3e85b1bcc874e0cf67c793006 ae0f9b872040e3f8ae0f9b872040e3f8 ae0f9b872040e3f8ffffffff2040e3f8 ae0f9b872040e3f8ffffffff2040e3f8 fpscr=00000000
+vcvtm.s32.f64 s1, d0 13851ba938320db269030efc174d4c0d 2fdc34116d0084a6e5a259edf816ae46 2fdc34116d0084a680000000f816ae46 2fdc34116d0084a680000000f816ae46 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtn.s32.f32 s27, s5 8defe539621f9f1863b0f900e8ed86f0 37a27e97159492d5836eb1d620b43465 00000000621f9f1863b0f900e8ed86f0 37a27e97159492d5836eb1d620b43465 fpscr=00000000
+vcvtn.s32.f32 s27, s5 be8f2f957eab9b1088813bdb40cb2a6d 97e3350e4683a435fe703a92b45cf7fe 800000007eab9b1088813bdb40cb2a6d 97e3350e4683a435fe703a92b45cf7fe fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.s32.f32 s27, s5 d1856c45aa21c423d1856c45636b0051 a07a0416110534706050381697d5314f 7fffffffaa21c423d1856c45636b0051 a07a0416110534706050381697d5314f fpscr=00000000
+vcvtn.s32.f32 s27, s5 ed0352190d614eac9d1262bd6104d799 73aacf702477dfd80f212e415fc8de29 000000000d614eac9d1262bd6104d799 73aacf702477dfd80f212e415fc8de29 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtn.s32.f32 s27, s5 4ff7c62025bba7d64ff7c620c2691f99 8dfe8e3ef40ade7ea41223a95aa7ba2e 0000000025bba7d64ff7c620c2691f99 8dfe8e3ef40ade7ea41223a95aa7ba2e fpscr=00000000
+vcvtn.s32.f32 s27, s5 697578b920499a626b38c5f2de39aead d92e89a3b8e6d8b8b1cfd058b6d175aa 0000000020499a626b38c5f2de39aead d92e89a3b8e6d8b8b1cfd058b6d175aa fpscr=00000000
+vcvtn.s32.f32 s27, s5 4aa5d5601df01425c229e32656aa0e77 5b8692565d16e774e132db275e739e92 800000001df01425c229e32656aa0e77 5b8692565d16e774e132db275e739e92 fpscr=00000000
+vcvtn.s32.f32 s27, s5 55298bfcda938aef240a6476516b6941 e5542363d2c4d3bcaca89c90e64279eb 00000000da938aef240a6476516b6941 e5542363d2c4d3bcaca89c90e64279eb fpscr=00000000
+vcvtn.s32.f32 s27, s5 77906503d54fa4f0e31f28b1dda5c88c f6834ff786930382c152e923a6458957 fffffff3d54fa4f0e31f28b1dda5c88c f6834ff786930382c152e923a6458957 fpscr=00000000
+vcvtn.s32.f32 s27, s5 4c8f2a073101f4bd53f13c45c5290f86 ae84865378255a3a2d2817b90a90b5eb 000000003101f4bd53f13c45c5290f86 ae84865378255a3a2d2817b90a90b5eb fpscr=00000000
+vcvtn.s32.f32 s27, s5 df17751b1e8c68e3ceacf8e530efb3db 948f2d2523fff4cb6e82d60bbc743f67 7fffffff1e8c68e3ceacf8e530efb3db 948f2d2523fff4cb6e82d60bbc743f67 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtn.s32.f32 s27, s5 d65aed259eef21551961711c1961711c 914983cd4a4f223b50d1c6e85cfcf2a6 7fffffff9eef21551961711c1961711c 914983cd4a4f223b50d1c6e85cfcf2a6 fpscr=00000000
+vcvtn.s32.f32 s27, s5 dc604538f3a5d50eae4aaab82e1d4dba 33e53f0e19e5139bbc1c19c5fcbcec44 00000000f3a5d50eae4aaab82e1d4dba 33e53f0e19e5139bbc1c19c5fcbcec44 fpscr=00000000
+vcvtn.s32.f32 s27, s5 af809995fe1e07cdc6b78e925deefe24 e1cecdf55d4fc4f8ae36ed2e2c177d7e 00000000fe1e07cdc6b78e925deefe24 e1cecdf55d4fc4f8ae36ed2e2c177d7e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtn.s32.f32 s27, s5 a12cc7a70a624855c30b4c57d5bb547c 4d175e8ad62b258961b330fd309bf0e7 7fffffff0a624855c30b4c57d5bb547c 4d175e8ad62b258961b330fd309bf0e7 fpscr=00000000
+vcvtn.s32.f32 s27, s5 7e7e75fe25881907ff662e72b0598a09 739deabf51c9d6e1573d5428e3ee2171 7fffffff25881907ff662e72b0598a09 739deabf51c9d6e1573d5428e3ee2171 fpscr=00000000
+vcvtn.s32.f32 s27, s5 857bea41da7a23f54935dfee86957a90 2a9ad69bed8e4c298655755214d73b25 00000000da7a23f54935dfee86957a90 2a9ad69bed8e4c298655755214d73b25 fpscr=00000000
+vcvtn.s32.f32 s27, s5 b96b8312ad507ea5710205b6b16154c1 c9d8aa9a01f5b5eca654339fbc3e0cca 00000000ad507ea5710205b6b16154c1 c9d8aa9a01f5b5eca654339fbc3e0cca fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtn.s32.f32 s27, s5 e479a85a42c3a142c7808c71a4f77c21 3ca32a6c6209e890155a670f7f4c7e82 0000000042c3a142c7808c71a4f77c21 3ca32a6c6209e890155a670f7f4c7e82 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtn.s32.f32 s27, s5 6558d80e32afa89d4ca3d225df5832eb ed483065ce874addc79917da277d4729 fffecdd032afa89d4ca3d225df5832eb ed483065ce874addc79917da277d4729 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtn.s32.f32 s27, s5 ab47c377c0c34d1057c40d2be958162f 55ea02bc317d348b9400c7b432ad7244 00000000c0c34d1057c40d2be958162f 55ea02bc317d348b9400c7b432ad7244 fpscr=00000000
+vcvtn.s32.f32 s27, s5 196f87bd46d3720dce53db27c186812d 43be33f113ccdf684510ab716e0fda57 0000090b46d3720dce53db27c186812d 43be33f113ccdf684510ab716e0fda57 fpscr=00000000
+vcvtn.s32.f32 s27, s5 5378d36352a359919d0f8c76969ccaa8 bb7a6503de1830b498dac4872dbf754f 0000000052a359919d0f8c76969ccaa8 bb7a6503de1830b498dac4872dbf754f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtn.s32.f32 s27, s5 6394e4f0e7ed500b950ed62118c45c8e f218d2eaf28a71cf9cd41cbbd2e55b73 00000000e7ed500b950ed62118c45c8e f218d2eaf28a71cf9cd41cbbd2e55b73 fpscr=00000000
+vcvtn.s32.f32 s27, s5 66a24d838d525fe591c62b172f3d4291 e285157623b99480841b7a216c155c53 000000008d525fe591c62b172f3d4291 e285157623b99480841b7a216c155c53 fpscr=00000000
+vcvtn.s32.f32 s27, s5 34fff44414e6701e344e104bb5d580d7 9585c82f6d13f1105d7396f6025c32a1 7fffffff14e6701e344e104bb5d580d7 9585c82f6d13f1105d7396f6025c32a1 fpscr=00000000
+vcvtn.s32.f32 s27, s5 0dfb6aab8d661840257fb00ac812d8a5 f35e71605afb8a6a409c1a9e2031d6db 000000058d661840257fb00ac812d8a5 f35e71605afb8a6a409c1a9e2031d6db fpscr=00000000
+vcvtn.s32.f32 s27, s5 55358ee18db6daaf7f6f1dacfa4d6d29 d09566d01f1082a2e52367df3b817081 800000008db6daaf7f6f1dacfa4d6d29 d09566d01f1082a2e52367df3b817081 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtn.s32.f32 s27, s5 20d317c63e936f033c4153216afb6668 4a79fe736e8a5cc46e8a5cc4155b3eef 7fffffff3e936f033c4153216afb6668 4a79fe736e8a5cc46e8a5cc4155b3eef fpscr=00000000
+vcvtn.s32.f32 s27, s5 2cdf27cc06f1fa28dc23c3674dd0df70 492d53fb65717c51e11a44aa4ce68fbe 8000000006f1fa28dc23c3674dd0df70 492d53fb65717c51e11a44aa4ce68fbe fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtn.s32.f32 s27, s5 4a85eff954eb2ae8815e5eda1240e213 925be8738cb7dccd8cb7dccdf9ce4f2e 0000000054eb2ae8815e5eda1240e213 925be8738cb7dccd8cb7dccdf9ce4f2e fpscr=00000000
+vcvtn.s32.f32 s27, s5 4770f6ff5ed0ac93c6f464602d4a2e66 5ba1073dc5aef06b864b4bc0c67794b8 000000005ed0ac93c6f464602d4a2e66 5ba1073dc5aef06b864b4bc0c67794b8 fpscr=00000000
+vcvtn.s32.f32 s27, s5 5a49aaaabe27f1349a256b97a393bc1e 4e75eb00cfebc10cd63588f1938166a8 80000000be27f1349a256b97a393bc1e 4e75eb00cfebc10cd63588f1938166a8 fpscr=00000000
+vcvtn.s32.f32 s27, s5 75bdd03dd53ba58a08fe20cd435be872 263dbed7bd3d504c8f6053a744003a4c 00000000d53ba58a08fe20cd435be872 263dbed7bd3d504c8f6053a744003a4c fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[1]
+vcvtn.s32.f32 s27, s5 6fe6dc798830978a494b091c83d5e2ac 25d60a1a48af0b4525d60a1a795f9d6d 000000008830978a494b091c83d5e2ac 25d60a1a48af0b4525d60a1a795f9d6d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[3]
+vcvtn.s32.f32 s27, s5 4a669ffb0113199ebeb6e36c0113199e 5bff3a5ef94a26d7c2fd81ab34c95d11 ffffff810113199ebeb6e36c0113199e 5bff3a5ef94a26d7c2fd81ab34c95d11 fpscr=00000000
+vcvtn.s32.f32 s27, s5 c133028e99ff75a04760f802b94e7dd8 188ff1fa57040f6286983ceed567477b 0000000099ff75a04760f802b94e7dd8 188ff1fa57040f6286983ceed567477b fpscr=00000000
+vcvtn.s32.f32 s27, s5 b010fb66bb06d6918e5589a89bf342fe 1ece11398920f53dd14382b3fec10f5b 80000000bb06d6918e5589a89bf342fe 1ece11398920f53dd14382b3fec10f5b fpscr=00000000
+vcvtn.s32.f32 s27, s5 3954f09d12fcdd50f88fa74650d29404 586fc755308670aba38da55435679452 0000000012fcdd50f88fa74650d29404 586fc755308670aba38da55435679452 fpscr=00000000
+vcvtn.s32.f32 s27, s5 d124a0f261ea0e75eeea820bd9acd48d 0d86707495814c3c67cf4a374436e39f 7fffffff61ea0e75eeea820bd9acd48d 0d86707495814c3c67cf4a374436e39f fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtn.s32.f32 s27, s5 798d7f3be014fc2e98b0141ca3bb4975 32cec9c8d26d836b573bfae3a40a7f3e 7fffffffe014fc2e98b0141ca3bb4975 32cec9c8d26d836b573bfae3a40a7f3e fpscr=00000000
+vcvtn.s32.f32 s27, s5 aac796ef1f9eb884539df542c7163e87 0fd302fdd97688ab4e205a724c287dfd 28169c801f9eb884539df542c7163e87 0fd302fdd97688ab4e205a724c287dfd fpscr=00000000
+vcvtn.s32.f32 s27, s5 0ce6254ff2afd37a3a1753a87c696f8f f7687e7bc4e17ff61597bd7bf8a483f5 00000000f2afd37a3a1753a87c696f8f f7687e7bc4e17ff61597bd7bf8a483f5 fpscr=00000000
+vcvtn.s32.f32 s27, s5 2c99cb76774a271c39a9da18c5abb39f ee97411ab5f00b0ef62d114a6e579381 80000000774a271c39a9da18c5abb39f ee97411ab5f00b0ef62d114a6e579381 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtn.s32.f32 s27, s5 95fd52358391782c95fd523585075d75 638ccd747cab3007e1b008fdf0c1ebb2 800000008391782c95fd523585075d75 638ccd747cab3007e1b008fdf0c1ebb2 fpscr=00000000
+vcvtn.s32.f32 s27, s5 534e255948e6b840c65f5b41acf04231 9099b35166958d37327009ce79ea3bcc 0000000048e6b840c65f5b41acf04231 9099b35166958d37327009ce79ea3bcc fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtn.s32.f32 s27, s5 5838e180949d48f628aedfc5fe18d685 15f56df902dd901fb2ff738b634f69d2 00000000949d48f628aedfc5fe18d685 15f56df902dd901fb2ff738b634f69d2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtn.s32.f32 s27, s5 d0efa931702f5bdf9be7e3b87ac3f143 414f8d605d54fc64c14b4b87f1942629 fffffff3702f5bdf9be7e3b87ac3f143 414f8d605d54fc64c14b4b87f1942629 fpscr=00000000
+vcvtn.s32.f32 s27, s5 f7b610a4733167b6dd410b0d52105b8c 0cd729b4cd7430494d01324c299fd8bb 081324c0733167b6dd410b0d52105b8c 0cd729b4cd7430494d01324c299fd8bb fpscr=00000000
+vcvtn.s32.f32 s27, s5 0790a8e28dbef40a3ec9b0984c790018 847186b6944e557008c61c0da136e737 000000008dbef40a3ec9b0984c790018 847186b6944e557008c61c0da136e737 fpscr=00000000
+vcvta.s32.f32 s4, s20 5c5c76d0fbca73f0aaeb9f39e9060974 174121ce178f63270aa45e8c05d0e6fa 5c5c76d0fbca73f0aaeb9f3900000000 174121ce178f63270aa45e8c05d0e6fa fpscr=00000000
+randV128: 4608 calls, 4743 iters
+vcvta.s32.f32 s4, s20 f36e7080d570680bdb667b54ad1b7112 5391642370c5500b8671dbee4f372267 f36e7080d570680bdb667b547fffffff 5391642370c5500b8671dbee4f372267 fpscr=00000000
+vcvta.s32.f32 s4, s20 482455c8ec3194cc7454b8f5b278cc69 8915ec12e996b7a8b53c4765952bc912 482455c8ec3194cc7454b8f500000000 8915ec12e996b7a8b53c4765952bc912 fpscr=00000000
+vcvta.s32.f32 s4, s20 96bc76513aec2361df827ad6024d37e9 469029844994204006395a5e2758111d 96bc76513aec2361df827ad600000000 469029844994204006395a5e2758111d fpscr=00000000
+vcvta.s32.f32 s4, s20 57fe85c5766c4da4136904710ae2f6a2 ef17ac0d40094ffaae71623a330ee6e3 57fe85c5766c4da41369047100000000 ef17ac0d40094ffaae71623a330ee6e3 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvta.s32.f32 s4, s20 fccf5413913533dc35ce69fa198e13e0 9906c22ed6ed7a25d5c53b37ce5c035d fccf5413913533dc35ce69fac8ff28c0 9906c22ed6ed7a25d5c53b37ce5c035d fpscr=00000000
+vcvta.s32.f32 s4, s20 e793a53cadc6e8e12ea127ae4e2adaa3 d191bffa187e033fafd770bd042d6754 e793a53cadc6e8e12ea127ae00000000 d191bffa187e033fafd770bd042d6754 fpscr=00000000
+vcvta.s32.f32 s4, s20 9db18b84cf07069af5faffd3dc708a41 b91fb0a7b8b8aa31f5391c7b9801c8aa 9db18b84cf07069af5faffd300000000 b91fb0a7b8b8aa31f5391c7b9801c8aa fpscr=00000000
+vcvta.s32.f32 s4, s20 1bb1602ac83fc47c994f04c9ab76ad38 dca2ba4e92c67958665b63dddc79f4a5 1bb1602ac83fc47c994f04c980000000 dca2ba4e92c67958665b63dddc79f4a5 fpscr=00000000
+vcvta.s32.f32 s4, s20 9e6a1dcf840b3ee10bf05f63a74dfeab 057b6dcd539e4b5db09fddc3bcd9c95d 9e6a1dcf840b3ee10bf05f6300000000 057b6dcd539e4b5db09fddc3bcd9c95d fpscr=00000000
+vcvta.s32.f32 s4, s20 ca4dd6b095e64d766ee225cdf409bd48 a343637f0de8b7e0e740691ff9793234 ca4dd6b095e64d766ee225cd80000000 a343637f0de8b7e0e740691ff9793234 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvta.s32.f32 s4, s20 275970189de70be5080e04860dcd28fd 0b0babec63d1698964d6bd18a7137d87 275970189de70be5080e048600000000 0b0babec63d1698964d6bd18a7137d87 fpscr=00000000
+vcvta.s32.f32 s4, s20 c0a4009c3972b082a532af169bcf60be 95aafa8f4ac35acbcb978f24df02d341 c0a4009c3972b082a532af1680000000 95aafa8f4ac35acbcb978f24df02d341 fpscr=00000000
+vcvta.s32.f32 s4, s20 0179c920e62813192acf852e8083e4f4 e249856f18eaab2fc6590813e8f90e4c 0179c920e62813192acf852e80000000 e249856f18eaab2fc6590813e8f90e4c fpscr=00000000
+vcvta.s32.f32 s4, s20 b5ef157c83138d8d1a145d2913e5eaf1 20c1eb8e88cb58c9c5503b5e8e7f67c3 b5ef157c83138d8d1a145d2900000000 20c1eb8e88cb58c9c5503b5e8e7f67c3 fpscr=00000000
+vcvta.s32.f32 s4, s20 94573cec2a14e173e983eeccba463ead 81523a53a8740c92f5c9f8987b3b897b 94573cec2a14e173e983eecc7fffffff 81523a53a8740c92f5c9f8987b3b897b fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.s32.f32 s4, s20 92a74bbdf8b8dd93b95c105992a74bbd 93063e8af04b970992e57557c7500aa2 92a74bbdf8b8dd93b95c1059ffff2ff5 93063e8af04b970992e57557c7500aa2 fpscr=00000000
+vcvta.s32.f32 s4, s20 cdfd28a7b61e128521e4006e0c690728 31f0a2b05e400ab15e6107a7510733d8 cdfd28a7b61e128521e4006e7fffffff 31f0a2b05e400ab15e6107a7510733d8 fpscr=00000000
+vcvta.s32.f32 s4, s20 adfc8b61338e7bad66647e99dcaf2826 150465274fe2f558b0f5e7c95ff4f56a adfc8b61338e7bad66647e997fffffff 150465274fe2f558b0f5e7c95ff4f56a fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.s32.f32 s4, s20 a59af3305bcf5f40eb5aa8f911f7de37 205d4cc1623255ea8a3dfb33023e08ad a59af3305bcf5f40eb5aa8f900000000 205d4cc1623255ea8a3dfb33023e08ad fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvta.s32.f32 s4, s20 a0347b4fbe88d3d6a2166f8ab2e55541 5efa315a5efa315ab992ac602605c362 a0347b4fbe88d3d6a2166f8a00000000 5efa315a5efa315ab992ac602605c362 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvta.s32.f32 s4, s20 edb7d8dab09fff260a9a5b6fdf89d81f 7722926319b1a8dad25e2602fb4c1440 edb7d8dab09fff260a9a5b6f80000000 7722926319b1a8dad25e2602fb4c1440 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.s32.f32 s4, s20 cd60933f2db239eac4af87fdb1b74dca eef04722eef0472287bc00fa86d8bf2d cd60933f2db239eac4af87fd00000000 eef04722eef0472287bc00fa86d8bf2d fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvta.s32.f32 s4, s20 440ee0e3a82bbd3e9018b830a49d2822 bdbe8058475439b0477bde7111cff665 440ee0e3a82bbd3e9018b83000000000 bdbe8058475439b0477bde7111cff665 fpscr=00000000
+vcvta.s32.f32 s4, s20 d13c19bdbe31f022521f2d293176a280 2054fa535581401161dcfc3c19ccd801 d13c19bdbe31f022521f2d2900000000 2054fa535581401161dcfc3c19ccd801 fpscr=00000000
+vcvta.s32.f32 s4, s20 a5dc15f2e87bdabd283a5da18e531ea4 e6ba1df7626f90713f56923d25826127 a5dc15f2e87bdabd283a5da100000000 e6ba1df7626f90713f56923d25826127 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.s32.f32 s4, s20 ab5675189a3116b715ae73d702b9eb6a 01c67cc3397491a3e3f9d3fe397491a3 ab5675189a3116b715ae73d700000000 01c67cc3397491a3e3f9d3fe397491a3 fpscr=00000000
+vcvta.s32.f32 s4, s20 5b24391ea2d7b6bb86f70bb96522b8b5 cd9e255ede913f81b025071460348351 5b24391ea2d7b6bb86f70bb97fffffff cd9e255ede913f81b025071460348351 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.s32.f32 s4, s20 ca22d7dce7e007199a840370bbeb5952 eb5ed66dd81777d6d81777d6ec41bba0 ca22d7dce7e007199a84037080000000 eb5ed66dd81777d6d81777d6ec41bba0 fpscr=00000000
+vcvta.s32.f32 s4, s20 250f7a5c40cc86a0ec62034d3e63ec93 96d5bf9f796dc312173c22f3640d570e 250f7a5c40cc86a0ec62034d7fffffff 96d5bf9f796dc312173c22f3640d570e fpscr=00000000
+vcvta.s32.f32 s4, s20 a53dd659cffb2dca5520c7ddef150d4b 5635ec203e4c4f111526dd638e52b239 a53dd659cffb2dca5520c7dd00000000 5635ec203e4c4f111526dd638e52b239 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.s32.f32 s4, s20 0e0666c73e5eedb9338ebce43e5eedb9 db34d8545cd1f1b54cf6f9d63ff5568b 0e0666c73e5eedb9338ebce400000002 db34d8545cd1f1b54cf6f9d63ff5568b fpscr=00000000
+vcvta.s32.f32 s4, s20 6d0974a7d270ae1cfc565ea2d0fedaf6 bfc596f59de8d0c00a6c9ce7a6af1016 6d0974a7d270ae1cfc565ea200000000 bfc596f59de8d0c00a6c9ce7a6af1016 fpscr=00000000
+vcvta.s32.f32 s4, s20 c9009bcabd05fc28a0c09946da76c8fe d3a28f811fa2440f3d221b5749ac776f c9009bcabd05fc28a0c0994600158eee d3a28f811fa2440f3d221b5749ac776f fpscr=00000000
+vcvta.s32.f32 s4, s20 5d14f6bbf578b58c784f47a909e61e1a 0a8faefafddc16c26b5d157c2c0fe29d 5d14f6bbf578b58c784f47a900000000 0a8faefafddc16c26b5d157c2c0fe29d fpscr=00000000
+vcvta.s32.f32 s4, s20 53c2515d78c59ea29f258e2eaa2d8125 b68432e5822a5de93ef28fdbf220a666 53c2515d78c59ea29f258e2e80000000 b68432e5822a5de93ef28fdbf220a666 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvta.s32.f32 s4, s20 949f9e0cf94535b087b23896949f9e0c 1c1070c5d727b8efd4c715b22003a5e7 949f9e0cf94535b087b2389600000000 1c1070c5d727b8efd4c715b22003a5e7 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.s32.f32 s4, s20 26919b8dd20e99610462e3ca28e76c3c a9ef1002e53f7009f2bb8c14d1722306 26919b8dd20e99610462e3ca80000000 a9ef1002e53f7009f2bb8c14d1722306 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.s32.f32 s4, s20 d488c40d08643462eed16f640f4b78d1 f179b83d558cf1bacac8543258b60d95 d488c40d08643462eed16f647fffffff f179b83d558cf1bacac8543258b60d95 fpscr=00000000
+vcvta.s32.f32 s4, s20 c988ac89952710599e3396a40b79bfc4 cd9aaacd18293a3ec7ec28f84686e184 c988ac89952710599e3396a400004371 cd9aaacd18293a3ec7ec28f84686e184 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.s32.f32 s4, s20 35b517a535b517a59baea6a5e0f39279 ac4e49f2afc259e9aa51ac948dd6a8bb 35b517a535b517a59baea6a500000000 ac4e49f2afc259e9aa51ac948dd6a8bb fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.s32.f32 s4, s20 20bc8ac9e094a5a76147623df2228787 b06b7e104a31d0169704045449d5371c 20bc8ac9e094a5a76147623d001aa6e4 b06b7e104a31d0169704045449d5371c fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvta.s32.f32 s4, s20 1b4db7163b1ba2cffe6239561b4db716 49633be1b0a68ab8ebe2b71800ea7330 1b4db7163b1ba2cffe62395600000000 49633be1b0a68ab8ebe2b71800ea7330 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvta.s32.f32 s4, s20 3b872c4ccb889635fde561b7067e4efb 990c1aa8990c1aa8c6325fe95c6000b0 3b872c4ccb889635fde561b77fffffff 990c1aa8990c1aa8c6325fe95c6000b0 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.s32.f32 s4, s20 b4bed5ea1342e5e706001c50a67afba3 e71f9da7249848ff967f868767b67332 b4bed5ea1342e5e706001c507fffffff e71f9da7249848ff967f868767b67332 fpscr=00000000
+vcvta.s32.f32 s4, s20 b481eb16866ff7701fd521c3c6f39cd9 a1812fdbfa03379b4b09df3cc2e2ab3f b481eb16866ff7701fd521c3ffffff8f a1812fdbfa03379b4b09df3cc2e2ab3f fpscr=00000000
+vcvta.s32.f32 s4, s20 946494b472c9270f0e6994d31f21baae 8c54617b0da72fbb1d5a8c0d99f4ea4a 946494b472c9270f0e6994d300000000 8c54617b0da72fbb1d5a8c0d99f4ea4a fpscr=00000000
+vcvta.s32.f32 s4, s20 b39fdd1d388cd2bbfd7758cbd49e4667 0fb29b763b49af9d854b6cfbe8e9459f b39fdd1d388cd2bbfd7758cb80000000 0fb29b763b49af9d854b6cfbe8e9459f fpscr=00000000
+vcvta.s32.f32 s4, s20 3e63396d9339c145b2d5eaebe951c5b1 b29f94ab1b8192fe9d6ffd5243bb6b58 3e63396d9339c145b2d5eaeb00000177 b29f94ab1b8192fe9d6ffd5243bb6b58 fpscr=00000000
+vcvta.s32.f32 s4, s20 580d3280b9c53945f29a568865465c47 3b57a404fa3b5ac507a8874e91282bfa 580d3280b9c53945f29a568800000000 3b57a404fa3b5ac507a8874e91282bfa fpscr=00000000
+vcvtp.s32.f32 s7, s31 d418f60c8130ea0fbb4a01e533a1fdc6 79a2a4459feaaba232b6fb3eb5875bc8 7fffffff8130ea0fbb4a01e533a1fdc6 79a2a4459feaaba232b6fb3eb5875bc8 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.s32.f32 s7, s31 7f35889a0ce9b3eb8c80df424b95386f 913498ddf2c13f055dce1ecae7e22e1e 000000000ce9b3eb8c80df424b95386f 913498ddf2c13f055dce1ecae7e22e1e fpscr=00000000
+vcvtp.s32.f32 s7, s31 1e330ad2f354134f8560973fad66dcbd f7475480bb8fe360621345406bb0ceb1 80000000f354134f8560973fad66dcbd f7475480bb8fe360621345406bb0ceb1 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[0]
+vcvtp.s32.f32 s7, s31 61212ddceb66fdfe9a89f6b4b43707fd 727013547dbcc13f7dbcc13f5b53c37d 7fffffffeb66fdfe9a89f6b4b43707fd 727013547dbcc13f7dbcc13f5b53c37d fpscr=00000000
+vcvtp.s32.f32 s7, s31 e8e83a3b601c9d2dc2781e402b26d7e1 c49fb86cb91a634d64308a1d98dbd35d fffffb03601c9d2dc2781e402b26d7e1 c49fb86cb91a634d64308a1d98dbd35d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtp.s32.f32 s7, s31 84ebbbd1a76151651bad81a1b33264c1 fbaa6128cd5c0c211c6452cc3038fc33 80000000a76151651bad81a1b33264c1 fbaa6128cd5c0c211c6452cc3038fc33 fpscr=00000000
+vcvtp.s32.f32 s7, s31 663668c9760b966737f5f2aa583765d8 25dd861476667adaa677fb5cc8c0ff73 00000001760b966737f5f2aa583765d8 25dd861476667adaa677fb5cc8c0ff73 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtp.s32.f32 s7, s31 27c229a4fad79f52c623f3aab247a822 6e406f276a5b45818df5868cc83db081 7ffffffffad79f52c623f3aab247a822 6e406f276a5b45818df5868cc83db081 fpscr=00000000
+vcvtp.s32.f32 s7, s31 a028594ba9f537c565c76a72bff6034f 9bf23182fbae2116aa27392c568d5768 00000000a9f537c565c76a72bff6034f 9bf23182fbae2116aa27392c568d5768 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtp.s32.f32 s7, s31 1a349fc3f626ad2db527d069b527d069 42c6538bb254ba5c052fc606f46c5dc4 00000064f626ad2db527d069b527d069 42c6538bb254ba5c052fc606f46c5dc4 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtp.s32.f32 s7, s31 23e8e0f247ee06857cb46d2117b58540 8190aec1a50ce4028190aec1ee6a8eda 0000000047ee06857cb46d2117b58540 8190aec1a50ce4028190aec1ee6a8eda fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.s32.f32 s7, s31 1c4d14b50a771bac5a9c513632a9deb2 e32a061c9bf76af327b5c9be9bf76af3 800000000a771bac5a9c513632a9deb2 e32a061c9bf76af327b5c9be9bf76af3 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtp.s32.f32 s7, s31 34081150aeb033810d9b76e834081150 dd6a4c029b76fe83c7cb9e73c7c4296f 80000000aeb033810d9b76e834081150 dd6a4c029b76fe83c7cb9e73c7c4296f fpscr=00000000
+vcvtp.s32.f32 s7, s31 6620e4cadfd5e2d6b7e9c62144ea349e 1af21a7172a2c21f85d61625289d8472 00000001dfd5e2d6b7e9c62144ea349e 1af21a7172a2c21f85d61625289d8472 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtp.s32.f32 s7, s31 8117f7e2bbae32b4d47d14d04ea3fa95 3f3b7e62b18652dc0f4831bfb18652dc 00000001bbae32b4d47d14d04ea3fa95 3f3b7e62b18652dc0f4831bfb18652dc fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[2]
+randV128: 4864 calls, 5008 iters
+vcvtp.s32.f32 s7, s31 c180651287de57b7e391a534392ee066 8fe0143cf1398f91903333688fe0143c 0000000087de57b7e391a534392ee066 8fe0143cf1398f91903333688fe0143c fpscr=00000000
+vcvtp.s32.f32 s7, s31 c3f5768101e25e7c075155b408f3ffc5 33012022bed81664d12fcafd6c2a52f0 0000000101e25e7c075155b408f3ffc5 33012022bed81664d12fcafd6c2a52f0 fpscr=00000000
+vcvtp.s32.f32 s7, s31 c7ea39a6f1058fc392d88e187084349b 45927bef98a25b9193a13efa024bcd4c 00001250f1058fc392d88e187084349b 45927bef98a25b9193a13efa024bcd4c fpscr=00000000
+vcvtp.s32.f32 s7, s31 e3eb2253f2b74d699fc494b37557ac2d c2c88b8f849a5bf75c3a9ca4aeb2c5b7 ffffff9cf2b74d699fc494b37557ac2d c2c88b8f849a5bf75c3a9ca4aeb2c5b7 fpscr=00000000
+vcvtp.s32.f32 s7, s31 ed0d7978d583608089180ad1ab9164b3 579a578041bcb95af708a8e2dca9443b 7fffffffd583608089180ad1ab9164b3 579a578041bcb95af708a8e2dca9443b fpscr=00000000
+vcvtp.s32.f32 s7, s31 cfb2353b3176207d01f5e6a86d6d503e b50a0226e23beec52a621925fcbac18e 000000003176207d01f5e6a86d6d503e b50a0226e23beec52a621925fcbac18e fpscr=00000000
+vcvtp.s32.f32 s7, s31 9207dc958c47746d5d5f8e3349a1942b 0dadd927df37f7086dbdde07db9c0bcf 000000018c47746d5d5f8e3349a1942b 0dadd927df37f7086dbdde07db9c0bcf fpscr=00000000
+vcvtp.s32.f32 s7, s31 48ef3a426ed9ac8ec061d6665228a2fb e321b3ad8e46551bfe54cac756ff8627 800000006ed9ac8ec061d6665228a2fb e321b3ad8e46551bfe54cac756ff8627 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.s32.f32 s7, s31 e347051b472645434b633d864b633d86 28374355bc80f9e076535abb95a8723f 00000001472645434b633d864b633d86 28374355bc80f9e076535abb95a8723f fpscr=00000000
+vcvtp.s32.f32 s7, s31 b09cd98d57c847808169790fcf56b5a2 122b5ab8970713b47a86104a4230d1ed 0000000157c847808169790fcf56b5a2 122b5ab8970713b47a86104a4230d1ed fpscr=00000000
+vcvtp.s32.f32 s7, s31 2554bce311db033be9100c927a00be0b 7d986949e3254dcf5c0bf96de943893f 7fffffff11db033be9100c927a00be0b 7d986949e3254dcf5c0bf96de943893f fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtp.s32.f32 s7, s31 95c29e7b124208b1ac909b48d73812db a3e71e8328f691afa3e71e83d723585e 00000000124208b1ac909b48d73812db a3e71e8328f691afa3e71e83d723585e fpscr=00000000
+vcvtp.s32.f32 s7, s31 94692f8d68575d1e49a7d7fbb1c36119 6c282ff2472f166f912b56e41c6a1b50 7fffffff68575d1e49a7d7fbb1c36119 6c282ff2472f166f912b56e41c6a1b50 fpscr=00000000
+vcvtp.s32.f32 s7, s31 2156406bea0a2cda814b30859d776642 a1fa7b711111ab50f48380b3cfd74f3a 00000000ea0a2cda814b30859d776642 a1fa7b711111ab50f48380b3cfd74f3a fpscr=00000000
+vcvtp.s32.f32 s7, s31 aae9d412ba5bc1342eea572dea38540a 5b61d3288b61fe267075161ef5373cff 7fffffffba5bc1342eea572dea38540a 5b61d3288b61fe267075161ef5373cff fpscr=00000000
+vcvtp.s32.f32 s7, s31 13a18bdbee5d696f704d562896a911cd 7f339dbaa890e972147c66c83116d7d2 7fffffffee5d696f704d562896a911cd 7f339dbaa890e972147c66c83116d7d2 fpscr=00000000
+vcvtp.s32.f32 s7, s31 0e6b4354f477883693a9326e1eab93b6 37746cb7b35458afb9ccfba01ef6a50d 00000001f477883693a9326e1eab93b6 37746cb7b35458afb9ccfba01ef6a50d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.s32.f32 s7, s31 2b0243cabed66376e539d48afb0b8e7d 194687c2ab7779afab7779af2ab7fe6c 00000001bed66376e539d48afb0b8e7d 194687c2ab7779afab7779af2ab7fe6c fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtp.s32.f32 s7, s31 e7ac39c3a3fd57cba3fd57cbf2f632dc 07c1dfb6a1ae7a9557a34a4f5cfab63b 00000001a3fd57cba3fd57cbf2f632dc 07c1dfb6a1ae7a9557a34a4f5cfab63b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.s32.f32 s7, s31 c710b81fd883389f2faa24fc5b6006f0 92fdf21229fb44e8d62638d418907031 00000000d883389f2faa24fc5b6006f0 92fdf21229fb44e8d62638d418907031 fpscr=00000000
+vcvtp.s32.f32 s7, s31 2b8fb7baec5947f3c6b6db5ad72b8261 1f89d40d6c9fee66824c1b6a19c2790c 00000001ec5947f3c6b6db5ad72b8261 1f89d40d6c9fee66824c1b6a19c2790c fpscr=00000000
+vcvtp.s32.f32 s7, s31 f4dd009a9edf1ba099667358d70a866c 730ce15eeefab1fd59d3e25225e50ac1 7fffffff9edf1ba099667358d70a866c 730ce15eeefab1fd59d3e25225e50ac1 fpscr=00000000
+vcvtp.s32.f32 s7, s31 a71df7e473d1a5e85f89e32776f794fa 10fdbf1cdab0778afdf200c940eff32a 0000000173d1a5e85f89e32776f794fa 10fdbf1cdab0778afdf200c940eff32a fpscr=00000000
+vcvtp.s32.f32 s7, s31 d27ed00a74b6ec7f1db4daff4eeceeb1 6564d8aae18e694b8838953fad4f214f 7fffffff74b6ec7f1db4daff4eeceeb1 6564d8aae18e694b8838953fad4f214f fpscr=00000000
+vcvtp.s32.f32 s7, s31 f273717d5de5230b2a358068d3e6813e 9bf46e15874d94225e420f92dc849a5d 000000005de5230b2a358068d3e6813e 9bf46e15874d94225e420f92dc849a5d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtp.s32.f32 s7, s31 74e7c36ebc560d9470880241aaf99200 3b8458e9e8f814cf1b752520e8f814cf 00000001bc560d9470880241aaf99200 3b8458e9e8f814cf1b752520e8f814cf fpscr=00000000
+vcvtp.s32.f32 s7, s31 83dd8fd5e3f7e8da533f8b2b0425ecc5 9c93356f12d6ed6cb51ed39d25b481bd 00000000e3f7e8da533f8b2b0425ecc5 9c93356f12d6ed6cb51ed39d25b481bd fpscr=00000000
+vcvtp.s32.f32 s7, s31 a01a053f2aa0e9b4ae7ec0d6ec313f51 49d8afa78f206dbbc4cc6eda9734d1c4 001b15f52aa0e9b4ae7ec0d6ec313f51 49d8afa78f206dbbc4cc6eda9734d1c4 fpscr=00000000
+vcvtp.s32.f32 s7, s31 ae3bbaa854c98c645d1732e2d2ec0a6f b3a800f8ab74aa1f3ac8c084e40bd01f 0000000054c98c645d1732e2d2ec0a6f b3a800f8ab74aa1f3ac8c084e40bd01f fpscr=00000000
+vcvtp.s32.f32 s7, s31 58989ace205e406f69421d6e6fe597c3 9ffcfe4f1196ac0a5b68093a16f30889 00000000205e406f69421d6e6fe597c3 9ffcfe4f1196ac0a5b68093a16f30889 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.s32.f32 s7, s31 02242bdae919b72de919b72d208658d1 8e96ca440934cdcd3a406add9a74e8e3 00000000e919b72de919b72d208658d1 8e96ca440934cdcd3a406add9a74e8e3 fpscr=00000000
+vcvtp.s32.f32 s7, s31 a296e624de70d6dd54f5c97099ddb3d4 704d0beee0f3429353f606f1bf6a75b9 7fffffffde70d6dd54f5c97099ddb3d4 704d0beee0f3429353f606f1bf6a75b9 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtp.s32.f32 s7, s31 d9fe44b07e9570fe1f3718881f371888 b160bdf1e85671efff54398158e136fc 000000007e9570fe1f3718881f371888 b160bdf1e85671efff54398158e136fc fpscr=00000000
+vcvtp.s32.f32 s7, s31 c184e05f8c003607ede7ddfd6ac4e3a6 ed762249783ec6ca0e83bc63120390d6 800000008c003607ede7ddfd6ac4e3a6 ed762249783ec6ca0e83bc63120390d6 fpscr=00000000
+vcvtp.s32.f32 s7, s31 b9ef4a3af20c9ee12080178a060ee5f5 78fb2125ed8a24f53fb0146ff7cdbe9d 7ffffffff20c9ee12080178a060ee5f5 78fb2125ed8a24f53fb0146ff7cdbe9d fpscr=00000000
+vcvtm.s32.f32 s1, s0 9457fd43d7383f63d4b0978b102d4d77 bb299941d772be21eb68ba33e6158841 bb299941d772be2180000000e6158841 bb299941d772be2180000000e6158841 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.s32.f32 s1, s0 ce009f8d3967e422bc491433c84f293d 11471dd6ebf491e011471dd6c76fc263 11471dd6ebf491e0ffff103dc76fc263 11471dd6ebf491e0ffff103dc76fc263 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtm.s32.f32 s1, s0 dd1ca2613a5de9fb3a5de9fb1bcdb204 175dbc7b753aac882d29404cf0aab414 175dbc7b753aac8880000000f0aab414 175dbc7b753aac8880000000f0aab414 fpscr=00000000
+vcvtm.s32.f32 s1, s0 9bf7eacf3a99919de79979ab1bdab97f f03622b304980837f1056ecbf3421930 f03622b30498083780000000f3421930 f03622b30498083780000000f3421930 fpscr=00000000
+vcvtm.s32.f32 s1, s0 c50b1e291095d5d4b5a7c57e054f3c4c da7c1def7d935852f8298809c57fe670 da7c1def7d935852fffff001c57fe670 da7c1def7d935852fffff001c57fe670 fpscr=00000000
+vcvtm.s32.f32 s1, s0 0af4d6ff13f47811696c35488e11d9a0 03048499afbb33cb2cea7ab3d082ac0f 03048499afbb33cb80000000d082ac0f 03048499afbb33cb80000000d082ac0f fpscr=00000000
+vcvtm.s32.f32 s1, s0 20a7e64a66a71a3b1fec617ad6e3fb99 3d865449752b7baceb9b440c1b517e05 3d865449752b7bac000000001b517e05 3d865449752b7bac000000001b517e05 fpscr=00000000
+vcvtm.s32.f32 s1, s0 e5d7c1bedd6f4a709eceec73c748bb35 79510b96705567a34d3af385d9969075 79510b96705567a380000000d9969075 79510b96705567a380000000d9969075 fpscr=00000000
+vcvtm.s32.f32 s1, s0 8c76e66b86e3c6ad996719c5a7fd2ca5 877b9bb1c792113c8bcded22d0603065 877b9bb1c792113c80000000d0603065 877b9bb1c792113c80000000d0603065 fpscr=00000000
+vcvtm.s32.f32 s1, s0 70b775e4d49f9203d474792ecc3a81a2 cae50ad6a2488d92a8a589aba318ab73 cae50ad6a2488d92ffffffffa318ab73 cae50ad6a2488d92ffffffffa318ab73 fpscr=00000000
+vcvtm.s32.f32 s1, s0 19186216a0befd8b1944db086e3df36d 4b25e31435dccca39416297ec063bf3f 4b25e31435dccca3fffffffcc063bf3f 4b25e31435dccca3fffffffcc063bf3f fpscr=00000000
+vcvtm.s32.f32 s1, s0 2d9157222f1450834f265db0a7fc356e aa6cd67b91af8ed8d4e9e7213b4651d4 aa6cd67b91af8ed8000000003b4651d4 aa6cd67b91af8ed8000000003b4651d4 fpscr=00000000
+vcvtm.s32.f32 s1, s0 37e4f41862df5448bb7f9c4cddcff632 7d580d01039bfff848c72053876f3caf 7d580d01039bfff8ffffffff876f3caf 7d580d01039bfff8ffffffff876f3caf fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.s32.f32 s1, s0 cba9ad2b49c13f18628b95881c39a651 ec2d7d91b042a80eec2d7d9152cd78e4 ec2d7d91b042a80e7fffffff52cd78e4 ec2d7d91b042a80e7fffffff52cd78e4 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtm.s32.f32 s1, s0 8330a68d1f78eba85f0f7b34ddca15d0 5792d578824f1ebc12c83fb171c5e7fd 5792d578824f1ebc7fffffff71c5e7fd 5792d578824f1ebc7fffffff71c5e7fd fpscr=00000000
+vcvtm.s32.f32 s1, s0 a3a141a72eeefcf798da1ffec9d68a4e 507c0d67db4f2ea6a419124e1e8ab617 507c0d67db4f2ea6000000001e8ab617 507c0d67db4f2ea6000000001e8ab617 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtm.s32.f32 s1, s0 5ee937795cb6ffbaa88d9e6fd2ec55a9 75b5bf3adb8960df01d8d7ab75b5bf3a 75b5bf3adb8960df7fffffff75b5bf3a 75b5bf3adb8960df7fffffff75b5bf3a fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vcvtm.s32.f32 s1, s0 2ffb347fa72b6a633c832d7219068a1b 525e6ff7525e6ff7218a86172bf51194 525e6ff7525e6ff7000000002bf51194 525e6ff7525e6ff7000000002bf51194 fpscr=00000000
+vcvtm.s32.f32 s1, s0 0d8256b006ce896a639f13244988977e 65dc1f17a142da0873167bce1430b627 65dc1f17a142da08000000001430b627 65dc1f17a142da08000000001430b627 fpscr=00000000
+vcvtm.s32.f32 s1, s0 e6569c986f417eb936aa7a6d257f3720 8cb75b086725cde962dd6b74ef806e35 8cb75b086725cde980000000ef806e35 8cb75b086725cde980000000ef806e35 fpscr=00000000
+vcvtm.s32.f32 s1, s0 348c74fff83a2b2420bee202871eaa79 a0e9c86fb95c5721583491aff9916c56 a0e9c86fb95c572180000000f9916c56 a0e9c86fb95c572180000000f9916c56 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.s32.f32 s1, s0 3e3e8dab14356a0648c2b3e5ff5a62ea f818ac6f6ebf4ac7a936cf6b95ebcb48 f818ac6f6ebf4ac7ffffffff95ebcb48 f818ac6f6ebf4ac7ffffffff95ebcb48 fpscr=00000000
+vcvtm.s32.f32 s1, s0 2424c78028dc962ec440fbabfec7f998 536c855f7dc17f5f432f618d36160e6f 536c855f7dc17f5f0000000036160e6f 536c855f7dc17f5f0000000036160e6f fpscr=00000000
+vcvtm.s32.f32 s1, s0 d174465508b51579cc23778c02d27fed 84ac5df62ac7ec2de84aea391df77ff9 84ac5df62ac7ec2d000000001df77ff9 84ac5df62ac7ec2d000000001df77ff9 fpscr=00000000
+vcvtm.s32.f32 s1, s0 50659331cfdd2ed0c0e335deb700cc41 daf5df37dbe53d957df0c804d892443e daf5df37dbe53d9580000000d892443e daf5df37dbe53d9580000000d892443e fpscr=00000000
+vcvtm.s32.f32 s1, s0 78ed4f011a733b24f0a9058e2e0d0711 b6d7e9cf87f61e4564b9d8dbabc678c5 b6d7e9cf87f61e45ffffffffabc678c5 b6d7e9cf87f61e45ffffffffabc678c5 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[2]
+vcvtm.s32.f32 s1, s0 285c50c8de444cc9de444cc91337acef 9454bb5f0759d127c2da7a40be797f09 9454bb5f0759d127ffffffffbe797f09 9454bb5f0759d127ffffffffbe797f09 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtm.s32.f32 s1, s0 4e026915b21eb38ab3bddf19f7d58588 85be6f6c31ae2dd92a085a1706046cbb 85be6f6c31ae2dd90000000006046cbb 85be6f6c31ae2dd90000000006046cbb fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[0]
+vcvtm.s32.f32 s1, s0 4a9487dd956a6651dae4ef9de0a02c08 ecfd5554195fd216ecfd5554221d7195 ecfd5554195fd21600000000221d7195 ecfd5554195fd21600000000221d7195 fpscr=00000000
+randV128: 5120 calls, 5270 iters
+vcvtm.s32.f32 s1, s0 d752cbc22852cff27a0b25f740e44f74 823d85e85789c82c390a874daa721efc 823d85e85789c82cffffffffaa721efc 823d85e85789c82cffffffffaa721efc fpscr=00000000
+vcvtm.s32.f32 s1, s0 f8b3ae2a8302101bf8e63b694f76dbb9 1b16184dee8f7fbf8994bc891d65014d 1b16184dee8f7fbf000000001d65014d 1b16184dee8f7fbf000000001d65014d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtm.s32.f32 s1, s0 0812c23316395797fa5daebfa53f4036 1aa79a93e076c1d613247ba59f734db8 1aa79a93e076c1d6ffffffff9f734db8 1aa79a93e076c1d6ffffffff9f734db8 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtm.s32.f32 s1, s0 7bf808d9988cd1188adbae0fd5071cc1 e6a9f4c1d5b39a053683f447926c52dc e6a9f4c1d5b39a05ffffffff926c52dc e6a9f4c1d5b39a05ffffffff926c52dc fpscr=00000000
+vcvtm.s32.f32 s1, s0 68ecf10a96fa22f431c30bd7a0768699 20ce496ec2c9ee36b80bdd0d60e2805f 20ce496ec2c9ee367fffffff60e2805f 20ce496ec2c9ee367fffffff60e2805f fpscr=00000000
+vcvtm.s32.f32 s1, s0 1dd8078bbb2e449b333d78f4cf68f0b0 0fbf656b76072c57d8ca712b18c17911 0fbf656b76072c570000000018c17911 0fbf656b76072c570000000018c17911 fpscr=00000000
+vcvtm.s32.f32 s1, s0 8cf1e44670d41ffcd34a2f254006ce68 877d999aff54e2392b166c46ab3e8324 877d999aff54e239ffffffffab3e8324 877d999aff54e239ffffffffab3e8324 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtm.s32.f32 s1, s0 138bc20e79a8259b4f80fed29775b3ba 209726ce271c9559c82784084ba4cafc 209726ce271c9559014995f84ba4cafc 209726ce271c9559014995f84ba4cafc fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtm.s32.f32 s1, s0 b7771cd225ab56beecf819f9b7771cd2 33436e3f481df16dc918de05222f9658 33436e3f481df16d00000000222f9658 33436e3f481df16d00000000222f9658 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtm.s32.f32 s1, s0 14465fceb25510bbaffd8a342eb73a25 4aaa315255b9b47588e0b1d435904e31 4aaa315255b9b4750000000035904e31 4aaa315255b9b4750000000035904e31 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.s32.f32 s1, s0 acc916d780a2ea3a1abea25e90f596e0 34bb46482d458b6f15f54b18df4a17af 34bb46482d458b6f80000000df4a17af 34bb46482d458b6f80000000df4a17af fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.s32.f32 s1, s0 267541509e546a7fd4e68adad1568fd2 790021611f52bb989d93ecda5d42e6bb 790021611f52bb987fffffff5d42e6bb 790021611f52bb987fffffff5d42e6bb fpscr=00000000
+vcvtm.s32.f32 s1, s0 9452727f9abc6fefc3341466509ff14d 18a3939f94cb7236f9f34ce2cde86165 18a3939f94cb7236e2f3d360cde86165 18a3939f94cb7236e2f3d360cde86165 fpscr=00000000
+vcvtm.s32.f32 s1, s0 34cd95c69dd8f0f22d6c6ba5ade77182 90e78d037189c8396b5790f70d2c4424 90e78d037189c839000000000d2c4424 90e78d037189c839000000000d2c4424 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.s32.f32 s1, s0 17600a4617600a4690df3416db578fb7 c9b23055a0b6a0a967bb009cc95156d2 c9b23055a0b6a0a9fff2ea92c95156d2 c9b23055a0b6a0a9fff2ea92c95156d2 fpscr=00000000
+vcvtm.s32.f32 s1, s0 da9c48d309e2f96feb176e097079a28d 398abc76ab0c8619ae557ab2347e5110 398abc76ab0c861900000000347e5110 398abc76ab0c861900000000347e5110 fpscr=00000000
+vcvtm.s32.f32 s1, s0 0fe140f803fb7c26eed7f97d32b4366d 94d0fc949f37487d2f31863508d01956 94d0fc949f37487d0000000008d01956 94d0fc949f37487d0000000008d01956 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[2]
+vcvtm.s32.f32 s1, s0 08dc732e4f0f0d8fadd24d62add24d62 03505564bb248807699abd5c2459b401 03505564bb248807000000002459b401 03505564bb248807000000002459b401 fpscr=00000000
+vcvtm.s32.f32 s1, s0 dab0eb9b5b06f31edd23ea1c1e3c55a5 1e78f89a03c449f487db6bb4a9452cd4 1e78f89a03c449f4ffffffffa9452cd4 1e78f89a03c449f4ffffffffa9452cd4 fpscr=00000000
+vcvtm.s32.f32 s1, s0 69a6229e924d13432146569a2f4e9b7e 593bfed3e7d9c0cb2a8fb348bdc7d6b7 593bfed3e7d9c0cbffffffffbdc7d6b7 593bfed3e7d9c0cbffffffffbdc7d6b7 fpscr=00000000
+vcvtm.s32.f32 s1, s0 085e0bf555366421625bb10c31b091e1 afcedebc20a3aae41f4ad1a98b1d9e2c afcedebc20a3aae4ffffffff8b1d9e2c afcedebc20a3aae4ffffffff8b1d9e2c fpscr=00000000
+vcvtn.u32.f64 s27, d5 4f6c80b37e6392dee73c79dc2b38a557 2a10e0481ccc09514c2a258227ac8915 000000007e6392dee73c79dc2b38a557 2a10e0481ccc09514c2a258227ac8915 fpscr=00000000
+vcvtn.u32.f64 s27, d5 df4af078027c243309442a750119432e ce658dbd6b10b83344d7e7313db0cf8b 00000000027c243309442a750119432e ce658dbd6b10b83344d7e7313db0cf8b fpscr=00000000
+vcvtn.u32.f64 s27, d5 1506e125c37418c5192ff7368861b419 2fded8acf89038dc1deb8a0687cfdb3a 00000000c37418c5192ff7368861b419 2fded8acf89038dc1deb8a0687cfdb3a fpscr=00000000
+vcvtn.u32.f64 s27, d5 93424ef0392c62da38666dcb73e4db1d 644da0d29bfcd0cba9448360a180b7a0 ffffffff392c62da38666dcb73e4db1d 644da0d29bfcd0cba9448360a180b7a0 fpscr=00000000
+vcvtn.u32.f64 s27, d5 b09ee2df057e4b71fca1efe01d80d1eb 62319ad813a4188d05316fae4161ce2b ffffffff057e4b71fca1efe01d80d1eb 62319ad813a4188d05316fae4161ce2b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 ae8495eb5b66d977ae8495eb5b66d977 cfb006185cc94b8267b355b84b944dc9 000000005b66d977ae8495eb5b66d977 cfb006185cc94b8267b355b84b944dc9 fpscr=00000000
+vcvtn.u32.f64 s27, d5 b663dc61766721425e7858455e6eea36 871aff9c3238a9dbbd87629234083df5 00000000766721425e7858455e6eea36 871aff9c3238a9dbbd87629234083df5 fpscr=00000000
+vcvtn.u32.f64 s27, d5 dd4fbcf704b693750f1afc9cad6c14be 6be6bfb1da119c04c70cf214f27d7273 ffffffff04b693750f1afc9cad6c14be 6be6bfb1da119c04c70cf214f27d7273 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 03c1d781342509547d2c4e476f8ec324 6a38e8b66cd6e3552ca4dcfe3c9189b8 ffffffff342509547d2c4e476f8ec324 6a38e8b66cd6e3552ca4dcfe3c9189b8 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 a3a08651367adc526a4b94c93782c26d d99a4849e7f0a939d99a4849e7f0a939 00000000367adc526a4b94c93782c26d d99a4849e7f0a939d99a4849e7f0a939 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 9ea3c8364a1a8fb49ea3c8364a1a8fb4 18be694a03332affe378bc8c0412a0fd 000000004a1a8fb49ea3c8364a1a8fb4 18be694a03332affe378bc8c0412a0fd fpscr=00000000
+vcvtn.u32.f64 s27, d5 7a65723edcc94303aaf72badbecedc56 1ab9c6cfaf3021605be36865235cd2f9 00000000dcc94303aaf72badbecedc56 1ab9c6cfaf3021605be36865235cd2f9 fpscr=00000000
+vcvtn.u32.f64 s27, d5 19cb88f8e69fa45e615c228fcc3cce33 dfccc7530aa93bfe529f16b1e422688a 00000000e69fa45e615c228fcc3cce33 dfccc7530aa93bfe529f16b1e422688a fpscr=00000000
+vcvtn.u32.f64 s27, d5 30b1e8631f16f1d7434cb713b8648f16 175d9032deb4ff2561e7a02cf28f23a2 000000001f16f1d7434cb713b8648f16 175d9032deb4ff2561e7a02cf28f23a2 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.u32.f64 s27, d5 20ad2a15816130f3705ba4bba46e8484 ca74ab00e312598e3499ff894a05f87e 00000000816130f3705ba4bba46e8484 ca74ab00e312598e3499ff894a05f87e fpscr=00000000
+vcvtn.u32.f64 s27, d5 6025e3a4d51733152947f7d9406366b2 82bdbfeadf848d6af9a88ea482ac445c 00000000d51733152947f7d9406366b2 82bdbfeadf848d6af9a88ea482ac445c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.u32.f64 s27, d5 6a6bdddd8b536003115da8ba7f5f7079 958b1239a76739c3958b1239a76739c3 000000008b536003115da8ba7f5f7079 958b1239a76739c3958b1239a76739c3 fpscr=00000000
+vcvtn.u32.f64 s27, d5 d360a1c005f543feda72a90bfc7ae833 b452b492427917bc56776486f7a2cdbb 0000000005f543feda72a90bfc7ae833 b452b492427917bc56776486f7a2cdbb fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 c2549babfb02abf06963f7833ff94a84 bf9c8dedb4f3b77e1a37f91fb20e4ad9 00000000fb02abf06963f7833ff94a84 bf9c8dedb4f3b77e1a37f91fb20e4ad9 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.u32.f64 s27, d5 666969c4b9a76533779de6631b0f3205 13d2424bab49c429d09a957dd644bedf 00000000b9a76533779de6631b0f3205 13d2424bab49c429d09a957dd644bedf fpscr=00000000
+vcvtn.u32.f64 s27, d5 d07b25299560e8c679ed58db0a49a107 27f8d626de80526b0a1930f8edb02a45 000000009560e8c679ed58db0a49a107 27f8d626de80526b0a1930f8edb02a45 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.u32.f64 s27, d5 272b7eb1c7027656808e9b71318dca47 702b7fc977020c465b33e66e37058432 ffffffffc7027656808e9b71318dca47 702b7fc977020c465b33e66e37058432 fpscr=00000000
+vcvtn.u32.f64 s27, d5 6ed906dd6e94f32dba29f007d90e6f35 aca84c4317cbbb3d9d0f74d7bcada302 000000006e94f32dba29f007d90e6f35 aca84c4317cbbb3d9d0f74d7bcada302 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 c6fd82a69aace6a87de8a08a3141ba17 83c795fd1698ca8457c83520c5138463 000000009aace6a87de8a08a3141ba17 83c795fd1698ca8457c83520c5138463 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 44c2c83a59312799c2df8b7a2b5180ce 50322c993c7b3c057d0f18c3f92632f8 ffffffff59312799c2df8b7a2b5180ce 50322c993c7b3c057d0f18c3f92632f8 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.u32.f64 s27, d5 155bc1dc015182a8155bc1dc015182a8 b911c2f3074e42201299a90a102ed5b0 00000000015182a8155bc1dc015182a8 b911c2f3074e42201299a90a102ed5b0 fpscr=00000000
+vcvtn.u32.f64 s27, d5 1be4cacdf3fb52a89b3ef9c83d97e789 14472e95166a0bbeb4057968e7bd896f 00000000f3fb52a89b3ef9c83d97e789 14472e95166a0bbeb4057968e7bd896f fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 f4697434e67611f55b99c9b2c98c0bae b76c014881a995085be299e2422213f5 00000000e67611f55b99c9b2c98c0bae b76c014881a995085be299e2422213f5 fpscr=00000000
+vcvtn.u32.f64 s27, d5 239aec17f5e0201b5f67e0be29b2d6c0 cf96cb06d89ed0c8391b32edd031a956 00000000f5e0201b5f67e0be29b2d6c0 cf96cb06d89ed0c8391b32edd031a956 fpscr=00000000
+vcvtn.u32.f64 s27, d5 c85c44fb99ef597319c7b4c2ca837d20 065989bafb2b6cc6dda0acaade3a632a 0000000099ef597319c7b4c2ca837d20 065989bafb2b6cc6dda0acaade3a632a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 46f6a50047135a4350c937aa38956356 8fdfc12d6b289499c7d9cb0f36f3273f 0000000047135a4350c937aa38956356 8fdfc12d6b289499c7d9cb0f36f3273f fpscr=00000000
+vcvtn.u32.f64 s27, d5 42c1fa23e7b79dcbbefb0baff713a70a d6ead07c88d0cad169dc7e953b9614ff 00000000e7b79dcbbefb0baff713a70a d6ead07c88d0cad169dc7e953b9614ff fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtn.u32.f64 s27, d5 0d12459853885e102e27a2476ba02000 f376ba58b2903bf3f376ba58b2903bf3 0000000053885e102e27a2476ba02000 f376ba58b2903bf3f376ba58b2903bf3 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 c5f7070dde81abd1f5e5604466e7566f f85eb26692014099c1c58f7753d19409 00000000de81abd1f5e5604466e7566f f85eb26692014099c1c58f7753d19409 fpscr=00000000
+vcvtn.u32.f64 s27, d5 0c325a6c8a06a4970b847db42960d28f 332bc686522d9ad48aba17385e542c32 000000008a06a4970b847db42960d28f 332bc686522d9ad48aba17385e542c32 fpscr=00000000
+vcvtn.u32.f64 s27, d5 2f662a9e91ba71ddafb3f3fb44774e35 90b622b015c8dfe4b8e57772be3bf1d9 0000000091ba71ddafb3f3fb44774e35 90b622b015c8dfe4b8e57772be3bf1d9 fpscr=00000000
+vcvtn.u32.f64 s27, d5 c97fc32908cf8fbce74af64755a29182 71b7f030395a6d03be2dd9e73098ee18 ffffffff08cf8fbce74af64755a29182 71b7f030395a6d03be2dd9e73098ee18 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 c0c53f69ee42c90bc0c53f69ee42c90b b476ac9f287f21e8de521f559e598e3b 00000000ee42c90bc0c53f69ee42c90b b476ac9f287f21e8de521f559e598e3b fpscr=00000000
+vcvtn.u32.f64 s27, d5 dd19b5a2861693e6d2ec60d36e2afb3c 4b327dcfd3af4460ec9e1de2aa4141f9 ffffffff861693e6d2ec60d36e2afb3c 4b327dcfd3af4460ec9e1de2aa4141f9 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 f66cd41b78003b23cf349125d2c695bf 2653a7bc7e719620c24823e2e4d35ecc 0000000078003b23cf349125d2c695bf 2653a7bc7e719620c24823e2e4d35ecc fpscr=00000000
+vcvtn.u32.f64 s27, d5 3b084831f1121022d9991c2d93ab2750 d4b0773972b8a018e352f957f0604d91 00000000f1121022d9991c2d93ab2750 d4b0773972b8a018e352f957f0604d91 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 3afcb016fd032dab3afcb016fd032dab 5c619fa42b9e520c060ec3540d5a193a fffffffffd032dab3afcb016fd032dab 5c619fa42b9e520c060ec3540d5a193a fpscr=00000000
+vcvtn.u32.f64 s27, d5 a51ff6b6f025917a90dc1bf235d34a1e 6bb3a5dc6b90fc33939bc23a573b9a3d fffffffff025917a90dc1bf235d34a1e 6bb3a5dc6b90fc33939bc23a573b9a3d fpscr=00000000
+randV128: 5376 calls, 5535 iters
+vcvtn.u32.f64 s27, d5 97de57f7f893acf472c2b3efc3ce3455 30aaa20f9730585f755a617d084b7c2d 00000000f893acf472c2b3efc3ce3455 30aaa20f9730585f755a617d084b7c2d fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 9f8e25f1618e979b6cec9053591eade2 9dc909671e9738179dc909671e973817 00000000618e979b6cec9053591eade2 9dc909671e9738179dc909671e973817 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 746a7a20c8b93cac18dfcab970aeca49 62ea68c49c1d9fd241ad23998c7c1b5f ffffffffc8b93cac18dfcab970aeca49 62ea68c49c1d9fd241ad23998c7c1b5f fpscr=00000000
+vcvtn.u32.f64 s27, d5 29dd5d8e1bd7cd7c465e210b7e762ccb dea75feb3a9203c51c00d641ad78fd4d 000000001bd7cd7c465e210b7e762ccb dea75feb3a9203c51c00d641ad78fd4d fpscr=00000000
+vcvtn.u32.f64 s27, d5 9b9e27cc288d9ae018948338050fbb30 9010cb35facd3d12833ab53690a7db5d 00000000288d9ae018948338050fbb30 9010cb35facd3d12833ab53690a7db5d fpscr=00000000
+vcvtn.u32.f64 s27, d5 980a516a1b831b3176fc137236e978fd 6124f102666208f203ba322da3fbd71d ffffffff1b831b3176fc137236e978fd 6124f102666208f203ba322da3fbd71d fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtn.u32.f64 s27, d5 b5ca5a3eb4c3fddad70c09cbf288a7a3 b5dba8456876c44fb5dba8456876c44f 00000000b4c3fddad70c09cbf288a7a3 b5dba8456876c44fb5dba8456876c44f fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.u32.f64 s4, d20 ecbd8457e35d67dfbeeb48edcc37dc67 f725c93fbfa8684bf725c93fbfa8684b ecbd8457e35d67dfbeeb48ed00000000 f725c93fbfa8684bf725c93fbfa8684b fpscr=00000000
+vcvta.u32.f64 s4, d20 a5d3936d543d59c28391b8fd1529d66f 6e9a42a5cdb276b134ee9a58166c8f57 a5d3936d543d59c28391b8fd00000000 6e9a42a5cdb276b134ee9a58166c8f57 fpscr=00000000
+vcvta.u32.f64 s4, d20 66d358f274c5f4454dfabe75b63be780 5bcbab1d03ca3a6b912159a07e826a97 66d358f274c5f4454dfabe7500000000 5bcbab1d03ca3a6b912159a07e826a97 fpscr=00000000
+vcvta.u32.f64 s4, d20 5f4de967d3bb0596cb7c788102889e08 3269659dbeb3b87cf20fc130d10f9c68 5f4de967d3bb0596cb7c788100000000 3269659dbeb3b87cf20fc130d10f9c68 fpscr=00000000
+vcvta.u32.f64 s4, d20 dc20686be623ac7f1329be3b7f290261 14967b92d269e375190741c01bcab753 dc20686be623ac7f1329be3b00000000 14967b92d269e375190741c01bcab753 fpscr=00000000
+vcvta.u32.f64 s4, d20 5afc3444e9c500cf76cc43b786fbe4c3 61ae16004ef183b7e88bab774c272848 5afc3444e9c500cf76cc43b700000000 61ae16004ef183b7e88bab774c272848 fpscr=00000000
+vcvta.u32.f64 s4, d20 714c749b1f703438956a90506f280cef 71468e0a5ff0609e5c8484ac532d9f03 714c749b1f703438956a9050ffffffff 71468e0a5ff0609e5c8484ac532d9f03 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.u32.f64 s4, d20 b19d79ba478ca5b279f2b22841f179cf 347d5ad90d9e510370df32131daf5ed2 b19d79ba478ca5b279f2b228ffffffff 347d5ad90d9e510370df32131daf5ed2 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.u32.f64 s4, d20 89ad77863bb509ca89ad77863bb509ca a5c05d38d6ab2cbeb1b3daded4212924 89ad77863bb509ca89ad778600000000 a5c05d38d6ab2cbeb1b3daded4212924 fpscr=00000000
+vcvta.u32.f64 s4, d20 33ab362a37575ab8629f087c2a4187e8 0600f213a64deba11b446179c612c561 33ab362a37575ab8629f087c00000000 0600f213a64deba11b446179c612c561 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.u32.f64 s4, d20 ed35b6ae75b81ea972c9030cd7798389 1a3c685411379a0d1a3c685411379a0d ed35b6ae75b81ea972c9030c00000000 1a3c685411379a0d1a3c685411379a0d fpscr=00000000
+vcvta.u32.f64 s4, d20 3cce4648ab414b3b6cec5472dd568142 a6cec120fa871fffb037b15f53ccecfa 3cce4648ab414b3b6cec547200000000 a6cec120fa871fffb037b15f53ccecfa fpscr=00000000
+vcvta.u32.f64 s4, d20 9e47b98bf35cbf51c21e06de6e4b1bf6 ae2b46777b40bb6d2519da3a056e388b 9e47b98bf35cbf51c21e06de00000000 ae2b46777b40bb6d2519da3a056e388b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.u32.f64 s4, d20 c15fb8028e0b2c67aa7e7d269a187849 3694e58ba7c57441db6ae1f8f4a5caa5 c15fb8028e0b2c67aa7e7d2600000000 3694e58ba7c57441db6ae1f8f4a5caa5 fpscr=00000000
+vcvta.u32.f64 s4, d20 71265756c774b8b4de744bacd0968316 5b2f0bfd14417549d77e9b37769339e9 71265756c774b8b4de744bac00000000 5b2f0bfd14417549d77e9b37769339e9 fpscr=00000000
+vcvta.u32.f64 s4, d20 98c8d9874ef0ce355f859fa3bce9a786 4e0abe1244ec95732b70c6626b41c7d0 98c8d9874ef0ce355f859fa300000000 4e0abe1244ec95732b70c6626b41c7d0 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.u32.f64 s4, d20 f21f594d648582302ecb28e89468f4d9 e531d61401f069f9e904e6650f122001 f21f594d648582302ecb28e800000000 e531d61401f069f9e904e6650f122001 fpscr=00000000
+vcvta.u32.f64 s4, d20 1128d6e0329f896486b0f28332725a4f a02d84c5daeade6ad0d2091b503f1dd7 1128d6e0329f896486b0f28300000000 a02d84c5daeade6ad0d2091b503f1dd7 fpscr=00000000
+vcvta.u32.f64 s4, d20 b2821d72bae2c2613abc357250209fd3 fa5dd757a44a88aff1619ae9945c240b b2821d72bae2c2613abc357200000000 fa5dd757a44a88aff1619ae9945c240b fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.u32.f64 s4, d20 a4166210cc0f248f54f7294ade47752a e5705f6b270abbd5e5705f6b270abbd5 a4166210cc0f248f54f7294a00000000 e5705f6b270abbd5e5705f6b270abbd5 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.u32.f64 s4, d20 5a5c47208da009bf7f16eda64c924047 935341023d8c44ff935341023d8c44ff 5a5c47208da009bf7f16eda600000000 935341023d8c44ff935341023d8c44ff fpscr=00000000
+vcvta.u32.f64 s4, d20 a3d2fba25805db7277aa72aaebffc35f c4bf32e6afad476795b5eb03dc7e03b7 a3d2fba25805db7277aa72aa00000000 c4bf32e6afad476795b5eb03dc7e03b7 fpscr=00000000
+vcvta.u32.f64 s4, d20 2463fa78a42722ddda944e48fb39e335 11bb9452575653a2c488dfce0d2cf6de 2463fa78a42722ddda944e4800000000 11bb9452575653a2c488dfce0d2cf6de fpscr=00000000
+vcvta.u32.f64 s4, d20 efde7e5320917abd641e62d6e67714bd daef733503fb81fa5e450d4fd00540e0 efde7e5320917abd641e62d6ffffffff daef733503fb81fa5e450d4fd00540e0 fpscr=00000000
+vcvta.u32.f64 s4, d20 99ea3f59a32703c9a7089597b9ec3f4c 17b8c1ea9b4573731f6aeb94f34f1d77 99ea3f59a32703c9a708959700000000 17b8c1ea9b4573731f6aeb94f34f1d77 fpscr=00000000
+vcvta.u32.f64 s4, d20 7ea0f3f24171a5f13d0327badc43b08c 74694fe7e07e75fbdb86d677ed47607c 7ea0f3f24171a5f13d0327ba00000000 74694fe7e07e75fbdb86d677ed47607c fpscr=00000000
+vcvta.u32.f64 s4, d20 ce7ac2437932a11bb6d1edab86e1c066 712881df7eaa243c6a4a1b67942ed5e9 ce7ac2437932a11bb6d1edabffffffff 712881df7eaa243c6a4a1b67942ed5e9 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.u32.f64 s4, d20 1ecfa7a7df99486020335f8cda6bf8e8 e507e8fb0d1f51bf4e4f009a15fc120e 1ecfa7a7df99486020335f8cffffffff e507e8fb0d1f51bf4e4f009a15fc120e fpscr=00000000
+vcvta.u32.f64 s4, d20 b79f36453744e04074bad0f735249253 562405a09ec69816e03f6f91799c332c b79f36453744e04074bad0f700000000 562405a09ec69816e03f6f91799c332c fpscr=00000000
+vcvta.u32.f64 s4, d20 f0d26228d1c924c2444fef4b91748c60 7cae02e0d4e2d6f653ae14f34ae9bc37 f0d26228d1c924c2444fef4bffffffff 7cae02e0d4e2d6f653ae14f34ae9bc37 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.u32.f64 s4, d20 519330d8e5247d694d3168255481a796 82bf9dd861bda0301739fc1b47534f70 519330d8e5247d694d31682500000000 82bf9dd861bda0301739fc1b47534f70 fpscr=00000000
+vcvta.u32.f64 s4, d20 f0d993aa6ec857525c6359895df50b37 52ac2c5de9d282cfa6bc4f05e93c7e0b f0d993aa6ec857525c63598900000000 52ac2c5de9d282cfa6bc4f05e93c7e0b fpscr=00000000
+vcvta.u32.f64 s4, d20 e56936c9536a4f84cd9bda5c9b012e62 d8383a0d787e530be2a53395112aa864 e56936c9536a4f84cd9bda5c00000000 d8383a0d787e530be2a53395112aa864 fpscr=00000000
+vcvta.u32.f64 s4, d20 04ccbbfe0b389b2f2559673d6da7bc0e 6517528a52f849c42b3730cd52b0f4f1 04ccbbfe0b389b2f2559673d00000000 6517528a52f849c42b3730cd52b0f4f1 fpscr=00000000
+vcvta.u32.f64 s4, d20 d425c38a281aea898d4c1a6b4606ba36 e8b144684ab921622f0d75cccbb62483 d425c38a281aea898d4c1a6b00000000 e8b144684ab921622f0d75cccbb62483 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.u32.f64 s4, d20 c8fed3aad0571e06c8fed3aad0571e06 e54f3caa255e07ebd3a405eea5a08faa c8fed3aad0571e06c8fed3aa00000000 e54f3caa255e07ebd3a405eea5a08faa fpscr=00000000
+vcvta.u32.f64 s4, d20 5c6e15190fa77d7fbe10afee06173fc6 91489181c386e540498eb2b1a932d2b3 5c6e15190fa77d7fbe10afeeffffffff 91489181c386e540498eb2b1a932d2b3 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.u32.f64 s4, d20 fb4f4498a23405eefb4f4498a23405ee 5461a1ddce258d27799528b9c898315e fb4f4498a23405eefb4f4498ffffffff 5461a1ddce258d27799528b9c898315e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.u32.f64 s4, d20 1b62f57b58fabe9d1b62f57b58fabe9d 95eef97dc392ddbd86bdcf7d29a8943d 1b62f57b58fabe9d1b62f57b00000000 95eef97dc392ddbd86bdcf7d29a8943d fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.u32.f64 s4, d20 6e1a5a83b03f8581d2b60504b2c7f2b7 95a758875c43bcf595a758875c43bcf5 6e1a5a83b03f8581d2b6050400000000 95a758875c43bcf595a758875c43bcf5 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.u32.f64 s4, d20 f890d9757e6f1d6d51f990869a68447b 6f45987dc55d3d3e29af6e33dd4bd450 f890d9757e6f1d6d51f9908600000000 6f45987dc55d3d3e29af6e33dd4bd450 fpscr=00000000
+vcvta.u32.f64 s4, d20 ef39bcc36d4bfb60ed2c6d03dcda753b 1db937ec6ec344b2585383ebe6b4a8af ef39bcc36d4bfb60ed2c6d03ffffffff 1db937ec6ec344b2585383ebe6b4a8af fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.u32.f64 s4, d20 c7378decfb812b15b6c93a2bc0a12d1d df84a7e827ae2732865cfb0c6dbf3aad c7378decfb812b15b6c93a2b00000000 df84a7e827ae2732865cfb0c6dbf3aad fpscr=00000000
+vcvta.u32.f64 s4, d20 e9018f15eb8420b7a572730b7c6cb747 e3fa04b0923e33ae973dcfb7c56d4627 e9018f15eb8420b7a572730b00000000 e3fa04b0923e33ae973dcfb7c56d4627 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.u32.f64 s4, d20 46bffd3415d85564aba321cae5d61399 b074f39ee45d520d126dcaf9c5baa32c 46bffd3415d85564aba321ca00000000 b074f39ee45d520d126dcaf9c5baa32c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.u32.f64 s4, d20 e501c48290d9e867a0e27f7b47463e70 6fa8366b97decf36c5f4ea929d613ac5 e501c48290d9e867a0e27f7b00000000 6fa8366b97decf36c5f4ea929d613ac5 fpscr=00000000
+vcvta.u32.f64 s4, d20 b432f2d3731c1c5fe537bb3e293868b9 b551b66488dc09bf85abf22b6cb47ee4 b432f2d3731c1c5fe537bb3e00000000 b551b66488dc09bf85abf22b6cb47ee4 fpscr=00000000
+vcvta.u32.f64 s4, d20 c66db381b18425dba532d9d7c62b8961 476e7d4cec811a377c894a10dfc8843a c66db381b18425dba532d9d7ffffffff 476e7d4cec811a377c894a10dfc8843a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvta.u32.f64 s4, d20 df4b78b1f3fb83a3cd400b16d7dbda1b f407fe34faeeb79ef407fe34faeeb79e df4b78b1f3fb83a3cd400b1600000000 f407fe34faeeb79ef407fe34faeeb79e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvta.u32.f64 s4, d20 7b2cc2c43c63eaaf48e0cfa8c5e11d88 8d56cb5830cc4f2c9eb702941e06beb1 7b2cc2c43c63eaaf48e0cfa800000000 8d56cb5830cc4f2c9eb702941e06beb1 fpscr=00000000
+vcvtp.u32.f64 s7, d31 250bf11c598af09c899bc082b8f494cc 86d779cc9b78ee7b1d6db8bd0d9c9e92 00000000598af09c899bc082b8f494cc 86d779cc9b78ee7b1d6db8bd0d9c9e92 fpscr=00000000
+vcvtp.u32.f64 s7, d31 733afab7c1cac77ccfad1e88520f435d 4a679181a32f30d953df40e013132870 ffffffffc1cac77ccfad1e88520f435d 4a679181a32f30d953df40e013132870 fpscr=00000000
+vcvtp.u32.f64 s7, d31 69fe98cb1c6607ddf221a18de7f26630 95700c1119383ffdb635a24f6fea8a8a 000000001c6607ddf221a18de7f26630 95700c1119383ffdb635a24f6fea8a8a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.u32.f64 s7, d31 e78978250a2c0704e78978250a2c0704 a94a60d3ee4fe758c3594e6274d2e448 000000000a2c0704e78978250a2c0704 a94a60d3ee4fe758c3594e6274d2e448 fpscr=00000000
+vcvtp.u32.f64 s7, d31 ccca3f516562b4b118ecd3956832ddc1 57b35c7494e552114cefa54c5315c960 ffffffff6562b4b118ecd3956832ddc1 57b35c7494e552114cefa54c5315c960 fpscr=00000000
+vcvtp.u32.f64 s7, d31 07fd844cd520a5dbec5f0162dc95fac8 efab063f3de34e7e48552662f0379aed 00000000d520a5dbec5f0162dc95fac8 efab063f3de34e7e48552662f0379aed fpscr=00000000
+vcvtp.u32.f64 s7, d31 0aab93f88f4127d4dd5863633befe1f2 15680d566907d819d8ab19b933a6069d 000000018f4127d4dd5863633befe1f2 15680d566907d819d8ab19b933a6069d fpscr=00000000
+randV128: 5632 calls, 5803 iters
+vcvtp.u32.f64 s7, d31 38d024dfc8ba9df20c73a9394550d9c9 555fd3c6d980d541d470122906699d85 ffffffffc8ba9df20c73a9394550d9c9 555fd3c6d980d541d470122906699d85 fpscr=00000000
+vcvtp.u32.f64 s7, d31 35a68946acca0618ae7c73c7104792d0 29cba957c68701319a5872e32a6f8519 00000001acca0618ae7c73c7104792d0 29cba957c68701319a5872e32a6f8519 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.u32.f64 s7, d31 8d0cd5e0d360d8cd114e5bcc72bbc54a d8bf28f145ff361dbf935b7b5ecb61de 00000000d360d8cd114e5bcc72bbc54a d8bf28f145ff361dbf935b7b5ecb61de fpscr=00000000
+vcvtp.u32.f64 s7, d31 3f3cc68b65f175d70f3f5dca77dd644c b7f7f5848a2daadd345668d70b2c17c4 0000000065f175d70f3f5dca77dd644c b7f7f5848a2daadd345668d70b2c17c4 fpscr=00000000
+vcvtp.u32.f64 s7, d31 6331fb225e9529515a030749a9aeb343 031816689e5824b4d638e7dcfe92f133 000000015e9529515a030749a9aeb343 031816689e5824b4d638e7dcfe92f133 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.u32.f64 s7, d31 8540f20aa46a1850b8c8d4129b0923bf f06c84e4b487f29ef06c84e4b487f29e 00000000a46a1850b8c8d4129b0923bf f06c84e4b487f29ef06c84e4b487f29e fpscr=00000000
+vcvtp.u32.f64 s7, d31 f487fc2801490fb5f6f5cd24fa302c36 70653d475e99cd7506840bb4c0580a12 ffffffff01490fb5f6f5cd24fa302c36 70653d475e99cd7506840bb4c0580a12 fpscr=00000000
+vcvtp.u32.f64 s7, d31 2d4f2b5dc4ac75ebe68b10b11da7c0be 2d4bfd28c958d6bc0be2759ffa47ee34 00000001c4ac75ebe68b10b11da7c0be 2d4bfd28c958d6bc0be2759ffa47ee34 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.u32.f64 s7, d31 2906791eec71bc94cda2bb0e7dc47297 d7ccf2a7d76ad73403fe8d534ef97b5e 00000000ec71bc94cda2bb0e7dc47297 d7ccf2a7d76ad73403fe8d534ef97b5e fpscr=00000000
+vcvtp.u32.f64 s7, d31 04ef45502dc7df79ede8f91b82fafb6c c01b8cb301b2029962800a71705c2cb5 000000002dc7df79ede8f91b82fafb6c c01b8cb301b2029962800a71705c2cb5 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.u32.f64 s7, d31 c1d3876c4ddf4fe4abd52109aa4d1f64 a2b8e26ba011a7e5bb3770391af7bbc3 000000004ddf4fe4abd52109aa4d1f64 a2b8e26ba011a7e5bb3770391af7bbc3 fpscr=00000000
+vcvtp.u32.f64 s7, d31 584b6e7b13cc250d35aa427c6fb17b27 b06bbc149cecab9c9defe00786f91d90 0000000013cc250d35aa427c6fb17b27 b06bbc149cecab9c9defe00786f91d90 fpscr=00000000
+vcvtp.u32.f64 s7, d31 32ce174774749765351bf4ee18934639 5f4c309f5f65b201ec3ed59efb2de8c3 ffffffff74749765351bf4ee18934639 5f4c309f5f65b201ec3ed59efb2de8c3 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.u32.f64 s7, d31 d3d800e41c9ad7d9ebc915babc89925b 2b104934c532eea6ee53cd1bde0d96c7 000000011c9ad7d9ebc915babc89925b 2b104934c532eea6ee53cd1bde0d96c7 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.u32.f64 s7, d31 93edc152b9cd766440911d1b18613273 4e6e4f3109411e9e4e6e4f3109411e9e ffffffffb9cd766440911d1b18613273 4e6e4f3109411e9e4e6e4f3109411e9e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.u32.f64 s7, d31 8bf7450bd9a1e92b87f25328a35c0b2e 5b4bbab030647bde5b4bbab030647bde ffffffffd9a1e92b87f25328a35c0b2e 5b4bbab030647bde5b4bbab030647bde fpscr=00000000
+vcvtp.u32.f64 s7, d31 df273d10cea6c81fd2ab5b57e6998fbc 018c6b484f1d8f8fddc25aaf69be13e7 00000001cea6c81fd2ab5b57e6998fbc 018c6b484f1d8f8fddc25aaf69be13e7 fpscr=00000000
+vcvtp.u32.f64 s7, d31 0aec5e399c2c303d119c84a838c92620 c2f2b990363109ef6b76f7ea5a843a5c 000000009c2c303d119c84a838c92620 c2f2b990363109ef6b76f7ea5a843a5c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.u32.f64 s7, d31 57b0cac51fbe40c857b0cac51fbe40c8 5ffe45c8eb122bb1fbace0931a246d86 ffffffff1fbe40c857b0cac51fbe40c8 5ffe45c8eb122bb1fbace0931a246d86 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.u32.f64 s7, d31 4637ace365dd9a9c59f45f66edb523c4 20036df61fdd358e98b957f3cd2bdf11 0000000165dd9a9c59f45f66edb523c4 20036df61fdd358e98b957f3cd2bdf11 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.u32.f64 s7, d31 0b11b6a8482646a40b11b6a8482646a4 d4713e8a1bf44560c0100380c0df4435 00000000482646a40b11b6a8482646a4 d4713e8a1bf44560c0100380c0df4435 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.u32.f64 s7, d31 33b12c36462268c633b12c36462268c6 ad529eae364043d3a3b29b942c67debe 00000000462268c633b12c36462268c6 ad529eae364043d3a3b29b942c67debe fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.u32.f64 s7, d31 01c47598dfd6679c01c47598dfd6679c 8e8b67641a87f91489e7aaa3047e895e 00000000dfd6679c01c47598dfd6679c 8e8b67641a87f91489e7aaa3047e895e fpscr=00000000
+vcvtp.u32.f64 s7, d31 3563168028dd3b30e50884bbe5428805 6ed9fb74f9a0c03adf3afa5b66c3a5ac ffffffff28dd3b30e50884bbe5428805 6ed9fb74f9a0c03adf3afa5b66c3a5ac fpscr=00000000
+vcvtp.u32.f64 s7, d31 23f9cabdebb84d90d16ad110085519d0 cf59828c4166820abc66cf712f5812ac 00000000ebb84d90d16ad110085519d0 cf59828c4166820abc66cf712f5812ac fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.u32.f64 s7, d31 412269d768875e50ff6863e1b15411e3 fba81d17b83c746afba81d17b83c746a 0000000068875e50ff6863e1b15411e3 fba81d17b83c746afba81d17b83c746a fpscr=00000000
+vcvtp.u32.f64 s7, d31 ff13b97b01acfbcd828f85ef540af22b cdfd52297790487a0fee6e002055981f 0000000001acfbcd828f85ef540af22b cdfd52297790487a0fee6e002055981f fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.u32.f64 s7, d31 0bd9fc215cb614a3d00f17db9800201f 9ee225edf0c04506d3147322f620988b 000000005cb614a3d00f17db9800201f 9ee225edf0c04506d3147322f620988b fpscr=00000000
+vcvtp.u32.f64 s7, d31 3882a82ec609faae5a2f0f6f0569fd91 86b4931f71c7dafbdd23b40e12e33cd6 00000000c609faae5a2f0f6f0569fd91 86b4931f71c7dafbdd23b40e12e33cd6 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtp.u32.f64 s7, d31 de3cdb3dc4e8706807eb6217fc14edbb dc590213d90c87df6dc3e206cd87cf91 00000000c4e8706807eb6217fc14edbb dc590213d90c87df6dc3e206cd87cf91 fpscr=00000000
+vcvtp.u32.f64 s7, d31 97468b51e66c33035a27c559bd6136fa 173c1a968773c07c6f51f1b1bd3ca104 00000001e66c33035a27c559bd6136fa 173c1a968773c07c6f51f1b1bd3ca104 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.u32.f64 s7, d31 97ebec7e10288f1897ebec7e10288f18 343f2fd3bfc23ebdf65ecbeeb18183d4 0000000110288f1897ebec7e10288f18 343f2fd3bfc23ebdf65ecbeeb18183d4 fpscr=00000000
+vcvtp.u32.f64 s7, d31 a5dddfa15a4786f05f6e4f2ddbd2d153 9938b063c6fb7e6b1daa1b7b80e5db7f 000000005a4786f05f6e4f2ddbd2d153 9938b063c6fb7e6b1daa1b7b80e5db7f fpscr=00000000
+vcvtp.u32.f64 s7, d31 2a2750826174f35ed4733d9629a9c545 77ee6d69f581fa08a2e1a5ced8d6120f ffffffff6174f35ed4733d9629a9c545 77ee6d69f581fa08a2e1a5ced8d6120f fpscr=00000000
+vcvtp.u32.f64 s7, d31 a602d8608e8ec07c162970ce819f8882 67c5d4ca56f1efc04a9b9a2faa51845d ffffffff8e8ec07c162970ce819f8882 67c5d4ca56f1efc04a9b9a2faa51845d fpscr=00000000
+vcvtp.u32.f64 s7, d31 acfb77e47bcd377770f2305623ddb7d0 1e242bfffe6298bdbbc924af78e56f37 000000017bcd377770f2305623ddb7d0 1e242bfffe6298bdbbc924af78e56f37 fpscr=00000000
+vcvtp.u32.f64 s7, d31 bf5b81b951ea7df5b4528b7c3031fff2 3ebe2f6c0153ea1e893b4ebd87d8ee94 0000000151ea7df5b4528b7c3031fff2 3ebe2f6c0153ea1e893b4ebd87d8ee94 fpscr=00000000
+vcvtp.u32.f64 s7, d31 7e2bd1de8a3c6b81a030cee3b1703451 fe34971a3eec314f2784ba21eab1d62b 000000008a3c6b81a030cee3b1703451 fe34971a3eec314f2784ba21eab1d62b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.u32.f64 s7, d31 231066d41abcc6d7a5f358f4faaeca8f c12068c40da490bbb042414a6f177967 000000001abcc6d7a5f358f4faaeca8f c12068c40da490bbb042414a6f177967 fpscr=00000000
+vcvtp.u32.f64 s7, d31 bfbb6d0850a9f1dbcf150c81d2287161 c1ae7a763f58cb4c5be79bc3750c7320 0000000050a9f1dbcf150c81d2287161 c1ae7a763f58cb4c5be79bc3750c7320 fpscr=00000000
+vcvtp.u32.f64 s7, d31 6c66e70a0de9e5473dc87c19c43db55a f401034f63c24c6e5de4430df8af87f0 000000000de9e5473dc87c19c43db55a f401034f63c24c6e5de4430df8af87f0 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtp.u32.f64 s7, d31 7db28c823b6af7847db28c823b6af784 8c2fd5104309ce2c2617eb275940c36c 000000003b6af7847db28c823b6af784 8c2fd5104309ce2c2617eb275940c36c fpscr=00000000
+vcvtp.u32.f64 s7, d31 4c5050f8ccb0b0fdf66bda60af8bb66e 8c4e84f243d4038ce0feedbd3360393d 00000000ccb0b0fdf66bda60af8bb66e 8c4e84f243d4038ce0feedbd3360393d fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 892d65a4f3e6eff6892d65a4f3e6eff6 18dfed002a791892cf9f0006b3e4f479 18dfed002a79189200000000b3e4f479 18dfed002a79189200000000b3e4f479 fpscr=00000000
+vcvtm.u32.f64 s1, d0 07810bec72e8b020e83df729baffa125 5b99fa2acf60035baedb734811bfee65 5b99fa2acf60035b0000000011bfee65 5b99fa2acf60035b0000000011bfee65 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 7dc577ffee0a85fc6811f5b943eb0972 882f111930e2201b9e10339accc1ea92 882f111930e2201b00000000ccc1ea92 882f111930e2201b00000000ccc1ea92 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 c83ae7439f777e71bd96ea61bc7413c3 2420c4b672f6327b170c3cee0d58bfdf 2420c4b672f6327b000000000d58bfdf 2420c4b672f6327b000000000d58bfdf fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.u32.f64 s1, d0 e9234cf1c432425f5795e1cd5a11437c 3c2201955a60b8eedf35a2989d4750a4 3c2201955a60b8ee000000009d4750a4 3c2201955a60b8ee000000009d4750a4 fpscr=00000000
+vcvtm.u32.f64 s1, d0 82e87ec008860e06f8c9baabe4ee9360 6d8e515d40cf0f4c82cfb67b212b60af 6d8e515d40cf0f4c00000000212b60af 6d8e515d40cf0f4c00000000212b60af fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 ff086dd456b47ae2ff086dd456b47ae2 19377cc8b5f9d277e4ef1dff7456f62d 19377cc8b5f9d277000000007456f62d 19377cc8b5f9d277000000007456f62d fpscr=00000000
+vcvtm.u32.f64 s1, d0 2582e062985a26bb5bf69720305e23a2 b58052df59e12edef2ad125a0118b2d2 b58052df59e12ede000000000118b2d2 b58052df59e12ede000000000118b2d2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 e9f2d3c71a47e71ee9f2d3c71a47e71e 62f8b963423caeec09d72018081dd321 62f8b963423caeec00000000081dd321 62f8b963423caeec00000000081dd321 fpscr=00000000
+vcvtm.u32.f64 s1, d0 542b331bba5d78950a07d5e81a439997 c9979d0006b3a68a903c67a8d50f2c9c c9979d0006b3a68a00000000d50f2c9c c9979d0006b3a68a00000000d50f2c9c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 344fd0f849e5ccef344fd0f849e5ccef 1045592d21459ecda406ff99adba81bc 1045592d21459ecd00000000adba81bc 1045592d21459ecd00000000adba81bc fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.u32.f64 s1, d0 6d3b8eec070db5666d3b8eec070db566 f81cc36b265d9629ce2ed4eea76916ef f81cc36b265d962900000000a76916ef f81cc36b265d962900000000a76916ef fpscr=00000000
+vcvtm.u32.f64 s1, d0 4956998acb4f88bb16d188b26f655079 945ccf68430880f007ec132cace3ba97 945ccf68430880f000000000ace3ba97 945ccf68430880f000000000ace3ba97 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 2b3220d24fc1e5dbd5a9e4c2b02034de 1530d4173fa68c202204bb70e75be92c 1530d4173fa68c2000000000e75be92c 1530d4173fa68c2000000000e75be92c fpscr=00000000
+vcvtm.u32.f64 s1, d0 eed5cd278c770a25e59d68b559b9b40a 167c53c3b309029252fb23fbfb039658 167c53c3b3090292fffffffffb039658 167c53c3b3090292fffffffffb039658 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 d76bf686a1733ab3f0fb3d818bffbbc6 2fc3eae0c27528be3e4c180921be0ee5 2fc3eae0c27528be0000000021be0ee5 2fc3eae0c27528be0000000021be0ee5 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 de9fa8fe9b1b3183eef591ed9dd26ea1 7d6ab3df1dfd29a97d6ab3df1dfd29a9 7d6ab3df1dfd29a9ffffffff1dfd29a9 7d6ab3df1dfd29a9ffffffff1dfd29a9 fpscr=00000000
+vcvtm.u32.f64 s1, d0 1f8d8cdcd6b9778eff562077cfc8f12c cb3e8a0132957fea83ce4d17f950c640 cb3e8a0132957fea00000000f950c640 cb3e8a0132957fea00000000f950c640 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.u32.f64 s1, d0 8175757c10e82a0800c340e005a3717f 74ebf60c77eea16b74ebf60c77eea16b 74ebf60c77eea16bffffffff77eea16b 74ebf60c77eea16bffffffff77eea16b fpscr=00000000
+vcvtm.u32.f64 s1, d0 0d2f4a22d659c6e1d20afb8edb8bc381 51b77a1606ac007981ed7270b0fddadc 51b77a1606ac007900000000b0fddadc 51b77a1606ac007900000000b0fddadc fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.u32.f64 s1, d0 e3548943a46532bae3548943a46532ba 113201188121f85a113201188121f85a 113201188121f85a000000008121f85a 113201188121f85a000000008121f85a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: 5888 calls, 6066 iters
+vcvtm.u32.f64 s1, d0 9b000ae7ed5e3ce19b000ae7ed5e3ce1 49ec35e51be3327af30e5b5a2e51cf09 49ec35e51be3327a000000002e51cf09 49ec35e51be3327a000000002e51cf09 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 6679e7a289ffa61c6679e7a289ffa61c b35b58f8f94a1228ec73b29efd9cdcd8 b35b58f8f94a122800000000fd9cdcd8 b35b58f8f94a122800000000fd9cdcd8 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.u32.f64 s1, d0 616f0b7dfabe909b616f0b7dfabe909b 3c64469fa1d882b5bc9b5d080cc5ec3f 3c64469fa1d882b5000000000cc5ec3f 3c64469fa1d882b5000000000cc5ec3f fpscr=00000000
+vcvtm.u32.f64 s1, d0 16d08d0d22f3c63cce9e6f2d2586d884 f1478fe367db84d41bc55d07363548a0 f1478fe367db84d400000000363548a0 f1478fe367db84d400000000363548a0 fpscr=00000000
+vcvtm.u32.f64 s1, d0 e0ccc6ecb2db4f1851cd6d7ab8d775b9 a42c78bc3806e718c4eb8936c582b889 a42c78bc3806e71800000000c582b889 a42c78bc3806e71800000000c582b889 fpscr=00000000
+vcvtm.u32.f64 s1, d0 7db70441bb6f09c44fdf308c34d8144c 0b0d3a71819d7ad8b5be10a3a1251850 0b0d3a71819d7ad800000000a1251850 0b0d3a71819d7ad800000000a1251850 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 6a9202fc94bb5a77a590479acc3b0eca 7351aa78ae67c6800b9652a9cb4f6963 7351aa78ae67c68000000000cb4f6963 7351aa78ae67c68000000000cb4f6963 fpscr=00000000
+vcvtm.u32.f64 s1, d0 f5600dd799523a619a562c49a9236aa2 921931e76d48ecc11227b833d4b68e81 921931e76d48ecc100000000d4b68e81 921931e76d48ecc100000000d4b68e81 fpscr=00000000
+vcvtm.u32.f64 s1, d0 d9f254a79b04e53c7b2c060295c4ade1 071b7dc7e1dc1230a56ce96e6b40c8fd 071b7dc7e1dc1230000000006b40c8fd 071b7dc7e1dc1230000000006b40c8fd fpscr=00000000
+vcvtm.u32.f64 s1, d0 7b3ab82bb153d879689f1157d756a9a6 56846c7e841c24fc153d41842e010e29 56846c7e841c24fc000000002e010e29 56846c7e841c24fc000000002e010e29 fpscr=00000000
+vcvtm.u32.f64 s1, d0 e6bcd2caba6f421b1f10ef793c90718a ca1d8e77afae88ef3ca9fffa8f1e1fc4 ca1d8e77afae88ef000000008f1e1fc4 ca1d8e77afae88ef000000008f1e1fc4 fpscr=00000000
+vcvtm.u32.f64 s1, d0 5d0bd0acfd52488fdbc67c0f018a7805 bfe05eed941ac584fa331fc890a46fa2 bfe05eed941ac5840000000090a46fa2 bfe05eed941ac5840000000090a46fa2 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.u32.f64 s1, d0 ebd3d4d3dc66876324306c8ebfa04666 9509c4c4d4f9abe265211c7796f390e9 9509c4c4d4f9abe2ffffffff96f390e9 9509c4c4d4f9abe2ffffffff96f390e9 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 10f430e3ce3b32895f8c6f5d798fcbe9 375987b309fdfd4d7603d9bd66a91f1c 375987b309fdfd4dffffffff66a91f1c 375987b309fdfd4dffffffff66a91f1c fpscr=00000000
+vcvtm.u32.f64 s1, d0 38d6d018799ec9ac8e42a48183efe0f9 810a7bd9d120e81edfde3bfca012a902 810a7bd9d120e81e00000000a012a902 810a7bd9d120e81e00000000a012a902 fpscr=00000000
+vcvtm.u32.f64 s1, d0 7890e60715834ef9dac52aa5731254c1 2d14393350022777825658854ec7f74f 2d14393350022777000000004ec7f74f 2d14393350022777000000004ec7f74f fpscr=00000000
+vcvtm.u32.f64 s1, d0 4e9cd43e5d8b8fe134cd021f2074143e f5cff071790d5848447488c4d127e86c f5cff071790d5848ffffffffd127e86c f5cff071790d5848ffffffffd127e86c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 74f7b4f7538a6cf974f7b4f7538a6cf9 9458e4384e1ffa93efcc72568a3a156b 9458e4384e1ffa93000000008a3a156b 9458e4384e1ffa93000000008a3a156b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 4bcd55082881d5bf4e441a4f4fe2c073 bf40230a2c07c6cbc5e9b072da0e90af bf40230a2c07c6cb00000000da0e90af bf40230a2c07c6cb00000000da0e90af fpscr=00000000
+vcvtm.u32.f64 s1, d0 c070c0be51039448c1d11adfcea9b37c 79fa9bf9956561e73ace0cb1f452c6b9 79fa9bf9956561e700000000f452c6b9 79fa9bf9956561e700000000f452c6b9 fpscr=00000000
+vcvtm.u32.f64 s1, d0 2e31edbadc9340dd9aa47766100acf72 05bb4a9a602074ec4bc0c93f6ccd14b7 05bb4a9a602074ecffffffff6ccd14b7 05bb4a9a602074ecffffffff6ccd14b7 fpscr=00000000
+vcvtm.u32.f64 s1, d0 652477b7bee5e8cd2621f1cdecb35407 1fd13b00ab3f5474becd70a7cafbd7a9 1fd13b00ab3f547400000000cafbd7a9 1fd13b00ab3f547400000000cafbd7a9 fpscr=00000000
+vcvtm.u32.f64 s1, d0 5739c22488da1f0236afc08c7260708a e8dc7b6cda0c2e746a056a698381cf6b e8dc7b6cda0c2e74ffffffff8381cf6b e8dc7b6cda0c2e74ffffffff8381cf6b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 c6919bcec564b894c6919bcec564b894 81bba4ccc84e75a4b6de2f6279c5ab6c 81bba4ccc84e75a40000000079c5ab6c 81bba4ccc84e75a40000000079c5ab6c fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 088c23ae3ed6fa689a1c45b099514758 ee09f8d98b208700ee09f8d98b208700 ee09f8d98b208700000000008b208700 ee09f8d98b208700000000008b208700 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vcvtm.u32.f64 s1, d0 39387fee4994b24239387fee4994b242 8d88561f3f617cbb71dc485b240f5e77 8d88561f3f617cbbffffffff240f5e77 8d88561f3f617cbbffffffff240f5e77 fpscr=00000000
+vcvtm.u32.f64 s1, d0 51f4908912f3897b54a5be94773e38b8 e14c6440c6c49039a4275b34e931f627 e14c6440c6c4903900000000e931f627 e14c6440c6c4903900000000e931f627 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vcvtm.u32.f64 s1, d0 6ad6b3c15370b696a2213e5d8cf6786c b55025cfbac313bea4daf4c1f6eebc77 b55025cfbac313be00000000f6eebc77 b55025cfbac313be00000000f6eebc77 fpscr=00000000
+vcvtm.u32.f64 s1, d0 45e2bcd8c59aee7c3dfec01badaba048 57f99a5c2f8b1ce96b631a5f89046297 57f99a5c2f8b1ce9ffffffff89046297 57f99a5c2f8b1ce9ffffffff89046297 fpscr=00000000
+vcvtn.u32.f32 s27, s5 f361d94ea4c8730f01619b46a6ca7a56 07613c35a97ab6bf4cbd70e4ee4f60fe 05eb8720a4c8730f01619b46a6ca7a56 07613c35a97ab6bf4cbd70e4ee4f60fe fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[1]
+vcvtn.u32.f32 s27, s5 71ed814b6b008206bd09f1c171ed814b d558ee7fe8088c57aa9ae42d84a27db4 000000006b008206bd09f1c171ed814b d558ee7fe8088c57aa9ae42d84a27db4 fpscr=00000000
+vcvtn.u32.f32 s27, s5 f365e620505c7f2cab20c8574c9f70ef 34bb15d0277193c2bb491c1391adf07d 00000000505c7f2cab20c8574c9f70ef 34bb15d0277193c2bb491c1391adf07d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtn.u32.f32 s27, s5 446fbd95acb8699771b4e0a7db59b3aa 0d5c51e20d5c51e2726e3566fc82ae7a ffffffffacb8699771b4e0a7db59b3aa 0d5c51e20d5c51e2726e3566fc82ae7a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtn.u32.f32 s27, s5 c81c24130afe1c99fc863ccc37dd0c42 09d572be21acfdd14037b5d323488cb4 000000030afe1c99fc863ccc37dd0c42 09d572be21acfdd14037b5d323488cb4 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtn.u32.f32 s27, s5 1a2dde68caca5ea8dc5fc16ddb5db496 a91722ce4106f4b6adf7aafacb69aa0b 00000000caca5ea8dc5fc16ddb5db496 a91722ce4106f4b6adf7aafacb69aa0b fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtn.u32.f32 s27, s5 ce6eb6abb84f97187f2d789712376e41 68656e571ec58105959df98d03abc543 00000000b84f97187f2d789712376e41 68656e571ec58105959df98d03abc543 fpscr=00000000
+vcvtn.u32.f32 s27, s5 2fc3a22f79ebdd442df05474c14061cf 232a576e7d487fa8e4f8849b2c63c171 0000000079ebdd442df05474c14061cf 232a576e7d487fa8e4f8849b2c63c171 fpscr=00000000
+vcvtn.u32.f32 s27, s5 851833d0c300af1fd871d8e3dab478b4 2008f48ced0bb9b91bcb4b333d38a67a 00000000c300af1fd871d8e3dab478b4 2008f48ced0bb9b91bcb4b333d38a67a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtn.u32.f32 s27, s5 1e8c4213a7b527db11e698bb0be2b921 fd9146dbfd9146dbcaff7b785efa38bc 00000000a7b527db11e698bb0be2b921 fd9146dbfd9146dbcaff7b785efa38bc fpscr=00000000
+vcvtn.u32.f32 s27, s5 0a253528a2150a1650032a79ac617953 62e3e468aa8ae1839c021b53f5d49a65 00000000a2150a1650032a79ac617953 62e3e468aa8ae1839c021b53f5d49a65 fpscr=00000000
+vcvtn.u32.f32 s27, s5 d53d9da0d052ddf946535d24061d6d41 4197b833b6434424687d5cd9db421e8f ffffffffd052ddf946535d24061d6d41 4197b833b6434424687d5cd9db421e8f fpscr=00000000
+vcvtn.u32.f32 s27, s5 fac3aadc64ab98b854f1a320be430e29 53bb5810d4057c16be78cb2c06c5d0dd 0000000064ab98b854f1a320be430e29 53bb5810d4057c16be78cb2c06c5d0dd fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtn.u32.f32 s27, s5 1ff168b265ff9e44102110504199bd53 9c67ac4476e6f9156fe1397c08fe7548 ffffffff65ff9e44102110504199bd53 9c67ac4476e6f9156fe1397c08fe7548 fpscr=00000000
+vcvtn.u32.f32 s27, s5 45f5b4a25a386b1f5abf64334b3dd1d9 ebd32f0b0d95a9b2cc9b285e29cb730b 000000005a386b1f5abf64334b3dd1d9 ebd32f0b0d95a9b2cc9b285e29cb730b fpscr=00000000
+vcvtn.u32.f32 s27, s5 123f632051e479b3408c89bb9462d8be 82a22227b99a1507766c2a0872b1c801 ffffffff51e479b3408c89bb9462d8be 82a22227b99a1507766c2a0872b1c801 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtn.u32.f32 s27, s5 66b6b0b9ca33c90a7f352e07dcdc5924 a468b3480411c773b7fdb6acbaef8047 00000000ca33c90a7f352e07dcdc5924 a468b3480411c773b7fdb6acbaef8047 fpscr=00000000
+vcvtn.u32.f32 s27, s5 d839ff0b50cf99534bd7d2af1d6db149 aa8a5512cfe8f5065371cec9cde548da ffffffff50cf99534bd7d2af1d6db149 aa8a5512cfe8f5065371cec9cde548da fpscr=00000000
+vcvtn.u32.f32 s27, s5 5dc912a76c547d2a03452cfeb2050b14 ec0237faf52b36e55a49037b591d3eaa ffffffff6c547d2a03452cfeb2050b14 ec0237faf52b36e55a49037b591d3eaa fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.u32.f32 s27, s5 2eb7937abb9c85b8486a473d40c0fd18 7c9439b7b16b2fa773ccaafeb16b2fa7 ffffffffbb9c85b8486a473d40c0fd18 7c9439b7b16b2fa773ccaafeb16b2fa7 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtn.u32.f32 s27, s5 0b0274a08648b6c74f0df25f6ff56d67 13b067be1d55745aba8d0c2bbc520083 000000008648b6c74f0df25f6ff56d67 13b067be1d55745aba8d0c2bbc520083 fpscr=00000000
+vcvtn.u32.f32 s27, s5 9ab04df1c694c1a6e31fc031e3690161 c4d75a3c4f9873301c86566fcf7464cd 00000000c694c1a6e31fc031e3690161 c4d75a3c4f9873301c86566fcf7464cd fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtn.u32.f32 s27, s5 fa54a3bd603c39d7a99922a19d7abeb5 1664374e46f2a8cb96b316b2e0326326 00000000603c39d7a99922a19d7abeb5 1664374e46f2a8cb96b316b2e0326326 fpscr=00000000
+vcvtn.u32.f32 s27, s5 d6f469b35b0e249b632fd45c6682eae7 c9a1fb8fb0217f13e3dbe1fc9f48ffa8 000000005b0e249b632fd45c6682eae7 c9a1fb8fb0217f13e3dbe1fc9f48ffa8 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtn.u32.f32 s27, s5 c788c93b0b02558d52bcfd170dbf4e76 a37263ce589f878f78368020a0b034c3 ffffffff0b02558d52bcfd170dbf4e76 a37263ce589f878f78368020a0b034c3 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtn.u32.f32 s27, s5 10195cec0f4f6ed1f0c89a8ba803b7fd 4399f070a08937bf4399f070e5af74b1 000001340f4f6ed1f0c89a8ba803b7fd 4399f070a08937bf4399f070e5af74b1 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[1]
+vcvtn.u32.f32 s27, s5 82f1f476cf03702882f1f476bf821f3b 7d910a60b1351f51c9d358eac9d358ea 00000000cf03702882f1f476bf821f3b 7d910a60b1351f51c9d358eac9d358ea fpscr=00000000
+vcvtn.u32.f32 s27, s5 bcd169747bae3c9f3b4c6abc0a99cf85 df2a41411bc500ac2f1278693d5b5ebc 000000007bae3c9f3b4c6abc0a99cf85 df2a41411bc500ac2f1278693d5b5ebc fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.u32.f32 s27, s5 6ce79e70a1aea1cca1aea1cc2b362fb0 1d0a3759027c438abeab202573e9d94d 00000000a1aea1cca1aea1cc2b362fb0 1d0a3759027c438abeab202573e9d94d fpscr=00000000
+vcvtn.u32.f32 s27, s5 cc7d9ada21659e79481ad905634f747a ae756c8373766f409d93173f89bfd8e7 0000000021659e79481ad905634f747a ae756c8373766f409d93173f89bfd8e7 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[2]
+vcvtn.u32.f32 s27, s5 6da48ae99a7d9f926da48ae9cf584b45 e068c91f84ffb47a901840f0d83be984 000000009a7d9f926da48ae9cf584b45 e068c91f84ffb47a901840f0d83be984 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[1]
+vcvtn.u32.f32 s27, s5 49ed52ecb6164fc876412660543d6fd3 ac0e51fc2ac9b9dd2ac9b9dd8421b639 00000000b6164fc876412660543d6fd3 ac0e51fc2ac9b9dd2ac9b9dd8421b639 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[2]
+vcvtn.u32.f32 s27, s5 dc8a28e97283ba547283ba54b5e89125 019d6d2b8ab49b4f87f518f9376b27fc 000000007283ba547283ba54b5e89125 019d6d2b8ab49b4f87f518f9376b27fc fpscr=00000000
+vcvtn.u32.f32 s27, s5 8f898f4a4826e314b707fabc3556c142 1834fd46eb2d769acd00cd3811c9341b 000000004826e314b707fabc3556c142 1834fd46eb2d769acd00cd3811c9341b fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtn.u32.f32 s27, s5 48d1a6017208c0a3da7b438139a136ad 34028be834028be8a464245041576366 000000007208c0a3da7b438139a136ad 34028be834028be8a464245041576366 fpscr=00000000
+randV128: 6144 calls, 6328 iters
+vcvtn.u32.f32 s27, s5 c66d8b22067087c136d7d66567829198 f022b699a7fca58fd65bb4890e783c76 00000000067087c136d7d66567829198 f022b699a7fca58fd65bb4890e783c76 fpscr=00000000
+vcvtn.u32.f32 s27, s5 d81144ffdeb27d6af9eb6566ab9a9cff 81fcee6f2c3da8dda1afab084685f9ab 00000000deb27d6af9eb6566ab9a9cff 81fcee6f2c3da8dda1afab084685f9ab fpscr=00000000
+vcvtn.u32.f32 s27, s5 6b614674e686aeec766f0d9c1f18c41d de621b46ab8121941fd0eaf79c0dbcba 00000000e686aeec766f0d9c1f18c41d de621b46ab8121941fd0eaf79c0dbcba fpscr=00000000
+vcvtn.u32.f32 s27, s5 f6378388ee4f3b1783f894586f041a17 eeb2eccba607f0d5020daaec2abdddc8 00000000ee4f3b1783f894586f041a17 eeb2eccba607f0d5020daaec2abdddc8 fpscr=00000000
+vcvtn.u32.f32 s27, s5 e2e02e17497d441aed206a2f8fc9d6a3 5bb4dca50c8bdbfd722182d5e77fea57 ffffffff497d441aed206a2f8fc9d6a3 5bb4dca50c8bdbfd722182d5e77fea57 fpscr=00000000
+vcvtn.u32.f32 s27, s5 a24bd6efe914d34162274dbfa2903028 d6b916c1c8a1de05eac0492320105169 00000000e914d34162274dbfa2903028 d6b916c1c8a1de05eac0492320105169 fpscr=00000000
+vcvtn.u32.f32 s27, s5 93fd399b84a0972b4764716b5266a1f1 baf5308c47a47eccfab206f51a66dc66 0000000084a0972b4764716b5266a1f1 baf5308c47a47eccfab206f51a66dc66 fpscr=00000000
+vcvtn.u32.f32 s27, s5 1c6a44aad0b6bef92bf486d2d4851804 5fec30c9770067453a6b5d5e4f8af6c5 00000000d0b6bef92bf486d2d4851804 5fec30c9770067453a6b5d5e4f8af6c5 fpscr=00000000
+vcvtn.u32.f32 s27, s5 898fd54e44d21cda2a5c5780f82704c6 22523845c0ff3b57d5bf83ea8f7093d7 0000000044d21cda2a5c5780f82704c6 22523845c0ff3b57d5bf83ea8f7093d7 fpscr=00000000
+vcvtn.u32.f32 s27, s5 13ff95e610b186103ef54fd3fecf6512 4463ef6debba5745bffc7897b29264dc 0000000010b186103ef54fd3fecf6512 4463ef6debba5745bffc7897b29264dc fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtn.u32.f32 s27, s5 d8e97adeb383fae77e3c381869b43c73 285615568831835330a1d71d88318353 00000000b383fae77e3c381869b43c73 285615568831835330a1d71d88318353 fpscr=00000000
+vcvtn.u32.f32 s27, s5 67982e16320bae6df1f42599b0fd668c 82870b447138ee1f28c37cca06758697 00000000320bae6df1f42599b0fd668c 82870b447138ee1f28c37cca06758697 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[2]
+vcvtn.u32.f32 s27, s5 8ed899ae6d7ad72e2b20460a3d643b35 a73a48d5a73a48d5b39829702e0a15f7 000000006d7ad72e2b20460a3d643b35 a73a48d5a73a48d5b39829702e0a15f7 fpscr=00000000
+vcvtn.u32.f32 s27, s5 b35ec515b16446153ba3c22bd2b71514 8e12c0008174823ab70380ad9b1dd5a1 00000000b16446153ba3c22bd2b71514 8e12c0008174823ab70380ad9b1dd5a1 fpscr=00000000
+vcvtn.u32.f32 s27, s5 49276c8639e7ed7f38989f3ebc53a295 ca16ca0bd30653b8d4f9441ee80b194d 0000000039e7ed7f38989f3ebc53a295 ca16ca0bd30653b8d4f9441ee80b194d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.u32.f32 s4, s20 facddafffacddaff0cfec6510d265b0a ec345b3df19253fa3a77fefe0e186705 facddafffacddaff0cfec65100000000 ec345b3df19253fa3a77fefe0e186705 fpscr=00000000
+vcvta.u32.f32 s4, s20 019b767b5899b2fc3430009c7f560a05 607133e9b488ae99df1a2720471b70db 019b767b5899b2fc3430009c00009b71 607133e9b488ae99df1a2720471b70db fpscr=00000000
+vcvta.u32.f32 s4, s20 d5887b7953d02db16dd911073a354a7f a43c45c4c2784ed4c5ef14554047a868 d5887b7953d02db16dd9110700000003 a43c45c4c2784ed4c5ef14554047a868 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvta.u32.f32 s4, s20 f936b1ba86a6bfe9ee640b78fe33f84e a7108efbd9af5d4f52c6a43a6cc12db0 f936b1ba86a6bfe9ee640b78ffffffff a7108efbd9af5d4f52c6a43a6cc12db0 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.u32.f32 s4, s20 3a6706966e1c586de801567e72ff8429 207e2fb63b0fb7de0c1bfe644616a239 3a6706966e1c586de801567e000025a9 207e2fb63b0fb7de0c1bfe644616a239 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvta.u32.f32 s4, s20 334e5ed0334e5ed06fcdde227d898814 68c8e285c4ebe959e323e822a7332545 334e5ed0334e5ed06fcdde2200000000 68c8e285c4ebe959e323e822a7332545 fpscr=00000000
+vcvta.u32.f32 s4, s20 b1fb7ac38b2564391ce0127b9c1e98d1 43e9a56f88ad43410670686a8170e0b5 b1fb7ac38b2564391ce0127b00000000 43e9a56f88ad43410670686a8170e0b5 fpscr=00000000
+vcvta.u32.f32 s4, s20 14be4c6ad8113401a2a3124890bf379e 3b3737c58195b2ae31e6f79cfbdad3dd 14be4c6ad8113401a2a3124800000000 3b3737c58195b2ae31e6f79cfbdad3dd fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.u32.f32 s4, s20 098b92d4eee3c76789c8551089c85510 78d5c454388bc451044cdfc2388bc451 098b92d4eee3c76789c8551000000000 78d5c454388bc451044cdfc2388bc451 fpscr=00000000
+vcvta.u32.f32 s4, s20 acd04fbc5097e6a0cfd6b37fddef694a 6237c0f5920b496ec2856c5b7c0cac8a acd04fbc5097e6a0cfd6b37fffffffff 6237c0f5920b496ec2856c5b7c0cac8a fpscr=00000000
+vcvta.u32.f32 s4, s20 8389ea5408cf98bec5055561815e2ad9 5b162088f01e75208648557c4486c98f 8389ea5408cf98bec505556100000436 5b162088f01e75208648557c4486c98f fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvta.u32.f32 s4, s20 be2ab989846dc1d49b2d877bd018d2ca 51fc85e6b14e546d079c10ecd3c7c9bb be2ab989846dc1d49b2d877b00000000 51fc85e6b14e546d079c10ecd3c7c9bb fpscr=00000000
+vcvta.u32.f32 s4, s20 96870ada29659ee18ec21d222fe2b5a6 b11654c96eb2a9d104bb6f03f0df701c 96870ada29659ee18ec21d2200000000 b11654c96eb2a9d104bb6f03f0df701c fpscr=00000000
+vcvta.u32.f32 s4, s20 19cd481d378f8e855c6ee33a729ab0f9 8c00dc75bdd98336d140a3643cab5a00 19cd481d378f8e855c6ee33a00000000 8c00dc75bdd98336d140a3643cab5a00 fpscr=00000000
+vcvta.u32.f32 s4, s20 59cf4f2bf4dd596b39d56916929fd1d3 a688b07cdf76b83a8d370871738a5c97 59cf4f2bf4dd596b39d56916ffffffff a688b07cdf76b83a8d370871738a5c97 fpscr=00000000
+vcvta.u32.f32 s4, s20 71354c56a52cd1a44e002f067cb97aed a215c38df55fd8363c2340bc820e425b 71354c56a52cd1a44e002f0600000000 a215c38df55fd8363c2340bc820e425b fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvta.u32.f32 s4, s20 3f91d4f2d38d61f86fd466300997aa4d 208887b5f7e9ba95f3eb607b03e8d2db 3f91d4f2d38d61f86fd4663000000000 208887b5f7e9ba95f3eb607b03e8d2db fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvta.u32.f32 s4, s20 90c4b7d1a6d07759aa55bc8f90c4b7d1 f250e1130aa3a6fee4713dc4180402d1 90c4b7d1a6d07759aa55bc8f00000000 f250e1130aa3a6fee4713dc4180402d1 fpscr=00000000
+vcvta.u32.f32 s4, s20 1924ac6e3181a51525503b9a6ffb2fef 4ac2ce646ccbe46c8d9b63bc7f7c7753 1924ac6e3181a51525503b9affffffff 4ac2ce646ccbe46c8d9b63bc7f7c7753 fpscr=00000000
+vcvta.u32.f32 s4, s20 bc2e1362d6bd5ceb84d193024a96878e 570d5071d8f35b1bb6388e52a93603ea bc2e1362d6bd5ceb84d1930200000000 570d5071d8f35b1bb6388e52a93603ea fpscr=00000000
+vcvta.u32.f32 s4, s20 54e5676011c0e5db192cbfffaf51b6d0 ca8c65fd0162610b2b23163f2f7542a6 54e5676011c0e5db192cbfff00000000 ca8c65fd0162610b2b23163f2f7542a6 fpscr=00000000
+vcvta.u32.f32 s4, s20 625d482dd56a15655a90a961c3d1b70b ab02adfb1e518a2ac6a386cea43260ae 625d482dd56a15655a90a96100000000 ab02adfb1e518a2ac6a386cea43260ae fpscr=00000000
+vcvta.u32.f32 s4, s20 0098492fe141185599f1d24e79fb3f55 f6be90891e406a7943d0081e07b2209b 0098492fe141185599f1d24e00000000 f6be90891e406a7943d0081e07b2209b fpscr=00000000
+vcvta.u32.f32 s4, s20 87b0c4d3411dc10678e7283d9aeb41bb 6e01e2626c0bb5ad4e36a970705fb622 87b0c4d3411dc10678e7283dffffffff 6e01e2626c0bb5ad4e36a970705fb622 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvta.u32.f32 s4, s20 7a5533cf0c56faca0c56faca1ad74528 e0c6312baf966adae56326fb94bd6be8 7a5533cf0c56faca0c56faca00000000 e0c6312baf966adae56326fb94bd6be8 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.u32.f32 s4, s20 8bc4da8442db9fc61668c5629da251a0 502c48ede90524a2b3c4a5e752c34549 8bc4da8442db9fc61668c562ffffffff 502c48ede90524a2b3c4a5e752c34549 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvta.u32.f32 s4, s20 144c2a5f19a03125a49c1b9b15997c3e ed3ba49c12d289d4c8832e7892771af6 144c2a5f19a03125a49c1b9b00000000 ed3ba49c12d289d4c8832e7892771af6 fpscr=00000000
+vcvta.u32.f32 s4, s20 e9ee00cb51216a3ea9d8463b877b7686 f5ec03b48b06cd6eb3e3a2d037b5f196 e9ee00cb51216a3ea9d8463b00000000 f5ec03b48b06cd6eb3e3a2d037b5f196 fpscr=00000000
+vcvta.u32.f32 s4, s20 d13a8d06906ba092b03de12ac9018ece cca90eb4fd9b448b17114a5b8b2901e4 d13a8d06906ba092b03de12a00000000 cca90eb4fd9b448b17114a5b8b2901e4 fpscr=00000000
+vcvta.u32.f32 s4, s20 822445b98ab9cb5ebd70dfc0e013b3dd a8bf34224238e6dba26906da4105fafa 822445b98ab9cb5ebd70dfc000000008 a8bf34224238e6dba26906da4105fafa fpscr=00000000
+vcvta.u32.f32 s4, s20 42bdac9c4fed523d4150af7ad3dd2033 4da48df8eb0821e211de4dffc2b72a01 42bdac9c4fed523d4150af7a00000000 4da48df8eb0821e211de4dffc2b72a01 fpscr=00000000
+vcvta.u32.f32 s4, s20 e58e61ee2873d094ef3b6cc255dd993a dd7621a3cd04eb3026bc8b851af82382 e58e61ee2873d094ef3b6cc200000000 dd7621a3cd04eb3026bc8b851af82382 fpscr=00000000
+vcvta.u32.f32 s4, s20 e848c4f55112593218fcc6acc3edf12a b8941a27f7320928c3859392393b526d e848c4f55112593218fcc6ac00000000 b8941a27f7320928c3859392393b526d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.u32.f32 s4, s20 e656f95ae656f95a5d984a937237efc4 6e443692d0a796364425e425ea7e0e88 e656f95ae656f95a5d984a9300000000 6e443692d0a796364425e425ea7e0e88 fpscr=00000000
+vcvta.u32.f32 s4, s20 04906c4555671c768a50c8fe019869ff 3ce6478fba4cb24a73008685f5fa86af 04906c4555671c768a50c8fe00000000 3ce6478fba4cb24a73008685f5fa86af fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvta.u32.f32 s4, s20 05bb31171a28910e7f0178507f017850 450a889ef2eb3888c79469f75d860b95 05bb31171a28910e7f017850ffffffff 450a889ef2eb3888c79469f75d860b95 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvta.u32.f32 s4, s20 a577c71cab6da7640a2221b5a577c71c 0ef5949b748db05e44bc4bd9c5f17552 a577c71cab6da7640a2221b500000000 0ef5949b748db05e44bc4bd9c5f17552 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.u32.f32 s4, s20 84312a6fb3c40798f58242f33e629aa7 0c30a043fd410697fd4106979f28b016 84312a6fb3c40798f58242f300000000 0c30a043fd410697fd4106979f28b016 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.u32.f32 s4, s20 51aa57f5441d8a54441d8a54e84119cd 98e034df62db756abf864d6ae008b9cd 51aa57f5441d8a54441d8a5400000000 98e034df62db756abf864d6ae008b9cd fpscr=00000000
+vcvta.u32.f32 s4, s20 1fa1d98801e9e90ee899b15e29549ad6 8c1058c92005415e972dd0974af86886 1fa1d98801e9e90ee899b15e007c3443 8c1058c92005415e972dd0974af86886 fpscr=00000000
+vcvta.u32.f32 s4, s20 64b9d1675128e6bbd10e3c4a7f1b4f93 088c240fbd1d86f17880ce0956375502 64b9d1675128e6bbd10e3c4affffffff 088c240fbd1d86f17880ce0956375502 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.u32.f32 s4, s20 d86689ad80aed34780aed3479ffb2118 fc81e4cb0478c48b5e78c5dd4bf20131 d86689ad80aed34780aed34701e40262 fc81e4cb0478c48b5e78c5dd4bf20131 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvta.u32.f32 s4, s20 ac1bf7ee5ef4f263ac1bf7ee73e78a94 210809f741bb4bc72275da37bc7ca647 ac1bf7ee5ef4f263ac1bf7ee00000000 210809f741bb4bc72275da37bc7ca647 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvta.u32.f32 s4, s20 3f5a5dd8fa1cfe25b440c99263ab6fa2 e86fc0fa3240f28b6e585550623094ca 3f5a5dd8fa1cfe25b440c992ffffffff e86fc0fa3240f28b6e585550623094ca fpscr=00000000
+vcvta.u32.f32 s4, s20 0277fb04da9112e2b4dc9aa316e7ca7f 58859be0011cd699bf93a4cb91842a90 0277fb04da9112e2b4dc9aa300000000 58859be0011cd699bf93a4cb91842a90 fpscr=00000000
+vcvta.u32.f32 s4, s20 b412e5a19b13aa695432f0cfbb8cdec4 a347e2b8ff7da47a4e7e3e96ca81ce1c b412e5a19b13aa695432f0cf00000000 a347e2b8ff7da47a4e7e3e96ca81ce1c fpscr=00000000
+vcvta.u32.f32 s4, s20 199dcbbbb0096c6702883bf07ed54279 e2a0daaa5ac95c25667a9f6f14474201 199dcbbbb0096c6702883bf000000000 e2a0daaa5ac95c25667a9f6f14474201 fpscr=00000000
+vcvta.u32.f32 s4, s20 5841b8fe3b72ba46586f037516378ff9 3d31e3f2fbe79f33d7afdd9ced5ceb9f 5841b8fe3b72ba46586f037500000000 3d31e3f2fbe79f33d7afdd9ced5ceb9f fpscr=00000000
+vcvta.u32.f32 s4, s20 14c4baf51e27745c3fd1e1537ad8c6fb 78174a67ef434289d5e97acd0f065fcb 14c4baf51e27745c3fd1e15300000000 78174a67ef434289d5e97acd0f065fcb fpscr=00000000
+randV128: 6400 calls, 6595 iters
+vcvta.u32.f32 s4, s20 a9c92c159be09c64f2dd57cb103c01ea 389aa0b779333fa3660a9a61c024c9d3 a9c92c159be09c64f2dd57cb00000000 389aa0b779333fa3660a9a61c024c9d3 fpscr=00000000
+vcvtp.u32.f32 s7, s31 23b12e5d8aee4dec3bb908271732ef1f 55f3da6105a1870612402b7fa87b4b84 ffffffff8aee4dec3bb908271732ef1f 55f3da6105a1870612402b7fa87b4b84 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.u32.f32 s7, s31 f733520d47143f1a09af8c43532f5d1c 3fede8f3c4e75ecff99fc20cc4e75ecf 0000000247143f1a09af8c43532f5d1c 3fede8f3c4e75ecff99fc20cc4e75ecf fpscr=00000000
+vcvtp.u32.f32 s7, s31 f3312a90ab639d0ddd332b2fefd06566 78935ff8f1bbd40485e4612fc9377369 ffffffffab639d0ddd332b2fefd06566 78935ff8f1bbd40485e4612fc9377369 fpscr=00000000
+vcvtp.u32.f32 s7, s31 a246bd589ea23aea7f4429c4adff8b6e cce07f8fb8737563b552ac3565df802b 000000009ea23aea7f4429c4adff8b6e cce07f8fb8737563b552ac3565df802b fpscr=00000000
+vcvtp.u32.f32 s7, s31 6674fa9341fdaed80420c14c1d152cbd 4e6dc8dc84cc7a66e833a5e7f18fb6c7 3b72370041fdaed80420c14c1d152cbd 4e6dc8dc84cc7a66e833a5e7f18fb6c7 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtp.u32.f32 s7, s31 b6411ec408a2f2490c0808bd886cd37d c124f962d180bc5130dea2de958afcb0 0000000008a2f2490c0808bd886cd37d c124f962d180bc5130dea2de958afcb0 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.u32.f32 s7, s31 d82058d99cffa5ac1cdea46bf2bae4c8 1a6184e202ff9de1c3ec7f07a3852ef4 000000019cffa5ac1cdea46bf2bae4c8 1a6184e202ff9de1c3ec7f07a3852ef4 fpscr=00000000
+vcvtp.u32.f32 s7, s31 34b5e0dc5ae0eff634e87c9c8d923d58 741a1740fc2a34dabc980ae75684383e ffffffff5ae0eff634e87c9c8d923d58 741a1740fc2a34dabc980ae75684383e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.u32.f32 s7, s31 a4f21c0119d5ecc7aea6afe3d24dd8a6 336609b8d40a8003336609b8834a469b 0000000119d5ecc7aea6afe3d24dd8a6 336609b8d40a8003336609b8834a469b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtp.u32.f32 s7, s31 91924fce91924fce402c5b347d3e0bc4 4c18f86704dab7a49ec2baf4626ae4b0 0263e19c91924fce402c5b347d3e0bc4 4c18f86704dab7a49ec2baf4626ae4b0 fpscr=00000000
+vcvtp.u32.f32 s7, s31 5605ecd70c87c8b255fe9a5e91883846 a4ca39c957d7a58fde7a273ab15bf896 000000000c87c8b255fe9a5e91883846 a4ca39c957d7a58fde7a273ab15bf896 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtp.u32.f32 s7, s31 ba4c2cda5a969e841035d79db772f9fa 96059222016fcebb9c59d5471b6fb323 000000005a969e841035d79db772f9fa 96059222016fcebb9c59d5471b6fb323 fpscr=00000000
+vcvtp.u32.f32 s7, s31 6f1c99bb3dffc11696b957f8a6b3406e 4c4cceb342c22601d0132c050a3b7a7e 03333acc3dffc11696b957f8a6b3406e 4c4cceb342c22601d0132c050a3b7a7e fpscr=00000000
+vcvtp.u32.f32 s7, s31 2951263be640d7a069fa4eb7b32f2d8a 935c1dd1680b9a7225357bfb3e71876c 00000000e640d7a069fa4eb7b32f2d8a 935c1dd1680b9a7225357bfb3e71876c fpscr=00000000
+vcvtp.u32.f32 s7, s31 1a7284fd658231318ee70bc18702428e 1c9aaebec28fb49f7eb1811e1cd3f6d4 00000001658231318ee70bc18702428e 1c9aaebec28fb49f7eb1811e1cd3f6d4 fpscr=00000000
+vcvtp.u32.f32 s7, s31 7af66b24ef4c2d73cf6c7f2a4572137f 06049a6bd90e83a691271b29ee20e497 00000001ef4c2d73cf6c7f2a4572137f 06049a6bd90e83a691271b29ee20e497 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.u32.f32 s7, s31 3621bcc80bdba25c4770ef864770ef86 d9ab4680de69825368153c453ff76005 000000000bdba25c4770ef864770ef86 d9ab4680de69825368153c453ff76005 fpscr=00000000
+vcvtp.u32.f32 s7, s31 91900adeec5fd49b6f3c670658439d4e 7afbec7fb7d4c9f306fa0ba393b5a520 ffffffffec5fd49b6f3c670658439d4e 7afbec7fb7d4c9f306fa0ba393b5a520 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtp.u32.f32 s7, s31 2c757eee538014fae61edab08e456cd6 dab0c6754e2333ed9ecf1f8660ef00d6 00000000538014fae61edab08e456cd6 dab0c6754e2333ed9ecf1f8660ef00d6 fpscr=00000000
+vcvtp.u32.f32 s7, s31 194e2ac1ca815a0b41a01f9003671bb9 a5b084e36a3cd6d76524c14b737aee7e 00000000ca815a0b41a01f9003671bb9 a5b084e36a3cd6d76524c14b737aee7e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtp.u32.f32 s7, s31 0408bfc18c2f89ae0408bfc148b9d321 2b5be864f5d39b4e01072abd680c82ce 000000018c2f89ae0408bfc148b9d321 2b5be864f5d39b4e01072abd680c82ce fpscr=00000000
+vcvtp.u32.f32 s7, s31 317d54051f5b6c4b74cdbf64ed287865 265becbbd4300de7d1cfdb646a274ef9 000000011f5b6c4b74cdbf64ed287865 265becbbd4300de7d1cfdb646a274ef9 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtp.u32.f32 s7, s31 2437cecb24b7979624b797967b2c914c 483cc146697a874d8dffd49f235f4f96 0002f30624b7979624b797967b2c914c 483cc146697a874d8dffd49f235f4f96 fpscr=00000000
+vcvtp.u32.f32 s7, s31 adce08ba767dde431e5dc68f754777a5 b0f91d5b36e32b2b862bb56624978b87 00000000767dde431e5dc68f754777a5 b0f91d5b36e32b2b862bb56624978b87 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.u32.f32 s7, s31 635ac79f34e735d534e735d5c704f766 1edbff30bd659a4de566e75937a4ff6d 0000000134e735d534e735d5c704f766 1edbff30bd659a4de566e75937a4ff6d fpscr=00000000
+vcvtp.u32.f32 s7, s31 7f47923522f98db443a040c64c516c43 52a62fd869779967e7a8a0076c708753 ffffffff22f98db443a040c64c516c43 52a62fd869779967e7a8a0076c708753 fpscr=00000000
+vcvtp.u32.f32 s7, s31 4061031035bad58728d05a6e16bed25d a1d6400a3fb39a2b89d51a313eccf2bb 0000000035bad58728d05a6e16bed25d a1d6400a3fb39a2b89d51a313eccf2bb fpscr=00000000
+vcvtp.u32.f32 s7, s31 7b145f499fd556485bf14d5561f3cf9f 11071036b53b69b166e860abfd9dff1a 000000019fd556485bf14d5561f3cf9f 11071036b53b69b166e860abfd9dff1a fpscr=00000000
+vcvtp.u32.f32 s7, s31 b67d8cf007d1ac7aa945a4522825e238 b98cf9a8ec9f73fd93cbe0353e464fc3 0000000007d1ac7aa945a4522825e238 b98cf9a8ec9f73fd93cbe0353e464fc3 fpscr=00000000
+vcvtp.u32.f32 s7, s31 550e98561e181db0d64c140a857675cc 89e1fe2ce9b16bf5eed6b66c1e939eb6 000000001e181db0d64c140a857675cc 89e1fe2ce9b16bf5eed6b66c1e939eb6 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtp.u32.f32 s7, s31 709751359ed67d903fc8bc6d70975135 d2cfc4ecbc88087dd9ccca8cec9b5e0d 000000009ed67d903fc8bc6d70975135 d2cfc4ecbc88087dd9ccca8cec9b5e0d fpscr=00000000
+vcvtp.u32.f32 s7, s31 56588e1753bb035114663621c346945d 9b26ace0e09edd66e4be6abd26b7e6bb 0000000053bb035114663621c346945d 9b26ace0e09edd66e4be6abd26b7e6bb fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtp.u32.f32 s7, s31 1d6a865aa4fbb41a2e12e1faa97722a5 c5d47a87dee0fc9fc5d47a8735b4d2ee 00000000a4fbb41a2e12e1faa97722a5 c5d47a87dee0fc9fc5d47a8735b4d2ee fpscr=00000000
+vcvtp.u32.f32 s7, s31 af8eca2071b15d364c94e727e05b7815 dd9d4e5e1eee6fe5377867680e7a61d0 0000000071b15d364c94e727e05b7815 dd9d4e5e1eee6fe5377867680e7a61d0 fpscr=00000000
+vcvtp.u32.f32 s7, s31 d494f3bf3ed16134a6afd82a6dfb7fbe 97dd4d774506667c869ede25a78f141b 000000003ed16134a6afd82a6dfb7fbe 97dd4d774506667c869ede25a78f141b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.u32.f32 s7, s31 fac65bf90a3e9c2795dcd8edeba7ed26 6cfd84e271ba5f5889ce3e52cc77c157 ffffffff0a3e9c2795dcd8edeba7ed26 6cfd84e271ba5f5889ce3e52cc77c157 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtp.u32.f32 s7, s31 41d0d9f6dca8185d88917e3f2b941490 bf3285e7cdef58674f11e4ec41788a55 00000000dca8185d88917e3f2b941490 bf3285e7cdef58674f11e4ec41788a55 fpscr=00000000
+vcvtp.u32.f32 s7, s31 d4d13626fbb2a872255e13f949b9006b b6b29d74a76d359e317cec8a7b7cd764 00000000fbb2a872255e13f949b9006b b6b29d74a76d359e317cec8a7b7cd764 fpscr=00000000
+vcvtp.u32.f32 s7, s31 2bca4ea717e32ac7b1b203ba9372978f c8e38f3f8684560b3f3e2275a6f7de94 0000000017e32ac7b1b203ba9372978f c8e38f3f8684560b3f3e2275a6f7de94 fpscr=00000000
+vcvtp.u32.f32 s7, s31 f716af304f108aa2e9a29fd1cf6e0ae7 666fcb4188a7a9122af5433426e8ec17 ffffffff4f108aa2e9a29fd1cf6e0ae7 666fcb4188a7a9122af5433426e8ec17 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtp.u32.f32 s7, s31 978bfa9a0be2fb1014b1d6355ef2fd3d 67df2d5067df2d507b68b951595fe57b ffffffff0be2fb1014b1d6355ef2fd3d 67df2d5067df2d507b68b951595fe57b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.u32.f32 s7, s31 83adf6283f636d6f45a325a53a64e164 12113144381b8155f533c2d97b6d02bb 000000013f636d6f45a325a53a64e164 12113144381b8155f533c2d97b6d02bb fpscr=00000000
+vcvtp.u32.f32 s7, s31 7622f23011fb0059090719ede144c976 8d89e0bfc618b005e50a865161238baa 0000000011fb0059090719ede144c976 8d89e0bfc618b005e50a865161238baa fpscr=00000000
+vcvtp.u32.f32 s7, s31 81633df7782224a33e4898a842452814 52c50ed02f3a24ddcc36fc680f4fb822 ffffffff782224a33e4898a842452814 52c50ed02f3a24ddcc36fc680f4fb822 fpscr=00000000
+vcvtp.u32.f32 s7, s31 40a7185f93ea6ef29aa3ceb455c7e278 95fa89fc30b44c0024a2e04ca757f3d6 0000000093ea6ef29aa3ceb455c7e278 95fa89fc30b44c0024a2e04ca757f3d6 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtp.u32.f32 s7, s31 d874aeec3b3392f6bc009e693b855043 4cabfb3f70d83b4a4cabfb3fc3b919d1 055fd9f83b3392f6bc009e693b855043 4cabfb3f70d83b4a4cabfb3fc3b919d1 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[3]
+vcvtp.u32.f32 s7, s31 a784ceed886cef6171ce2bb8dafd817a 223f945580f6487143957cda43957cda 00000001886cef6171ce2bb8dafd817a 223f945580f6487143957cda43957cda fpscr=00000000
+vcvtp.u32.f32 s7, s31 1ddc266224380ded3473d7b38f3051cf aaa24e40833402846e33d449f6941ede 0000000024380ded3473d7b38f3051cf aaa24e40833402846e33d449f6941ede fpscr=00000000
+vcvtp.u32.f32 s7, s31 1723ae018f26d282961043ca695a25b1 cc9c38574ee894dde9a34f7fe80503ea 000000008f26d282961043ca695a25b1 cc9c38574ee894dde9a34f7fe80503ea fpscr=00000000
+vcvtp.u32.f32 s7, s31 5910018dbdf0477ea682793d0fa2845c d7c9e56e939ff63daa0c03ee41d1f07f 00000000bdf0477ea682793d0fa2845c d7c9e56e939ff63daa0c03ee41d1f07f fpscr=00000000
+vcvtm.u32.f32 s1, s0 a04464e00f5a708367e5893c444ffaf3 79bf10594bda6d3d995d73c51feefb51 79bf10594bda6d3d000000001feefb51 79bf10594bda6d3d000000001feefb51 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.u32.f32 s1, s0 6edde749eeab0e1ff561549af561549a afc3139589b1ba60dbb0e465abbc3db7 afc3139589b1ba6000000000abbc3db7 afc3139589b1ba6000000000abbc3db7 fpscr=00000000
+vcvtm.u32.f32 s1, s0 c9e08d2c36d16c0890b99c865d0a2126 15afdee06a203655960a6519b2a3014b 15afdee06a20365500000000b2a3014b 15afdee06a20365500000000b2a3014b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.u32.f32 s1, s0 38627091aa914d3c3862709164cddbca 0d0f869b2fe75515829320b723f15e05 0d0f869b2fe755150000000023f15e05 0d0f869b2fe755150000000023f15e05 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtm.u32.f32 s1, s0 f5f317eb0bf7a6b218414ed32c3bd38c 951959d5cf15f5488f721e93ef4129b5 951959d5cf15f54800000000ef4129b5 951959d5cf15f54800000000ef4129b5 fpscr=00000000
+vcvtm.u32.f32 s1, s0 94f3d3eea6eb03b3e605aba62ad3ba55 89f35a1f2828b6daf1f5f06bf8bcc0a5 89f35a1f2828b6da00000000f8bcc0a5 89f35a1f2828b6da00000000f8bcc0a5 fpscr=00000000
+vcvtm.u32.f32 s1, s0 caf8936349402bb2c6834044bd8d45d8 981a42af30dc3d9777eafc6251f5b6d1 981a42af30dc3d97ffffffff51f5b6d1 981a42af30dc3d97ffffffff51f5b6d1 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.u32.f32 s1, s0 3603aaced2199c7912b8a75573660d86 9f31b11113d88f1ebcb1824c1d924511 9f31b11113d88f1e000000001d924511 9f31b11113d88f1e000000001d924511 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.u32.f32 s1, s0 5361340148ec17b553613401205c5039 f0c8e31a45a5735e2e61a0bdc0495da0 f0c8e31a45a5735e00000000c0495da0 f0c8e31a45a5735e00000000c0495da0 fpscr=00000000
+vcvtm.u32.f32 s1, s0 cb8a9602a1b2eeec166366e7f8ae2e90 57b43f014a88189849baa8f51e6a0db4 57b43f014a881898000000001e6a0db4 57b43f014a881898000000001e6a0db4 fpscr=00000000
+vcvtm.u32.f32 s1, s0 abd75333c0f75f7d7b5c9bd7b1f8cc2b 5e4d6f05f1fc2f1e212d868cbc2e396c 5e4d6f05f1fc2f1e00000000bc2e396c 5e4d6f05f1fc2f1e00000000bc2e396c fpscr=00000000
+vcvtm.u32.f32 s1, s0 7f28553c53f36a7fd76ff70654160e55 67334fe992cc78c152c0087d0b283c6a 67334fe992cc78c1000000000b283c6a 67334fe992cc78c1000000000b283c6a fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtm.u32.f32 s1, s0 63faed5a865897b8416abb7be76d771a 126a76f4a46f33f39b9409ca3d061f9e 126a76f4a46f33f3000000003d061f9e 126a76f4a46f33f3000000003d061f9e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: 6656 calls, 6860 iters
+vcvtm.u32.f32 s1, s0 4221cf780eaab39382c2155d8ecb0811 843f792aeed95b7a4e11a7aa466ad32c 843f792aeed95b7a00003ab4466ad32c 843f792aeed95b7a00003ab4466ad32c fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtm.u32.f32 s1, s0 57cec4e62c9a75a6075ffb74af8ef76a 996e95813a1b1663483a5c5a49b9bf77 996e95813a1b1663001737ee49b9bf77 996e95813a1b1663001737ee49b9bf77 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtm.u32.f32 s1, s0 4e71fa56409aa77b9c751a514e71fa56 a42884c8cf4af550e0c46d439e835395 a42884c8cf4af550000000009e835395 a42884c8cf4af550000000009e835395 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtm.u32.f32 s1, s0 bb0dbf2477e17e1043f6c96faf59b7cf 285d8b822dbc963f1b26b72775707ee0 285d8b822dbc963fffffffff75707ee0 285d8b822dbc963fffffffff75707ee0 fpscr=00000000
+vcvtm.u32.f32 s1, s0 f17d5c62020df526e072ab0188d5106d feceb68b1f676f1aa9ec14ac88f79e5f feceb68b1f676f1a0000000088f79e5f feceb68b1f676f1a0000000088f79e5f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtm.u32.f32 s1, s0 d0bbd7958e576879883710fbd92763c9 aa7bf3d5aa7bf3d5e302fbf19da4b9d8 aa7bf3d5aa7bf3d5000000009da4b9d8 aa7bf3d5aa7bf3d5000000009da4b9d8 fpscr=00000000
+vcvtm.u32.f32 s1, s0 c1c78c7d1f89a9cf6c72dd647424532d 630b103a787861b06c548972cc51d1d9 630b103a787861b000000000cc51d1d9 630b103a787861b000000000cc51d1d9 fpscr=00000000
+vcvtm.u32.f32 s1, s0 a84bce606c8583bf6358643cff19c003 98cfab205faf637fb18dafbe160af264 98cfab205faf637f00000000160af264 98cfab205faf637f00000000160af264 fpscr=00000000
+vcvtm.u32.f32 s1, s0 d69b418c76b1bff9d13968e08287df61 6722df41266f2a8b9845c42b2037f585 6722df41266f2a8b000000002037f585 6722df41266f2a8b000000002037f585 fpscr=00000000
+vcvtm.u32.f32 s1, s0 5492e47c97e6e93c9d628d57cf431d3f 73b7b27cf5042147b71e8dcc6ead911e 73b7b27cf5042147ffffffff6ead911e 73b7b27cf5042147ffffffff6ead911e fpscr=00000000
+vcvtm.u32.f32 s1, s0 c72d3821c5e6bdf72e323cf5fbbe18d9 5597e3294490b3ceabf47c6fabbe33c1 5597e3294490b3ce00000000abbe33c1 5597e3294490b3ce00000000abbe33c1 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.u32.f32 s1, s0 2d7d4b6e72f559736a52ee227cdf191a 025c5ca5e26a6597ead1519bead1519b 025c5ca5e26a659700000000ead1519b 025c5ca5e26a659700000000ead1519b fpscr=00000000
+vcvtm.u32.f32 s1, s0 44117d00a9394cca4a59904b617c2335 9219904e0cc4595a49fd02e78e6350e6 9219904e0cc4595a000000008e6350e6 9219904e0cc4595a000000008e6350e6 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[2]
+vcvtm.u32.f32 s1, s0 6e4b23532880d6e77a93fb7a9e60ff8e a7b761671c1cb9b6d1b18ba01c1cb9b6 a7b761671c1cb9b6000000001c1cb9b6 a7b761671c1cb9b6000000001c1cb9b6 fpscr=00000000
+vcvtm.u32.f32 s1, s0 b9f80d7472815f4e9815ec52fe98be68 a07b9139eff5a22a8234b5660e0961e4 a07b9139eff5a22a000000000e0961e4 a07b9139eff5a22a000000000e0961e4 fpscr=00000000
+vcvtm.u32.f32 s1, s0 beebb7cfbcff8373509f1aa6c10e2080 67db792d3be83664fb9134ba3b289088 67db792d3be83664000000003b289088 67db792d3be83664000000003b289088 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[2]
+vcvtm.u32.f32 s1, s0 7251aea71cb411c89900e18d1ad1fe24 8fd7fba3d07efacb60a72d2ebb12b2ac 8fd7fba3d07efacb00000000bb12b2ac 8fd7fba3d07efacb00000000bb12b2ac fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtm.u32.f32 s1, s0 99d6798f587de0c4f459b90f031ed093 c5da39caba01052d79316b7959a3f306 c5da39caba01052dffffffff59a3f306 c5da39caba01052dffffffff59a3f306 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.u32.f32 s1, s0 4e781adacb6128c4c0c59e9123d543f4 de539a572bddfaf84c78fd8f307ffc90 de539a572bddfaf800000000307ffc90 de539a572bddfaf800000000307ffc90 fpscr=00000000
+vcvtm.u32.f32 s1, s0 aef22caa9c3caaec72a77948eeced8c5 0303cf00aab22c80db1666b518aa8b8a 0303cf00aab22c800000000018aa8b8a 0303cf00aab22c800000000018aa8b8a fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.u32.f32 s1, s0 743a121219deb1241932636f1932636f ad3478aa2815366bbdaef52d96fe099b ad3478aa2815366b0000000096fe099b ad3478aa2815366b0000000096fe099b fpscr=00000000
+vcvtm.u32.f32 s1, s0 ae85c880203b37b9f0afae54eec9aa84 abc827416adc728603eb02768dcc04dd abc827416adc7286000000008dcc04dd abc827416adc7286000000008dcc04dd fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtm.u32.f32 s1, s0 e62fc704ec522ae156ef9b33e62fc704 61e5726fb51a22817e217d4da798a8c2 61e5726fb51a228100000000a798a8c2 61e5726fb51a228100000000a798a8c2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.u32.f32 s1, s0 33cd0eb0834d3f6838c041065360cf4e 60b6ce15db4d4d2fb5b47bc881753349 60b6ce15db4d4d2f0000000081753349 60b6ce15db4d4d2f0000000081753349 fpscr=00000000
+vcvtm.u32.f32 s1, s0 602d72e2f97ec265987b5c42b0301590 d9f56aa86a957bee71f3e0824fb07f24 d9f56aa86a957beeffffffff4fb07f24 d9f56aa86a957beeffffffff4fb07f24 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtm.u32.f32 s1, s0 1ad9008f7a3a8ded970d7a487a3a8ded f136adf7ccdaedfc237bdb6dd653f399 f136adf7ccdaedfc00000000d653f399 f136adf7ccdaedfc00000000d653f399 fpscr=00000000
+vcvtm.u32.f32 s1, s0 c6425072f3945f15feac625217e7c383 ea1228ab7a448d812cd8699f48e2f6ec ea1228ab7a448d81000717b748e2f6ec ea1228ab7a448d81000717b748e2f6ec fpscr=00000000
+vcvtm.u32.f32 s1, s0 3d9b6f8aa73d7564e9ccdc147e5949f4 1bc3e0203ea621ab0c73535cc7b02d3d 1bc3e0203ea621ab00000000c7b02d3d 1bc3e0203ea621ab00000000c7b02d3d fpscr=00000000
+vcvtm.u32.f32 s1, s0 c3193659ecaa58a257c46a478691f3b6 1a76d5ce008f0cd129615d138621dfe8 1a76d5ce008f0cd1000000008621dfe8 1a76d5ce008f0cd1000000008621dfe8 fpscr=00000000
+vcvtm.u32.f32 s1, s0 b110862d6f0deb05500206b936b68efb 7af10de7b540fd11ebe7ba608ba2be42 7af10de7b540fd11000000008ba2be42 7af10de7b540fd11000000008ba2be42 fpscr=00000000
+vcvtm.u32.f32 s1, s0 c92298b580c895b917e8bb9ec885daaf 743c160f2bf789a2a25dc607ba2bca2c 743c160f2bf789a200000000ba2bca2c 743c160f2bf789a200000000ba2bca2c fpscr=00000000
+vcvtm.u32.f32 s1, s0 bc1c9533376a762bf0e576ff188c0704 79a56170bc92aa8e5d76a346c22c0e10 79a56170bc92aa8e00000000c22c0e10 79a56170bc92aa8e00000000c22c0e10 fpscr=00000000
+vcvtm.u32.f32 s1, s0 0eb68d86f990fc3a4b763b08604887e0 a1268232d69420c593e7ba8bf1ce3a33 a1268232d69420c500000000f1ce3a33 a1268232d69420c500000000f1ce3a33 fpscr=00000000
+vcvtm.u32.f32 s1, s0 5e30c91b629fdd444206c0376526472f f42c4a516f8ead96b068198fd99a2669 f42c4a516f8ead9600000000d99a2669 f42c4a516f8ead9600000000d99a2669 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[0]
+vcvtm.u32.f32 s1, s0 0bce86b98663691488a76166f85d420b 4ce130824ce130828720b0c5e7802c2f 4ce130824ce1308200000000e7802c2f 4ce130824ce1308200000000e7802c2f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtm.u32.f32 s1, s0 3c6b205b3c3904329b9142afa6b573bf aece18b9f1f6325936e9a9759d676c35 aece18b9f1f63259000000009d676c35 aece18b9f1f63259000000009d676c35 fpscr=00000000
+vcvtm.u32.f32 s1, s0 afc71dddc91943bd06ebfd206f04a951 7559fb8bd1986a068421047f125857ee 7559fb8bd1986a0600000000125857ee 7559fb8bd1986a0600000000125857ee fpscr=00000000
+vrintzeq.f64.f64 d0, d9 65e02960e1a963659e529488d87822c0 7cb9b60d9207675c414d89e1200c0b44 65e02960e1a963659e529488d87822c0 7cb9b60d9207675c414d89e1200c0b44 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 dbe8a688deaffaf96a259ae215568faa c3bd0178d8bde25bdca564f6debbebbe dbe8a688deaffaf96a259ae215568faa c3bd0178d8bde25bdca564f6debbebbe fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vrintzeq.f64.f64 d0, d9 3608b2eacd3ffa5c1da6acf83192d2b8 f7abee35b074ad7c1ff1d4a45062edb7 3608b2eacd3ffa5c1da6acf83192d2b8 f7abee35b074ad7c1ff1d4a45062edb7 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 a0de02e340e1cf0f220565a07770bd84 24bc58ac5673b759557421e5a99e9c7e a0de02e340e1cf0f220565a07770bd84 24bc58ac5673b759557421e5a99e9c7e fpscr=00000000
+vrintzeq.f64.f64 d0, d9 866337f680b1a1318eca98772ac8ca8b f9a64cba9adb8dd047bc359ba9b4c228 866337f680b1a1318eca98772ac8ca8b f9a64cba9adb8dd047bc359ba9b4c228 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 21b8d5c28cf97ce171d544de5e52b257 0eecdbcf81ff6c3578e342b9e920ed05 21b8d5c28cf97ce171d544de5e52b257 0eecdbcf81ff6c3578e342b9e920ed05 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 7f4077c49b62cbc691be2cfb33015585 f462aa778724f99be5ce13d31db5d749 7f4077c49b62cbc691be2cfb33015585 f462aa778724f99be5ce13d31db5d749 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzeq.f64.f64 d0, d9 2fac5ec2b88dd04a0220ecf0751028a5 adb85527447ded3db34104c987f5a076 2fac5ec2b88dd04a0220ecf0751028a5 adb85527447ded3db34104c987f5a076 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 39c75274fc3d3222dab8ad35f24b3552 a575c72719bb22f85a1f7ecbe283f223 39c75274fc3d3222dab8ad35f24b3552 a575c72719bb22f85a1f7ecbe283f223 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 2aa5a95eca04c7ee46789e999be03c97 7c64c7fddbd272ec548916993794012c 2aa5a95eca04c7ee46789e999be03c97 7c64c7fddbd272ec548916993794012c fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzeq.f64.f64 d0, d9 682e8064102bb56d5e9e326e34fa536f f4699220edb3e97bf4699220edb3e97b 682e8064102bb56d5e9e326e34fa536f f4699220edb3e97bf4699220edb3e97b fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzeq.f64.f64 d0, d9 1a88a34419fc7efb7964a7b016e525e9 5ea9667c1df6f604e82e52d6c18fc6aa 1a88a34419fc7efb7964a7b016e525e9 5ea9667c1df6f604e82e52d6c18fc6aa fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vrintzeq.f64.f64 d0, d9 54ba9aae82a2a90354ba9aae82a2a903 a052d8c66f45cde5d0958e84b1110fe3 54ba9aae82a2a90354ba9aae82a2a903 a052d8c66f45cde5d0958e84b1110fe3 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 141ce1bf9b3097c4c33098734a5b4a74 aa9166db76a38f52c9b0cdae6b461f93 141ce1bf9b3097c4c33098734a5b4a74 aa9166db76a38f52c9b0cdae6b461f93 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzeq.f64.f64 d0, d9 9caa83450abd44670c7c7db0aa27e1fb ed4d5894fc39627013d5c066dedc4c2d 9caa83450abd44670c7c7db0aa27e1fb ed4d5894fc39627013d5c066dedc4c2d fpscr=00000000
+vrintzeq.f64.f64 d0, d9 5f08de972718b1a245cdd906dfbeaf28 1a70111e64a1b2a7e1cefbe4f6f738e4 5f08de972718b1a245cdd906dfbeaf28 1a70111e64a1b2a7e1cefbe4f6f738e4 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 2422dabc5978107edca1e96a6fb018be 2cee659f4290f56cdcbcd7750fb41c8b 2422dabc5978107edca1e96a6fb018be 2cee659f4290f56cdcbcd7750fb41c8b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzeq.f64.f64 d0, d9 a73e904457ae1838b20ed5dfacb15dbe 73de451857faeeeeabe9386447493c16 a73e904457ae1838b20ed5dfacb15dbe 73de451857faeeeeabe9386447493c16 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 e13e9176f28bdfdf4538d1c5b27b35da da56e7e875b606410c009980327f4cb5 e13e9176f28bdfdf4538d1c5b27b35da da56e7e875b606410c009980327f4cb5 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzeq.f64.f64 d0, d9 baa0da1ea991590b6a7787853f8f7aad fb14b97b84d72ae624cf1cb3e1fbac3f baa0da1ea991590b6a7787853f8f7aad fb14b97b84d72ae624cf1cb3e1fbac3f fpscr=00000000
+vrintzeq.f64.f64 d0, d9 3b93086c8697a88bd9dda8c62c8b7aee fc11d374e649a682c94b36c666671537 3b93086c8697a88bd9dda8c62c8b7aee fc11d374e649a682c94b36c666671537 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vrintzeq.f64.f64 d0, d9 4e9864983845d733661bde3c68cc5003 a74386d8a99a8838a74386d8a99a8838 4e9864983845d733661bde3c68cc5003 a74386d8a99a8838a74386d8a99a8838 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintzeq.f64.f64 d0, d9 59355852126d6419b4ae5b3ab237f047 0b06697d7100ac17739e7b16b4f8d934 59355852126d6419b4ae5b3ab237f047 0b06697d7100ac17739e7b16b4f8d934 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 2138012201cf2f43267d1dac23e56b34 64eee9a2cd3d3de8663227bc0481647f 2138012201cf2f43267d1dac23e56b34 64eee9a2cd3d3de8663227bc0481647f fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzeq.f64.f64 d0, d9 e199f546a020ca129d80f2c5c661d906 bb15f6746d5c7b22298e692490e54e8c e199f546a020ca129d80f2c5c661d906 bb15f6746d5c7b22298e692490e54e8c fpscr=00000000
+vrintzeq.f64.f64 d0, d9 ce3eff35e371f20d4e126545292e3992 4bc8487f542538e55436688f3b90f004 ce3eff35e371f20d4e126545292e3992 4bc8487f542538e55436688f3b90f004 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 f9a1abe0f09d19754fe0d4e9547fd5d3 f2bc144dc2f083761c22713c6393a685 f9a1abe0f09d19754fe0d4e9547fd5d3 f2bc144dc2f083761c22713c6393a685 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: 6912 calls, 7126 iters
+vrintzeq.f64.f64 d0, d9 bac422d35ded595c1fb07d7ab97d21f4 29dbc0711ac93ef08b1d4af0c29731b8 bac422d35ded595c1fb07d7ab97d21f4 29dbc0711ac93ef08b1d4af0c29731b8 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 caa563d83736892244199b33f0f33bd7 40a74610c2aaef2f1518cb2ab934082f caa563d83736892244199b33f0f33bd7 40a74610c2aaef2f1518cb2ab934082f fpscr=00000000
+vrintzeq.f64.f64 d0, d9 f79906fde72565c49abbe121cd3095d4 b48e3b7bda975d2b5819d505e35d66bd f79906fde72565c49abbe121cd3095d4 b48e3b7bda975d2b5819d505e35d66bd fpscr=00000000
+vrintzeq.f64.f64 d0, d9 204a63281b9d82a926a37f57c127a221 0e826ee370fd7bdbf8e189d5eb043a3b 204a63281b9d82a926a37f57c127a221 0e826ee370fd7bdbf8e189d5eb043a3b fpscr=00000000
+vrintzeq.f64.f64 d0, d9 4b7eb26940d8fcdb7e748361677e8ff1 6ed5ed0262dd35e4f76326b8fb652aee 4b7eb26940d8fcdb7e748361677e8ff1 6ed5ed0262dd35e4f76326b8fb652aee fpscr=00000000
+vrintzeq.f64.f64 d0, d9 03a1568ecd024ae09f6f6760017ee886 af1508b0257a80bd27ae1d2fa8a19cf1 03a1568ecd024ae09f6f6760017ee886 af1508b0257a80bd27ae1d2fa8a19cf1 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzeq.f64.f64 d0, d9 973e682d9b4eec5c6c25e24f1b6f8618 55cb41f84b2ef0de52f24a71bbd587a6 973e682d9b4eec5c6c25e24f1b6f8618 55cb41f84b2ef0de52f24a71bbd587a6 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzeq.f64.f64 d0, d9 fe8032d22709246bfc1d0d8f92aa0647 f643ca18a7fd6c32b0cdc3598692561f fe8032d22709246bfc1d0d8f92aa0647 f643ca18a7fd6c32b0cdc3598692561f fpscr=00000000
+vrintzeq.f64.f64 d0, d9 762aad90df0443d6a45e93792a848c71 ee5a3ca00c308cd26b33d30f26c8a298 762aad90df0443d6a45e93792a848c71 ee5a3ca00c308cd26b33d30f26c8a298 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzeq.f64.f64 d0, d9 6f7837c7653a0f6013b4221b0d8cca93 8e5df439adc0971f19d511f2d47bb864 6f7837c7653a0f6013b4221b0d8cca93 8e5df439adc0971f19d511f2d47bb864 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 85e58265d2b7db0005918c1406189827 5585126929e0b1933c223db54010d73d 85e58265d2b7db0005918c1406189827 5585126929e0b1933c223db54010d73d fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzeq.f64.f64 d0, d9 2b5dd97e2169647e2b5dd97e2169647e 8892e737e3af79c9a1ef80390b8397f9 2b5dd97e2169647e2b5dd97e2169647e 8892e737e3af79c9a1ef80390b8397f9 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 2c6dba4725e13563ef88d59788fc7680 0746786d21940c44eb607ce754dd9633 2c6dba4725e13563ef88d59788fc7680 0746786d21940c44eb607ce754dd9633 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzeq.f64.f64 d0, d9 2eb43572bb95b66522fcf8b33cb90f1d 184ca7c8b93143a2eb96c595bfd49dbc 2eb43572bb95b66522fcf8b33cb90f1d 184ca7c8b93143a2eb96c595bfd49dbc fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzeq.f64.f64 d0, d9 78720bc0e93b286dc43821b6106fcdbc 2cee6ea7383e9ed6d84645c8c41ad86b 78720bc0e93b286dc43821b6106fcdbc 2cee6ea7383e9ed6d84645c8c41ad86b fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzeq.f64.f64 d0, d9 8a87e196a6981a71864d80b70a937d84 39ae5c966226fe0639ae5c966226fe06 8a87e196a6981a71864d80b70a937d84 39ae5c966226fe0639ae5c966226fe06 fpscr=00000000
+vrintzeq.f64.f64 d0, d9 1f22496021170a017e9617e3ac095ccf 64ba85005731ed0722e2504836f37117 1f22496021170a017e9617e3ac095ccf 64ba85005731ed0722e2504836f37117 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzeq.f64.f64 d0, d9 3c7fc973d39ef910eb5703a82035b051 9e42b5e2e85ee9b6761c8256b1b1e79c 3c7fc973d39ef910eb5703a82035b051 9e42b5e2e85ee9b6761c8256b1b1e79c fpscr=00000000
+vrintzeq.f64.f64 d0, d9 522c30d079afff913dd92bae0552e19e 9d6520886f994828ac91cd9f32247c6f 522c30d079afff913dd92bae0552e19e 9d6520886f994828ac91cd9f32247c6f fpscr=00000000
+vrintzeq.f64.f64 d0, d9 d767b03a0f50d6cfc0d548148a9369b8 0ee404a16abab7c8e83e4565d92a7920 d767b03a0f50d6cfc0d548148a9369b8 0ee404a16abab7c8e83e4565d92a7920 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzeq.f64.f64 d0, d9 7756a146d01eb2c61b7cc7a7891b8647 ddd21ba3652935d76c3f6b2501e53bbf 7756a146d01eb2c61b7cc7a7891b8647 ddd21ba3652935d76c3f6b2501e53bbf fpscr=00000000
+vrintzeq.f64.f64 d0, d9 7e1a6d8917cf56c6020ded0256cfbecf 74752b02839b3e01e7af498a6be704d3 7e1a6d8917cf56c6020ded0256cfbecf 74752b02839b3e01e7af498a6be704d3 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vrintzeq.f64.f64 d0, d9 b09155b0b292b58fb09155b0b292b58f e5420ab303a19358cdc67a071474fad6 b09155b0b292b58fb09155b0b292b58f e5420ab303a19358cdc67a071474fad6 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzne.f64.f64 d1, d10 d84be620422a322401bd0e3124641473 23738d678ae6d4698536e5459e45e3d3 800000000000000001bd0e3124641473 23738d678ae6d4698536e5459e45e3d3 fpscr=00000000
+vrintzne.f64.f64 d1, d10 84eb9d1adb29d9eee8f69215cf78acfd 6f9e81d32a8e1fa657554353b97fcfd5 57554353b97fcfd5e8f69215cf78acfd 6f9e81d32a8e1fa657554353b97fcfd5 fpscr=00000000
+vrintzne.f64.f64 d1, d10 09be2fce748bc02884303ee01f65e2f6 7664cb9c53fd6ad425a38d71912c510b 000000000000000084303ee01f65e2f6 7664cb9c53fd6ad425a38d71912c510b fpscr=00000000
+vrintzne.f64.f64 d1, d10 70f36d16f3bd55579413b00f0f5952d6 b0a3fc774ff0e4c8df8413db121276a5 df8413db121276a59413b00f0f5952d6 b0a3fc774ff0e4c8df8413db121276a5 fpscr=00000000
+vrintzne.f64.f64 d1, d10 bb391f380289599d1b292650c6e34f30 f30359a49f4296084633c3587315dcc8 4633c3587315dcc81b292650c6e34f30 f30359a49f4296084633c3587315dcc8 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 c749668c1efadd8381065c3bbb0dc82b 152f58a904f7033969fba5b608c387fd 69fba5b608c387fd81065c3bbb0dc82b 152f58a904f7033969fba5b608c387fd fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 f3207b018140ba19af3272635223b7d0 8c1ca226c9bb323973070425f4222ba5 73070425f4222ba5af3272635223b7d0 8c1ca226c9bb323973070425f4222ba5 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 56f9f4b0b6469a0df5d3884944906c89 b4791370b34ba4f6b4791370b34ba4f6 8000000000000000f5d3884944906c89 b4791370b34ba4f6b4791370b34ba4f6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 a9ae33e0f1d05953374fef2238e06a0b b3dbf1d9dea0e10db3dbf1d9dea0e10d 8000000000000000374fef2238e06a0b b3dbf1d9dea0e10db3dbf1d9dea0e10d fpscr=00000000
+vrintzne.f64.f64 d1, d10 8bb6e6beb71a303535c22a4550b549a8 e00620a04fa5f75779c544e781323d30 79c544e781323d3035c22a4550b549a8 e00620a04fa5f75779c544e781323d30 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 2f130b0ba3cdf11fc6a6a8b6bd890fb2 0f086e75eafd0c2b9edfb7261f93ff40 8000000000000000c6a6a8b6bd890fb2 0f086e75eafd0c2b9edfb7261f93ff40 fpscr=00000000
+vrintzne.f64.f64 d1, d10 9ef3eb72dabe3ec88643cf48f59ed0ed 203e3599ba2303be3e15cc92dfb390ed 00000000000000008643cf48f59ed0ed 203e3599ba2303be3e15cc92dfb390ed fpscr=00000000
+vrintzne.f64.f64 d1, d10 c93bc68591429cdb4bf3ac0be6e6e509 b78543dee5b167af86b09dc471d3145a 80000000000000004bf3ac0be6e6e509 b78543dee5b167af86b09dc471d3145a fpscr=00000000
+vrintzne.f64.f64 d1, d10 7ec031a1374059e3f882f52a42f9e850 edd41d793476282f43503d48084c88b9 43503d48084c88b9f882f52a42f9e850 edd41d793476282f43503d48084c88b9 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzne.f64.f64 d1, d10 e848fb25335f20e7e848fb25335f20e7 7b193937966a4c8f2a02190fab6c8323 0000000000000000e848fb25335f20e7 7b193937966a4c8f2a02190fab6c8323 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 a6036a620ad1d4a776fba089052466d2 9ebdfac81bb7c4f6b174e1bc3c442cb3 800000000000000076fba089052466d2 9ebdfac81bb7c4f6b174e1bc3c442cb3 fpscr=00000000
+vrintzne.f64.f64 d1, d10 df542a86a02805142c7653c27afacc2d 5efbf9a7ab17cc097ed42d952239d880 7ed42d952239d8802c7653c27afacc2d 5efbf9a7ab17cc097ed42d952239d880 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 e26c6d83d9d39488b6d76a174905044d 8c745c92ac36e805965292920cb31193 8000000000000000b6d76a174905044d 8c745c92ac36e805965292920cb31193 fpscr=00000000
+vrintzne.f64.f64 d1, d10 1f7d937437bd68f6717962fb74ee76b5 4a223cb6acbf025b9e05e6b4b6e076f7 8000000000000000717962fb74ee76b5 4a223cb6acbf025b9e05e6b4b6e076f7 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 560e5e594cc5963b560e5e594cc5963b ac267c87814f475510d4882a700533ac 0000000000000000560e5e594cc5963b ac267c87814f475510d4882a700533ac fpscr=00000000
+vrintzne.f64.f64 d1, d10 e30729b5d1dcf18d43a9509c01c18773 a74ee29a2597b80fca88570e96cdef56 ca88570e96cdef5643a9509c01c18773 a74ee29a2597b80fca88570e96cdef56 fpscr=00000000
+vrintzne.f64.f64 d1, d10 3a600955af0695f709d04dd5de4b2dff b6c9ed29f36dff8027a85b68cd1a3043 000000000000000009d04dd5de4b2dff b6c9ed29f36dff8027a85b68cd1a3043 fpscr=00000000
+vrintzne.f64.f64 d1, d10 67b052e87cbca0c5ca1150ab69d2c23f 38ad25541bc785295632e04e92b943f3 5632e04e92b943f3ca1150ab69d2c23f 38ad25541bc785295632e04e92b943f3 fpscr=00000000
+vrintzne.f64.f64 d1, d10 062799745ad282cd06d22086b1fd6564 67b1566cd2f5da3578c69005a3f2c6a2 78c69005a3f2c6a206d22086b1fd6564 67b1566cd2f5da3578c69005a3f2c6a2 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzne.f64.f64 d1, d10 50c9ff7a55499ca150c9ff7a55499ca1 0159db9593813ca95c162c57fc4b7ded 5c162c57fc4b7ded50c9ff7a55499ca1 0159db9593813ca95c162c57fc4b7ded fpscr=00000000
+vrintzne.f64.f64 d1, d10 cbaa5dd44a66efca85a937db8b32a890 16c62800ef04c809fdf89bdc8874d398 fdf89bdc8874d39885a937db8b32a890 16c62800ef04c809fdf89bdc8874d398 fpscr=00000000
+vrintzne.f64.f64 d1, d10 abaa0f3556c2652347283b0ef4a80cdf bf6bc84babffb26100c4928e15f7d1c2 000000000000000047283b0ef4a80cdf bf6bc84babffb26100c4928e15f7d1c2 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 5c3d3d069a119b03cd24e45e424e4047 989bddf194789805989bddf194789805 8000000000000000cd24e45e424e4047 989bddf194789805989bddf194789805 fpscr=00000000
+vrintzne.f64.f64 d1, d10 6df5e3407a0b920c023b4ecd08402b18 c077bdc1a630650f414d054f5aba952b 414d054f00000000023b4ecd08402b18 c077bdc1a630650f414d054f5aba952b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 a2a315542819d4007b9c22c740da482e c9a9bf7449a95158c9a9bf7449a95158 c9a9bf7449a951587b9c22c740da482e c9a9bf7449a95158c9a9bf7449a95158 fpscr=00000000
+vrintzne.f64.f64 d1, d10 1552a7046d25095eebb934c4b23a80ef 0f66500be338913a3e97192346156396 0000000000000000ebb934c4b23a80ef 0f66500be338913a3e97192346156396 fpscr=00000000
+vrintzne.f64.f64 d1, d10 d87b61f4449488310b52ce298d2e7058 e708e6a6196218013d4416a2233f91c7 00000000000000000b52ce298d2e7058 e708e6a6196218013d4416a2233f91c7 fpscr=00000000
+vrintzne.f64.f64 d1, d10 4b1174d081e56603bbd1b5533384d261 f5e86dc02c8e7465565e733c6311b9c1 565e733c6311b9c1bbd1b5533384d261 f5e86dc02c8e7465565e733c6311b9c1 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 d33b2c89671becebc911cab8253ac19d b1de3a37e1a442afe12f584f3875fe36 e12f584f3875fe36c911cab8253ac19d b1de3a37e1a442afe12f584f3875fe36 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vrintzne.f64.f64 d1, d10 90deb72bcbd61e7290deb72bcbd61e72 8c47c047fd44dba58c47c047fd44dba5 800000000000000090deb72bcbd61e72 8c47c047fd44dba58c47c047fd44dba5 fpscr=00000000
+vrintzne.f64.f64 d1, d10 8ad7d1d1c33d4d18c56079e8f2e7f4c5 9f3b4b47e617eae8b504d813487e1bfa 8000000000000000c56079e8f2e7f4c5 9f3b4b47e617eae8b504d813487e1bfa fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 2fdde04d966ff4602fdde04d966ff460 b4e5ff1bf701e6dc973ae4ddb870aff2 80000000000000002fdde04d966ff460 b4e5ff1bf701e6dc973ae4ddb870aff2 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzne.f64.f64 d1, d10 4f1b1a0bdabf139c4f1b1a0bdabf139c 8fe443ab470dc8f37c17c2a73979520e 7c17c2a73979520e4f1b1a0bdabf139c 8fe443ab470dc8f37c17c2a73979520e fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzne.f64.f64 d1, d10 5db6f757b301be8de54a63e41bae09da 109e43a55c692f1ca1fc8bbb052971fa 8000000000000000e54a63e41bae09da 109e43a55c692f1ca1fc8bbb052971fa fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzne.f64.f64 d1, d10 b2bcc2177494b28af0441e98020a1bab cc8dd741aeda7c94cc8dd741aeda7c94 cc8dd741aeda7c94f0441e98020a1bab cc8dd741aeda7c94cc8dd741aeda7c94 fpscr=00000000
+vrintzne.f64.f64 d1, d10 6de3dd1c6c1589dbdbd6425fb08310b9 b51f999bfd05c80451b57daae126ffcd 51b57daae126ffcddbd6425fb08310b9 b51f999bfd05c80451b57daae126ffcd fpscr=00000000
+randV128: 7168 calls, 7393 iters
+vrintzne.f64.f64 d1, d10 537784c1daa995aff0dfdb6aa5d80ef4 1f8c7c8dcbaf679546ae15369f7fb70c 46ae15369f7fb70cf0dfdb6aa5d80ef4 1f8c7c8dcbaf679546ae15369f7fb70c fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzne.f64.f64 d1, d10 c5bfe29406ae295d370116702dec2f08 c5c7be2ff6281ec1c5c7be2ff6281ec1 c5c7be2ff6281ec1370116702dec2f08 c5c7be2ff6281ec1c5c7be2ff6281ec1 fpscr=00000000
+vrintzne.f64.f64 d1, d10 9b891076a383c67ec9ebd4c10772e674 45615e5f60c2c335ef9111b6d6f33e14 ef9111b6d6f33e14c9ebd4c10772e674 45615e5f60c2c335ef9111b6d6f33e14 fpscr=00000000
+vrintzne.f64.f64 d1, d10 5118debc4ed1ae7687e50c87c40611df 3250b285c11ea98428bf61cd25cb1967 000000000000000087e50c87c40611df 3250b285c11ea98428bf61cd25cb1967 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzne.f64.f64 d1, d10 9d5e20798112db006efa0a4cd2cbfab8 b7f380100d6c27ae99200e7d3f7a3ba3 80000000000000006efa0a4cd2cbfab8 b7f380100d6c27ae99200e7d3f7a3ba3 fpscr=00000000
+vrintzne.f64.f64 d1, d10 ad85543119d367c24466e40c6c8a5ae5 4aa8ba44e58beaa24e5c12125403afc7 4e5c12125403afc74466e40c6c8a5ae5 4aa8ba44e58beaa24e5c12125403afc7 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintzne.f64.f64 d1, d10 8f0c8a2330e7d9e58f0c8a2330e7d9e5 b4590c0c33befc81dd1328fff582518a dd1328fff582518a8f0c8a2330e7d9e5 b4590c0c33befc81dd1328fff582518a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintzne.f64.f64 d1, d10 c0063b9f153d9a715ceda0676718006b bc986f66e849f5a7bc986f66e849f5a7 80000000000000005ceda0676718006b bc986f66e849f5a7bc986f66e849f5a7 fpscr=00000000
+vrintzne.f64.f64 d1, d10 ccf5ea603cd76ac81f4aeb27b92437ba f2e087a50cb268a28eb68cc46da8d47b 80000000000000001f4aeb27b92437ba f2e087a50cb268a28eb68cc46da8d47b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vrintz.f64.f64 d2, d11 4126e58b04e2117a4126e58b04e2117a 1d66fb90508d9b554cc88bd9417c3fde 4126e58b04e2117a0000000000000000 1d66fb90508d9b554cc88bd9417c3fde fpscr=00000000
+vrintz.f64.f64 d2, d11 1385230615cca44486d82cc5b652778e d1255cee5b7ff5a32c6188ced8f5a82f 1385230615cca444d1255cee5b7ff5a3 d1255cee5b7ff5a32c6188ced8f5a82f fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintz.f64.f64 d2, d11 6458cc3f2583a0d06458cc3f2583a0d0 a91030fb0fd6ad847a846bf8526da307 6458cc3f2583a0d08000000000000000 a91030fb0fd6ad847a846bf8526da307 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintz.f64.f64 d2, d11 533c9abbf1a2346d1898f8c916c78127 9896321a24700fe09896321a24700fe0 533c9abbf1a2346d8000000000000000 9896321a24700fe09896321a24700fe0 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintz.f64.f64 d2, d11 9d12483f33fd3e0b25adea9aa46156bb a7fecb16241b16507dd0dc4674f12d8e 9d12483f33fd3e0b8000000000000000 a7fecb16241b16507dd0dc4674f12d8e fpscr=00000000
+vrintz.f64.f64 d2, d11 dac42e831264fa33fa5f00e572723e87 bab9b5f090842789429a24ea168e8d2b dac42e831264fa338000000000000000 bab9b5f090842789429a24ea168e8d2b fpscr=00000000
+vrintz.f64.f64 d2, d11 be2881a7924ab2b2b41304878a5e399f 21183d7fc6677aae46a1db9de0e287f5 be2881a7924ab2b20000000000000000 21183d7fc6677aae46a1db9de0e287f5 fpscr=00000000
+vrintz.f64.f64 d2, d11 b554185c8b4730acd9cfb260b79b8c24 d72008703993a3364f35887e2724737d b554185c8b4730acd72008703993a336 d72008703993a3364f35887e2724737d fpscr=00000000
+vrintz.f64.f64 d2, d11 85cc1d8d0b3fee53b96b0882c7ba66a6 36c38a63566430f164401ff0290e2a14 85cc1d8d0b3fee530000000000000000 36c38a63566430f164401ff0290e2a14 fpscr=00000000
+vrintz.f64.f64 d2, d11 9aacd059be2f5244bbfa914cd7e9e89e 7f19fcc8135a26c603d67447d299c6b7 9aacd059be2f52447f19fcc8135a26c6 7f19fcc8135a26c603d67447d299c6b7 fpscr=00000000
+vrintz.f64.f64 d2, d11 7180b390457862f68a0104a6e5420ee2 3014f06070ef160a5109910dac15f7f6 7180b390457862f60000000000000000 3014f06070ef160a5109910dac15f7f6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintz.f64.f64 d2, d11 32a317fb088eb4fb32a317fb088eb4fb f35fe8b24c04913cf35fe8b24c04913c 32a317fb088eb4fbf35fe8b24c04913c f35fe8b24c04913cf35fe8b24c04913c fpscr=00000000
+vrintz.f64.f64 d2, d11 7bd77e115984f311f14e8dca281210d2 00e6c0f1df8d62ff1c80fb6c7103fb48 7bd77e115984f3110000000000000000 00e6c0f1df8d62ff1c80fb6c7103fb48 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintz.f64.f64 d2, d11 5a12390957466abb5a12390957466abb 03de4dd629b91eb970437d5fed910e6b 5a12390957466abb0000000000000000 03de4dd629b91eb970437d5fed910e6b fpscr=00000000
+vrintz.f64.f64 d2, d11 28668669a2b9eeb2691d4dc035f32bb1 e71de82ab385857cd60fd9c13b46d171 28668669a2b9eeb2e71de82ab385857c e71de82ab385857cd60fd9c13b46d171 fpscr=00000000
+vrintz.f64.f64 d2, d11 e1648c1992ddd5a36b908b2ecde06c46 4f91e03b46b21ae4c170d7f7d223d009 e1648c1992ddd5a34f91e03b46b21ae4 4f91e03b46b21ae4c170d7f7d223d009 fpscr=00000000
+vrintz.f64.f64 d2, d11 56e2f0137514104c2d54b72101284560 f345a626574a3b29d1d103ca0cff23a7 56e2f0137514104cf345a626574a3b29 f345a626574a3b29d1d103ca0cff23a7 fpscr=00000000
+vrintz.f64.f64 d2, d11 9348ed3707f1d7e161c25e115baa8cc4 9ac2a2053bad464b3833ccf866db853b 9348ed3707f1d7e18000000000000000 9ac2a2053bad464b3833ccf866db853b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintz.f64.f64 d2, d11 07f5fae7381a73aceb4b7a68d2ac7208 a734c38f3c9f5aa31f2300494155eaae 07f5fae7381a73ac8000000000000000 a734c38f3c9f5aa31f2300494155eaae fpscr=00000000
+vrintz.f64.f64 d2, d11 618ac9772a2770959500ac0e16c1e17f e008f5ed33ff4d999ba0ed42bdbe7e36 618ac9772a277095e008f5ed33ff4d99 e008f5ed33ff4d999ba0ed42bdbe7e36 fpscr=00000000
+vrintz.f64.f64 d2, d11 c2c3e7308522ae2cb5a9fb971f5dd4ff 041ebfb18a42e0c9d9b025982d597a93 c2c3e7308522ae2c0000000000000000 041ebfb18a42e0c9d9b025982d597a93 fpscr=00000000
+vrintz.f64.f64 d2, d11 9a437060904c189e956ae36a2ea58a5c f51a19be44a1098c3a2013ede0878f12 9a437060904c189ef51a19be44a1098c f51a19be44a1098c3a2013ede0878f12 fpscr=00000000
+vrintz.f64.f64 d2, d11 64e9e70044a6bb5f087ca71a71c14a90 28abb5bf7210839ef007103e5182ec3b 64e9e70044a6bb5f0000000000000000 28abb5bf7210839ef007103e5182ec3b fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintz.f64.f64 d2, d11 48ce928e2795f701340652530ab07605 7675d65f965c25c82b412e11f097a5aa 48ce928e2795f7017675d65f965c25c8 7675d65f965c25c82b412e11f097a5aa fpscr=00000000
+vrintz.f64.f64 d2, d11 48e522971eef5ebfce191b1b56d0f4ee 6234dbd360878142d79e1f36761095bf 48e522971eef5ebf6234dbd360878142 6234dbd360878142d79e1f36761095bf fpscr=00000000
+vrintz.f64.f64 d2, d11 e1e9179fc5babdee4527958a6948813a 1a1b57374cbc19cd1db80a139d59ffc8 e1e9179fc5babdee0000000000000000 1a1b57374cbc19cd1db80a139d59ffc8 fpscr=00000000
+vrintz.f64.f64 d2, d11 b0b1c88948b0c6183186fa1016b81832 2f30f438a37f4e7bc70b85821deba4c8 b0b1c88948b0c6180000000000000000 2f30f438a37f4e7bc70b85821deba4c8 fpscr=00000000
+vrintz.f64.f64 d2, d11 dd949e723328dbefc60b409ec367190e 7ed8353860809954ef33f256ddf389dd dd949e723328dbef7ed8353860809954 7ed8353860809954ef33f256ddf389dd fpscr=00000000
+vrintz.f64.f64 d2, d11 f26266f9856e5bc7844afd027c1ea31b 7da0dada6b38f74938251841c52f8d92 f26266f9856e5bc77da0dada6b38f749 7da0dada6b38f74938251841c52f8d92 fpscr=00000000
+vrintz.f64.f64 d2, d11 2b8c8246d46c77c8cebb0584e895f472 527c16bfdf6264db9f7f10384e28fc72 2b8c8246d46c77c8527c16bfdf6264db 527c16bfdf6264db9f7f10384e28fc72 fpscr=00000000
+vrintz.f64.f64 d2, d11 31c254b0164fb13dfe700d8787be3d49 4eaf6d86beb75b248b54f54a78f103a6 31c254b0164fb13d4eaf6d86beb75b24 4eaf6d86beb75b248b54f54a78f103a6 fpscr=00000000
+vrintz.f64.f64 d2, d11 d0ef974f8aab4c9113bf680bdd0b7c76 0ea749bc778f3e3dde3c658765b3b58a d0ef974f8aab4c910000000000000000 0ea749bc778f3e3dde3c658765b3b58a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintz.f64.f64 d2, d11 5d057ba5fd35eb12131739b0023c850f 14c6a2d3190a34149a562ae212ea95c9 5d057ba5fd35eb120000000000000000 14c6a2d3190a34149a562ae212ea95c9 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintz.f64.f64 d2, d11 54baa34ac9253344fdb8583482d8ab67 1cd4c5d4f02617e61cd4c5d4f02617e6 54baa34ac92533440000000000000000 1cd4c5d4f02617e61cd4c5d4f02617e6 fpscr=00000000
+vrintz.f64.f64 d2, d11 3e71e3ded34f1dd5723845e469ca15d2 d5e9ce20207b88975b45c938261e8df2 3e71e3ded34f1dd5d5e9ce20207b8897 d5e9ce20207b88975b45c938261e8df2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vrintz.f64.f64 d2, d11 67a40e26f17e185dfba2dc531ee9b1c4 8cfcb7084e499ac2936d586cc70fcfda 67a40e26f17e185d8000000000000000 8cfcb7084e499ac2936d586cc70fcfda fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vrintz.f64.f64 d2, d11 8720ad75cc4b53ce8720ad75cc4b53ce 08797ff851c4b2e197d888dd251c07ca 8720ad75cc4b53ce0000000000000000 08797ff851c4b2e197d888dd251c07ca fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintz.f64.f64 d2, d11 11b9edb14c5f4c5a11b9edb14c5f4c5a f771c49cf094a5a3f46e2cfefa3368da 11b9edb14c5f4c5af771c49cf094a5a3 f771c49cf094a5a3f46e2cfefa3368da fpscr=00000000
+vrintz.f64.f64 d2, d11 73a81ecc3ac47977bdd260ea993c6486 318fbb3ae6e0f3edb1bd641115f5e788 73a81ecc3ac479770000000000000000 318fbb3ae6e0f3edb1bd641115f5e788 fpscr=00000000
+vrintz.f64.f64 d2, d11 83fa7e97e92e65589242542f195baae2 96020adc013bee6768c4be80ed93d3bf 83fa7e97e92e65588000000000000000 96020adc013bee6768c4be80ed93d3bf fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintz.f64.f64 d2, d11 b026f31cb2724501ba7d28b15dc9b4a7 818fa179dc003e27818fa179dc003e27 b026f31cb27245018000000000000000 818fa179dc003e27818fa179dc003e27 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintz.f64.f64 d2, d11 733e104de1303e05733e104de1303e05 43e7908b771e1325102b71f09b537c8e 733e104de1303e0543e7908b771e1325 43e7908b771e1325102b71f09b537c8e fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintz.f64.f64 d2, d11 75b38269e502f923ed08e20cb82a6969 bc51395e556bdb02e8d569805d5de542 75b38269e502f9238000000000000000 bc51395e556bdb02e8d569805d5de542 fpscr=00000000
+vrintz.f64.f64 d2, d11 b697a706d47369fc5526b6708c5040ff 11730405849497c9ea7b5b1ca6b72715 b697a706d47369fc0000000000000000 11730405849497c9ea7b5b1ca6b72715 fpscr=00000000
+vrintz.f64.f64 d2, d11 348764ae0e5f2ee798194a935096371a 0aa922648fa3385b4f0d49a285cdedcc 348764ae0e5f2ee70000000000000000 0aa922648fa3385b4f0d49a285cdedcc fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintz.f64.f64 d2, d11 1eade9e382ef21302da68406dec165d9 bb8f22cb4b06f4a01fce07b9d693afc5 1eade9e382ef21308000000000000000 bb8f22cb4b06f4a01fce07b9d693afc5 fpscr=00000000
+vrintz.f64.f64 d2, d11 fe780629116b4efc512881bf2c0caf8f 2f0609a81cd9b901abd9b30d056120d3 fe780629116b4efc0000000000000000 2f0609a81cd9b901abd9b30d056120d3 fpscr=00000000
+vrintz.f64.f64 d2, d11 88f394f40c96461868763d39e55d1158 de184f45a03864962f7555ab7bcba39c 88f394f40c964618de184f45a0386496 de184f45a03864962f7555ab7bcba39c fpscr=00000000
+vrintz.f64.f64 d2, d11 817a9369f6f7efd2c18f32dba866cbc4 35c01f52f73aaf7224cb3328ee33ee6b 817a9369f6f7efd20000000000000000 35c01f52f73aaf7224cb3328ee33ee6b fpscr=00000000
+vrintz.f64.f64 d2, d11 f2e4236ddb99d47c898cc5cafec3abd2 10a94f03ca568fc049bab7921a9dd540 f2e4236ddb99d47c0000000000000000 10a94f03ca568fc049bab7921a9dd540 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vrintreq.f64.f64 d3, d12 8faabdf19497b150b95e3e4f2212f63d 1e273d4f3377c9851e273d4f3377c985 8faabdf19497b150b95e3e4f2212f63d 1e273d4f3377c9851e273d4f3377c985 fpscr=00000000
+vrintreq.f64.f64 d3, d12 5c28d090158bdf1653442add81137ef6 f2973ab32647b3c3967cb3c4f187a0b1 5c28d090158bdf1653442add81137ef6 f2973ab32647b3c3967cb3c4f187a0b1 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vrintreq.f64.f64 d3, d12 44581cab0d45dc8044581cab0d45dc80 558c3575f7fbfdc26b8e8d82ff078ef8 44581cab0d45dc8044581cab0d45dc80 558c3575f7fbfdc26b8e8d82ff078ef8 fpscr=00000000
+vrintreq.f64.f64 d3, d12 a5b2fb345d44dea9d02a524304178900 1bc750c664ecd959da25773f7e58f178 a5b2fb345d44dea9d02a524304178900 1bc750c664ecd959da25773f7e58f178 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintreq.f64.f64 d3, d12 ef4d9f5c013190559328cc55595d95de 2a53d417f8dec693dc12ea7e908ba7b2 ef4d9f5c013190559328cc55595d95de 2a53d417f8dec693dc12ea7e908ba7b2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: 7424 calls, 7662 iters
+vrintreq.f64.f64 d3, d12 e6d18d2b9025312df6d1d5557f1216b9 e3ee24e455a606bdbd1209330791f707 e6d18d2b9025312df6d1d5557f1216b9 e3ee24e455a606bdbd1209330791f707 fpscr=00000000
+vrintreq.f64.f64 d3, d12 75a7be4303bf46eb660c13529c5c4fdd c5eacdb8df2aa0add332b69436b6961a 75a7be4303bf46eb660c13529c5c4fdd c5eacdb8df2aa0add332b69436b6961a fpscr=00000000
+vrintreq.f64.f64 d3, d12 33174bf5bd39460967ea149ae992f68d 7e219d65f216aac2ba9b90d0ee63d559 33174bf5bd39460967ea149ae992f68d 7e219d65f216aac2ba9b90d0ee63d559 fpscr=00000000
+vrintreq.f64.f64 d3, d12 5511d528139f846ceb1c09a913102e3d f836e455636d667c1861f07fc80b1439 5511d528139f846ceb1c09a913102e3d f836e455636d667c1861f07fc80b1439 fpscr=00000000
+vrintreq.f64.f64 d3, d12 5c8cc6e9eacae8aa388fa662dfb0e683 5486b37f5e362b59c6b62e7496a900ce 5c8cc6e9eacae8aa388fa662dfb0e683 5486b37f5e362b59c6b62e7496a900ce fpscr=00000000
+vrintreq.f64.f64 d3, d12 a7296ddf9af9314d28f0684b08da562c 673a3b43536de399d9fbc17d59b8982a a7296ddf9af9314d28f0684b08da562c 673a3b43536de399d9fbc17d59b8982a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintreq.f64.f64 d3, d12 1ffa00c523e061348bc5fbf9b643fb0d 467f78553642be14467f78553642be14 1ffa00c523e061348bc5fbf9b643fb0d 467f78553642be14467f78553642be14 fpscr=00000000
+vrintreq.f64.f64 d3, d12 f3fc5449856d78007bb08e1bef6c5634 eab545a9d2deeb480d1ed55113a077b3 f3fc5449856d78007bb08e1bef6c5634 eab545a9d2deeb480d1ed55113a077b3 fpscr=00000000
+vrintreq.f64.f64 d3, d12 708971742a50f6f024ae096e2f9a32c9 98dad91a6e530094191c93d4073e1f7b 708971742a50f6f024ae096e2f9a32c9 98dad91a6e530094191c93d4073e1f7b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintreq.f64.f64 d3, d12 badfa5a78fb3d0b74d6c2319cdede505 1aa77712d4b4c92d1aa77712d4b4c92d badfa5a78fb3d0b74d6c2319cdede505 1aa77712d4b4c92d1aa77712d4b4c92d fpscr=00000000
+vrintreq.f64.f64 d3, d12 8b4b8eed2bcc2c126dee24eb90adada5 b960588477e22088f793cfbe185231e7 8b4b8eed2bcc2c126dee24eb90adada5 b960588477e22088f793cfbe185231e7 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintreq.f64.f64 d3, d12 d0f29ecff2fe5e7f5fc34f36b724e895 2f7bc25255d727bfe51a29d76a8da565 d0f29ecff2fe5e7f5fc34f36b724e895 2f7bc25255d727bfe51a29d76a8da565 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintreq.f64.f64 d3, d12 e0d27759e9fe106c33d3cba4ee659846 ca1da99bded6e9065041323840723f50 e0d27759e9fe106c33d3cba4ee659846 ca1da99bded6e9065041323840723f50 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintreq.f64.f64 d3, d12 27b164047ce462c7828f2f4c2860f0fd 7d7dd94364572c1174292b927858fa29 27b164047ce462c7828f2f4c2860f0fd 7d7dd94364572c1174292b927858fa29 fpscr=00000000
+vrintreq.f64.f64 d3, d12 b0082dc3c69ee2313bd1be34311d9e02 bd41af714d68879068ef6cdac64b1ae7 b0082dc3c69ee2313bd1be34311d9e02 bd41af714d68879068ef6cdac64b1ae7 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vrintreq.f64.f64 d3, d12 bb1d53139c0a1990bb1d53139c0a1990 649f8f54194d2db6649f8f54194d2db6 bb1d53139c0a1990bb1d53139c0a1990 649f8f54194d2db6649f8f54194d2db6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vrintreq.f64.f64 d3, d12 0c895c8d0d67d7200c895c8d0d67d720 07fce33ab8bc7465339ae49f2f6958d3 0c895c8d0d67d7200c895c8d0d67d720 07fce33ab8bc7465339ae49f2f6958d3 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintreq.f64.f64 d3, d12 a74e60526388d207a25f63e551506609 c650c10d513c2c67488e717eaabfc3f0 a74e60526388d207a25f63e551506609 c650c10d513c2c67488e717eaabfc3f0 fpscr=00000000
+vrintreq.f64.f64 d3, d12 f55e123863d3f97419dba241a82e2c66 a516a1fde031ec9149ac27de727705ee f55e123863d3f97419dba241a82e2c66 a516a1fde031ec9149ac27de727705ee fpscr=00000000
+vrintreq.f64.f64 d3, d12 6ef61084faa0f51ffdae1af25eee35ed 03f1397c09a98e5c92f8d11e01f01500 6ef61084faa0f51ffdae1af25eee35ed 03f1397c09a98e5c92f8d11e01f01500 fpscr=00000000
+vrintreq.f64.f64 d3, d12 ad43c8600dce5809960ed1cabb92180f f9b5add039e9a41968adc8587b453160 ad43c8600dce5809960ed1cabb92180f f9b5add039e9a41968adc8587b453160 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintreq.f64.f64 d3, d12 6a0feb007cd1028f58c89ca6d84094de e5e770d032c046060c676acc55af7ed4 6a0feb007cd1028f58c89ca6d84094de e5e770d032c046060c676acc55af7ed4 fpscr=00000000
+vrintreq.f64.f64 d3, d12 f5b11090304ec84a1f7cbe9f1042afc3 0831b515057d5b7aa6fed596d7a85cc8 f5b11090304ec84a1f7cbe9f1042afc3 0831b515057d5b7aa6fed596d7a85cc8 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintreq.f64.f64 d3, d12 16096e82f35c30ddcaf9bec45dcbd38e 9604a38c2a133ffb34e6e97d524ec496 16096e82f35c30ddcaf9bec45dcbd38e 9604a38c2a133ffb34e6e97d524ec496 fpscr=00000000
+vrintreq.f64.f64 d3, d12 426f5738877051541edd2061aef3b994 a1728ac66c7b51cf385e263e98079746 426f5738877051541edd2061aef3b994 a1728ac66c7b51cf385e263e98079746 fpscr=00000000
+vrintreq.f64.f64 d3, d12 2d9fdde41f278af0bfd0558bd001951a 9517bd5ecf292e45e418c206a0573864 2d9fdde41f278af0bfd0558bd001951a 9517bd5ecf292e45e418c206a0573864 fpscr=00000000
+vrintreq.f64.f64 d3, d12 aaad2c6cd69db03c0a45f33befe8e9d9 6e74c63d9680b3882706b153a745e4a6 aaad2c6cd69db03c0a45f33befe8e9d9 6e74c63d9680b3882706b153a745e4a6 fpscr=00000000
+vrintreq.f64.f64 d3, d12 61960e3ab665f7fd636f206661aaf2fa 1484a7dc9b634050acb2bc5ec0d0b4ed 61960e3ab665f7fd636f206661aaf2fa 1484a7dc9b634050acb2bc5ec0d0b4ed fpscr=00000000
+vrintreq.f64.f64 d3, d12 5964c04d5c373d7ad8b8487dce25e597 ee3667d58a999eac03b096f08ebf1234 5964c04d5c373d7ad8b8487dce25e597 ee3667d58a999eac03b096f08ebf1234 fpscr=00000000
+vrintreq.f64.f64 d3, d12 0c3b8f29e3718b49d1fc611bd784d114 b83cd26bf285ba285e0a74bda45a9582 0c3b8f29e3718b49d1fc611bd784d114 b83cd26bf285ba285e0a74bda45a9582 fpscr=00000000
+vrintreq.f64.f64 d3, d12 439ee80b79984ecf503c2cabca69ad7d 654579bf8be41a7e3bece3caf0b78aef 439ee80b79984ecf503c2cabca69ad7d 654579bf8be41a7e3bece3caf0b78aef fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintreq.f64.f64 d3, d12 df2058a73b75d5afe8448ecf294e419b 0b53741332f3fdef86326295a59724a1 df2058a73b75d5afe8448ecf294e419b 0b53741332f3fdef86326295a59724a1 fpscr=00000000
+vrintreq.f64.f64 d3, d12 56d4919969d945f7cb4e42dc12aa303b 76dfd463a0a526c5cbabaaed54342feb 56d4919969d945f7cb4e42dc12aa303b 76dfd463a0a526c5cbabaaed54342feb fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vrintreq.f64.f64 d3, d12 d23b47349af9c7003eaee16136adda59 c62d20c66dd3d34fc62d20c66dd3d34f d23b47349af9c7003eaee16136adda59 c62d20c66dd3d34fc62d20c66dd3d34f fpscr=00000000
+vrintreq.f64.f64 d3, d12 3ad8b53bea8c7acc298aa5c4c2f39a39 ca1850321439cd76090d78e043188995 3ad8b53bea8c7acc298aa5c4c2f39a39 ca1850321439cd76090d78e043188995 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintreq.f64.f64 d3, d12 a5fa129d6284935b70b1d4926e81819a f6897c938d7b590dfcad3fcdb4c99997 a5fa129d6284935b70b1d4926e81819a f6897c938d7b590dfcad3fcdb4c99997 fpscr=00000000
+vrintreq.f64.f64 d3, d12 57437d906598e26441a1713e13ba7cfc 9987f1510be55ba698d67298d4b13519 57437d906598e26441a1713e13ba7cfc 9987f1510be55ba698d67298d4b13519 fpscr=00000000
+vrintreq.f64.f64 d3, d12 2c21cf2cf04988211e143a37bedb5db6 c3a97fcf517f3dbfea0164b0fd72187f 2c21cf2cf04988211e143a37bedb5db6 c3a97fcf517f3dbfea0164b0fd72187f fpscr=00000000
+vrintreq.f64.f64 d3, d12 39481e46e3b180b5b86cb051d789af75 d99ebf25fbeb0042571dff0101163e0f 39481e46e3b180b5b86cb051d789af75 d99ebf25fbeb0042571dff0101163e0f fpscr=00000000
+vrintreq.f64.f64 d3, d12 0448a5ac0c635520b8460bd48f0fd480 16caeb8168de0b7457425dc60a4398f6 0448a5ac0c635520b8460bd48f0fd480 16caeb8168de0b7457425dc60a4398f6 fpscr=00000000
+vrintreq.f64.f64 d3, d12 cf677f55abe251b5c9c803e5893f4fe8 ac46d12b38f911155181faf4378df63c cf677f55abe251b5c9c803e5893f4fe8 ac46d12b38f911155181faf4378df63c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintreq.f64.f64 d3, d12 ae2b84f8a2cd7d52ea6df26051d70af6 3977d2dd6476b3d83977d2dd6476b3d8 ae2b84f8a2cd7d52ea6df26051d70af6 3977d2dd6476b3d83977d2dd6476b3d8 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintreq.f64.f64 d3, d12 ec15a7af6f3e0300835d7ef39c29ce07 04a2c27ba1735002afb58bc60145e391 ec15a7af6f3e0300835d7ef39c29ce07 04a2c27ba1735002afb58bc60145e391 fpscr=00000000
+vrintreq.f64.f64 d3, d12 aa8d78607f7779e492c236bc6eb364e4 8ab7f6cd19d0638cdf56622f3f5469d7 aa8d78607f7779e492c236bc6eb364e4 8ab7f6cd19d0638cdf56622f3f5469d7 fpscr=00000000
+vrintreq.f64.f64 d3, d12 2fd139573c4556adb6f8d66c3fafa7dc 908463a9294b4338acded0167f652a65 2fd139573c4556adb6f8d66c3fafa7dc 908463a9294b4338acded0167f652a65 fpscr=00000000
+vrintrne.f64.f64 d4, d13 2bb8000c125a817c09d77cf53b6dbdfa 808dd0d93bc51a8d3192c3a3d2300a63 2bb8000c125a817c8000000000000000 808dd0d93bc51a8d3192c3a3d2300a63 fpscr=00000000
+vrintrne.f64.f64 d4, d13 a76f5178886ddf5edf638f52f1a3ca99 8b6b8904ca5be55be6e62a6f036bd5ee a76f5178886ddf5e8000000000000000 8b6b8904ca5be55be6e62a6f036bd5ee fpscr=00000000
+vrintrne.f64.f64 d4, d13 b8d9f9582361c1915ca8e177744c423a 32b965542ba325970917d9b9f0c9f32f b8d9f9582361c1910000000000000000 32b965542ba325970917d9b9f0c9f32f fpscr=00000000
+vrintrne.f64.f64 d4, d13 4cd3ad825730a378844093e786c9e7b7 846690916818489917b985c59da30ad4 4cd3ad825730a3788000000000000000 846690916818489917b985c59da30ad4 fpscr=00000000
+vrintrne.f64.f64 d4, d13 dddb8aa1502cc9f02939ceabaa6aa7da ade3ad2274666f379f223517ae8b0a6c dddb8aa1502cc9f08000000000000000 ade3ad2274666f379f223517ae8b0a6c fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vrintrne.f64.f64 d4, d13 fa136d46a6a9bc09b65e63a70e555852 7abefd9338b68cac7abefd9338b68cac fa136d46a6a9bc097abefd9338b68cac 7abefd9338b68cac7abefd9338b68cac fpscr=00000000
+vrintrne.f64.f64 d4, d13 7ef94f9c8592b6ad395fe501a81bded6 1ed9069d1f3ff5c32305363409f6613a 7ef94f9c8592b6ad0000000000000000 1ed9069d1f3ff5c32305363409f6613a fpscr=00000000
+vrintrne.f64.f64 d4, d13 55f09fe02a4ef9abed0d01f99e382e33 7358285c6dd59168b268880b7093e28f 55f09fe02a4ef9ab7358285c6dd59168 7358285c6dd59168b268880b7093e28f fpscr=00000000
+vrintrne.f64.f64 d4, d13 91501f1ae5cbac08a9db9c8bab0a76d0 3dd48ec36077c5dd8a5cea24ed1eb4f6 91501f1ae5cbac080000000000000000 3dd48ec36077c5dd8a5cea24ed1eb4f6 fpscr=00000000
+vrintrne.f64.f64 d4, d13 42da6412dfe2c43d87543f07ddff189b 2333e930f6e9476801e1295dd55073b1 42da6412dfe2c43d0000000000000000 2333e930f6e9476801e1295dd55073b1 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintrne.f64.f64 d4, d13 8f8cefdbb45835275cf85d9c1beb393c abe51dfab674b1bcabe51dfab674b1bc 8f8cefdbb45835278000000000000000 abe51dfab674b1bcabe51dfab674b1bc fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintrne.f64.f64 d4, d13 59e012c0da77fa94be4f5490493eeaf0 00897e8997ab532e00897e8997ab532e 59e012c0da77fa940000000000000000 00897e8997ab532e00897e8997ab532e fpscr=00000000
+vrintrne.f64.f64 d4, d13 337e56e4b2dec726c2fa384ef35b147b 31fb003f08ade43bb1ff81fa1a4107e4 337e56e4b2dec7260000000000000000 31fb003f08ade43bb1ff81fa1a4107e4 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintrne.f64.f64 d4, d13 403684a4f5ab034bdecc686f57f1fe14 5e4aa7b008b4d9e02992ba2f7de8d48b 403684a4f5ab034b5e4aa7b008b4d9e0 5e4aa7b008b4d9e02992ba2f7de8d48b fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintrne.f64.f64 d4, d13 4e219d84604815b3e2cdf7f948ef138e b4323e355621ccc3c395d344caf3c099 4e219d84604815b38000000000000000 b4323e355621ccc3c395d344caf3c099 fpscr=00000000
+vrintrne.f64.f64 d4, d13 f0710cb4d5ad2028f77d7d70d9e61f60 3e7744e2e570c4a636f53b3f0dcb6b89 f0710cb4d5ad20280000000000000000 3e7744e2e570c4a636f53b3f0dcb6b89 fpscr=00000000
+vrintrne.f64.f64 d4, d13 501cfdd122c46c76e8d0897f8b71e87a 5f66910535b517667976d7163bfa886c 501cfdd122c46c765f66910535b51766 5f66910535b517667976d7163bfa886c fpscr=00000000
+vrintrne.f64.f64 d4, d13 a2041c9913bf7f828aaac2f28c0834c1 b18265a0d83ef4380b82357abee438e0 a2041c9913bf7f828000000000000000 b18265a0d83ef4380b82357abee438e0 fpscr=00000000
+vrintrne.f64.f64 d4, d13 1bc7634e4c91b02f71346d7a88047007 a01230a0d7e4e94b1e8a60f1a03d7f7d 1bc7634e4c91b02f8000000000000000 a01230a0d7e4e94b1e8a60f1a03d7f7d fpscr=00000000
+randV128: 7680 calls, 7927 iters
+vrintrne.f64.f64 d4, d13 46d5cfdb7a63001b580d8779cc5b2a99 0d826f0b5ee27312980014d210acb690 46d5cfdb7a63001b0000000000000000 0d826f0b5ee27312980014d210acb690 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintrne.f64.f64 d4, d13 01d77486fe17d17262ee15ec27590158 56f08c97ebfcff786513dc15d436c795 01d77486fe17d17256f08c97ebfcff78 56f08c97ebfcff786513dc15d436c795 fpscr=00000000
+vrintrne.f64.f64 d4, d13 044b0a6be7e2f27ceba1fd97c425e23b 07dfc60c440b9b9d5806c4789fdd138c 044b0a6be7e2f27c0000000000000000 07dfc60c440b9b9d5806c4789fdd138c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintrne.f64.f64 d4, d13 848aa7cd15a0503d848aa7cd15a0503d 389464c2f8f35d8a220add60f775cfc4 848aa7cd15a0503d0000000000000000 389464c2f8f35d8a220add60f775cfc4 fpscr=00000000
+vrintrne.f64.f64 d4, d13 a8ee0f4b7f0cf658f30c524629efa7bb 7883c11e6adad5e2bfbd10f8c2259439 a8ee0f4b7f0cf6587883c11e6adad5e2 7883c11e6adad5e2bfbd10f8c2259439 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintrne.f64.f64 d4, d13 a00bca34047f4cd33c7d91764d85a625 a941cff4e0b9dacf150c42673f7db245 a00bca34047f4cd38000000000000000 a941cff4e0b9dacf150c42673f7db245 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintrne.f64.f64 d4, d13 8fbe2a17898cb15a9322d074db2374ff b18e0bf13047ca63b18e0bf13047ca63 8fbe2a17898cb15a8000000000000000 b18e0bf13047ca63b18e0bf13047ca63 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintrne.f64.f64 d4, d13 9052b1941fee5d419052b1941fee5d41 78885bbe0d7260926a150ae3f4914cc5 9052b1941fee5d4178885bbe0d726092 78885bbe0d7260926a150ae3f4914cc5 fpscr=00000000
+vrintrne.f64.f64 d4, d13 0a3b54f24252878eccb7d6d7f2f6cf41 f2f97dd98cb58ae5db2679a0fd9e7c01 0a3b54f24252878ef2f97dd98cb58ae5 f2f97dd98cb58ae5db2679a0fd9e7c01 fpscr=00000000
+vrintrne.f64.f64 d4, d13 a256ba2e16d4887afb3f935e5ffe1021 b1d357f39cf2432678493db4d19a97a0 a256ba2e16d4887a8000000000000000 b1d357f39cf2432678493db4d19a97a0 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintrne.f64.f64 d4, d13 aa52b691549fbe858ab7cb901aa3538a f68ab21956b50fea8491c2821e134e2b aa52b691549fbe85f68ab21956b50fea f68ab21956b50fea8491c2821e134e2b fpscr=00000000
+vrintrne.f64.f64 d4, d13 68859814bc2f29ebe86d548f89fd050a 06abc0ad581d207accdbcb99d5ba495c 68859814bc2f29eb0000000000000000 06abc0ad581d207accdbcb99d5ba495c fpscr=00000000
+vrintrne.f64.f64 d4, d13 aacd45b23dae67ff55ee04e1e742d0b6 f7a75f3dedb9486eaf3dee9f98e57530 aacd45b23dae67fff7a75f3dedb9486e f7a75f3dedb9486eaf3dee9f98e57530 fpscr=00000000
+vrintrne.f64.f64 d4, d13 870fbcf765fb8709ee9ad13fbcec9a96 d6e8fc1410802fc7b69d6d0174a35337 870fbcf765fb8709d6e8fc1410802fc7 d6e8fc1410802fc7b69d6d0174a35337 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintrne.f64.f64 d4, d13 cb34000d5cabb435cb34000d5cabb435 cd108f59527580861e3de18f437b6141 cb34000d5cabb435cd108f5952758086 cd108f59527580861e3de18f437b6141 fpscr=00000000
+vrintrne.f64.f64 d4, d13 7a568c74620b1dc5c35f438b1793371f 84de9f29455d2a188c161e8516e24ff7 7a568c74620b1dc58000000000000000 84de9f29455d2a188c161e8516e24ff7 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintrne.f64.f64 d4, d13 044565123ec677f5044565123ec677f5 4d5eb546485a8e234d5eb546485a8e23 044565123ec677f54d5eb546485a8e23 4d5eb546485a8e234d5eb546485a8e23 fpscr=00000000
+vrintrne.f64.f64 d4, d13 0d5f0deaa327a3681f7e714f53e5c994 77b05bec059012f1cead9f5201e15a14 0d5f0deaa327a36877b05bec059012f1 77b05bec059012f1cead9f5201e15a14 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintrne.f64.f64 d4, d13 518d0e3ebcf785f83e92acd253f7cd99 c221fd898874baf9cedd83b66e67730b 518d0e3ebcf785f8c221fd8988740000 c221fd898874baf9cedd83b66e67730b fpscr=00000000
+vrintrne.f64.f64 d4, d13 b030c2f9fad2e4c09ce73c6226d44682 4bae058dc7320df8ca32636e2f6f0c07 b030c2f9fad2e4c04bae058dc7320df8 4bae058dc7320df8ca32636e2f6f0c07 fpscr=00000000
+vrintrne.f64.f64 d4, d13 879bc0440fa1b72920018d3bae9d6209 fea88f1cfbcb9c44261baab3b7c464ee 879bc0440fa1b729fea88f1cfbcb9c44 fea88f1cfbcb9c44261baab3b7c464ee fpscr=00000000
+vrintrne.f64.f64 d4, d13 0170a7405c4ff2641cb04979c8a9d4a0 683fcad0a6671370780f2a4f3d7e9744 0170a7405c4ff264683fcad0a6671370 683fcad0a6671370780f2a4f3d7e9744 fpscr=00000000
+vrintrne.f64.f64 d4, d13 39358bf5c9e6772ace877e9ab8be5648 7d6ee9b05fd55119f1bbf356235a0e8e 39358bf5c9e6772a7d6ee9b05fd55119 7d6ee9b05fd55119f1bbf356235a0e8e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintrne.f64.f64 d4, d13 8ba9e1102de36806fb273f7fbda44446 a668315b7f4c02d52f4dfc12408490ad 8ba9e1102de368068000000000000000 a668315b7f4c02d52f4dfc12408490ad fpscr=00000000
+vrintrne.f64.f64 d4, d13 a93988289bf3a2495680845a288c3a01 a8f73cea65c63a27fd64351d3fb2f03a a93988289bf3a2498000000000000000 a8f73cea65c63a27fd64351d3fb2f03a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintrne.f64.f64 d4, d13 9468f57e32f223819468f57e32f22381 569887088f658df7c31f54db238eff42 9468f57e32f22381569887088f658df7 569887088f658df7c31f54db238eff42 fpscr=00000000
+vrintrne.f64.f64 d4, d13 5d806ae803e5c525e3a1c97fd978c788 1865b9cf9a622125fc220836beec7ec8 5d806ae803e5c5250000000000000000 1865b9cf9a622125fc220836beec7ec8 fpscr=00000000
+vrintrne.f64.f64 d4, d13 401990cf151c7f4da2c476be7da12afa ec8869e8e1097b1aca8ef99a4fe2aa1e 401990cf151c7f4dec8869e8e1097b1a ec8869e8e1097b1aca8ef99a4fe2aa1e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintrne.f64.f64 d4, d13 86d48fd6f985127d943461254a29e745 70bd5f21d73e984470bd5f21d73e9844 86d48fd6f985127d70bd5f21d73e9844 70bd5f21d73e984470bd5f21d73e9844 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintrne.f64.f64 d4, d13 0829eee569b2f8230829eee569b2f823 ee58238e8d54116de6834db0f029a9b0 0829eee569b2f823ee58238e8d54116d ee58238e8d54116de6834db0f029a9b0 fpscr=00000000
+vrintrne.f64.f64 d4, d13 f1d28096033415e976b518a51db2c16f 234303ce9f64bf98a05b41c3a69823b2 f1d28096033415e90000000000000000 234303ce9f64bf98a05b41c3a69823b2 fpscr=00000000
+vrintr.f64.f64 d5, d14 c7cf036df53b712ad2604abc5a05b647 0f250b4007a9ba23c0e67cecde3a3c76 c0e67ce000000000d2604abc5a05b647 0f250b4007a9ba23c0e67cecde3a3c76 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintr.f64.f64 d5, d14 d1636652f0b18328144363b7c0f531c0 84168ffba70f689661e3a970b2beba6b 61e3a970b2beba6b144363b7c0f531c0 84168ffba70f689661e3a970b2beba6b fpscr=00000000
+vrintr.f64.f64 d5, d14 95d4ccdaf659001572fff3271262304b cca93dc66d36685ec38a1c0c737492d0 c38a1c0c737492d072fff3271262304b cca93dc66d36685ec38a1c0c737492d0 fpscr=00000000
+vrintr.f64.f64 d5, d14 b8f952ad7486ef3c6b56a6b27b10af93 035d89fbc7117bd2ae91efd57a0ecdfa 80000000000000006b56a6b27b10af93 035d89fbc7117bd2ae91efd57a0ecdfa fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintr.f64.f64 d5, d14 ec29093fabfea59bec29093fabfea59b 9fab4a3e48f1134503a1b00a810ca82f 0000000000000000ec29093fabfea59b 9fab4a3e48f1134503a1b00a810ca82f fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintr.f64.f64 d5, d14 53bbef63d4f373652b65f5ea900fdc1c a2c603e15a9198b3185209cccb52ea73 00000000000000002b65f5ea900fdc1c a2c603e15a9198b3185209cccb52ea73 fpscr=00000000
+vrintr.f64.f64 d5, d14 d142efd22e668948b3111b74160b2fe5 544388650be1629a3ed0300021b61c7d 0000000000000000b3111b74160b2fe5 544388650be1629a3ed0300021b61c7d fpscr=00000000
+vrintr.f64.f64 d5, d14 25b5522436c757ca19058daf59e112f9 bbda94f04d0ae894c6f4e274691a7fd6 c6f4e274691a7fd619058daf59e112f9 bbda94f04d0ae894c6f4e274691a7fd6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintr.f64.f64 d5, d14 9faaf466e142b109d9bb6c3216ec3e4e 7196fb59b964e5b463880e2688108234 63880e2688108234d9bb6c3216ec3e4e 7196fb59b964e5b463880e2688108234 fpscr=00000000
+vrintr.f64.f64 d5, d14 9baa14631bf69d5bfdb214a3b9153f0e e4d140e502acde9ef977706a31b89b27 f977706a31b89b27fdb214a3b9153f0e e4d140e502acde9ef977706a31b89b27 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintr.f64.f64 d5, d14 f0ee2c429eefc86cf0ee2c429eefc86c 3051d7286469671f791bb4b7b856b6b7 791bb4b7b856b6b7f0ee2c429eefc86c 3051d7286469671f791bb4b7b856b6b7 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintr.f64.f64 d5, d14 a32f5d61564ee0f3400ae6cb833141e7 e419853ca193083c74280d6807322ff4 74280d6807322ff4400ae6cb833141e7 e419853ca193083c74280d6807322ff4 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintr.f64.f64 d5, d14 7c0348b78eb37c7b7c0348b78eb37c7b dea0ce85e9db944a5d4d32bddffc2fa4 5d4d32bddffc2fa47c0348b78eb37c7b dea0ce85e9db944a5d4d32bddffc2fa4 fpscr=00000000
+vrintr.f64.f64 d5, d14 6cac401bf0a95a8640a3f76654edf5ba dbd57e02c16248aac136d4907a173bd0 c136d4900000000040a3f76654edf5ba dbd57e02c16248aac136d4907a173bd0 fpscr=00000000
+vrintr.f64.f64 d5, d14 55015443c3dff071b960c438f85c7c4c 45ef59dd67b1f649b454aa9c72733786 8000000000000000b960c438f85c7c4c 45ef59dd67b1f649b454aa9c72733786 fpscr=00000000
+vrintr.f64.f64 d5, d14 731d0c1de8e32b29e029949e9b88a40b 400eb0ffc092090bf7cbdd3d1758543d f7cbdd3d1758543de029949e9b88a40b 400eb0ffc092090bf7cbdd3d1758543d fpscr=00000000
+vrintr.f64.f64 d5, d14 89f7b7bb7905670397620da3ed0492bd b76dd6dd3d3a5b8c2d6ebd8d10327c24 000000000000000097620da3ed0492bd b76dd6dd3d3a5b8c2d6ebd8d10327c24 fpscr=00000000
+vrintr.f64.f64 d5, d14 37ae4e266cca7801e458763bafce187a f3592ca24df6f39660c70e83aabf9668 60c70e83aabf9668e458763bafce187a f3592ca24df6f39660c70e83aabf9668 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintr.f64.f64 d5, d14 3c351c902cc58863dde6ba3c4900e43d 4b438b040737889bb1293e9c083e2671 8000000000000000dde6ba3c4900e43d 4b438b040737889bb1293e9c083e2671 fpscr=00000000
+vrintr.f64.f64 d5, d14 1b018c410a4ff07f8dd09a92713eeb22 a905062f6f7f5cb8a05f17c7b1bb0bb1 80000000000000008dd09a92713eeb22 a905062f6f7f5cb8a05f17c7b1bb0bb1 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vrintr.f64.f64 d5, d14 e2bb6b5bf2ab8fbce2bb6b5bf2ab8fbc 366ecb91520d88ce4242917130fd5750 4242917130fd8000e2bb6b5bf2ab8fbc 366ecb91520d88ce4242917130fd5750 fpscr=00000000
+vrintr.f64.f64 d5, d14 4526f212b5ac7cebf0223aec026528f9 5e027e651cf114e102e4bd3376c76724 0000000000000000f0223aec026528f9 5e027e651cf114e102e4bd3376c76724 fpscr=00000000
+vrintr.f64.f64 d5, d14 d2d4b3c3dc9f77306ff161bcc49ffd54 977fbc50f1354e01f27be8de3d759706 f27be8de3d7597066ff161bcc49ffd54 977fbc50f1354e01f27be8de3d759706 fpscr=00000000
+vrintr.f64.f64 d5, d14 253f6500cdead09216f96c125db279db c51286743711e334358259c524320f44 000000000000000016f96c125db279db c51286743711e334358259c524320f44 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintr.f64.f64 d5, d14 99085c5bd397b11799085c5bd397b117 ccb784a19f830c0cbfad9e6deabe8bcb 800000000000000099085c5bd397b117 ccb784a19f830c0cbfad9e6deabe8bcb fpscr=00000000
+vrintr.f64.f64 d5, d14 cd52ef9d4419a6dbd0d062794548168f 87248dfee158b2885ceb905ddee92c71 5ceb905ddee92c71d0d062794548168f 87248dfee158b2885ceb905ddee92c71 fpscr=00000000
+vrintr.f64.f64 d5, d14 0942fe1a43ebcd96c09c2440b4e1afcd 5d3f68b77e96e9b6a878f4346495b1e4 8000000000000000c09c2440b4e1afcd 5d3f68b77e96e9b6a878f4346495b1e4 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintr.f64.f64 d5, d14 feb4464ae3fb4f79feb4464ae3fb4f79 4ad3187a1b1b534787c2aa279e624e86 8000000000000000feb4464ae3fb4f79 4ad3187a1b1b534787c2aa279e624e86 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintr.f64.f64 d5, d14 4e55d3dc3fceb9315adb2e4c18627584 3f8381041239787db70d9f9809a0556b 80000000000000005adb2e4c18627584 3f8381041239787db70d9f9809a0556b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintr.f64.f64 d5, d14 581f5b2f0361cdbe581f5b2f0361cdbe 6da282fdb8db1b2e1610a860ac5ee2f3 0000000000000000581f5b2f0361cdbe 6da282fdb8db1b2e1610a860ac5ee2f3 fpscr=00000000
+vrintr.f64.f64 d5, d14 14bd5cacd566c416ebb1e76368ee2846 8305908645ae9ccea6ce98443b36b193 8000000000000000ebb1e76368ee2846 8305908645ae9ccea6ce98443b36b193 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintr.f64.f64 d5, d14 6e684ccf7d309eda9fb2ab1515d08f9c 28de38244daee7592728af22d612386e 00000000000000009fb2ab1515d08f9c 28de38244daee7592728af22d612386e fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintr.f64.f64 d5, d14 6c027b9999997f3f6c027b9999997f3f 29527c1d7cd2cc7c347c3b876f29a4a3 00000000000000006c027b9999997f3f 29527c1d7cd2cc7c347c3b876f29a4a3 fpscr=00000000
+randV128: 7936 calls, 8186 iters
+vrintr.f64.f64 d5, d14 edebc5a4f182e642d37e09628252945e ded85716faa6e741200819b713e1c33a 0000000000000000d37e09628252945e ded85716faa6e741200819b713e1c33a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintr.f64.f64 d5, d14 f21fd8cc4f7ff2c977bcea82efb57dac 893a008268ad1699b26252abf5d82099 800000000000000077bcea82efb57dac 893a008268ad1699b26252abf5d82099 fpscr=00000000
+vrintr.f64.f64 d5, d14 681e3b5b234103c291af3fb331c20b9d c8cd8173235543b52cb7a4de4f79dbc0 000000000000000091af3fb331c20b9d c8cd8173235543b52cb7a4de4f79dbc0 fpscr=00000000
+vrintr.f64.f64 d5, d14 1c076b5897aad1b3c9ddd5539cd4503f 224bcf549761646e45fd74140298b51d 45fd74140298b51dc9ddd5539cd4503f 224bcf549761646e45fd74140298b51d fpscr=00000000
+vrintr.f64.f64 d5, d14 bf931db576f97906ce564d5caa53efdf 61d323b2da9eca4f06f64086d258d873 0000000000000000ce564d5caa53efdf 61d323b2da9eca4f06f64086d258d873 fpscr=00000000
+vrintr.f64.f64 d5, d14 45ceb2ca0a9cbff56711cc1cef838fb6 c46400c75ae3ff3f27ff4345756c749c 00000000000000006711cc1cef838fb6 c46400c75ae3ff3f27ff4345756c749c fpscr=00000000
+vrintr.f64.f64 d5, d14 a26091a7a6b6b17a5a32e311cfb042f9 b06ed98edc0c1ca83fef3f876a509a18 3ff00000000000005a32e311cfb042f9 b06ed98edc0c1ca83fef3f876a509a18 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vrintr.f64.f64 d5, d14 6f30a6d0796542af6f30a6d0796542af 1cf74d043dc1ac491cf74d043dc1ac49 00000000000000006f30a6d0796542af 1cf74d043dc1ac491cf74d043dc1ac49 fpscr=00000000
+vrintr.f64.f64 d5, d14 a5609c8d6d519db3534a7e6cc4503d64 28061d843bfb0fbb46d377e655b43849 46d377e655b43849534a7e6cc4503d64 28061d843bfb0fbb46d377e655b43849 fpscr=00000000
+vrintr.f64.f64 d5, d14 034f9479bd2b4840fd6e45eedd30c119 90dbab155efeec62c1dc1372d315ff4b c1dc1372d3000000fd6e45eedd30c119 90dbab155efeec62c1dc1372d315ff4b fpscr=00000000
+vrintr.f64.f64 d5, d14 078b253cc3f4c778e96d2e02234b59f4 f001b246d7bbe2cca2c1cb702f8bf00b 8000000000000000e96d2e02234b59f4 f001b246d7bbe2cca2c1cb702f8bf00b fpscr=00000000
+vrintr.f64.f64 d5, d14 477f15f9b9da998514251fc255311a8f bb0a7c06540b6675a13a63e6fe70fa82 800000000000000014251fc255311a8f bb0a7c06540b6675a13a63e6fe70fa82 fpscr=00000000
+vrintr.f64.f64 d5, d14 3bec53b1f7707a4cbddbdbf1a4f9c1d8 24d165d2b8810227591424ed93279590 591424ed93279590bddbdbf1a4f9c1d8 24d165d2b8810227591424ed93279590 fpscr=00000000
+vrintr.f64.f64 d5, d14 a04818c58d01eb628807f1995be4d96a e15de7046b9c961b75b06571d010a1b9 75b06571d010a1b98807f1995be4d96a e15de7046b9c961b75b06571d010a1b9 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintr.f64.f64 d5, d14 5dbf3867055dddbac51aaabb5823d9c2 82a58423d4f8864482a58423d4f88644 8000000000000000c51aaabb5823d9c2 82a58423d4f8864482a58423d4f88644 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintr.f64.f64 d5, d14 4c0d4bb3b84401975e5ccb07b7b33fe7 e86c92c537ec535c93afba3d3fd0c240 80000000000000005e5ccb07b7b33fe7 e86c92c537ec535c93afba3d3fd0c240 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintr.f64.f64 d5, d14 623d6493fb6cebe8c9cb2ba1120313bd 5ad5a24e88f0fbb15ad5a24e88f0fbb1 5ad5a24e88f0fbb1c9cb2ba1120313bd 5ad5a24e88f0fbb15ad5a24e88f0fbb1 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 9fdddfc98cedc34cf26cbdd053636547 5603d7762626b1389e5067719c25e928 9fdddfc98cedc34cf26cbdd053636547 5603d7762626b1389e5067719c25e928 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 7e73d5fe512a26007e73d5fe512a2600 6528daa4530293262a4854ebaeb9b199 7e73d5fe512a26007e73d5fe512a2600 6528daa4530293262a4854ebaeb9b199 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 5c00f87c073ca5df7e24f28de955c9e2 a5bcbbb92b4cf1dbaaeffe9d12f7310d 5c00f87c073ca5df7e24f28de955c9e2 a5bcbbb92b4cf1dbaaeffe9d12f7310d fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 f53f350dcb8118b1f53f350dcb8118b1 cdb58e6f81a4f30bdbb176a17af6fc41 f53f350dcb8118b1f53f350dcb8118b1 cdb58e6f81a4f30bdbb176a17af6fc41 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 f825348ce754d8295a79ed75cc2978c3 67db9e19f6d44c36abffb6129a3ff778 f825348ce754d8295a79ed75cc2978c3 67db9e19f6d44c36abffb6129a3ff778 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 2f679302f7fff43f4076020a62b1bf41 dd308b502ea0a8bbbe42164c46828732 2f679302f7fff43f4076020a62b1bf41 dd308b502ea0a8bbbe42164c46828732 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 12318e45cc60e2a752b5526ce1f9efcc 704a5927204d2d4a325681997ca3045e 12318e45cc60e2a752b5526ce1f9efcc 704a5927204d2d4a325681997ca3045e fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 27fa30aa884ee74e82d24027b79714dd f34baa4d361af822dd3cc3c6d8df41f8 27fa30aa884ee74e82d24027b79714dd f34baa4d361af822dd3cc3c6d8df41f8 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 90be4e98954fa902c38e207b2b7bbe0c d1767539330f0ed158503525e4016972 90be4e98954fa902c38e207b2b7bbe0c d1767539330f0ed158503525e4016972 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxeq.f64.f64 d6, d15 48df279b0bbff81748df279b0bbff817 da7b95b68c15f9e2342da868efbd4f83 48df279b0bbff81748df279b0bbff817 da7b95b68c15f9e2342da868efbd4f83 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 bf94c2782dd80f67561dbe8f98bb3b9d 4a806ee10f3fca677b53c497750d4d8a bf94c2782dd80f67561dbe8f98bb3b9d 4a806ee10f3fca677b53c497750d4d8a fpscr=00000000
+vrintxeq.f64.f64 d6, d15 7645fe8674beeeabc83cadbe8b04940a 1f1d052540408ccfdd58ce5627523165 7645fe8674beeeabc83cadbe8b04940a 1f1d052540408ccfdd58ce5627523165 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 6f1eab11c97024213cad662001d691f9 521716f18779a76e6fad67e1262782e3 6f1eab11c97024213cad662001d691f9 521716f18779a76e6fad67e1262782e3 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 0bc46f310c6cca2b65ae5c1d78408ab7 55afbf8ec79397aca437d523b524df77 0bc46f310c6cca2b65ae5c1d78408ab7 55afbf8ec79397aca437d523b524df77 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 07d4f1a46475595089fb20a4abdf0758 d39c8da5421417275086517857b66ea1 07d4f1a46475595089fb20a4abdf0758 d39c8da5421417275086517857b66ea1 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxeq.f64.f64 d6, d15 56514a09b626b09a937501aa44ab105a 53636a20525c313c826835d6cd5024b4 56514a09b626b09a937501aa44ab105a 53636a20525c313c826835d6cd5024b4 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 fb1d52f0c1ff78607dd790b4148af8a3 02c4ad076a760af42eed41e00a4ff308 fb1d52f0c1ff78607dd790b4148af8a3 02c4ad076a760af42eed41e00a4ff308 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxeq.f64.f64 d6, d15 3f765647f722ec95feb37b799b3cf560 d6bf70247b4db14560262f7e75fc8087 3f765647f722ec95feb37b799b3cf560 d6bf70247b4db14560262f7e75fc8087 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxeq.f64.f64 d6, d15 3fa2621faeeeb1da3fa2621faeeeb1da 1f13af32de563d860642900504bffd56 3fa2621faeeeb1da3fa2621faeeeb1da 1f13af32de563d860642900504bffd56 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxeq.f64.f64 d6, d15 3734504153f58d1109d9b8e3c5ea687e 92c6a7c92b31f16bf839d3e10ae6629c 3734504153f58d1109d9b8e3c5ea687e 92c6a7c92b31f16bf839d3e10ae6629c fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 4a165e7933af8a6d4a165e7933af8a6d 3dc6babb215621d5cab9427bafc67d2d 4a165e7933af8a6d4a165e7933af8a6d 3dc6babb215621d5cab9427bafc67d2d fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 c49ca98e742dbacdc49ca98e742dbacd 234c08fd75f8b2254c9162e9222503df c49ca98e742dbacdc49ca98e742dbacd 234c08fd75f8b2254c9162e9222503df fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 632173feee3c645b632173feee3c645b 644336f1f89ebfc73a4ca59d47f71131 632173feee3c645b632173feee3c645b 644336f1f89ebfc73a4ca59d47f71131 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 bbcf152b991da773bbcf152b991da773 9aedea40996f50d29aedea40996f50d2 bbcf152b991da773bbcf152b991da773 9aedea40996f50d29aedea40996f50d2 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 17da099240ecf3df6509aa6414257d45 4a976e0b5f48cbe084e614a5b9e2e3db 17da099240ecf3df6509aa6414257d45 4a976e0b5f48cbe084e614a5b9e2e3db fpscr=00000000
+vrintxeq.f64.f64 d6, d15 575ac7f98349fb67aae06e334208d0fe 589c263d76ed21bc5b74ee1e45d5854b 575ac7f98349fb67aae06e334208d0fe 589c263d76ed21bc5b74ee1e45d5854b fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 9af79c8e037c70516a6e9cdaaff469ff 9ef4a3944df3c9d49ef4a3944df3c9d4 9af79c8e037c70516a6e9cdaaff469ff 9ef4a3944df3c9d49ef4a3944df3c9d4 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 7395a6bbe31716cb78e8c8aab62daaa8 ab5052451e0d74e776296d47a2f8228e 7395a6bbe31716cb78e8c8aab62daaa8 ab5052451e0d74e776296d47a2f8228e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vrintxeq.f64.f64 d6, d15 35df52dd395b5564e43fb140cab5fb34 523e46b870bec885523e46b870bec885 35df52dd395b5564e43fb140cab5fb34 523e46b870bec885523e46b870bec885 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 026ca90693fc6583dc4ba1f9e4a13d51 469676575afcde6353320bf3ab4a56e7 026ca90693fc6583dc4ba1f9e4a13d51 469676575afcde6353320bf3ab4a56e7 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 498b43c7c3a7f4130bc7a4df785044b4 47526f4aade6a2828b4c7e29034a825b 498b43c7c3a7f4130bc7a4df785044b4 47526f4aade6a2828b4c7e29034a825b fpscr=00000000
+vrintxeq.f64.f64 d6, d15 8b6db5dd9cc52b456259c5434a5ac3e0 c5c18507a358e55ccf2bbc8b97fcdfa7 8b6db5dd9cc52b456259c5434a5ac3e0 c5c18507a358e55ccf2bbc8b97fcdfa7 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 6be03ddd55aa6275a2e4ff253e627c77 19508a18e4bd02bf56aa38328ac5a5d3 6be03ddd55aa6275a2e4ff253e627c77 19508a18e4bd02bf56aa38328ac5a5d3 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 153eb9c3fa624dc7091ac18dbbc82047 368dcb81b766872cd8ba2a8242a8482d 153eb9c3fa624dc7091ac18dbbc82047 368dcb81b766872cd8ba2a8242a8482d fpscr=00000000
+vrintxeq.f64.f64 d6, d15 b0f5ac4f7a659ea30845342f069d3306 6c172942df2661fc8993ddf18218ddaf b0f5ac4f7a659ea30845342f069d3306 6c172942df2661fc8993ddf18218ddaf fpscr=00000000
+vrintxeq.f64.f64 d6, d15 38fba740241f101855fbe1dff56954f4 00feff415845ede6f94dde2e6f376dc6 38fba740241f101855fbe1dff56954f4 00feff415845ede6f94dde2e6f376dc6 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 b2150b787a63c91364a6b8fb05e0e257 af6ef38ff6d6e5e5d4d706a666612176 b2150b787a63c91364a6b8fb05e0e257 af6ef38ff6d6e5e5d4d706a666612176 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 3cf6759ece6904d83cf6759ece6904d8 2e1258560acfa50be56e2d807b486e6b 3cf6759ece6904d83cf6759ece6904d8 2e1258560acfa50be56e2d807b486e6b fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 b47a33fba3b7fbb4d27dc958b03067c6 41059e1db1323b6d0138836d869d3879 b47a33fba3b7fbb4d27dc958b03067c6 41059e1db1323b6d0138836d869d3879 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 de9ca56d372c772fd0a71c6d0b9823c7 fb3b5eb50b0cdfe8fb3b5eb50b0cdfe8 de9ca56d372c772fd0a71c6d0b9823c7 fb3b5eb50b0cdfe8fb3b5eb50b0cdfe8 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 94b24979c2d04c4097e399a4554c5c16 db721b8ed5700e78ab59218e159731d0 94b24979c2d04c4097e399a4554c5c16 db721b8ed5700e78ab59218e159731d0 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 b5880f61fedd20425c5543e8c7936b85 5307fb644310e267befa0eba8f6c446c b5880f61fedd20425c5543e8c7936b85 5307fb644310e267befa0eba8f6c446c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxeq.f64.f64 d6, d15 fd4a84aa423eaacaa94054b3e94c7a63 2e7d81d1653b606922e6bad669efd9f5 fd4a84aa423eaacaa94054b3e94c7a63 2e7d81d1653b606922e6bad669efd9f5 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxeq.f64.f64 d6, d15 7e57ef5abda44c6436db62d8d503bb36 e1a082289b9dff1de1a082289b9dff1d 7e57ef5abda44c6436db62d8d503bb36 e1a082289b9dff1de1a082289b9dff1d fpscr=00000000
+vrintxeq.f64.f64 d6, d15 3d96deb3906a9e6fda4a3243fab1d7cc 425762ffef7ae5c0019f5f8976908972 3d96deb3906a9e6fda4a3243fab1d7cc 425762ffef7ae5c0019f5f8976908972 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 3e25e79c36592546e9193ca251e28a22 a1d0a7d64b462ca55d7e51971a1f5611 3e25e79c36592546e9193ca251e28a22 a1d0a7d64b462ca55d7e51971a1f5611 fpscr=00000000
+vrintxeq.f64.f64 d6, d15 f2ec4d6bd823991353cb02104eff712c 99c93dd4c3ed00c62274b20a6d9b7bf8 f2ec4d6bd823991353cb02104eff712c 99c93dd4c3ed00c62274b20a6d9b7bf8 fpscr=00000000
+randV128: 8192 calls, 8449 iters
+vrintxeq.f64.f64 d6, d15 3043412377039d9dbf63e8c0b7216563 9621bc486f32a787a12dd36ca840d48f 3043412377039d9dbf63e8c0b7216563 9621bc486f32a787a12dd36ca840d48f fpscr=00000000
+vrintxeq.f64.f64 d6, d15 0b7293ee9e89d5d40f79607452c53585 659338cb7aecc4bccf0528461cf30127 0b7293ee9e89d5d40f79607452c53585 659338cb7aecc4bccf0528461cf30127 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxeq.f64.f64 d6, d15 9c685842346c76209c685842346c7620 88ee453421d5502a5be597c762f29ba2 9c685842346c76209c685842346c7620 88ee453421d5502a5be597c762f29ba2 fpscr=00000000
+vrintxne.f64.f64 d7, d16 49b16af265688ae95e141ba29973810e bcdccf6002b5acbaabc002d873d6cd12 80000000000000005e141ba29973810e bcdccf6002b5acbaabc002d873d6cd12 fpscr=00000000
+vrintxne.f64.f64 d7, d16 8d96c7fe1ee4860cec4048bc67f75afc e9ca67a7f85bfd5ae80ae4905125e8ff e80ae4905125e8ffec4048bc67f75afc e9ca67a7f85bfd5ae80ae4905125e8ff fpscr=00000000
+vrintxne.f64.f64 d7, d16 baa8cb25ecbbe07eeee5c0fa26eef99b 6b49ae52d3d7d78fa069cc5f1e0bba41 8000000000000000eee5c0fa26eef99b 6b49ae52d3d7d78fa069cc5f1e0bba41 fpscr=00000000
+vrintxne.f64.f64 d7, d16 f3abde207a8c76fa986faa650c405d8b 1e1c6703e8d6cbffa3e96e2088fe0c40 8000000000000000986faa650c405d8b 1e1c6703e8d6cbffa3e96e2088fe0c40 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxne.f64.f64 d7, d16 f81ddbd8a4184905f81ddbd8a4184905 1d9fc6b5613bb6b1d2dcb2a585e4bade d2dcb2a585e4badef81ddbd8a4184905 1d9fc6b5613bb6b1d2dcb2a585e4bade fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxne.f64.f64 d7, d16 df779793bd9b3960111dfc6061bff646 027e25ce9c17766a027e25ce9c17766a 0000000000000000111dfc6061bff646 027e25ce9c17766a027e25ce9c17766a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxne.f64.f64 d7, d16 dc615cab8952d23af4e089849f34c37d 0445d96206c45df9c127fad05f7cc7be c127fad000000000f4e089849f34c37d 0445d96206c45df9c127fad05f7cc7be fpscr=00000000
+vrintxne.f64.f64 d7, d16 c31cbc98a9e0cdd84c6d3145c49a5d25 73866d7cacfd3aa9b5ed9fd5aa1e9794 80000000000000004c6d3145c49a5d25 73866d7cacfd3aa9b5ed9fd5aa1e9794 fpscr=00000000
+vrintxne.f64.f64 d7, d16 16cd5df4bc956cd5845a3b538d8f86bd 0e964d4d9595c587107358421905c51d 0000000000000000845a3b538d8f86bd 0e964d4d9595c587107358421905c51d fpscr=00000000
+vrintxne.f64.f64 d7, d16 28d4fd2d2c0601f0c38c1911402ca796 02f7c22f576e8f2a652cf2450cc2a710 652cf2450cc2a710c38c1911402ca796 02f7c22f576e8f2a652cf2450cc2a710 fpscr=00000000
+vrintxne.f64.f64 d7, d16 ca87f5e4362e559f3ea55fe1ba61a1ad 3dd94ef0a72be697243a0df943295698 00000000000000003ea55fe1ba61a1ad 3dd94ef0a72be697243a0df943295698 fpscr=00000000
+vrintxne.f64.f64 d7, d16 6d515e486a56cf0c0f33045d2d075627 08056454dc3bc12b06a20c10d3dc289a 00000000000000000f33045d2d075627 08056454dc3bc12b06a20c10d3dc289a fpscr=00000000
+vrintxne.f64.f64 d7, d16 323eeda6d842784a847780359341ebc6 796c6d7403856a16ca0d5c737f3b9478 ca0d5c737f3b9478847780359341ebc6 796c6d7403856a16ca0d5c737f3b9478 fpscr=00000000
+vrintxne.f64.f64 d7, d16 d8dfb05d1db2d2eb4a89c663f647e6c0 48932df957f87ec043831ec4683180aa 43831ec4683180aa4a89c663f647e6c0 48932df957f87ec043831ec4683180aa fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxne.f64.f64 d7, d16 7de128bea28728f37de128bea28728f3 5a1b186606e28c3e18f65a00d1f024b6 00000000000000007de128bea28728f3 5a1b186606e28c3e18f65a00d1f024b6 fpscr=00000000
+vrintxne.f64.f64 d7, d16 35be36127d106331ebe06141993b10f4 3683eceab5d2bb4abda7da3f3a94614f 8000000000000000ebe06141993b10f4 3683eceab5d2bb4abda7da3f3a94614f fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxne.f64.f64 d7, d16 4da2c617a7ad20624da2c617a7ad2062 ce180ae8dfbc29bc05a479dcbcfbb7b1 00000000000000004da2c617a7ad2062 ce180ae8dfbc29bc05a479dcbcfbb7b1 fpscr=00000000
+vrintxne.f64.f64 d7, d16 780efa43e5d4bdc2cb5672f2017e45a2 4d60b36fea0553d0f6c0f6753d013350 f6c0f6753d013350cb5672f2017e45a2 4d60b36fea0553d0f6c0f6753d013350 fpscr=00000000
+vrintxne.f64.f64 d7, d16 b13e6323da51a536010b0ccfea446548 fc5f4cdbe6b7b8b55cc1d973cc64dbec 5cc1d973cc64dbec010b0ccfea446548 fc5f4cdbe6b7b8b55cc1d973cc64dbec fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintxne.f64.f64 d7, d16 893901aa94fdf7c301e192c653873f64 1f4fc515b0b92d021f4fc515b0b92d02 000000000000000001e192c653873f64 1f4fc515b0b92d021f4fc515b0b92d02 fpscr=00000000
+vrintxne.f64.f64 d7, d16 81730899abc69f7940797a9090bf2722 425fffadcad311238aae0a664a7a78d0 800000000000000040797a9090bf2722 425fffadcad311238aae0a664a7a78d0 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxne.f64.f64 d7, d16 e036df19023efb7cd69df0907634a723 99c628398b953fee99c628398b953fee 8000000000000000d69df0907634a723 99c628398b953fee99c628398b953fee fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxne.f64.f64 d7, d16 6777120d0cd8c98b97e1b66077e106d1 d399bbcb4fe2482ed399bbcb4fe2482e d399bbcb4fe2482e97e1b66077e106d1 d399bbcb4fe2482ed399bbcb4fe2482e fpscr=00000000
+vrintxne.f64.f64 d7, d16 187487fe5123690c4da5d27097608e72 47f628ed49aef1c736395a7f240f9adb 00000000000000004da5d27097608e72 47f628ed49aef1c736395a7f240f9adb fpscr=00000000
+vrintxne.f64.f64 d7, d16 4e72cf1414e81d11838612c33924fbbc 7c30dd06df527dd2bbd9f74c08dcf616 8000000000000000838612c33924fbbc 7c30dd06df527dd2bbd9f74c08dcf616 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxne.f64.f64 d7, d16 d6f8672776585cdb337bc51aaac07015 55db5155ab05154466fcab4678818ce8 66fcab4678818ce8337bc51aaac07015 55db5155ab05154466fcab4678818ce8 fpscr=00000000
+vrintxne.f64.f64 d7, d16 b11065f24e9b3a1e6e97d8d317dbd2d5 5b5d6cc3aec098422e32a9cc522c2383 00000000000000006e97d8d317dbd2d5 5b5d6cc3aec098422e32a9cc522c2383 fpscr=00000000
+vrintxne.f64.f64 d7, d16 02e72354d08d90099f05a10f05b1c8e0 612d730a26cea390e8fa9b5d0edf355b e8fa9b5d0edf355b9f05a10f05b1c8e0 612d730a26cea390e8fa9b5d0edf355b fpscr=00000000
+vrintxne.f64.f64 d7, d16 43d4618ce941857cba03269dd5a87d6f 1fa62a10c3bf566bd361896096ef1006 d361896096ef1006ba03269dd5a87d6f 1fa62a10c3bf566bd361896096ef1006 fpscr=00000000
+vrintxne.f64.f64 d7, d16 01d69c62bd683fde401109eece50888e 5f347396a9bc0d233799e6064377ff93 0000000000000000401109eece50888e 5f347396a9bc0d233799e6064377ff93 fpscr=00000000
+vrintxne.f64.f64 d7, d16 6fe58ad090ce8097add0532968370d8c 21bd62a99f68fa3c52a17d059b1c043a 52a17d059b1c043aadd0532968370d8c 21bd62a99f68fa3c52a17d059b1c043a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxne.f64.f64 d7, d16 a79067eca91aa31dfbd8115274eb004d e66c5b79823f5eebe66c5b79823f5eeb e66c5b79823f5eebfbd8115274eb004d e66c5b79823f5eebe66c5b79823f5eeb fpscr=00000000
+vrintxne.f64.f64 d7, d16 48264ec838815680b6b69a6aeee58580 8b3f911a5301e2d210909361abe5bfbb 0000000000000000b6b69a6aeee58580 8b3f911a5301e2d210909361abe5bfbb fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxne.f64.f64 d7, d16 22b692ef212cc0cd4ec7e6d3462d5672 5e68a2b5819bc9f65e68a2b5819bc9f6 5e68a2b5819bc9f64ec7e6d3462d5672 5e68a2b5819bc9f65e68a2b5819bc9f6 fpscr=00000000
+vrintxne.f64.f64 d7, d16 f1dbaf7fec31e8c99edcf1990d5f2072 c2349b046fe01bd5849cd9c2bfd37fd0 80000000000000009edcf1990d5f2072 c2349b046fe01bd5849cd9c2bfd37fd0 fpscr=00000000
+vrintxne.f64.f64 d7, d16 87f0cb9fe4e306e7c17bbdbe6d100802 d07558761ab72e82059f5c556e25c6c0 0000000000000000c17bbdbe6d100802 d07558761ab72e82059f5c556e25c6c0 fpscr=00000000
+vrintxne.f64.f64 d7, d16 24d40a63132c23bcefc0ac0ed205b34b 99ddec2c78ea26a08f8db0c6b25175ee 8000000000000000efc0ac0ed205b34b 99ddec2c78ea26a08f8db0c6b25175ee fpscr=00000000
+vrintxne.f64.f64 d7, d16 d8c480f279647ed45794b87df5d28152 cea53c9cdfea6bd603cfb8fe81947eb2 00000000000000005794b87df5d28152 cea53c9cdfea6bd603cfb8fe81947eb2 fpscr=00000000
+vrintxne.f64.f64 d7, d16 adfa24cf13aceb4d04d5fd3033876943 f6bdc312d46049d82d65e403d0036d72 000000000000000004d5fd3033876943 f6bdc312d46049d82d65e403d0036d72 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintxne.f64.f64 d7, d16 68a5db59b884fdffe18a0f39a48867d6 d3030b431687ff106966e4c5e32eb693 6966e4c5e32eb693e18a0f39a48867d6 d3030b431687ff106966e4c5e32eb693 fpscr=00000000
+vrintxne.f64.f64 d7, d16 986f4262254166b2dcc118ff957a1dc6 b016fab92b6880b9fc6e3f31ab5bc0cd fc6e3f31ab5bc0cddcc118ff957a1dc6 b016fab92b6880b9fc6e3f31ab5bc0cd fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintxne.f64.f64 d7, d16 1a6728bed649310a1a6728bed649310a 4530b29683b38f1dc9e7e7461045d006 c9e7e7461045d0061a6728bed649310a 4530b29683b38f1dc9e7e7461045d006 fpscr=00000000
+vrintxne.f64.f64 d7, d16 5fbcd60391328198a0566d5337855215 ddfa2fd659288e5dd7afe760612f560a d7afe760612f560aa0566d5337855215 ddfa2fd659288e5dd7afe760612f560a fpscr=00000000
+vrintxne.f64.f64 d7, d16 833667aff8dd8fcea9f041f2a8f306c3 987462b14b2bcd12cd92df35bb1be23f cd92df35bb1be23fa9f041f2a8f306c3 987462b14b2bcd12cd92df35bb1be23f fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintxne.f64.f64 d7, d16 b5764c93c54cd5ba47f50e30b1be648a 90762c0bdb61e64f90762c0bdb61e64f 800000000000000047f50e30b1be648a 90762c0bdb61e64f90762c0bdb61e64f fpscr=00000000
+vrintxne.f64.f64 d7, d16 28b8e1e22460e460589391b22537e28c 093a87fee536969b4782c22a73fb8eab 4782c22a73fb8eab589391b22537e28c 093a87fee536969b4782c22a73fb8eab fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintxne.f64.f64 d7, d16 e22da3faf3b11cddd2e2ce82bba699f6 6de19dfb5b5949be6de19dfb5b5949be 6de19dfb5b5949bed2e2ce82bba699f6 6de19dfb5b5949be6de19dfb5b5949be fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vrintxne.f64.f64 d7, d16 70424d142aff413a70424d142aff413a 86f1439befff1f920d379e41130f36e3 000000000000000070424d142aff413a 86f1439befff1f920d379e41130f36e3 fpscr=00000000
+vrintxne.f64.f64 d7, d16 fa4672afc17bcacde325047f295230bb 40fba23a53272c49830fc1d06f871244 8000000000000000e325047f295230bb 40fba23a53272c49830fc1d06f871244 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintxne.f64.f64 d7, d16 53d485794e47af5f43505e44bed446f1 95b68f21913cd08f95b68f21913cd08f 800000000000000043505e44bed446f1 95b68f21913cd08f95b68f21913cd08f fpscr=00000000
+vrintx.f64.f64 d8, d8 441b58e61151b4c1976b8d1d2853604a f48b9d03ab878310eed12ed64f651a8b f48b9d03ab878310eed12ed64f651a8b f48b9d03ab878310eed12ed64f651a8b fpscr=00000000
+vrintx.f64.f64 d8, d8 4da1b86d9dc4d8f18f4f856b7e897280 8276e559e8be88c43ebfd5f04e498ccf 8276e559e8be88c40000000000000000 8276e559e8be88c40000000000000000 fpscr=00000000
+vrintx.f64.f64 d8, d8 55e181a24c69d0b96f595462c64246f2 571ac88bbe1d4d177d20f67b0ee83438 571ac88bbe1d4d177d20f67b0ee83438 571ac88bbe1d4d177d20f67b0ee83438 fpscr=00000000
+vrintx.f64.f64 d8, d8 e301c610d68dcc8440d3b3b09839ad96 c8e0ac00c00a4816c3f26e1815934806 c8e0ac00c00a4816c3f26e1815934806 c8e0ac00c00a4816c3f26e1815934806 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vrintx.f64.f64 d8, d8 aaf08fb60b3e41b1aaf08fb60b3e41b1 d27e23e5c84b773da94a78061913f0d5 d27e23e5c84b773d8000000000000000 d27e23e5c84b773d8000000000000000 fpscr=00000000
+vrintx.f64.f64 d8, d8 ee9861a6a55c62cc27151ca9ce6236ac b7efcf717a15f490c7ffc8415a63ea13 b7efcf717a15f490c7ffc8415a63ea13 b7efcf717a15f490c7ffc8415a63ea13 fpscr=00000000
+vrintx.f64.f64 d8, d8 33d23a52a227df4444ea6bac0951662b 33946081a7bf8e3347182600fb56828e 33946081a7bf8e3347182600fb56828e 33946081a7bf8e3347182600fb56828e fpscr=00000000
+vrintx.f64.f64 d8, d8 fd50c38a7187b1389bc7fa4518656aa5 a59c2e23fc3e5314615dd8cdd2669e07 a59c2e23fc3e5314615dd8cdd2669e07 a59c2e23fc3e5314615dd8cdd2669e07 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintx.f64.f64 d8, d8 0d13d85136feecec8da80cd097a87b9c 1586268ba970c7a7e3ed203d2a791d66 1586268ba970c7a7e3ed203d2a791d66 1586268ba970c7a7e3ed203d2a791d66 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintx.f64.f64 d8, d8 00a65be1733f5f6c6d66d238616c6753 9f0d3310e93a84500e7a54de988fd716 9f0d3310e93a84500000000000000000 9f0d3310e93a84500000000000000000 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintx.f64.f64 d8, d8 d3525940d186d7c7ce68ac1c173be477 0d88852b62cf51dd0d88852b62cf51dd 0d88852b62cf51dd0000000000000000 0d88852b62cf51dd0000000000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: 8448 calls, 8713 iters
+vrintx.f64.f64 d8, d8 ef16d5aa9470c9b72ce03804d361f79d ef3992c5d807de0e3fb8c3ffb9a9f94d ef3992c5d807de0e0000000000000000 ef3992c5d807de0e0000000000000000 fpscr=00000000
+vrintx.f64.f64 d8, d8 d3b5d147ff0d9c3d8b0e7a2021a76b98 e324bbd3f7ba2f91593f2c809e0dfd08 e324bbd3f7ba2f91593f2c809e0dfd08 e324bbd3f7ba2f91593f2c809e0dfd08 fpscr=00000000
+vrintx.f64.f64 d8, d8 e59d7ad6aa26b6063f66fe78b8aa7065 c58c2d11241b056e964ccdf9ecc9b2e1 c58c2d11241b056e8000000000000000 c58c2d11241b056e8000000000000000 fpscr=00000000
+vrintx.f64.f64 d8, d8 c3488a67f7006f46e4ecb7186c8777a7 bfcef9a18ffb2c5dab0d9bfdbfe4aace bfcef9a18ffb2c5d8000000000000000 bfcef9a18ffb2c5d8000000000000000 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintx.f64.f64 d8, d8 e1a672f58bcfdc30a2064627e1e7345b 757fc7d9400917041f1c45e45b5b5ee0 757fc7d9400917040000000000000000 757fc7d9400917040000000000000000 fpscr=00000000
+vrintx.f64.f64 d8, d8 9bd2d4fe3c3ca7220c0de40cfe47554d ab18fd38ac71b6fecc358d358ff85432 ab18fd38ac71b6fecc358d358ff85432 ab18fd38ac71b6fecc358d358ff85432 fpscr=00000000
+vrintx.f64.f64 d8, d8 4d0fb2c2ec6361482fb43b02a9298d37 b9ac53262ba999df4298306e6bb23972 b9ac53262ba999df4298306e6bb23800 b9ac53262ba999df4298306e6bb23800 fpscr=00000000
+vrintx.f64.f64 d8, d8 de834a152342d0fa70a66da6e779117f 5771447a92fd8b4eace540bf837ccf57 5771447a92fd8b4e8000000000000000 5771447a92fd8b4e8000000000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintx.f64.f64 d8, d8 fdf29a2899cc9ee75b4d6c7b07fcda76 68861137f59b23c083a8732c8eac51b6 68861137f59b23c08000000000000000 68861137f59b23c08000000000000000 fpscr=00000000
+vrintx.f64.f64 d8, d8 a032dd2da588fbfa1706c3734e99d391 968b3987e19ada1e59061fabb81aeb8b 968b3987e19ada1e59061fabb81aeb8b 968b3987e19ada1e59061fabb81aeb8b fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintx.f64.f64 d8, d8 682b87d58af85a336c0b5546aeba3cd8 6a7406f71cd469626a7406f71cd46962 6a7406f71cd469626a7406f71cd46962 6a7406f71cd469626a7406f71cd46962 fpscr=00000000
+vrintx.f64.f64 d8, d8 a0c6dacb0adf97f5fbe8176e8b1ed2e9 c9bba7eaba4b75b2d070ca287010db4d c9bba7eaba4b75b2d070ca287010db4d c9bba7eaba4b75b2d070ca287010db4d fpscr=00000000
+vrintx.f64.f64 d8, d8 4d47c1ec047d957777515c0bee473494 766eb5db356d5d597c59f29a132e78ee 766eb5db356d5d597c59f29a132e78ee 766eb5db356d5d597c59f29a132e78ee fpscr=00000000
+vrintx.f64.f64 d8, d8 13cff5bffb8d2f4a8320644c0aa2b06c bf46985265871d7f41d2f7b49fa4c669 bf46985265871d7f41d2f7b49fc00000 bf46985265871d7f41d2f7b49fc00000 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintx.f64.f64 d8, d8 8cd07d8680af9c908cd07d8680af9c90 2ce3c5ded81bf613f5c8f28ab8d5cc4b 2ce3c5ded81bf613f5c8f28ab8d5cc4b 2ce3c5ded81bf613f5c8f28ab8d5cc4b fpscr=00000000
+vrintx.f64.f64 d8, d8 3eb73659b08a72f13875d4f843a62b2b 69d0cbcf14aa57728ad6a960b316fdd6 69d0cbcf14aa57728000000000000000 69d0cbcf14aa57728000000000000000 fpscr=00000000
+vrintx.f64.f64 d8, d8 9d65cc0719e2f6e21113b50afa08708a a4815483727ff9627954237cabf0b88d a4815483727ff9627954237cabf0b88d a4815483727ff9627954237cabf0b88d fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintx.f64.f64 d8, d8 c903f9d2bc0ccb7bc903f9d2bc0ccb7b c55362dbad5b37ea2171e7ed6dd3c558 c55362dbad5b37ea0000000000000000 c55362dbad5b37ea0000000000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintx.f64.f64 d8, d8 a544bbbd4a39d6e96fb9bf6904f3d4d0 23cdeef7a486ab1e0eab6c3f6223232a 23cdeef7a486ab1e0000000000000000 23cdeef7a486ab1e0000000000000000 fpscr=00000000
+vrintx.f64.f64 d8, d8 a9296b566c38978158cd09135f556ea3 37a3b90ce2319f4b3907a536d2dd083e 37a3b90ce2319f4b0000000000000000 37a3b90ce2319f4b0000000000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintx.f64.f64 d8, d8 b85b9ae7b54ccddfad06943b4d41a1e1 da568ebcdce1815322afb6939c9bbf18 da568ebcdce181530000000000000000 da568ebcdce181530000000000000000 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintx.f64.f64 d8, d8 1c5ea42ce81bfc9f7582931d2db6c5db eaefef6166e8e1f2eaefef6166e8e1f2 eaefef6166e8e1f2eaefef6166e8e1f2 eaefef6166e8e1f2eaefef6166e8e1f2 fpscr=00000000
+vrintx.f64.f64 d8, d8 5e224c2e0c06d877ddcb4f9b42fe765f a564798c153279adb243f7068a7e188d a564798c153279ad8000000000000000 a564798c153279ad8000000000000000 fpscr=00000000
+vrintx.f64.f64 d8, d8 360637a8d6d29bf083eaaa55581616f1 2cbe6946132fc6a7494a061b59c9c1dd 2cbe6946132fc6a7494a061b59c9c1dd 2cbe6946132fc6a7494a061b59c9c1dd fpscr=00000000
+vrintx.f64.f64 d8, d8 7023f314c1c601b66b82945baac56053 8f7f1dc807e8158b4d5858dc53b151c4 8f7f1dc807e8158b4d5858dc53b151c4 8f7f1dc807e8158b4d5858dc53b151c4 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintx.f64.f64 d8, d8 47bb8ac6187e2647feb9cb5744fe50e4 643e4b88b1be8f0b643e4b88b1be8f0b 643e4b88b1be8f0b643e4b88b1be8f0b 643e4b88b1be8f0b643e4b88b1be8f0b fpscr=00000000
+vrintx.f64.f64 d8, d8 9e6c1ca240c91467eba34c4ba1305744 be53480286ccc2167027d954b14c2f79 be53480286ccc2167027d954b14c2f79 be53480286ccc2167027d954b14c2f79 fpscr=00000000
+vrintx.f64.f64 d8, d8 c44d85a7cb75fae1045ff912f1dd83ed de54f99186183d166201342ce310188e de54f99186183d166201342ce310188e de54f99186183d166201342ce310188e fpscr=00000000
+vrintx.f64.f64 d8, d8 540925f2123798401b9eb271fc711cdb b1ad508646d077d947feb864c00c2a76 b1ad508646d077d947feb864c00c2a76 b1ad508646d077d947feb864c00c2a76 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintx.f64.f64 d8, d8 96de54eb60390f9296de54eb60390f92 303f98e6d9384961dae495491a7bc6f0 303f98e6d9384961dae495491a7bc6f0 303f98e6d9384961dae495491a7bc6f0 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintx.f64.f64 d8, d8 947ef2242dc2eb8a9d1e50a36fa1b375 c4c02e467a4395a5b67b56d2d5d0cb77 c4c02e467a4395a58000000000000000 c4c02e467a4395a58000000000000000 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintx.f64.f64 d8, d8 5f22a9c7bc7c8550649b93c4690eb1ad eee839ec02267fa6e0fb718154e52321 eee839ec02267fa6e0fb718154e52321 eee839ec02267fa6e0fb718154e52321 fpscr=00000000
+vrintx.f64.f64 d8, d8 58b608008b4f68a2d06b77faad1aa768 34fdec19937f4d570895da96c55a8359 34fdec19937f4d570000000000000000 34fdec19937f4d570000000000000000 fpscr=00000000
+vrintx.f64.f64 d8, d8 3ff7bfea289b6d2d18fb4e33a495092d 6fa23573265b5d8647f4b97b2003b134 6fa23573265b5d8647f4b97b2003b134 6fa23573265b5d8647f4b97b2003b134 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintx.f64.f64 d8, d8 97676176b21c8e2b52e37589289b70b6 98996bb894b9e1039d2aa8ede28412b3 98996bb894b9e1038000000000000000 98996bb894b9e1038000000000000000 fpscr=00000000
+vrintx.f64.f64 d8, d8 caafaf46903760afb0dc7ca015d2259a 284ae2f3b849f196aac21be59c561633 284ae2f3b849f1968000000000000000 284ae2f3b849f1968000000000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintx.f64.f64 d8, d8 dcb4639e9c502b51770ae1e5aeefe6d6 9cdc0c0180f8d5942086ea94dee9e1b9 9cdc0c0180f8d5940000000000000000 9cdc0c0180f8d5940000000000000000 fpscr=00000000
+vrintx.f64.f64 d8, d8 9d136d9f94d8a89bf4e7ff6cc1e49969 44f317ecb1f9c87aa050364ebba8c896 44f317ecb1f9c87a8000000000000000 44f317ecb1f9c87a8000000000000000 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintx.f64.f64 d8, d8 8f90da4a132baf33d5cc1cab453654e3 57568aee3bcbea4c062a2f56553929ae 57568aee3bcbea4c0000000000000000 57568aee3bcbea4c0000000000000000 fpscr=00000000
+vrintzeq.f32.f32 s0, s9 bbb66909e2ea5a3304096e47b7e1897a 1ba52a7cf514a2aef5a25175319fe6fe bbb66909e2ea5a3304096e47b7e1897a 1ba52a7cf514a2aef5a25175319fe6fe fpscr=00000000
+vrintzeq.f32.f32 s0, s9 40a5dfbc0cb0537f133e68f917afbfc8 f8493741ac3709f71ef6bd2aedce7948 40a5dfbc0cb0537f133e68f917afbfc8 f8493741ac3709f71ef6bd2aedce7948 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintzeq.f32.f32 s0, s9 29250fffd27127b7f1a2f5865bd3620a 5d5adf28535a766ecc147823af263209 29250fffd27127b7f1a2f5865bd3620a 5d5adf28535a766ecc147823af263209 fpscr=00000000
+vrintzeq.f32.f32 s0, s9 e00984602a2495b3ac2036abb6494beb 4efe40b9402a717c463423763a5ada1d e00984602a2495b3ac2036abb6494beb 4efe40b9402a717c463423763a5ada1d fpscr=00000000
+vrintzeq.f32.f32 s0, s9 e43732830e8bf0a76f24f086fd3e4bb2 c14cbf548e63f38b1d22404788eec77b e43732830e8bf0a76f24f086fd3e4bb2 c14cbf548e63f38b1d22404788eec77b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[2]
+vrintzeq.f32.f32 s0, s9 349f4ad2ee4133e0ee4133e0b6e61bfb 5d05d104a604b0404d631611a604b040 349f4ad2ee4133e0ee4133e0b6e61bfb 5d05d104a604b0404d631611a604b040 fpscr=00000000
+vrintzeq.f32.f32 s0, s9 e7db81ea638d531ee80cc366565a004c b6f9983ba9b3a2dbfd030028254cc47a e7db81ea638d531ee80cc366565a004c b6f9983ba9b3a2dbfd030028254cc47a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintzeq.f32.f32 s0, s9 0d3f3dbc1dd80bf894648293225c2512 b7f89b477397f084d3b07d8ab7f89b47 0d3f3dbc1dd80bf894648293225c2512 b7f89b477397f084d3b07d8ab7f89b47 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintzeq.f32.f32 s0, s9 710467b3cdbec4fee108e3cc21fd348f 71ae57b0cc4f8ce9c389bceeac2f947b 710467b3cdbec4fee108e3cc21fd348f 71ae57b0cc4f8ce9c389bceeac2f947b fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintzeq.f32.f32 s0, s9 aa1662e89a69e732c2f9bba665b5e136 8fe70a5b2f3457a864ca12758fe70a5b aa1662e89a69e732c2f9bba665b5e136 8fe70a5b2f3457a864ca12758fe70a5b fpscr=00000000
+vrintzeq.f32.f32 s0, s9 2bc635c6f43a232d1d1e656f0d5cccab 4d01e6b0f3a37ef8ddb354cda483eba9 2bc635c6f43a232d1d1e656f0d5cccab 4d01e6b0f3a37ef8ddb354cda483eba9 fpscr=00000000
+vrintzeq.f32.f32 s0, s9 c60c71939e0df818f06f5d38194a9bf1 5159e333be70d1a5100e04f36b67b56a c60c71939e0df818f06f5d38194a9bf1 5159e333be70d1a5100e04f36b67b56a fpscr=00000000
+vrintzeq.f32.f32 s0, s9 fa57406eb220ab3ae4d9c86c4b9a9de5 40d56a4fe03f1f00274a397f67eff74c fa57406eb220ab3ae4d9c86c4b9a9de5 40d56a4fe03f1f00274a397f67eff74c fpscr=00000000
+vrintzeq.f32.f32 s0, s9 a53a637acd1aae3fa807b7005d0904a1 5733846c487710cbe347a5f868effd9d a53a637acd1aae3fa807b7005d0904a1 5733846c487710cbe347a5f868effd9d fpscr=00000000
+vrintzeq.f32.f32 s0, s9 c0ff5f4390ac99bc3fde152e08a0f6c5 ce66690b031a4cc02350af163dcf577a c0ff5f4390ac99bc3fde152e08a0f6c5 ce66690b031a4cc02350af163dcf577a fpscr=00000000
+vrintzeq.f32.f32 s0, s9 3913e7f21c1d2688112d4dfab082d41c 77ee70b4f8c48a1ac1af9bebb3c02792 3913e7f21c1d2688112d4dfab082d41c 77ee70b4f8c48a1ac1af9bebb3c02792 fpscr=00000000
+vrintzeq.f32.f32 s0, s9 28589f72e5ba9efb64395186879cdf13 388bd93a85f97d7552a59f657152524c 28589f72e5ba9efb64395186879cdf13 388bd93a85f97d7552a59f657152524c fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintzeq.f32.f32 s0, s9 614f436de7219c0e312cff5bf631411f a98910dea66ac575a29e3247bed23ad6 614f436de7219c0e312cff5bf631411f a98910dea66ac575a29e3247bed23ad6 fpscr=00000000
+vrintzeq.f32.f32 s0, s9 31bb43416e734f69784993137b685bce a62ff141a47e38ed9d69448d46f05ec3 31bb43416e734f69784993137b685bce a62ff141a47e38ed9d69448d46f05ec3 fpscr=00000000
+vrintzeq.f32.f32 s0, s9 fe87dc3ee8e69066cfe5014c3dab8660 aaf0d3f463a003e24c33076943742f59 fe87dc3ee8e69066cfe5014c3dab8660 aaf0d3f463a003e24c33076943742f59 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[0]
+vrintzeq.f32.f32 s0, s9 5569e3145569e314a9e4afab63bd2010 0486ad668881d1cdc072963261adccb4 5569e3145569e314a9e4afab63bd2010 0486ad668881d1cdc072963261adccb4 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintzeq.f32.f32 s0, s9 46e90204609b8fbd609b8fbd391b36dd b7563d8ee64a59b5371c69390708cbe1 46e90204609b8fbd609b8fbd391b36dd b7563d8ee64a59b5371c69390708cbe1 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintzeq.f32.f32 s0, s9 667a8c6540de3b7c40de3b7cf9511749 92e340a4447a47c8ec8b27fc81ae7f8d 667a8c6540de3b7c40de3b7cf9511749 92e340a4447a47c8ec8b27fc81ae7f8d fpscr=00000000
+vrintzeq.f32.f32 s0, s9 2abb3cf5467bfabc2fdd4fb271facc1b 9201b9c21123d29dbed988a3e9e1cb4f 2abb3cf5467bfabc2fdd4fb271facc1b 9201b9c21123d29dbed988a3e9e1cb4f fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintzeq.f32.f32 s0, s9 f0b1a5428acd8686412f2572f0b1a542 39c09f4405f744b0ea48f1787bfb99e8 f0b1a5428acd8686412f2572f0b1a542 39c09f4405f744b0ea48f1787bfb99e8 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: 8704 calls, 8981 iters
+vrintzeq.f32.f32 s0, s9 080b9213b916c69c114d18bb5e9b2d93 bf3323aedc60e7b6bf3323aee710f8cb 080b9213b916c69c114d18bb5e9b2d93 bf3323aedc60e7b6bf3323aee710f8cb fpscr=00000000
+vrintzeq.f32.f32 s0, s9 3d5ff3885ae5494782819db414306573 8677650d8b922a53a4887507d36ec2d0 3d5ff3885ae5494782819db414306573 8677650d8b922a53a4887507d36ec2d0 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintzeq.f32.f32 s0, s9 a6a3bf8435027a3f4f41a855f875e513 2e52fba832c176d4fa2750a0cfa65e4f a6a3bf8435027a3f4f41a855f875e513 2e52fba832c176d4fa2750a0cfa65e4f fpscr=00000000
+vrintzeq.f32.f32 s0, s9 70d8af9faf18a50b917003f841a41384 db3d4546af7ae96c4ad583791533229e 70d8af9faf18a50b917003f841a41384 db3d4546af7ae96c4ad583791533229e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintzeq.f32.f32 s0, s9 9d35ade95ce492761db2a17343b5ceb6 38a78d049365d3da9b77b07ce3a42787 9d35ade95ce492761db2a17343b5ceb6 38a78d049365d3da9b77b07ce3a42787 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[3]
+vrintzeq.f32.f32 s0, s9 683cff6f24c520d1c25a860f2bf1925c 8b0aeabcb5a51aae8b0aeabcafc2e862 683cff6f24c520d1c25a860f2bf1925c 8b0aeabcb5a51aae8b0aeabcafc2e862 fpscr=00000000
+vrintzeq.f32.f32 s0, s9 85456b088e581d3fd28142c149488adf e36bdcaea1d2aad875524d73cc9ccd64 85456b088e581d3fd28142c149488adf e36bdcaea1d2aad875524d73cc9ccd64 fpscr=00000000
+vrintzeq.f32.f32 s0, s9 c84e23f18e9986ce3cad4d8127e86a52 e58b56bd650f42af8495e644748f26c6 c84e23f18e9986ce3cad4d8127e86a52 e58b56bd650f42af8495e644748f26c6 fpscr=00000000
+vrintzeq.f32.f32 s0, s9 2bf71f3e3c1743a52868bb1d268fb28c 6387c63cec8f8d5b465d9b22a82da6bc 2bf71f3e3c1743a52868bb1d268fb28c 6387c63cec8f8d5b465d9b22a82da6bc fpscr=00000000
+vrintzeq.f32.f32 s0, s9 f7cca157839edf4d560a235fb4926bd3 7bc5458cc1beedac2fd3e59364b4c767 f7cca157839edf4d560a235fb4926bd3 7bc5458cc1beedac2fd3e59364b4c767 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintzeq.f32.f32 s0, s9 74a6df2d553652fbf9fc65bf790624ff 4b3c35da30277c38192a443b8eb63ec2 74a6df2d553652fbf9fc65bf790624ff 4b3c35da30277c38192a443b8eb63ec2 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintzeq.f32.f32 s0, s9 2caa48e898784adbfe17e950a6c53041 87d31a25f0ac89e3674777c07e14cfe7 2caa48e898784adbfe17e950a6c53041 87d31a25f0ac89e3674777c07e14cfe7 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintzeq.f32.f32 s0, s9 f044ec20fc3623fe341fda728af3b1fc 8fcdd2bb9c326436f51f71c58ff89a93 f044ec20fc3623fe341fda728af3b1fc 8fcdd2bb9c326436f51f71c58ff89a93 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintzeq.f32.f32 s0, s9 352efec2819aca61104dd4bb6f225e11 16426ee6215da3493950fb42130717af 352efec2819aca61104dd4bb6f225e11 16426ee6215da3493950fb42130717af fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[3]
+vrintzeq.f32.f32 s0, s9 4f74a56036ad5c454f74a560afb7e037 9c86a9ab6e1475b386d6be38381bdb27 4f74a56036ad5c454f74a560afb7e037 9c86a9ab6e1475b386d6be38381bdb27 fpscr=00000000
+vrintzeq.f32.f32 s0, s9 1a60113d5315c8b5a6b8b86771b01329 a1e1a5ce996b291ba9ca7232485ad17d 1a60113d5315c8b5a6b8b86771b01329 a1e1a5ce996b291ba9ca7232485ad17d fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintzeq.f32.f32 s0, s9 0202aa1e4eb75f310202aa1e1eaaa94e 122362547744f5b1da44b90cbdcd277e 0202aa1e4eb75f310202aa1e1eaaa94e 122362547744f5b1da44b90cbdcd277e fpscr=00000000
+vrintzeq.f32.f32 s0, s9 c2b240fe399a61caa37c609421b551ea baf02abb4ec0b0fb0e92f76e38232cb7 c2b240fe399a61caa37c609421b551ea baf02abb4ec0b0fb0e92f76e38232cb7 fpscr=00000000
+vrintzeq.f32.f32 s0, s9 e4f7609d4bcfe26a6f5a3728cfdcb5d9 09828f4b1a709c62ed7aae7964e4b468 e4f7609d4bcfe26a6f5a3728cfdcb5d9 09828f4b1a709c62ed7aae7964e4b468 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintzeq.f32.f32 s0, s9 3246953f54bcf142280be54cca32bab6 20d2e56f20d2e56fe4a7056f42c76050 3246953f54bcf142280be54cca32bab6 20d2e56f20d2e56fe4a7056f42c76050 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintzeq.f32.f32 s0, s9 5bdc97b07ea8f8e6c40eee1f5852ffa2 0486073822781e43b9abf4ad65866312 5bdc97b07ea8f8e6c40eee1f5852ffa2 0486073822781e43b9abf4ad65866312 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintzeq.f32.f32 s0, s9 21d459b994b3a2236fe2a17ff0fd6c21 39995e07e4593275134cf35639995e07 21d459b994b3a2236fe2a17ff0fd6c21 39995e07e4593275134cf35639995e07 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[0]
+vrintzeq.f32.f32 s0, s9 07a2142e468dcb7d07a2142ee0cc0cd5 743b2e313014c9ea47d77d782219fb5f 07a2142e468dcb7d07a2142ee0cc0cd5 743b2e313014c9ea47d77d782219fb5f fpscr=00000000
+vrintzeq.f32.f32 s0, s9 a7373f48f0eb571da87a6a6281aa0ad0 5f8752d52ab9daf82b1e8a7f0aebbb82 a7373f48f0eb571da87a6a6281aa0ad0 5f8752d52ab9daf82b1e8a7f0aebbb82 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[3]
+vrintzeq.f32.f32 s0, s9 3d4e3c40479241ae479241ae4574971d 45960d315e9f4faf2124191d45960d31 3d4e3c40479241ae479241ae4574971d 45960d315e9f4faf2124191d45960d31 fpscr=00000000
+vrintzne.f32.f32 s1, s10 472c8ee6d1b2519d09f15e3624a1eb3d 94903517526e6d330a56c3834db94d06 472c8ee6d1b2519d526e6d3324a1eb3d 94903517526e6d330a56c3834db94d06 fpscr=00000000
+vrintzne.f32.f32 s1, s10 b4874fa305bb220162152b734d807c90 513e2ebe598680743827ef33aaaaab5c b4874fa305bb2201598680744d807c90 513e2ebe598680743827ef33aaaaab5c fpscr=00000000
+vrintzne.f32.f32 s1, s10 0f77095e812ddf9a38a14e0de819d0f4 621de13e15039feb0ca8bb61e70e2a75 0f77095e812ddf9a00000000e819d0f4 621de13e15039feb0ca8bb61e70e2a75 fpscr=00000000
+vrintzne.f32.f32 s1, s10 84293ffe7620a048aeb1f6b60dd745c0 f0e72970f1452d25b66707475687e610 84293ffe7620a048f1452d250dd745c0 f0e72970f1452d25b66707475687e610 fpscr=00000000
+vrintzne.f32.f32 s1, s10 fa4eb4682ceafad2a4ab9ae07c299201 0c843cbcbc4f561f8ff1cd0d6c88b523 fa4eb4682ceafad2800000007c299201 0c843cbcbc4f561f8ff1cd0d6c88b523 fpscr=00000000
+vrintzne.f32.f32 s1, s10 1644bc18d23a00b095b1a7014d9e30e4 089054678e64d3072379201cf5d11d45 1644bc18d23a00b0800000004d9e30e4 089054678e64d3072379201cf5d11d45 fpscr=00000000
+vrintzne.f32.f32 s1, s10 8c91b826f1e827dd543617c496474bf8 4e4eb993e485d86df8775a9d5ec27e90 8c91b826f1e827dde485d86d96474bf8 4e4eb993e485d86df8775a9d5ec27e90 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vrintzne.f32.f32 s1, s10 e40c3a6c52f0c2a47981455f9f9c8f18 0f10b6e6c2824ab7e49039850f10b6e6 e40c3a6c52f0c2a4c28200009f9c8f18 0f10b6e6c2824ab7e49039850f10b6e6 fpscr=00000000
+vrintzne.f32.f32 s1, s10 0b6890d68f331049c4fabf2af95a0499 38f918b6b0f6cd8584e4063b19e38e19 0b6890d68f33104980000000f95a0499 38f918b6b0f6cd8584e4063b19e38e19 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintzne.f32.f32 s1, s10 b915f2b16ecf64106bc55773151b3239 088c4ae0088c4ae09889e9292ae63c2f b915f2b16ecf641000000000151b3239 088c4ae0088c4ae09889e9292ae63c2f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintzne.f32.f32 s1, s10 6b1ef3c195269db4ef49c179ed46f924 c3c0dea4c4e0e8d05aebf0a7ab056c4d 6b1ef3c195269db4c4e0e000ed46f924 c3c0dea4c4e0e8d05aebf0a7ab056c4d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintzne.f32.f32 s1, s10 66ca08c95265252d7299e29eff4645bb 75a57e6575a57e65932246d03b7bf665 66ca08c95265252d75a57e65ff4645bb 75a57e6575a57e65932246d03b7bf665 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[1]
+vrintzne.f32.f32 s1, s10 00afbed100afbed13f8ac3842ab0fe24 b878608979589ff1dc6278080a71ddb0 00afbed100afbed179589ff12ab0fe24 b878608979589ff1dc6278080a71ddb0 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintzne.f32.f32 s1, s10 d5dda871c8cab9e0cf24f9c9d468bb48 ed43a379a326823215ff09b842476ea9 d5dda871c8cab9e080000000d468bb48 ed43a379a326823215ff09b842476ea9 fpscr=00000000
+vrintzne.f32.f32 s1, s10 cfa6806e892110ded53dca28d2c17e0c a98ef2018cb45a18ed6592cd83a89c86 cfa6806e892110de80000000d2c17e0c a98ef2018cb45a18ed6592cd83a89c86 fpscr=00000000
+vrintzne.f32.f32 s1, s10 04473a6439131786b7e763fcfc3de337 22a2adf60e009f4fc966ff290cc42825 04473a643913178600000000fc3de337 22a2adf60e009f4fc966ff290cc42825 fpscr=00000000
+vrintzne.f32.f32 s1, s10 f033888b1ee01b953548dc5727afc5fe 72db71f87977d934fafbed02d8d2ff03 f033888b1ee01b957977d93427afc5fe 72db71f87977d934fafbed02d8d2ff03 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[2]
+vrintzne.f32.f32 s1, s10 a2a5ae42c812d438d8c70715a2a5ae42 d103bea8a121bd5ad103bea8ab36cd5f a2a5ae42c812d43880000000a2a5ae42 d103bea8a121bd5ad103bea8ab36cd5f fpscr=00000000
+vrintzne.f32.f32 s1, s10 5d338d804783dce70cea1ae95c8d8dca 37cb7067bad25749bcf3be0e037473bf 5d338d804783dce7800000005c8d8dca 37cb7067bad25749bcf3be0e037473bf fpscr=00000000
+vrintzne.f32.f32 s1, s10 12187d2dc6873bf001c205a9e1593fab 459f3fa4b4c8a650c8cd076767ed4458 12187d2dc6873bf080000000e1593fab 459f3fa4b4c8a650c8cd076767ed4458 fpscr=00000000
+vrintzne.f32.f32 s1, s10 e9c3bf0864ee3b1273a7aa7d72c79372 78890b6c260959945d0181330cf7d5a0 e9c3bf0864ee3b120000000072c79372 78890b6c260959945d0181330cf7d5a0 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintzne.f32.f32 s1, s10 3021d6fac69a24894957d8ea45f4bb87 994c650dc0389f74e87d5e1d91585fef 3021d6fac69a2489c000000045f4bb87 994c650dc0389f74e87d5e1d91585fef fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintzne.f32.f32 s1, s10 1eb1aba266b2574be7a363296733a0b3 eab369a0c391ebdc5e2800a1c391ebdc 1eb1aba266b2574bc39180006733a0b3 eab369a0c391ebdc5e2800a1c391ebdc fpscr=00000000
+vrintzne.f32.f32 s1, s10 70edb797a3d8a59006a6761cdbaa76d6 85cc2e48c5731c76f214451405c2bca9 70edb797a3d8a590c5731000dbaa76d6 85cc2e48c5731c76f214451405c2bca9 fpscr=00000000
+vrintzne.f32.f32 s1, s10 9ab854304c739ae51d3d8e36dbaa0732 9bdce719ddfd081341e73c38273f0266 9ab854304c739ae5ddfd0813dbaa0732 9bdce719ddfd081341e73c38273f0266 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintzne.f32.f32 s1, s10 6c828769061092932e4fb14bf0532d3e e4b5e5f2a7281eff7aac91ca6babe5e7 6c8287690610929380000000f0532d3e e4b5e5f2a7281eff7aac91ca6babe5e7 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+vrintzne.f32.f32 s1, s10 4ca5a176655e7d2458f0e7254282f8e2 1edf424edf3bb2e9df3bb2e9e88ebcbb 4ca5a176655e7d24df3bb2e94282f8e2 1edf424edf3bb2e9df3bb2e9e88ebcbb fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintzne.f32.f32 s1, s10 7b4fa74fa603082e7b4fa74f90205048 9419b925f28e676805b2d60cc6f4f2f5 7b4fa74fa603082ef28e676890205048 9419b925f28e676805b2d60cc6f4f2f5 fpscr=00000000
+vrintzne.f32.f32 s1, s10 828574a1e1ba3aed1bbb29b0740236c8 304abf01e0143642e60796097af0b47c 828574a1e1ba3aede0143642740236c8 304abf01e0143642e60796097af0b47c fpscr=00000000
+vrintzne.f32.f32 s1, s10 a6191164d9f89a83660ae1a65b83f622 a42be55e546f91b45582a41f2c85522b a6191164d9f89a83546f91b45b83f622 a42be55e546f91b45582a41f2c85522b fpscr=00000000
+vrintzne.f32.f32 s1, s10 e8fbaf5db364a93fd9ab45d6c556717a 0c6d839df218c18a37347c245444659b e8fbaf5db364a93ff218c18ac556717a 0c6d839df218c18a37347c245444659b fpscr=00000000
+vrintzne.f32.f32 s1, s10 38d8983410ef758bf6f625a162ff57fa 99893e65fdc15277f6b43b52397adf31 38d8983410ef758bfdc1527762ff57fa 99893e65fdc15277f6b43b52397adf31 fpscr=00000000
+vrintzne.f32.f32 s1, s10 211abd6d3f5ef4b5dd915cb5512e65ea c30bccba2cc07f4cfab2a5aa0fdfb396 211abd6d3f5ef4b500000000512e65ea c30bccba2cc07f4cfab2a5aa0fdfb396 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintzne.f32.f32 s1, s10 798a361d098ea747395690092e3e463d e3bd1cffdb5ef51e7f618b2b6220dd17 798a361d098ea747db5ef51e2e3e463d e3bd1cffdb5ef51e7f618b2b6220dd17 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintzne.f32.f32 s1, s10 e296ea599e01622012bd129ace2b0520 c2fc25bcdcd2ab05f83ccbca8ef8f54e e296ea599e016220dcd2ab05ce2b0520 c2fc25bcdcd2ab05f83ccbca8ef8f54e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintzne.f32.f32 s1, s10 2ff828eb658151f4f2791f9a7ad409fe b7378c07e55e5ccc6e4eec14c0f34a4e 2ff828eb658151f4e55e5ccc7ad409fe b7378c07e55e5ccc6e4eec14c0f34a4e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintzne.f32.f32 s1, s10 6883697313b06d928dc3872c58de169e 20be760f9cbb5b06d91d84ee38ecdaf4 6883697313b06d928000000058de169e 20be760f9cbb5b06d91d84ee38ecdaf4 fpscr=00000000
+vrintzne.f32.f32 s1, s10 e1b73bc99002ae5445d26d6663bc09dd 6089e589f53d1f84b9d0200c8d868f81 e1b73bc99002ae54f53d1f8463bc09dd 6089e589f53d1f84b9d0200c8d868f81 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintzne.f32.f32 s1, s10 970c132f16389b9c00c7c69168c83a73 b8ea2c3590fbde9f90fbde9f8150928a 970c132f16389b9c8000000068c83a73 b8ea2c3590fbde9f90fbde9f8150928a fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: 8960 calls, 9246 iters
+vrintzne.f32.f32 s1, s10 0c2f6f52132019b3b3fa6f1beab22689 d75dad5b54f1bca3043bf007915e26ac 0c2f6f52132019b354f1bca3eab22689 d75dad5b54f1bca3043bf007915e26ac fpscr=00000000
+vrintzne.f32.f32 s1, s10 8e5ea4e7c65790210cc18841ebe1413f ed2f2b6d646b68d6a0e4457408a53b68 8e5ea4e7c6579021646b68d6ebe1413f ed2f2b6d646b68d6a0e4457408a53b68 fpscr=00000000
+vrintzne.f32.f32 s1, s10 cf3499c670a652444d68bdba093ec871 adf969bd9c1308a806c8643151439d7b cf3499c670a6524480000000093ec871 adf969bd9c1308a806c8643151439d7b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintzne.f32.f32 s1, s10 59bbe5f5034cb1fb034cb1fb216d7357 9949e6cfb7b26889b071b4aa18e33c6b 59bbe5f5034cb1fb80000000216d7357 9949e6cfb7b26889b071b4aa18e33c6b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintzne.f32.f32 s1, s10 fd6532230b6a060094561fe58fe2c524 76e9c94a61f240ed5c0422fb502496d3 fd6532230b6a060061f240ed8fe2c524 76e9c94a61f240ed5c0422fb502496d3 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[0]
+vrintzne.f32.f32 s1, s10 2ea9b4a16f4ed8e2fea54b9329cb667f dd195df9da053ea77ad28d56da053ea7 2ea9b4a16f4ed8e2da053ea729cb667f dd195df9da053ea77ad28d56da053ea7 fpscr=00000000
+vrintzne.f32.f32 s1, s10 bc75377d5333d5a11d15011902365f35 95d22b73f109e17899ef25ef7a991fb4 bc75377d5333d5a1f109e17802365f35 95d22b73f109e17899ef25ef7a991fb4 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[1]
+vrintzne.f32.f32 s1, s10 0f670e2e0a1d5992cb8d5f02a30e5502 92a5e81b0c20ddc016e2d77992a5e81b 0f670e2e0a1d599200000000a30e5502 92a5e81b0c20ddc016e2d77992a5e81b fpscr=00000000
+vrintzne.f32.f32 s1, s10 4cfa812da33be7073c0ff2156fcf182b 980c79d0bd5bf0df8421780d453e31a1 4cfa812da33be707800000006fcf182b 980c79d0bd5bf0df8421780d453e31a1 fpscr=00000000
+vrintzne.f32.f32 s1, s10 0c89f7d529ab70592bc9c836fe7942c6 195e03d7cb08bd442d7a1bea5e6ce1e3 0c89f7d529ab7059cb08bd44fe7942c6 195e03d7cb08bd442d7a1bea5e6ce1e3 fpscr=00000000
+vrintzne.f32.f32 s1, s10 64847b7d6a44a22f5749259ba72fc2d5 9dc415bc8e13b692f48e05f60c46b505 64847b7d6a44a22f80000000a72fc2d5 9dc415bc8e13b692f48e05f60c46b505 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintz.f32.f32 s2, s11 9e1f114beac0b63d38c38206b7358253 8994edc2b950064a3eefc47a707eb3c7 9e1f114b8000000038c38206b7358253 8994edc2b950064a3eefc47a707eb3c7 fpscr=00000000
+vrintz.f32.f32 s2, s11 6fa1b726979461b8ee1edff5743f5665 810f738ff9ff0705d16eb58309d488d4 6fa1b72680000000ee1edff5743f5665 810f738ff9ff0705d16eb58309d488d4 fpscr=00000000
+vrintz.f32.f32 s2, s11 39cca17351e61bbf46fe70e17c592184 2b8001a2cc67c4c0cab16c7adcc3f23b 39cca1730000000046fe70e17c592184 2b8001a2cc67c4c0cab16c7adcc3f23b fpscr=00000000
+vrintz.f32.f32 s2, s11 a2cf5ac2586a35d400a088ddb456acf8 3c17388074b9ad1c2b846233399916d4 a2cf5ac20000000000a088ddb456acf8 3c17388074b9ad1c2b846233399916d4 fpscr=00000000
+vrintz.f32.f32 s2, s11 9967f1e9e8acbe3912c371105b2edfe0 76581b212f533d5806056cf5fc45acc8 9967f1e976581b2112c371105b2edfe0 76581b212f533d5806056cf5fc45acc8 fpscr=00000000
+vrintz.f32.f32 s2, s11 8c025f6e8fbfb2ab78ea484147373687 f7c3b32386d74bde02d0798f41449d0e 8c025f6ef7c3b32378ea484147373687 f7c3b32386d74bde02d0798f41449d0e fpscr=00000000
+vrintz.f32.f32 s2, s11 56a0477a37c5d7f45c7df61431e8d83b 10387705bbc218976ba539d6136e4e03 56a0477a000000005c7df61431e8d83b 10387705bbc218976ba539d6136e4e03 fpscr=00000000
+vrintz.f32.f32 s2, s11 0c1c96351bd680e628541198e0019f84 7d4c0f45a8d4b030abff210485a246eb 0c1c96357d4c0f4528541198e0019f84 7d4c0f45a8d4b030abff210485a246eb fpscr=00000000
+vrintz.f32.f32 s2, s11 aed1fb758c4226ac729e99453d10eeb9 f7777d61ec5fb238217bd4f426582f4c aed1fb75f7777d61729e99453d10eeb9 f7777d61ec5fb238217bd4f426582f4c fpscr=00000000
+vrintz.f32.f32 s2, s11 afa14ed9a83be885cc20944d3c5871f8 2f1c9fb188787518532be640db0d4230 afa14ed900000000cc20944d3c5871f8 2f1c9fb188787518532be640db0d4230 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintz.f32.f32 s2, s11 6a5bc33fe2d8e9d471e29054ae17c078 1f7d1928d2028df687c0034211900a3f 6a5bc33f0000000071e29054ae17c078 1f7d1928d2028df687c0034211900a3f fpscr=00000000
+vrintz.f32.f32 s2, s11 c0866d7e1394727d8f9cd233fe84ea29 35d7c48899f0cb9bb574b99c78ed532f c0866d7e000000008f9cd233fe84ea29 35d7c48899f0cb9bb574b99c78ed532f fpscr=00000000
+vrintz.f32.f32 s2, s11 764da5637213a3a29d53050b72055f12 616d31807de9d56f104af1bb149144cb 764da563616d31809d53050b72055f12 616d31807de9d56f104af1bb149144cb fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintz.f32.f32 s2, s11 5dd26fc370d302f5381713d7bdd30262 c85d0993db07cae17073f0bf7073f0bf 5dd26fc3c85d0980381713d7bdd30262 c85d0993db07cae17073f0bf7073f0bf fpscr=00000000
+vrintz.f32.f32 s2, s11 b11849298598b9c368e3bd48259df1f3 0f3e87504f41e390721c492b69829850 b11849290000000068e3bd48259df1f3 0f3e87504f41e390721c492b69829850 fpscr=00000000
+vrintz.f32.f32 s2, s11 412b66e6cb69aefbee7e857896803b09 650a657ba2afa93b577e38eb36d20bb9 412b66e6650a657bee7e857896803b09 650a657ba2afa93b577e38eb36d20bb9 fpscr=00000000
+vrintz.f32.f32 s2, s11 47d85580cfd2492bfceaabcc6fb6284e e8daf14f7e8313cc366df0003827b742 47d85580e8daf14ffceaabcc6fb6284e e8daf14f7e8313cc366df0003827b742 fpscr=00000000
+vrintz.f32.f32 s2, s11 1deb612ac87e6dcf76f213de7dcdeee2 c6c7d913bb678b2968a8d4e73eb7583a 1deb612ac6c7d80076f213de7dcdeee2 c6c7d913bb678b2968a8d4e73eb7583a fpscr=00000000
+vrintz.f32.f32 s2, s11 7cfb586cc9afb809c5a0e227cc8343a0 06b3ff1cc049c16f6e936cde4da7951e 7cfb586c00000000c5a0e227cc8343a0 06b3ff1cc049c16f6e936cde4da7951e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintz.f32.f32 s2, s11 3e7a4b634dc3d69482f92269e7e3d6a9 ea51916c41a40c0bfa9332265fae9134 3e7a4b63ea51916c82f92269e7e3d6a9 ea51916c41a40c0bfa9332265fae9134 fpscr=00000000
+vrintz.f32.f32 s2, s11 c17379baff5e48ec5f2732028cccd104 101f035150c486bad5448a61282a1dab c17379ba000000005f2732028cccd104 101f035150c486bad5448a61282a1dab fpscr=00000000
+vrintz.f32.f32 s2, s11 5b8970ff1e0ad4461fe1a34b39020b19 73c220cb71987143143518ad1f5b42c9 5b8970ff73c220cb1fe1a34b39020b19 73c220cb71987143143518ad1f5b42c9 fpscr=00000000
+vrintz.f32.f32 s2, s11 92c8be0e7c9cc31c1e839f9674e131f7 69d0b763c1fac564832c1a5d34d2fd0a 92c8be0e69d0b7631e839f9674e131f7 69d0b763c1fac564832c1a5d34d2fd0a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintz.f32.f32 s2, s11 6eb98433c77c1e986eb98433a13eb909 c3eb6e906b2c3dd04eb1d6fb4aa4a7ba 6eb98433c3eb00006eb98433a13eb909 c3eb6e906b2c3dd04eb1d6fb4aa4a7ba fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintz.f32.f32 s2, s11 6a3c249a8805124581dcdbbf6a3c249a 83e3f23b745e1a35f5610add650a4f27 6a3c249a8000000081dcdbbf6a3c249a 83e3f23b745e1a35f5610add650a4f27 fpscr=00000000
+vrintz.f32.f32 s2, s11 2affb48e3ad6d97695a248315a767668 3312da54b0e5d7ab6906c4b3db58b9ef 2affb48e0000000095a248315a767668 3312da54b0e5d7ab6906c4b3db58b9ef fpscr=00000000
+vrintz.f32.f32 s2, s11 aedca69f6cac59f9348174dc063a0883 60559a865820f649da633b7c372cb744 aedca69f60559a86348174dc063a0883 60559a865820f649da633b7c372cb744 fpscr=00000000
+vrintz.f32.f32 s2, s11 af54c83c44d2e29fafb6f469d27359a3 d85d8ca35eae245e626786ad633d7e8e af54c83cd85d8ca3afb6f469d27359a3 d85d8ca35eae245e626786ad633d7e8e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintz.f32.f32 s2, s11 5301c1db71fa1e79fafc820ad57d6640 835144998351449986df7992b0c8ec60 5301c1db80000000fafc820ad57d6640 835144998351449986df7992b0c8ec60 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[2]
+vrintz.f32.f32 s2, s11 c8fa04a2228742108523f571500928e7 06079193c7090907d3879afd0e0e65e8 c8fa04a2000000008523f571500928e7 06079193c7090907d3879afd0e0e65e8 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintz.f32.f32 s2, s11 a44d935ec701f7206ecb9a1b984c83fd 9ac449a64501f4367729a83f9ac449a6 a44d935e800000006ecb9a1b984c83fd 9ac449a64501f4367729a83f9ac449a6 fpscr=00000000
+vrintz.f32.f32 s2, s11 d638b970901895e9ebd1dad9a8080eff 616f362291247576bd81131b227eb64a d638b970616f3622ebd1dad9a8080eff 616f362291247576bd81131b227eb64a fpscr=00000000
+vrintz.f32.f32 s2, s11 fdb0334348b3a4015c63db92b51bfe90 e2654cff78e4cb1a06ee2e9f6c9bd891 fdb03343e2654cff5c63db92b51bfe90 e2654cff78e4cb1a06ee2e9f6c9bd891 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[1]
+vrintz.f32.f32 s2, s11 b3b3ae9063131c63eac94939045af525 2dd00af52dd00af50da27324dc2c8c76 b3b3ae9000000000eac94939045af525 2dd00af52dd00af50da27324dc2c8c76 fpscr=00000000
+vrintz.f32.f32 s2, s11 033d58ff0a0ea1f13d6e580f2885d2cd 0f6026fd616d07c0528eacccc38c65f1 033d58ff000000003d6e580f2885d2cd 0f6026fd616d07c0528eacccc38c65f1 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintz.f32.f32 s2, s11 1c0fab6c00f73a307b7cf12682b6a7c4 d9598a9525ed83ab84b0d5bbc2be48bd 1c0fab6cd9598a957b7cf12682b6a7c4 d9598a9525ed83ab84b0d5bbc2be48bd fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintz.f32.f32 s2, s11 40ea1a20521ce3e784fd9db2137e559d a654bb5bd8ea84dc794c10b1d92afd73 40ea1a208000000084fd9db2137e559d a654bb5bd8ea84dc794c10b1d92afd73 fpscr=00000000
+vrintz.f32.f32 s2, s11 0c08d9ab18d0b0aa0116eca03ecfdb8a 746686edf6145735d404908c410cefda 0c08d9ab746686ed0116eca03ecfdb8a 746686edf6145735d404908c410cefda fpscr=00000000
+vrintz.f32.f32 s2, s11 c852808ddf7537f8e31a6bb91c303c6a 9ee80bb80237c3ff9ce0c8037150f356 c852808d80000000e31a6bb91c303c6a 9ee80bb80237c3ff9ce0c8037150f356 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintz.f32.f32 s2, s11 a01b886540c741a4757479cbfdd9c13f f1adfba4ab2690b32cabfdc0086a45d6 a01b8865f1adfba4757479cbfdd9c13f f1adfba4ab2690b32cabfdc0086a45d6 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[3]
+vrintz.f32.f32 s2, s11 a10917c343a6971d66a2a321a10917c3 8ef0afe3bcf801fa8ef0afe38cfeb102 a10917c38000000066a2a321a10917c3 8ef0afe3bcf801fa8ef0afe38cfeb102 fpscr=00000000
+vrintz.f32.f32 s2, s11 cf324e97e9d416aa5f258cc7180d9e95 9d83ffbf9f44c64ef1d34739dda623ba cf324e97800000005f258cc7180d9e95 9d83ffbf9f44c64ef1d34739dda623ba fpscr=00000000
+vrintz.f32.f32 s2, s11 73c8879edb35e295a575447ed866b067 b49339eff5e0946b2764c6c2279bebeb 73c8879e80000000a575447ed866b067 b49339eff5e0946b2764c6c2279bebeb fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintz.f32.f32 s2, s11 9a886cd6c297e00411741a8e96458f6e 9695dfc6d491fe21bd015e93e2d26cac 9a886cd68000000011741a8e96458f6e 9695dfc6d491fe21bd015e93e2d26cac fpscr=00000000
+vrintz.f32.f32 s2, s11 98aeed9a6dee30fe1eb4f2712203d4d1 f20a3b019919ec167280b7fd5d198ae1 98aeed9af20a3b011eb4f2712203d4d1 f20a3b019919ec167280b7fd5d198ae1 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintz.f32.f32 s2, s11 87c0282ecc7c1f11e7d8dd1bcc7c1f11 b5cf216142d8df4cdf8cec148245df80 87c0282e80000000e7d8dd1bcc7c1f11 b5cf216142d8df4cdf8cec148245df80 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintz.f32.f32 s2, s11 58d408f5089ab15036b1e40867311fe2 6ec30a3773c42c24604ce053ce59dd47 58d408f56ec30a3736b1e40867311fe2 6ec30a3773c42c24604ce053ce59dd47 fpscr=00000000
+vrintz.f32.f32 s2, s11 ff6a47cb90e22fb0f9e48653759bed0f cee4f6ae8db3f25edf9d093780fa911f ff6a47cbcee4f6aef9e48653759bed0f cee4f6ae8db3f25edf9d093780fa911f fpscr=00000000
+vrintz.f32.f32 s2, s11 c334329b2f133816d16baad432342a9d 37f84b83e9f0e8e29efcd4559344d807 c334329b00000000d16baad432342a9d 37f84b83e9f0e8e29efcd4559344d807 fpscr=00000000
+vrintz.f32.f32 s2, s11 0c3f16855fa96515c5280a1ee85ba99f 218c42518f73ec71cf5a1f3085937488 0c3f168500000000c5280a1ee85ba99f 218c42518f73ec71cf5a1f3085937488 fpscr=00000000
+vrintreq.f32.f32 s3, s12 5a33d61ad59f42f5ae5198239f099f44 2017a5485b70c72869191817e101fa78 5a33d61ad59f42f5ae5198239f099f44 2017a5485b70c72869191817e101fa78 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintreq.f32.f32 s3, s12 c4da9a53307021ac7f576c2f8f8bab25 5e22bc9326fc98252c2c7c3524cb2d55 c4da9a53307021ac7f576c2f8f8bab25 5e22bc9326fc98252c2c7c3524cb2d55 fpscr=00000000
+vrintreq.f32.f32 s3, s12 5720678d0a07851e75faf48b479ee9c7 1212f12f3615c11c60603947c295f5a2 5720678d0a07851e75faf48b479ee9c7 1212f12f3615c11c60603947c295f5a2 fpscr=00000000
+randV128: 9216 calls, 9508 iters
+vrintreq.f32.f32 s3, s12 7915b1f770bece9818db2227ebf788e5 b8278e8c6b0b46b3e26b07eca1ffbad9 7915b1f770bece9818db2227ebf788e5 b8278e8c6b0b46b3e26b07eca1ffbad9 fpscr=00000000
+vrintreq.f32.f32 s3, s12 4f08923ab2ec387d5e5de0ad5d5a7c54 4606a3030387d24dec11b55bf1b19070 4f08923ab2ec387d5e5de0ad5d5a7c54 4606a3030387d24dec11b55bf1b19070 fpscr=00000000
+vrintreq.f32.f32 s3, s12 c8bc8977328452471edb18b3025e7c2c e138cc5ffdd099cffdd3c65ff6069c05 c8bc8977328452471edb18b3025e7c2c e138cc5ffdd099cffdd3c65ff6069c05 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintreq.f32.f32 s3, s12 c85e93b48eec17cd878df80a9d4132fa d2f8a7e6149d5c06494434fa05ebc9a1 c85e93b48eec17cd878df80a9d4132fa d2f8a7e6149d5c06494434fa05ebc9a1 fpscr=00000000
+vrintreq.f32.f32 s3, s12 f98942d5657cae3bf4223958e32ae47f 4c22d08595dda82c0c9c85363f12214a f98942d5657cae3bf4223958e32ae47f 4c22d08595dda82c0c9c85363f12214a fpscr=00000000
+vrintreq.f32.f32 s3, s12 58681fcd191da9dbeec1fe7d390537ec 4e43f1bc68c8c14aa379377201b8b93b 58681fcd191da9dbeec1fe7d390537ec 4e43f1bc68c8c14aa379377201b8b93b fpscr=00000000
+vrintreq.f32.f32 s3, s12 9ccde6e39a4afb6f46665ba67634b9ee 965d37e97cae300ed8733e918f8c4ddb 9ccde6e39a4afb6f46665ba67634b9ee 965d37e97cae300ed8733e918f8c4ddb fpscr=00000000
+vrintreq.f32.f32 s3, s12 db3a7aa7c3ef021e336cc2fffb03a73a 792161ace75fa572c75e8de1df131b08 db3a7aa7c3ef021e336cc2fffb03a73a 792161ace75fa572c75e8de1df131b08 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintreq.f32.f32 s3, s12 6ddcd878b873e5840e0246f0d45d0671 a0520243d95ad1963e7173fce48876c8 6ddcd878b873e5840e0246f0d45d0671 a0520243d95ad1963e7173fce48876c8 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vrintreq.f32.f32 s3, s12 35b714ea1b00d33a2c10aa3b4fddd976 4b701fed423fcbc1423fcbc148d6c99b 35b714ea1b00d33a2c10aa3b4fddd976 4b701fed423fcbc1423fcbc148d6c99b fpscr=00000000
+vrintreq.f32.f32 s3, s12 f82eb5a6cd683cfb7f2061c83794a415 8784c74fad4c550b9425d0f9e5237ae4 f82eb5a6cd683cfb7f2061c83794a415 8784c74fad4c550b9425d0f9e5237ae4 fpscr=00000000
+vrintreq.f32.f32 s3, s12 b83fcd9961e8949b8fb6f778ee232f3f 34be464f2408c103b4c0ad428ff6d88a b83fcd9961e8949b8fb6f778ee232f3f 34be464f2408c103b4c0ad428ff6d88a fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintreq.f32.f32 s3, s12 7bac317f9f90a50bdf5b532874c87065 54c021567678f66344a819944cc4a1e8 7bac317f9f90a50bdf5b532874c87065 54c021567678f66344a819944cc4a1e8 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintreq.f32.f32 s3, s12 ddb6af8aa1472aeb34ca1fa2ef11139a ef7d8bf65e6c49a71c238d2128d313ed ddb6af8aa1472aeb34ca1fa2ef11139a ef7d8bf65e6c49a71c238d2128d313ed fpscr=00000000
+vrintreq.f32.f32 s3, s12 f81385e5412dfabd6ce1a16d4c81d106 4cb3aa91c8cb834b80aa7f092cb90780 f81385e5412dfabd6ce1a16d4c81d106 4cb3aa91c8cb834b80aa7f092cb90780 fpscr=00000000
+vrintreq.f32.f32 s3, s12 d7424f73dd185b1a86ecccc0db05c88a 23e37875c43e845a0cbef2c549498544 d7424f73dd185b1a86ecccc0db05c88a 23e37875c43e845a0cbef2c549498544 fpscr=00000000
+vrintreq.f32.f32 s3, s12 b1d1ff3de12b6f02af9633119a4f341f 5ff88e26c53bcc039defef9e6a3a9ccd b1d1ff3de12b6f02af9633119a4f341f 5ff88e26c53bcc039defef9e6a3a9ccd fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintreq.f32.f32 s3, s12 1de241d8c3c2182bb724bf7a50edef2a 3188c7ff1d78d7e2ce16c8bb3188c7ff 1de241d8c3c2182bb724bf7a50edef2a 3188c7ff1d78d7e2ce16c8bb3188c7ff fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintreq.f32.f32 s3, s12 7cef43fa17f64823025e5eb97188388d a9ada46cf9ab123826cfa7b93e559d56 7cef43fa17f64823025e5eb97188388d a9ada46cf9ab123826cfa7b93e559d56 fpscr=00000000
+vrintreq.f32.f32 s3, s12 9c235f93d9362529a6590ce39ac0f039 f41506a54347acec25e494d285c878c3 9c235f93d9362529a6590ce39ac0f039 f41506a54347acec25e494d285c878c3 fpscr=00000000
+vrintreq.f32.f32 s3, s12 171ebca102e4df0f81689743aecafc6b b78ba8e421dd2e4eb88b0feb5e39586b 171ebca102e4df0f81689743aecafc6b b78ba8e421dd2e4eb88b0feb5e39586b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintreq.f32.f32 s3, s12 4ca557a207779ad0c9e3b7712cc1b29e b1dca6333a560cb61240acc76b8a318c 4ca557a207779ad0c9e3b7712cc1b29e b1dca6333a560cb61240acc76b8a318c fpscr=00000000
+vrintreq.f32.f32 s3, s12 1cdfeebc2573ad7afddc760c76e33d4c 54540777163e03924158e6cac8581d45 1cdfeebc2573ad7afddc760c76e33d4c 54540777163e03924158e6cac8581d45 fpscr=00000000
+vrintreq.f32.f32 s3, s12 723871c25227a40c3c342f1c2b5da889 1c775c5d1764435cbd07a347808987ec 723871c25227a40c3c342f1c2b5da889 1c775c5d1764435cbd07a347808987ec fpscr=00000000
+vrintreq.f32.f32 s3, s12 50ea798385bf1a41c2e4c9baafd4f2f7 e84738b1c83a5d6095e60d2819e4ba35 50ea798385bf1a41c2e4c9baafd4f2f7 e84738b1c83a5d6095e60d2819e4ba35 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintreq.f32.f32 s3, s12 b5a93c908d6e50706f121f044c773d26 f78dc1b86b8514c6f78dc1b830b9c4ba b5a93c908d6e50706f121f044c773d26 f78dc1b86b8514c6f78dc1b830b9c4ba fpscr=00000000
+vrintreq.f32.f32 s3, s12 4448bec9f4755acf3c21207452e71090 7db0ea7635f9105eace39750897e0850 4448bec9f4755acf3c21207452e71090 7db0ea7635f9105eace39750897e0850 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintreq.f32.f32 s3, s12 b95b6334e63cd57bb435b28c15e2e85b c1c05fe630929c9402e65cb60e0dcb89 b95b6334e63cd57bb435b28c15e2e85b c1c05fe630929c9402e65cb60e0dcb89 fpscr=00000000
+vrintreq.f32.f32 s3, s12 ddf3b2375b00e86710bf5751a5027d6c 89c47dace912164b8084aee235e8fe61 ddf3b2375b00e86710bf5751a5027d6c 89c47dace912164b8084aee235e8fe61 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintreq.f32.f32 s3, s12 b147fd9d2f6b3c002be154ccc5403749 74ed0004e75c84f14440b2b6fe286dbe b147fd9d2f6b3c002be154ccc5403749 74ed0004e75c84f14440b2b6fe286dbe fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintreq.f32.f32 s3, s12 8a7c115d364e226c45ac6bc766170711 25e09d54b0e0033bfbf2f215894d4632 8a7c115d364e226c45ac6bc766170711 25e09d54b0e0033bfbf2f215894d4632 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintreq.f32.f32 s3, s12 d1eba14f20de285320de28531bcd1af0 11f0536652886f31402abb50a41c05c9 d1eba14f20de285320de28531bcd1af0 11f0536652886f31402abb50a41c05c9 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintreq.f32.f32 s3, s12 2ad977cb3f8e6e0bcbbee271ecfa3550 3e5db93f3e5db93f10f34e3f9b947189 2ad977cb3f8e6e0bcbbee271ecfa3550 3e5db93f3e5db93f10f34e3f9b947189 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[2]
+vrintreq.f32.f32 s3, s12 8d4c69958d4c6995ece025605cdece48 664ac83b664ac83bf3c9d36d17fb9706 8d4c69958d4c6995ece025605cdece48 664ac83b664ac83bf3c9d36d17fb9706 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[3]
+vrintreq.f32.f32 s3, s12 7cf84b3485e3d8126cae58c1c05bb7c1 57113deca5c9bd99ed262544a5c9bd99 7cf84b3485e3d8126cae58c1c05bb7c1 57113deca5c9bd99ed262544a5c9bd99 fpscr=00000000
+vrintreq.f32.f32 s3, s12 7204c2681229b69ff93c8f2dd375efa1 1159376f58f8f0421c7a4409b6148f49 7204c2681229b69ff93c8f2dd375efa1 1159376f58f8f0421c7a4409b6148f49 fpscr=00000000
+vrintreq.f32.f32 s3, s12 6f735bf5029b5ee1d507bd994e7b96d2 a3ff282d2c8dd8a06649f3a637380ee9 6f735bf5029b5ee1d507bd994e7b96d2 a3ff282d2c8dd8a06649f3a637380ee9 fpscr=00000000
+vrintreq.f32.f32 s3, s12 c836f55bcf15290b9889a75168bc4ed7 0bd32b3a5bcfc6c5fe87b97404ed297b c836f55bcf15290b9889a75168bc4ed7 0bd32b3a5bcfc6c5fe87b97404ed297b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintreq.f32.f32 s3, s12 00bdac85222a36f4222a36f4b383f11e 937dc68ac64198508160d4092f553bfe 00bdac85222a36f4222a36f4b383f11e 937dc68ac64198508160d4092f553bfe fpscr=00000000
+vrintreq.f32.f32 s3, s12 bd43d286aa00620f195a8b9008e34811 222bd04ef46e538b9f4ffde547fa6e8f bd43d286aa00620f195a8b9008e34811 222bd04ef46e538b9f4ffde547fa6e8f fpscr=00000000
+vrintreq.f32.f32 s3, s12 eb8a3fdfdd77e333cc1ef280a1cf7e82 c563548659ec2e29d2922d32ee329973 eb8a3fdfdd77e333cc1ef280a1cf7e82 c563548659ec2e29d2922d32ee329973 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintreq.f32.f32 s3, s12 c9ccd9a51287fae6953610e5953610e5 a21dc48d5ca5807a59efd2fdaf188cc7 c9ccd9a51287fae6953610e5953610e5 a21dc48d5ca5807a59efd2fdaf188cc7 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintreq.f32.f32 s3, s12 fd82ee4bf670f3f7f9fc4ec5a038c5e1 6c249aa4e9d784ef438ea2dfb6bbee3d fd82ee4bf670f3f7f9fc4ec5a038c5e1 6c249aa4e9d784ef438ea2dfb6bbee3d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintreq.f32.f32 s3, s12 088d72cdc90c8e9bd2629179d2629179 6232591d107c8fcc61776c8e1b94b650 088d72cdc90c8e9bd2629179d2629179 6232591d107c8fcc61776c8e1b94b650 fpscr=00000000
+vrintreq.f32.f32 s3, s12 37b0713bca62527f94c395f1f16647a5 6758b9f6259b8f90e8e70e5e77bf0ef3 37b0713bca62527f94c395f1f16647a5 6758b9f6259b8f90e8e70e5e77bf0ef3 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintreq.f32.f32 s3, s12 e79bf7371589a9fc3836922a79312d91 e5e8b23c45bf16352fa21ea1408be8e8 e79bf7371589a9fc3836922a79312d91 e5e8b23c45bf16352fa21ea1408be8e8 fpscr=00000000
+vrintreq.f32.f32 s3, s12 488867eaf2b9c7ff7c1de2472f5e5f45 7d1e878c116b0d4765f2424e59207f6b 488867eaf2b9c7ff7c1de2472f5e5f45 7d1e878c116b0d4765f2424e59207f6b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintrne.f32.f32 s4, s13 2ef7bcfe92104bd2e233fb357a0d0ef2 ae946f3bafe4e50e1242e2e18599c93f 2ef7bcfe92104bd2e233fb3500000000 ae946f3bafe4e50e1242e2e18599c93f fpscr=00000000
+vrintrne.f32.f32 s4, s13 abdb215b19aec98b104970a6adb5d18e c57ea78d9ef2beb08557f457cb67c8b0 abdb215b19aec98b104970a680000000 c57ea78d9ef2beb08557f457cb67c8b0 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[2]
+vrintrne.f32.f32 s4, s13 0546ead80546ead83e1d4e1dc94d442c bb68fe8fada9b563fb3601a0fe5091b1 0546ead80546ead83e1d4e1dfb3601a0 bb68fe8fada9b563fb3601a0fe5091b1 fpscr=00000000
+vrintrne.f32.f32 s4, s13 66c3cec2ab7d7be0ee321a7b36117d98 0d48392167a74acaa2c4559ef025bddb 66c3cec2ab7d7be0ee321a7b80000000 0d48392167a74acaa2c4559ef025bddb fpscr=00000000
+vrintrne.f32.f32 s4, s13 4ec4d1b6e3a67cf8a8f5243e7d22939c 0941b0a0b9d601ecb38bfe31e8c5706d 4ec4d1b6e3a67cf8a8f5243e80000000 0941b0a0b9d601ecb38bfe31e8c5706d fpscr=00000000
+vrintrne.f32.f32 s4, s13 be91e0a0c02ced58daa4b26933a297e1 aa172089952096e80e573cf7d2f4be9a be91e0a0c02ced58daa4b26900000000 aa172089952096e80e573cf7d2f4be9a fpscr=00000000
+vrintrne.f32.f32 s4, s13 c1ebe4ec8d19d7435a540feb2c1b5076 d46568e8e96658b46120166f6dab4a22 c1ebe4ec8d19d7435a540feb6120166f d46568e8e96658b46120166f6dab4a22 fpscr=00000000
+vrintrne.f32.f32 s4, s13 b2894d0ad4e4f06a136732edfe9d17d0 ff0b368abe435ca85de5affacc208d13 b2894d0ad4e4f06a136732ed5de5affa ff0b368abe435ca85de5affacc208d13 fpscr=00000000
+vrintrne.f32.f32 s4, s13 025db5c74b5b58e40b0a9f6530dbd0ff 6c7ec81c1275e4c0333f53426773843d 025db5c74b5b58e40b0a9f6500000000 6c7ec81c1275e4c0333f53426773843d fpscr=00000000
+vrintrne.f32.f32 s4, s13 ef375b00a5e535825720231047bccf3e bbf014270d2c25b667c9dc6d9437b095 ef375b00a5e535825720231067c9dc6d bbf014270d2c25b667c9dc6d9437b095 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintrne.f32.f32 s4, s13 0cd083ba3b29358ae88673c7b7378df0 e26450f4943a6d045de87f735de87f73 0cd083ba3b29358ae88673c75de87f73 e26450f4943a6d045de87f735de87f73 fpscr=00000000
+vrintrne.f32.f32 s4, s13 34b43211ad54b22bb0979e15eac435b9 ab07d095477e819bd5434321a5bd3aab 34b43211ad54b22bb0979e15d5434321 ab07d095477e819bd5434321a5bd3aab fpscr=00000000
+vrintrne.f32.f32 s4, s13 180d2361987b4a60c9ac064305facdde 6293b9ce3d4b9cde68ebc1fd3e514772 180d2361987b4a60c9ac064368ebc1fd 6293b9ce3d4b9cde68ebc1fd3e514772 fpscr=00000000
+vrintrne.f32.f32 s4, s13 0f4f38c4e46e81bc10b99bbf7bc6c624 0fdcb534c67facb1dd5b77597225da43 0f4f38c4e46e81bc10b99bbfdd5b7759 0fdcb534c67facb1dd5b77597225da43 fpscr=00000000
+vrintrne.f32.f32 s4, s13 0e2d4bd75dba534e03bca72e7bcf058e 6ea96a68b481185f1ef5a4d4eb17c1e4 0e2d4bd75dba534e03bca72e00000000 6ea96a68b481185f1ef5a4d4eb17c1e4 fpscr=00000000
+vrintrne.f32.f32 s4, s13 5edb60bf8419f6c71be9a35453587317 e55015adba260b66934ed6b7cbd50215 5edb60bf8419f6c71be9a35480000000 e55015adba260b66934ed6b7cbd50215 fpscr=00000000
+vrintrne.f32.f32 s4, s13 ff2655d41224adc268fe24f9283b0737 0993241993b2a9c9e648be600d23501c ff2655d41224adc268fe24f9e648be60 0993241993b2a9c9e648be600d23501c fpscr=00000000
+randV128: 9472 calls, 9772 iters
+vrintrne.f32.f32 s4, s13 dfe56ea1526e746d11fdab2e9a3db5ce 835d2aa08bb4a53b2717658e52f1e235 dfe56ea1526e746d11fdab2e00000000 835d2aa08bb4a53b2717658e52f1e235 fpscr=00000000
+vrintrne.f32.f32 s4, s13 556135015fc6392c5817c4930260a7dc 2d50f33f0807776bbf5948939e8148e0 556135015fc6392c5817c493bf800000 2d50f33f0807776bbf5948939e8148e0 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[3]
+vrintrne.f32.f32 s4, s13 8399839a892a77bdd39be003d39be003 700bd9b003fb8ca13e2233f10ba855c5 8399839a892a77bdd39be00300000000 700bd9b003fb8ca13e2233f10ba855c5 fpscr=00000000
+vrintrne.f32.f32 s4, s13 a697516816a29d0de3460687f650636c 55f8bb08d8af4c56ef3f9a7424031fc7 a697516816a29d0de3460687ef3f9a74 55f8bb08d8af4c56ef3f9a7424031fc7 fpscr=00000000
+vrintrne.f32.f32 s4, s13 d6768dac85fbc6d7ab06324b012fc795 9e85c4d3f498080e1a9c7990cbe325c5 d6768dac85fbc6d7ab06324b00000000 9e85c4d3f498080e1a9c7990cbe325c5 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintrne.f32.f32 s4, s13 76b546d32143290a361bc5d79105d916 b42587c8040826df0724c550a4c70cb6 76b546d32143290a361bc5d700000000 b42587c8040826df0724c550a4c70cb6 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintrne.f32.f32 s4, s13 e3781390af012db4d9177509fd3bfbe1 2abc26a06fcf6327e8c853ebd5b1c575 e3781390af012db4d9177509e8c853eb 2abc26a06fcf6327e8c853ebd5b1c575 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintrne.f32.f32 s4, s13 77c408f4a0595f694c29d2f5c340b7eb c895843109b267243c0fd37f4f7f2fcd 77c408f4a0595f694c29d2f500000000 c895843109b267243c0fd37f4f7f2fcd fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintrne.f32.f32 s4, s13 0d66438471d90fbdb5c78c54c6f5877a 7b35161723ebcd72e0dd676723ebcd72 0d66438471d90fbdb5c78c54e0dd6767 7b35161723ebcd72e0dd676723ebcd72 fpscr=00000000
+vrintrne.f32.f32 s4, s13 8d859a9a23da455855021ce1855fb5f1 97665306fb2bf01938082f14c47d3037 8d859a9a23da455855021ce100000000 97665306fb2bf01938082f14c47d3037 fpscr=00000000
+vrintrne.f32.f32 s4, s13 161a1d2899820e4ab8910bccdd73794a b22c9714591c07e6603b2086c0d3b38e 161a1d2899820e4ab8910bcc603b2086 b22c9714591c07e6603b2086c0d3b38e fpscr=00000000
+vrintrne.f32.f32 s4, s13 760265f0c9da51b9e0bfa3928c51a312 f2ab39190268bba731c693de35c1713f 760265f0c9da51b9e0bfa39200000000 f2ab39190268bba731c693de35c1713f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintrne.f32.f32 s4, s13 9c4422aed17d78cc76cfb569449b39d2 08679eb708679eb7ced62ce27f4356cf 9c4422aed17d78cc76cfb569ced62ce2 08679eb708679eb7ced62ce27f4356cf fpscr=00000000
+vrintrne.f32.f32 s4, s13 a3a475b098b1aef810d5c483a9adfd5a 35bd2c98e2756709cf8a6073266a7756 a3a475b098b1aef810d5c483cf8a6073 35bd2c98e2756709cf8a6073266a7756 fpscr=00000000
+vrintrne.f32.f32 s4, s13 115cc978cbff3a021b17d6ede9462f75 c462c8c9d4caab55b0815819a4495bae 115cc978cbff3a021b17d6ed80000000 c462c8c9d4caab55b0815819a4495bae fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[2]
+vrintrne.f32.f32 s4, s13 4a58fa208ede0c113af073ab376ef384 6a013dd98a4ef8c46e1e12576e1e1257 4a58fa208ede0c113af073ab6e1e1257 6a013dd98a4ef8c46e1e12576e1e1257 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[2]
+vrintrne.f32.f32 s4, s13 aa0200d6337b2bf5a3da6fb73552bf5c 07e6372007e6372075b6a7da6c842ce8 aa0200d6337b2bf5a3da6fb775b6a7da 07e6372007e6372075b6a7da6c842ce8 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[1]
+vrintrne.f32.f32 s4, s13 f4e43c4646e88e752db5b60a0e345950 f0e405e3ad16548a1761811aad16548a f4e43c4646e88e752db5b60a00000000 f0e405e3ad16548a1761811aad16548a fpscr=00000000
+vrintrne.f32.f32 s4, s13 11da416c7f0d11939f38aed5fd1c6c35 ad8af7ea172a4d04db100a8a8ee941db 11da416c7f0d11939f38aed5db100a8a ad8af7ea172a4d04db100a8a8ee941db fpscr=00000000
+vrintrne.f32.f32 s4, s13 06c43b96746668be2e9259bd0152856b 3756558e0b4406846da4cc00fb6b2d4c 06c43b96746668be2e9259bd6da4cc00 3756558e0b4406846da4cc00fb6b2d4c fpscr=00000000
+vrintrne.f32.f32 s4, s13 d4ce0b3c04a0995469846e0301444364 a5a5ef4ccc672ecf4a0a00b54e3c50d5 d4ce0b3c04a0995469846e034a0a00b4 a5a5ef4ccc672ecf4a0a00b54e3c50d5 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintrne.f32.f32 s4, s13 d194359c2d4da5f1c234d63bd194359c 054605bd035cbc847d3159309825caba d194359c2d4da5f1c234d63b7d315930 054605bd035cbc847d3159309825caba fpscr=00000000
+vrintrne.f32.f32 s4, s13 72ec3532613242e58e5c540bfc6722e1 0fbab5bf95918f61e8af41aaa2893d93 72ec3532613242e58e5c540be8af41aa 0fbab5bf95918f61e8af41aaa2893d93 fpscr=00000000
+vrintrne.f32.f32 s4, s13 35d86e9b940f5b2b9af570b632122a67 bf870f78b4f4a77b88cb5cb9c9b493f7 35d86e9b940f5b2b9af570b680000000 bf870f78b4f4a77b88cb5cb9c9b493f7 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintrne.f32.f32 s4, s13 4b124b2e6c940b8e6c940b8eebc43b0b 4e115535880e1d47c7dee11d13393dd5 4b124b2e6c940b8e6c940b8ec7dee100 4e115535880e1d47c7dee11d13393dd5 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintrne.f32.f32 s4, s13 db148f410800531f865509b51061dada 2313ccbc218b455d28cd89d38e74f714 db148f410800531f865509b500000000 2313ccbc218b455d28cd89d38e74f714 fpscr=00000000
+vrintrne.f32.f32 s4, s13 0bc41c56b8d73f6dd918bf16ad198893 094627f8a2a23f53bd5df052290fcccb 0bc41c56b8d73f6dd918bf1680000000 094627f8a2a23f53bd5df052290fcccb fpscr=00000000
+vrintrne.f32.f32 s4, s13 2bd6e80ccecab45ceaef46a993b3aba8 0e5940f9fcffdf68fadb0cade9251b46 2bd6e80ccecab45ceaef46a9fadb0cad 0e5940f9fcffdf68fadb0cade9251b46 fpscr=00000000
+vrintrne.f32.f32 s4, s13 f601474e91a504e4feff1d6c8a01d027 2d661b4a2f542fa076dd5fa032baeb03 f601474e91a504e4feff1d6c76dd5fa0 2d661b4a2f542fa076dd5fa032baeb03 fpscr=00000000
+vrintrne.f32.f32 s4, s13 1e3b346faf023550209aff4979c437e3 b453800ea34b82ae3cb15c9dd6be0781 1e3b346faf023550209aff4900000000 b453800ea34b82ae3cb15c9dd6be0781 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintrne.f32.f32 s4, s13 8335ebc3e95d1f892f7ff0c5b914b99d 8f6a09231c59a513cbb1fcd7965027d2 8335ebc3e95d1f892f7ff0c5cbb1fcd7 8f6a09231c59a513cbb1fcd7965027d2 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintrne.f32.f32 s4, s13 2b0676eabeddf9b01dca0c4bbeddf9b0 98c16a189dd1d3a252bc37d05c3798eb 2b0676eabeddf9b01dca0c4b52bc37d0 98c16a189dd1d3a252bc37d05c3798eb fpscr=00000000
+vrintrne.f32.f32 s4, s13 3773d079055e3a0b9d59e8512f42a39b 20f0ddf00755bb14cda21c59884b9b67 3773d079055e3a0b9d59e851cda21c59 20f0ddf00755bb14cda21c59884b9b67 fpscr=00000000
+vrintr.f32.f32 s5, s14 c4044c8ca87a0d46e4712d49c8b9c85c 5ba802b295bdf421b6764fdec88f65cb c4044c8ca87a0d4680000000c8b9c85c 5ba802b295bdf421b6764fdec88f65cb fpscr=00000000
+vrintr.f32.f32 s5, s14 5e1d0179b99f7feb9054810c92daa0b1 4b7a07483603ec672959962255407041 5e1d0179b99f7feb0000000092daa0b1 4b7a07483603ec672959962255407041 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintr.f32.f32 s5, s14 a2810252f89397891e1321e1bc24a552 fa216c76a75e5f8e72f2f470fa216c76 a2810252f893978980000000bc24a552 fa216c76a75e5f8e72f2f470fa216c76 fpscr=00000000
+vrintr.f32.f32 s5, s14 5c66c23e54cb4a7d16ae7fa60fe5f337 af445da7b3cc9be9f340d8c4ab9c27bb 5c66c23e54cb4a7d800000000fe5f337 af445da7b3cc9be9f340d8c4ab9c27bb fpscr=00000000
+vrintr.f32.f32 s5, s14 3bdf35a81626c9754edff07d4ac39d64 bbf1dff955eb7fcf6e4d85fa5df158fd 3bdf35a81626c97555eb7fcf4ac39d64 bbf1dff955eb7fcf6e4d85fa5df158fd fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[3]
+vrintr.f32.f32 s5, s14 518e97de44aeb941b1c1eac8518e97de 2e2e064c2e2e064ca7cce8a090ee3425 518e97de44aeb94100000000518e97de 2e2e064c2e2e064ca7cce8a090ee3425 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintr.f32.f32 s5, s14 29d2cadb2877c9a04940ae5b07d8b2d5 fc5e036f1e08aa3b1cf52bef1cf52bef 29d2cadb2877c9a00000000007d8b2d5 fc5e036f1e08aa3b1cf52bef1cf52bef fpscr=00000000
+vrintr.f32.f32 s5, s14 3e6cf017afd55687ae5d3c0948e85745 4c795d6e8ddb0736d4be2a46fa5187e8 3e6cf017afd556878000000048e85745 4c795d6e8ddb0736d4be2a46fa5187e8 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintr.f32.f32 s5, s14 8cde6bb706ebebff8cde6bb715aa861d 37014f45105abe46ca30c42901129b51 8cde6bb706ebebff0000000015aa861d 37014f45105abe46ca30c42901129b51 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintr.f32.f32 s5, s14 c9c2a52c7a613928afa1d3d204c53377 88e36ec0a9e5717acdc01b0f88e36ec0 c9c2a52c7a6139288000000004c53377 88e36ec0a9e5717acdc01b0f88e36ec0 fpscr=00000000
+vrintr.f32.f32 s5, s14 b530c37173f13ca899a2c13239c3933e ed2a9667de4b459903f70cbe337a357f b530c37173f13ca8de4b459939c3933e ed2a9667de4b459903f70cbe337a357f fpscr=00000000
+vrintr.f32.f32 s5, s14 25a6751819ea54a82ea64bae0e90a6ed 20ef8a5e8bf79f99f1bdf9a250a8bf6e 25a6751819ea54a8800000000e90a6ed 20ef8a5e8bf79f99f1bdf9a250a8bf6e fpscr=00000000
+vrintr.f32.f32 s5, s14 b123d31d5b83837819283ef47959d633 832af8af6d72f765cd59065d323603df b123d31d5b8383786d72f7657959d633 832af8af6d72f765cd59065d323603df fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintr.f32.f32 s5, s14 95c4308f954b62b6fc298943954b62b6 a030e0ee86d93bd5577293d9881c1230 95c4308f954b62b680000000954b62b6 a030e0ee86d93bd5577293d9881c1230 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintr.f32.f32 s5, s14 63ba5c671abbbc9b74414f7b3f0ce7fa b6c202f108c0428f70bd5869fbc5c93b 63ba5c671abbbc9b000000003f0ce7fa b6c202f108c0428f70bd5869fbc5c93b fpscr=00000000
+vrintr.f32.f32 s5, s14 53c0a60f29af65b32abe8ed791d3bb0e 59c18663fe60072c05a377fd68e345c9 53c0a60f29af65b3fe60072c91d3bb0e 59c18663fe60072c05a377fd68e345c9 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintr.f32.f32 s5, s14 2174e4aa044d67fb290924c12174e4aa d121ea41b5d1eae36f626004f673cb89 2174e4aa044d67fb800000002174e4aa d121ea41b5d1eae36f626004f673cb89 fpscr=00000000
+vrintr.f32.f32 s5, s14 0fe3382a5f457e1a8133d567dc83696c 1dfb0265cea5f7791a7eee6d42c4dbbc 0fe3382a5f457e1acea5f779dc83696c 1dfb0265cea5f7791a7eee6d42c4dbbc fpscr=00000000
+vrintr.f32.f32 s5, s14 b67d2ba6fc4a83aa03d4c1d6fadfa095 5387cedca1eb4edbbad4f6d16c2b6bc4 b67d2ba6fc4a83aa80000000fadfa095 5387cedca1eb4edbbad4f6d16c2b6bc4 fpscr=00000000
+vrintr.f32.f32 s5, s14 fd97f47b121b7b0c90fb9059510f28b7 c857d8cd7dc3725edbcfe6f5bbdad25a fd97f47b121b7b0c7dc3725e510f28b7 c857d8cd7dc3725edbcfe6f5bbdad25a fpscr=00000000
+vrintr.f32.f32 s5, s14 90b258bb42500a6e82320583ba6d08d3 0a1b0e6243bb2368b5cb2510fd8257f3 90b258bb42500a6e43bb0000ba6d08d3 0a1b0e6243bb2368b5cb2510fd8257f3 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vrintr.f32.f32 s5, s14 e201b384d6f5ab5dd8f6e878e61fa76a 561c94beb4a97443b4a974435b7f47d3 e201b384d6f5ab5d80000000e61fa76a 561c94beb4a97443b4a974435b7f47d3 fpscr=00000000
+vrintr.f32.f32 s5, s14 a2ba118e74be7ddf5678012a3cd0be39 bef21083ff3b12976721285d1e23932e a2ba118e74be7ddfff3b12973cd0be39 bef21083ff3b12976721285d1e23932e fpscr=00000000
+vrintr.f32.f32 s5, s14 a6d98895f7feab9826d04a31f3f1a2a5 0b26850edb53f3eadd1682d8863cd595 a6d98895f7feab98db53f3eaf3f1a2a5 0b26850edb53f3eadd1682d8863cd595 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintr.f32.f32 s5, s14 5d70dbe9b756ef0fb756ef0f454444ba d0b20d64c881e555a3007bbfa8ebf41b 5d70dbe9b756ef0fc881e560454444ba d0b20d64c881e555a3007bbfa8ebf41b fpscr=00000000
+vrintr.f32.f32 s5, s14 a401f59a468a68a1da186fc91d0cb2d9 4669cd1ee1dc649f4bd7560277d534b3 a401f59a468a68a1e1dc649f1d0cb2d9 4669cd1ee1dc649f4bd7560277d534b3 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintr.f32.f32 s5, s14 8951ce39cad568b6301747b0937e1654 4ed6b0d48fa15310f1399f4bf1399f4b 8951ce39cad568b680000000937e1654 4ed6b0d48fa15310f1399f4bf1399f4b fpscr=00000000
+vrintr.f32.f32 s5, s14 03ff27ad8fe4ddcb360180019908f3f1 668cf64b62743e159e65db2228518dc0 03ff27ad8fe4ddcb62743e159908f3f1 668cf64b62743e159e65db2228518dc0 fpscr=00000000
+vrintr.f32.f32 s5, s14 192c11ec2a8d0ac246c51438c339d85b f108bd36f71620f6aae1ede66808a1a5 192c11ec2a8d0ac2f71620f6c339d85b f108bd36f71620f6aae1ede66808a1a5 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintr.f32.f32 s5, s14 ca2ab02cd4176c6df979b6c6481bc3ef c5fa91b974ee5fffd8add460fb14cb19 ca2ab02cd4176c6d74ee5fff481bc3ef c5fa91b974ee5fffd8add460fb14cb19 fpscr=00000000
+vrintr.f32.f32 s5, s14 743ee21ac6ad8d1a38c7b9d1e21a6173 5ee8422b6c76b9fd84cd5b4d9db5a3e7 743ee21ac6ad8d1a6c76b9fde21a6173 5ee8422b6c76b9fd84cd5b4d9db5a3e7 fpscr=00000000
+randV128: 9728 calls, 10041 iters
+vrintr.f32.f32 s5, s14 5dd83f7d2d7a2558eb525e274bc9549f 12f11cedd66f222dd83f23deccf33b23 5dd83f7d2d7a2558d66f222d4bc9549f 12f11cedd66f222dd83f23deccf33b23 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintr.f32.f32 s5, s14 bfdfe09f0554c9b6a15d4442e4e014d2 da4909ef7e80cc53610962a1e8b4aebd bfdfe09f0554c9b67e80cc53e4e014d2 da4909ef7e80cc53610962a1e8b4aebd fpscr=00000000
+vrintr.f32.f32 s5, s14 ea7e363cf97f9127e59e0ef5e46a30c8 9720a029966678b40dc42a48d961df15 ea7e363cf97f912780000000e46a30c8 9720a029966678b40dc42a48d961df15 fpscr=00000000
+vrintr.f32.f32 s5, s14 792ff382657824abf3accaf390c6d79c f7f0b9393247af79c17e64dd4dd9f6a8 792ff382657824ab0000000090c6d79c f7f0b9393247af79c17e64dd4dd9f6a8 fpscr=00000000
+vrintr.f32.f32 s5, s14 26fe284f4b1b540d849afb6ee6cb8025 c20681c1181401cecd5831c776a43e5b 26fe284f4b1b540d00000000e6cb8025 c20681c1181401cecd5831c776a43e5b fpscr=00000000
+vrintr.f32.f32 s5, s14 9cb5d49e4f302a3dd527facc6f786366 52fb351c4c709854b94ed4e2bd5c91b2 9cb5d49e4f302a3d4c7098546f786366 52fb351c4c709854b94ed4e2bd5c91b2 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintr.f32.f32 s5, s14 8f7492348639b4910c5ae5bb74748bd5 a376fdf026652ce163253e98c3d60159 8f7492348639b4910000000074748bd5 a376fdf026652ce163253e98c3d60159 fpscr=00000000
+vrintr.f32.f32 s5, s14 6d958ce712e5d33b46cd422bdb1a3edb da912ad775b7b0719b156dd8a8646906 6d958ce712e5d33b75b7b071db1a3edb da912ad775b7b0719b156dd8a8646906 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintr.f32.f32 s5, s14 87bef3baefdc0645efdc0645af63b0ea 819e9bd05555848b530e55010a487713 87bef3baefdc06455555848baf63b0ea 819e9bd05555848b530e55010a487713 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintr.f32.f32 s5, s14 53583dcb45da5db029c1cc4e4911015f a7f58adfe5daffecfce10a7212d4e151 53583dcb45da5db0e5daffec4911015f a7f58adfe5daffecfce10a7212d4e151 fpscr=00000000
+vrintr.f32.f32 s5, s14 dd79c32da747b9b4cf1b10be2efc29d2 eeb668fd17348a5d7bfe7b7cd0eb6044 dd79c32da747b9b4000000002efc29d2 eeb668fd17348a5d7bfe7b7cd0eb6044 fpscr=00000000
+vrintr.f32.f32 s5, s14 2e30b7f6a8719752b30cd7789f1da562 e517da6c66b99e9f6f8afda13625f74a 2e30b7f6a871975266b99e9f9f1da562 e517da6c66b99e9f6f8afda13625f74a fpscr=00000000
+vrintr.f32.f32 s5, s14 b62103b6ca7dc417e227c687a7e2ec25 e995b58af73ae1ce96a9e60cb87bb638 b62103b6ca7dc417f73ae1cea7e2ec25 e995b58af73ae1ce96a9e60cb87bb638 fpscr=00000000
+vrintr.f32.f32 s5, s14 fc84111c92c2a783ca85c728f9ba537e 97bc0af8f7bae809fe9bda3d2dcfc371 fc84111c92c2a783f7bae809f9ba537e 97bc0af8f7bae809fe9bda3d2dcfc371 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vrintr.f32.f32 s5, s14 8b132d5419bc972c19bc972c8e261f07 d74a5a1f3b2d73513b2d73512a6ad997 8b132d5419bc972c000000008e261f07 d74a5a1f3b2d73513b2d73512a6ad997 fpscr=00000000
+vrintr.f32.f32 s5, s14 0e6174bb6d5c0f699022c4103eb7a168 b5bd26a291e4c1bec2470356f467070d 0e6174bb6d5c0f69800000003eb7a168 b5bd26a291e4c1bec2470356f467070d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[1]
+vrintr.f32.f32 s5, s14 5dbf9d5d54023831b95f588fb95f588f 1456fb1ab51842cc25d3f418aacf07ba 5dbf9d5d5402383180000000b95f588f 1456fb1ab51842cc25d3f418aacf07ba fpscr=00000000
+vrintr.f32.f32 s5, s14 f6b1c7fb7bbac2999f8461433c2c8270 bbf3429b7269b894a22695b9be39f79b f6b1c7fb7bbac2997269b8943c2c8270 bbf3429b7269b894a22695b9be39f79b fpscr=00000000
+vrintr.f32.f32 s5, s14 63b68a156aa9509422b9bec39c3ad373 3179177c020b74d210ae4515f113e61e 63b68a156aa95094000000009c3ad373 3179177c020b74d210ae4515f113e61e fpscr=00000000
+vrintxeq.f32.f32 s6, s15 7dceaaddf35dfac68fbb145524e50f57 8e333c704723d4b347eb389b8de6f7c1 7dceaaddf35dfac68fbb145524e50f57 8e333c704723d4b347eb389b8de6f7c1 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 72aefa55c52dbcb34bcd4a1dc6c9711d abe575e8e56143fb382c51a36af57056 72aefa55c52dbcb34bcd4a1dc6c9711d abe575e8e56143fb382c51a36af57056 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 89fa64a9b14a202a4ae2b48ccbe7dbf9 ff0a6e42e3b0854fd5e419c3e5f470aa 89fa64a9b14a202a4ae2b48ccbe7dbf9 ff0a6e42e3b0854fd5e419c3e5f470aa fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintxeq.f32.f32 s6, s15 dc0f2aca06b7240603ab91416ccff349 a306038ec91123a5532652db3f1d9f2b dc0f2aca06b7240603ab91416ccff349 a306038ec91123a5532652db3f1d9f2b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintxeq.f32.f32 s6, s15 eb046bb390f3420f83c7cc87f7c3c9b1 a88d29b972b79acbb60448786274dca8 eb046bb390f3420f83c7cc87f7c3c9b1 a88d29b972b79acbb60448786274dca8 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintxeq.f32.f32 s6, s15 a10d0c5c95a3e0022e36541489501421 d8513d775d7c6902b9091ca9a509a38a a10d0c5c95a3e0022e36541489501421 d8513d775d7c6902b9091ca9a509a38a fpscr=00000000
+vrintxeq.f32.f32 s6, s15 b2a41da880e8eb03cfb44de7191ac708 9c252da5b6e993c07baf4e77b482fd75 b2a41da880e8eb03cfb44de7191ac708 9c252da5b6e993c07baf4e77b482fd75 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vrintxeq.f32.f32 s6, s15 3cba7d2d1021b7403cba7d2d46634fd4 79f7e2b9861fab196cf50258861fab19 3cba7d2d1021b7403cba7d2d46634fd4 79f7e2b9861fab196cf50258861fab19 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[1]
+vrintxeq.f32.f32 s6, s15 8f5925edb5988521b59885215b83bd48 e94e481317270cc50c5264d68bfb9f1e 8f5925edb5988521b59885215b83bd48 e94e481317270cc50c5264d68bfb9f1e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[2]
+vrintxeq.f32.f32 s6, s15 1f02550600e4d0bb1f02550676f46810 d9a6c051a773d2019436a659353d2ee2 1f02550600e4d0bb1f02550676f46810 d9a6c051a773d2019436a659353d2ee2 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 43d6052773d139b2f24b57b56460aa63 183d8255ec977b56f12c86326d81074f 43d6052773d139b2f24b57b56460aa63 183d8255ec977b56f12c86326d81074f fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintxeq.f32.f32 s6, s15 2e80be9e43d17dd566e8db794e1c0ac9 9aa0fc5c8dc32d206bf11fc9f1abf94d 2e80be9e43d17dd566e8db794e1c0ac9 9aa0fc5c8dc32d206bf11fc9f1abf94d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintxeq.f32.f32 s6, s15 5ea12de1253869e1e4c7bc0406191a69 c8b63bc1b511d8ed6247cf580ad4b724 5ea12de1253869e1e4c7bc0406191a69 c8b63bc1b511d8ed6247cf580ad4b724 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintxeq.f32.f32 s6, s15 5cf7d1b291f175e1121e192991091fe5 16e255b4e2e46ee5521e8254a040069f 5cf7d1b291f175e1121e192991091fe5 16e255b4e2e46ee5521e8254a040069f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintxeq.f32.f32 s6, s15 ead2f7c9c63730d5753a97de6f91ba90 b21ef5bd73c505e88b2af1202f4e90d6 ead2f7c9c63730d5753a97de6f91ba90 b21ef5bd73c505e88b2af1202f4e90d6 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 80a56cea52d74a83354d758b1b1c3384 a08a7b92edd19478b71d86da403d18b6 80a56cea52d74a83354d758b1b1c3384 a08a7b92edd19478b71d86da403d18b6 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 9c30ac3017e02a815006d97794f3172c 66748822cc1839bba50470eda1097935 9c30ac3017e02a815006d97794f3172c 66748822cc1839bba50470eda1097935 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 7beba304d9c290007a1e96ce90ebcb75 9acaa5103b4d8bf21419371c662d6faf 7beba304d9c290007a1e96ce90ebcb75 9acaa5103b4d8bf21419371c662d6faf fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintxeq.f32.f32 s6, s15 d2aab42e98822582fb475d9993230fda 6899e9abc1eba0ec9ea008c06899e9ab d2aab42e98822582fb475d9993230fda 6899e9abc1eba0ec9ea008c06899e9ab fpscr=00000000
+vrintxeq.f32.f32 s6, s15 9e8929cd220f50c9dcddb5916030215e d794348be5758411e8914fa8075dab98 9e8929cd220f50c9dcddb5916030215e d794348be5758411e8914fa8075dab98 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintxeq.f32.f32 s6, s15 c2429600e95629c1e1f807aa871c35f5 3d9b94b5cd137ee5f9ed7ca6e5132560 c2429600e95629c1e1f807aa871c35f5 3d9b94b5cd137ee5f9ed7ca6e5132560 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 ecfdd022739c7c43f83a03aff7a64970 47f9c3fdb262e4f132605ab70da7f5e6 ecfdd022739c7c43f83a03aff7a64970 47f9c3fdb262e4f132605ab70da7f5e6 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 30bbbf9e440f2728428aea8e21734b73 84c41b22b7643ff26d3f90d352e95de2 30bbbf9e440f2728428aea8e21734b73 84c41b22b7643ff26d3f90d352e95de2 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 afb8f376e029d9870dfd78162c656c02 b241a0b14efecff3e5580f38c7cf21a1 afb8f376e029d9870dfd78162c656c02 b241a0b14efecff3e5580f38c7cf21a1 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintxeq.f32.f32 s6, s15 7277bc98124a4b10182093d6a7a523cb 5711e39809fb0b71b456033cb0361132 7277bc98124a4b10182093d6a7a523cb 5711e39809fb0b71b456033cb0361132 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 5dfa5d263ddc8972837e73f2496e3780 adb9564a1a709c248291bbca0430962e 5dfa5d263ddc8972837e73f2496e3780 adb9564a1a709c248291bbca0430962e fpscr=00000000
+vrintxeq.f32.f32 s6, s15 4dd4e66eb7a22e2ebb5673f156653191 9320f4aa6e47f8134a82d9a29e6ea60f 4dd4e66eb7a22e2ebb5673f156653191 9320f4aa6e47f8134a82d9a29e6ea60f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+vrintxeq.f32.f32 s6, s15 284edc65284edc65a98708080bf091d6 4f31046dae3029c2506f484710ffc4be 284edc65284edc65a98708080bf091d6 4f31046dae3029c2506f484710ffc4be fpscr=00000000
+vrintxeq.f32.f32 s6, s15 1f97af341d723650fd0fc4a3ee7b65da 410d3d98bafb1082e9ace9f4252c5163 1f97af341d723650fd0fc4a3ee7b65da 410d3d98bafb1082e9ace9f4252c5163 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 46251313c2906c67f107d4b3fb1198b6 a09650331f5e8124160e73ec937112c9 46251313c2906c67f107d4b3fb1198b6 a09650331f5e8124160e73ec937112c9 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 1e588b5c8a1da2ddb119da0313f6d5b7 051788d951a781c5e3b3ed59b3a64731 1e588b5c8a1da2ddb119da0313f6d5b7 051788d951a781c5e3b3ed59b3a64731 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintxeq.f32.f32 s6, s15 a5ed303692181975d79bf095cd91d966 7142f649117147d54ffa4f8deeecdf17 a5ed303692181975d79bf095cd91d966 7142f649117147d54ffa4f8deeecdf17 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintxeq.f32.f32 s6, s15 caefaeb43e2de9c3caefaeb455630eff f8e845e4ea12d8e1d6fbe8752f2a7977 caefaeb43e2de9c3caefaeb455630eff f8e845e4ea12d8e1d6fbe8752f2a7977 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 237e9eb0e54443568adbaecb532cdfc2 849dab0c7922b4437aae0a3e73128494 237e9eb0e54443568adbaecb532cdfc2 849dab0c7922b4437aae0a3e73128494 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 662986243cb629d33e2af074afa44729 0e630b1f93f1d0ec3d76f9f1c9877cbb 662986243cb629d33e2af074afa44729 0e630b1f93f1d0ec3d76f9f1c9877cbb fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintxeq.f32.f32 s6, s15 7c8d3ad5d9372ab95582fac2582e5458 43c81db2e100029c2cfd2009a7c373ce 7c8d3ad5d9372ab95582fac2582e5458 43c81db2e100029c2cfd2009a7c373ce fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintxeq.f32.f32 s6, s15 4215eb83b9206c9d9a5b490f62e14e42 1b2d4a559d3b64caeca5e4d3db23b0a1 4215eb83b9206c9d9a5b490f62e14e42 1b2d4a559d3b64caeca5e4d3db23b0a1 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 bbf6957ebdc179e7cd8894ea390dba9a 8c17fec3b2513b1efca88f1cbc60b351 bbf6957ebdc179e7cd8894ea390dba9a 8c17fec3b2513b1efca88f1cbc60b351 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 6bd195fb9ab2d2f630d38c7d48e23df2 dbd2fa2fb356f19d4c8d3fe34bcded44 6bd195fb9ab2d2f630d38c7d48e23df2 dbd2fa2fb356f19d4c8d3fe34bcded44 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 a4199390c9a753cf4e6fba79dc905c38 b1ac5c99d5d8bca502a3fd9b48b9865e a4199390c9a753cf4e6fba79dc905c38 b1ac5c99d5d8bca502a3fd9b48b9865e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[0]
+vrintxeq.f32.f32 s6, s15 b6706d3d0d73e9cb0d73e9cbb88d2d66 46f7dfd0128fa030f67cb07c7cca2e6d b6706d3d0d73e9cb0d73e9cbb88d2d66 46f7dfd0128fa030f67cb07c7cca2e6d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintxeq.f32.f32 s6, s15 0091c86174cb27164497b35a6d4dd0f6 b821770180b4b527bda2bbd480b4b527 0091c86174cb27164497b35a6d4dd0f6 b821770180b4b527bda2bbd480b4b527 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 7c179b2cf96e6f2c5f890034281bfa99 866c38b77d0f55c74be10c7f502f9f7b 7c179b2cf96e6f2c5f890034281bfa99 866c38b77d0f55c74be10c7f502f9f7b fpscr=00000000
+vrintxeq.f32.f32 s6, s15 f87e1ec5b78f76c9f8ba5b5d1cf4f285 bbc9fc55e4c21a6d1e20cc012e3f5c0a f87e1ec5b78f76c9f8ba5b5d1cf4f285 bbc9fc55e4c21a6d1e20cc012e3f5c0a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintxeq.f32.f32 s6, s15 7b87f5de793bea87e5c7a36a83872506 9d23dfb2ae6013fb2d63750fbb95fd31 7b87f5de793bea87e5c7a36a83872506 9d23dfb2ae6013fb2d63750fbb95fd31 fpscr=00000000
+randV128: 9984 calls, 10305 iters
+vrintxeq.f32.f32 s6, s15 fc35cec7b7a0f66fa02613b63f9b659e ac56febd78457c44080b3ae7204141af fc35cec7b7a0f66fa02613b63f9b659e ac56febd78457c44080b3ae7204141af fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintxeq.f32.f32 s6, s15 8a000512946c2c0bf1ef10f2f1ef10f2 b4f83a29fcf36f01d738a06a5e5c825c 8a000512946c2c0bf1ef10f2f1ef10f2 b4f83a29fcf36f01d738a06a5e5c825c fpscr=00000000
+vrintxeq.f32.f32 s6, s15 a08fca36439b459d334ac51438400ea9 60106840856409c426c40653d3bed675 a08fca36439b459d334ac51438400ea9 60106840856409c426c40653d3bed675 fpscr=00000000
+vrintxeq.f32.f32 s6, s15 46813bbf7283effbe332ddcc9eff4f0e 4eb47e7ca9b420ea21e008471d6e81c7 46813bbf7283effbe332ddcc9eff4f0e 4eb47e7ca9b420ea21e008471d6e81c7 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintxeq.f32.f32 s6, s15 52bebdb933811efa313d2ab459e1e571 961bf0bd20d9cf6d7c5d17016acc1912 52bebdb933811efa313d2ab459e1e571 961bf0bd20d9cf6d7c5d17016acc1912 fpscr=00000000
+vrintxne.f32.f32 s7, s16 e73f871a86f6cf9e9664e2b67e673e9f 246edc11d0c60f8d64c51a584cb2b96c 4cb2b96c86f6cf9e9664e2b67e673e9f 246edc11d0c60f8d64c51a584cb2b96c fpscr=00000000
+vrintxne.f32.f32 s7, s16 ac3f4143fb7f71ec02974501b25eb500 2298339404650a86b1ac2f11d2681c93 d2681c93fb7f71ec02974501b25eb500 2298339404650a86b1ac2f11d2681c93 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[0]
+vrintxne.f32.f32 s7, s16 0505e94ce68615c79e0bea6fe68615c7 413ce5f9d6c64ff3f1063a423d223bd1 00000000e68615c79e0bea6fe68615c7 413ce5f9d6c64ff3f1063a423d223bd1 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintxne.f32.f32 s7, s16 5149001ff61f59a3c946433eacd64199 c0396961c0396961c432fcfe284070b5 00000000f61f59a3c946433eacd64199 c0396961c0396961c432fcfe284070b5 fpscr=00000000
+vrintxne.f32.f32 s7, s16 1fbc82eef0bd3ec4d5aa54e30ad0ce99 5c2936e8e377c51625ed6109cb064ffa cb064ffaf0bd3ec4d5aa54e30ad0ce99 5c2936e8e377c51625ed6109cb064ffa fpscr=00000000
+vrintxne.f32.f32 s7, s16 e3ea5827ab19bbd8a72765b419930e87 eae30ccd523b3d920749ee0fe298b9ed e298b9edab19bbd8a72765b419930e87 eae30ccd523b3d920749ee0fe298b9ed fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintxne.f32.f32 s7, s16 0927c557d9f52c3e81a1cc8ebcd5a67a 03f80334129f73738894ffe3cb531f54 cb531f54d9f52c3e81a1cc8ebcd5a67a 03f80334129f73738894ffe3cb531f54 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintxne.f32.f32 s7, s16 3e842d83bc8225361c8f8603d1844886 b42cfb6524756cbba358bc0753fab112 53fab112bc8225361c8f8603d1844886 b42cfb6524756cbba358bc0753fab112 fpscr=00000000
+vrintxne.f32.f32 s7, s16 37fb637fa08f3445c3f4d9d8a5c223ae 0c4ecd81eba6a47f30c913c6575ab902 575ab902a08f3445c3f4d9d8a5c223ae 0c4ecd81eba6a47f30c913c6575ab902 fpscr=00000000
+vrintxne.f32.f32 s7, s16 3727925a8f4c0bd4a03025ed74520a57 2d688cc7b2ee23a14491e62506e0e703 000000008f4c0bd4a03025ed74520a57 2d688cc7b2ee23a14491e62506e0e703 fpscr=00000000
+vrintxne.f32.f32 s7, s16 0a808d33b2cc69106e26548e728b6f5e 6723355c0ff8cac7f3aefa393b665b7d 00000000b2cc69106e26548e728b6f5e 6723355c0ff8cac7f3aefa393b665b7d fpscr=00000000
+vrintxne.f32.f32 s7, s16 84e3e810a8bdc3e42a87e68934699d8e cf87ac4be77dd7854b9e96c4b0ed32a9 80000000a8bdc3e42a87e68934699d8e cf87ac4be77dd7854b9e96c4b0ed32a9 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintxne.f32.f32 s7, s16 0bab52824c5ec50619800596ff3969a6 d741cc0e5c080f7b5c080f7bc1bad120 c1b800004c5ec50619800596ff3969a6 d741cc0e5c080f7b5c080f7bc1bad120 fpscr=00000000
+vrintxne.f32.f32 s7, s16 e251ab5b3b1d694593931dac741bbea8 976230408ebcce2d091c5faabcd6afd2 800000003b1d694593931dac741bbea8 976230408ebcce2d091c5faabcd6afd2 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[3]
+vrintxne.f32.f32 s7, s16 bbb78e2ad7dbd113738e66e0cdc157ac 266780a71a88bb223ffbb7ce3ffbb7ce 40000000d7dbd113738e66e0cdc157ac 266780a71a88bb223ffbb7ce3ffbb7ce fpscr=00000000
+vrintxne.f32.f32 s7, s16 c1170c4e0a46d3788b57d500d13f8ddb fae3d53e04370826b7a979b0b28a58b2 800000000a46d3788b57d500d13f8ddb fae3d53e04370826b7a979b0b28a58b2 fpscr=00000000
+vrintxne.f32.f32 s7, s16 c8e74f71e52abf16a9eb1946a56e08d2 907237b0dc6c1fae95a1d58cab8ca13c 80000000e52abf16a9eb1946a56e08d2 907237b0dc6c1fae95a1d58cab8ca13c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintxne.f32.f32 s7, s16 72daaca0a2485a75a0b0c976398501df ae79fc5fa23b8f857de3960db6d4d0ab 80000000a2485a75a0b0c976398501df ae79fc5fa23b8f857de3960db6d4d0ab fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintxne.f32.f32 s7, s16 bb492fd9e43bbb025fb6795be43bbb02 2d899a33dcee40f5647dfbd1d4c260d8 d4c260d8e43bbb025fb6795be43bbb02 2d899a33dcee40f5647dfbd1d4c260d8 fpscr=00000000
+vrintxne.f32.f32 s7, s16 60aba9de3f7b1c86192d13d09697c6fa aa5c45d76ec9836a98b79222391cc344 000000003f7b1c86192d13d09697c6fa aa5c45d76ec9836a98b79222391cc344 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintxne.f32.f32 s7, s16 9a640f949a640f94e5999fc08641df94 b40acaf6c1843e1c136992c74307d827 430800009a640f94e5999fc08641df94 b40acaf6c1843e1c136992c74307d827 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintxne.f32.f32 s7, s16 6a7c9e931dd58f44f809cf6969d48ff5 717ffeb8d58667fbd979d26f26c777e2 000000001dd58f44f809cf6969d48ff5 717ffeb8d58667fbd979d26f26c777e2 fpscr=00000000
+vrintxne.f32.f32 s7, s16 b55f52fe7ac8f3637c00aa5b22bdf940 087af15f95c5935d54563144504fac19 504fac197ac8f3637c00aa5b22bdf940 087af15f95c5935d54563144504fac19 fpscr=00000000
+vrintxne.f32.f32 s7, s16 227ebeeb07b5f43d6c47ddb171069ce9 15c73add7f2ba51206f28e6f43b71e54 43b7000007b5f43d6c47ddb171069ce9 15c73add7f2ba51206f28e6f43b71e54 fpscr=00000000
+vrintxne.f32.f32 s7, s16 2173ad24981bb6fef8d9249b74d3118d 3b3671457d1653c5881c93f5feddb6ef feddb6ef981bb6fef8d9249b74d3118d 3b3671457d1653c5881c93f5feddb6ef fpscr=00000000
+vrintxne.f32.f32 s7, s16 9dc75512d9d457beb61339efd30072d8 31b8ee41641928814e66b1dd2dc72ab3 00000000d9d457beb61339efd30072d8 31b8ee41641928814e66b1dd2dc72ab3 fpscr=00000000
+vrintxne.f32.f32 s7, s16 8c48acd692a2ff474021afa95df836e2 1357477741c0bfec8502830468153588 6815358892a2ff474021afa95df836e2 1357477741c0bfec8502830468153588 fpscr=00000000
+vrintxne.f32.f32 s7, s16 85bf23c6ccce41761a2750dbb53a17c4 5a9979278f2c5a52b73571557c52622f 7c52622fccce41761a2750dbb53a17c4 5a9979278f2c5a52b73571557c52622f fpscr=00000000
+vrintxne.f32.f32 s7, s16 68a461f6162f107be69cd1629836a5af 862267e2035885f7bd346dc07176e5db 7176e5db162f107be69cd1629836a5af 862267e2035885f7bd346dc07176e5db fpscr=00000000
+vrintxne.f32.f32 s7, s16 e4fcde6fa52bfb2b2765af4b3b92bd7b 0b44b9aacdc0808e2d72add0de730901 de730901a52bfb2b2765af4b3b92bd7b 0b44b9aacdc0808e2d72add0de730901 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintxne.f32.f32 s7, s16 efc9973b4e64f4a9e03b9827d7407754 636f0a99cd1ebe5740eb0ade636f0a99 636f0a994e64f4a9e03b9827d7407754 636f0a99cd1ebe5740eb0ade636f0a99 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintxne.f32.f32 s7, s16 a2d5b7e8cb383633856fcccc4a0553f5 f74826ca74dd18d316d073ce5ed5215d 5ed5215dcb383633856fcccc4a0553f5 f74826ca74dd18d316d073ce5ed5215d fpscr=00000000
+vrintxne.f32.f32 s7, s16 32fb06cff641ba0d1ece993827a8aa4e 7c207b34c21ea288ca6b56c4e75b84f6 e75b84f6f641ba0d1ece993827a8aa4e 7c207b34c21ea288ca6b56c4e75b84f6 fpscr=00000000
+vrintxne.f32.f32 s7, s16 e5b5ece92bf4c9aa96ae065cde651d98 4b8d6d55d03992df17cbfcb41e5dbf99 000000002bf4c9aa96ae065cde651d98 4b8d6d55d03992df17cbfcb41e5dbf99 fpscr=00000000
+vrintxne.f32.f32 s7, s16 7f113b505308937899aafd131cd26622 107f13e2f25eff9ac0bf3e3313d664ac 000000005308937899aafd131cd26622 107f13e2f25eff9ac0bf3e3313d664ac fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[3]
+vrintxne.f32.f32 s7, s16 213b4f54b2ac8cab83ddc86cb2ac8cab cf7899f3535ec8e568421b4b5a87ffe9 5a87ffe9b2ac8cab83ddc86cb2ac8cab cf7899f3535ec8e568421b4b5a87ffe9 fpscr=00000000
+vrintxne.f32.f32 s7, s16 c96884ab4bd5d95bea30006e5152799d 39b68cac9064fc61f5065eda43bd01d8 43bd00004bd5d95bea30006e5152799d 39b68cac9064fc61f5065eda43bd01d8 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintxne.f32.f32 s7, s16 2c6475cbf4629b5c1f99e1a2f4629b5c 39a5f53915022771ed50d3652c8a5a62 00000000f4629b5c1f99e1a2f4629b5c 39a5f53915022771ed50d3652c8a5a62 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintxne.f32.f32 s7, s16 bf9a39605088e553101fab6422d8f57c 29a9a9606b6bcb3f651577a86918d360 6918d3605088e553101fab6422d8f57c 29a9a9606b6bcb3f651577a86918d360 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintxne.f32.f32 s7, s16 eeec7fcdeeec7fcde41ec4609021359d b822ada82e148eb4a6b87abd1dd3711a 00000000eeec7fcde41ec4609021359d b822ada82e148eb4a6b87abd1dd3711a fpscr=00000000
+vrintxne.f32.f32 s7, s16 d4ab938707503f65483ab17fa090da46 35e2dbc73ab0fc4127bc43966685e55a 6685e55a07503f65483ab17fa090da46 35e2dbc73ab0fc4127bc43966685e55a fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintxne.f32.f32 s7, s16 adcb5e1789ab16c389ab16c3724f43ec fe3f9152447945a616987815b25dc88c 8000000089ab16c389ab16c3724f43ec fe3f9152447945a616987815b25dc88c fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintxne.f32.f32 s7, s16 de7066504c1b108baa5dfb3d63d94b75 3120bf064429f8ae728ae9ae1d2ad431 000000004c1b108baa5dfb3d63d94b75 3120bf064429f8ae728ae9ae1d2ad431 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintxne.f32.f32 s7, s16 db515eade4d0a3802867dfcf8e851dff 303d0e13167cb409a79de211279e327b 00000000e4d0a3802867dfcf8e851dff 303d0e13167cb409a79de211279e327b fpscr=00000000
+vrintxne.f32.f32 s7, s16 f638d88000e52b6b0e1114640ef98b57 4b5a5c9abc774ca0ceabf86c730f16cd 730f16cd00e52b6b0e1114640ef98b57 4b5a5c9abc774ca0ceabf86c730f16cd fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintxne.f32.f32 s7, s16 70b64df6efa75b63b6e97c0925bd2c58 4725157541d7f7f0d06c5d0bb8f6a660 80000000efa75b63b6e97c0925bd2c58 4725157541d7f7f0d06c5d0bb8f6a660 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintxne.f32.f32 s7, s16 af4dfe79cd8e80f4691d698e7d2f9ea1 adcbb98edd92cb2c91cbefcce31de50c e31de50ccd8e80f4691d698e7d2f9ea1 adcbb98edd92cb2c91cbefcce31de50c fpscr=00000000
+vrintxne.f32.f32 s7, s16 1b80ff5c37fd6aeea3d0940b203101c3 846ccc42281304bf7bd59c727d3a6555 7d3a655537fd6aeea3d0940b203101c3 846ccc42281304bf7bd59c727d3a6555 fpscr=00000000
+vrintxne.f32.f32 s7, s16 2feef3f0a22d7794cc4c1dfac50c95fd a0f48a78dd9da4c3dfaf7d63419118c5 41900000a22d7794cc4c1dfac50c95fd a0f48a78dd9da4c3dfaf7d63419118c5 fpscr=00000000
+vrintxne.f32.f32 s7, s16 a2b069e8ea8e8503424a65edadc6a8d2 e89cb42df72c47d9a5dec4f1d00d7997 d00d7997ea8e8503424a65edadc6a8d2 e89cb42df72c47d9a5dec4f1d00d7997 fpscr=00000000
+vrintx.f32.f32 s8, s8 0e563b57e8c440614da5ea4edb38a9c8 64448f57e46aee13b384d2c73d108dad 64448f57e46aee13b384d2c700000000 64448f57e46aee13b384d2c700000000 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vrintx.f32.f32 s8, s8 135ed7dd92772e6743b52888135ed7dd dd4334daa539341376929c45dd4334da dd4334daa539341376929c45dd4334da dd4334daa539341376929c45dd4334da fpscr=00000000
+vrintx.f32.f32 s8, s8 0de09cdb0fd3c65bc7974fba793952fa 330c5eaf9acbe865d2485fa876be59b5 330c5eaf9acbe865d2485fa876be59b5 330c5eaf9acbe865d2485fa876be59b5 fpscr=00000000
+vrintx.f32.f32 s8, s8 23959fbea2580007020997a00c99f550 5f0670cb008f399896b9f1d413ccba7c 5f0670cb008f399896b9f1d400000000 5f0670cb008f399896b9f1d400000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 b91696cf248c31e8e3a44d18958d7436 dcbdb6ce3f184c7a40b7c1a390bfa007 dcbdb6ce3f184c7a40b7c1a380000000 dcbdb6ce3f184c7a40b7c1a380000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 bb55deaaefd1d6a59f9e4b4db224646f 1335e980dd60f13bc81d9b69536356b0 1335e980dd60f13bc81d9b69536356b0 1335e980dd60f13bc81d9b69536356b0 fpscr=00000000
+vrintx.f32.f32 s8, s8 75579efb8e7139c14e4d1c6d7529cd4e 2649292b0589b50f1c24c4e55bf5bd78 2649292b0589b50f1c24c4e55bf5bd78 2649292b0589b50f1c24c4e55bf5bd78 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintx.f32.f32 s8, s8 7f108773cb244e2d1853f8dfb5ea4886 cf1a62dd046cf08f2e0ba0b9fbe98fad cf1a62dd046cf08f2e0ba0b9fbe98fad cf1a62dd046cf08f2e0ba0b9fbe98fad fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintx.f32.f32 s8, s8 60da8eb3741d9df660da8eb3a1dd395c 21781d1b8d5b1383160824f76dabbccd 21781d1b8d5b1383160824f76dabbccd 21781d1b8d5b1383160824f76dabbccd fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: 10240 calls, 10568 iters
+vrintx.f32.f32 s8, s8 e8ecc49e1e51e218f590180c2dcf2561 0f7fc9d5417f73e7a1cdc5429ee03089 0f7fc9d5417f73e7a1cdc54280000000 0f7fc9d5417f73e7a1cdc54280000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 f6c883e7726101e156a76dd72015fc84 d69813577c5d20caf690cdcd5f270dd7 d69813577c5d20caf690cdcd5f270dd7 d69813577c5d20caf690cdcd5f270dd7 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintx.f32.f32 s8, s8 bc315b5980f3d0a794add7fa61646bfb b6080a4fc33b0d3b367f76ca1ffd2742 b6080a4fc33b0d3b367f76ca00000000 b6080a4fc33b0d3b367f76ca00000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 716e60a4fcafbe7b846c37fbc17fa9d2 de38d1f48580e70adcb0495c38cb8121 de38d1f48580e70adcb0495c00000000 de38d1f48580e70adcb0495c00000000 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintx.f32.f32 s8, s8 2aceeb52136a6ae66cc4216b5f1e4cae 3b209bed3b209bedbd108ef21024989b 3b209bed3b209bedbd108ef200000000 3b209bed3b209bedbd108ef200000000 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[2]
+vrintx.f32.f32 s8, s8 18b34357ea3d3655777445c9c9442fc6 db315bfbdb315bfbbf5576028486e92a db315bfbdb315bfbbf55760280000000 db315bfbdb315bfbbf55760280000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 d769b3362269ae4d5d24efe42a8cd075 9c30bd68e45028f6f878069a1b48fb9b 9c30bd68e45028f6f878069a00000000 9c30bd68e45028f6f878069a00000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 70485f6c57d8a89520779159f046485f 15105a9d4913a806f17f5a8aa4b8b9d2 15105a9d4913a806f17f5a8a80000000 15105a9d4913a806f17f5a8a80000000 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintx.f32.f32 s8, s8 ebffcb7ee8d6973d9ad2e6630f83e61e eb9535e875b7ab422dc8228f1afada22 eb9535e875b7ab422dc8228f00000000 eb9535e875b7ab422dc8228f00000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 237a2017dedfd4f562b780e647acc7ff 3fdf4d983ce467da61fe28167637e67e 3fdf4d983ce467da61fe28167637e67e 3fdf4d983ce467da61fe28167637e67e fpscr=00000000
+vrintx.f32.f32 s8, s8 dd5595f621f252f11e93d279f86c9756 2813c432bcef3e2bf9cc744c946a0f8c 2813c432bcef3e2bf9cc744c80000000 2813c432bcef3e2bf9cc744c80000000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintx.f32.f32 s8, s8 8d0a79f5925a6e11ea62ef484381456c 85b76e3a6e3411ca2a71f44c2a71f44c 85b76e3a6e3411ca2a71f44c00000000 85b76e3a6e3411ca2a71f44c00000000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintx.f32.f32 s8, s8 9c40d510bdb032c53d6bb9d53d6bb9d5 e4e42550dbf46596cfa85d61224d6cf3 e4e42550dbf46596cfa85d6100000000 e4e42550dbf46596cfa85d6100000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 b1f77c0baf9607066cb17a6a6fc97416 6e4732aac3077531b53bd5a3524bb01e 6e4732aac3077531b53bd5a3524bb01e 6e4732aac3077531b53bd5a3524bb01e fpscr=00000000
+vrintx.f32.f32 s8, s8 a34ca09943ed3423c98d6b4f46a25b3a 6096b5cf743c966d6a0a6a228a1c4d6c 6096b5cf743c966d6a0a6a2280000000 6096b5cf743c966d6a0a6a2280000000 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintx.f32.f32 s8, s8 f7ac505e0f13483364307cec4bd229fb 4c6a4bc113cf096fd118fe5713cf096f 4c6a4bc113cf096fd118fe5700000000 4c6a4bc113cf096fd118fe5700000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 c99331c7baa42cd4b0a8f0e3758c739e 6ba67fb556ff906d17de8b549fac6439 6ba67fb556ff906d17de8b5480000000 6ba67fb556ff906d17de8b5480000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 e70f015b22d516ee20a91ca3eb9fa59d d8c4b16a7f387680b140e783436fa785 d8c4b16a7f387680b140e78343700000 d8c4b16a7f387680b140e78343700000 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintx.f32.f32 s8, s8 bff18e8515639bd1efa9ae846b2b310b 88a3f3228f9667ed47acacd78f9667ed 88a3f3228f9667ed47acacd780000000 88a3f3228f9667ed47acacd780000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 d4048bb3baab93b840ec2a6a4634a991 9be209475700e25ad085c7391a0bc080 9be209475700e25ad085c73900000000 9be209475700e25ad085c73900000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 7f1133b40b8508381d21c111762bc625 db03f55b9d75f6e8bfb2fd26fa9ba28b db03f55b9d75f6e8bfb2fd26fa9ba28b db03f55b9d75f6e8bfb2fd26fa9ba28b fpscr=00000000
+vrintx.f32.f32 s8, s8 97477cf355225f2680b489055ac9c58f 761c96c104607aaa83e70fccf3189dc6 761c96c104607aaa83e70fccf3189dc6 761c96c104607aaa83e70fccf3189dc6 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[3]
+vrintx.f32.f32 s8, s8 4c7c211733052bcc7d862a4bdacf6c10 2b2ec3f793fc4103cf88a9502b2ec3f7 2b2ec3f793fc4103cf88a95000000000 2b2ec3f793fc4103cf88a95000000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 1a9b5be32f9040ee43bb2ff918a4513b 51bf466ff8d165c9b5a246c83fe86854 51bf466ff8d165c9b5a246c840000000 51bf466ff8d165c9b5a246c840000000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[3]
+vrintx.f32.f32 s8, s8 0d5406e8e7c9b9870d5406e8950fa175 5f86c0d9c5680f1d9b1a2ec12ed364ce 5f86c0d9c5680f1d9b1a2ec100000000 5f86c0d9c5680f1d9b1a2ec100000000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintx.f32.f32 s8, s8 60fb52ce6b64f09946b7f0a44ab881f6 074ddae4d8a307d2cdea05bcb649c9a9 074ddae4d8a307d2cdea05bc80000000 074ddae4d8a307d2cdea05bc80000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 20a62231fa618f2b26565b283f3873f1 ddf43ee27b11b91342086d2ab55e49a6 ddf43ee27b11b91342086d2a80000000 ddf43ee27b11b91342086d2a80000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 0893ef34753d8932ee1e2d1f2f597c38 5b8493494f60678f7199a5010659561a 5b8493494f60678f7199a50100000000 5b8493494f60678f7199a50100000000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintx.f32.f32 s8, s8 b7f455a0b10ba3e29bdd5e2c651d1c36 6dd9e9d694f7eeec889570e3791b2cf6 6dd9e9d694f7eeec889570e3791b2cf6 6dd9e9d694f7eeec889570e3791b2cf6 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[1]
+vrintx.f32.f32 s8, s8 74babcf279add41f02a7ba9e3912a41f 72b65f56e9673a02addae8470ac22f92 72b65f56e9673a02addae84700000000 72b65f56e9673a02addae84700000000 fpscr=00000000
+vrintx.f32.f32 s8, s8 cc00a032fb1ec3b71cd0dba4fc3c9189 27fd8b281a2932e129bd7a5ad81277d9 27fd8b281a2932e129bd7a5ad81277d9 27fd8b281a2932e129bd7a5ad81277d9 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintx.f32.f32 s8, s8 4c4e5e9ff7c70b29d12edce56a9fab8e 11e4e72e9e324e3743cab14a43cab14a 11e4e72e9e324e3743cab14a43ca8000 11e4e72e9e324e3743cab14a43ca8000 fpscr=00000000
+vrintx.f32.f32 s8, s8 2264bc6aa5b4e3cfd64d6161fa2da99c f5a584d89a41d07661cedf5f7cc351a5 f5a584d89a41d07661cedf5f7cc351a5 f5a584d89a41d07661cedf5f7cc351a5 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintx.f32.f32 s8, s8 aca39a70497026110cd6b95920cdeb2f a7b58b5aa3ab56240f8bff7efcb84b64 a7b58b5aa3ab56240f8bff7efcb84b64 a7b58b5aa3ab56240f8bff7efcb84b64 fpscr=00000000
+vrintx.f32.f32 s8, s8 44bcceffdc19ce42219ad199896f9e9a e8df53fea9b7cb76dae035e5f28a9e57 e8df53fea9b7cb76dae035e5f28a9e57 e8df53fea9b7cb76dae035e5f28a9e57 fpscr=00000000
+vrintx.f32.f32 s8, s8 cc478bbd1701ea2f6f17ee22764a1494 418e24d15372fd2b0c7b11846ccde729 418e24d15372fd2b0c7b11846ccde729 418e24d15372fd2b0c7b11846ccde729 fpscr=00000000
+vrintx.f32.f32 s8, s8 eb1d63b400fe25127f3cbfef1956f94d ed5ccaa816c1cdd04d523509d78daff5 ed5ccaa816c1cdd04d523509d78daff5 ed5ccaa816c1cdd04d523509d78daff5 fpscr=00000000
+vrintx.f32.f32 s8, s8 cd08a8d8183571cf062106fd5acf2ca0 814a029c1bc03aa660fefb8e355d5d78 814a029c1bc03aa660fefb8e00000000 814a029c1bc03aa660fefb8e00000000 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintx.f32.f32 s8, s8 74d457271b797f71369235e7be120edf ba66a2e9ee7e89a604cd86527e260eea ba66a2e9ee7e89a604cd86527e260eea ba66a2e9ee7e89a604cd86527e260eea fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintx.f32.f32 s8, s8 8ad01767c65077fb58cd239158cd2391 d2adec2706a92f1da2f773c9bcd8a12b d2adec2706a92f1da2f773c980000000 d2adec2706a92f1da2f773c980000000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintx.f32.f32 s8, s8 38aa0b855d3030b7b26500434631e999 5518fa1e65b6d52259f1c63af00cecd2 5518fa1e65b6d52259f1c63af00cecd2 5518fa1e65b6d52259f1c63af00cecd2 fpscr=00000000
+vrintn.f64.f64 d3, d15 0e04846ce3f87e0526dea14e2292d769 eae42dc4f1d1b27ab8322bbf516379fc eae42dc4f1d1b27a26dea14e2292d769 eae42dc4f1d1b27ab8322bbf516379fc fpscr=00000000
+vrintn.f64.f64 d3, d15 c8c4a8ab793e4154de278a125c700dc8 6537073aaa3f48a5b1a168da40da83a8 6537073aaa3f48a5de278a125c700dc8 6537073aaa3f48a5b1a168da40da83a8 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 f4ce5182329cd6ba5bff2103a1363c30 83591b83dbde090c5f8a4261d131d618 80000000000000005bff2103a1363c30 83591b83dbde090c5f8a4261d131d618 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 d9b0635d142b626a99f98160660693a6 c4e79d61d07769a3c4e79d61d07769a3 c4e79d61d07769a399f98160660693a6 c4e79d61d07769a3c4e79d61d07769a3 fpscr=00000000
+vrintn.f64.f64 d3, d15 eb5c5e76820ba1bb5d296b50eeaf155c b77c971b12dcecbf247f7dc593cd3746 80000000000000005d296b50eeaf155c b77c971b12dcecbf247f7dc593cd3746 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 4fd4ccac462a419435837e2a9cfec324 fcbada6cbea7cd8b01c8863efcd8868b fcbada6cbea7cd8b35837e2a9cfec324 fcbada6cbea7cd8b01c8863efcd8868b fpscr=00000000
+vrintn.f64.f64 d3, d15 328fa31d3820e5e88b7136ba8e7be067 20a9cb6d982be2680bd4ae9fdcdf1264 00000000000000008b7136ba8e7be067 20a9cb6d982be2680bd4ae9fdcdf1264 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintn.f64.f64 d3, d15 f5a590267b3fbfa1ab586fd363a69c6c 4f4554dc9983c9614f4554dc9983c961 4f4554dc9983c961ab586fd363a69c6c 4f4554dc9983c9614f4554dc9983c961 fpscr=00000000
+vrintn.f64.f64 d3, d15 2b5aa71bb8c77a06ae1b2ceaf96c0d73 d70778b11b70abbb66d239076d891bbf d70778b11b70abbbae1b2ceaf96c0d73 d70778b11b70abbb66d239076d891bbf fpscr=00000000
+vrintn.f64.f64 d3, d15 9c22663439abf9baf3b01ce2ead418d2 51331a8a5020ec3085fb3d1c8f59b939 51331a8a5020ec30f3b01ce2ead418d2 51331a8a5020ec3085fb3d1c8f59b939 fpscr=00000000
+vrintn.f64.f64 d3, d15 bc3454a89b3e3832268b96e9df020c17 5073e659e229c1a9079046b3162e1002 5073e659e229c1a9268b96e9df020c17 5073e659e229c1a9079046b3162e1002 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintn.f64.f64 d3, d15 ea834f94d90836cf68cd13b7d1595f07 0dc642b03f2a49a087e3b50a5c36e71a 000000000000000068cd13b7d1595f07 0dc642b03f2a49a087e3b50a5c36e71a fpscr=00000000
+vrintn.f64.f64 d3, d15 8dadf42e452f0ff6e1319297c0d1e231 4139a9938f6906605c3777f4bd489f43 4139a99400000000e1319297c0d1e231 4139a9938f6906605c3777f4bd489f43 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintn.f64.f64 d3, d15 2f8a2801115da87b14767cca9960c540 2d15a13638011e502d15a13638011e50 000000000000000014767cca9960c540 2d15a13638011e502d15a13638011e50 fpscr=00000000
+vrintn.f64.f64 d3, d15 3bf6379a3e44415d36a8711a78c9332f 3d0879a41e5ea77212d72b5473e3695c 000000000000000036a8711a78c9332f 3d0879a41e5ea77212d72b5473e3695c fpscr=00000000
+vrintn.f64.f64 d3, d15 bfe9961cddad347e7e9883493d5a00ff 4d83e1111f85d7bc2749650c8151e1ae 4d83e1111f85d7bc7e9883493d5a00ff 4d83e1111f85d7bc2749650c8151e1ae fpscr=00000000
+vrintn.f64.f64 d3, d15 6222263674ffe01d7c6412babcb659c7 ebb10b10b8f24b69d6b5cdac606a04b1 ebb10b10b8f24b697c6412babcb659c7 ebb10b10b8f24b69d6b5cdac606a04b1 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 a0e5427fec4f9a7ee40a19fdf67ab0ae 6153c228c479b9566153c228c479b956 6153c228c479b956e40a19fdf67ab0ae 6153c228c479b9566153c228c479b956 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintn.f64.f64 d3, d15 dfc9f6fc42a586a72e49b2fd99e3cd66 620c62655d9da852620c62655d9da852 620c62655d9da8522e49b2fd99e3cd66 620c62655d9da852620c62655d9da852 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 8808961da7da7b1b10297be66b595bc4 44aebafd2fe6adc944aebafd2fe6adc9 44aebafd2fe6adc910297be66b595bc4 44aebafd2fe6adc944aebafd2fe6adc9 fpscr=00000000
+vrintn.f64.f64 d3, d15 ebea4407091c281fdcabb0a61930faf9 9dfc2379f702cc97bc2af5ae43a64180 8000000000000000dcabb0a61930faf9 9dfc2379f702cc97bc2af5ae43a64180 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 8bb8b986453a4c06a9e894465221864b cfc4338966880c1acfc4338966880c1a cfc4338966880c1aa9e894465221864b cfc4338966880c1acfc4338966880c1a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintn.f64.f64 d3, d15 df17ee436de9aa093ab5ec7ede0a8723 77ded03987b40cc077ded03987b40cc0 77ded03987b40cc03ab5ec7ede0a8723 77ded03987b40cc077ded03987b40cc0 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: 10496 calls, 10828 iters
+vrintn.f64.f64 d3, d15 d5637ddb7f364db378303efb8617e594 9e4cc5f1f1c5ad44ecdb019e0661f5ac 800000000000000078303efb8617e594 9e4cc5f1f1c5ad44ecdb019e0661f5ac fpscr=00000000
+vrintn.f64.f64 d3, d15 b592c43eed070cd1fb77dc5c5b86d38d db68e8a3c26819ca1514ccccdc84e374 db68e8a3c26819cafb77dc5c5b86d38d db68e8a3c26819ca1514ccccdc84e374 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 dc6f72cf4ae28a8d35a3bea7c03e20ca c7a12e5692bf672d7ec426fc36351f85 c7a12e5692bf672d35a3bea7c03e20ca c7a12e5692bf672d7ec426fc36351f85 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vrintn.f64.f64 d3, d15 f534d9628d1dfa5fafaf20fe7b52d155 6b95cb3a406a9e2f6b95cb3a406a9e2f 6b95cb3a406a9e2fafaf20fe7b52d155 6b95cb3a406a9e2f6b95cb3a406a9e2f fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintn.f64.f64 d3, d15 538668456916742c8777a16b1a962544 b512d910383a7e3eb512d910383a7e3e 80000000000000008777a16b1a962544 b512d910383a7e3eb512d910383a7e3e fpscr=00000000
+vrintn.f64.f64 d3, d15 1dfd67967041fc4f9ea8e57e2e068df6 b695dca03bde2c0ccfa33e34d256b47a 80000000000000009ea8e57e2e068df6 b695dca03bde2c0ccfa33e34d256b47a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 a962d8b4c79ac47de6248cbcaf97aa62 726495fb79f99d48af9a3b48296bd6ca 726495fb79f99d48e6248cbcaf97aa62 726495fb79f99d48af9a3b48296bd6ca fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 8df1a313b0ccf92d3ff4c48eb4615233 062a435b12b0e7e2cb06c38864059535 00000000000000003ff4c48eb4615233 062a435b12b0e7e2cb06c38864059535 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 43bff6e353c2894eef2972a8a60a4335 404a44f6cfc54bf6404a44f6cfc54bf6 404a800000000000ef2972a8a60a4335 404a44f6cfc54bf6404a44f6cfc54bf6 fpscr=00000000
+vrintn.f64.f64 d3, d15 59ba94f10c0c629101330d3773c4a9f9 f13ada049adfab01aea537649b03a659 f13ada049adfab0101330d3773c4a9f9 f13ada049adfab01aea537649b03a659 fpscr=00000000
+vrintn.f64.f64 d3, d15 f818b7d8e4b27dbb8424c517083695d2 84cfd9566b3679c257677214dd7269cf 80000000000000008424c517083695d2 84cfd9566b3679c257677214dd7269cf fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 74657f799c76c52cf799df87bf0dcc32 4eadb235dd3585cf2d933e118f0ac162 4eadb235dd3585cff799df87bf0dcc32 4eadb235dd3585cf2d933e118f0ac162 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintn.f64.f64 d3, d15 522226784cc1090b522226784cc1090b 5b36fb47d94639ba8c6fc5e20d02b4ef 5b36fb47d94639ba522226784cc1090b 5b36fb47d94639ba8c6fc5e20d02b4ef fpscr=00000000
+vrintn.f64.f64 d3, d15 9548160eedbae4f01d773136943b2ed3 07f6c79cece388fd616bbdbd0ffe9bad 00000000000000001d773136943b2ed3 07f6c79cece388fd616bbdbd0ffe9bad fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintn.f64.f64 d3, d15 b812f5724f20a5ebab3127d94f9e72d8 30afcf12355182c45fe8147b7b2220b3 0000000000000000ab3127d94f9e72d8 30afcf12355182c45fe8147b7b2220b3 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 891a4b92a57d2309891a4b92a57d2309 aa055169649f13e5de9fa4cf2ccee63b 8000000000000000891a4b92a57d2309 aa055169649f13e5de9fa4cf2ccee63b fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintn.f64.f64 d3, d15 037ac39d841f8e128b5a0c533e45cfed 22fe7db8a7f8daf402c2178bc8dd4ef9 00000000000000008b5a0c533e45cfed 22fe7db8a7f8daf402c2178bc8dd4ef9 fpscr=00000000
+vrintn.f64.f64 d3, d15 4885a1b8de641fa954d3cdeb6c53ef1d 36ee8e49dec27cce35a569f92646a309 000000000000000054d3cdeb6c53ef1d 36ee8e49dec27cce35a569f92646a309 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 aabfc54091dc28c2aabfc54091dc28c2 a0694e4ce13b69d1e5ca1782d75e4eef 8000000000000000aabfc54091dc28c2 a0694e4ce13b69d1e5ca1782d75e4eef fpscr=00000000
+vrintn.f64.f64 d3, d15 c6cebe7736a635488242cc7353951fbf db85cb91a381452af8276ed470b0bc25 db85cb91a381452a8242cc7353951fbf db85cb91a381452af8276ed470b0bc25 fpscr=00000000
+vrintn.f64.f64 d3, d15 da2d8926e414f159f16694e5a78c8ab3 10904397079c1aaf469a352779c5a6d7 0000000000000000f16694e5a78c8ab3 10904397079c1aaf469a352779c5a6d7 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintn.f64.f64 d3, d15 f770ba9f29cb8fd9998167a396a7ba34 bbc676d8bda3b288c9c2e7cae9937d21 8000000000000000998167a396a7ba34 bbc676d8bda3b288c9c2e7cae9937d21 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 3480d693c0eb4e7df9359b2c5d047df5 ec52433dad0385db1b90c8b3665e55b3 ec52433dad0385dbf9359b2c5d047df5 ec52433dad0385db1b90c8b3665e55b3 fpscr=00000000
+vrintn.f64.f64 d3, d15 6a013b39a11f798cb97c73aca9968f32 02e3af0229bfbdc1d41ffeb7b539e178 0000000000000000b97c73aca9968f32 02e3af0229bfbdc1d41ffeb7b539e178 fpscr=00000000
+vrintn.f64.f64 d3, d15 11f73625cba650c84bdc394e4c05c18d c7fa0a9e80db4e19c2938ae2322845bf c7fa0a9e80db4e194bdc394e4c05c18d c7fa0a9e80db4e19c2938ae2322845bf fpscr=00000000
+vrintn.f64.f64 d3, d15 38e2fb9c41beab35b8b57e63921d5225 cad298ff52421191af405932e3d3265d cad298ff52421191b8b57e63921d5225 cad298ff52421191af405932e3d3265d fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vrintn.f64.f64 d3, d15 ddee26f549b33295ddee26f549b33295 3632c0d88ab4d8973632c0d88ab4d897 0000000000000000ddee26f549b33295 3632c0d88ab4d8973632c0d88ab4d897 fpscr=00000000
+vrinta.f64.f64 d6, d18 750df7e73f1592950d5f0978b2ff1b20 90c97f9f3d4de279ea37dd74eff68b2b 750df7e73f159295ea37dd74eff68b2b 90c97f9f3d4de279ea37dd74eff68b2b fpscr=00000000
+vrinta.f64.f64 d6, d18 15774aa77a78bbbb98ac6a3a04d02db0 b9d7061609e6002aa6612a564c63d3f5 15774aa77a78bbbb8000000000000000 b9d7061609e6002aa6612a564c63d3f5 fpscr=00000000
+vrinta.f64.f64 d6, d18 e3ce029b10daf0e146ad5f36033edbe7 6633c644b4b911345f63416ded9fe625 e3ce029b10daf0e15f63416ded9fe625 6633c644b4b911345f63416ded9fe625 fpscr=00000000
+vrinta.f64.f64 d6, d18 67f4472f16aefb1449947d1e398a4437 4f95a9ca82f21a8048f1ec91709f24c8 67f4472f16aefb1448f1ec91709f24c8 4f95a9ca82f21a8048f1ec91709f24c8 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vrinta.f64.f64 d6, d18 fb879d9518351b70fb879d9518351b70 e241d75c2be056dde241d75c2be056dd fb879d9518351b70e241d75c2be056dd e241d75c2be056dde241d75c2be056dd fpscr=00000000
+vrinta.f64.f64 d6, d18 dc43bfdf6ba52443d2d9c4bfdf8d8646 af91c79efb49100a6cdc35fbad7baef1 dc43bfdf6ba524436cdc35fbad7baef1 af91c79efb49100a6cdc35fbad7baef1 fpscr=00000000
+vrinta.f64.f64 d6, d18 7e5b78958df49918c8d4d0a7b3048d61 ad9d77db769f61e37c65852001b73a44 7e5b78958df499187c65852001b73a44 ad9d77db769f61e37c65852001b73a44 fpscr=00000000
+vrinta.f64.f64 d6, d18 f594a96670d015f815bde3c7464da7e3 984048e84af8a8d5e91d0b71acbabcb9 f594a96670d015f8e91d0b71acbabcb9 984048e84af8a8d5e91d0b71acbabcb9 fpscr=00000000
+vrinta.f64.f64 d6, d18 a99634bbf7238a1daeeb282ed57ffecc 35542a5bfc919f2f51b9f99de769a6a6 a99634bbf7238a1d51b9f99de769a6a6 35542a5bfc919f2f51b9f99de769a6a6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrinta.f64.f64 d6, d18 e512e49492f3f1a01cc748e69a8e1219 b7af8e0e5eca1320b7af8e0e5eca1320 e512e49492f3f1a08000000000000000 b7af8e0e5eca1320b7af8e0e5eca1320 fpscr=00000000
+vrinta.f64.f64 d6, d18 3b1ceb761808f12f8b0dd4b350b4c45f dd04a0b39844945e32760eb1d6dfbbc6 3b1ceb761808f12f0000000000000000 dd04a0b39844945e32760eb1d6dfbbc6 fpscr=00000000
+vrinta.f64.f64 d6, d18 f9d66a72c0a11c628beaecddfab4cfb5 66d27749292de9f5c0ca54935f7e236a f9d66a72c0a11c62c0ca548000000000 66d27749292de9f5c0ca54935f7e236a fpscr=00000000
+vrinta.f64.f64 d6, d18 867e546ecd9ae93c190f33ee4cd836fc 0b1a6e35d1cc971e1a025533fef6d8b0 867e546ecd9ae93c0000000000000000 0b1a6e35d1cc971e1a025533fef6d8b0 fpscr=00000000
+vrinta.f64.f64 d6, d18 280015d4ef00cf02bbe5a394a6478ef9 e3e3decc97425ca42f38f7c690e3c3cf 280015d4ef00cf020000000000000000 e3e3decc97425ca42f38f7c690e3c3cf fpscr=00000000
+vrinta.f64.f64 d6, d18 3112293fc1ac21dc18873bf12498f958 d99fa00cb06dfd414402871c5f7677a2 3112293fc1ac21dc4402871c5f7677a2 d99fa00cb06dfd414402871c5f7677a2 fpscr=00000000
+vrinta.f64.f64 d6, d18 e7f7108a4b24a00220bb34ec62f3f91b 1c88510e05f3a4b9ac143955f2bad1fd e7f7108a4b24a0028000000000000000 1c88510e05f3a4b9ac143955f2bad1fd fpscr=00000000
+vrinta.f64.f64 d6, d18 cb18a8b9ea5773ce92d7945ca60fafe6 706e70e1a2a71c4d4d4c83fcb73a7169 cb18a8b9ea5773ce4d4c83fcb73a7169 706e70e1a2a71c4d4d4c83fcb73a7169 fpscr=00000000
+vrinta.f64.f64 d6, d18 58d855ba0a4def8e13105f7692091c34 8a3c436677f66cc9739923148193917d 58d855ba0a4def8e739923148193917d 8a3c436677f66cc9739923148193917d fpscr=00000000
+vrinta.f64.f64 d6, d18 288b19915fc2679b3e1c65dd4f23f9eb e02f432766a0a9276dab9e5fb9321838 288b19915fc2679b6dab9e5fb9321838 e02f432766a0a9276dab9e5fb9321838 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrinta.f64.f64 d6, d18 8da1cc34ea3bb02d8da1cc34ea3bb02d 2364d62c9400a250bae0bf6428a35df4 8da1cc34ea3bb02d8000000000000000 2364d62c9400a250bae0bf6428a35df4 fpscr=00000000
+vrinta.f64.f64 d6, d18 24c0ada747db94f2ae892e1f4fd346fd d295a14b420ac25c1aebe35acf1e6f6b 24c0ada747db94f20000000000000000 d295a14b420ac25c1aebe35acf1e6f6b fpscr=00000000
+vrinta.f64.f64 d6, d18 cab41cdb053132abefa6f4a451c5c130 b76edd5197d8ed9509d86e9292319fcc cab41cdb053132ab0000000000000000 b76edd5197d8ed9509d86e9292319fcc fpscr=00000000
+vrinta.f64.f64 d6, d18 b235862cc2ed578c2411631ea7b90190 d98782f24134dbf279d2ff44d8b03bae b235862cc2ed578c79d2ff44d8b03bae d98782f24134dbf279d2ff44d8b03bae fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrinta.f64.f64 d6, d18 e77afca362bf1f61e77afca362bf1f61 3198ee95c0054f1598d1bf1f0434d863 e77afca362bf1f618000000000000000 3198ee95c0054f1598d1bf1f0434d863 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrinta.f64.f64 d6, d18 0f047614a80adc6ccc99ee15a16f8f10 00f8d144d1160cd100f8d144d1160cd1 0f047614a80adc6c0000000000000000 00f8d144d1160cd100f8d144d1160cd1 fpscr=00000000
+vrinta.f64.f64 d6, d18 ee5a5fa305b7b4292cd633852ed35e39 5cc5b15a81fc67168fd7bb547c818f33 ee5a5fa305b7b4298000000000000000 5cc5b15a81fc67168fd7bb547c818f33 fpscr=00000000
+vrinta.f64.f64 d6, d18 8b7446c0c14e811ee074a53a271c7c80 327510060806de7814a6bb00a1dc2bad 8b7446c0c14e811e0000000000000000 327510060806de7814a6bb00a1dc2bad fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vrinta.f64.f64 d6, d18 843063c7c260af78ac9a544e1dbd0063 c7d3e1500826085ca0f55b1d95ca11ad 843063c7c260af788000000000000000 c7d3e1500826085ca0f55b1d95ca11ad fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrinta.f64.f64 d6, d18 df74b7887d60c004f40aabe3c84b7c16 67a5a9a2095c29b167a5a9a2095c29b1 df74b7887d60c00467a5a9a2095c29b1 67a5a9a2095c29b167a5a9a2095c29b1 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrinta.f64.f64 d6, d18 53ac2ce014009b71e6531492daf69314 c2424536450d84b5e44a178238a95a76 53ac2ce014009b71e44a178238a95a76 c2424536450d84b5e44a178238a95a76 fpscr=00000000
+vrinta.f64.f64 d6, d18 8f09742261564433fb7199f3bf12485f 2c2a2d8147bfb84be2cd6a4e28de42e3 8f09742261564433e2cd6a4e28de42e3 2c2a2d8147bfb84be2cd6a4e28de42e3 fpscr=00000000
+vrinta.f64.f64 d6, d18 fa60ce40285c1b60d30cfc83aca730e1 ec2438193f2d640f2faa89b43f1c6db8 fa60ce40285c1b600000000000000000 ec2438193f2d640f2faa89b43f1c6db8 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrinta.f64.f64 d6, d18 842eabaa671d6dbcad1100f62bc5db7c 2ff534f2e5d316dc2ff534f2e5d316dc 842eabaa671d6dbc0000000000000000 2ff534f2e5d316dc2ff534f2e5d316dc fpscr=00000000
+vrinta.f64.f64 d6, d18 8b4a9a3f24bd648d8847885b20fd7f08 c2bd1382ac26e9e004eb6ba1a01bdce0 8b4a9a3f24bd648d0000000000000000 c2bd1382ac26e9e004eb6ba1a01bdce0 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vrinta.f64.f64 d6, d18 eb9d1c6aaef7baf8eb9d1c6aaef7baf8 2c68d1c24a0bc0dfb61e834c7cb563b2 eb9d1c6aaef7baf88000000000000000 2c68d1c24a0bc0dfb61e834c7cb563b2 fpscr=00000000
+vrinta.f64.f64 d6, d18 e9489b583b15c86949eda5015da284e5 ce165dc84b43fdcb6209ebdf2f8f4071 e9489b583b15c8696209ebdf2f8f4071 ce165dc84b43fdcb6209ebdf2f8f4071 fpscr=00000000
+vrinta.f64.f64 d6, d18 2c90da4d5e2df1c3e6eaeba162113ef9 448080adbd80236236c590af83b3e1d0 2c90da4d5e2df1c30000000000000000 448080adbd80236236c590af83b3e1d0 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: 10752 calls, 11089 iters
+vrinta.f64.f64 d6, d18 200b3ee41788b9ff200b3ee41788b9ff cab65110b3360f2687edac4137b8daa3 200b3ee41788b9ff8000000000000000 cab65110b3360f2687edac4137b8daa3 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrinta.f64.f64 d6, d18 b14b88e9af066f66b14b88e9af066f66 397a0e48c3c545bbb05796211bae0eae b14b88e9af066f668000000000000000 397a0e48c3c545bbb05796211bae0eae fpscr=00000000
+vrinta.f64.f64 d6, d18 859fcc157ccadb531b60052e1b6bb52c 9e6f35c0ce5b0fb0dfec08d02ee998a3 859fcc157ccadb53dfec08d02ee998a3 9e6f35c0ce5b0fb0dfec08d02ee998a3 fpscr=00000000
+vrinta.f64.f64 d6, d18 b740589f416db4ca02b7dea557814e42 56614e1935ffe6d55df4d30c1a74cad6 b740589f416db4ca5df4d30c1a74cad6 56614e1935ffe6d55df4d30c1a74cad6 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrinta.f64.f64 d6, d18 780c3d4d03311fe45ead402baaa2f99d 2586c4962ff0a01036a6a38670e8acf7 780c3d4d03311fe40000000000000000 2586c4962ff0a01036a6a38670e8acf7 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrinta.f64.f64 d6, d18 1767b1a6b96302afef05ab909caa1814 c7cb3ea69010e8fec7cb3ea69010e8fe 1767b1a6b96302afc7cb3ea69010e8fe c7cb3ea69010e8fec7cb3ea69010e8fe fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrinta.f64.f64 d6, d18 7ec25f5e74b55a05e39129c6fe805680 2c13912baed24b562c13912baed24b56 7ec25f5e74b55a050000000000000000 2c13912baed24b562c13912baed24b56 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrinta.f64.f64 d6, d18 2a67fa4dfbf69f809665e6b7a8735f6d 9c5477320eb264ec1cb3c77d7e39602c 2a67fa4dfbf69f800000000000000000 9c5477320eb264ec1cb3c77d7e39602c fpscr=00000000
+vrinta.f64.f64 d6, d18 54bd7429d4494b8d31745571673fe230 ff12a497f01dccb18c4a8e756eed8e04 54bd7429d4494b8d8000000000000000 ff12a497f01dccb18c4a8e756eed8e04 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrinta.f64.f64 d6, d18 0b9af11cdd5508e5a9139660ec771369 8cf4ffba308c3cf78cf4ffba308c3cf7 0b9af11cdd5508e58000000000000000 8cf4ffba308c3cf78cf4ffba308c3cf7 fpscr=00000000
+vrinta.f64.f64 d6, d18 61558a05f1e2728531a0482857595020 6f42744ba9c4fe297ac26d78c7e53709 61558a05f1e272857ac26d78c7e53709 6f42744ba9c4fe297ac26d78c7e53709 fpscr=00000000
+vrinta.f64.f64 d6, d18 c0f4e64d353b221da7247667dd030516 e77466648aa853c424a219228ac58214 c0f4e64d353b221d0000000000000000 e77466648aa853c424a219228ac58214 fpscr=00000000
+vrinta.f64.f64 d6, d18 7dab2743ac488585d31a25b242a1f0b8 c0fd4ae2aa4b82428930e241133da7a8 7dab2743ac4885858000000000000000 c0fd4ae2aa4b82428930e241133da7a8 fpscr=00000000
+vrintp.f64.f64 d9, d21 f4861b414cc712b6081045099cd0f3a3 551811d4bca9f7417f6a4b5a4a3a0122 551811d4bca9f741081045099cd0f3a3 551811d4bca9f7417f6a4b5a4a3a0122 fpscr=00000000
+vrintp.f64.f64 d9, d21 2790c5cf2898dba691b83322352f87b7 347bdf981631f297d6232f704432a30b 3ff000000000000091b83322352f87b7 347bdf981631f297d6232f704432a30b fpscr=00000000
+vrintp.f64.f64 d9, d21 0268b595566f8c5d37bb4993ad5ced67 702128ae2732c5c7e4ff1c1fefcbd4ce 702128ae2732c5c737bb4993ad5ced67 702128ae2732c5c7e4ff1c1fefcbd4ce fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintp.f64.f64 d9, d21 02c4bc213b7bb9de287dd6e084d0c5e6 cc6baef1bf9af2d7f5e392119fe171cd cc6baef1bf9af2d7287dd6e084d0c5e6 cc6baef1bf9af2d7f5e392119fe171cd fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintp.f64.f64 d9, d21 d27def28d62738cf009e27e098f93bbc 73b8a195f78ec9a95f293d22298896b4 73b8a195f78ec9a9009e27e098f93bbc 73b8a195f78ec9a95f293d22298896b4 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintp.f64.f64 d9, d21 07d5cf96fea0b56507d5cf96fea0b565 42ccc978ecf6d99990ff87d726f69d3f 42ccc978ecf6da0007d5cf96fea0b565 42ccc978ecf6d99990ff87d726f69d3f fpscr=00000000
+vrintp.f64.f64 d9, d21 b025707ddf6b4f0304ec0845e548ce5e 1459f3ae523de656e834a43dd87ca5ee 3ff000000000000004ec0845e548ce5e 1459f3ae523de656e834a43dd87ca5ee fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintp.f64.f64 d9, d21 b7ff45b302eaaa388fe5cdc8a496e39b acd9db0041b689b7acd9db0041b689b7 80000000000000008fe5cdc8a496e39b acd9db0041b689b7acd9db0041b689b7 fpscr=00000000
+vrintp.f64.f64 d9, d21 d4d6dc68663411743b8b4dcd4da6725f c25c064125c24962080c81e839c631ff c25c064125c240003b8b4dcd4da6725f c25c064125c24962080c81e839c631ff fpscr=00000000
+vrintp.f64.f64 d9, d21 041a3426a0bebab3571aedb0cc010d48 7899dd049e0e9723ccd5238f932369ea 7899dd049e0e9723571aedb0cc010d48 7899dd049e0e9723ccd5238f932369ea fpscr=00000000
+vrintp.f64.f64 d9, d21 5aecfdef74111228a29a3cc5d1f87cfe 5f953c99d7bfeb6fe0088c454adf8e37 5f953c99d7bfeb6fa29a3cc5d1f87cfe 5f953c99d7bfeb6fe0088c454adf8e37 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintp.f64.f64 d9, d21 3cc16581c505508d11f0170801ef5d33 0e6126b9a028e1cd72ab0578d974c563 3ff000000000000011f0170801ef5d33 0e6126b9a028e1cd72ab0578d974c563 fpscr=00000000
+vrintp.f64.f64 d9, d21 6f9ecbe5f35ff5a947169140d6e28a94 352b667aeffa4ea7f35d061370ba0280 3ff000000000000047169140d6e28a94 352b667aeffa4ea7f35d061370ba0280 fpscr=00000000
+vrintp.f64.f64 d9, d21 aa7f12ac6c95c6e4e4385ab05d6c1af7 a4eac7c51d1d172fd63faa60563e20e2 8000000000000000e4385ab05d6c1af7 a4eac7c51d1d172fd63faa60563e20e2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintp.f64.f64 d9, d21 6354873d5838e4096354873d5838e409 e4265ff0ad78fc69d11f22261e803e05 e4265ff0ad78fc696354873d5838e409 e4265ff0ad78fc69d11f22261e803e05 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintp.f64.f64 d9, d21 b2bb5d64a7ca9413b2bb5d64a7ca9413 3da1e06407878e2176967638ecca7471 3ff0000000000000b2bb5d64a7ca9413 3da1e06407878e2176967638ecca7471 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintp.f64.f64 d9, d21 c74f476c44ff4c33edeb156e96cb8b4e 4f3f9ab0057fe7f36adc327719d68b8e 4f3f9ab0057fe7f3edeb156e96cb8b4e 4f3f9ab0057fe7f36adc327719d68b8e fpscr=00000000
+vrintp.f64.f64 d9, d21 350a700285d54720599f95c004a91477 5866a9a414fa9a3f23d9f883cd0f18bf 5866a9a414fa9a3f599f95c004a91477 5866a9a414fa9a3f23d9f883cd0f18bf fpscr=00000000
+vrintp.f64.f64 d9, d21 7d00daefbd8636b44babaebb7875f40c 604107f6d36cf90f90caeb8c10bee89b 604107f6d36cf90f4babaebb7875f40c 604107f6d36cf90f90caeb8c10bee89b fpscr=00000000
+vrintp.f64.f64 d9, d21 e7d57f9173c456e48ba709f61c176912 ad33dcabe5080c7601ef0017aeed7da4 80000000000000008ba709f61c176912 ad33dcabe5080c7601ef0017aeed7da4 fpscr=00000000
+vrintp.f64.f64 d9, d21 0281fc3d94cf6485608e7621a22702c9 0812d96741fd6014e03e6f520fb3407d 3ff0000000000000608e7621a22702c9 0812d96741fd6014e03e6f520fb3407d fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintp.f64.f64 d9, d21 98182044eb5774f1a7342c3724bf1a05 74a65f09691b1bdaa1232897b0c3906a 74a65f09691b1bdaa7342c3724bf1a05 74a65f09691b1bdaa1232897b0c3906a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintp.f64.f64 d9, d21 14b577d09d477ee9e17d8760ec38fe67 95b54b4ee7052c8795b54b4ee7052c87 8000000000000000e17d8760ec38fe67 95b54b4ee7052c8795b54b4ee7052c87 fpscr=00000000
+vrintp.f64.f64 d9, d21 96108c9ec74207056b503a8ecd334411 556ee144e53f88bf49adae33f7eba926 556ee144e53f88bf6b503a8ecd334411 556ee144e53f88bf49adae33f7eba926 fpscr=00000000
+vrintp.f64.f64 d9, d21 fa36050ed786d0a818f6c414683b0141 1a02509ef970b88eb8e9921ab8f86fe2 3ff000000000000018f6c414683b0141 1a02509ef970b88eb8e9921ab8f86fe2 fpscr=00000000
+vrintp.f64.f64 d9, d21 b83b166ff9efd3fb20936efaa511c2e0 8cabede730d3a7672513f4aa45ee65f1 800000000000000020936efaa511c2e0 8cabede730d3a7672513f4aa45ee65f1 fpscr=00000000
+vrintp.f64.f64 d9, d21 ac9fe25d5c7b60e95e4ac217bab777f6 6d7220418caa74c81059f7e25aa7a908 6d7220418caa74c85e4ac217bab777f6 6d7220418caa74c81059f7e25aa7a908 fpscr=00000000
+vrintp.f64.f64 d9, d21 f22cdd7ad9b6b9f8b158d54882c7810f c3d8eec738060b1bfbdb9a803586cd1c c3d8eec738060b1bb158d54882c7810f c3d8eec738060b1bfbdb9a803586cd1c fpscr=00000000
+vrintp.f64.f64 d9, d21 026193ab5e47ef15d99fb0c76aa12b64 1841515c9a67574c25e620cd35690552 3ff0000000000000d99fb0c76aa12b64 1841515c9a67574c25e620cd35690552 fpscr=00000000
+vrintp.f64.f64 d9, d21 33151e60ac142612cb5a201a8bbba728 2ff81b9e848362c9a8ef8f2792f0bf37 3ff0000000000000cb5a201a8bbba728 2ff81b9e848362c9a8ef8f2792f0bf37 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vrintp.f64.f64 d9, d21 0549398c1b28c4266645b47819c64ee7 586125036221b7fe9e4b4aea4d4ff837 586125036221b7fe6645b47819c64ee7 586125036221b7fe9e4b4aea4d4ff837 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintp.f64.f64 d9, d21 408f4fc57a689eea408f4fc57a689eea 7182cd86305f99927182cd86305f9992 7182cd86305f9992408f4fc57a689eea 7182cd86305f99927182cd86305f9992 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintp.f64.f64 d9, d21 256ee5ecc09d7670ef6328b23304715a 90b7ac8e076807dc8cc9d3a101f29387 8000000000000000ef6328b23304715a 90b7ac8e076807dc8cc9d3a101f29387 fpscr=00000000
+vrintp.f64.f64 d9, d21 5918d50a3ab9980067262220df5c4f77 4717ae4359235d926179458c986a717c 4717ae4359235d9267262220df5c4f77 4717ae4359235d926179458c986a717c fpscr=00000000
+vrintp.f64.f64 d9, d21 2fb5d867836e8b05f9bd625c9884d4c5 89fb53c1b3d5c88df1ec64e385c2df8f 8000000000000000f9bd625c9884d4c5 89fb53c1b3d5c88df1ec64e385c2df8f fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintp.f64.f64 d9, d21 0d4e6e985f66073869bcb9a2e6fa8509 aa65027ce9b824b4d3af7ab17ad272b0 800000000000000069bcb9a2e6fa8509 aa65027ce9b824b4d3af7ab17ad272b0 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintp.f64.f64 d9, d21 4152fd7131c4d23b4152fd7131c4d23b 6395554a939495259373a6a46faf62d6 6395554a939495254152fd7131c4d23b 6395554a939495259373a6a46faf62d6 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintp.f64.f64 d9, d21 c525a5f35eb1ed19e2e8b1c40a0ba740 165dd6bbfaee6874165dd6bbfaee6874 3ff0000000000000e2e8b1c40a0ba740 165dd6bbfaee6874165dd6bbfaee6874 fpscr=00000000
+vrintp.f64.f64 d9, d21 f17a27b496287b9c59908bee3b09939f c830f7f1e3b0846b69da5e8c7658d7e2 c830f7f1e3b0846b59908bee3b09939f c830f7f1e3b0846b69da5e8c7658d7e2 fpscr=00000000
+vrintp.f64.f64 d9, d21 753604f6a872fee9ebe1b027d27afac8 aeecc4eeaea23412a2fde0b418bf624e 8000000000000000ebe1b027d27afac8 aeecc4eeaea23412a2fde0b418bf624e fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vrintp.f64.f64 d9, d21 41ea6a6d2294a195c042526753ab4525 ac6e22eac1d4a614ac6e22eac1d4a614 8000000000000000c042526753ab4525 ac6e22eac1d4a614ac6e22eac1d4a614 fpscr=00000000
+vrintp.f64.f64 d9, d21 89e3a021721f57a217366cf64057c0e8 083039a6caced193ecf5bfdcf70ffa99 3ff000000000000017366cf64057c0e8 083039a6caced193ecf5bfdcf70ffa99 fpscr=00000000
+vrintp.f64.f64 d9, d21 0492e69dc8d8765ae4a35dddbd101ded 378403345d9abf3f631f2e0e86045abc 3ff0000000000000e4a35dddbd101ded 378403345d9abf3f631f2e0e86045abc fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintp.f64.f64 d9, d21 10bd300dd91e57a4a0652d910c26e348 3be18d206604aae9b7dedbe77a6b8b69 3ff0000000000000a0652d910c26e348 3be18d206604aae9b7dedbe77a6b8b69 fpscr=00000000
+vrintp.f64.f64 d9, d21 7d6f94468622fa4a16d46efccd38facf 56142d72203b3b6533cee0fb3c9c75db 56142d72203b3b6516d46efccd38facf 56142d72203b3b6533cee0fb3c9c75db fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintp.f64.f64 d9, d21 2bf77352e3a378c22bf77352e3a378c2 dda37e01a63e1982601fc1f947d98a7c dda37e01a63e19822bf77352e3a378c2 dda37e01a63e1982601fc1f947d98a7c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintp.f64.f64 d9, d21 93ab366b30c46b34d2a3779e846ef775 4819b367988c163b4e472c789712f903 4819b367988c163bd2a3779e846ef775 4819b367988c163b4e472c789712f903 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintp.f64.f64 d9, d21 032a965e15bf81e4485b366f1acd7138 65853eedbe771c67712bdc632877b91f 65853eedbe771c67485b366f1acd7138 65853eedbe771c67712bdc632877b91f fpscr=00000000
+vrintp.f64.f64 d9, d21 51fff75e1cf7fe1e0483c374fe803e1f 02632d98f10733580576f9fdd7fe91b7 3ff00000000000000483c374fe803e1f 02632d98f10733580576f9fdd7fe91b7 fpscr=00000000
+vrintp.f64.f64 d9, d21 c1158e89be9f399c43e69303bea2ceb1 9d6e8f800340aafee95ca70bf834be78 800000000000000043e69303bea2ceb1 9d6e8f800340aafee95ca70bf834be78 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintm.f64.f64 d12, d12 1f25711cabdccdd61f25711cabdccdd6 ea67c1d95d7ca5229fb93bf83b58e675 ea67c1d95d7ca522bff0000000000000 ea67c1d95d7ca522bff0000000000000 fpscr=00000000
+randV128: 11008 calls, 11357 iters
+vrintm.f64.f64 d12, d12 8f89627e84711d0eab2e960e46811bc8 d17f79839d98462694eabe83ebf5c961 d17f79839d984626bff0000000000000 d17f79839d984626bff0000000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 8725080685ce689566c149c25830f959 aa78114056240076476b961e22a3b4a8 aa78114056240076476b961e22a3b4a8 aa78114056240076476b961e22a3b4a8 fpscr=00000000
+vrintm.f64.f64 d12, d12 1fe80767f232ce304de59b93e64a3144 ef67453e9accab9bd3842f8001b9c63f ef67453e9accab9bd3842f8001b9c63f ef67453e9accab9bd3842f8001b9c63f fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 adfb75178cc777b7c0ec2aca90402fb9 4cc23feb9b1e3cf44cc23feb9b1e3cf4 4cc23feb9b1e3cf44cc23feb9b1e3cf4 4cc23feb9b1e3cf44cc23feb9b1e3cf4 fpscr=00000000
+vrintm.f64.f64 d12, d12 7445c94b6f5ddfecb1c66c07c29d5284 2f10162eb715fad0a2151fff7885a3e4 2f10162eb715fad0bff0000000000000 2f10162eb715fad0bff0000000000000 fpscr=00000000
+vrintm.f64.f64 d12, d12 27ba9def449c94c2d672a29725078443 d3317995fced05e36b589f07ae4d606e d3317995fced05e36b589f07ae4d606e d3317995fced05e36b589f07ae4d606e fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 2c2f770eac4118a08f25addfb35a9c3b 012810b982e64ee1f51f5efe3d6ad00e 012810b982e64ee1f51f5efe3d6ad00e 012810b982e64ee1f51f5efe3d6ad00e fpscr=00000000
+vrintm.f64.f64 d12, d12 e8fb0400df0eab6c4479156c7aad7318 a732c60b9b155e7f2e0cde79cbc92d35 a732c60b9b155e7f0000000000000000 a732c60b9b155e7f0000000000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 e4be79540af865f7e4be79540af865f7 900200c3ea3ddafa6f5275935189bdf5 900200c3ea3ddafa6f5275935189bdf5 900200c3ea3ddafa6f5275935189bdf5 fpscr=00000000
+vrintm.f64.f64 d12, d12 d82f64733db49cf3227fa8ad6da36f2d 22bcc9b1dcc32459852e8cd5dde490ae 22bcc9b1dcc32459bff0000000000000 22bcc9b1dcc32459bff0000000000000 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintm.f64.f64 d12, d12 24cec7bbce65bceb6fa120ce80b4201a 47cf610cb37383c18a5dc63832319e24 47cf610cb37383c1bff0000000000000 47cf610cb37383c1bff0000000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 c1d1a7f046886f0e3df2cb3f5aac02b4 a409b38899b0782fa409b38899b0782f a409b38899b0782fbff0000000000000 a409b38899b0782fbff0000000000000 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintm.f64.f64 d12, d12 5bebdf86990353445bebdf8699035344 db506e3363007094a2f8a62016c50bbf db506e3363007094bff0000000000000 db506e3363007094bff0000000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 71d9fd58e27f4d58ad96fb5e4e6a6ad4 336f9668735342446a355adc681ce3de 336f9668735342446a355adc681ce3de 336f9668735342446a355adc681ce3de fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 40897e0cbdc27a8740897e0cbdc27a87 7b9f4983c99e0c0309a983f31d049e2a 7b9f4983c99e0c030000000000000000 7b9f4983c99e0c030000000000000000 fpscr=00000000
+vrintm.f64.f64 d12, d12 45a4000e6664bab9c2604775c59b5c75 ec44a6fdbaf5d3ae145395f4425fcf96 ec44a6fdbaf5d3ae0000000000000000 ec44a6fdbaf5d3ae0000000000000000 fpscr=00000000
+vrintm.f64.f64 d12, d12 0fe672eba580ff24071b1d27ee69fb38 ccec2b5a42a23ef406ee7a40ba897aa4 ccec2b5a42a23ef40000000000000000 ccec2b5a42a23ef40000000000000000 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintm.f64.f64 d12, d12 a5ffa3350f6e76a11f7f6029eb867d47 7f2ff5e4a1fe6a0fdf3070a5fac2cda6 7f2ff5e4a1fe6a0fdf3070a5fac2cda6 7f2ff5e4a1fe6a0fdf3070a5fac2cda6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 7077d1ae40a206037077d1ae40a20603 349407aaf5d7f86c7d11f4884e106493 349407aaf5d7f86c7d11f4884e106493 349407aaf5d7f86c7d11f4884e106493 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintm.f64.f64 d12, d12 829823feaea9a91658a2fb696225b65b da69a12c8c6b90bce43e9d58a23482c8 da69a12c8c6b90bce43e9d58a23482c8 da69a12c8c6b90bce43e9d58a23482c8 fpscr=00000000
+vrintm.f64.f64 d12, d12 fd6cfabe565f86808b716aa58577615c b267aa73d646bdf1d50e329d0521b187 b267aa73d646bdf1d50e329d0521b187 b267aa73d646bdf1d50e329d0521b187 fpscr=00000000
+vrintm.f64.f64 d12, d12 0479d0abfb348a8e76307d8d1e85a438 70854dadbce2d404f5c2390427f3b265 70854dadbce2d404f5c2390427f3b265 70854dadbce2d404f5c2390427f3b265 fpscr=00000000
+vrintm.f64.f64 d12, d12 3deb22fbc51e77e4b1da43d088c0c89f b8f176d41a2407288ddee0070d52baf7 b8f176d41a240728bff0000000000000 b8f176d41a240728bff0000000000000 fpscr=00000000
+vrintm.f64.f64 d12, d12 ff415e850c7f2b48fb80aafb38fc7e9e 40b12e04a1d752a34d003a36604b1a8f 40b12e04a1d752a34d003a36604b1a8f 40b12e04a1d752a34d003a36604b1a8f fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 1920c79499ca62383bb9b4a6c27c9cd9 b25cb3a8a9eee892b25cb3a8a9eee892 b25cb3a8a9eee892bff0000000000000 b25cb3a8a9eee892bff0000000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 2d6f6005c4ce81732d6f6005c4ce8173 bcd0483e722ed4082aaf0fd1942c99fb bcd0483e722ed4080000000000000000 bcd0483e722ed4080000000000000000 fpscr=00000000
+vrintm.f64.f64 d12, d12 53d6b4d675eb2eb96d77387240e33846 c0ceeeb62d44c8bb40e795e295e66eb1 c0ceeeb62d44c8bb40e795e000000000 c0ceeeb62d44c8bb40e795e000000000 fpscr=00000000
+vrintm.f64.f64 d12, d12 49093684b1428c01390917f2fecbd9e2 3a1408e4a4c2511ff148b5ae76e00c8e 3a1408e4a4c2511ff148b5ae76e00c8e 3a1408e4a4c2511ff148b5ae76e00c8e fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 eaf0f2ead31365b33f2efa796c319387 f2d233550b81dc91f2d233550b81dc91 f2d233550b81dc91f2d233550b81dc91 f2d233550b81dc91f2d233550b81dc91 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintm.f64.f64 d12, d12 de211341b6c4315347560b396ab20793 02276311eab7a9f1f07eeb9650df609e 02276311eab7a9f1f07eeb9650df609e 02276311eab7a9f1f07eeb9650df609e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintm.f64.f64 d12, d12 e1275facadc8ed83e1275facadc8ed83 bff20659339abb469b470409ed82e196 bff20659339abb46bff0000000000000 bff20659339abb46bff0000000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 e3bffc3c77cce1458d90c3bcaa1e854b c640debb1e03c1b5a0119290e48bd9a4 c640debb1e03c1b5bff0000000000000 c640debb1e03c1b5bff0000000000000 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintm.f64.f64 d12, d12 766350d31a70a8767b81f3461f88fa9e cab2a72f144af361cab2a72f144af361 cab2a72f144af361cab2a72f144af361 cab2a72f144af361cab2a72f144af361 fpscr=00000000
+vrintm.f64.f64 d12, d12 ab8270b3aa067e2ab9065e579a7bab67 95c48cab90d0ab8b1330dedb740e0f98 95c48cab90d0ab8b0000000000000000 95c48cab90d0ab8b0000000000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 c5a455d372304e609d1f6ab6ee7e2eda 2b3df8ebc7d38d1373b5db08e55ae9db 2b3df8ebc7d38d1373b5db08e55ae9db 2b3df8ebc7d38d1373b5db08e55ae9db fpscr=00000000
+vrintm.f64.f64 d12, d12 e3091bcffd72babe59d17cc005027962 02f356bdb8676b16f6b232434d090033 02f356bdb8676b16f6b232434d090033 02f356bdb8676b16f6b232434d090033 fpscr=00000000
+vrintm.f64.f64 d12, d12 39e651fdca5e5da7c0fde8f29ea391ea 34510650cedd585142ea82dff6ab86b5 34510650cedd585142ea82dff6ab86a0 34510650cedd585142ea82dff6ab86a0 fpscr=00000000
+vrintm.f64.f64 d12, d12 61ffa0d3176a0b7a322b3c69b73a9739 428c3cb4eea649c45141aabbcd18a3e0 428c3cb4eea649c45141aabbcd18a3e0 428c3cb4eea649c45141aabbcd18a3e0 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 d12efa58b4fce50684ed4176fbd09a74 1301a7969a012193d502e36cecfdacdb 1301a7969a012193d502e36cecfdacdb 1301a7969a012193d502e36cecfdacdb fpscr=00000000
+vrintm.f64.f64 d12, d12 e34a453228fef2bf9168f5830b7a84de b2ff6dce70e55179c09dc1aaa618f6eb b2ff6dce70e55179c09dc40000000000 b2ff6dce70e55179c09dc40000000000 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vrintm.f64.f64 d12, d12 2ab62a8186ac4e98d8e80043bd376303 c1df48203ef979d472e46fa8c689a717 c1df48203ef979d472e46fa8c689a717 c1df48203ef979d472e46fa8c689a717 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vrintm.f64.f64 d12, d12 6c1efc469f0f15706c1efc469f0f1570 f7baa102cd24a19df7baa102cd24a19d f7baa102cd24a19df7baa102cd24a19d f7baa102cd24a19df7baa102cd24a19d fpscr=00000000
+vrintm.f64.f64 d12, d12 b424d02366a58231f836d96f19a84b2a 7f08a4261823d4105e71802fc42d3041 7f08a4261823d4105e71802fc42d3041 7f08a4261823d4105e71802fc42d3041 fpscr=00000000
+vrintm.f64.f64 d12, d12 428a2b868f84c7e3facbdaafd0a47020 8500e4c59114f715c2fbb9909e78b133 8500e4c59114f715c2fbb9909e78b140 8500e4c59114f715c2fbb9909e78b140 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vrintm.f64.f64 d12, d12 365c8821588f1fc715a1e31e42a0d2c8 9264fe011ea0c5069264fe011ea0c506 9264fe011ea0c506bff0000000000000 9264fe011ea0c506bff0000000000000 fpscr=00000000
+vrintm.f64.f64 d12, d12 e263589a490b72d8d2f80c5f8e70d01e 30423a32499324352290fc4826dc57c4 30423a32499324350000000000000000 30423a32499324350000000000000000 fpscr=00000000
+vrintm.f64.f64 d12, d12 0583866c94d31a48324e63e861172ff2 2b2743ce28a8184d891605eb157b88ad 2b2743ce28a8184dbff0000000000000 2b2743ce28a8184dbff0000000000000 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vrintm.f64.f64 d12, d12 53308a9fda85f0fb3340425a68fd2c9f fb4a5ec360d9f4541a40f23af99af89a fb4a5ec360d9f4540000000000000000 fb4a5ec360d9f4540000000000000000 fpscr=00000000
+vrintm.f64.f64 d12, d12 065d4418ea62c2ffabfa9908203bede6 9defdfe4b0056faa0e08956dfed9d66c 9defdfe4b0056faa0000000000000000 9defdfe4b0056faa0000000000000000 fpscr=00000000
+vrintn.f32.f32 s3, s15 3bbb0abc9313f2c4bc25a854ef1d206b 1f44fab0afde49ce867bd8f89b2829c1 000000009313f2c4bc25a854ef1d206b 1f44fab0afde49ce867bd8f89b2829c1 fpscr=00000000
+vrintn.f32.f32 s3, s15 047cb79b5b29fb6dbf7d855cf025e58f b1e3fabe27379ae16c26ff95208a9616 800000005b29fb6dbf7d855cf025e58f b1e3fabe27379ae16c26ff95208a9616 fpscr=00000000
+vrintn.f32.f32 s3, s15 140ae2d17cee2dee198120d06cfbdd41 98dacca69f7019312e737963fbb3585f 800000007cee2dee198120d06cfbdd41 98dacca69f7019312e737963fbb3585f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[1]
+vrintn.f32.f32 s3, s15 b628ed6c89fc6866597b04f9877d3d24 c1b217662acec7cdf6dc5fc72acec7cd c1b0000089fc6866597b04f9877d3d24 c1b217662acec7cdf6dc5fc72acec7cd fpscr=00000000
+vrintn.f32.f32 s3, s15 023ebbab56716c5612e410c6dba87fa4 4179130bbcfcff9b29a1794a7c97b6d7 4180000056716c5612e410c6dba87fa4 4179130bbcfcff9b29a1794a7c97b6d7 fpscr=00000000
+vrintn.f32.f32 s3, s15 569d44e9d4d61da03e2e81949fae8c61 2dd59c326d5050decb577b4ac62692e4 00000000d4d61da03e2e81949fae8c61 2dd59c326d5050decb577b4ac62692e4 fpscr=00000000
+vrintn.f32.f32 s3, s15 2c712f834fac0d33fad8e5b3f57864c2 a9bbae056f54e8b1bd522f2e71d83a61 800000004fac0d33fad8e5b3f57864c2 a9bbae056f54e8b1bd522f2e71d83a61 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintn.f32.f32 s3, s15 e01e3f9a12f68c8ee3c2918ad52372c5 044d163185c07fb525c6f48212e1905c 0000000012f68c8ee3c2918ad52372c5 044d163185c07fb525c6f48212e1905c fpscr=00000000
+vrintn.f32.f32 s3, s15 bd48df92a98a188b52ff01de0eef2d89 b817ab3521df91b26a205402325d4af0 80000000a98a188b52ff01de0eef2d89 b817ab3521df91b26a205402325d4af0 fpscr=00000000
+vrintn.f32.f32 s3, s15 5576a3de7c84caf38229db6929edfe74 ba72786f8c16318ad3590c2c46f1883a 800000007c84caf38229db6929edfe74 ba72786f8c16318ad3590c2c46f1883a fpscr=00000000
+vrintn.f32.f32 s3, s15 f6d4cc990203e1e252cc52dab4dd2d44 c0ba1e66d9b02dfa21e55b75e165b5ac c0c000000203e1e252cc52dab4dd2d44 c0ba1e66d9b02dfa21e55b75e165b5ac fpscr=00000000
+vrintn.f32.f32 s3, s15 e2eb14610f9796b5455289b1207f57a4 cd92e6ae2dabbe99e0bbbb68d96487d4 cd92e6ae0f9796b5455289b1207f57a4 cd92e6ae2dabbe99e0bbbb68d96487d4 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[1]
+vrintn.f32.f32 s3, s15 73188893731888931c327941fec37daa 256904f007a2c2f9f31a0847cdde2f75 00000000731888931c327941fec37daa 256904f007a2c2f9f31a0847cdde2f75 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintn.f32.f32 s3, s15 70ac1327bce46e31f26b70f6b37f18d5 4ac29f36683a7cd051be2ad30cc966a4 4ac29f36bce46e31f26b70f6b37f18d5 4ac29f36683a7cd051be2ad30cc966a4 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintn.f32.f32 s3, s15 c590c1e22d8b04ba1927713ec590c1e2 674cc96b17dcea2b0545384bd16ee333 674cc96b2d8b04ba1927713ec590c1e2 674cc96b17dcea2b0545384bd16ee333 fpscr=00000000
+randV128: 11264 calls, 11622 iters
+vrintn.f32.f32 s3, s15 27bc711951033c1c28fc95f1e558d08f 39390c163d77694c752ec1d6a6cbf909 0000000051033c1c28fc95f1e558d08f 39390c163d77694c752ec1d6a6cbf909 fpscr=00000000
+vrintn.f32.f32 s3, s15 354151c547676954d67933a377dfbc46 98cdc30812d5f969c7211df220c234b7 8000000047676954d67933a377dfbc46 98cdc30812d5f969c7211df220c234b7 fpscr=00000000
+vrintn.f32.f32 s3, s15 78a5b01c6370000fac43fc4a04cad8fe a9e980d6e77fabedc3ee31ce622b433c 800000006370000fac43fc4a04cad8fe a9e980d6e77fabedc3ee31ce622b433c fpscr=00000000
+vrintn.f32.f32 s3, s15 763e0cda2f739fb035e6f9ba37b00a5b 9b6c300d16a4d48e948d7213ad661125 800000002f739fb035e6f9ba37b00a5b 9b6c300d16a4d48e948d7213ad661125 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintn.f32.f32 s3, s15 1bfb5051e06b41aac9fe65ab8b041b25 7159f6a067518ad6c879fe94c879fe94 7159f6a0e06b41aac9fe65ab8b041b25 7159f6a067518ad6c879fe94c879fe94 fpscr=00000000
+vrintn.f32.f32 s3, s15 ca893d1fa2aaef4e2e634a2cba4624a7 e53b25cd5d34d0967395bdee0fdb1f48 e53b25cda2aaef4e2e634a2cba4624a7 e53b25cd5d34d0967395bdee0fdb1f48 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintn.f32.f32 s3, s15 0f919ec40f919ec4ca7dc06b9e0893e0 e072944b32e3ee4fa4800130600ad196 e072944b0f919ec4ca7dc06b9e0893e0 e072944b32e3ee4fa4800130600ad196 fpscr=00000000
+vrintn.f32.f32 s3, s15 94708189d01a1d38533c4278dcc9b408 818022347470296511f704c959c79de4 80000000d01a1d38533c4278dcc9b408 818022347470296511f704c959c79de4 fpscr=00000000
+vrintn.f32.f32 s3, s15 8390329113b137bed46119bc4f7b459c 747ef5b674a0dac80b7da2538ddd888a 747ef5b613b137bed46119bc4f7b459c 747ef5b674a0dac80b7da2538ddd888a fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintn.f32.f32 s3, s15 75d972e668f398fe68f398fe1053d264 300a2b4cb3552c060b75cd7591cdab7f 0000000068f398fe68f398fe1053d264 300a2b4cb3552c060b75cd7591cdab7f fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintn.f32.f32 s3, s15 e9f638c148bd2fd99e57617fd5fc1804 9de38bc3937e12646626e5c24f585386 8000000048bd2fd99e57617fd5fc1804 9de38bc3937e12646626e5c24f585386 fpscr=00000000
+vrintn.f32.f32 s3, s15 dca307e9c7c2d31bd49fc520dc6a3a63 fccee7c47de88b23f583715a95eaada1 fccee7c4c7c2d31bd49fc520dc6a3a63 fccee7c47de88b23f583715a95eaada1 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintn.f32.f32 s3, s15 bce8a5a71a986a781a986a7834ffd2e6 0e94ed35e64310825b1d5dd99a49b07e 000000001a986a781a986a7834ffd2e6 0e94ed35e64310825b1d5dd99a49b07e fpscr=00000000
+vrintn.f32.f32 s3, s15 351c941bc9ecbb771470aef448c45d15 81fda2cac65dbc7a91cfa1cdf6baa4b3 80000000c9ecbb771470aef448c45d15 81fda2cac65dbc7a91cfa1cdf6baa4b3 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintn.f32.f32 s3, s15 7ab35798cdfe25b21d81c7bbcdfe25b2 0d76f1b25a1f501bb3c471e6dfc4c9dd 00000000cdfe25b21d81c7bbcdfe25b2 0d76f1b25a1f501bb3c471e6dfc4c9dd fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintn.f32.f32 s3, s15 f3ee4dbca71e3eeaa347de8990305931 320b75d6786f890a993136f74e116e0e 00000000a71e3eeaa347de8990305931 320b75d6786f890a993136f74e116e0e fpscr=00000000
+vrintn.f32.f32 s3, s15 71d2921db69ee75fff05f76be7a87897 492636a672cfff2bc09c9717bffef7c3 492636a0b69ee75fff05f76be7a87897 492636a672cfff2bc09c9717bffef7c3 fpscr=00000000
+vrintn.f32.f32 s3, s15 6ed5b6cd699f25debffb807cd24c5d60 663854925e606568ef62d8e88fbbcd4e 66385492699f25debffb807cd24c5d60 663854925e606568ef62d8e88fbbcd4e fpscr=00000000
+vrintn.f32.f32 s3, s15 1477f4873a93ea3dbe15aa12072b9da5 6d19a35be7aec8318330559637ed1c22 6d19a35b3a93ea3dbe15aa12072b9da5 6d19a35be7aec8318330559637ed1c22 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintn.f32.f32 s3, s15 502bb83b87f7e9d8428f3f4552950319 597512dd7d1688af7f1814e91876660f 597512dd87f7e9d8428f3f4552950319 597512dd7d1688af7f1814e91876660f fpscr=00000000
+vrintn.f32.f32 s3, s15 9a7d12f9b2a56b668cd7f4ac0d48662c 9356b1adb92e2ff1363b0944b9a98e55 80000000b2a56b668cd7f4ac0d48662c 9356b1adb92e2ff1363b0944b9a98e55 fpscr=00000000
+vrintn.f32.f32 s3, s15 2b7347b12413e46d608b1e2c7c783af7 32b42a599271fa2ff44a47bc7ead7284 000000002413e46d608b1e2c7c783af7 32b42a599271fa2ff44a47bc7ead7284 fpscr=00000000
+vrintn.f32.f32 s3, s15 1517b684138eccc3673acb22f9bc48dd 8cd5b3a791816ad7213dabff89c802b8 80000000138eccc3673acb22f9bc48dd 8cd5b3a791816ad7213dabff89c802b8 fpscr=00000000
+vrintn.f32.f32 s3, s15 8abfc3f95159bade423fc52c4251a979 bfb1d3931382a362750d98809f9925fd bf8000005159bade423fc52c4251a979 bfb1d3931382a362750d98809f9925fd fpscr=00000000
+vrintn.f32.f32 s3, s15 67c7093f6fdebfeb4397700598e7124c ff64770cbc4ac2fd75db67073e381535 ff64770c6fdebfeb4397700598e7124c ff64770cbc4ac2fd75db67073e381535 fpscr=00000000
+vrintn.f32.f32 s3, s15 e13fd6e986f2021f56c08a80c931b85a 335c13eda7b2aba44a5dccf012c25f77 0000000086f2021f56c08a80c931b85a 335c13eda7b2aba44a5dccf012c25f77 fpscr=00000000
+vrintn.f32.f32 s3, s15 c4407e98c2f7a829ec5f85f3a1e671e1 4a101514fb7d0b4365b1ba2a8f39a25a 4a101514c2f7a829ec5f85f3a1e671e1 4a101514fb7d0b4365b1ba2a8f39a25a fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[0]
+vrintn.f32.f32 s3, s15 04bfd4fd1d55b8d77ed8c20b6e766237 64425adeb38bd599eaba27f5a60d7821 64425ade1d55b8d77ed8c20b6e766237 64425adeb38bd599eaba27f5a60d7821 fpscr=00000000
+vrintn.f32.f32 s3, s15 32b609f12dbe1ecdf29105bf59b60ff7 595ccc96befc3a1035a970b4e1915f56 595ccc962dbe1ecdf29105bf59b60ff7 595ccc96befc3a1035a970b4e1915f56 fpscr=00000000
+vrintn.f32.f32 s3, s15 b690a641c0236b16c8406d6dbf7ce573 95f0ecfe85617ac74b1758f5923b1c73 80000000c0236b16c8406d6dbf7ce573 95f0ecfe85617ac74b1758f5923b1c73 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintn.f32.f32 s3, s15 0f8c5e79ed0a9bd32c80bcfd1b3716a9 cb47193a3e0ac4ea2234de83c0b0ee82 cb47193aed0a9bd32c80bcfd1b3716a9 cb47193a3e0ac4ea2234de83c0b0ee82 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintn.f32.f32 s3, s15 0ed66d7aa7613d605f36c36d5cbb3213 8c2e59a25fd3fce78c2e59a2085b4545 80000000a7613d605f36c36d5cbb3213 8c2e59a25fd3fce78c2e59a2085b4545 fpscr=00000000
+vrintn.f32.f32 s3, s15 d00e37324e6716cf647a3bdac713a12c 4af93d5abb99590cba412ccee49a765c 4af93d5a4e6716cf647a3bdac713a12c 4af93d5abb99590cba412ccee49a765c fpscr=00000000
+vrintn.f32.f32 s3, s15 4238a21f74365d4a2f2c7b0d75501e11 e24cf597695e7c7fd4a3f183905be68f e24cf59774365d4a2f2c7b0d75501e11 e24cf597695e7c7fd4a3f183905be68f fpscr=00000000
+vrintn.f32.f32 s3, s15 a8eef856be31e18b6edeaeecc81d1def cc8913204bd0bbf02f505446d01d4b2f cc891320be31e18b6edeaeecc81d1def cc8913204bd0bbf02f505446d01d4b2f fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrinta.f32.f32 s6, s18 e7c9ef1206a2e7a1edc1f927edc1f927 c033c5300afb79aea2fce2bfb019feb0 e7c9ef1200000000edc1f927edc1f927 c033c5300afb79aea2fce2bfb019feb0 fpscr=00000000
+vrinta.f32.f32 s6, s18 f3365e503cefe0cba57d56653d22b149 27ad2df4d02346a8cba93afe57b708fb f3365e50d02346a8a57d56653d22b149 27ad2df4d02346a8cba93afe57b708fb fpscr=00000000
+vrinta.f32.f32 s6, s18 311c62a85d363a342cd2eaaf2f847895 53b92cb516d7067eb1cf20e907247057 311c62a8000000002cd2eaaf2f847895 53b92cb516d7067eb1cf20e907247057 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrinta.f32.f32 s6, s18 4b7a9ab04a7fd56c3f17e3d73f17e3d7 d80b8de0e308375edbc539feec6adf4f 4b7a9ab0e308375e3f17e3d73f17e3d7 d80b8de0e308375edbc539feec6adf4f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrinta.f32.f32 s6, s18 e70217d0c8c6b0d6faa5641b09e1c0c7 1bc60591c528546f1b147251e5b940ff e70217d0c5285000faa5641b09e1c0c7 1bc60591c528546f1b147251e5b940ff fpscr=00000000
+vrinta.f32.f32 s6, s18 9aa0004c922785ba99a79174398a1992 2a3eb21993f7cb8e52c6272118ff92f1 9aa0004c8000000099a79174398a1992 2a3eb21993f7cb8e52c6272118ff92f1 fpscr=00000000
+vrinta.f32.f32 s6, s18 746abdb920f937555a6792a563a5dbc4 6685a79afdf40d0cb39e66c2d8355055 746abdb9fdf40d0c5a6792a563a5dbc4 6685a79afdf40d0cb39e66c2d8355055 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrinta.f32.f32 s6, s18 d4ae6a74d4da14dea92d026da1a49f70 c1a525c2475670b3e4867aac475670b3 d4ae6a7447567100a92d026da1a49f70 c1a525c2475670b3e4867aac475670b3 fpscr=00000000
+vrinta.f32.f32 s6, s18 54d95966d097504e0323c1927ec25601 67225d3ee63b8182a19fc2388ac9684f 54d95966e63b81820323c1927ec25601 67225d3ee63b8182a19fc2388ac9684f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrinta.f32.f32 s6, s18 1bed6affbe0a74ba1bed6aff238db87b 252f71ab0845c87b8623d742c7f11362 1bed6aff000000001bed6aff238db87b 252f71ab0845c87b8623d742c7f11362 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrinta.f32.f32 s6, s18 b0f64d65afbb186992d925edafbb1869 5706d227c1b8a44d0f93afb8d7a898ed b0f64d65c1b8000092d925edafbb1869 5706d227c1b8a44d0f93afb8d7a898ed fpscr=00000000
+vrinta.f32.f32 s6, s18 0974fd759b571d2ac12c7167b331f8d4 5f5b390b91cd5eff637449fc2795de67 0974fd7580000000c12c7167b331f8d4 5f5b390b91cd5eff637449fc2795de67 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrinta.f32.f32 s6, s18 09c92ef67e7d2c19a1fa6d7f2ff1f49c 658c4cee8e1e3f430933aab8dca8905e 09c92ef680000000a1fa6d7f2ff1f49c 658c4cee8e1e3f430933aab8dca8905e fpscr=00000000
+vrinta.f32.f32 s6, s18 58651a9ccbff714e9159e16be24368ed 7f062b07f8aa248b9405348d68eb6a32 58651a9cf8aa248b9159e16be24368ed 7f062b07f8aa248b9405348d68eb6a32 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrinta.f32.f32 s6, s18 6e6141a0f3ec6d0136de6b65d5b06a86 12670d832f7431ad9a37c4959a37c495 6e6141a00000000036de6b65d5b06a86 12670d832f7431ad9a37c4959a37c495 fpscr=00000000
+vrinta.f32.f32 s6, s18 77903ce9ab1543d5a54717752f0cccdb 54877799ca7cb669c04d34c62c538876 77903ce9ca7cb668a54717752f0cccdb 54877799ca7cb669c04d34c62c538876 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrinta.f32.f32 s6, s18 16ed2ec84304cccd1f5ca59d2c0d3500 856d3f6a022bf28cd8a027a0a0ca9529 16ed2ec8000000001f5ca59d2c0d3500 856d3f6a022bf28cd8a027a0a0ca9529 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrinta.f32.f32 s6, s18 4fa8712da26c9d394fa8712dc008852a 39dd21ecf37c9190f8b88400894eb692 4fa8712df37c91904fa8712dc008852a 39dd21ecf37c9190f8b88400894eb692 fpscr=00000000
+vrinta.f32.f32 s6, s18 cf248b8ce6c2dcc409ae12e6c8cdb9e7 b9c4390ba0a3ac29d6601209ca5fa8d7 cf248b8c8000000009ae12e6c8cdb9e7 b9c4390ba0a3ac29d6601209ca5fa8d7 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrinta.f32.f32 s6, s18 420ccf9f8d9b57f1c9aca1c98b2659c5 eac6c25a5ef501b7314102c3fd5e69d1 420ccf9f5ef501b7c9aca1c98b2659c5 eac6c25a5ef501b7314102c3fd5e69d1 fpscr=00000000
+vrinta.f32.f32 s6, s18 978499c855f5c809400fc8ee697bd589 b6a3be415e415051f79f6c6ed27b4b8d 978499c85e415051400fc8ee697bd589 b6a3be415e415051f79f6c6ed27b4b8d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrinta.f32.f32 s6, s18 38766e5285918d982717cd363b11a196 397603ddad6a0d77b5ccc665db2bad5b 38766e52800000002717cd363b11a196 397603ddad6a0d77b5ccc665db2bad5b fpscr=00000000
+vrinta.f32.f32 s6, s18 4949e1f54be601ad0be23aa2ea8a7dcc 3984146c6975a6a7baf10f4e4761e0a1 4949e1f56975a6a70be23aa2ea8a7dcc 3984146c6975a6a7baf10f4e4761e0a1 fpscr=00000000
+vrinta.f32.f32 s6, s18 6796a17a983aa3a5e0763fd2d3f0d19c 872e4abad84b4f4b56790b27039ad403 6796a17ad84b4f4be0763fd2d3f0d19c 872e4abad84b4f4b56790b27039ad403 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrinta.f32.f32 s6, s18 51b2dbe15e8f55a799f88c4cc8bdf748 b0b7652a155373964bfb6fc84bfb6fc8 51b2dbe10000000099f88c4cc8bdf748 b0b7652a155373964bfb6fc84bfb6fc8 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrinta.f32.f32 s6, s18 c57b8523596df50ab5a2242b9e302be4 a84c962b724772ba2bf0be00d700f275 c57b8523724772bab5a2242b9e302be4 a84c962b724772ba2bf0be00d700f275 fpscr=00000000
+vrinta.f32.f32 s6, s18 15d7d62e99e020744d96cc4f683c7285 b15d3afd2e638cca297968a0f5c3e111 15d7d62e000000004d96cc4f683c7285 b15d3afd2e638cca297968a0f5c3e111 fpscr=00000000
+vrinta.f32.f32 s6, s18 b2e96ddd72d2f95e47f1badac1784f7a 587f4ff25cbfd3aee2368dff822b6503 b2e96ddd5cbfd3ae47f1badac1784f7a 587f4ff25cbfd3aee2368dff822b6503 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrinta.f32.f32 s6, s18 66a2e41566a2e415f72849e35e67740f b3582612657a0f0e43c9c41a99005f85 66a2e415657a0f0ef72849e35e67740f b3582612657a0f0e43c9c41a99005f85 fpscr=00000000
+randV128: 11520 calls, 11887 iters
+vrinta.f32.f32 s6, s18 98f367908a3368fde3b0eb2fe6f062b6 c4e9d1ec65693546326b1a752ea5b277 98f3679065693546e3b0eb2fe6f062b6 c4e9d1ec65693546326b1a752ea5b277 fpscr=00000000
+vrinta.f32.f32 s6, s18 ceaa101165ef86c425a7ffb8a0a188f2 8577540f1018d63d8cfc9221ab4ecd40 ceaa10110000000025a7ffb8a0a188f2 8577540f1018d63d8cfc9221ab4ecd40 fpscr=00000000
+vrinta.f32.f32 s6, s18 28d4c2b24777aa293d2450b5e5954c21 6a5f001de615d074f64cbb1994cac160 28d4c2b2e615d0743d2450b5e5954c21 6a5f001de615d074f64cbb1994cac160 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[1]
+vrinta.f32.f32 s6, s18 1b8ba9c5814f90e9c5688edbf0fd9108 5744740643bc2157057f3f5e6d9aaa13 1b8ba9c543bc0000c5688edbf0fd9108 5744740643bc2157057f3f5e6d9aaa13 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrinta.f32.f32 s6, s18 d43ca1564355a24135c2d073b5bffc32 3764948a35c9faff35c9faffe2f6e6bd d43ca1560000000035c2d073b5bffc32 3764948a35c9faff35c9faffe2f6e6bd fpscr=00000000
+vrinta.f32.f32 s6, s18 06b9b519e5005895bc68e244909c5c16 06178afb6605189f6263587969e9e05f 06b9b5196605189fbc68e244909c5c16 06178afb6605189f6263587969e9e05f fpscr=00000000
+vrinta.f32.f32 s6, s18 70e9352b2b04225d40313ec412b3be90 5bee5c24b85a0bf6e8559f65db1c1060 70e9352b8000000040313ec412b3be90 5bee5c24b85a0bf6e8559f65db1c1060 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrinta.f32.f32 s6, s18 a24d9753a4edb016bdef2ba44f91866a 616b90b2616b90b28808c62f17759eee a24d9753616b90b2bdef2ba44f91866a 616b90b2616b90b28808c62f17759eee fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrinta.f32.f32 s6, s18 a2bccd012b33021b83896e64a2f2f636 0a32ebb18924f5c29dd89fa55df5adf8 a2bccd018000000083896e64a2f2f636 0a32ebb18924f5c29dd89fa55df5adf8 fpscr=00000000
+vrinta.f32.f32 s6, s18 448aa73372862d6dc2e9c3c0f1e8eb3f 88697a9e03e3f1f6be48d8d5b6200032 448aa73300000000c2e9c3c0f1e8eb3f 88697a9e03e3f1f6be48d8d5b6200032 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[1]
+vrinta.f32.f32 s6, s18 34b494c31bc7ef7b5865b08934b494c3 e2efcbce9919f1eae2efcbcefa6a9454 34b494c3800000005865b08934b494c3 e2efcbce9919f1eae2efcbcefa6a9454 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrinta.f32.f32 s6, s18 edcb7d866ecdb50c6c41704902e40b74 03bea473b2700e033464d5c6e64bca7b edcb7d86800000006c41704902e40b74 03bea473b2700e033464d5c6e64bca7b fpscr=00000000
+vrinta.f32.f32 s6, s18 6d010871fdeb7a65cef4e2ca4bb012cb 224ac38ae1918fe43b0aa92d0c6f805f 6d010871e1918fe4cef4e2ca4bb012cb 224ac38ae1918fe43b0aa92d0c6f805f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrinta.f32.f32 s6, s18 85a9921354b7077da15e378a54b7077d 6aa99b4becab5c4e9be29ceed564be0e 85a99213ecab5c4ea15e378a54b7077d 6aa99b4becab5c4e9be29ceed564be0e fpscr=00000000
+vrinta.f32.f32 s6, s18 f68e4f03fb8f2bab4eb7b28a2b691b3a 8f5c440dc058b7bf667f5e30add04491 f68e4f03c04000004eb7b28a2b691b3a 8f5c440dc058b7bf667f5e30add04491 fpscr=00000000
+vrinta.f32.f32 s6, s18 739cd2cfa8e00964a2de85ca2a8a1d43 1e77f1a9d554d08ceb087e3d18001e35 739cd2cfd554d08ca2de85ca2a8a1d43 1e77f1a9d554d08ceb087e3d18001e35 fpscr=00000000
+vrinta.f32.f32 s6, s18 8b7ac01f2b821296d9929c429240f14a 534bf150dd23063f4e64b6bccc19d025 8b7ac01fdd23063fd9929c429240f14a 534bf150dd23063f4e64b6bccc19d025 fpscr=00000000
+vrinta.f32.f32 s6, s18 ec8cd7a582522e4058d7b0b9e985677f 66961019c6bc24bf0f5d028cdaebd4fb ec8cd7a5c6bc240058d7b0b9e985677f 66961019c6bc24bf0f5d028cdaebd4fb fpscr=00000000
+vrinta.f32.f32 s6, s18 4a0bac30e094b43f4588e1795b7b0c18 0436654354e25637c990ac4a9284c4ef 4a0bac3054e256374588e1795b7b0c18 0436654354e25637c990ac4a9284c4ef fpscr=00000000
+vrinta.f32.f32 s6, s18 f92ec8b0e03b2c7356c61b9133fb39ad ab41fedea0d9ee5ecfc73e383c286951 f92ec8b08000000056c61b9133fb39ad ab41fedea0d9ee5ecfc73e383c286951 fpscr=00000000
+vrinta.f32.f32 s6, s18 e33b350f1b1e78b80d44ddebad036d7a ee7a73d27a7e1b1aa9ab4882b8a5a97b e33b350f7a7e1b1a0d44ddebad036d7a ee7a73d27a7e1b1aa9ab4882b8a5a97b fpscr=00000000
+vrintp.f32.f32 s9, s21 dd7661f1210155c84a755e5532061f7a 8f284e41a0b9728872df17e5fd0d530f dd7661f1210155c872df17e532061f7a 8f284e41a0b9728872df17e5fd0d530f fpscr=00000000
+vrintp.f32.f32 s9, s21 5eef6454ce8749f4439d1253e713da65 7e4b5d51e3575a6119723db374c6d29e 5eef6454ce8749f43f800000e713da65 7e4b5d51e3575a6119723db374c6d29e fpscr=00000000
+vrintp.f32.f32 s9, s21 932ca509fefce1c7d9bb93e6a8edcb8f b631df51203e61c07cb7013b3a07b6b2 932ca509fefce1c77cb7013ba8edcb8f b631df51203e61c07cb7013b3a07b6b2 fpscr=00000000
+vrintp.f32.f32 s9, s21 d8bbe517a5045b814e59e7285df1a0a8 fd70933b220362496678ad8e3ba8232f d8bbe517a5045b816678ad8e5df1a0a8 fd70933b220362496678ad8e3ba8232f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintp.f32.f32 s9, s21 8aa09ef58aa09ef55c3c1fc5ade8d456 d7518138a2a25be29baf7093bda8305a 8aa09ef58aa09ef580000000ade8d456 d7518138a2a25be29baf7093bda8305a fpscr=00000000
+vrintp.f32.f32 s9, s21 cd5e43a2cdabbe58e74eaaed696118b2 7ba3530a73ef880f9499b9e7e9ef7f40 cd5e43a2cdabbe5880000000696118b2 7ba3530a73ef880f9499b9e7e9ef7f40 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[0]
+vrintp.f32.f32 s9, s21 150fcccf530f2874150fcccf1822f7df aa68eb50b4b851cb8c981b47c10a3344 150fcccf530f2874800000001822f7df aa68eb50b4b851cb8c981b47c10a3344 fpscr=00000000
+vrintp.f32.f32 s9, s21 03211377023a745fc44e0973e2bd1b59 404b438a209b2dcc64428ea5d493a6a6 03211377023a745f64428ea5e2bd1b59 404b438a209b2dcc64428ea5d493a6a6 fpscr=00000000
+vrintp.f32.f32 s9, s21 2d2efbe332d8b4acb5ff3e78bdd9d99a 65ebc080ecaa8f2d38ef6974df434a68 2d2efbe332d8b4ac3f800000bdd9d99a 65ebc080ecaa8f2d38ef6974df434a68 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintp.f32.f32 s9, s21 344bdf1079837789b546cf313ec5b29c e6152a4087a63851e6152a407850be3f 344bdf1079837789e6152a403ec5b29c e6152a4087a63851e6152a407850be3f fpscr=00000000
+vrintp.f32.f32 s9, s21 a541a08d0c5cf6eeeb885706fa856ccc 56539287a37c8749b4b6de2bf5a08f6c a541a08d0c5cf6ee80000000fa856ccc 56539287a37c8749b4b6de2bf5a08f6c fpscr=00000000
+vrintp.f32.f32 s9, s21 4f468fcf3af2be35bc1e67956cbda616 b0c5040af390a4fb915049197a0fc95a 4f468fcf3af2be35800000006cbda616 b0c5040af390a4fb915049197a0fc95a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintp.f32.f32 s9, s21 b5a813be3c6c5e98e1eb89173062689f c803af3dc80ddcd697d5d655d05fe531 b5a813be3c6c5e98800000003062689f c803af3dc80ddcd697d5d655d05fe531 fpscr=00000000
+vrintp.f32.f32 s9, s21 75c089bc705a88db368b4860b831788d 08a015d99e0bc549d9a35596303540a9 75c089bc705a88dbd9a35596b831788d 08a015d99e0bc549d9a35596303540a9 fpscr=00000000
+vrintp.f32.f32 s9, s21 f350ed38fdbc9cf28edd413bdb3fd042 8fa2a9e858e80287744da56333a9baaf f350ed38fdbc9cf2744da563db3fd042 8fa2a9e858e80287744da56333a9baaf fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintp.f32.f32 s9, s21 73ba1d7cef1df09e08ccbb536ffa5c3e 6bee80cd9b85f7da4020e4d71539dcc9 73ba1d7cef1df09e404000006ffa5c3e 6bee80cd9b85f7da4020e4d71539dcc9 fpscr=00000000
+vrintp.f32.f32 s9, s21 2861304cdb5e623341b8898513848b7a 52fc7b7d7ac5096ddb0dce5d9983a2a8 2861304cdb5e6233db0dce5d13848b7a 52fc7b7d7ac5096ddb0dce5d9983a2a8 fpscr=00000000
+vrintp.f32.f32 s9, s21 445ce00bdb3791d3f7efd5067a832269 4f7329b39116dfaf3b033c48c77b088d 445ce00bdb3791d33f8000007a832269 4f7329b39116dfaf3b033c48c77b088d fpscr=00000000
+vrintp.f32.f32 s9, s21 b6aa190551c8c5279d092605ab45e5e0 68c93aac46ce24f7fca6f71295aa2b45 b6aa190551c8c527fca6f712ab45e5e0 68c93aac46ce24f7fca6f71295aa2b45 fpscr=00000000
+vrintp.f32.f32 s9, s21 bdf3b85110095b66fda2bc57a6cbdc80 fcde961b5313c4b9949fe1e9d3616c58 bdf3b85110095b6680000000a6cbdc80 fcde961b5313c4b9949fe1e9d3616c58 fpscr=00000000
+vrintp.f32.f32 s9, s21 e480b556bb0e92dadf5ad1ad76b4294e ca17f543bb411a69115337606b72831a e480b556bb0e92da3f80000076b4294e ca17f543bb411a69115337606b72831a fpscr=00000000
+vrintp.f32.f32 s9, s21 d4e4becf36a08b5ad4a031caee961a93 645992fe93eaf368cbff00050b5a6585 d4e4becf36a08b5acbff0005ee961a93 645992fe93eaf368cbff00050b5a6585 fpscr=00000000
+vrintp.f32.f32 s9, s21 75aef41b3b5aa6ef5d094c91160f8240 5ca27e8ff621e031a0b191d5911cd3b0 75aef41b3b5aa6ef80000000160f8240 5ca27e8ff621e031a0b191d5911cd3b0 fpscr=00000000
+vrintp.f32.f32 s9, s21 b7ef6e6af06a08bf5210d7fadc2da588 720f2175906876870c4344f3acf4aea4 b7ef6e6af06a08bf3f800000dc2da588 720f2175906876870c4344f3acf4aea4 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[1]
+vrintp.f32.f32 s9, s21 93aab306afb41f95abf9a070afb41f95 1f8d8f2607e9be421f8d8f26d9fc079f 93aab306afb41f953f800000afb41f95 1f8d8f2607e9be421f8d8f26d9fc079f fpscr=00000000
+vrintp.f32.f32 s9, s21 bc07cd4615cda43e6ee6e275e683a392 eee60eb932dd01457370523c7aeb40f1 bc07cd4615cda43e7370523ce683a392 eee60eb932dd01457370523c7aeb40f1 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintp.f32.f32 s9, s21 eae17f6b85b1538585b1538565c113dd e7a1357242b0e8e21bd5bd2e3b551211 eae17f6b85b153853f80000065c113dd e7a1357242b0e8e21bd5bd2e3b551211 fpscr=00000000
+vrintp.f32.f32 s9, s21 13397f35d2f05695c5edadc31f641809 3d624b3e14ab1e6b4a35a6584c7bc8f5 13397f35d2f056954a35a6581f641809 3d624b3e14ab1e6b4a35a6584c7bc8f5 fpscr=00000000
+vrintp.f32.f32 s9, s21 6e2b1efb02e3e2e1c7cb8a47defe8a11 5c5da2ed4f0ff5d957e02b43e105f47f 6e2b1efb02e3e2e157e02b43defe8a11 5c5da2ed4f0ff5d957e02b43e105f47f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vrintp.f32.f32 s9, s21 fa41f90bd66cfc55ba851b400d1ebeda 6250d6e75fae363b30f84cab1b96263f fa41f90bd66cfc553f8000000d1ebeda 6250d6e75fae363b30f84cab1b96263f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[0]
+vrintp.f32.f32 s9, s21 c44682d550c18858b85fd82b50c18858 8cbe6a27f6cd565c787fb490787fb490 c44682d550c18858787fb49050c18858 8cbe6a27f6cd565c787fb490787fb490 fpscr=00000000
+vrintp.f32.f32 s9, s21 ab76f64aaaa7b2cd02802c15b173def9 dbaf866aba6aee485af9f30b32f9a36b ab76f64aaaa7b2cd5af9f30bb173def9 dbaf866aba6aee485af9f30b32f9a36b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintp.f32.f32 s9, s21 db6845ba47afad015c4d4c6812da09ba c8e75cfc3111a1f0c8e75cfc94f4c814 db6845ba47afad01c8e75ce012da09ba c8e75cfc3111a1f0c8e75cfc94f4c814 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintp.f32.f32 s9, s21 20f97b5549e061275560010503b90610 91ade7b987a847de5c082de991ade7b9 20f97b5549e061275c082de903b90610 91ade7b987a847de5c082de991ade7b9 fpscr=00000000
+vrintp.f32.f32 s9, s21 9835015379582e6aeb790973ecc0f915 0b12844168fa172c9499456adcb16ec1 9835015379582e6a80000000ecc0f915 0b12844168fa172c9499456adcb16ec1 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintp.f32.f32 s9, s21 c072879b7d6c4d77c9d17ec5a616b402 ff4667da5a9c338a9655f9db545e32af c072879b7d6c4d7780000000a616b402 ff4667da5a9c338a9655f9db545e32af fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vrintp.f32.f32 s9, s21 43582530d8c46b48bbccf81743582530 759c1ec003333a41e0cc4ca14d207518 43582530d8c46b48e0cc4ca143582530 759c1ec003333a41e0cc4ca14d207518 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[3]
+vrintp.f32.f32 s9, s21 9471db94bd08140ddb5aea303fd83a45 567bfb5dc325e1fc89f328fc89f328fc 9471db94bd08140d800000003fd83a45 567bfb5dc325e1fc89f328fc89f328fc fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[0]
+vrintp.f32.f32 s9, s21 196518081965180834074d37c20af3f1 4847669dd875a6c8b190a5c32f12c9de 196518081965180880000000c20af3f1 4847669dd875a6c8b190a5c32f12c9de fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintp.f32.f32 s9, s21 a4f119ffefc9cbf94088331689e7e94c 7b795c93a184d944dd0fb55350d546cb a4f119ffefc9cbf9dd0fb55389e7e94c 7b795c93a184d944dd0fb55350d546cb fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintp.f32.f32 s9, s21 62468851d95e7e84d95e7e8497081db2 b73a5378629cf7d1f64d1ea98aa130f1 62468851d95e7e84f64d1ea997081db2 b73a5378629cf7d1f64d1ea98aa130f1 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+vrintp.f32.f32 s9, s21 cfb0aeecc3f4c6947d6372cbc3f4c694 968c9d940de060bb0de060bb2822a70c cfb0aeecc3f4c6943f800000c3f4c694 968c9d940de060bb0de060bb2822a70c fpscr=00000000
+vrintp.f32.f32 s9, s21 17b15a5bf2ee28136e0c6517245c4e67 06ffd511230d17a368df696f4993ac35 17b15a5bf2ee281368df696f245c4e67 06ffd511230d17a368df696f4993ac35 fpscr=00000000
+randV128: 11776 calls, 12159 iters
+vrintp.f32.f32 s9, s21 2d10d5621071d7f36033a881df22770b 75797043bbcfed77071c1a32d213594f 2d10d5621071d7f33f800000df22770b 75797043bbcfed77071c1a32d213594f fpscr=00000000
+vrintp.f32.f32 s9, s21 905c40d9391822260747fb4fb5e12834 ee027c1df8029d42cab494db67aa7d99 905c40d939182226cab494dab5e12834 ee027c1df8029d42cab494db67aa7d99 fpscr=00000000
+vrintp.f32.f32 s9, s21 92b8040baea21a9474f64725130eaa9e f1091f21ecccc7fe8f6b77f55bd5676d 92b8040baea21a9480000000130eaa9e f1091f21ecccc7fe8f6b77f55bd5676d fpscr=00000000
+vrintp.f32.f32 s9, s21 c1fb3113ecb42cd0e4630236c7b54d4d 499724b5d633d0eab5422065b367888e c1fb3113ecb42cd080000000c7b54d4d 499724b5d633d0eab5422065b367888e fpscr=00000000
+vrintp.f32.f32 s9, s21 d35d5c58e0dc9b511ae74d6670a61662 3a22a43f2cc5481489e850a52546126e d35d5c58e0dc9b518000000070a61662 3a22a43f2cc5481489e850a52546126e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintp.f32.f32 s9, s21 b8fdfa018f553ef1106b8d66fbb1472c 4a2543a24a2543a2c23d31726a0aff30 b8fdfa018f553ef1c23c0000fbb1472c 4a2543a24a2543a2c23d31726a0aff30 fpscr=00000000
+vrintp.f32.f32 s9, s21 de40afda773d6c807842e8eb7ad016c6 1583992e7989af8e322359b0550ffff2 de40afda773d6c803f8000007ad016c6 1583992e7989af8e322359b0550ffff2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintm.f32.f32 s12, s12 c1350f8d8ad4ab38106b382a66401ad8 353fd41d99b4fd24aac0d79a353fd41d 353fd41d99b4fd24aac0d79a00000000 353fd41d99b4fd24aac0d79a00000000 fpscr=00000000
+vrintm.f32.f32 s12, s12 0f38a18125d81c47d8811f4e46e4b5e8 033542abcb1c6217d98ec9075f3281bb 033542abcb1c6217d98ec9075f3281bb 033542abcb1c6217d98ec9075f3281bb fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintm.f32.f32 s12, s12 365e5a3fcd9c29bfa912fe95a912fe95 607f64f2fcedeb602560bd29d9ced4c3 607f64f2fcedeb602560bd29d9ced4c3 607f64f2fcedeb602560bd29d9ced4c3 fpscr=00000000
+vrintm.f32.f32 s12, s12 a5035cae929b11a27c3eb4c0b7ef87c5 3bba4a932b31bf4ef04413aca052b809 3bba4a932b31bf4ef04413acbf800000 3bba4a932b31bf4ef04413acbf800000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintm.f32.f32 s12, s12 621c9b9e7cc53b237cc53b230344a304 485461e1edb83a04103d9add4fd803b7 485461e1edb83a04103d9add4fd803b7 485461e1edb83a04103d9add4fd803b7 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintm.f32.f32 s12, s12 729425a026e0714ac1ac337a3ec5254c 440f31524d952ad29cad24e6440f3152 440f31524d952ad29cad24e6440f0000 440f31524d952ad29cad24e6440f0000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintm.f32.f32 s12, s12 3f9dc9e6a28ffa0470c615645da159ad 16932442ed45cc1eb0e74a8f83d98c8d 16932442ed45cc1eb0e74a8fbf800000 16932442ed45cc1eb0e74a8fbf800000 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintm.f32.f32 s12, s12 22cdd51e3836f1256a827c0052b276ac 84fea6491e15c1481e15c148c174c4ef 84fea6491e15c1481e15c148c1800000 84fea6491e15c1481e15c148c1800000 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintm.f32.f32 s12, s12 fd83f1cf4ba92d67a7b18e1fda58c843 3c87600fd49f1ff2766087d92f068ab0 3c87600fd49f1ff2766087d900000000 3c87600fd49f1ff2766087d900000000 fpscr=00000000
+vrintm.f32.f32 s12, s12 47be2209922b59b24adac4039bf924d9 d829381bb7a6836717a744390f2f5c04 d829381bb7a6836717a7443900000000 d829381bb7a6836717a7443900000000 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintm.f32.f32 s12, s12 261ebea9eefb5d3e99349c5c2ab2d3f3 4459663aabe799e1ae03d9b158330920 4459663aabe799e1ae03d9b158330920 4459663aabe799e1ae03d9b158330920 fpscr=00000000
+vrintm.f32.f32 s12, s12 2e5721325f52c6df377c7e9e19105891 5aff7150324311ea1a82819473cb8b12 5aff7150324311ea1a82819473cb8b12 5aff7150324311ea1a82819473cb8b12 fpscr=00000000
+vrintm.f32.f32 s12, s12 ebc6df674f83504934a356e305be33ac a33a2f40c8b99f809091764995a2c11b a33a2f40c8b99f8090917649bf800000 a33a2f40c8b99f8090917649bf800000 fpscr=00000000
+vrintm.f32.f32 s12, s12 55f95c9c2141966ee89b7bc4c2e9d6c5 789b51210ad8095cd9a351a62cd1e80f 789b51210ad8095cd9a351a600000000 789b51210ad8095cd9a351a600000000 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintm.f32.f32 s12, s12 e3c81c8d7c8836e84c5e181fd8fe8403 5b7ff0cfbcf275fc3aa39dbcec9ce6a0 5b7ff0cfbcf275fc3aa39dbcec9ce6a0 5b7ff0cfbcf275fc3aa39dbcec9ce6a0 fpscr=00000000
+vrintm.f32.f32 s12, s12 3f6186be5097a77550cbf7ce88854d7c 8af1cbf0f14895b2bf584e55e848937d 8af1cbf0f14895b2bf584e55e848937d 8af1cbf0f14895b2bf584e55e848937d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vrintm.f32.f32 s12, s12 e5734572c4993f399427fc4fe5734572 9857a2610acade22aa50f56c03afd45f 9857a2610acade22aa50f56c00000000 9857a2610acade22aa50f56c00000000 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[0]
+vrintm.f32.f32 s12, s12 fe06568ec6debf3db23cda722cf3a8b8 23ae0418feea42b817d534b623ae0418 23ae0418feea42b817d534b600000000 23ae0418feea42b817d534b600000000 fpscr=00000000
+vrintm.f32.f32 s12, s12 537e88ba7538282edcfd874e6b9c86de f73c3f475ccc1cd92fb80a0f6eeab27d f73c3f475ccc1cd92fb80a0f6eeab27d f73c3f475ccc1cd92fb80a0f6eeab27d fpscr=00000000
+vrintm.f32.f32 s12, s12 81488577b949200357a76023e7492273 29f3c9dcb37791332020518e1a0972c7 29f3c9dcb37791332020518e00000000 29f3c9dcb37791332020518e00000000 fpscr=00000000
+vrintm.f32.f32 s12, s12 5f6601268f65b222e8f45d5c33af9fd4 7166ba5a9a691fe5cf749bfd0de67703 7166ba5a9a691fe5cf749bfd00000000 7166ba5a9a691fe5cf749bfd00000000 fpscr=00000000
+vrintm.f32.f32 s12, s12 f6afa0b7aed59cd261aeb2a9aa11be85 765021d9a385631df6277cee024a821c 765021d9a385631df6277cee00000000 765021d9a385631df6277cee00000000 fpscr=00000000
+vrintm.f32.f32 s12, s12 cb1bbc6b9fb32f1f9801a3c3dca3e509 19ac85023f483be28cf83ab4c9bf675f 19ac85023f483be28cf83ab4c9bf6760 19ac85023f483be28cf83ab4c9bf6760 fpscr=00000000
+vrintm.f32.f32 s12, s12 8459276a640e0d51a941289e8cca2f0e fb3c731b47c928a5f5ba57ac440fa5a7 fb3c731b47c928a5f5ba57ac440f8000 fb3c731b47c928a5f5ba57ac440f8000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintm.f32.f32 s12, s12 28855704d732a44b74396dcd753bec15 f463d8fa71a1505d71a1505d7a065699 f463d8fa71a1505d71a1505d7a065699 f463d8fa71a1505d71a1505d7a065699 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintm.f32.f32 s12, s12 ad7f7e5fad7f7e5fc3589d14710c6d0e 61c85d204931f9ed00f9407ca8caa205 61c85d204931f9ed00f9407cbf800000 61c85d204931f9ed00f9407cbf800000 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintm.f32.f32 s12, s12 c2ec4c677062551dacadb1372d50b9a8 518f073e8f6387b080f48e488f6387b0 518f073e8f6387b080f48e48bf800000 518f073e8f6387b080f48e48bf800000 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[2]
+vrintm.f32.f32 s12, s12 131777db159db432a307c0c3159db432 f1512819f15128191518b3ce62201e88 f1512819f15128191518b3ce62201e88 f1512819f15128191518b3ce62201e88 fpscr=00000000
+vrintm.f32.f32 s12, s12 a2e5feb98f375e4e3195f117366d9c41 abc15b3e5fa3fc5eef80de95e87fe406 abc15b3e5fa3fc5eef80de95e87fe406 abc15b3e5fa3fc5eef80de95e87fe406 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintm.f32.f32 s12, s12 38a0e70b011ad91b35fbf1f7713cdcbc 18d647fa89789eeffa8a0a5ce9626136 18d647fa89789eeffa8a0a5ce9626136 18d647fa89789eeffa8a0a5ce9626136 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintm.f32.f32 s12, s12 ee3fd612df862574205e16af3fe7f4cb b58abcc0fc3f3fe260a4f01e5ba25841 b58abcc0fc3f3fe260a4f01e5ba25841 b58abcc0fc3f3fe260a4f01e5ba25841 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintm.f32.f32 s12, s12 92f138d8a871f552bb506f3626bf92c2 0895b8b6a3c80ae905050c9374bb8880 0895b8b6a3c80ae905050c9374bb8880 0895b8b6a3c80ae905050c9374bb8880 fpscr=00000000
+vrintm.f32.f32 s12, s12 271840206cd6b3c192db9f895181f37b 071117d642e258c5652b7d565a9542d4 071117d642e258c5652b7d565a9542d4 071117d642e258c5652b7d565a9542d4 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintm.f32.f32 s12, s12 4916622ad98a51864916622a8ebf0665 55c91ab47f49cb16141d9cd629bac3ba 55c91ab47f49cb16141d9cd600000000 55c91ab47f49cb16141d9cd600000000 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintm.f32.f32 s12, s12 56334540c96c541a8fdd8a2acd1cf75e 337dd953a13c8e5839a26b929787bd94 337dd953a13c8e5839a26b92bf800000 337dd953a13c8e5839a26b92bf800000 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintm.f32.f32 s12, s12 5c496500f505facc7714aae96fee2774 170822eb13bc095edce3e59a13bc095e 170822eb13bc095edce3e59a00000000 170822eb13bc095edce3e59a00000000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintm.f32.f32 s12, s12 ecb79f44371a6497371a6497f98afde7 a7282a4c5bab80f5b636745bbe50cc4d a7282a4c5bab80f5b636745bbf800000 a7282a4c5bab80f5b636745bbf800000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintm.f32.f32 s12, s12 7dd85c6ac8530df4c8530df43580da3f 8ed9edbdfc14c3fb75cf5852bf54a59b 8ed9edbdfc14c3fb75cf5852bf800000 8ed9edbdfc14c3fb75cf5852bf800000 fpscr=00000000
+vrintm.f32.f32 s12, s12 35d2af9c919d65eb206461f8e2232e2d b8864dd69489332910cf8e232df23b64 b8864dd69489332910cf8e2300000000 b8864dd69489332910cf8e2300000000 fpscr=00000000
+vrintm.f32.f32 s12, s12 842ebe324fc344924420f73236725b0c f7de7e6a973e1903e034c689ae9098ba f7de7e6a973e1903e034c689bf800000 f7de7e6a973e1903e034c689bf800000 fpscr=00000000
+vrintm.f32.f32 s12, s12 b6c21f81e612c1d00356bcf8bbd805aa bf86755dddf239bd3ca8006b553a863e bf86755dddf239bd3ca8006b553a863e bf86755dddf239bd3ca8006b553a863e fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintm.f32.f32 s12, s12 fc53a608a1eab2dc77c7ccdcb16c76ae cded29c6cded29c6e6cebdf28622e26c cded29c6cded29c6e6cebdf2bf800000 cded29c6cded29c6e6cebdf2bf800000 fpscr=00000000
+vrintm.f32.f32 s12, s12 66570e9e6936d90d2483b2f1d483982d 598fc69a7ccc5e30594fefdb31b0f3d2 598fc69a7ccc5e30594fefdb00000000 598fc69a7ccc5e30594fefdb00000000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintm.f32.f32 s12, s12 12e45ca17b8dcc16bf633294150848b6 7733b7e70cf3395b4e257ac14e257ac1 7733b7e70cf3395b4e257ac14e257ac1 7733b7e70cf3395b4e257ac14e257ac1 fpscr=00000000
+vrintm.f32.f32 s12, s12 86d0785c6d15dfbdb0d2202f2a65b1a7 77239f28b78f34140c831cec4908c361 77239f28b78f34140c831cec4908c360 77239f28b78f34140c831cec4908c360 fpscr=00000000
+vrintm.f32.f32 s12, s12 1130e069bac1f3b5df9cb6a5049d75a4 a129d0241d888a7d9093481123c2ddec a129d0241d888a7d9093481100000000 a129d0241d888a7d9093481100000000 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintm.f32.f32 s12, s12 f576068d90bea9d0c67eca526bf9dc4b f4dac128bf2836ac467dd82785e849d6 f4dac128bf2836ac467dd827bf800000 f4dac128bf2836ac467dd827bf800000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintm.f32.f32 s12, s12 d651e2e906f6709841f3fc46183864ce e4fedc9748d6bfd727624ca91e1384b5 e4fedc9748d6bfd727624ca900000000 e4fedc9748d6bfd727624ca900000000 fpscr=00000000
+vrintm.f32.f32 s12, s12 e3aacf52b02d839e971efa440994346d 283db81f212f6a3631d3648a4bf8bd01 283db81f212f6a3631d3648a4bf8bd01 283db81f212f6a3631d3648a4bf8bd01 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintm.f32.f32 s12, s12 43797fe769c63c89fa7f928e7cd7e2ce d8fac5b6f7e9761318ae614a18ae614a d8fac5b6f7e9761318ae614a00000000 d8fac5b6f7e9761318ae614a00000000 fpscr=00000000
+vmaxnm.f32 d15,d16,d20 9429182ae250990097babcea1cd03a88 9886929a9c6e483612844b6ad8d38bae 2ba9aff5af5bd454521218ff58f4a0dd 521218ff58f4a0dd97babcea1cd03a88 9886929a9c6e483612844b6ad8d38bae 2ba9aff5af5bd454521218ff58f4a0dd fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vmaxnm.f32 d15,d16,d20 8d11418bc55da54110ae660c90a95a06 97935a052a97593c38208726ed1791ab 95d3b3c8767d85b0ee506dc8dcc33763 38208726dcc3376310ae660c90a95a06 97935a052a97593c38208726ed1791ab 95d3b3c8767d85b0ee506dc8dcc33763 fpscr=00000000
+vmaxnm.f32 d15,d16,d20 1bd65ad797754ddf6143662b17b4f2dd a3219d5dd4a4f91fd8de70d05ecb74a4 6e7b920237d03500dbbcb6fb44ef8e01 d8de70d05ecb74a46143662b17b4f2dd a3219d5dd4a4f91fd8de70d05ecb74a4 6e7b920237d03500dbbcb6fb44ef8e01 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vmaxnm.f32 d15,d16,d20 a14fe66dc8329a2516714cbba14fe66d 5d78c087b055d5be60d531d9b858f81e 0ff1fd02f9086031d18ae2b50ff1fd02 60d531d90ff1fd0216714cbba14fe66d 5d78c087b055d5be60d531d9b858f81e 0ff1fd02f9086031d18ae2b50ff1fd02 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vmaxnm.f32 d15,d16,d20 d7f374e27e0bae2fae3881cb7a98c692 991ceaf53cf40d67ac65acf0787d06f3 25bd24bc4786ed156b0c9dcab3025cd7 6b0c9dca787d06f3ae3881cb7a98c692 991ceaf53cf40d67ac65acf0787d06f3 25bd24bc4786ed156b0c9dcab3025cd7 fpscr=00000000
+randV128: 12032 calls, 12424 iters
+randV128: doing v->u32[0] = v->u32[1]
+vmaxnm.f32 d15,d16,d20 32c414ad795aa32c596443350875a2ba e3ab30d70fab55cdcc7627fe960f64ef f8d3e4381b5cf17d670ff9db670ff9db 670ff9db670ff9db596443350875a2ba e3ab30d70fab55cdcc7627fe960f64ef f8d3e4381b5cf17d670ff9db670ff9db fpscr=00000000
+vmaxnm.f32 d15,d16,d20 21ed3ce3404dbde2930b87b1bd942384 6f3f5b270440b990b5abddf791bf6f0d cfc0533fbc64a010f0c24902e52e4aa0 b5abddf791bf6f0d930b87b1bd942384 6f3f5b270440b990b5abddf791bf6f0d cfc0533fbc64a010f0c24902e52e4aa0 fpscr=00000000
+vmaxnm.f32 d15,d16,d20 a9ed0eea3e3054c3c4077d0ba6113c87 ac6fffdc5a000229c0a12ddeda362651 77ed80fb0d0a637fdb8c4402335c9fd7 c0a12dde335c9fd7c4077d0ba6113c87 ac6fffdc5a000229c0a12ddeda362651 77ed80fb0d0a637fdb8c4402335c9fd7 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[2]
+vmaxnm.f32 d15,d16,d20 b98a57db51167f870a88b5a8412baae6 a7c22fd9b551394c341a6e00ebed8de7 8ac7e7000882bdbd0882bdbd59dad998 341a6e0059dad9980a88b5a8412baae6 a7c22fd9b551394c341a6e00ebed8de7 8ac7e7000882bdbd0882bdbd59dad998 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+vmaxnm.f32 d15,d16,d20 5dae0f3178a0e74fbd470dc478a0e74f bd521d4c8a552b13c305f582e698373f 3eb797e326f98e713e9ad5ae798ee349 3e9ad5ae798ee349bd470dc478a0e74f bd521d4c8a552b13c305f582e698373f 3eb797e326f98e713e9ad5ae798ee349 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vmaxnm.f32 d15,d16,d20 f822baf50afa8a96a0723b5d090e4e59 db0aecc9ec1da68c0091fc5dd0d95933 1e6204d410bc321e89693d572f4dda70 0091fc5d2f4dda70a0723b5d090e4e59 db0aecc9ec1da68c0091fc5dd0d95933 1e6204d410bc321e89693d572f4dda70 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vmaxnm.f32 d15,d16,d20 8c02fc3f182ecea363ddccfda45a73a7 e90fb36af91d836da05ad169f9f1df98 2ebef630dc9373f58aa8ee4baacfa509 8aa8ee4baacfa50963ddccfda45a73a7 e90fb36af91d836da05ad169f9f1df98 2ebef630dc9373f58aa8ee4baacfa509 fpscr=00000000
+vmaxnm.f32 d15,d16,d20 f424534fce111a1bee8a4ca9111c8aa4 7185e05991a2e3fce4a96d68fae2c489 c02d7f16d40c8a9563f1d5665e36daa6 63f1d5665e36daa6ee8a4ca9111c8aa4 7185e05991a2e3fce4a96d68fae2c489 c02d7f16d40c8a9563f1d5665e36daa6 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vmaxnm.f32 d15,d16,d20 3ef850850ea6ad7ec9992199c2c85237 245272db78efbfd99bec679dae761184 d1a6c03f48b87d0be8ee15a215913182 9bec679d15913182c9992199c2c85237 245272db78efbfd99bec679dae761184 d1a6c03f48b87d0be8ee15a215913182 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[1]
+vmaxnm.f32 d15,d16,d20 d299613d37c638b725e3bcf2c6f3232e f75012201e8c3b5bcc3d58d204f8f581 4af863b224b08d08eaafdf775171f92f cc3d58d25171f92f25e3bcf2c6f3232e f75012201e8c3b5bcc3d58d204f8f581 4af863b224b08d08eaafdf775171f92f fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vmaxnm.f32 d15,d16,d20 e18c253f8b0a46d84cfbc5e9d16f9097 8fdda124a6ea567cd688843c8fdda124 86a10e3e0dee6e820d18c8cd57362328 0d18c8cd573623284cfbc5e9d16f9097 8fdda124a6ea567cd688843c8fdda124 86a10e3e0dee6e820d18c8cd57362328 fpscr=00000000
+vmaxnm.f32 d15,d16,d20 d89c42c60812524c0f7f663b1bc471b6 b240803cda9573ac730696154abe769b 27bba58b8b1f1f0252fbde9accae2440 730696154abe769b0f7f663b1bc471b6 b240803cda9573ac730696154abe769b 27bba58b8b1f1f0252fbde9accae2440 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[2]
+vmaxnm.f32 d15,d16,d20 b6234b6f0aca4525b6234b6fb60d5a16 9cb3ce95a4bdb65d78bd7b18fc385ca1 2cecb47e840ca8acca03cdab2cecb47e 78bd7b182cecb47eb6234b6fb60d5a16 9cb3ce95a4bdb65d78bd7b18fc385ca1 2cecb47e840ca8acca03cdab2cecb47e fpscr=00000000
+vmaxnm.f32 d15,d16,d20 04eb23b1eda89eb80d7a68ccd8029ad3 d7dbf8067078e6d0bc1a29cda619d2fa c6e9a4e176356485753e4cab71343af7 753e4cab71343af70d7a68ccd8029ad3 d7dbf8067078e6d0bc1a29cda619d2fa c6e9a4e176356485753e4cab71343af7 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vmaxnm.f32 d15,d16,d20 2ef255a3e553788ee553788e28db04af 2c95fb469d2b6afbb67100619e1495d0 19443419731d349210fbc4bb0f1a2a4c 10fbc4bb0f1a2a4ce553788e28db04af 2c95fb469d2b6afbb67100619e1495d0 19443419731d349210fbc4bb0f1a2a4c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+vmaxnm.f32 d15,d16,d20 fec024cc1d51ec593d346ad61d51ec59 13c0733071afd05171afd051d98c6d1d 0b25cee1393bd63e6d22b28c9cfd1ad8 71afd0519cfd1ad83d346ad61d51ec59 13c0733071afd05171afd051d98c6d1d 0b25cee1393bd63e6d22b28c9cfd1ad8 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vmaxnm.f32 d15,d16,d20 df01369d6192b282d192020b6192b282 bcc85d8ecaa17a098329a55c5cfecf99 3bbd27fd813db871cf3fbd97743fae14 8329a55c743fae14d192020b6192b282 bcc85d8ecaa17a098329a55c5cfecf99 3bbd27fd813db871cf3fbd97743fae14 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vmaxnm.f32 d15,d16,d20 5bca9b084ab7d4d1675f979dad6f2056 384a161d02b1613fab5053abb54649c0 eab271415a8e503f5adfc4be4cadb5eb 5adfc4be4cadb5eb675f979dad6f2056 384a161d02b1613fab5053abb54649c0 eab271415a8e503f5adfc4be4cadb5eb fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vmaxnm.f32 d15,d16,d20 246ddd3e14083a0883122e6f52cf5fd3 f111dd8d14c4beea3a7d15463e5527fa 24b8c458e02adc89370899e4370899e4 3a7d15463e5527fa83122e6f52cf5fd3 f111dd8d14c4beea3a7d15463e5527fa 24b8c458e02adc89370899e4370899e4 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vmaxnm.f32 d15,d16,d20 d38f4dfad38f4dfa50ebdac87854f9c1 33e59695b099d0009686812325ab6f1f 4c8b2821e6264b41165816504951550a 165816504951550a50ebdac87854f9c1 33e59695b099d0009686812325ab6f1f 4c8b2821e6264b41165816504951550a fpscr=00000000
+vmaxnm.f32 d15,d16,d20 8371d547a6366729c62e0fd9576b3161 3cc640ed916c2d33a16a1f355aaefcae 7677092eae282d6914568959713828d8 14568959713828d8c62e0fd9576b3161 3cc640ed916c2d33a16a1f355aaefcae 7677092eae282d6914568959713828d8 fpscr=00000000
+vmaxnm.f32 d15,d16,d20 c52d6e6dfcbee08177d0c050cdcb3c18 ece528697dad25aab9dc3de134ccdf49 b294eac5fc5c85a4bb6fc80f63a9f11b b9dc3de163a9f11b77d0c050cdcb3c18 ece528697dad25aab9dc3de134ccdf49 b294eac5fc5c85a4bb6fc80f63a9f11b fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vmaxnm.f32 d15,d16,d20 2404668f9033dd433808fa6d4f5cec42 4e4b43308d6b1f739da90a6593977084 3ecac70ae125fd44e3415f1c9de90133 9da90a65939770843808fa6d4f5cec42 4e4b43308d6b1f739da90a6593977084 3ecac70ae125fd44e3415f1c9de90133 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[2]
+vmaxnm.f32 d15,d16,d20 8879c7c6637e46848879c7c651bafd0a 412033bd4d78c69df786127d56ca7832 7cf82a7639440d894aab654eb1c6e692 4aab654e56ca78328879c7c651bafd0a 412033bd4d78c69df786127d56ca7832 7cf82a7639440d894aab654eb1c6e692 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vmaxnm.f32 d15,d16,d20 f70b0e084e62b670537b5d91133d2660 bfcc58cedc80ee971a5c7e551a5c7e55 9aa2e6d65ae322c034c23beea5d8c4a3 34c23bee1a5c7e55537b5d91133d2660 bfcc58cedc80ee971a5c7e551a5c7e55 9aa2e6d65ae322c034c23beea5d8c4a3 fpscr=00000000
+vmaxnm.f32 d15,d16,d20 943166b359ebd1d3e262a64c4745fb9e 88e1a8887e9e80d4d4a732b83035f9a3 a4769097e234f188823e9e00ee588ce0 823e9e003035f9a3e262a64c4745fb9e 88e1a8887e9e80d4d4a732b83035f9a3 a4769097e234f188823e9e00ee588ce0 fpscr=00000000
+vmaxnm.f32 d15,d16,d20 2df82b1fad56fd9aa251cd5d38bb83e5 25ebe2dde927e1443a7b1c30760169ce dd0adc48c44a0bbb062fbe262a0e9584 3a7b1c30760169cea251cd5d38bb83e5 25ebe2dde927e1443a7b1c30760169ce dd0adc48c44a0bbb062fbe262a0e9584 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[3]
+vmaxnm.f32 d15,d16,d20 74524332448d91a728b5d9bcbaeb0ae9 0f8b09c4d2ea2e27d2ea2e272c52a281 a6c52a73947448f535676fee0a6da110 35676fee2c52a28128b5d9bcbaeb0ae9 0f8b09c4d2ea2e27d2ea2e272c52a281 a6c52a73947448f535676fee0a6da110 fpscr=00000000
+vmaxnm.f32 d15,d16,d20 b27ac3da0b9c7705b49f8ef37e73ace8 b189c58e22216b076f88abf83ec3e057 cedff95d485c6905dea2cf7bbaf701aa 6f88abf83ec3e057b49f8ef37e73ace8 b189c58e22216b076f88abf83ec3e057 cedff95d485c6905dea2cf7bbaf701aa fpscr=00000000
+vmaxnm.f32 d15,d16,d20 7cdeb58ed1ab0492a592f5b549c2f16c 39ac84ff7c8918b46dead156357ea5e6 d1a9d4357eee765b1e9b163efb3564be 6dead156357ea5e6a592f5b549c2f16c 39ac84ff7c8918b46dead156357ea5e6 d1a9d4357eee765b1e9b163efb3564be fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[3]
+vmaxnm.f32 d15,d16,d20 74bf3262de7d0dfd5c57f9a35c57f9a3 c203551ba3dd2faf41017e07dd3f7e6c b3b7d340547e43d75a1f86672a067d63 5a1f86672a067d635c57f9a35c57f9a3 c203551ba3dd2faf41017e07dd3f7e6c b3b7d340547e43d75a1f86672a067d63 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vmaxnm.f32 d15,d16,d20 0e4914c93cfbffc222b65513bc56de7d f69821ad33f5892ae027ccc78611352d d27847579b2005ba9b2005ba0a12b92c 9b2005ba0a12b92c22b65513bc56de7d f69821ad33f5892ae027ccc78611352d d27847579b2005ba9b2005ba0a12b92c fpscr=00000000
+vmaxnm.f32 d15,d16,d20 b869929d4471940abc62a003e20dc91e f61ce2c29d5aa3e5919fb6ef17a4b063 084953889bd616f9891e10d6df7a9494 891e10d617a4b063bc62a003e20dc91e f61ce2c29d5aa3e5919fb6ef17a4b063 084953889bd616f9891e10d6df7a9494 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[0]
+vmaxnm.f32 d15,d16,d20 43ff18eeb8a6740eddb9a19fb5eba9cb c32f0f4021800bbb21800bbb394cc51c 5fed098da2df78129b6111ee6d1cf3b5 21800bbb6d1cf3b5ddb9a19fb5eba9cb c32f0f4021800bbb21800bbb394cc51c 5fed098da2df78129b6111ee6d1cf3b5 fpscr=00000000
+vmaxnm.f32 d15,d16,d20 8a6851cdf14be812df82f606d313cd21 3b6a727913a9ccef57abd1ec21ec71fb b60b9b58364158fa361c08af532fc76e 57abd1ec532fc76edf82f606d313cd21 3b6a727913a9ccef57abd1ec21ec71fb b60b9b58364158fa361c08af532fc76e fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vmaxnm.f32 d15,d16,d20 3fba6d6eb3a7c0546f895160f6c43d3f 21b674ffc393b603dcc9f9ebc9340c5a ac22b90b20674d3987599b3c96a4f5eb 87599b3c96a4f5eb6f895160f6c43d3f 21b674ffc393b603dcc9f9ebc9340c5a ac22b90b20674d3987599b3c96a4f5eb fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vmaxnm.f32 d15,d16,d20 ba6bef434207a9ba612bcf6f9b3eef5a 4db2d14ab02942d08f7dbb0a567498fd 8bb7d515238dcb463c81f8d51234c2ba 3c81f8d5567498fd612bcf6f9b3eef5a 4db2d14ab02942d08f7dbb0a567498fd 8bb7d515238dcb463c81f8d51234c2ba fpscr=00000000
+vmaxnm.f32 d15,d16,d20 a9aaf2286533169145c6e6eeec484204 e5e9899ff0579c78b13349d8a137d72e b536444a0f4ac0878f98881e964c0fd5 8f98881e964c0fd545c6e6eeec484204 e5e9899ff0579c78b13349d8a137d72e b536444a0f4ac0878f98881e964c0fd5 fpscr=00000000
+vmaxnm.f32 d15,d16,d20 2e4b577c8f7d3cd444b197a7efda9a9b 394d7c040a81e0c52e29848b490c7745 ccdd3fb74184bb95b236b3afad6bae4e 2e29848b490c774544b197a7efda9a9b 394d7c040a81e0c52e29848b490c7745 ccdd3fb74184bb95b236b3afad6bae4e fpscr=00000000
+vmaxnm.f32 d15,d16,d20 afcfe17ee0c6d8042db32e3dcce0170a 1f21553545365b1ed9863fe12d14433b 49b054a8bda186f3b89cc7d34d0489a1 b89cc7d34d0489a12db32e3dcce0170a 1f21553545365b1ed9863fe12d14433b 49b054a8bda186f3b89cc7d34d0489a1 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vmaxnm.f32 d15,d16,d20 c9bf1a9c78eacac25d3cc6eefbff3e90 244d750d5ec75021db87f16ed82d9618 5ae74aba276ff27233fcf8ee276ff272 33fcf8ee276ff2725d3cc6eefbff3e90 244d750d5ec75021db87f16ed82d9618 5ae74aba276ff27233fcf8ee276ff272 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vmaxnm.f32 d15,d16,d20 0ac4ec069fe93ff81f8a1b0e8424deb6 2e08e267f05b988a8ca1de82417ef4b1 2bc31b41cf70530b7aa24c961951f606 7aa24c96417ef4b11f8a1b0e8424deb6 2e08e267f05b988a8ca1de82417ef4b1 2bc31b41cf70530b7aa24c961951f606 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: 12288 calls, 12689 iters
+vmaxnm.f32 d15,d16,d20 2b322c1f30bfd4062034743630bfd406 91dff5eb9bb7bcf91fe6d153f0157fce b520d40cb2b08c2a36819c0eebe24d0a 36819c0eebe24d0a2034743630bfd406 91dff5eb9bb7bcf91fe6d153f0157fce b520d40cb2b08c2a36819c0eebe24d0a fpscr=00000000
+vmaxnm.f32 d15,d16,d20 3b8c4833302e08edd0664fcb7e678fd5 8c7e0f851764cf0cf40abd4383a072c1 5b9f156203011bead0d83ed6cad91744 d0d83ed683a072c1d0664fcb7e678fd5 8c7e0f851764cf0cf40abd4383a072c1 5b9f156203011bead0d83ed6cad91744 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vmaxnm.f32 d15,d16,d20 027a8eb24fb9252ac361a716b70e746c cb32c6c4d34fd139d34fd139fb86b38f 7828904f3045661c41a53254de6aa03e 41a53254de6aa03ec361a716b70e746c cb32c6c4d34fd139d34fd139fb86b38f 7828904f3045661c41a53254de6aa03e fpscr=00000000
+vmaxnm.f32 q7, q8, q10 34dcde47d1475c29397668959126753e 38b1bc6a51338d198306c6e3e2987180 76cd23f4226ad0e9fedc2c55eb5c88b4 76cd23f451338d198306c6e3e2987180 38b1bc6a51338d198306c6e3e2987180 76cd23f4226ad0e9fedc2c55eb5c88b4 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 182430ffb768323bbce770c2565a2a4b da8c2e35606782404c9d57a39f30f28c c27cc265d7a7da4d6be169f9a9efe45e c27cc265606782406be169f99f30f28c da8c2e35606782404c9d57a39f30f28c c27cc265d7a7da4d6be169f9a9efe45e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vmaxnm.f32 q7, q8, q10 419b3f0d074c054f1c11424efb5ee111 ce864d28c9dca7ecc9dca7eca64f6d5c 8c77dd9de32dc8a22cc3f6af51cc5ea4 8c77dd9dc9dca7ec2cc3f6af51cc5ea4 ce864d28c9dca7ecc9dca7eca64f6d5c 8c77dd9de32dc8a22cc3f6af51cc5ea4 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[2]
+vmaxnm.f32 q7, q8, q10 d0e08219a273cb0a929528c7ba7b5015 d1cfe56648e2ad131bec16acd1cfe566 536ef05e77d94eb693dd8f153763d88e 536ef05e77d94eb61bec16ac3763d88e d1cfe56648e2ad131bec16acd1cfe566 536ef05e77d94eb693dd8f153763d88e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vmaxnm.f32 q7, q8, q10 bd145f60552c496a7a16c6db814dfeb3 9821d8ee08f20a33a4bc7f558456ac99 00971f74ced838021c001a7f00971f74 00971f7408f20a331c001a7f00971f74 9821d8ee08f20a33a4bc7f558456ac99 00971f74ced838021c001a7f00971f74 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[0]
+vmaxnm.f32 q7, q8, q10 58e6986ce63f9144529726efe63f9144 24ca7588fdb7198ba423f942fdb7198b f115c77e9ec45198f2e898e2595a56ab 24ca75889ec45198a423f942595a56ab 24ca7588fdb7198ba423f942fdb7198b f115c77e9ec45198f2e898e2595a56ab fpscr=00000000
+vmaxnm.f32 q7, q8, q10 dd9a725f760d93ebd87eeece494d87a8 c3b1d05f0a18e0b074959edb1ab94e8b 92a197cc9c421ac2bbff48b5aaca9ded 92a197cc0a18e0b074959edb1ab94e8b c3b1d05f0a18e0b074959edb1ab94e8b 92a197cc9c421ac2bbff48b5aaca9ded fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[1]
+vmaxnm.f32 q7, q8, q10 594976658ae250d4e11382e88a516b5f 0c24134dd6dec3eadede091e0306dc7d 26e214792dc5124626e214799c11c986 26e214792dc5124626e214790306dc7d 0c24134dd6dec3eadede091e0306dc7d 26e214792dc5124626e214799c11c986 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 fb6b4c9e837b719b3876278abf0447a6 9ade037108c0e145643630995654e6bf bf499cc73581930bcebc05fca5759180 9ade03713581930b643630995654e6bf 9ade037108c0e145643630995654e6bf bf499cc73581930bcebc05fca5759180 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 9fc14a5633e863961c6b42d88b53ccf6 7af7f9305039a0b431ba6a3ed9ab4bee d5e92d48560e01813166f6b3d828dadc 7af7f930560e018131ba6a3ed828dadc 7af7f9305039a0b431ba6a3ed9ab4bee d5e92d48560e01813166f6b3d828dadc fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vmaxnm.f32 q7, q8, q10 a88aac1bef64147b1b59405ba88aac1b 9620330f7eb34717dd31f3cbd27e3da2 3107763b30d670a07a66061eac24c915 3107763b7eb347177a66061eac24c915 9620330f7eb34717dd31f3cbd27e3da2 3107763b30d670a07a66061eac24c915 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vmaxnm.f32 q7, q8, q10 abc6d76bb8dd4d96e540e0e6e540e0e6 34ebdaa4699a49cef173db4d34ebdaa4 11d63b134409e0cfa3b207c581b320e0 34ebdaa4699a49cea3b207c534ebdaa4 34ebdaa4699a49cef173db4d34ebdaa4 11d63b134409e0cfa3b207c581b320e0 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vmaxnm.f32 q7, q8, q10 f13df8be44e80fbcb15ab31e87fd985c c2ce95233ca157e856c409bed2b7ef44 bc5887ad790f6976a4960aa5a4960aa5 bc5887ad790f697656c409bea4960aa5 c2ce95233ca157e856c409bed2b7ef44 bc5887ad790f6976a4960aa5a4960aa5 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 4175fa30b045415166dbaffb9eee7290 f793011a8a30e5cbbfd3135bb060739b 80fc7b81a41c646fd3cb6a18822bb7b6 80fc7b818a30e5cbbfd3135b822bb7b6 f793011a8a30e5cbbfd3135bb060739b 80fc7b81a41c646fd3cb6a18822bb7b6 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vmaxnm.f32 q7, q8, q10 22443ce2edbb41847790accb9bdceae1 e56c81c77e081753cbc3233adda92a3a a555c764f8a34d14e4f4f9d1d7f6a8ac a555c7647e081753cbc3233ad7f6a8ac e56c81c77e081753cbc3233adda92a3a a555c764f8a34d14e4f4f9d1d7f6a8ac fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+vmaxnm.f32 q7, q8, q10 c294ada1a9d330162d3265777dc665d9 c8eafd09368389153c200fba98b3e36c 162ca2b4156f8b9b68514697ae812457 162ca2b4368389156851469798b3e36c c8eafd09368389153c200fba98b3e36c 162ca2b4156f8b9b68514697ae812457 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 2e6a39381562f46a37a9519bd47d4548 0c6da62316cc0282386fa1274d093645 a46f245cb7538a8ed4ad990d86959aa3 0c6da62316cc0282386fa1274d093645 0c6da62316cc0282386fa1274d093645 a46f245cb7538a8ed4ad990d86959aa3 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vmaxnm.f32 q7, q8, q10 c2842a6c3ddec3ba0cd956eedfbb18c8 c20abfb1cd9ccd20e0aa086cd70c65e8 888453c17b667b5737889d9595495740 888453c17b667b5737889d9595495740 c20abfb1cd9ccd20e0aa086cd70c65e8 888453c17b667b5737889d9595495740 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 7b1f97468c355277ef3bcac25e2032f9 e038beeaef82c97963caf7cfb0733274 61910d03dbf9929e85bbd116dda9f4ee 61910d03dbf9929e63caf7cfb0733274 e038beeaef82c97963caf7cfb0733274 61910d03dbf9929e85bbd116dda9f4ee fpscr=00000000
+vmaxnm.f32 q7, q8, q10 90d2021fb9991a24be11ad1cc0b44dc3 2298f7741eb4eb371c5cec260addb55c 2b366fbf7ec3054301879e4c3aa750fb 2b366fbf7ec305431c5cec263aa750fb 2298f7741eb4eb371c5cec260addb55c 2b366fbf7ec3054301879e4c3aa750fb fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[1]
+vmaxnm.f32 q7, q8, q10 7104bd56f967c62b4cd6b263d554362d 0c749a1e754c2adeba611e4324b45c14 7bb8ac544e198e9216e2b6bb6b905ab6 7bb8ac54754c2ade16e2b6bb6b905ab6 0c749a1e754c2adeba611e4324b45c14 7bb8ac544e198e9216e2b6bb6b905ab6 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vmaxnm.f32 q7, q8, q10 453febd4bacd6b3f8ce30f1a1c55e21a 119d29a95991af30dde39898b2847138 e65638c4f68fd22912b6839be65638c4 119d29a95991af3012b6839bb2847138 119d29a95991af30dde39898b2847138 e65638c4f68fd22912b6839be65638c4 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vmaxnm.f32 q7, q8, q10 2042f731b00141a258f520b8437d4f71 6da12c203a3a70a21c5c8f8c98d2f176 06274e3fbc0efde447c11b98175eb4ec 6da12c203a3a70a247c11b98175eb4ec 6da12c203a3a70a21c5c8f8c98d2f176 06274e3fbc0efde447c11b98175eb4ec fpscr=00000000
+vmaxnm.f32 q7, q8, q10 ce5823143cd8634996c9c67d3b1ddebd 52c87c92e87520532a4d8783525ffb1f ab9ef0bbaf5b4cd3885c494ce34745ec 52c87c92af5b4cd32a4d8783525ffb1f 52c87c92e87520532a4d8783525ffb1f ab9ef0bbaf5b4cd3885c494ce34745ec fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vmaxnm.f32 q7, q8, q10 21e91df65b3ff818d23f95b61bd1c93f a5ac3d9cf10bbc4305cba0da1a7b230c 960e77ba960e77ba750b4314e716e1ea 960e77ba960e77ba750b43141a7b230c a5ac3d9cf10bbc4305cba0da1a7b230c 960e77ba960e77ba750b4314e716e1ea fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vmaxnm.f32 q7, q8, q10 c11f6d20c033057e5ef9e446c6b6b58f ab1f444dca6e5cc73b72c693396df2a0 a2299153dcc7ef37a229915354027061 a2299153ca6e5cc73b72c69354027061 ab1f444dca6e5cc73b72c693396df2a0 a2299153dcc7ef37a229915354027061 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 3864cf48db9e77b873a6dbbb26a4e1c0 51a189d468de23143130846d6f268bda dce8274cb4fab05301177e9ca320a665 51a189d468de23143130846d6f268bda 51a189d468de23143130846d6f268bda dce8274cb4fab05301177e9ca320a665 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vmaxnm.f32 q7, q8, q10 c16e8b88e169a1c1d8ea166021bd3d7e ccb3074c1af9daaac80b62bd8e4e6f20 1a4e4ce09667b01d42089b5cd0e1fa92 1a4e4ce01af9daaa42089b5c8e4e6f20 ccb3074c1af9daaac80b62bd8e4e6f20 1a4e4ce09667b01d42089b5cd0e1fa92 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vmaxnm.f32 q7, q8, q10 2d570263aea1492d26b1cdeacfed15d8 5ac37c2aac7febf718fe229604f35be6 ea9bd4ac184e07a7168d4e49110677c0 5ac37c2a184e07a718fe2296110677c0 5ac37c2aac7febf718fe229604f35be6 ea9bd4ac184e07a7168d4e49110677c0 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vmaxnm.f32 q7, q8, q10 92a8308fca9221ce95870b01174b9618 3bc01a1395e03851149814becf131a67 1e99974c6b4ca067e77b5670e5c32387 3bc01a136b4ca067149814becf131a67 3bc01a1395e03851149814becf131a67 1e99974c6b4ca067e77b5670e5c32387 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 27b1045e727f0280ec05c75e6710b81c 2cf38eb7f43f12876962edc5e3182769 e0f08e4327256ee81f47dc0b094e9b8b 2cf38eb727256ee86962edc5094e9b8b 2cf38eb7f43f12876962edc5e3182769 e0f08e4327256ee81f47dc0b094e9b8b fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vmaxnm.f32 q7, q8, q10 d29a892b1cbf6f57436eba166e707878 9493b2379cf43e8743df8af1f360026e 89d06ccb49a69c86e32553a3cc7a0d3e 89d06ccb49a69c8643df8af1cc7a0d3e 9493b2379cf43e8743df8af1f360026e 89d06ccb49a69c86e32553a3cc7a0d3e fpscr=00000000
+vmaxnm.f32 q7, q8, q10 4f23cca734f5ebae7d0e87e96bc81604 76b89c7d43af61cc40b5f698f5099c8f 7723f0dbdfd5dea7499c7ad8b580a5ba 7723f0db43af61cc499c7ad8b580a5ba 76b89c7d43af61cc40b5f698f5099c8f 7723f0dbdfd5dea7499c7ad8b580a5ba fpscr=00000000
+vmaxnm.f32 q7, q8, q10 7a5aaf3bd07a3fb1f34b13f51f3ab783 5d3226c1e25f210d8a0f8667ab492780 9948331506c1d325ff6b65772d361487 5d3226c106c1d3258a0f86672d361487 5d3226c1e25f210d8a0f8667ab492780 9948331506c1d325ff6b65772d361487 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 b15bc802978cc877ecfbf18bd94f58a5 4259fa86eb02542a7e434b6b7d9a5a7f bbd3732e81322c76b75788c3850edd9e 4259fa8681322c767e434b6b7d9a5a7f 4259fa86eb02542a7e434b6b7d9a5a7f bbd3732e81322c76b75788c3850edd9e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vmaxnm.f32 q7, q8, q10 a7b388190eb641a741b96677acb0e78f 2bf250362bf250368e4867aff4ae2181 dd745df50fe87e4aad26b684910db7bd 2bf250362bf250368e4867af910db7bd 2bf250362bf250368e4867aff4ae2181 dd745df50fe87e4aad26b684910db7bd fpscr=00000000
+vmaxnm.f32 q7, q8, q10 acca231f49ae8f15947b5dd6cf6b590a ebd51889f2a8e7a2663a187f8665c5fe aae3dad225501e8dbdd6c9509fe9eb39 aae3dad225501e8d663a187f8665c5fe ebd51889f2a8e7a2663a187f8665c5fe aae3dad225501e8dbdd6c9509fe9eb39 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 92e4d3a1a9cb12a47c8e83bb5dc6d641 d5bfa9f92050578f2847c82f29962ec5 d9e372b191b5d3d033e62853ab01a82c d5bfa9f92050578f33e6285329962ec5 d5bfa9f92050578f2847c82f29962ec5 d9e372b191b5d3d033e62853ab01a82c fpscr=00000000
+vmaxnm.f32 q7, q8, q10 8a8764826ac8c802be5cef6ebd051194 9a5182d3b8616c07092bc51b0f733ddf 0c37c69aa7328aad4a7b4c8139097d55 0c37c69aa7328aad4a7b4c8139097d55 9a5182d3b8616c07092bc51b0f733ddf 0c37c69aa7328aad4a7b4c8139097d55 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[0]
+vmaxnm.f32 q7, q8, q10 61b518d6138d674e0558a15a96afaa79 91be67b58279a0fa983a03f0ebfc68a2 6c8616225ee203f13f4f7917a12d304a 6c8616225ee203f13f4f7917a12d304a 91be67b58279a0fa983a03f0ebfc68a2 6c8616225ee203f13f4f7917a12d304a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: 12544 calls, 12962 iters
+vmaxnm.f32 q7, q8, q10 141365b890733a739c8f4dcda30a3320 033aa6fff771e2498ce8897a86897392 4e70253e82b28130feb979e287a29a00 4e70253e82b281308ce8897a86897392 033aa6fff771e2498ce8897a86897392 4e70253e82b28130feb979e287a29a00 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vmaxnm.f32 q7, q8, q10 98289fde39d478daba217a8a6589b672 fdf82bffb09f75dc69cf164c8ca44b9f 845f81336f87cb770d014ffd0d014ffd 845f81336f87cb7769cf164c0d014ffd fdf82bffb09f75dc69cf164c8ca44b9f 845f81336f87cb770d014ffd0d014ffd fpscr=00000000
+vmaxnm.f32 q7, q8, q10 d44316d7cecca454409260f3da8a20ca 9346e6721dc388f4e43c85b1d182248d bc193e663e0a8f8217fc8e3d384e4ed2 9346e6723e0a8f8217fc8e3d384e4ed2 9346e6721dc388f4e43c85b1d182248d bc193e663e0a8f8217fc8e3d384e4ed2 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[1]
+vmaxnm.f32 q7, q8, q10 d28957f3b1471ad2ce6133eace6133ea 192c47fe4ed86ce1afdd03724ed86ce1 964dab57341f2c209a46113f517dd549 192c47fe4ed86ce19a46113f517dd549 192c47fe4ed86ce1afdd03724ed86ce1 964dab57341f2c209a46113f517dd549 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vmaxnm.f32 q7, q8, q10 91052e7b10bf91cb8a92d43265a2a488 ac595a7a7509bb860faa9253495f1a26 5d598049f6fe6bc7a6a4c6f88fa00c49 5d5980497509bb860faa9253495f1a26 ac595a7a7509bb860faa9253495f1a26 5d598049f6fe6bc7a6a4c6f88fa00c49 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 66bd9dfc4d3a225df53a09e981785f34 eee3f2a588f5651281a35010fbe658b0 2082ac8dad5d1aef94f44a835a393078 2082ac8d88f5651281a350105a393078 eee3f2a588f5651281a35010fbe658b0 2082ac8dad5d1aef94f44a835a393078 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 3d1355856e85c61a8e1a5429914d1fd4 af32d3ae5ea9dfa05561f0da83687173 d90c2ef13fd650c743ea0aded39d24b9 af32d3ae5ea9dfa05561f0da83687173 af32d3ae5ea9dfa05561f0da83687173 d90c2ef13fd650c743ea0aded39d24b9 fpscr=00000000
+vmaxnm.f32 q7, q8, q10 89a765d410fd6af683d95cbb538d6da5 778a6dd4f090e7fb02f446b40e0a855f 25f43f33409d106ffe344d46e0044ffb 778a6dd4409d106f02f446b40e0a855f 778a6dd4f090e7fb02f446b40e0a855f 25f43f33409d106ffe344d46e0044ffb fpscr=00000000
+vmaxnm.f32 q7, q8, q10 5a0b13b185e88f7b408f0d108f325f78 554015caca460802719ac6767ac2b261 adbd0f57ef7319fc604fdd10c2d983ca 554015caca460802719ac6767ac2b261 554015caca460802719ac6767ac2b261 adbd0f57ef7319fc604fdd10c2d983ca fpscr=00000000
+vmaxnm.f32 q7, q8, q10 541574232a5b9deb95caf17262137f7b bf0ba2e3078c894a8e9d1d679d476e12 b3a3d7c97cc1938ced8b17f82daccb1b b3a3d7c97cc1938c8e9d1d672daccb1b bf0ba2e3078c894a8e9d1d679d476e12 b3a3d7c97cc1938ced8b17f82daccb1b fpscr=00000000
+vminnm.f32 d15,d16,d20 909acc2a927b5e3c273945f0505345d5 1cf76bf45bf0ce1f4e30ce4926d2167b cbfa1a6f34e7489b1992c2ebc63ad9d3 1992c2ebc63ad9d3273945f0505345d5 1cf76bf45bf0ce1f4e30ce4926d2167b cbfa1a6f34e7489b1992c2ebc63ad9d3 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vminnm.f32 d15,d16,d20 0870ae4e1a5e536205686ea005686ea0 9877ea3b0ba4d259e10a9c50d40e6131 c8c433b6af2093c7d157f959a74355dd e10a9c50d40e613105686ea005686ea0 9877ea3b0ba4d259e10a9c50d40e6131 c8c433b6af2093c7d157f959a74355dd fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vminnm.f32 d15,d16,d20 faa25148a99d765ee58ebfabafdc2c54 efe33ebdd12d8e275eb0a2e443242cda 8cda13cc4f8a9fc0462cdd8d609e5ecf 462cdd8d43242cdae58ebfabafdc2c54 efe33ebdd12d8e275eb0a2e443242cda 8cda13cc4f8a9fc0462cdd8d609e5ecf fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vminnm.f32 d15,d16,d20 81f7b7262d85e25f5ae36d7d15a522c9 2f0de8f9bdc05ca0c76c84ec5525d15a 53a6d62efbd02d1b3dee81a8c6460ebf c76c84ecc6460ebf5ae36d7d15a522c9 2f0de8f9bdc05ca0c76c84ec5525d15a 53a6d62efbd02d1b3dee81a8c6460ebf fpscr=00000000
+vminnm.f32 d15,d16,d20 288da89490cb473dfecda7f992822321 5cd0ed4773c0bbde51d7a96dc18d12d2 9508275efab4ad14fa2fca0c478f6eac fa2fca0cc18d12d2fecda7f992822321 5cd0ed4773c0bbde51d7a96dc18d12d2 9508275efab4ad14fa2fca0c478f6eac fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vminnm.f32 d15,d16,d20 b0ef9896cf46abbe6350c39e205d3c07 fca5b0cd2925b3e32925b3e335384a30 efaa92b623efbe1bbc86c7fa49c9ffe5 bc86c7fa35384a306350c39e205d3c07 fca5b0cd2925b3e32925b3e335384a30 efaa92b623efbe1bbc86c7fa49c9ffe5 fpscr=00000000
+vminnm.f32 d15,d16,d20 435c3ff467772e1abefc2f2aebe35662 5dd15f482188c7815f23f47f866d23db 16feae8567747f9d0299aaf2e911c726 0299aaf2e911c726befc2f2aebe35662 5dd15f482188c7815f23f47f866d23db 16feae8567747f9d0299aaf2e911c726 fpscr=00000000
+vminnm.f32 d15,d16,d20 4d9431b7bc681d698e3fc4b5ad9d5b4c e7a61879940538bcd639b57b74c2f4ff 72b0b4400f76be2ef95ca400495e1e1b f95ca400495e1e1b8e3fc4b5ad9d5b4c e7a61879940538bcd639b57b74c2f4ff 72b0b4400f76be2ef95ca400495e1e1b fpscr=00000000
+vminnm.f32 d15,d16,d20 07035ece1e8b7df93b6f9ccb174f9269 88721f6b51edc13b03778442216ca496 5a307af641a22fdaf77ee26210993187 f77ee262109931873b6f9ccb174f9269 88721f6b51edc13b03778442216ca496 5a307af641a22fdaf77ee26210993187 fpscr=00000000
+vminnm.f32 d15,d16,d20 99ab463c233b4fa9d80363c552882eff 6213d3b87ac75e1c156c506f74eba764 b6c4c9eac91e3f87082123875f9a4b84 082123875f9a4b84d80363c552882eff 6213d3b87ac75e1c156c506f74eba764 b6c4c9eac91e3f87082123875f9a4b84 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[3]
+vminnm.f32 d15,d16,d20 62f4fad7e5b80d6aae12a4d5779ab5a5 36e6e6f4238c29c971f3a936d96d74a6 45ca8c7a054f8353b9a3e85c054f8353 b9a3e85cd96d74a6ae12a4d5779ab5a5 36e6e6f4238c29c971f3a936d96d74a6 45ca8c7a054f8353b9a3e85c054f8353 fpscr=00000000
+vminnm.f32 d15,d16,d20 37054689934a896f9df4aa35ac689d65 a87800c5c86edd0fbf16c3a7b13632ab 74132093429a90861a05ee7778a30a1b bf16c3a7b13632ab9df4aa35ac689d65 a87800c5c86edd0fbf16c3a7b13632ab 74132093429a90861a05ee7778a30a1b fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vminnm.f32 d15,d16,d20 88f055822cdf6024148da208923bd4c2 84e97e3904d1940896c3d63f96c3d63f 2054f5e57c4b011973bd4f1ec2a7cdc5 96c3d63fc2a7cdc5148da208923bd4c2 84e97e3904d1940896c3d63f96c3d63f 2054f5e57c4b011973bd4f1ec2a7cdc5 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[3]
+vminnm.f32 d15,d16,d20 48fa3d99e61864c86b9595e9b2364962 a3eec96dbfa6e30805c3fffe926bc26e 5a6e5138b7edb3daa5ff3ebb959a0288 a5ff3ebb959a02886b9595e9b2364962 a3eec96dbfa6e30805c3fffe926bc26e 5a6e5138b7edb3daa5ff3ebb959a0288 fpscr=00000000
+vminnm.f32 d15,d16,d20 820dea189e98b5e6adbeb6a82b6f7b6c f41f8f3382f9a2c726f6b8297232c8bd 135b99aa1da93c225080aa90eb123d16 26f6b829eb123d16adbeb6a82b6f7b6c f41f8f3382f9a2c726f6b8297232c8bd 135b99aa1da93c225080aa90eb123d16 fpscr=00000000
+vminnm.f32 d15,d16,d20 d918e1353b95f4b242bf5eea52b3ca77 839e66627195d4e8a83e957204664c74 70a2414332876553d1160d7cf9a11004 d1160d7cf9a1100442bf5eea52b3ca77 839e66627195d4e8a83e957204664c74 70a2414332876553d1160d7cf9a11004 fpscr=00000000
+vminnm.f32 d15,d16,d20 459582ae6bde602e3e59425fe407aee7 cc84dc5421eadbd0a9ec512daf846044 e8cb105974340160ee2712514e64b28d ee271251af8460443e59425fe407aee7 cc84dc5421eadbd0a9ec512daf846044 e8cb105974340160ee2712514e64b28d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vminnm.f32 d15,d16,d20 b9b876c9bfffdc18bfffdc1823290e89 6a4f42f1c1bf24f38e23a8c08ce32ce3 bee4e203240159909f5ea6ab6ffdb945 9f5ea6ab8ce32ce3bfffdc1823290e89 6a4f42f1c1bf24f38e23a8c08ce32ce3 bee4e203240159909f5ea6ab6ffdb945 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vminnm.f32 d15,d16,d20 7df0b2b419d8f7f9710a3cc83df25e24 b6e19465158a6ebba69de5c382afae72 b8b4b865b9cc0bddb9cc0bddb74e6c62 b9cc0bddb74e6c62710a3cc83df25e24 b6e19465158a6ebba69de5c382afae72 b8b4b865b9cc0bddb9cc0bddb74e6c62 fpscr=00000000
+vminnm.f32 d15,d16,d20 b1d5b3e2f4eaf6336f037d34a9409d1b 35646f257e925e2bbef4ce1ee3ff79fd c18cec07d42305ee4555842311bd6d16 bef4ce1ee3ff79fd6f037d34a9409d1b 35646f257e925e2bbef4ce1ee3ff79fd c18cec07d42305ee4555842311bd6d16 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vminnm.f32 d15,d16,d20 99a6f61af79fb7269c6de9184b3f4d15 a227cda51eab8251610c91d1cb17049c dbe8ba329c4780b6d184471f9c3d04f2 d184471fcb17049c9c6de9184b3f4d15 a227cda51eab8251610c91d1cb17049c dbe8ba329c4780b6d184471f9c3d04f2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 d15,d16,d20 65b22bebd319bb4edb5b6d5655ff9235 20e3ecec3cb679a2fa65ded07c200c4d 3edfd82048979fab1597d3d0d0501a8a fa65ded0d0501a8adb5b6d5655ff9235 20e3ecec3cb679a2fa65ded07c200c4d 3edfd82048979fab1597d3d0d0501a8a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 d15,d16,d20 72daeaa3f40335fba59ba62976a8e753 0e1ec1a798a0d25eba1428db0e1ec1a7 9ded261c3caf1c152fc9f28bf77f1f27 ba1428dbf77f1f27a59ba62976a8e753 0e1ec1a798a0d25eba1428db0e1ec1a7 9ded261c3caf1c152fc9f28bf77f1f27 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vminnm.f32 d15,d16,d20 6e34db798fed8af561a5e6d8fa0cbc28 cd6dd50785a8d617c2cce2b264e731c7 08eb2dee9b2f791827dcb49cb74003e0 c2cce2b2b74003e061a5e6d8fa0cbc28 cd6dd50785a8d617c2cce2b264e731c7 08eb2dee9b2f791827dcb49cb74003e0 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vminnm.f32 d15,d16,d20 d41e48f6c24be1f5857762405d2181a0 137d8826297a38a1accf867375040f48 d74fbe2fe6a7b684d74fbe2fa1b2cf57 d74fbe2fa1b2cf57857762405d2181a0 137d8826297a38a1accf867375040f48 d74fbe2fe6a7b684d74fbe2fa1b2cf57 fpscr=00000000
+vminnm.f32 d15,d16,d20 aff8d7bc5e3add705557e99306c562a0 cc2bb71e41f2cec845ac575b12687503 c4be92cf7a57cea10b21f94586e6da26 0b21f94586e6da265557e99306c562a0 cc2bb71e41f2cec845ac575b12687503 c4be92cf7a57cea10b21f94586e6da26 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vminnm.f32 d15,d16,d20 4c419f3b5e4ca28ea81c0d7c0bc26171 8720dfd7561b5002a1d1f555a1d1f555 8d9e59822d9b5b1ea974cf45094197c2 a974cf45a1d1f555a81c0d7c0bc26171 8720dfd7561b5002a1d1f555a1d1f555 8d9e59822d9b5b1ea974cf45094197c2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vminnm.f32 d15,d16,d20 60755588f5a7ef5abf88b86ff113d174 4d00d36dcc43cd15258704e583ed0ba7 f4ca8a12b45e3bb4d200ef6ed788568c d200ef6ed788568cbf88b86ff113d174 4d00d36dcc43cd15258704e583ed0ba7 f4ca8a12b45e3bb4d200ef6ed788568c fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vminnm.f32 d15,d16,d20 63e23dd804a48c646636a59376cfc78f 30d296ebd5c8ba366df94698be535b8e ae3b24f53e0b134e3e0b134e0e2b8255 3e0b134ebe535b8e6636a59376cfc78f 30d296ebd5c8ba366df94698be535b8e ae3b24f53e0b134e3e0b134e0e2b8255 fpscr=00000000
+vminnm.f32 d15,d16,d20 0fef52ee563ee930a22f9fbb043bfef9 8687bd1a34f39932c9ee9b70ef997428 8305f27652568c275b27f64ed771fef7 c9ee9b70ef997428a22f9fbb043bfef9 8687bd1a34f39932c9ee9b70ef997428 8305f27652568c275b27f64ed771fef7 fpscr=00000000
+vminnm.f32 d15,d16,d20 4bcb0d8f521c4761fed011cb4759c7fd 85ab568210944316bb3fee52d500fec7 0e209e1702701d5d52bd811b78ff194d bb3fee52d500fec7fed011cb4759c7fd 85ab568210944316bb3fee52d500fec7 0e209e1702701d5d52bd811b78ff194d fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 d15,d16,d20 635cbb04e0875e5b68de5715a52fffd9 84cbf00ae257ae9daee36a06306244e0 1e44843de01b0456a18cf2e31e44843d aee36a061e44843d68de5715a52fffd9 84cbf00ae257ae9daee36a06306244e0 1e44843de01b0456a18cf2e31e44843d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 d15,d16,d20 65db7e006cec6042ea83890fbe978d95 a679fb2a6c8c8ba91aeddd931aeddd93 85cb67a47b3a75d1c4fcd17f85cb67a4 c4fcd17f85cb67a4ea83890fbe978d95 a679fb2a6c8c8ba91aeddd931aeddd93 85cb67a47b3a75d1c4fcd17f85cb67a4 fpscr=00000000
+randV128: 12800 calls, 13227 iters
+vminnm.f32 d15,d16,d20 690abb6f1a2822266f884d37a0693b47 7adf034d9f30234834c659db8be68a6d a15a6392a284d4ee80dc72d3214c2ce9 80dc72d38be68a6d6f884d37a0693b47 7adf034d9f30234834c659db8be68a6d a15a6392a284d4ee80dc72d3214c2ce9 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vminnm.f32 d15,d16,d20 01358e4cdaa01c3769404a29cd88aba0 5fb230021670466f9c0f4ca51670466f 09bdebfcca541b20b2c22cb7cd38e39c b2c22cb7cd38e39c69404a29cd88aba0 5fb230021670466f9c0f4ca51670466f 09bdebfcca541b20b2c22cb7cd38e39c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vminnm.f32 d15,d16,d20 6268f7c48e0986a90b913216e420dc11 78b75538e8ba1e705eb9177278b75538 52a0bf649f655584091063386452f11c 091063386452f11c0b913216e420dc11 78b75538e8ba1e705eb9177278b75538 52a0bf649f655584091063386452f11c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vminnm.f32 d15,d16,d20 cb08f38fa4bd2667566a1a5bab214fac 076940ac5744188fa8a40c59fc606654 7eaac24c5da22a0edfd577de7eaac24c dfd577defc606654566a1a5bab214fac 076940ac5744188fa8a40c59fc606654 7eaac24c5da22a0edfd577de7eaac24c fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 d15,d16,d20 b065b8d67d5449e0a0923d54b065b8d6 e22f2180d56fc20aba9ef245c6a0e3a4 3823ed0ef5e60f31e96742201f8b8b2a e9674220c6a0e3a4a0923d54b065b8d6 e22f2180d56fc20aba9ef245c6a0e3a4 3823ed0ef5e60f31e96742201f8b8b2a fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[2]
+vminnm.f32 d15,d16,d20 fd772f32d693feefa038d3bca01739b6 c46ea3fbf4eb6fd47c415e6804e4f82b b638078c388ce0ec388ce0ec4980022d 388ce0ec04e4f82ba038d3bca01739b6 c46ea3fbf4eb6fd47c415e6804e4f82b b638078c388ce0ec388ce0ec4980022d fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[0]
+vminnm.f32 d15,d16,d20 beba9e85844effeddeeb95e7beba9e85 933aa7c26cdc070c14d239054ab32810 664c70c1f23dc82aac2b65cef23dc82a ac2b65cef23dc82adeeb95e7beba9e85 933aa7c26cdc070c14d239054ab32810 664c70c1f23dc82aac2b65cef23dc82a fpscr=00000000
+vminnm.f32 d15,d16,d20 809b2345d1ebea66a8c2c6aee06d4a3c 07438a867b3ed8ac3471b4a4498bc0a1 b4b8ddba2e8428f224d63b53d6e0b976 24d63b53d6e0b976a8c2c6aee06d4a3c 07438a867b3ed8ac3471b4a4498bc0a1 b4b8ddba2e8428f224d63b53d6e0b976 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[3]
+vminnm.f32 d15,d16,d20 a4b5aaef8491569033b0ffb873965a54 f1a3b839455f7f4af1a3b83930e11841 a369d662799beb423836aa5ea4f5360e f1a3b839a4f5360e33b0ffb873965a54 f1a3b839455f7f4af1a3b83930e11841 a369d662799beb423836aa5ea4f5360e fpscr=00000000
+vminnm.f32 d15,d16,d20 6e471c996e361a9a9fa9ca126512a590 1b51e6858f5b6e116c8d1d61e4c1dd30 17c4ca0a540fabdec7520b92bffa5627 c7520b92e4c1dd309fa9ca126512a590 1b51e6858f5b6e116c8d1d61e4c1dd30 17c4ca0a540fabdec7520b92bffa5627 fpscr=00000000
+vminnm.f32 d15,d16,d20 f7997a4db0224cc897a4f64c156842fd 881c7682b5807b7758ed7657f0ed5f0a de7dce5479329dec4884a262f8773182 4884a262f877318297a4f64c156842fd 881c7682b5807b7758ed7657f0ed5f0a de7dce5479329dec4884a262f8773182 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vminnm.f32 d15,d16,d20 16125f00f365545d3e015eb0aa03b6d5 02fe905a8ff6e67dc91555430fbfe7b2 977b3e5152970bc61b245ca4cba3e9fd c9155543cba3e9fd3e015eb0aa03b6d5 02fe905a8ff6e67dc91555430fbfe7b2 977b3e5152970bc61b245ca4cba3e9fd fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vminnm.f32 d15,d16,d20 d60785e77f6b9f6ef1c6363e72716d5f 4cb3c4d024a6187f24a6187f6875a7cf ddd69145272ce28027c2d996d4b3be47 24a6187fd4b3be47f1c6363e72716d5f 4cb3c4d024a6187f24a6187f6875a7cf ddd69145272ce28027c2d996d4b3be47 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vminnm.f32 d15,d16,d20 94c4a3a01340d866eafdcd169cd8f6ee 95b6973f04ed747123a3c730ba2cfcde 847e87b3840ab8b5840ab8b5f30b41cf 840ab8b5f30b41cfeafdcd169cd8f6ee 95b6973f04ed747123a3c730ba2cfcde 847e87b3840ab8b5840ab8b5f30b41cf fpscr=00000000
+vminnm.f32 d15,d16,d20 4ee16e42966a36406a48cbca34265a57 cbc2cbb85de7b6254d87b0da626bc002 cb22d4d5a5e39dfb5b98b3a7ca18e35c 4d87b0daca18e35c6a48cbca34265a57 cbc2cbb85de7b6254d87b0da626bc002 cb22d4d5a5e39dfb5b98b3a7ca18e35c fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[3]
+vminnm.f32 d15,d16,d20 92f4774a8828db460f390a6878e1cf58 62c489c23f2fda779eb68bff6bb891ec 6d40aac9487b884bb37bd9e6487b884b b37bd9e6487b884b0f390a6878e1cf58 62c489c23f2fda779eb68bff6bb891ec 6d40aac9487b884bb37bd9e6487b884b fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 d15,d16,d20 7893adfa541fae48440a79457893adfa 70e9e46087bb7d5144824d9cc340e211 cfea81c3992967a93f9668d582bad44e 3f9668d5c340e211440a79457893adfa 70e9e46087bb7d5144824d9cc340e211 cfea81c3992967a93f9668d582bad44e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[3]
+vminnm.f32 q7, q8, q10 af593304cac5f4db3f7a65e17bca6f22 f082e9cb013fa42f013fa42f7c51d4e4 78f8293c697891435d05b3d5df82b2c7 f082e9cb013fa42f013fa42fdf82b2c7 f082e9cb013fa42f013fa42f7c51d4e4 78f8293c697891435d05b3d5df82b2c7 fpscr=00000000
+vminnm.f32 q7, q8, q10 b9b284ad1e04ffb4dbda23c718a8e15a e8b41b551743f6db9000c6b9cccaeaae 0bae0ff1ebe101f176c39fd4bcee1906 e8b41b55ebe101f19000c6b9cccaeaae e8b41b551743f6db9000c6b9cccaeaae 0bae0ff1ebe101f176c39fd4bcee1906 fpscr=00000000
+vminnm.f32 q7, q8, q10 9194616763e47e4417a35c9288715a68 ba0636201bb6ee7771e617b0294e9a44 acfa0a123c52751df0107429ae7e3c88 ba0636201bb6ee77f0107429ae7e3c88 ba0636201bb6ee7771e617b0294e9a44 acfa0a123c52751df0107429ae7e3c88 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[0]
+vminnm.f32 q7, q8, q10 23bb356afbb98d53756fa37723bb356a d9d7103d52311d40028d9a6b23ca658a 4946718d91893cae9ce434f83b852f0d d9d7103d91893cae9ce434f823ca658a d9d7103d52311d40028d9a6b23ca658a 4946718d91893cae9ce434f83b852f0d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vminnm.f32 q7, q8, q10 2f4d09438d8d3a1014b1d11d6ca9ad6c 1d3eaf6ce42a6fc9da735b996929531d 36d9e8fe75ce31a336d9e8fe786b8f04 1d3eaf6ce42a6fc9da735b996929531d 1d3eaf6ce42a6fc9da735b996929531d 36d9e8fe75ce31a336d9e8fe786b8f04 fpscr=00000000
+vminnm.f32 q7, q8, q10 8fd3a8095e5da8bbe5f6a84dd3c315d7 6ec70299b4b65de43291a9644d7c4d77 1e5d09abf7b68befd8ec42b6c7f96ac6 1e5d09abf7b68befd8ec42b6c7f96ac6 6ec70299b4b65de43291a9644d7c4d77 1e5d09abf7b68befd8ec42b6c7f96ac6 fpscr=00000000
+vminnm.f32 q7, q8, q10 46f2acbb9a176e4b0ee8d5d144d973e9 d449ffd56782b7e6689619b54caa98f3 dd6c5aaba55f46f4718c2e268a1858ce dd6c5aaba55f46f4689619b58a1858ce d449ffd56782b7e6689619b54caa98f3 dd6c5aaba55f46f4718c2e268a1858ce fpscr=00000000
+vminnm.f32 q7, q8, q10 8f670bc127b737083ccd153b549870b8 c47b1a19f206ab2014f8998d1302b016 f0dd2263c799c8b16c6421550dd00e43 f0dd2263f206ab2014f8998d0dd00e43 c47b1a19f206ab2014f8998d1302b016 f0dd2263c799c8b16c6421550dd00e43 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vminnm.f32 q7, q8, q10 d4660bde72d544618a81ccf98f6e6c54 8e5b3c1b537d55631b4cbd9ae283937d 6556870b3b6f5932c00e98c031af688d 8e5b3c1b3b6f5932c00e98c0e283937d 8e5b3c1b537d55631b4cbd9ae283937d 6556870b3b6f5932c00e98c031af688d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[0]
+vminnm.f32 q7, q8, q10 dc89569eb93484e1ba546b49ba546b49 57a38630d8c1e2db8f4838986d21b45e b3ce661022ec200422ec20045f56fbc6 b3ce6610d8c1e2db8f4838985f56fbc6 57a38630d8c1e2db8f4838986d21b45e b3ce661022ec200422ec20045f56fbc6 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vminnm.f32 q7, q8, q10 f14ddb1077227b6e58d6920c4d3182a8 15fc16fe2d822740d6950bf3a8ff53a4 399f110fedba28b1639d241676e182bc 15fc16feedba28b1d6950bf3a8ff53a4 15fc16fe2d822740d6950bf3a8ff53a4 399f110fedba28b1639d241676e182bc fpscr=00000000
+vminnm.f32 q7, q8, q10 0b382d7562e1a15bae5b931d3baebfec d1578cc1babf3ee2879d04fa25e31768 9ddd29852f66c1341382a52a4c220fef d1578cc1babf3ee2879d04fa25e31768 d1578cc1babf3ee2879d04fa25e31768 9ddd29852f66c1341382a52a4c220fef fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[3]
+vminnm.f32 q7, q8, q10 5899d153e997f64cf126a024d92f4c56 2c6e79d1a394e9a17b50c3ac7b50c3ac 39b53c8c042e692ed90ebc3c0aacb7b8 2c6e79d1a394e9a1d90ebc3c0aacb7b8 2c6e79d1a394e9a17b50c3ac7b50c3ac 39b53c8c042e692ed90ebc3c0aacb7b8 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[3]
+vminnm.f32 q7, q8, q10 06bef665c2737d2d2ff0b927cd74673a 281f1541292bb5bf11c57718c7376bcd 196df3e28e6a354a9f83ba9d194231d8 196df3e28e6a354a9f83ba9dc7376bcd 281f1541292bb5bf11c57718c7376bcd 196df3e28e6a354a9f83ba9d194231d8 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vminnm.f32 q7, q8, q10 a14023e501e2f0c2a14023e548a8d6d3 c1deeff8bd163e37596260b7d812a116 de5acb5bf30a462ba4242c5aedbb9070 de5acb5bf30a462ba4242c5aedbb9070 c1deeff8bd163e37596260b7d812a116 de5acb5bf30a462ba4242c5aedbb9070 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vminnm.f32 q7, q8, q10 fcfc5fbe422ab89a31194082daf69781 33794f2f4ef03d1c663f90ff9c81e48f 5cc9adb1de4439bf60a1c90debf1a644 33794f2fde4439bf60a1c90debf1a644 33794f2f4ef03d1c663f90ff9c81e48f 5cc9adb1de4439bf60a1c90debf1a644 fpscr=00000000
+vminnm.f32 q7, q8, q10 41a418d5b06307b06aa15c1bee67af09 20b982a3771fcb31065c0084aa1411a6 7a1c2639914cdcfcc2f5946d071f3602 20b982a3914cdcfcc2f5946daa1411a6 20b982a3771fcb31065c0084aa1411a6 7a1c2639914cdcfcc2f5946d071f3602 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[1]
+vminnm.f32 q7, q8, q10 5ecc11480a49c8d8a23de5f13567da1f 1e85a6005f30476d47c20b561a0a23d7 75505d3d0c10bf6bbcf9b20f75505d3d 1e85a6000c10bf6bbcf9b20f1a0a23d7 1e85a6005f30476d47c20b561a0a23d7 75505d3d0c10bf6bbcf9b20f75505d3d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vminnm.f32 q7, q8, q10 cad21082a17e8c2e23f9efe323f9efe3 b262117934d0faca399db34140aa03bd 51e504f7c964858d167891423a2fc026 b2621179c964858d167891423a2fc026 b262117934d0faca399db34140aa03bd 51e504f7c964858d167891423a2fc026 fpscr=00000000
+vminnm.f32 q7, q8, q10 be1749d9214c3e0a42e7e100357ac90a 96a8392b8eea7df670d0b04031017c00 347b2275f04d293f492dea92e63ab09e 96a8392bf04d293f492dea92e63ab09e 96a8392b8eea7df670d0b04031017c00 347b2275f04d293f492dea92e63ab09e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vminnm.f32 q7, q8, q10 b4ee284d0585eab3b2731a96760eed35 4e5aeeda21782661edf1af9c7246af84 caa502cc96995402ff5cd6f1c9516eb0 caa502cc96995402ff5cd6f1c9516eb0 4e5aeeda21782661edf1af9c7246af84 caa502cc96995402ff5cd6f1c9516eb0 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[3]
+vminnm.f32 q7, q8, q10 06ddef1a202594e078e4eb71bc55244f d1dbe1bc0c7127010982b8a50982b8a5 bd70b110f0d9b796e9824df4f0d9b796 d1dbe1bcf0d9b796e9824df4f0d9b796 d1dbe1bc0c7127010982b8a50982b8a5 bd70b110f0d9b796e9824df4f0d9b796 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vminnm.f32 q7, q8, q10 a6265627653622eb347a55fea66c079d 4fdb52a921ed7d1b19472c02f72fc744 0afb87621a33a6c4aad6eb7973c5eef4 0afb87621a33a6c4aad6eb79f72fc744 4fdb52a921ed7d1b19472c02f72fc744 0afb87621a33a6c4aad6eb7973c5eef4 fpscr=00000000
+vminnm.f32 q7, q8, q10 42af77e26e0db08b2d09c6ff00ee1181 977132dc67a7b0aab3d09d91d4338d90 1fe184f99c8d5eb9b972d40d15133ec0 977132dc9c8d5eb9b972d40dd4338d90 977132dc67a7b0aab3d09d91d4338d90 1fe184f99c8d5eb9b972d40d15133ec0 fpscr=00000000
+vminnm.f32 q7, q8, q10 8dd8dd6eb2a0ca0e0ec799f35503c906 a5ca7cdfc2546f8990cbdfb7ec9f977e aa78152b42960fc0a45333ccc2154d51 aa78152bc2546f89a45333ccec9f977e a5ca7cdfc2546f8990cbdfb7ec9f977e aa78152b42960fc0a45333ccc2154d51 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: 13056 calls, 13498 iters
+vminnm.f32 q7, q8, q10 b7d77cf4b7d77cf41897ca4b433b74b5 d767d0f75cf0a158e1d83b8799283ae7 0712b86fa266eb2c2f5532a1a0e8806e d767d0f7a266eb2ce1d83b87a0e8806e d767d0f75cf0a158e1d83b8799283ae7 0712b86fa266eb2c2f5532a1a0e8806e fpscr=00000000
+vminnm.f32 q7, q8, q10 1e3ff117a17c1b9a0cc3e2c495afd522 4182692b24be906b71a317956c3eedd8 4ffa22496d587c04f431210be0e40e44 4182692b24be906bf431210be0e40e44 4182692b24be906b71a317956c3eedd8 4ffa22496d587c04f431210be0e40e44 fpscr=00000000
+vminnm.f32 q7, q8, q10 2589c66b15ba976384770b3bb231f4e9 979334f699b79484b8634ecd12c53402 911f9ff59f225ccb418c97ad76828f71 979334f69f225ccbb8634ecd12c53402 979334f699b79484b8634ecd12c53402 911f9ff59f225ccb418c97ad76828f71 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vminnm.f32 q7, q8, q10 2691b466fef46a67f92b1febff507644 fd9893ec46502d490aa7068a39b24687 19eb9001674d155c33c5331593d34b04 fd9893ec46502d490aa7068a93d34b04 fd9893ec46502d490aa7068a39b24687 19eb9001674d155c33c5331593d34b04 fpscr=00000000
+vminnm.f32 q7, q8, q10 5510ac1202576ca17d12cc680de4b928 8661fc09f634f5ade9953ca012c69157 32fe3b7d61253496a6b0b94b7574271c 8661fc09f634f5ade9953ca012c69157 8661fc09f634f5ade9953ca012c69157 32fe3b7d61253496a6b0b94b7574271c fpscr=00000000
+vminnm.f32 q7, q8, q10 3f39c08811da333b33046730e5128699 461b9c3b25215a5e58d018f1a4421722 c9e424c5976b8d9afc2547a89ea363bc c9e424c5976b8d9afc2547a8a4421722 461b9c3b25215a5e58d018f1a4421722 c9e424c5976b8d9afc2547a89ea363bc fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[3]
+vminnm.f32 q7, q8, q10 74534e2af3655e21760a31f3760a31f3 9d00730c2825b488f7ef29c53a22685e 62bdd8654fe2f5142e1aaaca2e710334 9d00730c2825b488f7ef29c52e710334 9d00730c2825b488f7ef29c53a22685e 62bdd8654fe2f5142e1aaaca2e710334 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vminnm.f32 q7, q8, q10 84813a1f44d19586a5e8b448a3c7bcec a11fbfae7ee9f1156ba16b7467c03b96 e983b1c351991ad67dda8ffb7dda8ffb e983b1c351991ad66ba16b7467c03b96 a11fbfae7ee9f1156ba16b7467c03b96 e983b1c351991ad67dda8ffb7dda8ffb fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[2]
+vminnm.f32 q7, q8, q10 3e74c9a606f5ae8a6d070d983e74c9a6 f3c0263187457f0872477b17088a5492 635fc469b4e52b81237ed708b4e52b81 f3c02631b4e52b81237ed708b4e52b81 f3c0263187457f0872477b17088a5492 635fc469b4e52b81237ed708b4e52b81 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[2]
+vminnm.f32 q7, q8, q10 7d5b63ac260837b97d5b63aceb72ff28 67a90cd35fbefafc5bd4174ec05d25d1 82c80f1bf8a79116f8a79116e84da7fd 82c80f1bf8a79116f8a79116e84da7fd 67a90cd35fbefafc5bd4174ec05d25d1 82c80f1bf8a79116f8a79116e84da7fd fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 q7, q8, q10 5d977e009461885a8315b8ff5445cf39 8af8812669f6d6369d130ef98a734854 af177f40826b7b3ef269cc6140e1adef af177f40826b7b3ef269cc618a734854 8af8812669f6d6369d130ef98a734854 af177f40826b7b3ef269cc6140e1adef fpscr=00000000
+vminnm.f32 q7, q8, q10 17be0e3fd7dc4a37abfa5fb667fb774a b499e8f5d43569d809987bb430de1ca7 ab455f2b8b3104724335aee272ade533 b499e8f5d43569d809987bb430de1ca7 b499e8f5d43569d809987bb430de1ca7 ab455f2b8b3104724335aee272ade533 fpscr=00000000
+vminnm.f32 q7, q8, q10 ebbdf6452c14c25adc6fd4bf578a7ae6 d9896a4d50546afb42213864b80f98e8 a54388a55a365f04d5f4e9d2f1cd2a79 d9896a4d50546afbd5f4e9d2f1cd2a79 d9896a4d50546afb42213864b80f98e8 a54388a55a365f04d5f4e9d2f1cd2a79 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[2]
+vminnm.f32 q7, q8, q10 0d80ee3a7ae13dd49275faf32ac8585e 9ee6a816e6b98b396807b9450f0754b8 188864da60d78b398c32de1a188864da 9ee6a816e6b98b398c32de1a0f0754b8 9ee6a816e6b98b396807b9450f0754b8 188864da60d78b398c32de1a188864da fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 q7, q8, q10 f96966935026d2ffae64046529f4e316 749df956350a551ec096dab8a6bc80bb ab81306a6dfa5de3661a5f842bdb370c ab81306a350a551ec096dab8a6bc80bb 749df956350a551ec096dab8a6bc80bb ab81306a6dfa5de3661a5f842bdb370c fpscr=00000000
+vminnm.f32 q7, q8, q10 ccc83b6bcf4dd7ab3a33bf00aa346e2a f717da6320590803562dbf16a968ee18 f5fb2c5bdedf2a540c85451481f7a460 f717da63dedf2a540c854514a968ee18 f717da6320590803562dbf16a968ee18 f5fb2c5bdedf2a540c85451481f7a460 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vminnm.f32 q7, q8, q10 719d67d7662088ad429c054fa0e27189 36feb82a849183131e2d557acfbe44b2 42ba039e1b0cf2afbc85793c3ddaf63c 36feb82a84918313bc85793ccfbe44b2 36feb82a849183131e2d557acfbe44b2 42ba039e1b0cf2afbc85793c3ddaf63c fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vminnm.f32 q7, q8, q10 5e215066e8a29f53bc323b961c61bdce 5709336246fd083994396122d39ea245 e56e48a8c26319d2a4915b1c5e83b35d e56e48a8c26319d2a4915b1cd39ea245 5709336246fd083994396122d39ea245 e56e48a8c26319d2a4915b1c5e83b35d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[2]
+vminnm.f32 q7, q8, q10 00f28517c2d01538a37cca258dd115d3 7d5f9f126d65804be72f14616a4d9cb6 cf3f67f44895ade6d0eef9c6da739fdc cf3f67f44895ade6e72f1461da739fdc 7d5f9f126d65804be72f14616a4d9cb6 cf3f67f44895ade6d0eef9c6da739fdc fpscr=00000000
+vminnm.f32 q7, q8, q10 d032fbff5585b1dfb371961437fd3cff 9a8185284416a7d4d90d2ce5a67db465 9f071e6eba1f8ce3291b768a944ad93e 9f071e6eba1f8ce3d90d2ce5a67db465 9a8185284416a7d4d90d2ce5a67db465 9f071e6eba1f8ce3291b768a944ad93e fpscr=00000000
+vminnm.f32 q7, q8, q10 e380143f474d2f21a6662bd0e8145d47 d8752ad74bb3033b3572ef972a649d68 08e918d038a99f9da1b173e572edb1da d8752ad738a99f9da1b173e52a649d68 d8752ad74bb3033b3572ef972a649d68 08e918d038a99f9da1b173e572edb1da fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[2]
+vminnm.f32 q7, q8, q10 32a79d2f5776ad9d17cfd5022cc237a8 df3d4a7042f5c979df3d4a7083aabd4b ce7ef43a33a96d699fe3e651ea040bce df3d4a7033a96d69df3d4a70ea040bce df3d4a7042f5c979df3d4a7083aabd4b ce7ef43a33a96d699fe3e651ea040bce fpscr=00000000
+vminnm.f32 q7, q8, q10 9755f485f82cee30373758a526535a37 d95ee1198480e4045c48f64a4a7f7d3a 1484e97a0a958449bf0859475b354c05 d95ee1198480e404bf0859474a7f7d3a d95ee1198480e4045c48f64a4a7f7d3a 1484e97a0a958449bf0859475b354c05 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vminnm.f32 q7, q8, q10 59c0717ad5df8ec03e8fac87da585a06 f722c7a943c765a7ebcf73081c3c8bf1 b17b6909323b419c0c067b5b323b419c f722c7a9323b419cebcf73081c3c8bf1 f722c7a943c765a7ebcf73081c3c8bf1 b17b6909323b419c0c067b5b323b419c fpscr=00000000
+vminnm.f32 q7, q8, q10 a968d0aa5a62d7133869247c1ffcfeaf da61a37210752f3815732c37a7a6c643 4df27aafb3731a19a13c06d76fec9ddf da61a372b3731a19a13c06d7a7a6c643 da61a37210752f3815732c37a7a6c643 4df27aafb3731a19a13c06d76fec9ddf fpscr=00000000
+vcvtn.s32.f32 d0, d20 e8d027cee9b2ebd002ba7e4bc6bb618e 9129c3b47d14f066ee78982ffb879866 e8d027cee9b2ebd08000000080000000 9129c3b47d14f066ee78982ffb879866 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtn.s32.f32 d0, d20 1948dae321bfff87368d9619ac2e37e6 a29868da2e7ac852ca1c7c18f4599244 1948dae321bfff87ffd8e0fa80000000 a29868da2e7ac852ca1c7c18f4599244 fpscr=00000000
+vcvtn.s32.f32 d0, d20 bbb98c91e46f896fd3402178b7e59563 61c7bb692aac01ee384ca72b8daaf54e bbb98c91e46f896f0000000000000000 61c7bb692aac01ee384ca72b8daaf54e fpscr=00000000
+vcvtn.s32.f32 d0, d20 19de0aceb11f7375724c36edb4a148d9 3f52d49533087bdc827bf99ad6fddd9b 19de0aceb11f73750000000080000000 3f52d49533087bdc827bf99ad6fddd9b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.s32.f32 d0, d20 4cae2bdb0165af5359046e1e4c6b80a1 665685ffe180a6c3665685ff976f6bfb 4cae2bdb0165af537fffffff00000000 665685ffe180a6c3665685ff976f6bfb fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtn.s32.f32 d0, d20 2449e73771ff9afb3a23c26a9deb1449 f6fc87e3df09f17a046ddc5d046ddc5d 2449e73771ff9afb0000000000000000 f6fc87e3df09f17a046ddc5d046ddc5d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[2]
+vcvtn.s32.f32 d0, d20 4b4aa42b8b8cb9784b4aa42b46a428ac ef769616ef76961693e265132a95763c 4b4aa42b8b8cb9780000000000000000 ef769616ef76961693e265132a95763c fpscr=00000000
+vcvtn.s32.f32 d0, d20 f929f3d4c3fd3dac85bb7783ad9c9a27 e0e4721999f22ef95018b5627c4470b8 f929f3d4c3fd3dac7fffffff7fffffff e0e4721999f22ef95018b5627c4470b8 fpscr=00000000
+vcvtn.s32.f32 d0, d20 facb20922b28fbda1ed9a8e099d79a03 f08cb7e7b388369d949426814dffdb3b facb20922b28fbda000000001ffb6760 f08cb7e7b388369d949426814dffdb3b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[3]
+vcvtn.s32.f32 d0, d20 5d88372a79062efc57c00b9a86695cdb 204b265ee33aaa8bb09eece2e33aaa8b 5d88372a79062efc0000000080000000 204b265ee33aaa8bb09eece2e33aaa8b fpscr=00000000
+vcvtn.s32.f32 d0, d20 07f5c6e5c51af73f111b370da182c1d7 ad4b09db0d549560f6e04af207c604d9 07f5c6e5c51af73f8000000000000000 ad4b09db0d549560f6e04af207c604d9 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtn.s32.f32 d0, d20 342fcfa7fdf51b7615d7a5f5fdf51b76 6aa97cf43643669f281206d02b218225 342fcfa7fdf51b760000000000000000 6aa97cf43643669f281206d02b218225 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.s32.f32 d0, d20 3c23f8ccce9b03334360527eef830a40 e390be3fc2472537e390be3fb1610be9 3c23f8ccce9b03338000000000000000 e390be3fc2472537e390be3fb1610be9 fpscr=00000000
+vcvtn.s32.f32 d0, d20 c705a97b7f46913a3aebd605136e14c2 f17616b37b4823362168cff945b20746 c705a97b7f46913a0000000000001641 f17616b37b4823362168cff945b20746 fpscr=00000000
+vcvtn.s32.f32 d0, d20 4669075a5b83c8b6718a0026cac91aad b77fd4a98688167b08cd7f2e7157f39e 4669075a5b83c8b6000000007fffffff b77fd4a98688167b08cd7f2e7157f39e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[1]
+vcvtn.s32.f32 d0, d20 ee8d186cd39a1fd9ee8d186ca1726947 92e1c992bc5a33a5e139b43df8b35987 ee8d186cd39a1fd98000000080000000 92e1c992bc5a33a5e139b43df8b35987 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtn.s32.f32 d0, d20 bb043da3fb9445656f1cf9c7de9cf637 856a78b503121a87201e02d5856a78b5 bb043da3fb9445650000000000000000 856a78b503121a87201e02d5856a78b5 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[2]
+vcvtn.s32.f32 d0, d20 32d00c12a9a26c30a163235a32d00c12 5dc63fabd0074cbcd0074cbcf9d1662f 32d00c12a9a26c308000000080000000 5dc63fabd0074cbcd0074cbcf9d1662f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtn.s32.f32 d0, d20 61de638fcfc675b1f7ac9f4960437a57 59614594c5d13f0559614594a9ea4000 61de638fcfc675b17fffffff00000000 59614594c5d13f0559614594a9ea4000 fpscr=00000000
+vcvtn.s32.f32 d0, d20 f037cac0beb92ea8979ad41cbb947b72 f2c5f87ee1fbb8cb45a182b5c9e83e07 f037cac0beb92ea800001430ffe2f83f f2c5f87ee1fbb8cb45a182b5c9e83e07 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.s32.f32 d0, d20 dcb96e1b17bd15bd605d6fe12901b9b3 4dfd3e5dd8d52f434dfd3e5d25e15310 dcb96e1b17bd15bd1fa7cba000000000 4dfd3e5dd8d52f434dfd3e5d25e15310 fpscr=00000000
+vcvtn.s32.f32 d0, d20 54cb3818436640aaf687671b2b17471b 8a7f403731c489242f3c8168f66ce45d 54cb3818436640aa0000000080000000 8a7f403731c489242f3c8168f66ce45d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtn.s32.f32 d0, d20 a7bca564a7bca564123bb6f4aeb5cddc e9c73ad9943f3304bc94a7d29417abbb a7bca564a7bca5640000000000000000 e9c73ad9943f3304bc94a7d29417abbb fpscr=00000000
+vcvtn.s32.f32 d0, d20 25ed26d369513433db3ae55b44695ee1 8418e9017d0b161b19337d2c6d60ba0d 25ed26d369513433000000007fffffff 8418e9017d0b161b19337d2c6d60ba0d fpscr=00000000
+vcvtn.s32.f32 d0, d20 b71dab056513223799a245fe510cb3b6 4607aaf431f74bb589e5a1d382f69e0f b71dab05651322370000000000000000 4607aaf431f74bb589e5a1d382f69e0f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.s32.f32 d0, d20 a6e8ecf5994f53f3668fd30b9f6c2660 e727d9e2e727d9e2d9fec3ebe7b4a398 a6e8ecf5994f53f38000000080000000 e727d9e2e727d9e2d9fec3ebe7b4a398 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vcvtn.s32.f32 d0, d20 18b51d93d2fbe430c70460cfc70460cf 93d2bd7a6e84e22b1b2f75896e84e22b 18b51d93d2fbe430000000007fffffff 93d2bd7a6e84e22b1b2f75896e84e22b fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: 13312 calls, 13761 iters
+vcvtn.s32.f32 d0, d20 a24d20f22ca4e460311d699a8ca5b39c cc78987601b70f9f4a19779dd832cf06 a24d20f22ca4e46000265de780000000 cc78987601b70f9f4a19779dd832cf06 fpscr=00000000
+vcvtn.s32.f32 d0, d20 6d325902a9cb8c2e4b32516aa7335334 c4bae7315c46efdc473e1d742c5b2d09 6d325902a9cb8c2e0000be1d00000000 c4bae7315c46efdc473e1d742c5b2d09 fpscr=00000000
+vcvtn.s32.f32 d0, d20 713d4ebca3ab4ec21bff1f9c0f15599f 6a58e85df9f87371126bfabfbcb7546c 713d4ebca3ab4ec20000000000000000 6a58e85df9f87371126bfabfbcb7546c fpscr=00000000
+vcvtn.s32.f32 d0, d20 4286febd435a47de9f2371edbc04ba78 f5e7550f2cf8848ab0147636eb57ce84 4286febd435a47de0000000080000000 f5e7550f2cf8848ab0147636eb57ce84 fpscr=00000000
+vcvtn.s32.f32 d0, d20 6a4b88773e928af230645429bf7a2365 03588d559ace04518d4b04a4c96dcfe3 6a4b88773e928af200000000fff12302 03588d559ace04518d4b04a4c96dcfe3 fpscr=00000000
+vcvtn.s32.f32 d0, d20 6360d58a05512d7e0c5970ee993bd57f 132879da50d49149dd9fe5456fb14809 6360d58a05512d7e800000007fffffff 132879da50d49149dd9fe5456fb14809 fpscr=00000000
+vcvtn.s32.f32 d0, d20 8b321ba157076e0f87c0d2ca0abc1193 cacf17f41b4b31f419cff5159eb9d94c 8b321ba157076e0f0000000000000000 cacf17f41b4b31f419cff5159eb9d94c fpscr=00000000
+vcvtn.s32.f32 d0, d20 7dc0c53138a13a1fa8a50e385178d83c 0997ec02ced0e2dd5de2586c3ea99a1a 7dc0c53138a13a1f7fffffff00000000 0997ec02ced0e2dd5de2586c3ea99a1a fpscr=00000000
+vcvtn.s32.f32 d0, d20 c360b7194a7910d21974c580b61a14e4 f2d74e37583605f9aa9c090ab94fcea2 c360b7194a7910d20000000000000000 f2d74e37583605f9aa9c090ab94fcea2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtn.s32.f32 d0, d20 7c264d937c264d9380e68e738d8d1ca2 e962c28197bec9b7b072fd55497a3e94 7c264d937c264d9300000000000fa3e9 e962c28197bec9b7b072fd55497a3e94 fpscr=00000000
+vcvtn.s32.f32 d0, d20 e66917efb13f2926ca9435ce3a0c80e6 124b8e212c402b8dd9c8532eebddd756 e66917efb13f29268000000080000000 124b8e212c402b8dd9c8532eebddd756 fpscr=00000000
+vcvtn.s32.f32 d0, d20 d8c899d39c0d866eeb2856c87ce84c36 4987e62b72cb43e9655a86a78308729d d8c899d39c0d866e7fffffff00000000 4987e62b72cb43e9655a86a78308729d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtn.s32.f32 d0, d20 de04636bc4ae7cd8fd0840c9e9acd83a 16494db597162d46154d07957211b32d de04636bc4ae7cd8000000007fffffff 16494db597162d46154d07957211b32d fpscr=00000000
+vcvtn.s32.f32 d0, d20 954f50d62ab99b8e422adb1f55cd817a dc20163693b0ea4a967a9cc322f70aff 954f50d62ab99b8e0000000000000000 dc20163693b0ea4a967a9cc322f70aff fpscr=00000000
+vcvtn.s32.f32 d0, d20 e6e12ee56b1ea2365bc5eb57534fef8a 328166eae5b068dccaf1c83f911f2771 e6e12ee56b1ea236ff871be000000000 328166eae5b068dccaf1c83f911f2771 fpscr=00000000
+vcvtn.s32.f32 d0, d20 b7941b107a2e0eb003ef005657405947 190e78985465175763d958a6e599570f b7941b107a2e0eb07fffffff80000000 190e78985465175763d958a6e599570f fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[1]
+vcvtn.s32.f32 d0, d20 8807e6ec63156977dda5400a6239bedf 4b7758cc7668e4fa4b7758cc79a0672f 8807e6ec6315697700f758cc7fffffff 4b7758cc7668e4fa4b7758cc79a0672f fpscr=00000000
+vcvtn.s32.f32 d0, d20 69c9f89102cafa9f29e71eb7eb00a837 983f744d77759a0146c312ca353ecded 69c9f89102cafa9f0000618900000000 983f744d77759a0146c312ca353ecded fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtn.s32.f32 d0, d20 c79bcc5798900aac8bd5049e3ba2506a 40a8b27a6beddcb0e6c72a02c940ef31 c79bcc5798900aac80000000fff3f10d 40a8b27a6beddcb0e6c72a02c940ef31 fpscr=00000000
+vcvtn.s32.f32 d0, d20 7ce9a7fe4c74632ef8d0648f63ab9c69 9c2f61bc0e33b2e83140b74ff3b1f139 7ce9a7fe4c74632e0000000080000000 9c2f61bc0e33b2e83140b74ff3b1f139 fpscr=00000000
+vcvtn.s32.f32 d0, d20 b17829aecf88572078b37365d06b2ea4 8e0e1f65411e028e1fdb3c344d8a5dc7 b17829aecf88572000000000114bb8e0 8e0e1f65411e028e1fdb3c344d8a5dc7 fpscr=00000000
+vcvtn.s32.f32 d0, d20 b93db5ae0f5bfa615985b13517335622 287afd6a491a6cac201e39219c4ebfeb b93db5ae0f5bfa610000000000000000 287afd6a491a6cac201e39219c4ebfeb fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtn.s32.f32 d0, d20 eb196ddc2c3778122b7a0a347dbf141c 959e936970c54051cc3dadcb178ee6d5 eb196ddc2c377812fd0948d400000000 959e936970c54051cc3dadcb178ee6d5 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvta.s32.f32 d5, d25 2107cfe80b56122a1b0e432b70a566b4 a2ca2a31352c3d5fa2ca2a31b586f5d7 00000000000000001b0e432b70a566b4 a2ca2a31352c3d5fa2ca2a31b586f5d7 fpscr=00000000
+vcvta.s32.f32 d5, d25 3c7f303c68a6468a0ed04021225324d4 288326fd977a13196a5c4415deca6862 00000000000000000ed04021225324d4 288326fd977a13196a5c4415deca6862 fpscr=00000000
+vcvta.s32.f32 d5, d25 c2f608fb3a0510b557bdece6f3514170 65bd3d189981e573509ccfa47f7e0f62 7fffffff0000000057bdece6f3514170 65bd3d189981e573509ccfa47f7e0f62 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[2]
+vcvta.s32.f32 d5, d25 8f6b76fa73c7b0be1c618d00b41b29b6 d3fb715d79ab0af7d3fb715d12434a1d 800000007fffffff1c618d00b41b29b6 d3fb715d79ab0af7d3fb715d12434a1d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvta.s32.f32 d5, d25 d772292b53cf041e87c012df0cc3d2cb cc3512ea2b3d7a328ae2731b9bdecf31 fd2bb4580000000087c012df0cc3d2cb cc3512ea2b3d7a328ae2731b9bdecf31 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvta.s32.f32 d5, d25 5de6189d9d4f03242729b79630b0ca78 259eaf116b05ea8858abbd3c4b61a2ee 000000007fffffff2729b79630b0ca78 259eaf116b05ea8858abbd3c4b61a2ee fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvta.s32.f32 d5, d25 e8e6059f1bdfecd87bfe094fdee12927 087e07332014fe95031ed8f5031ed8f5 00000000000000007bfe094fdee12927 087e07332014fe95031ed8f5031ed8f5 fpscr=00000000
+vcvta.s32.f32 d5, d25 0a53bc02e5653c18f74345630cb84732 c135b50071b99bc148b6cce412777f92 fffffff57ffffffff74345630cb84732 c135b50071b99bc148b6cce412777f92 fpscr=00000000
+vcvta.s32.f32 d5, d25 1ed381d99774639bcf27d29a0dfc4cf9 711efc19160da5d0486f299f91f38569 7fffffff00000000cf27d29a0dfc4cf9 711efc19160da5d0486f299f91f38569 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvta.s32.f32 d5, d25 4d2b02f7eb06ffcdb3467381114c0a4b 7ca21255c6233292700c3ee0a5979177 7fffffffffffd733b3467381114c0a4b 7ca21255c6233292700c3ee0a5979177 fpscr=00000000
+vcvta.s32.f32 d5, d25 916791b4aaba219e10893df86becbfa9 c610d60ff7b25975f3475dc69e50ad93 ffffdbca8000000010893df86becbfa9 c610d60ff7b25975f3475dc69e50ad93 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.s32.f32 d5, d25 b5ae01eb436fbc73975ad1bdf2047588 e2ceb7e446e85255470497bb78e51566 8000000000007429975ad1bdf2047588 e2ceb7e446e85255470497bb78e51566 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[2]
+vcvta.s32.f32 d5, d25 d48390d0639c2153639c215378ac9e82 2dfa8f66cbf5fde8e51258aa2dfa8f66 00000000fe140430639c215378ac9e82 2dfa8f66cbf5fde8e51258aa2dfa8f66 fpscr=00000000
+vcvta.s32.f32 d5, d25 1435b0e9a2453e9f61b120f3a66c1ded 9c50471fbf4653d5a23d679f8eae9501 00000000ffffffff61b120f3a66c1ded 9c50471fbf4653d5a23d679f8eae9501 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.s32.f32 d5, d25 0c274fb8352d55cc447ca0682a4e00a7 d11689ea420af7033d8cb420420af703 8000000000000023447ca0682a4e00a7 d11689ea420af7033d8cb420420af703 fpscr=00000000
+vcvta.s32.f32 d5, d25 4eeec21ff2ad6d933347d422fa903eb0 cf2b9ed9e3b6b1802ea25225a04e9403 80000000800000003347d422fa903eb0 cf2b9ed9e3b6b1802ea25225a04e9403 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.s32.f32 d5, d25 a9a40bf7bc84c4bfccc733b80cc652f2 13c1b59ca4b95aa593eb8526c567d731 0000000000000000ccc733b80cc652f2 13c1b59ca4b95aa593eb8526c567d731 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvta.s32.f32 d5, d25 032f682e9aa3d3495b4c029acce570b6 991f03db778f5e5111c81e37a7005973 000000007fffffff5b4c029acce570b6 991f03db778f5e5111c81e37a7005973 fpscr=00000000
+vcvta.s32.f32 d5, d25 fab8617aa3045e8da7499a966cabc46e 02db84042c34f82a09e0c17265fe1b1e 0000000000000000a7499a966cabc46e 02db84042c34f82a09e0c17265fe1b1e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvta.s32.f32 d5, d25 5a11242546b63b9f96845c8043f5c890 2561866c9d6f62cbbd8edf719d19d599 000000000000000096845c8043f5c890 2561866c9d6f62cbbd8edf719d19d599 fpscr=00000000
+vcvta.s32.f32 d5, d25 529de79367d1c4d339817a83eea6abb5 14be9e9b1493aee64d8460c44584a863 000000000000000039817a83eea6abb5 14be9e9b1493aee64d8460c44584a863 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.s32.f32 d5, d25 8ece12c539f59d4039f59d40bdeef6fd 013d6284d48d30b9fa6101d6ed3179a3 000000008000000039f59d40bdeef6fd 013d6284d48d30b9fa6101d6ed3179a3 fpscr=00000000
+vcvta.s32.f32 d5, d25 a3e92ae2309c490efc846864c08d7139 dc9331074c7a057b47fd2ca77a549096 8000000003e815ecfc846864c08d7139 dc9331074c7a057b47fd2ca77a549096 fpscr=00000000
+vcvta.s32.f32 d5, d25 29820855518361865870869b2c5ee8e9 0799d581747837d94821936f613c4997 000000007fffffff5870869b2c5ee8e9 0799d581747837d94821936f613c4997 fpscr=00000000
+vcvta.s32.f32 d5, d25 74c9cdbb87af17ae96b24cc4047dc544 4bb63993ba6a7af991fb0d0635108e41 016c73260000000096b24cc4047dc544 4bb63993ba6a7af991fb0d0635108e41 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[2]
+vcvta.s32.f32 d5, d25 79d9e89857533c67a3019fbd897fd322 f66efc42f66efc42b0ef1c227ca5d887 8000000080000000a3019fbd897fd322 f66efc42f66efc42b0ef1c227ca5d887 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvta.s32.f32 d5, d25 fd0742da99f8beecfbe1d01f1b2a82c2 d5b2c4ca78d0673ab0fab2a29e778517 800000007ffffffffbe1d01f1b2a82c2 d5b2c4ca78d0673ab0fab2a29e778517 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvta.s32.f32 d5, d25 cc3d7a303ac73f42cc3d7a3011541b8d d3ea3c5dd0b77e28acc80299703482a7 8000000080000000cc3d7a3011541b8d d3ea3c5dd0b77e28acc80299703482a7 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvta.s32.f32 d5, d25 4a8450af0e9c70e2a7d073a84a8450af 5228531553a960960f62a44af034038e 7fffffff7fffffffa7d073a84a8450af 5228531553a960960f62a44af034038e fpscr=00000000
+vcvta.s32.f32 d5, d25 dc0dc728e939ec40cfd282820b8653ab c330ff3cde6397ee382655d968bf4aef ffffff4f80000000cfd282820b8653ab c330ff3cde6397ee382655d968bf4aef fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvta.s32.f32 d5, d25 67677fc4e8d0f6954cc7e6d307c26d7f d1d56fbfe59cb4d8d1d56fbfd6345f5e 80000000800000004cc7e6d307c26d7f d1d56fbfe59cb4d8d1d56fbfd6345f5e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvta.s32.f32 d5, d25 debce70d315f83bbbadd5b89debce70d bc3b51e54362b25834edcb96ca49dda4 00000000000000e3badd5b89debce70d bc3b51e54362b25834edcb96ca49dda4 fpscr=00000000
+vcvta.s32.f32 d5, d25 da89a974b76cdd5cc6bc8036ab75178a 1c654903a47347780bae9ba123e41aed 0000000000000000c6bc8036ab75178a 1c654903a47347780bae9ba123e41aed fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.s32.f32 d5, d25 546d05f7bad43230bad43230bdc47ec2 00ed527a06378161aa8356f1bbbabfaa 0000000000000000bad43230bdc47ec2 00ed527a06378161aa8356f1bbbabfaa fpscr=00000000
+vcvta.s32.f32 d5, d25 148f0a3fb53f2caa9da241254780287b ca865796d9ed524893489fb24ef97896 ffbcd435800000009da241254780287b ca865796d9ed524893489fb24ef97896 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvta.s32.f32 d5, d25 8c949e983da1c96b2fba2f03209afee3 deb34758d59f0447ba687307ba687307 80000000800000002fba2f03209afee3 deb34758d59f0447ba687307ba687307 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.s32.f32 d5, d25 c0a73a6297a07adcfbe8cbd256227927 6d3c17e176b1d7d715118335481ef07f 7fffffff7ffffffffbe8cbd256227927 6d3c17e176b1d7d715118335481ef07f fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvta.s32.f32 d5, d25 56b2a9027cc243fc9c391d4bc0e42431 966610f090ae261e86b7769786b77697 00000000000000009c391d4bc0e42431 966610f090ae261e86b7769786b77697 fpscr=00000000
+vcvta.s32.f32 d5, d25 d7f012eb7aa087435a14c1972eb1b852 f663ba43e4d4c2d9bd9fc2c3cf52414b 80000000800000005a14c1972eb1b852 f663ba43e4d4c2d9bd9fc2c3cf52414b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.s32.f32 d5, d25 a67c574ea95d4b50b81d0516a95d4b50 eb79288b373efc154b72d136ab71e304 8000000000000000b81d0516a95d4b50 eb79288b373efc154b72d136ab71e304 fpscr=00000000
+vcvta.s32.f32 d5, d25 8d637e1428d579183b8772353dfd6a3f c31217370a011bbd8740b729670dd5a4 ffffff6e000000003b8772353dfd6a3f c31217370a011bbd8740b729670dd5a4 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[2]
+randV128: 13568 calls, 14026 iters
+vcvta.s32.f32 d5, d25 34ef517fa09363b3104022660f5108fe af2fbd52903a12766f8291e93672aaf2 0000000000000000104022660f5108fe af2fbd52903a12766f8291e93672aaf2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[3]
+vcvta.s32.f32 d5, d25 3c3d2b430b43f4acf46f3946c3400eb5 f44177748823b69b36c02d44da5a6526 8000000000000000f46f3946c3400eb5 f44177748823b69b36c02d44da5a6526 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.s32.f32 d5, d25 caace0b6a04822c76bbd497cb3c38af1 3fd1c1d49821ef2133b613b0899e40e8 00000002000000006bbd497cb3c38af1 3fd1c1d49821ef2133b613b0899e40e8 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvta.s32.f32 d5, d25 6e689051586c9d0b22a4e0c525cca7f1 257284a8acda8435e8bda75fb56bf093 000000000000000022a4e0c525cca7f1 257284a8acda8435e8bda75fb56bf093 fpscr=00000000
+vcvta.s32.f32 d5, d25 c0059b7263e4253313c31c6d2f84deb3 26d8a13a1d1920f06b40298754480ed3 000000000000000013c31c6d2f84deb3 26d8a13a1d1920f06b40298754480ed3 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvta.s32.f32 d5, d25 adec28ea1539d8d9660f62834d39ab45 0952db9d1da76ec79a96cdb7650b7f33 0000000000000000660f62834d39ab45 0952db9d1da76ec79a96cdb7650b7f33 fpscr=00000000
+vcvta.s32.f32 d5, d25 03b1984cb7a96b7a4d8f64ff29cd1bd5 eb3bd2cad7f9087c5401b243cb238930 80000000800000004d8f64ff29cd1bd5 eb3bd2cad7f9087c5401b243cb238930 fpscr=00000000
+vcvta.s32.f32 d5, d25 c26d77614eff34a6b1222db08b90dd3f 24492b7be153a67c5c61dae0a544b623 0000000080000000b1222db08b90dd3f 24492b7be153a67c5c61dae0a544b623 fpscr=00000000
+vcvta.s32.f32 d5, d25 9e50a00715aa85b60a6b0d74af8ac9fb 63602b281909e55ba6596b89a5245180 7fffffff000000000a6b0d74af8ac9fb 63602b281909e55ba6596b89a5245180 fpscr=00000000
+vcvtp.s32.f32 d10, d30 b5473b5d7c1fac6e5e09a785c5636790 82eb3db81435cdb2d38f673f8430cebf b5473b5d7c1fac6e8000000000000000 82eb3db81435cdb2d38f673f8430cebf fpscr=00000000
+vcvtp.s32.f32 d10, d30 51a9e0e2aaf8ebaf39cb17955f46f3c6 689284e91a801f142d40023446a5ff64 51a9e0e2aaf8ebaf0000000100005300 689284e91a801f142d40023446a5ff64 fpscr=00000000
+vcvtp.s32.f32 d10, d30 ac8c2be11cdb4ddd6442f0cf3432415e b43c0ce55a3f400886b2d3de8ce2ab0d ac8c2be11cdb4ddd0000000000000000 b43c0ce55a3f400886b2d3de8ce2ab0d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtp.s32.f32 d10, d30 79a99dd603eff320f245669479a99dd6 ccec7d8a7e23b7d9b2cfc8bd6e4eeb6a 79a99dd603eff320000000007fffffff ccec7d8a7e23b7d9b2cfc8bd6e4eeb6a fpscr=00000000
+vcvtp.s32.f32 d10, d30 20666f5d6a313a9f68da45b30b081de9 d828389de3d59c09573e08c600e9710d 20666f5d6a313a9f7fffffff00000001 d828389de3d59c09573e08c600e9710d fpscr=00000000
+vcvtp.s32.f32 d10, d30 ece9388014917889b19a8b120c1e64c9 e0438d83769c42466651652d906725c2 ece93880149178897fffffff00000000 e0438d83769c42466651652d906725c2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vcvtp.s32.f32 d10, d30 1456cb4d380e9b3d8b4ce4091456cb4d 18618b5b35258f47c1c44fea94ea36c2 1456cb4d380e9b3dffffffe800000000 18618b5b35258f47c1c44fea94ea36c2 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.s32.f32 d10, d30 730dea338874e69d654268912bc2989d a0339c73744cbf52744cbf5227ccbbb7 730dea338874e69d7fffffff00000001 a0339c73744cbf52744cbf5227ccbbb7 fpscr=00000000
+vcvtp.s32.f32 d10, d30 c26e4789315aba32958fa43d027b3a32 d26211d7f1576225f9f4d33c6a4e4eed c26e4789315aba32800000007fffffff d26211d7f1576225f9f4d33c6a4e4eed fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.s32.f32 d10, d30 288cdf8a20206493d78030fb20206493 ca4ebecd391de9d0d87c40b3ccc6a406 288cdf8a2020649380000000f9cadfd0 ca4ebecd391de9d0d87c40b3ccc6a406 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[3]
+vcvtp.s32.f32 d10, d30 1d661e167441dc4e7441dc4e3a411088 ed7f0e990afa9f01f421cd6b0fb9de5d 1d661e167441dc4e8000000000000001 ed7f0e990afa9f01f421cd6b0fb9de5d fpscr=00000000
+vcvtp.s32.f32 d10, d30 72bffdffadcd1d14651abf2935409753 75f8c1fb9abbd5d4ec32a6a9047b95ff 72bffdffadcd1d148000000000000001 75f8c1fb9abbd5d4ec32a6a9047b95ff fpscr=00000000
+vcvtp.s32.f32 d10, d30 a5385164eafc27d611277a2f4390ca07 6f2e65d0159090aab6b7cc5bb2991b3a a5385164eafc27d60000000000000000 6f2e65d0159090aab6b7cc5bb2991b3a fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtp.s32.f32 d10, d30 adca8e945f40f82ab42619c46859f0ba f8b33e5e103f6487a9b26599415f32f2 adca8e945f40f82a000000000000000e f8b33e5e103f6487a9b26599415f32f2 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtp.s32.f32 d10, d30 3e9fa69a92687a774f128580890ad36c 241471406e81e60e4fdfdbcd7439ce57 3e9fa69a92687a777fffffff7fffffff 241471406e81e60e4fdfdbcd7439ce57 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtp.s32.f32 d10, d30 6f8466f7afe30d843a5a7b73b4895fed e7baa8be1676a5e501040f4fc046ad24 6f8466f7afe30d8400000001fffffffd e7baa8be1676a5e501040f4fc046ad24 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtp.s32.f32 d10, d30 64de919424dcce0941cb0252e756b227 b2e4051c6d473b34a5784d4942fc5266 64de919424dcce09000000000000007f b2e4051c6d473b34a5784d4942fc5266 fpscr=00000000
+vcvtp.s32.f32 d10, d30 e3b03e880f56d3d2150218da090f5428 a33a9e6122693a3cff10fc8f8d57d984 e3b03e880f56d3d28000000000000000 a33a9e6122693a3cff10fc8f8d57d984 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.s32.f32 d10, d30 66bbe0066b97847f8892d8222a9c132e c70903cccde0b252c18afe20cde0b252 66bbe0066b97847fffffffefe3e9b5c0 c70903cccde0b252c18afe20cde0b252 fpscr=00000000
+vcvtp.s32.f32 d10, d30 71f1344b7d9d41ad6e8fc057ac9ab2d1 af6feac66b12302a3801b78cb89edb12 71f1344b7d9d41ad0000000100000000 af6feac66b12302a3801b78cb89edb12 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.s32.f32 d10, d30 25cfe1b6e31bc80fe31bc80f0c60c350 b2cc61ece383675be59d9bd260ae743e 25cfe1b6e31bc80f800000007fffffff b2cc61ece383675be59d9bd260ae743e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtp.s32.f32 d10, d30 c479e4ffc479e4ffd7f8136d0d154829 0c62397fb44cc35fbb0e65cfb2bc18f8 c479e4ffc479e4ff0000000000000000 0c62397fb44cc35fbb0e65cfb2bc18f8 fpscr=00000000
+vcvtp.s32.f32 d10, d30 836692a2d9f94558f7417d86e0508e03 a156aadab56e463dc36900034d41adef 836692a2d9f94558ffffff170c1adef0 a156aadab56e463dc36900034d41adef fpscr=00000000
+vcvtp.s32.f32 d10, d30 cb8efff1ea7fd791d729e78f7d46d10b 196eaef91cf561406d5e2798a4f4843d cb8efff1ea7fd7917fffffff00000000 196eaef91cf561406d5e2798a4f4843d fpscr=00000000
+vcvtp.s32.f32 d10, d30 8db92c261b9cc1d5a5ad3a081591bdef 9ef94c0a3eb4c76fcaff94518adf0ac2 8db92c261b9cc1d5ff8035d800000000 9ef94c0a3eb4c76fcaff94518adf0ac2 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtp.s32.f32 d10, d30 4ffece8c8c8a2352c7fc786aa864c623 4b622f55a42991d1f003bf894a6b5664 4ffece8c8c8a235280000000003ad599 4b622f55a42991d1f003bf894a6b5664 fpscr=00000000
+vcvtp.s32.f32 d10, d30 e1eb6f55808192120ddb9e2da093e4bc 73dd892175574f103e40069df06df010 e1eb6f55808192120000000180000000 73dd892175574f103e40069df06df010 fpscr=00000000
+vcvtp.s32.f32 d10, d30 3e203c42da8d6c7205180626e06e7c93 f432e051ddbc86837d867f490557a6b5 3e203c42da8d6c727fffffff00000001 f432e051ddbc86837d867f490557a6b5 fpscr=00000000
+vcvtp.s32.f32 d10, d30 f962d27ba55fe68dd110c18e54430d19 0da3e68b202d6df2fa325c15ba96b96b f962d27ba55fe68d8000000000000000 0da3e68b202d6df2fa325c15ba96b96b fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtp.s32.f32 d10, d30 871c5368871c5368018c6fb52853ce87 7348fc1530ccb54a1aac3e3561c9aba0 871c5368871c5368000000017fffffff 7348fc1530ccb54a1aac3e3561c9aba0 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.s32.f32 d10, d30 36d165124a57dacef06960b298eeb289 4a1ff60f1cbe66ff7ec56cd5226a2eab 36d165124a57dace7fffffff00000001 4a1ff60f1cbe66ff7ec56cd5226a2eab fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[3]
+vcvtp.s32.f32 d10, d30 a3e024d0eefe9a4aeefe9a4ace6912cf 0c741d448b7382ce8157d7380c741d44 a3e024d0eefe9a4a0000000000000001 0c741d448b7382ce8157d7380c741d44 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[2]
+vcvtp.s32.f32 d10, d30 e7c6409b6131abbabbbe3ee7def9373e c169bd6ae49ae989e49ae98976da4654 e7c6409b6131abba800000007fffffff c169bd6ae49ae989e49ae98976da4654 fpscr=00000000
+vcvtp.s32.f32 d10, d30 2d437e6b0d2ecb304571028b6b4da579 7511352cda8b4d0f41fc9192fe04b14e 2d437e6b0d2ecb300000002080000000 7511352cda8b4d0f41fc9192fe04b14e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.s32.f32 d10, d30 9101fdc1c031b92c0134f9c60823ce9b 85e9c88f8de690fd6667ca808b49f57d 9101fdc1c031b92c7fffffff00000000 85e9c88f8de690fd6667ca808b49f57d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[1]
+vcvtp.s32.f32 d10, d30 bccbaf0566cf1d31c81276b5c81276b5 755703750845adda82298fcd82298fcd bccbaf0566cf1d310000000000000000 755703750845adda82298fcd82298fcd fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtp.s32.f32 d10, d30 ff2633322d6e57adff263332597a2702 8cef6726264f4da99ac068b79b5f1900 ff2633322d6e57ad0000000000000000 8cef6726264f4da99ac068b79b5f1900 fpscr=00000000
+vcvtp.s32.f32 d10, d30 ed90abe0f5cb88c29a296253e3632455 d3ade5f1565e79b6d5a1951b7b849675 ed90abe0f5cb88c2800000007fffffff d3ade5f1565e79b6d5a1951b7b849675 fpscr=00000000
+vcvtp.s32.f32 d10, d30 026b0e0750f03b8e208bace3fb90b05a 817c3d99860cc32a36744f2dedf322bf 026b0e0750f03b8e0000000180000000 817c3d99860cc32a36744f2dedf322bf fpscr=00000000
+vcvtp.s32.f32 d10, d30 a6d5f4ec9ac8e2a1e81a11bafa378054 c11b4e88c1122fdcbd77a2c00e91c9eb a6d5f4ec9ac8e2a10000000000000001 c11b4e88c1122fdcbd77a2c00e91c9eb fpscr=00000000
+vcvtp.s32.f32 d10, d30 14c751d7198e1b3dad8d52a714ee8c46 e509fd1870a52b3ad47a41515a4f6414 14c751d7198e1b3d800000007fffffff e509fd1870a52b3ad47a41515a4f6414 fpscr=00000000
+vcvtp.s32.f32 d10, d30 f3e785215d29be6aac2d93c99a9abdfa f68d95ad031b0b06202727559915535a f3e785215d29be6a0000000100000000 f68d95ad031b0b06202727559915535a fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.s32.f32 d10, d30 42455641c40c731dccce93e5c092bc70 2319fe2781f065692fab15f4b002203a 42455641c40c731d0000000100000000 2319fe2781f065692fab15f4b002203a fpscr=00000000
+vcvtp.s32.f32 d10, d30 1afa400296f748bd61f6a64c21b43f8f 4b1d50e60d11e6b9f62c536a08b7f01b 1afa400296f748bd8000000000000001 4b1d50e60d11e6b9f62c536a08b7f01b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.s32.f32 d10, d30 43142335c79b4df4418cdfdcd348a93d c056ac21f5f1b321c2298dc294e9fff9 43142335c79b4df4ffffffd600000000 c056ac21f5f1b321c2298dc294e9fff9 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.s32.f32 d10, d30 ccddb1e4e0cf12d8e0cf12d8786765bf c7b2b9b67e1af850ccd56b3ac4bb6a13 ccddb1e4e0cf12d8f954a630fffffa25 c7b2b9b67e1af850ccd56b3ac4bb6a13 fpscr=00000000
+vcvtp.s32.f32 d10, d30 f64ec2c6405ffdc9205e6df76cb2bd81 937f59a4e993c9c110e512cdde3b01cf f64ec2c6405ffdc90000000180000000 937f59a4e993c9c110e512cdde3b01cf fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtp.s32.f32 d10, d30 294f72a7f92919a4e9f40eb5a4c492a2 376d4b3352648f410ae4bf29418d7851 294f72a7f92919a40000000100000012 376d4b3352648f410ae4bf29418d7851 fpscr=00000000
+vcvtp.s32.f32 d10, d30 77c470b81d6f63929ed33a731cf2a4d1 293501ee00de5bf6d3452d008b42323d 77c470b81d6f63928000000000000000 293501ee00de5bf6d3452d008b42323d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.s32.f32 d10, d30 86c1806c8bf96e331190ca2a35639a8a f2cc49d5479db15d404e72a386fa8733 86c1806c8bf96e330000000400000000 f2cc49d5479db15d404e72a386fa8733 fpscr=00000000
+vcvtm.s32.f32 d15, d15 40727fdd55c630bddd57ee188be3443e 26973ad3a0d30d682dbed31011ad1de3 00000000ffffffff2dbed31011ad1de3 00000000ffffffff2dbed31011ad1de3 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtm.s32.f32 d15, d15 270ce7ec75f74ffbecf3c831dee65b97 43eebd5c0a9e3cdb0a9e3cdb5fa0f311 000001dd000000000a9e3cdb5fa0f311 000001dd000000000a9e3cdb5fa0f311 fpscr=00000000
+vcvtm.s32.f32 d15, d15 c94730b1ad3e21738938dd2ea02c486b 526de5bcafee706429084f2b65e21f26 7fffffffffffffff29084f2b65e21f26 7fffffffffffffff29084f2b65e21f26 fpscr=00000000
+vcvtm.s32.f32 d15, d15 1d404b6610444f6ec5647cb3a8cd5878 d1522d5d92ce164902f8b532456a45d6 80000000ffffffff02f8b532456a45d6 80000000ffffffff02f8b532456a45d6 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtm.s32.f32 d15, d15 62fdec3a51cced2291b7dd89396a182a 498ea9ae498ea9ae8da0d5be0c167139 0011d5350011d5358da0d5be0c167139 0011d5350011d5358da0d5be0c167139 fpscr=00000000
+randV128: 13824 calls, 14294 iters
+vcvtm.s32.f32 d15, d15 fa2c28055a10d0d74c345c23eb212cff f01c445d07d6ea3c198c462a1c2aa5c5 8000000000000000198c462a1c2aa5c5 8000000000000000198c462a1c2aa5c5 fpscr=00000000
+vcvtm.s32.f32 d15, d15 f03a1b7bdcc20ed0727d9431d8b81ea6 7552c4cf2cf34fca1e883279230da44e 7fffffff000000001e883279230da44e 7fffffff000000001e883279230da44e fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtm.s32.f32 d15, d15 1144c219caab8322452fa732641b8e6d de73a405adad337e2ec989a4660b8423 80000000ffffffff2ec989a4660b8423 80000000ffffffff2ec989a4660b8423 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtm.s32.f32 d15, d15 58547e50c93c3f3d1b837887652c9a58 934b731ac64913a06553a09d06a800f4 ffffffffffffcdbb6553a09d06a800f4 ffffffffffffcdbb6553a09d06a800f4 fpscr=00000000
+vcvtm.s32.f32 d15, d15 83c312cf09ad3b00f2061a0204bf419a 6846fd1f71d7efb4f0894e38d4a440a8 7fffffff7ffffffff0894e38d4a440a8 7fffffff7ffffffff0894e38d4a440a8 fpscr=00000000
+vcvtm.s32.f32 d15, d15 111b42f8033a2579cb790892050b7717 7ef41b5ac8d85a4e317ef73e690e7eeb 7ffffffffff93d2d317ef73e690e7eeb 7ffffffffff93d2d317ef73e690e7eeb fpscr=00000000
+vcvtm.s32.f32 d15, d15 8bb3426cc657024efecbbf5e197a9f69 cce4a7c3fe17d646d25d29bdc4ab0bcb f8dac1e880000000d25d29bdc4ab0bcb f8dac1e880000000d25d29bdc4ab0bcb fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtm.s32.f32 d15, d15 78f1bfa73fb8f3d278f1bfa7e5b4ca4c e578055fa1636b44ce5101ebdac7d352 80000000ffffffffce5101ebdac7d352 80000000ffffffffce5101ebdac7d352 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtm.s32.f32 d15, d15 38c6383a5011d593068ae7bb5efd1da0 f9264e05671a06f18e5bd129671a06f1 800000007fffffff8e5bd129671a06f1 800000007fffffff8e5bd129671a06f1 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[2]
+vcvtm.s32.f32 d15, d15 e753989c9b48833ae753989c9b928f2f d30e5990c3a0488473f689fdd53898f6 80000000fffffebf73f689fdd53898f6 80000000fffffebf73f689fdd53898f6 fpscr=00000000
+vcvtm.s32.f32 d15, d15 38479ba2b94e587482ad07cb7d939f1a b634ea050ed0074727f34b460d0f3e2e ffffffff0000000027f34b460d0f3e2e ffffffff0000000027f34b460d0f3e2e fpscr=00000000
+vcvtm.s32.f32 d15, d15 b479bce403a59e41f65d819d7ec8ba22 1e1bb83e533cd785f06664958e9d8a3e 000000007ffffffff06664958e9d8a3e 000000007ffffffff06664958e9d8a3e fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtm.s32.f32 d15, d15 ec7558d9715b0f473703e711cd2753a2 55f22c4271285b146fa59c831b0fd443 7fffffff7fffffff6fa59c831b0fd443 7fffffff7fffffff6fa59c831b0fd443 fpscr=00000000
+vcvtm.s32.f32 d15, d15 4f9adef0abb63217bf6d731b244404f1 9fe4f382370cb63197612e613aa45c46 ffffffff0000000097612e613aa45c46 ffffffff0000000097612e613aa45c46 fpscr=00000000
+vcvtm.s32.f32 d15, d15 6f1bb4a51a3078ce1a6a40f9f8d1711b 5f5a0ed3a992974e261b55baa42e749a 7fffffffffffffff261b55baa42e749a 7fffffffffffffff261b55baa42e749a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.s32.f32 d15, d15 385eccab68f93d7fe6bf2f153b514e6e 1d6494fe2faa0bf6ea390a70975480fb 0000000000000000ea390a70975480fb 0000000000000000ea390a70975480fb fpscr=00000000
+vcvtm.s32.f32 d15, d15 c7e99894d4a15e4dd9137155c35992a6 0824d8d78b6ce38dca85ac82ddcec2b9 00000000ffffffffca85ac82ddcec2b9 00000000ffffffffca85ac82ddcec2b9 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.s32.f32 d15, d15 6e6dd07548facb6cf40e2daa3efd36c0 bc4d0c9409415afd8d2d00bf48bd2f9a ffffffff000000008d2d00bf48bd2f9a ffffffff000000008d2d00bf48bd2f9a fpscr=00000000
+vcvtm.s32.f32 d15, d15 432bfbb09c960a7c8b474ffe77445fbf 04839c3e4051983c39cb9b220ca6208f 000000000000000339cb9b220ca6208f 000000000000000339cb9b220ca6208f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.s32.f32 d15, d15 a3ba0d1ba3ba0d1b8496f597978b8010 9e5120380f7b3cbcd2dd80c1d0e6a408 ffffffff00000000d2dd80c1d0e6a408 ffffffff00000000d2dd80c1d0e6a408 fpscr=00000000
+vcvtm.s32.f32 d15, d15 653daa2dfa8dd846d830d796c170587d 2f83f435711be5d9dd931c6ef3f431e6 000000007fffffffdd931c6ef3f431e6 000000007fffffffdd931c6ef3f431e6 fpscr=00000000
+vcvtm.s32.f32 d15, d15 6e372721d39e639c3f827e4152164a5e d9a736fd985a124af055bbc358e5bfa3 80000000fffffffff055bbc358e5bfa3 80000000fffffffff055bbc358e5bfa3 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtm.s32.f32 d15, d15 d005bac5ac72e5a48da593debb70f592 205a95e8fa5e83546b974e2efa5e8354 00000000800000006b974e2efa5e8354 00000000800000006b974e2efa5e8354 fpscr=00000000
+vcvtm.s32.f32 d15, d15 4171961beed9b4ce13350dc27e39f534 449afa2f428f96cce949c07e49f9889a 000004d700000047e949c07e49f9889a 000004d700000047e949c07e49f9889a fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.s32.f32 d15, d15 e5cec1a3e1335d64f19ef2fa0fd6f106 da04a54820f5e299125391af19a4a0e2 8000000000000000125391af19a4a0e2 8000000000000000125391af19a4a0e2 fpscr=00000000
+vcvtm.s32.f32 d15, d15 b7f363035a47c10f451e6e7b7021143d 379a6108cffb6b50d209ba063497ae8b 0000000080000000d209ba063497ae8b 0000000080000000d209ba063497ae8b fpscr=00000000
+vcvtm.s32.f32 d15, d15 df3e642d1b9a4988ca967c867a5901f3 e1a843d9aee63dcaa69017616fbaf2c0 80000000ffffffffa69017616fbaf2c0 80000000ffffffffa69017616fbaf2c0 fpscr=00000000
+vcvtm.s32.f32 d15, d15 782cd97f2d728437e067c089546e7389 b69a111c4b8f33cb6669763470980345 ffffffff011e67966669763470980345 ffffffff011e67966669763470980345 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.s32.f32 d15, d15 720f5c17a247ae78e22a4c6ba247ae78 acd6c9d7f9865126e81003345ffc3f86 ffffffff80000000e81003345ffc3f86 ffffffff80000000e81003345ffc3f86 fpscr=00000000
+vcvtm.s32.f32 d15, d15 3aebf8a6cc189a83855c7f1b07e29824 c24359b3bf64dff72b5cb1a7b8742856 ffffffcfffffffff2b5cb1a7b8742856 ffffffcfffffffff2b5cb1a7b8742856 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtm.s32.f32 d15, d15 ee1d8b63ee1d8b639bd307162c3f1e07 7d33f60e2f4a66969eecd4b2eda1e1c5 7fffffff000000009eecd4b2eda1e1c5 7fffffff000000009eecd4b2eda1e1c5 fpscr=00000000
+vcvtm.s32.f32 d15, d15 dcad6e8067dd540e24c8acc75b09ca4e 8bb2b97240c1968d9a83fcf74a5b7ef8 ffffffff000000069a83fcf74a5b7ef8 ffffffff000000069a83fcf74a5b7ef8 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.s32.f32 d15, d15 609b9513076eb928170405dc82c6b67c 196ebe756b409bb4465245f0db5964c4 000000007fffffff465245f0db5964c4 000000007fffffff465245f0db5964c4 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtm.s32.f32 d15, d15 96d02b7e60575c0ce9ec8205057bd062 ac2e8a000ed6083f9776bdf68b0f6e46 ffffffff000000009776bdf68b0f6e46 ffffffff000000009776bdf68b0f6e46 fpscr=00000000
+vcvtm.s32.f32 d15, d15 3568e49afb54e05a59292878aeb1551d cd9323ecd15d437f748de15876be5c27 ed9b828080000000748de15876be5c27 ed9b828080000000748de15876be5c27 fpscr=00000000
+vcvtm.s32.f32 d15, d15 4bede7335c1493a8d4732d5944477e80 70ee7415c89ba55f83b4416cccad5e81 7ffffffffffb22d583b4416cccad5e81 7ffffffffffb22d583b4416cccad5e81 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtm.s32.f32 d15, d15 c265ae4d462a1617cb6d7a792e22ddad ed07535a561c2e9f561c2e9f70e68754 800000007fffffff561c2e9f70e68754 800000007fffffff561c2e9f70e68754 fpscr=00000000
+vcvtm.s32.f32 d15, d15 9b7853f497412cd6417710f315ede355 63b3faace0d2840d6135d3702d91b86c 7fffffff800000006135d3702d91b86c 7fffffff800000006135d3702d91b86c fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.s32.f32 d15, d15 4a6df60e227b5a6a961f4a9199a00927 f0aa4a44444e67510bde209ff1eec74b 80000000000003390bde209ff1eec74b 80000000000003390bde209ff1eec74b fpscr=00000000
+vcvtm.s32.f32 d15, d15 1de3e4110c752acbbf681b585bc8b0e9 5e0b5d0236762a13edc5e2732648d59e 7fffffff00000000edc5e2732648d59e 7fffffff00000000edc5e2732648d59e fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vcvtm.s32.f32 d15, d15 f12072e72927e6f1148092b22927e6f1 503024ecafa8d3981914315d503024ec 7fffffffffffffff1914315d503024ec 7fffffffffffffff1914315d503024ec fpscr=00000000
+vcvtm.s32.f32 d15, d15 9fdfd945eb795552a4978fd7d81dacca 09259bc90acd766624fd27d74fd0ce0b 000000000000000024fd27d74fd0ce0b 000000000000000024fd27d74fd0ce0b fpscr=00000000
+vcvtm.s32.f32 d15, d15 caedcd934deb67a15fd122008b5d99ef 6496026a270dc117370e35a1fc1bd916 7fffffff00000000370e35a1fc1bd916 7fffffff00000000370e35a1fc1bd916 fpscr=00000000
+vcvtm.s32.f32 d15, d15 11a3c5e9e558b918c7533815a978adea 3b3b9973acc96a58d5583c81b53cbaf3 00000000ffffffffd5583c81b53cbaf3 00000000ffffffffd5583c81b53cbaf3 fpscr=00000000
+vcvtm.s32.f32 d15, d15 b8e7bb673e6644c782ed2f556cf9af84 3f1a2065e335754e82957528f367ec67 000000008000000082957528f367ec67 000000008000000082957528f367ec67 fpscr=00000000
+vcvtn.s32.f32 q15, q0 99b12a27e19a5abb0201f4db008d902a 33e6dd97c91dc051f65e2231c65a033a 00000000fff623fb80000000ffffc97f 33e6dd97c91dc051f65e2231c65a033a fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtn.s32.f32 q15, q0 79f4effe4e6a29db17b42fa2be563504 07d60c9a4f5b8fec7d463fca4f5b8fec 000000007fffffff7fffffff7fffffff 07d60c9a4f5b8fec7d463fca4f5b8fec fpscr=00000000
+vcvtn.s32.f32 q15, q0 32e0bf6f91185128a6ace7f9c561bb15 5737dcd92a0676abfb49344c0eb53af4 7fffffff000000008000000000000000 5737dcd92a0676abfb49344c0eb53af4 fpscr=00000000
+vcvtn.s32.f32 q15, q0 53e1885ae978b6cfcde6437ebf49c33c 5855de30269849e341f32ab286b2c018 7fffffff000000000000001e00000000 5855de30269849e341f32ab286b2c018 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtn.s32.f32 q15, q0 35d41ff2265260b54efa5c7f91a2add8 fc5f015e6ebcc489ecff5a35a041044a 800000007fffffff8000000000000000 fc5f015e6ebcc489ecff5a35a041044a fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.s32.f32 q15, q0 9f89cdef2e294fe4d4eb3350c2178d6d 60fac6cea3d11abaa383dd738ac6ea8f 7fffffff000000000000000000000000 60fac6cea3d11abaa383dd738ac6ea8f fpscr=00000000
+vcvtn.s32.f32 q15, q0 c272b813c2aa2e17d3dd61e82ebb7eaa c9999f5717abb57f1ea493eb08128998 ffeccc15000000000000000000000000 c9999f5717abb57f1ea493eb08128998 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtn.s32.f32 q15, q0 53d8cd66c999917cb18ffa4384c81c24 a26e60420ca2168b2bb6df9db6e46f86 00000000000000000000000000000000 a26e60420ca2168b2bb6df9db6e46f86 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.s32.f32 q15, q0 72cfde6d73fccd8e9dfb044f86dc0062 21786dea499601dfe384e91b648b1fe8 000000000012c03c800000007fffffff 21786dea499601dfe384e91b648b1fe8 fpscr=00000000
+vcvtn.s32.f32 q15, q0 fb3cc9be73732ad360882643f866a745 cc41ba594147b5f3dc275348d2f231f9 fcf9169c0000000c8000000080000000 cc41ba594147b5f3dc275348d2f231f9 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.s32.f32 q15, q0 063dbeb76b9fda9f2fbe51e521ff6597 f26241ce6099514674295d701564c7af 800000007fffffff7fffffff00000000 f26241ce6099514674295d701564c7af fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtn.s32.f32 q15, q0 c0d3ad3d73d620edcade3c287efc0691 1439ff9310023815adac342947dc9a7d 0000000000000000000000000001b935 1439ff9310023815adac342947dc9a7d fpscr=00000000
+vcvtn.s32.f32 q15, q0 517a7c93a34e44f56394f5aaa1217e2e 7b6c0755c6fb176836ab23a2cd8655c9 7fffffffffff827400000000ef3546e0 7b6c0755c6fb176836ab23a2cd8655c9 fpscr=00000000
+vcvtn.s32.f32 q15, q0 1618851e71cc863efc555b5de5ad9435 5524f078ccf243080a17d2c3aa673077 7ffffffff86de7c00000000000000000 5524f078ccf243080a17d2c3aa673077 fpscr=00000000
+vcvtn.s32.f32 q15, q0 2817e26324d840f5ea1b587de73d65e9 136ac98b762981b2f6a8b49c581e24a9 000000007fffffff800000007fffffff 136ac98b762981b2f6a8b49c581e24a9 fpscr=00000000
+vcvtn.s32.f32 q15, q0 6fef7bc74db7422511735b8c1c48552e 887c476f1a2f9b98ff64a7e4d8ee3c71 00000000000000008000000080000000 887c476f1a2f9b98ff64a7e4d8ee3c71 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtn.s32.f32 q15, q0 25b9e8956a11973236f2f7b53bca35c5 5341754eea59f23ef7913f11ce35406d 7fffffff8000000080000000d2afe4c0 5341754eea59f23ef7913f11ce35406d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[0]
+vcvtn.s32.f32 q15, q0 58c4fd2dad49ac0d6044706c605944a6 94998bf33855c1033855c1038d5088ef 00000000000000000000000000000000 94998bf33855c1033855c1038d5088ef fpscr=00000000
+vcvtn.s32.f32 q15, q0 d7f69af905aea97ccdc01b4e0596e316 c509246e461f4f1fa3c8d53e79f27f4e fffff76e000027d4000000007fffffff c509246e461f4f1fa3c8d53e79f27f4e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: 14080 calls, 14558 iters
+vcvtn.s32.f32 q15, q0 5c9c7d9703a93212407843cc5c9c7d97 085ea38bd7fe986f00c9cd006b099a39 0000000080000000000000007fffffff 085ea38bd7fe986f00c9cd006b099a39 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtn.s32.f32 q15, q0 90cc47b5bcac4507811d8a98279a7b90 6f84b3d667baa346d921cfec638aa2c3 7fffffff7fffffff800000007fffffff 6f84b3d667baa346d921cfec638aa2c3 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vcvtn.s32.f32 q15, q0 491f484018d5f7f17b460634491f4840 ae4ee4797459cec425d5ee51481674cd 000000007fffffff00000000000259d3 ae4ee4797459cec425d5ee51481674cd fpscr=00000000
+vcvtn.s32.f32 q15, q0 8c4e616c1f20c293dfc3c8ba3a9b6893 e14b186626df43c7d62fdcb8e29d3bee 80000000000000008000000080000000 e14b186626df43c7d62fdcb8e29d3bee fpscr=00000000
+vcvtn.s32.f32 q15, q0 55ffb0a838503c3b8118932069a44f58 4c5801993dd8d15f9689adca9be2403e 03600664000000000000000000000000 4c5801993dd8d15f9689adca9be2403e fpscr=00000000
+vcvtn.s32.f32 q15, q0 4673ebe1617aec32bb53c2141abb21d0 04a22638dc8ce90ec373a37a69245a82 0000000080000000ffffff0c7fffffff 04a22638dc8ce90ec373a37a69245a82 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vcvtn.s32.f32 q15, q0 8eabcf793dd29f32a10d806df3b8d357 6ef36452408000f91aac81d31aac81d3 7fffffff000000040000000000000000 6ef36452408000f91aac81d31aac81d3 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtn.s32.f32 q15, q0 9728cac652149ab5a8ff9253a5bf393a 106ca7df11c6976a65ac172d11c6976a 00000000000000007fffffff00000000 106ca7df11c6976a65ac172d11c6976a fpscr=00000000
+vcvtn.s32.f32 q15, q0 54d41a0477202f3ed10556735eee52b6 156a9c421d0cbd42d8c6c999930a36ad 00000000000000008000000000000000 156a9c421d0cbd42d8c6c999930a36ad fpscr=00000000
+vcvtn.s32.f32 q15, q0 7f6c5ba95544111b0f9c915c71950132 6e97020bff16998641e774299fa3d66c 7fffffff800000000000001d00000000 6e97020bff16998641e774299fa3d66c fpscr=00000000
+vcvtn.s32.f32 q15, q0 b37b23f8114b5e4ee9231276dfa3eb99 a6bdde0c3237a7fc696ff0ab953a7829 00000000000000007fffffff00000000 a6bdde0c3237a7fc696ff0ab953a7829 fpscr=00000000
+vcvtn.s32.f32 q15, q0 fcc86630626944442f109ba4e8712c21 f044cce5dac5721752b3ab8c6c18f4d5 80000000800000007fffffff7fffffff f044cce5dac5721752b3ab8c6c18f4d5 fpscr=00000000
+vcvtn.s32.f32 q15, q0 b23db4e070e5ca5e8e1fc7d1e09ef850 37880c391a270b9d5dd855939a3cc93e 00000000000000007fffffff00000000 37880c391a270b9d5dd855939a3cc93e fpscr=00000000
+vcvtn.s32.f32 q15, q0 b460f4f91b282961762f35e2eceda20e bd65289e0798808d79d490d58ed7e85f 00000000000000007fffffff00000000 bd65289e0798808d79d490d58ed7e85f fpscr=00000000
+vcvtn.s32.f32 q15, q0 a18a5d24fad08c433417129ded07861c ac86808cd701dd5a50108e4e6b2bba6b 00000000800000007fffffff7fffffff ac86808cd701dd5a50108e4e6b2bba6b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtn.s32.f32 q15, q0 0cea407a189b6b25ed7ae710dd6950f7 9c40e68c0cfb6c391283e45175d0995d 0000000000000000000000007fffffff 9c40e68c0cfb6c391283e45175d0995d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtn.s32.f32 q15, q0 63d3b8fe988e577f35f61b7c6acf6ebd 167779529146f3a89146f3a8c0d0cdcb 000000000000000000000000fffffff9 167779529146f3a89146f3a8c0d0cdcb fpscr=00000000
+vcvtn.s32.f32 q15, q0 90db2f68b9666fcca71fe07eebd928a1 d5afa4c7cb84736e8f7740ccd7927e91 80000000fef719240000000080000000 d5afa4c7cb84736e8f7740ccd7927e91 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtn.s32.f32 q15, q0 def62593701d37432ca157bf7f5b1482 3abf05ac5923ef94debc59b7f83ba237 000000007fffffff8000000080000000 3abf05ac5923ef94debc59b7f83ba237 fpscr=00000000
+vcvtn.s32.f32 q15, q0 41e6235ffb5a3160f0d07b335ae26992 7e46bad238f71e7d12af6172b29cda87 7fffffff000000000000000000000000 7e46bad238f71e7d12af6172b29cda87 fpscr=00000000
+vcvtn.s32.f32 q15, q0 a5fcc814bba50d8e5f53ac5bf2849cbf fa26231de528078da07dba6126e48329 80000000800000000000000000000000 fa26231de528078da07dba6126e48329 fpscr=00000000
+vcvtn.s32.f32 q15, q0 a78c97c225581940f7cfc0b52fc80c90 c74d76cca3c3289919e4366ab807ca00 ffff3289000000000000000000000000 c74d76cca3c3289919e4366ab807ca00 fpscr=00000000
+vcvtn.s32.f32 q15, q0 f52fbc85575b1b477dccdae254439eb4 eb439de97628c26cf9d03d5dfcd828c9 800000007fffffff8000000080000000 eb439de97628c26cf9d03d5dfcd828c9 fpscr=00000000
+vcvtn.s32.f32 q15, q0 66bd0b78a5c8f59055d215a10c396cda dc51b8fc9203bf4890682edbdbac43ca 80000000000000000000000080000000 dc51b8fc9203bf4890682edbdbac43ca fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[3]
+vcvtn.s32.f32 q15, q0 b71a3f4aeed590e079770aac00cfe6ae 475d6c4a8b882d4859976eac475d6c4a 0000dd6c000000007fffffff0000dd6c 475d6c4a8b882d4859976eac475d6c4a fpscr=00000000
+vcvtn.s32.f32 q15, q0 dbebbe6801580293feb9382d9b6c5a8e 3d9faa076b9eb96f3d31329ee02fdea9 000000007fffffff0000000080000000 3d9faa076b9eb96f3d31329ee02fdea9 fpscr=00000000
+vcvtn.s32.f32 q15, q0 74793c039e7c95681ed8047f613e902c 56943b8d8ff5deca058ed08ad3a01874 7fffffff000000000000000080000000 56943b8d8ff5deca058ed08ad3a01874 fpscr=00000000
+vcvtn.s32.f32 q15, q0 8b7daa55375de243c28011145d561e12 086b358f995941224b641e2a23d8fc34 000000000000000000e41e2a00000000 086b358f995941224b641e2a23d8fc34 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtn.s32.f32 q15, q0 5c9d4d58d2c1213457eb7bf6255712cc 7be59f49a91cf031edb40823d2cac907 7fffffff000000008000000080000000 7be59f49a91cf031edb40823d2cac907 fpscr=00000000
+vcvtn.s32.f32 q15, q0 6e83083f406dfa14b5095445b9abb682 8f211bdb58469acc3bcf60c183ecb285 000000007fffffff0000000000000000 8f211bdb58469acc3bcf60c183ecb285 fpscr=00000000
+vcvtn.s32.f32 q15, q0 a046ac5ae5befee1b75892c14bd7f368 b354dde1684df0f2a40736e523fd8d39 000000007fffffff0000000000000000 b354dde1684df0f2a40736e523fd8d39 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvta.s32.f32 q14, q1 59bfe8bfb93215af3afc075913dcae10 33c394d16576da4eb13d815dd1b7354f 000000007fffffff0000000080000000 33c394d16576da4eb13d815dd1b7354f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.s32.f32 q14, q1 f627a938f627a93807374fc1b6ca660e 1abb5248730d7e409d11962a842e712f 000000007fffffff0000000000000000 1abb5248730d7e409d11962a842e712f fpscr=00000000
+vcvta.s32.f32 q14, q1 6e90b1bab167e944170858378afe14dc 04ae3d0cce21fc8ab5b9fc2349fdd0ca 00000000d780dd8000000000001fba19 04ae3d0cce21fc8ab5b9fc2349fdd0ca fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.s32.f32 q14, q1 e520104ce520104c045297096084eb87 39b2cd5e9cc94e8efaf600d0b9dd57d8 00000000000000008000000000000000 39b2cd5e9cc94e8efaf600d0b9dd57d8 fpscr=00000000
+vcvta.s32.f32 q14, q1 a339cac64ee62c685cb603e816daeab8 2f7cd63b7d58a02bac2ef44df8178f29 000000007fffffff0000000080000000 2f7cd63b7d58a02bac2ef44df8178f29 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvta.s32.f32 q14, q1 d25d8bec3c3befd356972f863c3befd3 326144a1a0e45200538c1e428dcd0b51 00000000000000007fffffff00000000 326144a1a0e45200538c1e428dcd0b51 fpscr=00000000
+vcvta.s32.f32 q14, q1 a49993d3ea3784485621063da8242a0b b349e09dc9663f39f6d99f0e8809fbd0 00000000fff19c0c8000000000000000 b349e09dc9663f39f6d99f0e8809fbd0 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvta.s32.f32 q14, q1 11f66335113553cd88378f31ebea631f 82aff707edca4bd41502130182aff707 00000000800000000000000000000000 82aff707edca4bd41502130182aff707 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvta.s32.f32 q14, q1 96a05923c63a4a9904ed5aaf73c1f2a2 a62518679556846360116b8160116b81 00000000000000007fffffff7fffffff a62518679556846360116b8160116b81 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.s32.f32 q14, q1 823134177f48373681c5a2ba7f483736 313c4bdd54abce24cc0229a53f93cd86 000000007ffffffffdf7596c00000001 313c4bdd54abce24cc0229a53f93cd86 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[0]
+vcvta.s32.f32 q14, q1 e713cf7e649a36ade4c71e763eef2364 1654f595743dcf81b861ed0f6151b874 000000007fffffff000000007fffffff 1654f595743dcf81b861ed0f6151b874 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.s32.f32 q14, q1 4bd640744d33f3bfc4469290d8008ebd b3e7a67e3158dc60aeb947853158dc60 00000000000000000000000000000000 b3e7a67e3158dc60aeb947853158dc60 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvta.s32.f32 q14, q1 6749ee50db06ca6916e7597a81d88948 7ceca994c75566d27ceca9949d526fe0 7fffffffffff2a997fffffff00000000 7ceca994c75566d27ceca9949d526fe0 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvta.s32.f32 q14, q1 378e2a3826dd9a9c5e0c51b03d86f298 9ee6ac445406d682f67148295f89e979 000000007fffffff800000007fffffff 9ee6ac445406d682f67148295f89e979 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvta.s32.f32 q14, q1 e1a9f07c6d8d825d8ac36aebede07e09 40c216ecd996de77d996de77dc542ee2 00000006800000008000000080000000 40c216ecd996de77d996de77dc542ee2 fpscr=00000000
+vcvta.s32.f32 q14, q1 2b39d5245a646b2844c90b9eddb36977 264fbbfd056a43b35bd89aba3830a704 00000000000000007fffffff00000000 264fbbfd056a43b35bd89aba3830a704 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[3]
+vcvta.s32.f32 q14, q1 8f0be6067b290c0e79587dcdf98ad9a5 54ce8a94f7862d23409875d4409875d4 7fffffff800000000000000500000005 54ce8a94f7862d23409875d4409875d4 fpscr=00000000
+vcvta.s32.f32 q14, q1 d3bbf24d8c2a7d4d7a8d7a24eecaac5e 9556bd39437ffabe90d96b0fe237f10d 00000000000001000000000080000000 9556bd39437ffabe90d96b0fe237f10d fpscr=00000000
+vcvta.s32.f32 q14, q1 99de29038663d6ac752b7862e858b4fb 1204904e93a121ee4f2768ad6ec54b38 00000000000000007fffffff7fffffff 1204904e93a121ee4f2768ad6ec54b38 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvta.s32.f32 q14, q1 844b933267ae028f844b93321e3265d1 3ed440c1d2ad80341b46e0aac1e37c67 000000008000000000000000ffffffe4 3ed440c1d2ad80341b46e0aac1e37c67 fpscr=00000000
+vcvta.s32.f32 q14, q1 77aaa0dc0682744b82d1013ff9d27e1f d2202566f2de3b7685e02c09a0735cd2 80000000800000000000000000000000 d2202566f2de3b7685e02c09a0735cd2 fpscr=00000000
+vcvta.s32.f32 q14, q1 36e678340ab831a33179f82a6495c772 0ff5a7225c328734dbca4214d09ef4e1 000000007fffffff8000000080000000 0ff5a7225c328734dbca4214d09ef4e1 fpscr=00000000
+vcvta.s32.f32 q14, q1 48ba1e17ee60fcc7fd887a4985e26dca 28b29b075959e8f6793ca292dbf833fd 000000007fffffff7fffffff80000000 28b29b075959e8f6793ca292dbf833fd fpscr=00000000
+vcvta.s32.f32 q14, q1 c7ef91ad3d5c20cafba8bf17aff8dcab aa03b2e6cb59af80752b6f5f0a9d56e1 00000000ff2650807fffffff00000000 aa03b2e6cb59af80752b6f5f0a9d56e1 fpscr=00000000
+vcvta.s32.f32 q14, q1 f893489ecee2eebd5f4379f642ca1dbf 996764bcdcd7bddf4f434bc89420a112 00000000800000007fffffff00000000 996764bcdcd7bddf4f434bc89420a112 fpscr=00000000
+vcvta.s32.f32 q14, q1 a72814bd31083f00e03b2e57c2d0d7c8 307e3ce31a3e2c02ce5308f3853b4732 0000000000000000cb3dc34000000000 307e3ce31a3e2c02ce5308f3853b4732 fpscr=00000000
+vcvta.s32.f32 q14, q1 0cc6a93513ed7028ca794b30743dbb10 4b060582065116065ebb2a7282d622b6 00860582000000007fffffff00000000 4b060582065116065ebb2a7282d622b6 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.s32.f32 q14, q1 515ae2c71045b37c900dd2a25da89987 6da0a3651e8ef79018c9ea5ed1554581 7fffffff000000000000000080000000 6da0a3651e8ef79018c9ea5ed1554581 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvta.s32.f32 q14, q1 4c536e5c8fcd2591d8d4a6a4b0e73acf 530e6a2ef30e1571bcdcfbff81294844 7fffffff800000000000000000000000 530e6a2ef30e1571bcdcfbff81294844 fpscr=00000000
+vcvta.s32.f32 q14, q1 bb83ad7424ff2fc3664efd23b2a5f755 36db8046076dac5d61342f5377d3eb95 00000000000000007fffffff7fffffff 36db8046076dac5d61342f5377d3eb95 fpscr=00000000
+vcvta.s32.f32 q14, q1 250fee5622dc7d7dc90167029cfc2b1a a980cd45e7e32288424ad71a9fd0dfef 00000000800000000000003300000000 a980cd45e7e32288424ad71a9fd0dfef fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvta.s32.f32 q14, q1 927c55f1c7094a94936df843927c55f1 0baf6244fd5629bdf1f4a352edee7f84 00000000800000008000000080000000 0baf6244fd5629bdf1f4a352edee7f84 fpscr=00000000
+vcvta.s32.f32 q14, q1 20f85924575343e014917a1736b85823 b7867e0ff1094f335c67ebd13ae549a5 00000000800000007fffffff00000000 b7867e0ff1094f335c67ebd13ae549a5 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: 14336 calls, 14823 iters
+vcvta.s32.f32 q14, q1 705b8d43f7cf3e08d68151af914ac929 3a9771d7a436788e5b0b65e2c16a0860 00000000000000007ffffffffffffff1 3a9771d7a436788e5b0b65e2c16a0860 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvta.s32.f32 q14, q1 1583b10cbe60c9e4f7ba69cdd4e69097 0663fc1b5016c34338bc5e38530329d3 000000007fffffff000000007fffffff 0663fc1b5016c34338bc5e38530329d3 fpscr=00000000
+vcvta.s32.f32 q14, q1 c4a54d713f3a858b011cc3d36c05da46 d3c0a9ba77fd7bed1932f6d7e8ec16d4 800000007fffffff0000000080000000 d3c0a9ba77fd7bed1932f6d7e8ec16d4 fpscr=00000000
+vcvta.s32.f32 q14, q1 0b116beb66435fc8de67ccd6f70179c1 848cded0b3abec78ba920add42842b72 00000000000000000000000000000042 848cded0b3abec78ba920add42842b72 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvta.s32.f32 q14, q1 c680c66e754b0496754b04961510da7e aa0d58e65467e0d47972900e2cb26187 000000007fffffff7fffffff00000000 aa0d58e65467e0d47972900e2cb26187 fpscr=00000000
+vcvta.s32.f32 q14, q1 9ed6a39fd0a78025ef548a8ed4ec04f6 273393a4c518139ab469553e7603b025 00000000fffff67f000000007fffffff 273393a4c518139ab469553e7603b025 fpscr=00000000
+vcvta.s32.f32 q14, q1 6473d1001b79c6bc274d947bce9c2a3d 2a9fc1449e5870948d0f7e9f9d5944ac 00000000000000000000000000000000 2a9fc1449e5870948d0f7e9f9d5944ac fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvta.s32.f32 q14, q1 160dfc18753af2550ba9cf8e926ae0e1 68bc70b80b0fa83da927f2e265d2f8d4 7fffffff00000000000000007fffffff 68bc70b80b0fa83da927f2e265d2f8d4 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvta.s32.f32 q14, q1 6faa40e11a87820e0f7d166468c64cc6 cf67c7c768b7bab6cf67c7c78a83a880 800000007fffffff8000000000000000 cf67c7c768b7bab6cf67c7c78a83a880 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.s32.f32 q14, q1 a7c7f6fb42661cbe3b9a52497ba9c5c3 ca7fd03267f241e8015294858d76df30 ffc00bf47fffffff0000000000000000 ca7fd03267f241e8015294858d76df30 fpscr=00000000
+vcvta.s32.f32 q14, q1 1d40db01f54f8fc076034f19c700a182 860269c5e362789c57f06354d3dea526 00000000800000007fffffff80000000 860269c5e362789c57f06354d3dea526 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvta.s32.f32 q14, q1 2a31fea15d34c79495da5ed4e31f86f0 48df1dafa90794752263795991934b18 0006f8ed000000000000000000000000 48df1dafa90794752263795991934b18 fpscr=00000000
+vcvta.s32.f32 q14, q1 95defb801e11ae02ba4326c818f9efc0 2232b8fc72f08cbbd7b7ec8e37c34a97 000000007fffffff8000000000000000 2232b8fc72f08cbbd7b7ec8e37c34a97 fpscr=00000000
+vcvta.s32.f32 q14, q1 8ebbdef2319f0861467c487a3bcc585c f45b8aafa35af42d0563e526903bae75 80000000000000000000000000000000 f45b8aafa35af42d0563e526903bae75 fpscr=00000000
+vcvta.s32.f32 q14, q1 c8b41d415dff1e91ef799cdb7d10b400 ad2494f15fa3f6e066ffb9ea6a788b09 000000007fffffff7fffffff7fffffff ad2494f15fa3f6e066ffb9ea6a788b09 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[0]
+vcvta.s32.f32 q14, q1 4cdb111ce4324ded3619d3bd3619d3bd a2f484feaa77b15ce1d6ac80502d10f6 0000000000000000800000007fffffff a2f484feaa77b15ce1d6ac80502d10f6 fpscr=00000000
+vcvta.s32.f32 q14, q1 0438135dd06938d99c5d674b7783b492 b831475446a7418cde753c0fd463bb8a 00000000000053a18000000080000000 b831475446a7418cde753c0fd463bb8a fpscr=00000000
+vcvtp.s32.f32 q13, q2 98006dfa918ff22decc9e4c0c9f16a00 43b2d52816675c80628be8e045a0186d 00000166000000017fffffff00001404 43b2d52816675c80628be8e045a0186d fpscr=00000000
+vcvtp.s32.f32 q13, q2 df1deff75c92dfb987332b60ab58149b dbcbfbc5c7f04cfe1ddef61e5869764f 80000000fffe1f67000000017fffffff dbcbfbc5c7f04cfe1ddef61e5869764f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[0]
+vcvtp.s32.f32 q13, q2 a2cd3ab9a2cd3ab90e4f410a45051dd6 e46adf3d655a60db7403eae3909e8175 800000007fffffff7fffffff00000000 e46adf3d655a60db7403eae3909e8175 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtp.s32.f32 q13, q2 df9da7477353a0c69ea60c3d2f5695cb ef73c43ca0b0971ac7a74dfb9f96beb4 8000000000000000fffeb16500000000 ef73c43ca0b0971ac7a74dfb9f96beb4 fpscr=00000000
+vcvtp.s32.f32 q13, q2 daf233efa5c14df6d9579ca968a406c3 c322f14d0c887df6731ab382c1129bce ffffff5e000000017ffffffffffffff7 c322f14d0c887df6731ab382c1129bce fpscr=00000000
+vcvtp.s32.f32 q13, q2 50ea6b13cdce7c2fa80a83444bb6b278 cdaba67aa3769097a3c90894d3deeae2 ea8b30c0000000000000000080000000 cdaba67aa3769097a3c90894d3deeae2 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtp.s32.f32 q13, q2 d79d73f536afdbb5b97b1bf1d7dd71be 29fe07ad1045a03351bbd86ed4ad75a3 00000001000000017fffffff80000000 29fe07ad1045a03351bbd86ed4ad75a3 fpscr=00000000
+vcvtp.s32.f32 q13, q2 b3ff1424023ee52d16e3a24b00ee7e58 a65458875f38d84c555819dec85730d2 000000007fffffff7ffffffffffca33d a65458875f38d84c555819dec85730d2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtp.s32.f32 q13, q2 c89d98e04683de769108e7f9abde751d a09d01d4a09d01d49186a286b72c4656 00000000000000000000000000000000 a09d01d4a09d01d49186a286b72c4656 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.s32.f32 q13, q2 8e8d0bf98d2464faf06107c0ebca2fb6 180ca6b90ad6161a80bda74bc72b7dd0 000000010000000100000000ffff5483 180ca6b90ad6161a80bda74bc72b7dd0 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtp.s32.f32 q13, q2 186570b7b9a002d23c93e64df91c3b6c 4bb908611542ac8f36cf5d649ec39e65 017210c2000000010000000100000000 4bb908611542ac8f36cf5d649ec39e65 fpscr=00000000
+vcvtp.s32.f32 q13, q2 93179d4b5d328ca1f36b69006d1d561d 7533f89cb9be8fd931bdeb8d927d678a 7fffffff000000000000000100000000 7533f89cb9be8fd931bdeb8d927d678a fpscr=00000000
+vcvtp.s32.f32 q13, q2 73a2658513cb5240502df4677b5d880b b85c4232d957e5ffb34f19c51c36789e 00000000800000000000000000000001 b85c4232d957e5ffb34f19c51c36789e fpscr=00000000
+vcvtp.s32.f32 q13, q2 2c9cd669cfc5c152449a425d9e55b097 9ce43827a9d27b553a4366f48cd4c7de 00000000000000000000000100000000 9ce43827a9d27b553a4366f48cd4c7de fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtp.s32.f32 q13, q2 ab7a83b9ff36941af3b2fdc48763cc81 bd5160ab8f9e7c5d77a77431795a59dc 00000000000000007fffffff7fffffff bd5160ab8f9e7c5d77a77431795a59dc fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtp.s32.f32 q13, q2 3b0f24763b0f24763612142a112838d0 cdee57ee923147de51de22de51686c7f e2350240000000007fffffff7fffffff cdee57ee923147de51de22de51686c7f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtp.s32.f32 q13, q2 2b3577222b357722ee2a901182190219 7e09eca91d6bf50f4f8031ab1d8f36f0 7fffffff000000017fffffff00000001 7e09eca91d6bf50f4f8031ab1d8f36f0 fpscr=00000000
+vcvtp.s32.f32 q13, q2 f1d2638f6802f89bf3824ca0f7c621a6 fef6eb77481449d96590ae5e4e68043d 80000000000251287fffffff3a010f40 fef6eb77481449d96590ae5e4e68043d fpscr=00000000
+vcvtp.s32.f32 q13, q2 07eb47b5630398f52dde317e531c9c5f 5ef0aaef50d3656bf443560c2270da39 7fffffff7fffffff8000000000000001 5ef0aaef50d3656bf443560c2270da39 fpscr=00000000
+vcvtp.s32.f32 q13, q2 6e5703e0bcc5273645aaeea71b9236be d692fa81c70294c4b2f88c9963f3f3a2 80000000ffff7d6c000000007fffffff d692fa81c70294c4b2f88c9963f3f3a2 fpscr=00000000
+vcvtp.s32.f32 q13, q2 8600fb7be7061934e7743fb0f8a6c683 d7f3dfece572f81a4fe20b6905c64160 80000000800000007fffffff00000001 d7f3dfece572f81a4fe20b6905c64160 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.s32.f32 q13, q2 9c64200a5b5c78d73dc8dd0ee9d6ee03 536cad0ef8d0c250d6f0ed3dd6f0ed3d 7fffffff800000008000000080000000 536cad0ef8d0c250d6f0ed3dd6f0ed3d fpscr=00000000
+vcvtp.s32.f32 q13, q2 fc3c8d1ca1fedbd53a02d3e97927cf7b 753aedc00523af6c54cdf4a78ed10aae 7fffffff000000017fffffff00000000 753aedc00523af6c54cdf4a78ed10aae fpscr=00000000
+vcvtp.s32.f32 q13, q2 cce0cb3005611876f364e2740d3d4d85 e082059db7544c5d3eb1940c615eaad9 8000000000000000000000017fffffff e082059db7544c5d3eb1940c615eaad9 fpscr=00000000
+vcvtp.s32.f32 q13, q2 20fbc55da362bc96f425f1dc963b1121 a337ac8a78aeae0b1a6ac3a13a26e2ac 000000007fffffff0000000100000001 a337ac8a78aeae0b1a6ac3a13a26e2ac fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtp.s32.f32 q13, q2 e279ad2e73c7cb20b672e1c62867792e 95306a25887e420e50afdc8480df30ec 00000000000000007fffffff00000000 95306a25887e420e50afdc8480df30ec fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.s32.f32 q13, q2 6ac710749cfd46396eadb7ef4c4b63ee cbbe13e9f3ce2dfdcf7eacceab6548e2 fe83d82e800000008000000000000000 cbbe13e9f3ce2dfdcf7eacceab6548e2 fpscr=00000000
+vcvtp.s32.f32 q13, q2 87c6ed40a9461cd15f6f1485b2014f12 a0b56dd538fdaeaa106f278ee16935ce 00000000000000010000000180000000 a0b56dd538fdaeaa106f278ee16935ce fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.s32.f32 q13, q2 d47c772c0a7508186342fb7c2b01b151 36b219c002f92c0b7b93af9b02f92c0b 00000001000000017fffffff00000001 36b219c002f92c0b7b93af9b02f92c0b fpscr=00000000
+vcvtp.s32.f32 q13, q2 f077999be81c9f83d849b69616af7143 1bde161bd1874b946b37797ed58c3515 00000001800000007fffffff80000000 1bde161bd1874b946b37797ed58c3515 fpscr=00000000
+vcvtp.s32.f32 q13, q2 b848e28709a1ff9b4363292c5224eb0a 7a72a574686faa441089d4cd579de7a5 7fffffff7fffffff000000017fffffff 7a72a574686faa441089d4cd579de7a5 fpscr=00000000
+vcvtp.s32.f32 q13, q2 552acd68ee925a1e4746194a3c46d355 d0387bef6ee2303669fdf03c7681b1be 800000007fffffff7fffffff7fffffff d0387bef6ee2303669fdf03c7681b1be fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.s32.f32 q13, q2 cfc2c579bc2357118ef5de5209444988 a15124e4d06f404a7e70b455a2bc6aab 00000000800000007fffffff00000000 a15124e4d06f404a7e70b455a2bc6aab fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtp.s32.f32 q13, q2 3faa2047540c6bc6e67a5e165c2a4068 ad84b832d6c73ecd88a7eff58478ceee 00000000800000000000000000000000 ad84b832d6c73ecd88a7eff58478ceee fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[3]
+vcvtp.s32.f32 q13, q2 c3be8e46a73571aed0188695c3be8e46 1a5cd1691a5cd16923cb48fb9ab06c5f 00000001000000010000000100000000 1a5cd1691a5cd16923cb48fb9ab06c5f fpscr=00000000
+vcvtp.s32.f32 q13, q2 b6ecdec2be3f609682781a502cd97190 e0f29713a9ad59385ae88d4e67bea3cb 80000000000000007fffffff7fffffff e0f29713a9ad59385ae88d4e67bea3cb fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtp.s32.f32 q13, q2 b61f9bbe0ae63a27b61f9bbe12625fdf 5004443545510690214a47052adf0a86 7fffffff00000d110000000100000001 5004443545510690214a47052adf0a86 fpscr=00000000
+vcvtp.s32.f32 q13, q2 f400ba6adf33a1e68d700937e2687298 3571156c684db8c2c1ba6f30bc63bbf9 000000017fffffffffffffe900000000 3571156c684db8c2c1ba6f30bc63bbf9 fpscr=00000000
+vcvtp.s32.f32 q13, q2 c0e3ea22d61de5660bdf5b58406611c1 409d629f39b6c62b8ce59d774c3cfa32 00000005000000010000000002f3e8c8 409d629f39b6c62b8ce59d774c3cfa32 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtp.s32.f32 q13, q2 3889f7a0c1a03808e54166964de3c680 dee2d13481663f0b073ff7999c2dd2b5 80000000000000000000000100000000 dee2d13481663f0b073ff7999c2dd2b5 fpscr=00000000
+vcvtp.s32.f32 q13, q2 6f8615788439db0b0efadeaac5d24161 3ec3dd0c496feab2bb3ca65b2bc98a0a 00000001000efeac0000000000000001 3ec3dd0c496feab2bb3ca65b2bc98a0a fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[2]
+vcvtp.s32.f32 q13, q2 2921fe81a35500004ab04900a3550000 873bad6353d365e853d365e841997ee8 000000007fffffff7fffffff00000014 873bad6353d365e853d365e841997ee8 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtp.s32.f32 q13, q2 9980010745e1973445e197343d42b913 7ad157375df9fe30647d83539d782e8b 7fffffff7fffffff7fffffff00000000 7ad157375df9fe30647d83539d782e8b fpscr=00000000
+vcvtp.s32.f32 q13, q2 a97a0abd7745a9884936b4066d5559b6 d9943ff499d3a1f872e0f972b3b01997 80000000000000007fffffff00000000 d9943ff499d3a1f872e0f972b3b01997 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.s32.f32 q13, q2 364e8e20c626c78ae777e139d2ea9407 4ff11fbb81f307af8814a67828dfb23d 7fffffff000000000000000000000001 4ff11fbb81f307af8814a67828dfb23d fpscr=00000000
+vcvtp.s32.f32 q13, q2 f34717605809f22b6e0498193015228f 7ce112303a7afe0b1ccde7e9e6774a20 7fffffff000000010000000180000000 7ce112303a7afe0b1ccde7e9e6774a20 fpscr=00000000
+vcvtp.s32.f32 q13, q2 799fc1c2579561ad85e755ab7413c723 02fac3dc4f538d4714decffd296473ad 000000017fffffff0000000100000001 02fac3dc4f538d4714decffd296473ad fpscr=00000000
+randV128: 14592 calls, 15088 iters
+vcvtp.s32.f32 q13, q2 6cedb65dd30c294a1800c4a30965420b 0216c60ec12be6232a59fc02664cb833 00000001fffffff6000000017fffffff 0216c60ec12be6232a59fc02664cb833 fpscr=00000000
+vcvtp.s32.f32 q13, q2 caea16a337e94f5f8195e2bfa1811b6f 643463e9b97d1abe7baafdf3099eda69 7fffffff000000007fffffff00000001 643463e9b97d1abe7baafdf3099eda69 fpscr=00000000
+vcvtp.s32.f32 q13, q2 03865bb839c38896a5c85825639bcd82 3e7d6ef0683b4d2022fea9969055692e 000000017fffffff0000000100000000 3e7d6ef0683b4d2022fea9969055692e fpscr=00000000
+vcvtm.s32.f32 q12, q3 0c89b3586660ba7879a5678296eab10e 6e15ee16292aabbc330a19fe9c7bd276 7fffffff0000000000000000ffffffff 6e15ee16292aabbc330a19fe9c7bd276 fpscr=00000000
+vcvtm.s32.f32 q12, q3 ea0ffa7680f0ee52512fcf8d25822461 4b65e672fe6cd28dee8c12e13b637b4a 00e5e672800000008000000000000000 4b65e672fe6cd28dee8c12e13b637b4a fpscr=00000000
+vcvtm.s32.f32 q12, q3 7e3905f36afb45aaa5903bd0166b3841 c51c95df3e57e03a9c5a5d7f0ced1293 fffff63600000000ffffffff00000000 c51c95df3e57e03a9c5a5d7f0ced1293 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtm.s32.f32 q12, q3 2589085f24e55f21a258b93a2589085f 76ed9428b76719ead22202ae71f786b3 7fffffffffffffff800000007fffffff 76ed9428b76719ead22202ae71f786b3 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.s32.f32 q12, q3 9694bbce0bef686a9dfaa6162ba2be44 213ec9ea9005da3e3ce47b842096aed3 00000000ffffffff0000000000000000 213ec9ea9005da3e3ce47b842096aed3 fpscr=00000000
+vcvtm.s32.f32 q12, q3 cadc1ca2a581f823536be0db31cbddae 1f78506044cbe3fb7159a56a14dec7a0 000000000000065f7fffffff00000000 1f78506044cbe3fb7159a56a14dec7a0 fpscr=00000000
+vcvtm.s32.f32 q12, q3 e8b77beb9b68923f05bffd955acbe944 54c14a6b88c00e2db1b256d452f015fc 7fffffffffffffffffffffff7fffffff 54c14a6b88c00e2db1b256d452f015fc fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.s32.f32 q12, q3 8f419be53b6c56b8d923d9e4d3f78549 6614c7bbe698e7af41478a8e41478a8e 7fffffff800000000000000c0000000c 6614c7bbe698e7af41478a8e41478a8e fpscr=00000000
+vcvtm.s32.f32 q12, q3 3e4dc05445c92605cd21ef8056954af7 0427051120def925183cb255368bd6f4 00000000000000000000000000000000 0427051120def925183cb255368bd6f4 fpscr=00000000
+vcvtm.s32.f32 q12, q3 0d1cd88f082e87e00a28bc4bcb553a84 eeb45870a14187b462a2530298ffb2a9 80000000ffffffff7fffffffffffffff eeb45870a14187b462a2530298ffb2a9 fpscr=00000000
+vcvtm.s32.f32 q12, q3 72675eb6f97ac85f566863face03d1f1 9e4cd7124232b041d4b79b85abbcdff5 ffffffff0000002c80000000ffffffff 9e4cd7124232b041d4b79b85abbcdff5 fpscr=00000000
+vcvtm.s32.f32 q12, q3 8c806184f6b2d527b0d023ac88dcb583 2792feb119bbeac878d2b7167bea20e3 00000000000000007fffffff7fffffff 2792feb119bbeac878d2b7167bea20e3 fpscr=00000000
+vcvtm.s32.f32 q12, q3 39f72ed17315a3afea736de291fe4a55 634240dd5a562369a672acb871f54e4e 7fffffff7fffffffffffffff7fffffff 634240dd5a562369a672acb871f54e4e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtm.s32.f32 q12, q3 fa554aa70401c66ffa554aa7af8987c9 bbe262934272dcf41978ace8d3ef23d2 ffffffff0000003c0000000080000000 bbe262934272dcf41978ace8d3ef23d2 fpscr=00000000
+vcvtm.s32.f32 q12, q3 a6713ab8c32c41ab69edac1c0c93049a 92ceb5fff7728d62a0f9625a3cd8fda8 ffffffff80000000ffffffff00000000 92ceb5fff7728d62a0f9625a3cd8fda8 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtm.s32.f32 q12, q3 5e2df758eb700ac39fae2a320b289029 106ca066a036bc10b873922be59bd5d4 00000000ffffffffffffffff80000000 106ca066a036bc10b873922be59bd5d4 fpscr=00000000
+vcvtm.s32.f32 q12, q3 46534ff3b915c3df691c34ec2000a3fc 2f62c4bbdf47259aac084a3692264bc2 0000000080000000ffffffffffffffff 2f62c4bbdf47259aac084a3692264bc2 fpscr=00000000
+vcvtm.s32.f32 q12, q3 4762c1c251c2f13f7216b7596aa10aac b393ddbcdca4bc6c50c8dfee65dd46e2 ffffffff800000007fffffff7fffffff b393ddbcdca4bc6c50c8dfee65dd46e2 fpscr=00000000
+vcvtm.s32.f32 q12, q3 a0c26245ddd22f14d1ca113544b8cf25 fd50b3d0b7538415631ebeb3d95d15a2 80000000ffffffff7fffffff80000000 fd50b3d0b7538415631ebeb3d95d15a2 fpscr=00000000
+vcvtm.s32.f32 q12, q3 ca16b3557d143199ae80befe8edc04fd 5e410a46af36e97dd10601875a0de146 7fffffffffffffff800000007fffffff 5e410a46af36e97dd10601875a0de146 fpscr=00000000
+vcvtm.s32.f32 q12, q3 538603ccee430013539b2f0b9cce4ee1 7d681bd5f647a09ddd4e6dd2618eb6f2 7fffffff80000000800000007fffffff 7d681bd5f647a09ddd4e6dd2618eb6f2 fpscr=00000000
+vcvtm.s32.f32 q12, q3 c9023619cf0ccbf4abfb6bd604b83bfb 30ff0041a815e88bd09c5a0ae8799ead 00000000ffffffff8000000080000000 30ff0041a815e88bd09c5a0ae8799ead fpscr=00000000
+vcvtm.s32.f32 q12, q3 95dcef65994633a260d37e67e09fd2fd 84d0cd04724641473c0f0fa44d22976c ffffffff7fffffff000000000a2976c0 84d0cd04724641473c0f0fa44d22976c fpscr=00000000
+vcvtm.s32.f32 q12, q3 b7b8a21383887898dce1c81be83cfc85 217affe195f5836aa2b971de9836ef00 00000000ffffffffffffffffffffffff 217affe195f5836aa2b971de9836ef00 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.s32.f32 q12, q3 6ce87ead3d1c8ef37334d7e47334d7e4 40c1148a5a5052ee53b57c041e6f2038 000000067fffffff7fffffff00000000 40c1148a5a5052ee53b57c041e6f2038 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtm.s32.f32 q12, q3 dc28fa3377b6be9001e037fa77b6be90 4e0de3456085d588da5dc71d81a76417 2378d1407fffffff80000000ffffffff 4e0de3456085d588da5dc71d81a76417 fpscr=00000000
+vcvtm.s32.f32 q12, q3 426fc804fa33fde86d11f632bd0a625b e37803fee3b2f7c8408cc474e3da2233 80000000800000000000000480000000 e37803fee3b2f7c8408cc474e3da2233 fpscr=00000000
+vcvtm.s32.f32 q12, q3 ff12556d3603a5deceb544dfe40236aa 413d71e361c0134d83036f5554217d87 0000000b7fffffffffffffff7fffffff 413d71e361c0134d83036f5554217d87 fpscr=00000000
+vcvtm.s32.f32 q12, q3 3714116e47c94145cfa97e53a9f2988b 53e7dbaa8361999b97e64c10161439e7 7fffffffffffffffffffffff00000000 53e7dbaa8361999b97e64c10161439e7 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.s32.f32 q12, q3 c4b75e80afe8f25d94a7d55cefc032c2 662c9e48e13a6e6c034280f5e5ca0f25 7fffffff800000000000000080000000 662c9e48e13a6e6c034280f5e5ca0f25 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtm.s32.f32 q12, q3 cfac4cba6d92f5499a5968590993c40d 914a7a432973602f13b09407b5dc21be ffffffff0000000000000000ffffffff 914a7a432973602f13b09407b5dc21be fpscr=00000000
+vcvtm.s32.f32 q12, q3 2f13db3db60d0a4c4bb0c83b854e7bde 0f653c8d6ae135f8f78580fec64a94b5 000000007fffffff80000000ffffcd5a 0f653c8d6ae135f8f78580fec64a94b5 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.s32.f32 q12, q3 5d8037e790e549b80a728624a94e1657 1e7bff1b6b175be2d3df52df845d98f4 000000007fffffff80000000ffffffff 1e7bff1b6b175be2d3df52df845d98f4 fpscr=00000000
+vcvtm.s32.f32 q12, q3 df81abd1344f483715470b8d06f29917 1f94738f6c2cf90f088ce31c67fe53d1 000000007fffffff000000007fffffff 1f94738f6c2cf90f088ce31c67fe53d1 fpscr=00000000
+vcvtm.s32.f32 q12, q3 c0499670d84f4f8c9f33eb1a314b7f6a cb8f6f4b97261cacd68db713d532d752 fee1216affffffff8000000080000000 cb8f6f4b97261cacd68db713d532d752 fpscr=00000000
+vcvtm.s32.f32 q12, q3 eca89ac809161032aa4d292816022688 3206480d2c4508053e89cd363971b867 00000000000000000000000000000000 3206480d2c4508053e89cd363971b867 fpscr=00000000
+vcvtm.s32.f32 q12, q3 b85aea389cb5d4dcba191dec35db1805 6a957225e52e2bc7b3da300a749de60e 7fffffff80000000ffffffff7fffffff 6a957225e52e2bc7b3da300a749de60e fpscr=00000000
+vcvtm.s32.f32 q12, q3 42c8146c42ff7e8f205fe05eb1b39ffd 441a61f25e5b8e6f1323838abf2e463b 000002697fffffff00000000ffffffff 441a61f25e5b8e6f1323838abf2e463b fpscr=00000000
+vcvtm.s32.f32 q12, q3 20aa781057d227fbee0701295a059ead e0e2b5e44d669d6d83bb65621dc4af37 800000000e69d6d0ffffffff00000000 e0e2b5e44d669d6d83bb65621dc4af37 fpscr=00000000
+vcvtm.s32.f32 q12, q3 f30faee792bda134be6529049ed05467 a1bdb952173e4a1b9cfc380d399656dc ffffffff00000000ffffffff00000000 a1bdb952173e4a1b9cfc380d399656dc fpscr=00000000
+vcvtm.s32.f32 q12, q3 ccc2be438e04cfc362de966855e0f9e7 87e44e41c72e9aa00b7246d593bb94b3 ffffffffffff516500000000ffffffff 87e44e41c72e9aa00b7246d593bb94b3 fpscr=00000000
+vcvtm.s32.f32 q12, q3 82113fd93d08e82076ed7aa5726e370c e5ce2efc64cf81b081e547b11d5c08f4 800000007fffffffffffffff00000000 e5ce2efc64cf81b081e547b11d5c08f4 fpscr=00000000
+vcvtm.s32.f32 q12, q3 dcf157f7330e9084c9893a578b2b8fec 73d89694a4d43222094c47ff2ec02063 7fffffffffffffff0000000000000000 73d89694a4d43222094c47ff2ec02063 fpscr=00000000
+vcvtm.s32.f32 q12, q3 a0869719d460dd24aceb883f50a4934a c7d9473f06b9be76c29aee26d83d000d fffe4d7100000000ffffffb280000000 c7d9473f06b9be76c29aee26d83d000d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[3]
+vcvtm.s32.f32 q12, q3 2c8aef9347521c30ef6824159f01c3e8 b62ff77d553e33a9c3cd61a4c3cd61a4 ffffffff7ffffffffffffe65fffffe65 b62ff77d553e33a9c3cd61a4c3cd61a4 fpscr=00000000
+vcvtm.s32.f32 q12, q3 7394b28f073667e8d3d8efa737389014 904720ed857d0dd30ce3e4d2b9093a17 ffffffffffffffff00000000ffffffff 904720ed857d0dd30ce3e4d2b9093a17 fpscr=00000000
+vcvtm.s32.f32 q12, q3 5d8174294c8917ee6f128010ed147247 615cb797c9e73670cb5ff6d914035227 7fffffffffe31932ff20092700000000 615cb797c9e73670cb5ff6d914035227 fpscr=00000000
+vcvtm.s32.f32 q12, q3 32f065688aaaf32c28f339bf64d4504c 37d37082b60f44566a23b888bbe63ded 00000000ffffffff7fffffffffffffff 37d37082b60f44566a23b888bbe63ded fpscr=00000000
+vcvtm.s32.f32 q12, q3 73c47068d09fecd4f196f5bd67b277e1 77ce63fff58dfe82f1130cef535a8794 7fffffff80000000800000007fffffff 77ce63fff58dfe82f1130cef535a8794 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtm.s32.f32 q12, q3 ec83f4186569c1733e401acff125d9bf f0d2c92bb8c81b9af6ad7602f6ad7602 80000000ffffffff8000000080000000 f0d2c92bb8c81b9af6ad7602f6ad7602 fpscr=00000000
+vcvtn.u32.f32 d0, d20 bc1c95b662988fcc307c3a8c09461c0d 543f751aedbe7a22e7d97eee51747ba0 bc1c95b662988fcc00000000ffffffff 543f751aedbe7a22e7d97eee51747ba0 fpscr=00000000
+vcvtn.u32.f32 d0, d20 a9a0b5cfc545a59f02c5c785987da382 2c5d5f33fb187272dcd6ab4641f7abbd a9a0b5cfc545a59f000000000000001f 2c5d5f33fb187272dcd6ab4641f7abbd fpscr=00000000
+vcvtn.u32.f32 d0, d20 c7599fed2b07678c13523b114357d0f8 ae0cfae6c9f919fc508f0bea4b667a53 c7599fed2b07678cffffffff00e67a53 ae0cfae6c9f919fc508f0bea4b667a53 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[2]
+vcvtn.u32.f32 d0, d20 cec7a96fa966f5c30823baec0823baec 9b0d7753dcb9beead3f803192dda3405 cec7a96fa966f5c30000000000000000 9b0d7753dcb9beead3f803192dda3405 fpscr=00000000
+vcvtn.u32.f32 d0, d20 93a375ba1d7c2d87d991b72c6f71a801 dcc2f880b3c346ec6172f6db33e94172 93a375ba1d7c2d87ffffffff00000000 dcc2f880b3c346ec6172f6db33e94172 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[2]
+vcvtn.u32.f32 d0, d20 66e35629664bbdcd66e356296b3ecd5e ab375f56ab375f56895a996578b9a28b 66e35629664bbdcd00000000ffffffff ab375f56ab375f56895a996578b9a28b fpscr=00000000
+vcvtn.u32.f32 d0, d20 8559b3d61a36ea4e7bd6213e948285cd 6cda4e0b4d853c12dc8e3cf00ecb64cc 8559b3d61a36ea4e0000000000000000 6cda4e0b4d853c12dc8e3cf00ecb64cc fpscr=00000000
+vcvtn.u32.f32 d0, d20 213601545d02a30e179805c0d26e9938 a646c54a4ae6853979d77f77b152dff7 213601545d02a30effffffff00000000 a646c54a4ae6853979d77f77b152dff7 fpscr=00000000
+vcvtn.u32.f32 d0, d20 1ba9a814fc7911101dc6805a3d20ffc1 a4c81dee01e6b3bb7b936f4c928bff34 1ba9a814fc791110ffffffff00000000 a4c81dee01e6b3bb7b936f4c928bff34 fpscr=00000000
+vcvtn.u32.f32 d0, d20 811c286ec7fbe1d83e8edb25a406291b f50fc3918fc010e5d4248b5f5ebf6c24 811c286ec7fbe1d800000000ffffffff f50fc3918fc010e5d4248b5f5ebf6c24 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtn.u32.f32 d0, d20 4cdda108993732163734839dc5d440f5 114de927f37f580176f61e05114de927 4cdda10899373216ffffffff00000000 114de927f37f580176f61e05114de927 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: 14848 calls, 15355 iters
+vcvtn.u32.f32 d0, d20 0e14e67d6b154dff770060104bb6be04 744eceb8afd9c628bcb1ab6646cca62c 0e14e67d6b154dff0000000000006653 744eceb8afd9c628bcb1ab6646cca62c fpscr=00000000
+vcvtn.u32.f32 d0, d20 6a86849e7806ed30ef87d0b1f3e69a7b 512912178f3cb2e28bc4fad6e0504c26 6a86849e7806ed300000000000000000 512912178f3cb2e28bc4fad6e0504c26 fpscr=00000000
+vcvtn.u32.f32 d0, d20 5a4c5efaebf98a3c3a480445c9e6b778 62fd9f9e1bd0935f22737b463979d26c 5a4c5efaebf98a3c0000000000000000 62fd9f9e1bd0935f22737b463979d26c fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtn.u32.f32 d0, d20 3618fbdda69bba51487d3d62d33db233 71982135ee1136a2ee1136a2b4d8b1d9 3618fbdda69bba510000000000000000 71982135ee1136a2ee1136a2b4d8b1d9 fpscr=00000000
+vcvtn.u32.f32 d0, d20 9f25cc32fbe85cace480951b9a9ce1f3 efa051ace986e83eac84541fb5c1b69a 9f25cc32fbe85cac0000000000000000 efa051ace986e83eac84541fb5c1b69a fpscr=00000000
+vcvtn.u32.f32 d0, d20 5c467d545755aedf0da9496e866686aa 1e1193da73297b613493e8859ca37688 5c467d545755aedf0000000000000000 1e1193da73297b613493e8859ca37688 fpscr=00000000
+vcvtn.u32.f32 d0, d20 f432abe9d284363df424de986fdb603e 71077696299db6ce1aaebdbc438751cd f432abe9d284363d000000000000010f 71077696299db6ce1aaebdbc438751cd fpscr=00000000
+vcvtn.u32.f32 d0, d20 c203742ed669e85f834e22f0d771bd3d 6ec7b36ff99d361174fc5fcec392f51d c203742ed669e85fffffffff00000000 6ec7b36ff99d361174fc5fcec392f51d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.u32.f32 d0, d20 3204e52ca5dedc90aafba03dd085a34d 213f2eb4d9d3f32ec03cca5edf8f6d3b 3204e52ca5dedc900000000000000000 213f2eb4d9d3f32ec03cca5edf8f6d3b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtn.u32.f32 d0, d20 de4ab5bf759af0ca65d8cfc865d8cfc8 ece3f81ebb1b57787e7c21f3ec4b607e de4ab5bf759af0caffffffff00000000 ece3f81ebb1b57787e7c21f3ec4b607e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtn.u32.f32 d0, d20 60e22955f58616eaf095ce36da882b27 84be346e21f0bd716408cd2ebab4fb3d 60e22955f58616eaffffffff00000000 84be346e21f0bd716408cd2ebab4fb3d fpscr=00000000
+vcvtn.u32.f32 d0, d20 cef2508e7c7654403338be461137f4a0 d30e6828a7e1c7c0dd4f0f8e9705f840 cef2508e7c7654400000000000000000 d30e6828a7e1c7c0dd4f0f8e9705f840 fpscr=00000000
+vcvtn.u32.f32 d0, d20 3b572300ba08b0bc1002855bfcbb9ec4 f1a9fb63616cb0c0fefa5159f987951b 3b572300ba08b0bc0000000000000000 f1a9fb63616cb0c0fefa5159f987951b fpscr=00000000
+vcvtn.u32.f32 d0, d20 7795fa0e7261107e51da35635a3c5611 0ca248bfafaf9a4ae00dac5506e002e8 7795fa0e7261107e0000000000000000 0ca248bfafaf9a4ae00dac5506e002e8 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtn.u32.f32 d0, d20 f4bacd0d7ded886a0bf56713f4493e64 edafb53990aed1215c2f3df22e523d47 f4bacd0d7ded886affffffff00000000 edafb53990aed1215c2f3df22e523d47 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtn.u32.f32 d0, d20 6ad688c2be2c9943f4ad945969c5fc7e 722b74385393c90f8f8619e2d919e0c9 6ad688c2be2c99430000000000000000 722b74385393c90f8f8619e2d919e0c9 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtn.u32.f32 d0, d20 1b3b68dc5457fdff1b0a0bba459ebe0c 4001b2caa8eb1d366a687778aeb2fa1e 1b3b68dc5457fdffffffffff00000000 4001b2caa8eb1d366a687778aeb2fa1e fpscr=00000000
+vcvtn.u32.f32 d0, d20 98bbb1920beeb8bc8563ad1338b547f5 5e1667d22045bda7463125f7b0c22749 98bbb1920beeb8bc00002c4900000000 5e1667d22045bda7463125f7b0c22749 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtn.u32.f32 d0, d20 d05736a051d06a37ac581c3cd05736a0 f2351feb6bed7bbbc12df059431abc2b d05736a051d06a37000000000000009b f2351feb6bed7bbbc12df059431abc2b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtn.u32.f32 d0, d20 db1decb2f46cc712db72a00406cc40c9 c151cbb574da982f7611670a77971a95 db1decb2f46cc712ffffffffffffffff c151cbb574da982f7611670a77971a95 fpscr=00000000
+vcvtn.u32.f32 d0, d20 4361b3c3e318e9c04a4a0ef54aa027c1 545db7eb4425fa79c12aa51dad9301ad 4361b3c3e318e9c00000000000000000 545db7eb4425fa79c12aa51dad9301ad fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtn.u32.f32 d0, d20 76ed21fbc55de2cda589a385a6facf42 78fe2fcadf80231618a2d02518a2d025 76ed21fbc55de2cd0000000000000000 78fe2fcadf80231618a2d02518a2d025 fpscr=00000000
+vcvtn.u32.f32 d0, d20 b69bb395ff2b381ace62f14b83163a80 e3df157dc6eb4fb7086b0065f90ae48b b69bb395ff2b381a0000000000000000 e3df157dc6eb4fb7086b0065f90ae48b fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtn.u32.f32 d0, d20 298840d38b3f88125d543a68298840d3 b5c2b3cd6598650c83f6e2d01a47f97e 298840d38b3f88120000000000000000 b5c2b3cd6598650c83f6e2d01a47f97e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtn.u32.f32 d0, d20 0fe36084f367d2e420bf04dd92bfda99 4ba5d4bb5b39359062a21cb622bca62b 0fe36084f367d2e4ffffffff00000000 4ba5d4bb5b39359062a21cb622bca62b fpscr=00000000
+vcvtn.u32.f32 d0, d20 3bd330f05d0b6fa573a75cbe66d88bc9 2e1108f814b01e2968c16ea93a95afcf 3bd330f05d0b6fa5ffffffff00000000 2e1108f814b01e2968c16ea93a95afcf fpscr=00000000
+vcvtn.u32.f32 d0, d20 3d2b7fa8fe76b2a1c5f1c52117df0700 70dd4cc3a7e96b2bea7d3c3dad2fcf73 3d2b7fa8fe76b2a10000000000000000 70dd4cc3a7e96b2bea7d3c3dad2fcf73 fpscr=00000000
+vcvtn.u32.f32 d0, d20 665ef64de7b8133e5ceba099c34b7336 4f1d87f3963fd06eed35d7e47f388640 665ef64de7b8133e00000000ffffffff 4f1d87f3963fd06eed35d7e47f388640 fpscr=00000000
+vcvtn.u32.f32 d0, d20 41dc92cac5fa931af334ea88b7125db8 ac3d368e0dedca65575bfbf5df572d83 41dc92cac5fa931affffffff00000000 ac3d368e0dedca65575bfbf5df572d83 fpscr=00000000
+vcvtn.u32.f32 d0, d20 ac4e6765f91e9461ad85a8ebc2806467 e55bc34a8ab7c6fb141e33689391aeb8 ac4e6765f91e94610000000000000000 e55bc34a8ab7c6fb141e33689391aeb8 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.u32.f32 d0, d20 42c9154b9618f076bf2ca52a7dde989e c3264280e771fb2be771fb2b440fa25d 42c9154b9618f076000000000000023f c3264280e771fb2be771fb2b440fa25d fpscr=00000000
+vcvtn.u32.f32 d0, d20 3f512a7c20f7a3fccd2c6e84746b7ec7 bc05a94d4c2b0e884edf2af72f53f42a 3f512a7c20f7a3fc6f957b8000000000 bc05a94d4c2b0e884edf2af72f53f42a fpscr=00000000
+vcvtn.u32.f32 d0, d20 618fa6ab0d0dac9eb2129ae992b723ea 240db6306f73496803043ebb6d2af262 618fa6ab0d0dac9e00000000ffffffff 240db6306f73496803043ebb6d2af262 fpscr=00000000
+vcvtn.u32.f32 d0, d20 677a1f0cfcad002461ecf68824d2a3d1 19aa7caf919236f011c0c4e37a954b17 677a1f0cfcad002400000000ffffffff 19aa7caf919236f011c0c4e37a954b17 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtn.u32.f32 d0, d20 3f16fce2f7a19062842b97f39bd0681b 5a161462fd057e2cdbdc5106814bfb1e 3f16fce2f7a190620000000000000000 5a161462fd057e2cdbdc5106814bfb1e fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtn.u32.f32 d0, d20 d0a074ce772c617ecbfa3a49157d58ec 4b1f2804b954e34a483b8c6bb954e34a d0a074ce772c617e0002ee3200000000 4b1f2804b954e34a483b8c6bb954e34a fpscr=00000000
+vcvtn.u32.f32 d0, d20 3b0b88873cd3b14e9c1d50265b65e324 d68d1d32502613f3048337865c953174 3b0b88873cd3b14e00000000ffffffff d68d1d32502613f3048337865c953174 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtn.u32.f32 d0, d20 3db06f2ad65527a712fb066b22c80861 4daa95a32011194bcbfd4d55c8b74cb5 3db06f2ad65527a70000000000000000 4daa95a32011194bcbfd4d55c8b74cb5 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtn.u32.f32 d0, d20 a4530254bb4155a58bf99b7791252d3d 6eb4211edfd22d868b172d18a4c79bf0 a4530254bb4155a50000000000000000 6eb4211edfd22d868b172d18a4c79bf0 fpscr=00000000
+vcvta.u32.f32 d5, d25 019e06a05f954184c431f9b93df029f4 17f4a9a06a18fb530714031dfe090e24 00000000ffffffffc431f9b93df029f4 17f4a9a06a18fb530714031dfe090e24 fpscr=00000000
+vcvta.u32.f32 d5, d25 96ff2a102ce969baab648b3c5bc1cf0a 1a432b5a56a7fa6bc422d1b8ec389497 00000000ffffffffab648b3c5bc1cf0a 1a432b5a56a7fa6bc422d1b8ec389497 fpscr=00000000
+vcvta.u32.f32 d5, d25 eb70a0f38a3e8aa6fa6450c83325e25c a8d3757c747920df6f5434510b40d241 00000000fffffffffa6450c83325e25c a8d3757c747920df6f5434510b40d241 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[2]
+vcvta.u32.f32 d5, d25 47aba37f8c7899d747aba37fcaee19ac 0f67b0abd6aba8320453ad15d6aba832 000000000000000047aba37fcaee19ac 0f67b0abd6aba8320453ad15d6aba832 fpscr=00000000
+vcvta.u32.f32 d5, d25 d79e0101969c4ef61bc806046a16a82d f8e29a8a8e461e0ef2fab2f8beb66be8 00000000000000001bc806046a16a82d f8e29a8a8e461e0ef2fab2f8beb66be8 fpscr=00000000
+vcvta.u32.f32 d5, d25 3ee55f34eb970b35581202834fa2cceb 8b13301c455d01bef8f3c9bc78562081 0000000000000dd0581202834fa2cceb 8b13301c455d01bef8f3c9bc78562081 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.u32.f32 d5, d25 fdb8e27efdb8e27e4d4f51a73b20f319 e0d0578f8ea9c5fea237a20a86b77f9f 00000000000000004d4f51a73b20f319 e0d0578f8ea9c5fea237a20a86b77f9f fpscr=00000000
+vcvta.u32.f32 d5, d25 a2448c90c9d49c67d51b1d451d317d36 f6de4206f048d5c16b02dc4bfded93f5 0000000000000000d51b1d451d317d36 f6de4206f048d5c16b02dc4bfded93f5 fpscr=00000000
+vcvta.u32.f32 d5, d25 f3a31b63cfea9cece043121024fc6f0f 1b02e345b53f7d35d702f281e37afb69 0000000000000000e043121024fc6f0f 1b02e345b53f7d35d702f281e37afb69 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.u32.f32 d5, d25 33a0f903f39c5c9033a0f90386fe166a 3e6c8fcc3e6c8fcc09ec598d1aa314a3 000000000000000033a0f90386fe166a 3e6c8fcc3e6c8fcc09ec598d1aa314a3 fpscr=00000000
+vcvta.u32.f32 d5, d25 26f9ad898918d8ae8caa5b2e4e5c198b ab7ae9d77b2bd0bc3774ebb37320aea6 00000000ffffffff8caa5b2e4e5c198b ab7ae9d77b2bd0bc3774ebb37320aea6 fpscr=00000000
+vcvta.u32.f32 d5, d25 9ab3d4d06cf9b51416e12ec1e5faeef5 08c1decd1db2750d1739dd8b3ff5af61 000000000000000016e12ec1e5faeef5 08c1decd1db2750d1739dd8b3ff5af61 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[3]
+vcvta.u32.f32 d5, d25 add2b91587f8d562bffc1a97aa4ecb1d 5c6e3fd90ccf3bb90ccf3bb922a54539 ffffffff00000000bffc1a97aa4ecb1d 5c6e3fd90ccf3bb90ccf3bb922a54539 fpscr=00000000
+vcvta.u32.f32 d5, d25 6d464258301b3a7ccfea27f2ff321a33 87c3c256b1340db3a3956f8f698c920b 0000000000000000cfea27f2ff321a33 87c3c256b1340db3a3956f8f698c920b fpscr=00000000
+vcvta.u32.f32 d5, d25 7b3bbf60629e8ee035f5f00518abb45c 08b8a16f65d2bbcb0469e92542bc8a43 00000000ffffffff35f5f00518abb45c 08b8a16f65d2bbcb0469e92542bc8a43 fpscr=00000000
+vcvta.u32.f32 d5, d25 ba588f4e9a1a5413418d65863fa93c9c a420ea64b8ca700bc62303646c7bd645 0000000000000000418d65863fa93c9c a420ea64b8ca700bc62303646c7bd645 fpscr=00000000
+vcvta.u32.f32 d5, d25 4ef819b755b9846419458d018a177c81 5ea935c5ac390aa92dcd05976c4f2afc ffffffff0000000019458d018a177c81 5ea935c5ac390aa92dcd05976c4f2afc fpscr=00000000
+vcvta.u32.f32 d5, d25 d1d87b5730d0c11cc6404a530b87d8b0 abc377d533b9b23322e5a44d573ee150 0000000000000000c6404a530b87d8b0 abc377d533b9b23322e5a44d573ee150 fpscr=00000000
+vcvta.u32.f32 d5, d25 18bd4f76ee40a34abe7d5367d6151d91 ec1f6588253204597c6ddbc394a7e4b5 0000000000000000be7d5367d6151d91 ec1f6588253204597c6ddbc394a7e4b5 fpscr=00000000
+vcvta.u32.f32 d5, d25 602ac1c13bfa75a586c25278da5faff6 96114a7815ef611a4794041d98a71054 000000000000000086c25278da5faff6 96114a7815ef611a4794041d98a71054 fpscr=00000000
+vcvta.u32.f32 d5, d25 45b2c8f2f0d751c186f7a0c679bf6942 dfc5d5be4262e87c7ee0f5e973c9d701 000000000000003986f7a0c679bf6942 dfc5d5be4262e87c7ee0f5e973c9d701 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvta.u32.f32 d5, d25 2920fd9d2920fd9d374a45c8db14b038 3d958daa823806b57de724e2a39b86d2 0000000000000000374a45c8db14b038 3d958daa823806b57de724e2a39b86d2 fpscr=00000000
+vcvta.u32.f32 d5, d25 b78ea467c2672b72a9a131bbd4c515e4 cd1733c45fa3ad353467b8c12aea9a71 00000000ffffffffa9a131bbd4c515e4 cd1733c45fa3ad353467b8c12aea9a71 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvta.u32.f32 d5, d25 a606eef6aef438048bef18fc2ccb3ee2 b8b1bfd73499b0a3310d55ca310d55ca 00000000000000008bef18fc2ccb3ee2 b8b1bfd73499b0a3310d55ca310d55ca fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvta.u32.f32 d5, d25 3a4d611bb110fdc73a4d611b6cba1201 73f9cca33b2e1384787506714462328e ffffffff000000003a4d611b6cba1201 73f9cca33b2e1384787506714462328e fpscr=00000000
+randV128: 15104 calls, 15614 iters
+vcvta.u32.f32 d5, d25 1425d7120ba7cf16d48b42d3540acd3e fcabc659ad62faea4eeefefb568250e2 0000000000000000d48b42d3540acd3e fcabc659ad62faea4eeefefb568250e2 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.u32.f32 d5, d25 25f6e618cd7054b6544b747b4aa79172 4485c7f436b03df6951db120dbb2ac42 0000042e00000000544b747b4aa79172 4485c7f436b03df6951db120dbb2ac42 fpscr=00000000
+vcvta.u32.f32 d5, d25 2442587c395c3c595b266d70e5d1d7ff edcbbcd9dabd69f460c91715c25e8d08 00000000000000005b266d70e5d1d7ff edcbbcd9dabd69f460c91715c25e8d08 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[1]
+vcvta.u32.f32 d5, d25 73f50537d5e1c1cec044a8d82321d387 c9ed0bbf8d8b395e05db89b0ed28fcb8 0000000000000000c044a8d82321d387 c9ed0bbf8d8b395e05db89b0ed28fcb8 fpscr=00000000
+vcvta.u32.f32 d5, d25 c1428da3ce52a93c16c435c3ae1068fe 0ebf38e3342da351fd74feb3d9fccfae 000000000000000016c435c3ae1068fe 0ebf38e3342da351fd74feb3d9fccfae fpscr=00000000
+vcvta.u32.f32 d5, d25 dc0701ab5d45d257d73a1ac8e8be2690 98f2f64c5a8f1e5ba5e1aee871ff5595 00000000ffffffffd73a1ac8e8be2690 98f2f64c5a8f1e5ba5e1aee871ff5595 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.u32.f32 d5, d25 c96736afd5fdde024ce8caf0ce84c8aa b243837757983fda710a5b1ff25a54d4 00000000ffffffff4ce8caf0ce84c8aa b243837757983fda710a5b1ff25a54d4 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvta.u32.f32 d5, d25 8efcf67376a73215f6eb4691a48ced0a 71c05c1d74121b6aeb3f8e8e5d69338e fffffffffffffffff6eb4691a48ced0a 71c05c1d74121b6aeb3f8e8e5d69338e fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[2]
+vcvta.u32.f32 d5, d25 3431597f3431597f18ec2d28983f3688 098451934154356fb7dd2626877d8be7 000000000000000d18ec2d28983f3688 098451934154356fb7dd2626877d8be7 fpscr=00000000
+vcvta.u32.f32 d5, d25 f1507743f5330572d2adfc64ec0b76e2 1a075caaf8fb6e0bf18e0968be04545a 0000000000000000d2adfc64ec0b76e2 1a075caaf8fb6e0bf18e0968be04545a fpscr=00000000
+vcvta.u32.f32 d5, d25 b482eaaad844da479fd4f072b83380f7 f69752e6cfe08e27da1edd93cd0be6e3 00000000000000009fd4f072b83380f7 f69752e6cfe08e27da1edd93cd0be6e3 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.u32.f32 d5, d25 c2eaba31b81ae0e38dc40b3bf2027415 daa7d4514cf847e51bdf040ca6c212cc 0000000007c23f288dc40b3bf2027415 daa7d4514cf847e51bdf040ca6c212cc fpscr=00000000
+vcvta.u32.f32 d5, d25 f30de7ccfb6bf55656b1a7e5bec0dd65 883df6c5eb9ee1c2852639b79f2e21ad 000000000000000056b1a7e5bec0dd65 883df6c5eb9ee1c2852639b79f2e21ad fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.u32.f32 d5, d25 2338e7de642929076013635877c4e7be f2eebbbad3a3d86b9315f9b0d3a3d86b 00000000000000006013635877c4e7be f2eebbbad3a3d86b9315f9b0d3a3d86b fpscr=00000000
+vcvta.u32.f32 d5, d25 6314492a5722dcfb9105d0b97265ecbb 51c6027ef7df036e027ee4da46f8444a ffffffff000000009105d0b97265ecbb 51c6027ef7df036e027ee4da46f8444a fpscr=00000000
+vcvta.u32.f32 d5, d25 b25e2136668f6dec2378eabf59e74893 4d144bbd8dd92470cb24ba5f6e9f3a01 0944bbd0000000002378eabf59e74893 4d144bbd8dd92470cb24ba5f6e9f3a01 fpscr=00000000
+vcvta.u32.f32 d5, d25 bf58f5c3b83a39b6b2bb2144c11975c4 58df4d23420256e284218ab1c1d94c3f ffffffff00000021b2bb2144c11975c4 58df4d23420256e284218ab1c1d94c3f fpscr=00000000
+vcvta.u32.f32 d5, d25 a9e8154a93553054920d96c11f4a56db 06551dc530f7300f2e8e271a2ec7a744 0000000000000000920d96c11f4a56db 06551dc530f7300f2e8e271a2ec7a744 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvta.u32.f32 d5, d25 ee8b8841b4ac4701babbd1043a6cc3bc ea6d5144c5255eed2e3ab478b1413bba 0000000000000000babbd1043a6cc3bc ea6d5144c5255eed2e3ab478b1413bba fpscr=00000000
+vcvta.u32.f32 d5, d25 0ababfab7a74211cf515de8a597834c5 017626b2a0da8a5d12d3672df8e75e67 0000000000000000f515de8a597834c5 017626b2a0da8a5d12d3672df8e75e67 fpscr=00000000
+vcvta.u32.f32 d5, d25 fcff9517c72243fc99b0af203d24a5ae a733e2681d346af5d28a5af4db523ba0 000000000000000099b0af203d24a5ae a733e2681d346af5d28a5af4db523ba0 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvta.u32.f32 d5, d25 3da3e016175ed68ef51727edb2d8c6ab 1091a0e7dfda58451db9feff0e51bafc 0000000000000000f51727edb2d8c6ab 1091a0e7dfda58451db9feff0e51bafc fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvta.u32.f32 d5, d25 30502f9dd6765b50131d12f3e1be6a7e 919106e4b917ea619fea4d63bf8a6fd0 0000000000000000131d12f3e1be6a7e 919106e4b917ea619fea4d63bf8a6fd0 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvta.u32.f32 d5, d25 ce487ec55c59d31ef437c442b20cdbe5 e7ad171ceef993d3e7ad171cd36187ba 0000000000000000f437c442b20cdbe5 e7ad171ceef993d3e7ad171cd36187ba fpscr=00000000
+vcvta.u32.f32 d5, d25 ce2b72b83915fc53027e3d01c7db7fe7 d5b8e6ba88ea4dd2e0e3206a899fceb6 0000000000000000027e3d01c7db7fe7 d5b8e6ba88ea4dd2e0e3206a899fceb6 fpscr=00000000
+vcvtp.u32.f32 d10, d30 d51add7e0c537590452fcd41f5fb5326 959964003b6b4113327c9d773d66ac09 d51add7e0c5375900000000100000001 959964003b6b4113327c9d773d66ac09 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtp.u32.f32 d10, d30 f1f4b3d3552b0348b5aa4872bf422171 105ff6f0482e163127436335bcb5fd17 f1f4b3d3552b03480000000100000000 105ff6f0482e163127436335bcb5fd17 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtp.u32.f32 d10, d30 018774cf912763574be6fe62089faa91 98c6b58e854e387e3f7ee72505b8f91e 018774cf912763570000000100000001 98c6b58e854e387e3f7ee72505b8f91e fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.u32.f32 d10, d30 5e917712dd7d55f29873c7749e36b06e 4b352c4b9013c997ef6fac1e121e9cd1 5e917712dd7d55f20000000000000001 4b352c4b9013c997ef6fac1e121e9cd1 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.u32.f32 d10, d30 5a7ac901ce1c00ff1d6cc96bb91b4cd1 dcf166cd9296dd219296dd21559b64b1 5a7ac901ce1c00ff00000000ffffffff dcf166cd9296dd219296dd21559b64b1 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.u32.f32 d10, d30 d8547a443b12866efd0b3c4c8a36d45e 66daee2c34ea7791a9fe6d6b34ea7791 d8547a443b12866e0000000000000001 66daee2c34ea7791a9fe6d6b34ea7791 fpscr=00000000
+vcvtp.u32.f32 d10, d30 23719bca3322f2963077f595aa4adbda 985c689f2bd5055d42343fee1ed48cff 23719bca3322f2960000002e00000001 985c689f2bd5055d42343fee1ed48cff fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.u32.f32 d10, d30 bde5d361d2725ec0e609c404d2725ec0 5e18e9480566bb6e5ba4bb66049b903d bde5d361d2725ec0ffffffff00000001 5e18e9480566bb6e5ba4bb66049b903d fpscr=00000000
+vcvtp.u32.f32 d10, d30 04ef28499294c22b6ab42d155c0f5ba3 9bcd755ca9628cda27b5770b182c0d40 04ef28499294c22b0000000100000001 9bcd755ca9628cda27b5770b182c0d40 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.u32.f32 d10, d30 00eecbb4bba776af055309cba364057b f1848019e93b522def934a595e2e5987 00eecbb4bba776af00000000ffffffff f1848019e93b522def934a595e2e5987 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtp.u32.f32 d10, d30 3918ee681622bce21622bce200b98e8d dc8ebaedcd97bbc39cdf57c041ada9b4 3918ee681622bce20000000000000016 dc8ebaedcd97bbc39cdf57c041ada9b4 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.u32.f32 d10, d30 0277efb7f99323b769520b2f2e047fb8 77cbd44184c944d310447027fa12fdeb 0277efb7f99323b70000000100000000 77cbd44184c944d310447027fa12fdeb fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.u32.f32 d10, d30 7a27e6b330705d8dfa1e98cfc525d0d6 8232d5ab9dc88e5f1d2eee341d2eee34 7a27e6b330705d8d0000000100000001 8232d5ab9dc88e5f1d2eee341d2eee34 fpscr=00000000
+vcvtp.u32.f32 d10, d30 664eb0dd63958cb9e0c950895bc1961e 68b814c1bc54bf9c12a15038dd7e307e 664eb0dd63958cb90000000100000000 68b814c1bc54bf9c12a15038dd7e307e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.u32.f32 d10, d30 d66002c7cd0b18c2fec04f70b4b7d034 ec15274c193ad82fcbd02292cc43c5f6 d66002c7cd0b18c20000000000000000 ec15274c193ad82fcbd02292cc43c5f6 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtp.u32.f32 d10, d30 b6cbfc3948c86e11935e4458b6cbfc39 aabdeda4934df81f3088de77ca171d5e b6cbfc3948c86e110000000100000000 aabdeda4934df81f3088de77ca171d5e fpscr=00000000
+vcvtp.u32.f32 d10, d30 200b6643c39d571978661bf670949059 0b81d6d9cc7121e9dde6702a812f0e3a 200b6643c39d57190000000000000000 0b81d6d9cc7121e9dde6702a812f0e3a fpscr=00000000
+vcvtp.u32.f32 d10, d30 fbb9b3a6c7948e22835b14167903ae96 e785559d07a7d9c866772a2fd28a21e0 fbb9b3a6c7948e22ffffffff00000000 e785559d07a7d9c866772a2fd28a21e0 fpscr=00000000
+vcvtp.u32.f32 d10, d30 98e9a2384cbd41fa6d9935621b981a26 8c2989a0737eb29f0a2310ce5a2ce9d6 98e9a2384cbd41fa00000001ffffffff 8c2989a0737eb29f0a2310ce5a2ce9d6 fpscr=00000000
+vcvtp.u32.f32 d10, d30 f23e3f3c70a9cf5e80fb45bd71fabbe3 b29789ffbc6b7ac67432822ff3565a4b f23e3f3c70a9cf5effffffff00000000 b29789ffbc6b7ac67432822ff3565a4b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.u32.f32 d10, d30 9f999fcb2809ca727341c8e2f9531dcf 2b69e1f9d811d561af30fb51ca03a3ac 9f999fcb2809ca720000000000000000 2b69e1f9d811d561af30fb51ca03a3ac fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtp.u32.f32 d10, d30 5c45d7ec9e5551f677fb5eac2b092f2a 21ea686964eb70b1f105b7ddbc12ef32 5c45d7ec9e5551f60000000000000000 21ea686964eb70b1f105b7ddbc12ef32 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtp.u32.f32 d10, d30 11bd7f37d2a2666b0d5a2c44d019de17 689eb0940ef0e3c8a6321c31b382905b 11bd7f37d2a2666b0000000000000000 689eb0940ef0e3c8a6321c31b382905b fpscr=00000000
+vcvtp.u32.f32 d10, d30 cd4d05d8ff5a3ea837b1f3f5325e8d45 a7901b12093557ab2ce091d56d584413 cd4d05d8ff5a3ea800000001ffffffff a7901b12093557ab2ce091d56d584413 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtp.u32.f32 d10, d30 85cc2790eafa4d6de527a2dad3b39ce9 ed8892801e7fac86772ffa6746c8343b 85cc2790eafa4d6dffffffff0000641b ed8892801e7fac86772ffa6746c8343b fpscr=00000000
+vcvtp.u32.f32 d10, d30 82b4b25f2c56034c319d4eb5661b3aae 5044f396e359d3d520d9dc5f5f7dceb5 82b4b25f2c56034c00000001ffffffff 5044f396e359d3d520d9dc5f5f7dceb5 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtp.u32.f32 d10, d30 52be77ec55018fb8907dfee76ffab899 973a281b973a281b898355aa3dcd69d3 52be77ec55018fb80000000000000001 973a281b973a281b898355aa3dcd69d3 fpscr=00000000
+vcvtp.u32.f32 d10, d30 5f00785db0e889f454daf29d3c8f03d4 2efe0c54f8b14464dce1eb23371f571f 5f00785db0e889f40000000000000001 2efe0c54f8b14464dce1eb23371f571f fpscr=00000000
+vcvtp.u32.f32 d10, d30 e3d1eef431135868ad4b40278396a0de e1c60810c4c7f2b356ebc9dc1f2b12ad e3d1eef431135868ffffffff00000001 e1c60810c4c7f2b356ebc9dc1f2b12ad fpscr=00000000
+vcvtp.u32.f32 d10, d30 c0b123bd0c06b229e2029633628c20cc a07edd209d906e80c0c66b086db66596 c0b123bd0c06b22900000000ffffffff a07edd209d906e80c0c66b086db66596 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtp.u32.f32 d10, d30 71f6f04400a7e3dbd1ae95a0d1ae95a0 70da484ed7eff69f5d932df5a65e035b 71f6f04400a7e3dbffffffff00000000 70da484ed7eff69f5d932df5a65e035b fpscr=00000000
+vcvtp.u32.f32 d10, d30 096de7991a457c5e4ce649d650b60c1d 550332ae19ebea94975b6e23cc497357 096de7991a457c5e0000000000000000 550332ae19ebea94975b6e23cc497357 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[1]
+vcvtp.u32.f32 d10, d30 a24d150ce2dec90ee2dec90e0a14fe1c b52e6e05bb6df896efbdaeacdc634540 a24d150ce2dec90e0000000000000000 b52e6e05bb6df896efbdaeacdc634540 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtp.u32.f32 d10, d30 4e6189ed69fd06cfb7153c02621d45ce 06d47c31871adb710d62a05aad65c201 4e6189ed69fd06cf0000000100000000 06d47c31871adb710d62a05aad65c201 fpscr=00000000
+vcvtp.u32.f32 d10, d30 282b3d3b841f1487bcb63da4f4d752fa 33033f816b0243a8e2cbc246c5194fb5 282b3d3b841f14870000000000000000 33033f816b0243a8e2cbc246c5194fb5 fpscr=00000000
+vcvtp.u32.f32 d10, d30 6291f04c0fc11b275103e289f9ee3b2a 4eb876a398afa64a6440881b3d5c0218 6291f04c0fc11b27ffffffff00000001 4eb876a398afa64a6440881b3d5c0218 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtp.u32.f32 d10, d30 affac8f21fc6ea69fbe37bef956ed452 7f22565592bcde81e85773cee85773ce affac8f21fc6ea690000000000000000 7f22565592bcde81e85773cee85773ce fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[3]
+vcvtp.u32.f32 d10, d30 36262e4d7370a20b36262e4d8539ccf1 fd9422a12d0d67182d0d67181415788b 36262e4d7370a20b0000000100000001 fd9422a12d0d67182d0d67181415788b fpscr=00000000
+vcvtp.u32.f32 d10, d30 e24334eb6d078822ac5f050d24cb1fb8 6e02b07fb70d9fd77489491a1302730d e24334eb6d078822ffffffff00000001 6e02b07fb70d9fd77489491a1302730d fpscr=00000000
+randV128: 15360 calls, 15882 iters
+vcvtp.u32.f32 d10, d30 40680e056c075c0101be50e1f8a80994 4ebb6a5ead74eeb3b9815ad00525782d 40680e056c075c010000000000000001 4ebb6a5ead74eeb3b9815ad00525782d fpscr=00000000
+vcvtp.u32.f32 d10, d30 908222e72f6084e369586bcca9ec51b0 cb69dd8f8948c1ec8190d147c9c125fb 908222e72f6084e30000000000000000 cb69dd8f8948c1ec8190d147c9c125fb fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.u32.f32 d10, d30 10be492570ec1c59f5e287ec70ec1c59 d94f533821bd07b52e7effdf8a196888 10be492570ec1c590000000100000000 d94f533821bd07b52e7effdf8a196888 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[2]
+vcvtp.u32.f32 d10, d30 09592d5a09592d5a44761afa896f5da6 a35f1f63761367d81b64a6ca761367d8 09592d5a09592d5a00000001ffffffff a35f1f63761367d81b64a6ca761367d8 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[2]
+vcvtp.u32.f32 d10, d30 6d354ea12a9a8fce0f0fbde7e4944986 a454ac4654c919376b0dfbc5a454ac46 6d354ea12a9a8fceffffffff00000000 a454ac4654c919376b0dfbc5a454ac46 fpscr=00000000
+vcvtp.u32.f32 d10, d30 4c9f558dd8f3c3894c61a454db96bbf1 82dbb866eb3ffabfb2b576b012571192 4c9f558dd8f3c3890000000000000001 82dbb866eb3ffabfb2b576b012571192 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtp.u32.f32 d10, d30 8458f92afc6bf28e7e9c3076df89abd6 e164ebbf9c4236ea0219f31b8e30a427 8458f92afc6bf28e0000000100000000 e164ebbf9c4236ea0219f31b8e30a427 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtp.u32.f32 d10, d30 699e2f4d699e2f4d4ce1fcbf7e092808 127395a0a809c00f4a7ae2a0fdf11394 699e2f4d699e2f4d003eb8a800000000 127395a0a809c00f4a7ae2a0fdf11394 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtp.u32.f32 d10, d30 aefd542c1f944c58aefd542c3a506ba7 4fb825acee8fc0b7f7a538f921d523a7 aefd542c1f944c580000000000000001 4fb825acee8fc0b7f7a538f921d523a7 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtp.u32.f32 d10, d30 e55201b50b64cd16ab70da2f0afce007 da44c73d09d5d2e13f4d2e6a458a0e52 e55201b50b64cd160000000100001142 da44c73d09d5d2e13f4d2e6a458a0e52 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtp.u32.f32 d10, d30 1a5d01768b2c1aaefe7646afda8e76af 0c743a12d4aef5be75a45901fd128fed 1a5d01768b2c1aaeffffffff00000000 0c743a12d4aef5be75a45901fd128fed fpscr=00000000
+vcvtm.u32.f32 d15, d15 b5f36916f534df9c94c4e20afb3487c6 225b986c5dd95c84c8ac42a66e85292c 00000000ffffffffc8ac42a66e85292c 00000000ffffffffc8ac42a66e85292c fpscr=00000000
+vcvtm.u32.f32 d15, d15 c92fbbd6545b976053b9a3bb90419abd dc349e578b7e6a403556210a2dac8882 00000000000000003556210a2dac8882 00000000000000003556210a2dac8882 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtm.u32.f32 d15, d15 e0aab3f099485cf1c5124091dd8e597a ff46191c4ead2be058c1e196d933f638 000000005695f00058c1e196d933f638 000000005695f00058c1e196d933f638 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.u32.f32 d15, d15 e483b213af8e395d5f573dba4b77d5a6 38d81f0b38d81f0bc09232658bee3107 0000000000000000c09232658bee3107 0000000000000000c09232658bee3107 fpscr=00000000
+vcvtm.u32.f32 d15, d15 3d1f60772e460894b6d74faf98026637 a47a07f5e3f2783f5dde651dd70f70db 00000000000000005dde651dd70f70db 00000000000000005dde651dd70f70db fpscr=00000000
+vcvtm.u32.f32 d15, d15 3089d6d11545188918f5e36b1ea2f7f1 ac5b0f35500571b82fcf5d527d723163 00000000ffffffff2fcf5d527d723163 00000000ffffffff2fcf5d527d723163 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[1]
+vcvtm.u32.f32 d15, d15 01fd8a904f6c654ca3225569a3225569 059c049fb35ff29db3d4e72868998085 0000000000000000b3d4e72868998085 0000000000000000b3d4e72868998085 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.u32.f32 d15, d15 c2497635f64887986d2871524c7866b9 398e021d3b0d2174cf94f491c8f4995d 0000000000000000cf94f491c8f4995d 0000000000000000cf94f491c8f4995d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtm.u32.f32 d15, d15 5d8f4220b153b57630ae000d67539412 cd304fb28a9aa609e04a2d81ab9430fd 0000000000000000e04a2d81ab9430fd 0000000000000000e04a2d81ab9430fd fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+vcvtm.u32.f32 d15, d15 badea1a6badea1a665a8afe9df4ea84c d9c057dacaeea12ecaeea12e216e7575 0000000000000000caeea12e216e7575 0000000000000000caeea12e216e7575 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[3]
+vcvtm.u32.f32 d15, d15 97324607b0c8a1655f862636ab463f6d 0abb7778686721460abb777805bcbd00 00000000ffffffff0abb777805bcbd00 00000000ffffffff0abb777805bcbd00 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[1]
+vcvtm.u32.f32 d15, d15 6da96d9b3ac0adf87d2e08b46da96d9b 5e8c4ab4407df216bdcc8f03975516a9 ffffffff00000003bdcc8f03975516a9 ffffffff00000003bdcc8f03975516a9 fpscr=00000000
+vcvtm.u32.f32 d15, d15 412eb1e4f60775c9eca6cd56d82837e1 3227f3d222d5a34459cdfe27fd9d0a01 000000000000000059cdfe27fd9d0a01 000000000000000059cdfe27fd9d0a01 fpscr=00000000
+vcvtm.u32.f32 d15, d15 40663cc0cbaa70de1ecff64fadef3e85 8f61acc9adf12d99372af8c483dfba08 0000000000000000372af8c483dfba08 0000000000000000372af8c483dfba08 fpscr=00000000
+vcvtm.u32.f32 d15, d15 a2df37c34663a656496221e5aecd0acb 85bf5956c4eb89f243a77b89705eda91 000000000000000043a77b89705eda91 000000000000000043a77b89705eda91 fpscr=00000000
+vcvtm.u32.f32 d15, d15 50ab89e5f6cc948c8f6321d09db7a45a 9b5f72e8e8125fa1cb2fc1e4552b3e84 0000000000000000cb2fc1e4552b3e84 0000000000000000cb2fc1e4552b3e84 fpscr=00000000
+vcvtm.u32.f32 d15, d15 5cd568d4e2cb8ddebbe1ff6ffac68b8d 4303bdfce8247c0233ce6632030fb37d 000000830000000033ce6632030fb37d 000000830000000033ce6632030fb37d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtm.u32.f32 d15, d15 69bf9e6a19a016bef3997d85d07e58cb 24f734d6d95f5c5f92df8dc0c6d2cce9 000000000000000092df8dc0c6d2cce9 000000000000000092df8dc0c6d2cce9 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtm.u32.f32 d15, d15 020000f3a6871e46a6871e466e4d6275 d1739629dce24c256a6e10aca21f68a5 00000000000000006a6e10aca21f68a5 00000000000000006a6e10aca21f68a5 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtm.u32.f32 d15, d15 2540ac7fba40a741373b49920ea7f8ed 2949485a0c759c7b9e36832419971f82 00000000000000009e36832419971f82 00000000000000009e36832419971f82 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtm.u32.f32 d15, d15 219254c0219254c055819aa491ea5603 c3330556af7ed402d5f7deafdc8620c8 0000000000000000d5f7deafdc8620c8 0000000000000000d5f7deafdc8620c8 fpscr=00000000
+vcvtm.u32.f32 d15, d15 8583f2806059fc348353adf37ed68061 029f63797af4e10caab55b1b6ca3d9be 00000000ffffffffaab55b1b6ca3d9be 00000000ffffffffaab55b1b6ca3d9be fpscr=00000000
+vcvtm.u32.f32 d15, d15 2b9966be5424d760f6b995600539c34a 9728593f612c2b20894daeb747b78d8c 00000000ffffffff894daeb747b78d8c 00000000ffffffff894daeb747b78d8c fpscr=00000000
+vcvtm.u32.f32 d15, d15 64c934de707d888fd16358600e91cc74 143eae99ef570d828ee0e91b5020cb39 00000000000000008ee0e91b5020cb39 00000000000000008ee0e91b5020cb39 fpscr=00000000
+vcvtm.u32.f32 d15, d15 4b9870e59c6ff47752e50575dda055df 6cdc9990bb4466d2eb1b1d58e99bfd4a ffffffff00000000eb1b1d58e99bfd4a ffffffff00000000eb1b1d58e99bfd4a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.u32.f32 d15, d15 3cc78d83af763da63edfac7cb131bbd0 3c2c40bb1e29e2a63c2c40bbe954ea9f 00000000000000003c2c40bbe954ea9f 00000000000000003c2c40bbe954ea9f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.u32.f32 d15, d15 344ce2d339a6a5a8c3af2cc580882c7a 669b3f4353c2475a990940887369f5d7 ffffffffffffffff990940887369f5d7 ffffffffffffffff990940887369f5d7 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtm.u32.f32 d15, d15 b8114fcb2c365453b5ce1eddec9ea5dc a054aff7a054aff7610bd0a76335d126 0000000000000000610bd0a76335d126 0000000000000000610bd0a76335d126 fpscr=00000000
+vcvtm.u32.f32 d15, d15 1b1d7f5ec315e3c07a890693dd13e566 8dd0565419dc28f02b810816260456ca 00000000000000002b810816260456ca 00000000000000002b810816260456ca fpscr=00000000
+vcvtm.u32.f32 d15, d15 fdeb3c627c39074346c53618e5cc51cb 4e0e6b007c324d9adef06c4c4924100d 239ac000ffffffffdef06c4c4924100d 239ac000ffffffffdef06c4c4924100d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.u32.f32 d15, d15 3fb6ed8ba9ffc2e128962d5f105a0ff9 b3025708d21c526928b9be9652a24cc6 000000000000000028b9be9652a24cc6 000000000000000028b9be9652a24cc6 fpscr=00000000
+vcvtm.u32.f32 d15, d15 a75553a8c0e632da166a6673ba068216 891e69c40d6625d2bd93e19652de71c4 0000000000000000bd93e19652de71c4 0000000000000000bd93e19652de71c4 fpscr=00000000
+vcvtm.u32.f32 d15, d15 be37b48f2ec7626099265e5be83c9627 bf5a8cccdff1c1c26ff6d0b3b9df5bd9 00000000000000006ff6d0b3b9df5bd9 00000000000000006ff6d0b3b9df5bd9 fpscr=00000000
+vcvtm.u32.f32 d15, d15 4c1f4718695ae8ae89882f54b287221b f8d498d63757411888b1e1d6c55e9504 000000000000000088b1e1d6c55e9504 000000000000000088b1e1d6c55e9504 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.u32.f32 d15, d15 fc5126f23b0e3f9f40bac0c61b781b64 1f182be138727da81f182be162bfa760 00000000000000001f182be162bfa760 00000000000000001f182be162bfa760 fpscr=00000000
+vcvtm.u32.f32 d15, d15 864e7af5c1cc33e778f00b0922bda236 f5fbca6bd13839fb572de609e5bd57fc 0000000000000000572de609e5bd57fc 0000000000000000572de609e5bd57fc fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtm.u32.f32 d15, d15 73bf631e672c42a9583d60365a041cee 4eaf926d61b228a56af3a3a62f9be2fa 57c93680ffffffff6af3a3a62f9be2fa 57c93680ffffffff6af3a3a62f9be2fa fpscr=00000000
+vcvtm.u32.f32 d15, d15 4098d00ca4be2c36aee6e4dc78a48522 06e741de14c398e0c18f9ade8f65c29d 0000000000000000c18f9ade8f65c29d 0000000000000000c18f9ade8f65c29d fpscr=00000000
+vcvtm.u32.f32 d15, d15 0bb996d929712f4468ee489d3c635e3e d7075c65fd63526eb21c7ccb978d7fde 0000000000000000b21c7ccb978d7fde 0000000000000000b21c7ccb978d7fde fpscr=00000000
+vcvtm.u32.f32 d15, d15 c7f212fbf62e3d66c29c156aa42225d5 c4a1acd0e8f2bc8f9826ab5d7606dbd0 00000000000000009826ab5d7606dbd0 00000000000000009826ab5d7606dbd0 fpscr=00000000
+vcvtm.u32.f32 d15, d15 e19550bb9bd1dbc08603f2bf6af7e45d caf5ae4017bc6285da9bf31fb7912e0e 0000000000000000da9bf31fb7912e0e 0000000000000000da9bf31fb7912e0e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtm.u32.f32 d15, d15 04badef00e8aaac96bfd980f1b1615c3 cc9516b016061d886a6a5c078f61e175 00000000000000006a6a5c078f61e175 00000000000000006a6a5c078f61e175 fpscr=00000000
+vcvtm.u32.f32 d15, d15 2920f278839c37c7e00861df1e629d0b 150faa33b357ec032f15d5713d622d0f 00000000000000002f15d5713d622d0f 00000000000000002f15d5713d622d0f fpscr=00000000
+vcvtm.u32.f32 d15, d15 1e2de4750a04eebf67577d596a1989e2 11eefeb7172aee2066c2b69397abbbb4 000000000000000066c2b69397abbbb4 000000000000000066c2b69397abbbb4 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[3]
+vcvtm.u32.f32 d15, d15 da90ec17a5d712e9c7ac835b1b517faa 8774169807934a2dfd19cedf87741698 0000000000000000fd19cedf87741698 0000000000000000fd19cedf87741698 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[0]
+vcvtm.u32.f32 d15, d15 5af89326bdab4f75bdab4f7581b7fa56 f678d46658e556fbbb4e78c65f8d9d1e 00000000ffffffffbb4e78c65f8d9d1e 00000000ffffffffbb4e78c65f8d9d1e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtm.u32.f32 d15, d15 380eb2f9f93050780a9d2569380eb2f9 94e1d2b06d75bf7b4cb968ebc91cb102 00000000ffffffff4cb968ebc91cb102 00000000ffffffff4cb968ebc91cb102 fpscr=00000000
+vcvtm.u32.f32 d15, d15 2d84871a1bfecc49fea131d3b20aedfe 7e34812bca3d6a3281e4023972039c64 ffffffff0000000081e4023972039c64 ffffffff0000000081e4023972039c64 fpscr=00000000
+vcvtm.u32.f32 d15, d15 55efc3e8793154452edfea8988b714e6 977c9aac5ab9dbfd93dfce75b2090b5b 00000000ffffffff93dfce75b2090b5b 00000000ffffffff93dfce75b2090b5b fpscr=00000000
+vcvtm.u32.f32 d15, d15 c43bc03491c3e7d1e01849cc6e13712f 06474af644cc3566fed2c8ae4fa55f5a 0000000000000661fed2c8ae4fa55f5a 0000000000000661fed2c8ae4fa55f5a fpscr=00000000
+vcvtn.u32.f32 q15, q0 707cc1ebf7f149909577b2cc419a450e d39c42ee7823799c51de88fdcd5da820 00000000ffffffffffffffff00000000 d39c42ee7823799c51de88fdcd5da820 fpscr=00000000
+vcvtn.u32.f32 q15, q0 3bda322220858ab4818dd713426c0238 b76420d922c08dd240cde5fd1d90f452 00000000000000000000000600000000 b76420d922c08dd240cde5fd1d90f452 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtn.u32.f32 q15, q0 c3d8446595db951b95db951b4170481e c97c54bc3580816da87e1ca1fd30bc26 00000000000000000000000000000000 c97c54bc3580816da87e1ca1fd30bc26 fpscr=00000000
+randV128: 15616 calls, 16146 iters
+vcvtn.u32.f32 q15, q0 e84e0efa73745794b5ef70b4b442afdd adebce23aa271e040f73ac019a3a221f 00000000000000000000000000000000 adebce23aa271e040f73ac019a3a221f fpscr=00000000
+vcvtn.u32.f32 q15, q0 ee931acadb56656248be2c898423871d 6b9cbb85056e61a140e65f84f9fc99ff ffffffff000000000000000700000000 6b9cbb85056e61a140e65f84f9fc99ff fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtn.u32.f32 q15, q0 fba7493e7acf72e7e6330b8959482216 131189af131189af7a44e3e5ed98781d 0000000000000000ffffffff00000000 131189af131189af7a44e3e5ed98781d fpscr=00000000
+vcvtn.u32.f32 q15, q0 d1111fc7af7d5037bdafbe3707a8ec45 4774db1d78622b6fe10ddd898bd9be95 0000f4dbffffffff0000000000000000 4774db1d78622b6fe10ddd898bd9be95 fpscr=00000000
+vcvtn.u32.f32 q15, q0 76f2a134b6f1cf670cc778fc77026b2a a99679213d6a4586a079f7a65a13965e 000000000000000000000000ffffffff a99679213d6a4586a079f7a65a13965e fpscr=00000000
+vcvtn.u32.f32 q15, q0 8a292eea2e12c1fef2ef646da7b42ec5 ad31d5fe3974d00d959e05d5cdb86b1e 00000000000000000000000000000000 ad31d5fe3974d00d959e05d5cdb86b1e fpscr=00000000
+vcvtn.u32.f32 q15, q0 7d6836bfd3785755620056d2b3ace79f cfcf7de60f3dfdf54a65ec462f70fd6b 000000000000000000397b1200000000 cfcf7de60f3dfdf54a65ec462f70fd6b fpscr=00000000
+vcvtn.u32.f32 q15, q0 3e0ba7b12ace4e6a4d613b69719bbf91 4de1670da7b598e5ee9238ffbacaac2b 1c2ce1a0000000000000000000000000 4de1670da7b598e5ee9238ffbacaac2b fpscr=00000000
+vcvtn.u32.f32 q15, q0 02f21da96b11e9291f7cc73b58c53a04 6a3481ac8f13b5e8da7af41d2c91667a ffffffff000000000000000000000000 6a3481ac8f13b5e8da7af41d2c91667a fpscr=00000000
+vcvtn.u32.f32 q15, q0 9967c93a6e9d7b4854ed9224bb540012 86cb1c6a354c3f6ce91b52814a7f71ed 000000000000000000000000003fdc7b 86cb1c6a354c3f6ce91b52814a7f71ed fpscr=00000000
+vcvtn.u32.f32 q15, q0 23eeb6410a1a490a6d8ca5a95b800184 1f103e200ae667afb88f3bd13e591d39 00000000000000000000000000000000 1f103e200ae667afb88f3bd13e591d39 fpscr=00000000
+vcvtn.u32.f32 q15, q0 2bf86f5dc74dd7d845615dba5fa0fbad b16ecdfe7933f07ec4e2beddd35d5339 00000000ffffffff0000000000000000 b16ecdfe7933f07ec4e2beddd35d5339 fpscr=00000000
+vcvtn.u32.f32 q15, q0 16690655f3c184c1ca6db04da91a6229 6f459e13cbe35d61664c5b6c931fff57 ffffffff00000000ffffffff00000000 6f459e13cbe35d61664c5b6c931fff57 fpscr=00000000
+vcvtn.u32.f32 q15, q0 fe0b7a501b5b98d8105ad6e08c2da280 e63e6233e3fb021cb7c4345ac7be5e4b 00000000000000000000000000000000 e63e6233e3fb021cb7c4345ac7be5e4b fpscr=00000000
+vcvtn.u32.f32 q15, q0 e6db7af4dec1a872cb0a4ed4e3a1c89b 7908753cda2eee9a46f51c225574324a ffffffff0000000000007a8effffffff 7908753cda2eee9a46f51c225574324a fpscr=00000000
+vcvtn.u32.f32 q15, q0 5037906526b05a45200340ad8756882a bd658ebc828dbc2ebc977ec47993ca84 000000000000000000000000ffffffff bd658ebc828dbc2ebc977ec47993ca84 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtn.u32.f32 q15, q0 34eda326ba238d62ddbe4a2c23b0a2df bba848f9bea23e3e572133096bd9f010 0000000000000000ffffffffffffffff bba848f9bea23e3e572133096bd9f010 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[3]
+vcvtn.u32.f32 q15, q0 24bb2dc95525decf3865de1911d6a053 8d8278b20a849554c5e4104349e32e2d 000000000000000000000000001c65c6 8d8278b20a849554c5e4104349e32e2d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtn.u32.f32 q15, q0 34f67b0534f67b05ebe4f735f8b46afd 456c3c8bb32b72ee8aa330a8cf47090f 00000ec4000000000000000000000000 456c3c8bb32b72ee8aa330a8cf47090f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtn.u32.f32 q15, q0 c74a8868299b0da3a28b32b49e700877 1f9ce4b02d233c0f94d6fca38dbdb5a5 00000000000000000000000000000000 1f9ce4b02d233c0f94d6fca38dbdb5a5 fpscr=00000000
+vcvtn.u32.f32 q15, q0 fcc18ffd34334687cf9ccb53300e319f ab15669a34e54b1d90fb0f17a6f28bff 00000000000000000000000000000000 ab15669a34e54b1d90fb0f17a6f28bff fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[1]
+vcvtn.u32.f32 q15, q0 808c6167729760e4729760e498490bf5 3b6c3b3aab1c4056cf46ce9acf46ce9a 00000000000000000000000000000000 3b6c3b3aab1c4056cf46ce9acf46ce9a fpscr=00000000
+vcvtn.u32.f32 q15, q0 55e7f96eda2362de98f7dafec5f77f0e ddf2d8f55b50f13cef61674e782b9485 00000000ffffffff00000000ffffffff ddf2d8f55b50f13cef61674e782b9485 fpscr=00000000
+vcvtn.u32.f32 q15, q0 751636eaf81715603016786c1c2c4b00 87727daac5194da9eace8fdb7d6a4730 000000000000000000000000ffffffff 87727daac5194da9eace8fdb7d6a4730 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtn.u32.f32 q15, q0 36a8a25314b4382c625d242a9e79041b bd643a301e21e904b17f2f09e95d7527 00000000000000000000000000000000 bd643a301e21e904b17f2f09e95d7527 fpscr=00000000
+vcvtn.u32.f32 q15, q0 f4b7dd0402a3a5ec84b6e8ce6cbc7219 526ffe4b039dd2276e2010fdaac70305 ffffffff00000000ffffffff00000000 526ffe4b039dd2276e2010fdaac70305 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.u32.f32 q15, q0 d51a89bf4cb42f9bd51a89bfb63cd0c5 7c134ae2a182f67ed475466cc323f9e4 ffffffff000000000000000000000000 7c134ae2a182f67ed475466cc323f9e4 fpscr=00000000
+vcvtn.u32.f32 q15, q0 30917d04fa88bca80c57ec2def40309a af8e68f1fa20792e37876be33c7eb535 00000000000000000000000000000000 af8e68f1fa20792e37876be33c7eb535 fpscr=00000000
+vcvtn.u32.f32 q15, q0 6bac8765a2fbd026a2cc5ea64e190d89 ff1c32f99f3dd55e2aaebc3f18ce7e80 00000000000000000000000000000000 ff1c32f99f3dd55e2aaebc3f18ce7e80 fpscr=00000000
+vcvtn.u32.f32 q15, q0 378d33401c8a42065a96be03f2ecae78 7e4ca8c0d41189a9686a8bde6d9b72f5 ffffffff00000000ffffffffffffffff 7e4ca8c0d41189a9686a8bde6d9b72f5 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtn.u32.f32 q15, q0 c8fb3041a1fbde9b71b0460838c228fb 4eb02903e37a5cf30862bf9a68f4eb51 581481800000000000000000ffffffff 4eb02903e37a5cf30862bf9a68f4eb51 fpscr=00000000
+vcvtn.u32.f32 q15, q0 ef35ac02bd5497a915b7cf48ee255f5d b2eec08e61f747e68138d2f78cc2e575 00000000ffffffff0000000000000000 b2eec08e61f747e68138d2f78cc2e575 fpscr=00000000
+vcvtn.u32.f32 q15, q0 04a3250b974abf93a32690636207b41b 1f121a6da2f0fc3c980702b63e77a528 00000000000000000000000000000000 1f121a6da2f0fc3c980702b63e77a528 fpscr=00000000
+vcvtn.u32.f32 q15, q0 4f05752b20f6e59a3c5fb27d87c21baf fa7f6505796742bc67a7cfc3ff4e9f91 00000000ffffffffffffffff00000000 fa7f6505796742bc67a7cfc3ff4e9f91 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[1]
+vcvtn.u32.f32 q15, q0 4483d77a0fae77710fae777163f19a02 54ba3dd66744087b99abbad0ac7e5aa0 ffffffffffffffff0000000000000000 54ba3dd66744087b99abbad0ac7e5aa0 fpscr=00000000
+vcvtn.u32.f32 q15, q0 f0bcebf3ef6345b9ce368ea9735092e3 76e448321b45e06b57fa88b8b3f1014a ffffffff00000000ffffffff00000000 76e448321b45e06b57fa88b8b3f1014a fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtn.u32.f32 q15, q0 2110c57ae5b63d2b8d1d0bc482f75ffa 86178159d35540ad064d3005d81ef05e 00000000000000000000000000000000 86178159d35540ad064d3005d81ef05e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtn.u32.f32 q15, q0 e5a3a37d95b86ba77c3d0f7bd5e1d8c3 d5dc425c7cb910df2dfeb4d23985e75c 00000000ffffffff0000000000000000 d5dc425c7cb910df2dfeb4d23985e75c fpscr=00000000
+vcvtn.u32.f32 q15, q0 bc151b9fd19c6d97e810bed330a6cd6d a471a52d9b53c0ccda38b4ed6d79f9d5 000000000000000000000000ffffffff a471a52d9b53c0ccda38b4ed6d79f9d5 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtn.u32.f32 q15, q0 46c5408673b2ce0e0c77fc934d893829 409e525d3c6136163c613616740d098a 000000050000000000000000ffffffff 409e525d3c6136163c613616740d098a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtn.u32.f32 q15, q0 ecef3a5cf11fa5709e3655f1fe146d97 a6b379041739f3196997f156a195f9d9 0000000000000000ffffffff00000000 a6b379041739f3196997f156a195f9d9 fpscr=00000000
+vcvtn.u32.f32 q15, q0 afc5099fb9abdb2a1f8d8134f6dc50ec a6ef0fc3fd81ab733446059f57c068a0 000000000000000000000000ffffffff a6ef0fc3fd81ab733446059f57c068a0 fpscr=00000000
+vcvtn.u32.f32 q15, q0 86b90fc99ed4129145afed161fe924ad cd4e5358a06053a31591ed00a6e75341 00000000000000000000000000000000 cd4e5358a06053a31591ed00a6e75341 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtn.u32.f32 q15, q0 f9c9f1746e6c6f2f5466ebec1f6b1e2a 57a74efd7eead626767e6b6c12407e99 ffffffffffffffffffffffff00000000 57a74efd7eead626767e6b6c12407e99 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtn.u32.f32 q15, q0 ff556dbc1ed85bc88e095ae29e399e54 7c4a68a9b5cff3395639c001737c8828 ffffffff00000000ffffffffffffffff 7c4a68a9b5cff3395639c001737c8828 fpscr=00000000
+vcvtn.u32.f32 q15, q0 738b3a343f983c3dfa0a6f58efaffa77 defae1d4cb5e49b46998dce535f41e7b 0000000000000000ffffffff00000000 defae1d4cb5e49b46998dce535f41e7b fpscr=00000000
+vcvtn.u32.f32 q15, q0 b706a379207d40dca36d032bc5c56c47 47629fe74621c11f5191e2e0863ecb60 0000e2a000002870ffffffff00000000 47629fe74621c11f5191e2e0863ecb60 fpscr=00000000
+vcvta.u32.f32 q14, q1 7bdf1f31636f91afe8aa6ee03597347e 8bc6af5351630fa978da334acae8a8af 00000000ffffffffffffffff00000000 8bc6af5351630fa978da334acae8a8af fpscr=00000000
+vcvta.u32.f32 q14, q1 44faff9a2f7a01aad9b824f7aa70a49f 02bc950d2a620391bb263749d3079835 00000000000000000000000000000000 02bc950d2a620391bb263749d3079835 fpscr=00000000
+vcvta.u32.f32 q14, q1 864ebf178538b15039fbe74bf7423eb0 b5bfbe6d4eb1561b1fce958ce48978a7 0000000058ab0d800000000000000000 b5bfbe6d4eb1561b1fce958ce48978a7 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvta.u32.f32 q14, q1 6d31a38538b8caaa8bc3a5a47bc3b172 977b4b494ca90bca46643aa2c8e8c522 0000000005485e500000390f00000000 977b4b494ca90bca46643aa2c8e8c522 fpscr=00000000
+vcvta.u32.f32 q14, q1 c4381afe34f6feb33985451dc24048b3 4b78fc2db1387106cfeaefc21ce6537e 00f8fc2d000000000000000000000000 4b78fc2db1387106cfeaefc21ce6537e fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvta.u32.f32 q14, q1 113126c5d2241b7d308edc243857fffd cb7ec673497c08c0b579a1826a94497b 00000000000fc08c00000000ffffffff cb7ec673497c08c0b579a1826a94497b fpscr=00000000
+vcvta.u32.f32 q14, q1 6c1586526eaabe9f3100fc6309c24219 41db13d73512cfc38b7794749d59f727 0000001b000000000000000000000000 41db13d73512cfc38b7794749d59f727 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[2]
+vcvta.u32.f32 q14, q1 e49d99e99e4886c3d254ee43d254ee43 4783458ff40bda4a1ed38e10fb6e574e 0001068b000000000000000000000000 4783458ff40bda4a1ed38e10fb6e574e fpscr=00000000
+vcvta.u32.f32 q14, q1 59677d7d91d185b6d547c3818437207c d7873cd03e5e749508676ee4c924fcbe 00000000000000000000000000000000 d7873cd03e5e749508676ee4c924fcbe fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[0]
+vcvta.u32.f32 q14, q1 881de94f524f48da153ec7f4153ec7f4 4260d871f5b122efeba3bef6670c76c0 000000380000000000000000ffffffff 4260d871f5b122efeba3bef6670c76c0 fpscr=00000000
+vcvta.u32.f32 q14, q1 80c7f5093a612dbe3fc4912879a70ba0 bb9ea8cca50121bbf02b1cce073b84ec 00000000000000000000000000000000 bb9ea8cca50121bbf02b1cce073b84ec fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvta.u32.f32 q14, q1 0c960c041a1fbb4c0e28a651705dad4c a62b1692c8e4339ba62b169217d23554 00000000000000000000000000000000 a62b1692c8e4339ba62b169217d23554 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvta.u32.f32 q14, q1 743fcdaa5b0cb1bc614e55d2ba69db0a 447554fcb01e165eed05a2b6447554fc 000003d50000000000000000000003d5 447554fcb01e165eed05a2b6447554fc fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvta.u32.f32 q14, q1 ebc92aa3e40a0bc6927fbdfb4e09a500 038ab241b049323f4e2f4eb194c98a9c 00000000000000002bd3ac4000000000 038ab241b049323f4e2f4eb194c98a9c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvta.u32.f32 q14, q1 08547b0a39ead7b444746feba5411766 1ce12e17882697f6902f7f02e60a81bb 00000000000000000000000000000000 1ce12e17882697f6902f7f02e60a81bb fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvta.u32.f32 q14, q1 0a735b3c900ef47d6748c9a7e15eda8a c06ad6ff23367565fa817f56632cb1cf 000000000000000000000000ffffffff c06ad6ff23367565fa817f56632cb1cf fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvta.u32.f32 q14, q1 d21d6e0ae175baa063d9c53ed21d6e0a e04d7a0d5b4fc5dcdbd6bf73ec536128 00000000ffffffff0000000000000000 e04d7a0d5b4fc5dcdbd6bf73ec536128 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: 15872 calls, 16413 iters
+vcvta.u32.f32 q14, q1 231f7bcc159c8074c76979ff159c8074 6c226bc4d66fd5e78930b8427df98a55 ffffffff0000000000000000ffffffff 6c226bc4d66fd5e78930b8427df98a55 fpscr=00000000
+vcvta.u32.f32 q14, q1 6f3dbf6c430fcc9a2a6fd91759bddf2e c67a058b06ce521fed5d08a6518a5e06 000000000000000000000000ffffffff c67a058b06ce521fed5d08a6518a5e06 fpscr=00000000
+vcvta.u32.f32 q14, q1 13b4daedb0c6b0c807c2446456874fbd c24d541809331ec93abd83b3873dc11f 00000000000000000000000000000000 c24d541809331ec93abd83b3873dc11f fpscr=00000000
+vcvta.u32.f32 q14, q1 ed6b40ab35ad90c9b4841c56191d3302 86fd73b3bda4213e7447645cd811d216 0000000000000000ffffffff00000000 86fd73b3bda4213e7447645cd811d216 fpscr=00000000
+vcvta.u32.f32 q14, q1 2a20a73ecce6698d502988f5dc5765f7 b356577845a73e855d0de9fee617b7a3 00000000000014e8ffffffff00000000 b356577845a73e855d0de9fee617b7a3 fpscr=00000000
+vcvta.u32.f32 q14, q1 02f7fed1694dc71b3b12fabdc5082250 164dd411124d07120978b19884e78bb8 00000000000000000000000000000000 164dd411124d07120978b19884e78bb8 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvta.u32.f32 q14, q1 2d39d5246903ceed2d39d52499cf541b da9a414e899d9e31cf45b3e2eef3b0d1 00000000000000000000000000000000 da9a414e899d9e31cf45b3e2eef3b0d1 fpscr=00000000
+vcvta.u32.f32 q14, q1 7a1b1112fee270e19b2eabbd72f2d6c3 da6b0ef9b4f408c6935185896e257674 000000000000000000000000ffffffff da6b0ef9b4f408c6935185896e257674 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvta.u32.f32 q14, q1 113b63df082a99c012dade5485802803 f1d8fa34d7519911cf872de79078acb4 00000000000000000000000000000000 f1d8fa34d7519911cf872de79078acb4 fpscr=00000000
+vcvta.u32.f32 q14, q1 126072f3131d6ae10faafbbcc796e6d8 8086e1b664a64f531cbf23f560690bb2 00000000ffffffff00000000ffffffff 8086e1b664a64f531cbf23f560690bb2 fpscr=00000000
+vcvta.u32.f32 q14, q1 6047d60fa7e39d3a05eb9049d92cb5b3 ba9a1f0faa83bc651e9bea7238809eb8 00000000000000000000000000000000 ba9a1f0faa83bc651e9bea7238809eb8 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.u32.f32 q14, q1 d527f9215665528e04f85c61eadee154 7b3100432acf50880b62a1ff701ca196 ffffffff0000000000000000ffffffff 7b3100432acf50880b62a1ff701ca196 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvta.u32.f32 q14, q1 8371e33989551edd20a019dbac4386ea 31fce6cde95cca911ce800712ffc3991 00000000000000000000000000000000 31fce6cde95cca911ce800712ffc3991 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvta.u32.f32 q14, q1 35a780bc8bee450c725b41e76a27c1e7 8e158f0d15507e769efd53868e158f0d 00000000000000000000000000000000 8e158f0d15507e769efd53868e158f0d fpscr=00000000
+vcvta.u32.f32 q14, q1 1c94d96fff63701a8dda4995d9087a8f 8c3a819c634fa30e18ff9cf9a648486b 00000000ffffffff0000000000000000 8c3a819c634fa30e18ff9cf9a648486b fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvta.u32.f32 q14, q1 efc135852d6c066b9dfdf1186d32cf63 0b85c59fc6e1c76833a3fe3958acde6d 000000000000000000000000ffffffff 0b85c59fc6e1c76833a3fe3958acde6d fpscr=00000000
+vcvta.u32.f32 q14, q1 d8153bffdec80b949c2c5a3ca6e0a0fa c8cf1899de0110897956bb86d2a74098 0000000000000000ffffffff00000000 c8cf1899de0110897956bb86d2a74098 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[3]
+vcvta.u32.f32 q14, q1 6c4d0e77d04af46c2fe8bacd2fe8bacd a114a29655c8634e8a3a030b1443824d 00000000ffffffff0000000000000000 a114a29655c8634e8a3a030b1443824d fpscr=00000000
+vcvta.u32.f32 q14, q1 0578e2ba26fac3561da40c52c259bf6c bce4799a685fa4ea8e6d0e816f4f1f27 00000000ffffffff00000000ffffffff bce4799a685fa4ea8e6d0e816f4f1f27 fpscr=00000000
+vcvta.u32.f32 q14, q1 107908ae50288571871d2b872a49b8f9 fb5e1941ca85282f83653f4ec8851c8c 00000000000000000000000000000000 fb5e1941ca85282f83653f4ec8851c8c fpscr=00000000
+vcvta.u32.f32 q14, q1 655850cbd3e2cd9937aa946e7eb4ea50 24adf5850619b95da59be2495c5906a2 000000000000000000000000ffffffff 24adf5850619b95da59be2495c5906a2 fpscr=00000000
+vcvta.u32.f32 q14, q1 9bd946ce6da22e3ef83bd5381bde7192 e84edafe17662578ac8e02552c858548 00000000000000000000000000000000 e84edafe17662578ac8e02552c858548 fpscr=00000000
+vcvta.u32.f32 q14, q1 a3f28dcd8c98985bfdda84b3e065816c 746c83f04a4127fc53807bfcce1dd288 ffffffff003049ffffffffff00000000 746c83f04a4127fc53807bfcce1dd288 fpscr=00000000
+vcvta.u32.f32 q14, q1 270a57c2560977238b23fa1876dfb50c 63ca52464c8b4773849bf8a0b85ad772 ffffffff045a3b980000000000000000 63ca52464c8b4773849bf8a0b85ad772 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvta.u32.f32 q14, q1 551939000b8a2190fdaa67b8f95acce7 8a01f4e7141c976e6876ce1374bb2d4d 0000000000000000ffffffffffffffff 8a01f4e7141c976e6876ce1374bb2d4d fpscr=00000000
+vcvta.u32.f32 q14, q1 30fb01a5607ccf21b1d22a31478bf9b4 488aa82ed869b60350da5700bc8aa98e 0004554100000000ffffffff00000000 488aa82ed869b60350da5700bc8aa98e fpscr=00000000
+vcvta.u32.f32 q14, q1 f8f032a02bf8ce423b9b2bce3b9fe3e1 825cf2f2952b0f3451b5a2be8af70ed6 0000000000000000ffffffff00000000 825cf2f2952b0f3451b5a2be8af70ed6 fpscr=00000000
+vcvta.u32.f32 q14, q1 9e17ff251a1bc2ac634d82e23e63c602 541c82db21ca51857d21447885c03090 ffffffff00000000ffffffff00000000 541c82db21ca51857d21447885c03090 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvta.u32.f32 q14, q1 ea3edb182e53da29500a9ffa38d87b66 c4dda62af4f5761af9e36d3cdecd285a 00000000000000000000000000000000 c4dda62af4f5761af9e36d3cdecd285a fpscr=00000000
+vcvta.u32.f32 q14, q1 77998e9b3ba194adff2b07a2c88ef99f fd5b54310bf802a6882b4a30f5c3e808 00000000000000000000000000000000 fd5b54310bf802a6882b4a30f5c3e808 fpscr=00000000
+vcvta.u32.f32 q14, q1 b611c220cdbb9bb4d32553e6a33c362c 10f1ab66a61ccaa40a2e8a2534e3ecff 00000000000000000000000000000000 10f1ab66a61ccaa40a2e8a2534e3ecff fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.u32.f32 q14, q1 b970a17df2373324f2373324636999fe 33aba2ddb8d1b67be2ffe2a5cbd19414 00000000000000000000000000000000 33aba2ddb8d1b67be2ffe2a5cbd19414 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+vcvta.u32.f32 q14, q1 c91bb65e9de388fbbc699bf587eeb332 3e68dc10148cab0f89e97c2d28b6b280 00000000000000000000000000000000 3e68dc10148cab0f89e97c2d28b6b280 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.u32.f32 q13, q2 b5daa5ff7d267d8eb2e89fc127d00f34 a8c57b7b4129326d4129326d9a8a9480 000000000000000b0000000b00000000 a8c57b7b4129326d4129326d9a8a9480 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.u32.f32 q13, q2 7479d35bb65cd6065c92033a93f52308 4d46e8e4e6d9b746e6d9b74621a63b8c 0c6e8e40000000000000000000000001 4d46e8e4e6d9b746e6d9b74621a63b8c fpscr=00000000
+vcvtp.u32.f32 q13, q2 32f1f90af01c868fc7de100cade2b1c1 59a580639d81ee914022446d995e782d ffffffff000000000000000300000000 59a580639d81ee914022446d995e782d fpscr=00000000
+vcvtp.u32.f32 q13, q2 3e11d73d361afc8fb67202bdc7feee16 03b5ac3cd6ee1b7ab36e919f6704c673 000000010000000000000000ffffffff 03b5ac3cd6ee1b7ab36e919f6704c673 fpscr=00000000
+vcvtp.u32.f32 q13, q2 e8bd36d2ac9038aeb17d10aa3d3349e4 bacdae55b8f5f1211f46e679963418cf 00000000000000000000000100000000 bacdae55b8f5f1211f46e679963418cf fpscr=00000000
+vcvtp.u32.f32 q13, q2 346182a53109157a07d7ae1204f8943b 56e4b650b74e4a43f73b7475140dc3c0 ffffffff000000000000000000000001 56e4b650b74e4a43f73b7475140dc3c0 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtp.u32.f32 q13, q2 a490b047cd4d177c3c8a7153b0c49c4b 3d8599afbb723614dd2913849fe51697 00000001000000000000000000000000 3d8599afbb723614dd2913849fe51697 fpscr=00000000
+vcvtp.u32.f32 q13, q2 7a9256b7e7816a2ea8d45fbceea36b20 e9054070fc0017d64611c712b0730bc0 00000000000000000000247200000000 e9054070fc0017d64611c712b0730bc0 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[3]
+vcvtp.u32.f32 q13, q2 09af4b8e84afeb37c6b9c07d09af4b8e e000b24f5c86625b6a7ebe19f54f9cb2 00000000ffffffffffffffff00000000 e000b24f5c86625b6a7ebe19f54f9cb2 fpscr=00000000
+vcvtp.u32.f32 q13, q2 53a1263f997f54261c505ff2a0fed629 d87f71f45f74df98437b8a1e8386fcb2 00000000ffffffff000000fc00000000 d87f71f45f74df98437b8a1e8386fcb2 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vcvtp.u32.f32 q13, q2 0d7d0bfbb46830df162845959964c1d0 09c7a31ea4cf4e709ee5e64c94a7d98b 00000001000000000000000000000000 09c7a31ea4cf4e709ee5e64c94a7d98b fpscr=00000000
+vcvtp.u32.f32 q13, q2 96a63ff3f0a311e39e88848d965ed40a 1ea6f73226b289e6c982fc06e200548e 00000001000000010000000000000000 1ea6f73226b289e6c982fc06e200548e fpscr=00000000
+vcvtp.u32.f32 q13, q2 84e2508456d921362db5728d4beaa370 97e5f204292642126b186c580b384303 0000000000000001ffffffff00000001 97e5f204292642126b186c580b384303 fpscr=00000000
+vcvtp.u32.f32 q13, q2 21d6a8acdba70bdc6c8d2f0522f10fdb 6ec97e7fac4584d9db35269593ee1300 ffffffff000000000000000000000000 6ec97e7fac4584d9db35269593ee1300 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtp.u32.f32 q13, q2 14ddbd641b17d3a3e7039f64b72447bd 2094d068878a9a97ef10457e96b1039b 00000001000000000000000000000000 2094d068878a9a97ef10457e96b1039b fpscr=00000000
+vcvtp.u32.f32 q13, q2 d4ba7b3a040a692a6f3b076565d08657 9b0dccb89d7acc68dd11b476da8ec127 00000000000000000000000000000000 9b0dccb89d7acc68dd11b476da8ec127 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.u32.f32 q13, q2 44816ad5baa6732aaf19cf5bf5afc521 a63b5bd456b3915e8be1d3056688566b 00000000ffffffff00000000ffffffff a63b5bd456b3915e8be1d3056688566b fpscr=00000000
+vcvtp.u32.f32 q13, q2 e39349caaccc4b4c988fba6512ba7934 6028964f00c80495ba8314f9f8c2574a ffffffff000000010000000000000000 6028964f00c80495ba8314f9f8c2574a fpscr=00000000
+vcvtp.u32.f32 q13, q2 1a7c5c5a616f15695c76f43d6c4cf4a3 c2e3064544af2f70cdd642b42bc1d4c2 000000000000057a0000000000000001 c2e3064544af2f70cdd642b42bc1d4c2 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtp.u32.f32 q13, q2 d6fa0f739a6274fb39c549a479b547d3 fab150b1fc49c34231099ab1ce4aedb4 00000000000000000000000100000000 fab150b1fc49c34231099ab1ce4aedb4 fpscr=00000000
+vcvtp.u32.f32 q13, q2 f262026477a5a2e6c00b246972ee4bf5 eda4f18b6b4cbcf6c5ced5b0795c8716 00000000ffffffff00000000ffffffff eda4f18b6b4cbcf6c5ced5b0795c8716 fpscr=00000000
+vcvtp.u32.f32 q13, q2 74a7b56813e9e008db6f05f8b40a96f0 71a88590787094ad611b144ab8e6aef8 ffffffffffffffffffffffff00000000 71a88590787094ad611b144ab8e6aef8 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtp.u32.f32 q13, q2 dbe6004d6af0c88bf3c4c238c115df91 de4cbe518c39e86a4eb423cbbba5618c 00000000000000005a11e58000000000 de4cbe518c39e86a4eb423cbbba5618c fpscr=00000000
+vcvtp.u32.f32 q13, q2 c7d9c8039d9a8bdda92c1ec22dff7452 da18493860fed57fa47d98bfec0fcf4f 00000000ffffffff0000000000000000 da18493860fed57fa47d98bfec0fcf4f fpscr=00000000
+vcvtp.u32.f32 q13, q2 5f5a22827f1c665b5e48d7f3d483707e 11daeb8ae97a1cb6d4b5c1054123f41b 0000000100000000000000000000000b 11daeb8ae97a1cb6d4b5c1054123f41b fpscr=00000000
+vcvtp.u32.f32 q13, q2 21012e573a4f0e13d4e35dc8adf49f89 425f697ddf42b2ae9c724bc7767305bf 000000380000000000000000ffffffff 425f697ddf42b2ae9c724bc7767305bf fpscr=00000000
+vcvtp.u32.f32 q13, q2 c68976dd8b3fb12d878e9b8352de374a 7b6fb78d01835fa008fac0a88553b388 ffffffff000000010000000100000000 7b6fb78d01835fa008fac0a88553b388 fpscr=00000000
+vcvtp.u32.f32 q13, q2 f4bb75dccd26ba2d51d6b02ab5f82a2b 6c1fc940131e50b3b19e070512620ba2 ffffffff000000010000000000000001 6c1fc940131e50b3b19e070512620ba2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtp.u32.f32 q13, q2 e9f6597e945df962c05a54f2e491e934 ac3cd2fecb2947c8ac3cd2fe17165bd4 00000000000000000000000000000001 ac3cd2fecb2947c8ac3cd2fe17165bd4 fpscr=00000000
+vcvtp.u32.f32 q13, q2 375b690e636d4e0a82b4f4538275356c 662f840bfdeeb5d02d4374acb04ea915 ffffffff000000000000000100000000 662f840bfdeeb5d02d4374acb04ea915 fpscr=00000000
+vcvtp.u32.f32 q13, q2 b06b871840de7880948e71a7fe3cf3fc 3273fb22f876ae5c1e61c486bbbfc886 00000001000000000000000100000000 3273fb22f876ae5c1e61c486bbbfc886 fpscr=00000000
+randV128: 16128 calls, 16676 iters
+vcvtp.u32.f32 q13, q2 e52599c6cf50749af7ff24124528322e 47eee4e8dcfc31b057e4ce01f64e2311 0001ddca00000000ffffffff00000000 47eee4e8dcfc31b057e4ce01f64e2311 fpscr=00000000
+vcvtp.u32.f32 q13, q2 9332523d97eec3318bbbba333d1f4b23 b93b930560ed3d0c291bc3d0e35944da 00000000ffffffff0000000100000000 b93b930560ed3d0c291bc3d0e35944da fpscr=00000000
+vcvtp.u32.f32 q13, q2 b570c74d115229f0b480e508c4093a40 112c6db7fd229ea552d0badf7aae1261 0000000100000000ffffffffffffffff 112c6db7fd229ea552d0badf7aae1261 fpscr=00000000
+vcvtp.u32.f32 q13, q2 967d4504d7b3a78ca8e376c41b3ddfab c65ded31028b8d28b01af1f27e75b842 000000000000000100000000ffffffff c65ded31028b8d28b01af1f27e75b842 fpscr=00000000
+vcvtp.u32.f32 q13, q2 bd9914a6b2645a59a16d5c023843191a 139d0ad50ec2bb15590a7b253303edcd 0000000100000001ffffffff00000001 139d0ad50ec2bb15590a7b253303edcd fpscr=00000000
+vcvtp.u32.f32 q13, q2 bef1170188bc3741e428815bf1fcc50f 2c3dfd58df73b5ff10343d447687978d 000000010000000000000001ffffffff 2c3dfd58df73b5ff10343d447687978d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtp.u32.f32 q13, q2 e3424127285eae19b6828a5f0b289a6a d54168bd91afaaa61c255a102f93d39c 00000000000000000000000100000001 d54168bd91afaaa61c255a102f93d39c fpscr=00000000
+vcvtp.u32.f32 q13, q2 eac8bfdeff7efddb2258249373ea264a 5d69556adc2f2c1694fb7daaf8592b91 ffffffff000000000000000000000000 5d69556adc2f2c1694fb7daaf8592b91 fpscr=00000000
+vcvtp.u32.f32 q13, q2 526a99146b3d97bd4b2bb7c20ed891f0 9c1ad127bcc8a0e9b7f9810366fd500e 000000000000000000000000ffffffff 9c1ad127bcc8a0e9b7f9810366fd500e fpscr=00000000
+vcvtp.u32.f32 q13, q2 a36abbf5713c1be874edfdd0611df058 d2d0ff62892516f38e66beec9ec433e6 00000000000000000000000000000000 d2d0ff62892516f38e66beec9ec433e6 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtp.u32.f32 q13, q2 72a3a07dcc2c906496fef837e539cf78 d1473b2c82eeaa5c0f6f64910f6f6491 00000000000000000000000100000001 d1473b2c82eeaa5c0f6f64910f6f6491 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtp.u32.f32 q13, q2 588ed61be309e2f50212e13011825af5 b5732c789bfce57667dc091d08df64dd 0000000000000000ffffffff00000001 b5732c789bfce57667dc091d08df64dd fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[1]
+vcvtp.u32.f32 q13, q2 1261443ecc6ba054c3672a4bbbbc3984 678093a91c1a47fffc20ed40d306472c ffffffff000000010000000000000000 678093a91c1a47fffc20ed40d306472c fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtp.u32.f32 q13, q2 9d8f5d5fa766c6da85daccafa766c6da 7b466df81a3d0024e5f679b938fad963 ffffffff000000010000000000000001 7b466df81a3d0024e5f679b938fad963 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.u32.f32 q13, q2 eeeb907578ab294f8862670d8513e03b 58cae80fb1097ad6f7e4c2f547103c0c ffffffff00000000000000000000903d 58cae80fb1097ad6f7e4c2f547103c0c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtp.u32.f32 q13, q2 cd0ac99d5b9872edc7f05b9ac7f05b9a 16f6a2b1dc0f863c8addf0b43bfc964f 00000001000000000000000000000001 16f6a2b1dc0f863c8addf0b43bfc964f fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtp.u32.f32 q13, q2 0c79335269b99865e6b7e7dd4860f8be 39da442cb683a845fa7329a039da442c 00000001000000000000000000000001 39da442cb683a845fa7329a039da442c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtp.u32.f32 q13, q2 c247e9d3ae6e252feb8fd5c8ae6e252f fa93a8c642e0519ae4c45a8f2edc0c1e 00000000000000710000000000000001 fa93a8c642e0519ae4c45a8f2edc0c1e fpscr=00000000
+vcvtp.u32.f32 q13, q2 60ad9c641a3b03e0ae567044a798d4cc b1eb97ee2dbddfe535cc6f00e5309a7c 00000000000000010000000100000000 b1eb97ee2dbddfe535cc6f00e5309a7c fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vcvtm.u32.f32 q12, q3 6f6a1d6f6f6a1d6f1e6bc27473b98a18 55a60862be34d1bc167872959edbdb4f ffffffff000000000000000000000000 55a60862be34d1bc167872959edbdb4f fpscr=00000000
+vcvtm.u32.f32 q12, q3 0715ca15bf680b1b766569250435178a 0890d56ace987d101a1f22108b3eaa7a 00000000000000000000000000000000 0890d56ace987d101a1f22108b3eaa7a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.u32.f32 q12, q3 a1b2cd2fc9c49c5ed6aa3b1c42fdafbc 505b64ca110f7491d8532077b80d8348 ffffffff000000000000000000000000 505b64ca110f7491d8532077b80d8348 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtm.u32.f32 q12, q3 075336d0f87a5ed3c3d3ff6dc3d3ff6d f0e92c6d035f05a354b6af17f7804ecd 0000000000000000ffffffff00000000 f0e92c6d035f05a354b6af17f7804ecd fpscr=00000000
+vcvtm.u32.f32 q12, q3 d90214df58b42d1ea26ff23e70f3e166 bda97df0412810fd3e13828a8431367e 000000000000000a0000000000000000 bda97df0412810fd3e13828a8431367e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.u32.f32 q12, q3 e215621bc7600265e215621bf6dcc5e6 e53e843bf37374c3483669cc7835a289 00000000000000000002d9a7ffffffff e53e843bf37374c3483669cc7835a289 fpscr=00000000
+vcvtm.u32.f32 q12, q3 99483744740e1e6e8dd5f45c7cb8a948 160dd94f90418b6a2a8b0438af8e6fa9 00000000000000000000000000000000 160dd94f90418b6a2a8b0438af8e6fa9 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtm.u32.f32 q12, q3 9d8fbc0579bec9531b64349d68b6febb bf8165c9703cff81848076c7848076c7 00000000ffffffff0000000000000000 bf8165c9703cff81848076c7848076c7 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vcvtm.u32.f32 q12, q3 1f21dc8fe29c48a6feb55bb637abe187 b4699247e0b0d4fc3e578752b4699247 00000000000000000000000000000000 b4699247e0b0d4fc3e578752b4699247 fpscr=00000000
+vcvtm.u32.f32 q12, q3 9f33d9f9e0df7d6e096eac741ca213bf 0fb27dc4870381762262516bab9b1478 00000000000000000000000000000000 0fb27dc4870381762262516bab9b1478 fpscr=00000000
+vcvtm.u32.f32 q12, q3 45224440115c088ccd06fb3bb0ea5e7f 6eb61115357447cfd1efa23a2acd9927 ffffffff000000000000000000000000 6eb61115357447cfd1efa23a2acd9927 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[3]
+vcvtm.u32.f32 q12, q3 e996443c59491c9807de4cafb9a9f869 2231f716c95c30cfef93a3082231f716 00000000000000000000000000000000 2231f716c95c30cfef93a3082231f716 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.u32.f32 q12, q3 cf34de4334ade839cf34de4333f00824 af92234fe957cf6804e258427e7e3ff0 000000000000000000000000ffffffff af92234fe957cf6804e258427e7e3ff0 fpscr=00000000
+vcvtm.u32.f32 q12, q3 b257084e4c232fbff018ea4a2325bcd3 abf87b88c729338a1ffa9984d2f876ac 00000000000000000000000000000000 abf87b88c729338a1ffa9984d2f876ac fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[2]
+vcvtm.u32.f32 q12, q3 a5bb5bd9cef0e635f1710b4df1710b4d 6c998ce9b34cd78b656a1b3ba952d5a4 ffffffff00000000ffffffff00000000 6c998ce9b34cd78b656a1b3ba952d5a4 fpscr=00000000
+vcvtm.u32.f32 q12, q3 9d74cbb4ee697fc58d108246c8862d02 e048e8d0ad44190e1d21b84d02585bba 00000000000000000000000000000000 e048e8d0ad44190e1d21b84d02585bba fpscr=00000000
+vcvtm.u32.f32 q12, q3 341ca45870e41949de50faf53e7f24ac 1497d436281e0570f2f38c231886a84a 00000000000000000000000000000000 1497d436281e0570f2f38c231886a84a fpscr=00000000
+vcvtm.u32.f32 q12, q3 a8bdc200be7d2a51c4cd05c600e9f439 40cf01990a98f376276e74e63a4d0971 00000006000000000000000000000000 40cf01990a98f376276e74e63a4d0971 fpscr=00000000
+vcvtm.u32.f32 q12, q3 31f0d6726756936fd7db2cc9798f6e8e 0b0ce06594b083032da068ea3e169213 00000000000000000000000000000000 0b0ce06594b083032da068ea3e169213 fpscr=00000000
+vcvtm.u32.f32 q12, q3 f7c1d54c81a13390a3d49e535f988a20 ded9a90374e23b33ec06c0e0de8f9472 00000000ffffffff0000000000000000 ded9a90374e23b33ec06c0e0de8f9472 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.u32.f32 q12, q3 177a189178f4cbfb177a1891a7b11a0e bca0aa625f4d0d538ea81b687be9fad9 00000000ffffffff00000000ffffffff bca0aa625f4d0d538ea81b687be9fad9 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vcvtm.u32.f32 q12, q3 99d6e7491bf5a6a699d6e749968153b5 705ed2b134da2f0467da8150c68b2397 ffffffff00000000ffffffff00000000 705ed2b134da2f0467da8150c68b2397 fpscr=00000000
+vcvtm.u32.f32 q12, q3 e2d82f35a038026ccfd6baf3368dfb54 25f977a46ba4b817947fcbed6f9345a7 00000000ffffffff00000000ffffffff 25f977a46ba4b817947fcbed6f9345a7 fpscr=00000000
+vcvtm.u32.f32 q12, q3 1e7bbb5f3de4b252c107d2f2152b91c0 cf4bffd09351b3bb8aa8275ff72628f6 00000000000000000000000000000000 cf4bffd09351b3bb8aa8275ff72628f6 fpscr=00000000
+vcvtm.u32.f32 q12, q3 2f7542a1a6629c178f43ece932aca423 d11e58332ad956d39ff7fa231ad4a5c0 00000000000000000000000000000000 d11e58332ad956d39ff7fa231ad4a5c0 fpscr=00000000
+vcvtm.u32.f32 q12, q3 89119b07fb9331a98bdcaad637d63ed8 27f59f9406921daa139b771c2b4c2d39 00000000000000000000000000000000 27f59f9406921daa139b771c2b4c2d39 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtm.u32.f32 q12, q3 af2b5f0c2bc8467ce96024262bc8467c c6300ea7fb38bd97e0f32f8e977f49bd 00000000000000000000000000000000 c6300ea7fb38bd97e0f32f8e977f49bd fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtm.u32.f32 q12, q3 48bdcb0a3d97fe3f81d6f52e0b323da3 7b138b977b138b97f801c172077be7ad ffffffffffffffff0000000000000000 7b138b977b138b97f801c172077be7ad fpscr=00000000
+vcvtm.u32.f32 q12, q3 82b8fb0d3dbff1b94028cc7b256c9a66 b8a8ef8e3d0ff4baaf5bc9a75a43a70d 000000000000000000000000ffffffff b8a8ef8e3d0ff4baaf5bc9a75a43a70d fpscr=00000000
+vcvtm.u32.f32 q12, q3 454c07b66fc83bebab60bb7318dbe6c3 8a68bb97b05f565a7117ae4c1d9730fe 0000000000000000ffffffff00000000 8a68bb97b05f565a7117ae4c1d9730fe fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtm.u32.f32 q12, q3 2ae23103e047d05d17971de2d78bd980 b44f351178adbadf3e8914bf95160aa9 00000000ffffffff0000000000000000 b44f351178adbadf3e8914bf95160aa9 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vcvtm.u32.f32 q12, q3 8777e4875e9a509b1cab63a4864ec307 2bc78eaf2bc78eafd6ec5627f4305c30 00000000000000000000000000000000 2bc78eaf2bc78eafd6ec5627f4305c30 fpscr=00000000
+vcvtm.u32.f32 q12, q3 0ce4245f78f0985e5be184baafb8a7da 7cb8000ef6c68b374146188e02e2557a ffffffff000000000000000c00000000 7cb8000ef6c68b374146188e02e2557a fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vcvtm.u32.f32 q12, q3 0a6b325b5285957d65f1834c65f1834c 072a478abf671b1f08d1068bed8fcd6b 00000000000000000000000000000000 072a478abf671b1f08d1068bed8fcd6b fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtm.u32.f32 q12, q3 03fa9141738ce6b4eae2e9f75f8c57c2 f6c6094b7d166afdcbd2e6c27d166afd 00000000ffffffff00000000ffffffff f6c6094b7d166afdcbd2e6c27d166afd fpscr=00000000
+vcvtm.u32.f32 q12, q3 83652426816b722597aa72ce558f815c b3e8e382ab60eb07b3a423386e7bc2d5 000000000000000000000000ffffffff b3e8e382ab60eb07b3a423386e7bc2d5 fpscr=00000000
+vcvtm.u32.f32 q12, q3 e5034f7d407a75f67247bdb05fcb4f3a 7e280c130e1f9904271816dd55b7596f ffffffff0000000000000000ffffffff 7e280c130e1f9904271816dd55b7596f fpscr=00000000
+vcvtm.u32.f32 q12, q3 63809d9a18ee220ada545f1b3362c5fa 656e59855cb9d96e4d2cea581117d826 ffffffffffffffff0acea58000000000 656e59855cb9d96e4d2cea581117d826 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtm.u32.f32 q12, q3 3d8fc3fe87f7a082f7e42c433152c3f6 e5d101bac20b0be0546e09bac20b0be0 0000000000000000ffffffff00000000 e5d101bac20b0be0546e09bac20b0be0 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vcvtm.u32.f32 q12, q3 d5f443e2f5ad6a9e94c6051f59cc6144 ca8eaa7095c8844b3cabcffa452ac525 00000000000000000000000000000aac ca8eaa7095c8844b3cabcffa452ac525 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vcvtm.u32.f32 q12, q3 1968420fc00ea01d0e49ff1f7e627905 c823856863de5e3873933131c8238568 00000000ffffffffffffffff00000000 c823856863de5e3873933131c8238568 fpscr=00000000
+vcvtm.u32.f32 q12, q3 24123a3dd0764ad407921da5fba92ecc 46ed24e66100f6712b22c457cc2a3704 00007692ffffffff0000000000000000 46ed24e66100f6712b22c457cc2a3704 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vcvtm.u32.f32 q12, q3 4457a1a881c171c3c5d16be75aaf1d1e fdbb68b7c8e71c6f722a44a9d0bbd6eb 0000000000000000ffffffff00000000 fdbb68b7c8e71c6f722a44a9d0bbd6eb fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vcvtm.u32.f32 q12, q3 aa55fbfa79b866314b422835a677255b 70bac36b6d68de926d68de92f06f0978 ffffffffffffffffffffffff00000000 70bac36b6d68de926d68de92f06f0978 fpscr=00000000
+vcvtm.u32.f32 q12, q3 4102c686cb95551bc18fe3f56f28e1f0 bd56484dfe6a35aa3f752db41008ed6c 00000000000000000000000000000000 bd56484dfe6a35aa3f752db41008ed6c fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: 16384 calls, 16941 iters
+vcvtm.u32.f32 q12, q3 085a1e7a5e094db32b6c1a1a341dd732 fa59d05967258f62e4f4774baafecef5 00000000ffffffff0000000000000000 fa59d05967258f62e4f4774baafecef5 fpscr=00000000
+vcvtm.u32.f32 q12, q3 4e6f28b6c9363bbc3dd5831769a855ea 5edece48eb5d48deea1ae4323632c835 ffffffff000000000000000000000000 5edece48eb5d48deea1ae4323632c835 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vcvtm.u32.f32 q12, q3 8f932d6bc86c63345fe23915c7ad8d5e 5d2b3ed4faf5f42ef1f27a85b4ddd6fc ffffffff000000000000000000000000 5d2b3ed4faf5f42ef1f27a85b4ddd6fc fpscr=00000000
+vcvtm.u32.f32 q12, q3 af0e051de2b9d9253a631a820e2817d8 66f3d5b154a91f20cc7f417b2c5ca6c1 ffffffffffffffff0000000000000000 66f3d5b154a91f20cc7f417b2c5ca6c1 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vcvtm.u32.f32 q12, q3 33e82905bad8ef994455715dbf2fa391 2c045d5a50eeae2cd8b24a7a79f815d1 00000000ffffffff00000000ffffffff 2c045d5a50eeae2cd8b24a7a79f815d1 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintn.f32.f32 d0, d18 99269f54564d12988a1f09f2fd2a8303 87b725a587b725a54b8936848f62696f 99269f54564d12984b89368480000000 87b725a587b725a54b8936848f62696f fpscr=00000000
+vrintn.f32.f32 d0, d18 29f71457b3e74060deb0d5e06bf75996 7882b53d380704e1f434b2d6e9016555 29f71457b3e74060f434b2d6e9016555 7882b53d380704e1f434b2d6e9016555 fpscr=00000000
+vrintn.f32.f32 d0, d18 69a8bbca8ff74a35add1bd0aa34e774c f02470061c74c0acc481d2fa82c7fd7d 69a8bbca8ff74a35c481e00080000000 f02470061c74c0acc481d2fa82c7fd7d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintn.f32.f32 d0, d18 24436970468713db24b5f23f830f1be1 9aef0fde6433ae114a8b1fc4ca21ccbc 24436970468713db4a8b1fc4ca21ccbc 9aef0fde6433ae114a8b1fc4ca21ccbc fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[2]
+vrintn.f32.f32 d0, d18 469bb931fbf7baffc46c7f46ac23161d 2eec94c06355883857608f5663558838 469bb931fbf7baff57608f5663558838 2eec94c06355883857608f5663558838 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintn.f32.f32 d0, d18 4410908ca9d06cf0b2365b8314962961 03dda891861659aa5846fcbc48775019 4410908ca9d06cf05846fcbc48775000 03dda891861659aa5846fcbc48775019 fpscr=00000000
+vrintn.f32.f32 d0, d18 5076376eff10d948d38c8b3ac55da975 bd10e10ccfa116088275892b24dde209 5076376eff10d9488000000000000000 bd10e10ccfa116088275892b24dde209 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintn.f32.f32 d0, d18 da6e9476db1470abe8b06ac0b3d1555d 19fa0bd919fa0bd9f5a8eb26384923d6 da6e9476db1470abf5a8eb2600000000 19fa0bd919fa0bd9f5a8eb26384923d6 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintn.f32.f32 d0, d18 0160f9d3091fbe57bdfe46aea7371bc2 b6a9d89426d7aca9aaff9d3417fdf32f 0160f9d3091fbe578000000000000000 b6a9d89426d7aca9aaff9d3417fdf32f fpscr=00000000
+vrintn.f32.f32 d0, d18 0f9578796f1b0c54de33165d4352e772 c86d995391e31a189f5eb2befd04fe12 0f9578796f1b0c5480000000fd04fe12 c86d995391e31a189f5eb2befd04fe12 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintn.f32.f32 d0, d18 75e122996874cb7df8da29a83738cfbd 2044ad2b7e32db29d8cd09f17e32db29 75e122996874cb7dd8cd09f17e32db29 2044ad2b7e32db29d8cd09f17e32db29 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintn.f32.f32 d0, d18 163ac4e60eaa5677e58938d676c4b479 b62da0e45979c41cf99c3a06905200b8 163ac4e60eaa5677f99c3a0680000000 b62da0e45979c41cf99c3a06905200b8 fpscr=00000000
+vrintn.f32.f32 d0, d18 7c4418cb0b0d98b54b26388a1c43a356 c567ffe5cdaa304c866138ab07132e9e 7c4418cb0b0d98b58000000000000000 c567ffe5cdaa304c866138ab07132e9e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintn.f32.f32 d0, d18 6a5ef00d45f4b32a9d58ce116b24fdbc ef0f3713ef0f3713f7b1afd9b4076b44 6a5ef00d45f4b32af7b1afd980000000 ef0f3713ef0f3713f7b1afd9b4076b44 fpscr=00000000
+vrintn.f32.f32 d0, d18 2fc254b0d8e5c84a4f1059694db79ad4 c11d3a8f1350f18cd599a6384cb8a7dd 2fc254b0d8e5c84ad599a6384cb8a7dd c11d3a8f1350f18cd599a6384cb8a7dd fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vrintn.f32.f32 d0, d18 b33d0c622f112766461b0f519b279604 ddec642bf7a180e6c2db4ac3c2db4ac3 b33d0c622f112766c2dc0000c2dc0000 ddec642bf7a180e6c2db4ac3c2db4ac3 fpscr=00000000
+vrintn.f32.f32 d0, d18 a37bf3c3e2399090e61a1f57b7005fed 5d4004b6c1a312ab6437e94a4da63edb a37bf3c3e23990906437e94a4da63edb 5d4004b6c1a312ab6437e94a4da63edb fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintn.f32.f32 d0, d18 0cd44e9379acc6378ed57e7e2f9df633 471a9adffc370119f99a17b2c8d2338b 0cd44e9379acc637f99a17b2c8d23380 471a9adffc370119f99a17b2c8d2338b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintn.f32.f32 d0, d18 a50eef221b1221cf19a70a3726ea8c3f 8bd0af64df518022f879c02ff879c02f a50eef221b1221cff879c02ff879c02f 8bd0af64df518022f879c02ff879c02f fpscr=00000000
+vrintn.f32.f32 d0, d18 85515db15b17273ab4a5fbd9c26724bb af7fbbb9e2f6a63097edde5ad2d56499 85515db15b17273a80000000d2d56499 af7fbbb9e2f6a63097edde5ad2d56499 fpscr=00000000
+vrintn.f32.f32 d0, d18 27d5e05fa561a60d20dee22b3f6e5336 baa9792e043011f7d2eabcbbd05f77b5 27d5e05fa561a60dd2eabcbbd05f77b5 baa9792e043011f7d2eabcbbd05f77b5 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintn.f32.f32 d0, d18 8559d5f5cddee8eccddee8ec28f5c131 245c321cc41b950b442f21c10c47bc79 8559d5f5cddee8ec442f400000000000 245c321cc41b950b442f21c10c47bc79 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintn.f32.f32 d0, d18 088202df6449bf661be5b6da5c2c5da9 97641ba297641ba2ded9c8551257e793 088202df6449bf66ded9c85500000000 97641ba297641ba2ded9c8551257e793 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintn.f32.f32 d0, d18 e4c4073605759b02e6ac42486e7ce694 29592e63f01cb56729592e63c8753a35 e4c4073605759b0200000000c8753a40 29592e63f01cb56729592e63c8753a35 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintn.f32.f32 d0, d18 0f1bf4b78db21a3a9eee77a25e1e8422 28b3ddf51ae2fa4f28b3ddf59786d1c6 0f1bf4b78db21a3a0000000080000000 28b3ddf51ae2fa4f28b3ddf59786d1c6 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintn.f32.f32 d0, d18 07d74fb17c6e71f37f3743297c6e71f3 1745e444618513f3c350767e36c59d1f 07d74fb17c6e71f3c350000000000000 1745e444618513f3c350767e36c59d1f fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintn.f32.f32 d0, d18 9f3a31c9b810515ab1542163b1542163 e2c50be2092ae4b6851f5882933dc3d6 9f3a31c9b810515a8000000080000000 e2c50be2092ae4b6851f5882933dc3d6 fpscr=00000000
+vrintn.f32.f32 d0, d18 c4c93b93c2882c141ed17887e9be5fa9 2850ce7fd51dd0392118bcf99a70a0f7 c4c93b93c2882c140000000080000000 2850ce7fd51dd0392118bcf99a70a0f7 fpscr=00000000
+vrintn.f32.f32 d0, d18 969b03c27c05811bab05a43fa0425553 552fc0b13d3b3a0d4bb7e6b34ee3a6ea 969b03c27c05811b4bb7e6b34ee3a6ea 552fc0b13d3b3a0d4bb7e6b34ee3a6ea fpscr=00000000
+vrintn.f32.f32 d0, d18 ea82e937f42b077ec556088edefa0766 2e6fad8abc31c8b2038ff4f324f42cb0 ea82e937f42b077e0000000000000000 2e6fad8abc31c8b2038ff4f324f42cb0 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintn.f32.f32 d0, d18 338191668e305480e72e62d4fd9e31cc 4db8338815409300e221fba259aadc94 338191668e305480e221fba259aadc94 4db8338815409300e221fba259aadc94 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintn.f32.f32 d0, d18 5f3ae121efd24d7ed4c7b5112e908df0 ed3076e06d17e06fbfa9689ca9e6625b 5f3ae121efd24d7ebf80000080000000 ed3076e06d17e06fbfa9689ca9e6625b fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintn.f32.f32 d0, d18 ebc9c1fbfcea4c65d03abbb680bf38dc fa3c5f9977169b202f7a356de2cfacb5 ebc9c1fbfcea4c6500000000e2cfacb5 fa3c5f9977169b202f7a356de2cfacb5 fpscr=00000000
+vrintn.f32.f32 d0, d18 83ea21f43a48d6562f3e428c475cce83 7070f302a1dc2bec437468f520756cbb 83ea21f43a48d6564374000000000000 7070f302a1dc2bec437468f520756cbb fpscr=00000000
+vrintn.f32.f32 d0, d18 920c031fb9d8c3779ab4bc30930b8e6e 0cbd16394755fd081eaa5c306b1b1af1 920c031fb9d8c377000000006b1b1af1 0cbd16394755fd081eaa5c306b1b1af1 fpscr=00000000
+vrintn.f32.f32 d0, d18 ee6e6a2fd4f1b301708b18153548fd38 a2536b3bcfe01fc2fe9306d82d0a6d67 ee6e6a2fd4f1b301fe9306d800000000 a2536b3bcfe01fc2fe9306d82d0a6d67 fpscr=00000000
+vrintn.f32.f32 d0, d18 5c3ef20b4e44c1799df92aac07e57eae 2eec7a3d30dee43882e103aa778aecd1 5c3ef20b4e44c17980000000778aecd1 2eec7a3d30dee43882e103aa778aecd1 fpscr=00000000
+vrintn.f32.f32 d0, d18 9890538501ae30429b7c55194c05c801 00916c29439c05c79b2cf88a0321a351 9890538501ae30428000000000000000 00916c29439c05c79b2cf88a0321a351 fpscr=00000000
+vrintn.f32.f32 d0, d18 00df182b1fd1bf8d589f813e33f686f1 e7c509d1151db9de0357c9fcc49f8592 00df182b1fd1bf8d00000000c49f8000 e7c509d1151db9de0357c9fcc49f8592 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintn.f32.f32 d0, d18 430a92891538b336845abbf44e7ca43d bf9cf128c4de38e8ee5e4d462932acc1 430a92891538b336ee5e4d4600000000 bf9cf128c4de38e8ee5e4d462932acc1 fpscr=00000000
+vrintn.f32.f32 d0, d18 41fd9ffc9e040510833ab5f726bee7ae bf470a3b964c2faa8e88af8a8189dd4b 41fd9ffc9e0405108000000080000000 bf470a3b964c2faa8e88af8a8189dd4b fpscr=00000000
+vrintn.f32.f32 d0, d18 581d4e2bfa9a4dd6512f46d109d5ac50 492867ec1c6f830c2a2ddf095e12f0f1 581d4e2bfa9a4dd6000000005e12f0f1 492867ec1c6f830c2a2ddf095e12f0f1 fpscr=00000000
+vrintn.f32.f32 d0, d18 c9d3d6fe4ea0b9d434fdaccb3e81e3bf 3d1f0c7904beceef5bf0fba751a06f5b c9d3d6fe4ea0b9d45bf0fba751a06f5b 3d1f0c7904beceef5bf0fba751a06f5b fpscr=00000000
+vrintn.f32.f32 d0, d18 05be014b0c39977eca48eb464e051dbb 8692f24b334cd4a1ad3312525a29506b 05be014b0c39977e800000005a29506b 8692f24b334cd4a1ad3312525a29506b fpscr=00000000
+vrintn.f32.f32 d0, d18 7b63b8d6bdae5a293b0096562cf34461 643cb3797215bdaf053d371f26e61174 7b63b8d6bdae5a290000000000000000 643cb3797215bdaf053d371f26e61174 fpscr=00000000
+vrintn.f32.f32 d0, d18 37acb61c4514eff5271dc6ccb7083364 96518506c1cc2fb909a3bfc094531352 37acb61c4514eff50000000080000000 96518506c1cc2fb909a3bfc094531352 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintn.f32.f32 d0, d18 ed499a0387c3779ee7427027a4eca614 6c021b767bf84ea6760b605a2b9bd9db ed499a0387c3779e760b605a00000000 6c021b767bf84ea6760b605a2b9bd9db fpscr=00000000
+vrintn.f32.f32 d0, d18 bdb85eec62696cb9572835361761c2cf decbb06361c06f809d4047542bbd645b bdb85eec62696cb98000000000000000 decbb06361c06f809d4047542bbd645b fpscr=00000000
+vrintn.f32.f32 d0, d18 ac6b1b64418f4bd6b56e2f43ea9ca1e5 783c79b61ca7c592b424c71b70f7d9c7 ac6b1b64418f4bd68000000070f7d9c7 783c79b61ca7c592b424c71b70f7d9c7 fpscr=00000000
+vrintn.f32.f32 d0, d18 fc13b0a1d26bacf74791c27733b196c7 ed28d80b656fd2e2e71c7da3774c5333 fc13b0a1d26bacf7e71c7da3774c5333 ed28d80b656fd2e2e71c7da3774c5333 fpscr=00000000
+vrinta.f32.f32 d3, d21 97f5278caed370f98f446dbf2e9f24b1 cd5361470bf5c557bdd1fc16208ab8f6 cd536147000000008f446dbf2e9f24b1 cd5361470bf5c557bdd1fc16208ab8f6 fpscr=00000000
+vrinta.f32.f32 d3, d21 5256eccc658c57966dfa66e544d6be9e db01a190cf21300e54e6913262c3d7b2 db01a190cf21300e6dfa66e544d6be9e db01a190cf21300e54e6913262c3d7b2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[2]
+vrinta.f32.f32 d3, d21 5293379083ce77168f94e39352933790 17ecfd94fd76fa13fd76fa13c887ae5b 00000000fd76fa138f94e39352933790 17ecfd94fd76fa13fd76fa13c887ae5b fpscr=00000000
+vrinta.f32.f32 d3, d21 18c05207522f5c9edccbc9e7684f686b cf82405b73a5cd121cbc994fe2eea0d5 cf82405b73a5cd12dccbc9e7684f686b cf82405b73a5cd121cbc994fe2eea0d5 fpscr=00000000
+vrinta.f32.f32 d3, d21 40d528730624e858b43f7e5dc5e7eab8 6aa3acb84e6f2a9a3541f7f3ac701cde 6aa3acb84e6f2a9ab43f7e5dc5e7eab8 6aa3acb84e6f2a9a3541f7f3ac701cde fpscr=00000000
+vrinta.f32.f32 d3, d21 136684cd6a23ebdf15d2a881e1ace436 d2ef3befa9011bfe7a96d65b874076f1 d2ef3bef8000000015d2a881e1ace436 d2ef3befa9011bfe7a96d65b874076f1 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrinta.f32.f32 d3, d21 02296ca30256a191cb6a7ea0a6acf262 dd35775f752f7bed752f7bed355625ff dd35775f752f7bedcb6a7ea0a6acf262 dd35775f752f7bed752f7bed355625ff fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrinta.f32.f32 d3, d21 e45d0ff7e65be8f2c3c99fcd9308c38a 2225ae64fc47b64340346419043fac8c 00000000fc47b643c3c99fcd9308c38a 2225ae64fc47b64340346419043fac8c fpscr=00000000
+vrinta.f32.f32 d3, d21 b5470d30798e44d3222c6e9c52b056e1 6e22f7b3b7c5cb859b5c756f766cf61d 6e22f7b380000000222c6e9c52b056e1 6e22f7b3b7c5cb859b5c756f766cf61d fpscr=00000000
+randV128: 16640 calls, 17205 iters
+vrinta.f32.f32 d3, d21 10787b9dd749c9df55016c77eea3f9ee 02d89106959474c2841cfd86ed25a8f2 000000008000000055016c77eea3f9ee 02d89106959474c2841cfd86ed25a8f2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrinta.f32.f32 d3, d21 20762f2f90a8ada8dfead39a80e5bc28 de040777d0ee27f4de040777155a9887 de040777d0ee27f4dfead39a80e5bc28 de040777d0ee27f4de040777155a9887 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrinta.f32.f32 d3, d21 334ae07be943acbf86e74c64137d2c09 5f3833c80862772da145ddd742ee28d1 5f3833c80000000086e74c64137d2c09 5f3833c80862772da145ddd742ee28d1 fpscr=00000000
+vrinta.f32.f32 d3, d21 2c0af4c155555cf354030d880b072a63 ce9c24e621b1a173c18aa09dfa5b1ff6 ce9c24e60000000054030d880b072a63 ce9c24e621b1a173c18aa09dfa5b1ff6 fpscr=00000000
+vrinta.f32.f32 d3, d21 a269c25d7eba441a325ec39151fb2812 c75c10fae785f4139138bd4960512979 c75c1100e785f413325ec39151fb2812 c75c10fae785f4139138bd4960512979 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrinta.f32.f32 d3, d21 95fcbf941f94cb11ecee6d241227777e e52bdfe0044063b4360b316b970b5739 e52bdfe000000000ecee6d241227777e e52bdfe0044063b4360b316b970b5739 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[0]
+vrinta.f32.f32 d3, d21 29ee8ab3acf81b827de830ac596b5c5b 9dd87ce1cf58785010b3799101c4ecdd 80000000cf5878507de830ac596b5c5b 9dd87ce1cf58785010b3799101c4ecdd fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrinta.f32.f32 d3, d21 55008da055008da04046aa907f2569a5 27f529348e4950f486cab5126760596c 00000000800000004046aa907f2569a5 27f529348e4950f486cab5126760596c fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrinta.f32.f32 d3, d21 1e9c13884ac7b683b069841616d357b2 87393b2e6a05f737c5f0069dc5f0069d 800000006a05f737b069841616d357b2 87393b2e6a05f737c5f0069dc5f0069d fpscr=00000000
+vrinta.f32.f32 d3, d21 eebb2ace600972a024c319df94ea0da8 f1d392f6be8a0b95be46cfc6c9af2134 f1d392f68000000024c319df94ea0da8 f1d392f6be8a0b95be46cfc6c9af2134 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrinta.f32.f32 d3, d21 7ce53451a6c7586e3cd23cc58129c0c3 df85d4af9307bbf41307d79f7b20b716 df85d4af800000003cd23cc58129c0c3 df85d4af9307bbf41307d79f7b20b716 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrinta.f32.f32 d3, d21 754c38d19d81d5f77e26661704495945 434f34726dd254199b5ab17d9b5ab17d 434f00006dd254197e26661704495945 434f34726dd254199b5ab17d9b5ab17d fpscr=00000000
+vrinta.f32.f32 d3, d21 7d69acd7738ab4c93e209d8de5139442 f1b962c56d3361dd5b370a1e2770aba5 f1b962c56d3361dd3e209d8de5139442 f1b962c56d3361dd5b370a1e2770aba5 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrinta.f32.f32 d3, d21 ae8a2985325bdd8ab46ca4ae92c9003b 9e5c71f7adbc0d789b5aa714c1811844 8000000080000000b46ca4ae92c9003b 9e5c71f7adbc0d789b5aa714c1811844 fpscr=00000000
+vrinta.f32.f32 d3, d21 d4c832f8251eb5e57a28f2d3cd2d213e 9f12cccc20c754c84a36b50155631065 80000000000000007a28f2d3cd2d213e 9f12cccc20c754c84a36b50155631065 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrinta.f32.f32 d3, d21 642b3427fdcf2809a201631b77a09b31 b47521214cb07bb7cc551c93961a6968 800000004cb07bb7a201631b77a09b31 b47521214cb07bb7cc551c93961a6968 fpscr=00000000
+vrinta.f32.f32 d3, d21 9eb58329d13e5d4ca7236f3744ab99ff 156db91244191d769b10d88f61ff21d6 0000000044190000a7236f3744ab99ff 156db91244191d769b10d88f61ff21d6 fpscr=00000000
+vrinta.f32.f32 d3, d21 86802a65c90750561b9f2cd49ec6095f e91fa1ec4e5377b493df5cc5d33ba48f e91fa1ec4e5377b41b9f2cd49ec6095f e91fa1ec4e5377b493df5cc5d33ba48f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrinta.f32.f32 d3, d21 810f8f582a4931a4f4ed634f271db222 0132c6b8866ed24a11f16192879fd044 0000000080000000f4ed634f271db222 0132c6b8866ed24a11f16192879fd044 fpscr=00000000
+vrinta.f32.f32 d3, d21 8e7e39dad2ffc4797128ccdaca76ffc7 ed39264f830c8d066fad53f3e5b4bf27 ed39264f800000007128ccdaca76ffc7 ed39264f830c8d066fad53f3e5b4bf27 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrinta.f32.f32 d3, d21 08b7d43786db8cd94eb2e24314b04c95 a0fe86dd276ce394ee0f4f6e105bb08d 80000000000000004eb2e24314b04c95 a0fe86dd276ce394ee0f4f6e105bb08d fpscr=00000000
+vrinta.f32.f32 d3, d21 4b08a1fe1e30275adae35bfb7a2d9aa4 c3b6778bf8964e3aca2b45733babc759 c3b68000f8964e3adae35bfb7a2d9aa4 c3b6778bf8964e3aca2b45733babc759 fpscr=00000000
+vrinta.f32.f32 d3, d21 746dcaf67bb7619c8427f106173aed40 3ec85e28a60e93849215149a706aa630 00000000800000008427f106173aed40 3ec85e28a60e93849215149a706aa630 fpscr=00000000
+vrinta.f32.f32 d3, d21 78aa8141cf40429cdf7e79eba07f451e 9f6670250d0aacad38525fcdb38254fc 8000000000000000df7e79eba07f451e 9f6670250d0aacad38525fcdb38254fc fpscr=00000000
+vrinta.f32.f32 d3, d21 bc6d426436b247af9ba1a0f757bcca4a ad49cd436ac3d80371f69f90d8623a48 800000006ac3d8039ba1a0f757bcca4a ad49cd436ac3d80371f69f90d8623a48 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrinta.f32.f32 d3, d21 1e84d310a5c04a72841d6239baefc669 79dacc097900bd270f683b2ec96c97b3 79dacc097900bd27841d6239baefc669 79dacc097900bd270f683b2ec96c97b3 fpscr=00000000
+vrinta.f32.f32 d3, d21 86764cf5f4c3659e4f0a1bacf562424c cb83df0b94eda017985cc57d5e25ee35 cb83df0b800000004f0a1bacf562424c cb83df0b94eda017985cc57d5e25ee35 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[3]
+vrinta.f32.f32 d3, d21 34cf19e7ebd7761934cf19e79c0dff91 e0803f61741a126774cad7b84e792c78 e0803f61741a126734cf19e79c0dff91 e0803f61741a126774cad7b84e792c78 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrinta.f32.f32 d3, d21 dae2dee83d5d4835f4dcc6083d4cc961 e6eea1917812553a3490a66261db159c e6eea1917812553af4dcc6083d4cc961 e6eea1917812553a3490a66261db159c fpscr=00000000
+vrinta.f32.f32 d3, d21 e2de0e0e843f06fdfccf235d20784880 7e79182882b5be7fc913c7fc5cdbca12 7e79182880000000fccf235d20784880 7e79182882b5be7fc913c7fc5cdbca12 fpscr=00000000
+vrinta.f32.f32 d3, d21 2c15f572cc724ba4f04f507dfe20c609 79ee5a65777525c8fac9273ef8eb4afe 79ee5a65777525c8f04f507dfe20c609 79ee5a65777525c8fac9273ef8eb4afe fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrinta.f32.f32 d3, d21 7ae177538ef69a097ae177534199106c 3a7a03df8c3cfbbb84c95493e26be79a 00000000800000007ae177534199106c 3a7a03df8c3cfbbb84c95493e26be79a fpscr=00000000
+vrinta.f32.f32 d3, d21 71298730c3ea1e6cc804614d60eb6062 abad57e87f1d9de027818dd05b66f333 800000007f1d9de0c804614d60eb6062 abad57e87f1d9de027818dd05b66f333 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrinta.f32.f32 d3, d21 9d35b6ec3aa0f090496e3aca50ae03fa 365ae32037c796b72d2655b04d96108e 0000000000000000496e3aca50ae03fa 365ae32037c796b72d2655b04d96108e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrinta.f32.f32 d3, d21 afe0da645494cefa7cf9272b5494cefa 0616c6a38fd69ae0081834edca9be23b 00000000800000007cf9272b5494cefa 0616c6a38fd69ae0081834edca9be23b fpscr=00000000
+vrinta.f32.f32 d3, d21 8c1bd449e8a23bbeae6982b55822e335 cb1f9e3eb6021eea944c26cf5f475fb4 cb1f9e3e80000000ae6982b55822e335 cb1f9e3eb6021eea944c26cf5f475fb4 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrinta.f32.f32 d3, d21 4846d58970ff790361f7b6c870ff7903 64aad6ee02e0f171b449d2efa88cae78 64aad6ee0000000061f7b6c870ff7903 64aad6ee02e0f171b449d2efa88cae78 fpscr=00000000
+vrinta.f32.f32 d3, d21 1254ac282fb9f0207ac7b1753ed3c18b 74a396d014c809653aedc473fce5ab4c 74a396d0000000007ac7b1753ed3c18b 74a396d014c809653aedc473fce5ab4c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrinta.f32.f32 d3, d21 5608b5d1f6f1e6785b80e0493dc3a8e8 3a56dde30d8d7ca320c57d15cfa48ae7 00000000000000005b80e0493dc3a8e8 3a56dde30d8d7ca320c57d15cfa48ae7 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrinta.f32.f32 d3, d21 5da364225da364228bc99866874c2f6f 0d960dc098447e4ddda5b41bc04db034 00000000800000008bc99866874c2f6f 0d960dc098447e4ddda5b41bc04db034 fpscr=00000000
+vrinta.f32.f32 d3, d21 4214e4cbdea89d948d6ea6d430d22e82 8d5f01ba8a59fe66731761893820c7f7 80000000800000008d6ea6d430d22e82 8d5f01ba8a59fe66731761893820c7f7 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintp.f32.f32 d6, d24 b2a06289b84f289c279fa564b2a06289 509c9eaea3d83057baad8b909e57f4e7 b2a06289b84f289c8000000080000000 509c9eaea3d83057baad8b909e57f4e7 fpscr=00000000
+vrintp.f32.f32 d6, d24 894759efb28323bee7317340c7a9a65c 5dee2ef1db4142fe8b09469ff9041b8a 894759efb28323be80000000f9041b8a 5dee2ef1db4142fe8b09469ff9041b8a fpscr=00000000
+vrintp.f32.f32 d6, d24 f8e1cac941236c5bbdc098c0ad1da33b 63adf853f00887d304d01900f24d2132 f8e1cac941236c5b3f800000f24d2132 63adf853f00887d304d01900f24d2132 fpscr=00000000
+vrintp.f32.f32 d6, d24 05a0721deabfb114e168800dfa99c76b 74678a942141408c510986e7f767e9f5 05a0721deabfb114510986e7f767e9f5 74678a942141408c510986e7f767e9f5 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintp.f32.f32 d6, d24 a6a43a4d6f903b9df96343806a193d81 46dd750eb82263cfb83a621046dd750e a6a43a4d6f903b9d8000000046dd7600 46dd750eb82263cfb83a621046dd750e fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintp.f32.f32 d6, d24 5a51a63c4d385a80c9d251ba7978fb4e 31989c2131989c21bc6d7f6da05f6b86 5a51a63c4d385a808000000080000000 31989c2131989c21bc6d7f6da05f6b86 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintp.f32.f32 d6, d24 7489dd28289f249a03ce4cd2433a85e0 51115b874a23e95e8358903f4a23e95e 7489dd28289f249a800000004a23e960 51115b874a23e95e8358903f4a23e95e fpscr=00000000
+vrintp.f32.f32 d6, d24 e43756489c28254fd01333c2fea692d8 9c0914a5b18506402f85bd3474784def e43756489c28254f3f80000074784def 9c0914a5b18506402f85bd3474784def fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintp.f32.f32 d6, d24 26a06d6868a9f211afdd246f26a06d68 be0c1243cb2517b45ed0c2e79d9ffbf6 26a06d6868a9f2115ed0c2e780000000 be0c1243cb2517b45ed0c2e79d9ffbf6 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintp.f32.f32 d6, d24 4291118af3f2ef3b527e7acdf3f2ef3b e1298589e2753e71d17e18fa27292aa7 4291118af3f2ef3bd17e18fa3f800000 e1298589e2753e71d17e18fa27292aa7 fpscr=00000000
+vrintp.f32.f32 d6, d24 6ffdceb1f61ae14ff76c4e2873d22374 6952678a362650ee3de352b2cf94bbfb 6ffdceb1f61ae14f3f800000cf94bbfb 6952678a362650ee3de352b2cf94bbfb fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintp.f32.f32 d6, d24 0808efe9f5a37ae02ad4edf02ad4edf0 b83fecb1ad66979ba1d16f5d90c2f6ad 0808efe9f5a37ae08000000080000000 b83fecb1ad66979ba1d16f5d90c2f6ad fpscr=00000000
+vrintp.f32.f32 d6, d24 e56db278d7d3b95eb5559b7d8a7c3f4b 4ca7ce37bac5c79514cceebca776edae e56db278d7d3b95e3f80000080000000 4ca7ce37bac5c79514cceebca776edae fpscr=00000000
+vrintp.f32.f32 d6, d24 16ba93f1944f83f3f34473cffd5ed195 0c3e150ca2c9c707d58da3a781824544 16ba93f1944f83f3d58da3a780000000 0c3e150ca2c9c707d58da3a781824544 fpscr=00000000
+vrintp.f32.f32 d6, d24 113ec20add2416f90898e3df05c20cb7 8f0158bb480dfed99a8be23f31a4e24f 113ec20add2416f9800000003f800000 8f0158bb480dfed99a8be23f31a4e24f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintp.f32.f32 d6, d24 858a30b5758ef3ca962504fb978dde44 a7e80f3c7f6a938dbef2653da7e80f3c 858a30b5758ef3ca8000000080000000 a7e80f3c7f6a938dbef2653da7e80f3c fpscr=00000000
+vrintp.f32.f32 d6, d24 660187da71384ab89ace40b0dee416a2 ccbf8567b4d30af14c92e770b892e658 660187da71384ab84c92e77080000000 ccbf8567b4d30af14c92e770b892e658 fpscr=00000000
+vrintp.f32.f32 d6, d24 aa211dcd330747a1bc85d3ce6de85003 3d57783876f17db3aa2fd7bedb5a27f5 aa211dcd330747a180000000db5a27f5 3d57783876f17db3aa2fd7bedb5a27f5 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintp.f32.f32 d6, d24 63a0d83eb5ce228e861a0ac7fed8002c d3a890350d4a78c08ba05a3916fa03e7 63a0d83eb5ce228e800000003f800000 d3a890350d4a78c08ba05a3916fa03e7 fpscr=00000000
+vrintp.f32.f32 d6, d24 d95714ee4cf78db1f85f934d47833e99 afbb7fabe3c110756f480088a3206bab d95714ee4cf78db16f48008880000000 afbb7fabe3c110756f480088a3206bab fpscr=00000000
+vrintp.f32.f32 d6, d24 3777f44073cd5cf7cd45b8bb36e924ff f9446488a456b20acb9b843b1db173f0 3777f44073cd5cf7cb9b843b3f800000 f9446488a456b20acb9b843b1db173f0 fpscr=00000000
+vrintp.f32.f32 d6, d24 50c863f8e70e5a0ae6d8b47e4991c41d 5d9630860a4dbdb0760492f0882a8fda 50c863f8e70e5a0a760492f080000000 5d9630860a4dbdb0760492f0882a8fda fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintp.f32.f32 d6, d24 4c92326c045fc1e20f91bc3814d9fae3 7706d5d59773e60abe8699cc9773e60a 4c92326c045fc1e28000000080000000 7706d5d59773e60abe8699cc9773e60a fpscr=00000000
+randV128: 16896 calls, 17470 iters
+vrintp.f32.f32 d6, d24 be2f14dad207e2ec22cbaf97ea778e5e e0647b5f993ebe8c83879a7e55d074ce be2f14dad207e2ec8000000055d074ce e0647b5f993ebe8c83879a7e55d074ce fpscr=00000000
+vrintp.f32.f32 d6, d24 ba8c065c64d636028d88ccfd8c7c2fd0 8b5e971c93b2e8b1a30e541e82a9c597 ba8c065c64d636028000000080000000 8b5e971c93b2e8b1a30e541e82a9c597 fpscr=00000000
+vrintp.f32.f32 d6, d24 1d799ddfa6670f039fd9eb584e5fea26 21a7bc8a7ab6d98b818e89cdf35c989c 1d799ddfa6670f0380000000f35c989c 21a7bc8a7ab6d98b818e89cdf35c989c fpscr=00000000
+vrintp.f32.f32 d6, d24 0aeae6ecc11572bb7664c7ac4f99123a 5f18c6c3e1b27a755b6996630bd6bf93 0aeae6ecc11572bb5b6996633f800000 5f18c6c3e1b27a755b6996630bd6bf93 fpscr=00000000
+vrintp.f32.f32 d6, d24 6be9e3e3f6aadc1976f9f4cf08e30fba 04cdfb8bca1ff976a9c757468d572d81 6be9e3e3f6aadc198000000080000000 04cdfb8bca1ff976a9c757468d572d81 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintp.f32.f32 d6, d24 60fec8702d689d4301395d151d86047d 2c0bf912d7c4b5ddb2bd536ed7c4b5dd 60fec8702d689d4380000000d7c4b5dd 2c0bf912d7c4b5ddb2bd536ed7c4b5dd fpscr=00000000
+vrintp.f32.f32 d6, d24 89cd8af31965646a170cfc9ba0680bf7 55500514f79174b8435684623d3b78d2 89cd8af31965646a435700003f800000 55500514f79174b8435684623d3b78d2 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintp.f32.f32 d6, d24 b67b3df9a9ebfa72dccb42d1dccb42d1 67045bbae4d26cc3eb086dd845b8de3a b67b3df9a9ebfa72eb086dd845b8e000 67045bbae4d26cc3eb086dd845b8de3a fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintp.f32.f32 d6, d24 eb2d9dd18b30731beb2d9dd1f2910402 4a45cb6481dcbb68154b1b8d21d2f17d eb2d9dd18b30731b3f8000003f800000 4a45cb6481dcbb68154b1b8d21d2f17d fpscr=00000000
+vrintp.f32.f32 d6, d24 5d7653211f04318d60f5a7fc52b999b8 3e26b6e0aeaaf09a5eea1b68533567d8 5d7653211f04318d5eea1b68533567d8 3e26b6e0aeaaf09a5eea1b68533567d8 fpscr=00000000
+vrintp.f32.f32 d6, d24 592990e644da6a20e0b26a6063ec47d5 134933b4ff77922222a5d73b04f0e6e4 592990e644da6a203f8000003f800000 134933b4ff77922222a5d73b04f0e6e4 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintp.f32.f32 d6, d24 ce7cbedd97bf98b7677ea2b7de697606 358a1d6b358a1d6bd6bb447e0616df26 ce7cbedd97bf98b7d6bb447e3f800000 358a1d6b358a1d6bd6bb447e0616df26 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[2]
+vrintp.f32.f32 d6, d24 d1badd693c30643ed5e8cf8ccfa6a6c1 9f96e484b6d66fb1667c6ec09a4d8d39 d1badd693c30643e667c6ec080000000 9f96e484b6d66fb1667c6ec09a4d8d39 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintp.f32.f32 d6, d24 4aa46f8a7a3247c62f177087fc72527c a2bdce3b7e2aac7a1270b8a10128e415 4aa46f8a7a3247c63f8000003f800000 a2bdce3b7e2aac7a1270b8a10128e415 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintp.f32.f32 d6, d24 91d5f8637bf4ce4140354846a411f14d b2d23e9d9a3b8bc2c217c420eceaa1a0 91d5f8637bf4ce41c2140000eceaa1a0 b2d23e9d9a3b8bc2c217c420eceaa1a0 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintp.f32.f32 d6, d24 c04d728b14256f4e82e1da5582e1da55 770927f64db49a0b499cb6360619b8b8 c04d728b14256f4e499cb6383f800000 770927f64db49a0b499cb6360619b8b8 fpscr=00000000
+vrintp.f32.f32 d6, d24 67420418f0590d785ffc567aaf832340 c935340e914047aefd585ba89db6f0bc 67420418f0590d78fd585ba880000000 c935340e914047aefd585ba89db6f0bc fpscr=00000000
+vrintp.f32.f32 d6, d24 78efffe88501de85727bc61aa4a87ecc 8f2907b32d22d6f531d309521ac99bb2 78efffe88501de853f8000003f800000 8f2907b32d22d6f531d309521ac99bb2 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintp.f32.f32 d6, d24 661960b16f1c618643c0b0115d51b0bc b35f4267581d8b33644771ad26e8f780 661960b16f1c6186644771ad3f800000 b35f4267581d8b33644771ad26e8f780 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintp.f32.f32 d6, d24 9552deef995b8eb31311fc5941200161 fce0c416fb71b989fce0c416978a5003 9552deef995b8eb3fce0c41680000000 fce0c416fb71b989fce0c416978a5003 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintp.f32.f32 d6, d24 6c0917cfb7110d9415d2fc40a24b2a2c e539eaa068ce32636ead44ddee367099 6c0917cfb7110d946ead44ddee367099 e539eaa068ce32636ead44ddee367099 fpscr=00000000
+vrintp.f32.f32 d6, d24 a9b5b99e62aaa22bba5f80c08b6ef8af 2ee9a824d3c22390bf3fbc2f33edc629 a9b5b99e62aaa22b800000003f800000 2ee9a824d3c22390bf3fbc2f33edc629 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintp.f32.f32 d6, d24 f2c918d875349bbf866ea601796ab42f 31dc702c7b29439859847dfa513c3057 f2c918d875349bbf59847dfa513c3057 31dc702c7b29439859847dfa513c3057 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[3]
+vrintp.f32.f32 d6, d24 e8ef3b01756b9b12505e6744f8fa326d a109f2599c072981cb51ffc8a109f259 e8ef3b01756b9b12cb51ffc880000000 a109f2599c072981cb51ffc8a109f259 fpscr=00000000
+vrintp.f32.f32 d6, d24 fde06265971ca4d3391ea60a3cfa1b90 bceb2896d866fdc41fa5675deeb19f35 fde06265971ca4d33f800000eeb19f35 bceb2896d866fdc41fa5675deeb19f35 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintp.f32.f32 d6, d24 95f00bab22b45f9ede329f89261bc7fe 3848b7e89b27dcec3848b7e8bf696871 95f00bab22b45f9e3f80000080000000 3848b7e89b27dcec3848b7e8bf696871 fpscr=00000000
+vrintp.f32.f32 d6, d24 434038541d699746ba62550857d605a0 e61812921822d2b4368727e965f72f03 434038541d6997463f80000065f72f03 e61812921822d2b4368727e965f72f03 fpscr=00000000
+vrintm.f32.f32 d9, d27 951e761eb402f28a40579500240f7839 33ce7cc02db1f47218561b6dd062c012 000000000000000040579500240f7839 33ce7cc02db1f47218561b6dd062c012 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintm.f32.f32 d9, d27 0ec7827c0ec7827c1a66776abc91707f 482796c9510646d0178e3b788f941a9b 482796c0510646d01a66776abc91707f 482796c9510646d0178e3b788f941a9b fpscr=00000000
+vrintm.f32.f32 d9, d27 da7ecfb63c396d9b19c90e62084656cb 1c75fc4467118f5707b1a8de01cd734d 0000000067118f5719c90e62084656cb 1c75fc4467118f5707b1a8de01cd734d fpscr=00000000
+vrintm.f32.f32 d9, d27 5c32107222a5d3c813c85e9cb76ca876 684d194c37298bafc289bcaf03dcb8d8 684d194c0000000013c85e9cb76ca876 684d194c37298bafc289bcaf03dcb8d8 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintm.f32.f32 d9, d27 65d69e431ddaa0794eee87de6014c02b a64b85ba1375e2f344389382b76d7eb1 bf800000000000004eee87de6014c02b a64b85ba1375e2f344389382b76d7eb1 fpscr=00000000
+vrintm.f32.f32 d9, d27 82769da89e343d4b2d62105ceecbdfba 0db21fc957474914bc2e84e9c7a5cb80 00000000574749142d62105ceecbdfba 0db21fc957474914bc2e84e9c7a5cb80 fpscr=00000000
+vrintm.f32.f32 d9, d27 bf35d2b1e794e0f5fc3e335715bd0d44 83e27d0c5849c24959ab30e751a8a95d bf8000005849c249fc3e335715bd0d44 83e27d0c5849c24959ab30e751a8a95d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintm.f32.f32 d9, d27 9855f4c3a17fcbd2474c2bfd67fd7228 f9230bba9651e651cc525789af14a23c f9230bbabf800000474c2bfd67fd7228 f9230bba9651e651cc525789af14a23c fpscr=00000000
+vrintm.f32.f32 d9, d27 68b86202f371e0e890cd2c0a496481fe 63f3fa5a10e6260ceda968626854caae 63f3fa5a0000000090cd2c0a496481fe 63f3fa5a10e6260ceda968626854caae fpscr=00000000
+vrintm.f32.f32 d9, d27 f5b03dd9c8d575aeecbe5ec00f5d4035 744c262d21e6ba5956b309a36f345af3 744c262d00000000ecbe5ec00f5d4035 744c262d21e6ba5956b309a36f345af3 fpscr=00000000
+vrintm.f32.f32 d9, d27 3bcbe53414e1df8687642d060708f43f abc36659e46d77bf49f086f520d901c9 bf800000e46d77bf87642d060708f43f abc36659e46d77bf49f086f520d901c9 fpscr=00000000
+vrintm.f32.f32 d9, d27 396e5ecc9e1b183f90ba74a586c8696a efd883d938902eb764248abc3bf2bd0e efd883d90000000090ba74a586c8696a efd883d938902eb764248abc3bf2bd0e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintm.f32.f32 d9, d27 ccbf83c1b3b142693dab6ce24b9ddc96 6c271bf8ba9cebdbdb50cc2edb50cc2e 6c271bf8bf8000003dab6ce24b9ddc96 6c271bf8ba9cebdbdb50cc2edb50cc2e fpscr=00000000
+vrintm.f32.f32 d9, d27 9e15d47475005eed3659272a5523f8da aba1d700f53dacd9f2f402919f85f4e5 bf800000f53dacd93659272a5523f8da aba1d700f53dacd9f2f402919f85f4e5 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[0]
+vrintm.f32.f32 d9, d27 b5e42d0fe7068d0bf39188a6f39188a6 52d3740317eebe3b3b2914e830dced06 52d3740300000000f39188a6f39188a6 52d3740317eebe3b3b2914e830dced06 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintm.f32.f32 d9, d27 f6550f6c0d8691704c0a0a74e9875be4 e71dc58d13cd480b163e2182163e2182 e71dc58d000000004c0a0a74e9875be4 e71dc58d13cd480b163e2182163e2182 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintm.f32.f32 d9, d27 42f0629c42f0629c51cde8825c4d2ac6 c9f6430a6b14ed201aa4556925460dd8 c9f643106b14ed2051cde8825c4d2ac6 c9f6430a6b14ed201aa4556925460dd8 fpscr=00000000
+vrintm.f32.f32 d9, d27 a8e191f27a49d3620ed0af59f807ba08 80fd1c1a04a0f7d69df62064c87df550 bf800000000000000ed0af59f807ba08 80fd1c1a04a0f7d69df62064c87df550 fpscr=00000000
+vrintm.f32.f32 d9, d27 7c26b37391f2d665709beb58c6604c9f 83a85843b27b9afe4c4b099ad57c9bf1 bf800000bf800000709beb58c6604c9f 83a85843b27b9afe4c4b099ad57c9bf1 fpscr=00000000
+vrintm.f32.f32 d9, d27 85bca6a681497022e29e896d1092635c e718a20a66a34c12c635f76c41f726ca e718a20a66a34c12e29e896d1092635c e718a20a66a34c12c635f76c41f726ca fpscr=00000000
+vrintm.f32.f32 d9, d27 31e96d823fb8bc8647191ef3edb791d4 4aba3e254864551b1d67fe5310b0c874 4aba3e244864550047191ef3edb791d4 4aba3e254864551b1d67fe5310b0c874 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintm.f32.f32 d9, d27 143109917085a69bebce66437e5efeb7 a79f2dbf2f87bdc32f87bdc3ad5be575 bf80000000000000ebce66437e5efeb7 a79f2dbf2f87bdc32f87bdc3ad5be575 fpscr=00000000
+vrintm.f32.f32 d9, d27 63f6dfe3d9a3c31288c413dcd4a276bf d095bd184cdb4c585fd8b1045dcd7de0 d095bd184cdb4c5888c413dcd4a276bf d095bd184cdb4c585fd8b1045dcd7de0 fpscr=00000000
+vrintm.f32.f32 d9, d27 9413d0275ad854d6ddad1d4a53d47acc c437e7686f21a070e0573313a0d5b364 c43800006f21a070ddad1d4a53d47acc c437e7686f21a070e0573313a0d5b364 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintm.f32.f32 d9, d27 156ac0c229cfb5ea093219a0e46280ba 4e63a5c8bfeef8a31afcf4f082ed3e30 4e63a5c8c0000000093219a0e46280ba 4e63a5c8bfeef8a31afcf4f082ed3e30 fpscr=00000000
+vrintm.f32.f32 d9, d27 f911fb4b10d3f8b778e0ec91f2e1cee5 96dac9210bccf6ced15e84eb878bb187 bf8000000000000078e0ec91f2e1cee5 96dac9210bccf6ced15e84eb878bb187 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintm.f32.f32 d9, d27 8314216eea6fe43c1284df78ed703c3b 3cd05f55132c7d4f1fcd06d56a89f38d 00000000000000001284df78ed703c3b 3cd05f55132c7d4f1fcd06d56a89f38d fpscr=00000000
+vrintm.f32.f32 d9, d27 d751a8ec35a3e8232a54237a05ef97c5 a172ee3fe64fc4e86c39989e17ce6ea9 bf800000e64fc4e82a54237a05ef97c5 a172ee3fe64fc4e86c39989e17ce6ea9 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintm.f32.f32 d9, d27 fed8c0de34641b4f42ef1cbe032b0514 3b5583949ec548cf6724e327bc850791 00000000bf80000042ef1cbe032b0514 3b5583949ec548cf6724e327bc850791 fpscr=00000000
+vrintm.f32.f32 d9, d27 ec31983e647c403d71654d8443fc143a 750f361fccd5cd2ad1625b6ca6eb69d7 750f361fccd5cd2a71654d8443fc143a 750f361fccd5cd2ad1625b6ca6eb69d7 fpscr=00000000
+vrintm.f32.f32 d9, d27 f3cdc76697a9d21e7807f37c1cd58190 6653f373434b426271201d897383b7c6 6653f373434b00007807f37c1cd58190 6653f373434b426271201d897383b7c6 fpscr=00000000
+vrintm.f32.f32 d9, d27 569433f148725489880594872cf97877 101419959a82acd7bf25eac597e30bd1 00000000bf800000880594872cf97877 101419959a82acd7bf25eac597e30bd1 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintm.f32.f32 d9, d27 3cd0149d3cd0149d493adfc421253d59 e5460008ac3927b6e0f16b35c050cafe e5460008bf800000493adfc421253d59 e5460008ac3927b6e0f16b35c050cafe fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintm.f32.f32 d9, d27 3f44358e3f44358e9c08944cc8cf5604 c890f010ef9c001f0ebf3391f0eda821 c890f020ef9c001f9c08944cc8cf5604 c890f010ef9c001f0ebf3391f0eda821 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintm.f32.f32 d9, d27 c275b7364d63a974030d2a4a69cfbe48 4924f0104924f010e0c4285a2c0e7f8b 4924f0104924f010030d2a4a69cfbe48 4924f0104924f010e0c4285a2c0e7f8b fpscr=00000000
+vrintm.f32.f32 d9, d27 0d1e95c454ba196cd7850c4b29d4fc05 a8c13ef3c4c0d12add0ab81d9f74023a bf800000c4c0e000d7850c4b29d4fc05 a8c13ef3c4c0d12add0ab81d9f74023a fpscr=00000000
+vrintm.f32.f32 d9, d27 c1365d4c96c3b3e24eff516ee26c564f 52e0c4686a1623f6736ec7294d46b7e9 52e0c4686a1623f64eff516ee26c564f 52e0c4686a1623f6736ec7294d46b7e9 fpscr=00000000
+randV128: 17152 calls, 17733 iters
+vrintm.f32.f32 d9, d27 25e739a14a5c8d0855fdc9b8d95bca5b 40abedfc463f6a0a0bfa5488d3830b82 40a00000463f680055fdc9b8d95bca5b 40abedfc463f6a0a0bfa5488d3830b82 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintm.f32.f32 d9, d27 617d943506276bf170542b0baaaa3628 0f59d70d9104e307071319336bccb10a 00000000bf80000070542b0baaaa3628 0f59d70d9104e307071319336bccb10a fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintm.f32.f32 d9, d27 406aed1bdc2667fdc06e4a56e2f792fe 3bd6ce46b110a890bdce7e1781ed74bb 00000000bf800000c06e4a56e2f792fe 3bd6ce46b110a890bdce7e1781ed74bb fpscr=00000000
+vrintm.f32.f32 d9, d27 44a80e6f971593e7bb6f5cd8f66b65a9 fe6929230c80942a379814bb8a28c920 fe69292300000000bb6f5cd8f66b65a9 fe6929230c80942a379814bb8a28c920 fpscr=00000000
+vrintm.f32.f32 d9, d27 80db64a7ec36cbd608228bc49990ecbc b68d3752c2a6442649ddce3a764ffb0e bf800000c2a8000008228bc49990ecbc b68d3752c2a6442649ddce3a764ffb0e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintm.f32.f32 d9, d27 ce4568a8f8d3f9a46e0c838a6db989df 5a21ca732635cbca38165fbccc06cb68 5a21ca73000000006e0c838a6db989df 5a21ca732635cbca38165fbccc06cb68 fpscr=00000000
+vrintm.f32.f32 d9, d27 082dfd40837188015826fc8e78355e0c 36347ef1434a255bd6ee013bef50ecc0 00000000434a00005826fc8e78355e0c 36347ef1434a255bd6ee013bef50ecc0 fpscr=00000000
+vrintm.f32.f32 d9, d27 6d794bc7cc559b51ebfdccb0440a0b07 46b2dc1fda9ef01f2ded1190f161f393 46b2dc00da9ef01febfdccb0440a0b07 46b2dc1fda9ef01f2ded1190f161f393 fpscr=00000000
+vrintm.f32.f32 d9, d27 1b7b5fe824f7cb6d5b2790ad304ea9b4 3441e2c7c3aa7d80374a645efb649a97 00000000c3aa80005b2790ad304ea9b4 3441e2c7c3aa7d80374a645efb649a97 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintm.f32.f32 d9, d27 911f4fd0fcfa7f4854c52114fcfa7f48 e40ff630d960edb6f60f8f1346efad1a e40ff630d960edb654c52114fcfa7f48 e40ff630d960edb6f60f8f1346efad1a fpscr=00000000
+vrintm.f32.f32 d9, d27 4b9decd38ac052009a54e4cfd3bedc44 737e236665f57212d892ebabb7430bcc 737e236665f572129a54e4cfd3bedc44 737e236665f57212d892ebabb7430bcc fpscr=00000000
+vrintm.f32.f32 d9, d27 4296b7d27666a28e3878889e5764b25b 73bc2ea94e3f727f5f428a606c6e8efe 73bc2ea94e3f727f3878889e5764b25b 73bc2ea94e3f727f5f428a606c6e8efe fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintm.f32.f32 d9, d27 d43691c6ee90b2544e691acc76941358 0df1f9d3a4a6448449e612d335d69dfb 00000000bf8000004e691acc76941358 0df1f9d3a4a6448449e612d335d69dfb fpscr=00000000
+vrintz.f32.f32 d12, d30 4144930cc3d0a34442d3265a9e7fb405 6b35beabc9dc461e0f97fcd4c047c552 4144930cc3d0a34400000000c0400000 6b35beabc9dc461e0f97fcd4c047c552 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[2]
+vrintz.f32.f32 d12, d30 d32165c6abee5835abee5835f20ec953 6b69403e9d82a1c9c6e5c0300bcd03d2 d32165c6abee5835c6e5c00000000000 6b69403e9d82a1c9c6e5c0300bcd03d2 fpscr=00000000
+vrintz.f32.f32 d12, d30 68bcde34649e7a7008befd9af092057b 256a6f38d9f20092f478b01f60af20be 68bcde34649e7a70f478b01f60af20be 256a6f38d9f20092f478b01f60af20be fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[2]
+vrintz.f32.f32 d12, d30 c82c182a64ba3102c6fbfc40c6fbfc40 84e77f6b600408d387debd533458c834 c82c182a64ba31028000000000000000 84e77f6b600408d387debd533458c834 fpscr=00000000
+vrintz.f32.f32 d12, d30 dfb84365991b50a112fbf44ad15c0664 0873d11a9fbebe9e052212067a88f5d9 dfb84365991b50a1000000007a88f5d9 0873d11a9fbebe9e052212067a88f5d9 fpscr=00000000
+vrintz.f32.f32 d12, d30 3d64b1a8093ecda05d45e8a697f3670d 0e6b452122e731e9f10fec18e94fbd42 3d64b1a8093ecda0f10fec18e94fbd42 0e6b452122e731e9f10fec18e94fbd42 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintz.f32.f32 d12, d30 958590430da1675a265cb6ec32c0e8c7 97b27083b993998fa493663cfb40770d 958590430da1675a80000000fb40770d 97b27083b993998fa493663cfb40770d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[2]
+vrintz.f32.f32 d12, d30 f523408ef523408e77f5c04ee141bfab f6189bf3f6189bf3e009266022e1fcf5 f523408ef523408ee009266000000000 f6189bf3f6189bf3e009266022e1fcf5 fpscr=00000000
+vrintz.f32.f32 d12, d30 ae238b17ad3778f08ac160aebc2e7590 0292c9d4592464c812c4fbf365c05029 ae238b17ad3778f00000000065c05029 0292c9d4592464c812c4fbf365c05029 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintz.f32.f32 d12, d30 487febbbbaad898406fd5785295d2826 e6b2d4c486718511d19776dba83f559c 487febbbbaad8984d19776db80000000 e6b2d4c486718511d19776dba83f559c fpscr=00000000
+vrintz.f32.f32 d12, d30 ab633465f4136cce2d8a6421b9a3ded7 e96d815b4cb2cb10aa825a2542f95443 ab633465f4136cce8000000042f80000 e96d815b4cb2cb10aa825a2542f95443 fpscr=00000000
+vrintz.f32.f32 d12, d30 6c4106fc18a2838adcb80c9cd0328bde 169aa2ddd37c28c4a60806a29698df8f 6c4106fc18a2838a8000000080000000 169aa2ddd37c28c4a60806a29698df8f fpscr=00000000
+vrintz.f32.f32 d12, d30 e7738f4049f8c13002c60d2532bb0849 7254e57d767e8389c1008c9e8d45f748 e7738f4049f8c130c100000080000000 7254e57d767e8389c1008c9e8d45f748 fpscr=00000000
+vrintz.f32.f32 d12, d30 48ffe1365079054172da542f492eaf94 9a1c52f8625eed330e24e7c512d90ccb 48ffe136507905410000000000000000 9a1c52f8625eed330e24e7c512d90ccb fpscr=00000000
+vrintz.f32.f32 d12, d30 e7082983f37e4fa9b04ed1c4c5479f5a 7e1b6cdefebc45ee22589e77406d2d70 e7082983f37e4fa90000000040400000 7e1b6cdefebc45ee22589e77406d2d70 fpscr=00000000
+vrintz.f32.f32 d12, d30 39b56c5f09e1995224d270b3ea54d328 2d8c8fd25ebe4396285a664f1123572a 39b56c5f09e199520000000000000000 2d8c8fd25ebe4396285a664f1123572a fpscr=00000000
+vrintz.f32.f32 d12, d30 9f782af068e0981a21f6fb2ebc5e26b5 1112baa4177fd9fc594d2e7876d716fc 9f782af068e0981a594d2e7876d716fc 1112baa4177fd9fc594d2e7876d716fc fpscr=00000000
+vrintz.f32.f32 d12, d30 12b4d6fdac62582fd90dd3b90da82f78 83dbb6557a5efd00d22c7defcfaa8e63 12b4d6fdac62582fd22c7defcfaa8e63 83dbb6557a5efd00d22c7defcfaa8e63 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintz.f32.f32 d12, d30 b4c23804eda1bbbb297493866e9cfe9b c3b999f02529cd90ca1340a3bf75dc89 b4c23804eda1bbbbca1340a080000000 c3b999f02529cd90ca1340a3bf75dc89 fpscr=00000000
+vrintz.f32.f32 d12, d30 6b3d3856abaf4a2ad703473b8c27f80f fd714b08ad4bff2e1685246deb6f6110 6b3d3856abaf4a2a00000000eb6f6110 fd714b08ad4bff2e1685246deb6f6110 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[3]
+vrintz.f32.f32 d12, d30 d2a0374839ad564a35d74d2720a7ffe5 4d69857fb8a38628b8a38628fefbe188 d2a0374839ad564a80000000fefbe188 4d69857fb8a38628b8a38628fefbe188 fpscr=00000000
+vrintz.f32.f32 d12, d30 faf3796f26b434bb5ab998e667cded6e 0b671fd1ca78ba56e5e09f1c8c0c6cf4 faf3796f26b434bbe5e09f1c80000000 0b671fd1ca78ba56e5e09f1c8c0c6cf4 fpscr=00000000
+vrintz.f32.f32 d12, d30 7a7842986041706469950e12c329a394 4f395273fa9d48f35b806e1c4bb970ca 7a784298604170645b806e1c4bb970ca 4f395273fa9d48f35b806e1c4bb970ca fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintz.f32.f32 d12, d30 822055f9a83c6e2f388127adb1036a47 d884869b8c72ebba2abdbc8cd884869b 822055f9a83c6e2f00000000d884869b d884869b8c72ebba2abdbc8cd884869b fpscr=00000000
+vrintz.f32.f32 d12, d30 a8db7e9f6562b556190e9b1e7819584f 31cecaeaa8613152278bb0e4204575f6 a8db7e9f6562b5560000000000000000 31cecaeaa8613152278bb0e4204575f6 fpscr=00000000
+vrintz.f32.f32 d12, d30 904f09cf3d03a713046348bc5f9a7d62 cef6b465d4faed15262942462948fb80 904f09cf3d03a7130000000000000000 cef6b465d4faed15262942462948fb80 fpscr=00000000
+vrintz.f32.f32 d12, d30 0c9c50ce35dad1045e97e9913fe83537 bbea973f36cc117eef28d10f4686b0cd 0c9c50ce35dad104ef28d10f4686b000 bbea973f36cc117eef28d10f4686b0cd fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[0]
+vrintz.f32.f32 d12, d30 f7b7ea4c0a1a34baadd25764e53ad8b9 961b0383736799f2961b03837c1b0e1d f7b7ea4c0a1a34ba800000007c1b0e1d 961b0383736799f2961b03837c1b0e1d fpscr=00000000
+vrintz.f32.f32 d12, d30 cd7b9c2e92f6aa1eb7e62c38c81b3aab b74146b743f75b2daac28efc115d52d8 cd7b9c2e92f6aa1e8000000000000000 b74146b743f75b2daac28efc115d52d8 fpscr=00000000
+vrintz.f32.f32 d12, d30 cba9ed799ebfaab0864567573347a248 aa4c811a5ce00117c3bf678c24ce8b5c cba9ed799ebfaab0c3bf000000000000 aa4c811a5ce00117c3bf678c24ce8b5c fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintz.f32.f32 d12, d30 c5d235d53764bbff5de193913c4c02b9 b8dccdc09bb15c9a0ee6f20a3b3f0402 c5d235d53764bbff0000000000000000 b8dccdc09bb15c9a0ee6f20a3b3f0402 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintz.f32.f32 d12, d30 710a59916d3c87c465787fe424dbeb42 38b8077073958c7b20f970ecd3ec2e34 710a59916d3c87c400000000d3ec2e34 38b8077073958c7b20f970ecd3ec2e34 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintz.f32.f32 d12, d30 db47f01ba7f72d91eb6eae9af4bfcec6 cc23d5cb76ff0b5bbafb0bae793ed523 db47f01ba7f72d9180000000793ed523 cc23d5cb76ff0b5bbafb0bae793ed523 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintz.f32.f32 d12, d30 b6e0034d1c435f18863622cc1c2ed7fb 520b5cb1eefd0f888308ca468bea1dd8 b6e0034d1c435f188000000080000000 520b5cb1eefd0f888308ca468bea1dd8 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintz.f32.f32 d12, d30 ed1b448fe5348c20ace7c50258a48ddd 44610e0d7958bc37e27d8805ee59c6ef ed1b448fe5348c20e27d8805ee59c6ef 44610e0d7958bc37e27d8805ee59c6ef fpscr=00000000
+vrintz.f32.f32 d12, d30 55c877fd60c4d2184b7003860f9a1704 71d6d9a39ab8f4a1be1235164749b984 55c877fd60c4d218800000004749b900 71d6d9a39ab8f4a1be1235164749b984 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintz.f32.f32 d12, d30 2141a6abcdfdc2893b29d6e4de21137f 29046ebfe5cb043442b02178945a59bc 2141a6abcdfdc28942b0000080000000 29046ebfe5cb043442b02178945a59bc fpscr=00000000
+vrintz.f32.f32 d12, d30 c6f1c7442c3d9fdbc3f44cee1ac95f53 b1f03bca0107740e9bc54b8083ca762a c6f1c7442c3d9fdb8000000080000000 b1f03bca0107740e9bc54b8083ca762a fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[1]
+vrintz.f32.f32 d12, d30 459606746b3537564468a2e6ba37b4fa 29d07d0bb7760fce1ce4d6d6511f04d4 459606746b35375600000000511f04d4 29d07d0bb7760fce1ce4d6d6511f04d4 fpscr=00000000
+vrintz.f32.f32 d12, d30 8e7fa4ccbd6213ec523cc43c73aa816e 1f7e387a70773a5629c2c5641265bf8c 8e7fa4ccbd6213ec0000000000000000 1f7e387a70773a5629c2c5641265bf8c fpscr=00000000
+vrintz.f32.f32 d12, d30 6bf093df66b135f208314cab87458fc7 55325a178ddc1c5e6729966121197098 6bf093df66b135f26729966100000000 55325a178ddc1c5e6729966121197098 fpscr=00000000
+vrintz.f32.f32 d12, d30 739087cdfe095001b71cd6af136a5062 e1bd33ba0bd8789ac749302a2bb4d68e 739087cdfe095001c749300000000000 e1bd33ba0bd8789ac749302a2bb4d68e fpscr=00000000
+vrintz.f32.f32 d12, d30 79d83d01300593357ee92416dea0e7e0 2ce20353f0f238144b82d48aac25553e 79d83d01300593354b82d48a80000000 2ce20353f0f238144b82d48aac25553e fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintz.f32.f32 d12, d30 d16cfb9ed77dcfa9d16cfb9e4b6f6f00 67ae2affafb5b2757c5427826ac2f492 d16cfb9ed77dcfa97c5427826ac2f492 67ae2affafb5b2757c5427826ac2f492 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintz.f32.f32 d12, d30 25e867c936fbac53c00c2ea5a3a1546e 2bd43fa3ecbe36a5e524df1aeff065ce 25e867c936fbac53e524df1aeff065ce 2bd43fa3ecbe36a5e524df1aeff065ce fpscr=00000000
+vrintz.f32.f32 d12, d30 303e868c35d59d056222b22517ebedc8 c9579060f47f4dd7aa56c7b44573c4d2 303e868c35d59d05800000004573c000 c9579060f47f4dd7aa56c7b44573c4d2 fpscr=00000000
+vrintz.f32.f32 d12, d30 c82c21aa1847777a18cd882de23a1c7a 5b9554779ec133de47df342756a6daf1 c82c21aa1847777a47df340056a6daf1 5b9554779ec133de47df342756a6daf1 fpscr=00000000
+vrintz.f32.f32 d12, d30 f403d4ef04fd710830ec2211d673483e c4ce9d3cd6ca9a6ef176e96ffbb3c023 f403d4ef04fd7108f176e96ffbb3c023 c4ce9d3cd6ca9a6ef176e96ffbb3c023 fpscr=00000000
+vrintz.f32.f32 d12, d30 5ad02bf69f24bd4a8717208cdb0be72f f74089d9d840c67eadde219ca1d39272 5ad02bf69f24bd4a8000000080000000 f74089d9d840c67eadde219ca1d39272 fpscr=00000000
+vrintz.f32.f32 d12, d30 3a0e47013546a0a8081b0d29b25a9016 035d9ae3c587d36f06873e7ebf32c964 3a0e47013546a0a80000000080000000 035d9ae3c587d36f06873e7ebf32c964 fpscr=00000000
+vrintx.f32.f32 d15, d15 2572239c0a3c4f14a300e11c8ec9236b 18fe0423ba96206e4bf85aab2e03e59d 00000000800000004bf85aab2e03e59d 00000000800000004bf85aab2e03e59d fpscr=00000000
+randV128: 17408 calls, 17995 iters
+vrintx.f32.f32 d15, d15 159b3a1918fb3ba6a4fee90704df4f33 6100dfbbd530a138a7b1b2e468f6fdeb 6100dfbbd530a138a7b1b2e468f6fdeb 6100dfbbd530a138a7b1b2e468f6fdeb fpscr=00000000
+vrintx.f32.f32 d15, d15 de9d8feb1c3fb61f6a460b8e673275b9 c0302da90e730a452558f7dda90e2ea4 c0400000000000002558f7dda90e2ea4 c0400000000000002558f7dda90e2ea4 fpscr=00000000
+vrintx.f32.f32 d15, d15 0b750eec121bf74178b270e17b31f434 74abd2b1f7d6dd498c547c65e9d8e673 74abd2b1f7d6dd498c547c65e9d8e673 74abd2b1f7d6dd498c547c65e9d8e673 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintx.f32.f32 d15, d15 104d59700b668311f1558410f1558410 fd9d8f8d5aa15b7a5a1f1dbf41e6bd02 fd9d8f8d5aa15b7a5a1f1dbf41e6bd02 fd9d8f8d5aa15b7a5a1f1dbf41e6bd02 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintx.f32.f32 d15, d15 df80ddb5e94d5f0df0f46be3624edc2c 083d560aaaf7bbe14c0a30c2e450134c 00000000800000004c0a30c2e450134c 00000000800000004c0a30c2e450134c fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintx.f32.f32 d15, d15 e352a3badba895b4463b0dad2507970e 39451d5a39451d5aaa06b55fb3446e5c 0000000000000000aa06b55fb3446e5c 0000000000000000aa06b55fb3446e5c fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[1]
+vrintx.f32.f32 d15, d15 365617a1365617a178efcf6b673b9c89 03def0ba8c804132583d29c70ece6289 0000000080000000583d29c70ece6289 0000000080000000583d29c70ece6289 fpscr=00000000
+vrintx.f32.f32 d15, d15 6fc315627ecf6c69db86b8c539013255 b14f184809f9a84d6caab2d43cc63de6 80000000000000006caab2d43cc63de6 80000000000000006caab2d43cc63de6 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintx.f32.f32 d15, d15 3ac8a171b17f176f276197d13ac8a171 3d62b97b0251fdef4a1794d6cf985f20 00000000000000004a1794d6cf985f20 00000000000000004a1794d6cf985f20 fpscr=00000000
+vrintx.f32.f32 d15, d15 21a97c49346eeed8cd6ded243468e41c 905c65045fee2ca717699be01b9b04a0 800000005fee2ca717699be01b9b04a0 800000005fee2ca717699be01b9b04a0 fpscr=00000000
+vrintx.f32.f32 d15, d15 3139b52348291f7aff64434eca258490 1705b508ae997ecf1c9a1f4bca6a6c85 00000000800000001c9a1f4bca6a6c85 00000000800000001c9a1f4bca6a6c85 fpscr=00000000
+vrintx.f32.f32 d15, d15 b4503b1e3b1378106bc1686fb1c3990b a921505194caf3bc26eb269955c573c7 800000008000000026eb269955c573c7 800000008000000026eb269955c573c7 fpscr=00000000
+vrintx.f32.f32 d15, d15 cf087c89a727640f187146feed4fb708 7820d01bf2ce0fcd08fcae55d8b33dc1 7820d01bf2ce0fcd08fcae55d8b33dc1 7820d01bf2ce0fcd08fcae55d8b33dc1 fpscr=00000000
+vrintx.f32.f32 d15, d15 50a3a7ba19bec956a4d15f20283581cf f2afed3ceaf82936b19c187454f8c632 f2afed3ceaf82936b19c187454f8c632 f2afed3ceaf82936b19c187454f8c632 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintx.f32.f32 d15, d15 201ab36a2238aca702750f400b2d8d31 1d4d22646abc9560838b6a03d7723622 000000006abc9560838b6a03d7723622 000000006abc9560838b6a03d7723622 fpscr=00000000
+vrintx.f32.f32 d15, d15 54326503ef937f00d24e9d7c4b17adb4 c9ba4e89e7718fb6270771fa2363e66e c9ba4e88e7718fb6270771fa2363e66e c9ba4e88e7718fb6270771fa2363e66e fpscr=00000000
+vrintx.f32.f32 d15, d15 5799cf31d4395e727276350423ecb428 65fa7a4450bc440682c7a3ab38725b45 65fa7a4450bc440682c7a3ab38725b45 65fa7a4450bc440682c7a3ab38725b45 fpscr=00000000
+vrintx.f32.f32 d15, d15 16f04da4c401df6ff060d85994421dbc 48f21c9dc849fe4bcc12f2fb6ef4b84b 48f21ca0c849fe40cc12f2fb6ef4b84b 48f21ca0c849fe40cc12f2fb6ef4b84b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[3]
+vrintx.f32.f32 d15, d15 d62f76d8d62f76d88b7e7fac8806b418 475b17d9bb129fe6dee48729b059a09c 475b180080000000dee48729b059a09c 475b180080000000dee48729b059a09c fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintx.f32.f32 d15, d15 7cee4e29849d14374e670b27849d1437 890169ca782893d3857fa08cef5a72ae 80000000782893d3857fa08cef5a72ae 80000000782893d3857fa08cef5a72ae fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[3]
+vrintx.f32.f32 d15, d15 88630c14becdb19bcc0671d5cc0671d5 3f209c65f72e9c0c0b6b5fa4ea0b42e0 3f800000f72e9c0c0b6b5fa4ea0b42e0 3f800000f72e9c0c0b6b5fa4ea0b42e0 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintx.f32.f32 d15, d15 091e0940e323580496facc51051909aa 7ce1f9570d942d052704abc8100e3f18 7ce1f957000000002704abc8100e3f18 7ce1f957000000002704abc8100e3f18 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[1]
+vrintx.f32.f32 d15, d15 e262da48a3532dbaa9535ddd393feeb2 a5eff80da78f89540ecd7f7ffc915350 80000000800000000ecd7f7ffc915350 80000000800000000ecd7f7ffc915350 fpscr=00000000
+vrintx.f32.f32 d15, d15 b12a44afe3962df2f5425dc95446db86 a199acd4c69765913ca9193e6a2e0ef3 80000000c69766003ca9193e6a2e0ef3 80000000c69766003ca9193e6a2e0ef3 fpscr=00000000
+vrintx.f32.f32 d15, d15 1d6a93519e0cb41e5852c0f9a6bdfeca b10f4093eec1d08e9f5dc200fa598e27 80000000eec1d08e9f5dc200fa598e27 80000000eec1d08e9f5dc200fa598e27 fpscr=00000000
+vrintx.f32.f32 d15, d15 5f37273cbc7b9553f706302a5368688f 86bb443db7c1e2bb3dabc3ec0d7fb29d 80000000800000003dabc3ec0d7fb29d 80000000800000003dabc3ec0d7fb29d fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintx.f32.f32 d15, d15 5e14c76b1cf49e0a6c2258bf19f817b3 bce49c5ef6fcd991ef5c51be70b7664d 80000000f6fcd991ef5c51be70b7664d 80000000f6fcd991ef5c51be70b7664d fpscr=00000000
+vrintx.f32.f32 d15, d15 3f6ff9654599112859c7deddeea5ecf1 64f59fd945ea7e6d44ede760a5ac1955 64f59fd945ea800044ede760a5ac1955 64f59fd945ea800044ede760a5ac1955 fpscr=00000000
+vrintx.f32.f32 d15, d15 2ae6e870cb1acefdb63c9895d0ac42f7 d817c1e8b41291a3718b70c4f94b9cc7 d817c1e880000000718b70c4f94b9cc7 d817c1e880000000718b70c4f94b9cc7 fpscr=00000000
+vrintx.f32.f32 d15, d15 5d9af340d61eaa7a5f339d18692e4317 560fac1c70a6e835ce0f297f97c66ad7 560fac1c70a6e835ce0f297f97c66ad7 560fac1c70a6e835ce0f297f97c66ad7 fpscr=00000000
+vrintx.f32.f32 d15, d15 fb4b056a83c345ec11a3fb355c9ac596 90151a18bb81e2e65e1b12a9904c46cc 80000000800000005e1b12a9904c46cc 80000000800000005e1b12a9904c46cc fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintx.f32.f32 d15, d15 2ac9ea558bf5afe51ef51c573a533c81 f3bc90faa6f2e900e540594e84d720a5 f3bc90fa80000000e540594e84d720a5 f3bc90fa80000000e540594e84d720a5 fpscr=00000000
+vrintx.f32.f32 d15, d15 abf3b3c039f2888f09933aacd546340e 99c2bdab5798d710dc020ea5cfe1175a 800000005798d710dc020ea5cfe1175a 800000005798d710dc020ea5cfe1175a fpscr=00000000
+vrintx.f32.f32 d15, d15 43858907228f75f4a168b38c47821b7f 2ca3656889435cf35319898c067feafa 00000000800000005319898c067feafa 00000000800000005319898c067feafa fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintx.f32.f32 d15, d15 960357d97813eabf060cf4fe706285b1 a95cb910bac36ef6d60915119e597746 8000000080000000d60915119e597746 8000000080000000d60915119e597746 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintx.f32.f32 d15, d15 6418b781a19da43b1f7bdea1dfbdb64c da493a28da493a285b00746d2faf5f74 da493a28da493a285b00746d2faf5f74 da493a28da493a285b00746d2faf5f74 fpscr=00000000
+vrintx.f32.f32 d15, d15 d2380287f306e2554da09386faca0b70 70215759009514c0e046917b71c4d074 7021575900000000e046917b71c4d074 7021575900000000e046917b71c4d074 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintx.f32.f32 d15, d15 13892820e6e7e15822a9b59b2b184d68 71b1ecedc6946c42215eb2b3d8504f04 71b1ecedc6946c00215eb2b3d8504f04 71b1ecedc6946c00215eb2b3d8504f04 fpscr=00000000
+vrintx.f32.f32 d15, d15 43a2c85423bcbadacd049b616a819d29 9250ec96850800ed3f7549c0c32d530b 80000000800000003f7549c0c32d530b 80000000800000003f7549c0c32d530b fpscr=00000000
+vrintx.f32.f32 d15, d15 7a74fb4bcf1e0d80396f19a5c2bd5186 2e5a6c35a2e2d7fd06729b780325db06 000000008000000006729b780325db06 000000008000000006729b780325db06 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintx.f32.f32 d15, d15 8a658e088a658e08b72b7fb3a5568fc8 2310b1ca4e97571104503ea98caa058b 000000004e97571104503ea98caa058b 000000004e97571104503ea98caa058b fpscr=00000000
+vrintx.f32.f32 d15, d15 fc64b275fd5d7fa85d1cbc0625395cab bb92864cbc9d9e4df274db4304074703 8000000080000000f274db4304074703 8000000080000000f274db4304074703 fpscr=00000000
+vrintx.f32.f32 d15, d15 b99e53d454014873b6b3e8a42f3f7037 0c4057f68a9a7e94b83193ef7ca39a4f 0000000080000000b83193ef7ca39a4f 0000000080000000b83193ef7ca39a4f fpscr=00000000
+vrintx.f32.f32 d15, d15 847496bcc621f62711bdacfe3ffafa2d cd87fb36f84321b5fa1f0d02f92d7212 cd87fb36f84321b5fa1f0d02f92d7212 cd87fb36f84321b5fa1f0d02f92d7212 fpscr=00000000
+vrintx.f32.f32 d15, d15 f01915c1754977348fb14ec393783ef4 5ee343124f0cb934a59aef01ec8213f7 5ee343124f0cb934a59aef01ec8213f7 5ee343124f0cb934a59aef01ec8213f7 fpscr=00000000
+vrintx.f32.f32 d15, d15 2270d3c5da69593dd8f85293732dba8a 23fba9d35ad6588d8f1acb85f2a4a23a 000000005ad6588d8f1acb85f2a4a23a 000000005ad6588d8f1acb85f2a4a23a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[3]
+vrintx.f32.f32 d15, d15 c11abfd65f03f4124c423c1e0d6387bb f2e9ee80cc0e95ddf2e9ee806d120f88 f2e9ee80cc0e95ddf2e9ee806d120f88 f2e9ee80cc0e95ddf2e9ee806d120f88 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintx.f32.f32 d15, d15 e5067be54bc853669eea5236e5067be5 2a24d9f71c74412dd987626139d63be3 0000000000000000d987626139d63be3 0000000000000000d987626139d63be3 fpscr=00000000
+vrintx.f32.f32 d15, d15 3a2c7f2694ddb00cd6fa4c76ec1d4f82 08b00623ca5631ffab5f1282f3af061a 00000000ca563200ab5f1282f3af061a 00000000ca563200ab5f1282f3af061a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintn.f32.f32 q0, q2 bf6945adbf6945add7f8bc634a337222 1e297ed2c37a942bc560f2cdc06afaeb 00000000c37b0000c560f000c0800000 1e297ed2c37a942bc560f2cdc06afaeb fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintn.f32.f32 q0, q2 949a44bfc39d5de8949a44bf3d17c6d0 25361d780affd60c88f0a03af6d1feaf 000000000000000080000000f6d1feaf 25361d780affd60c88f0a03af6d1feaf fpscr=00000000
+vrintn.f32.f32 q0, q2 56d36232125133fd008ac0b640c230ad f9848c1293bcc27535330d2fff6b0c67 f9848c128000000000000000ff6b0c67 f9848c1293bcc27535330d2fff6b0c67 fpscr=00000000
+vrintn.f32.f32 q0, q2 faa1ba396af5a50258853b400faabfa2 693aa3c38c1293b7aa83ece33c612b6f 693aa3c3800000008000000000000000 693aa3c38c1293b7aa83ece33c612b6f fpscr=00000000
+vrintn.f32.f32 q0, q2 ea122994fe4092096c42d76366e7fdc5 57b71d6688a2c86c57e77ee44aea7c22 57b71d668000000057e77ee44aea7c22 57b71d6688a2c86c57e77ee44aea7c22 fpscr=00000000
+vrintn.f32.f32 q0, q2 5153935a2da0bf71d6ca4f77bc9b5835 3e1459aec5e0c8124cb60f1238622df8 00000000c5e0c8004cb60f1200000000 3e1459aec5e0c8124cb60f1238622df8 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[1]
+vrintn.f32.f32 q0, q2 e38053a5194f9531e38053a5e21d5265 184be1cae1e1fd5b8264267b8264267b 00000000e1e1fd5b8000000080000000 184be1cae1e1fd5b8264267b8264267b fpscr=00000000
+vrintn.f32.f32 q0, q2 e8be44426382d5c0cb57561fa1518963 d46a408cdeb9beea1162ec0cdd3ae823 d46a408cdeb9beea00000000dd3ae823 d46a408cdeb9beea1162ec0cdd3ae823 fpscr=00000000
+vrintn.f32.f32 q0, q2 116d4b4088c98a35bd6eb326799260a3 1e57292d128dbed59c0c5ebe701912d7 000000000000000080000000701912d7 1e57292d128dbed59c0c5ebe701912d7 fpscr=00000000
+vrintn.f32.f32 q0, q2 4e35a27f41ef3dbabab4c34c42fc0e23 d0746f70f3848da05b9ad4ab7864d828 d0746f70f3848da05b9ad4ab7864d828 d0746f70f3848da05b9ad4ab7864d828 fpscr=00000000
+vrintn.f32.f32 q0, q2 200b873a6233cc012a4f58a6de5e5068 42d1523191180dabe2613118133e5962 42d2000080000000e261311800000000 42d1523191180dabe2613118133e5962 fpscr=00000000
+vrintn.f32.f32 q0, q2 5afd90b155f8822ddd4f74c8a7f078aa 8f50e46057e9789f145f02d70fc90269 8000000057e9789f0000000000000000 8f50e46057e9789f145f02d70fc90269 fpscr=00000000
+vrintn.f32.f32 q0, q2 a1fbc8469a04ae72f2ad2b332efe84d8 225a99d80b037aae48ad73f77c44450f 000000000000000048ad74007c44450f 225a99d80b037aae48ad73f77c44450f fpscr=00000000
+vrintn.f32.f32 q0, q2 a93733b7cb7d15e6dccd9dd723bf6667 4f8ad4233972e48319322a8375ffa319 4f8ad423000000000000000075ffa319 4f8ad4233972e48319322a8375ffa319 fpscr=00000000
+vrintn.f32.f32 q0, q2 bd66e57d6c3723f225e72f6002b83b3f 12de08997b706f99f7b4ef3417bb55c0 000000007b706f99f7b4ef3400000000 12de08997b706f99f7b4ef3417bb55c0 fpscr=00000000
+randV128: 17664 calls, 18256 iters
+vrintn.f32.f32 q0, q2 7e5a45ffc81f3bd66fa6be9d9199f712 5f9d9b1c73774414c40dd072bcfe1acb 5f9d9b1c73774414c40dc00080000000 5f9d9b1c73774414c40dd072bcfe1acb fpscr=00000000
+vrintn.f32.f32 q0, q2 df2b2eb41c2de085c735ad328a415890 5e0419ba46ea2dfddded63bf487762bd 5e0419ba46ea2e00dded63bf487762c0 5e0419ba46ea2dfddded63bf487762bd fpscr=00000000
+vrintn.f32.f32 q0, q2 01b5431284355983023117af6ff8a2d1 b731444dc63fee7af0293828aa89a21e 80000000c63ff000f029382880000000 b731444dc63fee7af0293828aa89a21e fpscr=00000000
+vrintn.f32.f32 q0, q2 70be42e7e0d8082be8df9d107187a179 3f9880babd542538a1d25b2b8f0a0efe 3f800000800000008000000080000000 3f9880babd542538a1d25b2b8f0a0efe fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintn.f32.f32 q0, q2 ec8fde2b0298897e75a96be00298897e 4672b20c7e0c5df544d275452d1ad01d 4672b4007e0c5df544d2800000000000 4672b20c7e0c5df544d275452d1ad01d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintn.f32.f32 q0, q2 52337f81de30309a289fa00e566e1f09 a54b7ebe77b7edf757684af49c47be64 8000000077b7edf757684af480000000 a54b7ebe77b7edf757684af49c47be64 fpscr=00000000
+vrintn.f32.f32 q0, q2 f769777a103141aa58f9a0f135113c0b 4453ff622958df3e4df4d8e4f7bb14e6 44540000000000004df4d8e4f7bb14e6 4453ff622958df3e4df4d8e4f7bb14e6 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintn.f32.f32 q0, q2 d558e539d558e5394e5c58a0c7994b59 34407d91cbb1466634f2e4332dadbf4b 00000000cbb146660000000000000000 34407d91cbb1466634f2e4332dadbf4b fpscr=00000000
+vrintn.f32.f32 q0, q2 18f908d78d32e1651bcbf4eb106ddcc5 1d9ec32cf41033f153599e4fa3572fdf 00000000f41033f153599e4f80000000 1d9ec32cf41033f153599e4fa3572fdf fpscr=00000000
+vrintn.f32.f32 q0, q2 c1070d6dfabae886504193834cf86720 7e2d3403d2e9bde814a0a12f0473e9f8 7e2d3403d2e9bde80000000000000000 7e2d3403d2e9bde814a0a12f0473e9f8 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintn.f32.f32 q0, q2 e18540dc10cb9db93261cd5cbc91ca12 c2459f4e40b0fb6edc02f56040b0fb6e c244000040c00000dc02f56040c00000 c2459f4e40b0fb6edc02f56040b0fb6e fpscr=00000000
+vrintn.f32.f32 q0, q2 cacb75f28427c56281d5096524dc6fa2 b0e4ce143a7583c22f9d51e9aef0e654 80000000000000000000000080000000 b0e4ce143a7583c22f9d51e9aef0e654 fpscr=00000000
+vrintn.f32.f32 q0, q2 cd559371229f057097feddcf34363162 e94de78fb9aa3a96d7fb371dfd806f9c e94de78f80000000d7fb371dfd806f9c e94de78fb9aa3a96d7fb371dfd806f9c fpscr=00000000
+vrintn.f32.f32 q0, q2 cd56470a27a80cbce8d2f0cdeb0e52e6 6fdead8b87417a5a50575b2cebbafc0d 6fdead8b8000000050575b2cebbafc0d 6fdead8b87417a5a50575b2cebbafc0d fpscr=00000000
+vrintn.f32.f32 q0, q2 9231733f6668cabadd409fdcfcc4186a 6e3d32ddb7f440b7898a2a76d4ca93b6 6e3d32dd8000000080000000d4ca93b6 6e3d32ddb7f440b7898a2a76d4ca93b6 fpscr=00000000
+vrintn.f32.f32 q0, q2 e54113f963372e7129040594d17d2c31 4d0a55aedea7121199adb6534d0857c4 4d0a55aedea71211800000004d0857c4 4d0a55aedea7121199adb6534d0857c4 fpscr=00000000
+vrintn.f32.f32 q0, q2 9a5f242586c625b40d6d2085f78bd8fb 206bcddd2718a6007de2fbb375e96f3f 00000000000000007de2fbb375e96f3f 206bcddd2718a6007de2fbb375e96f3f fpscr=00000000
+vrintn.f32.f32 q0, q2 88c95aa022a576b18e81ca65703328db 7c7b8f3bcb6ae9af2505869dacce4da3 7c7b8f3bcb6ae9af0000000080000000 7c7b8f3bcb6ae9af2505869dacce4da3 fpscr=00000000
+vrintn.f32.f32 q0, q2 4b67c198692686ef7e869aabddd3e36e b2998ea6e798631df237788aaab05466 80000000e798631df237788a80000000 b2998ea6e798631df237788aaab05466 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintn.f32.f32 q0, q2 fb703b3738a9ed9f9064707290647072 82d2c0c46093e90cb2be01388451f2a7 800000006093e90c8000000080000000 82d2c0c46093e90cb2be01388451f2a7 fpscr=00000000
+vrintn.f32.f32 q0, q2 849bba31b775dfc2c53bfc5477740620 6c30bfd66db76c48104736dbf92bd5f0 6c30bfd66db76c4800000000f92bd5f0 6c30bfd66db76c48104736dbf92bd5f0 fpscr=00000000
+vrintn.f32.f32 q0, q2 c269aed212bf340a2aa11816ed148980 39a6655557c078dd8b0085af7cd2ea2e 0000000057c078dd800000007cd2ea2e 39a6655557c078dd8b0085af7cd2ea2e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintn.f32.f32 q0, q2 621d5243621d5243dbbdf6deeac3db70 7db65cf59764f0a34995ab0264e43d8f 7db65cf5800000004995ab0064e43d8f 7db65cf59764f0a34995ab0264e43d8f fpscr=00000000
+vrintn.f32.f32 q0, q2 cae3427ca10ded05df3cea52bc65bff6 b6c9c575616b723f9803a78185d3c9d8 80000000616b723f8000000080000000 b6c9c575616b723f9803a78185d3c9d8 fpscr=00000000
+vrintn.f32.f32 q0, q2 ef10205371dbfa1aedf23d2cfe613b67 b477b8815a53f2e9a9db7d78787dbd1f 800000005a53f2e980000000787dbd1f b477b8815a53f2e9a9db7d78787dbd1f fpscr=00000000
+vrintn.f32.f32 q0, q2 b3925f86c9e1bc16b88797a49b14e339 84f900c86ea439dca8346a3ab5e4dd7f 800000006ea439dc8000000080000000 84f900c86ea439dca8346a3ab5e4dd7f fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[3]
+vrintn.f32.f32 q0, q2 ccda5da0a8598fcb85683e6d7ab6378c 7a00fe9d90b587f03ca4a99d5dda9f95 7a00fe9d80000000000000005dda9f95 7a00fe9d90b587f03ca4a99d5dda9f95 fpscr=00000000
+vrintn.f32.f32 q0, q2 4ea2fe8a4a3f0c0a808b8eb0aaa1875e 1999e5fdac476e52a8561b355cbf2e25 0000000080000000800000005cbf2e25 1999e5fdac476e52a8561b355cbf2e25 fpscr=00000000
+vrintn.f32.f32 q0, q2 3531fd63e1252c1c00e5d990b97c8aa6 bb33aaf6e0fa4b39700eb40aa9bba013 80000000e0fa4b39700eb40a80000000 bb33aaf6e0fa4b39700eb40aa9bba013 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintn.f32.f32 q0, q2 4c6295b8e063f26513a852cb1f3fd716 7f62fc3128da330a7c93aa448a57264c 7f62fc31000000007c93aa4480000000 7f62fc3128da330a7c93aa448a57264c fpscr=00000000
+vrintn.f32.f32 q0, q2 80da81a279b368401cbc20a36762440d 8a0034a62f366980ddffa62f42f5cbc4 8000000000000000ddffa62f42f60000 8a0034a62f366980ddffa62f42f5cbc4 fpscr=00000000
+vrintn.f32.f32 q0, q2 16afebd24d3fec09f07b6f1b077b56d3 3a24c1bf84d70271fcb68221b20b1691 0000000080000000fcb6822180000000 3a24c1bf84d70271fcb68221b20b1691 fpscr=00000000
+vrintn.f32.f32 q0, q2 b2586175cd066a5c099bf93b119cc2d4 d9467fc5d4d848d30e77fef50b39aca6 d9467fc5d4d848d30000000000000000 d9467fc5d4d848d30e77fef50b39aca6 fpscr=00000000
+vrintn.f32.f32 q0, q2 1fc56ebc564cfe597bb1a15e16cc0718 1ce57b9e20f0e2850ddadb360a3f0892 00000000000000000000000000000000 1ce57b9e20f0e2850ddadb360a3f0892 fpscr=00000000
+vrintn.f32.f32 q0, q2 bf4391d1fd340b91f5ce108ac48b5a49 83b44ea230a85234cc3fea1f38446633 8000000000000000cc3fea1f00000000 83b44ea230a85234cc3fea1f38446633 fpscr=00000000
+vrinta.f32.f32 q3, q5 e55f7dfd60db0b5b01c3d13cbf2fa615 1266af0b6a50fbe023fa6fbf0c80d5a0 000000006a50fbe00000000000000000 1266af0b6a50fbe023fa6fbf0c80d5a0 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrinta.f32.f32 q3, q5 ebfec532eb33e2410de67479eb33e241 3a86e50c09b0ca418df8ee522424a1ef 00000000000000008000000000000000 3a86e50c09b0ca418df8ee522424a1ef fpscr=00000000
+vrinta.f32.f32 q3, q5 90202eea830bd494e243ef8527c0cdba 0ded32a6a943e67df269d2731b38b470 0000000080000000f269d27300000000 0ded32a6a943e67df269d2731b38b470 fpscr=00000000
+vrinta.f32.f32 q3, q5 86e1c495f258fd7f79491e9cc5867d93 65d26957470d334166584a910ba6cee1 65d26957470d330066584a9100000000 65d26957470d334166584a910ba6cee1 fpscr=00000000
+vrinta.f32.f32 q3, q5 c5a0ecea4056ae0bac28bd09115212fb 92247d50ae577afead1cc4a45127f0a7 8000000080000000800000005127f0a7 92247d50ae577afead1cc4a45127f0a7 fpscr=00000000
+vrinta.f32.f32 q3, q5 d01516c25937ac1de0c22af31f7ac72f 3271cc824ff7f103c3b7f8238aa0d91a 000000004ff7f103c3b8000080000000 3271cc824ff7f103c3b7f8238aa0d91a fpscr=00000000
+vrinta.f32.f32 q3, q5 4c52dc9e95644e65a885671fdc725897 d8eb2e394da30e846e5c2ddd18e9e87c d8eb2e394da30e846e5c2ddd00000000 d8eb2e394da30e846e5c2ddd18e9e87c fpscr=00000000
+vrinta.f32.f32 q3, q5 fc95acbd7b72c8bb60a5e1815f6f90b4 455bed46968eb7ca01125a5861e09d1b 455bf000800000000000000061e09d1b 455bed46968eb7ca01125a5861e09d1b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrinta.f32.f32 q3, q5 64a09e69d26093500f99bdf81137af78 f49f63d20d24ef660d24ef66ae9f10e0 f49f63d2000000000000000080000000 f49f63d20d24ef660d24ef66ae9f10e0 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[3]
+vrinta.f32.f32 q3, q5 ceb32b8efa3dc796110ae728110ae728 83523496f373dd2cc66d357fdac68594 80000000f373dd2cc66d3400dac68594 83523496f373dd2cc66d357fdac68594 fpscr=00000000
+vrinta.f32.f32 q3, q5 0222d095d2c30a73d115c6375e41e4b4 caa8f2573d115022c5331ac241985004 caa8f25800000000c533200041980000 caa8f2573d115022c5331ac241985004 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[1]
+vrinta.f32.f32 q3, q5 b28dadb2bd1b3ef578ee2808bd1b3ef5 67b24f2db35da93a5a7354415a735441 67b24f2d800000005a7354415a735441 67b24f2db35da93a5a7354415a735441 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrinta.f32.f32 q3, q5 635557fea45b96bc3603e6eeb8cabbc8 d849f92f6df06ceca8319df6c8382fa8 d849f92f6df06cec80000000c8382fc0 d849f92f6df06ceca8319df6c8382fa8 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrinta.f32.f32 q3, q5 50572d3d51128721511287219f170dd9 d81963f4ba8478c85982b98afd09b61f d81963f4800000005982b98afd09b61f d81963f4ba8478c85982b98afd09b61f fpscr=00000000
+vrinta.f32.f32 q3, q5 8985fae5b18c9b419db396224096b2a8 e44618e6f010410ba6897b533f275ca3 e44618e6f010410b800000003f800000 e44618e6f010410ba6897b533f275ca3 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrinta.f32.f32 q3, q5 98c0d983cfb8dca071eb3866e771d67e df6e8e7afb95368909003e8c44c17e71 df6e8e7afb9536890000000044c18000 df6e8e7afb95368909003e8c44c17e71 fpscr=00000000
+vrinta.f32.f32 q3, q5 62512c024838d5768b6182b836c68c38 c12e09b044d1748e05513f60f2dd7f3c c130000044d1800000000000f2dd7f3c c12e09b044d1748e05513f60f2dd7f3c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[3]
+vrinta.f32.f32 q3, q5 b12bf3350e472ebd4810481a4810481a 0336aed70336aed74a880aa6679bf241 00000000000000004a880aa6679bf241 0336aed70336aed74a880aa6679bf241 fpscr=00000000
+vrinta.f32.f32 q3, q5 6c4f49a9dca2dcf04a70ff18f7faef18 d8445e95e24a298ccea878073e39feb8 d8445e95e24a298ccea8780700000000 d8445e95e24a298ccea878073e39feb8 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrinta.f32.f32 q3, q5 8bed8f8ae9553513dae94025a2759965 bf70ee2fd66f39e32e3145fdf16cc143 bf800000d66f39e300000000f16cc143 bf70ee2fd66f39e32e3145fdf16cc143 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrinta.f32.f32 q3, q5 188dcaf6f508dd4aa877ab8d4aeff90b 32a9318d3b0e03018537ba19c5c09c06 000000000000000080000000c5c0a000 32a9318d3b0e03018537ba19c5c09c06 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vrinta.f32.f32 q3, q5 d5ed875b5950ff955950ff95ebe421f5 ddc5d70914ab490fee4e37e814ab490f ddc5d70900000000ee4e37e800000000 ddc5d70914ab490fee4e37e814ab490f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrinta.f32.f32 q3, q5 2ae659f86194911a6cdf26a92ae659f8 bbede7d77ee142befcbcda23e6705e48 800000007ee142befcbcda23e6705e48 bbede7d77ee142befcbcda23e6705e48 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vrinta.f32.f32 q3, q5 b04a659190296ff5bd74a971f3466260 5f49645b72b8042ac6ed98975f49645b 5f49645b72b8042ac6ed98005f49645b 5f49645b72b8042ac6ed98975f49645b fpscr=00000000
+vrinta.f32.f32 q3, q5 ad5f1817379f0f305a37cdd6156fab2c 974680a9068f0d611f84b1734372f6f5 80000000000000000000000043730000 974680a9068f0d611f84b1734372f6f5 fpscr=00000000
+vrinta.f32.f32 q3, q5 b92a73ee46e2eb82dd672668e8a5e995 eebc00091dbc00ac0636b818cfef8098 eebc00090000000000000000cfef8098 eebc00091dbc00ac0636b818cfef8098 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrinta.f32.f32 q3, q5 7eb1ae68b45aa237065c12a5fb8113a3 be53eac3129f36a889d0cebb554e8dde 800000000000000080000000554e8dde be53eac3129f36a889d0cebb554e8dde fpscr=00000000
+vrinta.f32.f32 q3, q5 b654b6e992dc0fa5933f44e664aecd2c 037442853f722e90864f7210a1113964 000000003f8000008000000080000000 037442853f722e90864f7210a1113964 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrinta.f32.f32 q3, q5 249056d67d62502e13f884bb281a492f 0882c6fee88193c6e54a90289b436ced 00000000e88193c6e54a902880000000 0882c6fee88193c6e54a90289b436ced fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: 17920 calls, 18522 iters
+vrinta.f32.f32 q3, q5 0843fb8b7f631793c1eb87d0f0e0fabc ebe28c3595f1ec103f04d28a95f1ec10 ebe28c35800000003f80000080000000 ebe28c3595f1ec103f04d28a95f1ec10 fpscr=00000000
+vrinta.f32.f32 q3, q5 ad67a6ab42f28ca7e9b6e3b46edac8ac b16157c8fe13b9ba6b95ef7ce243a229 80000000fe13b9ba6b95ef7ce243a229 b16157c8fe13b9ba6b95ef7ce243a229 fpscr=00000000
+vrinta.f32.f32 q3, q5 e592cfc247c07e323d19b51dd27b4fc1 8c5f46a3be64e87cf6dc40707567d11d 8000000080000000f6dc40707567d11d 8c5f46a3be64e87cf6dc40707567d11d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[1] = v->u32[3]
+vrinta.f32.f32 q3, q5 8d065dcb6c6fd76637ff5be16c6fd766 7b75e0df0629251a24862035b8edae45 7b75e0df000000000000000080000000 7b75e0df0629251a24862035b8edae45 fpscr=00000000
+vrinta.f32.f32 q3, q5 b527f9842ff5f683e5ed1e2cb89820a8 617dd01682ee9791a5ef50bc6b9227e3 617dd01680000000800000006b9227e3 617dd01682ee9791a5ef50bc6b9227e3 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrinta.f32.f32 q3, q5 f5b546f5c3fbd390f7ad6463cc8a0567 ccc66351be81d8b7be81d8b7a2040299 ccc66351800000008000000080000000 ccc66351be81d8b7be81d8b7a2040299 fpscr=00000000
+vrinta.f32.f32 q3, q5 04136b0e428c6ae1f237b2608d1ee3a4 8b23de8eb07f7f1c2773a08341355ffc 80000000800000000000000041300000 8b23de8eb07f7f1c2773a08341355ffc fpscr=00000000
+vrinta.f32.f32 q3, q5 22b174ac54310cdc6db04462bacc8e8b a1db82b79b6d4a4cdac27a6d38890c89 8000000080000000dac27a6d00000000 a1db82b79b6d4a4cdac27a6d38890c89 fpscr=00000000
+vrinta.f32.f32 q3, q5 f4e2f5b1dd8ebc4e4dde464d7b44e018 5dfd0e47fb61d63295367dbc1f3f9d19 5dfd0e47fb61d6328000000000000000 5dfd0e47fb61d63295367dbc1f3f9d19 fpscr=00000000
+vrinta.f32.f32 q3, q5 57c781c113012677c6d833c14ef87941 22fa1e0ba6d04319cc6d4d7457e1563c 0000000080000000cc6d4d7457e1563c 22fa1e0ba6d04319cc6d4d7457e1563c fpscr=00000000
+vrinta.f32.f32 q3, q5 cbb42f7969da04f9464b7d1b3e6d3ae5 304137ec5e42dd75d48fda28f45fc8dd 000000005e42dd75d48fda28f45fc8dd 304137ec5e42dd75d48fda28f45fc8dd fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrinta.f32.f32 q3, q5 9828ceb65679f24ed6b403feee9e597f 4fde45a2a19bb833cd3c1cf1c79bb3d4 4fde45a280000000cd3c1cf1c79bb400 4fde45a2a19bb833cd3c1cf1c79bb3d4 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrinta.f32.f32 q3, q5 1dda5f85f8cf55be2c7373ceb7c34f49 2455825ebefd30e113ace71f9588b2e7 00000000800000000000000080000000 2455825ebefd30e113ace71f9588b2e7 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrinta.f32.f32 q3, q5 5d751f25c3f7ff715d751f25cafc6f24 2c396edef18b375060e893b1cc4f0afd 00000000f18b375060e893b1cc4f0afd 2c396edef18b375060e893b1cc4f0afd fpscr=00000000
+vrinta.f32.f32 q3, q5 f2d1df02f90cb4c52cb9eb74b9d3ade7 98ce7f030c6ae196049823b51f0b0759 80000000000000000000000000000000 98ce7f030c6ae196049823b51f0b0759 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrinta.f32.f32 q3, q5 9e3f369fc8e6697c6e4204e68fcf3d7b 614f56b625739641ba26243f25739641 614f56b6000000008000000000000000 614f56b625739641ba26243f25739641 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrinta.f32.f32 q3, q5 b9843c2648a3819a2823afa879cb9610 8da9c06eb4a3cb38b4a3cb38727e964f 800000008000000080000000727e964f 8da9c06eb4a3cb38b4a3cb38727e964f fpscr=00000000
+vrinta.f32.f32 q3, q5 c8554268572eb2db2d7cb115310af707 255e7ca132d9c0cc52bc0229e71655f6 000000000000000052bc0229e71655f6 255e7ca132d9c0cc52bc0229e71655f6 fpscr=00000000
+vrinta.f32.f32 q3, q5 24138e0db6bd59fe422c5d963bef7f41 b380a1ca6ba7770fa02e8a994a59f23b 800000006ba7770f800000004a59f23c b380a1ca6ba7770fa02e8a994a59f23b fpscr=00000000
+vrinta.f32.f32 q3, q5 ce6096074331994c52476eaad4eef0ba c9df25f0fcdbcad14e74cd929d80d0e5 c9df25f0fcdbcad14e74cd9280000000 c9df25f0fcdbcad14e74cd929d80d0e5 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrinta.f32.f32 q3, q5 3172103df9d2e04ed5907710f9d2e04e dfba52098b114ec2ebeeb001eb43ae26 dfba520980000000ebeeb001eb43ae26 dfba52098b114ec2ebeeb001eb43ae26 fpscr=00000000
+vrintp.f32.f32 q6, q8 5fa2884d916ceb3f4b4bec15270dae51 f6580922bf09cdd58e1b26b8cc779146 f65809228000000080000000cc779146 f6580922bf09cdd58e1b26b8cc779146 fpscr=00000000
+vrintp.f32.f32 q6, q8 0161e59cf0758c58756c2cecdebb8338 06c8ecb21af96b2e6f7c8f8a2fb66468 3f8000003f8000006f7c8f8a3f800000 06c8ecb21af96b2e6f7c8f8a2fb66468 fpscr=00000000
+vrintp.f32.f32 q6, q8 bed1e9d2f92b0713d26ba53f6c19f36e 8ed37f32b7fe83a0d8a18947d43a163e 8000000080000000d8a18947d43a163e 8ed37f32b7fe83a0d8a18947d43a163e fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintp.f32.f32 q6, q8 22c3d15c11cd1bc23f4d8c2be4e4b362 1848b395e68c5e2ba7bb8b689032c24c 3f800000e68c5e2b8000000080000000 1848b395e68c5e2ba7bb8b689032c24c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintp.f32.f32 q6, q8 eca38a771f3b13f523a890b9de7ab329 9bc6a302038cea3f36628529c5ae38dd 800000003f8000003f800000c5ae3800 9bc6a302038cea3f36628529c5ae38dd fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintp.f32.f32 q6, q8 8a1398c945700a708a079ffdee0c1442 db6b2e0ce781c176d59f29726858b545 db6b2e0ce781c176d59f29726858b545 db6b2e0ce781c176d59f29726858b545 fpscr=00000000
+vrintp.f32.f32 q6, q8 dcf272931f168fa8ccbbd40ca35713d2 ec3cd0f8d001ff6cd42dd8bb91197a7c ec3cd0f8d001ff6cd42dd8bb80000000 ec3cd0f8d001ff6cd42dd8bb91197a7c fpscr=00000000
+vrintp.f32.f32 q6, q8 8ff2794eace96f2dd0c718e5296d6899 b929c608056069f0c9b2e1a9ba6f6134 800000003f800000c9b2e1a880000000 b929c608056069f0c9b2e1a9ba6f6134 fpscr=00000000
+vrintp.f32.f32 q6, q8 b1e3caacb79b760ec0ad2de53840052a 0c3aa35be42a73f848c0a7e1f793e202 3f800000e42a73f848c0a800f793e202 0c3aa35be42a73f848c0a7e1f793e202 fpscr=00000000
+vrintp.f32.f32 q6, q8 836156c4d5bc5eb873d753c1fa9c8d1a e225aaad50f1fa51f1350a7f183ee8ad e225aaad50f1fa51f1350a7f3f800000 e225aaad50f1fa51f1350a7f183ee8ad fpscr=00000000
+vrintp.f32.f32 q6, q8 b88e337361be87a7b94fd0eda106f0c8 298ff997870a96a78a61e15e402bed7f 3f800000800000008000000040400000 298ff997870a96a78a61e15e402bed7f fpscr=00000000
+vrintp.f32.f32 q6, q8 ec79d6d80ff952820f5a734b3ff900ab 1cf8744c20981b609a3718151d6ab960 3f8000003f800000800000003f800000 1cf8744c20981b609a3718151d6ab960 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintp.f32.f32 q6, q8 ebe13821581066892488eb466b95fb0d 5c563adb5d7a845d5c563adb7a8991d8 5c563adb5d7a845d5c563adb7a8991d8 5c563adb5d7a845d5c563adb7a8991d8 fpscr=00000000
+vrintp.f32.f32 q6, q8 e888e360cdc7c5bac7734f110d46d59b 042011d75775de1a359516fe573d3aaa 3f8000005775de1a3f800000573d3aaa 042011d75775de1a359516fe573d3aaa fpscr=00000000
+vrintp.f32.f32 q6, q8 cd1c72ed662224e6d79fd9a3eb87b0dc fc1f483eb23ebe1da197d3d749c1aa66 fc1f483e800000008000000049c1aa68 fc1f483eb23ebe1da197d3d749c1aa66 fpscr=00000000
+vrintp.f32.f32 q6, q8 9c7690c4ed618f4137ab2c82d54f05fc 6104e2858b1605eb54e671a15a6537a4 6104e2858000000054e671a15a6537a4 6104e2858b1605eb54e671a15a6537a4 fpscr=00000000
+vrintp.f32.f32 q6, q8 3845bc0f37f27d2655341ec54af78944 171f66d191f9b367f64db595f3575366 3f80000080000000f64db595f3575366 171f66d191f9b367f64db595f3575366 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintp.f32.f32 q6, q8 b6c4e4131038eaeeed872ac1b95bf2ac 1bdc83bdedf0f530fdcf94673c8fd0b7 3f800000edf0f530fdcf94673f800000 1bdc83bdedf0f530fdcf94673c8fd0b7 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintp.f32.f32 q6, q8 bc33f0d4ce303f7501979f16ce303f75 d3f72e45075f7bd2eea1d9eaf1f691ff d3f72e453f800000eea1d9eaf1f691ff d3f72e45075f7bd2eea1d9eaf1f691ff fpscr=00000000
+vrintp.f32.f32 q6, q8 e5e4ac278b972270639f69c7743199ac b55c99fdb47bf6700edcbe3cbc2d541c 80000000800000003f80000080000000 b55c99fdb47bf6700edcbe3cbc2d541c fpscr=00000000
+vrintp.f32.f32 q6, q8 c56cd21be9c6588a4885612b1f7dc162 7a27338dd055a900c917184bcbb98c10 7a27338dd055a900c9171840cbb98c10 7a27338dd055a900c917184bcbb98c10 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintp.f32.f32 q6, q8 c8016d98c8016d9863176249e5b4d743 999619d588cb09a422285edba1b8f22a 80000000800000003f80000080000000 999619d588cb09a422285edba1b8f22a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintp.f32.f32 q6, q8 870e15e593e71848773796f24c2db1b7 9ba4fe046eb5e2ed49d5288566df3d4e 800000006eb5e2ed49d5288866df3d4e 9ba4fe046eb5e2ed49d5288566df3d4e fpscr=00000000
+vrintp.f32.f32 q6, q8 28de134f0ec5ccff3651c0065af6cba4 c6bbe5dc698ab51e3633337d3a9eadc2 c6bbe400698ab51e3f8000003f800000 c6bbe5dc698ab51e3633337d3a9eadc2 fpscr=00000000
+vrintp.f32.f32 q6, q8 4894f196ef6c22727cb2e8a3f0961d5b 7f01e68daceab3aa9312cec6db91c94d 7f01e68d8000000080000000db91c94d 7f01e68daceab3aa9312cec6db91c94d fpscr=00000000
+vrintp.f32.f32 q6, q8 7f1086124cddc3a439ef6f87f8053adc 75746ea5492ab43e79346e8ce8c0c6fd 75746ea5492ab44079346e8ce8c0c6fd 75746ea5492ab43e79346e8ce8c0c6fd fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[3] = v->u32[0]
+vrintp.f32.f32 q6, q8 f37d22e75be88653096a97c36746576e 96dcdcddf00b45bf78253c4a78253c4a 80000000f00b45bf78253c4a78253c4a 96dcdcddf00b45bf78253c4a78253c4a fpscr=00000000
+vrintp.f32.f32 q6, q8 515f104c9a2a0e8f0bd2950f8830b0a1 b452151cb8e8323b5b9c653b2e8a84da 80000000800000005b9c653b3f800000 b452151cb8e8323b5b9c653b2e8a84da fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintp.f32.f32 q6, q8 0efdf0110efdf01177ec6da169a7b723 375f9bb037f72c314b7b3c83fcfa1232 3f8000003f8000004b7b3c83fcfa1232 375f9bb037f72c314b7b3c83fcfa1232 fpscr=00000000
+vrintp.f32.f32 q6, q8 aa8cb0570fcd963a6b75bfbf8f2abcf7 ebb442a390e1802ace32868822cd01bd ebb442a380000000ce3286883f800000 ebb442a390e1802ace32868822cd01bd fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[3]
+vrintp.f32.f32 q6, q8 25075fd970daef7725075fd9938cfb7e ebb34c111dc7fd6eebb34c113d8652e3 ebb34c113f800000ebb34c113f800000 ebb34c111dc7fd6eebb34c113d8652e3 fpscr=00000000
+vrintp.f32.f32 q6, q8 baf2774c166e8e2a2cd9fb9bad33c1c7 791dc138d45906f17eb58983f030c3f9 791dc138d45906f17eb58983f030c3f9 791dc138d45906f17eb58983f030c3f9 fpscr=00000000
+vrintp.f32.f32 q6, q8 65e7fd815f947c6f6fddb7f91427f79d 02825f233328d94ac5ea7815b3809e7f 3f8000003f800000c5ea780080000000 02825f233328d94ac5ea7815b3809e7f fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[0]
+vrintp.f32.f32 q6, q8 6810e1761c8b588f6c46b6a7f8182080 9e542db5d52259b35b51fc5d8c1d2cff 80000000d52259b35b51fc5d80000000 9e542db5d52259b35b51fc5d8c1d2cff fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintp.f32.f32 q6, q8 2ed5b54a4288fd86cf3589c3de3ab5de c0c7e2dc8aed850af75e06a73f64b63d c0c0000080000000f75e06a73f800000 c0c7e2dc8aed850af75e06a73f64b63d fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintp.f32.f32 q6, q8 6eadd0c7793034f390693d2ae6b553c3 23262fb70c7505238656428623262fb7 3f8000003f800000800000003f800000 23262fb70c7505238656428623262fb7 fpscr=00000000
+vrintp.f32.f32 q6, q8 543ee8357bb6001826aa1ed8e2e3c186 d1025b9ad678676a98e88d543b2e11de d1025b9ad678676a800000003f800000 d1025b9ad678676a98e88d543b2e11de fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintp.f32.f32 q6, q8 eab7a1d27dcd47b494bf5f0e4a7d6c0d 8384d140a9213016725942d5447ff7b3 8000000080000000725942d544800000 8384d140a9213016725942d5447ff7b3 fpscr=00000000
+vrintp.f32.f32 q6, q8 c615de2bf2d8b858fe3662695b7c72c6 df1411d817deb1e55bba42940a1e9018 df1411d83f8000005bba42943f800000 df1411d817deb1e55bba42940a1e9018 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintp.f32.f32 q6, q8 1210143c9de965077100f7d3558162f2 854d9e64687c7968854d9e6438877bba 80000000687c7968800000003f800000 854d9e64687c7968854d9e6438877bba fpscr=00000000
+vrintp.f32.f32 q6, q8 c426a3490633f34d53d2ad1cbba1726c 68ab601c414f8f28356873d3a0827d16 68ab601c415000003f80000080000000 68ab601c414f8f28356873d3a0827d16 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintp.f32.f32 q6, q8 87fd445ecb2ec16c984ba07640b64412 4c6d8b175e90aa9b949c33508207a258 4c6d8b175e90aa9b8000000080000000 4c6d8b175e90aa9b949c33508207a258 fpscr=00000000
+vrintp.f32.f32 q6, q8 8d4d8269151369bf10db8d858adb51b4 fa3ef5d5705c7a788d4f2a320ef0683d fa3ef5d5705c7a78800000003f800000 fa3ef5d5705c7a788d4f2a320ef0683d fpscr=00000000
+randV128: 18176 calls, 18788 iters
+vrintp.f32.f32 q6, q8 8661c49aa9ff3b4921474c278a77d5ea d53df7b0d5311e1f9f40d9d812997a1c d53df7b0d5311e1f800000003f800000 d53df7b0d5311e1f9f40d9d812997a1c fpscr=00000000
+vrintp.f32.f32 q6, q8 6f9af687aaf3ed40357329a560c9d705 8f34c60ab7e8beadea4ca295218d9d57 8000000080000000ea4ca2953f800000 8f34c60ab7e8beadea4ca295218d9d57 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintp.f32.f32 q6, q8 2526d6e6b0e9a1a03c7e9928110b2bde 1bc52ed933a3e004793897a49a6fe218 3f8000003f800000793897a480000000 1bc52ed933a3e004793897a49a6fe218 fpscr=00000000
+vrintp.f32.f32 q6, q8 0fe17744793d87a3e6d532f53dc8fd22 b7b075ca83ba24f1f3d495b9bd1721a8 8000000080000000f3d495b980000000 b7b075ca83ba24f1f3d495b9bd1721a8 fpscr=00000000
+vrintp.f32.f32 q6, q8 6eead41e4bfd04494c14c463b2094ef4 fa8af40c29a913f115f2781b16249acf fa8af40c3f8000003f8000003f800000 fa8af40c29a913f115f2781b16249acf fpscr=00000000
+vrintp.f32.f32 q6, q8 979cfd05899a69c2ce492d08c6c6aef7 9fbf83b872699d16741ffc2bba8940eb 8000000072699d16741ffc2b80000000 9fbf83b872699d16741ffc2bba8940eb fpscr=00000000
+vrintp.f32.f32 q6, q8 60db40c30cfb2182489246c57628d0e1 e6829e2ac577a8e548a32661f7f48d58 e6829e2ac577a00048a32680f7f48d58 e6829e2ac577a8e548a32661f7f48d58 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintm.f32.f32 q9, q11 062858ba57aaf90c57aaf90c8b304d89 9d96e223f825fb34d8b83049a361dc1a bf800000f825fb34d8b83049bf800000 9d96e223f825fb34d8b83049a361dc1a fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintm.f32.f32 q9, q11 0b8fad553a25372d0ad64e0bf8217b51 b7a29d10ab1e1afe652f9a9e3e824015 bf800000bf800000652f9a9e00000000 b7a29d10ab1e1afe652f9a9e3e824015 fpscr=00000000
+vrintm.f32.f32 q9, q11 a02f6a53bb99c5c03bbb889165fa5084 c02ac530a2b5d16a8531507e830eb444 c0400000bf800000bf800000bf800000 c02ac530a2b5d16a8531507e830eb444 fpscr=00000000
+vrintm.f32.f32 q9, q11 354545f8190c4ecb1a546dcfa68196b6 db101a05de357b4f7a06f899a3e5ed98 db101a05de357b4f7a06f899bf800000 db101a05de357b4f7a06f899a3e5ed98 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintm.f32.f32 q9, q11 0de14b6651770f76eb340f081464e51d ef288d0fe80d03eefe4f1542ef288d0f ef288d0fe80d03eefe4f1542ef288d0f ef288d0fe80d03eefe4f1542ef288d0f fpscr=00000000
+vrintm.f32.f32 q9, q11 eb60fdefac02898c76a144aa85fff407 2f4975f42f36a990c7141d1806fa805a 0000000000000000c7141e0000000000 2f4975f42f36a990c7141d1806fa805a fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[0]
+vrintm.f32.f32 q9, q11 08c53472282d647f5004394ffa8bec3e 8b3062f577a760438ecada108ecada10 bf80000077a76043bf800000bf800000 8b3062f577a760438ecada108ecada10 fpscr=00000000
+vrintm.f32.f32 q9, q11 86081e5b71e03be8f6937b65b080d7d7 51fd9a8b57f590d99d2de92cb142b867 51fd9a8b57f590d9bf800000bf800000 51fd9a8b57f590d99d2de92cb142b867 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintm.f32.f32 q9, q11 181faa92181faa928854bc9d44fd83ac 6a2df7bfafed21c7c901d49a88814216 6a2df7bfbf800000c901d4a0bf800000 6a2df7bfafed21c7c901d49a88814216 fpscr=00000000
+vrintm.f32.f32 q9, q11 ca6496cafcdbd807b36fc0452875cc1c 8e8cc8a90e1bd8945e8ab9238a564565 bf800000000000005e8ab923bf800000 8e8cc8a90e1bd8945e8ab9238a564565 fpscr=00000000
+vrintm.f32.f32 q9, q11 6c08345e95648cd4a96b60cf615e669b 0dc20a00a93aae4991e4192ac5057bf3 00000000bf800000bf800000c5058000 0dc20a00a93aae4991e4192ac5057bf3 fpscr=00000000
+vrintm.f32.f32 q9, q11 3ec71543227fe8fbc2a1dac45a2291d8 82c8b6ef5fd20c298983e9b752691960 bf8000005fd20c29bf80000052691960 82c8b6ef5fd20c298983e9b752691960 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[1] = v->u32[0]
+vrintm.f32.f32 q9, q11 8b39173d15fc6afc570a61e5317b5ffb ff35b1d1bfe9753cff35b1d18d45dad4 ff35b1d1c0000000ff35b1d1bf800000 ff35b1d1bfe9753cff35b1d18d45dad4 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintm.f32.f32 q9, q11 7b74901561e0810f28d82f0d697ad2c6 40417001951d5c663304af9dadc19413 40400000bf80000000000000bf800000 40417001951d5c663304af9dadc19413 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintm.f32.f32 q9, q11 a1aa2e755611d3998f82b75b9ccb2056 47c35efe8fda82048fda820464a81ee7 47c35e80bf800000bf80000064a81ee7 47c35efe8fda82048fda820464a81ee7 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintm.f32.f32 q9, q11 3e59b01ebe71be191077e3cc038aea33 532f038ed7ec89c10f62ecb7d7ec89c1 532f038ed7ec89c100000000d7ec89c1 532f038ed7ec89c10f62ecb7d7ec89c1 fpscr=00000000
+vrintm.f32.f32 q9, q11 4bde568a223c3eeac872035f99b16953 c6b8605f416b4d38e2d54e46f5f2ced8 c6b8620041600000e2d54e46f5f2ced8 c6b8605f416b4d38e2d54e46f5f2ced8 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintm.f32.f32 q9, q11 1b89f5ed115d95ef15df5ca33182fa09 68b9236ac63c060dbb62dfeba0d25fdc 68b9236ac63c0800bf800000bf800000 68b9236ac63c060dbb62dfeba0d25fdc fpscr=00000000
+vrintm.f32.f32 q9, q11 7a226ac5421eff05b2b0b974ce074971 7c914bd6f41882208dabb6b74e86e0b2 7c914bd6f4188220bf8000004e86e0b2 7c914bd6f41882208dabb6b74e86e0b2 fpscr=00000000
+vrintm.f32.f32 q9, q11 aa0f3946c6c97be156f07f9ff1ebff74 a93ae96e8f8782c92c2293daae65f607 bf800000bf80000000000000bf800000 a93ae96e8f8782c92c2293daae65f607 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintm.f32.f32 q9, q11 77e60d4259a8d8dbaff4e612f9c17bb9 341a27fabb7654464512154d9134fac8 00000000bf80000045121000bf800000 341a27fabb7654464512154d9134fac8 fpscr=00000000
+vrintm.f32.f32 q9, q11 44842d18ca97c2e7a9ae720b6fdb1504 affab653f987010e539ea695e1ceff12 bf800000f987010e539ea695e1ceff12 affab653f987010e539ea695e1ceff12 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintm.f32.f32 q9, q11 e61c67d18c64ed4cbf1f2658bb3bd799 9ecdb6d26919c190494d3d13c7f0cb78 bf8000006919c190494d3d10c7f0cb80 9ecdb6d26919c190494d3d13c7f0cb78 fpscr=00000000
+vrintm.f32.f32 q9, q11 09e4d189fde26efdf1b9079253f689de 5085b75d80b400e4a7e478a330eb689f 5085b75dbf800000bf80000000000000 5085b75d80b400e4a7e478a330eb689f fpscr=00000000
+vrintm.f32.f32 q9, q11 45b65c84d1091f4005174601907e936d f920d68f569b856a8407fb0253033b77 f920d68f569b856abf80000053033b77 f920d68f569b856a8407fb0253033b77 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintm.f32.f32 q9, q11 0f1274c07e91654f7e91654f6fed4d88 64693bbf64900cdb2c7e835a94fcfa36 64693bbf64900cdb00000000bf800000 64693bbf64900cdb2c7e835a94fcfa36 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[1]
+vrintm.f32.f32 q9, q11 f5421f42d75ce75e7ca1765b9b0951ed b16144c3c85138a2141dbdcec85138a2 bf800000c85138c000000000c85138c0 b16144c3c85138a2141dbdcec85138a2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintm.f32.f32 q9, q11 cc6ad70be8d453f233bba44d4e7a6d7e 0bc772280bc772280794585932302ff1 00000000000000000000000000000000 0bc772280bc772280794585932302ff1 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[0]
+vrintm.f32.f32 q9, q11 2416e2950337e2d97d76d75523b84d02 3c9d3f46ad7ee78f9ed76e32ad7ee78f 00000000bf800000bf800000bf800000 3c9d3f46ad7ee78f9ed76e32ad7ee78f fpscr=00000000
+vrintm.f32.f32 q9, q11 fd95e5158a0e709b17bdf3dc3ecbf671 00fe2f53c7e111b9a5c6b0de5782feb2 00000000c7e11200bf8000005782feb2 00fe2f53c7e111b9a5c6b0de5782feb2 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintm.f32.f32 q9, q11 e8e9186d6430edf1118d7feea0dddf0d 0a0d47687baf7adce0feeea19f6af475 000000007baf7adce0feeea1bf800000 0a0d47687baf7adce0feeea19f6af475 fpscr=00000000
+vrintm.f32.f32 q9, q11 3e30e769426c59bf15cae7d0cf63a68a a673076860030dac0e3f1a75a277a6a2 bf80000060030dac00000000bf800000 a673076860030dac0e3f1a75a277a6a2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintm.f32.f32 q9, q11 2428b5df6eb91d6f2428b5df8b1267d4 2dbcaa44d79d745bcde7b08e69ad7845 00000000d79d745bcde7b08e69ad7845 2dbcaa44d79d745bcde7b08e69ad7845 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[1]
+vrintm.f32.f32 q9, q11 efb27d66cb7c181a620c3170cb7c181a 4b8e3b6c044933b86c4fc7611993f6e7 4b8e3b6c000000006c4fc76100000000 4b8e3b6c044933b86c4fc7611993f6e7 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintm.f32.f32 q9, q11 738ddb9b3f9a7af8738ddb9b43e95bda 7b3096fa587f12ee0a04f928dd4bb14c 7b3096fa587f12ee00000000dd4bb14c 7b3096fa587f12ee0a04f928dd4bb14c fpscr=00000000
+vrintm.f32.f32 q9, q11 d450c2972917da45f0918606dd5b0d0b 0927d3c790e6ca509b7c120320f3e7fa 00000000bf800000bf80000000000000 0927d3c790e6ca509b7c120320f3e7fa fpscr=00000000
+vrintm.f32.f32 q9, q11 22f5641a66c30b097f139266249fe863 aa039f1f79cbe5fb7d685aeaf84d61d6 bf80000079cbe5fb7d685aeaf84d61d6 aa039f1f79cbe5fb7d685aeaf84d61d6 fpscr=00000000
+vrintm.f32.f32 q9, q11 337e0a05fa0731632334e4d5445ad2a5 bbc7cf43c0612b2512c7e8f0871a7f39 bf800000c080000000000000bf800000 bbc7cf43c0612b2512c7e8f0871a7f39 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintm.f32.f32 q9, q11 bc1c9bc83cf0964d2e826238ce60310b cd92df742604d6efb79b520bb79b520b cd92df7400000000bf800000bf800000 cd92df742604d6efb79b520bb79b520b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintm.f32.f32 q9, q11 90d6fa80fa8b4be490d6fa803fd8bcf3 2188367fe3e0e053269cf220dfbe7eef 00000000e3e0e05300000000dfbe7eef 2188367fe3e0e053269cf220dfbe7eef fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintm.f32.f32 q9, q11 3f0ded072a3f2de2cd848decfce8c24d 4e9568fe1ab8e097b56e293110459a64 4e9568fe00000000bf80000000000000 4e9568fe1ab8e097b56e293110459a64 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[3]
+vrintm.f32.f32 q9, q11 efe0e29f5523c45b78acc01f5d2245ba 83f385c3034ee0dba030f8a4dccb5ef4 bf80000000000000bf800000dccb5ef4 83f385c3034ee0dba030f8a4dccb5ef4 fpscr=00000000
+vrintm.f32.f32 q9, q11 b5e411429fca1a1cff4406dd3e3fc34d b94701e31565278e35614864dddb5106 bf8000000000000000000000dddb5106 b94701e31565278e35614864dddb5106 fpscr=00000000
+vrintm.f32.f32 q9, q11 e40bfc6d1827316d45643da90ae52f40 38caa3c8830d3d7106690ff6a81d4440 00000000bf80000000000000bf800000 38caa3c8830d3d7106690ff6a81d4440 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[2] = v->u32[1]
+vrintm.f32.f32 q9, q11 57d743e253ad73e12d858cc1462bb5a0 a9d8e77fa9d8e77f4b9d0d91d7601c89 bf800000bf8000004b9d0d91d7601c89 a9d8e77fa9d8e77f4b9d0d91d7601c89 fpscr=00000000
+vrintm.f32.f32 q9, q11 7cf1564fa367ab2ea9526de0ccab8a18 af78ecaa3e6394a6c468e2955a40a5ba bf80000000000000c46900005a40a5ba af78ecaa3e6394a6c468e2955a40a5ba fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintm.f32.f32 q9, q11 4005222c4b5598e40898a925b64ac141 c8f7e5050c74221d13d3dff0ef77b6a7 c8f7e5200000000000000000ef77b6a7 c8f7e5050c74221d13d3dff0ef77b6a7 fpscr=00000000
+vrintm.f32.f32 q9, q11 e5d7aa036f8bde01a8869257c4ad1f48 36e85fe500c4afd41b12e1c02f93934e 00000000000000000000000000000000 36e85fe500c4afd41b12e1c02f93934e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintm.f32.f32 q9, q11 699e33fee65c61aa4c0a7b79ae41b1d7 6c4df2920b0b8605c0d69d07853710bc 6c4df29200000000c0e00000bf800000 6c4df2920b0b8605c0d69d07853710bc fpscr=00000000
+vrintm.f32.f32 q9, q11 f103d377c9490113e391525efc8b9ff8 afe53f586a18cc656d6b8f3122e0f375 bf8000006a18cc656d6b8f3100000000 afe53f586a18cc656d6b8f3122e0f375 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintz.f32.f32 q12, q14 d877010dd877010d4617bad4bdfc89bd e8cf05b47328c70181808b99dbb5acc7 e8cf05b47328c70180000000dbb5acc7 e8cf05b47328c70181808b99dbb5acc7 fpscr=00000000
+vrintz.f32.f32 q12, q14 9f8d052606394d2ddb5067baf270943a 53c13b95fb2bb34f3944feec4f789dc1 53c13b95fb2bb34f000000004f789dc1 53c13b95fb2bb34f3944feec4f789dc1 fpscr=00000000
+vrintz.f32.f32 q12, q14 9f80f28183f185fa76749ef66119b4b3 fa4cb2111bf2eadd16436e9d49263406 fa4cb211000000000000000049263400 fa4cb2111bf2eadd16436e9d49263406 fpscr=00000000
+vrintz.f32.f32 q12, q14 2c49ad0e56148cd9bfb7a8fe6aa32bb0 cd037e1b65658d2c6a94751f18761601 cd037e1b65658d2c6a94751f00000000 cd037e1b65658d2c6a94751f18761601 fpscr=00000000
+vrintz.f32.f32 q12, q14 258ad8c5b81d43bffc39ee5fb5c1cd11 c7ff7092965f4c83b406f1e71e07babc c7ff7080800000008000000000000000 c7ff7092965f4c83b406f1e71e07babc fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[1]
+vrintz.f32.f32 q12, q14 ac9b1355ac9b13552a90287cf1cf78f3 a5c8ba1a8834072b569f787a81b93292 8000000080000000569f787a80000000 a5c8ba1a8834072b569f787a81b93292 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vrintz.f32.f32 q12, q14 6e6d700ebe38e2f6be38e2f6844f745a 05cbfcf7b7b40093d8283db5d51eecda 0000000080000000d8283db5d51eecda 05cbfcf7b7b40093d8283db5d51eecda fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: 18432 calls, 19051 iters
+vrintz.f32.f32 q12, q14 c8e1e85f11a45b14b9f6cf3ce5c124b9 4e2d77fe1a365f81010734c0010734c0 4e2d77fe000000000000000000000000 4e2d77fe1a365f81010734c0010734c0 fpscr=00000000
+vrintz.f32.f32 q12, q14 a1458f960bd1078514076d0e0f03f32c d76ee389dbbfb213374f6cfc21b9111b d76ee389dbbfb2130000000000000000 d76ee389dbbfb213374f6cfc21b9111b fpscr=00000000
+vrintz.f32.f32 q12, q14 da0be4e4cd63ad08d458450b98ad930c 78ddd3f03921bafb5b3fcb90d0d0f5a3 78ddd3f0000000005b3fcb90d0d0f5a3 78ddd3f03921bafb5b3fcb90d0d0f5a3 fpscr=00000000
+vrintz.f32.f32 q12, q14 e1948ba6467d99015d3ac0687bbae352 93058d37d592d67e8f12837a42f57705 80000000d592d67e8000000042f40000 93058d37d592d67e8f12837a42f57705 fpscr=00000000
+vrintz.f32.f32 q12, q14 4197d10ce32815295d4699fab1ac2898 937974d5bf2a0278764ae8f0bb9e1e67 8000000080000000764ae8f080000000 937974d5bf2a0278764ae8f0bb9e1e67 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintz.f32.f32 q12, q14 276b21c5840b54703592a0577e4744b0 08c240f77d5110c55c7784d33a65eba5 000000007d5110c55c7784d300000000 08c240f77d5110c55c7784d33a65eba5 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintz.f32.f32 q12, q14 a60042bdfd100c4a08211eb3ef2c37b2 8d0616c43cf89dc50658e5d79865494d 80000000000000000000000080000000 8d0616c43cf89dc50658e5d79865494d fpscr=00000000
+vrintz.f32.f32 q12, q14 6bec14680b3454a9413f59faae9a7d64 92671b15c788623823035db49f5d7660 80000000c78862000000000080000000 92671b15c788623823035db49f5d7660 fpscr=00000000
+vrintz.f32.f32 q12, q14 e9706cb36deb329711203a16c2511939 8f249227335c584ed6071dbc6b1cc66b 8000000000000000d6071dbc6b1cc66b 8f249227335c584ed6071dbc6b1cc66b fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[0] = v->u32[2]
+vrintz.f32.f32 q12, q14 70577e6bcad4ded83e7720b7c09aba25 cd079df2916054a26b78daefcd079df2 cd079df2800000006b78daefcd079df2 cd079df2916054a26b78daefcd079df2 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintz.f32.f32 q12, q14 1a7f578de7c4382c1a7f578d5f8215fc 1ad904fdb83ba5a4862c2766d15f9829 000000008000000080000000d15f9829 1ad904fdb83ba5a4862c2766d15f9829 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintz.f32.f32 q12, q14 da6d2a55da6d2a553613133b37cf0104 e8c9837a5888b999ac263a54c1472185 e8c9837a5888b99980000000c1400000 e8c9837a5888b999ac263a54c1472185 fpscr=00000000
+vrintz.f32.f32 q12, q14 129c71218f8e383e0db9c70decd5d3e4 afe607fb438adb35e685a9d99c18061c 80000000438a8000e685a9d980000000 afe607fb438adb35e685a9d99c18061c fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintz.f32.f32 q12, q14 3e9b28018b030b153e9b28017d8abba9 418c07906549367ef961fc41e7ac5981 418800006549367ef961fc41e7ac5981 418c07906549367ef961fc41e7ac5981 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintz.f32.f32 q12, q14 8eddbf532e016b01f9dadb401236b53b 960ee53b2733f46ca57022c81a43742e 80000000000000008000000000000000 960ee53b2733f46ca57022c81a43742e fpscr=00000000
+vrintz.f32.f32 q12, q14 30f2eb51228990474ef29b297d37a8a3 416ea9d94aa348bf6b2dbf0de1dc2963 416000004aa348be6b2dbf0de1dc2963 416ea9d94aa348bf6b2dbf0de1dc2963 fpscr=00000000
+vrintz.f32.f32 q12, q14 40d383211561ba727d4813778eac4179 568233dbfce209898fd8dcc9f0e9eb79 568233dbfce2098980000000f0e9eb79 568233dbfce209898fd8dcc9f0e9eb79 fpscr=00000000
+vrintz.f32.f32 q12, q14 ce89d73af6812ff3d8470fb6a0cf764c 1bcdef8a45ec1db1724b5716af6c308b 0000000045ec1800724b571680000000 1bcdef8a45ec1db1724b5716af6c308b fpscr=00000000
+vrintz.f32.f32 q12, q14 bf2666723c7a88666014c727d8844afe 2afdedb20e6d20478da2e44b810975e2 00000000000000008000000080000000 2afdedb20e6d20478da2e44b810975e2 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+vrintz.f32.f32 q12, q14 7d414c03949feb13949feb13de6cac9d b7c9b6ddbb95dcf6de0ad60efc0d0c03 8000000080000000de0ad60efc0d0c03 b7c9b6ddbb95dcf6de0ad60efc0d0c03 fpscr=00000000
+vrintz.f32.f32 q12, q14 3fa3708a4dee069cb5f72373e56b35d6 ee514f507b74b39b8594c20728125410 ee514f507b74b39b8000000000000000 ee514f507b74b39b8594c20728125410 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintz.f32.f32 q12, q14 2b68d4343a334827750b04667c47f58b 455d7ba3c576cfe2b3dc22e6364abc8f 455d7000c576c0008000000000000000 455d7ba3c576cfe2b3dc22e6364abc8f fpscr=00000000
+vrintz.f32.f32 q12, q14 1eae16aaef48b5f2ba51609aeb22e142 4d107f39354483ea451f601ddfd74060 4d107f3900000000451f6000dfd74060 4d107f39354483ea451f601ddfd74060 fpscr=00000000
+vrintz.f32.f32 q12, q14 900160d4a3cc586b86dd0ed2209810b8 933002a54fd892f07f27b11e9d359da7 800000004fd892f07f27b11e80000000 933002a54fd892f07f27b11e9d359da7 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintz.f32.f32 q12, q14 455d742f6cd83dd8d67171e1b44a98e7 4ddf4d3ea9b45980a9b45980343ab05c 4ddf4d3e800000008000000000000000 4ddf4d3ea9b45980a9b45980343ab05c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vrintz.f32.f32 q12, q14 4936dd600178ae7fe22ecba456ce177e a08accc7404457ad34cca8539d6f1018 80000000404000000000000080000000 a08accc7404457ad34cca8539d6f1018 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[0]
+vrintz.f32.f32 q12, q14 6daed38f5045ab636fa16fb9d0e5533e c74dd5b58f824bbe9754c00bc74dd5b5 c74dd5008000000080000000c74dd500 c74dd5b58f824bbe9754c00bc74dd5b5 fpscr=00000000
+vrintz.f32.f32 q12, q14 c8a9d27e1d1258dd636b0bf96e935c9c 039dccadfc9135a3fd8e7e03b6880c99 00000000fc9135a3fd8e7e0380000000 039dccadfc9135a3fd8e7e03b6880c99 fpscr=00000000
+vrintz.f32.f32 q12, q14 ebc47b5984dafa5a80c915d395b6772c 177a4df9b2e96b5405a6769ec86ea684 000000008000000000000000c86ea680 177a4df9b2e96b5405a6769ec86ea684 fpscr=00000000
+vrintz.f32.f32 q12, q14 2da007de9d795df29c752a934bc58a6b af9a7b977e6941629b6335a8ccd596bc 800000007e69416280000000ccd596bc af9a7b977e6941629b6335a8ccd596bc fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vrintz.f32.f32 q12, q14 e487da088b4aa6921dad9c08a3a0ebcb 7253776dcc19ce7f7253776d10430784 7253776dcc19ce7f7253776d00000000 7253776dcc19ce7f7253776d10430784 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintz.f32.f32 q12, q14 7d217dcf935cd87039b6285a0376817f 2ce0b55b910c860b7d087208d1c42be8 00000000800000007d087208d1c42be8 2ce0b55b910c860b7d087208d1c42be8 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintz.f32.f32 q12, q14 bfda0b857d2de740709d82fbbfda0b85 747561927cb8867e0f307438260bc79f 747561927cb8867e0000000000000000 747561927cb8867e0f307438260bc79f fpscr=00000000
+vrintz.f32.f32 q12, q14 024eeed29b41f8a8070b3cf27a31f51d 00818bf9e75649fcc400d09eba28afbd 00000000e75649fcc400c00080000000 00818bf9e75649fcc400d09eba28afbd fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[1]
+vrintz.f32.f32 q12, q14 bba5ebeda7a9269a60e51084bf647b79 444d7dd2f3af1a03584fd72af3af1a03 444d4000f3af1a03584fd72af3af1a03 444d7dd2f3af1a03584fd72af3af1a03 fpscr=00000000
+vrintz.f32.f32 q12, q14 3e6bfc69a8c58e03c9b6a079d83828a8 47ed0f14b582787d24a48b1d219b4566 47ed0f00800000000000000000000000 47ed0f14b582787d24a48b1d219b4566 fpscr=00000000
+vrintz.f32.f32 q12, q14 d01500b104665287ca301f623240bda1 2d25f37071f37a5ebcc9fa320ecf6c87 0000000071f37a5e8000000000000000 2d25f37071f37a5ebcc9fa320ecf6c87 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintz.f32.f32 q12, q14 ad7ef10f49b15b5a81270bacf4bb9612 46d49855b22a4a3fd02904c462117506 46d4980080000000d02904c462117506 46d49855b22a4a3fd02904c462117506 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintz.f32.f32 q12, q14 6e0c25073948d77e1d233ac3e77a5981 216edfc7045febe1a4d5d98ac24da4e7 000000000000000080000000c24c0000 216edfc7045febe1a4d5d98ac24da4e7 fpscr=00000000
+vrintz.f32.f32 q12, q14 37bd6c634aafa1f3630c23d386c401bb 0f978c74fcae37e8940ea0130c6b43c0 00000000fcae37e88000000000000000 0f978c74fcae37e8940ea0130c6b43c0 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintz.f32.f32 q12, q14 ea8476993b0468e7ea8476995cd1ad77 b8a5bf376dc7a6a405627894bba9e0ca 800000006dc7a6a40000000080000000 b8a5bf376dc7a6a405627894bba9e0ca fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[0]
+vrintz.f32.f32 q12, q14 9121d93d287e3fc6218fbde3218fbde3 8bf14e1bdc643e7e067c9064dc643e7e 80000000dc643e7e00000000dc643e7e 8bf14e1bdc643e7e067c9064dc643e7e fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintz.f32.f32 q12, q14 375c6f20375c6f203ec4558a80ba1cff f49727aea83ade82ee653533119dd8a1 f49727ae80000000ee65353300000000 f49727aea83ade82ee653533119dd8a1 fpscr=00000000
+vrintx.f32.f32 q15, q15 1836bb9e0eacb60d6aaed33aec83eb55 d28faf6da28b0097967a4842cc41b8b9 d28faf6d8000000080000000cc41b8b9 d28faf6d8000000080000000cc41b8b9 fpscr=00000000
+vrintx.f32.f32 q15, q15 65368b931c9a145f68b209e3010b339a 293bd0c4517ac32116e4e088a5a0033d 00000000517ac3210000000080000000 00000000517ac3210000000080000000 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintx.f32.f32 q15, q15 8c6f5376b00f8a228b638def4f874c60 e1049f09e1049f09fc06546cb1812762 e1049f09e1049f09fc06546c80000000 e1049f09e1049f09fc06546c80000000 fpscr=00000000
+vrintx.f32.f32 q15, q15 7a8280d56c399d8e1b32c6438c8dc253 b07352cb31e21547b95ccb70203277b3 80000000000000008000000000000000 80000000000000008000000000000000 fpscr=00000000
+vrintx.f32.f32 q15, q15 3abad55aa0cdebce0491dca0010e6190 ccb44bc4c552463aa961ef754d70793c ccb44bc4c5524000800000004d70793c ccb44bc4c5524000800000004d70793c fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintx.f32.f32 q15, q15 416bc65c1a40481b902ded7648d61d5a fc22bfe08e3708ee87c72ce9fc22bfe0 fc22bfe08000000080000000fc22bfe0 fc22bfe08000000080000000fc22bfe0 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[0]
+vrintx.f32.f32 q15, q15 896055f6d1f26a8fd1f26a8f1416ef64 0e2c10dfa3591529bceca35f12f3be22 00000000800000008000000000000000 00000000800000008000000000000000 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vrintx.f32.f32 q15, q15 3086a123bda7326bd369e63d3086a123 d2ae1069a882341672afa696058d76bd d2ae10698000000072afa69600000000 d2ae10698000000072afa69600000000 fpscr=00000000
+vrintx.f32.f32 q15, q15 789db5eb54a6234c5cfaa080ecc9a778 1f6cc3ed6f03101a928e6c7e69760810 000000006f03101a8000000069760810 000000006f03101a8000000069760810 fpscr=00000000
+vrintx.f32.f32 q15, q15 62972b80faeaf0eef5b7bdc4c940aab4 cfcba3316a9fb10c0a3a69c9442c38c6 cfcba3316a9fb10c00000000442c4000 cfcba3316a9fb10c00000000442c4000 fpscr=00000000
+vrintx.f32.f32 q15, q15 3ef5cd9153b2c85af3be50b85faafe4c f53897af80b9a832aac07d0805327a56 f53897af800000008000000000000000 f53897af800000008000000000000000 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[0]
+vrintx.f32.f32 q15, q15 caa4a186a205758229b9c7714379b3a9 2f71dc807d8371cc7d8371cc3fb088bf 000000007d8371cc7d8371cc3f800000 000000007d8371cc7d8371cc3f800000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+vrintx.f32.f32 q15, q15 0a5fe18a50321299e3468ad539c79c86 4e52822738b722594fc64333a4ab59ec 4e528227000000004fc6433380000000 4e528227000000004fc6433380000000 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintx.f32.f32 q15, q15 9c5e45a9bed92ed14fea7ed9e1f25dc1 3d99b2555bb1e3d81c6f8d1420da8773 000000005bb1e3d80000000000000000 000000005bb1e3d80000000000000000 fpscr=00000000
+vrintx.f32.f32 q15, q15 286f58d56f3659829bd949c389f8cf28 9707f4c9744a38c450616d1f5f2c7cd3 80000000744a38c450616d1f5f2c7cd3 80000000744a38c450616d1f5f2c7cd3 fpscr=00000000
+vrintx.f32.f32 q15, q15 377823e6343e62a0f8bd591a10759908 09d3a28418a9ae101b623324abd660ad 00000000000000000000000080000000 00000000000000000000000080000000 fpscr=00000000
+vrintx.f32.f32 q15, q15 d9eddd4eb238a8d5715a14e1547b5083 536770f6a19c3251eeb6cd769107fe76 536770f680000000eeb6cd7680000000 536770f680000000eeb6cd7680000000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintx.f32.f32 q15, q15 17f898bb4b7490fa7d1b41a1c0244cf9 435711f1c95604b5d46e7c2b770db1db 43570000c95604b0d46e7c2b770db1db 43570000c95604b0d46e7c2b770db1db fpscr=00000000
+vrintx.f32.f32 q15, q15 f2168dbb1f6874826b300a54a5477781 44093282caf7b059becb7ecc094f0128 44094000caf7b0588000000000000000 44094000caf7b0588000000000000000 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[2]
+vrintx.f32.f32 q15, q15 a389a9c48628184a2289fcfbce6cf6ed 1d1aeed3634b6852eab5643feab5643f 00000000634b6852eab5643feab5643f 00000000634b6852eab5643feab5643f fpscr=00000000
+vrintx.f32.f32 q15, q15 324c440689bee90dfa2ac8e792cbd281 105d0164ed06dcc4a3ce01da80dbd6d9 00000000ed06dcc48000000080000000 00000000ed06dcc48000000080000000 fpscr=00000000
+randV128: 18688 calls, 19312 iters
+vrintx.f32.f32 q15, q15 8e301f5c9d3b3781541e376f0fe10f80 e1760db50a65fa5bed9a554e5610f70d e1760db500000000ed9a554e5610f70d e1760db500000000ed9a554e5610f70d fpscr=00000000
+vrintx.f32.f32 q15, q15 73857fa2155c85f66e970db8f7e50979 3bd1aa4b099c2596cfca386cc37d8c14 0000000000000000cfca386cc37e0000 0000000000000000cfca386cc37e0000 fpscr=00000000
+vrintx.f32.f32 q15, q15 8fe2f6dbd60c0e224fbbeb2383bfa40d 2117910534101645b1edc72fc06c1a77 000000000000000080000000c0800000 000000000000000080000000c0800000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vrintx.f32.f32 q15, q15 2cfefdbdd506dc342cfefdbd3b4a5460 084947b8ca242595dbddc673084947b8 00000000ca242594dbddc67300000000 00000000ca242594dbddc67300000000 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintx.f32.f32 q15, q15 e33b8a07e33b8a072eb4680d985c5df8 6480f7aa5c384b23e2a18fee78e5754a 6480f7aa5c384b23e2a18fee78e5754a 6480f7aa5c384b23e2a18fee78e5754a fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[2]
+vrintx.f32.f32 q15, q15 1bce841017696b4c81d1c72b6d11123e 09dc14068611d5048611d5048e7bd02a 00000000800000008000000080000000 00000000800000008000000080000000 fpscr=00000000
+vrintx.f32.f32 q15, q15 f4c56f19eaa617d410b8421a2511a329 4776a02c765a3beb8aa887c697a2958e 4776a000765a3beb8000000080000000 4776a000765a3beb8000000080000000 fpscr=00000000
+vrintx.f32.f32 q15, q15 7418736607b28df5249cbc95c02896ce 34e43772d162895a3f93ddc355154c47 00000000d162895a3f80000055154c47 00000000d162895a3f80000055154c47 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintx.f32.f32 q15, q15 5431fc21b37c163f812352f91e9851b1 16079155073929694cb23212918151fe 00000000000000004cb2321280000000 00000000000000004cb2321280000000 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vrintx.f32.f32 q15, q15 adc507c02728804fd160084bf0aab4d5 939fd67f5e6d396520cefd0cdfc43fd2 800000005e6d396500000000dfc43fd2 800000005e6d396500000000dfc43fd2 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vrintx.f32.f32 q15, q15 665f853d7857fc90665f853db3af41b7 05b8b5a1e9b6d1931d6dc6b0f0bc5546 00000000e9b6d19300000000f0bc5546 00000000e9b6d19300000000f0bc5546 fpscr=00000000
+vrintx.f32.f32 q15, q15 59cb89648fb2d03f908c850bde537d8e 0a42952ed8efd136cdd431c536884590 00000000d8efd136cdd431c500000000 00000000d8efd136cdd431c500000000 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vrintx.f32.f32 q15, q15 ceb402ad24fa10da983281a9c1a7d956 01b11916667c823006ef689726fd16b6 00000000667c82300000000000000000 00000000667c82300000000000000000 fpscr=00000000
+vrintx.f32.f32 q15, q15 6e35105e6ef6c199aa70c3fba0ceee96 6f0564a7f6f93fa9748d57cb14aef212 6f0564a7f6f93fa9748d57cb00000000 6f0564a7f6f93fa9748d57cb00000000 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vrintx.f32.f32 q15, q15 51d392710aeec670be30882582127fa0 27fbf669f6b53ae68b50c108bb37a747 00000000f6b53ae68000000080000000 00000000f6b53ae68000000080000000 fpscr=00000000
+vrintx.f32.f32 q15, q15 253f1f175b75fd88e4d5d90de863cc40 6fdf94bf69112938cb2755316d6a3a7c 6fdf94bf69112938cb2755316d6a3a7c 6fdf94bf69112938cb2755316d6a3a7c fpscr=00000000
+vrintx.f32.f32 q15, q15 93e2dd9161dfa88967e212f069383c70 1208a2b545ba4d2e368381f7ca6f6cd7 0000000045ba500000000000ca6f6cd8 0000000045ba500000000000ca6f6cd8 fpscr=00000000
+vrintx.f32.f32 q15, q15 b5d018d721fd1e40a26abb34dc250e97 3a93815115b0c5be6503f50df18faea8 00000000000000006503f50df18faea8 00000000000000006503f50df18faea8 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[0] = v->u32[2]
+vrintx.f32.f32 q15, q15 8c2bcdac6032a7478c2bcdac70ac0106 6a8a25bca41f9e8a18e52399a41f9e8a 6a8a25bc800000000000000080000000 6a8a25bc800000000000000080000000 fpscr=00000000
+vrintx.f32.f32 q15, q15 0a2f0b0148c8b4dd70ddd39a578b2806 76a47b20c8f8e500f482d9cd42050bf3 76a47b20c8f8e500f482d9cd42040000 76a47b20c8f8e500f482d9cd42040000 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintx.f32.f32 q15, q15 c91114caee0a979fa6412764bcfeb3c8 e065ea1444c43b1e7304ef73e065ea14 e065ea1444c440007304ef73e065ea14 e065ea1444c440007304ef73e065ea14 fpscr=00000000
+vrintx.f32.f32 q15, q15 45e6eb4612e6370aa78da56b2f4061b1 fc8e08526e449b0c4a7b0a4f78015785 fc8e08526e449b0c4a7b0a5078015785 fc8e08526e449b0c4a7b0a5078015785 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vrintx.f32.f32 q15, q15 2855dc30d6c94f3e0c708f300c708f30 54f62fcd7ebbe3250dc589e9ccd4f60c 54f62fcd7ebbe32500000000ccd4f60c 54f62fcd7ebbe32500000000ccd4f60c fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vrintx.f32.f32 q15, q15 1ecc27fe27e8f34c682784c75237b980 e0e4cd51ca215049f8837032e66f9d5d e0e4cd51ca215048f8837032e66f9d5d e0e4cd51ca215048f8837032e66f9d5d fpscr=00000000
+vrintx.f32.f32 q15, q15 1672b08a020f49ad2dec34dcc31e8a2c 2b65a4f3a7840d96dc48917086a083f9 0000000080000000dc48917080000000 0000000080000000dc48917080000000 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vrintx.f32.f32 q15, q15 35007c003092e93038e2b5797d512dcc 59e4fb074b647c694b647c694de28843 59e4fb074b647c694b647c694de28843 59e4fb074b647c694b647c694de28843 fpscr=00000000
+vrintx.f32.f32 q15, q15 02a0dd5830849ee2156d8983c2422a51 ef5918a22b9cadcc7b5d4795c62b6d93 ef5918a2000000007b5d4795c62b6c00 ef5918a2000000007b5d4795c62b6c00 fpscr=00000000
+vrintx.f32.f32 q15, q15 5935442528a7c5bb0eb8e9703a9665f6 ad686658d603d8bff52e3ce9ae604518 80000000d603d8bff52e3ce980000000 80000000d603d8bff52e3ce980000000 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vrintx.f32.f32 q15, q15 a21820b1885beb51f2f5f67d117eaf19 2517c0ee339b13c81b08771df61e75f8 000000000000000000000000f61e75f8 000000000000000000000000f61e75f8 fpscr=00000000
diff --git a/none/tests/arm/v8fpsimd_t.vgtest b/none/tests/arm/v8fpsimd_t.vgtest
new file mode 100644
index 0000000..25f8602
--- /dev/null
+++ b/none/tests/arm/v8fpsimd_t.vgtest
@@ -0,0 +1,2 @@
+prog: v8fpsimd_t
+vgopts: -q
diff --git a/none/tests/arm64/Makefile.in b/none/tests/arm64/Makefile.in
index 1d94d1d..7a25757 100644
--- a/none/tests/arm64/Makefile.in
+++ b/none/tests/arm64/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -270,6 +270,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -440,6 +441,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -450,6 +452,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -524,8 +527,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -570,7 +571,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/none/tests/bug234814.vgtest b/none/tests/bug234814.vgtest
index 31f95aa..67a28e6 100644
--- a/none/tests/bug234814.vgtest
+++ b/none/tests/bug234814.vgtest
@@ -1,2 +1 @@
-prereq: ! ../../tests/arch_test tilegx
prog: bug234814
diff --git a/none/tests/cmdline1.stdout.exp b/none/tests/cmdline1.stdout.exp
index 0faec69..e35b382 100644
--- a/none/tests/cmdline1.stdout.exp
+++ b/none/tests/cmdline1.stdout.exp
@@ -58,6 +58,12 @@
--alignment=<number> set minimum alignment of heap allocations [not used by this tool]
--redzone-size=<number> set minimum size of redzones added before/after
heap blocks (in bytes). [not used by this tool]
+ --xtree-memory=none|allocs|full profile heap memory in an xtree [none]
+ and produces a report at the end of the execution
+ none: no profiling, allocs: current allocated
+ size/blocks, full: profile current and cumulative
+ allocated size/blocks and freed size/blocks.
+ --xtree-memory-file=<file> xtree memory report file [xtmemory.kcg.%p]
uncommon user options for all Valgrind tools:
--fullpath-after= (with nothing after the '=')
@@ -95,7 +101,7 @@
--sim-hints=hint1,hint2,... activate unusual sim behaviours [none]
where hint is one of:
lax-ioctls lax-doors fuse-compatible enable-outer
- no-inner-prefix no-nptl-pthread-stackcache none
+ no-inner-prefix no-nptl-pthread-stackcache fallback-llsc none
--fair-sched=no|yes|try schedule threads fairly on multicore systems [no]
--kernel-variant=variant1,variant2,...
handle non-standard kernel variants [none]
@@ -104,7 +110,7 @@
android-gpu-sgx5xx android-gpu-adreno3xx none
--merge-recursive-frames=<number> merge frames between identical
program counters in max <number> frames) [0]
- --num-transtab-sectors=<number> size of translated code cache [16]
+ --num-transtab-sectors=<number> size of translated code cache [32]
more sectors may increase performance, but use more memory.
--avg-transtab-entry-size=<number> avg size in bytes of a translated
basic block [0, meaning use tool provided default]
@@ -136,9 +142,9 @@
Extra options read from ~/.valgrindrc, $VALGRIND_OPTS, ./.valgrindrc
- Nulgrind is Copyright (C) 2002-2015, and GNU GPL'd, by Nicholas Nethercote.
- Valgrind is Copyright (C) 2000-2015, and GNU GPL'd, by Julian Seward et al.
- LibVEX is Copyright (C) 2004-2015, and GNU GPL'd, by OpenWorks LLP et al.
+ Nulgrind is Copyright (C) 2002-2017, and GNU GPL'd, by Nicholas Nethercote.
+ Valgrind is Copyright (C) 2000-2017, and GNU GPL'd, by Julian Seward et al.
+ LibVEX is Copyright (C) 2004-2017, and GNU GPL'd, by OpenWorks LLP et al.
Bug reports, feedback, admiration, abuse, etc, to: www.valgrind.org.
diff --git a/none/tests/cmdline2.stdout.exp b/none/tests/cmdline2.stdout.exp
index b124f20..fc7b36c 100644
--- a/none/tests/cmdline2.stdout.exp
+++ b/none/tests/cmdline2.stdout.exp
@@ -58,6 +58,12 @@
--alignment=<number> set minimum alignment of heap allocations [not used by this tool]
--redzone-size=<number> set minimum size of redzones added before/after
heap blocks (in bytes). [not used by this tool]
+ --xtree-memory=none|allocs|full profile heap memory in an xtree [none]
+ and produces a report at the end of the execution
+ none: no profiling, allocs: current allocated
+ size/blocks, full: profile current and cumulative
+ allocated size/blocks and freed size/blocks.
+ --xtree-memory-file=<file> xtree memory report file [xtmemory.kcg.%p]
uncommon user options for all Valgrind tools:
--fullpath-after= (with nothing after the '=')
@@ -95,7 +101,7 @@
--sim-hints=hint1,hint2,... activate unusual sim behaviours [none]
where hint is one of:
lax-ioctls lax-doors fuse-compatible enable-outer
- no-inner-prefix no-nptl-pthread-stackcache none
+ no-inner-prefix no-nptl-pthread-stackcache fallback-llsc none
--fair-sched=no|yes|try schedule threads fairly on multicore systems [no]
--kernel-variant=variant1,variant2,...
handle non-standard kernel variants [none]
@@ -104,7 +110,7 @@
android-gpu-sgx5xx android-gpu-adreno3xx none
--merge-recursive-frames=<number> merge frames between identical
program counters in max <number> frames) [0]
- --num-transtab-sectors=<number> size of translated code cache [16]
+ --num-transtab-sectors=<number> size of translated code cache [32]
more sectors may increase performance, but use more memory.
--avg-transtab-entry-size=<number> avg size in bytes of a translated
basic block [0, meaning use tool provided default]
@@ -199,15 +205,16 @@
debugging options for Valgrind tools that replace malloc:
--trace-malloc=no|yes show client malloc details? [no]
+ --xtree-compress-strings=no|yes compress strings in xtree callgrind format [yes]
debugging options for Nulgrind:
(none)
Extra options read from ~/.valgrindrc, $VALGRIND_OPTS, ./.valgrindrc
- Nulgrind is Copyright (C) 2002-2015, and GNU GPL'd, by Nicholas Nethercote.
- Valgrind is Copyright (C) 2000-2015, and GNU GPL'd, by Julian Seward et al.
- LibVEX is Copyright (C) 2004-2015, and GNU GPL'd, by OpenWorks LLP et al.
+ Nulgrind is Copyright (C) 2002-2017, and GNU GPL'd, by Nicholas Nethercote.
+ Valgrind is Copyright (C) 2000-2017, and GNU GPL'd, by Julian Seward et al.
+ LibVEX is Copyright (C) 2004-2017, and GNU GPL'd, by OpenWorks LLP et al.
Bug reports, feedback, admiration, abuse, etc, to: www.valgrind.org.
diff --git a/none/tests/darwin/Makefile.in b/none/tests/darwin/Makefile.in
index 47370fd..4b59c92 100644
--- a/none/tests/darwin/Makefile.in
+++ b/none/tests/darwin/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -252,6 +252,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -422,6 +423,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -432,6 +434,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -506,8 +509,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -552,7 +553,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/none/tests/filter_timestamp b/none/tests/filter_timestamp
index d524aef..fe6bdd2 100755
--- a/none/tests/filter_timestamp
+++ b/none/tests/filter_timestamp
@@ -21,7 +21,7 @@
# We replace the last 5 numbers to allow for a wide range of possible times.
# It's not a great test, but it will catch some breakage (eg. if the times
# don't start near 0, as happened in bug 200990, or if the space following
-# the time is omitted, as happend in r10465).
+# the time is omitted, as happened in r10465).
#
perl -p -e "s/^00:00:00:\d\d\.\d\d\d $/00:00:00:XX:YYY/"
diff --git a/none/tests/libvex_test.c b/none/tests/libvex_test.c
index 2c3986d..39fe715 100644
--- a/none/tests/libvex_test.c
+++ b/none/tests/libvex_test.c
@@ -48,7 +48,7 @@
#elif __BYTE_ORDER == __BIG_ENDIAN
return VexEndnessBE;
#else
- fprintf(stderr, "cannot determine endianess\n");
+ fprintf(stderr, "cannot determine endianness\n");
exit(1);
#endif
}
@@ -74,8 +74,6 @@
*ga = VexArchMIPS32;
#elif defined(VGA_mips64)
*ga = VexArchMIPS64;
-#elif defined(VGA_tilegx)
- *ga = VexArchTILEGX;
#else
missing arch;
#endif
@@ -98,10 +96,10 @@
case VexArchMIPS64:
/* mips32/64 supports BE or LE, but at compile time.
If mips64 is compiled on a non mips system, the VEX lib
- is missing bit and pieces of code related to endianess.
+ is missing bit and pieces of code related to endianness.
The mandatory code for this test is then compiled as BE.
So, if this test runs on a mips system, returns the
- running endianess. Otherwise, returns BE as this one
+ running endianness. Otherwise, returns BE as this one
has the more chances to work. */
{
VexArch ga;
@@ -112,7 +110,6 @@
else
return VexEndnessBE;
}
- case VexArchTILEGX: return VexEndnessLE;
default: failure_exit();
}
}
@@ -131,7 +128,6 @@
case VexArchS390X: return VEX_HWCAPS_S390X_LDISP;
case VexArchMIPS32: return VEX_PRID_COMP_MIPS;
case VexArchMIPS64: return VEX_PRID_COMP_MIPS;
- case VexArchTILEGX: return 0;
default: failure_exit();
}
}
@@ -148,7 +144,6 @@
case VexArchS390X: return True;
case VexArchMIPS32: return False;
case VexArchMIPS64: return True;
- case VexArchTILEGX: return True;
default: failure_exit();
}
}
@@ -265,10 +260,10 @@
// endness(host) != endness(guest) (not well supported)
// wordsize (host) != wordsize (guest) (not well supported)
// The not well supported combinations are not run, unless requested
- // explicitely via command line arguments.
+ // explicitly via command line arguments.
if (multiarch) {
VexArch va;
- for (va = VexArchX86; va <= VexArchTILEGX; va++) {
+ for (va = VexArchX86; va <= VexArchMIPS64; va++) {
vta.arch_host = va;
vta.archinfo_host.endness = arch_endness (vta.arch_host);
vta.archinfo_host.hwcaps = arch_hwcaps (vta.arch_host);
diff --git a/none/tests/linux/Makefile.am b/none/tests/linux/Makefile.am
index f407cb4..299476d 100644
--- a/none/tests/linux/Makefile.am
+++ b/none/tests/linux/Makefile.am
@@ -7,6 +7,7 @@
blockfault.stderr.exp blockfault.vgtest \
brk-overflow1.stderr.exp brk-overflow1.vgtest \
brk-overflow2.stderr.exp brk-overflow2.vgtest \
+ clonev.stdout.exp clonev.stderr.exp clonev.vgtest \
mremap.stderr.exp mremap.stderr.exp-glibc27 mremap.stdout.exp \
mremap.vgtest \
mremap2.stderr.exp mremap2.stdout.exp mremap2.vgtest \
@@ -21,6 +22,7 @@
blockfault \
brk-overflow1 \
brk-overflow2 \
+ clonev \
mremap \
mremap2 \
mremap3 \
@@ -35,6 +37,7 @@
AM_CXXFLAGS += $(AM_FLAG_M3264_PRI)
# Special needs
+clonev_LDADD = -lpthread
pthread_stack_LDADD = -lpthread
stack_overflow_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_UNINITIALIZED@ \
diff --git a/none/tests/linux/Makefile.in b/none/tests/linux/Makefile.in
index 10bd957..e316cbb 100644
--- a/none/tests/linux/Makefile.in
+++ b/none/tests/linux/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -121,9 +121,9 @@
@COMPILER_IS_CLANG_TRUE@ clang 3.0.0
@COMPILER_IS_CLANG_TRUE@am__append_7 = -Wno-unused-private-field # drd/tests/tsan_unittest.cpp
check_PROGRAMS = blockfault$(EXEEXT) brk-overflow1$(EXEEXT) \
- brk-overflow2$(EXEEXT) mremap$(EXEEXT) mremap2$(EXEEXT) \
- mremap3$(EXEEXT) mremap4$(EXEEXT) mremap5$(EXEEXT) \
- mremap6$(EXEEXT) pthread-stack$(EXEEXT) \
+ brk-overflow2$(EXEEXT) clonev$(EXEEXT) mremap$(EXEEXT) \
+ mremap2$(EXEEXT) mremap3$(EXEEXT) mremap4$(EXEEXT) \
+ mremap5$(EXEEXT) mremap6$(EXEEXT) pthread-stack$(EXEEXT) \
stack-overflow$(EXEEXT)
subdir = none/tests/linux
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
@@ -145,6 +145,9 @@
brk_overflow2_SOURCES = brk-overflow2.c
brk_overflow2_OBJECTS = brk-overflow2.$(OBJEXT)
brk_overflow2_LDADD = $(LDADD)
+clonev_SOURCES = clonev.c
+clonev_OBJECTS = clonev.$(OBJEXT)
+clonev_DEPENDENCIES =
mremap_SOURCES = mremap.c
mremap_OBJECTS = mremap.$(OBJEXT)
mremap_LDADD = $(LDADD)
@@ -204,11 +207,11 @@
am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@)
am__v_CCLD_0 = @echo " CCLD " $@;
am__v_CCLD_1 =
-SOURCES = blockfault.c brk-overflow1.c brk-overflow2.c mremap.c \
- mremap2.c mremap3.c mremap4.c mremap5.c mremap6.c \
+SOURCES = blockfault.c brk-overflow1.c brk-overflow2.c clonev.c \
+ mremap.c mremap2.c mremap3.c mremap4.c mremap5.c mremap6.c \
pthread-stack.c stack-overflow.c
-DIST_SOURCES = blockfault.c brk-overflow1.c brk-overflow2.c mremap.c \
- mremap2.c mremap3.c mremap4.c mremap5.c mremap6.c \
+DIST_SOURCES = blockfault.c brk-overflow1.c brk-overflow2.c clonev.c \
+ mremap.c mremap2.c mremap3.c mremap4.c mremap5.c mremap6.c \
pthread-stack.c stack-overflow.c
am__can_run_installinfo = \
case $$AM_UPDATE_INFO_DIR in \
@@ -281,6 +284,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -451,6 +455,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -461,6 +466,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -535,8 +541,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -581,7 +585,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
@@ -609,6 +612,7 @@
blockfault.stderr.exp blockfault.vgtest \
brk-overflow1.stderr.exp brk-overflow1.vgtest \
brk-overflow2.stderr.exp brk-overflow2.vgtest \
+ clonev.stdout.exp clonev.stderr.exp clonev.vgtest \
mremap.stderr.exp mremap.stderr.exp-glibc27 mremap.stdout.exp \
mremap.vgtest \
mremap2.stderr.exp mremap2.stdout.exp mremap2.vgtest \
@@ -621,6 +625,7 @@
# Special needs
+clonev_LDADD = -lpthread
pthread_stack_LDADD = -lpthread
stack_overflow_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_UNINITIALIZED@ \
@FLAG_W_NO_INFINITE_RECURSION@
@@ -675,6 +680,10 @@
@rm -f brk-overflow2$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(brk_overflow2_OBJECTS) $(brk_overflow2_LDADD) $(LIBS)
+clonev$(EXEEXT): $(clonev_OBJECTS) $(clonev_DEPENDENCIES) $(EXTRA_clonev_DEPENDENCIES)
+ @rm -f clonev$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(clonev_OBJECTS) $(clonev_LDADD) $(LIBS)
+
mremap$(EXEEXT): $(mremap_OBJECTS) $(mremap_DEPENDENCIES) $(EXTRA_mremap_DEPENDENCIES)
@rm -f mremap$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(mremap_OBJECTS) $(mremap_LDADD) $(LIBS)
@@ -716,6 +725,7 @@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/blockfault.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/brk-overflow1.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/brk-overflow2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/clonev.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mremap.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mremap2.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mremap3.Po@am__quote@
diff --git a/none/tests/linux/brk-overflow1.stderr.exp b/none/tests/linux/brk-overflow1.stderr.exp
index 96741db..46242e3 100644
--- a/none/tests/linux/brk-overflow1.stderr.exp
+++ b/none/tests/linux/brk-overflow1.stderr.exp
@@ -1,4 +1,5 @@
brk segment overflow in thread #1: can't grow to 0x........
(see section Limitations in user manual)
+NOTE: further instances of this message will not be shown
diff --git a/none/tests/linux/brk-overflow2.stderr.exp b/none/tests/linux/brk-overflow2.stderr.exp
index 5cdf1f7..46242e3 100644
--- a/none/tests/linux/brk-overflow2.stderr.exp
+++ b/none/tests/linux/brk-overflow2.stderr.exp
@@ -1,8 +1,5 @@
brk segment overflow in thread #1: can't grow to 0x........
(see section Limitations in user manual)
-brk segment overflow in thread #1: can't grow to 0x........
-(see section Limitations in user manual)
-brk segment overflow in thread #1: can't grow to 0x........
-(see section Limitations in user manual)
+NOTE: further instances of this message will not be shown
diff --git a/none/tests/linux/clonev.c b/none/tests/linux/clonev.c
new file mode 100644
index 0000000..b37cc8d
--- /dev/null
+++ b/none/tests/linux/clonev.c
@@ -0,0 +1,77 @@
+#define _GNU_SOURCE
+#include <assert.h>
+#include <errno.h>
+#include <sched.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/mman.h>
+#include <sys/wait.h>
+#include <unistd.h>
+// Based on a test by Steven Stewart-Gallus, see 342040
+int fork_routine(void *arg)
+{
+ write(1, "fork_routine\n", 13);
+ _Exit(EXIT_SUCCESS);
+}
+
+int main(void)
+{
+ long page_size = sysconf(_SC_PAGE_SIZE);
+ assert(page_size != -1);
+
+ /* We need an extra page for signals */
+ long stack_size = sysconf(_SC_THREAD_STACK_MIN) + page_size;
+ assert(stack_size != -1);
+
+ size_t stack_and_guard_size = page_size + stack_size + page_size;
+ void *child_stack = mmap(
+ NULL, stack_and_guard_size, PROT_READ | PROT_WRITE,
+ MAP_PRIVATE | MAP_ANONYMOUS | MAP_GROWSDOWN, -1, 0);
+ if (NULL == child_stack) {
+ perror("mmap");
+ return EXIT_FAILURE;
+ }
+
+ /* Guard pages are shared between the stacks */
+ if (-1 == mprotect((char *)child_stack, page_size, PROT_NONE)) {
+ perror("mprotect");
+ return EXIT_FAILURE;
+ }
+
+ if (-1 == mprotect((char *)child_stack + page_size + stack_size,
+ page_size, PROT_NONE)) {
+ perror("mprotect");
+ return EXIT_FAILURE;
+ }
+
+ void *stack_start = (char *)child_stack + page_size + stack_size;
+ if (0)
+ printf("stack_start %p page_size %d stack_size %d\n",
+ stack_start, (int)page_size, (int)stack_size);
+ write(1, "parent before clone\n", 20);
+ pid_t child =
+ clone(fork_routine, stack_start,
+ SIGCHLD | CLONE_VFORK | CLONE_VM, NULL);
+ write(1, "parent after clone\n", 19);
+ if (-1 == child) {
+ perror("clone");
+ return EXIT_FAILURE;
+ }
+
+ for (;;) {
+ int xx;
+ switch (waitpid(child, &xx, 0)) {
+ case -1:
+ switch (errno) {
+ case EINTR:
+ continue;
+ default:
+ perror("waitpid");
+ return EXIT_FAILURE;
+ }
+
+ default:
+ return EXIT_SUCCESS;
+ }
+ }
+}
diff --git a/none/tests/linux/clonev.stderr.exp b/none/tests/linux/clonev.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/linux/clonev.stderr.exp
diff --git a/none/tests/linux/clonev.stdout.exp b/none/tests/linux/clonev.stdout.exp
new file mode 100644
index 0000000..2410e69
--- /dev/null
+++ b/none/tests/linux/clonev.stdout.exp
@@ -0,0 +1,3 @@
+parent before clone
+fork_routine
+parent after clone
diff --git a/none/tests/linux/clonev.vgtest b/none/tests/linux/clonev.vgtest
new file mode 100644
index 0000000..61ed15c
--- /dev/null
+++ b/none/tests/linux/clonev.vgtest
@@ -0,0 +1,2 @@
+prog: clonev
+vgopts: -q
diff --git a/none/tests/mips32/LoadStore.c b/none/tests/mips32/LoadStore.c
index 08bc41c..38574ef 100644
--- a/none/tests/mips32/LoadStore.c
+++ b/none/tests/mips32/LoadStore.c
@@ -22,51 +22,52 @@
// sb $t0, 0($t1)
#define TESTINST1(instruction, RTval, offset, RT, RS) \
-{ \
- unsigned int out; \
- __asm__ volatile( \
- "move $" #RS", %1\n\t" \
- "li $" #RT", " #RTval"\n\t" \
- instruction "\n\t" \
- "lw %0, "#offset"($"#RS")\n\t" \
- : "=&r" (out) \
- : "r" (mem1), "r" (RTval) \
- : #RT, "cc", "memory" \
- ); \
- printf("%s :: RTval: 0x%x, out: 0x%x\n", \
- instruction, RTval, out); \
- out = 0; \
- __asm__ volatile( \
- "move $" #RS", %1\n\t" \
- "li $" #RT", " #RTval"\n\t" \
- instruction "\n\t" \
- "lw %0, "#offset"($"#RS")\n\t" \
- : "=&r" (out) \
- : "r" (mem), "r" (RTval) \
- : #RT, "cc", "memory" \
- ); \
- printf("%s :: RTval: 0x%x, out: 0x%x\n", \
- instruction, RTval, out); \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ "move $" #RS", %1 \n\t" \
+ "li $" #RT", " #RTval" \n\t" \
+ instruction " \n\t" \
+ "lw %0, "#offset"($"#RS") \n\t" \
+ : "=&r" (out) \
+ : "r" (mem1), "r" (RTval) \
+ : #RS, #RT, "memory" \
+ ); \
+ printf("%s :: RTval: 0x%x, out: 0x%x\n", \
+ instruction, RTval, out); \
+ out = 0; \
+ __asm__ volatile( \
+ "move $" #RS", %1 \n\t" \
+ "li $" #RT", " #RTval " \n\t" \
+ instruction " \n\t" \
+ "lw %0, "#offset"($"#RS") \n\t" \
+ : "=&r" (out) \
+ : "r" (mem), "r" (RTval) \
+ : #RS, #RT, "memory" \
+ ); \
+ printf("%s :: RTval: 0x%x, out: 0x%x\n", \
+ instruction, RTval, out); \
}
// swl $t0, 3($t1)
// swr $t0, 0($t1)
-#define TESTINSTsw(RTval, offset, RT, RS) \
-{ \
- unsigned int out; \
- __asm__ volatile( \
- "move $" #RS", %1\n\t" \
- "addiu $"#RS", $"#RS", "#offset"\n\t" \
- "li $" #RT", " #RTval"\n\t" \
- "swl $t0, 3($t1) \n\t" \
- "swr $t0, 0($t1) \n\t" \
- "lw %0, 0($"#RS")\n\t" \
- : "=&r" (out) \
- : "r" (mem2), "r" (RTval) \
- : #RT, #RS, "cc", "memory" \
- ); \
- printf("swl $t0, 3($t1)\nswr $t0, 0($t1)\n :: RTval: 0x%x, out: 0x%x\n", \
- RTval, out); \
+#define TESTINSTsw(RTval, offset, RT, RS) \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ "move $" #RS", %1\n\t" \
+ "addiu $"#RS", $"#RS", "#offset" \n\t" \
+ "li $" #RT", " #RTval" \n\t" \
+ "swl $t0, 3($t1) \n\t" \
+ "swr $t0, 0($t1) \n\t" \
+ "lw %0, 0($"#RS") \n\t" \
+ : "=&r" (out) \
+ : "r" (mem2), "r" (RTval) \
+ : #RT, #RS, "memory" \
+ ); \
+ printf("swl $t0, 3($t1)\nswr $t0, 0($t1)\n" \
+ " :: RTval: 0x%x, out: 0x%x\n", \
+ RTval, out); \
}
void ppMem(unsigned int* m, int len)
diff --git a/none/tests/mips32/LoadStore1.c b/none/tests/mips32/LoadStore1.c
index a6547b2..6a54303 100644
--- a/none/tests/mips32/LoadStore1.c
+++ b/none/tests/mips32/LoadStore1.c
@@ -22,51 +22,52 @@
// sb $t0, 0($t1)
#define TESTINST1(instruction, RTval, offset, RT, RS) \
-{ \
- unsigned int out; \
- __asm__ volatile( \
- "move $" #RS", %1\n\t" \
- "li $" #RT", " #RTval"\n\t" \
- instruction "\n\t" \
- "lw %0, "#offset"($"#RS")\n\t" \
- : "=&r" (out) \
- : "r" (mem1), "r" (RTval) \
- : #RT, "cc", "memory" \
- ); \
- printf("%s :: RTval: 0x%x, out: 0x%x\n", \
- instruction, RTval, out); \
- out = 0; \
- __asm__ volatile( \
- "move $" #RS", %1\n\t" \
- "li $" #RT", " #RTval"\n\t" \
- instruction "\n\t" \
- "lw %0, "#offset"($"#RS")\n\t" \
- : "=&r" (out) \
- : "r" (mem), "r" (RTval) \
- : #RT, "cc", "memory" \
- ); \
- printf("%s :: RTval: 0x%x, out: 0x%x\n", \
- instruction, RTval, out); \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ "move $" #RS", %1 \n\t" \
+ "li $" #RT", " #RTval" \n\t" \
+ instruction " \n\t" \
+ "lw %0, "#offset"($"#RS") \n\t" \
+ : "=&r" (out) \
+ : "r" (mem1), "r" (RTval) \
+ : #RS, #RT, "memory" \
+ ); \
+ printf("%s :: RTval: 0x%x, out: 0x%x\n", \
+ instruction, RTval, out); \
+ out = 0; \
+ __asm__ volatile( \
+ "move $" #RS", %1 \n\t" \
+ "li $" #RT", " #RTval " \n\t" \
+ instruction " \n\t" \
+ "lw %0, "#offset"($"#RS") \n\t" \
+ : "=&r" (out) \
+ : "r" (mem), "r" (RTval) \
+ : #RS, #RT, "memory" \
+ ); \
+ printf("%s :: RTval: 0x%x, out: 0x%x\n", \
+ instruction, RTval, out); \
}
// swl $t0, 3($t1)
// swr $t0, 0($t1)
-#define TESTINSTsw(RTval, offset, RT, RS) \
-{ \
- unsigned int out; \
- __asm__ volatile( \
- "move $" #RS", %1\n\t" \
- "addiu $"#RS", $"#RS", "#offset"\n\t" \
- "li $" #RT", " #RTval"\n\t" \
- "swl $t0, 3($t1) \n\t" \
- "swr $t0, 0($t1) \n\t" \
- "lw %0, 0($"#RS")\n\t" \
- : "=&r" (out) \
- : "r" (mem2), "r" (RTval) \
- : #RT, #RS, "cc", "memory" \
- ); \
- printf("swl $t0, 3($t1)\nswr $t0, 0($t1)\n :: RTval: 0x%x, out: 0x%x\n", \
- RTval, out); \
+#define TESTINSTsw(RTval, offset, RT, RS) \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ "move $" #RS", %1\n\t" \
+ "addiu $"#RS", $"#RS", "#offset" \n\t" \
+ "li $" #RT", " #RTval" \n\t" \
+ "swl $t0, 3($t1) \n\t" \
+ "swr $t0, 0($t1) \n\t" \
+ "lw %0, 0($"#RS") \n\t" \
+ : "=&r" (out) \
+ : "r" (mem2), "r" (RTval) \
+ : #RT, #RS, "memory" \
+ ); \
+ printf("swl $t0, 3($t1)\nswr $t0, 0($t1)\n" \
+ " :: RTval: 0x%x, out: 0x%x\n", \
+ RTval, out); \
}
void ppMem(unsigned int* m, int len)
diff --git a/none/tests/mips32/MIPS32int.c b/none/tests/mips32/MIPS32int.c
index d011a69..02d0815 100644
--- a/none/tests/mips32/MIPS32int.c
+++ b/none/tests/mips32/MIPS32int.c
@@ -101,9 +101,9 @@
instruction "\n\t" \
"move %0, $" #RT "\n\t" \
: "=&r" (out) \
- : "r" (mem), "r" (RTval) \
- : #RT, "cc", "memory" \
- ); \
+ : "r" (mem), "r" (RTval) \
+ : #RT, "cc", "memory" \
+ ); \
printf("%s :: rt 0x%08x\n", \
instruction, out); \
}
@@ -120,9 +120,9 @@
"mfhi %0\n\t" \
"mflo %1\n\t" \
: "=&r" (HI), "=&r" (LO) \
- : "r" (RSval)\
- : "cc", "memory" \
- ); \
+ : "r" (RSval) \
+ : "cc", "memory" \
+ ); \
printf("mfhi mflo :: HI: 0x%x, LO: 0x%x\n", \
HI, LO); \
}
@@ -662,7 +662,7 @@
TESTINSN5LOAD("lb $t0, 52($t1)", 0, 52, t0);
TESTINSN5LOAD("lb $t0, 56($t1)", 0, 56, t0);
TESTINSN5LOAD("lb $t0, 60($t1)", 0, 60, t0);
- TESTINSN5LOAD("lb $t0, 64($t1)", 0, 64, t0);
+ TESTINSN5LOAD("lb $t0, 1($t1)", 0, 1, t0);
TESTINSN5LOAD("lb $t0, 2($t1)", 0, 2, t0);
TESTINSN5LOAD("lb $t0, 6($t1)", 0, 6, t0);
TESTINSN5LOAD("lb $t0, 10($t1)", 0, 10, t0);
@@ -691,7 +691,7 @@
TESTINSN5LOAD("lbu $t0, 52($t1)", 0, 52, t0);
TESTINSN5LOAD("lbu $t0, 56($t1)", 0, 56, t0);
TESTINSN5LOAD("lbu $t0, 60($t1)", 0, 60, t0);
- TESTINSN5LOAD("lbu $t0, 64($t1)", 0, 64, t0);
+ TESTINSN5LOAD("lbu $t0, 1($t1)", 0, 1, t0);
TESTINSN5LOAD("lbu $t0, 2($t1)", 0, 2, t0);
TESTINSN5LOAD("lbu $t0, 6($t1)", 0, 6, t0);
TESTINSN5LOAD("lbu $t0, 10($t1)", 0, 10, t0);
@@ -720,7 +720,7 @@
TESTINSN5LOAD("lh $t0, 52($t1)", 0, 52, t0);
TESTINSN5LOAD("lh $t0, 56($t1)", 0, 56, t0);
TESTINSN5LOAD("lh $t0, 60($t1)", 0, 60, t0);
- TESTINSN5LOAD("lh $t0, 64($t1)", 0, 64, t0);
+ TESTINSN5LOAD("lh $t0, 62($t1)", 0, 62, t0);
TESTINSN5LOAD("lh $t0, 2($t1)", 0, 2, t0);
TESTINSN5LOAD("lh $t0, 6($t1)", 0, 6, t0);
TESTINSN5LOAD("lh $t0, 10($t1)", 0, 10, t0);
@@ -749,7 +749,7 @@
TESTINSN5LOAD("lhu $t0, 52($t1)", 0, 52, t0);
TESTINSN5LOAD("lhu $t0, 56($t1)", 0, 56, t0);
TESTINSN5LOAD("lhu $t0, 60($t1)", 0, 60, t0);
- TESTINSN5LOAD("lhu $t0, 64($t1)", 0, 64, t0);
+ TESTINSN5LOAD("lhu $t0, 62($t1)", 0, 62, t0);
TESTINSN5LOAD("lhu $t0, 2($t1)", 0, 2, t0);
TESTINSN5LOAD("lhu $t0, 6($t1)", 0, 6, t0);
TESTINSN5LOAD("lhu $t0, 10($t1)", 0, 10, t0);
@@ -786,7 +786,6 @@
TESTINSN5LOAD("lw $t0, 52($t1)", 0, 52, t0);
TESTINSN5LOAD("lw $t0, 56($t1)", 0, 56, t0);
TESTINSN5LOAD("lw $t0, 60($t1)", 0, 60, t0);
- TESTINSN5LOAD("lw $t0, 64($t1)", 0, 64, t0);
TESTINSN5LOAD("lw $t0, 2($t1)", 0, 2, t0);
TESTINSN5LOAD("lw $t0, 6($t1)", 0, 6, t0);
TESTINSN5LOAD("lw $t0, 10($t1)", 0, 10, t0);
@@ -799,62 +798,48 @@
TESTINSN5LOAD("lw $t0, 38($t1)", 0, 38, t0);
printf("LWL\n");
- TESTINSN5LOAD("lwl $t0, 0($t1)", 0, 0, t0);
- TESTINSN5LOAD("lwl $t0, 4($t1)", 0, 4, t0);
- TESTINSN5LOAD("lwl $t0, 8($t1)", 0, 8, t0);
- TESTINSN5LOAD("lwl $t0, 12($t1)", 0, 12, t0);
- TESTINSN5LOAD("lwl $t0, 16($t1)", 0, 16, t0);
- TESTINSN5LOAD("lwl $t0, 20($t1)", 0, 20, t0);
- TESTINSN5LOAD("lwl $t0, 24($t1)", 0, 24, t0);
- TESTINSN5LOAD("lwl $t0, 28($t1)", 0, 28, t0);
- TESTINSN5LOAD("lwl $t0, 32($t1)", 0, 32, t0);
- TESTINSN5LOAD("lwl $t0, 36($t1)", 0, 36, t0);
- TESTINSN5LOAD("lwl $t0, 40($t1)", 0, 40, t0);
- TESTINSN5LOAD("lwl $t0, 44($t1)", 0, 44, t0);
- TESTINSN5LOAD("lwl $t0, 48($t1)", 0, 48, t0);
- TESTINSN5LOAD("lwl $t0, 52($t1)", 0, 52, t0);
- TESTINSN5LOAD("lwl $t0, 56($t1)", 0, 56, t0);
- TESTINSN5LOAD("lwl $t0, 60($t1)", 0, 60, t0);
- TESTINSN5LOAD("lwl $t0, 64($t1)", 0, 64, t0);
- TESTINSN5LOAD("lwl $t0, 2($t1)", 0, 2, t0);
+ TESTINSN5LOAD("lwl $t0, 3($t1)", 0, 3, t0);
TESTINSN5LOAD("lwl $t0, 6($t1)", 0, 6, t0);
- TESTINSN5LOAD("lwl $t0, 10($t1)", 0, 10, t0);
- TESTINSN5LOAD("lwl $t0, 14($t1)", 0, 14, t0);
+ TESTINSN5LOAD("lwl $t0, 9($t1)", 0, 9, t0);
+ TESTINSN5LOAD("lwl $t0, 12($t1)", 0, 12, t0);
+ TESTINSN5LOAD("lwl $t0, 15($t1)", 0, 15, t0);
TESTINSN5LOAD("lwl $t0, 18($t1)", 0, 18, t0);
- TESTINSN5LOAD("lwl $t0, 22($t1)", 0, 22, t0);
- TESTINSN5LOAD("lwl $t0, 26($t1)", 0, 26, t0);
+ TESTINSN5LOAD("lwl $t0, 21($t1)", 0, 21, t0);
+ TESTINSN5LOAD("lwl $t0, 24($t1)", 0, 24, t0);
+ TESTINSN5LOAD("lwl $t0, 27($t1)", 0, 27, t0);
TESTINSN5LOAD("lwl $t0, 30($t1)", 0, 30, t0);
- TESTINSN5LOAD("lwl $t0, 34($t1)", 0, 34, t0);
- TESTINSN5LOAD("lwl $t0, 38($t1)", 0, 38, t0);
+ TESTINSN5LOAD("lwl $t0, 33($t1)", 0, 33, t0);
+ TESTINSN5LOAD("lwl $t0, 36($t1)", 0, 36, t0);
+ TESTINSN5LOAD("lwl $t0, 39($t1)", 0, 39, t0);
+ TESTINSN5LOAD("lwl $t0, 42($t1)", 0, 42, t0);
+ TESTINSN5LOAD("lwl $t0, 45($t1)", 0, 45, t0);
+ TESTINSN5LOAD("lwl $t0, 48($t1)", 0, 48, t0);
+ TESTINSN5LOAD("lwl $t0, 51($t1)", 0, 51, t0);
+ TESTINSN5LOAD("lwl $t0, 54($t1)", 0, 54, t0);
+ TESTINSN5LOAD("lwl $t0, 57($t1)", 0, 57, t0);
+ TESTINSN5LOAD("lwl $t0, 60($t1)", 0, 60, t0);
printf("LWR\n");
- TESTINSN5LOAD("lwr $t0, 0($t1)", 0, 0, t0);
- TESTINSN5LOAD("lwr $t0, 4($t1)", 0, 4, t0);
- TESTINSN5LOAD("lwr $t0, 8($t1)", 0, 8, t0);
+ TESTINSN5LOAD("lwr $t0, 3($t1)", 0, 0, t0);
+ TESTINSN5LOAD("lwr $t0, 6($t1)", 0, 4, t0);
+ TESTINSN5LOAD("lwr $t0, 9($t1)", 0, 8, t0);
TESTINSN5LOAD("lwr $t0, 12($t1)", 0, 12, t0);
- TESTINSN5LOAD("lwr $t0, 16($t1)", 0, 16, t0);
- TESTINSN5LOAD("lwr $t0, 20($t1)", 0, 20, t0);
- TESTINSN5LOAD("lwr $t0, 24($t1)", 0, 24, t0);
- TESTINSN5LOAD("lwr $t0, 28($t1)", 0, 28, t0);
- TESTINSN5LOAD("lwr $t0, 32($t1)", 0, 32, t0);
- TESTINSN5LOAD("lwr $t0, 36($t1)", 0, 36, t0);
- TESTINSN5LOAD("lwr $t0, 40($t1)", 0, 40, t0);
- TESTINSN5LOAD("lwr $t0, 44($t1)", 0, 44, t0);
- TESTINSN5LOAD("lwr $t0, 48($t1)", 0, 48, t0);
- TESTINSN5LOAD("lwr $t0, 52($t1)", 0, 52, t0);
- TESTINSN5LOAD("lwr $t0, 56($t1)", 0, 56, t0);
- TESTINSN5LOAD("lwr $t0, 60($t1)", 0, 60, t0);
- TESTINSN5LOAD("lwr $t0, 64($t1)", 0, 64, t0);
- TESTINSN5LOAD("lwr $t0, 2($t1)", 0, 2, t0);
- TESTINSN5LOAD("lwr $t0, 6($t1)", 0, 6, t0);
- TESTINSN5LOAD("lwr $t0, 10($t1)", 0, 10, t0);
- TESTINSN5LOAD("lwr $t0, 14($t1)", 0, 14, t0);
- TESTINSN5LOAD("lwr $t0, 18($t1)", 0, 18, t0);
- TESTINSN5LOAD("lwr $t0, 22($t1)", 0, 22, t0);
- TESTINSN5LOAD("lwr $t0, 26($t1)", 0, 26, t0);
- TESTINSN5LOAD("lwr $t0, 30($t1)", 0, 30, t0);
- TESTINSN5LOAD("lwr $t0, 34($t1)", 0, 34, t0);
- TESTINSN5LOAD("lwr $t0, 38($t1)", 0, 38, t0);
+ TESTINSN5LOAD("lwr $t0, 15($t1)", 0, 16, t0);
+ TESTINSN5LOAD("lwr $t0, 18($t1)", 0, 20, t0);
+ TESTINSN5LOAD("lwr $t0, 21($t1)", 0, 24, t0);
+ TESTINSN5LOAD("lwr $t0, 24($t1)", 0, 28, t0);
+ TESTINSN5LOAD("lwr $t0, 27($t1)", 0, 32, t0);
+ TESTINSN5LOAD("lwr $t0, 30($t1)", 0, 36, t0);
+ TESTINSN5LOAD("lwr $t0, 33($t1)", 0, 40, t0);
+ TESTINSN5LOAD("lwr $t0, 36($t1)", 0, 44, t0);
+ TESTINSN5LOAD("lwr $t0, 39($t1)", 0, 48, t0);
+ TESTINSN5LOAD("lwr $t0, 42($t1)", 0, 52, t0);
+ TESTINSN5LOAD("lwr $t0, 45($t1)", 0, 56, t0);
+ TESTINSN5LOAD("lwr $t0, 48($t1)", 0, 60, t0);
+ TESTINSN5LOAD("lwr $t0, 51($t1)", 0, 64, t0);
+ TESTINSN5LOAD("lwr $t0, 54($t1)", 0, 2, t0);
+ TESTINSN5LOAD("lwr $t0, 57($t1)", 0, 6, t0);
+ TESTINSN5LOAD("lwr $t0, 60($t1)", 0, 10, t0);
printf("MADD\n");
TESTINST3a("madd $t0, $t1", 0x6, 0x2, t0, t1);
@@ -1211,8 +1196,8 @@
TESTINST2("rotr $t0, $t1, 0x0000000F", 0x31415927, 0x0000000F, t0, t1);
TESTINST2("rotr $t0, $t1, 0x00000010", 0x31415927, 0x00000010, t0, t1);
TESTINST2("rotr $t0, $t1, 0x0000001F", 0x31415927, 0x0000001F, t0, t1);
- TESTINST2("rotr $t0, $t1, 0x00000020", 0x31415927, 0x00000020, t0, t1);
- TESTINST2("rotr $t0, $t1, 0x00000021", 0x31415927, 0x00000021, t0, t1);
+ TESTINST2("rotr $t0, $t1, 0x0000001A", 0x31415927, 0x0000001A, t0, t1);
+ TESTINST2("rotr $t0, $t1, 0x00000007", 0x31415927, 0x00000007, t0, t1);
TESTINST2("rotr $t0, $t1, 0x00000000", 0x00088000, 0x00000000, t0, t1);
TESTINST2("rotr $t0, $t1, 0x00000001", 0x00088000, 0x00000001, t0, t1);
TESTINST2("rotr $t0, $t1, 31", 0x00088000, 31, t0, t1);
@@ -1220,7 +1205,7 @@
TESTINST2("rotr $t0, $t1, 17", 0x00010000, 17, t0, t1);
TESTINST2("rotr $t0, $t1, 18", 0x00010000, 18, t0, t1);
TESTINST2("rotr $t0, $t1, 0", 0, 0, t0, t1);
- TESTINST2("rotr $t0, $t1, 0xffff", 0xffff, 0xffff, t0, t1);
+ TESTINST2("rotr $t0, $t1, 0x1F", 0xFFFF, 0x1F, t0, t1);
#endif
#if (__mips==32) && (__mips_isa_rev>=2)
diff --git a/none/tests/mips32/MIPS32int.stdout.exp-mips32-BE b/none/tests/mips32/MIPS32int.stdout.exp-mips32-BE
index 79bfb3e..738d525 100644
--- a/none/tests/mips32/MIPS32int.stdout.exp-mips32-BE
+++ b/none/tests/mips32/MIPS32int.stdout.exp-mips32-BE
@@ -125,7 +125,7 @@
lb $t0, 52($t1) :: rt 0x0000004e
lb $t0, 56($t1) :: rt 0x00000047
lb $t0, 60($t1) :: rt 0x0000004a
-lb $t0, 64($t1) :: rt 0x00000041
+lb $t0, 1($t1) :: rt 0x0000001f
lb $t0, 2($t1) :: rt 0x0000001e
lb $t0, 6($t1) :: rt 0x00000000
lb $t0, 10($t1) :: rt 0x00000000
@@ -153,7 +153,7 @@
lbu $t0, 52($t1) :: rt 0x0000004e
lbu $t0, 56($t1) :: rt 0x00000047
lbu $t0, 60($t1) :: rt 0x0000004a
-lbu $t0, 64($t1) :: rt 0x00000041
+lbu $t0, 1($t1) :: rt 0x0000001f
lbu $t0, 2($t1) :: rt 0x0000001e
lbu $t0, 6($t1) :: rt 0x00000000
lbu $t0, 10($t1) :: rt 0x00000000
@@ -181,7 +181,7 @@
lh $t0, 52($t1) :: rt 0x00004e46
lh $t0, 56($t1) :: rt 0x0000474d
lh $t0, 60($t1) :: rt 0x00004a48
-lh $t0, 64($t1) :: rt 0x00004144
+lh $t0, 62($t1) :: rt 0x00004a4c
lh $t0, 2($t1) :: rt 0x00001e1f
lh $t0, 6($t1) :: rt 0x00000000
lh $t0, 10($t1) :: rt 0x00000003
@@ -209,7 +209,7 @@
lhu $t0, 52($t1) :: rt 0x00004e46
lhu $t0, 56($t1) :: rt 0x0000474d
lhu $t0, 60($t1) :: rt 0x00004a48
-lhu $t0, 64($t1) :: rt 0x00004144
+lhu $t0, 62($t1) :: rt 0x00004a4c
lhu $t0, 2($t1) :: rt 0x00001e1f
lhu $t0, 6($t1) :: rt 0x00000000
lhu $t0, 10($t1) :: rt 0x00000003
@@ -244,7 +244,6 @@
lw $t0, 52($t1) :: rt 0x4e464d46
lw $t0, 56($t1) :: rt 0x474d474c
lw $t0, 60($t1) :: rt 0x4a484a4c
-lw $t0, 64($t1) :: rt 0x41444400
lw $t0, 2($t1) :: rt 0x1e1f0000
lw $t0, 6($t1) :: rt 0x00000000
lw $t0, 10($t1) :: rt 0x0003ffff
@@ -256,61 +255,47 @@
lw $t0, 34($t1) :: rt 0x3f3e3e35
lw $t0, 38($t1) :: rt 0x3d3c363a
LWL
-lwl $t0, 0($t1) :: rt 0x121f1e1f
-lwl $t0, 4($t1) :: rt 0x00000000
-lwl $t0, 8($t1) :: rt 0x00000003
-lwl $t0, 12($t1) :: rt 0xffffffff
-lwl $t0, 16($t1) :: rt 0x232f2e2f
-lwl $t0, 20($t1) :: rt 0x242c2b2b
-lwl $t0, 24($t1) :: rt 0x252a2e2b
-lwl $t0, 28($t1) :: rt 0x262d2d2a
-lwl $t0, 32($t1) :: rt 0x3f343f3e
-lwl $t0, 36($t1) :: rt 0x3e353d3c
-lwl $t0, 40($t1) :: rt 0x363a3c3b
-lwl $t0, 44($t1) :: rt 0x3b373b3a
-lwl $t0, 48($t1) :: rt 0x454f4e45
-lwl $t0, 52($t1) :: rt 0x4e464d46
-lwl $t0, 56($t1) :: rt 0x474d474c
-lwl $t0, 60($t1) :: rt 0x4a484a4c
-lwl $t0, 64($t1) :: rt 0x41444400
-lwl $t0, 2($t1) :: rt 0x1e1f0000
+lwl $t0, 3($t1) :: rt 0x1f000000
lwl $t0, 6($t1) :: rt 0x00000000
-lwl $t0, 10($t1) :: rt 0x00030000
-lwl $t0, 14($t1) :: rt 0xffff0000
+lwl $t0, 9($t1) :: rt 0x00000300
+lwl $t0, 12($t1) :: rt 0xffffffff
+lwl $t0, 15($t1) :: rt 0xff000000
lwl $t0, 18($t1) :: rt 0x2e2f0000
-lwl $t0, 22($t1) :: rt 0x2b2b0000
-lwl $t0, 26($t1) :: rt 0x2e2b0000
+lwl $t0, 21($t1) :: rt 0x2c2b2b00
+lwl $t0, 24($t1) :: rt 0x252a2e2b
+lwl $t0, 27($t1) :: rt 0x2b000000
lwl $t0, 30($t1) :: rt 0x2d2a0000
-lwl $t0, 34($t1) :: rt 0x3f3e0000
-lwl $t0, 38($t1) :: rt 0x3d3c0000
+lwl $t0, 33($t1) :: rt 0x343f3e00
+lwl $t0, 36($t1) :: rt 0x3e353d3c
+lwl $t0, 39($t1) :: rt 0x3c000000
+lwl $t0, 42($t1) :: rt 0x3c3b0000
+lwl $t0, 45($t1) :: rt 0x373b3a00
+lwl $t0, 48($t1) :: rt 0x454f4e45
+lwl $t0, 51($t1) :: rt 0x45000000
+lwl $t0, 54($t1) :: rt 0x4d460000
+lwl $t0, 57($t1) :: rt 0x4d474c00
+lwl $t0, 60($t1) :: rt 0x4a484a4c
LWR
-lwr $t0, 0($t1) :: rt 0x00000012
-lwr $t0, 4($t1) :: rt 0x00000000
-lwr $t0, 8($t1) :: rt 0x00000000
-lwr $t0, 12($t1) :: rt 0x000000ff
-lwr $t0, 16($t1) :: rt 0x00000023
-lwr $t0, 20($t1) :: rt 0x00000024
-lwr $t0, 24($t1) :: rt 0x00000025
-lwr $t0, 28($t1) :: rt 0x00000026
-lwr $t0, 32($t1) :: rt 0x0000003f
-lwr $t0, 36($t1) :: rt 0x0000003e
-lwr $t0, 40($t1) :: rt 0x00000036
-lwr $t0, 44($t1) :: rt 0x0000003b
-lwr $t0, 48($t1) :: rt 0x00000045
-lwr $t0, 52($t1) :: rt 0x0000004e
-lwr $t0, 56($t1) :: rt 0x00000047
-lwr $t0, 60($t1) :: rt 0x0000004a
-lwr $t0, 64($t1) :: rt 0x00000041
-lwr $t0, 2($t1) :: rt 0x00121f1e
+lwr $t0, 3($t1) :: rt 0x121f1e1f
lwr $t0, 6($t1) :: rt 0x00000000
-lwr $t0, 10($t1) :: rt 0x00000000
-lwr $t0, 14($t1) :: rt 0x00ffffff
+lwr $t0, 9($t1) :: rt 0x00000000
+lwr $t0, 12($t1) :: rt 0x000000ff
+lwr $t0, 15($t1) :: rt 0xffffffff
lwr $t0, 18($t1) :: rt 0x00232f2e
-lwr $t0, 22($t1) :: rt 0x00242c2b
-lwr $t0, 26($t1) :: rt 0x00252a2e
+lwr $t0, 21($t1) :: rt 0x0000242c
+lwr $t0, 24($t1) :: rt 0x00000025
+lwr $t0, 27($t1) :: rt 0x252a2e2b
lwr $t0, 30($t1) :: rt 0x00262d2d
-lwr $t0, 34($t1) :: rt 0x003f343f
-lwr $t0, 38($t1) :: rt 0x003e353d
+lwr $t0, 33($t1) :: rt 0x00003f34
+lwr $t0, 36($t1) :: rt 0x0000003e
+lwr $t0, 39($t1) :: rt 0x3e353d3c
+lwr $t0, 42($t1) :: rt 0x00363a3c
+lwr $t0, 45($t1) :: rt 0x00003b37
+lwr $t0, 48($t1) :: rt 0x00000045
+lwr $t0, 51($t1) :: rt 0x454f4e45
+lwr $t0, 54($t1) :: rt 0x004e464d
+lwr $t0, 57($t1) :: rt 0x0000474d
+lwr $t0, 60($t1) :: rt 0x0000004a
MADD
madd $t0, $t1 :: rs 0x00000006 rt 0x00000002 HI 0x00000000 LO 0x0000000c
madd $t0, $t1 :: rs 0x00000055 rt 0x00000028 HI 0x00000000 LO 0x00000d48
diff --git a/none/tests/mips32/MIPS32int.stdout.exp-mips32-LE b/none/tests/mips32/MIPS32int.stdout.exp-mips32-LE
index e7172e7..65d2b91 100644
--- a/none/tests/mips32/MIPS32int.stdout.exp-mips32-LE
+++ b/none/tests/mips32/MIPS32int.stdout.exp-mips32-LE
@@ -125,7 +125,7 @@
lb $t0, 52($t1) :: rt 0x00000046
lb $t0, 56($t1) :: rt 0x0000004c
lb $t0, 60($t1) :: rt 0x0000004c
-lb $t0, 64($t1) :: rt 0x00000041
+lb $t0, 1($t1) :: rt 0x0000001e
lb $t0, 2($t1) :: rt 0x0000001f
lb $t0, 6($t1) :: rt 0x00000000
lb $t0, 10($t1) :: rt 0x00000000
@@ -153,7 +153,7 @@
lbu $t0, 52($t1) :: rt 0x00000046
lbu $t0, 56($t1) :: rt 0x0000004c
lbu $t0, 60($t1) :: rt 0x0000004c
-lbu $t0, 64($t1) :: rt 0x00000041
+lbu $t0, 1($t1) :: rt 0x0000001e
lbu $t0, 2($t1) :: rt 0x0000001f
lbu $t0, 6($t1) :: rt 0x00000000
lbu $t0, 10($t1) :: rt 0x00000000
@@ -181,7 +181,7 @@
lh $t0, 52($t1) :: rt 0x00004d46
lh $t0, 56($t1) :: rt 0x0000474c
lh $t0, 60($t1) :: rt 0x00004a4c
-lh $t0, 64($t1) :: rt 0x00004441
+lh $t0, 62($t1) :: rt 0x00004a48
lh $t0, 2($t1) :: rt 0x0000121f
lh $t0, 6($t1) :: rt 0x00000000
lh $t0, 10($t1) :: rt 0x00000000
@@ -209,7 +209,7 @@
lhu $t0, 52($t1) :: rt 0x00004d46
lhu $t0, 56($t1) :: rt 0x0000474c
lhu $t0, 60($t1) :: rt 0x00004a4c
-lhu $t0, 64($t1) :: rt 0x00004441
+lhu $t0, 62($t1) :: rt 0x00004a48
lhu $t0, 2($t1) :: rt 0x0000121f
lhu $t0, 6($t1) :: rt 0x00000000
lhu $t0, 10($t1) :: rt 0x00000000
@@ -244,7 +244,6 @@
lw $t0, 52($t1) :: rt 0x4e464d46
lw $t0, 56($t1) :: rt 0x474d474c
lw $t0, 60($t1) :: rt 0x4a484a4c
-lw $t0, 64($t1) :: rt 0x00444441
lw $t0, 2($t1) :: rt 0x0000121f
lw $t0, 6($t1) :: rt 0x00030000
lw $t0, 10($t1) :: rt 0xffff0000
@@ -256,61 +255,47 @@
lw $t0, 34($t1) :: rt 0x3d3c3f34
lw $t0, 38($t1) :: rt 0x3c3b3e35
LWL
-lwl $t0, 0($t1) :: rt 0x1f000000
-lwl $t0, 4($t1) :: rt 0x00000000
-lwl $t0, 8($t1) :: rt 0x03000000
-lwl $t0, 12($t1) :: rt 0xff000000
-lwl $t0, 16($t1) :: rt 0x2f000000
-lwl $t0, 20($t1) :: rt 0x2b000000
-lwl $t0, 24($t1) :: rt 0x2b000000
-lwl $t0, 28($t1) :: rt 0x2a000000
-lwl $t0, 32($t1) :: rt 0x3e000000
-lwl $t0, 36($t1) :: rt 0x3c000000
-lwl $t0, 40($t1) :: rt 0x3b000000
-lwl $t0, 44($t1) :: rt 0x3a000000
-lwl $t0, 48($t1) :: rt 0x45000000
-lwl $t0, 52($t1) :: rt 0x46000000
-lwl $t0, 56($t1) :: rt 0x4c000000
-lwl $t0, 60($t1) :: rt 0x4c000000
-lwl $t0, 64($t1) :: rt 0x41000000
-lwl $t0, 2($t1) :: rt 0x1f1e1f00
+lwl $t0, 3($t1) :: rt 0x121f1e1f
lwl $t0, 6($t1) :: rt 0x00000000
-lwl $t0, 10($t1) :: rt 0x00000300
-lwl $t0, 14($t1) :: rt 0xffffff00
+lwl $t0, 9($t1) :: rt 0x00030000
+lwl $t0, 12($t1) :: rt 0xff000000
+lwl $t0, 15($t1) :: rt 0xffffffff
lwl $t0, 18($t1) :: rt 0x2f2e2f00
-lwl $t0, 22($t1) :: rt 0x2c2b2b00
-lwl $t0, 26($t1) :: rt 0x2a2e2b00
+lwl $t0, 21($t1) :: rt 0x2b2b0000
+lwl $t0, 24($t1) :: rt 0x2b000000
+lwl $t0, 27($t1) :: rt 0x252a2e2b
lwl $t0, 30($t1) :: rt 0x2d2d2a00
-lwl $t0, 34($t1) :: rt 0x343f3e00
-lwl $t0, 38($t1) :: rt 0x353d3c00
+lwl $t0, 33($t1) :: rt 0x3f3e0000
+lwl $t0, 36($t1) :: rt 0x3c000000
+lwl $t0, 39($t1) :: rt 0x3e353d3c
+lwl $t0, 42($t1) :: rt 0x3a3c3b00
+lwl $t0, 45($t1) :: rt 0x3b3a0000
+lwl $t0, 48($t1) :: rt 0x45000000
+lwl $t0, 51($t1) :: rt 0x454f4e45
+lwl $t0, 54($t1) :: rt 0x464d4600
+lwl $t0, 57($t1) :: rt 0x474c0000
+lwl $t0, 60($t1) :: rt 0x4c000000
LWR
-lwr $t0, 0($t1) :: rt 0x121f1e1f
-lwr $t0, 4($t1) :: rt 0x00000000
-lwr $t0, 8($t1) :: rt 0x00000003
-lwr $t0, 12($t1) :: rt 0xffffffff
-lwr $t0, 16($t1) :: rt 0x232f2e2f
-lwr $t0, 20($t1) :: rt 0x242c2b2b
-lwr $t0, 24($t1) :: rt 0x252a2e2b
-lwr $t0, 28($t1) :: rt 0x262d2d2a
-lwr $t0, 32($t1) :: rt 0x3f343f3e
-lwr $t0, 36($t1) :: rt 0x3e353d3c
-lwr $t0, 40($t1) :: rt 0x363a3c3b
-lwr $t0, 44($t1) :: rt 0x3b373b3a
-lwr $t0, 48($t1) :: rt 0x454f4e45
-lwr $t0, 52($t1) :: rt 0x4e464d46
-lwr $t0, 56($t1) :: rt 0x474d474c
-lwr $t0, 60($t1) :: rt 0x4a484a4c
-lwr $t0, 64($t1) :: rt 0x00444441
-lwr $t0, 2($t1) :: rt 0x0000121f
+lwr $t0, 3($t1) :: rt 0x00000012
lwr $t0, 6($t1) :: rt 0x00000000
-lwr $t0, 10($t1) :: rt 0x00000000
-lwr $t0, 14($t1) :: rt 0x0000ffff
+lwr $t0, 9($t1) :: rt 0x00000000
+lwr $t0, 12($t1) :: rt 0xffffffff
+lwr $t0, 15($t1) :: rt 0x000000ff
lwr $t0, 18($t1) :: rt 0x0000232f
-lwr $t0, 22($t1) :: rt 0x0000242c
-lwr $t0, 26($t1) :: rt 0x0000252a
+lwr $t0, 21($t1) :: rt 0x00242c2b
+lwr $t0, 24($t1) :: rt 0x252a2e2b
+lwr $t0, 27($t1) :: rt 0x00000025
lwr $t0, 30($t1) :: rt 0x0000262d
-lwr $t0, 34($t1) :: rt 0x00003f34
-lwr $t0, 38($t1) :: rt 0x00003e35
+lwr $t0, 33($t1) :: rt 0x003f343f
+lwr $t0, 36($t1) :: rt 0x3e353d3c
+lwr $t0, 39($t1) :: rt 0x0000003e
+lwr $t0, 42($t1) :: rt 0x0000363a
+lwr $t0, 45($t1) :: rt 0x003b373b
+lwr $t0, 48($t1) :: rt 0x454f4e45
+lwr $t0, 51($t1) :: rt 0x00000045
+lwr $t0, 54($t1) :: rt 0x00004e46
+lwr $t0, 57($t1) :: rt 0x00474d47
+lwr $t0, 60($t1) :: rt 0x4a484a4c
MADD
madd $t0, $t1 :: rs 0x00000006 rt 0x00000002 HI 0x00000000 LO 0x0000000c
madd $t0, $t1 :: rs 0x00000055 rt 0x00000028 HI 0x00000000 LO 0x00000d48
diff --git a/none/tests/mips32/MIPS32int.stdout.exp-mips32r2-BE b/none/tests/mips32/MIPS32int.stdout.exp-mips32r2-BE
index 62261f9..f57c563 100644
--- a/none/tests/mips32/MIPS32int.stdout.exp-mips32r2-BE
+++ b/none/tests/mips32/MIPS32int.stdout.exp-mips32r2-BE
@@ -511,7 +511,7 @@
lb $t0, 52($t1) :: rt 0x0000004e
lb $t0, 56($t1) :: rt 0x00000047
lb $t0, 60($t1) :: rt 0x0000004a
-lb $t0, 64($t1) :: rt 0x00000041
+lb $t0, 1($t1) :: rt 0x0000001f
lb $t0, 2($t1) :: rt 0x0000001e
lb $t0, 6($t1) :: rt 0x00000000
lb $t0, 10($t1) :: rt 0x00000000
@@ -539,7 +539,7 @@
lbu $t0, 52($t1) :: rt 0x0000004e
lbu $t0, 56($t1) :: rt 0x00000047
lbu $t0, 60($t1) :: rt 0x0000004a
-lbu $t0, 64($t1) :: rt 0x00000041
+lbu $t0, 1($t1) :: rt 0x0000001f
lbu $t0, 2($t1) :: rt 0x0000001e
lbu $t0, 6($t1) :: rt 0x00000000
lbu $t0, 10($t1) :: rt 0x00000000
@@ -567,7 +567,7 @@
lh $t0, 52($t1) :: rt 0x00004e46
lh $t0, 56($t1) :: rt 0x0000474d
lh $t0, 60($t1) :: rt 0x00004a48
-lh $t0, 64($t1) :: rt 0x00004144
+lh $t0, 62($t1) :: rt 0x00004a4c
lh $t0, 2($t1) :: rt 0x00001e1f
lh $t0, 6($t1) :: rt 0x00000000
lh $t0, 10($t1) :: rt 0x00000003
@@ -595,7 +595,7 @@
lhu $t0, 52($t1) :: rt 0x00004e46
lhu $t0, 56($t1) :: rt 0x0000474d
lhu $t0, 60($t1) :: rt 0x00004a48
-lhu $t0, 64($t1) :: rt 0x00004144
+lhu $t0, 62($t1) :: rt 0x00004a4c
lhu $t0, 2($t1) :: rt 0x00001e1f
lhu $t0, 6($t1) :: rt 0x00000000
lhu $t0, 10($t1) :: rt 0x00000003
@@ -630,7 +630,6 @@
lw $t0, 52($t1) :: rt 0x4e464d46
lw $t0, 56($t1) :: rt 0x474d474c
lw $t0, 60($t1) :: rt 0x4a484a4c
-lw $t0, 64($t1) :: rt 0x41444400
lw $t0, 2($t1) :: rt 0x1e1f0000
lw $t0, 6($t1) :: rt 0x00000000
lw $t0, 10($t1) :: rt 0x0003ffff
@@ -642,61 +641,47 @@
lw $t0, 34($t1) :: rt 0x3f3e3e35
lw $t0, 38($t1) :: rt 0x3d3c363a
LWL
-lwl $t0, 0($t1) :: rt 0x121f1e1f
-lwl $t0, 4($t1) :: rt 0x00000000
-lwl $t0, 8($t1) :: rt 0x00000003
-lwl $t0, 12($t1) :: rt 0xffffffff
-lwl $t0, 16($t1) :: rt 0x232f2e2f
-lwl $t0, 20($t1) :: rt 0x242c2b2b
-lwl $t0, 24($t1) :: rt 0x252a2e2b
-lwl $t0, 28($t1) :: rt 0x262d2d2a
-lwl $t0, 32($t1) :: rt 0x3f343f3e
-lwl $t0, 36($t1) :: rt 0x3e353d3c
-lwl $t0, 40($t1) :: rt 0x363a3c3b
-lwl $t0, 44($t1) :: rt 0x3b373b3a
-lwl $t0, 48($t1) :: rt 0x454f4e45
-lwl $t0, 52($t1) :: rt 0x4e464d46
-lwl $t0, 56($t1) :: rt 0x474d474c
-lwl $t0, 60($t1) :: rt 0x4a484a4c
-lwl $t0, 64($t1) :: rt 0x41444400
-lwl $t0, 2($t1) :: rt 0x1e1f0000
+lwl $t0, 3($t1) :: rt 0x1f000000
lwl $t0, 6($t1) :: rt 0x00000000
-lwl $t0, 10($t1) :: rt 0x00030000
-lwl $t0, 14($t1) :: rt 0xffff0000
+lwl $t0, 9($t1) :: rt 0x00000300
+lwl $t0, 12($t1) :: rt 0xffffffff
+lwl $t0, 15($t1) :: rt 0xff000000
lwl $t0, 18($t1) :: rt 0x2e2f0000
-lwl $t0, 22($t1) :: rt 0x2b2b0000
-lwl $t0, 26($t1) :: rt 0x2e2b0000
+lwl $t0, 21($t1) :: rt 0x2c2b2b00
+lwl $t0, 24($t1) :: rt 0x252a2e2b
+lwl $t0, 27($t1) :: rt 0x2b000000
lwl $t0, 30($t1) :: rt 0x2d2a0000
-lwl $t0, 34($t1) :: rt 0x3f3e0000
-lwl $t0, 38($t1) :: rt 0x3d3c0000
+lwl $t0, 33($t1) :: rt 0x343f3e00
+lwl $t0, 36($t1) :: rt 0x3e353d3c
+lwl $t0, 39($t1) :: rt 0x3c000000
+lwl $t0, 42($t1) :: rt 0x3c3b0000
+lwl $t0, 45($t1) :: rt 0x373b3a00
+lwl $t0, 48($t1) :: rt 0x454f4e45
+lwl $t0, 51($t1) :: rt 0x45000000
+lwl $t0, 54($t1) :: rt 0x4d460000
+lwl $t0, 57($t1) :: rt 0x4d474c00
+lwl $t0, 60($t1) :: rt 0x4a484a4c
LWR
-lwr $t0, 0($t1) :: rt 0x00000012
-lwr $t0, 4($t1) :: rt 0x00000000
-lwr $t0, 8($t1) :: rt 0x00000000
-lwr $t0, 12($t1) :: rt 0x000000ff
-lwr $t0, 16($t1) :: rt 0x00000023
-lwr $t0, 20($t1) :: rt 0x00000024
-lwr $t0, 24($t1) :: rt 0x00000025
-lwr $t0, 28($t1) :: rt 0x00000026
-lwr $t0, 32($t1) :: rt 0x0000003f
-lwr $t0, 36($t1) :: rt 0x0000003e
-lwr $t0, 40($t1) :: rt 0x00000036
-lwr $t0, 44($t1) :: rt 0x0000003b
-lwr $t0, 48($t1) :: rt 0x00000045
-lwr $t0, 52($t1) :: rt 0x0000004e
-lwr $t0, 56($t1) :: rt 0x00000047
-lwr $t0, 60($t1) :: rt 0x0000004a
-lwr $t0, 64($t1) :: rt 0x00000041
-lwr $t0, 2($t1) :: rt 0x00121f1e
+lwr $t0, 3($t1) :: rt 0x121f1e1f
lwr $t0, 6($t1) :: rt 0x00000000
-lwr $t0, 10($t1) :: rt 0x00000000
-lwr $t0, 14($t1) :: rt 0x00ffffff
+lwr $t0, 9($t1) :: rt 0x00000000
+lwr $t0, 12($t1) :: rt 0x000000ff
+lwr $t0, 15($t1) :: rt 0xffffffff
lwr $t0, 18($t1) :: rt 0x00232f2e
-lwr $t0, 22($t1) :: rt 0x00242c2b
-lwr $t0, 26($t1) :: rt 0x00252a2e
+lwr $t0, 21($t1) :: rt 0x0000242c
+lwr $t0, 24($t1) :: rt 0x00000025
+lwr $t0, 27($t1) :: rt 0x252a2e2b
lwr $t0, 30($t1) :: rt 0x00262d2d
-lwr $t0, 34($t1) :: rt 0x003f343f
-lwr $t0, 38($t1) :: rt 0x003e353d
+lwr $t0, 33($t1) :: rt 0x00003f34
+lwr $t0, 36($t1) :: rt 0x0000003e
+lwr $t0, 39($t1) :: rt 0x3e353d3c
+lwr $t0, 42($t1) :: rt 0x00363a3c
+lwr $t0, 45($t1) :: rt 0x00003b37
+lwr $t0, 48($t1) :: rt 0x00000045
+lwr $t0, 51($t1) :: rt 0x454f4e45
+lwr $t0, 54($t1) :: rt 0x004e464d
+lwr $t0, 57($t1) :: rt 0x0000474d
+lwr $t0, 60($t1) :: rt 0x0000004a
MADD
madd $t0, $t1 :: rs 0x00000006 rt 0x00000002 HI 0x00000000 LO 0x0000000c
madd $t0, $t1 :: rs 0x00000055 rt 0x00000028 HI 0x00000000 LO 0x00000d48
@@ -1034,8 +1019,8 @@
rotr $t0, $t1, 0x0000000F :: rt 0xb24e6282 rs 0x31415927, imm 0x0000000f
rotr $t0, $t1, 0x00000010 :: rt 0x59273141 rs 0x31415927, imm 0x00000010
rotr $t0, $t1, 0x0000001F :: rt 0x6282b24e rs 0x31415927, imm 0x0000001f
-rotr $t0, $t1, 0x00000020 :: rt 0x31415927 rs 0x31415927, imm 0x00000020
-rotr $t0, $t1, 0x00000021 :: rt 0x98a0ac93 rs 0x31415927, imm 0x00000021
+rotr $t0, $t1, 0x0000001A :: rt 0x505649cc rs 0x31415927, imm 0x0000001a
+rotr $t0, $t1, 0x00000007 :: rt 0x4e6282b2 rs 0x31415927, imm 0x00000007
rotr $t0, $t1, 0x00000000 :: rt 0x00088000 rs 0x00088000, imm 0x00000000
rotr $t0, $t1, 0x00000001 :: rt 0x00044000 rs 0x00088000, imm 0x00000001
rotr $t0, $t1, 31 :: rt 0x00110000 rs 0x00088000, imm 0x0000001f
@@ -1043,7 +1028,7 @@
rotr $t0, $t1, 17 :: rt 0x80000000 rs 0x00010000, imm 0x00000011
rotr $t0, $t1, 18 :: rt 0x40000000 rs 0x00010000, imm 0x00000012
rotr $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
-rotr $t0, $t1, 0xffff :: rt 0x0001fffe rs 0x0000ffff, imm 0x0000ffff
+rotr $t0, $t1, 0x1F :: rt 0x0001fffe rs 0x0000ffff, imm 0x0000001f
ROTRV
rotrv $t0, $t1, $t2 :: rd 0x6282b24e rs 0x31415927, rt 0xffffffff
rotrv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
diff --git a/none/tests/mips32/MIPS32int.stdout.exp-mips32r2-LE b/none/tests/mips32/MIPS32int.stdout.exp-mips32r2-LE
index cfbae0d..4b61ae6 100644
--- a/none/tests/mips32/MIPS32int.stdout.exp-mips32r2-LE
+++ b/none/tests/mips32/MIPS32int.stdout.exp-mips32r2-LE
@@ -511,7 +511,7 @@
lb $t0, 52($t1) :: rt 0x00000046
lb $t0, 56($t1) :: rt 0x0000004c
lb $t0, 60($t1) :: rt 0x0000004c
-lb $t0, 64($t1) :: rt 0x00000041
+lb $t0, 1($t1) :: rt 0x0000001e
lb $t0, 2($t1) :: rt 0x0000001f
lb $t0, 6($t1) :: rt 0x00000000
lb $t0, 10($t1) :: rt 0x00000000
@@ -539,7 +539,7 @@
lbu $t0, 52($t1) :: rt 0x00000046
lbu $t0, 56($t1) :: rt 0x0000004c
lbu $t0, 60($t1) :: rt 0x0000004c
-lbu $t0, 64($t1) :: rt 0x00000041
+lbu $t0, 1($t1) :: rt 0x0000001e
lbu $t0, 2($t1) :: rt 0x0000001f
lbu $t0, 6($t1) :: rt 0x00000000
lbu $t0, 10($t1) :: rt 0x00000000
@@ -567,7 +567,7 @@
lh $t0, 52($t1) :: rt 0x00004d46
lh $t0, 56($t1) :: rt 0x0000474c
lh $t0, 60($t1) :: rt 0x00004a4c
-lh $t0, 64($t1) :: rt 0x00004441
+lh $t0, 62($t1) :: rt 0x00004a48
lh $t0, 2($t1) :: rt 0x0000121f
lh $t0, 6($t1) :: rt 0x00000000
lh $t0, 10($t1) :: rt 0x00000000
@@ -595,7 +595,7 @@
lhu $t0, 52($t1) :: rt 0x00004d46
lhu $t0, 56($t1) :: rt 0x0000474c
lhu $t0, 60($t1) :: rt 0x00004a4c
-lhu $t0, 64($t1) :: rt 0x00004441
+lhu $t0, 62($t1) :: rt 0x00004a48
lhu $t0, 2($t1) :: rt 0x0000121f
lhu $t0, 6($t1) :: rt 0x00000000
lhu $t0, 10($t1) :: rt 0x00000000
@@ -630,7 +630,6 @@
lw $t0, 52($t1) :: rt 0x4e464d46
lw $t0, 56($t1) :: rt 0x474d474c
lw $t0, 60($t1) :: rt 0x4a484a4c
-lw $t0, 64($t1) :: rt 0x00444441
lw $t0, 2($t1) :: rt 0x0000121f
lw $t0, 6($t1) :: rt 0x00030000
lw $t0, 10($t1) :: rt 0xffff0000
@@ -642,61 +641,47 @@
lw $t0, 34($t1) :: rt 0x3d3c3f34
lw $t0, 38($t1) :: rt 0x3c3b3e35
LWL
-lwl $t0, 0($t1) :: rt 0x1f000000
-lwl $t0, 4($t1) :: rt 0x00000000
-lwl $t0, 8($t1) :: rt 0x03000000
-lwl $t0, 12($t1) :: rt 0xff000000
-lwl $t0, 16($t1) :: rt 0x2f000000
-lwl $t0, 20($t1) :: rt 0x2b000000
-lwl $t0, 24($t1) :: rt 0x2b000000
-lwl $t0, 28($t1) :: rt 0x2a000000
-lwl $t0, 32($t1) :: rt 0x3e000000
-lwl $t0, 36($t1) :: rt 0x3c000000
-lwl $t0, 40($t1) :: rt 0x3b000000
-lwl $t0, 44($t1) :: rt 0x3a000000
-lwl $t0, 48($t1) :: rt 0x45000000
-lwl $t0, 52($t1) :: rt 0x46000000
-lwl $t0, 56($t1) :: rt 0x4c000000
-lwl $t0, 60($t1) :: rt 0x4c000000
-lwl $t0, 64($t1) :: rt 0x41000000
-lwl $t0, 2($t1) :: rt 0x1f1e1f00
+lwl $t0, 3($t1) :: rt 0x121f1e1f
lwl $t0, 6($t1) :: rt 0x00000000
-lwl $t0, 10($t1) :: rt 0x00000300
-lwl $t0, 14($t1) :: rt 0xffffff00
+lwl $t0, 9($t1) :: rt 0x00030000
+lwl $t0, 12($t1) :: rt 0xff000000
+lwl $t0, 15($t1) :: rt 0xffffffff
lwl $t0, 18($t1) :: rt 0x2f2e2f00
-lwl $t0, 22($t1) :: rt 0x2c2b2b00
-lwl $t0, 26($t1) :: rt 0x2a2e2b00
+lwl $t0, 21($t1) :: rt 0x2b2b0000
+lwl $t0, 24($t1) :: rt 0x2b000000
+lwl $t0, 27($t1) :: rt 0x252a2e2b
lwl $t0, 30($t1) :: rt 0x2d2d2a00
-lwl $t0, 34($t1) :: rt 0x343f3e00
-lwl $t0, 38($t1) :: rt 0x353d3c00
+lwl $t0, 33($t1) :: rt 0x3f3e0000
+lwl $t0, 36($t1) :: rt 0x3c000000
+lwl $t0, 39($t1) :: rt 0x3e353d3c
+lwl $t0, 42($t1) :: rt 0x3a3c3b00
+lwl $t0, 45($t1) :: rt 0x3b3a0000
+lwl $t0, 48($t1) :: rt 0x45000000
+lwl $t0, 51($t1) :: rt 0x454f4e45
+lwl $t0, 54($t1) :: rt 0x464d4600
+lwl $t0, 57($t1) :: rt 0x474c0000
+lwl $t0, 60($t1) :: rt 0x4c000000
LWR
-lwr $t0, 0($t1) :: rt 0x121f1e1f
-lwr $t0, 4($t1) :: rt 0x00000000
-lwr $t0, 8($t1) :: rt 0x00000003
-lwr $t0, 12($t1) :: rt 0xffffffff
-lwr $t0, 16($t1) :: rt 0x232f2e2f
-lwr $t0, 20($t1) :: rt 0x242c2b2b
-lwr $t0, 24($t1) :: rt 0x252a2e2b
-lwr $t0, 28($t1) :: rt 0x262d2d2a
-lwr $t0, 32($t1) :: rt 0x3f343f3e
-lwr $t0, 36($t1) :: rt 0x3e353d3c
-lwr $t0, 40($t1) :: rt 0x363a3c3b
-lwr $t0, 44($t1) :: rt 0x3b373b3a
-lwr $t0, 48($t1) :: rt 0x454f4e45
-lwr $t0, 52($t1) :: rt 0x4e464d46
-lwr $t0, 56($t1) :: rt 0x474d474c
-lwr $t0, 60($t1) :: rt 0x4a484a4c
-lwr $t0, 64($t1) :: rt 0x00444441
-lwr $t0, 2($t1) :: rt 0x0000121f
+lwr $t0, 3($t1) :: rt 0x00000012
lwr $t0, 6($t1) :: rt 0x00000000
-lwr $t0, 10($t1) :: rt 0x00000000
-lwr $t0, 14($t1) :: rt 0x0000ffff
+lwr $t0, 9($t1) :: rt 0x00000000
+lwr $t0, 12($t1) :: rt 0xffffffff
+lwr $t0, 15($t1) :: rt 0x000000ff
lwr $t0, 18($t1) :: rt 0x0000232f
-lwr $t0, 22($t1) :: rt 0x0000242c
-lwr $t0, 26($t1) :: rt 0x0000252a
+lwr $t0, 21($t1) :: rt 0x00242c2b
+lwr $t0, 24($t1) :: rt 0x252a2e2b
+lwr $t0, 27($t1) :: rt 0x00000025
lwr $t0, 30($t1) :: rt 0x0000262d
-lwr $t0, 34($t1) :: rt 0x00003f34
-lwr $t0, 38($t1) :: rt 0x00003e35
+lwr $t0, 33($t1) :: rt 0x003f343f
+lwr $t0, 36($t1) :: rt 0x3e353d3c
+lwr $t0, 39($t1) :: rt 0x0000003e
+lwr $t0, 42($t1) :: rt 0x0000363a
+lwr $t0, 45($t1) :: rt 0x003b373b
+lwr $t0, 48($t1) :: rt 0x454f4e45
+lwr $t0, 51($t1) :: rt 0x00000045
+lwr $t0, 54($t1) :: rt 0x00004e46
+lwr $t0, 57($t1) :: rt 0x00474d47
+lwr $t0, 60($t1) :: rt 0x4a484a4c
MADD
madd $t0, $t1 :: rs 0x00000006 rt 0x00000002 HI 0x00000000 LO 0x0000000c
madd $t0, $t1 :: rs 0x00000055 rt 0x00000028 HI 0x00000000 LO 0x00000d48
@@ -1034,8 +1019,8 @@
rotr $t0, $t1, 0x0000000F :: rt 0xb24e6282 rs 0x31415927, imm 0x0000000f
rotr $t0, $t1, 0x00000010 :: rt 0x59273141 rs 0x31415927, imm 0x00000010
rotr $t0, $t1, 0x0000001F :: rt 0x6282b24e rs 0x31415927, imm 0x0000001f
-rotr $t0, $t1, 0x00000020 :: rt 0x31415927 rs 0x31415927, imm 0x00000020
-rotr $t0, $t1, 0x00000021 :: rt 0x98a0ac93 rs 0x31415927, imm 0x00000021
+rotr $t0, $t1, 0x0000001A :: rt 0x505649cc rs 0x31415927, imm 0x0000001a
+rotr $t0, $t1, 0x00000007 :: rt 0x4e6282b2 rs 0x31415927, imm 0x00000007
rotr $t0, $t1, 0x00000000 :: rt 0x00088000 rs 0x00088000, imm 0x00000000
rotr $t0, $t1, 0x00000001 :: rt 0x00044000 rs 0x00088000, imm 0x00000001
rotr $t0, $t1, 31 :: rt 0x00110000 rs 0x00088000, imm 0x0000001f
@@ -1043,7 +1028,7 @@
rotr $t0, $t1, 17 :: rt 0x80000000 rs 0x00010000, imm 0x00000011
rotr $t0, $t1, 18 :: rt 0x40000000 rs 0x00010000, imm 0x00000012
rotr $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
-rotr $t0, $t1, 0xffff :: rt 0x0001fffe rs 0x0000ffff, imm 0x0000ffff
+rotr $t0, $t1, 0x1F :: rt 0x0001fffe rs 0x0000ffff, imm 0x0000001f
ROTRV
rotrv $t0, $t1, $t2 :: rd 0x6282b24e rs 0x31415927, rt 0xffffffff
rotrv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
diff --git a/none/tests/mips32/Makefile.in b/none/tests/mips32/Makefile.in
index 74970d2..c45d18d 100644
--- a/none/tests/mips32/Makefile.in
+++ b/none/tests/mips32/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -336,6 +336,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -506,6 +507,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -516,6 +518,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -590,8 +593,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -636,7 +637,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/none/tests/mips32/MoveIns.c b/none/tests/mips32/MoveIns.c
index ce2cb13..691a796 100644
--- a/none/tests/mips32/MoveIns.c
+++ b/none/tests/mips32/MoveIns.c
@@ -354,7 +354,7 @@
TESTINSNMOVEtd("mthc1 $v1, $f6", 12, 24, f6, v1);
TESTINSNMOVEtd("mthc1 $a0, $f8", 16, 32, f8, a0);
TESTINSNMOVEtd("mthc1 $a1, $f10", 20, 40, f10, a1);
- TESTINSNMOVEtd("mthc1 $a2, $f12", 24, 48, f12, a1);
+ TESTINSNMOVEtd("mthc1 $a2, $f12", 24, 48, f12, a2);
TESTINSNMOVEtd("mthc1 $a3, $f14", 28, 56, f14, a3);
TESTINSNMOVEtd("mthc1 $s0, $f16", 32, 64, f16, s0);
TESTINSNMOVEtd("mthc1 $s1, $f18", 36, 72, f18, s1);
diff --git a/none/tests/mips32/MoveIns.stdout.exp-mips32r2-BE b/none/tests/mips32/MoveIns.stdout.exp-mips32r2-BE
index a354f3b..5351d4e 100644
--- a/none/tests/mips32/MoveIns.stdout.exp-mips32r2-BE
+++ b/none/tests/mips32/MoveIns.stdout.exp-mips32r2-BE
@@ -78,7 +78,7 @@
mthc1 $v1, $f6 :: out: 36500000
mthc1 $a0, $f8 :: out: 3ff0000056789600
mthc1 $a1, $f10 :: out: 78000000
-mthc1 $a2, $f12 :: out: 1252a2e2b
+mthc1 $a2, $f12 :: out: 252a2e2b252a2e2b
mthc1 $a3, $f14 :: out: 262d2d2a962d2d2a
mthc1 $s0, $f16 :: out: ffffffff87654321
mthc1 $s1, $f18 :: out: ffffffff68466667
diff --git a/none/tests/mips32/MoveIns.stdout.exp-mips32r2-LE b/none/tests/mips32/MoveIns.stdout.exp-mips32r2-LE
index 22f1ab9..9c0650b 100644
--- a/none/tests/mips32/MoveIns.stdout.exp-mips32r2-LE
+++ b/none/tests/mips32/MoveIns.stdout.exp-mips32r2-LE
@@ -78,7 +78,7 @@
mthc1 $v1, $f6 :: out: 36500000
mthc1 $a0, $f8 :: out: 3ff0000056789600
mthc1 $a1, $f10 :: out: 78000000
-mthc1 $a2, $f12 :: out: 1252a2e2b
+mthc1 $a2, $f12 :: out: 252a2e2b252a2e2b
mthc1 $a3, $f14 :: out: 262d2d2a962d2d2a
mthc1 $s0, $f16 :: out: ffffffff87654321
mthc1 $s1, $f18 :: out: ffffffff68466667
diff --git a/none/tests/mips32/branches.c b/none/tests/mips32/branches.c
index f455195..3b994c6 100644
--- a/none/tests/mips32/branches.c
+++ b/none/tests/mips32/branches.c
@@ -4,6 +4,8 @@
{ \
unsigned int out = 0; \
__asm__ volatile( \
+ ".set push \n\t" \
+ ".set noreorder \n\t" \
"move $" #RD ", %1\n\t" \
"b end"#RSval"\n\t" \
"nop\n\t" \
@@ -11,9 +13,10 @@
"end"#RSval":\n\t" \
"addi $" #RD ", $" #RD", 1\n\t" \
"move %0, $" #RD "\n\t" \
+ ".set pop \n\t" \
: "=&r" (out) \
: "r" (RSval) \
- : #RD, "cc", "memory" \
+ : #RD, "memory" \
); \
printf("B :: %d, RSval: %d\n", \
out, RSval); \
@@ -23,6 +26,8 @@
{ \
unsigned int out = 0; \
__asm__ volatile( \
+ ".set push \n\t" \
+ ".set noreorder \n\t" \
"move $" #RD ", %1\n\t" \
"b end12"#RSval"\n\t" \
"addi $" #RD ", $" #RD", 3\n\t" \
@@ -30,9 +35,10 @@
"end12"#RSval":\n\t" \
"addi $" #RD ", $" #RD", 3\n\t" \
"move %0, $" #RD "\n\t" \
+ ".set pop \n\t" \
: "=&r" (out) \
: "r" (RSval) \
- : #RD, "cc", "memory" \
+ : #RD, "memory" \
); \
printf("B :: %d, RSval: %d\n", \
out, RSval); \
@@ -42,6 +48,8 @@
{ \
unsigned int out = 0; \
__asm__ volatile( \
+ ".set push \n\t" \
+ ".set noreorder \n\t" \
"move $" #RD ", %1\n\t" \
"bal end21"#RSval"\n\t" \
"nop\n\t" \
@@ -53,9 +61,10 @@
"jr $ra\n\t" \
"r_end"#RSval":\n\t" \
"move %0, $" #RD "\n\t" \
+ ".set pop \n\t" \
: "=&r" (out) \
: "r" (RSval) \
- : #RD, "cc", "memory" \
+ : #RD, "memory" \
); \
printf("B BAL JR :: %d, RSval: %d\n", \
out, RSval); \
@@ -65,6 +74,8 @@
{ \
unsigned int out = 0; \
__asm__ volatile( \
+ ".set push \n\t" \
+ ".set noreorder \n\t" \
"move $" #RD ", %1\n\t" \
"la $t0, end31"#RSval"\n\t" \
"jal $t0\n\t" \
@@ -78,9 +89,10 @@
"jr $ra\n\t" \
"r_end11"#RSval":\n\t" \
"move %0, $" #RD "\n\t" \
+ ".set pop \n\t" \
: "=&r" (out) \
: "r" (RSval) \
- : #RD, "t0", "cc", "memory" \
+ : #RD, "t0", "memory" \
); \
printf("J JAL JR :: %d, RSval: %d\n", \
out, RSval); \
@@ -90,6 +102,8 @@
{ \
unsigned int out = 0; \
__asm__ volatile( \
+ ".set push \n\t" \
+ ".set noreorder \n\t" \
"move $" #RD ", %1\n\t" \
"la $t0, end41"#RSval"\n\t" \
"jalr $t1, $t0\n\t" \
@@ -103,9 +117,10 @@
"jr $t1\n\t" \
"r_end21"#RSval":\n\t" \
"move %0, $" #RD "\n\t" \
+ ".set pop \n\t" \
: "=&r" (out) \
: "r" (RSval) \
- : #RD, "t0", "t1", "cc", "memory" \
+ : #RD, "t0", "t1", "memory" \
); \
printf("J JALR JR :: %d, RSval: %d\n", \
out, RSval); \
@@ -115,6 +130,8 @@
{ \
unsigned int out = 0; \
__asm__ volatile( \
+ ".set push \n\t" \
+ ".set noreorder \n\t" \
"move $" #RS ", %1\n\t" \
"move $" #RT ", %2\n\t" \
"move $" #RD ", %3\n\t" \
@@ -124,9 +141,10 @@
"end"instruction#RDval":\n\t" \
"addi $" #RD ", $" #RD", 1\n\t" \
"move %0, $" #RD "\n\t" \
+ ".set pop \n\t" \
: "=&r" (out) \
: "r" (RSval), "r" (RTval), "r" (RDval) \
- : #RD, #RS, #RT, "cc", "memory" \
+ : #RD, #RS, #RT, "memory" \
); \
printf(instruction" :: %d, RSval: %d, RTval: %d\n", \
out, RSval, RTval); \
@@ -136,6 +154,8 @@
{ \
unsigned int out = 0; \
__asm__ volatile( \
+ ".set push \n\t" \
+ ".set noreorder \n\t" \
"move $" #RS ", %1\n\t" \
"move $" #RD ", %2\n\t" \
instruction" $" #RS ", end"instruction#RDval"\n\t" \
@@ -144,9 +164,10 @@
"end"instruction#RDval":\n\t" \
"addi $" #RD ", $" #RD", 1\n\t" \
"move %0, $" #RD "\n\t" \
+ ".set pop \n\t" \
: "=&r" (out) \
: "r" (RSval), "r" (RDval) \
- : #RD, #RS, "cc", "memory" \
+ : #RD, #RS, "memory" \
); \
printf(instruction" :: %d, RSval: %d\n", \
out, RSval); \
@@ -156,6 +177,8 @@
{ \
unsigned int out = 0; \
__asm__ volatile( \
+ ".set push \n\t" \
+ ".set noreorder \n\t" \
"move $" #RD ", %2\n\t" \
"move $" #RS ", %1\n\t" \
instruction" $" #RS ", end21"instruction#RDval"\n\t" \
@@ -168,9 +191,10 @@
"jr $ra\n\t" \
"r_end"instruction#RDval":\n\t" \
"move %0, $" #RD "\n\t" \
+ ".set pop \n\t" \
: "=&r" (out) \
: "r" (RSval), "r" (RDval) \
- : #RD, #RS, "cc", "memory" \
+ : #RD, #RS, "memory" \
); \
printf(instruction" :: %d, RSval: %d\n", \
out, RSval); \
@@ -180,6 +204,8 @@
{ \
unsigned int out = 0; \
__asm__ volatile( \
+ ".set push \n\t" \
+ ".set noreorder \n\t" \
"move $" #RS ", %1\n\t" \
"move $" #RT ", %2\n\t" \
"move $" #RD ", %3\n\t" \
@@ -189,9 +215,10 @@
"end"instruction#RDval":\n\t" \
"addi $" #RD ", $" #RD", 1\n\t" \
"move %0, $" #RD "\n\t" \
+ ".set pop \n\t" \
: "=&r" (out) \
: "r" (RSval), "r" (RTval), "r" (RDval) \
- : #RD, #RS, #RT, "cc", "memory" \
+ : #RD, #RS, #RT, "memory" \
); \
printf(instruction" :: %d, RSval: %d, RTval: %d\n", \
out, RSval, RTval); \
@@ -201,6 +228,8 @@
{ \
unsigned int out = 0; \
__asm__ volatile( \
+ ".set push \n\t" \
+ ".set noreorder \n\t" \
"move $" #RS ", %1\n\t" \
"move $" #RD ", %2\n\t" \
instruction" $" #RS ", end"instruction#RDval"\n\t" \
@@ -209,9 +238,10 @@
"end"instruction#RDval":\n\t" \
"addi $" #RD ", $" #RD", 1\n\t" \
"move %0, $" #RD "\n\t" \
+ ".set pop \n\t" \
: "=&r" (out) \
: "r" (RSval), "r" (RDval) \
- : #RD, #RS, "cc", "memory" \
+ : #RD, #RS, "memory" \
); \
printf(instruction" :: %d, RSval: %d\n", \
out, RSval); \
@@ -221,6 +251,8 @@
{ \
unsigned int out = 0; \
__asm__ volatile( \
+ ".set push \n\t" \
+ ".set noreorder \n\t" \
"move $" #RD ", %2\n\t" \
"move $" #RS ", %1\n\t" \
instruction" $" #RS ", end21"instruction#RDval"\n\t" \
@@ -233,9 +265,10 @@
"jr $ra\n\t" \
"r_end"instruction#RDval":\n\t" \
"move %0, $" #RD "\n\t" \
+ ".set pop \n\t" \
: "=&r" (out) \
: "r" (RSval), "r" (RDval) \
- : #RD, #RS, "cc", "memory" \
+ : #RD, #RS, "memory" \
); \
printf(instruction" :: %d, RSval: %d\n", \
out, RSval); \
diff --git a/none/tests/mips32/branches.stdout.exp b/none/tests/mips32/branches.stdout.exp
index f22933b..369f461 100644
--- a/none/tests/mips32/branches.stdout.exp
+++ b/none/tests/mips32/branches.stdout.exp
@@ -24,30 +24,30 @@
B :: 23, RSval: 22
B :: 24, RSval: 23
b
-B :: 3, RSval: 0
-B :: 4, RSval: 1
-B :: 5, RSval: 2
-B :: 6, RSval: 3
-B :: 7, RSval: 4
-B :: 8, RSval: 5
-B :: 9, RSval: 6
-B :: 10, RSval: 7
-B :: 11, RSval: 8
-B :: 12, RSval: 9
-B :: 13, RSval: 10
-B :: 14, RSval: 11
-B :: 15, RSval: 12
-B :: 16, RSval: 13
-B :: 17, RSval: 14
-B :: 18, RSval: 15
-B :: 19, RSval: 16
-B :: 20, RSval: 17
-B :: 21, RSval: 18
-B :: 22, RSval: 19
-B :: 23, RSval: 20
-B :: 24, RSval: 21
-B :: 25, RSval: 22
-B :: 26, RSval: 23
+B :: 6, RSval: 0
+B :: 7, RSval: 1
+B :: 8, RSval: 2
+B :: 9, RSval: 3
+B :: 10, RSval: 4
+B :: 11, RSval: 5
+B :: 12, RSval: 6
+B :: 13, RSval: 7
+B :: 14, RSval: 8
+B :: 15, RSval: 9
+B :: 16, RSval: 10
+B :: 17, RSval: 11
+B :: 18, RSval: 12
+B :: 19, RSval: 13
+B :: 20, RSval: 14
+B :: 21, RSval: 15
+B :: 22, RSval: 16
+B :: 23, RSval: 17
+B :: 24, RSval: 18
+B :: 25, RSval: 19
+B :: 26, RSval: 20
+B :: 27, RSval: 21
+B :: 28, RSval: 22
+B :: 29, RSval: 23
b, bal, jr
B BAL JR :: 6, RSval: 0
B BAL JR :: 7, RSval: 1
@@ -244,141 +244,141 @@
bnez :: 15, RSval: -1
bnez :: 16, RSval: -1
beql
-beql :: 9, RSval: 0, RTval: 1
-beql :: 2, RSval: 1, RTval: 1
-beql :: 3, RSval: -1, RTval: -1
-beql :: 12, RSval: -1, RTval: -2
-beql :: 13, RSval: -2, RTval: -1
+beql :: 6, RSval: 0, RTval: 1
+beql :: 5, RSval: 1, RTval: 1
beql :: 6, RSval: -1, RTval: -1
-beql :: 7, RSval: 5, RTval: 5
-beql :: 16, RSval: -3, RTval: -4
-beql :: 9, RSval: 125, RTval: 125
-beql :: 10, RSval: -2147483648, RTval: -2147483648
-beql :: 19, RSval: -1, RTval: -2147483648
-beql :: 12, RSval: 598, RTval: 598
-beql :: 13, RSval: 85, RTval: 85
-beql :: 22, RSval: 4095, RTval: 221
-beql :: 23, RSval: -1, RTval: 5
-beql :: 16, RSval: -1, RTval: -1
+beql :: 9, RSval: -1, RTval: -2
+beql :: 10, RSval: -2, RTval: -1
+beql :: 9, RSval: -1, RTval: -1
+beql :: 10, RSval: 5, RTval: 5
+beql :: 13, RSval: -3, RTval: -4
+beql :: 12, RSval: 125, RTval: 125
+beql :: 13, RSval: -2147483648, RTval: -2147483648
+beql :: 16, RSval: -1, RTval: -2147483648
+beql :: 15, RSval: 598, RTval: 598
+beql :: 16, RSval: 85, RTval: 85
+beql :: 19, RSval: 4095, RTval: 221
+beql :: 20, RSval: -1, RTval: 5
+beql :: 19, RSval: -1, RTval: -1
BGEZALL
-bgezall :: 1, RSval: 0
-bgezall :: 2, RSval: 1
+bgezall :: 4, RSval: 0
+bgezall :: 5, RSval: 1
+bgezall :: 8, RSval: -1
+bgezall :: 9, RSval: -1
+bgezall :: 10, RSval: -2
bgezall :: 11, RSval: -1
-bgezall :: 12, RSval: -1
-bgezall :: 13, RSval: -2
-bgezall :: 14, RSval: -1
-bgezall :: 7, RSval: 5
-bgezall :: 16, RSval: -3
-bgezall :: 9, RSval: 125
-bgezall :: 18, RSval: -2147483648
-bgezall :: 19, RSval: -1
-bgezall :: 12, RSval: 598
-bgezall :: 13, RSval: 85
-bgezall :: 14, RSval: 4095
-bgezall :: 23, RSval: -1
-bgezall :: 24, RSval: -1
+bgezall :: 10, RSval: 5
+bgezall :: 13, RSval: -3
+bgezall :: 12, RSval: 125
+bgezall :: 15, RSval: -2147483648
+bgezall :: 16, RSval: -1
+bgezall :: 15, RSval: 598
+bgezall :: 16, RSval: 85
+bgezall :: 17, RSval: 4095
+bgezall :: 20, RSval: -1
+bgezall :: 21, RSval: -1
BGEZL
-bgezl :: 1, RSval: 0
-bgezl :: 2, RSval: 1
+bgezl :: 4, RSval: 0
+bgezl :: 5, RSval: 1
+bgezl :: 8, RSval: -1
+bgezl :: 9, RSval: -1
+bgezl :: 10, RSval: -2
bgezl :: 11, RSval: -1
-bgezl :: 12, RSval: -1
-bgezl :: 13, RSval: -2
-bgezl :: 14, RSval: -1
-bgezl :: 7, RSval: 5
-bgezl :: 16, RSval: -3
-bgezl :: 9, RSval: 125
-bgezl :: 18, RSval: -2147483648
-bgezl :: 19, RSval: -1
-bgezl :: 12, RSval: 598
-bgezl :: 13, RSval: 85
-bgezl :: 14, RSval: 4095
-bgezl :: 23, RSval: -1
-bgezl :: 24, RSval: -1
+bgezl :: 10, RSval: 5
+bgezl :: 13, RSval: -3
+bgezl :: 12, RSval: 125
+bgezl :: 15, RSval: -2147483648
+bgezl :: 16, RSval: -1
+bgezl :: 15, RSval: 598
+bgezl :: 16, RSval: 85
+bgezl :: 17, RSval: 4095
+bgezl :: 20, RSval: -1
+bgezl :: 21, RSval: -1
BGTZL
-bgtzl :: 9, RSval: 0
-bgtzl :: 2, RSval: 1
+bgtzl :: 6, RSval: 0
+bgtzl :: 5, RSval: 1
+bgtzl :: 8, RSval: -1
+bgtzl :: 9, RSval: -1
+bgtzl :: 10, RSval: -2
bgtzl :: 11, RSval: -1
-bgtzl :: 12, RSval: -1
-bgtzl :: 13, RSval: -2
-bgtzl :: 14, RSval: -1
-bgtzl :: 7, RSval: 5
-bgtzl :: 16, RSval: -3
-bgtzl :: 9, RSval: 125
-bgtzl :: 18, RSval: -2147483648
-bgtzl :: 19, RSval: -1
-bgtzl :: 12, RSval: 598
-bgtzl :: 13, RSval: 85
-bgtzl :: 14, RSval: 4095
-bgtzl :: 23, RSval: -1
-bgtzl :: 24, RSval: -1
+bgtzl :: 10, RSval: 5
+bgtzl :: 13, RSval: -3
+bgtzl :: 12, RSval: 125
+bgtzl :: 15, RSval: -2147483648
+bgtzl :: 16, RSval: -1
+bgtzl :: 15, RSval: 598
+bgtzl :: 16, RSval: 85
+bgtzl :: 17, RSval: 4095
+bgtzl :: 20, RSval: -1
+bgtzl :: 21, RSval: -1
BLEZL
-blezl :: 1, RSval: 0
-blezl :: 10, RSval: 1
-blezl :: 3, RSval: -1
-blezl :: 4, RSval: -1
-blezl :: 5, RSval: -2
+blezl :: 4, RSval: 0
+blezl :: 7, RSval: 1
blezl :: 6, RSval: -1
-blezl :: 15, RSval: 5
-blezl :: 8, RSval: -3
-blezl :: 17, RSval: 125
-blezl :: 10, RSval: -2147483648
-blezl :: 11, RSval: -1
-blezl :: 20, RSval: 598
-blezl :: 21, RSval: 85
-blezl :: 22, RSval: 4095
-blezl :: 15, RSval: -1
-blezl :: 16, RSval: -1
+blezl :: 7, RSval: -1
+blezl :: 8, RSval: -2
+blezl :: 9, RSval: -1
+blezl :: 12, RSval: 5
+blezl :: 11, RSval: -3
+blezl :: 14, RSval: 125
+blezl :: 13, RSval: -2147483648
+blezl :: 14, RSval: -1
+blezl :: 17, RSval: 598
+blezl :: 18, RSval: 85
+blezl :: 19, RSval: 4095
+blezl :: 18, RSval: -1
+blezl :: 19, RSval: -1
BGEZALL
bgezall :: 9, RSval: 0
bgezall :: 10, RSval: 1
+bgezall :: 7, RSval: -1
+bgezall :: 8, RSval: -1
+bgezall :: 9, RSval: -2
bgezall :: 10, RSval: -1
-bgezall :: 11, RSval: -1
-bgezall :: 12, RSval: -2
-bgezall :: 13, RSval: -1
bgezall :: 15, RSval: 5
-bgezall :: 15, RSval: -3
+bgezall :: 12, RSval: -3
bgezall :: 17, RSval: 125
-bgezall :: 17, RSval: -2147483648
-bgezall :: 18, RSval: -1
+bgezall :: 14, RSval: -2147483648
+bgezall :: 15, RSval: -1
bgezall :: 20, RSval: 598
bgezall :: 21, RSval: 85
bgezall :: 22, RSval: 4095
-bgezall :: 22, RSval: -1
-bgezall :: 23, RSval: -1
+bgezall :: 19, RSval: -1
+bgezall :: 20, RSval: -1
BLTZL
-bltzl :: 9, RSval: 0
-bltzl :: 10, RSval: 1
-bltzl :: 3, RSval: -1
-bltzl :: 4, RSval: -1
-bltzl :: 5, RSval: -2
+bltzl :: 6, RSval: 0
+bltzl :: 7, RSval: 1
bltzl :: 6, RSval: -1
-bltzl :: 15, RSval: 5
-bltzl :: 8, RSval: -3
-bltzl :: 17, RSval: 125
-bltzl :: 10, RSval: -2147483648
-bltzl :: 11, RSval: -1
-bltzl :: 20, RSval: 598
-bltzl :: 21, RSval: 85
-bltzl :: 22, RSval: 4095
-bltzl :: 15, RSval: -1
-bltzl :: 16, RSval: -1
+bltzl :: 7, RSval: -1
+bltzl :: 8, RSval: -2
+bltzl :: 9, RSval: -1
+bltzl :: 12, RSval: 5
+bltzl :: 11, RSval: -3
+bltzl :: 14, RSval: 125
+bltzl :: 13, RSval: -2147483648
+bltzl :: 14, RSval: -1
+bltzl :: 17, RSval: 598
+bltzl :: 18, RSval: 85
+bltzl :: 19, RSval: 4095
+bltzl :: 18, RSval: -1
+bltzl :: 19, RSval: -1
BNEL
-bnel :: 1, RSval: 0, RTval: 1
-bnel :: 10, RSval: 1, RTval: 1
+bnel :: 4, RSval: 0, RTval: 1
+bnel :: 7, RSval: 1, RTval: 1
+bnel :: 8, RSval: -1, RTval: -1
+bnel :: 7, RSval: -1, RTval: -2
+bnel :: 8, RSval: -2, RTval: -1
bnel :: 11, RSval: -1, RTval: -1
-bnel :: 4, RSval: -1, RTval: -2
-bnel :: 5, RSval: -2, RTval: -1
-bnel :: 14, RSval: -1, RTval: -1
-bnel :: 15, RSval: 5, RTval: 5
-bnel :: 8, RSval: -3, RTval: -4
-bnel :: 17, RSval: 125, RTval: 125
-bnel :: 18, RSval: -2147483648, RTval: -2147483648
-bnel :: 11, RSval: -1, RTval: -2147483648
-bnel :: 20, RSval: 598, RTval: 598
-bnel :: 21, RSval: 85, RTval: 85
-bnel :: 14, RSval: 4095, RTval: 221
-bnel :: 15, RSval: -1, RTval: 5
-bnel :: 24, RSval: -1, RTval: -1
+bnel :: 12, RSval: 5, RTval: 5
+bnel :: 11, RSval: -3, RTval: -4
+bnel :: 14, RSval: 125, RTval: 125
+bnel :: 15, RSval: -2147483648, RTval: -2147483648
+bnel :: 14, RSval: -1, RTval: -2147483648
+bnel :: 17, RSval: 598, RTval: 598
+bnel :: 18, RSval: 85, RTval: 85
+bnel :: 17, RSval: 4095, RTval: 221
+bnel :: 18, RSval: -1, RTval: 5
+bnel :: 21, RSval: -1, RTval: -1
j, jal, jr
J JAL JR :: 6, RSval: 0
J JAL JR :: 7, RSval: 1
diff --git a/none/tests/mips32/round_fpu64.c b/none/tests/mips32/round_fpu64.c
index a4715f2..e35c8b5 100644
--- a/none/tests/mips32/round_fpu64.c
+++ b/none/tests/mips32/round_fpu64.c
@@ -72,7 +72,8 @@
: "$f0" \
);
-#if (__mips==32) && (__mips_isa_rev>=2) && (__mips_fpr==64)
+#if (__mips==32) && (__mips_isa_rev>=2) && \
+ ((__mips_fpr==64) || (__mips_fpr==xx))
void set_rounding_mode(round_mode_t mode)
{
switch(mode) {
@@ -190,7 +191,8 @@
int main()
{
-#if (__mips==32) && (__mips_isa_rev>=2) && (__mips_fpr==64)
+#if (__mips==32) && (__mips_isa_rev>=2) && \
+ ((__mips_fpr==64) || (__mips_fpr==xx))
flt_round_op_t op;
signal(SIGILL, handler);
/* Test fpu64 mode. */
diff --git a/none/tests/mips64/Makefile.am b/none/tests/mips64/Makefile.am
index 3c603a0..ed72ca4 100644
--- a/none/tests/mips64/Makefile.am
+++ b/none/tests/mips64/Makefile.am
@@ -18,9 +18,10 @@
cvm_lx_ins.stdout.exp-LE cvm_lx_ins.stdout.exp-BE \
cvm_lx_ins.stdout.exp-non-octeon \
cvm_lx_ins.stderr.exp cvm_lx_ins.vgtest \
- cvm_atomic.stdout.exp-LE cvm_atomic.stdout.exp-non-octeon \
+ cvm_atomic.stdout.exp-LE cvm_atomic.stdout.exp-BE \
+ cvm_atomic.stdout.exp-non-octeon \
cvm_atomic.stderr.exp cvm_atomic.vgtest \
- cvm_atomic_thread.stdout.exp-LE cvm_atomic_thread.stdout.exp-non-octeon \
+ cvm_atomic_thread.stdout.exp cvm_atomic_thread.stdout.exp-non-octeon \
cvm_atomic_thread.stderr.exp cvm_atomic_thread.vgtest \
extract_insert_bit_field.stdout.exp-mips64 \
extract_insert_bit_field.stdout.exp-mips64r2 \
@@ -54,7 +55,8 @@
test_block_size.vgtest \
test_fcsr.stdout.exp test_fcsr.stderr.exp \
test_fcsr.vgtest \
- test_math.stdout.exp test_math.stderr.exp test_math.vgtest \
+ test_math.stdout.exp test_math.stdout.exp-older-gcc \
+ test_math.stderr.exp test_math.vgtest \
unaligned_load.stdout.exp-BE unaligned_load.stdout.exp-LE \
unaligned_load.stderr.exp unaligned_load.vgtest \
unaligned_load_store.stdout.exp-LE unaligned_load_store.stdout.exp-BE \
diff --git a/none/tests/mips64/Makefile.in b/none/tests/mips64/Makefile.in
index 66e6b0f..b09d7ed 100644
--- a/none/tests/mips64/Makefile.in
+++ b/none/tests/mips64/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -389,6 +389,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -559,6 +560,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -569,6 +571,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -643,8 +646,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -689,7 +690,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
@@ -727,9 +727,10 @@
cvm_lx_ins.stdout.exp-LE cvm_lx_ins.stdout.exp-BE \
cvm_lx_ins.stdout.exp-non-octeon \
cvm_lx_ins.stderr.exp cvm_lx_ins.vgtest \
- cvm_atomic.stdout.exp-LE cvm_atomic.stdout.exp-non-octeon \
+ cvm_atomic.stdout.exp-LE cvm_atomic.stdout.exp-BE \
+ cvm_atomic.stdout.exp-non-octeon \
cvm_atomic.stderr.exp cvm_atomic.vgtest \
- cvm_atomic_thread.stdout.exp-LE cvm_atomic_thread.stdout.exp-non-octeon \
+ cvm_atomic_thread.stdout.exp cvm_atomic_thread.stdout.exp-non-octeon \
cvm_atomic_thread.stderr.exp cvm_atomic_thread.vgtest \
extract_insert_bit_field.stdout.exp-mips64 \
extract_insert_bit_field.stdout.exp-mips64r2 \
@@ -763,7 +764,8 @@
test_block_size.vgtest \
test_fcsr.stdout.exp test_fcsr.stderr.exp \
test_fcsr.vgtest \
- test_math.stdout.exp test_math.stderr.exp test_math.vgtest \
+ test_math.stdout.exp test_math.stdout.exp-older-gcc \
+ test_math.stderr.exp test_math.vgtest \
unaligned_load.stdout.exp-BE unaligned_load.stdout.exp-LE \
unaligned_load.stderr.exp unaligned_load.vgtest \
unaligned_load_store.stdout.exp-LE unaligned_load_store.stdout.exp-BE \
diff --git a/none/tests/mips64/cvm_atomic.stdout.exp-BE b/none/tests/mips64/cvm_atomic.stdout.exp-BE
new file mode 100644
index 0000000..05bc539
--- /dev/null
+++ b/none/tests/mips64/cvm_atomic.stdout.exp-BE
@@ -0,0 +1,4721 @@
+baddu $t3, $t1, $t2 :: rd 0x4, rs 0x42b0c0a28677b502, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xa2, rs 0x42b0c0a28677b502, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x82, rs 0x42b0c0a28677b502, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0x42b0c0a28677b502, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0x42b0c0a28677b502, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x68, rs 0x42b0c0a28677b502, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x38, rs 0x42b0c0a28677b502, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xa9, rs 0x42b0c0a28677b502, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x16, rs 0x42b0c0a28677b502, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0x42b0c0a28677b502, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x5c, rs 0x42b0c0a28677b502, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0x42b0c0a28677b502, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xad, rs 0x42b0c0a28677b502, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x51, rs 0x42b0c0a28677b502, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x3c, rs 0x42b0c0a28677b502, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xaf, rs 0x42b0c0a28677b502, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x9d, rs 0x42b0c0a28677b502, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0x42b0c0a28677b502, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xc2, rs 0x42b0c0a28677b502, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x46, rs 0x42b0c0a28677b502, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0x42b0c0a28677b502, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x91, rs 0x42b0c0a28677b502, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0x42b0c0a28677b502, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x27, rs 0x42b0c0a28677b502, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0xe5, rs 0x42b0c0a28677b502, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xf, rs 0x42b0c0a28677b502, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x89, rs 0x42b0c0a28677b502, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x7b, rs 0x42b0c0a28677b502, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x35, rs 0x42b0c0a28677b502, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0xdc, rs 0x42b0c0a28677b502, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xa4, rs 0x42b0c0a28677b502, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0x42b0c0a28677b502, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xc, rs 0x42b0c0a28677b502, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0x42b0c0a28677b502, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0x42b0c0a28677b502, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x38, rs 0x42b0c0a28677b502, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0x42b0c0a28677b502, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0xf4, rs 0x42b0c0a28677b502, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x6d, rs 0x42b0c0a28677b502, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x63, rs 0x42b0c0a28677b502, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x3f, rs 0x42b0c0a28677b502, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x28, rs 0x42b0c0a28677b502, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x6d, rs 0x42b0c0a28677b502, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0x42b0c0a28677b502, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x4c, rs 0x42b0c0a28677b502, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0x42b0c0a28677b502, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0x42b0c0a28677b502, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x51, rs 0x42b0c0a28677b502, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x9f, rs 0x42b0c0a28677b502, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xcb, rs 0x42b0c0a28677b502, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x65, rs 0x42b0c0a28677b502, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0x42b0c0a28677b502, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0xf5, rs 0x42b0c0a28677b502, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0xdf, rs 0x42b0c0a28677b502, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0x42b0c0a28677b502, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x81, rs 0x42b0c0a28677b502, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xb4, rs 0x42b0c0a28677b502, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x59, rs 0x42b0c0a28677b502, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0x42b0c0a28677b502, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x8b, rs 0x42b0c0a28677b502, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x54, rs 0x42b0c0a28677b502, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0x42b0c0a28677b502, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x68, rs 0x42b0c0a28677b502, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xa2, rs 0x9e705cc51ad8dca0, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x40, rs 0x9e705cc51ad8dca0, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x20, rs 0x9e705cc51ad8dca0, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x37, rs 0x9e705cc51ad8dca0, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x65, rs 0x9e705cc51ad8dca0, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x6, rs 0x9e705cc51ad8dca0, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xd6, rs 0x9e705cc51ad8dca0, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0x9e705cc51ad8dca0, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0xb4, rs 0x9e705cc51ad8dca0, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xe0, rs 0x9e705cc51ad8dca0, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xfa, rs 0x9e705cc51ad8dca0, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x58, rs 0x9e705cc51ad8dca0, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x4b, rs 0x9e705cc51ad8dca0, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xef, rs 0x9e705cc51ad8dca0, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xda, rs 0x9e705cc51ad8dca0, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0x9e705cc51ad8dca0, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x3b, rs 0x9e705cc51ad8dca0, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xf0, rs 0x9e705cc51ad8dca0, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x60, rs 0x9e705cc51ad8dca0, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xe4, rs 0x9e705cc51ad8dca0, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0x9e705cc51ad8dca0, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x2f, rs 0x9e705cc51ad8dca0, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x77, rs 0x9e705cc51ad8dca0, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xc5, rs 0x9e705cc51ad8dca0, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x83, rs 0x9e705cc51ad8dca0, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xad, rs 0x9e705cc51ad8dca0, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x27, rs 0x9e705cc51ad8dca0, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x19, rs 0x9e705cc51ad8dca0, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xd3, rs 0x9e705cc51ad8dca0, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x7a, rs 0x9e705cc51ad8dca0, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0x9e705cc51ad8dca0, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0x9e705cc51ad8dca0, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xaa, rs 0x9e705cc51ad8dca0, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0x9e705cc51ad8dca0, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x2a, rs 0x9e705cc51ad8dca0, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xd6, rs 0x9e705cc51ad8dca0, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x31, rs 0x9e705cc51ad8dca0, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x92, rs 0x9e705cc51ad8dca0, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xb, rs 0x9e705cc51ad8dca0, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x1, rs 0x9e705cc51ad8dca0, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xdd, rs 0x9e705cc51ad8dca0, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xc6, rs 0x9e705cc51ad8dca0, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xb, rs 0x9e705cc51ad8dca0, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0x9e705cc51ad8dca0, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0x9e705cc51ad8dca0, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xe, rs 0x9e705cc51ad8dca0, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x95, rs 0x9e705cc51ad8dca0, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xef, rs 0x9e705cc51ad8dca0, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x3d, rs 0x9e705cc51ad8dca0, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x69, rs 0x9e705cc51ad8dca0, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x3, rs 0x9e705cc51ad8dca0, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x95, rs 0x9e705cc51ad8dca0, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0x9e705cc51ad8dca0, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x7d, rs 0x9e705cc51ad8dca0, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0x9e705cc51ad8dca0, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x1f, rs 0x9e705cc51ad8dca0, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0x9e705cc51ad8dca0, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0x9e705cc51ad8dca0, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xfb, rs 0x9e705cc51ad8dca0, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0x9e705cc51ad8dca0, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0x9e705cc51ad8dca0, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0x9e705cc51ad8dca0, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x6, rs 0x9e705cc51ad8dca0, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x82, rs 0x47f505569a08a180, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x20, rs 0x47f505569a08a180, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x0, rs 0x47f505569a08a180, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x17, rs 0x47f505569a08a180, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x45, rs 0x47f505569a08a180, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xe6, rs 0x47f505569a08a180, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0x47f505569a08a180, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x27, rs 0x47f505569a08a180, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x94, rs 0x47f505569a08a180, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xc0, rs 0x47f505569a08a180, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xda, rs 0x47f505569a08a180, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x38, rs 0x47f505569a08a180, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0x47f505569a08a180, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0x47f505569a08a180, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0x47f505569a08a180, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x2d, rs 0x47f505569a08a180, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x1b, rs 0x47f505569a08a180, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xd0, rs 0x47f505569a08a180, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x40, rs 0x47f505569a08a180, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xc4, rs 0x47f505569a08a180, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xa7, rs 0x47f505569a08a180, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xf, rs 0x47f505569a08a180, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x57, rs 0x47f505569a08a180, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xa5, rs 0x47f505569a08a180, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x63, rs 0x47f505569a08a180, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0x47f505569a08a180, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x7, rs 0x47f505569a08a180, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xf9, rs 0x47f505569a08a180, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xb3, rs 0x47f505569a08a180, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x5a, rs 0x47f505569a08a180, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x22, rs 0x47f505569a08a180, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xcb, rs 0x47f505569a08a180, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x8a, rs 0x47f505569a08a180, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0x47f505569a08a180, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xa, rs 0x47f505569a08a180, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0x47f505569a08a180, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x11, rs 0x47f505569a08a180, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x72, rs 0x47f505569a08a180, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0x47f505569a08a180, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x47f505569a08a180, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0x47f505569a08a180, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xa6, rs 0x47f505569a08a180, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0x47f505569a08a180, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0x47f505569a08a180, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xca, rs 0x47f505569a08a180, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0x47f505569a08a180, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0x47f505569a08a180, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0x47f505569a08a180, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x1d, rs 0x47f505569a08a180, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x49, rs 0x47f505569a08a180, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xe3, rs 0x47f505569a08a180, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0x47f505569a08a180, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x73, rs 0x47f505569a08a180, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0x47f505569a08a180, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xa7, rs 0x47f505569a08a180, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xff, rs 0x47f505569a08a180, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x32, rs 0x47f505569a08a180, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xd7, rs 0x47f505569a08a180, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xdb, rs 0x47f505569a08a180, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x9, rs 0x47f505569a08a180, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xd2, rs 0x47f505569a08a180, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0x47f505569a08a180, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xe6, rs 0x47f505569a08a180, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0x94ff52fc81afa797, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x37, rs 0x94ff52fc81afa797, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x17, rs 0x94ff52fc81afa797, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x2e, rs 0x94ff52fc81afa797, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x5c, rs 0x94ff52fc81afa797, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xfd, rs 0x94ff52fc81afa797, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xcd, rs 0x94ff52fc81afa797, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x3e, rs 0x94ff52fc81afa797, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0xab, rs 0x94ff52fc81afa797, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xd7, rs 0x94ff52fc81afa797, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xf1, rs 0x94ff52fc81afa797, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x4f, rs 0x94ff52fc81afa797, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0x94ff52fc81afa797, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xe6, rs 0x94ff52fc81afa797, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0x94ff52fc81afa797, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x44, rs 0x94ff52fc81afa797, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x32, rs 0x94ff52fc81afa797, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xe7, rs 0x94ff52fc81afa797, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x57, rs 0x94ff52fc81afa797, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xdb, rs 0x94ff52fc81afa797, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xbe, rs 0x94ff52fc81afa797, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0x94ff52fc81afa797, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x6e, rs 0x94ff52fc81afa797, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xbc, rs 0x94ff52fc81afa797, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x7a, rs 0x94ff52fc81afa797, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xa4, rs 0x94ff52fc81afa797, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x1e, rs 0x94ff52fc81afa797, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x10, rs 0x94ff52fc81afa797, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xca, rs 0x94ff52fc81afa797, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x71, rs 0x94ff52fc81afa797, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x39, rs 0x94ff52fc81afa797, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xe2, rs 0x94ff52fc81afa797, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xa1, rs 0x94ff52fc81afa797, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x83, rs 0x94ff52fc81afa797, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x21, rs 0x94ff52fc81afa797, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xcd, rs 0x94ff52fc81afa797, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x28, rs 0x94ff52fc81afa797, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x89, rs 0x94ff52fc81afa797, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0x94ff52fc81afa797, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xf8, rs 0x94ff52fc81afa797, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xd4, rs 0x94ff52fc81afa797, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0x94ff52fc81afa797, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0x94ff52fc81afa797, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x83, rs 0x94ff52fc81afa797, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x94ff52fc81afa797, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x5, rs 0x94ff52fc81afa797, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0x94ff52fc81afa797, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xe6, rs 0x94ff52fc81afa797, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x34, rs 0x94ff52fc81afa797, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x60, rs 0x94ff52fc81afa797, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xfa, rs 0x94ff52fc81afa797, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0x94ff52fc81afa797, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x8a, rs 0x94ff52fc81afa797, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x74, rs 0x94ff52fc81afa797, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xbe, rs 0x94ff52fc81afa797, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x16, rs 0x94ff52fc81afa797, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x49, rs 0x94ff52fc81afa797, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0x94ff52fc81afa797, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0x94ff52fc81afa797, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x20, rs 0x94ff52fc81afa797, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xe9, rs 0x94ff52fc81afa797, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x83, rs 0x94ff52fc81afa797, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xfd, rs 0x94ff52fc81afa797, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0x556b3ecaccf17ac5, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x65, rs 0x556b3ecaccf17ac5, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x45, rs 0x556b3ecaccf17ac5, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x5c, rs 0x556b3ecaccf17ac5, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x8a, rs 0x556b3ecaccf17ac5, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0x556b3ecaccf17ac5, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xfb, rs 0x556b3ecaccf17ac5, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0x556b3ecaccf17ac5, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0x556b3ecaccf17ac5, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x5, rs 0x556b3ecaccf17ac5, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x1f, rs 0x556b3ecaccf17ac5, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x7d, rs 0x556b3ecaccf17ac5, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0x556b3ecaccf17ac5, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x14, rs 0x556b3ecaccf17ac5, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xff, rs 0x556b3ecaccf17ac5, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x72, rs 0x556b3ecaccf17ac5, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x60, rs 0x556b3ecaccf17ac5, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x15, rs 0x556b3ecaccf17ac5, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x85, rs 0x556b3ecaccf17ac5, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x9, rs 0x556b3ecaccf17ac5, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xec, rs 0x556b3ecaccf17ac5, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x54, rs 0x556b3ecaccf17ac5, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0x556b3ecaccf17ac5, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0x556b3ecaccf17ac5, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0xa8, rs 0x556b3ecaccf17ac5, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xd2, rs 0x556b3ecaccf17ac5, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x4c, rs 0x556b3ecaccf17ac5, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x3e, rs 0x556b3ecaccf17ac5, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xf8, rs 0x556b3ecaccf17ac5, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x9f, rs 0x556b3ecaccf17ac5, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x67, rs 0x556b3ecaccf17ac5, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x10, rs 0x556b3ecaccf17ac5, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0x556b3ecaccf17ac5, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0x556b3ecaccf17ac5, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x4f, rs 0x556b3ecaccf17ac5, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xfb, rs 0x556b3ecaccf17ac5, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x56, rs 0x556b3ecaccf17ac5, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0xb7, rs 0x556b3ecaccf17ac5, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x30, rs 0x556b3ecaccf17ac5, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0x556b3ecaccf17ac5, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0x556b3ecaccf17ac5, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0x556b3ecaccf17ac5, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x30, rs 0x556b3ecaccf17ac5, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0x556b3ecaccf17ac5, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xf, rs 0x556b3ecaccf17ac5, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x33, rs 0x556b3ecaccf17ac5, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0x556b3ecaccf17ac5, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x14, rs 0x556b3ecaccf17ac5, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x62, rs 0x556b3ecaccf17ac5, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x8e, rs 0x556b3ecaccf17ac5, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x28, rs 0x556b3ecaccf17ac5, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0x556b3ecaccf17ac5, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0xb8, rs 0x556b3ecaccf17ac5, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0xa2, rs 0x556b3ecaccf17ac5, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xec, rs 0x556b3ecaccf17ac5, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x44, rs 0x556b3ecaccf17ac5, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x77, rs 0x556b3ecaccf17ac5, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x1c, rs 0x556b3ecaccf17ac5, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x20, rs 0x556b3ecaccf17ac5, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x4e, rs 0x556b3ecaccf17ac5, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x17, rs 0x556b3ecaccf17ac5, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0x556b3ecaccf17ac5, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0x556b3ecaccf17ac5, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x68, rs 0x3c2cd9a9cda20766, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x6, rs 0x3c2cd9a9cda20766, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xe6, rs 0x3c2cd9a9cda20766, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xfd, rs 0x3c2cd9a9cda20766, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0x3c2cd9a9cda20766, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xcc, rs 0x3c2cd9a9cda20766, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0x3c2cd9a9cda20766, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xd, rs 0x3c2cd9a9cda20766, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x7a, rs 0x3c2cd9a9cda20766, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xa6, rs 0x3c2cd9a9cda20766, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xc0, rs 0x3c2cd9a9cda20766, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x1e, rs 0x3c2cd9a9cda20766, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x11, rs 0x3c2cd9a9cda20766, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0x3c2cd9a9cda20766, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xa0, rs 0x3c2cd9a9cda20766, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0x3c2cd9a9cda20766, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x1, rs 0x3c2cd9a9cda20766, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0x3c2cd9a9cda20766, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0x3c2cd9a9cda20766, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xaa, rs 0x3c2cd9a9cda20766, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0x3c2cd9a9cda20766, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xf5, rs 0x3c2cd9a9cda20766, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x3d, rs 0x3c2cd9a9cda20766, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x8b, rs 0x3c2cd9a9cda20766, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x49, rs 0x3c2cd9a9cda20766, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x73, rs 0x3c2cd9a9cda20766, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xed, rs 0x3c2cd9a9cda20766, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xdf, rs 0x3c2cd9a9cda20766, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0x3c2cd9a9cda20766, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x40, rs 0x3c2cd9a9cda20766, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x8, rs 0x3c2cd9a9cda20766, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0x3c2cd9a9cda20766, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0x3c2cd9a9cda20766, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0x3c2cd9a9cda20766, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xf0, rs 0x3c2cd9a9cda20766, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0x3c2cd9a9cda20766, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0x3c2cd9a9cda20766, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x58, rs 0x3c2cd9a9cda20766, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0x3c2cd9a9cda20766, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0x3c2cd9a9cda20766, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xa3, rs 0x3c2cd9a9cda20766, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0x3c2cd9a9cda20766, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0x3c2cd9a9cda20766, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0x3c2cd9a9cda20766, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xb0, rs 0x3c2cd9a9cda20766, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xd4, rs 0x3c2cd9a9cda20766, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x5b, rs 0x3c2cd9a9cda20766, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0x3c2cd9a9cda20766, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x3, rs 0x3c2cd9a9cda20766, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x2f, rs 0x3c2cd9a9cda20766, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0x3c2cd9a9cda20766, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x5b, rs 0x3c2cd9a9cda20766, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x59, rs 0x3c2cd9a9cda20766, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x43, rs 0x3c2cd9a9cda20766, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0x3c2cd9a9cda20766, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xe5, rs 0x3c2cd9a9cda20766, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x18, rs 0x3c2cd9a9cda20766, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0x3c2cd9a9cda20766, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xc1, rs 0x3c2cd9a9cda20766, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xef, rs 0x3c2cd9a9cda20766, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xb8, rs 0x3c2cd9a9cda20766, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0x3c2cd9a9cda20766, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xcc, rs 0x3c2cd9a9cda20766, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x38, rs 0xd0d070db710cd036, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xd6, rs 0xd0d070db710cd036, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0xd0d070db710cd036, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xcd, rs 0xd0d070db710cd036, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xfb, rs 0xd0d070db710cd036, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0xd0d070db710cd036, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0xd0d070db710cd036, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xdd, rs 0xd0d070db710cd036, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x4a, rs 0xd0d070db710cd036, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x76, rs 0xd0d070db710cd036, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x90, rs 0xd0d070db710cd036, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0xd0d070db710cd036, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0xd0d070db710cd036, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x85, rs 0xd0d070db710cd036, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0xd0d070db710cd036, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xe3, rs 0xd0d070db710cd036, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0xd0d070db710cd036, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x86, rs 0xd0d070db710cd036, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xf6, rs 0xd0d070db710cd036, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x7a, rs 0xd0d070db710cd036, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0xd0d070db710cd036, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xc5, rs 0xd0d070db710cd036, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xd, rs 0xd0d070db710cd036, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x5b, rs 0xd0d070db710cd036, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x19, rs 0xd0d070db710cd036, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x43, rs 0xd0d070db710cd036, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0xd0d070db710cd036, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xaf, rs 0xd0d070db710cd036, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x69, rs 0xd0d070db710cd036, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x10, rs 0xd0d070db710cd036, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0xd0d070db710cd036, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x81, rs 0xd0d070db710cd036, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x40, rs 0xd0d070db710cd036, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x22, rs 0xd0d070db710cd036, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xc0, rs 0xd0d070db710cd036, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0xd0d070db710cd036, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0xd0d070db710cd036, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x28, rs 0xd0d070db710cd036, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xa1, rs 0xd0d070db710cd036, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x97, rs 0xd0d070db710cd036, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x73, rs 0xd0d070db710cd036, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x5c, rs 0xd0d070db710cd036, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xa1, rs 0xd0d070db710cd036, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x22, rs 0xd0d070db710cd036, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x80, rs 0xd0d070db710cd036, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xa4, rs 0xd0d070db710cd036, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0xd0d070db710cd036, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x85, rs 0xd0d070db710cd036, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xd3, rs 0xd0d070db710cd036, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xff, rs 0xd0d070db710cd036, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0xd0d070db710cd036, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0xd0d070db710cd036, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0xd0d070db710cd036, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0xd0d070db710cd036, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0xd0d070db710cd036, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0xd0d070db710cd036, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xe8, rs 0xd0d070db710cd036, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0xd0d070db710cd036, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x91, rs 0xd0d070db710cd036, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xbf, rs 0xd0d070db710cd036, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x88, rs 0xd0d070db710cd036, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x22, rs 0xd0d070db710cd036, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0xd0d070db710cd036, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xa9, rs 0x2f39454412d6e4a7, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0x2f39454412d6e4a7, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x27, rs 0x2f39454412d6e4a7, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x3e, rs 0x2f39454412d6e4a7, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0x2f39454412d6e4a7, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xd, rs 0x2f39454412d6e4a7, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xdd, rs 0x2f39454412d6e4a7, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x4e, rs 0x2f39454412d6e4a7, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0xbb, rs 0x2f39454412d6e4a7, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xe7, rs 0x2f39454412d6e4a7, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x1, rs 0x2f39454412d6e4a7, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x5f, rs 0x2f39454412d6e4a7, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0x2f39454412d6e4a7, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xf6, rs 0x2f39454412d6e4a7, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x2f39454412d6e4a7, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x54, rs 0x2f39454412d6e4a7, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0x2f39454412d6e4a7, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0x2f39454412d6e4a7, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x67, rs 0x2f39454412d6e4a7, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0x2f39454412d6e4a7, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xce, rs 0x2f39454412d6e4a7, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x36, rs 0x2f39454412d6e4a7, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x7e, rs 0x2f39454412d6e4a7, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xcc, rs 0x2f39454412d6e4a7, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x8a, rs 0x2f39454412d6e4a7, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xb4, rs 0x2f39454412d6e4a7, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x2e, rs 0x2f39454412d6e4a7, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x20, rs 0x2f39454412d6e4a7, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xda, rs 0x2f39454412d6e4a7, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x81, rs 0x2f39454412d6e4a7, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x49, rs 0x2f39454412d6e4a7, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0x2f39454412d6e4a7, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0x2f39454412d6e4a7, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0x2f39454412d6e4a7, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x31, rs 0x2f39454412d6e4a7, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xdd, rs 0x2f39454412d6e4a7, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x38, rs 0x2f39454412d6e4a7, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0x2f39454412d6e4a7, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x12, rs 0x2f39454412d6e4a7, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x8, rs 0x2f39454412d6e4a7, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xe4, rs 0x2f39454412d6e4a7, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xcd, rs 0x2f39454412d6e4a7, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x12, rs 0x2f39454412d6e4a7, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0x2f39454412d6e4a7, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xf1, rs 0x2f39454412d6e4a7, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x15, rs 0x2f39454412d6e4a7, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0x2f39454412d6e4a7, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xf6, rs 0x2f39454412d6e4a7, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x44, rs 0x2f39454412d6e4a7, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0x2f39454412d6e4a7, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xa, rs 0x2f39454412d6e4a7, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0x2f39454412d6e4a7, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x9a, rs 0x2f39454412d6e4a7, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x84, rs 0x2f39454412d6e4a7, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xce, rs 0x2f39454412d6e4a7, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0x2f39454412d6e4a7, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x59, rs 0x2f39454412d6e4a7, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xfe, rs 0x2f39454412d6e4a7, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0x2f39454412d6e4a7, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x30, rs 0x2f39454412d6e4a7, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xf9, rs 0x2f39454412d6e4a7, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0x2f39454412d6e4a7, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xd, rs 0x2f39454412d6e4a7, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x16, rs 0xed5005cbc8b0a214, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xb4, rs 0xed5005cbc8b0a214, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x94, rs 0xed5005cbc8b0a214, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xab, rs 0xed5005cbc8b0a214, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0xed5005cbc8b0a214, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x7a, rs 0xed5005cbc8b0a214, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x4a, rs 0xed5005cbc8b0a214, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xbb, rs 0xed5005cbc8b0a214, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x28, rs 0xed5005cbc8b0a214, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x54, rs 0xed5005cbc8b0a214, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x6e, rs 0xed5005cbc8b0a214, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xcc, rs 0xed5005cbc8b0a214, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xbf, rs 0xed5005cbc8b0a214, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x63, rs 0xed5005cbc8b0a214, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x4e, rs 0xed5005cbc8b0a214, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xc1, rs 0xed5005cbc8b0a214, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xaf, rs 0xed5005cbc8b0a214, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x64, rs 0xed5005cbc8b0a214, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xd4, rs 0xed5005cbc8b0a214, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x58, rs 0xed5005cbc8b0a214, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x3b, rs 0xed5005cbc8b0a214, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xa3, rs 0xed5005cbc8b0a214, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0xed5005cbc8b0a214, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x39, rs 0xed5005cbc8b0a214, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0xed5005cbc8b0a214, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x21, rs 0xed5005cbc8b0a214, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x9b, rs 0xed5005cbc8b0a214, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0xed5005cbc8b0a214, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0xed5005cbc8b0a214, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0xed5005cbc8b0a214, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0xed5005cbc8b0a214, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x5f, rs 0xed5005cbc8b0a214, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x1e, rs 0xed5005cbc8b0a214, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x0, rs 0xed5005cbc8b0a214, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0xed5005cbc8b0a214, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x4a, rs 0xed5005cbc8b0a214, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xa5, rs 0xed5005cbc8b0a214, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x6, rs 0xed5005cbc8b0a214, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x7f, rs 0xed5005cbc8b0a214, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0xed5005cbc8b0a214, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x51, rs 0xed5005cbc8b0a214, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x3a, rs 0xed5005cbc8b0a214, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x7f, rs 0xed5005cbc8b0a214, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x0, rs 0xed5005cbc8b0a214, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x5e, rs 0xed5005cbc8b0a214, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x82, rs 0xed5005cbc8b0a214, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x9, rs 0xed5005cbc8b0a214, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x63, rs 0xed5005cbc8b0a214, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0xed5005cbc8b0a214, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xdd, rs 0xed5005cbc8b0a214, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x77, rs 0xed5005cbc8b0a214, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x9, rs 0xed5005cbc8b0a214, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x7, rs 0xed5005cbc8b0a214, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0xf1, rs 0xed5005cbc8b0a214, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x3b, rs 0xed5005cbc8b0a214, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0xed5005cbc8b0a214, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xc6, rs 0xed5005cbc8b0a214, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x6b, rs 0xed5005cbc8b0a214, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x6f, rs 0xed5005cbc8b0a214, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x9d, rs 0xed5005cbc8b0a214, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x66, rs 0xed5005cbc8b0a214, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x0, rs 0xed5005cbc8b0a214, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x7a, rs 0xed5005cbc8b0a214, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0x87750a04ad765040, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xe0, rs 0x87750a04ad765040, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xc0, rs 0x87750a04ad765040, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xd7, rs 0x87750a04ad765040, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x5, rs 0x87750a04ad765040, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xa6, rs 0x87750a04ad765040, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x76, rs 0x87750a04ad765040, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xe7, rs 0x87750a04ad765040, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x54, rs 0x87750a04ad765040, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x80, rs 0x87750a04ad765040, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x9a, rs 0x87750a04ad765040, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xf8, rs 0x87750a04ad765040, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0x87750a04ad765040, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x8f, rs 0x87750a04ad765040, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x7a, rs 0x87750a04ad765040, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xed, rs 0x87750a04ad765040, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xdb, rs 0x87750a04ad765040, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x90, rs 0x87750a04ad765040, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x0, rs 0x87750a04ad765040, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x84, rs 0x87750a04ad765040, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x67, rs 0x87750a04ad765040, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0x87750a04ad765040, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x17, rs 0x87750a04ad765040, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x65, rs 0x87750a04ad765040, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x23, rs 0x87750a04ad765040, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0x87750a04ad765040, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0x87750a04ad765040, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xb9, rs 0x87750a04ad765040, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x73, rs 0x87750a04ad765040, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x1a, rs 0x87750a04ad765040, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xe2, rs 0x87750a04ad765040, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x8b, rs 0x87750a04ad765040, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x4a, rs 0x87750a04ad765040, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x2c, rs 0x87750a04ad765040, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xca, rs 0x87750a04ad765040, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x76, rs 0x87750a04ad765040, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0x87750a04ad765040, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x32, rs 0x87750a04ad765040, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xab, rs 0x87750a04ad765040, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xa1, rs 0x87750a04ad765040, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x7d, rs 0x87750a04ad765040, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x66, rs 0x87750a04ad765040, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xab, rs 0x87750a04ad765040, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x2c, rs 0x87750a04ad765040, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x8a, rs 0x87750a04ad765040, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xae, rs 0x87750a04ad765040, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x35, rs 0x87750a04ad765040, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x8f, rs 0x87750a04ad765040, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xdd, rs 0x87750a04ad765040, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x9, rs 0x87750a04ad765040, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xa3, rs 0x87750a04ad765040, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x35, rs 0x87750a04ad765040, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x33, rs 0x87750a04ad765040, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x1d, rs 0x87750a04ad765040, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x67, rs 0x87750a04ad765040, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xbf, rs 0x87750a04ad765040, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0x87750a04ad765040, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x97, rs 0x87750a04ad765040, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x9b, rs 0x87750a04ad765040, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0x87750a04ad765040, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x92, rs 0x87750a04ad765040, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x2c, rs 0x87750a04ad765040, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xa6, rs 0x87750a04ad765040, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x5c, rs 0xc4c770f630dcca5a, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xfa, rs 0xc4c770f630dcca5a, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xda, rs 0xc4c770f630dcca5a, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xf1, rs 0xc4c770f630dcca5a, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x1f, rs 0xc4c770f630dcca5a, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xc0, rs 0xc4c770f630dcca5a, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x90, rs 0xc4c770f630dcca5a, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x1, rs 0xc4c770f630dcca5a, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x6e, rs 0xc4c770f630dcca5a, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x9a, rs 0xc4c770f630dcca5a, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xb4, rs 0xc4c770f630dcca5a, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x12, rs 0xc4c770f630dcca5a, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x5, rs 0xc4c770f630dcca5a, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xa9, rs 0xc4c770f630dcca5a, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x94, rs 0xc4c770f630dcca5a, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x7, rs 0xc4c770f630dcca5a, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xf5, rs 0xc4c770f630dcca5a, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xaa, rs 0xc4c770f630dcca5a, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x1a, rs 0xc4c770f630dcca5a, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0xc4c770f630dcca5a, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x81, rs 0xc4c770f630dcca5a, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xe9, rs 0xc4c770f630dcca5a, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x31, rs 0xc4c770f630dcca5a, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x7f, rs 0xc4c770f630dcca5a, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x3d, rs 0xc4c770f630dcca5a, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x67, rs 0xc4c770f630dcca5a, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0xc4c770f630dcca5a, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xd3, rs 0xc4c770f630dcca5a, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0xc4c770f630dcca5a, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x34, rs 0xc4c770f630dcca5a, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xfc, rs 0xc4c770f630dcca5a, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xa5, rs 0xc4c770f630dcca5a, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x64, rs 0xc4c770f630dcca5a, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x46, rs 0xc4c770f630dcca5a, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xe4, rs 0xc4c770f630dcca5a, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x90, rs 0xc4c770f630dcca5a, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0xc4c770f630dcca5a, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x4c, rs 0xc4c770f630dcca5a, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xc5, rs 0xc4c770f630dcca5a, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xbb, rs 0xc4c770f630dcca5a, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x97, rs 0xc4c770f630dcca5a, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x80, rs 0xc4c770f630dcca5a, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xc5, rs 0xc4c770f630dcca5a, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x46, rs 0xc4c770f630dcca5a, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xa4, rs 0xc4c770f630dcca5a, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xc8, rs 0xc4c770f630dcca5a, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x4f, rs 0xc4c770f630dcca5a, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xa9, rs 0xc4c770f630dcca5a, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0xc4c770f630dcca5a, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x23, rs 0xc4c770f630dcca5a, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0xc4c770f630dcca5a, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x4f, rs 0xc4c770f630dcca5a, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0xc4c770f630dcca5a, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x37, rs 0xc4c770f630dcca5a, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x81, rs 0xc4c770f630dcca5a, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0xc4c770f630dcca5a, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xc, rs 0xc4c770f630dcca5a, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0xc4c770f630dcca5a, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0xc4c770f630dcca5a, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xe3, rs 0xc4c770f630dcca5a, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xac, rs 0xc4c770f630dcca5a, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x46, rs 0xc4c770f630dcca5a, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xc0, rs 0xc4c770f630dcca5a, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0xbb8c035e0de0f0b8, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x58, rs 0xbb8c035e0de0f0b8, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x38, rs 0xbb8c035e0de0f0b8, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x4f, rs 0xbb8c035e0de0f0b8, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x7d, rs 0xbb8c035e0de0f0b8, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x1e, rs 0xbb8c035e0de0f0b8, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0xbb8c035e0de0f0b8, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x5f, rs 0xbb8c035e0de0f0b8, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0xcc, rs 0xbb8c035e0de0f0b8, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xf8, rs 0xbb8c035e0de0f0b8, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x12, rs 0xbb8c035e0de0f0b8, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0xbb8c035e0de0f0b8, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x63, rs 0xbb8c035e0de0f0b8, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x7, rs 0xbb8c035e0de0f0b8, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0xbb8c035e0de0f0b8, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x65, rs 0xbb8c035e0de0f0b8, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x53, rs 0xbb8c035e0de0f0b8, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x8, rs 0xbb8c035e0de0f0b8, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x78, rs 0xbb8c035e0de0f0b8, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xfc, rs 0xbb8c035e0de0f0b8, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xdf, rs 0xbb8c035e0de0f0b8, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0xbb8c035e0de0f0b8, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x8f, rs 0xbb8c035e0de0f0b8, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xdd, rs 0xbb8c035e0de0f0b8, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x9b, rs 0xbb8c035e0de0f0b8, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xc5, rs 0xbb8c035e0de0f0b8, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x3f, rs 0xbb8c035e0de0f0b8, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x31, rs 0xbb8c035e0de0f0b8, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0xbb8c035e0de0f0b8, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x92, rs 0xbb8c035e0de0f0b8, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x5a, rs 0xbb8c035e0de0f0b8, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x3, rs 0xbb8c035e0de0f0b8, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xc2, rs 0xbb8c035e0de0f0b8, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0xa4, rs 0xbb8c035e0de0f0b8, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0xbb8c035e0de0f0b8, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0xbb8c035e0de0f0b8, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x49, rs 0xbb8c035e0de0f0b8, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0xaa, rs 0xbb8c035e0de0f0b8, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x23, rs 0xbb8c035e0de0f0b8, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x19, rs 0xbb8c035e0de0f0b8, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xf5, rs 0xbb8c035e0de0f0b8, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xde, rs 0xbb8c035e0de0f0b8, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x23, rs 0xbb8c035e0de0f0b8, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0xa4, rs 0xbb8c035e0de0f0b8, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0xbb8c035e0de0f0b8, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0xbb8c035e0de0f0b8, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0xad, rs 0xbb8c035e0de0f0b8, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x7, rs 0xbb8c035e0de0f0b8, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x55, rs 0xbb8c035e0de0f0b8, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x81, rs 0xbb8c035e0de0f0b8, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x1b, rs 0xbb8c035e0de0f0b8, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0xad, rs 0xbb8c035e0de0f0b8, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0xab, rs 0xbb8c035e0de0f0b8, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x95, rs 0xbb8c035e0de0f0b8, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xdf, rs 0xbb8c035e0de0f0b8, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x37, rs 0xbb8c035e0de0f0b8, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x6a, rs 0xbb8c035e0de0f0b8, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xf, rs 0xbb8c035e0de0f0b8, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0xbb8c035e0de0f0b8, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x41, rs 0xbb8c035e0de0f0b8, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xa, rs 0xbb8c035e0de0f0b8, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0xa4, rs 0xbb8c035e0de0f0b8, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x1e, rs 0xbb8c035e0de0f0b8, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xad, rs 0x49fbf6a795b1a5ab, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x4b, rs 0x49fbf6a795b1a5ab, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0x49fbf6a795b1a5ab, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0x49fbf6a795b1a5ab, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0x49fbf6a795b1a5ab, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x11, rs 0x49fbf6a795b1a5ab, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x49fbf6a795b1a5ab, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0x49fbf6a795b1a5ab, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0xbf, rs 0x49fbf6a795b1a5ab, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0x49fbf6a795b1a5ab, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x5, rs 0x49fbf6a795b1a5ab, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x63, rs 0x49fbf6a795b1a5ab, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x56, rs 0x49fbf6a795b1a5ab, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xfa, rs 0x49fbf6a795b1a5ab, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xe5, rs 0x49fbf6a795b1a5ab, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x58, rs 0x49fbf6a795b1a5ab, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x46, rs 0x49fbf6a795b1a5ab, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xfb, rs 0x49fbf6a795b1a5ab, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x6b, rs 0x49fbf6a795b1a5ab, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xef, rs 0x49fbf6a795b1a5ab, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xd2, rs 0x49fbf6a795b1a5ab, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x3a, rs 0x49fbf6a795b1a5ab, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x82, rs 0x49fbf6a795b1a5ab, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xd0, rs 0x49fbf6a795b1a5ab, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x8e, rs 0x49fbf6a795b1a5ab, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xb8, rs 0x49fbf6a795b1a5ab, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x32, rs 0x49fbf6a795b1a5ab, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x24, rs 0x49fbf6a795b1a5ab, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xde, rs 0x49fbf6a795b1a5ab, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x85, rs 0x49fbf6a795b1a5ab, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0x49fbf6a795b1a5ab, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xf6, rs 0x49fbf6a795b1a5ab, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0x49fbf6a795b1a5ab, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x97, rs 0x49fbf6a795b1a5ab, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x35, rs 0x49fbf6a795b1a5ab, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x49fbf6a795b1a5ab, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x3c, rs 0x49fbf6a795b1a5ab, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x9d, rs 0x49fbf6a795b1a5ab, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x16, rs 0x49fbf6a795b1a5ab, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xc, rs 0x49fbf6a795b1a5ab, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xe8, rs 0x49fbf6a795b1a5ab, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0x49fbf6a795b1a5ab, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x16, rs 0x49fbf6a795b1a5ab, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x97, rs 0x49fbf6a795b1a5ab, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xf5, rs 0x49fbf6a795b1a5ab, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x19, rs 0x49fbf6a795b1a5ab, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0xa0, rs 0x49fbf6a795b1a5ab, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xfa, rs 0x49fbf6a795b1a5ab, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x48, rs 0x49fbf6a795b1a5ab, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x74, rs 0x49fbf6a795b1a5ab, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xe, rs 0x49fbf6a795b1a5ab, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0xa0, rs 0x49fbf6a795b1a5ab, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0x49fbf6a795b1a5ab, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x88, rs 0x49fbf6a795b1a5ab, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xd2, rs 0x49fbf6a795b1a5ab, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x2a, rs 0x49fbf6a795b1a5ab, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0x49fbf6a795b1a5ab, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0x49fbf6a795b1a5ab, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x6, rs 0x49fbf6a795b1a5ab, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x34, rs 0x49fbf6a795b1a5ab, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xfd, rs 0x49fbf6a795b1a5ab, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x97, rs 0x49fbf6a795b1a5ab, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x11, rs 0x49fbf6a795b1a5ab, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x51, rs 0xd685884e76558c4f, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xef, rs 0xd685884e76558c4f, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0xd685884e76558c4f, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xe6, rs 0xd685884e76558c4f, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x14, rs 0xd685884e76558c4f, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0xd685884e76558c4f, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x85, rs 0xd685884e76558c4f, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xf6, rs 0xd685884e76558c4f, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x63, rs 0xd685884e76558c4f, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x8f, rs 0xd685884e76558c4f, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xa9, rs 0xd685884e76558c4f, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x7, rs 0xd685884e76558c4f, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xfa, rs 0xd685884e76558c4f, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0xd685884e76558c4f, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x89, rs 0xd685884e76558c4f, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xfc, rs 0xd685884e76558c4f, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0xd685884e76558c4f, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x9f, rs 0xd685884e76558c4f, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xf, rs 0xd685884e76558c4f, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0xd685884e76558c4f, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x76, rs 0xd685884e76558c4f, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xde, rs 0xd685884e76558c4f, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0xd685884e76558c4f, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x74, rs 0xd685884e76558c4f, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x32, rs 0xd685884e76558c4f, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x5c, rs 0xd685884e76558c4f, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xd6, rs 0xd685884e76558c4f, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xc8, rs 0xd685884e76558c4f, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x82, rs 0xd685884e76558c4f, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0xd685884e76558c4f, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xf1, rs 0xd685884e76558c4f, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x9a, rs 0xd685884e76558c4f, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x59, rs 0xd685884e76558c4f, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x3b, rs 0xd685884e76558c4f, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0xd685884e76558c4f, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x85, rs 0xd685884e76558c4f, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xe0, rs 0xd685884e76558c4f, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x41, rs 0xd685884e76558c4f, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0xd685884e76558c4f, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xb0, rs 0xd685884e76558c4f, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0xd685884e76558c4f, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0xd685884e76558c4f, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0xd685884e76558c4f, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x3b, rs 0xd685884e76558c4f, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0xd685884e76558c4f, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0xd685884e76558c4f, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x44, rs 0xd685884e76558c4f, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0xd685884e76558c4f, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xec, rs 0xd685884e76558c4f, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x18, rs 0xd685884e76558c4f, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xb2, rs 0xd685884e76558c4f, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x44, rs 0xd685884e76558c4f, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0xd685884e76558c4f, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x2c, rs 0xd685884e76558c4f, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x76, rs 0xd685884e76558c4f, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xce, rs 0xd685884e76558c4f, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x1, rs 0xd685884e76558c4f, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xa6, rs 0xd685884e76558c4f, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xaa, rs 0xd685884e76558c4f, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0xd685884e76558c4f, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xa1, rs 0xd685884e76558c4f, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x3b, rs 0xd685884e76558c4f, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0xd685884e76558c4f, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x3c, rs 0x58300f029cae393a, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xda, rs 0x58300f029cae393a, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0x58300f029cae393a, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0x58300f029cae393a, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xff, rs 0x58300f029cae393a, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xa0, rs 0x58300f029cae393a, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0x58300f029cae393a, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x58300f029cae393a, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x4e, rs 0x58300f029cae393a, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x7a, rs 0x58300f029cae393a, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x94, rs 0x58300f029cae393a, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0x58300f029cae393a, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xe5, rs 0x58300f029cae393a, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x89, rs 0x58300f029cae393a, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x74, rs 0x58300f029cae393a, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xe7, rs 0x58300f029cae393a, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xd5, rs 0x58300f029cae393a, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x8a, rs 0x58300f029cae393a, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xfa, rs 0x58300f029cae393a, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x7e, rs 0x58300f029cae393a, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x61, rs 0x58300f029cae393a, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0x58300f029cae393a, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x11, rs 0x58300f029cae393a, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x5f, rs 0x58300f029cae393a, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x1d, rs 0x58300f029cae393a, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0x58300f029cae393a, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xc1, rs 0x58300f029cae393a, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xb3, rs 0x58300f029cae393a, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x6d, rs 0x58300f029cae393a, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x14, rs 0x58300f029cae393a, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xdc, rs 0x58300f029cae393a, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x85, rs 0x58300f029cae393a, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x44, rs 0x58300f029cae393a, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0x58300f029cae393a, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xc4, rs 0x58300f029cae393a, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0x58300f029cae393a, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xcb, rs 0x58300f029cae393a, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x2c, rs 0x58300f029cae393a, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xa5, rs 0x58300f029cae393a, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x9b, rs 0x58300f029cae393a, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x77, rs 0x58300f029cae393a, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x60, rs 0x58300f029cae393a, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xa5, rs 0x58300f029cae393a, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0x58300f029cae393a, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x84, rs 0x58300f029cae393a, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xa8, rs 0x58300f029cae393a, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x2f, rs 0x58300f029cae393a, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x89, rs 0x58300f029cae393a, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xd7, rs 0x58300f029cae393a, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x3, rs 0x58300f029cae393a, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x9d, rs 0x58300f029cae393a, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x2f, rs 0x58300f029cae393a, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x2d, rs 0x58300f029cae393a, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x17, rs 0x58300f029cae393a, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x61, rs 0x58300f029cae393a, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xb9, rs 0x58300f029cae393a, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xec, rs 0x58300f029cae393a, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x91, rs 0x58300f029cae393a, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x95, rs 0x58300f029cae393a, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xc3, rs 0x58300f029cae393a, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0x58300f029cae393a, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0x58300f029cae393a, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xa0, rs 0x58300f029cae393a, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xaf, rs 0xde230867a630f6ad, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0xde230867a630f6ad, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x2d, rs 0xde230867a630f6ad, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x44, rs 0xde230867a630f6ad, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x72, rs 0xde230867a630f6ad, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0xde230867a630f6ad, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xe3, rs 0xde230867a630f6ad, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x54, rs 0xde230867a630f6ad, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0xc1, rs 0xde230867a630f6ad, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xed, rs 0xde230867a630f6ad, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x7, rs 0xde230867a630f6ad, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x65, rs 0xde230867a630f6ad, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x58, rs 0xde230867a630f6ad, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xfc, rs 0xde230867a630f6ad, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xe7, rs 0xde230867a630f6ad, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x5a, rs 0xde230867a630f6ad, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x48, rs 0xde230867a630f6ad, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xfd, rs 0xde230867a630f6ad, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x6d, rs 0xde230867a630f6ad, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xf1, rs 0xde230867a630f6ad, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xd4, rs 0xde230867a630f6ad, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x3c, rs 0xde230867a630f6ad, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x84, rs 0xde230867a630f6ad, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xd2, rs 0xde230867a630f6ad, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x90, rs 0xde230867a630f6ad, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0xde230867a630f6ad, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x34, rs 0xde230867a630f6ad, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0xde230867a630f6ad, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xe0, rs 0xde230867a630f6ad, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x87, rs 0xde230867a630f6ad, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x4f, rs 0xde230867a630f6ad, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xf8, rs 0xde230867a630f6ad, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xb7, rs 0xde230867a630f6ad, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0xde230867a630f6ad, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x37, rs 0xde230867a630f6ad, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xe3, rs 0xde230867a630f6ad, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x3e, rs 0xde230867a630f6ad, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x9f, rs 0xde230867a630f6ad, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x18, rs 0xde230867a630f6ad, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xe, rs 0xde230867a630f6ad, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0xde230867a630f6ad, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xd3, rs 0xde230867a630f6ad, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x18, rs 0xde230867a630f6ad, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0xde230867a630f6ad, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0xde230867a630f6ad, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x1b, rs 0xde230867a630f6ad, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0xa2, rs 0xde230867a630f6ad, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xfc, rs 0xde230867a630f6ad, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x4a, rs 0xde230867a630f6ad, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x76, rs 0xde230867a630f6ad, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x10, rs 0xde230867a630f6ad, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0xa2, rs 0xde230867a630f6ad, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0xa0, rs 0xde230867a630f6ad, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x8a, rs 0xde230867a630f6ad, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xd4, rs 0xde230867a630f6ad, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x2c, rs 0xde230867a630f6ad, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x5f, rs 0xde230867a630f6ad, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x4, rs 0xde230867a630f6ad, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x8, rs 0xde230867a630f6ad, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x36, rs 0xde230867a630f6ad, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xff, rs 0xde230867a630f6ad, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0xde230867a630f6ad, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0xde230867a630f6ad, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x9d, rs 0x81daf8200468319b, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x3b, rs 0x81daf8200468319b, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x1b, rs 0x81daf8200468319b, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x32, rs 0x81daf8200468319b, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x60, rs 0x81daf8200468319b, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x1, rs 0x81daf8200468319b, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0x81daf8200468319b, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0x81daf8200468319b, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0xaf, rs 0x81daf8200468319b, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xdb, rs 0x81daf8200468319b, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xf5, rs 0x81daf8200468319b, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x53, rs 0x81daf8200468319b, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x46, rs 0x81daf8200468319b, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0x81daf8200468319b, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xd5, rs 0x81daf8200468319b, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x48, rs 0x81daf8200468319b, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x36, rs 0x81daf8200468319b, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0x81daf8200468319b, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x5b, rs 0x81daf8200468319b, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xdf, rs 0x81daf8200468319b, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xc2, rs 0x81daf8200468319b, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x2a, rs 0x81daf8200468319b, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x72, rs 0x81daf8200468319b, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xc0, rs 0x81daf8200468319b, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x7e, rs 0x81daf8200468319b, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xa8, rs 0x81daf8200468319b, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x22, rs 0x81daf8200468319b, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x14, rs 0x81daf8200468319b, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xce, rs 0x81daf8200468319b, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0x81daf8200468319b, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x3d, rs 0x81daf8200468319b, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xe6, rs 0x81daf8200468319b, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xa5, rs 0x81daf8200468319b, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x87, rs 0x81daf8200468319b, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x25, rs 0x81daf8200468319b, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0x81daf8200468319b, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x2c, rs 0x81daf8200468319b, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0x81daf8200468319b, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x6, rs 0x81daf8200468319b, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xfc, rs 0x81daf8200468319b, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0x81daf8200468319b, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xc1, rs 0x81daf8200468319b, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x6, rs 0x81daf8200468319b, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x87, rs 0x81daf8200468319b, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xe5, rs 0x81daf8200468319b, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x9, rs 0x81daf8200468319b, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x90, rs 0x81daf8200468319b, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0x81daf8200468319b, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x38, rs 0x81daf8200468319b, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x64, rs 0x81daf8200468319b, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xfe, rs 0x81daf8200468319b, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x90, rs 0x81daf8200468319b, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x8e, rs 0x81daf8200468319b, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x78, rs 0x81daf8200468319b, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xc2, rs 0x81daf8200468319b, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x1a, rs 0x81daf8200468319b, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0x81daf8200468319b, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0x81daf8200468319b, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xf6, rs 0x81daf8200468319b, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x24, rs 0x81daf8200468319b, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xed, rs 0x81daf8200468319b, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x87, rs 0x81daf8200468319b, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x1, rs 0x81daf8200468319b, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0x6778fdf3ba52a850, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xf0, rs 0x6778fdf3ba52a850, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xd0, rs 0x6778fdf3ba52a850, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xe7, rs 0x6778fdf3ba52a850, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x15, rs 0x6778fdf3ba52a850, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0x6778fdf3ba52a850, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x86, rs 0x6778fdf3ba52a850, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0x6778fdf3ba52a850, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x64, rs 0x6778fdf3ba52a850, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x90, rs 0x6778fdf3ba52a850, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xaa, rs 0x6778fdf3ba52a850, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x8, rs 0x6778fdf3ba52a850, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xfb, rs 0x6778fdf3ba52a850, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x9f, rs 0x6778fdf3ba52a850, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x8a, rs 0x6778fdf3ba52a850, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xfd, rs 0x6778fdf3ba52a850, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0x6778fdf3ba52a850, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xa0, rs 0x6778fdf3ba52a850, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x10, rs 0x6778fdf3ba52a850, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x94, rs 0x6778fdf3ba52a850, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x77, rs 0x6778fdf3ba52a850, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xdf, rs 0x6778fdf3ba52a850, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x27, rs 0x6778fdf3ba52a850, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0x6778fdf3ba52a850, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x33, rs 0x6778fdf3ba52a850, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0x6778fdf3ba52a850, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xd7, rs 0x6778fdf3ba52a850, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0x6778fdf3ba52a850, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x83, rs 0x6778fdf3ba52a850, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x2a, rs 0x6778fdf3ba52a850, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0x6778fdf3ba52a850, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x9b, rs 0x6778fdf3ba52a850, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x5a, rs 0x6778fdf3ba52a850, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x3c, rs 0x6778fdf3ba52a850, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xda, rs 0x6778fdf3ba52a850, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x86, rs 0x6778fdf3ba52a850, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x6778fdf3ba52a850, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0x6778fdf3ba52a850, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xbb, rs 0x6778fdf3ba52a850, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0x6778fdf3ba52a850, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0x6778fdf3ba52a850, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x76, rs 0x6778fdf3ba52a850, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xbb, rs 0x6778fdf3ba52a850, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x3c, rs 0x6778fdf3ba52a850, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x9a, rs 0x6778fdf3ba52a850, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xbe, rs 0x6778fdf3ba52a850, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x45, rs 0x6778fdf3ba52a850, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x9f, rs 0x6778fdf3ba52a850, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xed, rs 0x6778fdf3ba52a850, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x19, rs 0x6778fdf3ba52a850, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xb3, rs 0x6778fdf3ba52a850, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x45, rs 0x6778fdf3ba52a850, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x43, rs 0x6778fdf3ba52a850, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x2d, rs 0x6778fdf3ba52a850, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x77, rs 0x6778fdf3ba52a850, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0x6778fdf3ba52a850, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0x6778fdf3ba52a850, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xa7, rs 0x6778fdf3ba52a850, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xab, rs 0x6778fdf3ba52a850, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0x6778fdf3ba52a850, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xa2, rs 0x6778fdf3ba52a850, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x3c, rs 0x6778fdf3ba52a850, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0x6778fdf3ba52a850, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xc2, rs 0xe4627f3fe5255fc0, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x60, rs 0xe4627f3fe5255fc0, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x40, rs 0xe4627f3fe5255fc0, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x57, rs 0xe4627f3fe5255fc0, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x85, rs 0xe4627f3fe5255fc0, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0xe4627f3fe5255fc0, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xf6, rs 0xe4627f3fe5255fc0, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x67, rs 0xe4627f3fe5255fc0, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0xd4, rs 0xe4627f3fe5255fc0, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x0, rs 0xe4627f3fe5255fc0, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x1a, rs 0xe4627f3fe5255fc0, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x78, rs 0xe4627f3fe5255fc0, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x6b, rs 0xe4627f3fe5255fc0, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xf, rs 0xe4627f3fe5255fc0, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xfa, rs 0xe4627f3fe5255fc0, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x6d, rs 0xe4627f3fe5255fc0, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x5b, rs 0xe4627f3fe5255fc0, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x10, rs 0xe4627f3fe5255fc0, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x80, rs 0xe4627f3fe5255fc0, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x4, rs 0xe4627f3fe5255fc0, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xe7, rs 0xe4627f3fe5255fc0, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x4f, rs 0xe4627f3fe5255fc0, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x97, rs 0xe4627f3fe5255fc0, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xe5, rs 0xe4627f3fe5255fc0, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0xa3, rs 0xe4627f3fe5255fc0, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xcd, rs 0xe4627f3fe5255fc0, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0xe4627f3fe5255fc0, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x39, rs 0xe4627f3fe5255fc0, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xf3, rs 0xe4627f3fe5255fc0, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x9a, rs 0xe4627f3fe5255fc0, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x62, rs 0xe4627f3fe5255fc0, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xb, rs 0xe4627f3fe5255fc0, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xca, rs 0xe4627f3fe5255fc0, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0xac, rs 0xe4627f3fe5255fc0, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x4a, rs 0xe4627f3fe5255fc0, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xf6, rs 0xe4627f3fe5255fc0, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x51, rs 0xe4627f3fe5255fc0, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0xb2, rs 0xe4627f3fe5255fc0, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0xe4627f3fe5255fc0, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x21, rs 0xe4627f3fe5255fc0, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xfd, rs 0xe4627f3fe5255fc0, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xe6, rs 0xe4627f3fe5255fc0, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0xe4627f3fe5255fc0, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0xac, rs 0xe4627f3fe5255fc0, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xa, rs 0xe4627f3fe5255fc0, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x2e, rs 0xe4627f3fe5255fc0, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0xe4627f3fe5255fc0, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xf, rs 0xe4627f3fe5255fc0, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0xe4627f3fe5255fc0, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x89, rs 0xe4627f3fe5255fc0, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x23, rs 0xe4627f3fe5255fc0, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0xe4627f3fe5255fc0, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0xb3, rs 0xe4627f3fe5255fc0, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x9d, rs 0xe4627f3fe5255fc0, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xe7, rs 0xe4627f3fe5255fc0, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x3f, rs 0xe4627f3fe5255fc0, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x72, rs 0xe4627f3fe5255fc0, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x17, rs 0xe4627f3fe5255fc0, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x1b, rs 0xe4627f3fe5255fc0, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x49, rs 0xe4627f3fe5255fc0, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x12, rs 0xe4627f3fe5255fc0, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0xac, rs 0xe4627f3fe5255fc0, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0xe4627f3fe5255fc0, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x46, rs 0x7caf83d2880ff344, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xe4, rs 0x7caf83d2880ff344, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xc4, rs 0x7caf83d2880ff344, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xdb, rs 0x7caf83d2880ff344, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x9, rs 0x7caf83d2880ff344, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xaa, rs 0x7caf83d2880ff344, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x7a, rs 0x7caf83d2880ff344, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0x7caf83d2880ff344, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x58, rs 0x7caf83d2880ff344, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x84, rs 0x7caf83d2880ff344, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0x7caf83d2880ff344, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xfc, rs 0x7caf83d2880ff344, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xef, rs 0x7caf83d2880ff344, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0x7caf83d2880ff344, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x7e, rs 0x7caf83d2880ff344, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xf1, rs 0x7caf83d2880ff344, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xdf, rs 0x7caf83d2880ff344, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x94, rs 0x7caf83d2880ff344, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x4, rs 0x7caf83d2880ff344, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x88, rs 0x7caf83d2880ff344, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x6b, rs 0x7caf83d2880ff344, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xd3, rs 0x7caf83d2880ff344, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x1b, rs 0x7caf83d2880ff344, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x69, rs 0x7caf83d2880ff344, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x27, rs 0x7caf83d2880ff344, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x51, rs 0x7caf83d2880ff344, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xcb, rs 0x7caf83d2880ff344, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0x7caf83d2880ff344, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x77, rs 0x7caf83d2880ff344, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x1e, rs 0x7caf83d2880ff344, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xe6, rs 0x7caf83d2880ff344, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x8f, rs 0x7caf83d2880ff344, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x4e, rs 0x7caf83d2880ff344, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x30, rs 0x7caf83d2880ff344, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xce, rs 0x7caf83d2880ff344, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x7a, rs 0x7caf83d2880ff344, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xd5, rs 0x7caf83d2880ff344, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x36, rs 0x7caf83d2880ff344, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xaf, rs 0x7caf83d2880ff344, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xa5, rs 0x7caf83d2880ff344, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x81, rs 0x7caf83d2880ff344, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x6a, rs 0x7caf83d2880ff344, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xaf, rs 0x7caf83d2880ff344, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x30, rs 0x7caf83d2880ff344, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x8e, rs 0x7caf83d2880ff344, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xb2, rs 0x7caf83d2880ff344, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x39, rs 0x7caf83d2880ff344, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0x7caf83d2880ff344, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x7caf83d2880ff344, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xd, rs 0x7caf83d2880ff344, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xa7, rs 0x7caf83d2880ff344, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x39, rs 0x7caf83d2880ff344, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x37, rs 0x7caf83d2880ff344, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x21, rs 0x7caf83d2880ff344, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x6b, rs 0x7caf83d2880ff344, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xc3, rs 0x7caf83d2880ff344, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xf6, rs 0x7caf83d2880ff344, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x9b, rs 0x7caf83d2880ff344, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x9f, rs 0x7caf83d2880ff344, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xcd, rs 0x7caf83d2880ff344, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x96, rs 0x7caf83d2880ff344, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x30, rs 0x7caf83d2880ff344, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xaa, rs 0x7caf83d2880ff344, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0x24296b75a76fa427, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0x24296b75a76fa427, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xa7, rs 0x24296b75a76fa427, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xbe, rs 0x24296b75a76fa427, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xec, rs 0x24296b75a76fa427, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0x24296b75a76fa427, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0x24296b75a76fa427, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xce, rs 0x24296b75a76fa427, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x3b, rs 0x24296b75a76fa427, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x67, rs 0x24296b75a76fa427, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x81, rs 0x24296b75a76fa427, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xdf, rs 0x24296b75a76fa427, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xd2, rs 0x24296b75a76fa427, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x76, rs 0x24296b75a76fa427, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x61, rs 0x24296b75a76fa427, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xd4, rs 0x24296b75a76fa427, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xc2, rs 0x24296b75a76fa427, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x77, rs 0x24296b75a76fa427, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xe7, rs 0x24296b75a76fa427, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x6b, rs 0x24296b75a76fa427, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x4e, rs 0x24296b75a76fa427, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0x24296b75a76fa427, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xfe, rs 0x24296b75a76fa427, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x4c, rs 0x24296b75a76fa427, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0xa, rs 0x24296b75a76fa427, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x34, rs 0x24296b75a76fa427, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xae, rs 0x24296b75a76fa427, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xa0, rs 0x24296b75a76fa427, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x5a, rs 0x24296b75a76fa427, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x1, rs 0x24296b75a76fa427, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0x24296b75a76fa427, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x72, rs 0x24296b75a76fa427, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x31, rs 0x24296b75a76fa427, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0x24296b75a76fa427, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0x24296b75a76fa427, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0x24296b75a76fa427, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xb8, rs 0x24296b75a76fa427, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x19, rs 0x24296b75a76fa427, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x92, rs 0x24296b75a76fa427, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x88, rs 0x24296b75a76fa427, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x64, rs 0x24296b75a76fa427, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0x24296b75a76fa427, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x92, rs 0x24296b75a76fa427, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0x24296b75a76fa427, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x71, rs 0x24296b75a76fa427, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x95, rs 0x24296b75a76fa427, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x1c, rs 0x24296b75a76fa427, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x76, rs 0x24296b75a76fa427, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xc4, rs 0x24296b75a76fa427, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xf0, rs 0x24296b75a76fa427, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x8a, rs 0x24296b75a76fa427, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x1c, rs 0x24296b75a76fa427, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x1a, rs 0x24296b75a76fa427, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x4, rs 0x24296b75a76fa427, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x4e, rs 0x24296b75a76fa427, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xa6, rs 0x24296b75a76fa427, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0x24296b75a76fa427, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x7e, rs 0x24296b75a76fa427, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x82, rs 0x24296b75a76fa427, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xb0, rs 0x24296b75a76fa427, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x79, rs 0x24296b75a76fa427, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0x24296b75a76fa427, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0x24296b75a76fa427, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x91, rs 0x70dc3454bfe348f, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x2f, rs 0x70dc3454bfe348f, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xf, rs 0x70dc3454bfe348f, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0x70dc3454bfe348f, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x54, rs 0x70dc3454bfe348f, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xf5, rs 0x70dc3454bfe348f, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xc5, rs 0x70dc3454bfe348f, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x36, rs 0x70dc3454bfe348f, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0xa3, rs 0x70dc3454bfe348f, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0x70dc3454bfe348f, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xe9, rs 0x70dc3454bfe348f, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0x70dc3454bfe348f, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x3a, rs 0x70dc3454bfe348f, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xde, rs 0x70dc3454bfe348f, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0x70dc3454bfe348f, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x3c, rs 0x70dc3454bfe348f, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x2a, rs 0x70dc3454bfe348f, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xdf, rs 0x70dc3454bfe348f, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x4f, rs 0x70dc3454bfe348f, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xd3, rs 0x70dc3454bfe348f, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0x70dc3454bfe348f, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x1e, rs 0x70dc3454bfe348f, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x66, rs 0x70dc3454bfe348f, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xb4, rs 0x70dc3454bfe348f, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x72, rs 0x70dc3454bfe348f, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0x70dc3454bfe348f, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x16, rs 0x70dc3454bfe348f, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x8, rs 0x70dc3454bfe348f, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xc2, rs 0x70dc3454bfe348f, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x69, rs 0x70dc3454bfe348f, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x31, rs 0x70dc3454bfe348f, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xda, rs 0x70dc3454bfe348f, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0x70dc3454bfe348f, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x7b, rs 0x70dc3454bfe348f, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x19, rs 0x70dc3454bfe348f, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xc5, rs 0x70dc3454bfe348f, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x20, rs 0x70dc3454bfe348f, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x81, rs 0x70dc3454bfe348f, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xfa, rs 0x70dc3454bfe348f, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xf0, rs 0x70dc3454bfe348f, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xcc, rs 0x70dc3454bfe348f, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0x70dc3454bfe348f, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xfa, rs 0x70dc3454bfe348f, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x7b, rs 0x70dc3454bfe348f, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0x70dc3454bfe348f, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xfd, rs 0x70dc3454bfe348f, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x84, rs 0x70dc3454bfe348f, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xde, rs 0x70dc3454bfe348f, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x2c, rs 0x70dc3454bfe348f, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x58, rs 0x70dc3454bfe348f, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0x70dc3454bfe348f, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x84, rs 0x70dc3454bfe348f, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x82, rs 0x70dc3454bfe348f, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0x70dc3454bfe348f, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0x70dc3454bfe348f, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xe, rs 0x70dc3454bfe348f, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x41, rs 0x70dc3454bfe348f, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xe6, rs 0x70dc3454bfe348f, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0x70dc3454bfe348f, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x18, rs 0x70dc3454bfe348f, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x70dc3454bfe348f, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x7b, rs 0x70dc3454bfe348f, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xf5, rs 0x70dc3454bfe348f, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0x3f63daa9afd199d7, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x77, rs 0x3f63daa9afd199d7, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x57, rs 0x3f63daa9afd199d7, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x6e, rs 0x3f63daa9afd199d7, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0x3f63daa9afd199d7, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x3d, rs 0x3f63daa9afd199d7, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xd, rs 0x3f63daa9afd199d7, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x7e, rs 0x3f63daa9afd199d7, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0x3f63daa9afd199d7, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x17, rs 0x3f63daa9afd199d7, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x31, rs 0x3f63daa9afd199d7, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x8f, rs 0x3f63daa9afd199d7, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x82, rs 0x3f63daa9afd199d7, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0x3f63daa9afd199d7, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x11, rs 0x3f63daa9afd199d7, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x84, rs 0x3f63daa9afd199d7, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x72, rs 0x3f63daa9afd199d7, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x27, rs 0x3f63daa9afd199d7, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x97, rs 0x3f63daa9afd199d7, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x1b, rs 0x3f63daa9afd199d7, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xfe, rs 0x3f63daa9afd199d7, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x66, rs 0x3f63daa9afd199d7, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xae, rs 0x3f63daa9afd199d7, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xfc, rs 0x3f63daa9afd199d7, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0x3f63daa9afd199d7, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xe4, rs 0x3f63daa9afd199d7, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x5e, rs 0x3f63daa9afd199d7, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x50, rs 0x3f63daa9afd199d7, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xa, rs 0x3f63daa9afd199d7, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0x3f63daa9afd199d7, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x79, rs 0x3f63daa9afd199d7, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x22, rs 0x3f63daa9afd199d7, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x3f63daa9afd199d7, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0xc3, rs 0x3f63daa9afd199d7, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x61, rs 0x3f63daa9afd199d7, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xd, rs 0x3f63daa9afd199d7, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x68, rs 0x3f63daa9afd199d7, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0x3f63daa9afd199d7, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0x3f63daa9afd199d7, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x38, rs 0x3f63daa9afd199d7, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x14, rs 0x3f63daa9afd199d7, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xfd, rs 0x3f63daa9afd199d7, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0x3f63daa9afd199d7, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0xc3, rs 0x3f63daa9afd199d7, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x21, rs 0x3f63daa9afd199d7, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x45, rs 0x3f63daa9afd199d7, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0xcc, rs 0x3f63daa9afd199d7, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0x3f63daa9afd199d7, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x74, rs 0x3f63daa9afd199d7, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xa0, rs 0x3f63daa9afd199d7, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x3a, rs 0x3f63daa9afd199d7, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0xcc, rs 0x3f63daa9afd199d7, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0xca, rs 0x3f63daa9afd199d7, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0xb4, rs 0x3f63daa9afd199d7, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xfe, rs 0x3f63daa9afd199d7, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x56, rs 0x3f63daa9afd199d7, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x89, rs 0x3f63daa9afd199d7, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x2e, rs 0x3f63daa9afd199d7, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x32, rs 0x3f63daa9afd199d7, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x60, rs 0x3f63daa9afd199d7, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0x3f63daa9afd199d7, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0xc3, rs 0x3f63daa9afd199d7, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x3d, rs 0x3f63daa9afd199d7, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x27, rs 0xe54750d5d9257f25, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xc5, rs 0xe54750d5d9257f25, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xa5, rs 0xe54750d5d9257f25, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xbc, rs 0xe54750d5d9257f25, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0xe54750d5d9257f25, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x8b, rs 0xe54750d5d9257f25, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x5b, rs 0xe54750d5d9257f25, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xcc, rs 0xe54750d5d9257f25, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x39, rs 0xe54750d5d9257f25, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x65, rs 0xe54750d5d9257f25, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x7f, rs 0xe54750d5d9257f25, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xdd, rs 0xe54750d5d9257f25, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xd0, rs 0xe54750d5d9257f25, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x74, rs 0xe54750d5d9257f25, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x5f, rs 0xe54750d5d9257f25, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xd2, rs 0xe54750d5d9257f25, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xc0, rs 0xe54750d5d9257f25, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0xe54750d5d9257f25, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xe5, rs 0xe54750d5d9257f25, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x69, rs 0xe54750d5d9257f25, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x4c, rs 0xe54750d5d9257f25, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xb4, rs 0xe54750d5d9257f25, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xfc, rs 0xe54750d5d9257f25, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x4a, rs 0xe54750d5d9257f25, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x8, rs 0xe54750d5d9257f25, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x32, rs 0xe54750d5d9257f25, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xac, rs 0xe54750d5d9257f25, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0xe54750d5d9257f25, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x58, rs 0xe54750d5d9257f25, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0xff, rs 0xe54750d5d9257f25, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0xe54750d5d9257f25, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0xe54750d5d9257f25, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x2f, rs 0xe54750d5d9257f25, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x11, rs 0xe54750d5d9257f25, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xaf, rs 0xe54750d5d9257f25, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x5b, rs 0xe54750d5d9257f25, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0xe54750d5d9257f25, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x17, rs 0xe54750d5d9257f25, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x90, rs 0xe54750d5d9257f25, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x86, rs 0xe54750d5d9257f25, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x62, rs 0xe54750d5d9257f25, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x4b, rs 0xe54750d5d9257f25, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x90, rs 0xe54750d5d9257f25, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x11, rs 0xe54750d5d9257f25, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x6f, rs 0xe54750d5d9257f25, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0xe54750d5d9257f25, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x1a, rs 0xe54750d5d9257f25, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x74, rs 0xe54750d5d9257f25, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xc2, rs 0xe54750d5d9257f25, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0xe54750d5d9257f25, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x88, rs 0xe54750d5d9257f25, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x1a, rs 0xe54750d5d9257f25, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x18, rs 0xe54750d5d9257f25, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0xe54750d5d9257f25, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x4c, rs 0xe54750d5d9257f25, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xa4, rs 0xe54750d5d9257f25, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xd7, rs 0xe54750d5d9257f25, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x7c, rs 0xe54750d5d9257f25, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x80, rs 0xe54750d5d9257f25, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xae, rs 0xe54750d5d9257f25, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x77, rs 0xe54750d5d9257f25, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x11, rs 0xe54750d5d9257f25, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x8b, rs 0xe54750d5d9257f25, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xe5, rs 0x3ce839a51cf929e3, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x83, rs 0x3ce839a51cf929e3, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x63, rs 0x3ce839a51cf929e3, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x7a, rs 0x3ce839a51cf929e3, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xa8, rs 0x3ce839a51cf929e3, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x49, rs 0x3ce839a51cf929e3, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x19, rs 0x3ce839a51cf929e3, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x8a, rs 0x3ce839a51cf929e3, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0x3ce839a51cf929e3, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x23, rs 0x3ce839a51cf929e3, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x3d, rs 0x3ce839a51cf929e3, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x9b, rs 0x3ce839a51cf929e3, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x8e, rs 0x3ce839a51cf929e3, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x32, rs 0x3ce839a51cf929e3, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x1d, rs 0x3ce839a51cf929e3, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x90, rs 0x3ce839a51cf929e3, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x7e, rs 0x3ce839a51cf929e3, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x33, rs 0x3ce839a51cf929e3, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xa3, rs 0x3ce839a51cf929e3, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x27, rs 0x3ce839a51cf929e3, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xa, rs 0x3ce839a51cf929e3, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x72, rs 0x3ce839a51cf929e3, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0x3ce839a51cf929e3, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x8, rs 0x3ce839a51cf929e3, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0xc6, rs 0x3ce839a51cf929e3, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xf0, rs 0x3ce839a51cf929e3, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x6a, rs 0x3ce839a51cf929e3, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x5c, rs 0x3ce839a51cf929e3, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x16, rs 0x3ce839a51cf929e3, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0x3ce839a51cf929e3, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x85, rs 0x3ce839a51cf929e3, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x2e, rs 0x3ce839a51cf929e3, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xed, rs 0x3ce839a51cf929e3, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0x3ce839a51cf929e3, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x6d, rs 0x3ce839a51cf929e3, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x19, rs 0x3ce839a51cf929e3, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x74, rs 0x3ce839a51cf929e3, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0xd5, rs 0x3ce839a51cf929e3, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x4e, rs 0x3ce839a51cf929e3, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x44, rs 0x3ce839a51cf929e3, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x20, rs 0x3ce839a51cf929e3, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x9, rs 0x3ce839a51cf929e3, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x4e, rs 0x3ce839a51cf929e3, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0x3ce839a51cf929e3, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x2d, rs 0x3ce839a51cf929e3, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x51, rs 0x3ce839a51cf929e3, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0x3ce839a51cf929e3, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x32, rs 0x3ce839a51cf929e3, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x80, rs 0x3ce839a51cf929e3, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xac, rs 0x3ce839a51cf929e3, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x46, rs 0x3ce839a51cf929e3, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0x3ce839a51cf929e3, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0xd6, rs 0x3ce839a51cf929e3, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0xc0, rs 0x3ce839a51cf929e3, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xa, rs 0x3ce839a51cf929e3, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x62, rs 0x3ce839a51cf929e3, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x95, rs 0x3ce839a51cf929e3, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x3a, rs 0x3ce839a51cf929e3, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x3e, rs 0x3ce839a51cf929e3, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0x3ce839a51cf929e3, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x35, rs 0x3ce839a51cf929e3, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0x3ce839a51cf929e3, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x49, rs 0x3ce839a51cf929e3, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xf, rs 0x84785280dd301d0d, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xad, rs 0x84785280dd301d0d, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0x84785280dd301d0d, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xa4, rs 0x84785280dd301d0d, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xd2, rs 0x84785280dd301d0d, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x73, rs 0x84785280dd301d0d, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x43, rs 0x84785280dd301d0d, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xb4, rs 0x84785280dd301d0d, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x21, rs 0x84785280dd301d0d, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0x84785280dd301d0d, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x67, rs 0x84785280dd301d0d, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xc5, rs 0x84785280dd301d0d, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xb8, rs 0x84785280dd301d0d, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x5c, rs 0x84785280dd301d0d, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0x84785280dd301d0d, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0x84785280dd301d0d, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xa8, rs 0x84785280dd301d0d, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0x84785280dd301d0d, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xcd, rs 0x84785280dd301d0d, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x51, rs 0x84785280dd301d0d, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x34, rs 0x84785280dd301d0d, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0x84785280dd301d0d, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xe4, rs 0x84785280dd301d0d, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x32, rs 0x84785280dd301d0d, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0xf0, rs 0x84785280dd301d0d, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x1a, rs 0x84785280dd301d0d, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x94, rs 0x84785280dd301d0d, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x86, rs 0x84785280dd301d0d, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x40, rs 0x84785280dd301d0d, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0xe7, rs 0x84785280dd301d0d, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xaf, rs 0x84785280dd301d0d, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x58, rs 0x84785280dd301d0d, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x17, rs 0x84785280dd301d0d, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0xf9, rs 0x84785280dd301d0d, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x97, rs 0x84785280dd301d0d, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x43, rs 0x84785280dd301d0d, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0x84785280dd301d0d, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0xff, rs 0x84785280dd301d0d, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x78, rs 0x84785280dd301d0d, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x6e, rs 0x84785280dd301d0d, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x4a, rs 0x84785280dd301d0d, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x33, rs 0x84785280dd301d0d, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x78, rs 0x84785280dd301d0d, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0xf9, rs 0x84785280dd301d0d, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x57, rs 0x84785280dd301d0d, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x7b, rs 0x84785280dd301d0d, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0x84785280dd301d0d, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x5c, rs 0x84785280dd301d0d, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xaa, rs 0x84785280dd301d0d, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xd6, rs 0x84785280dd301d0d, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0x84785280dd301d0d, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0x84785280dd301d0d, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x0, rs 0x84785280dd301d0d, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0x84785280dd301d0d, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x34, rs 0x84785280dd301d0d, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0x84785280dd301d0d, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xbf, rs 0x84785280dd301d0d, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x64, rs 0x84785280dd301d0d, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x68, rs 0x84785280dd301d0d, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x96, rs 0x84785280dd301d0d, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x5f, rs 0x84785280dd301d0d, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0xf9, rs 0x84785280dd301d0d, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x73, rs 0x84785280dd301d0d, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x89, rs 0x663d061055833287, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x27, rs 0x663d061055833287, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x7, rs 0x663d061055833287, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x1e, rs 0x663d061055833287, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x4c, rs 0x663d061055833287, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xed, rs 0x663d061055833287, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0x663d061055833287, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x2e, rs 0x663d061055833287, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x9b, rs 0x663d061055833287, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0x663d061055833287, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x663d061055833287, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x3f, rs 0x663d061055833287, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x32, rs 0x663d061055833287, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xd6, rs 0x663d061055833287, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xc1, rs 0x663d061055833287, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x34, rs 0x663d061055833287, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x22, rs 0x663d061055833287, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xd7, rs 0x663d061055833287, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0x663d061055833287, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xcb, rs 0x663d061055833287, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xae, rs 0x663d061055833287, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x16, rs 0x663d061055833287, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x5e, rs 0x663d061055833287, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xac, rs 0x663d061055833287, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x6a, rs 0x663d061055833287, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x94, rs 0x663d061055833287, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xe, rs 0x663d061055833287, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x0, rs 0x663d061055833287, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0x663d061055833287, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x61, rs 0x663d061055833287, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0x663d061055833287, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xd2, rs 0x663d061055833287, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x91, rs 0x663d061055833287, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x73, rs 0x663d061055833287, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x11, rs 0x663d061055833287, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0x663d061055833287, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x18, rs 0x663d061055833287, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x79, rs 0x663d061055833287, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0x663d061055833287, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xe8, rs 0x663d061055833287, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xc4, rs 0x663d061055833287, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xad, rs 0x663d061055833287, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0x663d061055833287, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x73, rs 0x663d061055833287, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0x663d061055833287, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xf5, rs 0x663d061055833287, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x7c, rs 0x663d061055833287, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xd6, rs 0x663d061055833287, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x24, rs 0x663d061055833287, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x50, rs 0x663d061055833287, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0x663d061055833287, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x7c, rs 0x663d061055833287, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x7a, rs 0x663d061055833287, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x64, rs 0x663d061055833287, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xae, rs 0x663d061055833287, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x6, rs 0x663d061055833287, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x39, rs 0x663d061055833287, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xde, rs 0x663d061055833287, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xe2, rs 0x663d061055833287, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x10, rs 0x663d061055833287, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0x663d061055833287, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x73, rs 0x663d061055833287, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xed, rs 0x663d061055833287, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x7b, rs 0x9ca4bdbd32be479, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x19, rs 0x9ca4bdbd32be479, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xf9, rs 0x9ca4bdbd32be479, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x10, rs 0x9ca4bdbd32be479, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x3e, rs 0x9ca4bdbd32be479, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xdf, rs 0x9ca4bdbd32be479, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xaf, rs 0x9ca4bdbd32be479, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x20, rs 0x9ca4bdbd32be479, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0x9ca4bdbd32be479, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xb9, rs 0x9ca4bdbd32be479, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xd3, rs 0x9ca4bdbd32be479, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x31, rs 0x9ca4bdbd32be479, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x24, rs 0x9ca4bdbd32be479, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xc8, rs 0x9ca4bdbd32be479, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xb3, rs 0x9ca4bdbd32be479, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0x9ca4bdbd32be479, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x14, rs 0x9ca4bdbd32be479, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0x9ca4bdbd32be479, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x39, rs 0x9ca4bdbd32be479, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0x9ca4bdbd32be479, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xa0, rs 0x9ca4bdbd32be479, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x8, rs 0x9ca4bdbd32be479, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x50, rs 0x9ca4bdbd32be479, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0x9ca4bdbd32be479, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x5c, rs 0x9ca4bdbd32be479, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x86, rs 0x9ca4bdbd32be479, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x0, rs 0x9ca4bdbd32be479, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0x9ca4bdbd32be479, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xac, rs 0x9ca4bdbd32be479, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x53, rs 0x9ca4bdbd32be479, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x1b, rs 0x9ca4bdbd32be479, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xc4, rs 0x9ca4bdbd32be479, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x83, rs 0x9ca4bdbd32be479, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x65, rs 0x9ca4bdbd32be479, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x3, rs 0x9ca4bdbd32be479, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xaf, rs 0x9ca4bdbd32be479, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xa, rs 0x9ca4bdbd32be479, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x6b, rs 0x9ca4bdbd32be479, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xe4, rs 0x9ca4bdbd32be479, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xda, rs 0x9ca4bdbd32be479, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0x9ca4bdbd32be479, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x9f, rs 0x9ca4bdbd32be479, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xe4, rs 0x9ca4bdbd32be479, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x65, rs 0x9ca4bdbd32be479, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xc3, rs 0x9ca4bdbd32be479, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xe7, rs 0x9ca4bdbd32be479, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x6e, rs 0x9ca4bdbd32be479, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xc8, rs 0x9ca4bdbd32be479, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x16, rs 0x9ca4bdbd32be479, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0x9ca4bdbd32be479, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xdc, rs 0x9ca4bdbd32be479, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x6e, rs 0x9ca4bdbd32be479, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0x9ca4bdbd32be479, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x56, rs 0x9ca4bdbd32be479, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xa0, rs 0x9ca4bdbd32be479, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xf8, rs 0x9ca4bdbd32be479, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0x9ca4bdbd32be479, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xd0, rs 0x9ca4bdbd32be479, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xd4, rs 0x9ca4bdbd32be479, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0x9ca4bdbd32be479, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xcb, rs 0x9ca4bdbd32be479, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x65, rs 0x9ca4bdbd32be479, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xdf, rs 0x9ca4bdbd32be479, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x35, rs 0x36a6f7fa3c0c9f33, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xd3, rs 0x36a6f7fa3c0c9f33, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xb3, rs 0x36a6f7fa3c0c9f33, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xca, rs 0x36a6f7fa3c0c9f33, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xf8, rs 0x36a6f7fa3c0c9f33, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0x36a6f7fa3c0c9f33, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x69, rs 0x36a6f7fa3c0c9f33, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xda, rs 0x36a6f7fa3c0c9f33, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0x36a6f7fa3c0c9f33, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x73, rs 0x36a6f7fa3c0c9f33, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0x36a6f7fa3c0c9f33, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0x36a6f7fa3c0c9f33, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xde, rs 0x36a6f7fa3c0c9f33, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x82, rs 0x36a6f7fa3c0c9f33, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x6d, rs 0x36a6f7fa3c0c9f33, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xe0, rs 0x36a6f7fa3c0c9f33, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xce, rs 0x36a6f7fa3c0c9f33, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x83, rs 0x36a6f7fa3c0c9f33, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xf3, rs 0x36a6f7fa3c0c9f33, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x77, rs 0x36a6f7fa3c0c9f33, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x5a, rs 0x36a6f7fa3c0c9f33, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xc2, rs 0x36a6f7fa3c0c9f33, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xa, rs 0x36a6f7fa3c0c9f33, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x58, rs 0x36a6f7fa3c0c9f33, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x16, rs 0x36a6f7fa3c0c9f33, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x40, rs 0x36a6f7fa3c0c9f33, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0x36a6f7fa3c0c9f33, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xac, rs 0x36a6f7fa3c0c9f33, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x66, rs 0x36a6f7fa3c0c9f33, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0xd, rs 0x36a6f7fa3c0c9f33, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xd5, rs 0x36a6f7fa3c0c9f33, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x7e, rs 0x36a6f7fa3c0c9f33, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x3d, rs 0x36a6f7fa3c0c9f33, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x1f, rs 0x36a6f7fa3c0c9f33, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0x36a6f7fa3c0c9f33, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x69, rs 0x36a6f7fa3c0c9f33, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xc4, rs 0x36a6f7fa3c0c9f33, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x25, rs 0x36a6f7fa3c0c9f33, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0x36a6f7fa3c0c9f33, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x94, rs 0x36a6f7fa3c0c9f33, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0x36a6f7fa3c0c9f33, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x59, rs 0x36a6f7fa3c0c9f33, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0x36a6f7fa3c0c9f33, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x1f, rs 0x36a6f7fa3c0c9f33, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x7d, rs 0x36a6f7fa3c0c9f33, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xa1, rs 0x36a6f7fa3c0c9f33, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x28, rs 0x36a6f7fa3c0c9f33, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x82, rs 0x36a6f7fa3c0c9f33, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xd0, rs 0x36a6f7fa3c0c9f33, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xfc, rs 0x36a6f7fa3c0c9f33, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x96, rs 0x36a6f7fa3c0c9f33, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x28, rs 0x36a6f7fa3c0c9f33, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0x36a6f7fa3c0c9f33, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x10, rs 0x36a6f7fa3c0c9f33, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x5a, rs 0x36a6f7fa3c0c9f33, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xb2, rs 0x36a6f7fa3c0c9f33, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xe5, rs 0x36a6f7fa3c0c9f33, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x8a, rs 0x36a6f7fa3c0c9f33, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x8e, rs 0x36a6f7fa3c0c9f33, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xbc, rs 0x36a6f7fa3c0c9f33, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x85, rs 0x36a6f7fa3c0c9f33, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x1f, rs 0x36a6f7fa3c0c9f33, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0x36a6f7fa3c0c9f33, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xdc, rs 0xa8b08fe67a8bc7da, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x7a, rs 0xa8b08fe67a8bc7da, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x5a, rs 0xa8b08fe67a8bc7da, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x71, rs 0xa8b08fe67a8bc7da, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x9f, rs 0xa8b08fe67a8bc7da, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x40, rs 0xa8b08fe67a8bc7da, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x10, rs 0xa8b08fe67a8bc7da, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x81, rs 0xa8b08fe67a8bc7da, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0xa8b08fe67a8bc7da, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x1a, rs 0xa8b08fe67a8bc7da, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x34, rs 0xa8b08fe67a8bc7da, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x92, rs 0xa8b08fe67a8bc7da, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x85, rs 0xa8b08fe67a8bc7da, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0xa8b08fe67a8bc7da, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x14, rs 0xa8b08fe67a8bc7da, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x87, rs 0xa8b08fe67a8bc7da, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0xa8b08fe67a8bc7da, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x2a, rs 0xa8b08fe67a8bc7da, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x9a, rs 0xa8b08fe67a8bc7da, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x1e, rs 0xa8b08fe67a8bc7da, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x1, rs 0xa8b08fe67a8bc7da, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x69, rs 0xa8b08fe67a8bc7da, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0xa8b08fe67a8bc7da, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xff, rs 0xa8b08fe67a8bc7da, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0xa8b08fe67a8bc7da, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xe7, rs 0xa8b08fe67a8bc7da, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x61, rs 0xa8b08fe67a8bc7da, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x53, rs 0xa8b08fe67a8bc7da, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xd, rs 0xa8b08fe67a8bc7da, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0xb4, rs 0xa8b08fe67a8bc7da, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x7c, rs 0xa8b08fe67a8bc7da, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x25, rs 0xa8b08fe67a8bc7da, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xe4, rs 0xa8b08fe67a8bc7da, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0xc6, rs 0xa8b08fe67a8bc7da, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x64, rs 0xa8b08fe67a8bc7da, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x10, rs 0xa8b08fe67a8bc7da, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x6b, rs 0xa8b08fe67a8bc7da, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0xcc, rs 0xa8b08fe67a8bc7da, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x45, rs 0xa8b08fe67a8bc7da, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x3b, rs 0xa8b08fe67a8bc7da, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x17, rs 0xa8b08fe67a8bc7da, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x0, rs 0xa8b08fe67a8bc7da, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x45, rs 0xa8b08fe67a8bc7da, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0xc6, rs 0xa8b08fe67a8bc7da, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x24, rs 0xa8b08fe67a8bc7da, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x48, rs 0xa8b08fe67a8bc7da, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0xa8b08fe67a8bc7da, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0xa8b08fe67a8bc7da, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x77, rs 0xa8b08fe67a8bc7da, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xa3, rs 0xa8b08fe67a8bc7da, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x3d, rs 0xa8b08fe67a8bc7da, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0xa8b08fe67a8bc7da, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0xcd, rs 0xa8b08fe67a8bc7da, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0xb7, rs 0xa8b08fe67a8bc7da, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x1, rs 0xa8b08fe67a8bc7da, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x59, rs 0xa8b08fe67a8bc7da, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0xa8b08fe67a8bc7da, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x31, rs 0xa8b08fe67a8bc7da, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x35, rs 0xa8b08fe67a8bc7da, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x63, rs 0xa8b08fe67a8bc7da, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x2c, rs 0xa8b08fe67a8bc7da, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0xc6, rs 0xa8b08fe67a8bc7da, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x40, rs 0xa8b08fe67a8bc7da, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xa4, rs 0xb665ed5e7f89e9a2, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0xb665ed5e7f89e9a2, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x22, rs 0xb665ed5e7f89e9a2, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x39, rs 0xb665ed5e7f89e9a2, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x67, rs 0xb665ed5e7f89e9a2, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x8, rs 0xb665ed5e7f89e9a2, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0xb665ed5e7f89e9a2, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x49, rs 0xb665ed5e7f89e9a2, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0xb665ed5e7f89e9a2, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xe2, rs 0xb665ed5e7f89e9a2, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xfc, rs 0xb665ed5e7f89e9a2, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x5a, rs 0xb665ed5e7f89e9a2, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0xb665ed5e7f89e9a2, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xf1, rs 0xb665ed5e7f89e9a2, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xdc, rs 0xb665ed5e7f89e9a2, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x4f, rs 0xb665ed5e7f89e9a2, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x3d, rs 0xb665ed5e7f89e9a2, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0xb665ed5e7f89e9a2, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x62, rs 0xb665ed5e7f89e9a2, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xe6, rs 0xb665ed5e7f89e9a2, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0xb665ed5e7f89e9a2, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x31, rs 0xb665ed5e7f89e9a2, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x79, rs 0xb665ed5e7f89e9a2, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0xb665ed5e7f89e9a2, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x85, rs 0xb665ed5e7f89e9a2, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xaf, rs 0xb665ed5e7f89e9a2, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0xb665ed5e7f89e9a2, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x1b, rs 0xb665ed5e7f89e9a2, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xd5, rs 0xb665ed5e7f89e9a2, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x7c, rs 0xb665ed5e7f89e9a2, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x44, rs 0xb665ed5e7f89e9a2, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xed, rs 0xb665ed5e7f89e9a2, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xac, rs 0xb665ed5e7f89e9a2, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x8e, rs 0xb665ed5e7f89e9a2, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x2c, rs 0xb665ed5e7f89e9a2, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0xb665ed5e7f89e9a2, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x33, rs 0xb665ed5e7f89e9a2, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x94, rs 0xb665ed5e7f89e9a2, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xd, rs 0xb665ed5e7f89e9a2, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x3, rs 0xb665ed5e7f89e9a2, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xdf, rs 0xb665ed5e7f89e9a2, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xc8, rs 0xb665ed5e7f89e9a2, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xd, rs 0xb665ed5e7f89e9a2, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x8e, rs 0xb665ed5e7f89e9a2, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xec, rs 0xb665ed5e7f89e9a2, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x10, rs 0xb665ed5e7f89e9a2, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x97, rs 0xb665ed5e7f89e9a2, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xf1, rs 0xb665ed5e7f89e9a2, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x3f, rs 0xb665ed5e7f89e9a2, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x6b, rs 0xb665ed5e7f89e9a2, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x5, rs 0xb665ed5e7f89e9a2, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x97, rs 0xb665ed5e7f89e9a2, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x95, rs 0xb665ed5e7f89e9a2, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x7f, rs 0xb665ed5e7f89e9a2, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0xb665ed5e7f89e9a2, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x21, rs 0xb665ed5e7f89e9a2, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x54, rs 0xb665ed5e7f89e9a2, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xf9, rs 0xb665ed5e7f89e9a2, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xfd, rs 0xb665ed5e7f89e9a2, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0xb665ed5e7f89e9a2, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xf4, rs 0xb665ed5e7f89e9a2, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x8e, rs 0xb665ed5e7f89e9a2, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x8, rs 0xb665ed5e7f89e9a2, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0x420b34f533734a4b, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0x420b34f533734a4b, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xcb, rs 0x420b34f533734a4b, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xe2, rs 0x420b34f533734a4b, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x10, rs 0x420b34f533734a4b, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0x420b34f533734a4b, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x81, rs 0x420b34f533734a4b, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0x420b34f533734a4b, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x5f, rs 0x420b34f533734a4b, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x8b, rs 0x420b34f533734a4b, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xa5, rs 0x420b34f533734a4b, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x3, rs 0x420b34f533734a4b, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xf6, rs 0x420b34f533734a4b, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x9a, rs 0x420b34f533734a4b, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x85, rs 0x420b34f533734a4b, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xf8, rs 0x420b34f533734a4b, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xe6, rs 0x420b34f533734a4b, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x9b, rs 0x420b34f533734a4b, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xb, rs 0x420b34f533734a4b, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x8f, rs 0x420b34f533734a4b, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x72, rs 0x420b34f533734a4b, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xda, rs 0x420b34f533734a4b, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x22, rs 0x420b34f533734a4b, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0x420b34f533734a4b, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x2e, rs 0x420b34f533734a4b, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x58, rs 0x420b34f533734a4b, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xd2, rs 0x420b34f533734a4b, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xc4, rs 0x420b34f533734a4b, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x7e, rs 0x420b34f533734a4b, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x25, rs 0x420b34f533734a4b, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xed, rs 0x420b34f533734a4b, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x96, rs 0x420b34f533734a4b, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x55, rs 0x420b34f533734a4b, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x37, rs 0x420b34f533734a4b, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xd5, rs 0x420b34f533734a4b, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x81, rs 0x420b34f533734a4b, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xdc, rs 0x420b34f533734a4b, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x3d, rs 0x420b34f533734a4b, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0x420b34f533734a4b, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xac, rs 0x420b34f533734a4b, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x88, rs 0x420b34f533734a4b, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x71, rs 0x420b34f533734a4b, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0x420b34f533734a4b, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x37, rs 0x420b34f533734a4b, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x95, rs 0x420b34f533734a4b, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xb9, rs 0x420b34f533734a4b, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x40, rs 0x420b34f533734a4b, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x9a, rs 0x420b34f533734a4b, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xe8, rs 0x420b34f533734a4b, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x14, rs 0x420b34f533734a4b, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xae, rs 0x420b34f533734a4b, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x40, rs 0x420b34f533734a4b, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x3e, rs 0x420b34f533734a4b, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x28, rs 0x420b34f533734a4b, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x72, rs 0x420b34f533734a4b, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xca, rs 0x420b34f533734a4b, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xfd, rs 0x420b34f533734a4b, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xa2, rs 0x420b34f533734a4b, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xa6, rs 0x420b34f533734a4b, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xd4, rs 0x420b34f533734a4b, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x9d, rs 0x420b34f533734a4b, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x37, rs 0x420b34f533734a4b, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0x420b34f533734a4b, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xc, rs 0xeaded5c53dad020a, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xaa, rs 0xeaded5c53dad020a, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x8a, rs 0xeaded5c53dad020a, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xa1, rs 0xeaded5c53dad020a, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0xeaded5c53dad020a, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0xeaded5c53dad020a, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x40, rs 0xeaded5c53dad020a, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0xeaded5c53dad020a, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x1e, rs 0xeaded5c53dad020a, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x4a, rs 0xeaded5c53dad020a, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x64, rs 0xeaded5c53dad020a, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xc2, rs 0xeaded5c53dad020a, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0xeaded5c53dad020a, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x59, rs 0xeaded5c53dad020a, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x44, rs 0xeaded5c53dad020a, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xb7, rs 0xeaded5c53dad020a, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xa5, rs 0xeaded5c53dad020a, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x5a, rs 0xeaded5c53dad020a, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xca, rs 0xeaded5c53dad020a, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x4e, rs 0xeaded5c53dad020a, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x31, rs 0xeaded5c53dad020a, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0xeaded5c53dad020a, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0xeaded5c53dad020a, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x2f, rs 0xeaded5c53dad020a, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0xed, rs 0xeaded5c53dad020a, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x17, rs 0xeaded5c53dad020a, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x91, rs 0xeaded5c53dad020a, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x83, rs 0xeaded5c53dad020a, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x3d, rs 0xeaded5c53dad020a, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0xe4, rs 0xeaded5c53dad020a, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xac, rs 0xeaded5c53dad020a, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x55, rs 0xeaded5c53dad020a, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x14, rs 0xeaded5c53dad020a, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0xf6, rs 0xeaded5c53dad020a, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x94, rs 0xeaded5c53dad020a, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x40, rs 0xeaded5c53dad020a, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x9b, rs 0xeaded5c53dad020a, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0xfc, rs 0xeaded5c53dad020a, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0xeaded5c53dad020a, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x6b, rs 0xeaded5c53dad020a, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0xeaded5c53dad020a, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x30, rs 0xeaded5c53dad020a, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0xeaded5c53dad020a, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0xf6, rs 0xeaded5c53dad020a, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x54, rs 0xeaded5c53dad020a, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x78, rs 0xeaded5c53dad020a, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0xff, rs 0xeaded5c53dad020a, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x59, rs 0xeaded5c53dad020a, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xa7, rs 0xeaded5c53dad020a, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xd3, rs 0xeaded5c53dad020a, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x6d, rs 0xeaded5c53dad020a, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0xff, rs 0xeaded5c53dad020a, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0xfd, rs 0xeaded5c53dad020a, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0xe7, rs 0xeaded5c53dad020a, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x31, rs 0xeaded5c53dad020a, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x89, rs 0xeaded5c53dad020a, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xbc, rs 0xeaded5c53dad020a, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x61, rs 0xeaded5c53dad020a, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x65, rs 0xeaded5c53dad020a, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0xeaded5c53dad020a, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x5c, rs 0xeaded5c53dad020a, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0xf6, rs 0xeaded5c53dad020a, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0xeaded5c53dad020a, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0x2299b0e01d5e68ec, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0x2299b0e01d5e68ec, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0x2299b0e01d5e68ec, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x83, rs 0x2299b0e01d5e68ec, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0x2299b0e01d5e68ec, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0x2299b0e01d5e68ec, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x22, rs 0x2299b0e01d5e68ec, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0x2299b0e01d5e68ec, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x0, rs 0x2299b0e01d5e68ec, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x2c, rs 0x2299b0e01d5e68ec, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x46, rs 0x2299b0e01d5e68ec, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xa4, rs 0x2299b0e01d5e68ec, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x97, rs 0x2299b0e01d5e68ec, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x3b, rs 0x2299b0e01d5e68ec, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0x2299b0e01d5e68ec, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0x2299b0e01d5e68ec, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x87, rs 0x2299b0e01d5e68ec, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x3c, rs 0x2299b0e01d5e68ec, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xac, rs 0x2299b0e01d5e68ec, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x30, rs 0x2299b0e01d5e68ec, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0x2299b0e01d5e68ec, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x7b, rs 0x2299b0e01d5e68ec, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xc3, rs 0x2299b0e01d5e68ec, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x11, rs 0x2299b0e01d5e68ec, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0x2299b0e01d5e68ec, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xf9, rs 0x2299b0e01d5e68ec, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x73, rs 0x2299b0e01d5e68ec, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x65, rs 0x2299b0e01d5e68ec, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x1f, rs 0x2299b0e01d5e68ec, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0xc6, rs 0x2299b0e01d5e68ec, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x8e, rs 0x2299b0e01d5e68ec, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x37, rs 0x2299b0e01d5e68ec, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xf6, rs 0x2299b0e01d5e68ec, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0x2299b0e01d5e68ec, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x76, rs 0x2299b0e01d5e68ec, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x22, rs 0x2299b0e01d5e68ec, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x7d, rs 0x2299b0e01d5e68ec, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0xde, rs 0x2299b0e01d5e68ec, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x57, rs 0x2299b0e01d5e68ec, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0x2299b0e01d5e68ec, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0x2299b0e01d5e68ec, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x12, rs 0x2299b0e01d5e68ec, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x57, rs 0x2299b0e01d5e68ec, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0x2299b0e01d5e68ec, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x36, rs 0x2299b0e01d5e68ec, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x5a, rs 0x2299b0e01d5e68ec, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x2299b0e01d5e68ec, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x3b, rs 0x2299b0e01d5e68ec, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x89, rs 0x2299b0e01d5e68ec, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0x2299b0e01d5e68ec, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x4f, rs 0x2299b0e01d5e68ec, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x2299b0e01d5e68ec, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0xdf, rs 0x2299b0e01d5e68ec, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0x2299b0e01d5e68ec, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0x2299b0e01d5e68ec, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x6b, rs 0x2299b0e01d5e68ec, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0x2299b0e01d5e68ec, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x43, rs 0x2299b0e01d5e68ec, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0x2299b0e01d5e68ec, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0x2299b0e01d5e68ec, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x3e, rs 0x2299b0e01d5e68ec, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0x2299b0e01d5e68ec, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0x2299b0e01d5e68ec, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0xe5e9a314be7fa08a, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x2a, rs 0xe5e9a314be7fa08a, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xa, rs 0xe5e9a314be7fa08a, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x21, rs 0xe5e9a314be7fa08a, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x4f, rs 0xe5e9a314be7fa08a, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xf0, rs 0xe5e9a314be7fa08a, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xc0, rs 0xe5e9a314be7fa08a, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x31, rs 0xe5e9a314be7fa08a, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0xe5e9a314be7fa08a, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xca, rs 0xe5e9a314be7fa08a, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xe4, rs 0xe5e9a314be7fa08a, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0xe5e9a314be7fa08a, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x35, rs 0xe5e9a314be7fa08a, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0xe5e9a314be7fa08a, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xc4, rs 0xe5e9a314be7fa08a, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x37, rs 0xe5e9a314be7fa08a, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x25, rs 0xe5e9a314be7fa08a, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xda, rs 0xe5e9a314be7fa08a, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x4a, rs 0xe5e9a314be7fa08a, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xce, rs 0xe5e9a314be7fa08a, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0xe5e9a314be7fa08a, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x19, rs 0xe5e9a314be7fa08a, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x61, rs 0xe5e9a314be7fa08a, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xaf, rs 0xe5e9a314be7fa08a, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x6d, rs 0xe5e9a314be7fa08a, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x97, rs 0xe5e9a314be7fa08a, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x11, rs 0xe5e9a314be7fa08a, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x3, rs 0xe5e9a314be7fa08a, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0xe5e9a314be7fa08a, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x64, rs 0xe5e9a314be7fa08a, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x2c, rs 0xe5e9a314be7fa08a, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xd5, rs 0xe5e9a314be7fa08a, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x94, rs 0xe5e9a314be7fa08a, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x76, rs 0xe5e9a314be7fa08a, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x14, rs 0xe5e9a314be7fa08a, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xc0, rs 0xe5e9a314be7fa08a, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x1b, rs 0xe5e9a314be7fa08a, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x7c, rs 0xe5e9a314be7fa08a, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xf5, rs 0xe5e9a314be7fa08a, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0xe5e9a314be7fa08a, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0xe5e9a314be7fa08a, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xb0, rs 0xe5e9a314be7fa08a, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xf5, rs 0xe5e9a314be7fa08a, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x76, rs 0xe5e9a314be7fa08a, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xd4, rs 0xe5e9a314be7fa08a, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xf8, rs 0xe5e9a314be7fa08a, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x7f, rs 0xe5e9a314be7fa08a, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0xe5e9a314be7fa08a, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x27, rs 0xe5e9a314be7fa08a, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x53, rs 0xe5e9a314be7fa08a, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xed, rs 0xe5e9a314be7fa08a, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x7f, rs 0xe5e9a314be7fa08a, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x7d, rs 0xe5e9a314be7fa08a, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x67, rs 0xe5e9a314be7fa08a, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0xe5e9a314be7fa08a, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x9, rs 0xe5e9a314be7fa08a, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x3c, rs 0xe5e9a314be7fa08a, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0xe5e9a314be7fa08a, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xe5, rs 0xe5e9a314be7fa08a, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0xe5e9a314be7fa08a, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xdc, rs 0xe5e9a314be7fa08a, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x76, rs 0xe5e9a314be7fa08a, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xf0, rs 0xe5e9a314be7fa08a, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x38, rs 0x4aeb6ca0e3459e36, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xd6, rs 0x4aeb6ca0e3459e36, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0x4aeb6ca0e3459e36, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xcd, rs 0x4aeb6ca0e3459e36, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xfb, rs 0x4aeb6ca0e3459e36, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0x4aeb6ca0e3459e36, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0x4aeb6ca0e3459e36, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xdd, rs 0x4aeb6ca0e3459e36, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x4a, rs 0x4aeb6ca0e3459e36, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x76, rs 0x4aeb6ca0e3459e36, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x90, rs 0x4aeb6ca0e3459e36, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0x4aeb6ca0e3459e36, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x4aeb6ca0e3459e36, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x85, rs 0x4aeb6ca0e3459e36, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0x4aeb6ca0e3459e36, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xe3, rs 0x4aeb6ca0e3459e36, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0x4aeb6ca0e3459e36, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x86, rs 0x4aeb6ca0e3459e36, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xf6, rs 0x4aeb6ca0e3459e36, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x7a, rs 0x4aeb6ca0e3459e36, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0x4aeb6ca0e3459e36, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xc5, rs 0x4aeb6ca0e3459e36, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xd, rs 0x4aeb6ca0e3459e36, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x5b, rs 0x4aeb6ca0e3459e36, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x19, rs 0x4aeb6ca0e3459e36, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x43, rs 0x4aeb6ca0e3459e36, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0x4aeb6ca0e3459e36, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xaf, rs 0x4aeb6ca0e3459e36, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x69, rs 0x4aeb6ca0e3459e36, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x10, rs 0x4aeb6ca0e3459e36, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0x4aeb6ca0e3459e36, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x81, rs 0x4aeb6ca0e3459e36, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x40, rs 0x4aeb6ca0e3459e36, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x22, rs 0x4aeb6ca0e3459e36, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xc0, rs 0x4aeb6ca0e3459e36, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0x4aeb6ca0e3459e36, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0x4aeb6ca0e3459e36, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x28, rs 0x4aeb6ca0e3459e36, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xa1, rs 0x4aeb6ca0e3459e36, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x97, rs 0x4aeb6ca0e3459e36, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x73, rs 0x4aeb6ca0e3459e36, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x5c, rs 0x4aeb6ca0e3459e36, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xa1, rs 0x4aeb6ca0e3459e36, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x22, rs 0x4aeb6ca0e3459e36, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x80, rs 0x4aeb6ca0e3459e36, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xa4, rs 0x4aeb6ca0e3459e36, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0x4aeb6ca0e3459e36, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x85, rs 0x4aeb6ca0e3459e36, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xd3, rs 0x4aeb6ca0e3459e36, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xff, rs 0x4aeb6ca0e3459e36, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0x4aeb6ca0e3459e36, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0x4aeb6ca0e3459e36, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0x4aeb6ca0e3459e36, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0x4aeb6ca0e3459e36, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0x4aeb6ca0e3459e36, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0x4aeb6ca0e3459e36, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xe8, rs 0x4aeb6ca0e3459e36, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0x4aeb6ca0e3459e36, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x91, rs 0x4aeb6ca0e3459e36, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xbf, rs 0x4aeb6ca0e3459e36, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x88, rs 0x4aeb6ca0e3459e36, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x22, rs 0x4aeb6ca0e3459e36, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0x4aeb6ca0e3459e36, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0x993138f16cfde991, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x31, rs 0x993138f16cfde991, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x11, rs 0x993138f16cfde991, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x28, rs 0x993138f16cfde991, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x56, rs 0x993138f16cfde991, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0x993138f16cfde991, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0x993138f16cfde991, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x38, rs 0x993138f16cfde991, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0xa5, rs 0x993138f16cfde991, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0x993138f16cfde991, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0x993138f16cfde991, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x49, rs 0x993138f16cfde991, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x3c, rs 0x993138f16cfde991, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xe0, rs 0x993138f16cfde991, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xcb, rs 0x993138f16cfde991, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x3e, rs 0x993138f16cfde991, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x2c, rs 0x993138f16cfde991, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x993138f16cfde991, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x51, rs 0x993138f16cfde991, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xd5, rs 0x993138f16cfde991, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xb8, rs 0x993138f16cfde991, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x20, rs 0x993138f16cfde991, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x68, rs 0x993138f16cfde991, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0x993138f16cfde991, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x74, rs 0x993138f16cfde991, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0x993138f16cfde991, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x18, rs 0x993138f16cfde991, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xa, rs 0x993138f16cfde991, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xc4, rs 0x993138f16cfde991, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x6b, rs 0x993138f16cfde991, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x33, rs 0x993138f16cfde991, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xdc, rs 0x993138f16cfde991, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x9b, rs 0x993138f16cfde991, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x7d, rs 0x993138f16cfde991, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x1b, rs 0x993138f16cfde991, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0x993138f16cfde991, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x22, rs 0x993138f16cfde991, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x83, rs 0x993138f16cfde991, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xfc, rs 0x993138f16cfde991, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0x993138f16cfde991, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xce, rs 0x993138f16cfde991, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xb7, rs 0x993138f16cfde991, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xfc, rs 0x993138f16cfde991, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x7d, rs 0x993138f16cfde991, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xdb, rs 0x993138f16cfde991, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xff, rs 0x993138f16cfde991, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x86, rs 0x993138f16cfde991, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xe0, rs 0x993138f16cfde991, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x2e, rs 0x993138f16cfde991, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x5a, rs 0x993138f16cfde991, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xf4, rs 0x993138f16cfde991, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x86, rs 0x993138f16cfde991, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x84, rs 0x993138f16cfde991, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x6e, rs 0x993138f16cfde991, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xb8, rs 0x993138f16cfde991, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x10, rs 0x993138f16cfde991, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x43, rs 0x993138f16cfde991, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xe8, rs 0x993138f16cfde991, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xec, rs 0x993138f16cfde991, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x1a, rs 0x993138f16cfde991, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xe3, rs 0x993138f16cfde991, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x7d, rs 0x993138f16cfde991, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0x993138f16cfde991, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xf4, rs 0x8cff404aede292f2, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x92, rs 0x8cff404aede292f2, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x72, rs 0x8cff404aede292f2, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x89, rs 0x8cff404aede292f2, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xb7, rs 0x8cff404aede292f2, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x58, rs 0x8cff404aede292f2, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x28, rs 0x8cff404aede292f2, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0x8cff404aede292f2, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x6, rs 0x8cff404aede292f2, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x32, rs 0x8cff404aede292f2, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x4c, rs 0x8cff404aede292f2, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xaa, rs 0x8cff404aede292f2, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x9d, rs 0x8cff404aede292f2, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x41, rs 0x8cff404aede292f2, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x2c, rs 0x8cff404aede292f2, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x9f, rs 0x8cff404aede292f2, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0x8cff404aede292f2, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0x8cff404aede292f2, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xb2, rs 0x8cff404aede292f2, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x36, rs 0x8cff404aede292f2, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x19, rs 0x8cff404aede292f2, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x81, rs 0x8cff404aede292f2, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0x8cff404aede292f2, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x17, rs 0x8cff404aede292f2, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0xd5, rs 0x8cff404aede292f2, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xff, rs 0x8cff404aede292f2, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x79, rs 0x8cff404aede292f2, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x6b, rs 0x8cff404aede292f2, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x25, rs 0x8cff404aede292f2, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0xcc, rs 0x8cff404aede292f2, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x94, rs 0x8cff404aede292f2, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x3d, rs 0x8cff404aede292f2, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xfc, rs 0x8cff404aede292f2, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0xde, rs 0x8cff404aede292f2, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x7c, rs 0x8cff404aede292f2, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x28, rs 0x8cff404aede292f2, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x83, rs 0x8cff404aede292f2, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0xe4, rs 0x8cff404aede292f2, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0x8cff404aede292f2, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x53, rs 0x8cff404aede292f2, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x2f, rs 0x8cff404aede292f2, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x18, rs 0x8cff404aede292f2, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0x8cff404aede292f2, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0xde, rs 0x8cff404aede292f2, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x3c, rs 0x8cff404aede292f2, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x60, rs 0x8cff404aede292f2, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0xe7, rs 0x8cff404aede292f2, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x41, rs 0x8cff404aede292f2, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x8f, rs 0x8cff404aede292f2, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xbb, rs 0x8cff404aede292f2, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x55, rs 0x8cff404aede292f2, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0xe7, rs 0x8cff404aede292f2, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0xe5, rs 0x8cff404aede292f2, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0x8cff404aede292f2, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x19, rs 0x8cff404aede292f2, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x71, rs 0x8cff404aede292f2, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xa4, rs 0x8cff404aede292f2, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x49, rs 0x8cff404aede292f2, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0x8cff404aede292f2, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x7b, rs 0x8cff404aede292f2, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x44, rs 0x8cff404aede292f2, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0xde, rs 0x8cff404aede292f2, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x58, rs 0x8cff404aede292f2, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x6d, rs 0x42e9f8548b739b6b, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xb, rs 0x42e9f8548b739b6b, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0x42e9f8548b739b6b, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0x42e9f8548b739b6b, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x30, rs 0x42e9f8548b739b6b, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0x42e9f8548b739b6b, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xa1, rs 0x42e9f8548b739b6b, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x12, rs 0x42e9f8548b739b6b, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x7f, rs 0x42e9f8548b739b6b, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xab, rs 0x42e9f8548b739b6b, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xc5, rs 0x42e9f8548b739b6b, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x23, rs 0x42e9f8548b739b6b, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x16, rs 0x42e9f8548b739b6b, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0x42e9f8548b739b6b, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xa5, rs 0x42e9f8548b739b6b, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x18, rs 0x42e9f8548b739b6b, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x6, rs 0x42e9f8548b739b6b, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xbb, rs 0x42e9f8548b739b6b, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0x42e9f8548b739b6b, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xaf, rs 0x42e9f8548b739b6b, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x92, rs 0x42e9f8548b739b6b, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xfa, rs 0x42e9f8548b739b6b, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0x42e9f8548b739b6b, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x90, rs 0x42e9f8548b739b6b, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x4e, rs 0x42e9f8548b739b6b, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x78, rs 0x42e9f8548b739b6b, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0x42e9f8548b739b6b, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xe4, rs 0x42e9f8548b739b6b, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0x42e9f8548b739b6b, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x45, rs 0x42e9f8548b739b6b, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xd, rs 0x42e9f8548b739b6b, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0x42e9f8548b739b6b, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0x42e9f8548b739b6b, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x57, rs 0x42e9f8548b739b6b, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xf5, rs 0x42e9f8548b739b6b, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xa1, rs 0x42e9f8548b739b6b, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xfc, rs 0x42e9f8548b739b6b, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0x42e9f8548b739b6b, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xd6, rs 0x42e9f8548b739b6b, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xcc, rs 0x42e9f8548b739b6b, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xa8, rs 0x42e9f8548b739b6b, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x91, rs 0x42e9f8548b739b6b, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xd6, rs 0x42e9f8548b739b6b, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x57, rs 0x42e9f8548b739b6b, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0x42e9f8548b739b6b, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0x42e9f8548b739b6b, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x60, rs 0x42e9f8548b739b6b, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0x42e9f8548b739b6b, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x8, rs 0x42e9f8548b739b6b, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x34, rs 0x42e9f8548b739b6b, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xce, rs 0x42e9f8548b739b6b, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x60, rs 0x42e9f8548b739b6b, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x5e, rs 0x42e9f8548b739b6b, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x48, rs 0x42e9f8548b739b6b, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x92, rs 0x42e9f8548b739b6b, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0x42e9f8548b739b6b, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x1d, rs 0x42e9f8548b739b6b, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xc2, rs 0x42e9f8548b739b6b, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xc6, rs 0x42e9f8548b739b6b, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xf4, rs 0x42e9f8548b739b6b, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0x42e9f8548b739b6b, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x57, rs 0x42e9f8548b739b6b, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0x42e9f8548b739b6b, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x63, rs 0x276af70a0e128561, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x1, rs 0x276af70a0e128561, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x276af70a0e128561, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xf8, rs 0x276af70a0e128561, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0x276af70a0e128561, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0x276af70a0e128561, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x97, rs 0x276af70a0e128561, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x8, rs 0x276af70a0e128561, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0x276af70a0e128561, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xa1, rs 0x276af70a0e128561, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xbb, rs 0x276af70a0e128561, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x19, rs 0x276af70a0e128561, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xc, rs 0x276af70a0e128561, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xb0, rs 0x276af70a0e128561, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x9b, rs 0x276af70a0e128561, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xe, rs 0x276af70a0e128561, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xfc, rs 0x276af70a0e128561, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0x276af70a0e128561, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x21, rs 0x276af70a0e128561, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xa5, rs 0x276af70a0e128561, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x88, rs 0x276af70a0e128561, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xf0, rs 0x276af70a0e128561, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x38, rs 0x276af70a0e128561, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x86, rs 0x276af70a0e128561, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x44, rs 0x276af70a0e128561, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x6e, rs 0x276af70a0e128561, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xe8, rs 0x276af70a0e128561, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xda, rs 0x276af70a0e128561, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x94, rs 0x276af70a0e128561, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x3b, rs 0x276af70a0e128561, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x3, rs 0x276af70a0e128561, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xac, rs 0x276af70a0e128561, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x6b, rs 0x276af70a0e128561, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0x276af70a0e128561, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0x276af70a0e128561, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x97, rs 0x276af70a0e128561, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0x276af70a0e128561, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x53, rs 0x276af70a0e128561, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xcc, rs 0x276af70a0e128561, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xc2, rs 0x276af70a0e128561, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0x276af70a0e128561, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x87, rs 0x276af70a0e128561, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xcc, rs 0x276af70a0e128561, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0x276af70a0e128561, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xab, rs 0x276af70a0e128561, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0x276af70a0e128561, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x56, rs 0x276af70a0e128561, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xb0, rs 0x276af70a0e128561, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xfe, rs 0x276af70a0e128561, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x2a, rs 0x276af70a0e128561, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xc4, rs 0x276af70a0e128561, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x56, rs 0x276af70a0e128561, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x54, rs 0x276af70a0e128561, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x3e, rs 0x276af70a0e128561, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x88, rs 0x276af70a0e128561, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xe0, rs 0x276af70a0e128561, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0x276af70a0e128561, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xb8, rs 0x276af70a0e128561, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xbc, rs 0x276af70a0e128561, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0x276af70a0e128561, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xb3, rs 0x276af70a0e128561, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0x276af70a0e128561, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0x276af70a0e128561, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x3f, rs 0x1f9720f946923c3d, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xdd, rs 0x1f9720f946923c3d, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0x1f9720f946923c3d, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xd4, rs 0x1f9720f946923c3d, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0x1f9720f946923c3d, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xa3, rs 0x1f9720f946923c3d, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x73, rs 0x1f9720f946923c3d, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xe4, rs 0x1f9720f946923c3d, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x51, rs 0x1f9720f946923c3d, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x7d, rs 0x1f9720f946923c3d, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x97, rs 0x1f9720f946923c3d, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xf5, rs 0x1f9720f946923c3d, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xe8, rs 0x1f9720f946923c3d, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0x1f9720f946923c3d, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x77, rs 0x1f9720f946923c3d, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0x1f9720f946923c3d, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0x1f9720f946923c3d, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0x1f9720f946923c3d, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xfd, rs 0x1f9720f946923c3d, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x81, rs 0x1f9720f946923c3d, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x64, rs 0x1f9720f946923c3d, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xcc, rs 0x1f9720f946923c3d, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x14, rs 0x1f9720f946923c3d, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x62, rs 0x1f9720f946923c3d, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x20, rs 0x1f9720f946923c3d, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x4a, rs 0x1f9720f946923c3d, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xc4, rs 0x1f9720f946923c3d, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0x1f9720f946923c3d, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0x1f9720f946923c3d, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x17, rs 0x1f9720f946923c3d, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xdf, rs 0x1f9720f946923c3d, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x88, rs 0x1f9720f946923c3d, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0x1f9720f946923c3d, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0x1f9720f946923c3d, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0x1f9720f946923c3d, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x73, rs 0x1f9720f946923c3d, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xce, rs 0x1f9720f946923c3d, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x2f, rs 0x1f9720f946923c3d, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xa8, rs 0x1f9720f946923c3d, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0x1f9720f946923c3d, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x7a, rs 0x1f9720f946923c3d, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x63, rs 0x1f9720f946923c3d, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xa8, rs 0x1f9720f946923c3d, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0x1f9720f946923c3d, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x87, rs 0x1f9720f946923c3d, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xab, rs 0x1f9720f946923c3d, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x32, rs 0x1f9720f946923c3d, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0x1f9720f946923c3d, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xda, rs 0x1f9720f946923c3d, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x6, rs 0x1f9720f946923c3d, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xa0, rs 0x1f9720f946923c3d, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x32, rs 0x1f9720f946923c3d, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x30, rs 0x1f9720f946923c3d, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x1a, rs 0x1f9720f946923c3d, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x64, rs 0x1f9720f946923c3d, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xbc, rs 0x1f9720f946923c3d, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xef, rs 0x1f9720f946923c3d, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x94, rs 0x1f9720f946923c3d, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x98, rs 0x1f9720f946923c3d, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xc6, rs 0x1f9720f946923c3d, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x8f, rs 0x1f9720f946923c3d, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0x1f9720f946923c3d, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xa3, rs 0x1f9720f946923c3d, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x28, rs 0xc7a59be7800f3d26, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xc6, rs 0xc7a59be7800f3d26, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xa6, rs 0xc7a59be7800f3d26, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0xc7a59be7800f3d26, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0xc7a59be7800f3d26, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0xc7a59be7800f3d26, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x5c, rs 0xc7a59be7800f3d26, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xcd, rs 0xc7a59be7800f3d26, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x3a, rs 0xc7a59be7800f3d26, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x66, rs 0xc7a59be7800f3d26, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x80, rs 0xc7a59be7800f3d26, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xde, rs 0xc7a59be7800f3d26, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0xc7a59be7800f3d26, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0xc7a59be7800f3d26, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x60, rs 0xc7a59be7800f3d26, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xd3, rs 0xc7a59be7800f3d26, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xc1, rs 0xc7a59be7800f3d26, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x76, rs 0xc7a59be7800f3d26, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xe6, rs 0xc7a59be7800f3d26, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x6a, rs 0xc7a59be7800f3d26, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0xc7a59be7800f3d26, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0xc7a59be7800f3d26, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xfd, rs 0xc7a59be7800f3d26, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x4b, rs 0xc7a59be7800f3d26, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x9, rs 0xc7a59be7800f3d26, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x33, rs 0xc7a59be7800f3d26, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xad, rs 0xc7a59be7800f3d26, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x9f, rs 0xc7a59be7800f3d26, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x59, rs 0xc7a59be7800f3d26, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x0, rs 0xc7a59be7800f3d26, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xc8, rs 0xc7a59be7800f3d26, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x71, rs 0xc7a59be7800f3d26, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x30, rs 0xc7a59be7800f3d26, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x12, rs 0xc7a59be7800f3d26, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xb0, rs 0xc7a59be7800f3d26, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x5c, rs 0xc7a59be7800f3d26, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xb7, rs 0xc7a59be7800f3d26, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x18, rs 0xc7a59be7800f3d26, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x91, rs 0xc7a59be7800f3d26, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x87, rs 0xc7a59be7800f3d26, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x63, rs 0xc7a59be7800f3d26, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x4c, rs 0xc7a59be7800f3d26, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x91, rs 0xc7a59be7800f3d26, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x12, rs 0xc7a59be7800f3d26, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0xc7a59be7800f3d26, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x94, rs 0xc7a59be7800f3d26, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x1b, rs 0xc7a59be7800f3d26, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0xc7a59be7800f3d26, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xc3, rs 0xc7a59be7800f3d26, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xef, rs 0xc7a59be7800f3d26, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x89, rs 0xc7a59be7800f3d26, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x1b, rs 0xc7a59be7800f3d26, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x19, rs 0xc7a59be7800f3d26, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x3, rs 0xc7a59be7800f3d26, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0xc7a59be7800f3d26, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xa5, rs 0xc7a59be7800f3d26, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0xc7a59be7800f3d26, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x7d, rs 0xc7a59be7800f3d26, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x81, rs 0xc7a59be7800f3d26, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xaf, rs 0xc7a59be7800f3d26, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x78, rs 0xc7a59be7800f3d26, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x12, rs 0xc7a59be7800f3d26, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0xc7a59be7800f3d26, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x6d, rs 0x743e568d2fcf486b, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xb, rs 0x743e568d2fcf486b, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xeb, rs 0x743e568d2fcf486b, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0x743e568d2fcf486b, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x30, rs 0x743e568d2fcf486b, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0x743e568d2fcf486b, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xa1, rs 0x743e568d2fcf486b, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x12, rs 0x743e568d2fcf486b, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x7f, rs 0x743e568d2fcf486b, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xab, rs 0x743e568d2fcf486b, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xc5, rs 0x743e568d2fcf486b, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x23, rs 0x743e568d2fcf486b, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x16, rs 0x743e568d2fcf486b, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0x743e568d2fcf486b, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xa5, rs 0x743e568d2fcf486b, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x18, rs 0x743e568d2fcf486b, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x6, rs 0x743e568d2fcf486b, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xbb, rs 0x743e568d2fcf486b, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0x743e568d2fcf486b, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xaf, rs 0x743e568d2fcf486b, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x92, rs 0x743e568d2fcf486b, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xfa, rs 0x743e568d2fcf486b, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0x743e568d2fcf486b, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x90, rs 0x743e568d2fcf486b, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x4e, rs 0x743e568d2fcf486b, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x78, rs 0x743e568d2fcf486b, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0x743e568d2fcf486b, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xe4, rs 0x743e568d2fcf486b, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0x743e568d2fcf486b, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x45, rs 0x743e568d2fcf486b, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xd, rs 0x743e568d2fcf486b, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0x743e568d2fcf486b, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0x743e568d2fcf486b, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x57, rs 0x743e568d2fcf486b, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xf5, rs 0x743e568d2fcf486b, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xa1, rs 0x743e568d2fcf486b, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xfc, rs 0x743e568d2fcf486b, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0x743e568d2fcf486b, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xd6, rs 0x743e568d2fcf486b, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xcc, rs 0x743e568d2fcf486b, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xa8, rs 0x743e568d2fcf486b, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x91, rs 0x743e568d2fcf486b, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xd6, rs 0x743e568d2fcf486b, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x57, rs 0x743e568d2fcf486b, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0x743e568d2fcf486b, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0x743e568d2fcf486b, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x60, rs 0x743e568d2fcf486b, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0x743e568d2fcf486b, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x8, rs 0x743e568d2fcf486b, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x34, rs 0x743e568d2fcf486b, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xce, rs 0x743e568d2fcf486b, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x60, rs 0x743e568d2fcf486b, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x5e, rs 0x743e568d2fcf486b, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x48, rs 0x743e568d2fcf486b, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x92, rs 0x743e568d2fcf486b, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0x743e568d2fcf486b, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x1d, rs 0x743e568d2fcf486b, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xc2, rs 0x743e568d2fcf486b, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xc6, rs 0x743e568d2fcf486b, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xf4, rs 0x743e568d2fcf486b, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0x743e568d2fcf486b, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x57, rs 0x743e568d2fcf486b, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0x743e568d2fcf486b, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0xdfb254da422346ec, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0xdfb254da422346ec, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0xdfb254da422346ec, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x83, rs 0xdfb254da422346ec, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0xdfb254da422346ec, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0xdfb254da422346ec, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x22, rs 0xdfb254da422346ec, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0xdfb254da422346ec, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x0, rs 0xdfb254da422346ec, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x2c, rs 0xdfb254da422346ec, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x46, rs 0xdfb254da422346ec, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xa4, rs 0xdfb254da422346ec, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x97, rs 0xdfb254da422346ec, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x3b, rs 0xdfb254da422346ec, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0xdfb254da422346ec, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0xdfb254da422346ec, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x87, rs 0xdfb254da422346ec, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x3c, rs 0xdfb254da422346ec, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xac, rs 0xdfb254da422346ec, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x30, rs 0xdfb254da422346ec, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0xdfb254da422346ec, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x7b, rs 0xdfb254da422346ec, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xc3, rs 0xdfb254da422346ec, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x11, rs 0xdfb254da422346ec, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0xdfb254da422346ec, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xf9, rs 0xdfb254da422346ec, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x73, rs 0xdfb254da422346ec, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x65, rs 0xdfb254da422346ec, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x1f, rs 0xdfb254da422346ec, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0xc6, rs 0xdfb254da422346ec, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x8e, rs 0xdfb254da422346ec, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x37, rs 0xdfb254da422346ec, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xf6, rs 0xdfb254da422346ec, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0xdfb254da422346ec, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x76, rs 0xdfb254da422346ec, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x22, rs 0xdfb254da422346ec, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x7d, rs 0xdfb254da422346ec, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0xde, rs 0xdfb254da422346ec, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x57, rs 0xdfb254da422346ec, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0xdfb254da422346ec, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0xdfb254da422346ec, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x12, rs 0xdfb254da422346ec, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x57, rs 0xdfb254da422346ec, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0xdfb254da422346ec, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x36, rs 0xdfb254da422346ec, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x5a, rs 0xdfb254da422346ec, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0xdfb254da422346ec, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x3b, rs 0xdfb254da422346ec, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x89, rs 0xdfb254da422346ec, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0xdfb254da422346ec, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x4f, rs 0xdfb254da422346ec, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0xdfb254da422346ec, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0xdf, rs 0xdfb254da422346ec, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0xdfb254da422346ec, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0xdfb254da422346ec, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x6b, rs 0xdfb254da422346ec, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0xdfb254da422346ec, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x43, rs 0xdfb254da422346ec, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0xdfb254da422346ec, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0xdfb254da422346ec, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x3e, rs 0xdfb254da422346ec, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0xdfb254da422346ec, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0xdfb254da422346ec, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x4c, rs 0x3c07af97fba6704a, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0x3c07af97fba6704a, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xca, rs 0x3c07af97fba6704a, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x3c07af97fba6704a, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xf, rs 0x3c07af97fba6704a, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xb0, rs 0x3c07af97fba6704a, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x80, rs 0x3c07af97fba6704a, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xf1, rs 0x3c07af97fba6704a, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x5e, rs 0x3c07af97fba6704a, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x8a, rs 0x3c07af97fba6704a, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xa4, rs 0x3c07af97fba6704a, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0x3c07af97fba6704a, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xf5, rs 0x3c07af97fba6704a, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0x3c07af97fba6704a, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x84, rs 0x3c07af97fba6704a, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0x3c07af97fba6704a, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xe5, rs 0x3c07af97fba6704a, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x9a, rs 0x3c07af97fba6704a, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xa, rs 0x3c07af97fba6704a, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x8e, rs 0x3c07af97fba6704a, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x71, rs 0x3c07af97fba6704a, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0x3c07af97fba6704a, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x21, rs 0x3c07af97fba6704a, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x6f, rs 0x3c07af97fba6704a, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x2d, rs 0x3c07af97fba6704a, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x57, rs 0x3c07af97fba6704a, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0x3c07af97fba6704a, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xc3, rs 0x3c07af97fba6704a, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x7d, rs 0x3c07af97fba6704a, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x24, rs 0x3c07af97fba6704a, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xec, rs 0x3c07af97fba6704a, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x95, rs 0x3c07af97fba6704a, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x54, rs 0x3c07af97fba6704a, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x36, rs 0x3c07af97fba6704a, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xd4, rs 0x3c07af97fba6704a, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x80, rs 0x3c07af97fba6704a, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xdb, rs 0x3c07af97fba6704a, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x3c, rs 0x3c07af97fba6704a, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0x3c07af97fba6704a, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xab, rs 0x3c07af97fba6704a, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x87, rs 0x3c07af97fba6704a, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0x3c07af97fba6704a, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0x3c07af97fba6704a, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x36, rs 0x3c07af97fba6704a, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x94, rs 0x3c07af97fba6704a, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xb8, rs 0x3c07af97fba6704a, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x3f, rs 0x3c07af97fba6704a, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0x3c07af97fba6704a, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xe7, rs 0x3c07af97fba6704a, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0x3c07af97fba6704a, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xad, rs 0x3c07af97fba6704a, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x3f, rs 0x3c07af97fba6704a, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x3d, rs 0x3c07af97fba6704a, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x27, rs 0x3c07af97fba6704a, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x71, rs 0x3c07af97fba6704a, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0x3c07af97fba6704a, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xfc, rs 0x3c07af97fba6704a, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xa1, rs 0x3c07af97fba6704a, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xa5, rs 0x3c07af97fba6704a, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xd3, rs 0x3c07af97fba6704a, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0x3c07af97fba6704a, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x36, rs 0x3c07af97fba6704a, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xb0, rs 0x3c07af97fba6704a, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0xd5b2120c6f52416e, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xe, rs 0xd5b2120c6f52416e, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0xd5b2120c6f52416e, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x5, rs 0xd5b2120c6f52416e, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x33, rs 0xd5b2120c6f52416e, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xd4, rs 0xd5b2120c6f52416e, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xa4, rs 0xd5b2120c6f52416e, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x15, rs 0xd5b2120c6f52416e, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x82, rs 0xd5b2120c6f52416e, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xae, rs 0xd5b2120c6f52416e, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xc8, rs 0xd5b2120c6f52416e, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0xd5b2120c6f52416e, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x19, rs 0xd5b2120c6f52416e, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0xd5b2120c6f52416e, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xa8, rs 0xd5b2120c6f52416e, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x1b, rs 0xd5b2120c6f52416e, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x9, rs 0xd5b2120c6f52416e, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xbe, rs 0xd5b2120c6f52416e, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x2e, rs 0xd5b2120c6f52416e, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xb2, rs 0xd5b2120c6f52416e, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x95, rs 0xd5b2120c6f52416e, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xfd, rs 0xd5b2120c6f52416e, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x45, rs 0xd5b2120c6f52416e, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0xd5b2120c6f52416e, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x51, rs 0xd5b2120c6f52416e, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x7b, rs 0xd5b2120c6f52416e, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xf5, rs 0xd5b2120c6f52416e, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xe7, rs 0xd5b2120c6f52416e, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xa1, rs 0xd5b2120c6f52416e, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x48, rs 0xd5b2120c6f52416e, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x10, rs 0xd5b2120c6f52416e, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xb9, rs 0xd5b2120c6f52416e, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x78, rs 0xd5b2120c6f52416e, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x5a, rs 0xd5b2120c6f52416e, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xf8, rs 0xd5b2120c6f52416e, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xa4, rs 0xd5b2120c6f52416e, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xff, rs 0xd5b2120c6f52416e, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x60, rs 0xd5b2120c6f52416e, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0xd5b2120c6f52416e, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0xd5b2120c6f52416e, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xab, rs 0xd5b2120c6f52416e, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x94, rs 0xd5b2120c6f52416e, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0xd5b2120c6f52416e, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x5a, rs 0xd5b2120c6f52416e, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xb8, rs 0xd5b2120c6f52416e, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xdc, rs 0xd5b2120c6f52416e, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x63, rs 0xd5b2120c6f52416e, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0xd5b2120c6f52416e, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xb, rs 0xd5b2120c6f52416e, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x37, rs 0xd5b2120c6f52416e, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0xd5b2120c6f52416e, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x63, rs 0xd5b2120c6f52416e, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x61, rs 0xd5b2120c6f52416e, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x4b, rs 0xd5b2120c6f52416e, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x95, rs 0xd5b2120c6f52416e, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xed, rs 0xd5b2120c6f52416e, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x20, rs 0xd5b2120c6f52416e, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xc5, rs 0xd5b2120c6f52416e, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0xd5b2120c6f52416e, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0xd5b2120c6f52416e, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xc0, rs 0xd5b2120c6f52416e, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x5a, rs 0xd5b2120c6f52416e, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xd4, rs 0xd5b2120c6f52416e, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0xa388c16272f1f8f5, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x95, rs 0xa388c16272f1f8f5, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0xa388c16272f1f8f5, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0xa388c16272f1f8f5, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0xa388c16272f1f8f5, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x5b, rs 0xa388c16272f1f8f5, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0xa388c16272f1f8f5, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0xa388c16272f1f8f5, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x9, rs 0xa388c16272f1f8f5, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x35, rs 0xa388c16272f1f8f5, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x4f, rs 0xa388c16272f1f8f5, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xad, rs 0xa388c16272f1f8f5, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xa0, rs 0xa388c16272f1f8f5, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x44, rs 0xa388c16272f1f8f5, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x2f, rs 0xa388c16272f1f8f5, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xa2, rs 0xa388c16272f1f8f5, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x90, rs 0xa388c16272f1f8f5, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x45, rs 0xa388c16272f1f8f5, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0xa388c16272f1f8f5, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x39, rs 0xa388c16272f1f8f5, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x1c, rs 0xa388c16272f1f8f5, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x84, rs 0xa388c16272f1f8f5, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xcc, rs 0xa388c16272f1f8f5, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x1a, rs 0xa388c16272f1f8f5, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0xa388c16272f1f8f5, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0xa388c16272f1f8f5, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x7c, rs 0xa388c16272f1f8f5, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x6e, rs 0xa388c16272f1f8f5, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x28, rs 0xa388c16272f1f8f5, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0xa388c16272f1f8f5, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x97, rs 0xa388c16272f1f8f5, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x40, rs 0xa388c16272f1f8f5, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xff, rs 0xa388c16272f1f8f5, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0xa388c16272f1f8f5, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x7f, rs 0xa388c16272f1f8f5, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0xa388c16272f1f8f5, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x86, rs 0xa388c16272f1f8f5, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0xe7, rs 0xa388c16272f1f8f5, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x60, rs 0xa388c16272f1f8f5, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x56, rs 0xa388c16272f1f8f5, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x32, rs 0xa388c16272f1f8f5, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x1b, rs 0xa388c16272f1f8f5, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x60, rs 0xa388c16272f1f8f5, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0xa388c16272f1f8f5, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x3f, rs 0xa388c16272f1f8f5, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x63, rs 0xa388c16272f1f8f5, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0xa388c16272f1f8f5, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x44, rs 0xa388c16272f1f8f5, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x92, rs 0xa388c16272f1f8f5, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xbe, rs 0xa388c16272f1f8f5, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x58, rs 0xa388c16272f1f8f5, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0xa388c16272f1f8f5, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0xe8, rs 0xa388c16272f1f8f5, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0xd2, rs 0xa388c16272f1f8f5, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x1c, rs 0xa388c16272f1f8f5, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x74, rs 0xa388c16272f1f8f5, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xa7, rs 0xa388c16272f1f8f5, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x4c, rs 0xa388c16272f1f8f5, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x50, rs 0xa388c16272f1f8f5, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x7e, rs 0xa388c16272f1f8f5, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0xa388c16272f1f8f5, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0xa388c16272f1f8f5, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x5b, rs 0xa388c16272f1f8f5, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x51, rs 0xb42ad6e659a7b04f, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xef, rs 0xb42ad6e659a7b04f, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0xb42ad6e659a7b04f, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xe6, rs 0xb42ad6e659a7b04f, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x14, rs 0xb42ad6e659a7b04f, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0xb42ad6e659a7b04f, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x85, rs 0xb42ad6e659a7b04f, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xf6, rs 0xb42ad6e659a7b04f, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x63, rs 0xb42ad6e659a7b04f, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x8f, rs 0xb42ad6e659a7b04f, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xa9, rs 0xb42ad6e659a7b04f, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x7, rs 0xb42ad6e659a7b04f, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xfa, rs 0xb42ad6e659a7b04f, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0xb42ad6e659a7b04f, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x89, rs 0xb42ad6e659a7b04f, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xfc, rs 0xb42ad6e659a7b04f, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0xb42ad6e659a7b04f, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x9f, rs 0xb42ad6e659a7b04f, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xf, rs 0xb42ad6e659a7b04f, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0xb42ad6e659a7b04f, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x76, rs 0xb42ad6e659a7b04f, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xde, rs 0xb42ad6e659a7b04f, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0xb42ad6e659a7b04f, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x74, rs 0xb42ad6e659a7b04f, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x32, rs 0xb42ad6e659a7b04f, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x5c, rs 0xb42ad6e659a7b04f, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xd6, rs 0xb42ad6e659a7b04f, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xc8, rs 0xb42ad6e659a7b04f, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x82, rs 0xb42ad6e659a7b04f, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0xb42ad6e659a7b04f, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xf1, rs 0xb42ad6e659a7b04f, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x9a, rs 0xb42ad6e659a7b04f, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x59, rs 0xb42ad6e659a7b04f, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x3b, rs 0xb42ad6e659a7b04f, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0xb42ad6e659a7b04f, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x85, rs 0xb42ad6e659a7b04f, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xe0, rs 0xb42ad6e659a7b04f, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x41, rs 0xb42ad6e659a7b04f, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0xb42ad6e659a7b04f, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xb0, rs 0xb42ad6e659a7b04f, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0xb42ad6e659a7b04f, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0xb42ad6e659a7b04f, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0xb42ad6e659a7b04f, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x3b, rs 0xb42ad6e659a7b04f, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0xb42ad6e659a7b04f, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0xb42ad6e659a7b04f, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x44, rs 0xb42ad6e659a7b04f, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0xb42ad6e659a7b04f, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xec, rs 0xb42ad6e659a7b04f, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x18, rs 0xb42ad6e659a7b04f, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xb2, rs 0xb42ad6e659a7b04f, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x44, rs 0xb42ad6e659a7b04f, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0xb42ad6e659a7b04f, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x2c, rs 0xb42ad6e659a7b04f, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x76, rs 0xb42ad6e659a7b04f, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xce, rs 0xb42ad6e659a7b04f, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x1, rs 0xb42ad6e659a7b04f, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xa6, rs 0xb42ad6e659a7b04f, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xaa, rs 0xb42ad6e659a7b04f, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0xb42ad6e659a7b04f, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xa1, rs 0xb42ad6e659a7b04f, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x3b, rs 0xb42ad6e659a7b04f, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0xb42ad6e659a7b04f, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x9f, rs 0x53606bb4bf0c999d, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x3d, rs 0x53606bb4bf0c999d, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x1d, rs 0x53606bb4bf0c999d, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x34, rs 0x53606bb4bf0c999d, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x62, rs 0x53606bb4bf0c999d, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x3, rs 0x53606bb4bf0c999d, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xd3, rs 0x53606bb4bf0c999d, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x44, rs 0x53606bb4bf0c999d, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0x53606bb4bf0c999d, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xdd, rs 0x53606bb4bf0c999d, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0x53606bb4bf0c999d, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x55, rs 0x53606bb4bf0c999d, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x48, rs 0x53606bb4bf0c999d, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xec, rs 0x53606bb4bf0c999d, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xd7, rs 0x53606bb4bf0c999d, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x4a, rs 0x53606bb4bf0c999d, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x38, rs 0x53606bb4bf0c999d, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xed, rs 0x53606bb4bf0c999d, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0x53606bb4bf0c999d, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x53606bb4bf0c999d, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xc4, rs 0x53606bb4bf0c999d, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x2c, rs 0x53606bb4bf0c999d, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x74, rs 0x53606bb4bf0c999d, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xc2, rs 0x53606bb4bf0c999d, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x80, rs 0x53606bb4bf0c999d, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xaa, rs 0x53606bb4bf0c999d, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x24, rs 0x53606bb4bf0c999d, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x16, rs 0x53606bb4bf0c999d, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xd0, rs 0x53606bb4bf0c999d, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x77, rs 0x53606bb4bf0c999d, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x3f, rs 0x53606bb4bf0c999d, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xe8, rs 0x53606bb4bf0c999d, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xa7, rs 0x53606bb4bf0c999d, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x89, rs 0x53606bb4bf0c999d, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x27, rs 0x53606bb4bf0c999d, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xd3, rs 0x53606bb4bf0c999d, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x2e, rs 0x53606bb4bf0c999d, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x8f, rs 0x53606bb4bf0c999d, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x8, rs 0x53606bb4bf0c999d, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xfe, rs 0x53606bb4bf0c999d, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xda, rs 0x53606bb4bf0c999d, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xc3, rs 0x53606bb4bf0c999d, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x8, rs 0x53606bb4bf0c999d, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x89, rs 0x53606bb4bf0c999d, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xe7, rs 0x53606bb4bf0c999d, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xb, rs 0x53606bb4bf0c999d, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x92, rs 0x53606bb4bf0c999d, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xec, rs 0x53606bb4bf0c999d, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x3a, rs 0x53606bb4bf0c999d, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x66, rs 0x53606bb4bf0c999d, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x0, rs 0x53606bb4bf0c999d, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x92, rs 0x53606bb4bf0c999d, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x90, rs 0x53606bb4bf0c999d, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x7a, rs 0x53606bb4bf0c999d, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xc4, rs 0x53606bb4bf0c999d, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x1c, rs 0x53606bb4bf0c999d, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x4f, rs 0x53606bb4bf0c999d, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xf4, rs 0x53606bb4bf0c999d, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xf8, rs 0x53606bb4bf0c999d, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0x53606bb4bf0c999d, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xef, rs 0x53606bb4bf0c999d, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x89, rs 0x53606bb4bf0c999d, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x3, rs 0x53606bb4bf0c999d, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xcb, rs 0x15ebf6121dca77c9, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x69, rs 0x15ebf6121dca77c9, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x49, rs 0x15ebf6121dca77c9, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x60, rs 0x15ebf6121dca77c9, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x8e, rs 0x15ebf6121dca77c9, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x2f, rs 0x15ebf6121dca77c9, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xff, rs 0x15ebf6121dca77c9, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0x15ebf6121dca77c9, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0xdd, rs 0x15ebf6121dca77c9, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x9, rs 0x15ebf6121dca77c9, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x23, rs 0x15ebf6121dca77c9, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x81, rs 0x15ebf6121dca77c9, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x74, rs 0x15ebf6121dca77c9, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x18, rs 0x15ebf6121dca77c9, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x3, rs 0x15ebf6121dca77c9, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x76, rs 0x15ebf6121dca77c9, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x64, rs 0x15ebf6121dca77c9, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x19, rs 0x15ebf6121dca77c9, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x89, rs 0x15ebf6121dca77c9, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xd, rs 0x15ebf6121dca77c9, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xf0, rs 0x15ebf6121dca77c9, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x58, rs 0x15ebf6121dca77c9, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xa0, rs 0x15ebf6121dca77c9, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0x15ebf6121dca77c9, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0xac, rs 0x15ebf6121dca77c9, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xd6, rs 0x15ebf6121dca77c9, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x50, rs 0x15ebf6121dca77c9, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0x15ebf6121dca77c9, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xfc, rs 0x15ebf6121dca77c9, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0xa3, rs 0x15ebf6121dca77c9, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x6b, rs 0x15ebf6121dca77c9, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x14, rs 0x15ebf6121dca77c9, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xd3, rs 0x15ebf6121dca77c9, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0x15ebf6121dca77c9, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x53, rs 0x15ebf6121dca77c9, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xff, rs 0x15ebf6121dca77c9, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x5a, rs 0x15ebf6121dca77c9, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0xbb, rs 0x15ebf6121dca77c9, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x34, rs 0x15ebf6121dca77c9, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x2a, rs 0x15ebf6121dca77c9, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x6, rs 0x15ebf6121dca77c9, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xef, rs 0x15ebf6121dca77c9, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x34, rs 0x15ebf6121dca77c9, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0x15ebf6121dca77c9, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0x15ebf6121dca77c9, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x37, rs 0x15ebf6121dca77c9, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0xbe, rs 0x15ebf6121dca77c9, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x18, rs 0x15ebf6121dca77c9, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x66, rs 0x15ebf6121dca77c9, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x92, rs 0x15ebf6121dca77c9, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x2c, rs 0x15ebf6121dca77c9, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0xbe, rs 0x15ebf6121dca77c9, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0xbc, rs 0x15ebf6121dca77c9, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0xa6, rs 0x15ebf6121dca77c9, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xf0, rs 0x15ebf6121dca77c9, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x48, rs 0x15ebf6121dca77c9, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x7b, rs 0x15ebf6121dca77c9, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x20, rs 0x15ebf6121dca77c9, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x24, rs 0x15ebf6121dca77c9, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0x15ebf6121dca77c9, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x1b, rs 0x15ebf6121dca77c9, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0x15ebf6121dca77c9, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x2f, rs 0x15ebf6121dca77c9, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x65, rs 0x14abf36419fb9e63, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x3, rs 0x14abf36419fb9e63, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xe3, rs 0x14abf36419fb9e63, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xfa, rs 0x14abf36419fb9e63, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x28, rs 0x14abf36419fb9e63, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0x14abf36419fb9e63, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0x14abf36419fb9e63, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xa, rs 0x14abf36419fb9e63, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x77, rs 0x14abf36419fb9e63, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xa3, rs 0x14abf36419fb9e63, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0x14abf36419fb9e63, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x1b, rs 0x14abf36419fb9e63, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xe, rs 0x14abf36419fb9e63, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xb2, rs 0x14abf36419fb9e63, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x9d, rs 0x14abf36419fb9e63, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x10, rs 0x14abf36419fb9e63, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xfe, rs 0x14abf36419fb9e63, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xb3, rs 0x14abf36419fb9e63, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x23, rs 0x14abf36419fb9e63, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xa7, rs 0x14abf36419fb9e63, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x8a, rs 0x14abf36419fb9e63, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0x14abf36419fb9e63, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x3a, rs 0x14abf36419fb9e63, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x88, rs 0x14abf36419fb9e63, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x46, rs 0x14abf36419fb9e63, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0x14abf36419fb9e63, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0x14abf36419fb9e63, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xdc, rs 0x14abf36419fb9e63, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x96, rs 0x14abf36419fb9e63, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x3d, rs 0x14abf36419fb9e63, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x5, rs 0x14abf36419fb9e63, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xae, rs 0x14abf36419fb9e63, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x6d, rs 0x14abf36419fb9e63, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x4f, rs 0x14abf36419fb9e63, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xed, rs 0x14abf36419fb9e63, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0x14abf36419fb9e63, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xf4, rs 0x14abf36419fb9e63, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x55, rs 0x14abf36419fb9e63, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xce, rs 0x14abf36419fb9e63, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xc4, rs 0x14abf36419fb9e63, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xa0, rs 0x14abf36419fb9e63, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x89, rs 0x14abf36419fb9e63, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xce, rs 0x14abf36419fb9e63, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x4f, rs 0x14abf36419fb9e63, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xad, rs 0x14abf36419fb9e63, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0x14abf36419fb9e63, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x58, rs 0x14abf36419fb9e63, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xb2, rs 0x14abf36419fb9e63, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x0, rs 0x14abf36419fb9e63, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x2c, rs 0x14abf36419fb9e63, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xc6, rs 0x14abf36419fb9e63, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x58, rs 0x14abf36419fb9e63, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x56, rs 0x14abf36419fb9e63, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x40, rs 0x14abf36419fb9e63, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x8a, rs 0x14abf36419fb9e63, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xe2, rs 0x14abf36419fb9e63, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x15, rs 0x14abf36419fb9e63, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0x14abf36419fb9e63, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xbe, rs 0x14abf36419fb9e63, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xec, rs 0x14abf36419fb9e63, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0x14abf36419fb9e63, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x4f, rs 0x14abf36419fb9e63, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0x14abf36419fb9e63, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0x7e35ce6d56e670f5, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x95, rs 0x7e35ce6d56e670f5, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0x7e35ce6d56e670f5, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0x7e35ce6d56e670f5, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0x7e35ce6d56e670f5, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x5b, rs 0x7e35ce6d56e670f5, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0x7e35ce6d56e670f5, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0x7e35ce6d56e670f5, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x9, rs 0x7e35ce6d56e670f5, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x35, rs 0x7e35ce6d56e670f5, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x4f, rs 0x7e35ce6d56e670f5, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xad, rs 0x7e35ce6d56e670f5, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xa0, rs 0x7e35ce6d56e670f5, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x44, rs 0x7e35ce6d56e670f5, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x2f, rs 0x7e35ce6d56e670f5, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xa2, rs 0x7e35ce6d56e670f5, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x90, rs 0x7e35ce6d56e670f5, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x45, rs 0x7e35ce6d56e670f5, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0x7e35ce6d56e670f5, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x39, rs 0x7e35ce6d56e670f5, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x1c, rs 0x7e35ce6d56e670f5, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x84, rs 0x7e35ce6d56e670f5, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xcc, rs 0x7e35ce6d56e670f5, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x1a, rs 0x7e35ce6d56e670f5, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0x7e35ce6d56e670f5, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0x7e35ce6d56e670f5, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x7c, rs 0x7e35ce6d56e670f5, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x6e, rs 0x7e35ce6d56e670f5, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x28, rs 0x7e35ce6d56e670f5, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0x7e35ce6d56e670f5, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x97, rs 0x7e35ce6d56e670f5, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x40, rs 0x7e35ce6d56e670f5, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xff, rs 0x7e35ce6d56e670f5, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x7e35ce6d56e670f5, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x7f, rs 0x7e35ce6d56e670f5, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0x7e35ce6d56e670f5, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x86, rs 0x7e35ce6d56e670f5, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0xe7, rs 0x7e35ce6d56e670f5, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x60, rs 0x7e35ce6d56e670f5, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x56, rs 0x7e35ce6d56e670f5, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x32, rs 0x7e35ce6d56e670f5, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x1b, rs 0x7e35ce6d56e670f5, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x60, rs 0x7e35ce6d56e670f5, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x7e35ce6d56e670f5, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x3f, rs 0x7e35ce6d56e670f5, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x63, rs 0x7e35ce6d56e670f5, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0x7e35ce6d56e670f5, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x44, rs 0x7e35ce6d56e670f5, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x92, rs 0x7e35ce6d56e670f5, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xbe, rs 0x7e35ce6d56e670f5, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x58, rs 0x7e35ce6d56e670f5, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0x7e35ce6d56e670f5, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0xe8, rs 0x7e35ce6d56e670f5, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0xd2, rs 0x7e35ce6d56e670f5, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x1c, rs 0x7e35ce6d56e670f5, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x74, rs 0x7e35ce6d56e670f5, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xa7, rs 0x7e35ce6d56e670f5, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x4c, rs 0x7e35ce6d56e670f5, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x50, rs 0x7e35ce6d56e670f5, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x7e, rs 0x7e35ce6d56e670f5, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0x7e35ce6d56e670f5, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x7e35ce6d56e670f5, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x5b, rs 0x7e35ce6d56e670f5, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xf5, rs 0xf2e7a490978058f3, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0xf2e7a490978058f3, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x73, rs 0xf2e7a490978058f3, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x8a, rs 0xf2e7a490978058f3, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xb8, rs 0xf2e7a490978058f3, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x59, rs 0xf2e7a490978058f3, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0xf2e7a490978058f3, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x9a, rs 0xf2e7a490978058f3, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x7, rs 0xf2e7a490978058f3, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x33, rs 0xf2e7a490978058f3, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0xf2e7a490978058f3, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xab, rs 0xf2e7a490978058f3, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0xf2e7a490978058f3, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0xf2e7a490978058f3, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x2d, rs 0xf2e7a490978058f3, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xa0, rs 0xf2e7a490978058f3, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x8e, rs 0xf2e7a490978058f3, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x43, rs 0xf2e7a490978058f3, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xb3, rs 0xf2e7a490978058f3, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x37, rs 0xf2e7a490978058f3, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x1a, rs 0xf2e7a490978058f3, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x82, rs 0xf2e7a490978058f3, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xca, rs 0xf2e7a490978058f3, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x18, rs 0xf2e7a490978058f3, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0xd6, rs 0xf2e7a490978058f3, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x0, rs 0xf2e7a490978058f3, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x7a, rs 0xf2e7a490978058f3, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0xf2e7a490978058f3, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0xf2e7a490978058f3, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0xcd, rs 0xf2e7a490978058f3, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x95, rs 0xf2e7a490978058f3, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x3e, rs 0xf2e7a490978058f3, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xfd, rs 0xf2e7a490978058f3, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0xdf, rs 0xf2e7a490978058f3, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x7d, rs 0xf2e7a490978058f3, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0xf2e7a490978058f3, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x84, rs 0xf2e7a490978058f3, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0xe5, rs 0xf2e7a490978058f3, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x5e, rs 0xf2e7a490978058f3, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x54, rs 0xf2e7a490978058f3, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x30, rs 0xf2e7a490978058f3, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x19, rs 0xf2e7a490978058f3, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x5e, rs 0xf2e7a490978058f3, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0xdf, rs 0xf2e7a490978058f3, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x3d, rs 0xf2e7a490978058f3, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x61, rs 0xf2e7a490978058f3, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0xe8, rs 0xf2e7a490978058f3, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x42, rs 0xf2e7a490978058f3, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x90, rs 0xf2e7a490978058f3, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xbc, rs 0xf2e7a490978058f3, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x56, rs 0xf2e7a490978058f3, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0xe8, rs 0xf2e7a490978058f3, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0xe6, rs 0xf2e7a490978058f3, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0xd0, rs 0xf2e7a490978058f3, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x1a, rs 0xf2e7a490978058f3, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x72, rs 0xf2e7a490978058f3, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xa5, rs 0xf2e7a490978058f3, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x4a, rs 0xf2e7a490978058f3, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x4e, rs 0xf2e7a490978058f3, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x7c, rs 0xf2e7a490978058f3, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x45, rs 0xf2e7a490978058f3, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0xdf, rs 0xf2e7a490978058f3, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x59, rs 0xf2e7a490978058f3, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xdf, rs 0xa3d991b79941dedd, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x7d, rs 0xa3d991b79941dedd, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0xa3d991b79941dedd, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x74, rs 0xa3d991b79941dedd, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xa2, rs 0xa3d991b79941dedd, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x43, rs 0xa3d991b79941dedd, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0xa3d991b79941dedd, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x84, rs 0xa3d991b79941dedd, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0xf1, rs 0xa3d991b79941dedd, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x1d, rs 0xa3d991b79941dedd, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x37, rs 0xa3d991b79941dedd, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x95, rs 0xa3d991b79941dedd, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x88, rs 0xa3d991b79941dedd, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x2c, rs 0xa3d991b79941dedd, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x17, rs 0xa3d991b79941dedd, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x8a, rs 0xa3d991b79941dedd, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x78, rs 0xa3d991b79941dedd, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x2d, rs 0xa3d991b79941dedd, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x9d, rs 0xa3d991b79941dedd, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x21, rs 0xa3d991b79941dedd, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x4, rs 0xa3d991b79941dedd, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0xa3d991b79941dedd, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xb4, rs 0xa3d991b79941dedd, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0xa3d991b79941dedd, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0xc0, rs 0xa3d991b79941dedd, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0xa3d991b79941dedd, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x64, rs 0xa3d991b79941dedd, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x56, rs 0xa3d991b79941dedd, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x10, rs 0xa3d991b79941dedd, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0xb7, rs 0xa3d991b79941dedd, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x7f, rs 0xa3d991b79941dedd, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x28, rs 0xa3d991b79941dedd, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xe7, rs 0xa3d991b79941dedd, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0xa3d991b79941dedd, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x67, rs 0xa3d991b79941dedd, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0xa3d991b79941dedd, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x6e, rs 0xa3d991b79941dedd, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0xa3d991b79941dedd, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x48, rs 0xa3d991b79941dedd, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x3e, rs 0xa3d991b79941dedd, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x1a, rs 0xa3d991b79941dedd, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x3, rs 0xa3d991b79941dedd, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x48, rs 0xa3d991b79941dedd, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0xa3d991b79941dedd, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x27, rs 0xa3d991b79941dedd, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x4b, rs 0xa3d991b79941dedd, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0xd2, rs 0xa3d991b79941dedd, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x2c, rs 0xa3d991b79941dedd, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x7a, rs 0xa3d991b79941dedd, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xa6, rs 0xa3d991b79941dedd, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x40, rs 0xa3d991b79941dedd, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0xd2, rs 0xa3d991b79941dedd, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0xd0, rs 0xa3d991b79941dedd, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0xa3d991b79941dedd, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x4, rs 0xa3d991b79941dedd, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x5c, rs 0xa3d991b79941dedd, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x8f, rs 0xa3d991b79941dedd, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x34, rs 0xa3d991b79941dedd, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x38, rs 0xa3d991b79941dedd, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x66, rs 0xa3d991b79941dedd, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x2f, rs 0xa3d991b79941dedd, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0xa3d991b79941dedd, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x43, rs 0xa3d991b79941dedd, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0x185b88e0db8d7d27, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0x185b88e0db8d7d27, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xa7, rs 0x185b88e0db8d7d27, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xbe, rs 0x185b88e0db8d7d27, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xec, rs 0x185b88e0db8d7d27, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0x185b88e0db8d7d27, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0x185b88e0db8d7d27, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xce, rs 0x185b88e0db8d7d27, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x3b, rs 0x185b88e0db8d7d27, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x67, rs 0x185b88e0db8d7d27, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x81, rs 0x185b88e0db8d7d27, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xdf, rs 0x185b88e0db8d7d27, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xd2, rs 0x185b88e0db8d7d27, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x76, rs 0x185b88e0db8d7d27, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x61, rs 0x185b88e0db8d7d27, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xd4, rs 0x185b88e0db8d7d27, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xc2, rs 0x185b88e0db8d7d27, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x77, rs 0x185b88e0db8d7d27, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xe7, rs 0x185b88e0db8d7d27, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x6b, rs 0x185b88e0db8d7d27, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x4e, rs 0x185b88e0db8d7d27, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0x185b88e0db8d7d27, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xfe, rs 0x185b88e0db8d7d27, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x4c, rs 0x185b88e0db8d7d27, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0xa, rs 0x185b88e0db8d7d27, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x34, rs 0x185b88e0db8d7d27, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xae, rs 0x185b88e0db8d7d27, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xa0, rs 0x185b88e0db8d7d27, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x5a, rs 0x185b88e0db8d7d27, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x1, rs 0x185b88e0db8d7d27, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0x185b88e0db8d7d27, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x72, rs 0x185b88e0db8d7d27, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x31, rs 0x185b88e0db8d7d27, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0x185b88e0db8d7d27, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0x185b88e0db8d7d27, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0x185b88e0db8d7d27, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xb8, rs 0x185b88e0db8d7d27, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x19, rs 0x185b88e0db8d7d27, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x92, rs 0x185b88e0db8d7d27, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x88, rs 0x185b88e0db8d7d27, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x64, rs 0x185b88e0db8d7d27, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0x185b88e0db8d7d27, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x92, rs 0x185b88e0db8d7d27, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0x185b88e0db8d7d27, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x71, rs 0x185b88e0db8d7d27, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x95, rs 0x185b88e0db8d7d27, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x1c, rs 0x185b88e0db8d7d27, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x76, rs 0x185b88e0db8d7d27, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xc4, rs 0x185b88e0db8d7d27, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xf0, rs 0x185b88e0db8d7d27, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x8a, rs 0x185b88e0db8d7d27, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x1c, rs 0x185b88e0db8d7d27, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x1a, rs 0x185b88e0db8d7d27, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x4, rs 0x185b88e0db8d7d27, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x4e, rs 0x185b88e0db8d7d27, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xa6, rs 0x185b88e0db8d7d27, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0x185b88e0db8d7d27, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x7e, rs 0x185b88e0db8d7d27, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x82, rs 0x185b88e0db8d7d27, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xb0, rs 0x185b88e0db8d7d27, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x79, rs 0x185b88e0db8d7d27, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0x185b88e0db8d7d27, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0x185b88e0db8d7d27, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x81, rs 0xd58ecbabde35697f, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x1f, rs 0xd58ecbabde35697f, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xff, rs 0xd58ecbabde35697f, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x16, rs 0xd58ecbabde35697f, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x44, rs 0xd58ecbabde35697f, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xe5, rs 0xd58ecbabde35697f, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0xd58ecbabde35697f, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0xd58ecbabde35697f, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0xd58ecbabde35697f, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xbf, rs 0xd58ecbabde35697f, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0xd58ecbabde35697f, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x37, rs 0xd58ecbabde35697f, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x2a, rs 0xd58ecbabde35697f, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xce, rs 0xd58ecbabde35697f, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xb9, rs 0xd58ecbabde35697f, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x2c, rs 0xd58ecbabde35697f, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x1a, rs 0xd58ecbabde35697f, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0xd58ecbabde35697f, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x3f, rs 0xd58ecbabde35697f, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xc3, rs 0xd58ecbabde35697f, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xa6, rs 0xd58ecbabde35697f, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xe, rs 0xd58ecbabde35697f, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x56, rs 0xd58ecbabde35697f, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xa4, rs 0xd58ecbabde35697f, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x62, rs 0xd58ecbabde35697f, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0xd58ecbabde35697f, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x6, rs 0xd58ecbabde35697f, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xf8, rs 0xd58ecbabde35697f, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xb2, rs 0xd58ecbabde35697f, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x59, rs 0xd58ecbabde35697f, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x21, rs 0xd58ecbabde35697f, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xca, rs 0xd58ecbabde35697f, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x89, rs 0xd58ecbabde35697f, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x6b, rs 0xd58ecbabde35697f, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x9, rs 0xd58ecbabde35697f, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0xd58ecbabde35697f, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x10, rs 0xd58ecbabde35697f, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x71, rs 0xd58ecbabde35697f, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0xd58ecbabde35697f, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xe0, rs 0xd58ecbabde35697f, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xbc, rs 0xd58ecbabde35697f, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xa5, rs 0xd58ecbabde35697f, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0xd58ecbabde35697f, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x6b, rs 0xd58ecbabde35697f, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0xd58ecbabde35697f, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xed, rs 0xd58ecbabde35697f, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x74, rs 0xd58ecbabde35697f, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xce, rs 0xd58ecbabde35697f, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x1c, rs 0xd58ecbabde35697f, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x48, rs 0xd58ecbabde35697f, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xe2, rs 0xd58ecbabde35697f, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x74, rs 0xd58ecbabde35697f, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x72, rs 0xd58ecbabde35697f, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x5c, rs 0xd58ecbabde35697f, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xa6, rs 0xd58ecbabde35697f, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xfe, rs 0xd58ecbabde35697f, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x31, rs 0xd58ecbabde35697f, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xd6, rs 0xd58ecbabde35697f, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xda, rs 0xd58ecbabde35697f, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x8, rs 0xd58ecbabde35697f, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0xd58ecbabde35697f, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x6b, rs 0xd58ecbabde35697f, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xe5, rs 0xd58ecbabde35697f, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xb4, rs 0x2f7e224a1c170ab2, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0x2f7e224a1c170ab2, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x32, rs 0x2f7e224a1c170ab2, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x49, rs 0x2f7e224a1c170ab2, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x77, rs 0x2f7e224a1c170ab2, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x18, rs 0x2f7e224a1c170ab2, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xe8, rs 0x2f7e224a1c170ab2, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x59, rs 0x2f7e224a1c170ab2, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0xc6, rs 0x2f7e224a1c170ab2, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0x2f7e224a1c170ab2, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xc, rs 0x2f7e224a1c170ab2, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x6a, rs 0x2f7e224a1c170ab2, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0x2f7e224a1c170ab2, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x1, rs 0x2f7e224a1c170ab2, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xec, rs 0x2f7e224a1c170ab2, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x5f, rs 0x2f7e224a1c170ab2, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0x2f7e224a1c170ab2, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0x2f7e224a1c170ab2, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x72, rs 0x2f7e224a1c170ab2, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xf6, rs 0x2f7e224a1c170ab2, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0x2f7e224a1c170ab2, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x41, rs 0x2f7e224a1c170ab2, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x89, rs 0x2f7e224a1c170ab2, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xd7, rs 0x2f7e224a1c170ab2, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x95, rs 0x2f7e224a1c170ab2, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xbf, rs 0x2f7e224a1c170ab2, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x39, rs 0x2f7e224a1c170ab2, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0x2f7e224a1c170ab2, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xe5, rs 0x2f7e224a1c170ab2, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0x2f7e224a1c170ab2, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x54, rs 0x2f7e224a1c170ab2, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xfd, rs 0x2f7e224a1c170ab2, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xbc, rs 0x2f7e224a1c170ab2, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0x2f7e224a1c170ab2, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x3c, rs 0x2f7e224a1c170ab2, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xe8, rs 0x2f7e224a1c170ab2, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x43, rs 0x2f7e224a1c170ab2, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0xa4, rs 0x2f7e224a1c170ab2, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x1d, rs 0x2f7e224a1c170ab2, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0x2f7e224a1c170ab2, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xef, rs 0x2f7e224a1c170ab2, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0x2f7e224a1c170ab2, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x1d, rs 0x2f7e224a1c170ab2, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0x2f7e224a1c170ab2, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xfc, rs 0x2f7e224a1c170ab2, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x20, rs 0x2f7e224a1c170ab2, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0xa7, rs 0x2f7e224a1c170ab2, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x1, rs 0x2f7e224a1c170ab2, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x4f, rs 0x2f7e224a1c170ab2, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x7b, rs 0x2f7e224a1c170ab2, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x15, rs 0x2f7e224a1c170ab2, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0xa7, rs 0x2f7e224a1c170ab2, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0xa5, rs 0x2f7e224a1c170ab2, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x8f, rs 0x2f7e224a1c170ab2, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0x2f7e224a1c170ab2, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x31, rs 0x2f7e224a1c170ab2, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x64, rs 0x2f7e224a1c170ab2, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x9, rs 0x2f7e224a1c170ab2, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xd, rs 0x2f7e224a1c170ab2, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x3b, rs 0x2f7e224a1c170ab2, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x4, rs 0x2f7e224a1c170ab2, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0x2f7e224a1c170ab2, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x18, rs 0x2f7e224a1c170ab2, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x59, rs 0xfe71fca06c0eb657, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0xfe71fca06c0eb657, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xd7, rs 0xfe71fca06c0eb657, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0xfe71fca06c0eb657, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x1c, rs 0xfe71fca06c0eb657, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0xfe71fca06c0eb657, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0xfe71fca06c0eb657, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xfe, rs 0xfe71fca06c0eb657, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x6b, rs 0xfe71fca06c0eb657, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x97, rs 0xfe71fca06c0eb657, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0xfe71fca06c0eb657, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xf, rs 0xfe71fca06c0eb657, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0xfe71fca06c0eb657, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xa6, rs 0xfe71fca06c0eb657, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x91, rs 0xfe71fca06c0eb657, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x4, rs 0xfe71fca06c0eb657, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0xfe71fca06c0eb657, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xa7, rs 0xfe71fca06c0eb657, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x17, rs 0xfe71fca06c0eb657, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x9b, rs 0xfe71fca06c0eb657, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x7e, rs 0xfe71fca06c0eb657, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xe6, rs 0xfe71fca06c0eb657, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x2e, rs 0xfe71fca06c0eb657, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x7c, rs 0xfe71fca06c0eb657, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x3a, rs 0xfe71fca06c0eb657, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x64, rs 0xfe71fca06c0eb657, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xde, rs 0xfe71fca06c0eb657, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xd0, rs 0xfe71fca06c0eb657, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x8a, rs 0xfe71fca06c0eb657, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x31, rs 0xfe71fca06c0eb657, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xf9, rs 0xfe71fca06c0eb657, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xa2, rs 0xfe71fca06c0eb657, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x61, rs 0xfe71fca06c0eb657, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x43, rs 0xfe71fca06c0eb657, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0xfe71fca06c0eb657, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0xfe71fca06c0eb657, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xe8, rs 0xfe71fca06c0eb657, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x49, rs 0xfe71fca06c0eb657, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xc2, rs 0xfe71fca06c0eb657, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xb8, rs 0xfe71fca06c0eb657, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x94, rs 0xfe71fca06c0eb657, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x7d, rs 0xfe71fca06c0eb657, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xc2, rs 0xfe71fca06c0eb657, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x43, rs 0xfe71fca06c0eb657, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xa1, rs 0xfe71fca06c0eb657, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xc5, rs 0xfe71fca06c0eb657, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x4c, rs 0xfe71fca06c0eb657, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xa6, rs 0xfe71fca06c0eb657, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xf4, rs 0xfe71fca06c0eb657, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x20, rs 0xfe71fca06c0eb657, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xba, rs 0xfe71fca06c0eb657, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x4c, rs 0xfe71fca06c0eb657, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x4a, rs 0xfe71fca06c0eb657, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x34, rs 0xfe71fca06c0eb657, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x7e, rs 0xfe71fca06c0eb657, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xd6, rs 0xfe71fca06c0eb657, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x9, rs 0xfe71fca06c0eb657, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xae, rs 0xfe71fca06c0eb657, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xb2, rs 0xfe71fca06c0eb657, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xe0, rs 0xfe71fca06c0eb657, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xa9, rs 0xfe71fca06c0eb657, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x43, rs 0xfe71fca06c0eb657, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0xfe71fca06c0eb657, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x5d, rs 0xeed8f3518102315b, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xfb, rs 0xeed8f3518102315b, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xdb, rs 0xeed8f3518102315b, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0xeed8f3518102315b, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x20, rs 0xeed8f3518102315b, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xc1, rs 0xeed8f3518102315b, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x91, rs 0xeed8f3518102315b, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0xeed8f3518102315b, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x6f, rs 0xeed8f3518102315b, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x9b, rs 0xeed8f3518102315b, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0xeed8f3518102315b, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0xeed8f3518102315b, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x6, rs 0xeed8f3518102315b, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xaa, rs 0xeed8f3518102315b, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x95, rs 0xeed8f3518102315b, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x8, rs 0xeed8f3518102315b, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xf6, rs 0xeed8f3518102315b, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xab, rs 0xeed8f3518102315b, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x1b, rs 0xeed8f3518102315b, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x9f, rs 0xeed8f3518102315b, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x82, rs 0xeed8f3518102315b, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0xeed8f3518102315b, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x32, rs 0xeed8f3518102315b, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x80, rs 0xeed8f3518102315b, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x3e, rs 0xeed8f3518102315b, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x68, rs 0xeed8f3518102315b, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xe2, rs 0xeed8f3518102315b, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xd4, rs 0xeed8f3518102315b, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x8e, rs 0xeed8f3518102315b, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x35, rs 0xeed8f3518102315b, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xfd, rs 0xeed8f3518102315b, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xa6, rs 0xeed8f3518102315b, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x65, rs 0xeed8f3518102315b, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0xeed8f3518102315b, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xe5, rs 0xeed8f3518102315b, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x91, rs 0xeed8f3518102315b, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xec, rs 0xeed8f3518102315b, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0xeed8f3518102315b, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xc6, rs 0xeed8f3518102315b, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xbc, rs 0xeed8f3518102315b, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x98, rs 0xeed8f3518102315b, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x81, rs 0xeed8f3518102315b, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xc6, rs 0xeed8f3518102315b, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0xeed8f3518102315b, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xa5, rs 0xeed8f3518102315b, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0xeed8f3518102315b, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x50, rs 0xeed8f3518102315b, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xaa, rs 0xeed8f3518102315b, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xf8, rs 0xeed8f3518102315b, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x24, rs 0xeed8f3518102315b, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xbe, rs 0xeed8f3518102315b, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x50, rs 0xeed8f3518102315b, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x4e, rs 0xeed8f3518102315b, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x38, rs 0xeed8f3518102315b, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x82, rs 0xeed8f3518102315b, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xda, rs 0xeed8f3518102315b, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0xd, rs 0xeed8f3518102315b, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xb2, rs 0xeed8f3518102315b, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0xeed8f3518102315b, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xe4, rs 0xeed8f3518102315b, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xad, rs 0xeed8f3518102315b, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0xeed8f3518102315b, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xc1, rs 0xeed8f3518102315b, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x8b, rs 0x34fdfc9a9302be89, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0x34fdfc9a9302be89, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x9, rs 0x34fdfc9a9302be89, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x20, rs 0x34fdfc9a9302be89, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x4e, rs 0x34fdfc9a9302be89, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xef, rs 0x34fdfc9a9302be89, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0xbf, rs 0x34fdfc9a9302be89, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x30, rs 0x34fdfc9a9302be89, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x9d, rs 0x34fdfc9a9302be89, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0x34fdfc9a9302be89, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xe3, rs 0x34fdfc9a9302be89, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x41, rs 0x34fdfc9a9302be89, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x34, rs 0x34fdfc9a9302be89, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0x34fdfc9a9302be89, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xc3, rs 0x34fdfc9a9302be89, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x36, rs 0x34fdfc9a9302be89, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x24, rs 0x34fdfc9a9302be89, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0x34fdfc9a9302be89, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x49, rs 0x34fdfc9a9302be89, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xcd, rs 0x34fdfc9a9302be89, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0xb0, rs 0x34fdfc9a9302be89, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x18, rs 0x34fdfc9a9302be89, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x60, rs 0x34fdfc9a9302be89, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0xae, rs 0x34fdfc9a9302be89, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0x34fdfc9a9302be89, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x96, rs 0x34fdfc9a9302be89, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x10, rs 0x34fdfc9a9302be89, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x2, rs 0x34fdfc9a9302be89, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0xbc, rs 0x34fdfc9a9302be89, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x63, rs 0x34fdfc9a9302be89, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0x34fdfc9a9302be89, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xd4, rs 0x34fdfc9a9302be89, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0x34fdfc9a9302be89, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0x34fdfc9a9302be89, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0x34fdfc9a9302be89, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0xbf, rs 0x34fdfc9a9302be89, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x1a, rs 0x34fdfc9a9302be89, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x7b, rs 0x34fdfc9a9302be89, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xf4, rs 0x34fdfc9a9302be89, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xea, rs 0x34fdfc9a9302be89, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xc6, rs 0x34fdfc9a9302be89, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0xaf, rs 0x34fdfc9a9302be89, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xf4, rs 0x34fdfc9a9302be89, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0x34fdfc9a9302be89, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xd3, rs 0x34fdfc9a9302be89, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0x34fdfc9a9302be89, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x7e, rs 0x34fdfc9a9302be89, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0x34fdfc9a9302be89, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0x34fdfc9a9302be89, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0x34fdfc9a9302be89, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xec, rs 0x34fdfc9a9302be89, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x7e, rs 0x34fdfc9a9302be89, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x7c, rs 0x34fdfc9a9302be89, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x66, rs 0x34fdfc9a9302be89, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0xb0, rs 0x34fdfc9a9302be89, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x8, rs 0x34fdfc9a9302be89, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x3b, rs 0x34fdfc9a9302be89, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xe0, rs 0x34fdfc9a9302be89, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xe4, rs 0x34fdfc9a9302be89, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x12, rs 0x34fdfc9a9302be89, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xdb, rs 0x34fdfc9a9302be89, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0x34fdfc9a9302be89, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xef, rs 0x34fdfc9a9302be89, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x54, rs 0xc49ee3ad81b5af52, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0xf2, rs 0xc49ee3ad81b5af52, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xd2, rs 0xc49ee3ad81b5af52, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xe9, rs 0xc49ee3ad81b5af52, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x17, rs 0xc49ee3ad81b5af52, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xb8, rs 0xc49ee3ad81b5af52, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x88, rs 0xc49ee3ad81b5af52, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xf9, rs 0xc49ee3ad81b5af52, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x66, rs 0xc49ee3ad81b5af52, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x92, rs 0xc49ee3ad81b5af52, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xac, rs 0xc49ee3ad81b5af52, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xa, rs 0xc49ee3ad81b5af52, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0xfd, rs 0xc49ee3ad81b5af52, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xa1, rs 0xc49ee3ad81b5af52, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0xc49ee3ad81b5af52, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0xff, rs 0xc49ee3ad81b5af52, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0xed, rs 0xc49ee3ad81b5af52, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xa2, rs 0xc49ee3ad81b5af52, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x12, rs 0xc49ee3ad81b5af52, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x96, rs 0xc49ee3ad81b5af52, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x79, rs 0xc49ee3ad81b5af52, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0xc49ee3ad81b5af52, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0xc49ee3ad81b5af52, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x77, rs 0xc49ee3ad81b5af52, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x35, rs 0xc49ee3ad81b5af52, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x5f, rs 0xc49ee3ad81b5af52, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xd9, rs 0xc49ee3ad81b5af52, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xcb, rs 0xc49ee3ad81b5af52, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x85, rs 0xc49ee3ad81b5af52, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x2c, rs 0xc49ee3ad81b5af52, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0xf4, rs 0xc49ee3ad81b5af52, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x9d, rs 0xc49ee3ad81b5af52, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x5c, rs 0xc49ee3ad81b5af52, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x3e, rs 0xc49ee3ad81b5af52, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xdc, rs 0xc49ee3ad81b5af52, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x88, rs 0xc49ee3ad81b5af52, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xe3, rs 0xc49ee3ad81b5af52, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x44, rs 0xc49ee3ad81b5af52, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0xc49ee3ad81b5af52, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xb3, rs 0xc49ee3ad81b5af52, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x8f, rs 0xc49ee3ad81b5af52, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x78, rs 0xc49ee3ad81b5af52, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0xc49ee3ad81b5af52, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x3e, rs 0xc49ee3ad81b5af52, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0xc49ee3ad81b5af52, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xc0, rs 0xc49ee3ad81b5af52, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0xc49ee3ad81b5af52, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xa1, rs 0xc49ee3ad81b5af52, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0xef, rs 0xc49ee3ad81b5af52, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x1b, rs 0xc49ee3ad81b5af52, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0xc49ee3ad81b5af52, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0xc49ee3ad81b5af52, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x45, rs 0xc49ee3ad81b5af52, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x2f, rs 0xc49ee3ad81b5af52, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x79, rs 0xc49ee3ad81b5af52, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0xc49ee3ad81b5af52, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x4, rs 0xc49ee3ad81b5af52, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xa9, rs 0xc49ee3ad81b5af52, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xad, rs 0xc49ee3ad81b5af52, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xdb, rs 0xc49ee3ad81b5af52, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xa4, rs 0xc49ee3ad81b5af52, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x3e, rs 0xc49ee3ad81b5af52, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xb8, rs 0xc49ee3ad81b5af52, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0xee, rs 0x9e02de4b678930ec, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0x9e02de4b678930ec, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0x6c, rs 0x9e02de4b678930ec, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0x83, rs 0x9e02de4b678930ec, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0x9e02de4b678930ec, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0x9e02de4b678930ec, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x22, rs 0x9e02de4b678930ec, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0x93, rs 0x9e02de4b678930ec, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x0, rs 0x9e02de4b678930ec, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0x2c, rs 0x9e02de4b678930ec, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0x46, rs 0x9e02de4b678930ec, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0xa4, rs 0x9e02de4b678930ec, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x97, rs 0x9e02de4b678930ec, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0x3b, rs 0x9e02de4b678930ec, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0x9e02de4b678930ec, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0x9e02de4b678930ec, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x87, rs 0x9e02de4b678930ec, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0x3c, rs 0x9e02de4b678930ec, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0xac, rs 0x9e02de4b678930ec, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0x30, rs 0x9e02de4b678930ec, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0x9e02de4b678930ec, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0x7b, rs 0x9e02de4b678930ec, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0xc3, rs 0x9e02de4b678930ec, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x11, rs 0x9e02de4b678930ec, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0xcf, rs 0x9e02de4b678930ec, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0xf9, rs 0x9e02de4b678930ec, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0x73, rs 0x9e02de4b678930ec, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0x65, rs 0x9e02de4b678930ec, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x1f, rs 0x9e02de4b678930ec, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0xc6, rs 0x9e02de4b678930ec, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x8e, rs 0x9e02de4b678930ec, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0x37, rs 0x9e02de4b678930ec, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0xf6, rs 0x9e02de4b678930ec, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0x9e02de4b678930ec, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0x76, rs 0x9e02de4b678930ec, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x22, rs 0x9e02de4b678930ec, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0x7d, rs 0x9e02de4b678930ec, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0xde, rs 0x9e02de4b678930ec, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0x57, rs 0x9e02de4b678930ec, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0x4d, rs 0x9e02de4b678930ec, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0x29, rs 0x9e02de4b678930ec, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x12, rs 0x9e02de4b678930ec, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0x57, rs 0x9e02de4b678930ec, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0x9e02de4b678930ec, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0x36, rs 0x9e02de4b678930ec, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0x5a, rs 0x9e02de4b678930ec, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x9e02de4b678930ec, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0x3b, rs 0x9e02de4b678930ec, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x89, rs 0x9e02de4b678930ec, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0x9e02de4b678930ec, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0x4f, rs 0x9e02de4b678930ec, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0xe1, rs 0x9e02de4b678930ec, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0xdf, rs 0x9e02de4b678930ec, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0x9e02de4b678930ec, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0x9e02de4b678930ec, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0x6b, rs 0x9e02de4b678930ec, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x9e, rs 0x9e02de4b678930ec, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0x43, rs 0x9e02de4b678930ec, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0x47, rs 0x9e02de4b678930ec, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0x75, rs 0x9e02de4b678930ec, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0x3e, rs 0x9e02de4b678930ec, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0xd8, rs 0x9e02de4b678930ec, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0x9e02de4b678930ec, rt 0x680cce5fb236b666
+baddu $t3, $t1, $t2 :: rd 0x68, rs 0x680cce5fb236b666, rt 0x42b0c0a28677b502
+baddu $t3, $t1, $t2 :: rd 0x6, rs 0x680cce5fb236b666, rt 0x9e705cc51ad8dca0
+baddu $t3, $t1, $t2 :: rd 0xe6, rs 0x680cce5fb236b666, rt 0x47f505569a08a180
+baddu $t3, $t1, $t2 :: rd 0xfd, rs 0x680cce5fb236b666, rt 0x94ff52fc81afa797
+baddu $t3, $t1, $t2 :: rd 0x2b, rs 0x680cce5fb236b666, rt 0x556b3ecaccf17ac5
+baddu $t3, $t1, $t2 :: rd 0xcc, rs 0x680cce5fb236b666, rt 0x3c2cd9a9cda20766
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0x680cce5fb236b666, rt 0xd0d070db710cd036
+baddu $t3, $t1, $t2 :: rd 0xd, rs 0x680cce5fb236b666, rt 0x2f39454412d6e4a7
+baddu $t3, $t1, $t2 :: rd 0x7a, rs 0x680cce5fb236b666, rt 0xed5005cbc8b0a214
+baddu $t3, $t1, $t2 :: rd 0xa6, rs 0x680cce5fb236b666, rt 0x87750a04ad765040
+baddu $t3, $t1, $t2 :: rd 0xc0, rs 0x680cce5fb236b666, rt 0xc4c770f630dcca5a
+baddu $t3, $t1, $t2 :: rd 0x1e, rs 0x680cce5fb236b666, rt 0xbb8c035e0de0f0b8
+baddu $t3, $t1, $t2 :: rd 0x11, rs 0x680cce5fb236b666, rt 0x49fbf6a795b1a5ab
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0x680cce5fb236b666, rt 0xd685884e76558c4f
+baddu $t3, $t1, $t2 :: rd 0xa0, rs 0x680cce5fb236b666, rt 0x58300f029cae393a
+baddu $t3, $t1, $t2 :: rd 0x13, rs 0x680cce5fb236b666, rt 0xde230867a630f6ad
+baddu $t3, $t1, $t2 :: rd 0x1, rs 0x680cce5fb236b666, rt 0x81daf8200468319b
+baddu $t3, $t1, $t2 :: rd 0xb6, rs 0x680cce5fb236b666, rt 0x6778fdf3ba52a850
+baddu $t3, $t1, $t2 :: rd 0x26, rs 0x680cce5fb236b666, rt 0xe4627f3fe5255fc0
+baddu $t3, $t1, $t2 :: rd 0xaa, rs 0x680cce5fb236b666, rt 0x7caf83d2880ff344
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0x680cce5fb236b666, rt 0x24296b75a76fa427
+baddu $t3, $t1, $t2 :: rd 0xf5, rs 0x680cce5fb236b666, rt 0x70dc3454bfe348f
+baddu $t3, $t1, $t2 :: rd 0x3d, rs 0x680cce5fb236b666, rt 0x3f63daa9afd199d7
+baddu $t3, $t1, $t2 :: rd 0x8b, rs 0x680cce5fb236b666, rt 0xe54750d5d9257f25
+baddu $t3, $t1, $t2 :: rd 0x49, rs 0x680cce5fb236b666, rt 0x3ce839a51cf929e3
+baddu $t3, $t1, $t2 :: rd 0x73, rs 0x680cce5fb236b666, rt 0x84785280dd301d0d
+baddu $t3, $t1, $t2 :: rd 0xed, rs 0x680cce5fb236b666, rt 0x663d061055833287
+baddu $t3, $t1, $t2 :: rd 0xdf, rs 0x680cce5fb236b666, rt 0x9ca4bdbd32be479
+baddu $t3, $t1, $t2 :: rd 0x99, rs 0x680cce5fb236b666, rt 0x36a6f7fa3c0c9f33
+baddu $t3, $t1, $t2 :: rd 0x40, rs 0x680cce5fb236b666, rt 0xa8b08fe67a8bc7da
+baddu $t3, $t1, $t2 :: rd 0x8, rs 0x680cce5fb236b666, rt 0xb665ed5e7f89e9a2
+baddu $t3, $t1, $t2 :: rd 0xb1, rs 0x680cce5fb236b666, rt 0x420b34f533734a4b
+baddu $t3, $t1, $t2 :: rd 0x70, rs 0x680cce5fb236b666, rt 0xeaded5c53dad020a
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0x680cce5fb236b666, rt 0x2299b0e01d5e68ec
+baddu $t3, $t1, $t2 :: rd 0xf0, rs 0x680cce5fb236b666, rt 0xe5e9a314be7fa08a
+baddu $t3, $t1, $t2 :: rd 0x9c, rs 0x680cce5fb236b666, rt 0x4aeb6ca0e3459e36
+baddu $t3, $t1, $t2 :: rd 0xf7, rs 0x680cce5fb236b666, rt 0x993138f16cfde991
+baddu $t3, $t1, $t2 :: rd 0x58, rs 0x680cce5fb236b666, rt 0x8cff404aede292f2
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0x680cce5fb236b666, rt 0x42e9f8548b739b6b
+baddu $t3, $t1, $t2 :: rd 0xc7, rs 0x680cce5fb236b666, rt 0x276af70a0e128561
+baddu $t3, $t1, $t2 :: rd 0xa3, rs 0x680cce5fb236b666, rt 0x1f9720f946923c3d
+baddu $t3, $t1, $t2 :: rd 0x8c, rs 0x680cce5fb236b666, rt 0xc7a59be7800f3d26
+baddu $t3, $t1, $t2 :: rd 0xd1, rs 0x680cce5fb236b666, rt 0x743e568d2fcf486b
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0x680cce5fb236b666, rt 0xdfb254da422346ec
+baddu $t3, $t1, $t2 :: rd 0xb0, rs 0x680cce5fb236b666, rt 0x3c07af97fba6704a
+baddu $t3, $t1, $t2 :: rd 0xd4, rs 0x680cce5fb236b666, rt 0xd5b2120c6f52416e
+baddu $t3, $t1, $t2 :: rd 0x5b, rs 0x680cce5fb236b666, rt 0xa388c16272f1f8f5
+baddu $t3, $t1, $t2 :: rd 0xb5, rs 0x680cce5fb236b666, rt 0xb42ad6e659a7b04f
+baddu $t3, $t1, $t2 :: rd 0x3, rs 0x680cce5fb236b666, rt 0x53606bb4bf0c999d
+baddu $t3, $t1, $t2 :: rd 0x2f, rs 0x680cce5fb236b666, rt 0x15ebf6121dca77c9
+baddu $t3, $t1, $t2 :: rd 0xc9, rs 0x680cce5fb236b666, rt 0x14abf36419fb9e63
+baddu $t3, $t1, $t2 :: rd 0x5b, rs 0x680cce5fb236b666, rt 0x7e35ce6d56e670f5
+baddu $t3, $t1, $t2 :: rd 0x59, rs 0x680cce5fb236b666, rt 0xf2e7a490978058f3
+baddu $t3, $t1, $t2 :: rd 0x43, rs 0x680cce5fb236b666, rt 0xa3d991b79941dedd
+baddu $t3, $t1, $t2 :: rd 0x8d, rs 0x680cce5fb236b666, rt 0x185b88e0db8d7d27
+baddu $t3, $t1, $t2 :: rd 0xe5, rs 0x680cce5fb236b666, rt 0xd58ecbabde35697f
+baddu $t3, $t1, $t2 :: rd 0x18, rs 0x680cce5fb236b666, rt 0x2f7e224a1c170ab2
+baddu $t3, $t1, $t2 :: rd 0xbd, rs 0x680cce5fb236b666, rt 0xfe71fca06c0eb657
+baddu $t3, $t1, $t2 :: rd 0xc1, rs 0x680cce5fb236b666, rt 0xeed8f3518102315b
+baddu $t3, $t1, $t2 :: rd 0xef, rs 0x680cce5fb236b666, rt 0x34fdfc9a9302be89
+baddu $t3, $t1, $t2 :: rd 0xb8, rs 0x680cce5fb236b666, rt 0xc49ee3ad81b5af52
+baddu $t3, $t1, $t2 :: rd 0x52, rs 0x680cce5fb236b666, rt 0x9e02de4b678930ec
+baddu $t3, $t1, $t2 :: rd 0xcc, rs 0x680cce5fb236b666, rt 0x680cce5fb236b666
+pop $t3, $t1 :: rd 0xf, rs 0x42b0c0a28677b502, rt 0x0
+pop $t3, $t1 :: rd 0xe, rs 0x9e705cc51ad8dca0, rt 0x0
+pop $t3, $t1 :: rd 0x9, rs 0x47f505569a08a180, rt 0x0
+pop $t3, $t1 :: rd 0x12, rs 0x94ff52fc81afa797, rt 0x0
+pop $t3, $t1 :: rd 0x12, rs 0x556b3ecaccf17ac5, rt 0x0
+pop $t3, $t1 :: rd 0xf, rs 0x3c2cd9a9cda20766, rt 0x0
+pop $t3, $t1 :: rd 0xd, rs 0xd0d070db710cd036, rt 0x0
+pop $t3, $t1 :: rd 0x10, rs 0x2f39454412d6e4a7, rt 0x0
+pop $t3, $t1 :: rd 0xb, rs 0xed5005cbc8b0a214, rt 0x0
+pop $t3, $t1 :: rd 0xd, rs 0x87750a04ad765040, rt 0x0
+pop $t3, $t1 :: rd 0xf, rs 0xc4c770f630dcca5a, rt 0x0
+pop $t3, $t1 :: rd 0xe, rs 0xbb8c035e0de0f0b8, rt 0x0
+pop $t3, $t1 :: rd 0x11, rs 0x49fbf6a795b1a5ab, rt 0x0
+pop $t3, $t1 :: rd 0x11, rs 0xd685884e76558c4f, rt 0x0
+pop $t3, $t1 :: rd 0x11, rs 0x58300f029cae393a, rt 0x0
+pop $t3, $t1 :: rd 0x11, rs 0xde230867a630f6ad, rt 0x0
+pop $t3, $t1 :: rd 0xc, rs 0x81daf8200468319b, rt 0x0
+pop $t3, $t1 :: rd 0xd, rs 0x6778fdf3ba52a850, rt 0x0
+pop $t3, $t1 :: rd 0x10, rs 0xe4627f3fe5255fc0, rt 0x0
+pop $t3, $t1 :: rd 0xe, rs 0x7caf83d2880ff344, rt 0x0
+pop $t3, $t1 :: rd 0x12, rs 0x24296b75a76fa427, rt 0x0
+pop $t3, $t1 :: rd 0x13, rs 0x70dc3454bfe348f, rt 0x0
+pop $t3, $t1 :: rd 0x14, rs 0x3f63daa9afd199d7, rt 0x0
+pop $t3, $t1 :: rd 0x12, rs 0xe54750d5d9257f25, rt 0x0
+pop $t3, $t1 :: rd 0x11, rs 0x3ce839a51cf929e3, rt 0x0
+pop $t3, $t1 :: rd 0xf, rs 0x84785280dd301d0d, rt 0x0
+pop $t3, $t1 :: rd 0xe, rs 0x663d061055833287, rt 0x0
+pop $t3, $t1 :: rd 0x12, rs 0x9ca4bdbd32be479, rt 0x0
+pop $t3, $t1 :: rd 0x10, rs 0x36a6f7fa3c0c9f33, rt 0x0
+pop $t3, $t1 :: rd 0x13, rs 0xa8b08fe67a8bc7da, rt 0x0
+pop $t3, $t1 :: rd 0x12, rs 0xb665ed5e7f89e9a2, rt 0x0
+pop $t3, $t1 :: rd 0x10, rs 0x420b34f533734a4b, rt 0x0
+pop $t3, $t1 :: rd 0xd, rs 0xeaded5c53dad020a, rt 0x0
+pop $t3, $t1 :: rd 0x11, rs 0x2299b0e01d5e68ec, rt 0x0
+pop $t3, $t1 :: rd 0x12, rs 0xe5e9a314be7fa08a, rt 0x0
+pop $t3, $t1 :: rd 0x11, rs 0x4aeb6ca0e3459e36, rt 0x0
+pop $t3, $t1 :: rd 0x13, rs 0x993138f16cfde991, rt 0x0
+pop $t3, $t1 :: rd 0x12, rs 0x8cff404aede292f2, rt 0x0
+pop $t3, $t1 :: rd 0x13, rs 0x42e9f8548b739b6b, rt 0x0
+pop $t3, $t1 :: rd 0xb, rs 0x276af70a0e128561, rt 0x0
+pop $t3, $t1 :: rd 0xf, rs 0x1f9720f946923c3d, rt 0x0
+pop $t3, $t1 :: rd 0xd, rs 0xc7a59be7800f3d26, rt 0x0
+pop $t3, $t1 :: rd 0x12, rs 0x743e568d2fcf486b, rt 0x0
+pop $t3, $t1 :: rd 0xd, rs 0xdfb254da422346ec, rt 0x0
+pop $t3, $t1 :: rd 0x11, rs 0x3c07af97fba6704a, rt 0x0
+pop $t3, $t1 :: rd 0x10, rs 0xd5b2120c6f52416e, rt 0x0
+pop $t3, $t1 :: rd 0x14, rs 0xa388c16272f1f8f5, rt 0x0
+pop $t3, $t1 :: rd 0x11, rs 0xb42ad6e659a7b04f, rt 0x0
+pop $t3, $t1 :: rd 0x12, rs 0x53606bb4bf0c999d, rt 0x0
+pop $t3, $t1 :: rd 0x12, rs 0x15ebf6121dca77c9, rt 0x0
+pop $t3, $t1 :: rd 0x13, rs 0x14abf36419fb9e63, rt 0x0
+pop $t3, $t1 :: rd 0x12, rs 0x7e35ce6d56e670f5, rt 0x0
+pop $t3, $t1 :: rd 0xf, rs 0xf2e7a490978058f3, rt 0x0
+pop $t3, $t1 :: rd 0x12, rs 0xa3d991b79941dedd, rt 0x0
+pop $t3, $t1 :: rd 0x14, rs 0x185b88e0db8d7d27, rt 0x0
+pop $t3, $t1 :: rd 0x15, rs 0xd58ecbabde35697f, rt 0x0
+pop $t3, $t1 :: rd 0xd, rs 0x2f7e224a1c170ab2, rt 0x0
+pop $t3, $t1 :: rd 0x11, rs 0xfe71fca06c0eb657, rt 0x0
+pop $t3, $t1 :: rd 0xb, rs 0xeed8f3518102315b, rt 0x0
+pop $t3, $t1 :: rd 0xe, rs 0x34fdfc9a9302be89, rt 0x0
+pop $t3, $t1 :: rd 0x10, rs 0xc49ee3ad81b5af52, rt 0x0
+pop $t3, $t1 :: rd 0xf, rs 0x9e02de4b678930ec, rt 0x0
+pop $t3, $t1 :: rd 0x11, rs 0x680cce5fb236b666, rt 0x0
+dpop $t3, $t1 :: rd 0x1e, rs 0x9e705cc51ad8dca0, rt 0x0
+dpop $t3, $t1 :: rd 0x26, rs 0x94ff52fc81afa797, rt 0x0
+dpop $t3, $t1 :: rd 0x1f, rs 0x3c2cd9a9cda20766, rt 0x0
+dpop $t3, $t1 :: rd 0x1e, rs 0x2f39454412d6e4a7, rt 0x0
+dpop $t3, $t1 :: rd 0x19, rs 0x87750a04ad765040, rt 0x0
+dpop $t3, $t1 :: rd 0x1e, rs 0xbb8c035e0de0f0b8, rt 0x0
+dpop $t3, $t1 :: rd 0x1f, rs 0xd685884e76558c4f, rt 0x0
+dpop $t3, $t1 :: rd 0x20, rs 0xde230867a630f6ad, rt 0x0
+dpop $t3, $t1 :: rd 0x23, rs 0x6778fdf3ba52a850, rt 0x0
+dpop $t3, $t1 :: rd 0x20, rs 0x7caf83d2880ff344, rt 0x0
+dpop $t3, $t1 :: rd 0x20, rs 0x70dc3454bfe348f, rt 0x0
+dpop $t3, $t1 :: rd 0x22, rs 0xe54750d5d9257f25, rt 0x0
+dpop $t3, $t1 :: rd 0x19, rs 0x84785280dd301d0d, rt 0x0
+dpop $t3, $t1 :: rd 0x22, rs 0x9ca4bdbd32be479, rt 0x0
+dpop $t3, $t1 :: rd 0x23, rs 0xa8b08fe67a8bc7da, rt 0x0
+dpop $t3, $t1 :: rd 0x1e, rs 0x420b34f533734a4b, rt 0x0
+dpop $t3, $t1 :: rd 0x1d, rs 0x2299b0e01d5e68ec, rt 0x0
+dpop $t3, $t1 :: rd 0x20, rs 0x4aeb6ca0e3459e36, rt 0x0
+dpop $t3, $t1 :: rd 0x21, rs 0x8cff404aede292f2, rt 0x0
+dpop $t3, $t1 :: rd 0x1c, rs 0x276af70a0e128561, rt 0x0
+dpop $t3, $t1 :: rd 0x21, rs 0xc7a59be7800f3d26, rt 0x0
+dpop $t3, $t1 :: rd 0x20, rs 0xdfb254da422346ec, rt 0x0
+dpop $t3, $t1 :: rd 0x1d, rs 0xd5b2120c6f52416e, rt 0x0
+dpop $t3, $t1 :: rd 0x22, rs 0xb42ad6e659a7b04f, rt 0x0
+dpop $t3, $t1 :: rd 0x23, rs 0x15ebf6121dca77c9, rt 0x0
+dpop $t3, $t1 :: rd 0x26, rs 0x7e35ce6d56e670f5, rt 0x0
+dpop $t3, $t1 :: rd 0x24, rs 0xa3d991b79941dedd, rt 0x0
+dpop $t3, $t1 :: rd 0x28, rs 0xd58ecbabde35697f, rt 0x0
+dpop $t3, $t1 :: rd 0x24, rs 0xfe71fca06c0eb657, rt 0x0
+dpop $t3, $t1 :: rd 0x22, rs 0x34fdfc9a9302be89, rt 0x0
+dpop $t3, $t1 :: rd 0x1f, rs 0x9e02de4b678930ec, rt 0x0
+saa :: value: 0x42b0c0a28677b502, memPre: 0x12bd6aa007e8763, mem: 0x87a38bac007e8763
+saa :: value: 0x9e705cc51ad8dca0, memPre: 0x7e876382d2ab13, mem: 0x1b57640382d2ab13
+saa :: value: 0x47f505569a08a180, memPre: 0x82d2ab13976d6e9a, mem: 0x1cdb4c93976d6e9a
+saa :: value: 0x94ff52fc81afa797, memPre: 0x976d6e9ac31510f3, mem: 0x191d1631c31510f3
+saa :: value: 0x556b3ecaccf17ac5, memPre: 0xc31510f3b7746d77, mem: 0x90068bb8b7746d77
+saa :: value: 0x3c2cd9a9cda20766, memPre: 0xb7746d775ad6a5fb, mem: 0x851674dd5ad6a5fb
+saa :: value: 0xd0d070db710cd036, memPre: 0x5ad6a5fb42b0c0a2, mem: 0xcbe3763142b0c0a2
+saa :: value: 0x2f39454412d6e4a7, memPre: 0x42b0c0a28677b502, mem: 0x5587a5498677b502
+saa :: value: 0xed5005cbc8b0a214, memPre: 0x8677b5022aa89d31, mem: 0x4f2857162aa89d31
+saa :: value: 0x87750a04ad765040, memPre: 0x2aa89d319e3c30ad, mem: 0xd81eed719e3c30ad
+saa :: value: 0xc4c770f630dcca5a, memPre: 0x9e3c30ad1f308ec3, mem: 0xcf18fb071f308ec3
+saa :: value: 0xbb8c035e0de0f0b8, memPre: 0x1f308ec377fb413d, mem: 0x2d117f7b77fb413d
+saa :: value: 0x49fbf6a795b1a5ab, memPre: 0x77fb413d7aa04213, mem: 0xdace6e87aa04213
+saa :: value: 0xd685884e76558c4f, memPre: 0x7aa04213c760e4f7, mem: 0xf0f5ce62c760e4f7
+saa :: value: 0x58300f029cae393a, memPre: 0xc760e4f79e705cc5, mem: 0x640f1e319e705cc5
+saa :: value: 0xde230867a630f6ad, memPre: 0x9e705cc51ad8dca0, mem: 0x44a153721ad8dca0
+saa :: value: 0x81daf8200468319b, memPre: 0x1ad8dca04b3dda86, mem: 0x1f410e3b4b3dda86
+saa :: value: 0x6778fdf3ba52a850, memPre: 0x4b3dda869615a60d, mem: 0x59082d69615a60d
+saa :: value: 0xe4627f3fe5255fc0, memPre: 0x9615a60d05e7a4dd, mem: 0x7b3b05cd05e7a4dd
+saa :: value: 0x7caf83d2880ff344, memPre: 0x5e7a4dd6353d41d, mem: 0x8df798216353d41d
+saa :: value: 0x24296b75a76fa427, memPre: 0x6353d41d3af35a9d, mem: 0xac378443af35a9d
+saa :: value: 0x70dc3454bfe348f, memPre: 0x3af35a9dc40bd413, mem: 0x86f18f2cc40bd413
+saa :: value: 0x3f63daa9afd199d7, memPre: 0xc40bd41347f50556, mem: 0x73dd6dea47f50556
+saa :: value: 0xe54750d5d9257f25, memPre: 0x47f505569a08a180, mem: 0x211a847b9a08a180
+saa :: value: 0x3ce839a51cf929e3, memPre: 0x9a08a1809564b77f, mem: 0xb701cb639564b77f
+saa :: value: 0x84785280dd301d0d, memPre: 0x9564b77fd6d2040f, mem: 0x7294d48cd6d2040f
+saa :: value: 0x663d061055833287, memPre: 0xd6d2040fcebc8279, mem: 0x2c553696cebc8279
+saa :: value: 0x9ca4bdbd32be479, memPre: 0xcebc8279b2c76bbe, mem: 0xa1e866f2b2c76bbe
+saa :: value: 0x36a6f7fa3c0c9f33, memPre: 0xb2c76bbeb5034c2f, mem: 0xeed40af1b5034c2f
+saa :: value: 0xa8b08fe67a8bc7da, memPre: 0xb5034c2f1f18e4c7, mem: 0x2f8f14091f18e4c7
+saa :: value: 0xb665ed5e7f89e9a2, memPre: 0x1f18e4c794ff52fc, mem: 0x9ea2ce6994ff52fc
+saa :: value: 0x420b34f533734a4b, memPre: 0x94ff52fc81afa797, mem: 0xc8729d4781afa797
+saa :: value: 0xeaded5c53dad020a, memPre: 0x81afa79731d8d916, mem: 0xbf5ca9a131d8d916
+saa :: value: 0x2299b0e01d5e68ec, memPre: 0x31d8d9166dfc50ea, mem: 0x4f3742026dfc50ea
+saa :: value: 0xe5e9a314be7fa08a, memPre: 0x6dfc50ea36549bd6, mem: 0x2c7bf17436549bd6
+saa :: value: 0x4aeb6ca0e3459e36, memPre: 0x36549bd678e895b1, mem: 0x199a3a0c78e895b1
+saa :: value: 0x993138f16cfde991, memPre: 0x78e895b185e0a631, mem: 0xe5e67f4285e0a631
+saa :: value: 0x8cff404aede292f2, memPre: 0x85e0a6319b63259b, mem: 0x73c339239b63259b
+saa :: value: 0x42e9f8548b739b6b, memPre: 0x9b63259b556b3eca, mem: 0x26d6c106556b3eca
+saa :: value: 0x276af70a0e128561, memPre: 0x556b3ecaccf17ac5, mem: 0x637dc42bccf17ac5
+saa :: value: 0x1f9720f946923c3d, memPre: 0xccf17ac5b42f5fc5, mem: 0x1383b702b42f5fc5
+saa :: value: 0xc7a59be7800f3d26, memPre: 0xb42f5fc581eea0fb, mem: 0x343e9ceb81eea0fb
+saa :: value: 0x743e568d2fcf486b, memPre: 0x81eea0fb25b50fec, mem: 0xb1bde96625b50fec
+saa :: value: 0xdfb254da422346ec, memPre: 0x25b50fec14682d97, mem: 0x67d856d814682d97
+saa :: value: 0x3c07af97fba6704a, memPre: 0x14682d97fc93c513, mem: 0x100e9de1fc93c513
+saa :: value: 0xd5b2120c6f52416e, memPre: 0xfc93c5132cfb087a, mem: 0x6be606812cfb087a
+saa :: value: 0xa388c16272f1f8f5, memPre: 0x2cfb087a3c2cd9a9, mem: 0x9fed016f3c2cd9a9
+saa :: value: 0xb42ad6e659a7b04f, memPre: 0x3c2cd9a9cda20766, mem: 0x95d489f8cda20766
+saa :: value: 0x53606bb4bf0c999d, memPre: 0xcda207661791722a, mem: 0x8caea1031791722a
+saa :: value: 0x15ebf6121dca77c9, memPre: 0x1791722a7d72da3e, mem: 0x355be9f37d72da3e
+saa :: value: 0x14abf36419fb9e63, memPre: 0x7d72da3e087cc9d1, mem: 0x976e78a1087cc9d1
+saa :: value: 0x7e35ce6d56e670f5, memPre: 0x87cc9d193ce24ad, mem: 0x5f633ac693ce24ad
+saa :: value: 0xf2e7a490978058f3, memPre: 0x93ce24ad1d2a7570, mem: 0x2b4e7da01d2a7570
+saa :: value: 0xa3d991b79941dedd, memPre: 0x1d2a757038984ed2, mem: 0xb66c544d38984ed2
+saa :: value: 0x185b88e0db8d7d27, memPre: 0x38984ed2d0d070db, mem: 0x1425cbf9d0d070db
+saa :: value: 0xd58ecbabde35697f, memPre: 0xd0d070db710cd036, mem: 0xaf05da5a710cd036
+saa :: value: 0x2f7e224a1c170ab2, memPre: 0x710cd03639c21c7d, mem: 0x8d23dae839c21c7d
+saa :: value: 0xfe71fca06c0eb657, memPre: 0x39c21c7d03415604, mem: 0xa5d0d2d403415604
+saa :: value: 0xeed8f3518102315b, memPre: 0x34156048e94b7af, mem: 0x8443875f8e94b7af
+saa :: value: 0x34fdfc9a9302be89, memPre: 0x8e94b7af8ecc31ce, mem: 0x219776388ecc31ce
+saa :: value: 0xc49ee3ad81b5af52, memPre: 0x8ecc31ce24eb6a8d, mem: 0x1081e12024eb6a8d
+saa :: value: 0x9e02de4b678930ec, memPre: 0x24eb6a8d1ce7674f, mem: 0x8c749b791ce7674f
+saa :: value: 0x680cce5fb236b666, memPre: 0x1ce7674f2f394544, mem: 0xcf1e1db52f394544
+saad :: value: 0x9e705cc51ad8dca0, memPre: 0x7e876382d2ab13, mem: 0x9eeee4289dab87b3
+saad :: value: 0x94ff52fc81afa797, memPre: 0x976d6e9ac31510f3, mem: 0x2c6cc19744c4b88a
+saad :: value: 0x3c2cd9a9cda20766, memPre: 0xb7746d775ad6a5fb, mem: 0xf3a147212878ad61
+saad :: value: 0x2f39454412d6e4a7, memPre: 0x42b0c0a28677b502, mem: 0x71ea05e6994e99a9
+saad :: value: 0x87750a04ad765040, memPre: 0x2aa89d319e3c30ad, mem: 0xb21da7364bb280ed
+saad :: value: 0xbb8c035e0de0f0b8, memPre: 0x1f308ec377fb413d, mem: 0xdabc922185dc31f5
+saad :: value: 0xd685884e76558c4f, memPre: 0x7aa04213c760e4f7, mem: 0x5125ca623db67146
+saad :: value: 0xde230867a630f6ad, memPre: 0x9e705cc51ad8dca0, mem: 0x7c93652cc109d34d
+saad :: value: 0x6778fdf3ba52a850, memPre: 0x4b3dda869615a60d, mem: 0xb2b6d87a50684e5d
+saad :: value: 0x7caf83d2880ff344, memPre: 0x5e7a4dd6353d41d, mem: 0x829728afeb63c761
+saad :: value: 0x70dc3454bfe348f, memPre: 0x3af35a9dc40bd413, mem: 0x42011de3100a08a2
+saad :: value: 0xe54750d5d9257f25, memPre: 0x47f505569a08a180, mem: 0x2d3c562c732e20a5
+saad :: value: 0x84785280dd301d0d, memPre: 0x9564b77fd6d2040f, mem: 0x19dd0a00b402211c
+saad :: value: 0x9ca4bdbd32be479, memPre: 0xcebc8279b2c76bbe, mem: 0xd886ce5585f35037
+saad :: value: 0xa8b08fe67a8bc7da, memPre: 0xb5034c2f1f18e4c7, mem: 0x5db3dc1599a4aca1
+saad :: value: 0x420b34f533734a4b, memPre: 0x94ff52fc81afa797, mem: 0xd70a87f1b522f1e2
+saad :: value: 0x2299b0e01d5e68ec, memPre: 0x31d8d9166dfc50ea, mem: 0x547289f68b5ab9d6
+saad :: value: 0x4aeb6ca0e3459e36, memPre: 0x36549bd678e895b1, mem: 0x814008775c2e33e7
+saad :: value: 0x8cff404aede292f2, memPre: 0x85e0a6319b63259b, mem: 0x12dfe67c8945b88d
+saad :: value: 0x276af70a0e128561, memPre: 0x556b3ecaccf17ac5, mem: 0x7cd635d4db040026
+saad :: value: 0xc7a59be7800f3d26, memPre: 0xb42f5fc581eea0fb, mem: 0x7bd4fbad01fdde21
+saad :: value: 0xdfb254da422346ec, memPre: 0x25b50fec14682d97, mem: 0x56764c6568b7483
+saad :: value: 0xd5b2120c6f52416e, memPre: 0xfc93c5132cfb087a, mem: 0xd245d71f9c4d49e8
+saad :: value: 0xb42ad6e659a7b04f, memPre: 0x3c2cd9a9cda20766, mem: 0xf057b0902749b7b5
+saad :: value: 0x15ebf6121dca77c9, memPre: 0x1791722a7d72da3e, mem: 0x2d7d683c9b3d5207
+saad :: value: 0x7e35ce6d56e670f5, memPre: 0x87cc9d193ce24ad, mem: 0x86b2983eeab495a2
+saad :: value: 0xa3d991b79941dedd, memPre: 0x1d2a757038984ed2, mem: 0xc1040727d1da2daf
+saad :: value: 0xd58ecbabde35697f, memPre: 0xd0d070db710cd036, mem: 0xa65f3c874f4239b5
+saad :: value: 0xfe71fca06c0eb657, memPre: 0x39c21c7d03415604, mem: 0x3834191d6f500c5b
+saad :: value: 0x34fdfc9a9302be89, memPre: 0x8e94b7af8ecc31ce, mem: 0xc392b44a21cef057
+saad :: value: 0x9e02de4b678930ec, memPre: 0x24eb6a8d1ce7674f, mem: 0xc2ee48d88470983b
+laa :: offset: 0x4, out: 0x12bd6aa, result:0x12bd6ae
+laa :: offset: 0x8, out: 0x7e8763, result:0x7e876b
+laa :: offset: 0xc, out: 0xffffffff82d2ab13, result:0xffffffff82d2ab1f
+laa :: offset: 0x10, out: 0xffffffff976d6e9a, result:0xffffffff976d6eaa
+laa :: offset: 0x14, out: 0xffffffffc31510f3, result:0xffffffffc3151107
+laa :: offset: 0x18, out: 0xffffffffb7746d77, result:0xffffffffb7746d8f
+laa :: offset: 0x1c, out: 0x5ad6a5fb, result:0x5ad6a617
+laa :: offset: 0x20, out: 0x42b0c0a2, result:0x42b0c0c2
+laa :: offset: 0x24, out: 0xffffffff8677b502, result:0xffffffff8677b526
+laa :: offset: 0x28, out: 0x2aa89d31, result:0x2aa89d59
+laa :: offset: 0x2c, out: 0xffffffff9e3c30ad, result:0xffffffff9e3c30d9
+laa :: offset: 0x30, out: 0x1f308ec3, result:0x1f308ef3
+laa :: offset: 0x34, out: 0x77fb413d, result:0x77fb4171
+laa :: offset: 0x38, out: 0x7aa04213, result:0x7aa0424b
+laa :: offset: 0x3c, out: 0xffffffffc760e4f7, result:0xffffffffc760e533
+laa :: offset: 0x40, out: 0xffffffff9e705cc5, result:0xffffffff9e705d05
+laa :: offset: 0x44, out: 0x1ad8dca0, result:0x1ad8dce4
+laa :: offset: 0x48, out: 0x4b3dda86, result:0x4b3ddace
+laa :: offset: 0x4c, out: 0xffffffff9615a60d, result:0xffffffff9615a659
+laa :: offset: 0x50, out: 0x5e7a4dd, result:0x5e7a52d
+laa :: offset: 0x54, out: 0x6353d41d, result:0x6353d471
+laa :: offset: 0x58, out: 0x3af35a9d, result:0x3af35af5
+laa :: offset: 0x5c, out: 0xffffffffc40bd413, result:0xffffffffc40bd46f
+laa :: offset: 0x60, out: 0x47f50556, result:0x47f505b6
+laa :: offset: 0x64, out: 0xffffffff9a08a180, result:0xffffffff9a08a1e4
+laa :: offset: 0x68, out: 0xffffffff9564b77f, result:0xffffffff9564b7e7
+laa :: offset: 0x6c, out: 0xffffffffd6d2040f, result:0xffffffffd6d2047b
+laa :: offset: 0x70, out: 0xffffffffcebc8279, result:0xffffffffcebc82e9
+laa :: offset: 0x74, out: 0xffffffffb2c76bbe, result:0xffffffffb2c76c32
+laa :: offset: 0x78, out: 0xffffffffb5034c2f, result:0xffffffffb5034ca7
+laa :: offset: 0x7c, out: 0x1f18e4c7, result:0x1f18e543
+laa :: offset: 0x80, out: 0xffffffff94ff52fc, result:0xffffffff94ff537c
+laa :: offset: 0x84, out: 0xffffffff81afa797, result:0xffffffff81afa81b
+laa :: offset: 0x88, out: 0x31d8d916, result:0x31d8d99e
+laa :: offset: 0x8c, out: 0x6dfc50ea, result:0x6dfc5176
+laa :: offset: 0x90, out: 0x36549bd6, result:0x36549c66
+laa :: offset: 0x94, out: 0x78e895b1, result:0x78e89645
+laa :: offset: 0x98, out: 0xffffffff85e0a631, result:0xffffffff85e0a6c9
+laa :: offset: 0x9c, out: 0xffffffff9b63259b, result:0xffffffff9b632637
+laa :: offset: 0xa0, out: 0x556b3eca, result:0x556b3f6a
+laa :: offset: 0xa4, out: 0xffffffffccf17ac5, result:0xffffffffccf17b69
+laa :: offset: 0xa8, out: 0xffffffffb42f5fc5, result:0xffffffffb42f606d
+laa :: offset: 0xac, out: 0xffffffff81eea0fb, result:0xffffffff81eea1a7
+laa :: offset: 0xb0, out: 0x25b50fec, result:0x25b5109c
+laa :: offset: 0xb4, out: 0x14682d97, result:0x14682e4b
+laa :: offset: 0xb8, out: 0xfffffffffc93c513, result:0xfffffffffc93c5cb
+laa :: offset: 0xbc, out: 0x2cfb087a, result:0x2cfb0936
+laa :: offset: 0xc0, out: 0x3c2cd9a9, result:0x3c2cda69
+laa :: offset: 0xc4, out: 0xffffffffcda20766, result:0xffffffffcda2082a
+laa :: offset: 0xc8, out: 0x1791722a, result:0x179172f2
+laa :: offset: 0xcc, out: 0x7d72da3e, result:0x7d72db0a
+laa :: offset: 0xd0, out: 0x87cc9d1, result:0x87ccaa1
+laa :: offset: 0xd4, out: 0xffffffff93ce24ad, result:0xffffffff93ce2581
+laa :: offset: 0xd8, out: 0x1d2a7570, result:0x1d2a7648
+laa :: offset: 0xdc, out: 0x38984ed2, result:0x38984fae
+laa :: offset: 0xe0, out: 0xffffffffd0d070db, result:0xffffffffd0d071bb
+laa :: offset: 0xe4, out: 0x710cd036, result:0x710cd11a
+laa :: offset: 0xe8, out: 0x39c21c7d, result:0x39c21d65
+laa :: offset: 0xec, out: 0x3415604, result:0x34156f0
+laa :: offset: 0xf0, out: 0xffffffff8e94b7af, result:0xffffffff8e94b89f
+laa :: offset: 0xf4, out: 0xffffffff8ecc31ce, result:0xffffffff8ecc32c2
+laa :: offset: 0xf8, out: 0x24eb6a8d, result:0x24eb6b85
+laa :: offset: 0xfc, out: 0x1ce7674f, result:0x1ce7684b
+laad :: offset: 0x8, out: 0x7e876382d2ab13, result: 0x7e876382d2ab1b
+laad :: offset: 0x10, out: 0x976d6e9ac31510f3, result: 0x976d6e9ac3151103
+laad :: offset: 0x18, out: 0xb7746d775ad6a5fb, result: 0xb7746d775ad6a613
+laad :: offset: 0x20, out: 0x42b0c0a28677b502, result: 0x42b0c0a28677b522
+laad :: offset: 0x28, out: 0x2aa89d319e3c30ad, result: 0x2aa89d319e3c30d5
+laad :: offset: 0x30, out: 0x1f308ec377fb413d, result: 0x1f308ec377fb416d
+laad :: offset: 0x38, out: 0x7aa04213c760e4f7, result: 0x7aa04213c760e52f
+laad :: offset: 0x40, out: 0x9e705cc51ad8dca0, result: 0x9e705cc51ad8dce0
+laad :: offset: 0x48, out: 0x4b3dda869615a60d, result: 0x4b3dda869615a655
+laad :: offset: 0x50, out: 0x5e7a4dd6353d41d, result: 0x5e7a4dd6353d46d
+laad :: offset: 0x58, out: 0x3af35a9dc40bd413, result: 0x3af35a9dc40bd46b
+laad :: offset: 0x60, out: 0x47f505569a08a180, result: 0x47f505569a08a1e0
+laad :: offset: 0x68, out: 0x9564b77fd6d2040f, result: 0x9564b77fd6d20477
+laad :: offset: 0x70, out: 0xcebc8279b2c76bbe, result: 0xcebc8279b2c76c2e
+laad :: offset: 0x78, out: 0xb5034c2f1f18e4c7, result: 0xb5034c2f1f18e53f
+laad :: offset: 0x80, out: 0x94ff52fc81afa797, result: 0x94ff52fc81afa817
+laad :: offset: 0x88, out: 0x31d8d9166dfc50ea, result: 0x31d8d9166dfc5172
+laad :: offset: 0x90, out: 0x36549bd678e895b1, result: 0x36549bd678e89641
+laad :: offset: 0x98, out: 0x85e0a6319b63259b, result: 0x85e0a6319b632633
+laad :: offset: 0xa0, out: 0x556b3ecaccf17ac5, result: 0x556b3ecaccf17b65
+laad :: offset: 0xa8, out: 0xb42f5fc581eea0fb, result: 0xb42f5fc581eea1a3
+laad :: offset: 0xb0, out: 0x25b50fec14682d97, result: 0x25b50fec14682e47
+laad :: offset: 0xb8, out: 0xfc93c5132cfb087a, result: 0xfc93c5132cfb0932
+laad :: offset: 0xc0, out: 0x3c2cd9a9cda20766, result: 0x3c2cd9a9cda20826
+laad :: offset: 0xc8, out: 0x1791722a7d72da3e, result: 0x1791722a7d72db06
+laad :: offset: 0xd0, out: 0x87cc9d193ce24ad, result: 0x87cc9d193ce257d
+laad :: offset: 0xd8, out: 0x1d2a757038984ed2, result: 0x1d2a757038984faa
+laad :: offset: 0xe0, out: 0xd0d070db710cd036, result: 0xd0d070db710cd116
+laad :: offset: 0xe8, out: 0x39c21c7d03415604, result: 0x39c21c7d034156ec
+laad :: offset: 0xf0, out: 0x8e94b7af8ecc31ce, result: 0x8e94b7af8ecc32be
+laad :: offset: 0xf8, out: 0x24eb6a8d1ce7674f, result: 0x24eb6a8d1ce76847
+law :: offset: 0x4, out: 0x12bd6aa, result:0x4
+law :: offset: 0x8, out: 0x7e8763, result:0x8
+law :: offset: 0xc, out: 0xffffffff82d2ab13, result:0xc
+law :: offset: 0x10, out: 0xffffffff976d6e9a, result:0x10
+law :: offset: 0x14, out: 0xffffffffc31510f3, result:0x14
+law :: offset: 0x18, out: 0xffffffffb7746d77, result:0x18
+law :: offset: 0x1c, out: 0x5ad6a5fb, result:0x1c
+law :: offset: 0x20, out: 0x42b0c0a2, result:0x20
+law :: offset: 0x24, out: 0xffffffff8677b502, result:0x24
+law :: offset: 0x28, out: 0x2aa89d31, result:0x28
+law :: offset: 0x2c, out: 0xffffffff9e3c30ad, result:0x2c
+law :: offset: 0x30, out: 0x1f308ec3, result:0x30
+law :: offset: 0x34, out: 0x77fb413d, result:0x34
+law :: offset: 0x38, out: 0x7aa04213, result:0x38
+law :: offset: 0x3c, out: 0xffffffffc760e4f7, result:0x3c
+law :: offset: 0x40, out: 0xffffffff9e705cc5, result:0x40
+law :: offset: 0x44, out: 0x1ad8dca0, result:0x44
+law :: offset: 0x48, out: 0x4b3dda86, result:0x48
+law :: offset: 0x4c, out: 0xffffffff9615a60d, result:0x4c
+law :: offset: 0x50, out: 0x5e7a4dd, result:0x50
+law :: offset: 0x54, out: 0x6353d41d, result:0x54
+law :: offset: 0x58, out: 0x3af35a9d, result:0x58
+law :: offset: 0x5c, out: 0xffffffffc40bd413, result:0x5c
+law :: offset: 0x60, out: 0x47f50556, result:0x60
+law :: offset: 0x64, out: 0xffffffff9a08a180, result:0x64
+law :: offset: 0x68, out: 0xffffffff9564b77f, result:0x68
+law :: offset: 0x6c, out: 0xffffffffd6d2040f, result:0x6c
+law :: offset: 0x70, out: 0xffffffffcebc8279, result:0x70
+law :: offset: 0x74, out: 0xffffffffb2c76bbe, result:0x74
+law :: offset: 0x78, out: 0xffffffffb5034c2f, result:0x78
+law :: offset: 0x7c, out: 0x1f18e4c7, result:0x7c
+law :: offset: 0x80, out: 0xffffffff94ff52fc, result:0x80
+law :: offset: 0x84, out: 0xffffffff81afa797, result:0x84
+law :: offset: 0x88, out: 0x31d8d916, result:0x88
+law :: offset: 0x8c, out: 0x6dfc50ea, result:0x8c
+law :: offset: 0x90, out: 0x36549bd6, result:0x90
+law :: offset: 0x94, out: 0x78e895b1, result:0x94
+law :: offset: 0x98, out: 0xffffffff85e0a631, result:0x98
+law :: offset: 0x9c, out: 0xffffffff9b63259b, result:0x9c
+law :: offset: 0xa0, out: 0x556b3eca, result:0xa0
+law :: offset: 0xa4, out: 0xffffffffccf17ac5, result:0xa4
+law :: offset: 0xa8, out: 0xffffffffb42f5fc5, result:0xa8
+law :: offset: 0xac, out: 0xffffffff81eea0fb, result:0xac
+law :: offset: 0xb0, out: 0x25b50fec, result:0xb0
+law :: offset: 0xb4, out: 0x14682d97, result:0xb4
+law :: offset: 0xb8, out: 0xfffffffffc93c513, result:0xb8
+law :: offset: 0xbc, out: 0x2cfb087a, result:0xbc
+law :: offset: 0xc0, out: 0x3c2cd9a9, result:0xc0
+law :: offset: 0xc4, out: 0xffffffffcda20766, result:0xc4
+law :: offset: 0xc8, out: 0x1791722a, result:0xc8
+law :: offset: 0xcc, out: 0x7d72da3e, result:0xcc
+law :: offset: 0xd0, out: 0x87cc9d1, result:0xd0
+law :: offset: 0xd4, out: 0xffffffff93ce24ad, result:0xd4
+law :: offset: 0xd8, out: 0x1d2a7570, result:0xd8
+law :: offset: 0xdc, out: 0x38984ed2, result:0xdc
+law :: offset: 0xe0, out: 0xffffffffd0d070db, result:0xe0
+law :: offset: 0xe4, out: 0x710cd036, result:0xe4
+law :: offset: 0xe8, out: 0x39c21c7d, result:0xe8
+law :: offset: 0xec, out: 0x3415604, result:0xec
+law :: offset: 0xf0, out: 0xffffffff8e94b7af, result:0xf0
+law :: offset: 0xf4, out: 0xffffffff8ecc31ce, result:0xf4
+law :: offset: 0xf8, out: 0x24eb6a8d, result:0xf8
+law :: offset: 0xfc, out: 0x1ce7674f, result:0xfc
+lawd :: offset: 0x8, out: 0x7e876382d2ab13, result: 0x8
+lawd :: offset: 0x10, out: 0x976d6e9ac31510f3, result: 0x10
+lawd :: offset: 0x18, out: 0xb7746d775ad6a5fb, result: 0x18
+lawd :: offset: 0x20, out: 0x42b0c0a28677b502, result: 0x20
+lawd :: offset: 0x28, out: 0x2aa89d319e3c30ad, result: 0x28
+lawd :: offset: 0x30, out: 0x1f308ec377fb413d, result: 0x30
+lawd :: offset: 0x38, out: 0x7aa04213c760e4f7, result: 0x38
+lawd :: offset: 0x40, out: 0x9e705cc51ad8dca0, result: 0x40
+lawd :: offset: 0x48, out: 0x4b3dda869615a60d, result: 0x48
+lawd :: offset: 0x50, out: 0x5e7a4dd6353d41d, result: 0x50
+lawd :: offset: 0x58, out: 0x3af35a9dc40bd413, result: 0x58
+lawd :: offset: 0x60, out: 0x47f505569a08a180, result: 0x60
+lawd :: offset: 0x68, out: 0x9564b77fd6d2040f, result: 0x68
+lawd :: offset: 0x70, out: 0xcebc8279b2c76bbe, result: 0x70
+lawd :: offset: 0x78, out: 0xb5034c2f1f18e4c7, result: 0x78
+lawd :: offset: 0x80, out: 0x94ff52fc81afa797, result: 0x80
+lawd :: offset: 0x88, out: 0x31d8d9166dfc50ea, result: 0x88
+lawd :: offset: 0x90, out: 0x36549bd678e895b1, result: 0x90
+lawd :: offset: 0x98, out: 0x85e0a6319b63259b, result: 0x98
+lawd :: offset: 0xa0, out: 0x556b3ecaccf17ac5, result: 0xa0
+lawd :: offset: 0xa8, out: 0xb42f5fc581eea0fb, result: 0xa8
+lawd :: offset: 0xb0, out: 0x25b50fec14682d97, result: 0xb0
+lawd :: offset: 0xb8, out: 0xfc93c5132cfb087a, result: 0xb8
+lawd :: offset: 0xc0, out: 0x3c2cd9a9cda20766, result: 0xc0
+lawd :: offset: 0xc8, out: 0x1791722a7d72da3e, result: 0xc8
+lawd :: offset: 0xd0, out: 0x87cc9d193ce24ad, result: 0xd0
+lawd :: offset: 0xd8, out: 0x1d2a757038984ed2, result: 0xd8
+lawd :: offset: 0xe0, out: 0xd0d070db710cd036, result: 0xe0
+lawd :: offset: 0xe8, out: 0x39c21c7d03415604, result: 0xe8
+lawd :: offset: 0xf0, out: 0x8e94b7af8ecc31ce, result: 0xf0
+lawd :: offset: 0xf8, out: 0x24eb6a8d1ce7674f, result: 0xf8
+lai :: offset: 0x4, out: 0x12bd6aa, result:0x12bd6ab
+lai :: offset: 0x8, out: 0x7e8763, result:0x7e8764
+lai :: offset: 0xc, out: 0xffffffff82d2ab13, result:0xffffffff82d2ab14
+lai :: offset: 0x10, out: 0xffffffff976d6e9a, result:0xffffffff976d6e9b
+lai :: offset: 0x14, out: 0xffffffffc31510f3, result:0xffffffffc31510f4
+lai :: offset: 0x18, out: 0xffffffffb7746d77, result:0xffffffffb7746d78
+lai :: offset: 0x1c, out: 0x5ad6a5fb, result:0x5ad6a5fc
+lai :: offset: 0x20, out: 0x42b0c0a2, result:0x42b0c0a3
+lai :: offset: 0x24, out: 0xffffffff8677b502, result:0xffffffff8677b503
+lai :: offset: 0x28, out: 0x2aa89d31, result:0x2aa89d32
+lai :: offset: 0x2c, out: 0xffffffff9e3c30ad, result:0xffffffff9e3c30ae
+lai :: offset: 0x30, out: 0x1f308ec3, result:0x1f308ec4
+lai :: offset: 0x34, out: 0x77fb413d, result:0x77fb413e
+lai :: offset: 0x38, out: 0x7aa04213, result:0x7aa04214
+lai :: offset: 0x3c, out: 0xffffffffc760e4f7, result:0xffffffffc760e4f8
+lai :: offset: 0x40, out: 0xffffffff9e705cc5, result:0xffffffff9e705cc6
+lai :: offset: 0x44, out: 0x1ad8dca0, result:0x1ad8dca1
+lai :: offset: 0x48, out: 0x4b3dda86, result:0x4b3dda87
+lai :: offset: 0x4c, out: 0xffffffff9615a60d, result:0xffffffff9615a60e
+lai :: offset: 0x50, out: 0x5e7a4dd, result:0x5e7a4de
+lai :: offset: 0x54, out: 0x6353d41d, result:0x6353d41e
+lai :: offset: 0x58, out: 0x3af35a9d, result:0x3af35a9e
+lai :: offset: 0x5c, out: 0xffffffffc40bd413, result:0xffffffffc40bd414
+lai :: offset: 0x60, out: 0x47f50556, result:0x47f50557
+lai :: offset: 0x64, out: 0xffffffff9a08a180, result:0xffffffff9a08a181
+lai :: offset: 0x68, out: 0xffffffff9564b77f, result:0xffffffff9564b780
+lai :: offset: 0x6c, out: 0xffffffffd6d2040f, result:0xffffffffd6d20410
+lai :: offset: 0x70, out: 0xffffffffcebc8279, result:0xffffffffcebc827a
+lai :: offset: 0x74, out: 0xffffffffb2c76bbe, result:0xffffffffb2c76bbf
+lai :: offset: 0x78, out: 0xffffffffb5034c2f, result:0xffffffffb5034c30
+lai :: offset: 0x7c, out: 0x1f18e4c7, result:0x1f18e4c8
+lai :: offset: 0x80, out: 0xffffffff94ff52fc, result:0xffffffff94ff52fd
+lai :: offset: 0x84, out: 0xffffffff81afa797, result:0xffffffff81afa798
+lai :: offset: 0x88, out: 0x31d8d916, result:0x31d8d917
+lai :: offset: 0x8c, out: 0x6dfc50ea, result:0x6dfc50eb
+lai :: offset: 0x90, out: 0x36549bd6, result:0x36549bd7
+lai :: offset: 0x94, out: 0x78e895b1, result:0x78e895b2
+lai :: offset: 0x98, out: 0xffffffff85e0a631, result:0xffffffff85e0a632
+lai :: offset: 0x9c, out: 0xffffffff9b63259b, result:0xffffffff9b63259c
+lai :: offset: 0xa0, out: 0x556b3eca, result:0x556b3ecb
+lai :: offset: 0xa4, out: 0xffffffffccf17ac5, result:0xffffffffccf17ac6
+lai :: offset: 0xa8, out: 0xffffffffb42f5fc5, result:0xffffffffb42f5fc6
+lai :: offset: 0xac, out: 0xffffffff81eea0fb, result:0xffffffff81eea0fc
+lai :: offset: 0xb0, out: 0x25b50fec, result:0x25b50fed
+lai :: offset: 0xb4, out: 0x14682d97, result:0x14682d98
+lai :: offset: 0xb8, out: 0xfffffffffc93c513, result:0xfffffffffc93c514
+lai :: offset: 0xbc, out: 0x2cfb087a, result:0x2cfb087b
+lai :: offset: 0xc0, out: 0x3c2cd9a9, result:0x3c2cd9aa
+lai :: offset: 0xc4, out: 0xffffffffcda20766, result:0xffffffffcda20767
+lai :: offset: 0xc8, out: 0x1791722a, result:0x1791722b
+lai :: offset: 0xcc, out: 0x7d72da3e, result:0x7d72da3f
+lai :: offset: 0xd0, out: 0x87cc9d1, result:0x87cc9d2
+lai :: offset: 0xd4, out: 0xffffffff93ce24ad, result:0xffffffff93ce24ae
+lai :: offset: 0xd8, out: 0x1d2a7570, result:0x1d2a7571
+lai :: offset: 0xdc, out: 0x38984ed2, result:0x38984ed3
+lai :: offset: 0xe0, out: 0xffffffffd0d070db, result:0xffffffffd0d070dc
+lai :: offset: 0xe4, out: 0x710cd036, result:0x710cd037
+lai :: offset: 0xe8, out: 0x39c21c7d, result:0x39c21c7e
+lai :: offset: 0xec, out: 0x3415604, result:0x3415605
+lai :: offset: 0xf0, out: 0xffffffff8e94b7af, result:0xffffffff8e94b7b0
+lai :: offset: 0xf4, out: 0xffffffff8ecc31ce, result:0xffffffff8ecc31cf
+lai :: offset: 0xf8, out: 0x24eb6a8d, result:0x24eb6a8e
+lai :: offset: 0xfc, out: 0x1ce7674f, result:0x1ce76750
+laid :: offset: 0x8, out: 0x7e876382d2ab13, result: 0x7e876382d2ab14
+laid :: offset: 0x10, out: 0x976d6e9ac31510f3, result: 0x976d6e9ac31510f4
+laid :: offset: 0x18, out: 0xb7746d775ad6a5fb, result: 0xb7746d775ad6a5fc
+laid :: offset: 0x20, out: 0x42b0c0a28677b502, result: 0x42b0c0a28677b503
+laid :: offset: 0x28, out: 0x2aa89d319e3c30ad, result: 0x2aa89d319e3c30ae
+laid :: offset: 0x30, out: 0x1f308ec377fb413d, result: 0x1f308ec377fb413e
+laid :: offset: 0x38, out: 0x7aa04213c760e4f7, result: 0x7aa04213c760e4f8
+laid :: offset: 0x40, out: 0x9e705cc51ad8dca0, result: 0x9e705cc51ad8dca1
+laid :: offset: 0x48, out: 0x4b3dda869615a60d, result: 0x4b3dda869615a60e
+laid :: offset: 0x50, out: 0x5e7a4dd6353d41d, result: 0x5e7a4dd6353d41e
+laid :: offset: 0x58, out: 0x3af35a9dc40bd413, result: 0x3af35a9dc40bd414
+laid :: offset: 0x60, out: 0x47f505569a08a180, result: 0x47f505569a08a181
+laid :: offset: 0x68, out: 0x9564b77fd6d2040f, result: 0x9564b77fd6d20410
+laid :: offset: 0x70, out: 0xcebc8279b2c76bbe, result: 0xcebc8279b2c76bbf
+laid :: offset: 0x78, out: 0xb5034c2f1f18e4c7, result: 0xb5034c2f1f18e4c8
+laid :: offset: 0x80, out: 0x94ff52fc81afa797, result: 0x94ff52fc81afa798
+laid :: offset: 0x88, out: 0x31d8d9166dfc50ea, result: 0x31d8d9166dfc50eb
+laid :: offset: 0x90, out: 0x36549bd678e895b1, result: 0x36549bd678e895b2
+laid :: offset: 0x98, out: 0x85e0a6319b63259b, result: 0x85e0a6319b63259c
+laid :: offset: 0xa0, out: 0x556b3ecaccf17ac5, result: 0x556b3ecaccf17ac6
+laid :: offset: 0xa8, out: 0xb42f5fc581eea0fb, result: 0xb42f5fc581eea0fc
+laid :: offset: 0xb0, out: 0x25b50fec14682d97, result: 0x25b50fec14682d98
+laid :: offset: 0xb8, out: 0xfc93c5132cfb087a, result: 0xfc93c5132cfb087b
+laid :: offset: 0xc0, out: 0x3c2cd9a9cda20766, result: 0x3c2cd9a9cda20767
+laid :: offset: 0xc8, out: 0x1791722a7d72da3e, result: 0x1791722a7d72da3f
+laid :: offset: 0xd0, out: 0x87cc9d193ce24ad, result: 0x87cc9d193ce24ae
+laid :: offset: 0xd8, out: 0x1d2a757038984ed2, result: 0x1d2a757038984ed3
+laid :: offset: 0xe0, out: 0xd0d070db710cd036, result: 0xd0d070db710cd037
+laid :: offset: 0xe8, out: 0x39c21c7d03415604, result: 0x39c21c7d03415605
+laid :: offset: 0xf0, out: 0x8e94b7af8ecc31ce, result: 0x8e94b7af8ecc31cf
+laid :: offset: 0xf8, out: 0x24eb6a8d1ce7674f, result: 0x24eb6a8d1ce76750
+lad :: offset: 0x4, out: 0x12bd6aa, result:0x12bd6a9
+lad :: offset: 0x8, out: 0x7e8763, result:0x7e8762
+lad :: offset: 0xc, out: 0xffffffff82d2ab13, result:0xffffffff82d2ab12
+lad :: offset: 0x10, out: 0xffffffff976d6e9a, result:0xffffffff976d6e99
+lad :: offset: 0x14, out: 0xffffffffc31510f3, result:0xffffffffc31510f2
+lad :: offset: 0x18, out: 0xffffffffb7746d77, result:0xffffffffb7746d76
+lad :: offset: 0x1c, out: 0x5ad6a5fb, result:0x5ad6a5fa
+lad :: offset: 0x20, out: 0x42b0c0a2, result:0x42b0c0a1
+lad :: offset: 0x24, out: 0xffffffff8677b502, result:0xffffffff8677b501
+lad :: offset: 0x28, out: 0x2aa89d31, result:0x2aa89d30
+lad :: offset: 0x2c, out: 0xffffffff9e3c30ad, result:0xffffffff9e3c30ac
+lad :: offset: 0x30, out: 0x1f308ec3, result:0x1f308ec2
+lad :: offset: 0x34, out: 0x77fb413d, result:0x77fb413c
+lad :: offset: 0x38, out: 0x7aa04213, result:0x7aa04212
+lad :: offset: 0x3c, out: 0xffffffffc760e4f7, result:0xffffffffc760e4f6
+lad :: offset: 0x40, out: 0xffffffff9e705cc5, result:0xffffffff9e705cc4
+lad :: offset: 0x44, out: 0x1ad8dca0, result:0x1ad8dc9f
+lad :: offset: 0x48, out: 0x4b3dda86, result:0x4b3dda85
+lad :: offset: 0x4c, out: 0xffffffff9615a60d, result:0xffffffff9615a60c
+lad :: offset: 0x50, out: 0x5e7a4dd, result:0x5e7a4dc
+lad :: offset: 0x54, out: 0x6353d41d, result:0x6353d41c
+lad :: offset: 0x58, out: 0x3af35a9d, result:0x3af35a9c
+lad :: offset: 0x5c, out: 0xffffffffc40bd413, result:0xffffffffc40bd412
+lad :: offset: 0x60, out: 0x47f50556, result:0x47f50555
+lad :: offset: 0x64, out: 0xffffffff9a08a180, result:0xffffffff9a08a17f
+lad :: offset: 0x68, out: 0xffffffff9564b77f, result:0xffffffff9564b77e
+lad :: offset: 0x6c, out: 0xffffffffd6d2040f, result:0xffffffffd6d2040e
+lad :: offset: 0x70, out: 0xffffffffcebc8279, result:0xffffffffcebc8278
+lad :: offset: 0x74, out: 0xffffffffb2c76bbe, result:0xffffffffb2c76bbd
+lad :: offset: 0x78, out: 0xffffffffb5034c2f, result:0xffffffffb5034c2e
+lad :: offset: 0x7c, out: 0x1f18e4c7, result:0x1f18e4c6
+lad :: offset: 0x80, out: 0xffffffff94ff52fc, result:0xffffffff94ff52fb
+lad :: offset: 0x84, out: 0xffffffff81afa797, result:0xffffffff81afa796
+lad :: offset: 0x88, out: 0x31d8d916, result:0x31d8d915
+lad :: offset: 0x8c, out: 0x6dfc50ea, result:0x6dfc50e9
+lad :: offset: 0x90, out: 0x36549bd6, result:0x36549bd5
+lad :: offset: 0x94, out: 0x78e895b1, result:0x78e895b0
+lad :: offset: 0x98, out: 0xffffffff85e0a631, result:0xffffffff85e0a630
+lad :: offset: 0x9c, out: 0xffffffff9b63259b, result:0xffffffff9b63259a
+lad :: offset: 0xa0, out: 0x556b3eca, result:0x556b3ec9
+lad :: offset: 0xa4, out: 0xffffffffccf17ac5, result:0xffffffffccf17ac4
+lad :: offset: 0xa8, out: 0xffffffffb42f5fc5, result:0xffffffffb42f5fc4
+lad :: offset: 0xac, out: 0xffffffff81eea0fb, result:0xffffffff81eea0fa
+lad :: offset: 0xb0, out: 0x25b50fec, result:0x25b50feb
+lad :: offset: 0xb4, out: 0x14682d97, result:0x14682d96
+lad :: offset: 0xb8, out: 0xfffffffffc93c513, result:0xfffffffffc93c512
+lad :: offset: 0xbc, out: 0x2cfb087a, result:0x2cfb0879
+lad :: offset: 0xc0, out: 0x3c2cd9a9, result:0x3c2cd9a8
+lad :: offset: 0xc4, out: 0xffffffffcda20766, result:0xffffffffcda20765
+lad :: offset: 0xc8, out: 0x1791722a, result:0x17917229
+lad :: offset: 0xcc, out: 0x7d72da3e, result:0x7d72da3d
+lad :: offset: 0xd0, out: 0x87cc9d1, result:0x87cc9d0
+lad :: offset: 0xd4, out: 0xffffffff93ce24ad, result:0xffffffff93ce24ac
+lad :: offset: 0xd8, out: 0x1d2a7570, result:0x1d2a756f
+lad :: offset: 0xdc, out: 0x38984ed2, result:0x38984ed1
+lad :: offset: 0xe0, out: 0xffffffffd0d070db, result:0xffffffffd0d070da
+lad :: offset: 0xe4, out: 0x710cd036, result:0x710cd035
+lad :: offset: 0xe8, out: 0x39c21c7d, result:0x39c21c7c
+lad :: offset: 0xec, out: 0x3415604, result:0x3415603
+lad :: offset: 0xf0, out: 0xffffffff8e94b7af, result:0xffffffff8e94b7ae
+lad :: offset: 0xf4, out: 0xffffffff8ecc31ce, result:0xffffffff8ecc31cd
+lad :: offset: 0xf8, out: 0x24eb6a8d, result:0x24eb6a8c
+lad :: offset: 0xfc, out: 0x1ce7674f, result:0x1ce7674e
+ladd :: offset: 0x8, out: 0x7e876382d2ab13, result: 0x7e876382d2ab12
+ladd :: offset: 0x10, out: 0x976d6e9ac31510f3, result: 0x976d6e9ac31510f2
+ladd :: offset: 0x18, out: 0xb7746d775ad6a5fb, result: 0xb7746d775ad6a5fa
+ladd :: offset: 0x20, out: 0x42b0c0a28677b502, result: 0x42b0c0a28677b501
+ladd :: offset: 0x28, out: 0x2aa89d319e3c30ad, result: 0x2aa89d319e3c30ac
+ladd :: offset: 0x30, out: 0x1f308ec377fb413d, result: 0x1f308ec377fb413c
+ladd :: offset: 0x38, out: 0x7aa04213c760e4f7, result: 0x7aa04213c760e4f6
+ladd :: offset: 0x40, out: 0x9e705cc51ad8dca0, result: 0x9e705cc51ad8dc9f
+ladd :: offset: 0x48, out: 0x4b3dda869615a60d, result: 0x4b3dda869615a60c
+ladd :: offset: 0x50, out: 0x5e7a4dd6353d41d, result: 0x5e7a4dd6353d41c
+ladd :: offset: 0x58, out: 0x3af35a9dc40bd413, result: 0x3af35a9dc40bd412
+ladd :: offset: 0x60, out: 0x47f505569a08a180, result: 0x47f505569a08a17f
+ladd :: offset: 0x68, out: 0x9564b77fd6d2040f, result: 0x9564b77fd6d2040e
+ladd :: offset: 0x70, out: 0xcebc8279b2c76bbe, result: 0xcebc8279b2c76bbd
+ladd :: offset: 0x78, out: 0xb5034c2f1f18e4c7, result: 0xb5034c2f1f18e4c6
+ladd :: offset: 0x80, out: 0x94ff52fc81afa797, result: 0x94ff52fc81afa796
+ladd :: offset: 0x88, out: 0x31d8d9166dfc50ea, result: 0x31d8d9166dfc50e9
+ladd :: offset: 0x90, out: 0x36549bd678e895b1, result: 0x36549bd678e895b0
+ladd :: offset: 0x98, out: 0x85e0a6319b63259b, result: 0x85e0a6319b63259a
+ladd :: offset: 0xa0, out: 0x556b3ecaccf17ac5, result: 0x556b3ecaccf17ac4
+ladd :: offset: 0xa8, out: 0xb42f5fc581eea0fb, result: 0xb42f5fc581eea0fa
+ladd :: offset: 0xb0, out: 0x25b50fec14682d97, result: 0x25b50fec14682d96
+ladd :: offset: 0xb8, out: 0xfc93c5132cfb087a, result: 0xfc93c5132cfb0879
+ladd :: offset: 0xc0, out: 0x3c2cd9a9cda20766, result: 0x3c2cd9a9cda20765
+ladd :: offset: 0xc8, out: 0x1791722a7d72da3e, result: 0x1791722a7d72da3d
+ladd :: offset: 0xd0, out: 0x87cc9d193ce24ad, result: 0x87cc9d193ce24ac
+ladd :: offset: 0xd8, out: 0x1d2a757038984ed2, result: 0x1d2a757038984ed1
+ladd :: offset: 0xe0, out: 0xd0d070db710cd036, result: 0xd0d070db710cd035
+ladd :: offset: 0xe8, out: 0x39c21c7d03415604, result: 0x39c21c7d03415603
+ladd :: offset: 0xf0, out: 0x8e94b7af8ecc31ce, result: 0x8e94b7af8ecc31cd
+ladd :: offset: 0xf8, out: 0x24eb6a8d1ce7674f, result: 0x24eb6a8d1ce7674e
+las :: offset: 0x4, out: 0x12bd6aa, result:0xffffffffffffffff
+las :: offset: 0x8, out: 0x7e8763, result:0xffffffffffffffff
+las :: offset: 0xc, out: 0xffffffff82d2ab13, result:0xffffffffffffffff
+las :: offset: 0x10, out: 0xffffffff976d6e9a, result:0xffffffffffffffff
+las :: offset: 0x14, out: 0xffffffffc31510f3, result:0xffffffffffffffff
+las :: offset: 0x18, out: 0xffffffffb7746d77, result:0xffffffffffffffff
+las :: offset: 0x1c, out: 0x5ad6a5fb, result:0xffffffffffffffff
+las :: offset: 0x20, out: 0x42b0c0a2, result:0xffffffffffffffff
+las :: offset: 0x24, out: 0xffffffff8677b502, result:0xffffffffffffffff
+las :: offset: 0x28, out: 0x2aa89d31, result:0xffffffffffffffff
+las :: offset: 0x2c, out: 0xffffffff9e3c30ad, result:0xffffffffffffffff
+las :: offset: 0x30, out: 0x1f308ec3, result:0xffffffffffffffff
+las :: offset: 0x34, out: 0x77fb413d, result:0xffffffffffffffff
+las :: offset: 0x38, out: 0x7aa04213, result:0xffffffffffffffff
+las :: offset: 0x3c, out: 0xffffffffc760e4f7, result:0xffffffffffffffff
+las :: offset: 0x40, out: 0xffffffff9e705cc5, result:0xffffffffffffffff
+las :: offset: 0x44, out: 0x1ad8dca0, result:0xffffffffffffffff
+las :: offset: 0x48, out: 0x4b3dda86, result:0xffffffffffffffff
+las :: offset: 0x4c, out: 0xffffffff9615a60d, result:0xffffffffffffffff
+las :: offset: 0x50, out: 0x5e7a4dd, result:0xffffffffffffffff
+las :: offset: 0x54, out: 0x6353d41d, result:0xffffffffffffffff
+las :: offset: 0x58, out: 0x3af35a9d, result:0xffffffffffffffff
+las :: offset: 0x5c, out: 0xffffffffc40bd413, result:0xffffffffffffffff
+las :: offset: 0x60, out: 0x47f50556, result:0xffffffffffffffff
+las :: offset: 0x64, out: 0xffffffff9a08a180, result:0xffffffffffffffff
+las :: offset: 0x68, out: 0xffffffff9564b77f, result:0xffffffffffffffff
+las :: offset: 0x6c, out: 0xffffffffd6d2040f, result:0xffffffffffffffff
+las :: offset: 0x70, out: 0xffffffffcebc8279, result:0xffffffffffffffff
+las :: offset: 0x74, out: 0xffffffffb2c76bbe, result:0xffffffffffffffff
+las :: offset: 0x78, out: 0xffffffffb5034c2f, result:0xffffffffffffffff
+las :: offset: 0x7c, out: 0x1f18e4c7, result:0xffffffffffffffff
+las :: offset: 0x80, out: 0xffffffff94ff52fc, result:0xffffffffffffffff
+las :: offset: 0x84, out: 0xffffffff81afa797, result:0xffffffffffffffff
+las :: offset: 0x88, out: 0x31d8d916, result:0xffffffffffffffff
+las :: offset: 0x8c, out: 0x6dfc50ea, result:0xffffffffffffffff
+las :: offset: 0x90, out: 0x36549bd6, result:0xffffffffffffffff
+las :: offset: 0x94, out: 0x78e895b1, result:0xffffffffffffffff
+las :: offset: 0x98, out: 0xffffffff85e0a631, result:0xffffffffffffffff
+las :: offset: 0x9c, out: 0xffffffff9b63259b, result:0xffffffffffffffff
+las :: offset: 0xa0, out: 0x556b3eca, result:0xffffffffffffffff
+las :: offset: 0xa4, out: 0xffffffffccf17ac5, result:0xffffffffffffffff
+las :: offset: 0xa8, out: 0xffffffffb42f5fc5, result:0xffffffffffffffff
+las :: offset: 0xac, out: 0xffffffff81eea0fb, result:0xffffffffffffffff
+las :: offset: 0xb0, out: 0x25b50fec, result:0xffffffffffffffff
+las :: offset: 0xb4, out: 0x14682d97, result:0xffffffffffffffff
+las :: offset: 0xb8, out: 0xfffffffffc93c513, result:0xffffffffffffffff
+las :: offset: 0xbc, out: 0x2cfb087a, result:0xffffffffffffffff
+las :: offset: 0xc0, out: 0x3c2cd9a9, result:0xffffffffffffffff
+las :: offset: 0xc4, out: 0xffffffffcda20766, result:0xffffffffffffffff
+las :: offset: 0xc8, out: 0x1791722a, result:0xffffffffffffffff
+las :: offset: 0xcc, out: 0x7d72da3e, result:0xffffffffffffffff
+las :: offset: 0xd0, out: 0x87cc9d1, result:0xffffffffffffffff
+las :: offset: 0xd4, out: 0xffffffff93ce24ad, result:0xffffffffffffffff
+las :: offset: 0xd8, out: 0x1d2a7570, result:0xffffffffffffffff
+las :: offset: 0xdc, out: 0x38984ed2, result:0xffffffffffffffff
+las :: offset: 0xe0, out: 0xffffffffd0d070db, result:0xffffffffffffffff
+las :: offset: 0xe4, out: 0x710cd036, result:0xffffffffffffffff
+las :: offset: 0xe8, out: 0x39c21c7d, result:0xffffffffffffffff
+las :: offset: 0xec, out: 0x3415604, result:0xffffffffffffffff
+las :: offset: 0xf0, out: 0xffffffff8e94b7af, result:0xffffffffffffffff
+las :: offset: 0xf4, out: 0xffffffff8ecc31ce, result:0xffffffffffffffff
+las :: offset: 0xf8, out: 0x24eb6a8d, result:0xffffffffffffffff
+las :: offset: 0xfc, out: 0x1ce7674f, result:0xffffffffffffffff
+lasd :: offset: 0x8, out: 0x7e876382d2ab13, result: 0xffffffffffffffff
+lasd :: offset: 0x10, out: 0x976d6e9ac31510f3, result: 0xffffffffffffffff
+lasd :: offset: 0x18, out: 0xb7746d775ad6a5fb, result: 0xffffffffffffffff
+lasd :: offset: 0x20, out: 0x42b0c0a28677b502, result: 0xffffffffffffffff
+lasd :: offset: 0x28, out: 0x2aa89d319e3c30ad, result: 0xffffffffffffffff
+lasd :: offset: 0x30, out: 0x1f308ec377fb413d, result: 0xffffffffffffffff
+lasd :: offset: 0x38, out: 0x7aa04213c760e4f7, result: 0xffffffffffffffff
+lasd :: offset: 0x40, out: 0x9e705cc51ad8dca0, result: 0xffffffffffffffff
+lasd :: offset: 0x48, out: 0x4b3dda869615a60d, result: 0xffffffffffffffff
+lasd :: offset: 0x50, out: 0x5e7a4dd6353d41d, result: 0xffffffffffffffff
+lasd :: offset: 0x58, out: 0x3af35a9dc40bd413, result: 0xffffffffffffffff
+lasd :: offset: 0x60, out: 0x47f505569a08a180, result: 0xffffffffffffffff
+lasd :: offset: 0x68, out: 0x9564b77fd6d2040f, result: 0xffffffffffffffff
+lasd :: offset: 0x70, out: 0xcebc8279b2c76bbe, result: 0xffffffffffffffff
+lasd :: offset: 0x78, out: 0xb5034c2f1f18e4c7, result: 0xffffffffffffffff
+lasd :: offset: 0x80, out: 0x94ff52fc81afa797, result: 0xffffffffffffffff
+lasd :: offset: 0x88, out: 0x31d8d9166dfc50ea, result: 0xffffffffffffffff
+lasd :: offset: 0x90, out: 0x36549bd678e895b1, result: 0xffffffffffffffff
+lasd :: offset: 0x98, out: 0x85e0a6319b63259b, result: 0xffffffffffffffff
+lasd :: offset: 0xa0, out: 0x556b3ecaccf17ac5, result: 0xffffffffffffffff
+lasd :: offset: 0xa8, out: 0xb42f5fc581eea0fb, result: 0xffffffffffffffff
+lasd :: offset: 0xb0, out: 0x25b50fec14682d97, result: 0xffffffffffffffff
+lasd :: offset: 0xb8, out: 0xfc93c5132cfb087a, result: 0xffffffffffffffff
+lasd :: offset: 0xc0, out: 0x3c2cd9a9cda20766, result: 0xffffffffffffffff
+lasd :: offset: 0xc8, out: 0x1791722a7d72da3e, result: 0xffffffffffffffff
+lasd :: offset: 0xd0, out: 0x87cc9d193ce24ad, result: 0xffffffffffffffff
+lasd :: offset: 0xd8, out: 0x1d2a757038984ed2, result: 0xffffffffffffffff
+lasd :: offset: 0xe0, out: 0xd0d070db710cd036, result: 0xffffffffffffffff
+lasd :: offset: 0xe8, out: 0x39c21c7d03415604, result: 0xffffffffffffffff
+lasd :: offset: 0xf0, out: 0x8e94b7af8ecc31ce, result: 0xffffffffffffffff
+lasd :: offset: 0xf8, out: 0x24eb6a8d1ce7674f, result: 0xffffffffffffffff
+lac :: offset: 0x4, out: 0x12bd6aa, result:0x0
+lac :: offset: 0x8, out: 0x7e8763, result:0x0
+lac :: offset: 0xc, out: 0xffffffff82d2ab13, result:0x0
+lac :: offset: 0x10, out: 0xffffffff976d6e9a, result:0x0
+lac :: offset: 0x14, out: 0xffffffffc31510f3, result:0x0
+lac :: offset: 0x18, out: 0xffffffffb7746d77, result:0x0
+lac :: offset: 0x1c, out: 0x5ad6a5fb, result:0x0
+lac :: offset: 0x20, out: 0x42b0c0a2, result:0x0
+lac :: offset: 0x24, out: 0xffffffff8677b502, result:0x0
+lac :: offset: 0x28, out: 0x2aa89d31, result:0x0
+lac :: offset: 0x2c, out: 0xffffffff9e3c30ad, result:0x0
+lac :: offset: 0x30, out: 0x1f308ec3, result:0x0
+lac :: offset: 0x34, out: 0x77fb413d, result:0x0
+lac :: offset: 0x38, out: 0x7aa04213, result:0x0
+lac :: offset: 0x3c, out: 0xffffffffc760e4f7, result:0x0
+lac :: offset: 0x40, out: 0xffffffff9e705cc5, result:0x0
+lac :: offset: 0x44, out: 0x1ad8dca0, result:0x0
+lac :: offset: 0x48, out: 0x4b3dda86, result:0x0
+lac :: offset: 0x4c, out: 0xffffffff9615a60d, result:0x0
+lac :: offset: 0x50, out: 0x5e7a4dd, result:0x0
+lac :: offset: 0x54, out: 0x6353d41d, result:0x0
+lac :: offset: 0x58, out: 0x3af35a9d, result:0x0
+lac :: offset: 0x5c, out: 0xffffffffc40bd413, result:0x0
+lac :: offset: 0x60, out: 0x47f50556, result:0x0
+lac :: offset: 0x64, out: 0xffffffff9a08a180, result:0x0
+lac :: offset: 0x68, out: 0xffffffff9564b77f, result:0x0
+lac :: offset: 0x6c, out: 0xffffffffd6d2040f, result:0x0
+lac :: offset: 0x70, out: 0xffffffffcebc8279, result:0x0
+lac :: offset: 0x74, out: 0xffffffffb2c76bbe, result:0x0
+lac :: offset: 0x78, out: 0xffffffffb5034c2f, result:0x0
+lac :: offset: 0x7c, out: 0x1f18e4c7, result:0x0
+lac :: offset: 0x80, out: 0xffffffff94ff52fc, result:0x0
+lac :: offset: 0x84, out: 0xffffffff81afa797, result:0x0
+lac :: offset: 0x88, out: 0x31d8d916, result:0x0
+lac :: offset: 0x8c, out: 0x6dfc50ea, result:0x0
+lac :: offset: 0x90, out: 0x36549bd6, result:0x0
+lac :: offset: 0x94, out: 0x78e895b1, result:0x0
+lac :: offset: 0x98, out: 0xffffffff85e0a631, result:0x0
+lac :: offset: 0x9c, out: 0xffffffff9b63259b, result:0x0
+lac :: offset: 0xa0, out: 0x556b3eca, result:0x0
+lac :: offset: 0xa4, out: 0xffffffffccf17ac5, result:0x0
+lac :: offset: 0xa8, out: 0xffffffffb42f5fc5, result:0x0
+lac :: offset: 0xac, out: 0xffffffff81eea0fb, result:0x0
+lac :: offset: 0xb0, out: 0x25b50fec, result:0x0
+lac :: offset: 0xb4, out: 0x14682d97, result:0x0
+lac :: offset: 0xb8, out: 0xfffffffffc93c513, result:0x0
+lac :: offset: 0xbc, out: 0x2cfb087a, result:0x0
+lac :: offset: 0xc0, out: 0x3c2cd9a9, result:0x0
+lac :: offset: 0xc4, out: 0xffffffffcda20766, result:0x0
+lac :: offset: 0xc8, out: 0x1791722a, result:0x0
+lac :: offset: 0xcc, out: 0x7d72da3e, result:0x0
+lac :: offset: 0xd0, out: 0x87cc9d1, result:0x0
+lac :: offset: 0xd4, out: 0xffffffff93ce24ad, result:0x0
+lac :: offset: 0xd8, out: 0x1d2a7570, result:0x0
+lac :: offset: 0xdc, out: 0x38984ed2, result:0x0
+lac :: offset: 0xe0, out: 0xffffffffd0d070db, result:0x0
+lac :: offset: 0xe4, out: 0x710cd036, result:0x0
+lac :: offset: 0xe8, out: 0x39c21c7d, result:0x0
+lac :: offset: 0xec, out: 0x3415604, result:0x0
+lac :: offset: 0xf0, out: 0xffffffff8e94b7af, result:0x0
+lac :: offset: 0xf4, out: 0xffffffff8ecc31ce, result:0x0
+lac :: offset: 0xf8, out: 0x24eb6a8d, result:0x0
+lac :: offset: 0xfc, out: 0x1ce7674f, result:0x0
+lacd :: offset: 0x8, out: 0x7e876382d2ab13, result: 0x0
+lacd :: offset: 0x10, out: 0x976d6e9ac31510f3, result: 0x0
+lacd :: offset: 0x18, out: 0xb7746d775ad6a5fb, result: 0x0
+lacd :: offset: 0x20, out: 0x42b0c0a28677b502, result: 0x0
+lacd :: offset: 0x28, out: 0x2aa89d319e3c30ad, result: 0x0
+lacd :: offset: 0x30, out: 0x1f308ec377fb413d, result: 0x0
+lacd :: offset: 0x38, out: 0x7aa04213c760e4f7, result: 0x0
+lacd :: offset: 0x40, out: 0x9e705cc51ad8dca0, result: 0x0
+lacd :: offset: 0x48, out: 0x4b3dda869615a60d, result: 0x0
+lacd :: offset: 0x50, out: 0x5e7a4dd6353d41d, result: 0x0
+lacd :: offset: 0x58, out: 0x3af35a9dc40bd413, result: 0x0
+lacd :: offset: 0x60, out: 0x47f505569a08a180, result: 0x0
+lacd :: offset: 0x68, out: 0x9564b77fd6d2040f, result: 0x0
+lacd :: offset: 0x70, out: 0xcebc8279b2c76bbe, result: 0x0
+lacd :: offset: 0x78, out: 0xb5034c2f1f18e4c7, result: 0x0
+lacd :: offset: 0x80, out: 0x94ff52fc81afa797, result: 0x0
+lacd :: offset: 0x88, out: 0x31d8d9166dfc50ea, result: 0x0
+lacd :: offset: 0x90, out: 0x36549bd678e895b1, result: 0x0
+lacd :: offset: 0x98, out: 0x85e0a6319b63259b, result: 0x0
+lacd :: offset: 0xa0, out: 0x556b3ecaccf17ac5, result: 0x0
+lacd :: offset: 0xa8, out: 0xb42f5fc581eea0fb, result: 0x0
+lacd :: offset: 0xb0, out: 0x25b50fec14682d97, result: 0x0
+lacd :: offset: 0xb8, out: 0xfc93c5132cfb087a, result: 0x0
+lacd :: offset: 0xc0, out: 0x3c2cd9a9cda20766, result: 0x0
+lacd :: offset: 0xc8, out: 0x1791722a7d72da3e, result: 0x0
+lacd :: offset: 0xd0, out: 0x87cc9d193ce24ad, result: 0x0
+lacd :: offset: 0xd8, out: 0x1d2a757038984ed2, result: 0x0
+lacd :: offset: 0xe0, out: 0xd0d070db710cd036, result: 0x0
+lacd :: offset: 0xe8, out: 0x39c21c7d03415604, result: 0x0
+lacd :: offset: 0xf0, out: 0x8e94b7af8ecc31ce, result: 0x0
+lacd :: offset: 0xf8, out: 0x24eb6a8d1ce7674f, result: 0x0
diff --git a/none/tests/mips64/cvm_atomic_thread.c b/none/tests/mips64/cvm_atomic_thread.c
index 5e71ec1..e629bc4 100644
--- a/none/tests/mips64/cvm_atomic_thread.c
+++ b/none/tests/mips64/cvm_atomic_thread.c
@@ -14,7 +14,7 @@
#define NNN 3456987 // Number of repetition.
/* Expected values */
-long long int p1_expd[N] = { 2156643710, 2156643710, 3456986, 6913974,
+int p1_expd[N] = { 2156643710, 2156643710, 3456986, 6913974,
4288053322, 0, 4294967295,
6913974, 21777111,
3456986, 2153186724,
@@ -34,7 +34,7 @@
#define IS_8_ALIGNED(_ptr) (0 == (((unsigned long)(_ptr)) & 7))
-__attribute__((noinline)) void atomic_saa ( long long int* p, int n )
+__attribute__((noinline)) void atomic_saa ( int* p, int n )
{
#if (_MIPS_ARCH_OCTEON2)
unsigned long block[2] = { (unsigned long)p, (unsigned long)n };
@@ -66,7 +66,7 @@
#endif
}
-__attribute__((noinline)) void atomic_laa ( long long int* p, int n )
+__attribute__((noinline)) void atomic_laa ( int* p, int n )
{
#if (_MIPS_ARCH_OCTEON2)
unsigned long block[2] = { (unsigned long)p, (unsigned long)n };
@@ -98,7 +98,7 @@
#endif
}
-__attribute__((noinline)) void atomic_law ( long long int* p, int n )
+__attribute__((noinline)) void atomic_law ( int* p, int n )
{
#if (_MIPS_ARCH_OCTEON2)
unsigned long block[2] = { (unsigned long)p, (unsigned long)n };
@@ -130,7 +130,7 @@
#endif
}
-__attribute__((noinline)) void atomic_lai ( long long int* p )
+__attribute__((noinline)) void atomic_lai ( int* p )
{
#if (_MIPS_ARCH_OCTEON2)
unsigned long block[2] = { (unsigned long)p };
@@ -162,7 +162,7 @@
#endif
}
-__attribute__((noinline)) void atomic_lad ( long long int* p )
+__attribute__((noinline)) void atomic_lad ( int* p )
{
#if (_MIPS_ARCH_OCTEON2)
unsigned long block[2] = { (unsigned long)p };
@@ -194,7 +194,7 @@
#endif
}
-__attribute__((noinline)) void atomic_lac ( long long int* p )
+__attribute__((noinline)) void atomic_lac ( int* p )
{
#if (_MIPS_ARCH_OCTEON2)
unsigned long block[2] = { (unsigned long)p };
@@ -226,7 +226,7 @@
#endif
}
-__attribute__((noinline)) void atomic_las ( long long int* p )
+__attribute__((noinline)) void atomic_las ( int* p )
{
#if (_MIPS_ARCH_OCTEON2)
unsigned long block[2] = { (unsigned long)p };
@@ -307,12 +307,10 @@
#if (_MIPS_ARCH_OCTEON2)
int i, status;
char* page[N];
- long long int* p1[N];
+ int* p1[N];
long long int* p2[N];
pid_t child, pc2;
- printf("parent, pre-fork\n");
-
for (i = 0; i < N; i++) {
page[i] = mmap( 0, sysconf(_SC_PAGESIZE),
PROT_READ|PROT_WRITE,
@@ -321,8 +319,8 @@
perror("mmap failed");
exit(1);
}
- p1[i] = (long long int*)(page[i]+0);
- p2[i] = (long long int*)(page[i]+256);
+ p1[i] = (int*)(page[i] + 0);
+ p2[i] = (long long int*)(page[i] + 256);
assert( IS_8_ALIGNED(p1[i]) );
assert( IS_8_ALIGNED(p2[i]) );
@@ -342,14 +340,13 @@
if (child == 0) {
/* --- CHILD --- */
- printf("child\n");
for (i = 0; i < NNN; i++) {
atomic_saa(p1[0], i);
- atomic_saad(p2[0], i+98765 ); /* ensure we hit the upper 32 bits */
+ atomic_saad(p2[0], i + 98765 ); /* ensure we hit the upper 32 bits */
atomic_laa(p1[1], i);
- atomic_laad(p2[1], i+98765 ); /* ensure we hit the upper 32 bits */
+ atomic_laad(p2[1], i + 98765 ); /* ensure we hit the upper 32 bits */
atomic_law(p1[2], i);
- atomic_lawd(p2[2], i+98765 ); /* ensure we hit the upper 32 bits */
+ atomic_lawd(p2[2], i + 98765 ); /* ensure we hit the upper 32 bits */
atomic_lai(p1[3]);
atomic_laid(p2[3]);
atomic_lad(p1[4]);
@@ -377,15 +374,13 @@
}
/* --- PARENT --- */
- printf("parent\n");
-
for (i = 0; i < NNN; i++) {
atomic_saa(p1[0], i);
- atomic_saad(p2[0], i+98765); /* ensure we hit the upper 32 bits */
+ atomic_saad(p2[0], i + 98765); /* ensure we hit the upper 32 bits */
atomic_laa(p1[1], i);
- atomic_laad(p2[1], i+98765); /* ensure we hit the upper 32 bits */
+ atomic_laad(p2[1], i + 98765); /* ensure we hit the upper 32 bits */
atomic_law(p1[2], i);
- atomic_lawd(p2[2], i+98765 ); /* ensure we hit the upper 32 bits */
+ atomic_lawd(p2[2], i + 98765 ); /* ensure we hit the upper 32 bits */
atomic_lai(p1[3]);
atomic_laid(p2[3]);
atomic_lad(p1[4]);
@@ -414,25 +409,25 @@
/* assert that child finished normally */
assert(WIFEXITED(status));
- printf("Store Atomic Add: 32 bit %lld, 64 bit %lld\n", *p1[0], *p2[0]);
- printf("Load Atomic Add: 32 bit %lld, 64 bit %lld\n", *p1[1], *p2[1]);
- printf("Load Atomic Swap: 32 bit %lld, 64 bit %lld\n", *p1[2], *p2[2]);
- printf("Load Atomic Increment: 32 bit %lld, 64 bit %lld\n", *p1[3], *p2[3]);
- printf("Load Atomic Decrement: 32 bit %lld, 64 bit %lld\n", *p1[4], *p2[4]);
- printf("Load Atomic Clear: 32 bit %lld, 64 bit %lld\n", *p1[5], *p2[5]);
- printf("Load Atomic Set: 32 bit %lld, 64 bit %lld\n", *p1[6], *p2[6]);
- printf("laa and saa: base1: %lld, base2: %lld\n", *p1[7], *p1[8]);
- printf("laad and saad: base1: %lld, base2: %lld\n", *p2[7], *p2[8]);
- printf("law and saa: base1: %lld, base2: %lld\n", *p1[9], *p1[10]);
- printf("lawd and saad: base1: %lld, base2: %lld\n", *p2[9], *p2[10]);
- printf("lai and saa: base1: %lld, base2: %lld\n", *p1[11], *p1[12]);
- printf("laid and saad: base1: %lld, base2: %lld\n", *p2[11], *p2[12]);
- printf("las and saa: base1: %lld, base2: %lld\n", *p1[13], *p1[14]);
- printf("lasd and saad: base1: %lld, base2: %lld\n", *p2[13], *p2[14]);
- printf("lad and saa: base1: %lld, base2: %lld\n", *p1[15], *p1[16]);
- printf("ladd and saad: base1: %lld, base2: %lld\n", *p2[15], *p2[16]);
- printf("lac and saa: base1: %lld, base2: %lld\n", *p1[17], *p1[18]);
- printf("lacd and saad: base1: %lld, base2: %lld\n", *p2[17], *p2[18]);
+ printf("Store Atomic Add: 32 bit %u, 64 bit %lld\n", *p1[0], *p2[0]);
+ printf("Load Atomic Add: 32 bit %u, 64 bit %lld\n", *p1[1], *p2[1]);
+ printf("Load Atomic Swap: 32 bit %u, 64 bit %lld\n", *p1[2], *p2[2]);
+ printf("Load Atomic Increment: 32 bit %u, 64 bit %lld\n", *p1[3], *p2[3]);
+ printf("Load Atomic Decrement: 32 bit %u, 64 bit %lld\n", *p1[4], *p2[4]);
+ printf("Load Atomic Clear: 32 bit %u, 64 bit %lld\n", *p1[5], *p2[5]);
+ printf("Load Atomic Set: 32 bit %u, 64 bit %lld\n", *p1[6], *p2[6]);
+ printf("laa and saa: base1: %u, base2: %u\n", *p1[7], *p1[8]);
+ printf("laad and saad: base1: %lld, base2: %lld\n", *p2[7], *p2[8]);
+ printf("law and saa: base1: %u, base2: %u\n", *p1[9], *p1[10]);
+ printf("lawd and saad: base1: %lld, base2: %lld\n", *p2[9], *p2[10]);
+ printf("lai and saa: base1: %u, base2: %u\n", *p1[11], *p1[12]);
+ printf("laid and saad: base1: %lld, base2: %lld\n", *p2[11], *p2[12]);
+ printf("las and saa: base1: %u, base2: %u\n", *p1[13], *p1[14]);
+ printf("lasd and saad: base1: %lld, base2: %lld\n", *p2[13], *p2[14]);
+ printf("lad and saa: base1: %u, base2: %u\n", *p1[15], *p1[16]);
+ printf("ladd and saad: base1: %lld, base2: %lld\n", *p2[15], *p2[16]);
+ printf("lac and saa: base1: %u, base2: %u\n", *p1[17], *p1[18]);
+ printf("lacd and saad: base1: %lld, base2: %lld\n", *p2[17], *p2[18]);
for (i = 0; i < N; i++) {
if (p1_expd[i] == *p1[i] && p2_expd[i] == *p2[i]) {
diff --git a/none/tests/mips64/cvm_atomic_thread.stdout.exp b/none/tests/mips64/cvm_atomic_thread.stdout.exp
new file mode 100644
index 0000000..991d2c8
--- /dev/null
+++ b/none/tests/mips64/cvm_atomic_thread.stdout.exp
@@ -0,0 +1,39 @@
+Store Atomic Add: 32 bit 2156643710, 64 bit 12633614303292
+Load Atomic Add: 32 bit 2156643710, 64 bit 12633614303292
+Load Atomic Swap: 32 bit 3456986, 64 bit 3555751
+Load Atomic Increment: 32 bit 6913974, 64 bit 6913974
+Load Atomic Decrement: 32 bit 4288053322, 64 bit -6913974
+Load Atomic Clear: 32 bit 0, 64 bit 0
+Load Atomic Set: 32 bit 4294967295, 64 bit -1
+laa and saa: base1: 6913974, base2: 21777111
+laad and saad: base1: 6913974, base2: 23901514779351
+law and saa: base1: 3456986, base2: 2153186724
+lawd and saad: base1: 3456986, base2: 11950752204196
+lai and saa: base1: 6913974, base2: 21777111
+laid and saad: base1: 6913974, base2: 23901514779351
+las and saa: base1: 4294967295, base2: 4288053323
+lasd and saad: base1: -1, base2: -6913973
+lad and saa: base1: 4288053322, base2: 4273190185
+ladd and saad: base1: -6913974, base2: -23901514779351
+lac and saa: base1: 0, base2: 0
+lacd and saad: base1: 0, base2: 0
+PASS 1
+PASS 2
+PASS 3
+PASS 4
+PASS 5
+PASS 6
+PASS 7
+PASS 8
+PASS 9
+PASS 10
+PASS 11
+PASS 12
+PASS 13
+PASS 14
+PASS 15
+PASS 16
+PASS 17
+PASS 18
+PASS 19
+parent exits
diff --git a/none/tests/mips64/cvm_atomic_thread.stdout.exp-LE b/none/tests/mips64/cvm_atomic_thread.stdout.exp-LE
deleted file mode 100644
index ad132f8..0000000
--- a/none/tests/mips64/cvm_atomic_thread.stdout.exp-LE
+++ /dev/null
@@ -1,43 +0,0 @@
-parent, pre-fork
-child
-parent, pre-fork
-parent
-Store Atomic Add: 32 bit 2156643710, 64 bit 12633614303292
-Load Atomic Add: 32 bit 2156643710, 64 bit 12633614303292
-Load Atomic Swap: 32 bit 3456986, 64 bit 3555751
-Load Atomic Increment: 32 bit 6913974, 64 bit 6913974
-Load Atomic Decrement: 32 bit 4288053322, 64 bit -6913974
-Load Atomic Clear: 32 bit 0, 64 bit 0
-Load Atomic Set: 32 bit 4294967295, 64 bit -1
-laa and saa: base1: 6913974, base2: 21777111
-laad and saad: base1: 6913974, base2: 23901514779351
-law and saa: base1: 3456986, base2: 2153186724
-lawd and saad: base1: 3456986, base2: 11950752204196
-lai and saa: base1: 6913974, base2: 21777111
-laid and saad: base1: 6913974, base2: 23901514779351
-las and saa: base1: 4294967295, base2: 4288053323
-lasd and saad: base1: -1, base2: -6913973
-lad and saa: base1: 4288053322, base2: 4273190185
-ladd and saad: base1: -6913974, base2: -23901514779351
-lac and saa: base1: 0, base2: 0
-lacd and saad: base1: 0, base2: 0
-PASS 1
-PASS 2
-PASS 3
-PASS 4
-PASS 5
-PASS 6
-PASS 7
-PASS 8
-PASS 9
-PASS 10
-PASS 11
-PASS 12
-PASS 13
-PASS 14
-PASS 15
-PASS 16
-PASS 17
-PASS 18
-PASS 19
-parent exits
diff --git a/none/tests/mips64/test_math.stdout.exp b/none/tests/mips64/test_math.stdout.exp
index 2a0e71f..6017e26 100644
--- a/none/tests/mips64/test_math.stdout.exp
+++ b/none/tests/mips64/test_math.stdout.exp
@@ -1,7 +1,7 @@
fesetround(FE_UPWARD)
lrint(1234.01): 1235
lrintf(1234.01f): 1235
-lrintl(1234.01): 1234
+lrintl(1234.01): 1235
fesetround(FE_TOWARDZERO)
lrint(1234.01): 1234
lrintf(1234.01f): 1234
@@ -9,7 +9,7 @@
fesetround(FE_UPWARD)
llrint(1234.01): 1235
llrintf(1234.01f): 1235
-llrintf(1234.01f): 1234
+llrintf(1234.01f): 1235
fesetround(FE_TOWARDZERO)
llrint(1234.01): 1234
llrintf(1234.01f): 1234
@@ -28,8 +28,8 @@
feclearexcept(FE_ALL_EXCEPT)
rintl(1234.0): 1234.000000
(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): 0
-rintl(1234.01): 1234.000000
-(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): 0
+rintl(1234.01): 1235.000000
+(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): 4
fesetround(FE_TOWARDZERO)
rint(1234.01): 1234.000000
rintf(1234.01f): 1234.000000
@@ -43,7 +43,7 @@
nearbyintf(1234.01f): 1235.000000
feclearexcept(FE_ALL_EXCEPT)
nearbyintl(1234.0f): 1234.000000
-nearbyintl(1234.01f): 1234.000000
+nearbyintl(1234.01f): 1235.000000
fesetround(FE_TOWARDZERO)
nearbyint(1234.01): 1234.000000
nearbyintf(1234.01f): 1234.000000
diff --git a/none/tests/mips64/test_math.stdout.exp-older-gcc b/none/tests/mips64/test_math.stdout.exp-older-gcc
new file mode 100644
index 0000000..2a0e71f
--- /dev/null
+++ b/none/tests/mips64/test_math.stdout.exp-older-gcc
@@ -0,0 +1,55 @@
+fesetround(FE_UPWARD)
+lrint(1234.01): 1235
+lrintf(1234.01f): 1235
+lrintl(1234.01): 1234
+fesetround(FE_TOWARDZERO)
+lrint(1234.01): 1234
+lrintf(1234.01f): 1234
+lrintl(1234.01): 1234
+fesetround(FE_UPWARD)
+llrint(1234.01): 1235
+llrintf(1234.01f): 1235
+llrintf(1234.01f): 1234
+fesetround(FE_TOWARDZERO)
+llrint(1234.01): 1234
+llrintf(1234.01f): 1234
+llrintl(1234.01): 1234
+fesetround(FE_UPWARD)
+feclearexcept(FE_ALL_EXCEPT)
+rint(1234.0): 1234.000000
+(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): 0
+rint(1234.01): 1235.000000
+(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): 4
+feclearexcept(FE_ALL_EXCEPT)
+rintf(1234.0f): 1234.000000
+(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): 0
+rintf(1234.01f): 1235.000000
+(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): 4
+feclearexcept(FE_ALL_EXCEPT)
+rintl(1234.0): 1234.000000
+(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): 0
+rintl(1234.01): 1234.000000
+(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): 0
+fesetround(FE_TOWARDZERO)
+rint(1234.01): 1234.000000
+rintf(1234.01f): 1234.000000
+rintl(1234.01): 1234.000000
+fesetround(FE_UPWARD)
+feclearexcept(FE_ALL_EXCEPT)
+nearbyint(1234.0): 1234.000000
+nearbyint(1234.01): 1235.000000
+feclearexcept(FE_ALL_EXCEPT)
+nearbyintf(1234.0f): 1234.000000
+nearbyintf(1234.01f): 1235.000000
+feclearexcept(FE_ALL_EXCEPT)
+nearbyintl(1234.0f): 1234.000000
+nearbyintl(1234.01f): 1234.000000
+fesetround(FE_TOWARDZERO)
+nearbyint(1234.01): 1234.000000
+nearbyintf(1234.01f): 1234.000000
+nearbyintl(1234.01): 1234.000000
+log(M_E): 1.000000
+tgamma(5.0): 24.000000
+cbrt(27.0): 3.000000
+feclearexcept(FE_ALL_EXCEPT): 0
+raised: 32
diff --git a/none/tests/nocwd.vgtest b/none/tests/nocwd.vgtest
index 74e2b4a..f8d4c3b 100644
--- a/none/tests/nocwd.vgtest
+++ b/none/tests/nocwd.vgtest
@@ -1,2 +1,3 @@
prog: nocwd
vgopts: -q --trace-children=yes
+cleanup: chmod u+rwx /tmp/wd_test_*; rm -rf /tmp/wd_test_*
diff --git a/none/tests/ppc32/Makefile.am b/none/tests/ppc32/Makefile.am
index c4af707..11697c9 100644
--- a/none/tests/ppc32/Makefile.am
+++ b/none/tests/ppc32/Makefile.am
@@ -10,6 +10,7 @@
bug139050-ppc32.vgtest \
ldstrev.stderr.exp ldstrev.stdout.exp ldstrev.vgtest \
jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest \
+ jm-int_other.stderr.exp jm-int_other.stdout.exp jm-int_other.vgtest \
jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest jm-fp.stdout.exp-BE2 \
jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan \
jm-vmx.vgtest \
@@ -32,6 +33,8 @@
test_isa_2_06_part1.stderr.exp test_isa_2_06_part1.stdout.exp test_isa_2_06_part1.vgtest \
test_isa_2_06_part2.stderr.exp test_isa_2_06_part2.stdout.exp test_isa_2_06_part2.vgtest \
test_isa_2_06_part3.stderr.exp test_isa_2_06_part3.stdout.exp test_isa_2_06_part3.vgtest \
+ test_isa_2_06_part2-div.stderr.exp test_isa_2_06_part2-div.stdout.exp test_isa_2_06_part2-div.vgtest \
+ test_isa_2_06_part3-div.stderr.exp test_isa_2_06_part3-div.stdout.exp test_isa_2_06_part3-div.vgtest \
test_dfp1.stderr.exp test_dfp1.stdout.exp test_dfp1.vgtest \
test_dfp2.stderr.exp test_dfp2.stdout.exp test_dfp2.vgtest \
test_dfp2.stdout.exp_Without_dcffix \
diff --git a/none/tests/ppc32/Makefile.in b/none/tests/ppc32/Makefile.in
index ec161c6..cc29cec 100644
--- a/none/tests/ppc32/Makefile.in
+++ b/none/tests/ppc32/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -392,6 +392,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -562,6 +563,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -572,6 +574,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -646,8 +649,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -692,7 +693,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
@@ -722,6 +722,7 @@
bug139050-ppc32.vgtest \
ldstrev.stderr.exp ldstrev.stdout.exp ldstrev.vgtest \
jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest \
+ jm-int_other.stderr.exp jm-int_other.stdout.exp jm-int_other.vgtest \
jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest jm-fp.stdout.exp-BE2 \
jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan \
jm-vmx.vgtest \
@@ -744,6 +745,8 @@
test_isa_2_06_part1.stderr.exp test_isa_2_06_part1.stdout.exp test_isa_2_06_part1.vgtest \
test_isa_2_06_part2.stderr.exp test_isa_2_06_part2.stdout.exp test_isa_2_06_part2.vgtest \
test_isa_2_06_part3.stderr.exp test_isa_2_06_part3.stdout.exp test_isa_2_06_part3.vgtest \
+ test_isa_2_06_part2-div.stderr.exp test_isa_2_06_part2-div.stdout.exp test_isa_2_06_part2-div.vgtest \
+ test_isa_2_06_part3-div.stderr.exp test_isa_2_06_part3-div.stdout.exp test_isa_2_06_part3-div.vgtest \
test_dfp1.stderr.exp test_dfp1.stdout.exp test_dfp1.vgtest \
test_dfp2.stderr.exp test_dfp2.stdout.exp test_dfp2.vgtest \
test_dfp2.stdout.exp_Without_dcffix \
diff --git a/none/tests/ppc32/jm-insns.c b/none/tests/ppc32/jm-insns.c
index 27f9712..e1a7da9 100644
--- a/none/tests/ppc32/jm-insns.c
+++ b/none/tests/ppc32/jm-insns.c
@@ -45,7 +45,7 @@
* I always get the result in r17 and also save XER and CCR for fixed-point
* operations. I also check FPSCR for floating points operations.
*
- * Improvments:
+ * Improvements:
* a more clever FPSCR management is needed: for now, I always test
* the round-to-zero case. Other rounding modes also need to be tested.
*/
@@ -98,7 +98,7 @@
* }
*
*
- * Details of intruction patching for immediate operands
+ * Details of instruction patching for immediate operands
* -----------------------------------------------------
* All the immediate insn test functions are of the form {imm_insn, blr}
* In order to patch one of these functions, we simply copy both insns
@@ -3367,7 +3367,7 @@
/* Power ISA 2.03 support dcbtct and dcbtstct with valid hint values b00000 - 0b00111.
* The ISA 2.06 added support for more valid hint values, but rather than tie ourselves
- * in knots trying to test all permuations of ISAs and valid hint values, we'll just
+ * in knots trying to test all permutations of ISAs and valid hint values, we'll just
* verify some of the base hint values from ISA 2.03.
*
* In a similar vein, in ISA 2.03, dcbtds had valid values of 0b01000 - 0b01010, whereas
@@ -7620,7 +7620,10 @@
#else // #if !defined (USAGE_SIMPLE)
fprintf(stderr,
"Usage: jm-insns [OPTION]\n"
- "\t-i: test integer instructions (default)\n"
+ "\t-i: test integer arithmetic instructions (default)\n"
+ "\t-l: test integer logical instructions (default)\n"
+ "\t-c: test integer compare instructions (default)\n"
+ "\t-L: test integer load/store instructions (default)\n"
"\t-f: test floating point instructions\n"
"\t-a: test altivec instructions\n"
"\t-m: test miscellaneous instructions\n"
@@ -7767,7 +7770,8 @@
#else // #if !defined (USAGE_SIMPLE)
////////////////////////////////////////////////////////////////////////
/* Simple usage:
- ./jm-insns -i => int insns
+ ./jm-insns -i => int arithmetic insns
+ ./jm-insns -l => int logical insns
./jm-insns -f => fp insns
./jm-insns -a => av insns
./jm-insns -m => miscellaneous insns
@@ -7782,10 +7786,10 @@
flags.two_args = 1;
flags.three_args = 1;
// Type
- flags.arith = 1;
- flags.logical = 1;
- flags.compare = 1;
- flags.ldst = 1;
+ flags.arith = 0;
+ flags.logical = 0;
+ flags.compare = 0;
+ flags.ldst = 0;
// Family
flags.integer = 0;
flags.floats = 0;
@@ -7796,22 +7800,51 @@
// Flags
flags.cr = 2;
- while ((c = getopt(argc, argv, "ifmahvA")) != -1) {
+ while ((c = getopt(argc, argv, "ilcLfmahvA")) != -1) {
switch (c) {
case 'i':
+ flags.arith = 1;
+ flags.integer = 1;
+ break;
+ case 'l':
+ flags.logical = 1;
+ flags.integer = 1;
+ break;
+ case 'c':
+ flags.compare = 1;
+ flags.integer = 1;
+ break;
+ case 'L':
+ flags.ldst = 1;
flags.integer = 1;
break;
case 'f':
+ flags.arith = 1;
+ flags.logical = 1;
+ flags.compare = 1;
+ flags.ldst = 1;
flags.floats = 1;
break;
case 'a':
+ flags.arith = 1;
+ flags.logical = 1;
+ flags.compare = 1;
+ flags.ldst = 1;
flags.altivec = 1;
flags.faltivec = 1;
break;
case 'm':
+ flags.arith = 1;
+ flags.logical = 1;
+ flags.compare = 1;
+ flags.ldst = 1;
flags.misc = 1;
break;
case 'A':
+ flags.arith = 1;
+ flags.logical = 1;
+ flags.compare = 1;
+ flags.ldst = 1;
flags.integer = 1;
flags.floats = 1;
flags.altivec = 1;
diff --git a/none/tests/ppc32/jm-int.stdout.exp b/none/tests/ppc32/jm-int.stdout.exp
index 9035084..1fc8598 100644
--- a/none/tests/ppc32/jm-int.stdout.exp
+++ b/none/tests/ppc32/jm-int.stdout.exp
@@ -450,270 +450,6 @@
subfeo. ffffffff, 000f423f => 000f4240 (40000000 00000000)
subfeo. ffffffff, ffffffff => 00000000 (20000000 20000000)
-PPC integer logical insns with two args:
- and 00000000, 00000000 => 00000000 (00000000 00000000)
- and 00000000, 000f423f => 00000000 (00000000 00000000)
- and 00000000, ffffffff => 00000000 (00000000 00000000)
- and 000f423f, 00000000 => 00000000 (00000000 00000000)
- and 000f423f, 000f423f => 000f423f (00000000 00000000)
- and 000f423f, ffffffff => 000f423f (00000000 00000000)
- and ffffffff, 00000000 => 00000000 (00000000 00000000)
- and ffffffff, 000f423f => 000f423f (00000000 00000000)
- and ffffffff, ffffffff => ffffffff (00000000 00000000)
-
- andc 00000000, 00000000 => 00000000 (00000000 00000000)
- andc 00000000, 000f423f => 00000000 (00000000 00000000)
- andc 00000000, ffffffff => 00000000 (00000000 00000000)
- andc 000f423f, 00000000 => 000f423f (00000000 00000000)
- andc 000f423f, 000f423f => 00000000 (00000000 00000000)
- andc 000f423f, ffffffff => 00000000 (00000000 00000000)
- andc ffffffff, 00000000 => ffffffff (00000000 00000000)
- andc ffffffff, 000f423f => fff0bdc0 (00000000 00000000)
- andc ffffffff, ffffffff => 00000000 (00000000 00000000)
-
- eqv 00000000, 00000000 => ffffffff (00000000 00000000)
- eqv 00000000, 000f423f => fff0bdc0 (00000000 00000000)
- eqv 00000000, ffffffff => 00000000 (00000000 00000000)
- eqv 000f423f, 00000000 => fff0bdc0 (00000000 00000000)
- eqv 000f423f, 000f423f => ffffffff (00000000 00000000)
- eqv 000f423f, ffffffff => 000f423f (00000000 00000000)
- eqv ffffffff, 00000000 => 00000000 (00000000 00000000)
- eqv ffffffff, 000f423f => 000f423f (00000000 00000000)
- eqv ffffffff, ffffffff => ffffffff (00000000 00000000)
-
- nand 00000000, 00000000 => ffffffff (00000000 00000000)
- nand 00000000, 000f423f => ffffffff (00000000 00000000)
- nand 00000000, ffffffff => ffffffff (00000000 00000000)
- nand 000f423f, 00000000 => ffffffff (00000000 00000000)
- nand 000f423f, 000f423f => fff0bdc0 (00000000 00000000)
- nand 000f423f, ffffffff => fff0bdc0 (00000000 00000000)
- nand ffffffff, 00000000 => ffffffff (00000000 00000000)
- nand ffffffff, 000f423f => fff0bdc0 (00000000 00000000)
- nand ffffffff, ffffffff => 00000000 (00000000 00000000)
-
- nor 00000000, 00000000 => ffffffff (00000000 00000000)
- nor 00000000, 000f423f => fff0bdc0 (00000000 00000000)
- nor 00000000, ffffffff => 00000000 (00000000 00000000)
- nor 000f423f, 00000000 => fff0bdc0 (00000000 00000000)
- nor 000f423f, 000f423f => fff0bdc0 (00000000 00000000)
- nor 000f423f, ffffffff => 00000000 (00000000 00000000)
- nor ffffffff, 00000000 => 00000000 (00000000 00000000)
- nor ffffffff, 000f423f => 00000000 (00000000 00000000)
- nor ffffffff, ffffffff => 00000000 (00000000 00000000)
-
- or 00000000, 00000000 => 00000000 (00000000 00000000)
- or 00000000, 000f423f => 000f423f (00000000 00000000)
- or 00000000, ffffffff => ffffffff (00000000 00000000)
- or 000f423f, 00000000 => 000f423f (00000000 00000000)
- or 000f423f, 000f423f => 000f423f (00000000 00000000)
- or 000f423f, ffffffff => ffffffff (00000000 00000000)
- or ffffffff, 00000000 => ffffffff (00000000 00000000)
- or ffffffff, 000f423f => ffffffff (00000000 00000000)
- or ffffffff, ffffffff => ffffffff (00000000 00000000)
-
- orc 00000000, 00000000 => ffffffff (00000000 00000000)
- orc 00000000, 000f423f => fff0bdc0 (00000000 00000000)
- orc 00000000, ffffffff => 00000000 (00000000 00000000)
- orc 000f423f, 00000000 => ffffffff (00000000 00000000)
- orc 000f423f, 000f423f => ffffffff (00000000 00000000)
- orc 000f423f, ffffffff => 000f423f (00000000 00000000)
- orc ffffffff, 00000000 => ffffffff (00000000 00000000)
- orc ffffffff, 000f423f => ffffffff (00000000 00000000)
- orc ffffffff, ffffffff => ffffffff (00000000 00000000)
-
- xor 00000000, 00000000 => 00000000 (00000000 00000000)
- xor 00000000, 000f423f => 000f423f (00000000 00000000)
- xor 00000000, ffffffff => ffffffff (00000000 00000000)
- xor 000f423f, 00000000 => 000f423f (00000000 00000000)
- xor 000f423f, 000f423f => 00000000 (00000000 00000000)
- xor 000f423f, ffffffff => fff0bdc0 (00000000 00000000)
- xor ffffffff, 00000000 => ffffffff (00000000 00000000)
- xor ffffffff, 000f423f => fff0bdc0 (00000000 00000000)
- xor ffffffff, ffffffff => 00000000 (00000000 00000000)
-
- slw 00000000, 00000000 => 00000000 (00000000 00000000)
- slw 00000000, 000f423f => 00000000 (00000000 00000000)
- slw 00000000, ffffffff => 00000000 (00000000 00000000)
- slw 000f423f, 00000000 => 000f423f (00000000 00000000)
- slw 000f423f, 000f423f => 00000000 (00000000 00000000)
- slw 000f423f, ffffffff => 00000000 (00000000 00000000)
- slw ffffffff, 00000000 => ffffffff (00000000 00000000)
- slw ffffffff, 000f423f => 00000000 (00000000 00000000)
- slw ffffffff, ffffffff => 00000000 (00000000 00000000)
-
- sraw 00000000, 00000000 => 00000000 (00000000 00000000)
- sraw 00000000, 000f423f => 00000000 (00000000 00000000)
- sraw 00000000, ffffffff => 00000000 (00000000 00000000)
- sraw 000f423f, 00000000 => 000f423f (00000000 00000000)
- sraw 000f423f, 000f423f => 00000000 (00000000 00000000)
- sraw 000f423f, ffffffff => 00000000 (00000000 00000000)
- sraw ffffffff, 00000000 => ffffffff (00000000 00000000)
- sraw ffffffff, 000f423f => ffffffff (00000000 20000000)
- sraw ffffffff, ffffffff => ffffffff (00000000 20000000)
-
- srw 00000000, 00000000 => 00000000 (00000000 00000000)
- srw 00000000, 000f423f => 00000000 (00000000 00000000)
- srw 00000000, ffffffff => 00000000 (00000000 00000000)
- srw 000f423f, 00000000 => 000f423f (00000000 00000000)
- srw 000f423f, 000f423f => 00000000 (00000000 00000000)
- srw 000f423f, ffffffff => 00000000 (00000000 00000000)
- srw ffffffff, 00000000 => ffffffff (00000000 00000000)
- srw ffffffff, 000f423f => 00000000 (00000000 00000000)
- srw ffffffff, ffffffff => 00000000 (00000000 00000000)
-
-PPC integer logical insns with two args with flags update:
- and. 00000000, 00000000 => 00000000 (20000000 00000000)
- and. 00000000, 000f423f => 00000000 (20000000 00000000)
- and. 00000000, ffffffff => 00000000 (20000000 00000000)
- and. 000f423f, 00000000 => 00000000 (20000000 00000000)
- and. 000f423f, 000f423f => 000f423f (40000000 00000000)
- and. 000f423f, ffffffff => 000f423f (40000000 00000000)
- and. ffffffff, 00000000 => 00000000 (20000000 00000000)
- and. ffffffff, 000f423f => 000f423f (40000000 00000000)
- and. ffffffff, ffffffff => ffffffff (80000000 00000000)
-
- andc. 00000000, 00000000 => 00000000 (20000000 00000000)
- andc. 00000000, 000f423f => 00000000 (20000000 00000000)
- andc. 00000000, ffffffff => 00000000 (20000000 00000000)
- andc. 000f423f, 00000000 => 000f423f (40000000 00000000)
- andc. 000f423f, 000f423f => 00000000 (20000000 00000000)
- andc. 000f423f, ffffffff => 00000000 (20000000 00000000)
- andc. ffffffff, 00000000 => ffffffff (80000000 00000000)
- andc. ffffffff, 000f423f => fff0bdc0 (80000000 00000000)
- andc. ffffffff, ffffffff => 00000000 (20000000 00000000)
-
- eqv. 00000000, 00000000 => ffffffff (80000000 00000000)
- eqv. 00000000, 000f423f => fff0bdc0 (80000000 00000000)
- eqv. 00000000, ffffffff => 00000000 (20000000 00000000)
- eqv. 000f423f, 00000000 => fff0bdc0 (80000000 00000000)
- eqv. 000f423f, 000f423f => ffffffff (80000000 00000000)
- eqv. 000f423f, ffffffff => 000f423f (40000000 00000000)
- eqv. ffffffff, 00000000 => 00000000 (20000000 00000000)
- eqv. ffffffff, 000f423f => 000f423f (40000000 00000000)
- eqv. ffffffff, ffffffff => ffffffff (80000000 00000000)
-
- nand. 00000000, 00000000 => ffffffff (80000000 00000000)
- nand. 00000000, 000f423f => ffffffff (80000000 00000000)
- nand. 00000000, ffffffff => ffffffff (80000000 00000000)
- nand. 000f423f, 00000000 => ffffffff (80000000 00000000)
- nand. 000f423f, 000f423f => fff0bdc0 (80000000 00000000)
- nand. 000f423f, ffffffff => fff0bdc0 (80000000 00000000)
- nand. ffffffff, 00000000 => ffffffff (80000000 00000000)
- nand. ffffffff, 000f423f => fff0bdc0 (80000000 00000000)
- nand. ffffffff, ffffffff => 00000000 (20000000 00000000)
-
- nor. 00000000, 00000000 => ffffffff (80000000 00000000)
- nor. 00000000, 000f423f => fff0bdc0 (80000000 00000000)
- nor. 00000000, ffffffff => 00000000 (20000000 00000000)
- nor. 000f423f, 00000000 => fff0bdc0 (80000000 00000000)
- nor. 000f423f, 000f423f => fff0bdc0 (80000000 00000000)
- nor. 000f423f, ffffffff => 00000000 (20000000 00000000)
- nor. ffffffff, 00000000 => 00000000 (20000000 00000000)
- nor. ffffffff, 000f423f => 00000000 (20000000 00000000)
- nor. ffffffff, ffffffff => 00000000 (20000000 00000000)
-
- or. 00000000, 00000000 => 00000000 (20000000 00000000)
- or. 00000000, 000f423f => 000f423f (40000000 00000000)
- or. 00000000, ffffffff => ffffffff (80000000 00000000)
- or. 000f423f, 00000000 => 000f423f (40000000 00000000)
- or. 000f423f, 000f423f => 000f423f (40000000 00000000)
- or. 000f423f, ffffffff => ffffffff (80000000 00000000)
- or. ffffffff, 00000000 => ffffffff (80000000 00000000)
- or. ffffffff, 000f423f => ffffffff (80000000 00000000)
- or. ffffffff, ffffffff => ffffffff (80000000 00000000)
-
- orc. 00000000, 00000000 => ffffffff (80000000 00000000)
- orc. 00000000, 000f423f => fff0bdc0 (80000000 00000000)
- orc. 00000000, ffffffff => 00000000 (20000000 00000000)
- orc. 000f423f, 00000000 => ffffffff (80000000 00000000)
- orc. 000f423f, 000f423f => ffffffff (80000000 00000000)
- orc. 000f423f, ffffffff => 000f423f (40000000 00000000)
- orc. ffffffff, 00000000 => ffffffff (80000000 00000000)
- orc. ffffffff, 000f423f => ffffffff (80000000 00000000)
- orc. ffffffff, ffffffff => ffffffff (80000000 00000000)
-
- xor. 00000000, 00000000 => 00000000 (20000000 00000000)
- xor. 00000000, 000f423f => 000f423f (40000000 00000000)
- xor. 00000000, ffffffff => ffffffff (80000000 00000000)
- xor. 000f423f, 00000000 => 000f423f (40000000 00000000)
- xor. 000f423f, 000f423f => 00000000 (20000000 00000000)
- xor. 000f423f, ffffffff => fff0bdc0 (80000000 00000000)
- xor. ffffffff, 00000000 => ffffffff (80000000 00000000)
- xor. ffffffff, 000f423f => fff0bdc0 (80000000 00000000)
- xor. ffffffff, ffffffff => 00000000 (20000000 00000000)
-
- slw. 00000000, 00000000 => 00000000 (20000000 00000000)
- slw. 00000000, 000f423f => 00000000 (20000000 00000000)
- slw. 00000000, ffffffff => 00000000 (20000000 00000000)
- slw. 000f423f, 00000000 => 000f423f (40000000 00000000)
- slw. 000f423f, 000f423f => 00000000 (20000000 00000000)
- slw. 000f423f, ffffffff => 00000000 (20000000 00000000)
- slw. ffffffff, 00000000 => ffffffff (80000000 00000000)
- slw. ffffffff, 000f423f => 00000000 (20000000 00000000)
- slw. ffffffff, ffffffff => 00000000 (20000000 00000000)
-
- sraw. 00000000, 00000000 => 00000000 (20000000 00000000)
- sraw. 00000000, 000f423f => 00000000 (20000000 00000000)
- sraw. 00000000, ffffffff => 00000000 (20000000 00000000)
- sraw. 000f423f, 00000000 => 000f423f (40000000 00000000)
- sraw. 000f423f, 000f423f => 00000000 (20000000 00000000)
- sraw. 000f423f, ffffffff => 00000000 (20000000 00000000)
- sraw. ffffffff, 00000000 => ffffffff (80000000 00000000)
- sraw. ffffffff, 000f423f => ffffffff (80000000 20000000)
- sraw. ffffffff, ffffffff => ffffffff (80000000 20000000)
-
- srw. 00000000, 00000000 => 00000000 (20000000 00000000)
- srw. 00000000, 000f423f => 00000000 (20000000 00000000)
- srw. 00000000, ffffffff => 00000000 (20000000 00000000)
- srw. 000f423f, 00000000 => 000f423f (40000000 00000000)
- srw. 000f423f, 000f423f => 00000000 (20000000 00000000)
- srw. 000f423f, ffffffff => 00000000 (20000000 00000000)
- srw. ffffffff, 00000000 => ffffffff (80000000 00000000)
- srw. ffffffff, 000f423f => 00000000 (20000000 00000000)
- srw. ffffffff, ffffffff => 00000000 (20000000 00000000)
-
-PPC integer compare insns (two args):
- cmpw 00000000, 00000000 => 00000000 (00200000 00000000)
- cmpw 00000000, 000f423f => 00000000 (00800000 00000000)
- cmpw 00000000, ffffffff => 00000000 (00400000 00000000)
- cmpw 000f423f, 00000000 => 00000000 (00400000 00000000)
- cmpw 000f423f, 000f423f => 00000000 (00200000 00000000)
- cmpw 000f423f, ffffffff => 00000000 (00400000 00000000)
- cmpw ffffffff, 00000000 => 00000000 (00800000 00000000)
- cmpw ffffffff, 000f423f => 00000000 (00800000 00000000)
- cmpw ffffffff, ffffffff => 00000000 (00200000 00000000)
-
- cmplw 00000000, 00000000 => 00000000 (00200000 00000000)
- cmplw 00000000, 000f423f => 00000000 (00800000 00000000)
- cmplw 00000000, ffffffff => 00000000 (00800000 00000000)
- cmplw 000f423f, 00000000 => 00000000 (00400000 00000000)
- cmplw 000f423f, 000f423f => 00000000 (00200000 00000000)
- cmplw 000f423f, ffffffff => 00000000 (00800000 00000000)
- cmplw ffffffff, 00000000 => 00000000 (00400000 00000000)
- cmplw ffffffff, 000f423f => 00000000 (00400000 00000000)
- cmplw ffffffff, ffffffff => 00000000 (00200000 00000000)
-
-PPC integer compare with immediate insns (two args):
- cmpwi 00000000, 00000000 => 00000000 (00200000 00000000)
- cmpwi 00000000, 000003e7 => 00000000 (00800000 00000000)
- cmpwi 00000000, 0000ffff => 00000000 (00400000 00000000)
- cmpwi 000f423f, 00000000 => 00000000 (00400000 00000000)
- cmpwi 000f423f, 000003e7 => 00000000 (00400000 00000000)
- cmpwi 000f423f, 0000ffff => 00000000 (00400000 00000000)
- cmpwi ffffffff, 00000000 => 00000000 (00800000 00000000)
- cmpwi ffffffff, 000003e7 => 00000000 (00800000 00000000)
- cmpwi ffffffff, 0000ffff => 00000000 (00200000 00000000)
-
- cmplwi 00000000, 00000000 => 00000000 (00200000 00000000)
- cmplwi 00000000, 000003e7 => 00000000 (00800000 00000000)
- cmplwi 00000000, 0000ffff => 00000000 (00800000 00000000)
- cmplwi 000f423f, 00000000 => 00000000 (00400000 00000000)
- cmplwi 000f423f, 000003e7 => 00000000 (00400000 00000000)
- cmplwi 000f423f, 0000ffff => 00000000 (00400000 00000000)
- cmplwi ffffffff, 00000000 => 00000000 (00400000 00000000)
- cmplwi ffffffff, 000003e7 => 00000000 (00400000 00000000)
- cmplwi ffffffff, 0000ffff => 00000000 (00400000 00000000)
-
PPC integer arith insns
with one register + one 16 bits immediate args:
addi 00000000, 00000000 => 00000000 (00000000 00000000)
@@ -778,151 +514,6 @@
addic. ffffffff, 000003e7 => 000003e6 (40000000 20000000)
addic. ffffffff, 0000ffff => fffffffe (80000000 20000000)
-PPC integer logical insns
- with one register + one 16 bits immediate args:
- ori 00000000, 00000000 => 00000000 (00000000 00000000)
- ori 00000000, 000003e7 => 000003e7 (00000000 00000000)
- ori 00000000, 0000ffff => 0000ffff (00000000 00000000)
- ori 000f423f, 00000000 => 000f423f (00000000 00000000)
- ori 000f423f, 000003e7 => 000f43ff (00000000 00000000)
- ori 000f423f, 0000ffff => 000fffff (00000000 00000000)
- ori ffffffff, 00000000 => ffffffff (00000000 00000000)
- ori ffffffff, 000003e7 => ffffffff (00000000 00000000)
- ori ffffffff, 0000ffff => ffffffff (00000000 00000000)
-
- oris 00000000, 00000000 => 00000000 (00000000 00000000)
- oris 00000000, 000003e7 => 03e70000 (00000000 00000000)
- oris 00000000, 0000ffff => ffff0000 (00000000 00000000)
- oris 000f423f, 00000000 => 000f423f (00000000 00000000)
- oris 000f423f, 000003e7 => 03ef423f (00000000 00000000)
- oris 000f423f, 0000ffff => ffff423f (00000000 00000000)
- oris ffffffff, 00000000 => ffffffff (00000000 00000000)
- oris ffffffff, 000003e7 => ffffffff (00000000 00000000)
- oris ffffffff, 0000ffff => ffffffff (00000000 00000000)
-
- xori 00000000, 00000000 => 00000000 (00000000 00000000)
- xori 00000000, 000003e7 => 000003e7 (00000000 00000000)
- xori 00000000, 0000ffff => 0000ffff (00000000 00000000)
- xori 000f423f, 00000000 => 000f423f (00000000 00000000)
- xori 000f423f, 000003e7 => 000f41d8 (00000000 00000000)
- xori 000f423f, 0000ffff => 000fbdc0 (00000000 00000000)
- xori ffffffff, 00000000 => ffffffff (00000000 00000000)
- xori ffffffff, 000003e7 => fffffc18 (00000000 00000000)
- xori ffffffff, 0000ffff => ffff0000 (00000000 00000000)
-
- xoris 00000000, 00000000 => 00000000 (00000000 00000000)
- xoris 00000000, 000003e7 => 03e70000 (00000000 00000000)
- xoris 00000000, 0000ffff => ffff0000 (00000000 00000000)
- xoris 000f423f, 00000000 => 000f423f (00000000 00000000)
- xoris 000f423f, 000003e7 => 03e8423f (00000000 00000000)
- xoris 000f423f, 0000ffff => fff0423f (00000000 00000000)
- xoris ffffffff, 00000000 => ffffffff (00000000 00000000)
- xoris ffffffff, 000003e7 => fc18ffff (00000000 00000000)
- xoris ffffffff, 0000ffff => 0000ffff (00000000 00000000)
-
-PPC integer logical insns
- with one register + one 16 bits immediate args with flags update:
- andi. 00000000, 00000000 => 00000000 (20000000 00000000)
- andi. 00000000, 000003e7 => 00000000 (20000000 00000000)
- andi. 00000000, 0000ffff => 00000000 (20000000 00000000)
- andi. 000f423f, 00000000 => 00000000 (20000000 00000000)
- andi. 000f423f, 000003e7 => 00000227 (40000000 00000000)
- andi. 000f423f, 0000ffff => 0000423f (40000000 00000000)
- andi. ffffffff, 00000000 => 00000000 (20000000 00000000)
- andi. ffffffff, 000003e7 => 000003e7 (40000000 00000000)
- andi. ffffffff, 0000ffff => 0000ffff (40000000 00000000)
-
- andis. 00000000, 00000000 => 00000000 (20000000 00000000)
- andis. 00000000, 000003e7 => 00000000 (20000000 00000000)
- andis. 00000000, 0000ffff => 00000000 (20000000 00000000)
- andis. 000f423f, 00000000 => 00000000 (20000000 00000000)
- andis. 000f423f, 000003e7 => 00070000 (40000000 00000000)
- andis. 000f423f, 0000ffff => 000f0000 (40000000 00000000)
- andis. ffffffff, 00000000 => 00000000 (20000000 00000000)
- andis. ffffffff, 000003e7 => 03e70000 (40000000 00000000)
- andis. ffffffff, 0000ffff => ffff0000 (80000000 00000000)
-
-PPC condition register logical insns - two operands:
- crand 00000000, 00000000 => ffff0000 (00000000 00000000)
- crand 00000000, 000f423f => ffff0000 (00000000 00000000)
- crand 00000000, ffffffff => ffff0000 (00000000 00000000)
- crand 000f423f, 00000000 => ffff0000 (00000000 00000000)
- crand 000f423f, 000f423f => ffff0000 (00000000 00000000)
- crand 000f423f, ffffffff => ffff0000 (00000000 00000000)
- crand ffffffff, 00000000 => ffff0000 (00000000 00000000)
- crand ffffffff, 000f423f => ffff0000 (00000000 00000000)
- crand ffffffff, ffffffff => ffff0000 (00000000 00000000)
-
- crandc 00000000, 00000000 => ffff0000 (00000000 00000000)
- crandc 00000000, 000f423f => ffff0000 (00000000 00000000)
- crandc 00000000, ffffffff => ffff0000 (00000000 00000000)
- crandc 000f423f, 00000000 => ffff0000 (00000000 00000000)
- crandc 000f423f, 000f423f => ffff0000 (00000000 00000000)
- crandc 000f423f, ffffffff => ffff0000 (00000000 00000000)
- crandc ffffffff, 00000000 => ffff0000 (00000000 00000000)
- crandc ffffffff, 000f423f => ffff0000 (00000000 00000000)
- crandc ffffffff, ffffffff => ffff0000 (00000000 00000000)
-
- creqv 00000000, 00000000 => ffff0000 (00004000 00000000)
- creqv 00000000, 000f423f => ffff0000 (00004000 00000000)
- creqv 00000000, ffffffff => ffff0000 (00004000 00000000)
- creqv 000f423f, 00000000 => ffff0000 (00004000 00000000)
- creqv 000f423f, 000f423f => ffff0000 (00004000 00000000)
- creqv 000f423f, ffffffff => ffff0000 (00004000 00000000)
- creqv ffffffff, 00000000 => ffff0000 (00004000 00000000)
- creqv ffffffff, 000f423f => ffff0000 (00004000 00000000)
- creqv ffffffff, ffffffff => ffff0000 (00004000 00000000)
-
- crnand 00000000, 00000000 => ffff0000 (00004000 00000000)
- crnand 00000000, 000f423f => ffff0000 (00004000 00000000)
- crnand 00000000, ffffffff => ffff0000 (00004000 00000000)
- crnand 000f423f, 00000000 => ffff0000 (00004000 00000000)
- crnand 000f423f, 000f423f => ffff0000 (00004000 00000000)
- crnand 000f423f, ffffffff => ffff0000 (00004000 00000000)
- crnand ffffffff, 00000000 => ffff0000 (00004000 00000000)
- crnand ffffffff, 000f423f => ffff0000 (00004000 00000000)
- crnand ffffffff, ffffffff => ffff0000 (00004000 00000000)
-
- crnor 00000000, 00000000 => ffff0000 (00004000 00000000)
- crnor 00000000, 000f423f => ffff0000 (00004000 00000000)
- crnor 00000000, ffffffff => ffff0000 (00004000 00000000)
- crnor 000f423f, 00000000 => ffff0000 (00004000 00000000)
- crnor 000f423f, 000f423f => ffff0000 (00004000 00000000)
- crnor 000f423f, ffffffff => ffff0000 (00004000 00000000)
- crnor ffffffff, 00000000 => ffff0000 (00004000 00000000)
- crnor ffffffff, 000f423f => ffff0000 (00004000 00000000)
- crnor ffffffff, ffffffff => ffff0000 (00004000 00000000)
-
- cror 00000000, 00000000 => ffff0000 (00000000 00000000)
- cror 00000000, 000f423f => ffff0000 (00000000 00000000)
- cror 00000000, ffffffff => ffff0000 (00000000 00000000)
- cror 000f423f, 00000000 => ffff0000 (00000000 00000000)
- cror 000f423f, 000f423f => ffff0000 (00000000 00000000)
- cror 000f423f, ffffffff => ffff0000 (00000000 00000000)
- cror ffffffff, 00000000 => ffff0000 (00000000 00000000)
- cror ffffffff, 000f423f => ffff0000 (00000000 00000000)
- cror ffffffff, ffffffff => ffff0000 (00000000 00000000)
-
- crorc 00000000, 00000000 => ffff0000 (00004000 00000000)
- crorc 00000000, 000f423f => ffff0000 (00004000 00000000)
- crorc 00000000, ffffffff => ffff0000 (00004000 00000000)
- crorc 000f423f, 00000000 => ffff0000 (00004000 00000000)
- crorc 000f423f, 000f423f => ffff0000 (00004000 00000000)
- crorc 000f423f, ffffffff => ffff0000 (00004000 00000000)
- crorc ffffffff, 00000000 => ffff0000 (00004000 00000000)
- crorc ffffffff, 000f423f => ffff0000 (00004000 00000000)
- crorc ffffffff, ffffffff => ffff0000 (00004000 00000000)
-
- crxor 00000000, 00000000 => ffff0000 (00000000 00000000)
- crxor 00000000, 000f423f => ffff0000 (00000000 00000000)
- crxor 00000000, ffffffff => ffff0000 (00000000 00000000)
- crxor 000f423f, 00000000 => ffff0000 (00000000 00000000)
- crxor 000f423f, 000f423f => ffff0000 (00000000 00000000)
- crxor 000f423f, ffffffff => ffff0000 (00000000 00000000)
- crxor ffffffff, 00000000 => ffff0000 (00000000 00000000)
- crxor ffffffff, 000f423f => ffff0000 (00000000 00000000)
- crxor ffffffff, ffffffff => ffff0000 (00000000 00000000)
-
PPC integer arith insns with one arg and carry:
addme 00000000 => ffffffff (00000000 00000000)
addme 000f423f => 000f423e (00000000 20000000)
@@ -1037,568 +628,9 @@
subfzeo. 000f423f => fff0bdc1 (80000000 00000000)
subfzeo. ffffffff => 00000001 (40000000 00000000)
-PPC integer logical insns with one arg:
- cntlzw 00000000 => 00000020 (00000000 00000000)
- cntlzw 000f423f => 0000000c (00000000 00000000)
- cntlzw ffffffff => 00000000 (00000000 00000000)
-
- extsb 00000000 => 00000000 (00000000 00000000)
- extsb 000f423f => 0000003f (00000000 00000000)
- extsb ffffffff => ffffffff (00000000 00000000)
-
- extsh 00000000 => 00000000 (00000000 00000000)
- extsh 000f423f => 0000423f (00000000 00000000)
- extsh ffffffff => ffffffff (00000000 00000000)
-
- neg 00000000 => 00000000 (00000000 00000000)
- neg 000f423f => fff0bdc1 (00000000 00000000)
- neg ffffffff => 00000001 (00000000 00000000)
-
- nego 00000000 => 00000000 (00000000 00000000)
- nego 000f423f => fff0bdc1 (00000000 00000000)
- nego ffffffff => 00000001 (00000000 00000000)
-
-PPC integer logical insns with one arg with flags update:
- cntlzw. 00000000 => 00000020 (40000000 00000000)
- cntlzw. 000f423f => 0000000c (40000000 00000000)
- cntlzw. ffffffff => 00000000 (20000000 00000000)
-
- extsb. 00000000 => 00000000 (20000000 00000000)
- extsb. 000f423f => 0000003f (40000000 00000000)
- extsb. ffffffff => ffffffff (80000000 00000000)
-
- extsh. 00000000 => 00000000 (20000000 00000000)
- extsh. 000f423f => 0000423f (40000000 00000000)
- extsh. ffffffff => ffffffff (80000000 00000000)
-
- neg. 00000000 => 00000000 (20000000 00000000)
- neg. 000f423f => fff0bdc1 (80000000 00000000)
- neg. ffffffff => 00000001 (40000000 00000000)
-
- nego. 00000000 => 00000000 (20000000 00000000)
- nego. 000f423f => fff0bdc1 (80000000 00000000)
- nego. ffffffff => 00000001 (40000000 00000000)
-
-PPC logical insns with special forms:
- rlwimi 00000000, 0, 0, 0 => 00000000 (00000000 00000000)
- rlwimi 00000000, 0, 0, 31 => 00000000 (00000000 00000000)
- rlwimi 00000000, 0, 31, 0 => 00000000 (00000000 00000000)
- rlwimi 00000000, 0, 31, 31 => 00000000 (00000000 00000000)
- rlwimi 00000000, 31, 0, 0 => 00000000 (00000000 00000000)
- rlwimi 00000000, 31, 0, 31 => 00000000 (00000000 00000000)
- rlwimi 00000000, 31, 31, 0 => 00000000 (00000000 00000000)
- rlwimi 00000000, 31, 31, 31 => 00000000 (00000000 00000000)
- rlwimi 000f423f, 0, 0, 0 => 00000000 (00000000 00000000)
- rlwimi 000f423f, 0, 0, 31 => 000f423f (00000000 00000000)
- rlwimi 000f423f, 0, 31, 0 => 000f423f (00000000 00000000)
- rlwimi 000f423f, 0, 31, 31 => 000f423f (00000000 00000000)
- rlwimi 000f423f, 31, 0, 0 => 800f423f (00000000 00000000)
- rlwimi 000f423f, 31, 0, 31 => 8007a11f (00000000 00000000)
- rlwimi 000f423f, 31, 31, 0 => 8007a11f (00000000 00000000)
- rlwimi 000f423f, 31, 31, 31 => 8007a11f (00000000 00000000)
- rlwimi ffffffff, 0, 0, 0 => 8007a11f (00000000 00000000)
- rlwimi ffffffff, 0, 0, 31 => ffffffff (00000000 00000000)
- rlwimi ffffffff, 0, 31, 0 => ffffffff (00000000 00000000)
- rlwimi ffffffff, 0, 31, 31 => ffffffff (00000000 00000000)
- rlwimi ffffffff, 31, 0, 0 => ffffffff (00000000 00000000)
- rlwimi ffffffff, 31, 0, 31 => ffffffff (00000000 00000000)
- rlwimi ffffffff, 31, 31, 0 => ffffffff (00000000 00000000)
- rlwimi ffffffff, 31, 31, 31 => ffffffff (00000000 00000000)
-
- rlwinm 00000000, 0, 0, 0 => 00000000 (00000000 00000000)
- rlwinm 00000000, 0, 0, 31 => 00000000 (00000000 00000000)
- rlwinm 00000000, 0, 31, 0 => 00000000 (00000000 00000000)
- rlwinm 00000000, 0, 31, 31 => 00000000 (00000000 00000000)
- rlwinm 00000000, 31, 0, 0 => 00000000 (00000000 00000000)
- rlwinm 00000000, 31, 0, 31 => 00000000 (00000000 00000000)
- rlwinm 00000000, 31, 31, 0 => 00000000 (00000000 00000000)
- rlwinm 00000000, 31, 31, 31 => 00000000 (00000000 00000000)
- rlwinm 000f423f, 0, 0, 0 => 00000000 (00000000 00000000)
- rlwinm 000f423f, 0, 0, 31 => 000f423f (00000000 00000000)
- rlwinm 000f423f, 0, 31, 0 => 00000001 (00000000 00000000)
- rlwinm 000f423f, 0, 31, 31 => 00000001 (00000000 00000000)
- rlwinm 000f423f, 31, 0, 0 => 80000000 (00000000 00000000)
- rlwinm 000f423f, 31, 0, 31 => 8007a11f (00000000 00000000)
- rlwinm 000f423f, 31, 31, 0 => 80000001 (00000000 00000000)
- rlwinm 000f423f, 31, 31, 31 => 00000001 (00000000 00000000)
- rlwinm ffffffff, 0, 0, 0 => 80000000 (00000000 00000000)
- rlwinm ffffffff, 0, 0, 31 => ffffffff (00000000 00000000)
- rlwinm ffffffff, 0, 31, 0 => 80000001 (00000000 00000000)
- rlwinm ffffffff, 0, 31, 31 => 00000001 (00000000 00000000)
- rlwinm ffffffff, 31, 0, 0 => 80000000 (00000000 00000000)
- rlwinm ffffffff, 31, 0, 31 => ffffffff (00000000 00000000)
- rlwinm ffffffff, 31, 31, 0 => 80000001 (00000000 00000000)
- rlwinm ffffffff, 31, 31, 31 => 00000001 (00000000 00000000)
-
- rlwnm 00000000, 00000000, 0, 0 => 00000000 (00000000 00000000)
- rlwnm 00000000, 00000000, 0, 31 => 00000000 (00000000 00000000)
- rlwnm 00000000, 00000000, 31, 0 => 00000000 (00000000 00000000)
- rlwnm 00000000, 00000000, 31, 31 => 00000000 (00000000 00000000)
- rlwnm 00000000, 000f423f, 0, 0 => 00000000 (00000000 00000000)
- rlwnm 00000000, 000f423f, 0, 31 => 00000000 (00000000 00000000)
- rlwnm 00000000, 000f423f, 31, 0 => 00000000 (00000000 00000000)
- rlwnm 00000000, 000f423f, 31, 31 => 00000000 (00000000 00000000)
- rlwnm 00000000, ffffffff, 0, 0 => 00000000 (00000000 00000000)
- rlwnm 00000000, ffffffff, 0, 31 => 00000000 (00000000 00000000)
- rlwnm 00000000, ffffffff, 31, 0 => 00000000 (00000000 00000000)
- rlwnm 00000000, ffffffff, 31, 31 => 00000000 (00000000 00000000)
- rlwnm 000f423f, 00000000, 0, 0 => 00000000 (00000000 00000000)
- rlwnm 000f423f, 00000000, 0, 31 => 000f423f (00000000 00000000)
- rlwnm 000f423f, 00000000, 31, 0 => 00000001 (00000000 00000000)
- rlwnm 000f423f, 00000000, 31, 31 => 00000001 (00000000 00000000)
- rlwnm 000f423f, 000f423f, 0, 0 => 80000000 (00000000 00000000)
- rlwnm 000f423f, 000f423f, 0, 31 => 8007a11f (00000000 00000000)
- rlwnm 000f423f, 000f423f, 31, 0 => 80000001 (00000000 00000000)
- rlwnm 000f423f, 000f423f, 31, 31 => 00000001 (00000000 00000000)
- rlwnm 000f423f, ffffffff, 0, 0 => 80000000 (00000000 00000000)
- rlwnm 000f423f, ffffffff, 0, 31 => 8007a11f (00000000 00000000)
- rlwnm 000f423f, ffffffff, 31, 0 => 80000001 (00000000 00000000)
- rlwnm 000f423f, ffffffff, 31, 31 => 00000001 (00000000 00000000)
- rlwnm ffffffff, 00000000, 0, 0 => 80000000 (00000000 00000000)
- rlwnm ffffffff, 00000000, 0, 31 => ffffffff (00000000 00000000)
- rlwnm ffffffff, 00000000, 31, 0 => 80000001 (00000000 00000000)
- rlwnm ffffffff, 00000000, 31, 31 => 00000001 (00000000 00000000)
- rlwnm ffffffff, 000f423f, 0, 0 => 80000000 (00000000 00000000)
- rlwnm ffffffff, 000f423f, 0, 31 => ffffffff (00000000 00000000)
- rlwnm ffffffff, 000f423f, 31, 0 => 80000001 (00000000 00000000)
- rlwnm ffffffff, 000f423f, 31, 31 => 00000001 (00000000 00000000)
- rlwnm ffffffff, ffffffff, 0, 0 => 80000000 (00000000 00000000)
- rlwnm ffffffff, ffffffff, 0, 31 => ffffffff (00000000 00000000)
- rlwnm ffffffff, ffffffff, 31, 0 => 80000001 (00000000 00000000)
- rlwnm ffffffff, ffffffff, 31, 31 => 00000001 (00000000 00000000)
-
- srawi 00000000, 0 => 00000000 (00000000 00000000)
- srawi 00000000, 31 => 00000000 (00000000 00000000)
- srawi 000f423f, 0 => 000f423f (00000000 00000000)
- srawi 000f423f, 31 => 00000000 (00000000 00000000)
- srawi ffffffff, 0 => ffffffff (00000000 00000000)
- srawi ffffffff, 31 => ffffffff (00000000 20000000)
-
- mfcr (00000000) => 00000000 (00000000 00000000)
- mfcr (000f423f) => 000f423f (000f423f 00000000)
- mfcr (ffffffff) => ffffffff (ffffffff 00000000)
-
- mfspr 1 (00000000) -> mtxer -> mfxer => 00000000
- mfspr 1 (000f423f) -> mtxer -> mfxer => 0000003f
- mfspr 1 (ffffffff) -> mtxer -> mfxer => e000007f
- mfspr 8 (00000000) -> mtlr -> mflr => 00000000
- mfspr 8 (000f423f) -> mtlr -> mflr => 000f423f
- mfspr 8 (ffffffff) -> mtlr -> mflr => ffffffff
- mfspr 9 (00000000) -> mtctr -> mfctr => 00000000
- mfspr 9 (000f423f) -> mtctr -> mfctr => 000f423f
- mfspr 9 (ffffffff) -> mtctr -> mfctr => ffffffff
-
-
-PPC logical insns with special forms with flags update:
- rlwimi. 00000000, 0, 0, 0 => 00000000 (20000000 00000000)
- rlwimi. 00000000, 0, 0, 31 => 00000000 (20000000 00000000)
- rlwimi. 00000000, 0, 31, 0 => 00000000 (20000000 00000000)
- rlwimi. 00000000, 0, 31, 31 => 00000000 (20000000 00000000)
- rlwimi. 00000000, 31, 0, 0 => 00000000 (20000000 00000000)
- rlwimi. 00000000, 31, 0, 31 => 00000000 (20000000 00000000)
- rlwimi. 00000000, 31, 31, 0 => 00000000 (20000000 00000000)
- rlwimi. 00000000, 31, 31, 31 => 00000000 (20000000 00000000)
- rlwimi. 000f423f, 0, 0, 0 => 00000000 (20000000 00000000)
- rlwimi. 000f423f, 0, 0, 31 => 000f423f (40000000 00000000)
- rlwimi. 000f423f, 0, 31, 0 => 000f423f (40000000 00000000)
- rlwimi. 000f423f, 0, 31, 31 => 000f423f (40000000 00000000)
- rlwimi. 000f423f, 31, 0, 0 => 800f423f (80000000 00000000)
- rlwimi. 000f423f, 31, 0, 31 => 8007a11f (80000000 00000000)
- rlwimi. 000f423f, 31, 31, 0 => 8007a11f (80000000 00000000)
- rlwimi. 000f423f, 31, 31, 31 => 8007a11f (80000000 00000000)
- rlwimi. ffffffff, 0, 0, 0 => 8007a11f (80000000 00000000)
- rlwimi. ffffffff, 0, 0, 31 => ffffffff (80000000 00000000)
- rlwimi. ffffffff, 0, 31, 0 => ffffffff (80000000 00000000)
- rlwimi. ffffffff, 0, 31, 31 => ffffffff (80000000 00000000)
- rlwimi. ffffffff, 31, 0, 0 => ffffffff (80000000 00000000)
- rlwimi. ffffffff, 31, 0, 31 => ffffffff (80000000 00000000)
- rlwimi. ffffffff, 31, 31, 0 => ffffffff (80000000 00000000)
- rlwimi. ffffffff, 31, 31, 31 => ffffffff (80000000 00000000)
-
- rlwinm. 00000000, 0, 0, 0 => 00000000 (20000000 00000000)
- rlwinm. 00000000, 0, 0, 31 => 00000000 (20000000 00000000)
- rlwinm. 00000000, 0, 31, 0 => 00000000 (20000000 00000000)
- rlwinm. 00000000, 0, 31, 31 => 00000000 (20000000 00000000)
- rlwinm. 00000000, 31, 0, 0 => 00000000 (20000000 00000000)
- rlwinm. 00000000, 31, 0, 31 => 00000000 (20000000 00000000)
- rlwinm. 00000000, 31, 31, 0 => 00000000 (20000000 00000000)
- rlwinm. 00000000, 31, 31, 31 => 00000000 (20000000 00000000)
- rlwinm. 000f423f, 0, 0, 0 => 00000000 (20000000 00000000)
- rlwinm. 000f423f, 0, 0, 31 => 000f423f (40000000 00000000)
- rlwinm. 000f423f, 0, 31, 0 => 00000001 (40000000 00000000)
- rlwinm. 000f423f, 0, 31, 31 => 00000001 (40000000 00000000)
- rlwinm. 000f423f, 31, 0, 0 => 80000000 (80000000 00000000)
- rlwinm. 000f423f, 31, 0, 31 => 8007a11f (80000000 00000000)
- rlwinm. 000f423f, 31, 31, 0 => 80000001 (80000000 00000000)
- rlwinm. 000f423f, 31, 31, 31 => 00000001 (40000000 00000000)
- rlwinm. ffffffff, 0, 0, 0 => 80000000 (80000000 00000000)
- rlwinm. ffffffff, 0, 0, 31 => ffffffff (80000000 00000000)
- rlwinm. ffffffff, 0, 31, 0 => 80000001 (80000000 00000000)
- rlwinm. ffffffff, 0, 31, 31 => 00000001 (40000000 00000000)
- rlwinm. ffffffff, 31, 0, 0 => 80000000 (80000000 00000000)
- rlwinm. ffffffff, 31, 0, 31 => ffffffff (80000000 00000000)
- rlwinm. ffffffff, 31, 31, 0 => 80000001 (80000000 00000000)
- rlwinm. ffffffff, 31, 31, 31 => 00000001 (40000000 00000000)
-
- rlwnm. 00000000, 00000000, 0, 0 => 00000000 (20000000 00000000)
- rlwnm. 00000000, 00000000, 0, 31 => 00000000 (20000000 00000000)
- rlwnm. 00000000, 00000000, 31, 0 => 00000000 (20000000 00000000)
- rlwnm. 00000000, 00000000, 31, 31 => 00000000 (20000000 00000000)
- rlwnm. 00000000, 000f423f, 0, 0 => 00000000 (20000000 00000000)
- rlwnm. 00000000, 000f423f, 0, 31 => 00000000 (20000000 00000000)
- rlwnm. 00000000, 000f423f, 31, 0 => 00000000 (20000000 00000000)
- rlwnm. 00000000, 000f423f, 31, 31 => 00000000 (20000000 00000000)
- rlwnm. 00000000, ffffffff, 0, 0 => 00000000 (20000000 00000000)
- rlwnm. 00000000, ffffffff, 0, 31 => 00000000 (20000000 00000000)
- rlwnm. 00000000, ffffffff, 31, 0 => 00000000 (20000000 00000000)
- rlwnm. 00000000, ffffffff, 31, 31 => 00000000 (20000000 00000000)
- rlwnm. 000f423f, 00000000, 0, 0 => 00000000 (20000000 00000000)
- rlwnm. 000f423f, 00000000, 0, 31 => 000f423f (40000000 00000000)
- rlwnm. 000f423f, 00000000, 31, 0 => 00000001 (40000000 00000000)
- rlwnm. 000f423f, 00000000, 31, 31 => 00000001 (40000000 00000000)
- rlwnm. 000f423f, 000f423f, 0, 0 => 80000000 (80000000 00000000)
- rlwnm. 000f423f, 000f423f, 0, 31 => 8007a11f (80000000 00000000)
- rlwnm. 000f423f, 000f423f, 31, 0 => 80000001 (80000000 00000000)
- rlwnm. 000f423f, 000f423f, 31, 31 => 00000001 (40000000 00000000)
- rlwnm. 000f423f, ffffffff, 0, 0 => 80000000 (80000000 00000000)
- rlwnm. 000f423f, ffffffff, 0, 31 => 8007a11f (80000000 00000000)
- rlwnm. 000f423f, ffffffff, 31, 0 => 80000001 (80000000 00000000)
- rlwnm. 000f423f, ffffffff, 31, 31 => 00000001 (40000000 00000000)
- rlwnm. ffffffff, 00000000, 0, 0 => 80000000 (80000000 00000000)
- rlwnm. ffffffff, 00000000, 0, 31 => ffffffff (80000000 00000000)
- rlwnm. ffffffff, 00000000, 31, 0 => 80000001 (80000000 00000000)
- rlwnm. ffffffff, 00000000, 31, 31 => 00000001 (40000000 00000000)
- rlwnm. ffffffff, 000f423f, 0, 0 => 80000000 (80000000 00000000)
- rlwnm. ffffffff, 000f423f, 0, 31 => ffffffff (80000000 00000000)
- rlwnm. ffffffff, 000f423f, 31, 0 => 80000001 (80000000 00000000)
- rlwnm. ffffffff, 000f423f, 31, 31 => 00000001 (40000000 00000000)
- rlwnm. ffffffff, ffffffff, 0, 0 => 80000000 (80000000 00000000)
- rlwnm. ffffffff, ffffffff, 0, 31 => ffffffff (80000000 00000000)
- rlwnm. ffffffff, ffffffff, 31, 0 => 80000001 (80000000 00000000)
- rlwnm. ffffffff, ffffffff, 31, 31 => 00000001 (40000000 00000000)
-
- srawi. 00000000, 0 => 00000000 (20000000 00000000)
- srawi. 00000000, 31 => 00000000 (20000000 00000000)
- srawi. 000f423f, 0 => 000f423f (40000000 00000000)
- srawi. 000f423f, 31 => 00000000 (20000000 00000000)
- srawi. ffffffff, 0 => ffffffff (80000000 00000000)
- srawi. ffffffff, 31 => ffffffff (80000000 20000000)
-
- mcrf 0, 0 (00000000) => (00000000 00000000)
- mcrf 0, 7 (00000000) => (00000000 00000000)
- mcrf 7, 0 (00000000) => (00000000 00000000)
- mcrf 7, 7 (00000000) => (00000000 00000000)
- mcrf 0, 0 (000f423f) => (000f423f 00000000)
- mcrf 0, 7 (000f423f) => (f00f423f 00000000)
- mcrf 7, 0 (000f423f) => (000f4230 00000000)
- mcrf 7, 7 (000f423f) => (000f423f 00000000)
- mcrf 0, 0 (ffffffff) => (ffffffff 00000000)
- mcrf 0, 7 (ffffffff) => (ffffffff 00000000)
- mcrf 7, 0 (ffffffff) => (ffffffff 00000000)
- mcrf 7, 7 (ffffffff) => (ffffffff 00000000)
-
- mcrxr 0 (00000000) => (00000000 00000000)
- mcrxr 1 (00000000) => (00000000 00000000)
- mcrxr 2 (00000000) => (00000000 00000000)
- mcrxr 3 (00000000) => (00000000 00000000)
- mcrxr 4 (00000000) => (00000000 00000000)
- mcrxr 5 (00000000) => (00000000 00000000)
- mcrxr 6 (00000000) => (00000000 00000000)
- mcrxr 7 (00000000) => (00000000 00000000)
- mcrxr 0 (10000000) => (00000000 00000000)
- mcrxr 1 (10000000) => (00000000 00000000)
- mcrxr 2 (10000000) => (00000000 00000000)
- mcrxr 3 (10000000) => (00000000 00000000)
- mcrxr 4 (10000000) => (00000000 00000000)
- mcrxr 5 (10000000) => (00000000 00000000)
- mcrxr 6 (10000000) => (00000000 00000000)
- mcrxr 7 (10000000) => (00000000 00000000)
- mcrxr 0 (20000000) => (20000000 00000000)
- mcrxr 1 (20000000) => (02000000 00000000)
- mcrxr 2 (20000000) => (00200000 00000000)
- mcrxr 3 (20000000) => (00020000 00000000)
- mcrxr 4 (20000000) => (00002000 00000000)
- mcrxr 5 (20000000) => (00000200 00000000)
- mcrxr 6 (20000000) => (00000020 00000000)
- mcrxr 7 (20000000) => (00000002 00000000)
- mcrxr 0 (30000000) => (20000000 00000000)
- mcrxr 1 (30000000) => (02000000 00000000)
- mcrxr 2 (30000000) => (00200000 00000000)
- mcrxr 3 (30000000) => (00020000 00000000)
- mcrxr 4 (30000000) => (00002000 00000000)
- mcrxr 5 (30000000) => (00000200 00000000)
- mcrxr 6 (30000000) => (00000020 00000000)
- mcrxr 7 (30000000) => (00000002 00000000)
- mcrxr 0 (40000000) => (40000000 00000000)
- mcrxr 1 (40000000) => (04000000 00000000)
- mcrxr 2 (40000000) => (00400000 00000000)
- mcrxr 3 (40000000) => (00040000 00000000)
- mcrxr 4 (40000000) => (00004000 00000000)
- mcrxr 5 (40000000) => (00000400 00000000)
- mcrxr 6 (40000000) => (00000040 00000000)
- mcrxr 7 (40000000) => (00000004 00000000)
- mcrxr 0 (50000000) => (40000000 00000000)
- mcrxr 1 (50000000) => (04000000 00000000)
- mcrxr 2 (50000000) => (00400000 00000000)
- mcrxr 3 (50000000) => (00040000 00000000)
- mcrxr 4 (50000000) => (00004000 00000000)
- mcrxr 5 (50000000) => (00000400 00000000)
- mcrxr 6 (50000000) => (00000040 00000000)
- mcrxr 7 (50000000) => (00000004 00000000)
- mcrxr 0 (60000000) => (60000000 00000000)
- mcrxr 1 (60000000) => (06000000 00000000)
- mcrxr 2 (60000000) => (00600000 00000000)
- mcrxr 3 (60000000) => (00060000 00000000)
- mcrxr 4 (60000000) => (00006000 00000000)
- mcrxr 5 (60000000) => (00000600 00000000)
- mcrxr 6 (60000000) => (00000060 00000000)
- mcrxr 7 (60000000) => (00000006 00000000)
- mcrxr 0 (70000000) => (60000000 00000000)
- mcrxr 1 (70000000) => (06000000 00000000)
- mcrxr 2 (70000000) => (00600000 00000000)
- mcrxr 3 (70000000) => (00060000 00000000)
- mcrxr 4 (70000000) => (00006000 00000000)
- mcrxr 5 (70000000) => (00000600 00000000)
- mcrxr 6 (70000000) => (00000060 00000000)
- mcrxr 7 (70000000) => (00000006 00000000)
- mcrxr 0 (80000000) => (80000000 00000000)
- mcrxr 1 (80000000) => (08000000 00000000)
- mcrxr 2 (80000000) => (00800000 00000000)
- mcrxr 3 (80000000) => (00080000 00000000)
- mcrxr 4 (80000000) => (00008000 00000000)
- mcrxr 5 (80000000) => (00000800 00000000)
- mcrxr 6 (80000000) => (00000080 00000000)
- mcrxr 7 (80000000) => (00000008 00000000)
- mcrxr 0 (90000000) => (80000000 00000000)
- mcrxr 1 (90000000) => (08000000 00000000)
- mcrxr 2 (90000000) => (00800000 00000000)
- mcrxr 3 (90000000) => (00080000 00000000)
- mcrxr 4 (90000000) => (00008000 00000000)
- mcrxr 5 (90000000) => (00000800 00000000)
- mcrxr 6 (90000000) => (00000080 00000000)
- mcrxr 7 (90000000) => (00000008 00000000)
- mcrxr 0 (a0000000) => (a0000000 00000000)
- mcrxr 1 (a0000000) => (0a000000 00000000)
- mcrxr 2 (a0000000) => (00a00000 00000000)
- mcrxr 3 (a0000000) => (000a0000 00000000)
- mcrxr 4 (a0000000) => (0000a000 00000000)
- mcrxr 5 (a0000000) => (00000a00 00000000)
- mcrxr 6 (a0000000) => (000000a0 00000000)
- mcrxr 7 (a0000000) => (0000000a 00000000)
- mcrxr 0 (b0000000) => (a0000000 00000000)
- mcrxr 1 (b0000000) => (0a000000 00000000)
- mcrxr 2 (b0000000) => (00a00000 00000000)
- mcrxr 3 (b0000000) => (000a0000 00000000)
- mcrxr 4 (b0000000) => (0000a000 00000000)
- mcrxr 5 (b0000000) => (00000a00 00000000)
- mcrxr 6 (b0000000) => (000000a0 00000000)
- mcrxr 7 (b0000000) => (0000000a 00000000)
- mcrxr 0 (c0000000) => (c0000000 00000000)
- mcrxr 1 (c0000000) => (0c000000 00000000)
- mcrxr 2 (c0000000) => (00c00000 00000000)
- mcrxr 3 (c0000000) => (000c0000 00000000)
- mcrxr 4 (c0000000) => (0000c000 00000000)
- mcrxr 5 (c0000000) => (00000c00 00000000)
- mcrxr 6 (c0000000) => (000000c0 00000000)
- mcrxr 7 (c0000000) => (0000000c 00000000)
- mcrxr 0 (d0000000) => (c0000000 00000000)
- mcrxr 1 (d0000000) => (0c000000 00000000)
- mcrxr 2 (d0000000) => (00c00000 00000000)
- mcrxr 3 (d0000000) => (000c0000 00000000)
- mcrxr 4 (d0000000) => (0000c000 00000000)
- mcrxr 5 (d0000000) => (00000c00 00000000)
- mcrxr 6 (d0000000) => (000000c0 00000000)
- mcrxr 7 (d0000000) => (0000000c 00000000)
- mcrxr 0 (e0000000) => (e0000000 00000000)
- mcrxr 1 (e0000000) => (0e000000 00000000)
- mcrxr 2 (e0000000) => (00e00000 00000000)
- mcrxr 3 (e0000000) => (000e0000 00000000)
- mcrxr 4 (e0000000) => (0000e000 00000000)
- mcrxr 5 (e0000000) => (00000e00 00000000)
- mcrxr 6 (e0000000) => (000000e0 00000000)
- mcrxr 7 (e0000000) => (0000000e 00000000)
- mcrxr 0 (f0000000) => (e0000000 00000000)
- mcrxr 1 (f0000000) => (0e000000 00000000)
- mcrxr 2 (f0000000) => (00e00000 00000000)
- mcrxr 3 (f0000000) => (000e0000 00000000)
- mcrxr 4 (f0000000) => (0000e000 00000000)
- mcrxr 5 (f0000000) => (00000e00 00000000)
- mcrxr 6 (f0000000) => (000000e0 00000000)
- mcrxr 7 (f0000000) => (0000000e 00000000)
-
- mtcrf 0, 00000000 => (00000000 00000000)
- mtcrf 99, 00000000 => (00000000 00000000)
- mtcrf 198, 00000000 => (00000000 00000000)
- mtcrf 0, 000f423f => (00000000 00000000)
- mtcrf 99, 000f423f => (0000003f 00000000)
- mtcrf 198, 000f423f => (00000230 00000000)
- mtcrf 0, ffffffff => (00000000 00000000)
- mtcrf 99, ffffffff => (0ff000ff 00000000)
- mtcrf 198, ffffffff => (ff000ff0 00000000)
-
-PPC integer load insns
- with one register + one 16 bits immediate args with flags update:
- lbz 0, (00000000) => 00000000, 0 (00000000 00000000)
- lbz 3, (000f423f) => 00000000, 0 (00000000 00000000)
- lbz 7, (ffffffff) => 0000003f, 0 (00000000 00000000)
- lbz 1, (ffffffff) => 000000ff, 0 (00000000 00000000)
- lbz -3, (000f423f) => 0000000f, 0 (00000000 00000000)
- lbz -7, (00000000) => 00000000, 0 (00000000 00000000)
-
- lbzu 0, (00000000) => 00000000, 0 (00000000 00000000)
- lbzu 3, (000f423f) => 00000000, 3 (00000000 00000000)
- lbzu 7, (ffffffff) => 0000003f, 7 (00000000 00000000)
- lbzu 1, (ffffffff) => 000000ff, 1 (00000000 00000000)
- lbzu -3, (000f423f) => 0000000f, -3 (00000000 00000000)
- lbzu -7, (00000000) => 00000000, -7 (00000000 00000000)
-
- lha 0, (00000000) => 00000000, 0 (00000000 00000000)
- lha 3, (000f423f) => 00000000, 0 (00000000 00000000)
- lha 7, (ffffffff) => 00003fff, 0 (00000000 00000000)
- lha 1, (ffffffff) => ffffffff, 0 (00000000 00000000)
- lha -3, (000f423f) => 00000f42, 0 (00000000 00000000)
- lha -7, (00000000) => 00000000, 0 (00000000 00000000)
-
- lhau 0, (00000000) => 00000000, 0 (00000000 00000000)
- lhau 3, (000f423f) => 00000000, 3 (00000000 00000000)
- lhau 7, (ffffffff) => 00003fff, 7 (00000000 00000000)
- lhau 1, (ffffffff) => ffffffff, 1 (00000000 00000000)
- lhau -3, (000f423f) => 00000f42, -3 (00000000 00000000)
- lhau -7, (00000000) => 00000000, -7 (00000000 00000000)
-
- lhz 0, (00000000) => 00000000, 0 (00000000 00000000)
- lhz 3, (000f423f) => 00000000, 0 (00000000 00000000)
- lhz 7, (ffffffff) => 00003fff, 0 (00000000 00000000)
- lhz 1, (ffffffff) => 0000ffff, 0 (00000000 00000000)
- lhz -3, (000f423f) => 00000f42, 0 (00000000 00000000)
- lhz -7, (00000000) => 00000000, 0 (00000000 00000000)
-
- lhzu 0, (00000000) => 00000000, 0 (00000000 00000000)
- lhzu 3, (000f423f) => 00000000, 3 (00000000 00000000)
- lhzu 7, (ffffffff) => 00003fff, 7 (00000000 00000000)
- lhzu 1, (ffffffff) => 0000ffff, 1 (00000000 00000000)
- lhzu -3, (000f423f) => 00000f42, -3 (00000000 00000000)
- lhzu -7, (00000000) => 00000000, -7 (00000000 00000000)
-
- lwz 0, (00000000) => 00000000, 0 (00000000 00000000)
- lwz 3, (000f423f) => 00000f42, 0 (00000000 00000000)
- lwz 7, (ffffffff) => 3fffffff, 0 (00000000 00000000)
- lwz 1, (ffffffff) => ffffff00, 0 (00000000 00000000)
- lwz -3, (000f423f) => 0f423fff, 0 (00000000 00000000)
- lwz -7, (00000000) => 00000000, 0 (00000000 00000000)
-
- lwzu 0, (00000000) => 00000000, 0 (00000000 00000000)
- lwzu 3, (000f423f) => 00000f42, 3 (00000000 00000000)
- lwzu 7, (ffffffff) => 3fffffff, 7 (00000000 00000000)
- lwzu 1, (ffffffff) => ffffff00, 1 (00000000 00000000)
- lwzu -3, (000f423f) => 0f423fff, -3 (00000000 00000000)
- lwzu -7, (00000000) => 00000000, -7 (00000000 00000000)
-
-PPC integer load insns with two register args:
- lbzx 0 (00000000) => 00000000, 0 (00000000 00000000)
- lbzx 4 (000f423f) => 00000000, 0 (00000000 00000000)
- lbzx 8 (ffffffff) => 000000ff, 0 (00000000 00000000)
-
- lbzux 0 (00000000) => 00000000, 0 (00000000 00000000)
- lbzux 4 (000f423f) => 00000000, 4 (00000000 00000000)
- lbzux 8 (ffffffff) => 000000ff, 8 (00000000 00000000)
-
- lhax 0 (00000000) => 00000000, 0 (00000000 00000000)
- lhax 4 (000f423f) => 0000000f, 0 (00000000 00000000)
- lhax 8 (ffffffff) => ffffffff, 0 (00000000 00000000)
-
- lhaux 0 (00000000) => 00000000, 0 (00000000 00000000)
- lhaux 4 (000f423f) => 0000000f, 4 (00000000 00000000)
- lhaux 8 (ffffffff) => ffffffff, 8 (00000000 00000000)
-
- lhzx 0 (00000000) => 00000000, 0 (00000000 00000000)
- lhzx 4 (000f423f) => 0000000f, 0 (00000000 00000000)
- lhzx 8 (ffffffff) => 0000ffff, 0 (00000000 00000000)
-
- lhzux 0 (00000000) => 00000000, 0 (00000000 00000000)
- lhzux 4 (000f423f) => 0000000f, 4 (00000000 00000000)
- lhzux 8 (ffffffff) => 0000ffff, 8 (00000000 00000000)
-
- lwzx 0 (00000000) => 00000000, 0 (00000000 00000000)
- lwzx 4 (000f423f) => 000f423f, 0 (00000000 00000000)
- lwzx 8 (ffffffff) => ffffffff, 0 (00000000 00000000)
-
- lwzux 0 (00000000) => 00000000, 0 (00000000 00000000)
- lwzux 4 (000f423f) => 000f423f, 4 (00000000 00000000)
- lwzux 8 (ffffffff) => ffffffff, 8 (00000000 00000000)
-
-PPC integer store insns
- with one register + one 16 bits immediate args with flags update:
- stb 00000000, 0 => 00000000, 0 (00000000 00000000)
- stb 000f423f, 4 => 3f000000, 0 (00000000 00000000)
- stb ffffffff, 8 => ff000000, 0 (00000000 00000000)
- stb 00000000, -8 => 00000000, 0 (00000000 00000000)
- stb 000f423f, -4 => 3f000000, 0 (00000000 00000000)
- stb ffffffff, 0 => ff000000, 0 (00000000 00000000)
-
- stbu 00000000, 0 => 00000000, 0 (00000000 00000000)
- stbu 000f423f, 4 => 3f000000, 4 (00000000 00000000)
- stbu ffffffff, 8 => ff000000, 8 (00000000 00000000)
- stbu 00000000, -8 => 00000000, -8 (00000000 00000000)
- stbu 000f423f, -4 => 3f000000, -4 (00000000 00000000)
- stbu ffffffff, 0 => ff000000, 0 (00000000 00000000)
-
- sth 00000000, 0 => 00000000, 0 (00000000 00000000)
- sth 000f423f, 4 => 423f0000, 0 (00000000 00000000)
- sth ffffffff, 8 => ffff0000, 0 (00000000 00000000)
- sth 00000000, -8 => 00000000, 0 (00000000 00000000)
- sth 000f423f, -4 => 423f0000, 0 (00000000 00000000)
- sth ffffffff, 0 => ffff0000, 0 (00000000 00000000)
-
- sthu 00000000, 0 => 00000000, 0 (00000000 00000000)
- sthu 000f423f, 4 => 423f0000, 4 (00000000 00000000)
- sthu ffffffff, 8 => ffff0000, 8 (00000000 00000000)
- sthu 00000000, -8 => 00000000, -8 (00000000 00000000)
- sthu 000f423f, -4 => 423f0000, -4 (00000000 00000000)
- sthu ffffffff, 0 => ffff0000, 0 (00000000 00000000)
-
- stw 00000000, 0 => 00000000, 0 (00000000 00000000)
- stw 000f423f, 4 => 000f423f, 0 (00000000 00000000)
- stw ffffffff, 8 => ffffffff, 0 (00000000 00000000)
- stw 00000000, -8 => 00000000, 0 (00000000 00000000)
- stw 000f423f, -4 => 000f423f, 0 (00000000 00000000)
- stw ffffffff, 0 => ffffffff, 0 (00000000 00000000)
-
- stwu 00000000, 0 => 00000000, 0 (00000000 00000000)
- stwu 000f423f, 4 => 000f423f, 4 (00000000 00000000)
- stwu ffffffff, 8 => ffffffff, 8 (00000000 00000000)
- stwu 00000000, -8 => 00000000, -8 (00000000 00000000)
- stwu 000f423f, -4 => 000f423f, -4 (00000000 00000000)
- stwu ffffffff, 0 => ffffffff, 0 (00000000 00000000)
-
-PPC integer store insns with three register args:
- stbx 00000000, 0 => 00000000, 0 (00000000 00000000)
- stbx 000f423f, 4 => 3f000000, 0 (00000000 00000000)
- stbx ffffffff, 8 => ff000000, 0 (00000000 00000000)
-
- stbux 00000000, 0 => 00000000, 0 (00000000 00000000)
- stbux 000f423f, 4 => 3f000000, 4 (00000000 00000000)
- stbux ffffffff, 8 => ff000000, 8 (00000000 00000000)
-
- sthx 00000000, 0 => 00000000, 0 (00000000 00000000)
- sthx 000f423f, 4 => 423f0000, 0 (00000000 00000000)
- sthx ffffffff, 8 => ffff0000, 0 (00000000 00000000)
-
- sthux 00000000, 0 => 00000000, 0 (00000000 00000000)
- sthux 000f423f, 4 => 423f0000, 4 (00000000 00000000)
- sthux ffffffff, 8 => ffff0000, 8 (00000000 00000000)
-
- stwx 00000000, 0 => 00000000, 0 (00000000 00000000)
- stwx 000f423f, 4 => 000f423f, 0 (00000000 00000000)
- stwx ffffffff, 8 => ffffffff, 0 (00000000 00000000)
-
- stwux 00000000, 0 => 00000000, 0 (00000000 00000000)
- stwux 000f423f, 4 => 000f423f, 4 (00000000 00000000)
- stwux ffffffff, 8 => ffffffff, 8 (00000000 00000000)
-
PPC integer population count with one register args, no flags:
popcntb 00000000 => 00000000 (00000000 00000000)
popcntb 000f423f => 00040206 (00000000 00000000)
popcntb ffffffff => 08080808 (00000000 00000000)
-All done. Tested 155 different instructions
+All done. Tested 63 different instructions
diff --git a/none/tests/ppc32/jm-int_other.stderr.exp b/none/tests/ppc32/jm-int_other.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/none/tests/ppc32/jm-int_other.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/none/tests/ppc32/jm-int_other.stdout.exp b/none/tests/ppc32/jm-int_other.stdout.exp
new file mode 100644
index 0000000..577ddd1
--- /dev/null
+++ b/none/tests/ppc32/jm-int_other.stdout.exp
@@ -0,0 +1,969 @@
+PPC integer logical insns with two args:
+ and 00000000, 00000000 => 00000000 (00000000 00000000)
+ and 00000000, 000f423f => 00000000 (00000000 00000000)
+ and 00000000, ffffffff => 00000000 (00000000 00000000)
+ and 000f423f, 00000000 => 00000000 (00000000 00000000)
+ and 000f423f, 000f423f => 000f423f (00000000 00000000)
+ and 000f423f, ffffffff => 000f423f (00000000 00000000)
+ and ffffffff, 00000000 => 00000000 (00000000 00000000)
+ and ffffffff, 000f423f => 000f423f (00000000 00000000)
+ and ffffffff, ffffffff => ffffffff (00000000 00000000)
+
+ andc 00000000, 00000000 => 00000000 (00000000 00000000)
+ andc 00000000, 000f423f => 00000000 (00000000 00000000)
+ andc 00000000, ffffffff => 00000000 (00000000 00000000)
+ andc 000f423f, 00000000 => 000f423f (00000000 00000000)
+ andc 000f423f, 000f423f => 00000000 (00000000 00000000)
+ andc 000f423f, ffffffff => 00000000 (00000000 00000000)
+ andc ffffffff, 00000000 => ffffffff (00000000 00000000)
+ andc ffffffff, 000f423f => fff0bdc0 (00000000 00000000)
+ andc ffffffff, ffffffff => 00000000 (00000000 00000000)
+
+ eqv 00000000, 00000000 => ffffffff (00000000 00000000)
+ eqv 00000000, 000f423f => fff0bdc0 (00000000 00000000)
+ eqv 00000000, ffffffff => 00000000 (00000000 00000000)
+ eqv 000f423f, 00000000 => fff0bdc0 (00000000 00000000)
+ eqv 000f423f, 000f423f => ffffffff (00000000 00000000)
+ eqv 000f423f, ffffffff => 000f423f (00000000 00000000)
+ eqv ffffffff, 00000000 => 00000000 (00000000 00000000)
+ eqv ffffffff, 000f423f => 000f423f (00000000 00000000)
+ eqv ffffffff, ffffffff => ffffffff (00000000 00000000)
+
+ nand 00000000, 00000000 => ffffffff (00000000 00000000)
+ nand 00000000, 000f423f => ffffffff (00000000 00000000)
+ nand 00000000, ffffffff => ffffffff (00000000 00000000)
+ nand 000f423f, 00000000 => ffffffff (00000000 00000000)
+ nand 000f423f, 000f423f => fff0bdc0 (00000000 00000000)
+ nand 000f423f, ffffffff => fff0bdc0 (00000000 00000000)
+ nand ffffffff, 00000000 => ffffffff (00000000 00000000)
+ nand ffffffff, 000f423f => fff0bdc0 (00000000 00000000)
+ nand ffffffff, ffffffff => 00000000 (00000000 00000000)
+
+ nor 00000000, 00000000 => ffffffff (00000000 00000000)
+ nor 00000000, 000f423f => fff0bdc0 (00000000 00000000)
+ nor 00000000, ffffffff => 00000000 (00000000 00000000)
+ nor 000f423f, 00000000 => fff0bdc0 (00000000 00000000)
+ nor 000f423f, 000f423f => fff0bdc0 (00000000 00000000)
+ nor 000f423f, ffffffff => 00000000 (00000000 00000000)
+ nor ffffffff, 00000000 => 00000000 (00000000 00000000)
+ nor ffffffff, 000f423f => 00000000 (00000000 00000000)
+ nor ffffffff, ffffffff => 00000000 (00000000 00000000)
+
+ or 00000000, 00000000 => 00000000 (00000000 00000000)
+ or 00000000, 000f423f => 000f423f (00000000 00000000)
+ or 00000000, ffffffff => ffffffff (00000000 00000000)
+ or 000f423f, 00000000 => 000f423f (00000000 00000000)
+ or 000f423f, 000f423f => 000f423f (00000000 00000000)
+ or 000f423f, ffffffff => ffffffff (00000000 00000000)
+ or ffffffff, 00000000 => ffffffff (00000000 00000000)
+ or ffffffff, 000f423f => ffffffff (00000000 00000000)
+ or ffffffff, ffffffff => ffffffff (00000000 00000000)
+
+ orc 00000000, 00000000 => ffffffff (00000000 00000000)
+ orc 00000000, 000f423f => fff0bdc0 (00000000 00000000)
+ orc 00000000, ffffffff => 00000000 (00000000 00000000)
+ orc 000f423f, 00000000 => ffffffff (00000000 00000000)
+ orc 000f423f, 000f423f => ffffffff (00000000 00000000)
+ orc 000f423f, ffffffff => 000f423f (00000000 00000000)
+ orc ffffffff, 00000000 => ffffffff (00000000 00000000)
+ orc ffffffff, 000f423f => ffffffff (00000000 00000000)
+ orc ffffffff, ffffffff => ffffffff (00000000 00000000)
+
+ xor 00000000, 00000000 => 00000000 (00000000 00000000)
+ xor 00000000, 000f423f => 000f423f (00000000 00000000)
+ xor 00000000, ffffffff => ffffffff (00000000 00000000)
+ xor 000f423f, 00000000 => 000f423f (00000000 00000000)
+ xor 000f423f, 000f423f => 00000000 (00000000 00000000)
+ xor 000f423f, ffffffff => fff0bdc0 (00000000 00000000)
+ xor ffffffff, 00000000 => ffffffff (00000000 00000000)
+ xor ffffffff, 000f423f => fff0bdc0 (00000000 00000000)
+ xor ffffffff, ffffffff => 00000000 (00000000 00000000)
+
+ slw 00000000, 00000000 => 00000000 (00000000 00000000)
+ slw 00000000, 000f423f => 00000000 (00000000 00000000)
+ slw 00000000, ffffffff => 00000000 (00000000 00000000)
+ slw 000f423f, 00000000 => 000f423f (00000000 00000000)
+ slw 000f423f, 000f423f => 00000000 (00000000 00000000)
+ slw 000f423f, ffffffff => 00000000 (00000000 00000000)
+ slw ffffffff, 00000000 => ffffffff (00000000 00000000)
+ slw ffffffff, 000f423f => 00000000 (00000000 00000000)
+ slw ffffffff, ffffffff => 00000000 (00000000 00000000)
+
+ sraw 00000000, 00000000 => 00000000 (00000000 00000000)
+ sraw 00000000, 000f423f => 00000000 (00000000 00000000)
+ sraw 00000000, ffffffff => 00000000 (00000000 00000000)
+ sraw 000f423f, 00000000 => 000f423f (00000000 00000000)
+ sraw 000f423f, 000f423f => 00000000 (00000000 00000000)
+ sraw 000f423f, ffffffff => 00000000 (00000000 00000000)
+ sraw ffffffff, 00000000 => ffffffff (00000000 00000000)
+ sraw ffffffff, 000f423f => ffffffff (00000000 20000000)
+ sraw ffffffff, ffffffff => ffffffff (00000000 20000000)
+
+ srw 00000000, 00000000 => 00000000 (00000000 00000000)
+ srw 00000000, 000f423f => 00000000 (00000000 00000000)
+ srw 00000000, ffffffff => 00000000 (00000000 00000000)
+ srw 000f423f, 00000000 => 000f423f (00000000 00000000)
+ srw 000f423f, 000f423f => 00000000 (00000000 00000000)
+ srw 000f423f, ffffffff => 00000000 (00000000 00000000)
+ srw ffffffff, 00000000 => ffffffff (00000000 00000000)
+ srw ffffffff, 000f423f => 00000000 (00000000 00000000)
+ srw ffffffff, ffffffff => 00000000 (00000000 00000000)
+
+PPC integer logical insns with two args with flags update:
+ and. 00000000, 00000000 => 00000000 (20000000 00000000)
+ and. 00000000, 000f423f => 00000000 (20000000 00000000)
+ and. 00000000, ffffffff => 00000000 (20000000 00000000)
+ and. 000f423f, 00000000 => 00000000 (20000000 00000000)
+ and. 000f423f, 000f423f => 000f423f (40000000 00000000)
+ and. 000f423f, ffffffff => 000f423f (40000000 00000000)
+ and. ffffffff, 00000000 => 00000000 (20000000 00000000)
+ and. ffffffff, 000f423f => 000f423f (40000000 00000000)
+ and. ffffffff, ffffffff => ffffffff (80000000 00000000)
+
+ andc. 00000000, 00000000 => 00000000 (20000000 00000000)
+ andc. 00000000, 000f423f => 00000000 (20000000 00000000)
+ andc. 00000000, ffffffff => 00000000 (20000000 00000000)
+ andc. 000f423f, 00000000 => 000f423f (40000000 00000000)
+ andc. 000f423f, 000f423f => 00000000 (20000000 00000000)
+ andc. 000f423f, ffffffff => 00000000 (20000000 00000000)
+ andc. ffffffff, 00000000 => ffffffff (80000000 00000000)
+ andc. ffffffff, 000f423f => fff0bdc0 (80000000 00000000)
+ andc. ffffffff, ffffffff => 00000000 (20000000 00000000)
+
+ eqv. 00000000, 00000000 => ffffffff (80000000 00000000)
+ eqv. 00000000, 000f423f => fff0bdc0 (80000000 00000000)
+ eqv. 00000000, ffffffff => 00000000 (20000000 00000000)
+ eqv. 000f423f, 00000000 => fff0bdc0 (80000000 00000000)
+ eqv. 000f423f, 000f423f => ffffffff (80000000 00000000)
+ eqv. 000f423f, ffffffff => 000f423f (40000000 00000000)
+ eqv. ffffffff, 00000000 => 00000000 (20000000 00000000)
+ eqv. ffffffff, 000f423f => 000f423f (40000000 00000000)
+ eqv. ffffffff, ffffffff => ffffffff (80000000 00000000)
+
+ nand. 00000000, 00000000 => ffffffff (80000000 00000000)
+ nand. 00000000, 000f423f => ffffffff (80000000 00000000)
+ nand. 00000000, ffffffff => ffffffff (80000000 00000000)
+ nand. 000f423f, 00000000 => ffffffff (80000000 00000000)
+ nand. 000f423f, 000f423f => fff0bdc0 (80000000 00000000)
+ nand. 000f423f, ffffffff => fff0bdc0 (80000000 00000000)
+ nand. ffffffff, 00000000 => ffffffff (80000000 00000000)
+ nand. ffffffff, 000f423f => fff0bdc0 (80000000 00000000)
+ nand. ffffffff, ffffffff => 00000000 (20000000 00000000)
+
+ nor. 00000000, 00000000 => ffffffff (80000000 00000000)
+ nor. 00000000, 000f423f => fff0bdc0 (80000000 00000000)
+ nor. 00000000, ffffffff => 00000000 (20000000 00000000)
+ nor. 000f423f, 00000000 => fff0bdc0 (80000000 00000000)
+ nor. 000f423f, 000f423f => fff0bdc0 (80000000 00000000)
+ nor. 000f423f, ffffffff => 00000000 (20000000 00000000)
+ nor. ffffffff, 00000000 => 00000000 (20000000 00000000)
+ nor. ffffffff, 000f423f => 00000000 (20000000 00000000)
+ nor. ffffffff, ffffffff => 00000000 (20000000 00000000)
+
+ or. 00000000, 00000000 => 00000000 (20000000 00000000)
+ or. 00000000, 000f423f => 000f423f (40000000 00000000)
+ or. 00000000, ffffffff => ffffffff (80000000 00000000)
+ or. 000f423f, 00000000 => 000f423f (40000000 00000000)
+ or. 000f423f, 000f423f => 000f423f (40000000 00000000)
+ or. 000f423f, ffffffff => ffffffff (80000000 00000000)
+ or. ffffffff, 00000000 => ffffffff (80000000 00000000)
+ or. ffffffff, 000f423f => ffffffff (80000000 00000000)
+ or. ffffffff, ffffffff => ffffffff (80000000 00000000)
+
+ orc. 00000000, 00000000 => ffffffff (80000000 00000000)
+ orc. 00000000, 000f423f => fff0bdc0 (80000000 00000000)
+ orc. 00000000, ffffffff => 00000000 (20000000 00000000)
+ orc. 000f423f, 00000000 => ffffffff (80000000 00000000)
+ orc. 000f423f, 000f423f => ffffffff (80000000 00000000)
+ orc. 000f423f, ffffffff => 000f423f (40000000 00000000)
+ orc. ffffffff, 00000000 => ffffffff (80000000 00000000)
+ orc. ffffffff, 000f423f => ffffffff (80000000 00000000)
+ orc. ffffffff, ffffffff => ffffffff (80000000 00000000)
+
+ xor. 00000000, 00000000 => 00000000 (20000000 00000000)
+ xor. 00000000, 000f423f => 000f423f (40000000 00000000)
+ xor. 00000000, ffffffff => ffffffff (80000000 00000000)
+ xor. 000f423f, 00000000 => 000f423f (40000000 00000000)
+ xor. 000f423f, 000f423f => 00000000 (20000000 00000000)
+ xor. 000f423f, ffffffff => fff0bdc0 (80000000 00000000)
+ xor. ffffffff, 00000000 => ffffffff (80000000 00000000)
+ xor. ffffffff, 000f423f => fff0bdc0 (80000000 00000000)
+ xor. ffffffff, ffffffff => 00000000 (20000000 00000000)
+
+ slw. 00000000, 00000000 => 00000000 (20000000 00000000)
+ slw. 00000000, 000f423f => 00000000 (20000000 00000000)
+ slw. 00000000, ffffffff => 00000000 (20000000 00000000)
+ slw. 000f423f, 00000000 => 000f423f (40000000 00000000)
+ slw. 000f423f, 000f423f => 00000000 (20000000 00000000)
+ slw. 000f423f, ffffffff => 00000000 (20000000 00000000)
+ slw. ffffffff, 00000000 => ffffffff (80000000 00000000)
+ slw. ffffffff, 000f423f => 00000000 (20000000 00000000)
+ slw. ffffffff, ffffffff => 00000000 (20000000 00000000)
+
+ sraw. 00000000, 00000000 => 00000000 (20000000 00000000)
+ sraw. 00000000, 000f423f => 00000000 (20000000 00000000)
+ sraw. 00000000, ffffffff => 00000000 (20000000 00000000)
+ sraw. 000f423f, 00000000 => 000f423f (40000000 00000000)
+ sraw. 000f423f, 000f423f => 00000000 (20000000 00000000)
+ sraw. 000f423f, ffffffff => 00000000 (20000000 00000000)
+ sraw. ffffffff, 00000000 => ffffffff (80000000 00000000)
+ sraw. ffffffff, 000f423f => ffffffff (80000000 20000000)
+ sraw. ffffffff, ffffffff => ffffffff (80000000 20000000)
+
+ srw. 00000000, 00000000 => 00000000 (20000000 00000000)
+ srw. 00000000, 000f423f => 00000000 (20000000 00000000)
+ srw. 00000000, ffffffff => 00000000 (20000000 00000000)
+ srw. 000f423f, 00000000 => 000f423f (40000000 00000000)
+ srw. 000f423f, 000f423f => 00000000 (20000000 00000000)
+ srw. 000f423f, ffffffff => 00000000 (20000000 00000000)
+ srw. ffffffff, 00000000 => ffffffff (80000000 00000000)
+ srw. ffffffff, 000f423f => 00000000 (20000000 00000000)
+ srw. ffffffff, ffffffff => 00000000 (20000000 00000000)
+
+PPC integer compare insns (two args):
+ cmpw 00000000, 00000000 => 00000000 (00200000 00000000)
+ cmpw 00000000, 000f423f => 00000000 (00800000 00000000)
+ cmpw 00000000, ffffffff => 00000000 (00400000 00000000)
+ cmpw 000f423f, 00000000 => 00000000 (00400000 00000000)
+ cmpw 000f423f, 000f423f => 00000000 (00200000 00000000)
+ cmpw 000f423f, ffffffff => 00000000 (00400000 00000000)
+ cmpw ffffffff, 00000000 => 00000000 (00800000 00000000)
+ cmpw ffffffff, 000f423f => 00000000 (00800000 00000000)
+ cmpw ffffffff, ffffffff => 00000000 (00200000 00000000)
+
+ cmplw 00000000, 00000000 => 00000000 (00200000 00000000)
+ cmplw 00000000, 000f423f => 00000000 (00800000 00000000)
+ cmplw 00000000, ffffffff => 00000000 (00800000 00000000)
+ cmplw 000f423f, 00000000 => 00000000 (00400000 00000000)
+ cmplw 000f423f, 000f423f => 00000000 (00200000 00000000)
+ cmplw 000f423f, ffffffff => 00000000 (00800000 00000000)
+ cmplw ffffffff, 00000000 => 00000000 (00400000 00000000)
+ cmplw ffffffff, 000f423f => 00000000 (00400000 00000000)
+ cmplw ffffffff, ffffffff => 00000000 (00200000 00000000)
+
+PPC integer compare with immediate insns (two args):
+ cmpwi 00000000, 00000000 => 00000000 (00200000 00000000)
+ cmpwi 00000000, 000003e7 => 00000000 (00800000 00000000)
+ cmpwi 00000000, 0000ffff => 00000000 (00400000 00000000)
+ cmpwi 000f423f, 00000000 => 00000000 (00400000 00000000)
+ cmpwi 000f423f, 000003e7 => 00000000 (00400000 00000000)
+ cmpwi 000f423f, 0000ffff => 00000000 (00400000 00000000)
+ cmpwi ffffffff, 00000000 => 00000000 (00800000 00000000)
+ cmpwi ffffffff, 000003e7 => 00000000 (00800000 00000000)
+ cmpwi ffffffff, 0000ffff => 00000000 (00200000 00000000)
+
+ cmplwi 00000000, 00000000 => 00000000 (00200000 00000000)
+ cmplwi 00000000, 000003e7 => 00000000 (00800000 00000000)
+ cmplwi 00000000, 0000ffff => 00000000 (00800000 00000000)
+ cmplwi 000f423f, 00000000 => 00000000 (00400000 00000000)
+ cmplwi 000f423f, 000003e7 => 00000000 (00400000 00000000)
+ cmplwi 000f423f, 0000ffff => 00000000 (00400000 00000000)
+ cmplwi ffffffff, 00000000 => 00000000 (00400000 00000000)
+ cmplwi ffffffff, 000003e7 => 00000000 (00400000 00000000)
+ cmplwi ffffffff, 0000ffff => 00000000 (00400000 00000000)
+
+PPC integer logical insns
+ with one register + one 16 bits immediate args:
+ ori 00000000, 00000000 => 00000000 (00000000 00000000)
+ ori 00000000, 000003e7 => 000003e7 (00000000 00000000)
+ ori 00000000, 0000ffff => 0000ffff (00000000 00000000)
+ ori 000f423f, 00000000 => 000f423f (00000000 00000000)
+ ori 000f423f, 000003e7 => 000f43ff (00000000 00000000)
+ ori 000f423f, 0000ffff => 000fffff (00000000 00000000)
+ ori ffffffff, 00000000 => ffffffff (00000000 00000000)
+ ori ffffffff, 000003e7 => ffffffff (00000000 00000000)
+ ori ffffffff, 0000ffff => ffffffff (00000000 00000000)
+
+ oris 00000000, 00000000 => 00000000 (00000000 00000000)
+ oris 00000000, 000003e7 => 03e70000 (00000000 00000000)
+ oris 00000000, 0000ffff => ffff0000 (00000000 00000000)
+ oris 000f423f, 00000000 => 000f423f (00000000 00000000)
+ oris 000f423f, 000003e7 => 03ef423f (00000000 00000000)
+ oris 000f423f, 0000ffff => ffff423f (00000000 00000000)
+ oris ffffffff, 00000000 => ffffffff (00000000 00000000)
+ oris ffffffff, 000003e7 => ffffffff (00000000 00000000)
+ oris ffffffff, 0000ffff => ffffffff (00000000 00000000)
+
+ xori 00000000, 00000000 => 00000000 (00000000 00000000)
+ xori 00000000, 000003e7 => 000003e7 (00000000 00000000)
+ xori 00000000, 0000ffff => 0000ffff (00000000 00000000)
+ xori 000f423f, 00000000 => 000f423f (00000000 00000000)
+ xori 000f423f, 000003e7 => 000f41d8 (00000000 00000000)
+ xori 000f423f, 0000ffff => 000fbdc0 (00000000 00000000)
+ xori ffffffff, 00000000 => ffffffff (00000000 00000000)
+ xori ffffffff, 000003e7 => fffffc18 (00000000 00000000)
+ xori ffffffff, 0000ffff => ffff0000 (00000000 00000000)
+
+ xoris 00000000, 00000000 => 00000000 (00000000 00000000)
+ xoris 00000000, 000003e7 => 03e70000 (00000000 00000000)
+ xoris 00000000, 0000ffff => ffff0000 (00000000 00000000)
+ xoris 000f423f, 00000000 => 000f423f (00000000 00000000)
+ xoris 000f423f, 000003e7 => 03e8423f (00000000 00000000)
+ xoris 000f423f, 0000ffff => fff0423f (00000000 00000000)
+ xoris ffffffff, 00000000 => ffffffff (00000000 00000000)
+ xoris ffffffff, 000003e7 => fc18ffff (00000000 00000000)
+ xoris ffffffff, 0000ffff => 0000ffff (00000000 00000000)
+
+PPC integer logical insns
+ with one register + one 16 bits immediate args with flags update:
+ andi. 00000000, 00000000 => 00000000 (20000000 00000000)
+ andi. 00000000, 000003e7 => 00000000 (20000000 00000000)
+ andi. 00000000, 0000ffff => 00000000 (20000000 00000000)
+ andi. 000f423f, 00000000 => 00000000 (20000000 00000000)
+ andi. 000f423f, 000003e7 => 00000227 (40000000 00000000)
+ andi. 000f423f, 0000ffff => 0000423f (40000000 00000000)
+ andi. ffffffff, 00000000 => 00000000 (20000000 00000000)
+ andi. ffffffff, 000003e7 => 000003e7 (40000000 00000000)
+ andi. ffffffff, 0000ffff => 0000ffff (40000000 00000000)
+
+ andis. 00000000, 00000000 => 00000000 (20000000 00000000)
+ andis. 00000000, 000003e7 => 00000000 (20000000 00000000)
+ andis. 00000000, 0000ffff => 00000000 (20000000 00000000)
+ andis. 000f423f, 00000000 => 00000000 (20000000 00000000)
+ andis. 000f423f, 000003e7 => 00070000 (40000000 00000000)
+ andis. 000f423f, 0000ffff => 000f0000 (40000000 00000000)
+ andis. ffffffff, 00000000 => 00000000 (20000000 00000000)
+ andis. ffffffff, 000003e7 => 03e70000 (40000000 00000000)
+ andis. ffffffff, 0000ffff => ffff0000 (80000000 00000000)
+
+PPC condition register logical insns - two operands:
+ crand 00000000, 00000000 => ffff0000 (00000000 00000000)
+ crand 00000000, 000f423f => ffff0000 (00000000 00000000)
+ crand 00000000, ffffffff => ffff0000 (00000000 00000000)
+ crand 000f423f, 00000000 => ffff0000 (00000000 00000000)
+ crand 000f423f, 000f423f => ffff0000 (00000000 00000000)
+ crand 000f423f, ffffffff => ffff0000 (00000000 00000000)
+ crand ffffffff, 00000000 => ffff0000 (00000000 00000000)
+ crand ffffffff, 000f423f => ffff0000 (00000000 00000000)
+ crand ffffffff, ffffffff => ffff0000 (00000000 00000000)
+
+ crandc 00000000, 00000000 => ffff0000 (00000000 00000000)
+ crandc 00000000, 000f423f => ffff0000 (00000000 00000000)
+ crandc 00000000, ffffffff => ffff0000 (00000000 00000000)
+ crandc 000f423f, 00000000 => ffff0000 (00000000 00000000)
+ crandc 000f423f, 000f423f => ffff0000 (00000000 00000000)
+ crandc 000f423f, ffffffff => ffff0000 (00000000 00000000)
+ crandc ffffffff, 00000000 => ffff0000 (00000000 00000000)
+ crandc ffffffff, 000f423f => ffff0000 (00000000 00000000)
+ crandc ffffffff, ffffffff => ffff0000 (00000000 00000000)
+
+ creqv 00000000, 00000000 => ffff0000 (00004000 00000000)
+ creqv 00000000, 000f423f => ffff0000 (00004000 00000000)
+ creqv 00000000, ffffffff => ffff0000 (00004000 00000000)
+ creqv 000f423f, 00000000 => ffff0000 (00004000 00000000)
+ creqv 000f423f, 000f423f => ffff0000 (00004000 00000000)
+ creqv 000f423f, ffffffff => ffff0000 (00004000 00000000)
+ creqv ffffffff, 00000000 => ffff0000 (00004000 00000000)
+ creqv ffffffff, 000f423f => ffff0000 (00004000 00000000)
+ creqv ffffffff, ffffffff => ffff0000 (00004000 00000000)
+
+ crnand 00000000, 00000000 => ffff0000 (00004000 00000000)
+ crnand 00000000, 000f423f => ffff0000 (00004000 00000000)
+ crnand 00000000, ffffffff => ffff0000 (00004000 00000000)
+ crnand 000f423f, 00000000 => ffff0000 (00004000 00000000)
+ crnand 000f423f, 000f423f => ffff0000 (00004000 00000000)
+ crnand 000f423f, ffffffff => ffff0000 (00004000 00000000)
+ crnand ffffffff, 00000000 => ffff0000 (00004000 00000000)
+ crnand ffffffff, 000f423f => ffff0000 (00004000 00000000)
+ crnand ffffffff, ffffffff => ffff0000 (00004000 00000000)
+
+ crnor 00000000, 00000000 => ffff0000 (00004000 00000000)
+ crnor 00000000, 000f423f => ffff0000 (00004000 00000000)
+ crnor 00000000, ffffffff => ffff0000 (00004000 00000000)
+ crnor 000f423f, 00000000 => ffff0000 (00004000 00000000)
+ crnor 000f423f, 000f423f => ffff0000 (00004000 00000000)
+ crnor 000f423f, ffffffff => ffff0000 (00004000 00000000)
+ crnor ffffffff, 00000000 => ffff0000 (00004000 00000000)
+ crnor ffffffff, 000f423f => ffff0000 (00004000 00000000)
+ crnor ffffffff, ffffffff => ffff0000 (00004000 00000000)
+
+ cror 00000000, 00000000 => ffff0000 (00000000 00000000)
+ cror 00000000, 000f423f => ffff0000 (00000000 00000000)
+ cror 00000000, ffffffff => ffff0000 (00000000 00000000)
+ cror 000f423f, 00000000 => ffff0000 (00000000 00000000)
+ cror 000f423f, 000f423f => ffff0000 (00000000 00000000)
+ cror 000f423f, ffffffff => ffff0000 (00000000 00000000)
+ cror ffffffff, 00000000 => ffff0000 (00000000 00000000)
+ cror ffffffff, 000f423f => ffff0000 (00000000 00000000)
+ cror ffffffff, ffffffff => ffff0000 (00000000 00000000)
+
+ crorc 00000000, 00000000 => ffff0000 (00004000 00000000)
+ crorc 00000000, 000f423f => ffff0000 (00004000 00000000)
+ crorc 00000000, ffffffff => ffff0000 (00004000 00000000)
+ crorc 000f423f, 00000000 => ffff0000 (00004000 00000000)
+ crorc 000f423f, 000f423f => ffff0000 (00004000 00000000)
+ crorc 000f423f, ffffffff => ffff0000 (00004000 00000000)
+ crorc ffffffff, 00000000 => ffff0000 (00004000 00000000)
+ crorc ffffffff, 000f423f => ffff0000 (00004000 00000000)
+ crorc ffffffff, ffffffff => ffff0000 (00004000 00000000)
+
+ crxor 00000000, 00000000 => ffff0000 (00000000 00000000)
+ crxor 00000000, 000f423f => ffff0000 (00000000 00000000)
+ crxor 00000000, ffffffff => ffff0000 (00000000 00000000)
+ crxor 000f423f, 00000000 => ffff0000 (00000000 00000000)
+ crxor 000f423f, 000f423f => ffff0000 (00000000 00000000)
+ crxor 000f423f, ffffffff => ffff0000 (00000000 00000000)
+ crxor ffffffff, 00000000 => ffff0000 (00000000 00000000)
+ crxor ffffffff, 000f423f => ffff0000 (00000000 00000000)
+ crxor ffffffff, ffffffff => ffff0000 (00000000 00000000)
+
+PPC integer logical insns with one arg:
+ cntlzw 00000000 => 00000020 (00000000 00000000)
+ cntlzw 000f423f => 0000000c (00000000 00000000)
+ cntlzw ffffffff => 00000000 (00000000 00000000)
+
+ extsb 00000000 => 00000000 (00000000 00000000)
+ extsb 000f423f => 0000003f (00000000 00000000)
+ extsb ffffffff => ffffffff (00000000 00000000)
+
+ extsh 00000000 => 00000000 (00000000 00000000)
+ extsh 000f423f => 0000423f (00000000 00000000)
+ extsh ffffffff => ffffffff (00000000 00000000)
+
+ neg 00000000 => 00000000 (00000000 00000000)
+ neg 000f423f => fff0bdc1 (00000000 00000000)
+ neg ffffffff => 00000001 (00000000 00000000)
+
+ nego 00000000 => 00000000 (00000000 00000000)
+ nego 000f423f => fff0bdc1 (00000000 00000000)
+ nego ffffffff => 00000001 (00000000 00000000)
+
+PPC integer logical insns with one arg with flags update:
+ cntlzw. 00000000 => 00000020 (40000000 00000000)
+ cntlzw. 000f423f => 0000000c (40000000 00000000)
+ cntlzw. ffffffff => 00000000 (20000000 00000000)
+
+ extsb. 00000000 => 00000000 (20000000 00000000)
+ extsb. 000f423f => 0000003f (40000000 00000000)
+ extsb. ffffffff => ffffffff (80000000 00000000)
+
+ extsh. 00000000 => 00000000 (20000000 00000000)
+ extsh. 000f423f => 0000423f (40000000 00000000)
+ extsh. ffffffff => ffffffff (80000000 00000000)
+
+ neg. 00000000 => 00000000 (20000000 00000000)
+ neg. 000f423f => fff0bdc1 (80000000 00000000)
+ neg. ffffffff => 00000001 (40000000 00000000)
+
+ nego. 00000000 => 00000000 (20000000 00000000)
+ nego. 000f423f => fff0bdc1 (80000000 00000000)
+ nego. ffffffff => 00000001 (40000000 00000000)
+
+PPC logical insns with special forms:
+ rlwimi 00000000, 0, 0, 0 => 00000000 (00000000 00000000)
+ rlwimi 00000000, 0, 0, 31 => 00000000 (00000000 00000000)
+ rlwimi 00000000, 0, 31, 0 => 00000000 (00000000 00000000)
+ rlwimi 00000000, 0, 31, 31 => 00000000 (00000000 00000000)
+ rlwimi 00000000, 31, 0, 0 => 00000000 (00000000 00000000)
+ rlwimi 00000000, 31, 0, 31 => 00000000 (00000000 00000000)
+ rlwimi 00000000, 31, 31, 0 => 00000000 (00000000 00000000)
+ rlwimi 00000000, 31, 31, 31 => 00000000 (00000000 00000000)
+ rlwimi 000f423f, 0, 0, 0 => 00000000 (00000000 00000000)
+ rlwimi 000f423f, 0, 0, 31 => 000f423f (00000000 00000000)
+ rlwimi 000f423f, 0, 31, 0 => 000f423f (00000000 00000000)
+ rlwimi 000f423f, 0, 31, 31 => 000f423f (00000000 00000000)
+ rlwimi 000f423f, 31, 0, 0 => 800f423f (00000000 00000000)
+ rlwimi 000f423f, 31, 0, 31 => 8007a11f (00000000 00000000)
+ rlwimi 000f423f, 31, 31, 0 => 8007a11f (00000000 00000000)
+ rlwimi 000f423f, 31, 31, 31 => 8007a11f (00000000 00000000)
+ rlwimi ffffffff, 0, 0, 0 => 8007a11f (00000000 00000000)
+ rlwimi ffffffff, 0, 0, 31 => ffffffff (00000000 00000000)
+ rlwimi ffffffff, 0, 31, 0 => ffffffff (00000000 00000000)
+ rlwimi ffffffff, 0, 31, 31 => ffffffff (00000000 00000000)
+ rlwimi ffffffff, 31, 0, 0 => ffffffff (00000000 00000000)
+ rlwimi ffffffff, 31, 0, 31 => ffffffff (00000000 00000000)
+ rlwimi ffffffff, 31, 31, 0 => ffffffff (00000000 00000000)
+ rlwimi ffffffff, 31, 31, 31 => ffffffff (00000000 00000000)
+
+ rlwinm 00000000, 0, 0, 0 => 00000000 (00000000 00000000)
+ rlwinm 00000000, 0, 0, 31 => 00000000 (00000000 00000000)
+ rlwinm 00000000, 0, 31, 0 => 00000000 (00000000 00000000)
+ rlwinm 00000000, 0, 31, 31 => 00000000 (00000000 00000000)
+ rlwinm 00000000, 31, 0, 0 => 00000000 (00000000 00000000)
+ rlwinm 00000000, 31, 0, 31 => 00000000 (00000000 00000000)
+ rlwinm 00000000, 31, 31, 0 => 00000000 (00000000 00000000)
+ rlwinm 00000000, 31, 31, 31 => 00000000 (00000000 00000000)
+ rlwinm 000f423f, 0, 0, 0 => 00000000 (00000000 00000000)
+ rlwinm 000f423f, 0, 0, 31 => 000f423f (00000000 00000000)
+ rlwinm 000f423f, 0, 31, 0 => 00000001 (00000000 00000000)
+ rlwinm 000f423f, 0, 31, 31 => 00000001 (00000000 00000000)
+ rlwinm 000f423f, 31, 0, 0 => 80000000 (00000000 00000000)
+ rlwinm 000f423f, 31, 0, 31 => 8007a11f (00000000 00000000)
+ rlwinm 000f423f, 31, 31, 0 => 80000001 (00000000 00000000)
+ rlwinm 000f423f, 31, 31, 31 => 00000001 (00000000 00000000)
+ rlwinm ffffffff, 0, 0, 0 => 80000000 (00000000 00000000)
+ rlwinm ffffffff, 0, 0, 31 => ffffffff (00000000 00000000)
+ rlwinm ffffffff, 0, 31, 0 => 80000001 (00000000 00000000)
+ rlwinm ffffffff, 0, 31, 31 => 00000001 (00000000 00000000)
+ rlwinm ffffffff, 31, 0, 0 => 80000000 (00000000 00000000)
+ rlwinm ffffffff, 31, 0, 31 => ffffffff (00000000 00000000)
+ rlwinm ffffffff, 31, 31, 0 => 80000001 (00000000 00000000)
+ rlwinm ffffffff, 31, 31, 31 => 00000001 (00000000 00000000)
+
+ rlwnm 00000000, 00000000, 0, 0 => 00000000 (00000000 00000000)
+ rlwnm 00000000, 00000000, 0, 31 => 00000000 (00000000 00000000)
+ rlwnm 00000000, 00000000, 31, 0 => 00000000 (00000000 00000000)
+ rlwnm 00000000, 00000000, 31, 31 => 00000000 (00000000 00000000)
+ rlwnm 00000000, 000f423f, 0, 0 => 00000000 (00000000 00000000)
+ rlwnm 00000000, 000f423f, 0, 31 => 00000000 (00000000 00000000)
+ rlwnm 00000000, 000f423f, 31, 0 => 00000000 (00000000 00000000)
+ rlwnm 00000000, 000f423f, 31, 31 => 00000000 (00000000 00000000)
+ rlwnm 00000000, ffffffff, 0, 0 => 00000000 (00000000 00000000)
+ rlwnm 00000000, ffffffff, 0, 31 => 00000000 (00000000 00000000)
+ rlwnm 00000000, ffffffff, 31, 0 => 00000000 (00000000 00000000)
+ rlwnm 00000000, ffffffff, 31, 31 => 00000000 (00000000 00000000)
+ rlwnm 000f423f, 00000000, 0, 0 => 00000000 (00000000 00000000)
+ rlwnm 000f423f, 00000000, 0, 31 => 000f423f (00000000 00000000)
+ rlwnm 000f423f, 00000000, 31, 0 => 00000001 (00000000 00000000)
+ rlwnm 000f423f, 00000000, 31, 31 => 00000001 (00000000 00000000)
+ rlwnm 000f423f, 000f423f, 0, 0 => 80000000 (00000000 00000000)
+ rlwnm 000f423f, 000f423f, 0, 31 => 8007a11f (00000000 00000000)
+ rlwnm 000f423f, 000f423f, 31, 0 => 80000001 (00000000 00000000)
+ rlwnm 000f423f, 000f423f, 31, 31 => 00000001 (00000000 00000000)
+ rlwnm 000f423f, ffffffff, 0, 0 => 80000000 (00000000 00000000)
+ rlwnm 000f423f, ffffffff, 0, 31 => 8007a11f (00000000 00000000)
+ rlwnm 000f423f, ffffffff, 31, 0 => 80000001 (00000000 00000000)
+ rlwnm 000f423f, ffffffff, 31, 31 => 00000001 (00000000 00000000)
+ rlwnm ffffffff, 00000000, 0, 0 => 80000000 (00000000 00000000)
+ rlwnm ffffffff, 00000000, 0, 31 => ffffffff (00000000 00000000)
+ rlwnm ffffffff, 00000000, 31, 0 => 80000001 (00000000 00000000)
+ rlwnm ffffffff, 00000000, 31, 31 => 00000001 (00000000 00000000)
+ rlwnm ffffffff, 000f423f, 0, 0 => 80000000 (00000000 00000000)
+ rlwnm ffffffff, 000f423f, 0, 31 => ffffffff (00000000 00000000)
+ rlwnm ffffffff, 000f423f, 31, 0 => 80000001 (00000000 00000000)
+ rlwnm ffffffff, 000f423f, 31, 31 => 00000001 (00000000 00000000)
+ rlwnm ffffffff, ffffffff, 0, 0 => 80000000 (00000000 00000000)
+ rlwnm ffffffff, ffffffff, 0, 31 => ffffffff (00000000 00000000)
+ rlwnm ffffffff, ffffffff, 31, 0 => 80000001 (00000000 00000000)
+ rlwnm ffffffff, ffffffff, 31, 31 => 00000001 (00000000 00000000)
+
+ srawi 00000000, 0 => 00000000 (00000000 00000000)
+ srawi 00000000, 31 => 00000000 (00000000 00000000)
+ srawi 000f423f, 0 => 000f423f (00000000 00000000)
+ srawi 000f423f, 31 => 00000000 (00000000 00000000)
+ srawi ffffffff, 0 => ffffffff (00000000 00000000)
+ srawi ffffffff, 31 => ffffffff (00000000 20000000)
+
+ mfcr (00000000) => 00000000 (00000000 00000000)
+ mfcr (000f423f) => 000f423f (000f423f 00000000)
+ mfcr (ffffffff) => ffffffff (ffffffff 00000000)
+
+ mfspr 1 (00000000) -> mtxer -> mfxer => 00000000
+ mfspr 1 (000f423f) -> mtxer -> mfxer => 0000003f
+ mfspr 1 (ffffffff) -> mtxer -> mfxer => e000007f
+ mfspr 8 (00000000) -> mtlr -> mflr => 00000000
+ mfspr 8 (000f423f) -> mtlr -> mflr => 000f423f
+ mfspr 8 (ffffffff) -> mtlr -> mflr => ffffffff
+ mfspr 9 (00000000) -> mtctr -> mfctr => 00000000
+ mfspr 9 (000f423f) -> mtctr -> mfctr => 000f423f
+ mfspr 9 (ffffffff) -> mtctr -> mfctr => ffffffff
+
+
+PPC logical insns with special forms with flags update:
+ rlwimi. 00000000, 0, 0, 0 => 00000000 (20000000 00000000)
+ rlwimi. 00000000, 0, 0, 31 => 00000000 (20000000 00000000)
+ rlwimi. 00000000, 0, 31, 0 => 00000000 (20000000 00000000)
+ rlwimi. 00000000, 0, 31, 31 => 00000000 (20000000 00000000)
+ rlwimi. 00000000, 31, 0, 0 => 00000000 (20000000 00000000)
+ rlwimi. 00000000, 31, 0, 31 => 00000000 (20000000 00000000)
+ rlwimi. 00000000, 31, 31, 0 => 00000000 (20000000 00000000)
+ rlwimi. 00000000, 31, 31, 31 => 00000000 (20000000 00000000)
+ rlwimi. 000f423f, 0, 0, 0 => 00000000 (20000000 00000000)
+ rlwimi. 000f423f, 0, 0, 31 => 000f423f (40000000 00000000)
+ rlwimi. 000f423f, 0, 31, 0 => 000f423f (40000000 00000000)
+ rlwimi. 000f423f, 0, 31, 31 => 000f423f (40000000 00000000)
+ rlwimi. 000f423f, 31, 0, 0 => 800f423f (80000000 00000000)
+ rlwimi. 000f423f, 31, 0, 31 => 8007a11f (80000000 00000000)
+ rlwimi. 000f423f, 31, 31, 0 => 8007a11f (80000000 00000000)
+ rlwimi. 000f423f, 31, 31, 31 => 8007a11f (80000000 00000000)
+ rlwimi. ffffffff, 0, 0, 0 => 8007a11f (80000000 00000000)
+ rlwimi. ffffffff, 0, 0, 31 => ffffffff (80000000 00000000)
+ rlwimi. ffffffff, 0, 31, 0 => ffffffff (80000000 00000000)
+ rlwimi. ffffffff, 0, 31, 31 => ffffffff (80000000 00000000)
+ rlwimi. ffffffff, 31, 0, 0 => ffffffff (80000000 00000000)
+ rlwimi. ffffffff, 31, 0, 31 => ffffffff (80000000 00000000)
+ rlwimi. ffffffff, 31, 31, 0 => ffffffff (80000000 00000000)
+ rlwimi. ffffffff, 31, 31, 31 => ffffffff (80000000 00000000)
+
+ rlwinm. 00000000, 0, 0, 0 => 00000000 (20000000 00000000)
+ rlwinm. 00000000, 0, 0, 31 => 00000000 (20000000 00000000)
+ rlwinm. 00000000, 0, 31, 0 => 00000000 (20000000 00000000)
+ rlwinm. 00000000, 0, 31, 31 => 00000000 (20000000 00000000)
+ rlwinm. 00000000, 31, 0, 0 => 00000000 (20000000 00000000)
+ rlwinm. 00000000, 31, 0, 31 => 00000000 (20000000 00000000)
+ rlwinm. 00000000, 31, 31, 0 => 00000000 (20000000 00000000)
+ rlwinm. 00000000, 31, 31, 31 => 00000000 (20000000 00000000)
+ rlwinm. 000f423f, 0, 0, 0 => 00000000 (20000000 00000000)
+ rlwinm. 000f423f, 0, 0, 31 => 000f423f (40000000 00000000)
+ rlwinm. 000f423f, 0, 31, 0 => 00000001 (40000000 00000000)
+ rlwinm. 000f423f, 0, 31, 31 => 00000001 (40000000 00000000)
+ rlwinm. 000f423f, 31, 0, 0 => 80000000 (80000000 00000000)
+ rlwinm. 000f423f, 31, 0, 31 => 8007a11f (80000000 00000000)
+ rlwinm. 000f423f, 31, 31, 0 => 80000001 (80000000 00000000)
+ rlwinm. 000f423f, 31, 31, 31 => 00000001 (40000000 00000000)
+ rlwinm. ffffffff, 0, 0, 0 => 80000000 (80000000 00000000)
+ rlwinm. ffffffff, 0, 0, 31 => ffffffff (80000000 00000000)
+ rlwinm. ffffffff, 0, 31, 0 => 80000001 (80000000 00000000)
+ rlwinm. ffffffff, 0, 31, 31 => 00000001 (40000000 00000000)
+ rlwinm. ffffffff, 31, 0, 0 => 80000000 (80000000 00000000)
+ rlwinm. ffffffff, 31, 0, 31 => ffffffff (80000000 00000000)
+ rlwinm. ffffffff, 31, 31, 0 => 80000001 (80000000 00000000)
+ rlwinm. ffffffff, 31, 31, 31 => 00000001 (40000000 00000000)
+
+ rlwnm. 00000000, 00000000, 0, 0 => 00000000 (20000000 00000000)
+ rlwnm. 00000000, 00000000, 0, 31 => 00000000 (20000000 00000000)
+ rlwnm. 00000000, 00000000, 31, 0 => 00000000 (20000000 00000000)
+ rlwnm. 00000000, 00000000, 31, 31 => 00000000 (20000000 00000000)
+ rlwnm. 00000000, 000f423f, 0, 0 => 00000000 (20000000 00000000)
+ rlwnm. 00000000, 000f423f, 0, 31 => 00000000 (20000000 00000000)
+ rlwnm. 00000000, 000f423f, 31, 0 => 00000000 (20000000 00000000)
+ rlwnm. 00000000, 000f423f, 31, 31 => 00000000 (20000000 00000000)
+ rlwnm. 00000000, ffffffff, 0, 0 => 00000000 (20000000 00000000)
+ rlwnm. 00000000, ffffffff, 0, 31 => 00000000 (20000000 00000000)
+ rlwnm. 00000000, ffffffff, 31, 0 => 00000000 (20000000 00000000)
+ rlwnm. 00000000, ffffffff, 31, 31 => 00000000 (20000000 00000000)
+ rlwnm. 000f423f, 00000000, 0, 0 => 00000000 (20000000 00000000)
+ rlwnm. 000f423f, 00000000, 0, 31 => 000f423f (40000000 00000000)
+ rlwnm. 000f423f, 00000000, 31, 0 => 00000001 (40000000 00000000)
+ rlwnm. 000f423f, 00000000, 31, 31 => 00000001 (40000000 00000000)
+ rlwnm. 000f423f, 000f423f, 0, 0 => 80000000 (80000000 00000000)
+ rlwnm. 000f423f, 000f423f, 0, 31 => 8007a11f (80000000 00000000)
+ rlwnm. 000f423f, 000f423f, 31, 0 => 80000001 (80000000 00000000)
+ rlwnm. 000f423f, 000f423f, 31, 31 => 00000001 (40000000 00000000)
+ rlwnm. 000f423f, ffffffff, 0, 0 => 80000000 (80000000 00000000)
+ rlwnm. 000f423f, ffffffff, 0, 31 => 8007a11f (80000000 00000000)
+ rlwnm. 000f423f, ffffffff, 31, 0 => 80000001 (80000000 00000000)
+ rlwnm. 000f423f, ffffffff, 31, 31 => 00000001 (40000000 00000000)
+ rlwnm. ffffffff, 00000000, 0, 0 => 80000000 (80000000 00000000)
+ rlwnm. ffffffff, 00000000, 0, 31 => ffffffff (80000000 00000000)
+ rlwnm. ffffffff, 00000000, 31, 0 => 80000001 (80000000 00000000)
+ rlwnm. ffffffff, 00000000, 31, 31 => 00000001 (40000000 00000000)
+ rlwnm. ffffffff, 000f423f, 0, 0 => 80000000 (80000000 00000000)
+ rlwnm. ffffffff, 000f423f, 0, 31 => ffffffff (80000000 00000000)
+ rlwnm. ffffffff, 000f423f, 31, 0 => 80000001 (80000000 00000000)
+ rlwnm. ffffffff, 000f423f, 31, 31 => 00000001 (40000000 00000000)
+ rlwnm. ffffffff, ffffffff, 0, 0 => 80000000 (80000000 00000000)
+ rlwnm. ffffffff, ffffffff, 0, 31 => ffffffff (80000000 00000000)
+ rlwnm. ffffffff, ffffffff, 31, 0 => 80000001 (80000000 00000000)
+ rlwnm. ffffffff, ffffffff, 31, 31 => 00000001 (40000000 00000000)
+
+ srawi. 00000000, 0 => 00000000 (20000000 00000000)
+ srawi. 00000000, 31 => 00000000 (20000000 00000000)
+ srawi. 000f423f, 0 => 000f423f (40000000 00000000)
+ srawi. 000f423f, 31 => 00000000 (20000000 00000000)
+ srawi. ffffffff, 0 => ffffffff (80000000 00000000)
+ srawi. ffffffff, 31 => ffffffff (80000000 20000000)
+
+ mcrf 0, 0 (00000000) => (00000000 00000000)
+ mcrf 0, 7 (00000000) => (00000000 00000000)
+ mcrf 7, 0 (00000000) => (00000000 00000000)
+ mcrf 7, 7 (00000000) => (00000000 00000000)
+ mcrf 0, 0 (000f423f) => (000f423f 00000000)
+ mcrf 0, 7 (000f423f) => (f00f423f 00000000)
+ mcrf 7, 0 (000f423f) => (000f4230 00000000)
+ mcrf 7, 7 (000f423f) => (000f423f 00000000)
+ mcrf 0, 0 (ffffffff) => (ffffffff 00000000)
+ mcrf 0, 7 (ffffffff) => (ffffffff 00000000)
+ mcrf 7, 0 (ffffffff) => (ffffffff 00000000)
+ mcrf 7, 7 (ffffffff) => (ffffffff 00000000)
+
+ mcrxr 0 (00000000) => (00000000 00000000)
+ mcrxr 1 (00000000) => (00000000 00000000)
+ mcrxr 2 (00000000) => (00000000 00000000)
+ mcrxr 3 (00000000) => (00000000 00000000)
+ mcrxr 4 (00000000) => (00000000 00000000)
+ mcrxr 5 (00000000) => (00000000 00000000)
+ mcrxr 6 (00000000) => (00000000 00000000)
+ mcrxr 7 (00000000) => (00000000 00000000)
+ mcrxr 0 (10000000) => (00000000 00000000)
+ mcrxr 1 (10000000) => (00000000 00000000)
+ mcrxr 2 (10000000) => (00000000 00000000)
+ mcrxr 3 (10000000) => (00000000 00000000)
+ mcrxr 4 (10000000) => (00000000 00000000)
+ mcrxr 5 (10000000) => (00000000 00000000)
+ mcrxr 6 (10000000) => (00000000 00000000)
+ mcrxr 7 (10000000) => (00000000 00000000)
+ mcrxr 0 (20000000) => (20000000 00000000)
+ mcrxr 1 (20000000) => (02000000 00000000)
+ mcrxr 2 (20000000) => (00200000 00000000)
+ mcrxr 3 (20000000) => (00020000 00000000)
+ mcrxr 4 (20000000) => (00002000 00000000)
+ mcrxr 5 (20000000) => (00000200 00000000)
+ mcrxr 6 (20000000) => (00000020 00000000)
+ mcrxr 7 (20000000) => (00000002 00000000)
+ mcrxr 0 (30000000) => (20000000 00000000)
+ mcrxr 1 (30000000) => (02000000 00000000)
+ mcrxr 2 (30000000) => (00200000 00000000)
+ mcrxr 3 (30000000) => (00020000 00000000)
+ mcrxr 4 (30000000) => (00002000 00000000)
+ mcrxr 5 (30000000) => (00000200 00000000)
+ mcrxr 6 (30000000) => (00000020 00000000)
+ mcrxr 7 (30000000) => (00000002 00000000)
+ mcrxr 0 (40000000) => (40000000 00000000)
+ mcrxr 1 (40000000) => (04000000 00000000)
+ mcrxr 2 (40000000) => (00400000 00000000)
+ mcrxr 3 (40000000) => (00040000 00000000)
+ mcrxr 4 (40000000) => (00004000 00000000)
+ mcrxr 5 (40000000) => (00000400 00000000)
+ mcrxr 6 (40000000) => (00000040 00000000)
+ mcrxr 7 (40000000) => (00000004 00000000)
+ mcrxr 0 (50000000) => (40000000 00000000)
+ mcrxr 1 (50000000) => (04000000 00000000)
+ mcrxr 2 (50000000) => (00400000 00000000)
+ mcrxr 3 (50000000) => (00040000 00000000)
+ mcrxr 4 (50000000) => (00004000 00000000)
+ mcrxr 5 (50000000) => (00000400 00000000)
+ mcrxr 6 (50000000) => (00000040 00000000)
+ mcrxr 7 (50000000) => (00000004 00000000)
+ mcrxr 0 (60000000) => (60000000 00000000)
+ mcrxr 1 (60000000) => (06000000 00000000)
+ mcrxr 2 (60000000) => (00600000 00000000)
+ mcrxr 3 (60000000) => (00060000 00000000)
+ mcrxr 4 (60000000) => (00006000 00000000)
+ mcrxr 5 (60000000) => (00000600 00000000)
+ mcrxr 6 (60000000) => (00000060 00000000)
+ mcrxr 7 (60000000) => (00000006 00000000)
+ mcrxr 0 (70000000) => (60000000 00000000)
+ mcrxr 1 (70000000) => (06000000 00000000)
+ mcrxr 2 (70000000) => (00600000 00000000)
+ mcrxr 3 (70000000) => (00060000 00000000)
+ mcrxr 4 (70000000) => (00006000 00000000)
+ mcrxr 5 (70000000) => (00000600 00000000)
+ mcrxr 6 (70000000) => (00000060 00000000)
+ mcrxr 7 (70000000) => (00000006 00000000)
+ mcrxr 0 (80000000) => (80000000 00000000)
+ mcrxr 1 (80000000) => (08000000 00000000)
+ mcrxr 2 (80000000) => (00800000 00000000)
+ mcrxr 3 (80000000) => (00080000 00000000)
+ mcrxr 4 (80000000) => (00008000 00000000)
+ mcrxr 5 (80000000) => (00000800 00000000)
+ mcrxr 6 (80000000) => (00000080 00000000)
+ mcrxr 7 (80000000) => (00000008 00000000)
+ mcrxr 0 (90000000) => (80000000 00000000)
+ mcrxr 1 (90000000) => (08000000 00000000)
+ mcrxr 2 (90000000) => (00800000 00000000)
+ mcrxr 3 (90000000) => (00080000 00000000)
+ mcrxr 4 (90000000) => (00008000 00000000)
+ mcrxr 5 (90000000) => (00000800 00000000)
+ mcrxr 6 (90000000) => (00000080 00000000)
+ mcrxr 7 (90000000) => (00000008 00000000)
+ mcrxr 0 (a0000000) => (a0000000 00000000)
+ mcrxr 1 (a0000000) => (0a000000 00000000)
+ mcrxr 2 (a0000000) => (00a00000 00000000)
+ mcrxr 3 (a0000000) => (000a0000 00000000)
+ mcrxr 4 (a0000000) => (0000a000 00000000)
+ mcrxr 5 (a0000000) => (00000a00 00000000)
+ mcrxr 6 (a0000000) => (000000a0 00000000)
+ mcrxr 7 (a0000000) => (0000000a 00000000)
+ mcrxr 0 (b0000000) => (a0000000 00000000)
+ mcrxr 1 (b0000000) => (0a000000 00000000)
+ mcrxr 2 (b0000000) => (00a00000 00000000)
+ mcrxr 3 (b0000000) => (000a0000 00000000)
+ mcrxr 4 (b0000000) => (0000a000 00000000)
+ mcrxr 5 (b0000000) => (00000a00 00000000)
+ mcrxr 6 (b0000000) => (000000a0 00000000)
+ mcrxr 7 (b0000000) => (0000000a 00000000)
+ mcrxr 0 (c0000000) => (c0000000 00000000)
+ mcrxr 1 (c0000000) => (0c000000 00000000)
+ mcrxr 2 (c0000000) => (00c00000 00000000)
+ mcrxr 3 (c0000000) => (000c0000 00000000)
+ mcrxr 4 (c0000000) => (0000c000 00000000)
+ mcrxr 5 (c0000000) => (00000c00 00000000)
+ mcrxr 6 (c0000000) => (000000c0 00000000)
+ mcrxr 7 (c0000000) => (0000000c 00000000)
+ mcrxr 0 (d0000000) => (c0000000 00000000)
+ mcrxr 1 (d0000000) => (0c000000 00000000)
+ mcrxr 2 (d0000000) => (00c00000 00000000)
+ mcrxr 3 (d0000000) => (000c0000 00000000)
+ mcrxr 4 (d0000000) => (0000c000 00000000)
+ mcrxr 5 (d0000000) => (00000c00 00000000)
+ mcrxr 6 (d0000000) => (000000c0 00000000)
+ mcrxr 7 (d0000000) => (0000000c 00000000)
+ mcrxr 0 (e0000000) => (e0000000 00000000)
+ mcrxr 1 (e0000000) => (0e000000 00000000)
+ mcrxr 2 (e0000000) => (00e00000 00000000)
+ mcrxr 3 (e0000000) => (000e0000 00000000)
+ mcrxr 4 (e0000000) => (0000e000 00000000)
+ mcrxr 5 (e0000000) => (00000e00 00000000)
+ mcrxr 6 (e0000000) => (000000e0 00000000)
+ mcrxr 7 (e0000000) => (0000000e 00000000)
+ mcrxr 0 (f0000000) => (e0000000 00000000)
+ mcrxr 1 (f0000000) => (0e000000 00000000)
+ mcrxr 2 (f0000000) => (00e00000 00000000)
+ mcrxr 3 (f0000000) => (000e0000 00000000)
+ mcrxr 4 (f0000000) => (0000e000 00000000)
+ mcrxr 5 (f0000000) => (00000e00 00000000)
+ mcrxr 6 (f0000000) => (000000e0 00000000)
+ mcrxr 7 (f0000000) => (0000000e 00000000)
+
+ mtcrf 0, 00000000 => (00000000 00000000)
+ mtcrf 99, 00000000 => (00000000 00000000)
+ mtcrf 198, 00000000 => (00000000 00000000)
+ mtcrf 0, 000f423f => (00000000 00000000)
+ mtcrf 99, 000f423f => (0000003f 00000000)
+ mtcrf 198, 000f423f => (00000230 00000000)
+ mtcrf 0, ffffffff => (00000000 00000000)
+ mtcrf 99, ffffffff => (0ff000ff 00000000)
+ mtcrf 198, ffffffff => (ff000ff0 00000000)
+
+PPC integer load insns
+ with one register + one 16 bits immediate args with flags update:
+ lbz 0, (00000000) => 00000000, 0 (00000000 00000000)
+ lbz 3, (000f423f) => 00000000, 0 (00000000 00000000)
+ lbz 7, (ffffffff) => 0000003f, 0 (00000000 00000000)
+ lbz 1, (ffffffff) => 000000ff, 0 (00000000 00000000)
+ lbz -3, (000f423f) => 0000000f, 0 (00000000 00000000)
+ lbz -7, (00000000) => 00000000, 0 (00000000 00000000)
+
+ lbzu 0, (00000000) => 00000000, 0 (00000000 00000000)
+ lbzu 3, (000f423f) => 00000000, 3 (00000000 00000000)
+ lbzu 7, (ffffffff) => 0000003f, 7 (00000000 00000000)
+ lbzu 1, (ffffffff) => 000000ff, 1 (00000000 00000000)
+ lbzu -3, (000f423f) => 0000000f, -3 (00000000 00000000)
+ lbzu -7, (00000000) => 00000000, -7 (00000000 00000000)
+
+ lha 0, (00000000) => 00000000, 0 (00000000 00000000)
+ lha 3, (000f423f) => 00000000, 0 (00000000 00000000)
+ lha 7, (ffffffff) => 00003fff, 0 (00000000 00000000)
+ lha 1, (ffffffff) => ffffffff, 0 (00000000 00000000)
+ lha -3, (000f423f) => 00000f42, 0 (00000000 00000000)
+ lha -7, (00000000) => 00000000, 0 (00000000 00000000)
+
+ lhau 0, (00000000) => 00000000, 0 (00000000 00000000)
+ lhau 3, (000f423f) => 00000000, 3 (00000000 00000000)
+ lhau 7, (ffffffff) => 00003fff, 7 (00000000 00000000)
+ lhau 1, (ffffffff) => ffffffff, 1 (00000000 00000000)
+ lhau -3, (000f423f) => 00000f42, -3 (00000000 00000000)
+ lhau -7, (00000000) => 00000000, -7 (00000000 00000000)
+
+ lhz 0, (00000000) => 00000000, 0 (00000000 00000000)
+ lhz 3, (000f423f) => 00000000, 0 (00000000 00000000)
+ lhz 7, (ffffffff) => 00003fff, 0 (00000000 00000000)
+ lhz 1, (ffffffff) => 0000ffff, 0 (00000000 00000000)
+ lhz -3, (000f423f) => 00000f42, 0 (00000000 00000000)
+ lhz -7, (00000000) => 00000000, 0 (00000000 00000000)
+
+ lhzu 0, (00000000) => 00000000, 0 (00000000 00000000)
+ lhzu 3, (000f423f) => 00000000, 3 (00000000 00000000)
+ lhzu 7, (ffffffff) => 00003fff, 7 (00000000 00000000)
+ lhzu 1, (ffffffff) => 0000ffff, 1 (00000000 00000000)
+ lhzu -3, (000f423f) => 00000f42, -3 (00000000 00000000)
+ lhzu -7, (00000000) => 00000000, -7 (00000000 00000000)
+
+ lwz 0, (00000000) => 00000000, 0 (00000000 00000000)
+ lwz 3, (000f423f) => 00000f42, 0 (00000000 00000000)
+ lwz 7, (ffffffff) => 3fffffff, 0 (00000000 00000000)
+ lwz 1, (ffffffff) => ffffff00, 0 (00000000 00000000)
+ lwz -3, (000f423f) => 0f423fff, 0 (00000000 00000000)
+ lwz -7, (00000000) => 00000000, 0 (00000000 00000000)
+
+ lwzu 0, (00000000) => 00000000, 0 (00000000 00000000)
+ lwzu 3, (000f423f) => 00000f42, 3 (00000000 00000000)
+ lwzu 7, (ffffffff) => 3fffffff, 7 (00000000 00000000)
+ lwzu 1, (ffffffff) => ffffff00, 1 (00000000 00000000)
+ lwzu -3, (000f423f) => 0f423fff, -3 (00000000 00000000)
+ lwzu -7, (00000000) => 00000000, -7 (00000000 00000000)
+
+PPC integer load insns with two register args:
+ lbzx 0 (00000000) => 00000000, 0 (00000000 00000000)
+ lbzx 4 (000f423f) => 00000000, 0 (00000000 00000000)
+ lbzx 8 (ffffffff) => 000000ff, 0 (00000000 00000000)
+
+ lbzux 0 (00000000) => 00000000, 0 (00000000 00000000)
+ lbzux 4 (000f423f) => 00000000, 4 (00000000 00000000)
+ lbzux 8 (ffffffff) => 000000ff, 8 (00000000 00000000)
+
+ lhax 0 (00000000) => 00000000, 0 (00000000 00000000)
+ lhax 4 (000f423f) => 0000000f, 0 (00000000 00000000)
+ lhax 8 (ffffffff) => ffffffff, 0 (00000000 00000000)
+
+ lhaux 0 (00000000) => 00000000, 0 (00000000 00000000)
+ lhaux 4 (000f423f) => 0000000f, 4 (00000000 00000000)
+ lhaux 8 (ffffffff) => ffffffff, 8 (00000000 00000000)
+
+ lhzx 0 (00000000) => 00000000, 0 (00000000 00000000)
+ lhzx 4 (000f423f) => 0000000f, 0 (00000000 00000000)
+ lhzx 8 (ffffffff) => 0000ffff, 0 (00000000 00000000)
+
+ lhzux 0 (00000000) => 00000000, 0 (00000000 00000000)
+ lhzux 4 (000f423f) => 0000000f, 4 (00000000 00000000)
+ lhzux 8 (ffffffff) => 0000ffff, 8 (00000000 00000000)
+
+ lwzx 0 (00000000) => 00000000, 0 (00000000 00000000)
+ lwzx 4 (000f423f) => 000f423f, 0 (00000000 00000000)
+ lwzx 8 (ffffffff) => ffffffff, 0 (00000000 00000000)
+
+ lwzux 0 (00000000) => 00000000, 0 (00000000 00000000)
+ lwzux 4 (000f423f) => 000f423f, 4 (00000000 00000000)
+ lwzux 8 (ffffffff) => ffffffff, 8 (00000000 00000000)
+
+PPC integer store insns
+ with one register + one 16 bits immediate args with flags update:
+ stb 00000000, 0 => 00000000, 0 (00000000 00000000)
+ stb 000f423f, 4 => 3f000000, 0 (00000000 00000000)
+ stb ffffffff, 8 => ff000000, 0 (00000000 00000000)
+ stb 00000000, -8 => 00000000, 0 (00000000 00000000)
+ stb 000f423f, -4 => 3f000000, 0 (00000000 00000000)
+ stb ffffffff, 0 => ff000000, 0 (00000000 00000000)
+
+ stbu 00000000, 0 => 00000000, 0 (00000000 00000000)
+ stbu 000f423f, 4 => 3f000000, 4 (00000000 00000000)
+ stbu ffffffff, 8 => ff000000, 8 (00000000 00000000)
+ stbu 00000000, -8 => 00000000, -8 (00000000 00000000)
+ stbu 000f423f, -4 => 3f000000, -4 (00000000 00000000)
+ stbu ffffffff, 0 => ff000000, 0 (00000000 00000000)
+
+ sth 00000000, 0 => 00000000, 0 (00000000 00000000)
+ sth 000f423f, 4 => 423f0000, 0 (00000000 00000000)
+ sth ffffffff, 8 => ffff0000, 0 (00000000 00000000)
+ sth 00000000, -8 => 00000000, 0 (00000000 00000000)
+ sth 000f423f, -4 => 423f0000, 0 (00000000 00000000)
+ sth ffffffff, 0 => ffff0000, 0 (00000000 00000000)
+
+ sthu 00000000, 0 => 00000000, 0 (00000000 00000000)
+ sthu 000f423f, 4 => 423f0000, 4 (00000000 00000000)
+ sthu ffffffff, 8 => ffff0000, 8 (00000000 00000000)
+ sthu 00000000, -8 => 00000000, -8 (00000000 00000000)
+ sthu 000f423f, -4 => 423f0000, -4 (00000000 00000000)
+ sthu ffffffff, 0 => ffff0000, 0 (00000000 00000000)
+
+ stw 00000000, 0 => 00000000, 0 (00000000 00000000)
+ stw 000f423f, 4 => 000f423f, 0 (00000000 00000000)
+ stw ffffffff, 8 => ffffffff, 0 (00000000 00000000)
+ stw 00000000, -8 => 00000000, 0 (00000000 00000000)
+ stw 000f423f, -4 => 000f423f, 0 (00000000 00000000)
+ stw ffffffff, 0 => ffffffff, 0 (00000000 00000000)
+
+ stwu 00000000, 0 => 00000000, 0 (00000000 00000000)
+ stwu 000f423f, 4 => 000f423f, 4 (00000000 00000000)
+ stwu ffffffff, 8 => ffffffff, 8 (00000000 00000000)
+ stwu 00000000, -8 => 00000000, -8 (00000000 00000000)
+ stwu 000f423f, -4 => 000f423f, -4 (00000000 00000000)
+ stwu ffffffff, 0 => ffffffff, 0 (00000000 00000000)
+
+PPC integer store insns with three register args:
+ stbx 00000000, 0 => 00000000, 0 (00000000 00000000)
+ stbx 000f423f, 4 => 3f000000, 0 (00000000 00000000)
+ stbx ffffffff, 8 => ff000000, 0 (00000000 00000000)
+
+ stbux 00000000, 0 => 00000000, 0 (00000000 00000000)
+ stbux 000f423f, 4 => 3f000000, 4 (00000000 00000000)
+ stbux ffffffff, 8 => ff000000, 8 (00000000 00000000)
+
+ sthx 00000000, 0 => 00000000, 0 (00000000 00000000)
+ sthx 000f423f, 4 => 423f0000, 0 (00000000 00000000)
+ sthx ffffffff, 8 => ffff0000, 0 (00000000 00000000)
+
+ sthux 00000000, 0 => 00000000, 0 (00000000 00000000)
+ sthux 000f423f, 4 => 423f0000, 4 (00000000 00000000)
+ sthux ffffffff, 8 => ffff0000, 8 (00000000 00000000)
+
+ stwx 00000000, 0 => 00000000, 0 (00000000 00000000)
+ stwx 000f423f, 4 => 000f423f, 0 (00000000 00000000)
+ stwx ffffffff, 8 => ffffffff, 0 (00000000 00000000)
+
+ stwux 00000000, 0 => 00000000, 0 (00000000 00000000)
+ stwux 000f423f, 4 => 000f423f, 4 (00000000 00000000)
+ stwux ffffffff, 8 => ffffffff, 8 (00000000 00000000)
+
+All done. Tested 92 different instructions
diff --git a/none/tests/ppc32/jm-int_other.vgtest b/none/tests/ppc32/jm-int_other.vgtest
new file mode 100644
index 0000000..42255ae
--- /dev/null
+++ b/none/tests/ppc32/jm-int_other.vgtest
@@ -0,0 +1 @@
+prog: jm-insns -l -L -c
diff --git a/none/tests/ppc32/test_isa_2_06_part2-div.stderr.exp b/none/tests/ppc32/test_isa_2_06_part2-div.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/none/tests/ppc32/test_isa_2_06_part2-div.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/none/tests/ppc32/test_isa_2_06_part2-div.stdout.exp b/none/tests/ppc32/test_isa_2_06_part2-div.stdout.exp
new file mode 100644
index 0000000..fbc23dd
--- /dev/null
+++ b/none/tests/ppc32/test_isa_2_06_part2-div.stdout.exp
@@ -0,0 +1,31 @@
+Test div extensions
+#0: divweu: 0x00000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divweu: 0x00000002 / 0x00000000 = 0x00000000; CR=0; XER=0
+#2: divweu: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=0; XER=0
+#3: divweu: 0xfabc1234 / 0x00000005 = 0x00000000; CR=0; XER=0
+#4: divweu: 0x0000004d / 0x00000042 = 0x00000000; CR=0; XER=0
+#5: divweu: 0x00000005 / 0xfabc1234 = 0x00000005; CR=0; XER=0
+
+#0: divweu.: 0x00000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divweu.: 0x00000002 / 0x00000000 = 0x00000000; CR=2; XER=0
+#2: divweu.: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=8; XER=0
+#3: divweu.: 0xfabc1234 / 0x00000005 = 0x00000000; CR=2; XER=0
+#4: divweu.: 0x0000004d / 0x00000042 = 0x00000000; CR=2; XER=0
+#5: divweu.: 0x00000005 / 0xfabc1234 = 0x00000005; CR=4; XER=0
+
+
+#0: divweuo: 0x00000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divweuo: 0x00000002 / 0x00000000 = 0x00000000; CR=0; XER=c0000000
+#2: divweuo: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=0; XER=0
+#3: divweuo: 0xfabc1234 / 0x00000005 = 0x00000000; CR=0; XER=c0000000
+#4: divweuo: 0x0000004d / 0x00000042 = 0x00000000; CR=0; XER=c0000000
+#5: divweuo: 0x00000005 / 0xfabc1234 = 0x00000005; CR=0; XER=0
+
+#0: divweuo.: 0x00000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divweuo.: 0x00000002 / 0x00000000 = 0x00000000; CR=3; XER=c0000000
+#2: divweuo.: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=8; XER=0
+#3: divweuo.: 0xfabc1234 / 0x00000005 = 0x00000000; CR=3; XER=c0000000
+#4: divweuo.: 0x0000004d / 0x00000042 = 0x00000000; CR=3; XER=c0000000
+#5: divweuo.: 0x00000005 / 0xfabc1234 = 0x00000005; CR=4; XER=0
+
+
diff --git a/none/tests/ppc32/test_isa_2_06_part2-div.vgtest b/none/tests/ppc32/test_isa_2_06_part2-div.vgtest
new file mode 100644
index 0000000..7f9e006
--- /dev/null
+++ b/none/tests/ppc32/test_isa_2_06_part2-div.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_ppc64_auxv_cap arch_2_06
+prog: test_isa_2_06_part2 -d
diff --git a/none/tests/ppc32/test_isa_2_06_part2.c b/none/tests/ppc32/test_isa_2_06_part2.c
index b33849a..c7bf4fe 100644
--- a/none/tests/ppc32/test_isa_2_06_part2.c
+++ b/none/tests/ppc32/test_isa_2_06_part2.c
@@ -29,6 +29,7 @@
#include <malloc.h>
#include <altivec.h>
#include <math.h>
+#include <unistd.h> // getopt
#ifndef __powerpc64__
typedef uint32_t HWord_t;
@@ -92,6 +93,9 @@
typedef void (*test_func_t)(void);
typedef struct test_table test_table_t;
+/* Defines for the instructiion groups, use bit field to identify */
+#define SCALAR_DIV_INST 0x0001
+#define OTHER_INST 0x0002
/* These functions below that construct a table of floating point
* values were lifted from none/tests/ppc32/jm-insns.c.
@@ -541,6 +545,7 @@
{
test_func_t test_category;
char * name;
+ unsigned int test_group;
};
typedef enum {
@@ -1741,33 +1746,44 @@
all_tests[] =
{
{ &test_vx_vector_one_fp_arg,
- "Test VSX vector single arg instructions"},
+ "Test VSX vector single arg instructions", OTHER_INST },
{ &test_vx_vector_fp_ops,
- "Test VSX floating point compare and basic arithmetic instructions" },
+ "Test VSX floating point compare and basic arithmetic instructions", OTHER_INST },
#ifdef __powerpc64__
{ &test_bpermd,
- "Test bit permute double"},
+ "Test bit permute double", OTHER_INST },
#endif
{ &test_xxsel,
- "Test xxsel instruction" },
+ "Test xxsel instruction", OTHER_INST },
{ &test_xxspltw,
- "Test xxspltw instruction" },
+ "Test xxspltw instruction", OTHER_INST },
{ &test_div_extensions,
- "Test div extensions" },
+ "Test div extensions", SCALAR_DIV_INST },
{ &test_fct_ops,
- "Test floating point convert [word | doubleword] unsigned, with round toward zero" },
+ "Test floating point convert [word | doubleword] unsigned, with round toward zero", OTHER_INST },
#ifdef __powerpc64__
{ &test_stdbrx,
- "Test stdbrx instruction"},
+ "Test stdbrx instruction", OTHER_INST },
#endif
{ &test_vx_aORm_fp_ops,
- "Test floating point arithmetic instructions -- with a{d|s}p or m{d|s}p"},
+ "Test floating point arithmetic instructions -- with a{d|s}p or m{d|s}p", OTHER_INST },
{ &test_vx_simple_scalar_fp_ops,
- "Test scalar floating point arithmetic instructions"},
+ "Test scalar floating point arithmetic instructions", OTHER_INST },
{ NULL, NULL }
};
#endif // HAS_VSX
+static void usage (void)
+{
+ fprintf(stderr,
+ "Usage: test_isa_3_0 [OPTIONS]\n"
+ "\t-d: test scalar division instructions (default)\n"
+ "\t-o: test non scalar division instructions (default)\n"
+ "\t-A: test all instructions (default)\n"
+ "\t-h: display this help and exit\n"
+ );
+}
+
int main(int argc, char *argv[])
{
#ifdef HAS_VSX
@@ -1775,11 +1791,47 @@
test_table_t aTest;
test_func_t func;
int i = 0;
+ int c;
+ unsigned int test_run_mask = 0;
+
+ /* NOTE, ISA 3.0 introduces the OV32 and CA32 bits in the FPSCR. These
+ * bits are set on various arithimetic instructions. This means this
+ * test generates different FPSCR output for pre ISA 3.0 versus ISA 3.0
+ * hardware. The tests have been grouped so that the tests that generate
+ * different results are in one test and the rest are in a different test.
+ * this minimizes the size of the result expect files for the two cases.
+ */
+
+ while ((c = getopt(argc, argv, "doAh")) != -1) {
+ switch (c) {
+ case 'd':
+ test_run_mask |= SCALAR_DIV_INST;
+ break;
+ case 'o':
+ test_run_mask |= OTHER_INST;
+ break;
+ case 'A':
+ test_run_mask = 0xFFFF;
+ break;
+ case 'h':
+ usage();
+ return 0;
+
+ default:
+ usage();
+ fprintf(stderr, "Unknown argument: '%c'\n", c);
+ return 1;
+ }
+ }
while ((func = all_tests[i].test_category)) {
aTest = all_tests[i];
- printf( "%s\n", aTest.name );
- (*func)();
+ if(test_run_mask & aTest.test_group) {
+ /* Test group specified on command line */
+
+ printf( "%s\n", aTest.name );
+ (*func)();
+ }
i++;
}
if (spec_fargs)
diff --git a/none/tests/ppc32/test_isa_2_06_part2.stdout.exp b/none/tests/ppc32/test_isa_2_06_part2.stdout.exp
index 4da1afa..05fbd4f 100644
--- a/none/tests/ppc32/test_isa_2_06_part2.stdout.exp
+++ b/none/tests/ppc32/test_isa_2_06_part2.stdout.exp
@@ -699,37 +699,6 @@
xxspltw 0xfedc432124681235f1e2d3c4e0057708 2=> 0xf1e2d3c4f1e2d3c4f1e2d3c4f1e2d3c4
xxspltw 0xfedc432124681235f1e2d3c4e0057708 3=> 0xe0057708e0057708e0057708e0057708
-Test div extensions
-#0: divweu: 0x00000000 / 0x00000002 = 0x00000000; CR=0; XER=0
-#1: divweu: 0x00000002 / 0x00000000 = 0x00000000; CR=0; XER=0
-#2: divweu: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=0; XER=0
-#3: divweu: 0xfabc1234 / 0x00000005 = 0x00000000; CR=0; XER=0
-#4: divweu: 0x0000004d / 0x00000042 = 0x00000000; CR=0; XER=0
-#5: divweu: 0x00000005 / 0xfabc1234 = 0x00000005; CR=0; XER=0
-
-#0: divweu.: 0x00000000 / 0x00000002 = 0x00000000; CR=2; XER=0
-#1: divweu.: 0x00000002 / 0x00000000 = 0x00000000; CR=2; XER=0
-#2: divweu.: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=8; XER=0
-#3: divweu.: 0xfabc1234 / 0x00000005 = 0x00000000; CR=2; XER=0
-#4: divweu.: 0x0000004d / 0x00000042 = 0x00000000; CR=2; XER=0
-#5: divweu.: 0x00000005 / 0xfabc1234 = 0x00000005; CR=4; XER=0
-
-
-#0: divweuo: 0x00000000 / 0x00000002 = 0x00000000; CR=0; XER=0
-#1: divweuo: 0x00000002 / 0x00000000 = 0x00000000; CR=0; XER=c0000000
-#2: divweuo: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=0; XER=0
-#3: divweuo: 0xfabc1234 / 0x00000005 = 0x00000000; CR=0; XER=c0000000
-#4: divweuo: 0x0000004d / 0x00000042 = 0x00000000; CR=0; XER=c0000000
-#5: divweuo: 0x00000005 / 0xfabc1234 = 0x00000005; CR=0; XER=0
-
-#0: divweuo.: 0x00000000 / 0x00000002 = 0x00000000; CR=2; XER=0
-#1: divweuo.: 0x00000002 / 0x00000000 = 0x00000000; CR=3; XER=c0000000
-#2: divweuo.: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=8; XER=0
-#3: divweuo.: 0xfabc1234 / 0x00000005 = 0x00000000; CR=3; XER=c0000000
-#4: divweuo.: 0x0000004d / 0x00000042 = 0x00000000; CR=3; XER=c0000000
-#5: divweuo.: 0x00000005 / 0xfabc1234 = 0x00000005; CR=4; XER=0
-
-
Test floating point convert [word | doubleword] unsigned, with round toward zero
#0: fctiduz: 0x3fd8000000000000 (3.750000e-01) ==> 0x0000000000000000
#1: fctiduz: 0x404f000000000000 (6.200000e+01) ==> 0x000000000000003e
diff --git a/none/tests/ppc32/test_isa_2_06_part2.vgtest b/none/tests/ppc32/test_isa_2_06_part2.vgtest
index 7783c5e..fe4d659 100644
--- a/none/tests/ppc32/test_isa_2_06_part2.vgtest
+++ b/none/tests/ppc32/test_isa_2_06_part2.vgtest
@@ -1,2 +1,2 @@
prereq: ../../../tests/check_ppc64_auxv_cap arch_2_06
-prog: test_isa_2_06_part2
+prog: test_isa_2_06_part2 -o
diff --git a/none/tests/ppc32/test_isa_2_06_part3-div.stderr.exp b/none/tests/ppc32/test_isa_2_06_part3-div.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/none/tests/ppc32/test_isa_2_06_part3-div.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/none/tests/ppc32/test_isa_2_06_part3-div.stdout.exp b/none/tests/ppc32/test_isa_2_06_part3-div.stdout.exp
new file mode 100644
index 0000000..131f5a2
--- /dev/null
+++ b/none/tests/ppc32/test_isa_2_06_part3-div.stdout.exp
@@ -0,0 +1,31 @@
+Test div extensions
+#0: divwe: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divwe: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=0; XER=0
+#2: divwe: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=0; XER=0
+#3: divwe: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=0; XER=0
+#4: divwe: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=0; XER=0
+#5: divwe: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=0; XER=0
+
+#0: divwe.: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divwe.: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=2; XER=0
+#2: divwe.: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=2; XER=0
+#3: divwe.: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=2; XER=0
+#4: divwe.: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=2; XER=0
+#5: divwe.: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=8; XER=0
+
+
+#0: divweo: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divweo: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=0; XER=c0000000
+#2: divweo: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=0; XER=c0000000
+#3: divweo: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=0; XER=c0000000
+#4: divweo: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=0; XER=c0000000
+#5: divweo: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=0; XER=0
+
+#0: divweo.: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divweo.: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=3; XER=c0000000
+#2: divweo.: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=3; XER=c0000000
+#3: divweo.: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=3; XER=c0000000
+#4: divweo.: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=3; XER=c0000000
+#5: divweo.: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=8; XER=0
+
+
diff --git a/none/tests/ppc32/test_isa_2_06_part3-div.vgtest b/none/tests/ppc32/test_isa_2_06_part3-div.vgtest
new file mode 100644
index 0000000..5ab8320
--- /dev/null
+++ b/none/tests/ppc32/test_isa_2_06_part3-div.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_ppc64_auxv_cap arch_2_06
+prog: test_isa_2_06_part3 -d
diff --git a/none/tests/ppc32/test_isa_2_06_part3.c b/none/tests/ppc32/test_isa_2_06_part3.c
index 9f9cd79..8c74c09 100644
--- a/none/tests/ppc32/test_isa_2_06_part3.c
+++ b/none/tests/ppc32/test_isa_2_06_part3.c
@@ -29,6 +29,7 @@
#include <malloc.h>
#include <altivec.h>
#include <math.h>
+#include <unistd.h> // getopt
#ifndef __powerpc64__
typedef uint32_t HWord_t;
@@ -91,6 +92,9 @@
typedef void (*test_func_t)(void);
typedef struct test_table test_table_t;
+/* Defines for the instructiion groups, use bit field to identify */
+#define SCALAR_DIV_INST 0x0001
+#define OTHER_INST 0x0002
/* These functions below that construct a table of floating point
* values were lifted from none/tests/ppc32/jm-insns.c.
@@ -401,6 +405,7 @@
{
test_func_t test_category;
char * name;
+ unsigned int test_group;
};
/* Type of input for floating point operations.*/
@@ -1586,33 +1591,81 @@
{
{ &test_vsx_one_fp_arg,
- "Test VSX vector and scalar single argument instructions"} ,
+ "Test VSX vector and scalar single argument instructions", OTHER_INST } ,
{ &test_int_to_fp_convert,
- "Test VSX vector integer to float conversion instructions" },
+ "Test VSX vector integer to float conversion instructions", OTHER_INST },
{ &test_div_extensions,
- "Test div extensions" },
+ "Test div extensions", SCALAR_DIV_INST },
{ &test_ftsqrt,
- "Test ftsqrt instruction" },
+ "Test ftsqrt instruction", OTHER_INST },
{ &test_vx_tdivORtsqrt,
- "Test vector and scalar tdiv and tsqrt instructions" },
+ "Test vector and scalar tdiv and tsqrt instructions", OTHER_INST },
{ &test_popcntw,
- "Test popcntw instruction" },
+ "Test popcntw instruction", OTHER_INST },
{ NULL, NULL }
};
#endif // HAS_VSX
-int main(int argc, char *argv[])
+static void usage (void)
+{
+ fprintf(stderr,
+ "Usage: test_isa_3_0 [OPTIONS]\n"
+ "\t-d: test scalar division instructions (default)\n"
+ "\t-o: test non scalar division instructions (default)\n"
+ "\t-A: test all instructions (default)\n"
+ "\t-h: display this help and exit\n"
+ );
+}
+
+int main(int argc, char **argv)
{
#ifdef HAS_VSX
test_table_t aTest;
test_func_t func;
+ int c;
int i = 0;
+ unsigned int test_run_mask = 0;
+
+ /* NOTE, ISA 3.0 introduces the OV32 and CA32 bits in the FPSCR. These
+ * bits are set on various arithimetic instructions. This means this
+ * test generates different FPSCR output for pre ISA 3.0 versus ISA 3.0
+ * hardware. The tests have been grouped so that the tests that generate
+ * different results are in one test and the rest are in a different test.
+ * this minimizes the size of the result expect files for the two cases.
+ */
+
+ while ((c = getopt(argc, argv, "doAh")) != -1) {
+ switch (c) {
+ case 'd':
+ test_run_mask |= SCALAR_DIV_INST;
+ break;
+ case 'o':
+ test_run_mask |= OTHER_INST;
+ break;
+ case 'A':
+ test_run_mask = 0xFFFF;
+ break;
+ case 'h':
+ usage();
+ return 0;
+
+ default:
+ usage();
+ fprintf(stderr, "Unknown argument: '%c'\n", c);
+ return 1;
+ }
+ }
while ((func = all_tests[i].test_category)) {
aTest = all_tests[i];
- printf( "%s\n", aTest.name );
- (*func)();
+
+ if(test_run_mask & aTest.test_group) {
+ /* Test group specified on command line */
+
+ printf( "%s\n", aTest.name );
+ (*func)();
+ }
i++;
}
if (spec_fargs)
diff --git a/none/tests/ppc32/test_isa_2_06_part3.stdout.exp b/none/tests/ppc32/test_isa_2_06_part3.stdout.exp
index 7e713f1..d83a8c3 100644
--- a/none/tests/ppc32/test_isa_2_06_part3.stdout.exp
+++ b/none/tests/ppc32/test_isa_2_06_part3.stdout.exp
@@ -455,37 +455,6 @@
#0: xvcvuxwsp conv(00000000) = 00000000; conv(ffff0000) = 4f7fff00; conv(0000ffff) = 477fff00; conv(ffffffff) = 4f800000
#1: xvcvuxwsp conv(89a73522) = 4f09a735; conv(01020304) = 4b810182; conv(0000abcd) = 472bcd00; conv(11223344) = 4d89119a
-Test div extensions
-#0: divwe: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=0; XER=0
-#1: divwe: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=0; XER=0
-#2: divwe: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=0; XER=0
-#3: divwe: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=0; XER=0
-#4: divwe: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=0; XER=0
-#5: divwe: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=0; XER=0
-
-#0: divwe.: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=2; XER=0
-#1: divwe.: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=2; XER=0
-#2: divwe.: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=2; XER=0
-#3: divwe.: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=2; XER=0
-#4: divwe.: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=2; XER=0
-#5: divwe.: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=8; XER=0
-
-
-#0: divweo: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=0; XER=0
-#1: divweo: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=0; XER=c0000000
-#2: divweo: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=0; XER=c0000000
-#3: divweo: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=0; XER=c0000000
-#4: divweo: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=0; XER=c0000000
-#5: divweo: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=0; XER=0
-
-#0: divweo.: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=2; XER=0
-#1: divweo.: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=3; XER=c0000000
-#2: divweo.: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=3; XER=c0000000
-#3: divweo.: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=3; XER=c0000000
-#4: divweo.: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=3; XER=c0000000
-#5: divweo.: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=8; XER=0
-
-
Test ftsqrt instruction
ftsqrt: 3fd8000000000000 ? 8 (CRx)
ftsqrt: 404f000000000000 ? 8 (CRx)
diff --git a/none/tests/ppc32/test_isa_2_06_part3.vgtest b/none/tests/ppc32/test_isa_2_06_part3.vgtest
index e4ccfee..843fc16 100644
--- a/none/tests/ppc32/test_isa_2_06_part3.vgtest
+++ b/none/tests/ppc32/test_isa_2_06_part3.vgtest
@@ -1,2 +1,2 @@
prereq: ../../../tests/check_ppc64_auxv_cap arch_2_06
-prog: test_isa_2_06_part3
+prog: test_isa_2_06_part3 -o
diff --git a/none/tests/ppc64/Makefile.am b/none/tests/ppc64/Makefile.am
index a79d35a..80cde28 100644
--- a/none/tests/ppc64/Makefile.am
+++ b/none/tests/ppc64/Makefile.am
@@ -7,6 +7,9 @@
EXTRA_DIST = \
jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest jm-int.stdout.exp-LE \
+ jm-int.stdout.exp-LE-ISA3_0 \
+ jm-int_other.stderr.exp jm-int_other.stdout.exp jm-int_other.vgtest \
+ jm-int_other.stdout.exp-LE \
jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest jm-fp.stdout.exp-LE jm-fp.stdout.exp-LE2 jm-fp.stdout.exp-BE2 \
jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan jm-vmx.stdout.exp-LE \
jm-vmx.vgtest \
@@ -22,7 +25,11 @@
test_isa_2_06_part1.stderr.exp test_isa_2_06_part1.stdout.exp test_isa_2_06_part1.vgtest \
test_isa_2_06_part1.stdout.exp-LE \
test_isa_2_06_part2.stderr.exp test_isa_2_06_part2.stdout.exp test_isa_2_06_part2.vgtest \
+ test_isa_2_06_part2-div.stderr.exp test_isa_2_06_part2-div.stdout.exp \
+ test_isa_2_06_part2-div.stdout.exp-LE-ISA3_0 test_isa_2_06_part2-div.vgtest \
test_isa_2_06_part3.stderr.exp test_isa_2_06_part3.stdout.exp test_isa_2_06_part3.vgtest \
+ test_isa_2_06_part3-div.stderr.exp test_isa_2_06_part3-div.stdout.exp \
+ test_isa_2_06_part3-div.stdout.exp-LE-ISA3_0 test_isa_2_06_part3-div.vgtest \
test_dfp1.stderr.exp test_dfp1.stdout.exp test_dfp1.vgtest \
test_dfp2.stderr.exp test_dfp2.stdout.exp test_dfp2.vgtest \
test_dfp2.stdout.exp_Without_dcffix \
diff --git a/none/tests/ppc64/Makefile.in b/none/tests/ppc64/Makefile.in
index 0794d4f..c51f709 100644
--- a/none/tests/ppc64/Makefile.in
+++ b/none/tests/ppc64/Makefile.in
@@ -112,7 +112,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -368,6 +368,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -538,6 +539,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -548,6 +550,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -622,8 +625,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -668,7 +669,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
@@ -694,6 +694,9 @@
noinst_HEADERS = ppc64_helpers.h
EXTRA_DIST = \
jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest jm-int.stdout.exp-LE \
+ jm-int.stdout.exp-LE-ISA3_0 \
+ jm-int_other.stderr.exp jm-int_other.stdout.exp jm-int_other.vgtest \
+ jm-int_other.stdout.exp-LE \
jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest jm-fp.stdout.exp-LE jm-fp.stdout.exp-LE2 jm-fp.stdout.exp-BE2 \
jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan jm-vmx.stdout.exp-LE \
jm-vmx.vgtest \
@@ -709,7 +712,11 @@
test_isa_2_06_part1.stderr.exp test_isa_2_06_part1.stdout.exp test_isa_2_06_part1.vgtest \
test_isa_2_06_part1.stdout.exp-LE \
test_isa_2_06_part2.stderr.exp test_isa_2_06_part2.stdout.exp test_isa_2_06_part2.vgtest \
+ test_isa_2_06_part2-div.stderr.exp test_isa_2_06_part2-div.stdout.exp \
+ test_isa_2_06_part2-div.stdout.exp-LE-ISA3_0 test_isa_2_06_part2-div.vgtest \
test_isa_2_06_part3.stderr.exp test_isa_2_06_part3.stdout.exp test_isa_2_06_part3.vgtest \
+ test_isa_2_06_part3-div.stderr.exp test_isa_2_06_part3-div.stdout.exp \
+ test_isa_2_06_part3-div.stdout.exp-LE-ISA3_0 test_isa_2_06_part3-div.vgtest \
test_dfp1.stderr.exp test_dfp1.stdout.exp test_dfp1.vgtest \
test_dfp2.stderr.exp test_dfp2.stdout.exp test_dfp2.vgtest \
test_dfp2.stdout.exp_Without_dcffix \
diff --git a/none/tests/ppc64/jm-insns.c b/none/tests/ppc64/jm-insns.c
index 27f9712..e1a7da9 100644
--- a/none/tests/ppc64/jm-insns.c
+++ b/none/tests/ppc64/jm-insns.c
@@ -45,7 +45,7 @@
* I always get the result in r17 and also save XER and CCR for fixed-point
* operations. I also check FPSCR for floating points operations.
*
- * Improvments:
+ * Improvements:
* a more clever FPSCR management is needed: for now, I always test
* the round-to-zero case. Other rounding modes also need to be tested.
*/
@@ -98,7 +98,7 @@
* }
*
*
- * Details of intruction patching for immediate operands
+ * Details of instruction patching for immediate operands
* -----------------------------------------------------
* All the immediate insn test functions are of the form {imm_insn, blr}
* In order to patch one of these functions, we simply copy both insns
@@ -3367,7 +3367,7 @@
/* Power ISA 2.03 support dcbtct and dcbtstct with valid hint values b00000 - 0b00111.
* The ISA 2.06 added support for more valid hint values, but rather than tie ourselves
- * in knots trying to test all permuations of ISAs and valid hint values, we'll just
+ * in knots trying to test all permutations of ISAs and valid hint values, we'll just
* verify some of the base hint values from ISA 2.03.
*
* In a similar vein, in ISA 2.03, dcbtds had valid values of 0b01000 - 0b01010, whereas
@@ -7620,7 +7620,10 @@
#else // #if !defined (USAGE_SIMPLE)
fprintf(stderr,
"Usage: jm-insns [OPTION]\n"
- "\t-i: test integer instructions (default)\n"
+ "\t-i: test integer arithmetic instructions (default)\n"
+ "\t-l: test integer logical instructions (default)\n"
+ "\t-c: test integer compare instructions (default)\n"
+ "\t-L: test integer load/store instructions (default)\n"
"\t-f: test floating point instructions\n"
"\t-a: test altivec instructions\n"
"\t-m: test miscellaneous instructions\n"
@@ -7767,7 +7770,8 @@
#else // #if !defined (USAGE_SIMPLE)
////////////////////////////////////////////////////////////////////////
/* Simple usage:
- ./jm-insns -i => int insns
+ ./jm-insns -i => int arithmetic insns
+ ./jm-insns -l => int logical insns
./jm-insns -f => fp insns
./jm-insns -a => av insns
./jm-insns -m => miscellaneous insns
@@ -7782,10 +7786,10 @@
flags.two_args = 1;
flags.three_args = 1;
// Type
- flags.arith = 1;
- flags.logical = 1;
- flags.compare = 1;
- flags.ldst = 1;
+ flags.arith = 0;
+ flags.logical = 0;
+ flags.compare = 0;
+ flags.ldst = 0;
// Family
flags.integer = 0;
flags.floats = 0;
@@ -7796,22 +7800,51 @@
// Flags
flags.cr = 2;
- while ((c = getopt(argc, argv, "ifmahvA")) != -1) {
+ while ((c = getopt(argc, argv, "ilcLfmahvA")) != -1) {
switch (c) {
case 'i':
+ flags.arith = 1;
+ flags.integer = 1;
+ break;
+ case 'l':
+ flags.logical = 1;
+ flags.integer = 1;
+ break;
+ case 'c':
+ flags.compare = 1;
+ flags.integer = 1;
+ break;
+ case 'L':
+ flags.ldst = 1;
flags.integer = 1;
break;
case 'f':
+ flags.arith = 1;
+ flags.logical = 1;
+ flags.compare = 1;
+ flags.ldst = 1;
flags.floats = 1;
break;
case 'a':
+ flags.arith = 1;
+ flags.logical = 1;
+ flags.compare = 1;
+ flags.ldst = 1;
flags.altivec = 1;
flags.faltivec = 1;
break;
case 'm':
+ flags.arith = 1;
+ flags.logical = 1;
+ flags.compare = 1;
+ flags.ldst = 1;
flags.misc = 1;
break;
case 'A':
+ flags.arith = 1;
+ flags.logical = 1;
+ flags.compare = 1;
+ flags.ldst = 1;
flags.integer = 1;
flags.floats = 1;
flags.altivec = 1;
diff --git a/none/tests/ppc64/jm-int.stdout.exp b/none/tests/ppc64/jm-int.stdout.exp
index 9b8c5dd..a8a850c 100644
--- a/none/tests/ppc64/jm-int.stdout.exp
+++ b/none/tests/ppc64/jm-int.stdout.exp
@@ -610,370 +610,6 @@
subfeo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
subfeo. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 20000000)
-PPC integer logical insns with two args:
- and 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
- and 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
- and 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
- and 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
- and 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
- and 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 00000000)
- and ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
- and ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
- and ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
-
- andc 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
- andc 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
- andc 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
- andc 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
- andc 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
- andc 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
- andc ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
- andc ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
- andc ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-
- eqv 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
- eqv 0000000000000000, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
- eqv 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
- eqv 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (00000000 00000000)
- eqv 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
- eqv 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 00000000)
- eqv ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
- eqv ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
- eqv ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
-
- nand 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
- nand 0000000000000000, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
- nand 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
- nand 0000001cbe991def, 0000000000000000 => ffffffffffffffff (00000000 00000000)
- nand 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
- nand 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 00000000)
- nand ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
- nand ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
- nand ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-
- nor 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
- nor 0000000000000000, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
- nor 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
- nor 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (00000000 00000000)
- nor 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
- nor 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
- nor ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
- nor ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
- nor ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-
- or 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
- or 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
- or 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
- or 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
- or 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
- or 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
- or ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
- or ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
- or ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
-
- orc 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
- orc 0000000000000000, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
- orc 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
- orc 0000001cbe991def, 0000000000000000 => ffffffffffffffff (00000000 00000000)
- orc 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
- orc 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 00000000)
- orc ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
- orc ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
- orc ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
-
- xor 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
- xor 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
- xor 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
- xor 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
- xor 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
- xor 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 00000000)
- xor ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
- xor ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
- xor ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-
- slw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
- slw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
- slw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
- slw 0000001cbe991def, 0000000000000000 => 00000000be991def (00000000 00000000)
- slw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
- slw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
- slw ffffffffffffffff, 0000000000000000 => 00000000ffffffff (00000000 00000000)
- slw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
- slw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-
- sraw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
- sraw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
- sraw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
- sraw 0000001cbe991def, 0000000000000000 => ffffffffbe991def (00000000 00000000)
- sraw 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 20000000)
- sraw 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
- sraw ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
- sraw ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 20000000)
- sraw ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
-
- srw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
- srw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
- srw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
- srw 0000001cbe991def, 0000000000000000 => 00000000be991def (00000000 00000000)
- srw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
- srw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
- srw ffffffffffffffff, 0000000000000000 => 00000000ffffffff (00000000 00000000)
- srw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
- srw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-
- sld 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
- sld 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
- sld 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
- sld 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
- sld 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
- sld 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
- sld ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
- sld ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
- sld ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-
- srad 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
- srad 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
- srad 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
- srad 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
- srad 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
- srad 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
- srad ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
- srad ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 20000000)
- srad ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
-
- srd 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
- srd 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
- srd 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
- srd 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
- srd 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
- srd 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
- srd ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
- srd ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
- srd ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-
-PPC integer logical insns with two args with flags update:
- and. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
- and. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
- and. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
- and. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
- and. 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
- and. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 00000000)
- and. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
- and. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
- and. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
-
- andc. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
- andc. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
- andc. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
- andc. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
- andc. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
- andc. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
- andc. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
- andc. ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
- andc. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
-
- eqv. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
- eqv. 0000000000000000, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
- eqv. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
- eqv. 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (80000000 00000000)
- eqv. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
- eqv. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 00000000)
- eqv. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
- eqv. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
- eqv. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
-
- nand. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
- nand. 0000000000000000, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
- nand. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
- nand. 0000001cbe991def, 0000000000000000 => ffffffffffffffff (80000000 00000000)
- nand. 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
- nand. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 00000000)
- nand. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
- nand. ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
- nand. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
-
- nor. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
- nor. 0000000000000000, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
- nor. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
- nor. 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (80000000 00000000)
- nor. 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
- nor. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
- nor. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
- nor. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
- nor. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
-
- or. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
- or. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
- or. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
- or. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
- or. 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
- or. 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
- or. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
- or. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
- or. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
-
- orc. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
- orc. 0000000000000000, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
- orc. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
- orc. 0000001cbe991def, 0000000000000000 => ffffffffffffffff (80000000 00000000)
- orc. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
- orc. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 00000000)
- orc. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
- orc. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
- orc. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
-
- xor. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
- xor. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
- xor. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
- xor. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
- xor. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
- xor. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 00000000)
- xor. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
- xor. ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
- xor. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
-
- slw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
- slw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
- slw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
- slw. 0000001cbe991def, 0000000000000000 => 00000000be991def (40000000 00000000)
- slw. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
- slw. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
- slw. ffffffffffffffff, 0000000000000000 => 00000000ffffffff (40000000 00000000)
- slw. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
- slw. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
-
- sraw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
- sraw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
- sraw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
- sraw. 0000001cbe991def, 0000000000000000 => ffffffffbe991def (80000000 00000000)
- sraw. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 20000000)
- sraw. 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
- sraw. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
- sraw. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 20000000)
- sraw. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
-
- srw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
- srw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
- srw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
- srw. 0000001cbe991def, 0000000000000000 => 00000000be991def (40000000 00000000)
- srw. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
- srw. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
- srw. ffffffffffffffff, 0000000000000000 => 00000000ffffffff (40000000 00000000)
- srw. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
- srw. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
-
- sld. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
- sld. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
- sld. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
- sld. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
- sld. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
- sld. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
- sld. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
- sld. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
- sld. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
-
- srad. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
- srad. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
- srad. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
- srad. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
- srad. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
- srad. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
- srad. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
- srad. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 20000000)
- srad. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
-
- srd. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
- srd. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
- srd. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
- srd. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
- srd. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
- srd. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
- srd. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
- srd. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
- srd. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
-
-PPC integer compare insns (two args):
- cmpw 0000000000000000, 0000000000000000 => 0000000000000000 (00200000 00000000)
- cmpw 0000000000000000, 0000001cbe991def => 0000000000000000 (00400000 00000000)
- cmpw 0000000000000000, ffffffffffffffff => 0000000000000000 (00400000 00000000)
- cmpw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00800000 00000000)
- cmpw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00200000 00000000)
- cmpw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00800000 00000000)
- cmpw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00800000 00000000)
- cmpw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00400000 00000000)
- cmpw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00200000 00000000)
-
- cmplw 0000000000000000, 0000000000000000 => 0000000000000000 (00200000 00000000)
- cmplw 0000000000000000, 0000001cbe991def => 0000000000000000 (00800000 00000000)
- cmplw 0000000000000000, ffffffffffffffff => 0000000000000000 (00800000 00000000)
- cmplw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00400000 00000000)
- cmplw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00200000 00000000)
- cmplw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00800000 00000000)
- cmplw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00400000 00000000)
- cmplw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00400000 00000000)
- cmplw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00200000 00000000)
-
- cmpd 0000000000000000, 0000000000000000 => 0000000000000000 (00200000 00000000)
- cmpd 0000000000000000, 0000001cbe991def => 0000000000000000 (00800000 00000000)
- cmpd 0000000000000000, ffffffffffffffff => 0000000000000000 (00400000 00000000)
- cmpd 0000001cbe991def, 0000000000000000 => 0000000000000000 (00400000 00000000)
- cmpd 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00200000 00000000)
- cmpd 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00400000 00000000)
- cmpd ffffffffffffffff, 0000000000000000 => 0000000000000000 (00800000 00000000)
- cmpd ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00800000 00000000)
- cmpd ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00200000 00000000)
-
- cmpld 0000000000000000, 0000000000000000 => 0000000000000000 (00200000 00000000)
- cmpld 0000000000000000, 0000001cbe991def => 0000000000000000 (00800000 00000000)
- cmpld 0000000000000000, ffffffffffffffff => 0000000000000000 (00800000 00000000)
- cmpld 0000001cbe991def, 0000000000000000 => 0000000000000000 (00400000 00000000)
- cmpld 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00200000 00000000)
- cmpld 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00800000 00000000)
- cmpld ffffffffffffffff, 0000000000000000 => 0000000000000000 (00400000 00000000)
- cmpld ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00400000 00000000)
- cmpld ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00200000 00000000)
-
-PPC integer compare with immediate insns (two args):
- cmpwi 0000000000000000, 00000000 => 0000000000000000 (00200000 00000000)
- cmpwi 0000000000000000, 000003e7 => 0000000000000000 (00800000 00000000)
- cmpwi 0000000000000000, 0000ffff => 0000000000000000 (00400000 00000000)
- cmpwi 0000001cbe991def, 00000000 => 0000000000000000 (00800000 00000000)
- cmpwi 0000001cbe991def, 000003e7 => 0000000000000000 (00800000 00000000)
- cmpwi 0000001cbe991def, 0000ffff => 0000000000000000 (00800000 00000000)
- cmpwi ffffffffffffffff, 00000000 => 0000000000000000 (00800000 00000000)
- cmpwi ffffffffffffffff, 000003e7 => 0000000000000000 (00800000 00000000)
- cmpwi ffffffffffffffff, 0000ffff => 0000000000000000 (00200000 00000000)
-
- cmplwi 0000000000000000, 00000000 => 0000000000000000 (00200000 00000000)
- cmplwi 0000000000000000, 000003e7 => 0000000000000000 (00800000 00000000)
- cmplwi 0000000000000000, 0000ffff => 0000000000000000 (00800000 00000000)
- cmplwi 0000001cbe991def, 00000000 => 0000000000000000 (00400000 00000000)
- cmplwi 0000001cbe991def, 000003e7 => 0000000000000000 (00400000 00000000)
- cmplwi 0000001cbe991def, 0000ffff => 0000000000000000 (00400000 00000000)
- cmplwi ffffffffffffffff, 00000000 => 0000000000000000 (00400000 00000000)
- cmplwi ffffffffffffffff, 000003e7 => 0000000000000000 (00400000 00000000)
- cmplwi ffffffffffffffff, 0000ffff => 0000000000000000 (00400000 00000000)
-
- cmpdi 0000000000000000, 00000000 => 0000000000000000 (00200000 00000000)
- cmpdi 0000000000000000, 000003e7 => 0000000000000000 (00800000 00000000)
- cmpdi 0000000000000000, 0000ffff => 0000000000000000 (00400000 00000000)
- cmpdi 0000001cbe991def, 00000000 => 0000000000000000 (00400000 00000000)
- cmpdi 0000001cbe991def, 000003e7 => 0000000000000000 (00400000 00000000)
- cmpdi 0000001cbe991def, 0000ffff => 0000000000000000 (00400000 00000000)
- cmpdi ffffffffffffffff, 00000000 => 0000000000000000 (00800000 00000000)
- cmpdi ffffffffffffffff, 000003e7 => 0000000000000000 (00800000 00000000)
- cmpdi ffffffffffffffff, 0000ffff => 0000000000000000 (00200000 00000000)
-
- cmpldi 0000000000000000, 00000000 => 0000000000000000 (00200000 00000000)
- cmpldi 0000000000000000, 000003e7 => 0000000000000000 (00800000 00000000)
- cmpldi 0000000000000000, 0000ffff => 0000000000000000 (00800000 00000000)
- cmpldi 0000001cbe991def, 00000000 => 0000000000000000 (00400000 00000000)
- cmpldi 0000001cbe991def, 000003e7 => 0000000000000000 (00400000 00000000)
- cmpldi 0000001cbe991def, 0000ffff => 0000000000000000 (00400000 00000000)
- cmpldi ffffffffffffffff, 00000000 => 0000000000000000 (00400000 00000000)
- cmpldi ffffffffffffffff, 000003e7 => 0000000000000000 (00400000 00000000)
- cmpldi ffffffffffffffff, 0000ffff => 0000000000000000 (00400000 00000000)
-
PPC integer arith insns
with one register + one 16 bits immediate args:
addi 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
@@ -1038,151 +674,6 @@
addic. ffffffffffffffff, 000003e7 => 00000000000003e6 (40000000 20000000)
addic. ffffffffffffffff, 0000ffff => fffffffffffffffe (80000000 20000000)
-PPC integer logical insns
- with one register + one 16 bits immediate args:
- ori 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
- ori 0000000000000000, 000003e7 => 00000000000003e7 (00000000 00000000)
- ori 0000000000000000, 0000ffff => 000000000000ffff (00000000 00000000)
- ori 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
- ori 0000001cbe991def, 000003e7 => 0000001cbe991fef (00000000 00000000)
- ori 0000001cbe991def, 0000ffff => 0000001cbe99ffff (00000000 00000000)
- ori ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
- ori ffffffffffffffff, 000003e7 => ffffffffffffffff (00000000 00000000)
- ori ffffffffffffffff, 0000ffff => ffffffffffffffff (00000000 00000000)
-
- oris 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
- oris 0000000000000000, 000003e7 => 0000000003e70000 (00000000 00000000)
- oris 0000000000000000, 0000ffff => 00000000ffff0000 (00000000 00000000)
- oris 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
- oris 0000001cbe991def, 000003e7 => 0000001cbfff1def (00000000 00000000)
- oris 0000001cbe991def, 0000ffff => 0000001cffff1def (00000000 00000000)
- oris ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
- oris ffffffffffffffff, 000003e7 => ffffffffffffffff (00000000 00000000)
- oris ffffffffffffffff, 0000ffff => ffffffffffffffff (00000000 00000000)
-
- xori 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
- xori 0000000000000000, 000003e7 => 00000000000003e7 (00000000 00000000)
- xori 0000000000000000, 0000ffff => 000000000000ffff (00000000 00000000)
- xori 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
- xori 0000001cbe991def, 000003e7 => 0000001cbe991e08 (00000000 00000000)
- xori 0000001cbe991def, 0000ffff => 0000001cbe99e210 (00000000 00000000)
- xori ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
- xori ffffffffffffffff, 000003e7 => fffffffffffffc18 (00000000 00000000)
- xori ffffffffffffffff, 0000ffff => ffffffffffff0000 (00000000 00000000)
-
- xoris 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
- xoris 0000000000000000, 000003e7 => 0000000003e70000 (00000000 00000000)
- xoris 0000000000000000, 0000ffff => 00000000ffff0000 (00000000 00000000)
- xoris 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
- xoris 0000001cbe991def, 000003e7 => 0000001cbd7e1def (00000000 00000000)
- xoris 0000001cbe991def, 0000ffff => 0000001c41661def (00000000 00000000)
- xoris ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
- xoris ffffffffffffffff, 000003e7 => fffffffffc18ffff (00000000 00000000)
- xoris ffffffffffffffff, 0000ffff => ffffffff0000ffff (00000000 00000000)
-
-PPC integer logical insns
- with one register + one 16 bits immediate args with flags update:
- andi. 0000000000000000, 00000000 => 0000000000000000 (20000000 00000000)
- andi. 0000000000000000, 000003e7 => 0000000000000000 (20000000 00000000)
- andi. 0000000000000000, 0000ffff => 0000000000000000 (20000000 00000000)
- andi. 0000001cbe991def, 00000000 => 0000000000000000 (20000000 00000000)
- andi. 0000001cbe991def, 000003e7 => 00000000000001e7 (40000000 00000000)
- andi. 0000001cbe991def, 0000ffff => 0000000000001def (40000000 00000000)
- andi. ffffffffffffffff, 00000000 => 0000000000000000 (20000000 00000000)
- andi. ffffffffffffffff, 000003e7 => 00000000000003e7 (40000000 00000000)
- andi. ffffffffffffffff, 0000ffff => 000000000000ffff (40000000 00000000)
-
- andis. 0000000000000000, 00000000 => 0000000000000000 (20000000 00000000)
- andis. 0000000000000000, 000003e7 => 0000000000000000 (20000000 00000000)
- andis. 0000000000000000, 0000ffff => 0000000000000000 (20000000 00000000)
- andis. 0000001cbe991def, 00000000 => 0000000000000000 (20000000 00000000)
- andis. 0000001cbe991def, 000003e7 => 0000000002810000 (40000000 00000000)
- andis. 0000001cbe991def, 0000ffff => 00000000be990000 (40000000 00000000)
- andis. ffffffffffffffff, 00000000 => 0000000000000000 (20000000 00000000)
- andis. ffffffffffffffff, 000003e7 => 0000000003e70000 (40000000 00000000)
- andis. ffffffffffffffff, 0000ffff => 00000000ffff0000 (40000000 00000000)
-
-PPC condition register logical insns - two operands:
- crand 0000000000000000, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
- crand 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
- crand 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
- crand 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
- crand 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
- crand 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
- crand ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
- crand ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
- crand ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
-
- crandc 0000000000000000, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
- crandc 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
- crandc 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
- crandc 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
- crandc 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
- crandc 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
- crandc ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
- crandc ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
- crandc ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
-
- creqv 0000000000000000, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
- creqv 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
- creqv 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
- creqv 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
- creqv 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
- creqv 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
- creqv ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
- creqv ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
- creqv ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
-
- crnand 0000000000000000, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
- crnand 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
- crnand 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
- crnand 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
- crnand 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
- crnand 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
- crnand ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
- crnand ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
- crnand ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
-
- crnor 0000000000000000, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
- crnor 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
- crnor 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
- crnor 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
- crnor 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
- crnor 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
- crnor ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
- crnor ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
- crnor ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
-
- cror 0000000000000000, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
- cror 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
- cror 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
- cror 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
- cror 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
- cror 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
- cror ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
- cror ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
- cror ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
-
- crorc 0000000000000000, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
- crorc 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
- crorc 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
- crorc 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
- crorc 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
- crorc 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
- crorc ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
- crorc ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
- crorc ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
-
- crxor 0000000000000000, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
- crxor 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
- crxor 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
- crxor 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
- crxor 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
- crxor 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
- crxor ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
- crxor ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
- crxor ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
-
PPC integer arith insns with one arg and carry:
addme 0000000000000000 => ffffffffffffffff (00000000 00000000)
addme 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
@@ -1297,3477 +788,9 @@
subfzeo. 0000001cbe991def => ffffffe34166e211 (80000000 00000000)
subfzeo. ffffffffffffffff => 0000000000000001 (40000000 00000000)
-PPC integer logical insns with one arg:
- cntlzw 0000000000000000 => 0000000000000020 (00000000 00000000)
- cntlzw 0000001cbe991def => 0000000000000000 (00000000 00000000)
- cntlzw ffffffffffffffff => 0000000000000000 (00000000 00000000)
-
- extsb 0000000000000000 => 0000000000000000 (00000000 00000000)
- extsb 0000001cbe991def => ffffffffffffffef (00000000 00000000)
- extsb ffffffffffffffff => ffffffffffffffff (00000000 00000000)
-
- extsh 0000000000000000 => 0000000000000000 (00000000 00000000)
- extsh 0000001cbe991def => 0000000000001def (00000000 00000000)
- extsh ffffffffffffffff => ffffffffffffffff (00000000 00000000)
-
- neg 0000000000000000 => 0000000000000000 (00000000 00000000)
- neg 0000001cbe991def => ffffffe34166e211 (00000000 00000000)
- neg ffffffffffffffff => 0000000000000001 (00000000 00000000)
-
- nego 0000000000000000 => 0000000000000000 (00000000 00000000)
- nego 0000001cbe991def => ffffffe34166e211 (00000000 00000000)
- nego ffffffffffffffff => 0000000000000001 (00000000 00000000)
-
- cntlzd 0000000000000000 => 0000000000000040 (00000000 00000000)
- cntlzd 0000001cbe991def => 000000000000001b (00000000 00000000)
- cntlzd ffffffffffffffff => 0000000000000000 (00000000 00000000)
-
- extsw 0000000000000000 => 0000000000000000 (00000000 00000000)
- extsw 0000001cbe991def => ffffffffbe991def (00000000 00000000)
- extsw ffffffffffffffff => ffffffffffffffff (00000000 00000000)
-
-PPC integer logical insns with one arg with flags update:
- cntlzw. 0000000000000000 => 0000000000000020 (40000000 00000000)
- cntlzw. 0000001cbe991def => 0000000000000000 (20000000 00000000)
- cntlzw. ffffffffffffffff => 0000000000000000 (20000000 00000000)
-
- extsb. 0000000000000000 => 0000000000000000 (20000000 00000000)
- extsb. 0000001cbe991def => ffffffffffffffef (80000000 00000000)
- extsb. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
-
- extsh. 0000000000000000 => 0000000000000000 (20000000 00000000)
- extsh. 0000001cbe991def => 0000000000001def (40000000 00000000)
- extsh. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
-
- neg. 0000000000000000 => 0000000000000000 (20000000 00000000)
- neg. 0000001cbe991def => ffffffe34166e211 (80000000 00000000)
- neg. ffffffffffffffff => 0000000000000001 (40000000 00000000)
-
- nego. 0000000000000000 => 0000000000000000 (20000000 00000000)
- nego. 0000001cbe991def => ffffffe34166e211 (80000000 00000000)
- nego. ffffffffffffffff => 0000000000000001 (40000000 00000000)
-
- cntlzd. 0000000000000000 => 0000000000000040 (40000000 00000000)
- cntlzd. 0000001cbe991def => 000000000000001b (40000000 00000000)
- cntlzd. ffffffffffffffff => 0000000000000000 (20000000 00000000)
-
- extsw. 0000000000000000 => 0000000000000000 (20000000 00000000)
- extsw. 0000001cbe991def => ffffffffbe991def (80000000 00000000)
- extsw. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
-
-PPC logical insns with special forms:
- rlwimi 0000000000000000, 0, 0, 0 => 0000000000000000 (00000000 00000000)
- rlwimi 0000000000000000, 0, 0, 31 => 0000000000000000 (00000000 00000000)
- rlwimi 0000000000000000, 0, 31, 0 => 0000000000000000 (00000000 00000000)
- rlwimi 0000000000000000, 0, 31, 31 => 0000000000000000 (00000000 00000000)
- rlwimi 0000000000000000, 31, 0, 0 => 0000000000000000 (00000000 00000000)
- rlwimi 0000000000000000, 31, 0, 31 => 0000000000000000 (00000000 00000000)
- rlwimi 0000000000000000, 31, 31, 0 => 0000000000000000 (00000000 00000000)
- rlwimi 0000000000000000, 31, 31, 31 => 0000000000000000 (00000000 00000000)
- rlwimi 0000001cbe991def, 0, 0, 0 => 0000000080000000 (00000000 00000000)
- rlwimi 0000001cbe991def, 0, 0, 31 => 00000000be991def (00000000 00000000)
- rlwimi 0000001cbe991def, 0, 31, 0 => be991defbe991def (00000000 00000000)
- rlwimi 0000001cbe991def, 0, 31, 31 => be991defbe991def (00000000 00000000)
- rlwimi 0000001cbe991def, 31, 0, 0 => be991defbe991def (00000000 00000000)
- rlwimi 0000001cbe991def, 31, 0, 31 => be991defdf4c8ef7 (00000000 00000000)
- rlwimi 0000001cbe991def, 31, 31, 0 => df4c8ef7df4c8ef7 (00000000 00000000)
- rlwimi 0000001cbe991def, 31, 31, 31 => df4c8ef7df4c8ef7 (00000000 00000000)
- rlwimi ffffffffffffffff, 0, 0, 0 => df4c8ef7df4c8ef7 (00000000 00000000)
- rlwimi ffffffffffffffff, 0, 0, 31 => df4c8ef7ffffffff (00000000 00000000)
- rlwimi ffffffffffffffff, 0, 31, 0 => ffffffffffffffff (00000000 00000000)
- rlwimi ffffffffffffffff, 0, 31, 31 => ffffffffffffffff (00000000 00000000)
- rlwimi ffffffffffffffff, 31, 0, 0 => ffffffffffffffff (00000000 00000000)
- rlwimi ffffffffffffffff, 31, 0, 31 => ffffffffffffffff (00000000 00000000)
- rlwimi ffffffffffffffff, 31, 31, 0 => ffffffffffffffff (00000000 00000000)
- rlwimi ffffffffffffffff, 31, 31, 31 => ffffffffffffffff (00000000 00000000)
-
- rlwinm 0000000000000000, 0, 0, 0 => 0000000000000000 (00000000 00000000)
- rlwinm 0000000000000000, 0, 0, 31 => 0000000000000000 (00000000 00000000)
- rlwinm 0000000000000000, 0, 31, 0 => 0000000000000000 (00000000 00000000)
- rlwinm 0000000000000000, 0, 31, 31 => 0000000000000000 (00000000 00000000)
- rlwinm 0000000000000000, 31, 0, 0 => 0000000000000000 (00000000 00000000)
- rlwinm 0000000000000000, 31, 0, 31 => 0000000000000000 (00000000 00000000)
- rlwinm 0000000000000000, 31, 31, 0 => 0000000000000000 (00000000 00000000)
- rlwinm 0000000000000000, 31, 31, 31 => 0000000000000000 (00000000 00000000)
- rlwinm 0000001cbe991def, 0, 0, 0 => 0000000080000000 (00000000 00000000)
- rlwinm 0000001cbe991def, 0, 0, 31 => 00000000be991def (00000000 00000000)
- rlwinm 0000001cbe991def, 0, 31, 0 => be991def80000001 (00000000 00000000)
- rlwinm 0000001cbe991def, 0, 31, 31 => 0000000000000001 (00000000 00000000)
- rlwinm 0000001cbe991def, 31, 0, 0 => 0000000080000000 (00000000 00000000)
- rlwinm 0000001cbe991def, 31, 0, 31 => 00000000df4c8ef7 (00000000 00000000)
- rlwinm 0000001cbe991def, 31, 31, 0 => df4c8ef780000001 (00000000 00000000)
- rlwinm 0000001cbe991def, 31, 31, 31 => 0000000000000001 (00000000 00000000)
- rlwinm ffffffffffffffff, 0, 0, 0 => 0000000080000000 (00000000 00000000)
- rlwinm ffffffffffffffff, 0, 0, 31 => 00000000ffffffff (00000000 00000000)
- rlwinm ffffffffffffffff, 0, 31, 0 => ffffffff80000001 (00000000 00000000)
- rlwinm ffffffffffffffff, 0, 31, 31 => 0000000000000001 (00000000 00000000)
- rlwinm ffffffffffffffff, 31, 0, 0 => 0000000080000000 (00000000 00000000)
- rlwinm ffffffffffffffff, 31, 0, 31 => 00000000ffffffff (00000000 00000000)
- rlwinm ffffffffffffffff, 31, 31, 0 => ffffffff80000001 (00000000 00000000)
- rlwinm ffffffffffffffff, 31, 31, 31 => 0000000000000001 (00000000 00000000)
-
- rlwnm 0000000000000000, 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
- rlwnm 0000000000000000, 0000000000000000, 0, 31 => 0000000000000000 (00000000 00000000)
- rlwnm 0000000000000000, 0000000000000000, 31, 0 => 0000000000000000 (00000000 00000000)
- rlwnm 0000000000000000, 0000000000000000, 31, 31 => 0000000000000000 (00000000 00000000)
- rlwnm 0000000000000000, 0000001cbe991def, 0, 0 => 0000000000000000 (00000000 00000000)
- rlwnm 0000000000000000, 0000001cbe991def, 0, 31 => 0000000000000000 (00000000 00000000)
- rlwnm 0000000000000000, 0000001cbe991def, 31, 0 => 0000000000000000 (00000000 00000000)
- rlwnm 0000000000000000, 0000001cbe991def, 31, 31 => 0000000000000000 (00000000 00000000)
- rlwnm 0000000000000000, ffffffffffffffff, 0, 0 => 0000000000000000 (00000000 00000000)
- rlwnm 0000000000000000, ffffffffffffffff, 0, 31 => 0000000000000000 (00000000 00000000)
- rlwnm 0000000000000000, ffffffffffffffff, 31, 0 => 0000000000000000 (00000000 00000000)
- rlwnm 0000000000000000, ffffffffffffffff, 31, 31 => 0000000000000000 (00000000 00000000)
- rlwnm 0000001cbe991def, 0000000000000000, 0, 0 => 0000000080000000 (00000000 00000000)
- rlwnm 0000001cbe991def, 0000000000000000, 0, 31 => 00000000be991def (00000000 00000000)
- rlwnm 0000001cbe991def, 0000000000000000, 31, 0 => be991def80000001 (00000000 00000000)
- rlwnm 0000001cbe991def, 0000000000000000, 31, 31 => 0000000000000001 (00000000 00000000)
- rlwnm 0000001cbe991def, 0000001cbe991def, 0, 0 => 0000000080000000 (00000000 00000000)
- rlwnm 0000001cbe991def, 0000001cbe991def, 0, 31 => 000000008ef7df4c (00000000 00000000)
- rlwnm 0000001cbe991def, 0000001cbe991def, 31, 0 => 8ef7df4c80000000 (00000000 00000000)
- rlwnm 0000001cbe991def, 0000001cbe991def, 31, 31 => 0000000000000000 (00000000 00000000)
- rlwnm 0000001cbe991def, ffffffffffffffff, 0, 0 => 0000000080000000 (00000000 00000000)
- rlwnm 0000001cbe991def, ffffffffffffffff, 0, 31 => 00000000df4c8ef7 (00000000 00000000)
- rlwnm 0000001cbe991def, ffffffffffffffff, 31, 0 => df4c8ef780000001 (00000000 00000000)
- rlwnm 0000001cbe991def, ffffffffffffffff, 31, 31 => 0000000000000001 (00000000 00000000)
- rlwnm ffffffffffffffff, 0000000000000000, 0, 0 => 0000000080000000 (00000000 00000000)
- rlwnm ffffffffffffffff, 0000000000000000, 0, 31 => 00000000ffffffff (00000000 00000000)
- rlwnm ffffffffffffffff, 0000000000000000, 31, 0 => ffffffff80000001 (00000000 00000000)
- rlwnm ffffffffffffffff, 0000000000000000, 31, 31 => 0000000000000001 (00000000 00000000)
- rlwnm ffffffffffffffff, 0000001cbe991def, 0, 0 => 0000000080000000 (00000000 00000000)
- rlwnm ffffffffffffffff, 0000001cbe991def, 0, 31 => 00000000ffffffff (00000000 00000000)
- rlwnm ffffffffffffffff, 0000001cbe991def, 31, 0 => ffffffff80000001 (00000000 00000000)
- rlwnm ffffffffffffffff, 0000001cbe991def, 31, 31 => 0000000000000001 (00000000 00000000)
- rlwnm ffffffffffffffff, ffffffffffffffff, 0, 0 => 0000000080000000 (00000000 00000000)
- rlwnm ffffffffffffffff, ffffffffffffffff, 0, 31 => 00000000ffffffff (00000000 00000000)
- rlwnm ffffffffffffffff, ffffffffffffffff, 31, 0 => ffffffff80000001 (00000000 00000000)
- rlwnm ffffffffffffffff, ffffffffffffffff, 31, 31 => 0000000000000001 (00000000 00000000)
-
- srawi 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
- srawi 0000000000000000, 31 => 0000000000000000 (00000000 00000000)
- srawi 0000001cbe991def, 0 => ffffffffbe991def (00000000 00000000)
- srawi 0000001cbe991def, 31 => ffffffffffffffff (00000000 20000000)
- srawi ffffffffffffffff, 0 => ffffffffffffffff (00000000 00000000)
- srawi ffffffffffffffff, 31 => ffffffffffffffff (00000000 20000000)
-
- mfcr (0000000000000000) => 0000000000000000 (00000000 00000000)
- mfcr (0000001cbe991def) => 00000000be991def (be991def 00000000)
- mfcr (ffffffffffffffff) => 00000000ffffffff (ffffffff 00000000)
-
- mfspr 1 (00000000) -> mtxer -> mfxer => 0000000000000000
- mfspr 1 (be991def) -> mtxer -> mfxer => 00000000a000006f
- mfspr 1 (ffffffff) -> mtxer -> mfxer => 00000000e000007f
- mfspr 8 (00000000) -> mtlr -> mflr => 0000000000000000
- mfspr 8 (be991def) -> mtlr -> mflr => ffffffffbe991def
- mfspr 8 (ffffffff) -> mtlr -> mflr => ffffffffffffffff
- mfspr 9 (00000000) -> mtctr -> mfctr => 0000000000000000
- mfspr 9 (be991def) -> mtctr -> mfctr => ffffffffbe991def
- mfspr 9 (ffffffff) -> mtctr -> mfctr => ffffffffffffffff
-
-
- rldcl 0000000000000000, 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, 0000000000000000, 7 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, 0000000000000000, 14 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, 0000000000000000, 21 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, 0000000000000000, 28 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, 0000000000000000, 35 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, 0000000000000000, 42 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, 0000000000000000, 49 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, 0000000000000000, 56 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, 0000000000000000, 63 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, 0000001cbe991def, 0 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, 0000001cbe991def, 7 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, 0000001cbe991def, 14 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, 0000001cbe991def, 21 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, 0000001cbe991def, 28 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, 0000001cbe991def, 35 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, 0000001cbe991def, 42 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, 0000001cbe991def, 49 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, 0000001cbe991def, 56 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, ffffffffffffffff, 0 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, ffffffffffffffff, 7 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, ffffffffffffffff, 14 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, ffffffffffffffff, 21 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, ffffffffffffffff, 28 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, ffffffffffffffff, 35 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, ffffffffffffffff, 42 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, ffffffffffffffff, 49 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, ffffffffffffffff, 56 => 0000000000000000 (00000000 00000000)
- rldcl 0000000000000000, ffffffffffffffff, 63 => 0000000000000000 (00000000 00000000)
- rldcl 0000001cbe991def, 0000000000000000, 0 => 0000001cbe991def (00000000 00000000)
- rldcl 0000001cbe991def, 0000000000000000, 7 => 0000001cbe991def (00000000 00000000)
- rldcl 0000001cbe991def, 0000000000000000, 14 => 0000001cbe991def (00000000 00000000)
- rldcl 0000001cbe991def, 0000000000000000, 21 => 0000001cbe991def (00000000 00000000)
- rldcl 0000001cbe991def, 0000000000000000, 28 => 0000000cbe991def (00000000 00000000)
- rldcl 0000001cbe991def, 0000000000000000, 35 => 000000001e991def (00000000 00000000)
- rldcl 0000001cbe991def, 0000000000000000, 42 => 0000000000191def (00000000 00000000)
- rldcl 0000001cbe991def, 0000000000000000, 49 => 0000000000001def (00000000 00000000)
- rldcl 0000001cbe991def, 0000000000000000, 56 => 00000000000000ef (00000000 00000000)
- rldcl 0000001cbe991def, 0000000000000000, 63 => 0000000000000001 (00000000 00000000)
- rldcl 0000001cbe991def, 0000001cbe991def, 0 => 8ef78000000e5f4c (00000000 00000000)
- rldcl 0000001cbe991def, 0000001cbe991def, 7 => 00f78000000e5f4c (00000000 00000000)
- rldcl 0000001cbe991def, 0000001cbe991def, 14 => 00038000000e5f4c (00000000 00000000)
- rldcl 0000001cbe991def, 0000001cbe991def, 21 => 00000000000e5f4c (00000000 00000000)
- rldcl 0000001cbe991def, 0000001cbe991def, 28 => 00000000000e5f4c (00000000 00000000)
- rldcl 0000001cbe991def, 0000001cbe991def, 35 => 00000000000e5f4c (00000000 00000000)
- rldcl 0000001cbe991def, 0000001cbe991def, 42 => 00000000000e5f4c (00000000 00000000)
- rldcl 0000001cbe991def, 0000001cbe991def, 49 => 0000000000005f4c (00000000 00000000)
- rldcl 0000001cbe991def, 0000001cbe991def, 56 => 000000000000004c (00000000 00000000)
- rldcl 0000001cbe991def, 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000)
- rldcl 0000001cbe991def, ffffffffffffffff, 0 => 8000000e5f4c8ef7 (00000000 00000000)
- rldcl 0000001cbe991def, ffffffffffffffff, 7 => 0000000e5f4c8ef7 (00000000 00000000)
- rldcl 0000001cbe991def, ffffffffffffffff, 14 => 0000000e5f4c8ef7 (00000000 00000000)
- rldcl 0000001cbe991def, ffffffffffffffff, 21 => 0000000e5f4c8ef7 (00000000 00000000)
- rldcl 0000001cbe991def, ffffffffffffffff, 28 => 0000000e5f4c8ef7 (00000000 00000000)
- rldcl 0000001cbe991def, ffffffffffffffff, 35 => 000000001f4c8ef7 (00000000 00000000)
- rldcl 0000001cbe991def, ffffffffffffffff, 42 => 00000000000c8ef7 (00000000 00000000)
- rldcl 0000001cbe991def, ffffffffffffffff, 49 => 0000000000000ef7 (00000000 00000000)
- rldcl 0000001cbe991def, ffffffffffffffff, 56 => 00000000000000f7 (00000000 00000000)
- rldcl 0000001cbe991def, ffffffffffffffff, 63 => 0000000000000001 (00000000 00000000)
- rldcl ffffffffffffffff, 0000000000000000, 0 => ffffffffffffffff (00000000 00000000)
- rldcl ffffffffffffffff, 0000000000000000, 7 => 01ffffffffffffff (00000000 00000000)
- rldcl ffffffffffffffff, 0000000000000000, 14 => 0003ffffffffffff (00000000 00000000)
- rldcl ffffffffffffffff, 0000000000000000, 21 => 000007ffffffffff (00000000 00000000)
- rldcl ffffffffffffffff, 0000000000000000, 28 => 0000000fffffffff (00000000 00000000)
- rldcl ffffffffffffffff, 0000000000000000, 35 => 000000001fffffff (00000000 00000000)
- rldcl ffffffffffffffff, 0000000000000000, 42 => 00000000003fffff (00000000 00000000)
- rldcl ffffffffffffffff, 0000000000000000, 49 => 0000000000007fff (00000000 00000000)
- rldcl ffffffffffffffff, 0000000000000000, 56 => 00000000000000ff (00000000 00000000)
- rldcl ffffffffffffffff, 0000000000000000, 63 => 0000000000000001 (00000000 00000000)
- rldcl ffffffffffffffff, 0000001cbe991def, 0 => ffffffffffffffff (00000000 00000000)
- rldcl ffffffffffffffff, 0000001cbe991def, 7 => 01ffffffffffffff (00000000 00000000)
- rldcl ffffffffffffffff, 0000001cbe991def, 14 => 0003ffffffffffff (00000000 00000000)
- rldcl ffffffffffffffff, 0000001cbe991def, 21 => 000007ffffffffff (00000000 00000000)
- rldcl ffffffffffffffff, 0000001cbe991def, 28 => 0000000fffffffff (00000000 00000000)
- rldcl ffffffffffffffff, 0000001cbe991def, 35 => 000000001fffffff (00000000 00000000)
- rldcl ffffffffffffffff, 0000001cbe991def, 42 => 00000000003fffff (00000000 00000000)
- rldcl ffffffffffffffff, 0000001cbe991def, 49 => 0000000000007fff (00000000 00000000)
- rldcl ffffffffffffffff, 0000001cbe991def, 56 => 00000000000000ff (00000000 00000000)
- rldcl ffffffffffffffff, 0000001cbe991def, 63 => 0000000000000001 (00000000 00000000)
- rldcl ffffffffffffffff, ffffffffffffffff, 0 => ffffffffffffffff (00000000 00000000)
- rldcl ffffffffffffffff, ffffffffffffffff, 7 => 01ffffffffffffff (00000000 00000000)
- rldcl ffffffffffffffff, ffffffffffffffff, 14 => 0003ffffffffffff (00000000 00000000)
- rldcl ffffffffffffffff, ffffffffffffffff, 21 => 000007ffffffffff (00000000 00000000)
- rldcl ffffffffffffffff, ffffffffffffffff, 28 => 0000000fffffffff (00000000 00000000)
- rldcl ffffffffffffffff, ffffffffffffffff, 35 => 000000001fffffff (00000000 00000000)
- rldcl ffffffffffffffff, ffffffffffffffff, 42 => 00000000003fffff (00000000 00000000)
- rldcl ffffffffffffffff, ffffffffffffffff, 49 => 0000000000007fff (00000000 00000000)
- rldcl ffffffffffffffff, ffffffffffffffff, 56 => 00000000000000ff (00000000 00000000)
- rldcl ffffffffffffffff, ffffffffffffffff, 63 => 0000000000000001 (00000000 00000000)
-
- rldcr 0000000000000000, 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, 0000000000000000, 7 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, 0000000000000000, 14 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, 0000000000000000, 21 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, 0000000000000000, 28 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, 0000000000000000, 35 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, 0000000000000000, 42 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, 0000000000000000, 49 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, 0000000000000000, 56 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, 0000000000000000, 63 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, 0000001cbe991def, 0 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, 0000001cbe991def, 7 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, 0000001cbe991def, 14 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, 0000001cbe991def, 21 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, 0000001cbe991def, 28 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, 0000001cbe991def, 35 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, 0000001cbe991def, 42 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, 0000001cbe991def, 49 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, 0000001cbe991def, 56 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, ffffffffffffffff, 0 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, ffffffffffffffff, 7 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, ffffffffffffffff, 14 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, ffffffffffffffff, 21 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, ffffffffffffffff, 28 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, ffffffffffffffff, 35 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, ffffffffffffffff, 42 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, ffffffffffffffff, 49 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, ffffffffffffffff, 56 => 0000000000000000 (00000000 00000000)
- rldcr 0000000000000000, ffffffffffffffff, 63 => 0000000000000000 (00000000 00000000)
- rldcr 0000001cbe991def, 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
- rldcr 0000001cbe991def, 0000000000000000, 7 => 0000000000000000 (00000000 00000000)
- rldcr 0000001cbe991def, 0000000000000000, 14 => 0000000000000000 (00000000 00000000)
- rldcr 0000001cbe991def, 0000000000000000, 21 => 0000000000000000 (00000000 00000000)
- rldcr 0000001cbe991def, 0000000000000000, 28 => 0000001800000000 (00000000 00000000)
- rldcr 0000001cbe991def, 0000000000000000, 35 => 0000001cb0000000 (00000000 00000000)
- rldcr 0000001cbe991def, 0000000000000000, 42 => 0000001cbe800000 (00000000 00000000)
- rldcr 0000001cbe991def, 0000000000000000, 49 => 0000001cbe990000 (00000000 00000000)
- rldcr 0000001cbe991def, 0000000000000000, 56 => 0000001cbe991d80 (00000000 00000000)
- rldcr 0000001cbe991def, 0000000000000000, 63 => 0000001cbe991def (00000000 00000000)
- rldcr 0000001cbe991def, 0000001cbe991def, 0 => 8000000000000000 (00000000 00000000)
- rldcr 0000001cbe991def, 0000001cbe991def, 7 => 8e00000000000000 (00000000 00000000)
- rldcr 0000001cbe991def, 0000001cbe991def, 14 => 8ef6000000000000 (00000000 00000000)
- rldcr 0000001cbe991def, 0000001cbe991def, 21 => 8ef7800000000000 (00000000 00000000)
- rldcr 0000001cbe991def, 0000001cbe991def, 28 => 8ef7800000000000 (00000000 00000000)
- rldcr 0000001cbe991def, 0000001cbe991def, 35 => 8ef7800000000000 (00000000 00000000)
- rldcr 0000001cbe991def, 0000001cbe991def, 42 => 8ef7800000000000 (00000000 00000000)
- rldcr 0000001cbe991def, 0000001cbe991def, 49 => 8ef78000000e4000 (00000000 00000000)
- rldcr 0000001cbe991def, 0000001cbe991def, 56 => 8ef78000000e5f00 (00000000 00000000)
- rldcr 0000001cbe991def, 0000001cbe991def, 63 => 8ef78000000e5f4c (00000000 00000000)
- rldcr 0000001cbe991def, ffffffffffffffff, 0 => 8000000000000000 (00000000 00000000)
- rldcr 0000001cbe991def, ffffffffffffffff, 7 => 8000000000000000 (00000000 00000000)
- rldcr 0000001cbe991def, ffffffffffffffff, 14 => 8000000000000000 (00000000 00000000)
- rldcr 0000001cbe991def, ffffffffffffffff, 21 => 8000000000000000 (00000000 00000000)
- rldcr 0000001cbe991def, ffffffffffffffff, 28 => 8000000800000000 (00000000 00000000)
- rldcr 0000001cbe991def, ffffffffffffffff, 35 => 8000000e50000000 (00000000 00000000)
- rldcr 0000001cbe991def, ffffffffffffffff, 42 => 8000000e5f400000 (00000000 00000000)
- rldcr 0000001cbe991def, ffffffffffffffff, 49 => 8000000e5f4c8000 (00000000 00000000)
- rldcr 0000001cbe991def, ffffffffffffffff, 56 => 8000000e5f4c8e80 (00000000 00000000)
- rldcr 0000001cbe991def, ffffffffffffffff, 63 => 8000000e5f4c8ef7 (00000000 00000000)
- rldcr ffffffffffffffff, 0000000000000000, 0 => 8000000000000000 (00000000 00000000)
- rldcr ffffffffffffffff, 0000000000000000, 7 => ff00000000000000 (00000000 00000000)
- rldcr ffffffffffffffff, 0000000000000000, 14 => fffe000000000000 (00000000 00000000)
- rldcr ffffffffffffffff, 0000000000000000, 21 => fffffc0000000000 (00000000 00000000)
- rldcr ffffffffffffffff, 0000000000000000, 28 => fffffff800000000 (00000000 00000000)
- rldcr ffffffffffffffff, 0000000000000000, 35 => fffffffff0000000 (00000000 00000000)
- rldcr ffffffffffffffff, 0000000000000000, 42 => ffffffffffe00000 (00000000 00000000)
- rldcr ffffffffffffffff, 0000000000000000, 49 => ffffffffffffc000 (00000000 00000000)
- rldcr ffffffffffffffff, 0000000000000000, 56 => ffffffffffffff80 (00000000 00000000)
- rldcr ffffffffffffffff, 0000000000000000, 63 => ffffffffffffffff (00000000 00000000)
- rldcr ffffffffffffffff, 0000001cbe991def, 0 => 8000000000000000 (00000000 00000000)
- rldcr ffffffffffffffff, 0000001cbe991def, 7 => ff00000000000000 (00000000 00000000)
- rldcr ffffffffffffffff, 0000001cbe991def, 14 => fffe000000000000 (00000000 00000000)
- rldcr ffffffffffffffff, 0000001cbe991def, 21 => fffffc0000000000 (00000000 00000000)
- rldcr ffffffffffffffff, 0000001cbe991def, 28 => fffffff800000000 (00000000 00000000)
- rldcr ffffffffffffffff, 0000001cbe991def, 35 => fffffffff0000000 (00000000 00000000)
- rldcr ffffffffffffffff, 0000001cbe991def, 42 => ffffffffffe00000 (00000000 00000000)
- rldcr ffffffffffffffff, 0000001cbe991def, 49 => ffffffffffffc000 (00000000 00000000)
- rldcr ffffffffffffffff, 0000001cbe991def, 56 => ffffffffffffff80 (00000000 00000000)
- rldcr ffffffffffffffff, 0000001cbe991def, 63 => ffffffffffffffff (00000000 00000000)
- rldcr ffffffffffffffff, ffffffffffffffff, 0 => 8000000000000000 (00000000 00000000)
- rldcr ffffffffffffffff, ffffffffffffffff, 7 => ff00000000000000 (00000000 00000000)
- rldcr ffffffffffffffff, ffffffffffffffff, 14 => fffe000000000000 (00000000 00000000)
- rldcr ffffffffffffffff, ffffffffffffffff, 21 => fffffc0000000000 (00000000 00000000)
- rldcr ffffffffffffffff, ffffffffffffffff, 28 => fffffff800000000 (00000000 00000000)
- rldcr ffffffffffffffff, ffffffffffffffff, 35 => fffffffff0000000 (00000000 00000000)
- rldcr ffffffffffffffff, ffffffffffffffff, 42 => ffffffffffe00000 (00000000 00000000)
- rldcr ffffffffffffffff, ffffffffffffffff, 49 => ffffffffffffc000 (00000000 00000000)
- rldcr ffffffffffffffff, ffffffffffffffff, 56 => ffffffffffffff80 (00000000 00000000)
- rldcr ffffffffffffffff, ffffffffffffffff, 63 => ffffffffffffffff (00000000 00000000)
-
- rldic 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 0, 7 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 0, 14 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 0, 21 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 0, 28 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 0, 35 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 0, 42 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 0, 49 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 0, 56 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 0, 63 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 7, 0 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 7, 7 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 7, 14 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 7, 21 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 7, 28 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 7, 35 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 7, 42 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 7, 49 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 7, 56 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 7, 63 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 14, 0 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 14, 7 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 14, 14 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 14, 21 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 14, 28 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 14, 35 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 14, 42 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 14, 49 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 14, 56 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 14, 63 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 21, 0 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 21, 7 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 21, 14 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 21, 21 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 21, 28 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 21, 35 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 21, 42 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 21, 49 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 21, 56 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 21, 63 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 28, 0 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 28, 7 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 28, 14 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 28, 21 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 28, 28 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 28, 35 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 28, 42 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 28, 49 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 28, 56 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 28, 63 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 35, 0 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 35, 7 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 35, 14 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 35, 21 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 35, 28 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 35, 35 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 35, 42 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 35, 49 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 35, 56 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 35, 63 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 42, 0 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 42, 7 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 42, 14 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 42, 21 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 42, 28 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 42, 35 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 42, 42 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 42, 49 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 42, 56 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 42, 63 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 49, 0 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 49, 7 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 49, 14 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 49, 21 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 49, 28 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 49, 35 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 49, 42 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 49, 49 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 49, 56 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 49, 63 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 56, 0 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 56, 7 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 56, 14 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 56, 21 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 56, 28 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 56, 35 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 56, 42 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 56, 49 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 56, 56 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 56, 63 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 63, 0 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 63, 7 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 63, 14 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 63, 21 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 63, 28 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 63, 35 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 63, 42 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 63, 49 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 63, 56 => 0000000000000000 (00000000 00000000)
- rldic 0000000000000000, 63, 63 => 0000000000000000 (00000000 00000000)
- rldic 0000001cbe991def, 0, 0 => 0000001cbe991def (00000000 00000000)
- rldic 0000001cbe991def, 0, 7 => 0000001cbe991def (00000000 00000000)
- rldic 0000001cbe991def, 0, 14 => 0000001cbe991def (00000000 00000000)
- rldic 0000001cbe991def, 0, 21 => 0000001cbe991def (00000000 00000000)
- rldic 0000001cbe991def, 0, 28 => 0000000cbe991def (00000000 00000000)
- rldic 0000001cbe991def, 0, 35 => 000000001e991def (00000000 00000000)
- rldic 0000001cbe991def, 0, 42 => 0000000000191def (00000000 00000000)
- rldic 0000001cbe991def, 0, 49 => 0000000000001def (00000000 00000000)
- rldic 0000001cbe991def, 0, 56 => 00000000000000ef (00000000 00000000)
- rldic 0000001cbe991def, 0, 63 => 0000000000000001 (00000000 00000000)
- rldic 0000001cbe991def, 7, 0 => 00000e5f4c8ef780 (00000000 00000000)
- rldic 0000001cbe991def, 7, 7 => 00000e5f4c8ef780 (00000000 00000000)
- rldic 0000001cbe991def, 7, 14 => 00000e5f4c8ef780 (00000000 00000000)
- rldic 0000001cbe991def, 7, 21 => 0000065f4c8ef780 (00000000 00000000)
- rldic 0000001cbe991def, 7, 28 => 0000000f4c8ef780 (00000000 00000000)
- rldic 0000001cbe991def, 7, 35 => 000000000c8ef780 (00000000 00000000)
- rldic 0000001cbe991def, 7, 42 => 00000000000ef780 (00000000 00000000)
- rldic 0000001cbe991def, 7, 49 => 0000000000007780 (00000000 00000000)
- rldic 0000001cbe991def, 7, 56 => 0000000000000080 (00000000 00000000)
- rldic 0000001cbe991def, 7, 63 => 00000e5f4c8ef780 (00000000 00000000)
- rldic 0000001cbe991def, 14, 0 => 00072fa6477bc000 (00000000 00000000)
- rldic 0000001cbe991def, 14, 7 => 00072fa6477bc000 (00000000 00000000)
- rldic 0000001cbe991def, 14, 14 => 00032fa6477bc000 (00000000 00000000)
- rldic 0000001cbe991def, 14, 21 => 000007a6477bc000 (00000000 00000000)
- rldic 0000001cbe991def, 14, 28 => 00000006477bc000 (00000000 00000000)
- rldic 0000001cbe991def, 14, 35 => 00000000077bc000 (00000000 00000000)
- rldic 0000001cbe991def, 14, 42 => 00000000003bc000 (00000000 00000000)
- rldic 0000001cbe991def, 14, 49 => 0000000000004000 (00000000 00000000)
- rldic 0000001cbe991def, 14, 56 => 00072fa6477bc000 (00000000 00000000)
- rldic 0000001cbe991def, 14, 63 => 00072fa6477bc000 (00000000 00000000)
- rldic 0000001cbe991def, 21, 0 => 0397d323bde00000 (00000000 00000000)
- rldic 0000001cbe991def, 21, 7 => 0197d323bde00000 (00000000 00000000)
- rldic 0000001cbe991def, 21, 14 => 0003d323bde00000 (00000000 00000000)
- rldic 0000001cbe991def, 21, 21 => 00000323bde00000 (00000000 00000000)
- rldic 0000001cbe991def, 21, 28 => 00000003bde00000 (00000000 00000000)
- rldic 0000001cbe991def, 21, 35 => 000000001de00000 (00000000 00000000)
- rldic 0000001cbe991def, 21, 42 => 0000000000200000 (00000000 00000000)
- rldic 0000001cbe991def, 21, 49 => 0397d323bde00000 (00000000 00000000)
- rldic 0000001cbe991def, 21, 56 => 0397d323bde00000 (00000000 00000000)
- rldic 0000001cbe991def, 21, 63 => 0397d323bde00000 (00000000 00000000)
- rldic 0000001cbe991def, 28, 0 => cbe991def0000000 (00000000 00000000)
- rldic 0000001cbe991def, 28, 7 => 01e991def0000000 (00000000 00000000)
- rldic 0000001cbe991def, 28, 14 => 000191def0000000 (00000000 00000000)
- rldic 0000001cbe991def, 28, 21 => 000001def0000000 (00000000 00000000)
- rldic 0000001cbe991def, 28, 28 => 0000000ef0000000 (00000000 00000000)
- rldic 0000001cbe991def, 28, 35 => 0000000010000000 (00000000 00000000)
- rldic 0000001cbe991def, 28, 42 => cbe991def0000001 (00000000 00000000)
- rldic 0000001cbe991def, 28, 49 => cbe991def0000001 (00000000 00000000)
- rldic 0000001cbe991def, 28, 56 => cbe991def0000001 (00000000 00000000)
- rldic 0000001cbe991def, 28, 63 => cbe991def0000001 (00000000 00000000)
- rldic 0000001cbe991def, 35, 0 => f4c8ef7800000000 (00000000 00000000)
- rldic 0000001cbe991def, 35, 7 => 00c8ef7800000000 (00000000 00000000)
- rldic 0000001cbe991def, 35, 14 => 0000ef7800000000 (00000000 00000000)
- rldic 0000001cbe991def, 35, 21 => 0000077800000000 (00000000 00000000)
- rldic 0000001cbe991def, 35, 28 => 0000000800000000 (00000000 00000000)
- rldic 0000001cbe991def, 35, 35 => f4c8ef78000000e5 (00000000 00000000)
- rldic 0000001cbe991def, 35, 42 => f4c8ef78000000e5 (00000000 00000000)
- rldic 0000001cbe991def, 35, 49 => f4c8ef78000000e5 (00000000 00000000)
- rldic 0000001cbe991def, 35, 56 => f4c8ef78000000e5 (00000000 00000000)
- rldic 0000001cbe991def, 35, 63 => f4c8ef7800000001 (00000000 00000000)
- rldic 0000001cbe991def, 42, 0 => 6477bc0000000000 (00000000 00000000)
- rldic 0000001cbe991def, 42, 7 => 0077bc0000000000 (00000000 00000000)
- rldic 0000001cbe991def, 42, 14 => 0003bc0000000000 (00000000 00000000)
- rldic 0000001cbe991def, 42, 21 => 0000040000000000 (00000000 00000000)
- rldic 0000001cbe991def, 42, 28 => 6477bc00000072fa (00000000 00000000)
- rldic 0000001cbe991def, 42, 35 => 6477bc00000072fa (00000000 00000000)
- rldic 0000001cbe991def, 42, 42 => 6477bc00000072fa (00000000 00000000)
- rldic 0000001cbe991def, 42, 49 => 6477bc00000072fa (00000000 00000000)
- rldic 0000001cbe991def, 42, 56 => 6477bc00000000fa (00000000 00000000)
- rldic 0000001cbe991def, 42, 63 => 6477bc0000000000 (00000000 00000000)
- rldic 0000001cbe991def, 49, 0 => 3bde000000000000 (00000000 00000000)
- rldic 0000001cbe991def, 49, 7 => 01de000000000000 (00000000 00000000)
- rldic 0000001cbe991def, 49, 14 => 0002000000000000 (00000000 00000000)
- rldic 0000001cbe991def, 49, 21 => 3bde000000397d32 (00000000 00000000)
- rldic 0000001cbe991def, 49, 28 => 3bde000000397d32 (00000000 00000000)
- rldic 0000001cbe991def, 49, 35 => 3bde000000397d32 (00000000 00000000)
- rldic 0000001cbe991def, 49, 42 => 3bde000000397d32 (00000000 00000000)
- rldic 0000001cbe991def, 49, 49 => 3bde000000007d32 (00000000 00000000)
- rldic 0000001cbe991def, 49, 56 => 3bde000000000032 (00000000 00000000)
- rldic 0000001cbe991def, 49, 63 => 3bde000000000000 (00000000 00000000)
- rldic 0000001cbe991def, 56, 0 => ef00000000000000 (00000000 00000000)
- rldic 0000001cbe991def, 56, 7 => 0100000000000000 (00000000 00000000)
- rldic 0000001cbe991def, 56, 14 => ef0000001cbe991d (00000000 00000000)
- rldic 0000001cbe991def, 56, 21 => ef0000001cbe991d (00000000 00000000)
- rldic 0000001cbe991def, 56, 28 => ef0000001cbe991d (00000000 00000000)
- rldic 0000001cbe991def, 56, 35 => ef0000001cbe991d (00000000 00000000)
- rldic 0000001cbe991def, 56, 42 => ef000000003e991d (00000000 00000000)
- rldic 0000001cbe991def, 56, 49 => ef0000000000191d (00000000 00000000)
- rldic 0000001cbe991def, 56, 56 => ef0000000000001d (00000000 00000000)
- rldic 0000001cbe991def, 56, 63 => ef00000000000001 (00000000 00000000)
- rldic 0000001cbe991def, 63, 0 => 8000000000000000 (00000000 00000000)
- rldic 0000001cbe991def, 63, 7 => 8000000e5f4c8ef7 (00000000 00000000)
- rldic 0000001cbe991def, 63, 14 => 8000000e5f4c8ef7 (00000000 00000000)
- rldic 0000001cbe991def, 63, 21 => 8000000e5f4c8ef7 (00000000 00000000)
- rldic 0000001cbe991def, 63, 28 => 8000000e5f4c8ef7 (00000000 00000000)
- rldic 0000001cbe991def, 63, 35 => 800000001f4c8ef7 (00000000 00000000)
- rldic 0000001cbe991def, 63, 42 => 80000000000c8ef7 (00000000 00000000)
- rldic 0000001cbe991def, 63, 49 => 8000000000000ef7 (00000000 00000000)
- rldic 0000001cbe991def, 63, 56 => 80000000000000f7 (00000000 00000000)
- rldic 0000001cbe991def, 63, 63 => 8000000000000001 (00000000 00000000)
- rldic ffffffffffffffff, 0, 0 => ffffffffffffffff (00000000 00000000)
- rldic ffffffffffffffff, 0, 7 => 01ffffffffffffff (00000000 00000000)
- rldic ffffffffffffffff, 0, 14 => 0003ffffffffffff (00000000 00000000)
- rldic ffffffffffffffff, 0, 21 => 000007ffffffffff (00000000 00000000)
- rldic ffffffffffffffff, 0, 28 => 0000000fffffffff (00000000 00000000)
- rldic ffffffffffffffff, 0, 35 => 000000001fffffff (00000000 00000000)
- rldic ffffffffffffffff, 0, 42 => 00000000003fffff (00000000 00000000)
- rldic ffffffffffffffff, 0, 49 => 0000000000007fff (00000000 00000000)
- rldic ffffffffffffffff, 0, 56 => 00000000000000ff (00000000 00000000)
- rldic ffffffffffffffff, 0, 63 => 0000000000000001 (00000000 00000000)
- rldic ffffffffffffffff, 7, 0 => ffffffffffffff80 (00000000 00000000)
- rldic ffffffffffffffff, 7, 7 => 01ffffffffffff80 (00000000 00000000)
- rldic ffffffffffffffff, 7, 14 => 0003ffffffffff80 (00000000 00000000)
- rldic ffffffffffffffff, 7, 21 => 000007ffffffff80 (00000000 00000000)
- rldic ffffffffffffffff, 7, 28 => 0000000fffffff80 (00000000 00000000)
- rldic ffffffffffffffff, 7, 35 => 000000001fffff80 (00000000 00000000)
- rldic ffffffffffffffff, 7, 42 => 00000000003fff80 (00000000 00000000)
- rldic ffffffffffffffff, 7, 49 => 0000000000007f80 (00000000 00000000)
- rldic ffffffffffffffff, 7, 56 => 0000000000000080 (00000000 00000000)
- rldic ffffffffffffffff, 7, 63 => ffffffffffffff81 (00000000 00000000)
- rldic ffffffffffffffff, 14, 0 => ffffffffffffc000 (00000000 00000000)
- rldic ffffffffffffffff, 14, 7 => 01ffffffffffc000 (00000000 00000000)
- rldic ffffffffffffffff, 14, 14 => 0003ffffffffc000 (00000000 00000000)
- rldic ffffffffffffffff, 14, 21 => 000007ffffffc000 (00000000 00000000)
- rldic ffffffffffffffff, 14, 28 => 0000000fffffc000 (00000000 00000000)
- rldic ffffffffffffffff, 14, 35 => 000000001fffc000 (00000000 00000000)
- rldic ffffffffffffffff, 14, 42 => 00000000003fc000 (00000000 00000000)
- rldic ffffffffffffffff, 14, 49 => 0000000000004000 (00000000 00000000)
- rldic ffffffffffffffff, 14, 56 => ffffffffffffc0ff (00000000 00000000)
- rldic ffffffffffffffff, 14, 63 => ffffffffffffc001 (00000000 00000000)
- rldic ffffffffffffffff, 21, 0 => ffffffffffe00000 (00000000 00000000)
- rldic ffffffffffffffff, 21, 7 => 01ffffffffe00000 (00000000 00000000)
- rldic ffffffffffffffff, 21, 14 => 0003ffffffe00000 (00000000 00000000)
- rldic ffffffffffffffff, 21, 21 => 000007ffffe00000 (00000000 00000000)
- rldic ffffffffffffffff, 21, 28 => 0000000fffe00000 (00000000 00000000)
- rldic ffffffffffffffff, 21, 35 => 000000001fe00000 (00000000 00000000)
- rldic ffffffffffffffff, 21, 42 => 0000000000200000 (00000000 00000000)
- rldic ffffffffffffffff, 21, 49 => ffffffffffe07fff (00000000 00000000)
- rldic ffffffffffffffff, 21, 56 => ffffffffffe000ff (00000000 00000000)
- rldic ffffffffffffffff, 21, 63 => ffffffffffe00001 (00000000 00000000)
- rldic ffffffffffffffff, 28, 0 => fffffffff0000000 (00000000 00000000)
- rldic ffffffffffffffff, 28, 7 => 01fffffff0000000 (00000000 00000000)
- rldic ffffffffffffffff, 28, 14 => 0003fffff0000000 (00000000 00000000)
- rldic ffffffffffffffff, 28, 21 => 000007fff0000000 (00000000 00000000)
- rldic ffffffffffffffff, 28, 28 => 0000000ff0000000 (00000000 00000000)
- rldic ffffffffffffffff, 28, 35 => 0000000010000000 (00000000 00000000)
- rldic ffffffffffffffff, 28, 42 => fffffffff03fffff (00000000 00000000)
- rldic ffffffffffffffff, 28, 49 => fffffffff0007fff (00000000 00000000)
- rldic ffffffffffffffff, 28, 56 => fffffffff00000ff (00000000 00000000)
- rldic ffffffffffffffff, 28, 63 => fffffffff0000001 (00000000 00000000)
- rldic ffffffffffffffff, 35, 0 => fffffff800000000 (00000000 00000000)
- rldic ffffffffffffffff, 35, 7 => 01fffff800000000 (00000000 00000000)
- rldic ffffffffffffffff, 35, 14 => 0003fff800000000 (00000000 00000000)
- rldic ffffffffffffffff, 35, 21 => 000007f800000000 (00000000 00000000)
- rldic ffffffffffffffff, 35, 28 => 0000000800000000 (00000000 00000000)
- rldic ffffffffffffffff, 35, 35 => fffffff81fffffff (00000000 00000000)
- rldic ffffffffffffffff, 35, 42 => fffffff8003fffff (00000000 00000000)
- rldic ffffffffffffffff, 35, 49 => fffffff800007fff (00000000 00000000)
- rldic ffffffffffffffff, 35, 56 => fffffff8000000ff (00000000 00000000)
- rldic ffffffffffffffff, 35, 63 => fffffff800000001 (00000000 00000000)
- rldic ffffffffffffffff, 42, 0 => fffffc0000000000 (00000000 00000000)
- rldic ffffffffffffffff, 42, 7 => 01fffc0000000000 (00000000 00000000)
- rldic ffffffffffffffff, 42, 14 => 0003fc0000000000 (00000000 00000000)
- rldic ffffffffffffffff, 42, 21 => 0000040000000000 (00000000 00000000)
- rldic ffffffffffffffff, 42, 28 => fffffc0fffffffff (00000000 00000000)
- rldic ffffffffffffffff, 42, 35 => fffffc001fffffff (00000000 00000000)
- rldic ffffffffffffffff, 42, 42 => fffffc00003fffff (00000000 00000000)
- rldic ffffffffffffffff, 42, 49 => fffffc0000007fff (00000000 00000000)
- rldic ffffffffffffffff, 42, 56 => fffffc00000000ff (00000000 00000000)
- rldic ffffffffffffffff, 42, 63 => fffffc0000000001 (00000000 00000000)
- rldic ffffffffffffffff, 49, 0 => fffe000000000000 (00000000 00000000)
- rldic ffffffffffffffff, 49, 7 => 01fe000000000000 (00000000 00000000)
- rldic ffffffffffffffff, 49, 14 => 0002000000000000 (00000000 00000000)
- rldic ffffffffffffffff, 49, 21 => fffe07ffffffffff (00000000 00000000)
- rldic ffffffffffffffff, 49, 28 => fffe000fffffffff (00000000 00000000)
- rldic ffffffffffffffff, 49, 35 => fffe00001fffffff (00000000 00000000)
- rldic ffffffffffffffff, 49, 42 => fffe0000003fffff (00000000 00000000)
- rldic ffffffffffffffff, 49, 49 => fffe000000007fff (00000000 00000000)
- rldic ffffffffffffffff, 49, 56 => fffe0000000000ff (00000000 00000000)
- rldic ffffffffffffffff, 49, 63 => fffe000000000001 (00000000 00000000)
- rldic ffffffffffffffff, 56, 0 => ff00000000000000 (00000000 00000000)
- rldic ffffffffffffffff, 56, 7 => 0100000000000000 (00000000 00000000)
- rldic ffffffffffffffff, 56, 14 => ff03ffffffffffff (00000000 00000000)
- rldic ffffffffffffffff, 56, 21 => ff0007ffffffffff (00000000 00000000)
- rldic ffffffffffffffff, 56, 28 => ff00000fffffffff (00000000 00000000)
- rldic ffffffffffffffff, 56, 35 => ff0000001fffffff (00000000 00000000)
- rldic ffffffffffffffff, 56, 42 => ff000000003fffff (00000000 00000000)
- rldic ffffffffffffffff, 56, 49 => ff00000000007fff (00000000 00000000)
- rldic ffffffffffffffff, 56, 56 => ff000000000000ff (00000000 00000000)
- rldic ffffffffffffffff, 56, 63 => ff00000000000001 (00000000 00000000)
- rldic ffffffffffffffff, 63, 0 => 8000000000000000 (00000000 00000000)
- rldic ffffffffffffffff, 63, 7 => 81ffffffffffffff (00000000 00000000)
- rldic ffffffffffffffff, 63, 14 => 8003ffffffffffff (00000000 00000000)
- rldic ffffffffffffffff, 63, 21 => 800007ffffffffff (00000000 00000000)
- rldic ffffffffffffffff, 63, 28 => 8000000fffffffff (00000000 00000000)
- rldic ffffffffffffffff, 63, 35 => 800000001fffffff (00000000 00000000)
- rldic ffffffffffffffff, 63, 42 => 80000000003fffff (00000000 00000000)
- rldic ffffffffffffffff, 63, 49 => 8000000000007fff (00000000 00000000)
- rldic ffffffffffffffff, 63, 56 => 80000000000000ff (00000000 00000000)
- rldic ffffffffffffffff, 63, 63 => 8000000000000001 (00000000 00000000)
-
- rldicl 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 0, 7 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 0, 14 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 0, 21 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 0, 28 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 0, 35 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 0, 42 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 0, 49 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 0, 56 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 0, 63 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 7, 0 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 7, 7 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 7, 14 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 7, 21 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 7, 28 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 7, 35 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 7, 42 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 7, 49 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 7, 56 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 7, 63 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 14, 0 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 14, 7 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 14, 14 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 14, 21 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 14, 28 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 14, 35 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 14, 42 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 14, 49 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 14, 56 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 14, 63 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 21, 0 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 21, 7 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 21, 14 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 21, 21 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 21, 28 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 21, 35 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 21, 42 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 21, 49 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 21, 56 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 21, 63 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 28, 0 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 28, 7 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 28, 14 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 28, 21 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 28, 28 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 28, 35 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 28, 42 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 28, 49 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 28, 56 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 28, 63 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 35, 0 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 35, 7 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 35, 14 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 35, 21 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 35, 28 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 35, 35 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 35, 42 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 35, 49 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 35, 56 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 35, 63 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 42, 0 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 42, 7 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 42, 14 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 42, 21 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 42, 28 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 42, 35 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 42, 42 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 42, 49 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 42, 56 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 42, 63 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 49, 0 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 49, 7 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 49, 14 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 49, 21 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 49, 28 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 49, 35 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 49, 42 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 49, 49 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 49, 56 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 49, 63 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 56, 0 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 56, 7 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 56, 14 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 56, 21 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 56, 28 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 56, 35 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 56, 42 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 56, 49 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 56, 56 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 56, 63 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 63, 0 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 63, 7 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 63, 14 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 63, 21 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 63, 28 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 63, 35 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 63, 42 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 63, 49 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 63, 56 => 0000000000000000 (00000000 00000000)
- rldicl 0000000000000000, 63, 63 => 0000000000000000 (00000000 00000000)
- rldicl 0000001cbe991def, 0, 0 => 0000001cbe991def (00000000 00000000)
- rldicl 0000001cbe991def, 0, 7 => 0000001cbe991def (00000000 00000000)
- rldicl 0000001cbe991def, 0, 14 => 0000001cbe991def (00000000 00000000)
- rldicl 0000001cbe991def, 0, 21 => 0000001cbe991def (00000000 00000000)
- rldicl 0000001cbe991def, 0, 28 => 0000000cbe991def (00000000 00000000)
- rldicl 0000001cbe991def, 0, 35 => 000000001e991def (00000000 00000000)
- rldicl 0000001cbe991def, 0, 42 => 0000000000191def (00000000 00000000)
- rldicl 0000001cbe991def, 0, 49 => 0000000000001def (00000000 00000000)
- rldicl 0000001cbe991def, 0, 56 => 00000000000000ef (00000000 00000000)
- rldicl 0000001cbe991def, 0, 63 => 0000000000000001 (00000000 00000000)
- rldicl 0000001cbe991def, 7, 0 => 00000e5f4c8ef780 (00000000 00000000)
- rldicl 0000001cbe991def, 7, 7 => 00000e5f4c8ef780 (00000000 00000000)
- rldicl 0000001cbe991def, 7, 14 => 00000e5f4c8ef780 (00000000 00000000)
- rldicl 0000001cbe991def, 7, 21 => 0000065f4c8ef780 (00000000 00000000)
- rldicl 0000001cbe991def, 7, 28 => 0000000f4c8ef780 (00000000 00000000)
- rldicl 0000001cbe991def, 7, 35 => 000000000c8ef780 (00000000 00000000)
- rldicl 0000001cbe991def, 7, 42 => 00000000000ef780 (00000000 00000000)
- rldicl 0000001cbe991def, 7, 49 => 0000000000007780 (00000000 00000000)
- rldicl 0000001cbe991def, 7, 56 => 0000000000000080 (00000000 00000000)
- rldicl 0000001cbe991def, 7, 63 => 0000000000000000 (00000000 00000000)
- rldicl 0000001cbe991def, 14, 0 => 00072fa6477bc000 (00000000 00000000)
- rldicl 0000001cbe991def, 14, 7 => 00072fa6477bc000 (00000000 00000000)
- rldicl 0000001cbe991def, 14, 14 => 00032fa6477bc000 (00000000 00000000)
- rldicl 0000001cbe991def, 14, 21 => 000007a6477bc000 (00000000 00000000)
- rldicl 0000001cbe991def, 14, 28 => 00000006477bc000 (00000000 00000000)
- rldicl 0000001cbe991def, 14, 35 => 00000000077bc000 (00000000 00000000)
- rldicl 0000001cbe991def, 14, 42 => 00000000003bc000 (00000000 00000000)
- rldicl 0000001cbe991def, 14, 49 => 0000000000004000 (00000000 00000000)
- rldicl 0000001cbe991def, 14, 56 => 0000000000000000 (00000000 00000000)
- rldicl 0000001cbe991def, 14, 63 => 0000000000000000 (00000000 00000000)
- rldicl 0000001cbe991def, 21, 0 => 0397d323bde00000 (00000000 00000000)
- rldicl 0000001cbe991def, 21, 7 => 0197d323bde00000 (00000000 00000000)
- rldicl 0000001cbe991def, 21, 14 => 0003d323bde00000 (00000000 00000000)
- rldicl 0000001cbe991def, 21, 21 => 00000323bde00000 (00000000 00000000)
- rldicl 0000001cbe991def, 21, 28 => 00000003bde00000 (00000000 00000000)
- rldicl 0000001cbe991def, 21, 35 => 000000001de00000 (00000000 00000000)
- rldicl 0000001cbe991def, 21, 42 => 0000000000200000 (00000000 00000000)
- rldicl 0000001cbe991def, 21, 49 => 0000000000000000 (00000000 00000000)
- rldicl 0000001cbe991def, 21, 56 => 0000000000000000 (00000000 00000000)
- rldicl 0000001cbe991def, 21, 63 => 0000000000000000 (00000000 00000000)
- rldicl 0000001cbe991def, 28, 0 => cbe991def0000001 (00000000 00000000)
- rldicl 0000001cbe991def, 28, 7 => 01e991def0000001 (00000000 00000000)
- rldicl 0000001cbe991def, 28, 14 => 000191def0000001 (00000000 00000000)
- rldicl 0000001cbe991def, 28, 21 => 000001def0000001 (00000000 00000000)
- rldicl 0000001cbe991def, 28, 28 => 0000000ef0000001 (00000000 00000000)
- rldicl 0000001cbe991def, 28, 35 => 0000000010000001 (00000000 00000000)
- rldicl 0000001cbe991def, 28, 42 => 0000000000000001 (00000000 00000000)
- rldicl 0000001cbe991def, 28, 49 => 0000000000000001 (00000000 00000000)
- rldicl 0000001cbe991def, 28, 56 => 0000000000000001 (00000000 00000000)
- rldicl 0000001cbe991def, 28, 63 => 0000000000000001 (00000000 00000000)
- rldicl 0000001cbe991def, 35, 0 => f4c8ef78000000e5 (00000000 00000000)
- rldicl 0000001cbe991def, 35, 7 => 00c8ef78000000e5 (00000000 00000000)
- rldicl 0000001cbe991def, 35, 14 => 0000ef78000000e5 (00000000 00000000)
- rldicl 0000001cbe991def, 35, 21 => 00000778000000e5 (00000000 00000000)
- rldicl 0000001cbe991def, 35, 28 => 00000008000000e5 (00000000 00000000)
- rldicl 0000001cbe991def, 35, 35 => 00000000000000e5 (00000000 00000000)
- rldicl 0000001cbe991def, 35, 42 => 00000000000000e5 (00000000 00000000)
- rldicl 0000001cbe991def, 35, 49 => 00000000000000e5 (00000000 00000000)
- rldicl 0000001cbe991def, 35, 56 => 00000000000000e5 (00000000 00000000)
- rldicl 0000001cbe991def, 35, 63 => 0000000000000001 (00000000 00000000)
- rldicl 0000001cbe991def, 42, 0 => 6477bc00000072fa (00000000 00000000)
- rldicl 0000001cbe991def, 42, 7 => 0077bc00000072fa (00000000 00000000)
- rldicl 0000001cbe991def, 42, 14 => 0003bc00000072fa (00000000 00000000)
- rldicl 0000001cbe991def, 42, 21 => 00000400000072fa (00000000 00000000)
- rldicl 0000001cbe991def, 42, 28 => 00000000000072fa (00000000 00000000)
- rldicl 0000001cbe991def, 42, 35 => 00000000000072fa (00000000 00000000)
- rldicl 0000001cbe991def, 42, 42 => 00000000000072fa (00000000 00000000)
- rldicl 0000001cbe991def, 42, 49 => 00000000000072fa (00000000 00000000)
- rldicl 0000001cbe991def, 42, 56 => 00000000000000fa (00000000 00000000)
- rldicl 0000001cbe991def, 42, 63 => 0000000000000000 (00000000 00000000)
- rldicl 0000001cbe991def, 49, 0 => 3bde000000397d32 (00000000 00000000)
- rldicl 0000001cbe991def, 49, 7 => 01de000000397d32 (00000000 00000000)
- rldicl 0000001cbe991def, 49, 14 => 0002000000397d32 (00000000 00000000)
- rldicl 0000001cbe991def, 49, 21 => 0000000000397d32 (00000000 00000000)
- rldicl 0000001cbe991def, 49, 28 => 0000000000397d32 (00000000 00000000)
- rldicl 0000001cbe991def, 49, 35 => 0000000000397d32 (00000000 00000000)
- rldicl 0000001cbe991def, 49, 42 => 0000000000397d32 (00000000 00000000)
- rldicl 0000001cbe991def, 49, 49 => 0000000000007d32 (00000000 00000000)
- rldicl 0000001cbe991def, 49, 56 => 0000000000000032 (00000000 00000000)
- rldicl 0000001cbe991def, 49, 63 => 0000000000000000 (00000000 00000000)
- rldicl 0000001cbe991def, 56, 0 => ef0000001cbe991d (00000000 00000000)
- rldicl 0000001cbe991def, 56, 7 => 010000001cbe991d (00000000 00000000)
- rldicl 0000001cbe991def, 56, 14 => 000000001cbe991d (00000000 00000000)
- rldicl 0000001cbe991def, 56, 21 => 000000001cbe991d (00000000 00000000)
- rldicl 0000001cbe991def, 56, 28 => 000000001cbe991d (00000000 00000000)
- rldicl 0000001cbe991def, 56, 35 => 000000001cbe991d (00000000 00000000)
- rldicl 0000001cbe991def, 56, 42 => 00000000003e991d (00000000 00000000)
- rldicl 0000001cbe991def, 56, 49 => 000000000000191d (00000000 00000000)
- rldicl 0000001cbe991def, 56, 56 => 000000000000001d (00000000 00000000)
- rldicl 0000001cbe991def, 56, 63 => 0000000000000001 (00000000 00000000)
- rldicl 0000001cbe991def, 63, 0 => 8000000e5f4c8ef7 (00000000 00000000)
- rldicl 0000001cbe991def, 63, 7 => 0000000e5f4c8ef7 (00000000 00000000)
- rldicl 0000001cbe991def, 63, 14 => 0000000e5f4c8ef7 (00000000 00000000)
- rldicl 0000001cbe991def, 63, 21 => 0000000e5f4c8ef7 (00000000 00000000)
- rldicl 0000001cbe991def, 63, 28 => 0000000e5f4c8ef7 (00000000 00000000)
- rldicl 0000001cbe991def, 63, 35 => 000000001f4c8ef7 (00000000 00000000)
- rldicl 0000001cbe991def, 63, 42 => 00000000000c8ef7 (00000000 00000000)
- rldicl 0000001cbe991def, 63, 49 => 0000000000000ef7 (00000000 00000000)
- rldicl 0000001cbe991def, 63, 56 => 00000000000000f7 (00000000 00000000)
- rldicl 0000001cbe991def, 63, 63 => 0000000000000001 (00000000 00000000)
- rldicl ffffffffffffffff, 0, 0 => ffffffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 0, 7 => 01ffffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 0, 14 => 0003ffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 0, 21 => 000007ffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 0, 28 => 0000000fffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 0, 35 => 000000001fffffff (00000000 00000000)
- rldicl ffffffffffffffff, 0, 42 => 00000000003fffff (00000000 00000000)
- rldicl ffffffffffffffff, 0, 49 => 0000000000007fff (00000000 00000000)
- rldicl ffffffffffffffff, 0, 56 => 00000000000000ff (00000000 00000000)
- rldicl ffffffffffffffff, 0, 63 => 0000000000000001 (00000000 00000000)
- rldicl ffffffffffffffff, 7, 0 => ffffffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 7, 7 => 01ffffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 7, 14 => 0003ffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 7, 21 => 000007ffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 7, 28 => 0000000fffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 7, 35 => 000000001fffffff (00000000 00000000)
- rldicl ffffffffffffffff, 7, 42 => 00000000003fffff (00000000 00000000)
- rldicl ffffffffffffffff, 7, 49 => 0000000000007fff (00000000 00000000)
- rldicl ffffffffffffffff, 7, 56 => 00000000000000ff (00000000 00000000)
- rldicl ffffffffffffffff, 7, 63 => 0000000000000001 (00000000 00000000)
- rldicl ffffffffffffffff, 14, 0 => ffffffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 14, 7 => 01ffffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 14, 14 => 0003ffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 14, 21 => 000007ffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 14, 28 => 0000000fffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 14, 35 => 000000001fffffff (00000000 00000000)
- rldicl ffffffffffffffff, 14, 42 => 00000000003fffff (00000000 00000000)
- rldicl ffffffffffffffff, 14, 49 => 0000000000007fff (00000000 00000000)
- rldicl ffffffffffffffff, 14, 56 => 00000000000000ff (00000000 00000000)
- rldicl ffffffffffffffff, 14, 63 => 0000000000000001 (00000000 00000000)
- rldicl ffffffffffffffff, 21, 0 => ffffffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 21, 7 => 01ffffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 21, 14 => 0003ffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 21, 21 => 000007ffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 21, 28 => 0000000fffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 21, 35 => 000000001fffffff (00000000 00000000)
- rldicl ffffffffffffffff, 21, 42 => 00000000003fffff (00000000 00000000)
- rldicl ffffffffffffffff, 21, 49 => 0000000000007fff (00000000 00000000)
- rldicl ffffffffffffffff, 21, 56 => 00000000000000ff (00000000 00000000)
- rldicl ffffffffffffffff, 21, 63 => 0000000000000001 (00000000 00000000)
- rldicl ffffffffffffffff, 28, 0 => ffffffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 28, 7 => 01ffffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 28, 14 => 0003ffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 28, 21 => 000007ffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 28, 28 => 0000000fffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 28, 35 => 000000001fffffff (00000000 00000000)
- rldicl ffffffffffffffff, 28, 42 => 00000000003fffff (00000000 00000000)
- rldicl ffffffffffffffff, 28, 49 => 0000000000007fff (00000000 00000000)
- rldicl ffffffffffffffff, 28, 56 => 00000000000000ff (00000000 00000000)
- rldicl ffffffffffffffff, 28, 63 => 0000000000000001 (00000000 00000000)
- rldicl ffffffffffffffff, 35, 0 => ffffffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 35, 7 => 01ffffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 35, 14 => 0003ffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 35, 21 => 000007ffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 35, 28 => 0000000fffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 35, 35 => 000000001fffffff (00000000 00000000)
- rldicl ffffffffffffffff, 35, 42 => 00000000003fffff (00000000 00000000)
- rldicl ffffffffffffffff, 35, 49 => 0000000000007fff (00000000 00000000)
- rldicl ffffffffffffffff, 35, 56 => 00000000000000ff (00000000 00000000)
- rldicl ffffffffffffffff, 35, 63 => 0000000000000001 (00000000 00000000)
- rldicl ffffffffffffffff, 42, 0 => ffffffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 42, 7 => 01ffffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 42, 14 => 0003ffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 42, 21 => 000007ffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 42, 28 => 0000000fffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 42, 35 => 000000001fffffff (00000000 00000000)
- rldicl ffffffffffffffff, 42, 42 => 00000000003fffff (00000000 00000000)
- rldicl ffffffffffffffff, 42, 49 => 0000000000007fff (00000000 00000000)
- rldicl ffffffffffffffff, 42, 56 => 00000000000000ff (00000000 00000000)
- rldicl ffffffffffffffff, 42, 63 => 0000000000000001 (00000000 00000000)
- rldicl ffffffffffffffff, 49, 0 => ffffffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 49, 7 => 01ffffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 49, 14 => 0003ffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 49, 21 => 000007ffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 49, 28 => 0000000fffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 49, 35 => 000000001fffffff (00000000 00000000)
- rldicl ffffffffffffffff, 49, 42 => 00000000003fffff (00000000 00000000)
- rldicl ffffffffffffffff, 49, 49 => 0000000000007fff (00000000 00000000)
- rldicl ffffffffffffffff, 49, 56 => 00000000000000ff (00000000 00000000)
- rldicl ffffffffffffffff, 49, 63 => 0000000000000001 (00000000 00000000)
- rldicl ffffffffffffffff, 56, 0 => ffffffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 56, 7 => 01ffffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 56, 14 => 0003ffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 56, 21 => 000007ffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 56, 28 => 0000000fffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 56, 35 => 000000001fffffff (00000000 00000000)
- rldicl ffffffffffffffff, 56, 42 => 00000000003fffff (00000000 00000000)
- rldicl ffffffffffffffff, 56, 49 => 0000000000007fff (00000000 00000000)
- rldicl ffffffffffffffff, 56, 56 => 00000000000000ff (00000000 00000000)
- rldicl ffffffffffffffff, 56, 63 => 0000000000000001 (00000000 00000000)
- rldicl ffffffffffffffff, 63, 0 => ffffffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 63, 7 => 01ffffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 63, 14 => 0003ffffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 63, 21 => 000007ffffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 63, 28 => 0000000fffffffff (00000000 00000000)
- rldicl ffffffffffffffff, 63, 35 => 000000001fffffff (00000000 00000000)
- rldicl ffffffffffffffff, 63, 42 => 00000000003fffff (00000000 00000000)
- rldicl ffffffffffffffff, 63, 49 => 0000000000007fff (00000000 00000000)
- rldicl ffffffffffffffff, 63, 56 => 00000000000000ff (00000000 00000000)
- rldicl ffffffffffffffff, 63, 63 => 0000000000000001 (00000000 00000000)
-
- rldicr 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 0, 7 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 0, 14 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 0, 21 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 0, 28 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 0, 35 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 0, 42 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 0, 49 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 0, 56 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 0, 63 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 7, 0 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 7, 7 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 7, 14 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 7, 21 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 7, 28 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 7, 35 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 7, 42 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 7, 49 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 7, 56 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 7, 63 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 14, 0 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 14, 7 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 14, 14 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 14, 21 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 14, 28 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 14, 35 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 14, 42 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 14, 49 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 14, 56 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 14, 63 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 21, 0 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 21, 7 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 21, 14 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 21, 21 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 21, 28 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 21, 35 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 21, 42 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 21, 49 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 21, 56 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 21, 63 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 28, 0 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 28, 7 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 28, 14 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 28, 21 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 28, 28 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 28, 35 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 28, 42 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 28, 49 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 28, 56 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 28, 63 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 35, 0 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 35, 7 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 35, 14 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 35, 21 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 35, 28 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 35, 35 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 35, 42 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 35, 49 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 35, 56 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 35, 63 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 42, 0 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 42, 7 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 42, 14 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 42, 21 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 42, 28 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 42, 35 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 42, 42 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 42, 49 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 42, 56 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 42, 63 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 49, 0 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 49, 7 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 49, 14 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 49, 21 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 49, 28 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 49, 35 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 49, 42 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 49, 49 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 49, 56 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 49, 63 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 56, 0 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 56, 7 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 56, 14 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 56, 21 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 56, 28 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 56, 35 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 56, 42 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 56, 49 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 56, 56 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 56, 63 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 63, 0 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 63, 7 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 63, 14 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 63, 21 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 63, 28 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 63, 35 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 63, 42 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 63, 49 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 63, 56 => 0000000000000000 (00000000 00000000)
- rldicr 0000000000000000, 63, 63 => 0000000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 0, 0 => 0000000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 0, 7 => 0000000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 0, 14 => 0000000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 0, 21 => 0000000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 0, 28 => 0000001800000000 (00000000 00000000)
- rldicr 0000001cbe991def, 0, 35 => 0000001cb0000000 (00000000 00000000)
- rldicr 0000001cbe991def, 0, 42 => 0000001cbe800000 (00000000 00000000)
- rldicr 0000001cbe991def, 0, 49 => 0000001cbe990000 (00000000 00000000)
- rldicr 0000001cbe991def, 0, 56 => 0000001cbe991d80 (00000000 00000000)
- rldicr 0000001cbe991def, 0, 63 => 0000001cbe991def (00000000 00000000)
- rldicr 0000001cbe991def, 7, 0 => 0000000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 7, 7 => 0000000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 7, 14 => 0000000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 7, 21 => 00000c0000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 7, 28 => 00000e5800000000 (00000000 00000000)
- rldicr 0000001cbe991def, 7, 35 => 00000e5f40000000 (00000000 00000000)
- rldicr 0000001cbe991def, 7, 42 => 00000e5f4c800000 (00000000 00000000)
- rldicr 0000001cbe991def, 7, 49 => 00000e5f4c8ec000 (00000000 00000000)
- rldicr 0000001cbe991def, 7, 56 => 00000e5f4c8ef780 (00000000 00000000)
- rldicr 0000001cbe991def, 7, 63 => 00000e5f4c8ef780 (00000000 00000000)
- rldicr 0000001cbe991def, 14, 0 => 0000000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 14, 7 => 0000000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 14, 14 => 0006000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 14, 21 => 00072c0000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 14, 28 => 00072fa000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 14, 35 => 00072fa640000000 (00000000 00000000)
- rldicr 0000001cbe991def, 14, 42 => 00072fa647600000 (00000000 00000000)
- rldicr 0000001cbe991def, 14, 49 => 00072fa6477bc000 (00000000 00000000)
- rldicr 0000001cbe991def, 14, 56 => 00072fa6477bc000 (00000000 00000000)
- rldicr 0000001cbe991def, 14, 63 => 00072fa6477bc000 (00000000 00000000)
- rldicr 0000001cbe991def, 21, 0 => 0000000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 21, 7 => 0300000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 21, 14 => 0396000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 21, 21 => 0397d00000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 21, 28 => 0397d32000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 21, 35 => 0397d323b0000000 (00000000 00000000)
- rldicr 0000001cbe991def, 21, 42 => 0397d323bde00000 (00000000 00000000)
- rldicr 0000001cbe991def, 21, 49 => 0397d323bde00000 (00000000 00000000)
- rldicr 0000001cbe991def, 21, 56 => 0397d323bde00000 (00000000 00000000)
- rldicr 0000001cbe991def, 21, 63 => 0397d323bde00000 (00000000 00000000)
- rldicr 0000001cbe991def, 28, 0 => 8000000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 28, 7 => cb00000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 28, 14 => cbe8000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 28, 21 => cbe9900000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 28, 28 => cbe991d800000000 (00000000 00000000)
- rldicr 0000001cbe991def, 28, 35 => cbe991def0000000 (00000000 00000000)
- rldicr 0000001cbe991def, 28, 42 => cbe991def0000000 (00000000 00000000)
- rldicr 0000001cbe991def, 28, 49 => cbe991def0000000 (00000000 00000000)
- rldicr 0000001cbe991def, 28, 56 => cbe991def0000000 (00000000 00000000)
- rldicr 0000001cbe991def, 28, 63 => cbe991def0000001 (00000000 00000000)
- rldicr 0000001cbe991def, 35, 0 => 8000000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 35, 7 => f400000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 35, 14 => f4c8000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 35, 21 => f4c8ec0000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 35, 28 => f4c8ef7800000000 (00000000 00000000)
- rldicr 0000001cbe991def, 35, 35 => f4c8ef7800000000 (00000000 00000000)
- rldicr 0000001cbe991def, 35, 42 => f4c8ef7800000000 (00000000 00000000)
- rldicr 0000001cbe991def, 35, 49 => f4c8ef7800000000 (00000000 00000000)
- rldicr 0000001cbe991def, 35, 56 => f4c8ef7800000080 (00000000 00000000)
- rldicr 0000001cbe991def, 35, 63 => f4c8ef78000000e5 (00000000 00000000)
- rldicr 0000001cbe991def, 42, 0 => 0000000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 42, 7 => 6400000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 42, 14 => 6476000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 42, 21 => 6477bc0000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 42, 28 => 6477bc0000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 42, 35 => 6477bc0000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 42, 42 => 6477bc0000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 42, 49 => 6477bc0000004000 (00000000 00000000)
- rldicr 0000001cbe991def, 42, 56 => 6477bc0000007280 (00000000 00000000)
- rldicr 0000001cbe991def, 42, 63 => 6477bc00000072fa (00000000 00000000)
- rldicr 0000001cbe991def, 49, 0 => 0000000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 49, 7 => 3b00000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 49, 14 => 3bde000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 49, 21 => 3bde000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 49, 28 => 3bde000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 49, 35 => 3bde000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 49, 42 => 3bde000000200000 (00000000 00000000)
- rldicr 0000001cbe991def, 49, 49 => 3bde000000394000 (00000000 00000000)
- rldicr 0000001cbe991def, 49, 56 => 3bde000000397d00 (00000000 00000000)
- rldicr 0000001cbe991def, 49, 63 => 3bde000000397d32 (00000000 00000000)
- rldicr 0000001cbe991def, 56, 0 => 8000000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 56, 7 => ef00000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 56, 14 => ef00000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 56, 21 => ef00000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 56, 28 => ef00000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 56, 35 => ef00000010000000 (00000000 00000000)
- rldicr 0000001cbe991def, 56, 42 => ef0000001ca00000 (00000000 00000000)
- rldicr 0000001cbe991def, 56, 49 => ef0000001cbe8000 (00000000 00000000)
- rldicr 0000001cbe991def, 56, 56 => ef0000001cbe9900 (00000000 00000000)
- rldicr 0000001cbe991def, 56, 63 => ef0000001cbe991d (00000000 00000000)
- rldicr 0000001cbe991def, 63, 0 => 8000000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 63, 7 => 8000000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 63, 14 => 8000000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 63, 21 => 8000000000000000 (00000000 00000000)
- rldicr 0000001cbe991def, 63, 28 => 8000000800000000 (00000000 00000000)
- rldicr 0000001cbe991def, 63, 35 => 8000000e50000000 (00000000 00000000)
- rldicr 0000001cbe991def, 63, 42 => 8000000e5f400000 (00000000 00000000)
- rldicr 0000001cbe991def, 63, 49 => 8000000e5f4c8000 (00000000 00000000)
- rldicr 0000001cbe991def, 63, 56 => 8000000e5f4c8e80 (00000000 00000000)
- rldicr 0000001cbe991def, 63, 63 => 8000000e5f4c8ef7 (00000000 00000000)
- rldicr ffffffffffffffff, 0, 0 => 8000000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 0, 7 => ff00000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 0, 14 => fffe000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 0, 21 => fffffc0000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 0, 28 => fffffff800000000 (00000000 00000000)
- rldicr ffffffffffffffff, 0, 35 => fffffffff0000000 (00000000 00000000)
- rldicr ffffffffffffffff, 0, 42 => ffffffffffe00000 (00000000 00000000)
- rldicr ffffffffffffffff, 0, 49 => ffffffffffffc000 (00000000 00000000)
- rldicr ffffffffffffffff, 0, 56 => ffffffffffffff80 (00000000 00000000)
- rldicr ffffffffffffffff, 0, 63 => ffffffffffffffff (00000000 00000000)
- rldicr ffffffffffffffff, 7, 0 => 8000000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 7, 7 => ff00000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 7, 14 => fffe000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 7, 21 => fffffc0000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 7, 28 => fffffff800000000 (00000000 00000000)
- rldicr ffffffffffffffff, 7, 35 => fffffffff0000000 (00000000 00000000)
- rldicr ffffffffffffffff, 7, 42 => ffffffffffe00000 (00000000 00000000)
- rldicr ffffffffffffffff, 7, 49 => ffffffffffffc000 (00000000 00000000)
- rldicr ffffffffffffffff, 7, 56 => ffffffffffffff80 (00000000 00000000)
- rldicr ffffffffffffffff, 7, 63 => ffffffffffffffff (00000000 00000000)
- rldicr ffffffffffffffff, 14, 0 => 8000000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 14, 7 => ff00000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 14, 14 => fffe000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 14, 21 => fffffc0000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 14, 28 => fffffff800000000 (00000000 00000000)
- rldicr ffffffffffffffff, 14, 35 => fffffffff0000000 (00000000 00000000)
- rldicr ffffffffffffffff, 14, 42 => ffffffffffe00000 (00000000 00000000)
- rldicr ffffffffffffffff, 14, 49 => ffffffffffffc000 (00000000 00000000)
- rldicr ffffffffffffffff, 14, 56 => ffffffffffffff80 (00000000 00000000)
- rldicr ffffffffffffffff, 14, 63 => ffffffffffffffff (00000000 00000000)
- rldicr ffffffffffffffff, 21, 0 => 8000000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 21, 7 => ff00000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 21, 14 => fffe000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 21, 21 => fffffc0000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 21, 28 => fffffff800000000 (00000000 00000000)
- rldicr ffffffffffffffff, 21, 35 => fffffffff0000000 (00000000 00000000)
- rldicr ffffffffffffffff, 21, 42 => ffffffffffe00000 (00000000 00000000)
- rldicr ffffffffffffffff, 21, 49 => ffffffffffffc000 (00000000 00000000)
- rldicr ffffffffffffffff, 21, 56 => ffffffffffffff80 (00000000 00000000)
- rldicr ffffffffffffffff, 21, 63 => ffffffffffffffff (00000000 00000000)
- rldicr ffffffffffffffff, 28, 0 => 8000000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 28, 7 => ff00000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 28, 14 => fffe000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 28, 21 => fffffc0000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 28, 28 => fffffff800000000 (00000000 00000000)
- rldicr ffffffffffffffff, 28, 35 => fffffffff0000000 (00000000 00000000)
- rldicr ffffffffffffffff, 28, 42 => ffffffffffe00000 (00000000 00000000)
- rldicr ffffffffffffffff, 28, 49 => ffffffffffffc000 (00000000 00000000)
- rldicr ffffffffffffffff, 28, 56 => ffffffffffffff80 (00000000 00000000)
- rldicr ffffffffffffffff, 28, 63 => ffffffffffffffff (00000000 00000000)
- rldicr ffffffffffffffff, 35, 0 => 8000000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 35, 7 => ff00000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 35, 14 => fffe000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 35, 21 => fffffc0000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 35, 28 => fffffff800000000 (00000000 00000000)
- rldicr ffffffffffffffff, 35, 35 => fffffffff0000000 (00000000 00000000)
- rldicr ffffffffffffffff, 35, 42 => ffffffffffe00000 (00000000 00000000)
- rldicr ffffffffffffffff, 35, 49 => ffffffffffffc000 (00000000 00000000)
- rldicr ffffffffffffffff, 35, 56 => ffffffffffffff80 (00000000 00000000)
- rldicr ffffffffffffffff, 35, 63 => ffffffffffffffff (00000000 00000000)
- rldicr ffffffffffffffff, 42, 0 => 8000000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 42, 7 => ff00000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 42, 14 => fffe000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 42, 21 => fffffc0000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 42, 28 => fffffff800000000 (00000000 00000000)
- rldicr ffffffffffffffff, 42, 35 => fffffffff0000000 (00000000 00000000)
- rldicr ffffffffffffffff, 42, 42 => ffffffffffe00000 (00000000 00000000)
- rldicr ffffffffffffffff, 42, 49 => ffffffffffffc000 (00000000 00000000)
- rldicr ffffffffffffffff, 42, 56 => ffffffffffffff80 (00000000 00000000)
- rldicr ffffffffffffffff, 42, 63 => ffffffffffffffff (00000000 00000000)
- rldicr ffffffffffffffff, 49, 0 => 8000000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 49, 7 => ff00000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 49, 14 => fffe000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 49, 21 => fffffc0000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 49, 28 => fffffff800000000 (00000000 00000000)
- rldicr ffffffffffffffff, 49, 35 => fffffffff0000000 (00000000 00000000)
- rldicr ffffffffffffffff, 49, 42 => ffffffffffe00000 (00000000 00000000)
- rldicr ffffffffffffffff, 49, 49 => ffffffffffffc000 (00000000 00000000)
- rldicr ffffffffffffffff, 49, 56 => ffffffffffffff80 (00000000 00000000)
- rldicr ffffffffffffffff, 49, 63 => ffffffffffffffff (00000000 00000000)
- rldicr ffffffffffffffff, 56, 0 => 8000000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 56, 7 => ff00000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 56, 14 => fffe000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 56, 21 => fffffc0000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 56, 28 => fffffff800000000 (00000000 00000000)
- rldicr ffffffffffffffff, 56, 35 => fffffffff0000000 (00000000 00000000)
- rldicr ffffffffffffffff, 56, 42 => ffffffffffe00000 (00000000 00000000)
- rldicr ffffffffffffffff, 56, 49 => ffffffffffffc000 (00000000 00000000)
- rldicr ffffffffffffffff, 56, 56 => ffffffffffffff80 (00000000 00000000)
- rldicr ffffffffffffffff, 56, 63 => ffffffffffffffff (00000000 00000000)
- rldicr ffffffffffffffff, 63, 0 => 8000000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 63, 7 => ff00000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 63, 14 => fffe000000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 63, 21 => fffffc0000000000 (00000000 00000000)
- rldicr ffffffffffffffff, 63, 28 => fffffff800000000 (00000000 00000000)
- rldicr ffffffffffffffff, 63, 35 => fffffffff0000000 (00000000 00000000)
- rldicr ffffffffffffffff, 63, 42 => ffffffffffe00000 (00000000 00000000)
- rldicr ffffffffffffffff, 63, 49 => ffffffffffffc000 (00000000 00000000)
- rldicr ffffffffffffffff, 63, 56 => ffffffffffffff80 (00000000 00000000)
- rldicr ffffffffffffffff, 63, 63 => ffffffffffffffff (00000000 00000000)
-
- rldimi 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 0, 7 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 0, 14 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 0, 21 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 0, 28 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 0, 35 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 0, 42 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 0, 49 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 0, 56 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 0, 63 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 7, 0 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 7, 7 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 7, 14 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 7, 21 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 7, 28 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 7, 35 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 7, 42 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 7, 49 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 7, 56 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 7, 63 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 14, 0 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 14, 7 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 14, 14 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 14, 21 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 14, 28 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 14, 35 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 14, 42 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 14, 49 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 14, 56 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 14, 63 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 21, 0 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 21, 7 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 21, 14 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 21, 21 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 21, 28 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 21, 35 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 21, 42 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 21, 49 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 21, 56 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 21, 63 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 28, 0 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 28, 7 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 28, 14 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 28, 21 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 28, 28 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 28, 35 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 28, 42 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 28, 49 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 28, 56 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 28, 63 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 35, 0 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 35, 7 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 35, 14 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 35, 21 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 35, 28 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 35, 35 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 35, 42 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 35, 49 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 35, 56 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 35, 63 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 42, 0 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 42, 7 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 42, 14 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 42, 21 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 42, 28 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 42, 35 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 42, 42 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 42, 49 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 42, 56 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 42, 63 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 49, 0 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 49, 7 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 49, 14 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 49, 21 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 49, 28 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 49, 35 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 49, 42 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 49, 49 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 49, 56 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 49, 63 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 56, 0 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 56, 7 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 56, 14 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 56, 21 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 56, 28 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 56, 35 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 56, 42 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 56, 49 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 56, 56 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 56, 63 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 63, 0 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 63, 7 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 63, 14 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 63, 21 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 63, 28 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 63, 35 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 63, 42 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 63, 49 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 63, 56 => 0000000000000000 (00000000 00000000)
- rldimi 0000000000000000, 63, 63 => 0000000000000000 (00000000 00000000)
- rldimi 0000001cbe991def, 0, 0 => 0000001cbe991def (00000000 00000000)
- rldimi 0000001cbe991def, 0, 7 => 0000001cbe991def (00000000 00000000)
- rldimi 0000001cbe991def, 0, 14 => 0000001cbe991def (00000000 00000000)
- rldimi 0000001cbe991def, 0, 21 => 0000001cbe991def (00000000 00000000)
- rldimi 0000001cbe991def, 0, 28 => 0000001cbe991def (00000000 00000000)
- rldimi 0000001cbe991def, 0, 35 => 0000001cbe991def (00000000 00000000)
- rldimi 0000001cbe991def, 0, 42 => 0000001cbe991def (00000000 00000000)
- rldimi 0000001cbe991def, 0, 49 => 0000001cbe991def (00000000 00000000)
- rldimi 0000001cbe991def, 0, 56 => 0000001cbe991def (00000000 00000000)
- rldimi 0000001cbe991def, 0, 63 => 0000001cbe991def (00000000 00000000)
- rldimi 0000001cbe991def, 7, 0 => 00000e5f4c8ef7ef (00000000 00000000)
- rldimi 0000001cbe991def, 7, 7 => 00000e5f4c8ef7ef (00000000 00000000)
- rldimi 0000001cbe991def, 7, 14 => 00000e5f4c8ef7ef (00000000 00000000)
- rldimi 0000001cbe991def, 7, 21 => 00000e5f4c8ef7ef (00000000 00000000)
- rldimi 0000001cbe991def, 7, 28 => 00000e5f4c8ef7ef (00000000 00000000)
- rldimi 0000001cbe991def, 7, 35 => 00000e5f4c8ef7ef (00000000 00000000)
- rldimi 0000001cbe991def, 7, 42 => 00000e5f4c8ef7ef (00000000 00000000)
- rldimi 0000001cbe991def, 7, 49 => 00000e5f4c8ef7ef (00000000 00000000)
- rldimi 0000001cbe991def, 7, 56 => 00000e5f4c8ef7ef (00000000 00000000)
- rldimi 0000001cbe991def, 7, 63 => 00000e5f4c8ef7ee (00000000 00000000)
- rldimi 0000001cbe991def, 14, 0 => 00072fa6477bf7ee (00000000 00000000)
- rldimi 0000001cbe991def, 14, 7 => 00072fa6477bf7ee (00000000 00000000)
- rldimi 0000001cbe991def, 14, 14 => 00072fa6477bf7ee (00000000 00000000)
- rldimi 0000001cbe991def, 14, 21 => 00072fa6477bf7ee (00000000 00000000)
- rldimi 0000001cbe991def, 14, 28 => 00072fa6477bf7ee (00000000 00000000)
- rldimi 0000001cbe991def, 14, 35 => 00072fa6477bf7ee (00000000 00000000)
- rldimi 0000001cbe991def, 14, 42 => 00072fa6477bf7ee (00000000 00000000)
- rldimi 0000001cbe991def, 14, 49 => 00072fa6477bf7ee (00000000 00000000)
- rldimi 0000001cbe991def, 14, 56 => 00072fa6477bf700 (00000000 00000000)
- rldimi 0000001cbe991def, 14, 63 => 00072fa6477bf700 (00000000 00000000)
- rldimi 0000001cbe991def, 21, 0 => 0397d323bdfbf700 (00000000 00000000)
- rldimi 0000001cbe991def, 21, 7 => 0397d323bdfbf700 (00000000 00000000)
- rldimi 0000001cbe991def, 21, 14 => 0397d323bdfbf700 (00000000 00000000)
- rldimi 0000001cbe991def, 21, 21 => 0397d323bdfbf700 (00000000 00000000)
- rldimi 0000001cbe991def, 21, 28 => 0397d323bdfbf700 (00000000 00000000)
- rldimi 0000001cbe991def, 21, 35 => 0397d323bdfbf700 (00000000 00000000)
- rldimi 0000001cbe991def, 21, 42 => 0397d323bdfbf700 (00000000 00000000)
- rldimi 0000001cbe991def, 21, 49 => 0397d323bdfb8000 (00000000 00000000)
- rldimi 0000001cbe991def, 21, 56 => 0397d323bdfb8000 (00000000 00000000)
- rldimi 0000001cbe991def, 21, 63 => 0397d323bdfb8000 (00000000 00000000)
- rldimi 0000001cbe991def, 28, 0 => cbe991defdfb8000 (00000000 00000000)
- rldimi 0000001cbe991def, 28, 7 => cbe991defdfb8000 (00000000 00000000)
- rldimi 0000001cbe991def, 28, 14 => cbe991defdfb8000 (00000000 00000000)
- rldimi 0000001cbe991def, 28, 21 => cbe991defdfb8000 (00000000 00000000)
- rldimi 0000001cbe991def, 28, 28 => cbe991defdfb8000 (00000000 00000000)
- rldimi 0000001cbe991def, 28, 35 => cbe991defdfb8000 (00000000 00000000)
- rldimi 0000001cbe991def, 28, 42 => cbe991defdc00001 (00000000 00000000)
- rldimi 0000001cbe991def, 28, 49 => cbe991defdc00001 (00000000 00000000)
- rldimi 0000001cbe991def, 28, 56 => cbe991defdc00001 (00000000 00000000)
- rldimi 0000001cbe991def, 28, 63 => cbe991defdc00001 (00000000 00000000)
- rldimi 0000001cbe991def, 35, 0 => f4c8ef7efdc00001 (00000000 00000000)
- rldimi 0000001cbe991def, 35, 7 => f4c8ef7efdc00001 (00000000 00000000)
- rldimi 0000001cbe991def, 35, 14 => f4c8ef7efdc00001 (00000000 00000000)
- rldimi 0000001cbe991def, 35, 21 => f4c8ef7efdc00001 (00000000 00000000)
- rldimi 0000001cbe991def, 35, 28 => f4c8ef7efdc00001 (00000000 00000000)
- rldimi 0000001cbe991def, 35, 35 => f4c8ef7ee00000e5 (00000000 00000000)
- rldimi 0000001cbe991def, 35, 42 => f4c8ef7ee00000e5 (00000000 00000000)
- rldimi 0000001cbe991def, 35, 49 => f4c8ef7ee00000e5 (00000000 00000000)
- rldimi 0000001cbe991def, 35, 56 => f4c8ef7ee00000e5 (00000000 00000000)
- rldimi 0000001cbe991def, 35, 63 => f4c8ef7ee00000e5 (00000000 00000000)
- rldimi 0000001cbe991def, 42, 0 => 6477bf7ee00000e5 (00000000 00000000)
- rldimi 0000001cbe991def, 42, 7 => 6477bf7ee00000e5 (00000000 00000000)
- rldimi 0000001cbe991def, 42, 14 => 6477bf7ee00000e5 (00000000 00000000)
- rldimi 0000001cbe991def, 42, 21 => 6477bf7ee00000e5 (00000000 00000000)
- rldimi 0000001cbe991def, 42, 28 => 6477bf70000072fa (00000000 00000000)
- rldimi 0000001cbe991def, 42, 35 => 6477bf70000072fa (00000000 00000000)
- rldimi 0000001cbe991def, 42, 42 => 6477bf70000072fa (00000000 00000000)
- rldimi 0000001cbe991def, 42, 49 => 6477bf70000072fa (00000000 00000000)
- rldimi 0000001cbe991def, 42, 56 => 6477bf70000072fa (00000000 00000000)
- rldimi 0000001cbe991def, 42, 63 => 6477bf70000072fa (00000000 00000000)
- rldimi 0000001cbe991def, 49, 0 => 3bdfbf70000072fa (00000000 00000000)
- rldimi 0000001cbe991def, 49, 7 => 3bdfbf70000072fa (00000000 00000000)
- rldimi 0000001cbe991def, 49, 14 => 3bdfbf70000072fa (00000000 00000000)
- rldimi 0000001cbe991def, 49, 21 => 3bdfb80000397d32 (00000000 00000000)
- rldimi 0000001cbe991def, 49, 28 => 3bdfb80000397d32 (00000000 00000000)
- rldimi 0000001cbe991def, 49, 35 => 3bdfb80000397d32 (00000000 00000000)
- rldimi 0000001cbe991def, 49, 42 => 3bdfb80000397d32 (00000000 00000000)
- rldimi 0000001cbe991def, 49, 49 => 3bdfb80000397d32 (00000000 00000000)
- rldimi 0000001cbe991def, 49, 56 => 3bdfb80000397d32 (00000000 00000000)
- rldimi 0000001cbe991def, 49, 63 => 3bdfb80000397d32 (00000000 00000000)
- rldimi 0000001cbe991def, 56, 0 => efdfb80000397d32 (00000000 00000000)
- rldimi 0000001cbe991def, 56, 7 => efdfb80000397d32 (00000000 00000000)
- rldimi 0000001cbe991def, 56, 14 => efdc00001cbe991d (00000000 00000000)
- rldimi 0000001cbe991def, 56, 21 => efdc00001cbe991d (00000000 00000000)
- rldimi 0000001cbe991def, 56, 28 => efdc00001cbe991d (00000000 00000000)
- rldimi 0000001cbe991def, 56, 35 => efdc00001cbe991d (00000000 00000000)
- rldimi 0000001cbe991def, 56, 42 => efdc00001cbe991d (00000000 00000000)
- rldimi 0000001cbe991def, 56, 49 => efdc00001cbe991d (00000000 00000000)
- rldimi 0000001cbe991def, 56, 56 => efdc00001cbe991d (00000000 00000000)
- rldimi 0000001cbe991def, 56, 63 => efdc00001cbe991d (00000000 00000000)
- rldimi 0000001cbe991def, 63, 0 => efdc00001cbe991d (00000000 00000000)
- rldimi 0000001cbe991def, 63, 7 => ee00000e5f4c8ef7 (00000000 00000000)
- rldimi 0000001cbe991def, 63, 14 => ee00000e5f4c8ef7 (00000000 00000000)
- rldimi 0000001cbe991def, 63, 21 => ee00000e5f4c8ef7 (00000000 00000000)
- rldimi 0000001cbe991def, 63, 28 => ee00000e5f4c8ef7 (00000000 00000000)
- rldimi 0000001cbe991def, 63, 35 => ee00000e5f4c8ef7 (00000000 00000000)
- rldimi 0000001cbe991def, 63, 42 => ee00000e5f4c8ef7 (00000000 00000000)
- rldimi 0000001cbe991def, 63, 49 => ee00000e5f4c8ef7 (00000000 00000000)
- rldimi 0000001cbe991def, 63, 56 => ee00000e5f4c8ef7 (00000000 00000000)
- rldimi 0000001cbe991def, 63, 63 => ee00000e5f4c8ef7 (00000000 00000000)
- rldimi ffffffffffffffff, 0, 0 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 0, 7 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 0, 14 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 0, 21 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 0, 28 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 0, 35 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 0, 42 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 0, 49 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 0, 56 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 0, 63 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 7, 0 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 7, 7 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 7, 14 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 7, 21 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 7, 28 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 7, 35 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 7, 42 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 7, 49 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 7, 56 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 7, 63 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 14, 0 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 14, 7 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 14, 14 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 14, 21 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 14, 28 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 14, 35 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 14, 42 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 14, 49 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 14, 56 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 14, 63 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 21, 0 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 21, 7 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 21, 14 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 21, 21 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 21, 28 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 21, 35 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 21, 42 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 21, 49 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 21, 56 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 21, 63 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 28, 0 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 28, 7 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 28, 14 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 28, 21 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 28, 28 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 28, 35 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 28, 42 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 28, 49 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 28, 56 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 28, 63 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 35, 0 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 35, 7 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 35, 14 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 35, 21 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 35, 28 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 35, 35 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 35, 42 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 35, 49 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 35, 56 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 35, 63 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 42, 0 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 42, 7 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 42, 14 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 42, 21 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 42, 28 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 42, 35 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 42, 42 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 42, 49 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 42, 56 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 42, 63 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 49, 0 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 49, 7 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 49, 14 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 49, 21 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 49, 28 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 49, 35 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 49, 42 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 49, 49 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 49, 56 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 49, 63 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 56, 0 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 56, 7 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 56, 14 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 56, 21 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 56, 28 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 56, 35 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 56, 42 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 56, 49 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 56, 56 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 56, 63 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 63, 0 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 63, 7 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 63, 14 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 63, 21 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 63, 28 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 63, 35 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 63, 42 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 63, 49 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 63, 56 => ffffffffffffffff (00000000 00000000)
- rldimi ffffffffffffffff, 63, 63 => ffffffffffffffff (00000000 00000000)
-
- sradi 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
- sradi 0000000000000000, 7 => 0000000000000000 (00000000 00000000)
- sradi 0000000000000000, 14 => 0000000000000000 (00000000 00000000)
- sradi 0000000000000000, 21 => 0000000000000000 (00000000 00000000)
- sradi 0000000000000000, 28 => 0000000000000000 (00000000 00000000)
- sradi 0000000000000000, 35 => 0000000000000000 (00000000 00000000)
- sradi 0000000000000000, 42 => 0000000000000000 (00000000 00000000)
- sradi 0000000000000000, 49 => 0000000000000000 (00000000 00000000)
- sradi 0000000000000000, 56 => 0000000000000000 (00000000 00000000)
- sradi 0000000000000000, 63 => 0000000000000000 (00000000 00000000)
- sradi 0000001cbe991def, 0 => 0000001cbe991def (00000000 00000000)
- sradi 0000001cbe991def, 7 => 00000000397d323b (00000000 00000000)
- sradi 0000001cbe991def, 14 => 000000000072fa64 (00000000 00000000)
- sradi 0000001cbe991def, 21 => 000000000000e5f4 (00000000 00000000)
- sradi 0000001cbe991def, 28 => 00000000000001cb (00000000 00000000)
- sradi 0000001cbe991def, 35 => 0000000000000003 (00000000 00000000)
- sradi 0000001cbe991def, 42 => 0000000000000000 (00000000 00000000)
- sradi 0000001cbe991def, 49 => 0000000000000000 (00000000 00000000)
- sradi 0000001cbe991def, 56 => 0000000000000000 (00000000 00000000)
- sradi 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000)
- sradi ffffffffffffffff, 0 => ffffffffffffffff (00000000 00000000)
- sradi ffffffffffffffff, 7 => ffffffffffffffff (00000000 20000000)
- sradi ffffffffffffffff, 14 => ffffffffffffffff (00000000 20000000)
- sradi ffffffffffffffff, 21 => ffffffffffffffff (00000000 20000000)
- sradi ffffffffffffffff, 28 => ffffffffffffffff (00000000 20000000)
- sradi ffffffffffffffff, 35 => ffffffffffffffff (00000000 20000000)
- sradi ffffffffffffffff, 42 => ffffffffffffffff (00000000 20000000)
- sradi ffffffffffffffff, 49 => ffffffffffffffff (00000000 20000000)
- sradi ffffffffffffffff, 56 => ffffffffffffffff (00000000 20000000)
- sradi ffffffffffffffff, 63 => ffffffffffffffff (00000000 20000000)
-
-PPC logical insns with special forms with flags update:
- rlwimi. 0000000000000000, 0, 0, 0 => 0000000000000000 (20000000 00000000)
- rlwimi. 0000000000000000, 0, 0, 31 => 0000000000000000 (20000000 00000000)
- rlwimi. 0000000000000000, 0, 31, 0 => 0000000000000000 (20000000 00000000)
- rlwimi. 0000000000000000, 0, 31, 31 => 0000000000000000 (20000000 00000000)
- rlwimi. 0000000000000000, 31, 0, 0 => 0000000000000000 (20000000 00000000)
- rlwimi. 0000000000000000, 31, 0, 31 => 0000000000000000 (20000000 00000000)
- rlwimi. 0000000000000000, 31, 31, 0 => 0000000000000000 (20000000 00000000)
- rlwimi. 0000000000000000, 31, 31, 31 => 0000000000000000 (20000000 00000000)
- rlwimi. 0000001cbe991def, 0, 0, 0 => 0000000080000000 (40000000 00000000)
- rlwimi. 0000001cbe991def, 0, 0, 31 => 00000000be991def (40000000 00000000)
- rlwimi. 0000001cbe991def, 0, 31, 0 => be991defbe991def (80000000 00000000)
- rlwimi. 0000001cbe991def, 0, 31, 31 => be991defbe991def (80000000 00000000)
- rlwimi. 0000001cbe991def, 31, 0, 0 => be991defbe991def (80000000 00000000)
- rlwimi. 0000001cbe991def, 31, 0, 31 => be991defdf4c8ef7 (80000000 00000000)
- rlwimi. 0000001cbe991def, 31, 31, 0 => df4c8ef7df4c8ef7 (80000000 00000000)
- rlwimi. 0000001cbe991def, 31, 31, 31 => df4c8ef7df4c8ef7 (80000000 00000000)
- rlwimi. ffffffffffffffff, 0, 0, 0 => df4c8ef7df4c8ef7 (80000000 00000000)
- rlwimi. ffffffffffffffff, 0, 0, 31 => df4c8ef7ffffffff (80000000 00000000)
- rlwimi. ffffffffffffffff, 0, 31, 0 => ffffffffffffffff (80000000 00000000)
- rlwimi. ffffffffffffffff, 0, 31, 31 => ffffffffffffffff (80000000 00000000)
- rlwimi. ffffffffffffffff, 31, 0, 0 => ffffffffffffffff (80000000 00000000)
- rlwimi. ffffffffffffffff, 31, 0, 31 => ffffffffffffffff (80000000 00000000)
- rlwimi. ffffffffffffffff, 31, 31, 0 => ffffffffffffffff (80000000 00000000)
- rlwimi. ffffffffffffffff, 31, 31, 31 => ffffffffffffffff (80000000 00000000)
-
- rlwinm. 0000000000000000, 0, 0, 0 => 0000000000000000 (20000000 00000000)
- rlwinm. 0000000000000000, 0, 0, 31 => 0000000000000000 (20000000 00000000)
- rlwinm. 0000000000000000, 0, 31, 0 => 0000000000000000 (20000000 00000000)
- rlwinm. 0000000000000000, 0, 31, 31 => 0000000000000000 (20000000 00000000)
- rlwinm. 0000000000000000, 31, 0, 0 => 0000000000000000 (20000000 00000000)
- rlwinm. 0000000000000000, 31, 0, 31 => 0000000000000000 (20000000 00000000)
- rlwinm. 0000000000000000, 31, 31, 0 => 0000000000000000 (20000000 00000000)
- rlwinm. 0000000000000000, 31, 31, 31 => 0000000000000000 (20000000 00000000)
- rlwinm. 0000001cbe991def, 0, 0, 0 => 0000000080000000 (40000000 00000000)
- rlwinm. 0000001cbe991def, 0, 0, 31 => 00000000be991def (40000000 00000000)
- rlwinm. 0000001cbe991def, 0, 31, 0 => be991def80000001 (80000000 00000000)
- rlwinm. 0000001cbe991def, 0, 31, 31 => 0000000000000001 (40000000 00000000)
- rlwinm. 0000001cbe991def, 31, 0, 0 => 0000000080000000 (40000000 00000000)
- rlwinm. 0000001cbe991def, 31, 0, 31 => 00000000df4c8ef7 (40000000 00000000)
- rlwinm. 0000001cbe991def, 31, 31, 0 => df4c8ef780000001 (80000000 00000000)
- rlwinm. 0000001cbe991def, 31, 31, 31 => 0000000000000001 (40000000 00000000)
- rlwinm. ffffffffffffffff, 0, 0, 0 => 0000000080000000 (40000000 00000000)
- rlwinm. ffffffffffffffff, 0, 0, 31 => 00000000ffffffff (40000000 00000000)
- rlwinm. ffffffffffffffff, 0, 31, 0 => ffffffff80000001 (80000000 00000000)
- rlwinm. ffffffffffffffff, 0, 31, 31 => 0000000000000001 (40000000 00000000)
- rlwinm. ffffffffffffffff, 31, 0, 0 => 0000000080000000 (40000000 00000000)
- rlwinm. ffffffffffffffff, 31, 0, 31 => 00000000ffffffff (40000000 00000000)
- rlwinm. ffffffffffffffff, 31, 31, 0 => ffffffff80000001 (80000000 00000000)
- rlwinm. ffffffffffffffff, 31, 31, 31 => 0000000000000001 (40000000 00000000)
-
- rlwnm. 0000000000000000, 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
- rlwnm. 0000000000000000, 0000000000000000, 0, 31 => 0000000000000000 (20000000 00000000)
- rlwnm. 0000000000000000, 0000000000000000, 31, 0 => 0000000000000000 (20000000 00000000)
- rlwnm. 0000000000000000, 0000000000000000, 31, 31 => 0000000000000000 (20000000 00000000)
- rlwnm. 0000000000000000, 0000001cbe991def, 0, 0 => 0000000000000000 (20000000 00000000)
- rlwnm. 0000000000000000, 0000001cbe991def, 0, 31 => 0000000000000000 (20000000 00000000)
- rlwnm. 0000000000000000, 0000001cbe991def, 31, 0 => 0000000000000000 (20000000 00000000)
- rlwnm. 0000000000000000, 0000001cbe991def, 31, 31 => 0000000000000000 (20000000 00000000)
- rlwnm. 0000000000000000, ffffffffffffffff, 0, 0 => 0000000000000000 (20000000 00000000)
- rlwnm. 0000000000000000, ffffffffffffffff, 0, 31 => 0000000000000000 (20000000 00000000)
- rlwnm. 0000000000000000, ffffffffffffffff, 31, 0 => 0000000000000000 (20000000 00000000)
- rlwnm. 0000000000000000, ffffffffffffffff, 31, 31 => 0000000000000000 (20000000 00000000)
- rlwnm. 0000001cbe991def, 0000000000000000, 0, 0 => 0000000080000000 (40000000 00000000)
- rlwnm. 0000001cbe991def, 0000000000000000, 0, 31 => 00000000be991def (40000000 00000000)
- rlwnm. 0000001cbe991def, 0000000000000000, 31, 0 => be991def80000001 (80000000 00000000)
- rlwnm. 0000001cbe991def, 0000000000000000, 31, 31 => 0000000000000001 (40000000 00000000)
- rlwnm. 0000001cbe991def, 0000001cbe991def, 0, 0 => 0000000080000000 (40000000 00000000)
- rlwnm. 0000001cbe991def, 0000001cbe991def, 0, 31 => 000000008ef7df4c (40000000 00000000)
- rlwnm. 0000001cbe991def, 0000001cbe991def, 31, 0 => 8ef7df4c80000000 (80000000 00000000)
- rlwnm. 0000001cbe991def, 0000001cbe991def, 31, 31 => 0000000000000000 (20000000 00000000)
- rlwnm. 0000001cbe991def, ffffffffffffffff, 0, 0 => 0000000080000000 (40000000 00000000)
- rlwnm. 0000001cbe991def, ffffffffffffffff, 0, 31 => 00000000df4c8ef7 (40000000 00000000)
- rlwnm. 0000001cbe991def, ffffffffffffffff, 31, 0 => df4c8ef780000001 (80000000 00000000)
- rlwnm. 0000001cbe991def, ffffffffffffffff, 31, 31 => 0000000000000001 (40000000 00000000)
- rlwnm. ffffffffffffffff, 0000000000000000, 0, 0 => 0000000080000000 (40000000 00000000)
- rlwnm. ffffffffffffffff, 0000000000000000, 0, 31 => 00000000ffffffff (40000000 00000000)
- rlwnm. ffffffffffffffff, 0000000000000000, 31, 0 => ffffffff80000001 (80000000 00000000)
- rlwnm. ffffffffffffffff, 0000000000000000, 31, 31 => 0000000000000001 (40000000 00000000)
- rlwnm. ffffffffffffffff, 0000001cbe991def, 0, 0 => 0000000080000000 (40000000 00000000)
- rlwnm. ffffffffffffffff, 0000001cbe991def, 0, 31 => 00000000ffffffff (40000000 00000000)
- rlwnm. ffffffffffffffff, 0000001cbe991def, 31, 0 => ffffffff80000001 (80000000 00000000)
- rlwnm. ffffffffffffffff, 0000001cbe991def, 31, 31 => 0000000000000001 (40000000 00000000)
- rlwnm. ffffffffffffffff, ffffffffffffffff, 0, 0 => 0000000080000000 (40000000 00000000)
- rlwnm. ffffffffffffffff, ffffffffffffffff, 0, 31 => 00000000ffffffff (40000000 00000000)
- rlwnm. ffffffffffffffff, ffffffffffffffff, 31, 0 => ffffffff80000001 (80000000 00000000)
- rlwnm. ffffffffffffffff, ffffffffffffffff, 31, 31 => 0000000000000001 (40000000 00000000)
-
- srawi. 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
- srawi. 0000000000000000, 31 => 0000000000000000 (20000000 00000000)
- srawi. 0000001cbe991def, 0 => ffffffffbe991def (80000000 00000000)
- srawi. 0000001cbe991def, 31 => ffffffffffffffff (80000000 20000000)
- srawi. ffffffffffffffff, 0 => ffffffffffffffff (80000000 00000000)
- srawi. ffffffffffffffff, 31 => ffffffffffffffff (80000000 20000000)
-
- mcrf 0, 0 (0000000000000000) => (00000000 00000000)
- mcrf 0, 7 (0000000000000000) => (00000000 00000000)
- mcrf 7, 0 (0000000000000000) => (00000000 00000000)
- mcrf 7, 7 (0000000000000000) => (00000000 00000000)
- mcrf 0, 0 (0000001cbe991def) => (be991def 00000000)
- mcrf 0, 7 (0000001cbe991def) => (fe991def 00000000)
- mcrf 7, 0 (0000001cbe991def) => (be991deb 00000000)
- mcrf 7, 7 (0000001cbe991def) => (be991def 00000000)
- mcrf 0, 0 (ffffffffffffffff) => (ffffffff 00000000)
- mcrf 0, 7 (ffffffffffffffff) => (ffffffff 00000000)
- mcrf 7, 0 (ffffffffffffffff) => (ffffffff 00000000)
- mcrf 7, 7 (ffffffffffffffff) => (ffffffff 00000000)
-
- mcrxr 0 (00000000) => (00000000 00000000)
- mcrxr 1 (00000000) => (00000000 00000000)
- mcrxr 2 (00000000) => (00000000 00000000)
- mcrxr 3 (00000000) => (00000000 00000000)
- mcrxr 4 (00000000) => (00000000 00000000)
- mcrxr 5 (00000000) => (00000000 00000000)
- mcrxr 6 (00000000) => (00000000 00000000)
- mcrxr 7 (00000000) => (00000000 00000000)
- mcrxr 0 (10000000) => (00000000 00000000)
- mcrxr 1 (10000000) => (00000000 00000000)
- mcrxr 2 (10000000) => (00000000 00000000)
- mcrxr 3 (10000000) => (00000000 00000000)
- mcrxr 4 (10000000) => (00000000 00000000)
- mcrxr 5 (10000000) => (00000000 00000000)
- mcrxr 6 (10000000) => (00000000 00000000)
- mcrxr 7 (10000000) => (00000000 00000000)
- mcrxr 0 (20000000) => (20000000 00000000)
- mcrxr 1 (20000000) => (02000000 00000000)
- mcrxr 2 (20000000) => (00200000 00000000)
- mcrxr 3 (20000000) => (00020000 00000000)
- mcrxr 4 (20000000) => (00002000 00000000)
- mcrxr 5 (20000000) => (00000200 00000000)
- mcrxr 6 (20000000) => (00000020 00000000)
- mcrxr 7 (20000000) => (00000002 00000000)
- mcrxr 0 (30000000) => (20000000 00000000)
- mcrxr 1 (30000000) => (02000000 00000000)
- mcrxr 2 (30000000) => (00200000 00000000)
- mcrxr 3 (30000000) => (00020000 00000000)
- mcrxr 4 (30000000) => (00002000 00000000)
- mcrxr 5 (30000000) => (00000200 00000000)
- mcrxr 6 (30000000) => (00000020 00000000)
- mcrxr 7 (30000000) => (00000002 00000000)
- mcrxr 0 (40000000) => (40000000 00000000)
- mcrxr 1 (40000000) => (04000000 00000000)
- mcrxr 2 (40000000) => (00400000 00000000)
- mcrxr 3 (40000000) => (00040000 00000000)
- mcrxr 4 (40000000) => (00004000 00000000)
- mcrxr 5 (40000000) => (00000400 00000000)
- mcrxr 6 (40000000) => (00000040 00000000)
- mcrxr 7 (40000000) => (00000004 00000000)
- mcrxr 0 (50000000) => (40000000 00000000)
- mcrxr 1 (50000000) => (04000000 00000000)
- mcrxr 2 (50000000) => (00400000 00000000)
- mcrxr 3 (50000000) => (00040000 00000000)
- mcrxr 4 (50000000) => (00004000 00000000)
- mcrxr 5 (50000000) => (00000400 00000000)
- mcrxr 6 (50000000) => (00000040 00000000)
- mcrxr 7 (50000000) => (00000004 00000000)
- mcrxr 0 (60000000) => (60000000 00000000)
- mcrxr 1 (60000000) => (06000000 00000000)
- mcrxr 2 (60000000) => (00600000 00000000)
- mcrxr 3 (60000000) => (00060000 00000000)
- mcrxr 4 (60000000) => (00006000 00000000)
- mcrxr 5 (60000000) => (00000600 00000000)
- mcrxr 6 (60000000) => (00000060 00000000)
- mcrxr 7 (60000000) => (00000006 00000000)
- mcrxr 0 (70000000) => (60000000 00000000)
- mcrxr 1 (70000000) => (06000000 00000000)
- mcrxr 2 (70000000) => (00600000 00000000)
- mcrxr 3 (70000000) => (00060000 00000000)
- mcrxr 4 (70000000) => (00006000 00000000)
- mcrxr 5 (70000000) => (00000600 00000000)
- mcrxr 6 (70000000) => (00000060 00000000)
- mcrxr 7 (70000000) => (00000006 00000000)
- mcrxr 0 (80000000) => (80000000 00000000)
- mcrxr 1 (80000000) => (08000000 00000000)
- mcrxr 2 (80000000) => (00800000 00000000)
- mcrxr 3 (80000000) => (00080000 00000000)
- mcrxr 4 (80000000) => (00008000 00000000)
- mcrxr 5 (80000000) => (00000800 00000000)
- mcrxr 6 (80000000) => (00000080 00000000)
- mcrxr 7 (80000000) => (00000008 00000000)
- mcrxr 0 (90000000) => (80000000 00000000)
- mcrxr 1 (90000000) => (08000000 00000000)
- mcrxr 2 (90000000) => (00800000 00000000)
- mcrxr 3 (90000000) => (00080000 00000000)
- mcrxr 4 (90000000) => (00008000 00000000)
- mcrxr 5 (90000000) => (00000800 00000000)
- mcrxr 6 (90000000) => (00000080 00000000)
- mcrxr 7 (90000000) => (00000008 00000000)
- mcrxr 0 (a0000000) => (a0000000 00000000)
- mcrxr 1 (a0000000) => (0a000000 00000000)
- mcrxr 2 (a0000000) => (00a00000 00000000)
- mcrxr 3 (a0000000) => (000a0000 00000000)
- mcrxr 4 (a0000000) => (0000a000 00000000)
- mcrxr 5 (a0000000) => (00000a00 00000000)
- mcrxr 6 (a0000000) => (000000a0 00000000)
- mcrxr 7 (a0000000) => (0000000a 00000000)
- mcrxr 0 (b0000000) => (a0000000 00000000)
- mcrxr 1 (b0000000) => (0a000000 00000000)
- mcrxr 2 (b0000000) => (00a00000 00000000)
- mcrxr 3 (b0000000) => (000a0000 00000000)
- mcrxr 4 (b0000000) => (0000a000 00000000)
- mcrxr 5 (b0000000) => (00000a00 00000000)
- mcrxr 6 (b0000000) => (000000a0 00000000)
- mcrxr 7 (b0000000) => (0000000a 00000000)
- mcrxr 0 (c0000000) => (c0000000 00000000)
- mcrxr 1 (c0000000) => (0c000000 00000000)
- mcrxr 2 (c0000000) => (00c00000 00000000)
- mcrxr 3 (c0000000) => (000c0000 00000000)
- mcrxr 4 (c0000000) => (0000c000 00000000)
- mcrxr 5 (c0000000) => (00000c00 00000000)
- mcrxr 6 (c0000000) => (000000c0 00000000)
- mcrxr 7 (c0000000) => (0000000c 00000000)
- mcrxr 0 (d0000000) => (c0000000 00000000)
- mcrxr 1 (d0000000) => (0c000000 00000000)
- mcrxr 2 (d0000000) => (00c00000 00000000)
- mcrxr 3 (d0000000) => (000c0000 00000000)
- mcrxr 4 (d0000000) => (0000c000 00000000)
- mcrxr 5 (d0000000) => (00000c00 00000000)
- mcrxr 6 (d0000000) => (000000c0 00000000)
- mcrxr 7 (d0000000) => (0000000c 00000000)
- mcrxr 0 (e0000000) => (e0000000 00000000)
- mcrxr 1 (e0000000) => (0e000000 00000000)
- mcrxr 2 (e0000000) => (00e00000 00000000)
- mcrxr 3 (e0000000) => (000e0000 00000000)
- mcrxr 4 (e0000000) => (0000e000 00000000)
- mcrxr 5 (e0000000) => (00000e00 00000000)
- mcrxr 6 (e0000000) => (000000e0 00000000)
- mcrxr 7 (e0000000) => (0000000e 00000000)
- mcrxr 0 (f0000000) => (e0000000 00000000)
- mcrxr 1 (f0000000) => (0e000000 00000000)
- mcrxr 2 (f0000000) => (00e00000 00000000)
- mcrxr 3 (f0000000) => (000e0000 00000000)
- mcrxr 4 (f0000000) => (0000e000 00000000)
- mcrxr 5 (f0000000) => (00000e00 00000000)
- mcrxr 6 (f0000000) => (000000e0 00000000)
- mcrxr 7 (f0000000) => (0000000e 00000000)
-
- mtcrf 0, 0000000000000000 => (00000000 00000000)
- mtcrf 99, 0000000000000000 => (00000000 00000000)
- mtcrf 198, 0000000000000000 => (00000000 00000000)
- mtcrf 0, 0000001cbe991def => (00000000 00000000)
- mtcrf 99, 0000001cbe991def => (0e9000ef 00000000)
- mtcrf 198, 0000001cbe991def => (be000de0 00000000)
- mtcrf 0, ffffffffffffffff => (00000000 00000000)
- mtcrf 99, ffffffffffffffff => (0ff000ff 00000000)
- mtcrf 198, ffffffffffffffff => (ff000ff0 00000000)
-
- rldcl. 0000000000000000, 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, 0000000000000000, 7 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, 0000000000000000, 14 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, 0000000000000000, 21 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, 0000000000000000, 28 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, 0000000000000000, 35 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, 0000000000000000, 42 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, 0000000000000000, 49 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, 0000000000000000, 56 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, 0000000000000000, 63 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, 0000001cbe991def, 0 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, 0000001cbe991def, 7 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, 0000001cbe991def, 14 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, 0000001cbe991def, 21 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, 0000001cbe991def, 28 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, 0000001cbe991def, 35 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, 0000001cbe991def, 42 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, 0000001cbe991def, 49 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, 0000001cbe991def, 56 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, ffffffffffffffff, 0 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, ffffffffffffffff, 7 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, ffffffffffffffff, 14 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, ffffffffffffffff, 21 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, ffffffffffffffff, 28 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, ffffffffffffffff, 35 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, ffffffffffffffff, 42 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, ffffffffffffffff, 49 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, ffffffffffffffff, 56 => 0000000000000000 (20000000 00000000)
- rldcl. 0000000000000000, ffffffffffffffff, 63 => 0000000000000000 (20000000 00000000)
- rldcl. 0000001cbe991def, 0000000000000000, 0 => 0000001cbe991def (40000000 00000000)
- rldcl. 0000001cbe991def, 0000000000000000, 7 => 0000001cbe991def (40000000 00000000)
- rldcl. 0000001cbe991def, 0000000000000000, 14 => 0000001cbe991def (40000000 00000000)
- rldcl. 0000001cbe991def, 0000000000000000, 21 => 0000001cbe991def (40000000 00000000)
- rldcl. 0000001cbe991def, 0000000000000000, 28 => 0000000cbe991def (40000000 00000000)
- rldcl. 0000001cbe991def, 0000000000000000, 35 => 000000001e991def (40000000 00000000)
- rldcl. 0000001cbe991def, 0000000000000000, 42 => 0000000000191def (40000000 00000000)
- rldcl. 0000001cbe991def, 0000000000000000, 49 => 0000000000001def (40000000 00000000)
- rldcl. 0000001cbe991def, 0000000000000000, 56 => 00000000000000ef (40000000 00000000)
- rldcl. 0000001cbe991def, 0000000000000000, 63 => 0000000000000001 (40000000 00000000)
- rldcl. 0000001cbe991def, 0000001cbe991def, 0 => 8ef78000000e5f4c (80000000 00000000)
- rldcl. 0000001cbe991def, 0000001cbe991def, 7 => 00f78000000e5f4c (40000000 00000000)
- rldcl. 0000001cbe991def, 0000001cbe991def, 14 => 00038000000e5f4c (40000000 00000000)
- rldcl. 0000001cbe991def, 0000001cbe991def, 21 => 00000000000e5f4c (40000000 00000000)
- rldcl. 0000001cbe991def, 0000001cbe991def, 28 => 00000000000e5f4c (40000000 00000000)
- rldcl. 0000001cbe991def, 0000001cbe991def, 35 => 00000000000e5f4c (40000000 00000000)
- rldcl. 0000001cbe991def, 0000001cbe991def, 42 => 00000000000e5f4c (40000000 00000000)
- rldcl. 0000001cbe991def, 0000001cbe991def, 49 => 0000000000005f4c (40000000 00000000)
- rldcl. 0000001cbe991def, 0000001cbe991def, 56 => 000000000000004c (40000000 00000000)
- rldcl. 0000001cbe991def, 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000)
- rldcl. 0000001cbe991def, ffffffffffffffff, 0 => 8000000e5f4c8ef7 (80000000 00000000)
- rldcl. 0000001cbe991def, ffffffffffffffff, 7 => 0000000e5f4c8ef7 (40000000 00000000)
- rldcl. 0000001cbe991def, ffffffffffffffff, 14 => 0000000e5f4c8ef7 (40000000 00000000)
- rldcl. 0000001cbe991def, ffffffffffffffff, 21 => 0000000e5f4c8ef7 (40000000 00000000)
- rldcl. 0000001cbe991def, ffffffffffffffff, 28 => 0000000e5f4c8ef7 (40000000 00000000)
- rldcl. 0000001cbe991def, ffffffffffffffff, 35 => 000000001f4c8ef7 (40000000 00000000)
- rldcl. 0000001cbe991def, ffffffffffffffff, 42 => 00000000000c8ef7 (40000000 00000000)
- rldcl. 0000001cbe991def, ffffffffffffffff, 49 => 0000000000000ef7 (40000000 00000000)
- rldcl. 0000001cbe991def, ffffffffffffffff, 56 => 00000000000000f7 (40000000 00000000)
- rldcl. 0000001cbe991def, ffffffffffffffff, 63 => 0000000000000001 (40000000 00000000)
- rldcl. ffffffffffffffff, 0000000000000000, 0 => ffffffffffffffff (80000000 00000000)
- rldcl. ffffffffffffffff, 0000000000000000, 7 => 01ffffffffffffff (40000000 00000000)
- rldcl. ffffffffffffffff, 0000000000000000, 14 => 0003ffffffffffff (40000000 00000000)
- rldcl. ffffffffffffffff, 0000000000000000, 21 => 000007ffffffffff (40000000 00000000)
- rldcl. ffffffffffffffff, 0000000000000000, 28 => 0000000fffffffff (40000000 00000000)
- rldcl. ffffffffffffffff, 0000000000000000, 35 => 000000001fffffff (40000000 00000000)
- rldcl. ffffffffffffffff, 0000000000000000, 42 => 00000000003fffff (40000000 00000000)
- rldcl. ffffffffffffffff, 0000000000000000, 49 => 0000000000007fff (40000000 00000000)
- rldcl. ffffffffffffffff, 0000000000000000, 56 => 00000000000000ff (40000000 00000000)
- rldcl. ffffffffffffffff, 0000000000000000, 63 => 0000000000000001 (40000000 00000000)
- rldcl. ffffffffffffffff, 0000001cbe991def, 0 => ffffffffffffffff (80000000 00000000)
- rldcl. ffffffffffffffff, 0000001cbe991def, 7 => 01ffffffffffffff (40000000 00000000)
- rldcl. ffffffffffffffff, 0000001cbe991def, 14 => 0003ffffffffffff (40000000 00000000)
- rldcl. ffffffffffffffff, 0000001cbe991def, 21 => 000007ffffffffff (40000000 00000000)
- rldcl. ffffffffffffffff, 0000001cbe991def, 28 => 0000000fffffffff (40000000 00000000)
- rldcl. ffffffffffffffff, 0000001cbe991def, 35 => 000000001fffffff (40000000 00000000)
- rldcl. ffffffffffffffff, 0000001cbe991def, 42 => 00000000003fffff (40000000 00000000)
- rldcl. ffffffffffffffff, 0000001cbe991def, 49 => 0000000000007fff (40000000 00000000)
- rldcl. ffffffffffffffff, 0000001cbe991def, 56 => 00000000000000ff (40000000 00000000)
- rldcl. ffffffffffffffff, 0000001cbe991def, 63 => 0000000000000001 (40000000 00000000)
- rldcl. ffffffffffffffff, ffffffffffffffff, 0 => ffffffffffffffff (80000000 00000000)
- rldcl. ffffffffffffffff, ffffffffffffffff, 7 => 01ffffffffffffff (40000000 00000000)
- rldcl. ffffffffffffffff, ffffffffffffffff, 14 => 0003ffffffffffff (40000000 00000000)
- rldcl. ffffffffffffffff, ffffffffffffffff, 21 => 000007ffffffffff (40000000 00000000)
- rldcl. ffffffffffffffff, ffffffffffffffff, 28 => 0000000fffffffff (40000000 00000000)
- rldcl. ffffffffffffffff, ffffffffffffffff, 35 => 000000001fffffff (40000000 00000000)
- rldcl. ffffffffffffffff, ffffffffffffffff, 42 => 00000000003fffff (40000000 00000000)
- rldcl. ffffffffffffffff, ffffffffffffffff, 49 => 0000000000007fff (40000000 00000000)
- rldcl. ffffffffffffffff, ffffffffffffffff, 56 => 00000000000000ff (40000000 00000000)
- rldcl. ffffffffffffffff, ffffffffffffffff, 63 => 0000000000000001 (40000000 00000000)
-
- rldcr. 0000000000000000, 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, 0000000000000000, 7 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, 0000000000000000, 14 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, 0000000000000000, 21 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, 0000000000000000, 28 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, 0000000000000000, 35 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, 0000000000000000, 42 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, 0000000000000000, 49 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, 0000000000000000, 56 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, 0000000000000000, 63 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, 0000001cbe991def, 0 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, 0000001cbe991def, 7 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, 0000001cbe991def, 14 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, 0000001cbe991def, 21 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, 0000001cbe991def, 28 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, 0000001cbe991def, 35 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, 0000001cbe991def, 42 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, 0000001cbe991def, 49 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, 0000001cbe991def, 56 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, ffffffffffffffff, 0 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, ffffffffffffffff, 7 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, ffffffffffffffff, 14 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, ffffffffffffffff, 21 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, ffffffffffffffff, 28 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, ffffffffffffffff, 35 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, ffffffffffffffff, 42 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, ffffffffffffffff, 49 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, ffffffffffffffff, 56 => 0000000000000000 (20000000 00000000)
- rldcr. 0000000000000000, ffffffffffffffff, 63 => 0000000000000000 (20000000 00000000)
- rldcr. 0000001cbe991def, 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
- rldcr. 0000001cbe991def, 0000000000000000, 7 => 0000000000000000 (20000000 00000000)
- rldcr. 0000001cbe991def, 0000000000000000, 14 => 0000000000000000 (20000000 00000000)
- rldcr. 0000001cbe991def, 0000000000000000, 21 => 0000000000000000 (20000000 00000000)
- rldcr. 0000001cbe991def, 0000000000000000, 28 => 0000001800000000 (40000000 00000000)
- rldcr. 0000001cbe991def, 0000000000000000, 35 => 0000001cb0000000 (40000000 00000000)
- rldcr. 0000001cbe991def, 0000000000000000, 42 => 0000001cbe800000 (40000000 00000000)
- rldcr. 0000001cbe991def, 0000000000000000, 49 => 0000001cbe990000 (40000000 00000000)
- rldcr. 0000001cbe991def, 0000000000000000, 56 => 0000001cbe991d80 (40000000 00000000)
- rldcr. 0000001cbe991def, 0000000000000000, 63 => 0000001cbe991def (40000000 00000000)
- rldcr. 0000001cbe991def, 0000001cbe991def, 0 => 8000000000000000 (80000000 00000000)
- rldcr. 0000001cbe991def, 0000001cbe991def, 7 => 8e00000000000000 (80000000 00000000)
- rldcr. 0000001cbe991def, 0000001cbe991def, 14 => 8ef6000000000000 (80000000 00000000)
- rldcr. 0000001cbe991def, 0000001cbe991def, 21 => 8ef7800000000000 (80000000 00000000)
- rldcr. 0000001cbe991def, 0000001cbe991def, 28 => 8ef7800000000000 (80000000 00000000)
- rldcr. 0000001cbe991def, 0000001cbe991def, 35 => 8ef7800000000000 (80000000 00000000)
- rldcr. 0000001cbe991def, 0000001cbe991def, 42 => 8ef7800000000000 (80000000 00000000)
- rldcr. 0000001cbe991def, 0000001cbe991def, 49 => 8ef78000000e4000 (80000000 00000000)
- rldcr. 0000001cbe991def, 0000001cbe991def, 56 => 8ef78000000e5f00 (80000000 00000000)
- rldcr. 0000001cbe991def, 0000001cbe991def, 63 => 8ef78000000e5f4c (80000000 00000000)
- rldcr. 0000001cbe991def, ffffffffffffffff, 0 => 8000000000000000 (80000000 00000000)
- rldcr. 0000001cbe991def, ffffffffffffffff, 7 => 8000000000000000 (80000000 00000000)
- rldcr. 0000001cbe991def, ffffffffffffffff, 14 => 8000000000000000 (80000000 00000000)
- rldcr. 0000001cbe991def, ffffffffffffffff, 21 => 8000000000000000 (80000000 00000000)
- rldcr. 0000001cbe991def, ffffffffffffffff, 28 => 8000000800000000 (80000000 00000000)
- rldcr. 0000001cbe991def, ffffffffffffffff, 35 => 8000000e50000000 (80000000 00000000)
- rldcr. 0000001cbe991def, ffffffffffffffff, 42 => 8000000e5f400000 (80000000 00000000)
- rldcr. 0000001cbe991def, ffffffffffffffff, 49 => 8000000e5f4c8000 (80000000 00000000)
- rldcr. 0000001cbe991def, ffffffffffffffff, 56 => 8000000e5f4c8e80 (80000000 00000000)
- rldcr. 0000001cbe991def, ffffffffffffffff, 63 => 8000000e5f4c8ef7 (80000000 00000000)
- rldcr. ffffffffffffffff, 0000000000000000, 0 => 8000000000000000 (80000000 00000000)
- rldcr. ffffffffffffffff, 0000000000000000, 7 => ff00000000000000 (80000000 00000000)
- rldcr. ffffffffffffffff, 0000000000000000, 14 => fffe000000000000 (80000000 00000000)
- rldcr. ffffffffffffffff, 0000000000000000, 21 => fffffc0000000000 (80000000 00000000)
- rldcr. ffffffffffffffff, 0000000000000000, 28 => fffffff800000000 (80000000 00000000)
- rldcr. ffffffffffffffff, 0000000000000000, 35 => fffffffff0000000 (80000000 00000000)
- rldcr. ffffffffffffffff, 0000000000000000, 42 => ffffffffffe00000 (80000000 00000000)
- rldcr. ffffffffffffffff, 0000000000000000, 49 => ffffffffffffc000 (80000000 00000000)
- rldcr. ffffffffffffffff, 0000000000000000, 56 => ffffffffffffff80 (80000000 00000000)
- rldcr. ffffffffffffffff, 0000000000000000, 63 => ffffffffffffffff (80000000 00000000)
- rldcr. ffffffffffffffff, 0000001cbe991def, 0 => 8000000000000000 (80000000 00000000)
- rldcr. ffffffffffffffff, 0000001cbe991def, 7 => ff00000000000000 (80000000 00000000)
- rldcr. ffffffffffffffff, 0000001cbe991def, 14 => fffe000000000000 (80000000 00000000)
- rldcr. ffffffffffffffff, 0000001cbe991def, 21 => fffffc0000000000 (80000000 00000000)
- rldcr. ffffffffffffffff, 0000001cbe991def, 28 => fffffff800000000 (80000000 00000000)
- rldcr. ffffffffffffffff, 0000001cbe991def, 35 => fffffffff0000000 (80000000 00000000)
- rldcr. ffffffffffffffff, 0000001cbe991def, 42 => ffffffffffe00000 (80000000 00000000)
- rldcr. ffffffffffffffff, 0000001cbe991def, 49 => ffffffffffffc000 (80000000 00000000)
- rldcr. ffffffffffffffff, 0000001cbe991def, 56 => ffffffffffffff80 (80000000 00000000)
- rldcr. ffffffffffffffff, 0000001cbe991def, 63 => ffffffffffffffff (80000000 00000000)
- rldcr. ffffffffffffffff, ffffffffffffffff, 0 => 8000000000000000 (80000000 00000000)
- rldcr. ffffffffffffffff, ffffffffffffffff, 7 => ff00000000000000 (80000000 00000000)
- rldcr. ffffffffffffffff, ffffffffffffffff, 14 => fffe000000000000 (80000000 00000000)
- rldcr. ffffffffffffffff, ffffffffffffffff, 21 => fffffc0000000000 (80000000 00000000)
- rldcr. ffffffffffffffff, ffffffffffffffff, 28 => fffffff800000000 (80000000 00000000)
- rldcr. ffffffffffffffff, ffffffffffffffff, 35 => fffffffff0000000 (80000000 00000000)
- rldcr. ffffffffffffffff, ffffffffffffffff, 42 => ffffffffffe00000 (80000000 00000000)
- rldcr. ffffffffffffffff, ffffffffffffffff, 49 => ffffffffffffc000 (80000000 00000000)
- rldcr. ffffffffffffffff, ffffffffffffffff, 56 => ffffffffffffff80 (80000000 00000000)
- rldcr. ffffffffffffffff, ffffffffffffffff, 63 => ffffffffffffffff (80000000 00000000)
-
- rldic. 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 0, 7 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 0, 14 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 0, 21 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 0, 28 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 0, 35 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 0, 42 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 0, 49 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 0, 56 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 0, 63 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 7, 0 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 7, 7 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 7, 14 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 7, 21 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 7, 28 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 7, 35 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 7, 42 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 7, 49 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 7, 56 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 7, 63 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 14, 0 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 14, 7 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 14, 14 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 14, 21 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 14, 28 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 14, 35 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 14, 42 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 14, 49 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 14, 56 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 14, 63 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 21, 0 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 21, 7 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 21, 14 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 21, 21 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 21, 28 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 21, 35 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 21, 42 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 21, 49 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 21, 56 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 21, 63 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 28, 0 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 28, 7 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 28, 14 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 28, 21 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 28, 28 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 28, 35 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 28, 42 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 28, 49 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 28, 56 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 28, 63 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 35, 0 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 35, 7 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 35, 14 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 35, 21 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 35, 28 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 35, 35 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 35, 42 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 35, 49 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 35, 56 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 35, 63 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 42, 0 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 42, 7 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 42, 14 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 42, 21 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 42, 28 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 42, 35 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 42, 42 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 42, 49 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 42, 56 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 42, 63 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 49, 0 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 49, 7 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 49, 14 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 49, 21 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 49, 28 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 49, 35 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 49, 42 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 49, 49 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 49, 56 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 49, 63 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 56, 0 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 56, 7 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 56, 14 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 56, 21 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 56, 28 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 56, 35 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 56, 42 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 56, 49 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 56, 56 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 56, 63 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 63, 0 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 63, 7 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 63, 14 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 63, 21 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 63, 28 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 63, 35 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 63, 42 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 63, 49 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 63, 56 => 0000000000000000 (20000000 00000000)
- rldic. 0000000000000000, 63, 63 => 0000000000000000 (20000000 00000000)
- rldic. 0000001cbe991def, 0, 0 => 0000001cbe991def (40000000 00000000)
- rldic. 0000001cbe991def, 0, 7 => 0000001cbe991def (40000000 00000000)
- rldic. 0000001cbe991def, 0, 14 => 0000001cbe991def (40000000 00000000)
- rldic. 0000001cbe991def, 0, 21 => 0000001cbe991def (40000000 00000000)
- rldic. 0000001cbe991def, 0, 28 => 0000000cbe991def (40000000 00000000)
- rldic. 0000001cbe991def, 0, 35 => 000000001e991def (40000000 00000000)
- rldic. 0000001cbe991def, 0, 42 => 0000000000191def (40000000 00000000)
- rldic. 0000001cbe991def, 0, 49 => 0000000000001def (40000000 00000000)
- rldic. 0000001cbe991def, 0, 56 => 00000000000000ef (40000000 00000000)
- rldic. 0000001cbe991def, 0, 63 => 0000000000000001 (40000000 00000000)
- rldic. 0000001cbe991def, 7, 0 => 00000e5f4c8ef780 (40000000 00000000)
- rldic. 0000001cbe991def, 7, 7 => 00000e5f4c8ef780 (40000000 00000000)
- rldic. 0000001cbe991def, 7, 14 => 00000e5f4c8ef780 (40000000 00000000)
- rldic. 0000001cbe991def, 7, 21 => 0000065f4c8ef780 (40000000 00000000)
- rldic. 0000001cbe991def, 7, 28 => 0000000f4c8ef780 (40000000 00000000)
- rldic. 0000001cbe991def, 7, 35 => 000000000c8ef780 (40000000 00000000)
- rldic. 0000001cbe991def, 7, 42 => 00000000000ef780 (40000000 00000000)
- rldic. 0000001cbe991def, 7, 49 => 0000000000007780 (40000000 00000000)
- rldic. 0000001cbe991def, 7, 56 => 0000000000000080 (40000000 00000000)
- rldic. 0000001cbe991def, 7, 63 => 00000e5f4c8ef780 (40000000 00000000)
- rldic. 0000001cbe991def, 14, 0 => 00072fa6477bc000 (40000000 00000000)
- rldic. 0000001cbe991def, 14, 7 => 00072fa6477bc000 (40000000 00000000)
- rldic. 0000001cbe991def, 14, 14 => 00032fa6477bc000 (40000000 00000000)
- rldic. 0000001cbe991def, 14, 21 => 000007a6477bc000 (40000000 00000000)
- rldic. 0000001cbe991def, 14, 28 => 00000006477bc000 (40000000 00000000)
- rldic. 0000001cbe991def, 14, 35 => 00000000077bc000 (40000000 00000000)
- rldic. 0000001cbe991def, 14, 42 => 00000000003bc000 (40000000 00000000)
- rldic. 0000001cbe991def, 14, 49 => 0000000000004000 (40000000 00000000)
- rldic. 0000001cbe991def, 14, 56 => 00072fa6477bc000 (40000000 00000000)
- rldic. 0000001cbe991def, 14, 63 => 00072fa6477bc000 (40000000 00000000)
- rldic. 0000001cbe991def, 21, 0 => 0397d323bde00000 (40000000 00000000)
- rldic. 0000001cbe991def, 21, 7 => 0197d323bde00000 (40000000 00000000)
- rldic. 0000001cbe991def, 21, 14 => 0003d323bde00000 (40000000 00000000)
- rldic. 0000001cbe991def, 21, 21 => 00000323bde00000 (40000000 00000000)
- rldic. 0000001cbe991def, 21, 28 => 00000003bde00000 (40000000 00000000)
- rldic. 0000001cbe991def, 21, 35 => 000000001de00000 (40000000 00000000)
- rldic. 0000001cbe991def, 21, 42 => 0000000000200000 (40000000 00000000)
- rldic. 0000001cbe991def, 21, 49 => 0397d323bde00000 (40000000 00000000)
- rldic. 0000001cbe991def, 21, 56 => 0397d323bde00000 (40000000 00000000)
- rldic. 0000001cbe991def, 21, 63 => 0397d323bde00000 (40000000 00000000)
- rldic. 0000001cbe991def, 28, 0 => cbe991def0000000 (80000000 00000000)
- rldic. 0000001cbe991def, 28, 7 => 01e991def0000000 (40000000 00000000)
- rldic. 0000001cbe991def, 28, 14 => 000191def0000000 (40000000 00000000)
- rldic. 0000001cbe991def, 28, 21 => 000001def0000000 (40000000 00000000)
- rldic. 0000001cbe991def, 28, 28 => 0000000ef0000000 (40000000 00000000)
- rldic. 0000001cbe991def, 28, 35 => 0000000010000000 (40000000 00000000)
- rldic. 0000001cbe991def, 28, 42 => cbe991def0000001 (80000000 00000000)
- rldic. 0000001cbe991def, 28, 49 => cbe991def0000001 (80000000 00000000)
- rldic. 0000001cbe991def, 28, 56 => cbe991def0000001 (80000000 00000000)
- rldic. 0000001cbe991def, 28, 63 => cbe991def0000001 (80000000 00000000)
- rldic. 0000001cbe991def, 35, 0 => f4c8ef7800000000 (80000000 00000000)
- rldic. 0000001cbe991def, 35, 7 => 00c8ef7800000000 (40000000 00000000)
- rldic. 0000001cbe991def, 35, 14 => 0000ef7800000000 (40000000 00000000)
- rldic. 0000001cbe991def, 35, 21 => 0000077800000000 (40000000 00000000)
- rldic. 0000001cbe991def, 35, 28 => 0000000800000000 (40000000 00000000)
- rldic. 0000001cbe991def, 35, 35 => f4c8ef78000000e5 (80000000 00000000)
- rldic. 0000001cbe991def, 35, 42 => f4c8ef78000000e5 (80000000 00000000)
- rldic. 0000001cbe991def, 35, 49 => f4c8ef78000000e5 (80000000 00000000)
- rldic. 0000001cbe991def, 35, 56 => f4c8ef78000000e5 (80000000 00000000)
- rldic. 0000001cbe991def, 35, 63 => f4c8ef7800000001 (80000000 00000000)
- rldic. 0000001cbe991def, 42, 0 => 6477bc0000000000 (40000000 00000000)
- rldic. 0000001cbe991def, 42, 7 => 0077bc0000000000 (40000000 00000000)
- rldic. 0000001cbe991def, 42, 14 => 0003bc0000000000 (40000000 00000000)
- rldic. 0000001cbe991def, 42, 21 => 0000040000000000 (40000000 00000000)
- rldic. 0000001cbe991def, 42, 28 => 6477bc00000072fa (40000000 00000000)
- rldic. 0000001cbe991def, 42, 35 => 6477bc00000072fa (40000000 00000000)
- rldic. 0000001cbe991def, 42, 42 => 6477bc00000072fa (40000000 00000000)
- rldic. 0000001cbe991def, 42, 49 => 6477bc00000072fa (40000000 00000000)
- rldic. 0000001cbe991def, 42, 56 => 6477bc00000000fa (40000000 00000000)
- rldic. 0000001cbe991def, 42, 63 => 6477bc0000000000 (40000000 00000000)
- rldic. 0000001cbe991def, 49, 0 => 3bde000000000000 (40000000 00000000)
- rldic. 0000001cbe991def, 49, 7 => 01de000000000000 (40000000 00000000)
- rldic. 0000001cbe991def, 49, 14 => 0002000000000000 (40000000 00000000)
- rldic. 0000001cbe991def, 49, 21 => 3bde000000397d32 (40000000 00000000)
- rldic. 0000001cbe991def, 49, 28 => 3bde000000397d32 (40000000 00000000)
- rldic. 0000001cbe991def, 49, 35 => 3bde000000397d32 (40000000 00000000)
- rldic. 0000001cbe991def, 49, 42 => 3bde000000397d32 (40000000 00000000)
- rldic. 0000001cbe991def, 49, 49 => 3bde000000007d32 (40000000 00000000)
- rldic. 0000001cbe991def, 49, 56 => 3bde000000000032 (40000000 00000000)
- rldic. 0000001cbe991def, 49, 63 => 3bde000000000000 (40000000 00000000)
- rldic. 0000001cbe991def, 56, 0 => ef00000000000000 (80000000 00000000)
- rldic. 0000001cbe991def, 56, 7 => 0100000000000000 (40000000 00000000)
- rldic. 0000001cbe991def, 56, 14 => ef0000001cbe991d (80000000 00000000)
- rldic. 0000001cbe991def, 56, 21 => ef0000001cbe991d (80000000 00000000)
- rldic. 0000001cbe991def, 56, 28 => ef0000001cbe991d (80000000 00000000)
- rldic. 0000001cbe991def, 56, 35 => ef0000001cbe991d (80000000 00000000)
- rldic. 0000001cbe991def, 56, 42 => ef000000003e991d (80000000 00000000)
- rldic. 0000001cbe991def, 56, 49 => ef0000000000191d (80000000 00000000)
- rldic. 0000001cbe991def, 56, 56 => ef0000000000001d (80000000 00000000)
- rldic. 0000001cbe991def, 56, 63 => ef00000000000001 (80000000 00000000)
- rldic. 0000001cbe991def, 63, 0 => 8000000000000000 (80000000 00000000)
- rldic. 0000001cbe991def, 63, 7 => 8000000e5f4c8ef7 (80000000 00000000)
- rldic. 0000001cbe991def, 63, 14 => 8000000e5f4c8ef7 (80000000 00000000)
- rldic. 0000001cbe991def, 63, 21 => 8000000e5f4c8ef7 (80000000 00000000)
- rldic. 0000001cbe991def, 63, 28 => 8000000e5f4c8ef7 (80000000 00000000)
- rldic. 0000001cbe991def, 63, 35 => 800000001f4c8ef7 (80000000 00000000)
- rldic. 0000001cbe991def, 63, 42 => 80000000000c8ef7 (80000000 00000000)
- rldic. 0000001cbe991def, 63, 49 => 8000000000000ef7 (80000000 00000000)
- rldic. 0000001cbe991def, 63, 56 => 80000000000000f7 (80000000 00000000)
- rldic. 0000001cbe991def, 63, 63 => 8000000000000001 (80000000 00000000)
- rldic. ffffffffffffffff, 0, 0 => ffffffffffffffff (80000000 00000000)
- rldic. ffffffffffffffff, 0, 7 => 01ffffffffffffff (40000000 00000000)
- rldic. ffffffffffffffff, 0, 14 => 0003ffffffffffff (40000000 00000000)
- rldic. ffffffffffffffff, 0, 21 => 000007ffffffffff (40000000 00000000)
- rldic. ffffffffffffffff, 0, 28 => 0000000fffffffff (40000000 00000000)
- rldic. ffffffffffffffff, 0, 35 => 000000001fffffff (40000000 00000000)
- rldic. ffffffffffffffff, 0, 42 => 00000000003fffff (40000000 00000000)
- rldic. ffffffffffffffff, 0, 49 => 0000000000007fff (40000000 00000000)
- rldic. ffffffffffffffff, 0, 56 => 00000000000000ff (40000000 00000000)
- rldic. ffffffffffffffff, 0, 63 => 0000000000000001 (40000000 00000000)
- rldic. ffffffffffffffff, 7, 0 => ffffffffffffff80 (80000000 00000000)
- rldic. ffffffffffffffff, 7, 7 => 01ffffffffffff80 (40000000 00000000)
- rldic. ffffffffffffffff, 7, 14 => 0003ffffffffff80 (40000000 00000000)
- rldic. ffffffffffffffff, 7, 21 => 000007ffffffff80 (40000000 00000000)
- rldic. ffffffffffffffff, 7, 28 => 0000000fffffff80 (40000000 00000000)
- rldic. ffffffffffffffff, 7, 35 => 000000001fffff80 (40000000 00000000)
- rldic. ffffffffffffffff, 7, 42 => 00000000003fff80 (40000000 00000000)
- rldic. ffffffffffffffff, 7, 49 => 0000000000007f80 (40000000 00000000)
- rldic. ffffffffffffffff, 7, 56 => 0000000000000080 (40000000 00000000)
- rldic. ffffffffffffffff, 7, 63 => ffffffffffffff81 (80000000 00000000)
- rldic. ffffffffffffffff, 14, 0 => ffffffffffffc000 (80000000 00000000)
- rldic. ffffffffffffffff, 14, 7 => 01ffffffffffc000 (40000000 00000000)
- rldic. ffffffffffffffff, 14, 14 => 0003ffffffffc000 (40000000 00000000)
- rldic. ffffffffffffffff, 14, 21 => 000007ffffffc000 (40000000 00000000)
- rldic. ffffffffffffffff, 14, 28 => 0000000fffffc000 (40000000 00000000)
- rldic. ffffffffffffffff, 14, 35 => 000000001fffc000 (40000000 00000000)
- rldic. ffffffffffffffff, 14, 42 => 00000000003fc000 (40000000 00000000)
- rldic. ffffffffffffffff, 14, 49 => 0000000000004000 (40000000 00000000)
- rldic. ffffffffffffffff, 14, 56 => ffffffffffffc0ff (80000000 00000000)
- rldic. ffffffffffffffff, 14, 63 => ffffffffffffc001 (80000000 00000000)
- rldic. ffffffffffffffff, 21, 0 => ffffffffffe00000 (80000000 00000000)
- rldic. ffffffffffffffff, 21, 7 => 01ffffffffe00000 (40000000 00000000)
- rldic. ffffffffffffffff, 21, 14 => 0003ffffffe00000 (40000000 00000000)
- rldic. ffffffffffffffff, 21, 21 => 000007ffffe00000 (40000000 00000000)
- rldic. ffffffffffffffff, 21, 28 => 0000000fffe00000 (40000000 00000000)
- rldic. ffffffffffffffff, 21, 35 => 000000001fe00000 (40000000 00000000)
- rldic. ffffffffffffffff, 21, 42 => 0000000000200000 (40000000 00000000)
- rldic. ffffffffffffffff, 21, 49 => ffffffffffe07fff (80000000 00000000)
- rldic. ffffffffffffffff, 21, 56 => ffffffffffe000ff (80000000 00000000)
- rldic. ffffffffffffffff, 21, 63 => ffffffffffe00001 (80000000 00000000)
- rldic. ffffffffffffffff, 28, 0 => fffffffff0000000 (80000000 00000000)
- rldic. ffffffffffffffff, 28, 7 => 01fffffff0000000 (40000000 00000000)
- rldic. ffffffffffffffff, 28, 14 => 0003fffff0000000 (40000000 00000000)
- rldic. ffffffffffffffff, 28, 21 => 000007fff0000000 (40000000 00000000)
- rldic. ffffffffffffffff, 28, 28 => 0000000ff0000000 (40000000 00000000)
- rldic. ffffffffffffffff, 28, 35 => 0000000010000000 (40000000 00000000)
- rldic. ffffffffffffffff, 28, 42 => fffffffff03fffff (80000000 00000000)
- rldic. ffffffffffffffff, 28, 49 => fffffffff0007fff (80000000 00000000)
- rldic. ffffffffffffffff, 28, 56 => fffffffff00000ff (80000000 00000000)
- rldic. ffffffffffffffff, 28, 63 => fffffffff0000001 (80000000 00000000)
- rldic. ffffffffffffffff, 35, 0 => fffffff800000000 (80000000 00000000)
- rldic. ffffffffffffffff, 35, 7 => 01fffff800000000 (40000000 00000000)
- rldic. ffffffffffffffff, 35, 14 => 0003fff800000000 (40000000 00000000)
- rldic. ffffffffffffffff, 35, 21 => 000007f800000000 (40000000 00000000)
- rldic. ffffffffffffffff, 35, 28 => 0000000800000000 (40000000 00000000)
- rldic. ffffffffffffffff, 35, 35 => fffffff81fffffff (80000000 00000000)
- rldic. ffffffffffffffff, 35, 42 => fffffff8003fffff (80000000 00000000)
- rldic. ffffffffffffffff, 35, 49 => fffffff800007fff (80000000 00000000)
- rldic. ffffffffffffffff, 35, 56 => fffffff8000000ff (80000000 00000000)
- rldic. ffffffffffffffff, 35, 63 => fffffff800000001 (80000000 00000000)
- rldic. ffffffffffffffff, 42, 0 => fffffc0000000000 (80000000 00000000)
- rldic. ffffffffffffffff, 42, 7 => 01fffc0000000000 (40000000 00000000)
- rldic. ffffffffffffffff, 42, 14 => 0003fc0000000000 (40000000 00000000)
- rldic. ffffffffffffffff, 42, 21 => 0000040000000000 (40000000 00000000)
- rldic. ffffffffffffffff, 42, 28 => fffffc0fffffffff (80000000 00000000)
- rldic. ffffffffffffffff, 42, 35 => fffffc001fffffff (80000000 00000000)
- rldic. ffffffffffffffff, 42, 42 => fffffc00003fffff (80000000 00000000)
- rldic. ffffffffffffffff, 42, 49 => fffffc0000007fff (80000000 00000000)
- rldic. ffffffffffffffff, 42, 56 => fffffc00000000ff (80000000 00000000)
- rldic. ffffffffffffffff, 42, 63 => fffffc0000000001 (80000000 00000000)
- rldic. ffffffffffffffff, 49, 0 => fffe000000000000 (80000000 00000000)
- rldic. ffffffffffffffff, 49, 7 => 01fe000000000000 (40000000 00000000)
- rldic. ffffffffffffffff, 49, 14 => 0002000000000000 (40000000 00000000)
- rldic. ffffffffffffffff, 49, 21 => fffe07ffffffffff (80000000 00000000)
- rldic. ffffffffffffffff, 49, 28 => fffe000fffffffff (80000000 00000000)
- rldic. ffffffffffffffff, 49, 35 => fffe00001fffffff (80000000 00000000)
- rldic. ffffffffffffffff, 49, 42 => fffe0000003fffff (80000000 00000000)
- rldic. ffffffffffffffff, 49, 49 => fffe000000007fff (80000000 00000000)
- rldic. ffffffffffffffff, 49, 56 => fffe0000000000ff (80000000 00000000)
- rldic. ffffffffffffffff, 49, 63 => fffe000000000001 (80000000 00000000)
- rldic. ffffffffffffffff, 56, 0 => ff00000000000000 (80000000 00000000)
- rldic. ffffffffffffffff, 56, 7 => 0100000000000000 (40000000 00000000)
- rldic. ffffffffffffffff, 56, 14 => ff03ffffffffffff (80000000 00000000)
- rldic. ffffffffffffffff, 56, 21 => ff0007ffffffffff (80000000 00000000)
- rldic. ffffffffffffffff, 56, 28 => ff00000fffffffff (80000000 00000000)
- rldic. ffffffffffffffff, 56, 35 => ff0000001fffffff (80000000 00000000)
- rldic. ffffffffffffffff, 56, 42 => ff000000003fffff (80000000 00000000)
- rldic. ffffffffffffffff, 56, 49 => ff00000000007fff (80000000 00000000)
- rldic. ffffffffffffffff, 56, 56 => ff000000000000ff (80000000 00000000)
- rldic. ffffffffffffffff, 56, 63 => ff00000000000001 (80000000 00000000)
- rldic. ffffffffffffffff, 63, 0 => 8000000000000000 (80000000 00000000)
- rldic. ffffffffffffffff, 63, 7 => 81ffffffffffffff (80000000 00000000)
- rldic. ffffffffffffffff, 63, 14 => 8003ffffffffffff (80000000 00000000)
- rldic. ffffffffffffffff, 63, 21 => 800007ffffffffff (80000000 00000000)
- rldic. ffffffffffffffff, 63, 28 => 8000000fffffffff (80000000 00000000)
- rldic. ffffffffffffffff, 63, 35 => 800000001fffffff (80000000 00000000)
- rldic. ffffffffffffffff, 63, 42 => 80000000003fffff (80000000 00000000)
- rldic. ffffffffffffffff, 63, 49 => 8000000000007fff (80000000 00000000)
- rldic. ffffffffffffffff, 63, 56 => 80000000000000ff (80000000 00000000)
- rldic. ffffffffffffffff, 63, 63 => 8000000000000001 (80000000 00000000)
-
- rldicl. 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 0, 7 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 0, 14 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 0, 21 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 0, 28 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 0, 35 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 0, 42 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 0, 49 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 0, 56 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 0, 63 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 7, 0 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 7, 7 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 7, 14 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 7, 21 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 7, 28 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 7, 35 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 7, 42 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 7, 49 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 7, 56 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 7, 63 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 14, 0 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 14, 7 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 14, 14 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 14, 21 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 14, 28 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 14, 35 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 14, 42 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 14, 49 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 14, 56 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 14, 63 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 21, 0 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 21, 7 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 21, 14 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 21, 21 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 21, 28 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 21, 35 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 21, 42 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 21, 49 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 21, 56 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 21, 63 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 28, 0 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 28, 7 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 28, 14 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 28, 21 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 28, 28 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 28, 35 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 28, 42 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 28, 49 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 28, 56 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 28, 63 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 35, 0 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 35, 7 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 35, 14 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 35, 21 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 35, 28 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 35, 35 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 35, 42 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 35, 49 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 35, 56 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 35, 63 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 42, 0 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 42, 7 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 42, 14 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 42, 21 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 42, 28 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 42, 35 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 42, 42 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 42, 49 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 42, 56 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 42, 63 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 49, 0 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 49, 7 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 49, 14 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 49, 21 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 49, 28 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 49, 35 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 49, 42 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 49, 49 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 49, 56 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 49, 63 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 56, 0 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 56, 7 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 56, 14 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 56, 21 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 56, 28 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 56, 35 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 56, 42 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 56, 49 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 56, 56 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 56, 63 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 63, 0 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 63, 7 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 63, 14 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 63, 21 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 63, 28 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 63, 35 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 63, 42 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 63, 49 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 63, 56 => 0000000000000000 (20000000 00000000)
- rldicl. 0000000000000000, 63, 63 => 0000000000000000 (20000000 00000000)
- rldicl. 0000001cbe991def, 0, 0 => 0000001cbe991def (40000000 00000000)
- rldicl. 0000001cbe991def, 0, 7 => 0000001cbe991def (40000000 00000000)
- rldicl. 0000001cbe991def, 0, 14 => 0000001cbe991def (40000000 00000000)
- rldicl. 0000001cbe991def, 0, 21 => 0000001cbe991def (40000000 00000000)
- rldicl. 0000001cbe991def, 0, 28 => 0000000cbe991def (40000000 00000000)
- rldicl. 0000001cbe991def, 0, 35 => 000000001e991def (40000000 00000000)
- rldicl. 0000001cbe991def, 0, 42 => 0000000000191def (40000000 00000000)
- rldicl. 0000001cbe991def, 0, 49 => 0000000000001def (40000000 00000000)
- rldicl. 0000001cbe991def, 0, 56 => 00000000000000ef (40000000 00000000)
- rldicl. 0000001cbe991def, 0, 63 => 0000000000000001 (40000000 00000000)
- rldicl. 0000001cbe991def, 7, 0 => 00000e5f4c8ef780 (40000000 00000000)
- rldicl. 0000001cbe991def, 7, 7 => 00000e5f4c8ef780 (40000000 00000000)
- rldicl. 0000001cbe991def, 7, 14 => 00000e5f4c8ef780 (40000000 00000000)
- rldicl. 0000001cbe991def, 7, 21 => 0000065f4c8ef780 (40000000 00000000)
- rldicl. 0000001cbe991def, 7, 28 => 0000000f4c8ef780 (40000000 00000000)
- rldicl. 0000001cbe991def, 7, 35 => 000000000c8ef780 (40000000 00000000)
- rldicl. 0000001cbe991def, 7, 42 => 00000000000ef780 (40000000 00000000)
- rldicl. 0000001cbe991def, 7, 49 => 0000000000007780 (40000000 00000000)
- rldicl. 0000001cbe991def, 7, 56 => 0000000000000080 (40000000 00000000)
- rldicl. 0000001cbe991def, 7, 63 => 0000000000000000 (20000000 00000000)
- rldicl. 0000001cbe991def, 14, 0 => 00072fa6477bc000 (40000000 00000000)
- rldicl. 0000001cbe991def, 14, 7 => 00072fa6477bc000 (40000000 00000000)
- rldicl. 0000001cbe991def, 14, 14 => 00032fa6477bc000 (40000000 00000000)
- rldicl. 0000001cbe991def, 14, 21 => 000007a6477bc000 (40000000 00000000)
- rldicl. 0000001cbe991def, 14, 28 => 00000006477bc000 (40000000 00000000)
- rldicl. 0000001cbe991def, 14, 35 => 00000000077bc000 (40000000 00000000)
- rldicl. 0000001cbe991def, 14, 42 => 00000000003bc000 (40000000 00000000)
- rldicl. 0000001cbe991def, 14, 49 => 0000000000004000 (40000000 00000000)
- rldicl. 0000001cbe991def, 14, 56 => 0000000000000000 (20000000 00000000)
- rldicl. 0000001cbe991def, 14, 63 => 0000000000000000 (20000000 00000000)
- rldicl. 0000001cbe991def, 21, 0 => 0397d323bde00000 (40000000 00000000)
- rldicl. 0000001cbe991def, 21, 7 => 0197d323bde00000 (40000000 00000000)
- rldicl. 0000001cbe991def, 21, 14 => 0003d323bde00000 (40000000 00000000)
- rldicl. 0000001cbe991def, 21, 21 => 00000323bde00000 (40000000 00000000)
- rldicl. 0000001cbe991def, 21, 28 => 00000003bde00000 (40000000 00000000)
- rldicl. 0000001cbe991def, 21, 35 => 000000001de00000 (40000000 00000000)
- rldicl. 0000001cbe991def, 21, 42 => 0000000000200000 (40000000 00000000)
- rldicl. 0000001cbe991def, 21, 49 => 0000000000000000 (20000000 00000000)
- rldicl. 0000001cbe991def, 21, 56 => 0000000000000000 (20000000 00000000)
- rldicl. 0000001cbe991def, 21, 63 => 0000000000000000 (20000000 00000000)
- rldicl. 0000001cbe991def, 28, 0 => cbe991def0000001 (80000000 00000000)
- rldicl. 0000001cbe991def, 28, 7 => 01e991def0000001 (40000000 00000000)
- rldicl. 0000001cbe991def, 28, 14 => 000191def0000001 (40000000 00000000)
- rldicl. 0000001cbe991def, 28, 21 => 000001def0000001 (40000000 00000000)
- rldicl. 0000001cbe991def, 28, 28 => 0000000ef0000001 (40000000 00000000)
- rldicl. 0000001cbe991def, 28, 35 => 0000000010000001 (40000000 00000000)
- rldicl. 0000001cbe991def, 28, 42 => 0000000000000001 (40000000 00000000)
- rldicl. 0000001cbe991def, 28, 49 => 0000000000000001 (40000000 00000000)
- rldicl. 0000001cbe991def, 28, 56 => 0000000000000001 (40000000 00000000)
- rldicl. 0000001cbe991def, 28, 63 => 0000000000000001 (40000000 00000000)
- rldicl. 0000001cbe991def, 35, 0 => f4c8ef78000000e5 (80000000 00000000)
- rldicl. 0000001cbe991def, 35, 7 => 00c8ef78000000e5 (40000000 00000000)
- rldicl. 0000001cbe991def, 35, 14 => 0000ef78000000e5 (40000000 00000000)
- rldicl. 0000001cbe991def, 35, 21 => 00000778000000e5 (40000000 00000000)
- rldicl. 0000001cbe991def, 35, 28 => 00000008000000e5 (40000000 00000000)
- rldicl. 0000001cbe991def, 35, 35 => 00000000000000e5 (40000000 00000000)
- rldicl. 0000001cbe991def, 35, 42 => 00000000000000e5 (40000000 00000000)
- rldicl. 0000001cbe991def, 35, 49 => 00000000000000e5 (40000000 00000000)
- rldicl. 0000001cbe991def, 35, 56 => 00000000000000e5 (40000000 00000000)
- rldicl. 0000001cbe991def, 35, 63 => 0000000000000001 (40000000 00000000)
- rldicl. 0000001cbe991def, 42, 0 => 6477bc00000072fa (40000000 00000000)
- rldicl. 0000001cbe991def, 42, 7 => 0077bc00000072fa (40000000 00000000)
- rldicl. 0000001cbe991def, 42, 14 => 0003bc00000072fa (40000000 00000000)
- rldicl. 0000001cbe991def, 42, 21 => 00000400000072fa (40000000 00000000)
- rldicl. 0000001cbe991def, 42, 28 => 00000000000072fa (40000000 00000000)
- rldicl. 0000001cbe991def, 42, 35 => 00000000000072fa (40000000 00000000)
- rldicl. 0000001cbe991def, 42, 42 => 00000000000072fa (40000000 00000000)
- rldicl. 0000001cbe991def, 42, 49 => 00000000000072fa (40000000 00000000)
- rldicl. 0000001cbe991def, 42, 56 => 00000000000000fa (40000000 00000000)
- rldicl. 0000001cbe991def, 42, 63 => 0000000000000000 (20000000 00000000)
- rldicl. 0000001cbe991def, 49, 0 => 3bde000000397d32 (40000000 00000000)
- rldicl. 0000001cbe991def, 49, 7 => 01de000000397d32 (40000000 00000000)
- rldicl. 0000001cbe991def, 49, 14 => 0002000000397d32 (40000000 00000000)
- rldicl. 0000001cbe991def, 49, 21 => 0000000000397d32 (40000000 00000000)
- rldicl. 0000001cbe991def, 49, 28 => 0000000000397d32 (40000000 00000000)
- rldicl. 0000001cbe991def, 49, 35 => 0000000000397d32 (40000000 00000000)
- rldicl. 0000001cbe991def, 49, 42 => 0000000000397d32 (40000000 00000000)
- rldicl. 0000001cbe991def, 49, 49 => 0000000000007d32 (40000000 00000000)
- rldicl. 0000001cbe991def, 49, 56 => 0000000000000032 (40000000 00000000)
- rldicl. 0000001cbe991def, 49, 63 => 0000000000000000 (20000000 00000000)
- rldicl. 0000001cbe991def, 56, 0 => ef0000001cbe991d (80000000 00000000)
- rldicl. 0000001cbe991def, 56, 7 => 010000001cbe991d (40000000 00000000)
- rldicl. 0000001cbe991def, 56, 14 => 000000001cbe991d (40000000 00000000)
- rldicl. 0000001cbe991def, 56, 21 => 000000001cbe991d (40000000 00000000)
- rldicl. 0000001cbe991def, 56, 28 => 000000001cbe991d (40000000 00000000)
- rldicl. 0000001cbe991def, 56, 35 => 000000001cbe991d (40000000 00000000)
- rldicl. 0000001cbe991def, 56, 42 => 00000000003e991d (40000000 00000000)
- rldicl. 0000001cbe991def, 56, 49 => 000000000000191d (40000000 00000000)
- rldicl. 0000001cbe991def, 56, 56 => 000000000000001d (40000000 00000000)
- rldicl. 0000001cbe991def, 56, 63 => 0000000000000001 (40000000 00000000)
- rldicl. 0000001cbe991def, 63, 0 => 8000000e5f4c8ef7 (80000000 00000000)
- rldicl. 0000001cbe991def, 63, 7 => 0000000e5f4c8ef7 (40000000 00000000)
- rldicl. 0000001cbe991def, 63, 14 => 0000000e5f4c8ef7 (40000000 00000000)
- rldicl. 0000001cbe991def, 63, 21 => 0000000e5f4c8ef7 (40000000 00000000)
- rldicl. 0000001cbe991def, 63, 28 => 0000000e5f4c8ef7 (40000000 00000000)
- rldicl. 0000001cbe991def, 63, 35 => 000000001f4c8ef7 (40000000 00000000)
- rldicl. 0000001cbe991def, 63, 42 => 00000000000c8ef7 (40000000 00000000)
- rldicl. 0000001cbe991def, 63, 49 => 0000000000000ef7 (40000000 00000000)
- rldicl. 0000001cbe991def, 63, 56 => 00000000000000f7 (40000000 00000000)
- rldicl. 0000001cbe991def, 63, 63 => 0000000000000001 (40000000 00000000)
- rldicl. ffffffffffffffff, 0, 0 => ffffffffffffffff (80000000 00000000)
- rldicl. ffffffffffffffff, 0, 7 => 01ffffffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 0, 14 => 0003ffffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 0, 21 => 000007ffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 0, 28 => 0000000fffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 0, 35 => 000000001fffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 0, 42 => 00000000003fffff (40000000 00000000)
- rldicl. ffffffffffffffff, 0, 49 => 0000000000007fff (40000000 00000000)
- rldicl. ffffffffffffffff, 0, 56 => 00000000000000ff (40000000 00000000)
- rldicl. ffffffffffffffff, 0, 63 => 0000000000000001 (40000000 00000000)
- rldicl. ffffffffffffffff, 7, 0 => ffffffffffffffff (80000000 00000000)
- rldicl. ffffffffffffffff, 7, 7 => 01ffffffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 7, 14 => 0003ffffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 7, 21 => 000007ffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 7, 28 => 0000000fffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 7, 35 => 000000001fffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 7, 42 => 00000000003fffff (40000000 00000000)
- rldicl. ffffffffffffffff, 7, 49 => 0000000000007fff (40000000 00000000)
- rldicl. ffffffffffffffff, 7, 56 => 00000000000000ff (40000000 00000000)
- rldicl. ffffffffffffffff, 7, 63 => 0000000000000001 (40000000 00000000)
- rldicl. ffffffffffffffff, 14, 0 => ffffffffffffffff (80000000 00000000)
- rldicl. ffffffffffffffff, 14, 7 => 01ffffffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 14, 14 => 0003ffffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 14, 21 => 000007ffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 14, 28 => 0000000fffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 14, 35 => 000000001fffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 14, 42 => 00000000003fffff (40000000 00000000)
- rldicl. ffffffffffffffff, 14, 49 => 0000000000007fff (40000000 00000000)
- rldicl. ffffffffffffffff, 14, 56 => 00000000000000ff (40000000 00000000)
- rldicl. ffffffffffffffff, 14, 63 => 0000000000000001 (40000000 00000000)
- rldicl. ffffffffffffffff, 21, 0 => ffffffffffffffff (80000000 00000000)
- rldicl. ffffffffffffffff, 21, 7 => 01ffffffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 21, 14 => 0003ffffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 21, 21 => 000007ffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 21, 28 => 0000000fffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 21, 35 => 000000001fffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 21, 42 => 00000000003fffff (40000000 00000000)
- rldicl. ffffffffffffffff, 21, 49 => 0000000000007fff (40000000 00000000)
- rldicl. ffffffffffffffff, 21, 56 => 00000000000000ff (40000000 00000000)
- rldicl. ffffffffffffffff, 21, 63 => 0000000000000001 (40000000 00000000)
- rldicl. ffffffffffffffff, 28, 0 => ffffffffffffffff (80000000 00000000)
- rldicl. ffffffffffffffff, 28, 7 => 01ffffffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 28, 14 => 0003ffffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 28, 21 => 000007ffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 28, 28 => 0000000fffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 28, 35 => 000000001fffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 28, 42 => 00000000003fffff (40000000 00000000)
- rldicl. ffffffffffffffff, 28, 49 => 0000000000007fff (40000000 00000000)
- rldicl. ffffffffffffffff, 28, 56 => 00000000000000ff (40000000 00000000)
- rldicl. ffffffffffffffff, 28, 63 => 0000000000000001 (40000000 00000000)
- rldicl. ffffffffffffffff, 35, 0 => ffffffffffffffff (80000000 00000000)
- rldicl. ffffffffffffffff, 35, 7 => 01ffffffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 35, 14 => 0003ffffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 35, 21 => 000007ffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 35, 28 => 0000000fffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 35, 35 => 000000001fffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 35, 42 => 00000000003fffff (40000000 00000000)
- rldicl. ffffffffffffffff, 35, 49 => 0000000000007fff (40000000 00000000)
- rldicl. ffffffffffffffff, 35, 56 => 00000000000000ff (40000000 00000000)
- rldicl. ffffffffffffffff, 35, 63 => 0000000000000001 (40000000 00000000)
- rldicl. ffffffffffffffff, 42, 0 => ffffffffffffffff (80000000 00000000)
- rldicl. ffffffffffffffff, 42, 7 => 01ffffffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 42, 14 => 0003ffffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 42, 21 => 000007ffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 42, 28 => 0000000fffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 42, 35 => 000000001fffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 42, 42 => 00000000003fffff (40000000 00000000)
- rldicl. ffffffffffffffff, 42, 49 => 0000000000007fff (40000000 00000000)
- rldicl. ffffffffffffffff, 42, 56 => 00000000000000ff (40000000 00000000)
- rldicl. ffffffffffffffff, 42, 63 => 0000000000000001 (40000000 00000000)
- rldicl. ffffffffffffffff, 49, 0 => ffffffffffffffff (80000000 00000000)
- rldicl. ffffffffffffffff, 49, 7 => 01ffffffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 49, 14 => 0003ffffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 49, 21 => 000007ffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 49, 28 => 0000000fffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 49, 35 => 000000001fffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 49, 42 => 00000000003fffff (40000000 00000000)
- rldicl. ffffffffffffffff, 49, 49 => 0000000000007fff (40000000 00000000)
- rldicl. ffffffffffffffff, 49, 56 => 00000000000000ff (40000000 00000000)
- rldicl. ffffffffffffffff, 49, 63 => 0000000000000001 (40000000 00000000)
- rldicl. ffffffffffffffff, 56, 0 => ffffffffffffffff (80000000 00000000)
- rldicl. ffffffffffffffff, 56, 7 => 01ffffffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 56, 14 => 0003ffffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 56, 21 => 000007ffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 56, 28 => 0000000fffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 56, 35 => 000000001fffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 56, 42 => 00000000003fffff (40000000 00000000)
- rldicl. ffffffffffffffff, 56, 49 => 0000000000007fff (40000000 00000000)
- rldicl. ffffffffffffffff, 56, 56 => 00000000000000ff (40000000 00000000)
- rldicl. ffffffffffffffff, 56, 63 => 0000000000000001 (40000000 00000000)
- rldicl. ffffffffffffffff, 63, 0 => ffffffffffffffff (80000000 00000000)
- rldicl. ffffffffffffffff, 63, 7 => 01ffffffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 63, 14 => 0003ffffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 63, 21 => 000007ffffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 63, 28 => 0000000fffffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 63, 35 => 000000001fffffff (40000000 00000000)
- rldicl. ffffffffffffffff, 63, 42 => 00000000003fffff (40000000 00000000)
- rldicl. ffffffffffffffff, 63, 49 => 0000000000007fff (40000000 00000000)
- rldicl. ffffffffffffffff, 63, 56 => 00000000000000ff (40000000 00000000)
- rldicl. ffffffffffffffff, 63, 63 => 0000000000000001 (40000000 00000000)
-
- rldicr. 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 0, 7 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 0, 14 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 0, 21 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 0, 28 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 0, 35 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 0, 42 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 0, 49 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 0, 56 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 0, 63 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 7, 0 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 7, 7 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 7, 14 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 7, 21 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 7, 28 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 7, 35 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 7, 42 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 7, 49 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 7, 56 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 7, 63 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 14, 0 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 14, 7 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 14, 14 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 14, 21 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 14, 28 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 14, 35 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 14, 42 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 14, 49 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 14, 56 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 14, 63 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 21, 0 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 21, 7 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 21, 14 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 21, 21 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 21, 28 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 21, 35 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 21, 42 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 21, 49 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 21, 56 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 21, 63 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 28, 0 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 28, 7 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 28, 14 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 28, 21 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 28, 28 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 28, 35 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 28, 42 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 28, 49 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 28, 56 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 28, 63 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 35, 0 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 35, 7 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 35, 14 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 35, 21 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 35, 28 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 35, 35 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 35, 42 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 35, 49 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 35, 56 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 35, 63 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 42, 0 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 42, 7 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 42, 14 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 42, 21 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 42, 28 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 42, 35 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 42, 42 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 42, 49 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 42, 56 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 42, 63 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 49, 0 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 49, 7 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 49, 14 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 49, 21 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 49, 28 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 49, 35 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 49, 42 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 49, 49 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 49, 56 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 49, 63 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 56, 0 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 56, 7 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 56, 14 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 56, 21 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 56, 28 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 56, 35 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 56, 42 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 56, 49 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 56, 56 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 56, 63 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 63, 0 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 63, 7 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 63, 14 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 63, 21 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 63, 28 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 63, 35 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 63, 42 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 63, 49 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 63, 56 => 0000000000000000 (20000000 00000000)
- rldicr. 0000000000000000, 63, 63 => 0000000000000000 (20000000 00000000)
- rldicr. 0000001cbe991def, 0, 0 => 0000000000000000 (20000000 00000000)
- rldicr. 0000001cbe991def, 0, 7 => 0000000000000000 (20000000 00000000)
- rldicr. 0000001cbe991def, 0, 14 => 0000000000000000 (20000000 00000000)
- rldicr. 0000001cbe991def, 0, 21 => 0000000000000000 (20000000 00000000)
- rldicr. 0000001cbe991def, 0, 28 => 0000001800000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 0, 35 => 0000001cb0000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 0, 42 => 0000001cbe800000 (40000000 00000000)
- rldicr. 0000001cbe991def, 0, 49 => 0000001cbe990000 (40000000 00000000)
- rldicr. 0000001cbe991def, 0, 56 => 0000001cbe991d80 (40000000 00000000)
- rldicr. 0000001cbe991def, 0, 63 => 0000001cbe991def (40000000 00000000)
- rldicr. 0000001cbe991def, 7, 0 => 0000000000000000 (20000000 00000000)
- rldicr. 0000001cbe991def, 7, 7 => 0000000000000000 (20000000 00000000)
- rldicr. 0000001cbe991def, 7, 14 => 0000000000000000 (20000000 00000000)
- rldicr. 0000001cbe991def, 7, 21 => 00000c0000000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 7, 28 => 00000e5800000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 7, 35 => 00000e5f40000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 7, 42 => 00000e5f4c800000 (40000000 00000000)
- rldicr. 0000001cbe991def, 7, 49 => 00000e5f4c8ec000 (40000000 00000000)
- rldicr. 0000001cbe991def, 7, 56 => 00000e5f4c8ef780 (40000000 00000000)
- rldicr. 0000001cbe991def, 7, 63 => 00000e5f4c8ef780 (40000000 00000000)
- rldicr. 0000001cbe991def, 14, 0 => 0000000000000000 (20000000 00000000)
- rldicr. 0000001cbe991def, 14, 7 => 0000000000000000 (20000000 00000000)
- rldicr. 0000001cbe991def, 14, 14 => 0006000000000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 14, 21 => 00072c0000000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 14, 28 => 00072fa000000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 14, 35 => 00072fa640000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 14, 42 => 00072fa647600000 (40000000 00000000)
- rldicr. 0000001cbe991def, 14, 49 => 00072fa6477bc000 (40000000 00000000)
- rldicr. 0000001cbe991def, 14, 56 => 00072fa6477bc000 (40000000 00000000)
- rldicr. 0000001cbe991def, 14, 63 => 00072fa6477bc000 (40000000 00000000)
- rldicr. 0000001cbe991def, 21, 0 => 0000000000000000 (20000000 00000000)
- rldicr. 0000001cbe991def, 21, 7 => 0300000000000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 21, 14 => 0396000000000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 21, 21 => 0397d00000000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 21, 28 => 0397d32000000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 21, 35 => 0397d323b0000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 21, 42 => 0397d323bde00000 (40000000 00000000)
- rldicr. 0000001cbe991def, 21, 49 => 0397d323bde00000 (40000000 00000000)
- rldicr. 0000001cbe991def, 21, 56 => 0397d323bde00000 (40000000 00000000)
- rldicr. 0000001cbe991def, 21, 63 => 0397d323bde00000 (40000000 00000000)
- rldicr. 0000001cbe991def, 28, 0 => 8000000000000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 28, 7 => cb00000000000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 28, 14 => cbe8000000000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 28, 21 => cbe9900000000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 28, 28 => cbe991d800000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 28, 35 => cbe991def0000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 28, 42 => cbe991def0000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 28, 49 => cbe991def0000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 28, 56 => cbe991def0000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 28, 63 => cbe991def0000001 (80000000 00000000)
- rldicr. 0000001cbe991def, 35, 0 => 8000000000000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 35, 7 => f400000000000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 35, 14 => f4c8000000000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 35, 21 => f4c8ec0000000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 35, 28 => f4c8ef7800000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 35, 35 => f4c8ef7800000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 35, 42 => f4c8ef7800000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 35, 49 => f4c8ef7800000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 35, 56 => f4c8ef7800000080 (80000000 00000000)
- rldicr. 0000001cbe991def, 35, 63 => f4c8ef78000000e5 (80000000 00000000)
- rldicr. 0000001cbe991def, 42, 0 => 0000000000000000 (20000000 00000000)
- rldicr. 0000001cbe991def, 42, 7 => 6400000000000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 42, 14 => 6476000000000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 42, 21 => 6477bc0000000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 42, 28 => 6477bc0000000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 42, 35 => 6477bc0000000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 42, 42 => 6477bc0000000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 42, 49 => 6477bc0000004000 (40000000 00000000)
- rldicr. 0000001cbe991def, 42, 56 => 6477bc0000007280 (40000000 00000000)
- rldicr. 0000001cbe991def, 42, 63 => 6477bc00000072fa (40000000 00000000)
- rldicr. 0000001cbe991def, 49, 0 => 0000000000000000 (20000000 00000000)
- rldicr. 0000001cbe991def, 49, 7 => 3b00000000000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 49, 14 => 3bde000000000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 49, 21 => 3bde000000000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 49, 28 => 3bde000000000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 49, 35 => 3bde000000000000 (40000000 00000000)
- rldicr. 0000001cbe991def, 49, 42 => 3bde000000200000 (40000000 00000000)
- rldicr. 0000001cbe991def, 49, 49 => 3bde000000394000 (40000000 00000000)
- rldicr. 0000001cbe991def, 49, 56 => 3bde000000397d00 (40000000 00000000)
- rldicr. 0000001cbe991def, 49, 63 => 3bde000000397d32 (40000000 00000000)
- rldicr. 0000001cbe991def, 56, 0 => 8000000000000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 56, 7 => ef00000000000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 56, 14 => ef00000000000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 56, 21 => ef00000000000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 56, 28 => ef00000000000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 56, 35 => ef00000010000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 56, 42 => ef0000001ca00000 (80000000 00000000)
- rldicr. 0000001cbe991def, 56, 49 => ef0000001cbe8000 (80000000 00000000)
- rldicr. 0000001cbe991def, 56, 56 => ef0000001cbe9900 (80000000 00000000)
- rldicr. 0000001cbe991def, 56, 63 => ef0000001cbe991d (80000000 00000000)
- rldicr. 0000001cbe991def, 63, 0 => 8000000000000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 63, 7 => 8000000000000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 63, 14 => 8000000000000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 63, 21 => 8000000000000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 63, 28 => 8000000800000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 63, 35 => 8000000e50000000 (80000000 00000000)
- rldicr. 0000001cbe991def, 63, 42 => 8000000e5f400000 (80000000 00000000)
- rldicr. 0000001cbe991def, 63, 49 => 8000000e5f4c8000 (80000000 00000000)
- rldicr. 0000001cbe991def, 63, 56 => 8000000e5f4c8e80 (80000000 00000000)
- rldicr. 0000001cbe991def, 63, 63 => 8000000e5f4c8ef7 (80000000 00000000)
- rldicr. ffffffffffffffff, 0, 0 => 8000000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 0, 7 => ff00000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 0, 14 => fffe000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 0, 21 => fffffc0000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 0, 28 => fffffff800000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 0, 35 => fffffffff0000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 0, 42 => ffffffffffe00000 (80000000 00000000)
- rldicr. ffffffffffffffff, 0, 49 => ffffffffffffc000 (80000000 00000000)
- rldicr. ffffffffffffffff, 0, 56 => ffffffffffffff80 (80000000 00000000)
- rldicr. ffffffffffffffff, 0, 63 => ffffffffffffffff (80000000 00000000)
- rldicr. ffffffffffffffff, 7, 0 => 8000000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 7, 7 => ff00000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 7, 14 => fffe000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 7, 21 => fffffc0000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 7, 28 => fffffff800000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 7, 35 => fffffffff0000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 7, 42 => ffffffffffe00000 (80000000 00000000)
- rldicr. ffffffffffffffff, 7, 49 => ffffffffffffc000 (80000000 00000000)
- rldicr. ffffffffffffffff, 7, 56 => ffffffffffffff80 (80000000 00000000)
- rldicr. ffffffffffffffff, 7, 63 => ffffffffffffffff (80000000 00000000)
- rldicr. ffffffffffffffff, 14, 0 => 8000000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 14, 7 => ff00000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 14, 14 => fffe000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 14, 21 => fffffc0000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 14, 28 => fffffff800000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 14, 35 => fffffffff0000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 14, 42 => ffffffffffe00000 (80000000 00000000)
- rldicr. ffffffffffffffff, 14, 49 => ffffffffffffc000 (80000000 00000000)
- rldicr. ffffffffffffffff, 14, 56 => ffffffffffffff80 (80000000 00000000)
- rldicr. ffffffffffffffff, 14, 63 => ffffffffffffffff (80000000 00000000)
- rldicr. ffffffffffffffff, 21, 0 => 8000000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 21, 7 => ff00000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 21, 14 => fffe000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 21, 21 => fffffc0000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 21, 28 => fffffff800000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 21, 35 => fffffffff0000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 21, 42 => ffffffffffe00000 (80000000 00000000)
- rldicr. ffffffffffffffff, 21, 49 => ffffffffffffc000 (80000000 00000000)
- rldicr. ffffffffffffffff, 21, 56 => ffffffffffffff80 (80000000 00000000)
- rldicr. ffffffffffffffff, 21, 63 => ffffffffffffffff (80000000 00000000)
- rldicr. ffffffffffffffff, 28, 0 => 8000000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 28, 7 => ff00000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 28, 14 => fffe000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 28, 21 => fffffc0000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 28, 28 => fffffff800000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 28, 35 => fffffffff0000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 28, 42 => ffffffffffe00000 (80000000 00000000)
- rldicr. ffffffffffffffff, 28, 49 => ffffffffffffc000 (80000000 00000000)
- rldicr. ffffffffffffffff, 28, 56 => ffffffffffffff80 (80000000 00000000)
- rldicr. ffffffffffffffff, 28, 63 => ffffffffffffffff (80000000 00000000)
- rldicr. ffffffffffffffff, 35, 0 => 8000000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 35, 7 => ff00000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 35, 14 => fffe000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 35, 21 => fffffc0000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 35, 28 => fffffff800000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 35, 35 => fffffffff0000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 35, 42 => ffffffffffe00000 (80000000 00000000)
- rldicr. ffffffffffffffff, 35, 49 => ffffffffffffc000 (80000000 00000000)
- rldicr. ffffffffffffffff, 35, 56 => ffffffffffffff80 (80000000 00000000)
- rldicr. ffffffffffffffff, 35, 63 => ffffffffffffffff (80000000 00000000)
- rldicr. ffffffffffffffff, 42, 0 => 8000000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 42, 7 => ff00000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 42, 14 => fffe000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 42, 21 => fffffc0000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 42, 28 => fffffff800000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 42, 35 => fffffffff0000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 42, 42 => ffffffffffe00000 (80000000 00000000)
- rldicr. ffffffffffffffff, 42, 49 => ffffffffffffc000 (80000000 00000000)
- rldicr. ffffffffffffffff, 42, 56 => ffffffffffffff80 (80000000 00000000)
- rldicr. ffffffffffffffff, 42, 63 => ffffffffffffffff (80000000 00000000)
- rldicr. ffffffffffffffff, 49, 0 => 8000000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 49, 7 => ff00000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 49, 14 => fffe000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 49, 21 => fffffc0000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 49, 28 => fffffff800000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 49, 35 => fffffffff0000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 49, 42 => ffffffffffe00000 (80000000 00000000)
- rldicr. ffffffffffffffff, 49, 49 => ffffffffffffc000 (80000000 00000000)
- rldicr. ffffffffffffffff, 49, 56 => ffffffffffffff80 (80000000 00000000)
- rldicr. ffffffffffffffff, 49, 63 => ffffffffffffffff (80000000 00000000)
- rldicr. ffffffffffffffff, 56, 0 => 8000000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 56, 7 => ff00000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 56, 14 => fffe000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 56, 21 => fffffc0000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 56, 28 => fffffff800000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 56, 35 => fffffffff0000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 56, 42 => ffffffffffe00000 (80000000 00000000)
- rldicr. ffffffffffffffff, 56, 49 => ffffffffffffc000 (80000000 00000000)
- rldicr. ffffffffffffffff, 56, 56 => ffffffffffffff80 (80000000 00000000)
- rldicr. ffffffffffffffff, 56, 63 => ffffffffffffffff (80000000 00000000)
- rldicr. ffffffffffffffff, 63, 0 => 8000000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 63, 7 => ff00000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 63, 14 => fffe000000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 63, 21 => fffffc0000000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 63, 28 => fffffff800000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 63, 35 => fffffffff0000000 (80000000 00000000)
- rldicr. ffffffffffffffff, 63, 42 => ffffffffffe00000 (80000000 00000000)
- rldicr. ffffffffffffffff, 63, 49 => ffffffffffffc000 (80000000 00000000)
- rldicr. ffffffffffffffff, 63, 56 => ffffffffffffff80 (80000000 00000000)
- rldicr. ffffffffffffffff, 63, 63 => ffffffffffffffff (80000000 00000000)
-
- rldimi. 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 0, 7 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 0, 14 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 0, 21 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 0, 28 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 0, 35 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 0, 42 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 0, 49 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 0, 56 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 0, 63 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 7, 0 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 7, 7 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 7, 14 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 7, 21 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 7, 28 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 7, 35 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 7, 42 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 7, 49 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 7, 56 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 7, 63 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 14, 0 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 14, 7 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 14, 14 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 14, 21 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 14, 28 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 14, 35 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 14, 42 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 14, 49 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 14, 56 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 14, 63 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 21, 0 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 21, 7 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 21, 14 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 21, 21 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 21, 28 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 21, 35 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 21, 42 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 21, 49 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 21, 56 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 21, 63 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 28, 0 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 28, 7 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 28, 14 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 28, 21 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 28, 28 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 28, 35 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 28, 42 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 28, 49 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 28, 56 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 28, 63 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 35, 0 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 35, 7 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 35, 14 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 35, 21 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 35, 28 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 35, 35 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 35, 42 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 35, 49 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 35, 56 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 35, 63 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 42, 0 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 42, 7 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 42, 14 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 42, 21 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 42, 28 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 42, 35 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 42, 42 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 42, 49 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 42, 56 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 42, 63 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 49, 0 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 49, 7 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 49, 14 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 49, 21 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 49, 28 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 49, 35 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 49, 42 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 49, 49 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 49, 56 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 49, 63 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 56, 0 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 56, 7 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 56, 14 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 56, 21 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 56, 28 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 56, 35 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 56, 42 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 56, 49 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 56, 56 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 56, 63 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 63, 0 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 63, 7 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 63, 14 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 63, 21 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 63, 28 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 63, 35 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 63, 42 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 63, 49 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 63, 56 => 0000000000000000 (20000000 00000000)
- rldimi. 0000000000000000, 63, 63 => 0000000000000000 (20000000 00000000)
- rldimi. 0000001cbe991def, 0, 0 => 0000001cbe991def (40000000 00000000)
- rldimi. 0000001cbe991def, 0, 7 => 0000001cbe991def (40000000 00000000)
- rldimi. 0000001cbe991def, 0, 14 => 0000001cbe991def (40000000 00000000)
- rldimi. 0000001cbe991def, 0, 21 => 0000001cbe991def (40000000 00000000)
- rldimi. 0000001cbe991def, 0, 28 => 0000001cbe991def (40000000 00000000)
- rldimi. 0000001cbe991def, 0, 35 => 0000001cbe991def (40000000 00000000)
- rldimi. 0000001cbe991def, 0, 42 => 0000001cbe991def (40000000 00000000)
- rldimi. 0000001cbe991def, 0, 49 => 0000001cbe991def (40000000 00000000)
- rldimi. 0000001cbe991def, 0, 56 => 0000001cbe991def (40000000 00000000)
- rldimi. 0000001cbe991def, 0, 63 => 0000001cbe991def (40000000 00000000)
- rldimi. 0000001cbe991def, 7, 0 => 00000e5f4c8ef7ef (40000000 00000000)
- rldimi. 0000001cbe991def, 7, 7 => 00000e5f4c8ef7ef (40000000 00000000)
- rldimi. 0000001cbe991def, 7, 14 => 00000e5f4c8ef7ef (40000000 00000000)
- rldimi. 0000001cbe991def, 7, 21 => 00000e5f4c8ef7ef (40000000 00000000)
- rldimi. 0000001cbe991def, 7, 28 => 00000e5f4c8ef7ef (40000000 00000000)
- rldimi. 0000001cbe991def, 7, 35 => 00000e5f4c8ef7ef (40000000 00000000)
- rldimi. 0000001cbe991def, 7, 42 => 00000e5f4c8ef7ef (40000000 00000000)
- rldimi. 0000001cbe991def, 7, 49 => 00000e5f4c8ef7ef (40000000 00000000)
- rldimi. 0000001cbe991def, 7, 56 => 00000e5f4c8ef7ef (40000000 00000000)
- rldimi. 0000001cbe991def, 7, 63 => 00000e5f4c8ef7ee (40000000 00000000)
- rldimi. 0000001cbe991def, 14, 0 => 00072fa6477bf7ee (40000000 00000000)
- rldimi. 0000001cbe991def, 14, 7 => 00072fa6477bf7ee (40000000 00000000)
- rldimi. 0000001cbe991def, 14, 14 => 00072fa6477bf7ee (40000000 00000000)
- rldimi. 0000001cbe991def, 14, 21 => 00072fa6477bf7ee (40000000 00000000)
- rldimi. 0000001cbe991def, 14, 28 => 00072fa6477bf7ee (40000000 00000000)
- rldimi. 0000001cbe991def, 14, 35 => 00072fa6477bf7ee (40000000 00000000)
- rldimi. 0000001cbe991def, 14, 42 => 00072fa6477bf7ee (40000000 00000000)
- rldimi. 0000001cbe991def, 14, 49 => 00072fa6477bf7ee (40000000 00000000)
- rldimi. 0000001cbe991def, 14, 56 => 00072fa6477bf700 (40000000 00000000)
- rldimi. 0000001cbe991def, 14, 63 => 00072fa6477bf700 (40000000 00000000)
- rldimi. 0000001cbe991def, 21, 0 => 0397d323bdfbf700 (40000000 00000000)
- rldimi. 0000001cbe991def, 21, 7 => 0397d323bdfbf700 (40000000 00000000)
- rldimi. 0000001cbe991def, 21, 14 => 0397d323bdfbf700 (40000000 00000000)
- rldimi. 0000001cbe991def, 21, 21 => 0397d323bdfbf700 (40000000 00000000)
- rldimi. 0000001cbe991def, 21, 28 => 0397d323bdfbf700 (40000000 00000000)
- rldimi. 0000001cbe991def, 21, 35 => 0397d323bdfbf700 (40000000 00000000)
- rldimi. 0000001cbe991def, 21, 42 => 0397d323bdfbf700 (40000000 00000000)
- rldimi. 0000001cbe991def, 21, 49 => 0397d323bdfb8000 (40000000 00000000)
- rldimi. 0000001cbe991def, 21, 56 => 0397d323bdfb8000 (40000000 00000000)
- rldimi. 0000001cbe991def, 21, 63 => 0397d323bdfb8000 (40000000 00000000)
- rldimi. 0000001cbe991def, 28, 0 => cbe991defdfb8000 (80000000 00000000)
- rldimi. 0000001cbe991def, 28, 7 => cbe991defdfb8000 (80000000 00000000)
- rldimi. 0000001cbe991def, 28, 14 => cbe991defdfb8000 (80000000 00000000)
- rldimi. 0000001cbe991def, 28, 21 => cbe991defdfb8000 (80000000 00000000)
- rldimi. 0000001cbe991def, 28, 28 => cbe991defdfb8000 (80000000 00000000)
- rldimi. 0000001cbe991def, 28, 35 => cbe991defdfb8000 (80000000 00000000)
- rldimi. 0000001cbe991def, 28, 42 => cbe991defdc00001 (80000000 00000000)
- rldimi. 0000001cbe991def, 28, 49 => cbe991defdc00001 (80000000 00000000)
- rldimi. 0000001cbe991def, 28, 56 => cbe991defdc00001 (80000000 00000000)
- rldimi. 0000001cbe991def, 28, 63 => cbe991defdc00001 (80000000 00000000)
- rldimi. 0000001cbe991def, 35, 0 => f4c8ef7efdc00001 (80000000 00000000)
- rldimi. 0000001cbe991def, 35, 7 => f4c8ef7efdc00001 (80000000 00000000)
- rldimi. 0000001cbe991def, 35, 14 => f4c8ef7efdc00001 (80000000 00000000)
- rldimi. 0000001cbe991def, 35, 21 => f4c8ef7efdc00001 (80000000 00000000)
- rldimi. 0000001cbe991def, 35, 28 => f4c8ef7efdc00001 (80000000 00000000)
- rldimi. 0000001cbe991def, 35, 35 => f4c8ef7ee00000e5 (80000000 00000000)
- rldimi. 0000001cbe991def, 35, 42 => f4c8ef7ee00000e5 (80000000 00000000)
- rldimi. 0000001cbe991def, 35, 49 => f4c8ef7ee00000e5 (80000000 00000000)
- rldimi. 0000001cbe991def, 35, 56 => f4c8ef7ee00000e5 (80000000 00000000)
- rldimi. 0000001cbe991def, 35, 63 => f4c8ef7ee00000e5 (80000000 00000000)
- rldimi. 0000001cbe991def, 42, 0 => 6477bf7ee00000e5 (40000000 00000000)
- rldimi. 0000001cbe991def, 42, 7 => 6477bf7ee00000e5 (40000000 00000000)
- rldimi. 0000001cbe991def, 42, 14 => 6477bf7ee00000e5 (40000000 00000000)
- rldimi. 0000001cbe991def, 42, 21 => 6477bf7ee00000e5 (40000000 00000000)
- rldimi. 0000001cbe991def, 42, 28 => 6477bf70000072fa (40000000 00000000)
- rldimi. 0000001cbe991def, 42, 35 => 6477bf70000072fa (40000000 00000000)
- rldimi. 0000001cbe991def, 42, 42 => 6477bf70000072fa (40000000 00000000)
- rldimi. 0000001cbe991def, 42, 49 => 6477bf70000072fa (40000000 00000000)
- rldimi. 0000001cbe991def, 42, 56 => 6477bf70000072fa (40000000 00000000)
- rldimi. 0000001cbe991def, 42, 63 => 6477bf70000072fa (40000000 00000000)
- rldimi. 0000001cbe991def, 49, 0 => 3bdfbf70000072fa (40000000 00000000)
- rldimi. 0000001cbe991def, 49, 7 => 3bdfbf70000072fa (40000000 00000000)
- rldimi. 0000001cbe991def, 49, 14 => 3bdfbf70000072fa (40000000 00000000)
- rldimi. 0000001cbe991def, 49, 21 => 3bdfb80000397d32 (40000000 00000000)
- rldimi. 0000001cbe991def, 49, 28 => 3bdfb80000397d32 (40000000 00000000)
- rldimi. 0000001cbe991def, 49, 35 => 3bdfb80000397d32 (40000000 00000000)
- rldimi. 0000001cbe991def, 49, 42 => 3bdfb80000397d32 (40000000 00000000)
- rldimi. 0000001cbe991def, 49, 49 => 3bdfb80000397d32 (40000000 00000000)
- rldimi. 0000001cbe991def, 49, 56 => 3bdfb80000397d32 (40000000 00000000)
- rldimi. 0000001cbe991def, 49, 63 => 3bdfb80000397d32 (40000000 00000000)
- rldimi. 0000001cbe991def, 56, 0 => efdfb80000397d32 (80000000 00000000)
- rldimi. 0000001cbe991def, 56, 7 => efdfb80000397d32 (80000000 00000000)
- rldimi. 0000001cbe991def, 56, 14 => efdc00001cbe991d (80000000 00000000)
- rldimi. 0000001cbe991def, 56, 21 => efdc00001cbe991d (80000000 00000000)
- rldimi. 0000001cbe991def, 56, 28 => efdc00001cbe991d (80000000 00000000)
- rldimi. 0000001cbe991def, 56, 35 => efdc00001cbe991d (80000000 00000000)
- rldimi. 0000001cbe991def, 56, 42 => efdc00001cbe991d (80000000 00000000)
- rldimi. 0000001cbe991def, 56, 49 => efdc00001cbe991d (80000000 00000000)
- rldimi. 0000001cbe991def, 56, 56 => efdc00001cbe991d (80000000 00000000)
- rldimi. 0000001cbe991def, 56, 63 => efdc00001cbe991d (80000000 00000000)
- rldimi. 0000001cbe991def, 63, 0 => efdc00001cbe991d (80000000 00000000)
- rldimi. 0000001cbe991def, 63, 7 => ee00000e5f4c8ef7 (80000000 00000000)
- rldimi. 0000001cbe991def, 63, 14 => ee00000e5f4c8ef7 (80000000 00000000)
- rldimi. 0000001cbe991def, 63, 21 => ee00000e5f4c8ef7 (80000000 00000000)
- rldimi. 0000001cbe991def, 63, 28 => ee00000e5f4c8ef7 (80000000 00000000)
- rldimi. 0000001cbe991def, 63, 35 => ee00000e5f4c8ef7 (80000000 00000000)
- rldimi. 0000001cbe991def, 63, 42 => ee00000e5f4c8ef7 (80000000 00000000)
- rldimi. 0000001cbe991def, 63, 49 => ee00000e5f4c8ef7 (80000000 00000000)
- rldimi. 0000001cbe991def, 63, 56 => ee00000e5f4c8ef7 (80000000 00000000)
- rldimi. 0000001cbe991def, 63, 63 => ee00000e5f4c8ef7 (80000000 00000000)
- rldimi. ffffffffffffffff, 0, 0 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 0, 7 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 0, 14 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 0, 21 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 0, 28 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 0, 35 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 0, 42 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 0, 49 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 0, 56 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 0, 63 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 7, 0 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 7, 7 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 7, 14 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 7, 21 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 7, 28 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 7, 35 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 7, 42 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 7, 49 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 7, 56 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 7, 63 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 14, 0 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 14, 7 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 14, 14 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 14, 21 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 14, 28 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 14, 35 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 14, 42 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 14, 49 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 14, 56 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 14, 63 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 21, 0 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 21, 7 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 21, 14 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 21, 21 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 21, 28 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 21, 35 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 21, 42 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 21, 49 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 21, 56 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 21, 63 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 28, 0 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 28, 7 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 28, 14 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 28, 21 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 28, 28 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 28, 35 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 28, 42 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 28, 49 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 28, 56 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 28, 63 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 35, 0 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 35, 7 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 35, 14 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 35, 21 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 35, 28 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 35, 35 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 35, 42 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 35, 49 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 35, 56 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 35, 63 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 42, 0 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 42, 7 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 42, 14 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 42, 21 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 42, 28 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 42, 35 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 42, 42 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 42, 49 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 42, 56 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 42, 63 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 49, 0 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 49, 7 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 49, 14 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 49, 21 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 49, 28 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 49, 35 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 49, 42 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 49, 49 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 49, 56 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 49, 63 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 56, 0 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 56, 7 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 56, 14 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 56, 21 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 56, 28 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 56, 35 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 56, 42 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 56, 49 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 56, 56 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 56, 63 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 63, 0 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 63, 7 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 63, 14 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 63, 21 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 63, 28 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 63, 35 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 63, 42 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 63, 49 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 63, 56 => ffffffffffffffff (80000000 00000000)
- rldimi. ffffffffffffffff, 63, 63 => ffffffffffffffff (80000000 00000000)
-
- sradi. 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
- sradi. 0000000000000000, 7 => 0000000000000000 (20000000 00000000)
- sradi. 0000000000000000, 14 => 0000000000000000 (20000000 00000000)
- sradi. 0000000000000000, 21 => 0000000000000000 (20000000 00000000)
- sradi. 0000000000000000, 28 => 0000000000000000 (20000000 00000000)
- sradi. 0000000000000000, 35 => 0000000000000000 (20000000 00000000)
- sradi. 0000000000000000, 42 => 0000000000000000 (20000000 00000000)
- sradi. 0000000000000000, 49 => 0000000000000000 (20000000 00000000)
- sradi. 0000000000000000, 56 => 0000000000000000 (20000000 00000000)
- sradi. 0000000000000000, 63 => 0000000000000000 (20000000 00000000)
- sradi. 0000001cbe991def, 0 => 0000001cbe991def (40000000 00000000)
- sradi. 0000001cbe991def, 7 => 00000000397d323b (40000000 00000000)
- sradi. 0000001cbe991def, 14 => 000000000072fa64 (40000000 00000000)
- sradi. 0000001cbe991def, 21 => 000000000000e5f4 (40000000 00000000)
- sradi. 0000001cbe991def, 28 => 00000000000001cb (40000000 00000000)
- sradi. 0000001cbe991def, 35 => 0000000000000003 (40000000 00000000)
- sradi. 0000001cbe991def, 42 => 0000000000000000 (20000000 00000000)
- sradi. 0000001cbe991def, 49 => 0000000000000000 (20000000 00000000)
- sradi. 0000001cbe991def, 56 => 0000000000000000 (20000000 00000000)
- sradi. 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000)
- sradi. ffffffffffffffff, 0 => ffffffffffffffff (80000000 00000000)
- sradi. ffffffffffffffff, 7 => ffffffffffffffff (80000000 20000000)
- sradi. ffffffffffffffff, 14 => ffffffffffffffff (80000000 20000000)
- sradi. ffffffffffffffff, 21 => ffffffffffffffff (80000000 20000000)
- sradi. ffffffffffffffff, 28 => ffffffffffffffff (80000000 20000000)
- sradi. ffffffffffffffff, 35 => ffffffffffffffff (80000000 20000000)
- sradi. ffffffffffffffff, 42 => ffffffffffffffff (80000000 20000000)
- sradi. ffffffffffffffff, 49 => ffffffffffffffff (80000000 20000000)
- sradi. ffffffffffffffff, 56 => ffffffffffffffff (80000000 20000000)
- sradi. ffffffffffffffff, 63 => ffffffffffffffff (80000000 20000000)
-
-PPC integer load insns
- with one register + one 16 bits immediate args with flags update:
- lbz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
- lbz 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
- lbz 15, (ffffffffffffffff) => 00000000000000ef, 0 (00000000 00000000)
- lbz 1, (ffffffffffffffff) => 00000000000000ff, 0 (00000000 00000000)
- lbz -7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
- lbz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
-
- lbzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
- lbzu 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000)
- lbzu 15, (ffffffffffffffff) => 00000000000000ef, 15 (00000000 00000000)
- lbzu 1, (ffffffffffffffff) => 00000000000000ff, 1 (00000000 00000000)
- lbzu -7, (0000001cbe991def) => 0000000000000000, -7 (00000000 00000000)
- lbzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
-
- lha 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
- lha 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
- lha 15, (ffffffffffffffff) => ffffffffffffefff, 0 (00000000 00000000)
- lha 1, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
- lha -7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
- lha -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
-
- lhau 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
- lhau 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000)
- lhau 15, (ffffffffffffffff) => ffffffffffffefff, 15 (00000000 00000000)
- lhau 1, (ffffffffffffffff) => ffffffffffffffff, 1 (00000000 00000000)
- lhau -7, (0000001cbe991def) => 0000000000000000, -7 (00000000 00000000)
- lhau -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
-
- lhz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
- lhz 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
- lhz 15, (ffffffffffffffff) => 000000000000efff, 0 (00000000 00000000)
- lhz 1, (ffffffffffffffff) => 000000000000ffff, 0 (00000000 00000000)
- lhz -7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
- lhz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
-
- lhzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
- lhzu 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000)
- lhzu 15, (ffffffffffffffff) => 000000000000efff, 15 (00000000 00000000)
- lhzu 1, (ffffffffffffffff) => 000000000000ffff, 1 (00000000 00000000)
- lhzu -7, (0000001cbe991def) => 0000000000000000, -7 (00000000 00000000)
- lhzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
-
- lwz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
- lwz 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
- lwz 15, (ffffffffffffffff) => 00000000efffffff, 0 (00000000 00000000)
- lwz 1, (ffffffffffffffff) => 00000000ffffffff, 0 (00000000 00000000)
- lwz -7, (0000001cbe991def) => 0000000000001cbe, 0 (00000000 00000000)
- lwz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
-
- lwzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
- lwzu 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000)
- lwzu 15, (ffffffffffffffff) => 00000000efffffff, 15 (00000000 00000000)
- lwzu 1, (ffffffffffffffff) => 00000000ffffffff, 1 (00000000 00000000)
- lwzu -7, (0000001cbe991def) => 0000000000001cbe, -7 (00000000 00000000)
- lwzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
-
- ld 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
- ld 7, (0000001cbe991def) => 000000000000001c, 0 (00000000 00000000)
- ld 15, (ffffffffffffffff) => be991defffffffff, 0 (00000000 00000000)
- ld 1, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
- ld -7, (0000001cbe991def) => 0000001cbe991def, -8 (00000000 00000000)
- ld -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
-
- ldu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
- ldu 7, (0000001cbe991def) => 000000000000001c, 4 (00000000 00000000)
- ldu 15, (ffffffffffffffff) => be991defffffffff, 12 (00000000 00000000)
- ldu 1, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
- ldu -7, (0000001cbe991def) => 0000001cbe991def, -8 (00000000 00000000)
- ldu -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
-
- lwa 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
- lwa 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
- lwa 15, (ffffffffffffffff) => ffffffffbe991def, 0 (00000000 00000000)
- lwa 1, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
- lwa -7, (0000001cbe991def) => 0000001cbe991def, -8 (00000000 00000000)
- lwa -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
-
-PPC integer load insns with two register args:
- lbzx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
- lbzx 8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
- lbzx 16, (ffffffffffffffff) => 00000000000000ff, 0 (00000000 00000000)
-
- lbzux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
- lbzux 8, (0000001cbe991def) => 0000000000000000, 8 (00000000 00000000)
- lbzux 16, (ffffffffffffffff) => 00000000000000ff, 16 (00000000 00000000)
-
- lhax 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
- lhax 8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
- lhax 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
-
- lhaux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
- lhaux 8, (0000001cbe991def) => 0000000000000000, 8 (00000000 00000000)
- lhaux 16, (ffffffffffffffff) => ffffffffffffffff, 16 (00000000 00000000)
-
- lhzx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
- lhzx 8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
- lhzx 16, (ffffffffffffffff) => 000000000000ffff, 0 (00000000 00000000)
-
- lhzux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
- lhzux 8, (0000001cbe991def) => 0000000000000000, 8 (00000000 00000000)
- lhzux 16, (ffffffffffffffff) => 000000000000ffff, 16 (00000000 00000000)
-
- lwzx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
- lwzx 8, (0000001cbe991def) => 000000000000001c, 0 (00000000 00000000)
- lwzx 16, (ffffffffffffffff) => 00000000ffffffff, 0 (00000000 00000000)
-
- lwzux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
- lwzux 8, (0000001cbe991def) => 000000000000001c, 8 (00000000 00000000)
- lwzux 16, (ffffffffffffffff) => 00000000ffffffff, 16 (00000000 00000000)
-
- ldx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
- ldx 8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000)
- ldx 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
-
- ldux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
- ldux 8, (0000001cbe991def) => 0000001cbe991def, 8 (00000000 00000000)
- ldux 16, (ffffffffffffffff) => ffffffffffffffff, 16 (00000000 00000000)
-
- lwax 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
- lwax 8, (0000001cbe991def) => 000000000000001c, 0 (00000000 00000000)
- lwax 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
-
- lwaux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
- lwaux 8, (0000001cbe991def) => 000000000000001c, 8 (00000000 00000000)
- lwaux 16, (ffffffffffffffff) => ffffffffffffffff, 16 (00000000 00000000)
-
-PPC integer store insns
- with one register + one 16 bits immediate args with flags update:
- stb 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
- stb 0000001cbe991def, 8 => ef00000000000000, 0 (00000000 00000000)
- stb ffffffffffffffff, 16 => ff00000000000000, 0 (00000000 00000000)
- stb 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
- stb 0000001cbe991def, -8 => ef00000000000000, 0 (00000000 00000000)
- stb ffffffffffffffff, 0 => ff00000000000000, 0 (00000000 00000000)
-
- stbu 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
- stbu 0000001cbe991def, 8 => ef00000000000000, 8 (00000000 00000000)
- stbu ffffffffffffffff, 16 => ff00000000000000, 16 (00000000 00000000)
- stbu 0000000000000000, -16 => 0000000000000000, -16 (00000000 00000000)
- stbu 0000001cbe991def, -8 => ef00000000000000, -8 (00000000 00000000)
- stbu ffffffffffffffff, 0 => ff00000000000000, 0 (00000000 00000000)
-
- sth 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
- sth 0000001cbe991def, 8 => 1def000000000000, 0 (00000000 00000000)
- sth ffffffffffffffff, 16 => ffff000000000000, 0 (00000000 00000000)
- sth 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
- sth 0000001cbe991def, -8 => 1def000000000000, 0 (00000000 00000000)
- sth ffffffffffffffff, 0 => ffff000000000000, 0 (00000000 00000000)
-
- sthu 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
- sthu 0000001cbe991def, 8 => 1def000000000000, 8 (00000000 00000000)
- sthu ffffffffffffffff, 16 => ffff000000000000, 16 (00000000 00000000)
- sthu 0000000000000000, -16 => 0000000000000000, -16 (00000000 00000000)
- sthu 0000001cbe991def, -8 => 1def000000000000, -8 (00000000 00000000)
- sthu ffffffffffffffff, 0 => ffff000000000000, 0 (00000000 00000000)
-
- stw 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
- stw 0000001cbe991def, 8 => be991def00000000, 0 (00000000 00000000)
- stw ffffffffffffffff, 16 => ffffffff00000000, 0 (00000000 00000000)
- stw 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
- stw 0000001cbe991def, -8 => be991def00000000, 0 (00000000 00000000)
- stw ffffffffffffffff, 0 => ffffffff00000000, 0 (00000000 00000000)
-
- stwu 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
- stwu 0000001cbe991def, 8 => be991def00000000, 8 (00000000 00000000)
- stwu ffffffffffffffff, 16 => ffffffff00000000, 16 (00000000 00000000)
- stwu 0000000000000000, -16 => 0000000000000000, -16 (00000000 00000000)
- stwu 0000001cbe991def, -8 => be991def00000000, -8 (00000000 00000000)
- stwu ffffffffffffffff, 0 => ffffffff00000000, 0 (00000000 00000000)
-
- std 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
- std 0000001cbe991def, 8 => 0000001cbe991def, 0 (00000000 00000000)
- std ffffffffffffffff, 16 => ffffffffffffffff, 0 (00000000 00000000)
- std 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
- std 0000001cbe991def, -8 => 0000001cbe991def, 0 (00000000 00000000)
- std ffffffffffffffff, 0 => ffffffffffffffff, 0 (00000000 00000000)
-
- stdu 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
- stdu 0000001cbe991def, 8 => 0000001cbe991def, 0 (00000000 00000000)
- stdu ffffffffffffffff, 16 => ffffffffffffffff, 0 (00000000 00000000)
- stdu 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
- stdu 0000001cbe991def, -8 => 0000001cbe991def, 0 (00000000 00000000)
- stdu ffffffffffffffff, 0 => ffffffffffffffff, 0 (00000000 00000000)
-
-PPC integer store insns with three register args:
- stbx 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
- stbx 0000001cbe991def, 8 => ef00000000000000, 0 (00000000 00000000)
- stbx ffffffffffffffff, 16 => ff00000000000000, 0 (00000000 00000000)
-
- stbux 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
- stbux 0000001cbe991def, 8 => ef00000000000000, 8 (00000000 00000000)
- stbux ffffffffffffffff, 16 => ff00000000000000, 16 (00000000 00000000)
-
- sthx 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
- sthx 0000001cbe991def, 8 => 1def000000000000, 0 (00000000 00000000)
- sthx ffffffffffffffff, 16 => ffff000000000000, 0 (00000000 00000000)
-
- sthux 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
- sthux 0000001cbe991def, 8 => 1def000000000000, 8 (00000000 00000000)
- sthux ffffffffffffffff, 16 => ffff000000000000, 16 (00000000 00000000)
-
- stwx 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
- stwx 0000001cbe991def, 8 => be991def00000000, 0 (00000000 00000000)
- stwx ffffffffffffffff, 16 => ffffffff00000000, 0 (00000000 00000000)
-
- stwux 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
- stwux 0000001cbe991def, 8 => be991def00000000, 8 (00000000 00000000)
- stwux ffffffffffffffff, 16 => ffffffff00000000, 16 (00000000 00000000)
-
- stdx 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
- stdx 0000001cbe991def, 8 => 0000001cbe991def, 0 (00000000 00000000)
- stdx ffffffffffffffff, 16 => ffffffffffffffff, 0 (00000000 00000000)
-
- stdux 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
- stdux 0000001cbe991def, 8 => 0000001cbe991def, 8 (00000000 00000000)
- stdux ffffffffffffffff, 16 => ffffffffffffffff, 16 (00000000 00000000)
-
PPC integer population count with one register args, no flags:
popcntb 0000000000000000 => 0000000000000000 (00000000 00000000)
popcntb 0000001cbe991def => 0000000306040407 (00000000 00000000)
popcntb ffffffffffffffff => 0808080808080808 (00000000 00000000)
-All done. Tested 210 different instructions
+All done. Tested 79 different instructions
diff --git a/none/tests/ppc64/jm-int.stdout.exp-LE-ISA3_0 b/none/tests/ppc64/jm-int.stdout.exp-LE-ISA3_0
new file mode 100644
index 0000000..2396d4d
--- /dev/null
+++ b/none/tests/ppc64/jm-int.stdout.exp-LE-ISA3_0
@@ -0,0 +1,796 @@
+PPC integer arith insns with two args:
+ add 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ add 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+ add 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+ add 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
+ add 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000)
+ add 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 00000000)
+ add ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ add ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 00000000)
+ add ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 00000000)
+
+ addo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ addo 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+ addo 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+ addo 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
+ addo 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00080000)
+ addo 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 00000000)
+ addo ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ addo ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 00000000)
+ addo ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 00000000)
+
+ addc 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ addc 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+ addc 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+ addc 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
+ addc 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000)
+ addc 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 20000000)
+ addc ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ addc ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
+ addc ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 20000000)
+
+ addco 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ addco 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+ addco 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+ addco 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
+ addco 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00080000)
+ addco 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 20000000)
+ addco ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ addco ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
+ addco ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 20000000)
+
+ divw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ divw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ divw 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
+ divw 0000001cbe991def, ffffffffffffffff => 000000004166e211 (00000000 00000000)
+ divw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ divw ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+ divwo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ divwo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ divwo 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
+ divwo 0000001cbe991def, ffffffffffffffff => 000000004166e211 (00000000 00000000)
+ divwo ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ divwo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+ divwu 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ divwu 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ divwu 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
+ divwu 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ divwu ffffffffffffffff, 0000001cbe991def => 0000000000000001 (00000000 00000000)
+ divwu ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+ divwuo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ divwuo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ divwuo 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
+ divwuo 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ divwuo ffffffffffffffff, 0000001cbe991def => 0000000000000001 (00000000 00000000)
+ divwuo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+ mulhw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ mulhw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ mulhw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ mulhw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ mulhw 0000001cbe991def, 0000001cbe991def => 0000000010b56825 (00000000 00000000)
+ mulhw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ mulhw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ mulhw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ mulhw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+ mulhwu 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ mulhwu 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ mulhwu 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ mulhwu 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ mulhwu 0000001cbe991def, 0000001cbe991def => 000000008de7a403 (00000000 00000000)
+ mulhwu 0000001cbe991def, ffffffffffffffff => 00000000be991dee (00000000 00000000)
+ mulhwu ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ mulhwu ffffffffffffffff, 0000001cbe991def => 00000000be991dee (00000000 00000000)
+ mulhwu ffffffffffffffff, ffffffffffffffff => 00000000fffffffe (00000000 00000000)
+
+ mullw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ mullw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ mullw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ mullw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ mullw 0000001cbe991def, 0000001cbe991def => 10b568258f2e0521 (00000000 00000000)
+ mullw 0000001cbe991def, ffffffffffffffff => 000000004166e211 (00000000 00000000)
+ mullw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ mullw ffffffffffffffff, 0000001cbe991def => 000000004166e211 (00000000 00000000)
+ mullw ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+ mullwo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ mullwo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ mullwo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ mullwo 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ mullwo 0000001cbe991def, 0000001cbe991def => 10b568258f2e0521 (00000000 c0080000)
+ mullwo 0000001cbe991def, ffffffffffffffff => 000000004166e211 (00000000 00000000)
+ mullwo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ mullwo ffffffffffffffff, 0000001cbe991def => 000000004166e211 (00000000 00000000)
+ mullwo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+ subf 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ subf 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+ subf 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+ subf 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000)
+ subf 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ subf 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 00000000)
+ subf ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000)
+ subf ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
+ subf ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+ subfo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ subfo 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+ subfo 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+ subfo 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000)
+ subfo 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ subfo 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 00000000)
+ subfo ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000)
+ subfo ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
+ subfo ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+ subfc 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 20000000)
+ subfc 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 20000000)
+ subfc 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
+ subfc 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000)
+ subfc 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 20000000)
+ subfc 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 20000000)
+ subfc ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000)
+ subfc ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
+ subfc ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 20000000)
+
+ subfco 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 20000000)
+ subfco 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 20000000)
+ subfco 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
+ subfco 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000)
+ subfco 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 20000000)
+ subfco 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 20000000)
+ subfco ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000)
+ subfco ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
+ subfco ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 20000000)
+
+ mulhd 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ mulhd 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ mulhd 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ mulhd 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ mulhd 0000001cbe991def, 0000001cbe991def => 000000000000033a (00000000 00000000)
+ mulhd 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+ mulhd ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ mulhd ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
+ mulhd ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+ mulhdu 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ mulhdu 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ mulhdu 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ mulhdu 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ mulhdu 0000001cbe991def, 0000001cbe991def => 000000000000033a (00000000 00000000)
+ mulhdu 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 00000000)
+ mulhdu ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ mulhdu ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 00000000)
+ mulhdu ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 00000000)
+
+ mulld 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ mulld 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ mulld 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ mulld 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ mulld 0000001cbe991def, 0000001cbe991def => 3f66304b8f2e0521 (00000000 00000000)
+ mulld 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (00000000 00000000)
+ mulld ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ mulld ffffffffffffffff, 0000001cbe991def => ffffffe34166e211 (00000000 00000000)
+ mulld ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+ mulldo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ mulldo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ mulldo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ mulldo 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ mulldo 0000001cbe991def, 0000001cbe991def => 3f66304b8f2e0521 (00000000 c0080000)
+ mulldo 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (00000000 00000000)
+ mulldo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ mulldo ffffffffffffffff, 0000001cbe991def => ffffffe34166e211 (00000000 00000000)
+ mulldo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+ divd 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ divd 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ divd 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ divd 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ divd 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
+ divd 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (00000000 00000000)
+ divd ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ divd ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ divd ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+ divdu 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ divdu 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ divdu 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ divdu 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ divdu 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
+ divdu 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ divdu ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ divdu ffffffffffffffff, 0000001cbe991def => 0000000008e7f283 (00000000 00000000)
+ divdu ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+ divdo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 c0080000)
+ divdo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ divdo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ divdo 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 c0080000)
+ divdo 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
+ divdo 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (00000000 00000000)
+ divdo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 c0080000)
+ divdo ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ divdo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+ divduo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 c0080000)
+ divduo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ divduo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ divduo 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 c0080000)
+ divduo 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
+ divduo 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ divduo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 c0080000)
+ divduo ffffffffffffffff, 0000001cbe991def => 0000000008e7f283 (00000000 00000000)
+ divduo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+PPC integer arith insns with two args with flags update:
+ add. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ add. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+ add. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+ add. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
+ add. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00000000)
+ add. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 00000000)
+ add. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ add. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 00000000)
+ add. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 00000000)
+
+ addo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ addo. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+ addo. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+ addo. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
+ addo. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00080000)
+ addo. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 00000000)
+ addo. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ addo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 00000000)
+ addo. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 00000000)
+
+ addc. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ addc. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+ addc. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+ addc. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
+ addc. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00000000)
+ addc. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 20000000)
+ addc. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ addc. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
+ addc. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 20000000)
+
+ addco. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ addco. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+ addco. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+ addco. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
+ addco. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00080000)
+ addco. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 20000000)
+ addco. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ addco. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
+ addco. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 20000000)
+
+ divw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ divw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ divw. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
+ divw. 0000001cbe991def, ffffffffffffffff => 000000004166e211 (40000000 00000000)
+ divw. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ divw. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
+
+ divwo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ divwo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ divwo. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
+ divwo. 0000001cbe991def, ffffffffffffffff => 000000004166e211 (40000000 00000000)
+ divwo. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ divwo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
+
+ divwu. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ divwu. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ divwu. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
+ divwu. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ divwu. ffffffffffffffff, 0000001cbe991def => 0000000000000001 (40000000 00000000)
+ divwu. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
+
+ divwuo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ divwuo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ divwuo. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
+ divwuo. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ divwuo. ffffffffffffffff, 0000001cbe991def => 0000000000000001 (40000000 00000000)
+ divwuo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
+
+ mulhw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ mulhw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ mulhw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ mulhw. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ mulhw. 0000001cbe991def, 0000001cbe991def => 0000000010b56825 (40000000 00000000)
+ mulhw. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ mulhw. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ mulhw. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ mulhw. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+ mulhwu. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ mulhwu. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ mulhwu. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ mulhwu. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ mulhwu. 0000001cbe991def, 0000001cbe991def => 000000008de7a403 (80000000 00000000)
+ mulhwu. 0000001cbe991def, ffffffffffffffff => 00000000be991dee (80000000 00000000)
+ mulhwu. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ mulhwu. ffffffffffffffff, 0000001cbe991def => 00000000be991dee (80000000 00000000)
+ mulhwu. ffffffffffffffff, ffffffffffffffff => 00000000fffffffe (80000000 00000000)
+
+ mullw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ mullw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ mullw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ mullw. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ mullw. 0000001cbe991def, 0000001cbe991def => 10b568258f2e0521 (40000000 00000000)
+ mullw. 0000001cbe991def, ffffffffffffffff => 000000004166e211 (40000000 00000000)
+ mullw. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ mullw. ffffffffffffffff, 0000001cbe991def => 000000004166e211 (40000000 00000000)
+ mullw. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
+
+ mullwo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ mullwo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ mullwo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ mullwo. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ mullwo. 0000001cbe991def, 0000001cbe991def => 10b568258f2e0521 (50000000 c0080000)
+ mullwo. 0000001cbe991def, ffffffffffffffff => 000000004166e211 (40000000 00000000)
+ mullwo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ mullwo. ffffffffffffffff, 0000001cbe991def => 000000004166e211 (40000000 00000000)
+ mullwo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
+
+ subf. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ subf. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+ subf. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+ subf. 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (80000000 00000000)
+ subf. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ subf. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 00000000)
+ subf. ffffffffffffffff, 0000000000000000 => 0000000000000001 (40000000 00000000)
+ subf. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
+ subf. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+ subfo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ subfo. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+ subfo. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+ subfo. 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (80000000 00000000)
+ subfo. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ subfo. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 00000000)
+ subfo. ffffffffffffffff, 0000000000000000 => 0000000000000001 (40000000 00000000)
+ subfo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
+ subfo. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+ subfc. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 20000000)
+ subfc. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 20000000)
+ subfc. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
+ subfc. 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (80000000 00000000)
+ subfc. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 20000000)
+ subfc. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 20000000)
+ subfc. ffffffffffffffff, 0000000000000000 => 0000000000000001 (40000000 00000000)
+ subfc. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
+ subfc. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 20000000)
+
+ subfco. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 20000000)
+ subfco. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 20000000)
+ subfco. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
+ subfco. 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (80000000 00000000)
+ subfco. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 20000000)
+ subfco. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 20000000)
+ subfco. ffffffffffffffff, 0000000000000000 => 0000000000000001 (40000000 00000000)
+ subfco. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
+ subfco. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 20000000)
+
+ mulhd. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ mulhd. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ mulhd. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ mulhd. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ mulhd. 0000001cbe991def, 0000001cbe991def => 000000000000033a (40000000 00000000)
+ mulhd. 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+ mulhd. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ mulhd. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
+ mulhd. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+ mulhdu. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ mulhdu. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ mulhdu. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ mulhdu. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ mulhdu. 0000001cbe991def, 0000001cbe991def => 000000000000033a (40000000 00000000)
+ mulhdu. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 00000000)
+ mulhdu. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ mulhdu. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 00000000)
+ mulhdu. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 00000000)
+
+ mulld. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ mulld. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ mulld. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ mulld. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ mulld. 0000001cbe991def, 0000001cbe991def => 3f66304b8f2e0521 (40000000 00000000)
+ mulld. 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (80000000 00000000)
+ mulld. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ mulld. ffffffffffffffff, 0000001cbe991def => ffffffe34166e211 (80000000 00000000)
+ mulld. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
+
+ mulldo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ mulldo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ mulldo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ mulldo. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ mulldo. 0000001cbe991def, 0000001cbe991def => 3f66304b8f2e0521 (50000000 c0080000)
+ mulldo. 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (80000000 00000000)
+ mulldo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ mulldo. ffffffffffffffff, 0000001cbe991def => ffffffe34166e211 (80000000 00000000)
+ mulldo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
+
+ divd. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ divd. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ divd. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ divd. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ divd. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
+ divd. 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (80000000 00000000)
+ divd. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ divd. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ divd. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
+
+ divdu. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ divdu. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ divdu. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ divdu. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ divdu. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
+ divdu. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ divdu. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ divdu. ffffffffffffffff, 0000001cbe991def => 0000000008e7f283 (40000000 00000000)
+ divdu. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
+
+ divdo. 0000000000000000, 0000000000000000 => 0000000000000000 (30000000 c0080000)
+ divdo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ divdo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ divdo. 0000001cbe991def, 0000000000000000 => 0000000000000000 (30000000 c0080000)
+ divdo. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
+ divdo. 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (80000000 00000000)
+ divdo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (30000000 c0080000)
+ divdo. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ divdo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
+
+ divduo. 0000000000000000, 0000000000000000 => 0000000000000000 (30000000 c0080000)
+ divduo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ divduo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ divduo. 0000001cbe991def, 0000000000000000 => 0000000000000000 (30000000 c0080000)
+ divduo. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
+ divduo. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ divduo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (30000000 c0080000)
+ divduo. ffffffffffffffff, 0000001cbe991def => 0000000008e7f283 (40000000 00000000)
+ divduo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
+
+PPC integer arith insns with two args and carry:
+ adde 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ adde 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+ adde 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+ adde 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
+ adde 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000)
+ adde 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 20000000)
+ adde ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ adde ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
+ adde ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 20000000)
+ adde 0000000000000000, 0000000000000000 => 0000000000000001 (00000000 00000000)
+ adde 0000000000000000, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
+ adde 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 20000000)
+ adde 0000001cbe991def, 0000000000000000 => 0000001cbe991df0 (00000000 00000000)
+ adde 0000001cbe991def, 0000001cbe991def => 000000397d323bdf (00000000 00000000)
+ adde 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 20000000)
+ adde ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 20000000)
+ adde ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 20000000)
+ adde ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
+
+ addeo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ addeo 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+ addeo 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+ addeo 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
+ addeo 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00080000)
+ addeo 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 20000000)
+ addeo ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ addeo ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
+ addeo ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 20000000)
+ addeo 0000000000000000, 0000000000000000 => 0000000000000001 (00000000 00000000)
+ addeo 0000000000000000, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
+ addeo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 20000000)
+ addeo 0000001cbe991def, 0000000000000000 => 0000001cbe991df0 (00000000 00000000)
+ addeo 0000001cbe991def, 0000001cbe991def => 000000397d323bdf (00000000 00080000)
+ addeo 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 20000000)
+ addeo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 20000000)
+ addeo ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 20000000)
+ addeo ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
+
+ subfe 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ subfe 0000000000000000, 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
+ subfe 0000000000000000, ffffffffffffffff => fffffffffffffffe (00000000 20000000)
+ subfe 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (00000000 00000000)
+ subfe 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
+ subfe 0000001cbe991def, ffffffffffffffff => ffffffe34166e20f (00000000 20000000)
+ subfe ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ subfe ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+ subfe ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+ subfe 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 20000000)
+ subfe 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 20000000)
+ subfe 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
+ subfe 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000)
+ subfe 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 20000000)
+ subfe 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 20000000)
+ subfe ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000)
+ subfe ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
+ subfe ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 20000000)
+
+ subfeo 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ subfeo 0000000000000000, 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
+ subfeo 0000000000000000, ffffffffffffffff => fffffffffffffffe (00000000 20000000)
+ subfeo 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (00000000 00000000)
+ subfeo 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
+ subfeo 0000001cbe991def, ffffffffffffffff => ffffffe34166e20f (00000000 20000000)
+ subfeo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ subfeo ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+ subfeo ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+ subfeo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 20000000)
+ subfeo 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 20000000)
+ subfeo 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
+ subfeo 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000)
+ subfeo 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 20000000)
+ subfeo 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 20000000)
+ subfeo ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000)
+ subfeo ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
+ subfeo ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 20000000)
+
+PPC integer arith insns with two args and carry with flags update:
+ adde. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ adde. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+ adde. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+ adde. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
+ adde. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00000000)
+ adde. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 20000000)
+ adde. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ adde. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
+ adde. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 20000000)
+ adde. 0000000000000000, 0000000000000000 => 0000000000000001 (40000000 00000000)
+ adde. 0000000000000000, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
+ adde. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 20000000)
+ adde. 0000001cbe991def, 0000000000000000 => 0000001cbe991df0 (40000000 00000000)
+ adde. 0000001cbe991def, 0000001cbe991def => 000000397d323bdf (40000000 00000000)
+ adde. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 20000000)
+ adde. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 20000000)
+ adde. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 20000000)
+ adde. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
+
+ addeo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ addeo. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+ addeo. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+ addeo. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
+ addeo. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00080000)
+ addeo. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 20000000)
+ addeo. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ addeo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
+ addeo. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 20000000)
+ addeo. 0000000000000000, 0000000000000000 => 0000000000000001 (40000000 00000000)
+ addeo. 0000000000000000, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
+ addeo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 20000000)
+ addeo. 0000001cbe991def, 0000000000000000 => 0000001cbe991df0 (40000000 00000000)
+ addeo. 0000001cbe991def, 0000001cbe991def => 000000397d323bdf (40000000 00080000)
+ addeo. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 20000000)
+ addeo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 20000000)
+ addeo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 20000000)
+ addeo. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
+
+ subfe. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ subfe. 0000000000000000, 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
+ subfe. 0000000000000000, ffffffffffffffff => fffffffffffffffe (80000000 20000000)
+ subfe. 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (80000000 00000000)
+ subfe. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
+ subfe. 0000001cbe991def, ffffffffffffffff => ffffffe34166e20f (80000000 20000000)
+ subfe. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ subfe. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+ subfe. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+ subfe. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 20000000)
+ subfe. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 20000000)
+ subfe. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
+ subfe. 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (80000000 00000000)
+ subfe. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 20000000)
+ subfe. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 20000000)
+ subfe. ffffffffffffffff, 0000000000000000 => 0000000000000001 (40000000 00000000)
+ subfe. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
+ subfe. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 20000000)
+
+ subfeo. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ subfeo. 0000000000000000, 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
+ subfeo. 0000000000000000, ffffffffffffffff => fffffffffffffffe (80000000 20000000)
+ subfeo. 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (80000000 00000000)
+ subfeo. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
+ subfeo. 0000001cbe991def, ffffffffffffffff => ffffffe34166e20f (80000000 20000000)
+ subfeo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ subfeo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+ subfeo. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+ subfeo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 20000000)
+ subfeo. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 20000000)
+ subfeo. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
+ subfeo. 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (80000000 00000000)
+ subfeo. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 20000000)
+ subfeo. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 20000000)
+ subfeo. ffffffffffffffff, 0000000000000000 => 0000000000000001 (40000000 00000000)
+ subfeo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
+ subfeo. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 20000000)
+
+PPC integer arith insns
+ with one register + one 16 bits immediate args:
+ addi 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
+ addi 0000000000000000, 000003e7 => 00000000000003e7 (00000000 00000000)
+ addi 0000000000000000, 0000ffff => ffffffffffffffff (00000000 00000000)
+ addi 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
+ addi 0000001cbe991def, 000003e7 => 0000001cbe9921d6 (00000000 00000000)
+ addi 0000001cbe991def, 0000ffff => 0000001cbe991dee (00000000 00000000)
+ addi ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
+ addi ffffffffffffffff, 000003e7 => 00000000000003e6 (00000000 00000000)
+ addi ffffffffffffffff, 0000ffff => fffffffffffffffe (00000000 00000000)
+
+ addic 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
+ addic 0000000000000000, 000003e7 => 00000000000003e7 (00000000 00000000)
+ addic 0000000000000000, 0000ffff => ffffffffffffffff (00000000 00000000)
+ addic 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
+ addic 0000001cbe991def, 000003e7 => 0000001cbe9921d6 (00000000 00000000)
+ addic 0000001cbe991def, 0000ffff => 0000001cbe991dee (00000000 20000000)
+ addic ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
+ addic ffffffffffffffff, 000003e7 => 00000000000003e6 (00000000 20000000)
+ addic ffffffffffffffff, 0000ffff => fffffffffffffffe (00000000 20000000)
+
+ addis 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
+ addis 0000000000000000, 000003e7 => 0000000003e70000 (00000000 00000000)
+ addis 0000000000000000, 0000ffff => ffffffffffff0000 (00000000 00000000)
+ addis 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
+ addis 0000001cbe991def, 000003e7 => 0000001cc2801def (00000000 00000000)
+ addis 0000001cbe991def, 0000ffff => 0000001cbe981def (00000000 00000000)
+ addis ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
+ addis ffffffffffffffff, 000003e7 => 0000000003e6ffff (00000000 00000000)
+ addis ffffffffffffffff, 0000ffff => fffffffffffeffff (00000000 00000000)
+
+ mulli 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
+ mulli 0000000000000000, 000003e7 => 0000000000000000 (00000000 00000000)
+ mulli 0000000000000000, 0000ffff => 0000000000000000 (00000000 00000000)
+ mulli 0000001cbe991def, 00000000 => 0000000000000000 (00000000 00000000)
+ mulli 0000001cbe991def, 000003e7 => 0000702bc783cfa9 (00000000 00000000)
+ mulli 0000001cbe991def, 0000ffff => ffffffe34166e211 (00000000 00000000)
+ mulli ffffffffffffffff, 00000000 => 0000000000000000 (00000000 00000000)
+ mulli ffffffffffffffff, 000003e7 => fffffffffffffc19 (00000000 00000000)
+ mulli ffffffffffffffff, 0000ffff => 0000000000000001 (00000000 00000000)
+
+ subfic 0000000000000000, 00000000 => 0000000000000000 (00000000 20000000)
+ subfic 0000000000000000, 000003e7 => 00000000000003e7 (00000000 20000000)
+ subfic 0000000000000000, 0000ffff => ffffffffffffffff (00000000 20000000)
+ subfic 0000001cbe991def, 00000000 => ffffffe34166e211 (00000000 00000000)
+ subfic 0000001cbe991def, 000003e7 => ffffffe34166e5f8 (00000000 00000000)
+ subfic 0000001cbe991def, 0000ffff => ffffffe34166e210 (00000000 20000000)
+ subfic ffffffffffffffff, 00000000 => 0000000000000001 (00000000 00000000)
+ subfic ffffffffffffffff, 000003e7 => 00000000000003e8 (00000000 00000000)
+ subfic ffffffffffffffff, 0000ffff => 0000000000000000 (00000000 20000000)
+
+PPC integer arith insns
+ with one register + one 16 bits immediate args with flags update:
+ addic. 0000000000000000, 00000000 => 0000000000000000 (20000000 00000000)
+ addic. 0000000000000000, 000003e7 => 00000000000003e7 (40000000 00000000)
+ addic. 0000000000000000, 0000ffff => ffffffffffffffff (80000000 00000000)
+ addic. 0000001cbe991def, 00000000 => 0000001cbe991def (40000000 00000000)
+ addic. 0000001cbe991def, 000003e7 => 0000001cbe9921d6 (40000000 00000000)
+ addic. 0000001cbe991def, 0000ffff => 0000001cbe991dee (40000000 20000000)
+ addic. ffffffffffffffff, 00000000 => ffffffffffffffff (80000000 00000000)
+ addic. ffffffffffffffff, 000003e7 => 00000000000003e6 (40000000 20000000)
+ addic. ffffffffffffffff, 0000ffff => fffffffffffffffe (80000000 20000000)
+
+PPC integer arith insns with one arg and carry:
+ addme 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ addme 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
+ addme ffffffffffffffff => fffffffffffffffe (00000000 20000000)
+ addme 0000000000000000 => 0000000000000000 (00000000 20000000)
+ addme 0000001cbe991def => 0000001cbe991def (00000000 20000000)
+ addme ffffffffffffffff => ffffffffffffffff (00000000 20000000)
+
+ addmeo 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ addmeo 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
+ addmeo ffffffffffffffff => fffffffffffffffe (00000000 20000000)
+ addmeo 0000000000000000 => 0000000000000000 (00000000 20000000)
+ addmeo 0000001cbe991def => 0000001cbe991def (00000000 20000000)
+ addmeo ffffffffffffffff => ffffffffffffffff (00000000 20000000)
+
+ addze 0000000000000000 => 0000000000000000 (00000000 00000000)
+ addze 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+ addze ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+ addze 0000000000000000 => 0000000000000001 (00000000 00000000)
+ addze 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
+ addze ffffffffffffffff => 0000000000000000 (00000000 20000000)
+
+ addzeo 0000000000000000 => 0000000000000000 (00000000 00000000)
+ addzeo 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+ addzeo ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+ addzeo 0000000000000000 => 0000000000000001 (00000000 00000000)
+ addzeo 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
+ addzeo ffffffffffffffff => 0000000000000000 (00000000 20000000)
+
+ subfme 0000000000000000 => fffffffffffffffe (00000000 20000000)
+ subfme 0000001cbe991def => ffffffe34166e20f (00000000 20000000)
+ subfme ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+ subfme 0000000000000000 => ffffffffffffffff (00000000 20000000)
+ subfme 0000001cbe991def => ffffffe34166e210 (00000000 20000000)
+ subfme ffffffffffffffff => 0000000000000000 (00000000 20000000)
+
+ subfmeo 0000000000000000 => fffffffffffffffe (00000000 20000000)
+ subfmeo 0000001cbe991def => ffffffe34166e20f (00000000 20000000)
+ subfmeo ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+ subfmeo 0000000000000000 => ffffffffffffffff (00000000 20000000)
+ subfmeo 0000001cbe991def => ffffffe34166e210 (00000000 20000000)
+ subfmeo ffffffffffffffff => 0000000000000000 (00000000 20000000)
+
+ subfze 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ subfze 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
+ subfze ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ subfze 0000000000000000 => 0000000000000000 (00000000 20000000)
+ subfze 0000001cbe991def => ffffffe34166e211 (00000000 00000000)
+ subfze ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+ subfzeo 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ subfzeo 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
+ subfzeo ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ subfzeo 0000000000000000 => 0000000000000000 (00000000 20000000)
+ subfzeo 0000001cbe991def => ffffffe34166e211 (00000000 00000000)
+ subfzeo ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+PPC integer arith insns with one arg and carry with flags update:
+ addme. 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ addme. 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
+ addme. ffffffffffffffff => fffffffffffffffe (80000000 20000000)
+ addme. 0000000000000000 => 0000000000000000 (20000000 20000000)
+ addme. 0000001cbe991def => 0000001cbe991def (40000000 20000000)
+ addme. ffffffffffffffff => ffffffffffffffff (80000000 20000000)
+
+ addmeo. 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ addmeo. 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
+ addmeo. ffffffffffffffff => fffffffffffffffe (80000000 20000000)
+ addmeo. 0000000000000000 => 0000000000000000 (20000000 20000000)
+ addmeo. 0000001cbe991def => 0000001cbe991def (40000000 20000000)
+ addmeo. ffffffffffffffff => ffffffffffffffff (80000000 20000000)
+
+ addze. 0000000000000000 => 0000000000000000 (20000000 00000000)
+ addze. 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+ addze. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+ addze. 0000000000000000 => 0000000000000001 (40000000 00000000)
+ addze. 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
+ addze. ffffffffffffffff => 0000000000000000 (20000000 20000000)
+
+ addzeo. 0000000000000000 => 0000000000000000 (20000000 00000000)
+ addzeo. 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+ addzeo. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+ addzeo. 0000000000000000 => 0000000000000001 (40000000 00000000)
+ addzeo. 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
+ addzeo. ffffffffffffffff => 0000000000000000 (20000000 20000000)
+
+ subfme. 0000000000000000 => fffffffffffffffe (80000000 20000000)
+ subfme. 0000001cbe991def => ffffffe34166e20f (80000000 20000000)
+ subfme. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+ subfme. 0000000000000000 => ffffffffffffffff (80000000 20000000)
+ subfme. 0000001cbe991def => ffffffe34166e210 (80000000 20000000)
+ subfme. ffffffffffffffff => 0000000000000000 (20000000 20000000)
+
+ subfmeo. 0000000000000000 => fffffffffffffffe (80000000 20000000)
+ subfmeo. 0000001cbe991def => ffffffe34166e20f (80000000 20000000)
+ subfmeo. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+ subfmeo. 0000000000000000 => ffffffffffffffff (80000000 20000000)
+ subfmeo. 0000001cbe991def => ffffffe34166e210 (80000000 20000000)
+ subfmeo. ffffffffffffffff => 0000000000000000 (20000000 20000000)
+
+ subfze. 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ subfze. 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
+ subfze. ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ subfze. 0000000000000000 => 0000000000000000 (20000000 20000000)
+ subfze. 0000001cbe991def => ffffffe34166e211 (80000000 00000000)
+ subfze. ffffffffffffffff => 0000000000000001 (40000000 00000000)
+
+ subfzeo. 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ subfzeo. 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
+ subfzeo. ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ subfzeo. 0000000000000000 => 0000000000000000 (20000000 20000000)
+ subfzeo. 0000001cbe991def => ffffffe34166e211 (80000000 00000000)
+ subfzeo. ffffffffffffffff => 0000000000000001 (40000000 00000000)
+
+PPC integer population count with one register args, no flags:
+ popcntb 0000000000000000 => 0000000000000000 (00000000 00000000)
+ popcntb 0000001cbe991def => 0000000306040407 (00000000 00000000)
+ popcntb ffffffffffffffff => 0808080808080808 (00000000 00000000)
+
+All done. Tested 79 different instructions
diff --git a/none/tests/ppc64/jm-int_other.stderr.exp b/none/tests/ppc64/jm-int_other.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/none/tests/ppc64/jm-int_other.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/none/tests/ppc64/jm-int_other.stdout.exp b/none/tests/ppc64/jm-int_other.stdout.exp
new file mode 100644
index 0000000..6deb0d0
--- /dev/null
+++ b/none/tests/ppc64/jm-int_other.stdout.exp
@@ -0,0 +1,3978 @@
+PPC integer logical insns with two args:
+ and 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ and 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ and 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ and 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ and 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+ and 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 00000000)
+ and ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ and ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+ and ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+
+ andc 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ andc 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ andc 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ andc 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
+ andc 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ andc 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ andc ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ andc ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
+ andc ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+ eqv 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ eqv 0000000000000000, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
+ eqv 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ eqv 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (00000000 00000000)
+ eqv 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
+ eqv 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 00000000)
+ eqv ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ eqv ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+ eqv ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+
+ nand 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ nand 0000000000000000, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
+ nand 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+ nand 0000001cbe991def, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ nand 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
+ nand 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 00000000)
+ nand ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ nand ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
+ nand ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+ nor 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ nor 0000000000000000, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
+ nor 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ nor 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (00000000 00000000)
+ nor 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
+ nor 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ nor ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ nor ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ nor ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+ or 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ or 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+ or 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+ or 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
+ or 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+ or 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+ or ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ or ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
+ or ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+
+ orc 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ orc 0000000000000000, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
+ orc 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ orc 0000001cbe991def, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ orc 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
+ orc 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 00000000)
+ orc ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ orc ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
+ orc ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+
+ xor 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ xor 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+ xor 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+ xor 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
+ xor 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ xor 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 00000000)
+ xor ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ xor ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
+ xor ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+ slw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ slw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ slw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ slw 0000001cbe991def, 0000000000000000 => 00000000be991def (00000000 00000000)
+ slw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ slw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ slw ffffffffffffffff, 0000000000000000 => 00000000ffffffff (00000000 00000000)
+ slw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ slw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+ sraw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ sraw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ sraw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ sraw 0000001cbe991def, 0000000000000000 => ffffffffbe991def (00000000 00000000)
+ sraw 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 20000000)
+ sraw 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
+ sraw ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ sraw ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 20000000)
+ sraw ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
+
+ srw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ srw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ srw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ srw 0000001cbe991def, 0000000000000000 => 00000000be991def (00000000 00000000)
+ srw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ srw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ srw ffffffffffffffff, 0000000000000000 => 00000000ffffffff (00000000 00000000)
+ srw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ srw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+ sld 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ sld 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ sld 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ sld 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
+ sld 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ sld 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ sld ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ sld ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ sld ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+ srad 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ srad 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ srad 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ srad 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
+ srad 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ srad 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ srad ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ srad ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 20000000)
+ srad ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
+
+ srd 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ srd 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ srd 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ srd 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
+ srd 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ srd 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ srd ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ srd ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ srd ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+PPC integer logical insns with two args with flags update:
+ and. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ and. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ and. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ and. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ and. 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+ and. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 00000000)
+ and. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ and. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+ and. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+
+ andc. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ andc. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ andc. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ andc. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
+ andc. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ andc. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ andc. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ andc. ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
+ andc. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+ eqv. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ eqv. 0000000000000000, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
+ eqv. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ eqv. 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (80000000 00000000)
+ eqv. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
+ eqv. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 00000000)
+ eqv. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ eqv. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+ eqv. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+
+ nand. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ nand. 0000000000000000, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
+ nand. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+ nand. 0000001cbe991def, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ nand. 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
+ nand. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 00000000)
+ nand. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ nand. ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
+ nand. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+ nor. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ nor. 0000000000000000, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
+ nor. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ nor. 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (80000000 00000000)
+ nor. 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
+ nor. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ nor. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ nor. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ nor. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+ or. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ or. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+ or. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+ or. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
+ or. 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+ or. 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+ or. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ or. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
+ or. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+
+ orc. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ orc. 0000000000000000, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
+ orc. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ orc. 0000001cbe991def, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ orc. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
+ orc. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 00000000)
+ orc. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ orc. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
+ orc. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+
+ xor. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ xor. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+ xor. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+ xor. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
+ xor. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ xor. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 00000000)
+ xor. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ xor. ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
+ xor. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+ slw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ slw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ slw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ slw. 0000001cbe991def, 0000000000000000 => 00000000be991def (40000000 00000000)
+ slw. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ slw. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ slw. ffffffffffffffff, 0000000000000000 => 00000000ffffffff (40000000 00000000)
+ slw. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ slw. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+ sraw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ sraw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ sraw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ sraw. 0000001cbe991def, 0000000000000000 => ffffffffbe991def (80000000 00000000)
+ sraw. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 20000000)
+ sraw. 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
+ sraw. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ sraw. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 20000000)
+ sraw. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
+
+ srw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ srw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ srw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ srw. 0000001cbe991def, 0000000000000000 => 00000000be991def (40000000 00000000)
+ srw. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ srw. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ srw. ffffffffffffffff, 0000000000000000 => 00000000ffffffff (40000000 00000000)
+ srw. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ srw. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+ sld. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ sld. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ sld. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ sld. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
+ sld. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ sld. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ sld. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ sld. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ sld. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+ srad. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ srad. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ srad. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ srad. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
+ srad. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ srad. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ srad. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ srad. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 20000000)
+ srad. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
+
+ srd. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ srd. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ srd. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ srd. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
+ srd. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ srd. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ srd. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ srd. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ srd. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+PPC integer compare insns (two args):
+ cmpw 0000000000000000, 0000000000000000 => 0000000000000000 (00200000 00000000)
+ cmpw 0000000000000000, 0000001cbe991def => 0000000000000000 (00400000 00000000)
+ cmpw 0000000000000000, ffffffffffffffff => 0000000000000000 (00400000 00000000)
+ cmpw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00800000 00000000)
+ cmpw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00200000 00000000)
+ cmpw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00800000 00000000)
+ cmpw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00800000 00000000)
+ cmpw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00400000 00000000)
+ cmpw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00200000 00000000)
+
+ cmplw 0000000000000000, 0000000000000000 => 0000000000000000 (00200000 00000000)
+ cmplw 0000000000000000, 0000001cbe991def => 0000000000000000 (00800000 00000000)
+ cmplw 0000000000000000, ffffffffffffffff => 0000000000000000 (00800000 00000000)
+ cmplw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00400000 00000000)
+ cmplw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00200000 00000000)
+ cmplw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00800000 00000000)
+ cmplw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00400000 00000000)
+ cmplw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00400000 00000000)
+ cmplw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00200000 00000000)
+
+ cmpd 0000000000000000, 0000000000000000 => 0000000000000000 (00200000 00000000)
+ cmpd 0000000000000000, 0000001cbe991def => 0000000000000000 (00800000 00000000)
+ cmpd 0000000000000000, ffffffffffffffff => 0000000000000000 (00400000 00000000)
+ cmpd 0000001cbe991def, 0000000000000000 => 0000000000000000 (00400000 00000000)
+ cmpd 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00200000 00000000)
+ cmpd 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00400000 00000000)
+ cmpd ffffffffffffffff, 0000000000000000 => 0000000000000000 (00800000 00000000)
+ cmpd ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00800000 00000000)
+ cmpd ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00200000 00000000)
+
+ cmpld 0000000000000000, 0000000000000000 => 0000000000000000 (00200000 00000000)
+ cmpld 0000000000000000, 0000001cbe991def => 0000000000000000 (00800000 00000000)
+ cmpld 0000000000000000, ffffffffffffffff => 0000000000000000 (00800000 00000000)
+ cmpld 0000001cbe991def, 0000000000000000 => 0000000000000000 (00400000 00000000)
+ cmpld 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00200000 00000000)
+ cmpld 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00800000 00000000)
+ cmpld ffffffffffffffff, 0000000000000000 => 0000000000000000 (00400000 00000000)
+ cmpld ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00400000 00000000)
+ cmpld ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00200000 00000000)
+
+PPC integer compare with immediate insns (two args):
+ cmpwi 0000000000000000, 00000000 => 0000000000000000 (00200000 00000000)
+ cmpwi 0000000000000000, 000003e7 => 0000000000000000 (00800000 00000000)
+ cmpwi 0000000000000000, 0000ffff => 0000000000000000 (00400000 00000000)
+ cmpwi 0000001cbe991def, 00000000 => 0000000000000000 (00800000 00000000)
+ cmpwi 0000001cbe991def, 000003e7 => 0000000000000000 (00800000 00000000)
+ cmpwi 0000001cbe991def, 0000ffff => 0000000000000000 (00800000 00000000)
+ cmpwi ffffffffffffffff, 00000000 => 0000000000000000 (00800000 00000000)
+ cmpwi ffffffffffffffff, 000003e7 => 0000000000000000 (00800000 00000000)
+ cmpwi ffffffffffffffff, 0000ffff => 0000000000000000 (00200000 00000000)
+
+ cmplwi 0000000000000000, 00000000 => 0000000000000000 (00200000 00000000)
+ cmplwi 0000000000000000, 000003e7 => 0000000000000000 (00800000 00000000)
+ cmplwi 0000000000000000, 0000ffff => 0000000000000000 (00800000 00000000)
+ cmplwi 0000001cbe991def, 00000000 => 0000000000000000 (00400000 00000000)
+ cmplwi 0000001cbe991def, 000003e7 => 0000000000000000 (00400000 00000000)
+ cmplwi 0000001cbe991def, 0000ffff => 0000000000000000 (00400000 00000000)
+ cmplwi ffffffffffffffff, 00000000 => 0000000000000000 (00400000 00000000)
+ cmplwi ffffffffffffffff, 000003e7 => 0000000000000000 (00400000 00000000)
+ cmplwi ffffffffffffffff, 0000ffff => 0000000000000000 (00400000 00000000)
+
+ cmpdi 0000000000000000, 00000000 => 0000000000000000 (00200000 00000000)
+ cmpdi 0000000000000000, 000003e7 => 0000000000000000 (00800000 00000000)
+ cmpdi 0000000000000000, 0000ffff => 0000000000000000 (00400000 00000000)
+ cmpdi 0000001cbe991def, 00000000 => 0000000000000000 (00400000 00000000)
+ cmpdi 0000001cbe991def, 000003e7 => 0000000000000000 (00400000 00000000)
+ cmpdi 0000001cbe991def, 0000ffff => 0000000000000000 (00400000 00000000)
+ cmpdi ffffffffffffffff, 00000000 => 0000000000000000 (00800000 00000000)
+ cmpdi ffffffffffffffff, 000003e7 => 0000000000000000 (00800000 00000000)
+ cmpdi ffffffffffffffff, 0000ffff => 0000000000000000 (00200000 00000000)
+
+ cmpldi 0000000000000000, 00000000 => 0000000000000000 (00200000 00000000)
+ cmpldi 0000000000000000, 000003e7 => 0000000000000000 (00800000 00000000)
+ cmpldi 0000000000000000, 0000ffff => 0000000000000000 (00800000 00000000)
+ cmpldi 0000001cbe991def, 00000000 => 0000000000000000 (00400000 00000000)
+ cmpldi 0000001cbe991def, 000003e7 => 0000000000000000 (00400000 00000000)
+ cmpldi 0000001cbe991def, 0000ffff => 0000000000000000 (00400000 00000000)
+ cmpldi ffffffffffffffff, 00000000 => 0000000000000000 (00400000 00000000)
+ cmpldi ffffffffffffffff, 000003e7 => 0000000000000000 (00400000 00000000)
+ cmpldi ffffffffffffffff, 0000ffff => 0000000000000000 (00400000 00000000)
+
+PPC integer logical insns
+ with one register + one 16 bits immediate args:
+ ori 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
+ ori 0000000000000000, 000003e7 => 00000000000003e7 (00000000 00000000)
+ ori 0000000000000000, 0000ffff => 000000000000ffff (00000000 00000000)
+ ori 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
+ ori 0000001cbe991def, 000003e7 => 0000001cbe991fef (00000000 00000000)
+ ori 0000001cbe991def, 0000ffff => 0000001cbe99ffff (00000000 00000000)
+ ori ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
+ ori ffffffffffffffff, 000003e7 => ffffffffffffffff (00000000 00000000)
+ ori ffffffffffffffff, 0000ffff => ffffffffffffffff (00000000 00000000)
+
+ oris 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
+ oris 0000000000000000, 000003e7 => 0000000003e70000 (00000000 00000000)
+ oris 0000000000000000, 0000ffff => 00000000ffff0000 (00000000 00000000)
+ oris 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
+ oris 0000001cbe991def, 000003e7 => 0000001cbfff1def (00000000 00000000)
+ oris 0000001cbe991def, 0000ffff => 0000001cffff1def (00000000 00000000)
+ oris ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
+ oris ffffffffffffffff, 000003e7 => ffffffffffffffff (00000000 00000000)
+ oris ffffffffffffffff, 0000ffff => ffffffffffffffff (00000000 00000000)
+
+ xori 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
+ xori 0000000000000000, 000003e7 => 00000000000003e7 (00000000 00000000)
+ xori 0000000000000000, 0000ffff => 000000000000ffff (00000000 00000000)
+ xori 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
+ xori 0000001cbe991def, 000003e7 => 0000001cbe991e08 (00000000 00000000)
+ xori 0000001cbe991def, 0000ffff => 0000001cbe99e210 (00000000 00000000)
+ xori ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
+ xori ffffffffffffffff, 000003e7 => fffffffffffffc18 (00000000 00000000)
+ xori ffffffffffffffff, 0000ffff => ffffffffffff0000 (00000000 00000000)
+
+ xoris 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
+ xoris 0000000000000000, 000003e7 => 0000000003e70000 (00000000 00000000)
+ xoris 0000000000000000, 0000ffff => 00000000ffff0000 (00000000 00000000)
+ xoris 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
+ xoris 0000001cbe991def, 000003e7 => 0000001cbd7e1def (00000000 00000000)
+ xoris 0000001cbe991def, 0000ffff => 0000001c41661def (00000000 00000000)
+ xoris ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
+ xoris ffffffffffffffff, 000003e7 => fffffffffc18ffff (00000000 00000000)
+ xoris ffffffffffffffff, 0000ffff => ffffffff0000ffff (00000000 00000000)
+
+PPC integer logical insns
+ with one register + one 16 bits immediate args with flags update:
+ andi. 0000000000000000, 00000000 => 0000000000000000 (20000000 00000000)
+ andi. 0000000000000000, 000003e7 => 0000000000000000 (20000000 00000000)
+ andi. 0000000000000000, 0000ffff => 0000000000000000 (20000000 00000000)
+ andi. 0000001cbe991def, 00000000 => 0000000000000000 (20000000 00000000)
+ andi. 0000001cbe991def, 000003e7 => 00000000000001e7 (40000000 00000000)
+ andi. 0000001cbe991def, 0000ffff => 0000000000001def (40000000 00000000)
+ andi. ffffffffffffffff, 00000000 => 0000000000000000 (20000000 00000000)
+ andi. ffffffffffffffff, 000003e7 => 00000000000003e7 (40000000 00000000)
+ andi. ffffffffffffffff, 0000ffff => 000000000000ffff (40000000 00000000)
+
+ andis. 0000000000000000, 00000000 => 0000000000000000 (20000000 00000000)
+ andis. 0000000000000000, 000003e7 => 0000000000000000 (20000000 00000000)
+ andis. 0000000000000000, 0000ffff => 0000000000000000 (20000000 00000000)
+ andis. 0000001cbe991def, 00000000 => 0000000000000000 (20000000 00000000)
+ andis. 0000001cbe991def, 000003e7 => 0000000002810000 (40000000 00000000)
+ andis. 0000001cbe991def, 0000ffff => 00000000be990000 (40000000 00000000)
+ andis. ffffffffffffffff, 00000000 => 0000000000000000 (20000000 00000000)
+ andis. ffffffffffffffff, 000003e7 => 0000000003e70000 (40000000 00000000)
+ andis. ffffffffffffffff, 0000ffff => 00000000ffff0000 (40000000 00000000)
+
+PPC condition register logical insns - two operands:
+ crand 0000000000000000, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
+ crand 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
+ crand 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
+ crand 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
+ crand 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
+ crand 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
+ crand ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
+ crand ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
+ crand ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
+
+ crandc 0000000000000000, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
+ crandc 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
+ crandc 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
+ crandc 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
+ crandc 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
+ crandc 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
+ crandc ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
+ crandc ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
+ crandc ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
+
+ creqv 0000000000000000, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
+ creqv 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
+ creqv 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
+ creqv 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
+ creqv 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
+ creqv 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
+ creqv ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
+ creqv ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
+ creqv ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
+
+ crnand 0000000000000000, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
+ crnand 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
+ crnand 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
+ crnand 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
+ crnand 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
+ crnand 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
+ crnand ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
+ crnand ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
+ crnand ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
+
+ crnor 0000000000000000, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
+ crnor 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
+ crnor 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
+ crnor 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
+ crnor 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
+ crnor 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
+ crnor ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
+ crnor ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
+ crnor ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
+
+ cror 0000000000000000, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
+ cror 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
+ cror 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
+ cror 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
+ cror 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
+ cror 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
+ cror ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
+ cror ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
+ cror ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
+
+ crorc 0000000000000000, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
+ crorc 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
+ crorc 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
+ crorc 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
+ crorc 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
+ crorc 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
+ crorc ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
+ crorc ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
+ crorc ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
+
+ crxor 0000000000000000, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
+ crxor 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
+ crxor 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
+ crxor 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
+ crxor 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
+ crxor 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
+ crxor ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
+ crxor ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
+ crxor ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
+
+PPC integer logical insns with one arg:
+ cntlzw 0000000000000000 => 0000000000000020 (00000000 00000000)
+ cntlzw 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ cntlzw ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+ extsb 0000000000000000 => 0000000000000000 (00000000 00000000)
+ extsb 0000001cbe991def => ffffffffffffffef (00000000 00000000)
+ extsb ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+
+ extsh 0000000000000000 => 0000000000000000 (00000000 00000000)
+ extsh 0000001cbe991def => 0000000000001def (00000000 00000000)
+ extsh ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+
+ neg 0000000000000000 => 0000000000000000 (00000000 00000000)
+ neg 0000001cbe991def => ffffffe34166e211 (00000000 00000000)
+ neg ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+ nego 0000000000000000 => 0000000000000000 (00000000 00000000)
+ nego 0000001cbe991def => ffffffe34166e211 (00000000 00000000)
+ nego ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+ cntlzd 0000000000000000 => 0000000000000040 (00000000 00000000)
+ cntlzd 0000001cbe991def => 000000000000001b (00000000 00000000)
+ cntlzd ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+ extsw 0000000000000000 => 0000000000000000 (00000000 00000000)
+ extsw 0000001cbe991def => ffffffffbe991def (00000000 00000000)
+ extsw ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+
+PPC integer logical insns with one arg with flags update:
+ cntlzw. 0000000000000000 => 0000000000000020 (40000000 00000000)
+ cntlzw. 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ cntlzw. ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+ extsb. 0000000000000000 => 0000000000000000 (20000000 00000000)
+ extsb. 0000001cbe991def => ffffffffffffffef (80000000 00000000)
+ extsb. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+
+ extsh. 0000000000000000 => 0000000000000000 (20000000 00000000)
+ extsh. 0000001cbe991def => 0000000000001def (40000000 00000000)
+ extsh. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+
+ neg. 0000000000000000 => 0000000000000000 (20000000 00000000)
+ neg. 0000001cbe991def => ffffffe34166e211 (80000000 00000000)
+ neg. ffffffffffffffff => 0000000000000001 (40000000 00000000)
+
+ nego. 0000000000000000 => 0000000000000000 (20000000 00000000)
+ nego. 0000001cbe991def => ffffffe34166e211 (80000000 00000000)
+ nego. ffffffffffffffff => 0000000000000001 (40000000 00000000)
+
+ cntlzd. 0000000000000000 => 0000000000000040 (40000000 00000000)
+ cntlzd. 0000001cbe991def => 000000000000001b (40000000 00000000)
+ cntlzd. ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+ extsw. 0000000000000000 => 0000000000000000 (20000000 00000000)
+ extsw. 0000001cbe991def => ffffffffbe991def (80000000 00000000)
+ extsw. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+
+PPC logical insns with special forms:
+ rlwimi 0000000000000000, 0, 0, 0 => 0000000000000000 (00000000 00000000)
+ rlwimi 0000000000000000, 0, 0, 31 => 0000000000000000 (00000000 00000000)
+ rlwimi 0000000000000000, 0, 31, 0 => 0000000000000000 (00000000 00000000)
+ rlwimi 0000000000000000, 0, 31, 31 => 0000000000000000 (00000000 00000000)
+ rlwimi 0000000000000000, 31, 0, 0 => 0000000000000000 (00000000 00000000)
+ rlwimi 0000000000000000, 31, 0, 31 => 0000000000000000 (00000000 00000000)
+ rlwimi 0000000000000000, 31, 31, 0 => 0000000000000000 (00000000 00000000)
+ rlwimi 0000000000000000, 31, 31, 31 => 0000000000000000 (00000000 00000000)
+ rlwimi 0000001cbe991def, 0, 0, 0 => 0000000080000000 (00000000 00000000)
+ rlwimi 0000001cbe991def, 0, 0, 31 => 00000000be991def (00000000 00000000)
+ rlwimi 0000001cbe991def, 0, 31, 0 => be991defbe991def (00000000 00000000)
+ rlwimi 0000001cbe991def, 0, 31, 31 => be991defbe991def (00000000 00000000)
+ rlwimi 0000001cbe991def, 31, 0, 0 => be991defbe991def (00000000 00000000)
+ rlwimi 0000001cbe991def, 31, 0, 31 => be991defdf4c8ef7 (00000000 00000000)
+ rlwimi 0000001cbe991def, 31, 31, 0 => df4c8ef7df4c8ef7 (00000000 00000000)
+ rlwimi 0000001cbe991def, 31, 31, 31 => df4c8ef7df4c8ef7 (00000000 00000000)
+ rlwimi ffffffffffffffff, 0, 0, 0 => df4c8ef7df4c8ef7 (00000000 00000000)
+ rlwimi ffffffffffffffff, 0, 0, 31 => df4c8ef7ffffffff (00000000 00000000)
+ rlwimi ffffffffffffffff, 0, 31, 0 => ffffffffffffffff (00000000 00000000)
+ rlwimi ffffffffffffffff, 0, 31, 31 => ffffffffffffffff (00000000 00000000)
+ rlwimi ffffffffffffffff, 31, 0, 0 => ffffffffffffffff (00000000 00000000)
+ rlwimi ffffffffffffffff, 31, 0, 31 => ffffffffffffffff (00000000 00000000)
+ rlwimi ffffffffffffffff, 31, 31, 0 => ffffffffffffffff (00000000 00000000)
+ rlwimi ffffffffffffffff, 31, 31, 31 => ffffffffffffffff (00000000 00000000)
+
+ rlwinm 0000000000000000, 0, 0, 0 => 0000000000000000 (00000000 00000000)
+ rlwinm 0000000000000000, 0, 0, 31 => 0000000000000000 (00000000 00000000)
+ rlwinm 0000000000000000, 0, 31, 0 => 0000000000000000 (00000000 00000000)
+ rlwinm 0000000000000000, 0, 31, 31 => 0000000000000000 (00000000 00000000)
+ rlwinm 0000000000000000, 31, 0, 0 => 0000000000000000 (00000000 00000000)
+ rlwinm 0000000000000000, 31, 0, 31 => 0000000000000000 (00000000 00000000)
+ rlwinm 0000000000000000, 31, 31, 0 => 0000000000000000 (00000000 00000000)
+ rlwinm 0000000000000000, 31, 31, 31 => 0000000000000000 (00000000 00000000)
+ rlwinm 0000001cbe991def, 0, 0, 0 => 0000000080000000 (00000000 00000000)
+ rlwinm 0000001cbe991def, 0, 0, 31 => 00000000be991def (00000000 00000000)
+ rlwinm 0000001cbe991def, 0, 31, 0 => be991def80000001 (00000000 00000000)
+ rlwinm 0000001cbe991def, 0, 31, 31 => 0000000000000001 (00000000 00000000)
+ rlwinm 0000001cbe991def, 31, 0, 0 => 0000000080000000 (00000000 00000000)
+ rlwinm 0000001cbe991def, 31, 0, 31 => 00000000df4c8ef7 (00000000 00000000)
+ rlwinm 0000001cbe991def, 31, 31, 0 => df4c8ef780000001 (00000000 00000000)
+ rlwinm 0000001cbe991def, 31, 31, 31 => 0000000000000001 (00000000 00000000)
+ rlwinm ffffffffffffffff, 0, 0, 0 => 0000000080000000 (00000000 00000000)
+ rlwinm ffffffffffffffff, 0, 0, 31 => 00000000ffffffff (00000000 00000000)
+ rlwinm ffffffffffffffff, 0, 31, 0 => ffffffff80000001 (00000000 00000000)
+ rlwinm ffffffffffffffff, 0, 31, 31 => 0000000000000001 (00000000 00000000)
+ rlwinm ffffffffffffffff, 31, 0, 0 => 0000000080000000 (00000000 00000000)
+ rlwinm ffffffffffffffff, 31, 0, 31 => 00000000ffffffff (00000000 00000000)
+ rlwinm ffffffffffffffff, 31, 31, 0 => ffffffff80000001 (00000000 00000000)
+ rlwinm ffffffffffffffff, 31, 31, 31 => 0000000000000001 (00000000 00000000)
+
+ rlwnm 0000000000000000, 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000000000000000, 0000000000000000, 0, 31 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000000000000000, 0000000000000000, 31, 0 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000000000000000, 0000000000000000, 31, 31 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000000000000000, 0000001cbe991def, 0, 0 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000000000000000, 0000001cbe991def, 0, 31 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000000000000000, 0000001cbe991def, 31, 0 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000000000000000, 0000001cbe991def, 31, 31 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000000000000000, ffffffffffffffff, 0, 0 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000000000000000, ffffffffffffffff, 0, 31 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000000000000000, ffffffffffffffff, 31, 0 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000000000000000, ffffffffffffffff, 31, 31 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000001cbe991def, 0000000000000000, 0, 0 => 0000000080000000 (00000000 00000000)
+ rlwnm 0000001cbe991def, 0000000000000000, 0, 31 => 00000000be991def (00000000 00000000)
+ rlwnm 0000001cbe991def, 0000000000000000, 31, 0 => be991def80000001 (00000000 00000000)
+ rlwnm 0000001cbe991def, 0000000000000000, 31, 31 => 0000000000000001 (00000000 00000000)
+ rlwnm 0000001cbe991def, 0000001cbe991def, 0, 0 => 0000000080000000 (00000000 00000000)
+ rlwnm 0000001cbe991def, 0000001cbe991def, 0, 31 => 000000008ef7df4c (00000000 00000000)
+ rlwnm 0000001cbe991def, 0000001cbe991def, 31, 0 => 8ef7df4c80000000 (00000000 00000000)
+ rlwnm 0000001cbe991def, 0000001cbe991def, 31, 31 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000001cbe991def, ffffffffffffffff, 0, 0 => 0000000080000000 (00000000 00000000)
+ rlwnm 0000001cbe991def, ffffffffffffffff, 0, 31 => 00000000df4c8ef7 (00000000 00000000)
+ rlwnm 0000001cbe991def, ffffffffffffffff, 31, 0 => df4c8ef780000001 (00000000 00000000)
+ rlwnm 0000001cbe991def, ffffffffffffffff, 31, 31 => 0000000000000001 (00000000 00000000)
+ rlwnm ffffffffffffffff, 0000000000000000, 0, 0 => 0000000080000000 (00000000 00000000)
+ rlwnm ffffffffffffffff, 0000000000000000, 0, 31 => 00000000ffffffff (00000000 00000000)
+ rlwnm ffffffffffffffff, 0000000000000000, 31, 0 => ffffffff80000001 (00000000 00000000)
+ rlwnm ffffffffffffffff, 0000000000000000, 31, 31 => 0000000000000001 (00000000 00000000)
+ rlwnm ffffffffffffffff, 0000001cbe991def, 0, 0 => 0000000080000000 (00000000 00000000)
+ rlwnm ffffffffffffffff, 0000001cbe991def, 0, 31 => 00000000ffffffff (00000000 00000000)
+ rlwnm ffffffffffffffff, 0000001cbe991def, 31, 0 => ffffffff80000001 (00000000 00000000)
+ rlwnm ffffffffffffffff, 0000001cbe991def, 31, 31 => 0000000000000001 (00000000 00000000)
+ rlwnm ffffffffffffffff, ffffffffffffffff, 0, 0 => 0000000080000000 (00000000 00000000)
+ rlwnm ffffffffffffffff, ffffffffffffffff, 0, 31 => 00000000ffffffff (00000000 00000000)
+ rlwnm ffffffffffffffff, ffffffffffffffff, 31, 0 => ffffffff80000001 (00000000 00000000)
+ rlwnm ffffffffffffffff, ffffffffffffffff, 31, 31 => 0000000000000001 (00000000 00000000)
+
+ srawi 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
+ srawi 0000000000000000, 31 => 0000000000000000 (00000000 00000000)
+ srawi 0000001cbe991def, 0 => ffffffffbe991def (00000000 00000000)
+ srawi 0000001cbe991def, 31 => ffffffffffffffff (00000000 20000000)
+ srawi ffffffffffffffff, 0 => ffffffffffffffff (00000000 00000000)
+ srawi ffffffffffffffff, 31 => ffffffffffffffff (00000000 20000000)
+
+ mfcr (0000000000000000) => 0000000000000000 (00000000 00000000)
+ mfcr (0000001cbe991def) => 00000000be991def (be991def 00000000)
+ mfcr (ffffffffffffffff) => 00000000ffffffff (ffffffff 00000000)
+
+ mfspr 1 (00000000) -> mtxer -> mfxer => 0000000000000000
+ mfspr 1 (be991def) -> mtxer -> mfxer => 00000000a000006f
+ mfspr 1 (ffffffff) -> mtxer -> mfxer => 00000000e000007f
+ mfspr 8 (00000000) -> mtlr -> mflr => 0000000000000000
+ mfspr 8 (be991def) -> mtlr -> mflr => ffffffffbe991def
+ mfspr 8 (ffffffff) -> mtlr -> mflr => ffffffffffffffff
+ mfspr 9 (00000000) -> mtctr -> mfctr => 0000000000000000
+ mfspr 9 (be991def) -> mtctr -> mfctr => ffffffffbe991def
+ mfspr 9 (ffffffff) -> mtctr -> mfctr => ffffffffffffffff
+
+
+ rldcl 0000000000000000, 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000000000000000, 7 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000000000000000, 14 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000000000000000, 21 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000000000000000, 28 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000000000000000, 35 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000000000000000, 42 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000000000000000, 49 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000000000000000, 56 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000000000000000, 63 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000001cbe991def, 0 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000001cbe991def, 7 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000001cbe991def, 14 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000001cbe991def, 21 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000001cbe991def, 28 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000001cbe991def, 35 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000001cbe991def, 42 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000001cbe991def, 49 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000001cbe991def, 56 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, ffffffffffffffff, 0 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, ffffffffffffffff, 7 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, ffffffffffffffff, 14 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, ffffffffffffffff, 21 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, ffffffffffffffff, 28 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, ffffffffffffffff, 35 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, ffffffffffffffff, 42 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, ffffffffffffffff, 49 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, ffffffffffffffff, 56 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, ffffffffffffffff, 63 => 0000000000000000 (00000000 00000000)
+ rldcl 0000001cbe991def, 0000000000000000, 0 => 0000001cbe991def (00000000 00000000)
+ rldcl 0000001cbe991def, 0000000000000000, 7 => 0000001cbe991def (00000000 00000000)
+ rldcl 0000001cbe991def, 0000000000000000, 14 => 0000001cbe991def (00000000 00000000)
+ rldcl 0000001cbe991def, 0000000000000000, 21 => 0000001cbe991def (00000000 00000000)
+ rldcl 0000001cbe991def, 0000000000000000, 28 => 0000000cbe991def (00000000 00000000)
+ rldcl 0000001cbe991def, 0000000000000000, 35 => 000000001e991def (00000000 00000000)
+ rldcl 0000001cbe991def, 0000000000000000, 42 => 0000000000191def (00000000 00000000)
+ rldcl 0000001cbe991def, 0000000000000000, 49 => 0000000000001def (00000000 00000000)
+ rldcl 0000001cbe991def, 0000000000000000, 56 => 00000000000000ef (00000000 00000000)
+ rldcl 0000001cbe991def, 0000000000000000, 63 => 0000000000000001 (00000000 00000000)
+ rldcl 0000001cbe991def, 0000001cbe991def, 0 => 8ef78000000e5f4c (00000000 00000000)
+ rldcl 0000001cbe991def, 0000001cbe991def, 7 => 00f78000000e5f4c (00000000 00000000)
+ rldcl 0000001cbe991def, 0000001cbe991def, 14 => 00038000000e5f4c (00000000 00000000)
+ rldcl 0000001cbe991def, 0000001cbe991def, 21 => 00000000000e5f4c (00000000 00000000)
+ rldcl 0000001cbe991def, 0000001cbe991def, 28 => 00000000000e5f4c (00000000 00000000)
+ rldcl 0000001cbe991def, 0000001cbe991def, 35 => 00000000000e5f4c (00000000 00000000)
+ rldcl 0000001cbe991def, 0000001cbe991def, 42 => 00000000000e5f4c (00000000 00000000)
+ rldcl 0000001cbe991def, 0000001cbe991def, 49 => 0000000000005f4c (00000000 00000000)
+ rldcl 0000001cbe991def, 0000001cbe991def, 56 => 000000000000004c (00000000 00000000)
+ rldcl 0000001cbe991def, 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000)
+ rldcl 0000001cbe991def, ffffffffffffffff, 0 => 8000000e5f4c8ef7 (00000000 00000000)
+ rldcl 0000001cbe991def, ffffffffffffffff, 7 => 0000000e5f4c8ef7 (00000000 00000000)
+ rldcl 0000001cbe991def, ffffffffffffffff, 14 => 0000000e5f4c8ef7 (00000000 00000000)
+ rldcl 0000001cbe991def, ffffffffffffffff, 21 => 0000000e5f4c8ef7 (00000000 00000000)
+ rldcl 0000001cbe991def, ffffffffffffffff, 28 => 0000000e5f4c8ef7 (00000000 00000000)
+ rldcl 0000001cbe991def, ffffffffffffffff, 35 => 000000001f4c8ef7 (00000000 00000000)
+ rldcl 0000001cbe991def, ffffffffffffffff, 42 => 00000000000c8ef7 (00000000 00000000)
+ rldcl 0000001cbe991def, ffffffffffffffff, 49 => 0000000000000ef7 (00000000 00000000)
+ rldcl 0000001cbe991def, ffffffffffffffff, 56 => 00000000000000f7 (00000000 00000000)
+ rldcl 0000001cbe991def, ffffffffffffffff, 63 => 0000000000000001 (00000000 00000000)
+ rldcl ffffffffffffffff, 0000000000000000, 0 => ffffffffffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000000000000000, 7 => 01ffffffffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000000000000000, 14 => 0003ffffffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000000000000000, 21 => 000007ffffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000000000000000, 28 => 0000000fffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000000000000000, 35 => 000000001fffffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000000000000000, 42 => 00000000003fffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000000000000000, 49 => 0000000000007fff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000000000000000, 56 => 00000000000000ff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000000000000000, 63 => 0000000000000001 (00000000 00000000)
+ rldcl ffffffffffffffff, 0000001cbe991def, 0 => ffffffffffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000001cbe991def, 7 => 01ffffffffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000001cbe991def, 14 => 0003ffffffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000001cbe991def, 21 => 000007ffffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000001cbe991def, 28 => 0000000fffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000001cbe991def, 35 => 000000001fffffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000001cbe991def, 42 => 00000000003fffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000001cbe991def, 49 => 0000000000007fff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000001cbe991def, 56 => 00000000000000ff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000001cbe991def, 63 => 0000000000000001 (00000000 00000000)
+ rldcl ffffffffffffffff, ffffffffffffffff, 0 => ffffffffffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, ffffffffffffffff, 7 => 01ffffffffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, ffffffffffffffff, 14 => 0003ffffffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, ffffffffffffffff, 21 => 000007ffffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, ffffffffffffffff, 28 => 0000000fffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, ffffffffffffffff, 35 => 000000001fffffff (00000000 00000000)
+ rldcl ffffffffffffffff, ffffffffffffffff, 42 => 00000000003fffff (00000000 00000000)
+ rldcl ffffffffffffffff, ffffffffffffffff, 49 => 0000000000007fff (00000000 00000000)
+ rldcl ffffffffffffffff, ffffffffffffffff, 56 => 00000000000000ff (00000000 00000000)
+ rldcl ffffffffffffffff, ffffffffffffffff, 63 => 0000000000000001 (00000000 00000000)
+
+ rldcr 0000000000000000, 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000000000000000, 7 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000000000000000, 14 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000000000000000, 21 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000000000000000, 28 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000000000000000, 35 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000000000000000, 42 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000000000000000, 49 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000000000000000, 56 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000000000000000, 63 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000001cbe991def, 0 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000001cbe991def, 7 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000001cbe991def, 14 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000001cbe991def, 21 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000001cbe991def, 28 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000001cbe991def, 35 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000001cbe991def, 42 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000001cbe991def, 49 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000001cbe991def, 56 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, ffffffffffffffff, 0 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, ffffffffffffffff, 7 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, ffffffffffffffff, 14 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, ffffffffffffffff, 21 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, ffffffffffffffff, 28 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, ffffffffffffffff, 35 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, ffffffffffffffff, 42 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, ffffffffffffffff, 49 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, ffffffffffffffff, 56 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, ffffffffffffffff, 63 => 0000000000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000000000000000, 7 => 0000000000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000000000000000, 14 => 0000000000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000000000000000, 21 => 0000000000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000000000000000, 28 => 0000001800000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000000000000000, 35 => 0000001cb0000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000000000000000, 42 => 0000001cbe800000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000000000000000, 49 => 0000001cbe990000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000000000000000, 56 => 0000001cbe991d80 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000000000000000, 63 => 0000001cbe991def (00000000 00000000)
+ rldcr 0000001cbe991def, 0000001cbe991def, 0 => 8000000000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000001cbe991def, 7 => 8e00000000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000001cbe991def, 14 => 8ef6000000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000001cbe991def, 21 => 8ef7800000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000001cbe991def, 28 => 8ef7800000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000001cbe991def, 35 => 8ef7800000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000001cbe991def, 42 => 8ef7800000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000001cbe991def, 49 => 8ef78000000e4000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000001cbe991def, 56 => 8ef78000000e5f00 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000001cbe991def, 63 => 8ef78000000e5f4c (00000000 00000000)
+ rldcr 0000001cbe991def, ffffffffffffffff, 0 => 8000000000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, ffffffffffffffff, 7 => 8000000000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, ffffffffffffffff, 14 => 8000000000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, ffffffffffffffff, 21 => 8000000000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, ffffffffffffffff, 28 => 8000000800000000 (00000000 00000000)
+ rldcr 0000001cbe991def, ffffffffffffffff, 35 => 8000000e50000000 (00000000 00000000)
+ rldcr 0000001cbe991def, ffffffffffffffff, 42 => 8000000e5f400000 (00000000 00000000)
+ rldcr 0000001cbe991def, ffffffffffffffff, 49 => 8000000e5f4c8000 (00000000 00000000)
+ rldcr 0000001cbe991def, ffffffffffffffff, 56 => 8000000e5f4c8e80 (00000000 00000000)
+ rldcr 0000001cbe991def, ffffffffffffffff, 63 => 8000000e5f4c8ef7 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000000000000000, 0 => 8000000000000000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000000000000000, 7 => ff00000000000000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000000000000000, 14 => fffe000000000000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000000000000000, 21 => fffffc0000000000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000000000000000, 28 => fffffff800000000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000000000000000, 35 => fffffffff0000000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000000000000000, 42 => ffffffffffe00000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000000000000000, 49 => ffffffffffffc000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000000000000000, 56 => ffffffffffffff80 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000000000000000, 63 => ffffffffffffffff (00000000 00000000)
+ rldcr ffffffffffffffff, 0000001cbe991def, 0 => 8000000000000000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000001cbe991def, 7 => ff00000000000000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000001cbe991def, 14 => fffe000000000000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000001cbe991def, 21 => fffffc0000000000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000001cbe991def, 28 => fffffff800000000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000001cbe991def, 35 => fffffffff0000000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000001cbe991def, 42 => ffffffffffe00000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000001cbe991def, 49 => ffffffffffffc000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000001cbe991def, 56 => ffffffffffffff80 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000001cbe991def, 63 => ffffffffffffffff (00000000 00000000)
+ rldcr ffffffffffffffff, ffffffffffffffff, 0 => 8000000000000000 (00000000 00000000)
+ rldcr ffffffffffffffff, ffffffffffffffff, 7 => ff00000000000000 (00000000 00000000)
+ rldcr ffffffffffffffff, ffffffffffffffff, 14 => fffe000000000000 (00000000 00000000)
+ rldcr ffffffffffffffff, ffffffffffffffff, 21 => fffffc0000000000 (00000000 00000000)
+ rldcr ffffffffffffffff, ffffffffffffffff, 28 => fffffff800000000 (00000000 00000000)
+ rldcr ffffffffffffffff, ffffffffffffffff, 35 => fffffffff0000000 (00000000 00000000)
+ rldcr ffffffffffffffff, ffffffffffffffff, 42 => ffffffffffe00000 (00000000 00000000)
+ rldcr ffffffffffffffff, ffffffffffffffff, 49 => ffffffffffffc000 (00000000 00000000)
+ rldcr ffffffffffffffff, ffffffffffffffff, 56 => ffffffffffffff80 (00000000 00000000)
+ rldcr ffffffffffffffff, ffffffffffffffff, 63 => ffffffffffffffff (00000000 00000000)
+
+ rldic 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 0, 7 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 0, 14 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 0, 21 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 0, 28 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 0, 35 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 0, 42 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 0, 49 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 0, 56 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 0, 63 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 7, 0 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 7, 7 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 7, 14 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 7, 21 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 7, 28 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 7, 35 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 7, 42 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 7, 49 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 7, 56 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 7, 63 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 14, 0 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 14, 7 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 14, 14 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 14, 21 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 14, 28 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 14, 35 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 14, 42 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 14, 49 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 14, 56 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 14, 63 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 21, 0 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 21, 7 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 21, 14 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 21, 21 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 21, 28 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 21, 35 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 21, 42 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 21, 49 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 21, 56 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 21, 63 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 28, 0 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 28, 7 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 28, 14 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 28, 21 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 28, 28 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 28, 35 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 28, 42 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 28, 49 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 28, 56 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 28, 63 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 35, 0 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 35, 7 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 35, 14 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 35, 21 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 35, 28 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 35, 35 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 35, 42 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 35, 49 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 35, 56 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 35, 63 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 42, 0 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 42, 7 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 42, 14 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 42, 21 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 42, 28 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 42, 35 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 42, 42 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 42, 49 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 42, 56 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 42, 63 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 49, 0 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 49, 7 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 49, 14 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 49, 21 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 49, 28 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 49, 35 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 49, 42 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 49, 49 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 49, 56 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 49, 63 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 56, 0 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 56, 7 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 56, 14 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 56, 21 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 56, 28 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 56, 35 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 56, 42 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 56, 49 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 56, 56 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 56, 63 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 63, 0 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 63, 7 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 63, 14 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 63, 21 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 63, 28 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 63, 35 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 63, 42 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 63, 49 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 63, 56 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 63, 63 => 0000000000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 0, 0 => 0000001cbe991def (00000000 00000000)
+ rldic 0000001cbe991def, 0, 7 => 0000001cbe991def (00000000 00000000)
+ rldic 0000001cbe991def, 0, 14 => 0000001cbe991def (00000000 00000000)
+ rldic 0000001cbe991def, 0, 21 => 0000001cbe991def (00000000 00000000)
+ rldic 0000001cbe991def, 0, 28 => 0000000cbe991def (00000000 00000000)
+ rldic 0000001cbe991def, 0, 35 => 000000001e991def (00000000 00000000)
+ rldic 0000001cbe991def, 0, 42 => 0000000000191def (00000000 00000000)
+ rldic 0000001cbe991def, 0, 49 => 0000000000001def (00000000 00000000)
+ rldic 0000001cbe991def, 0, 56 => 00000000000000ef (00000000 00000000)
+ rldic 0000001cbe991def, 0, 63 => 0000000000000001 (00000000 00000000)
+ rldic 0000001cbe991def, 7, 0 => 00000e5f4c8ef780 (00000000 00000000)
+ rldic 0000001cbe991def, 7, 7 => 00000e5f4c8ef780 (00000000 00000000)
+ rldic 0000001cbe991def, 7, 14 => 00000e5f4c8ef780 (00000000 00000000)
+ rldic 0000001cbe991def, 7, 21 => 0000065f4c8ef780 (00000000 00000000)
+ rldic 0000001cbe991def, 7, 28 => 0000000f4c8ef780 (00000000 00000000)
+ rldic 0000001cbe991def, 7, 35 => 000000000c8ef780 (00000000 00000000)
+ rldic 0000001cbe991def, 7, 42 => 00000000000ef780 (00000000 00000000)
+ rldic 0000001cbe991def, 7, 49 => 0000000000007780 (00000000 00000000)
+ rldic 0000001cbe991def, 7, 56 => 0000000000000080 (00000000 00000000)
+ rldic 0000001cbe991def, 7, 63 => 00000e5f4c8ef780 (00000000 00000000)
+ rldic 0000001cbe991def, 14, 0 => 00072fa6477bc000 (00000000 00000000)
+ rldic 0000001cbe991def, 14, 7 => 00072fa6477bc000 (00000000 00000000)
+ rldic 0000001cbe991def, 14, 14 => 00032fa6477bc000 (00000000 00000000)
+ rldic 0000001cbe991def, 14, 21 => 000007a6477bc000 (00000000 00000000)
+ rldic 0000001cbe991def, 14, 28 => 00000006477bc000 (00000000 00000000)
+ rldic 0000001cbe991def, 14, 35 => 00000000077bc000 (00000000 00000000)
+ rldic 0000001cbe991def, 14, 42 => 00000000003bc000 (00000000 00000000)
+ rldic 0000001cbe991def, 14, 49 => 0000000000004000 (00000000 00000000)
+ rldic 0000001cbe991def, 14, 56 => 00072fa6477bc000 (00000000 00000000)
+ rldic 0000001cbe991def, 14, 63 => 00072fa6477bc000 (00000000 00000000)
+ rldic 0000001cbe991def, 21, 0 => 0397d323bde00000 (00000000 00000000)
+ rldic 0000001cbe991def, 21, 7 => 0197d323bde00000 (00000000 00000000)
+ rldic 0000001cbe991def, 21, 14 => 0003d323bde00000 (00000000 00000000)
+ rldic 0000001cbe991def, 21, 21 => 00000323bde00000 (00000000 00000000)
+ rldic 0000001cbe991def, 21, 28 => 00000003bde00000 (00000000 00000000)
+ rldic 0000001cbe991def, 21, 35 => 000000001de00000 (00000000 00000000)
+ rldic 0000001cbe991def, 21, 42 => 0000000000200000 (00000000 00000000)
+ rldic 0000001cbe991def, 21, 49 => 0397d323bde00000 (00000000 00000000)
+ rldic 0000001cbe991def, 21, 56 => 0397d323bde00000 (00000000 00000000)
+ rldic 0000001cbe991def, 21, 63 => 0397d323bde00000 (00000000 00000000)
+ rldic 0000001cbe991def, 28, 0 => cbe991def0000000 (00000000 00000000)
+ rldic 0000001cbe991def, 28, 7 => 01e991def0000000 (00000000 00000000)
+ rldic 0000001cbe991def, 28, 14 => 000191def0000000 (00000000 00000000)
+ rldic 0000001cbe991def, 28, 21 => 000001def0000000 (00000000 00000000)
+ rldic 0000001cbe991def, 28, 28 => 0000000ef0000000 (00000000 00000000)
+ rldic 0000001cbe991def, 28, 35 => 0000000010000000 (00000000 00000000)
+ rldic 0000001cbe991def, 28, 42 => cbe991def0000001 (00000000 00000000)
+ rldic 0000001cbe991def, 28, 49 => cbe991def0000001 (00000000 00000000)
+ rldic 0000001cbe991def, 28, 56 => cbe991def0000001 (00000000 00000000)
+ rldic 0000001cbe991def, 28, 63 => cbe991def0000001 (00000000 00000000)
+ rldic 0000001cbe991def, 35, 0 => f4c8ef7800000000 (00000000 00000000)
+ rldic 0000001cbe991def, 35, 7 => 00c8ef7800000000 (00000000 00000000)
+ rldic 0000001cbe991def, 35, 14 => 0000ef7800000000 (00000000 00000000)
+ rldic 0000001cbe991def, 35, 21 => 0000077800000000 (00000000 00000000)
+ rldic 0000001cbe991def, 35, 28 => 0000000800000000 (00000000 00000000)
+ rldic 0000001cbe991def, 35, 35 => f4c8ef78000000e5 (00000000 00000000)
+ rldic 0000001cbe991def, 35, 42 => f4c8ef78000000e5 (00000000 00000000)
+ rldic 0000001cbe991def, 35, 49 => f4c8ef78000000e5 (00000000 00000000)
+ rldic 0000001cbe991def, 35, 56 => f4c8ef78000000e5 (00000000 00000000)
+ rldic 0000001cbe991def, 35, 63 => f4c8ef7800000001 (00000000 00000000)
+ rldic 0000001cbe991def, 42, 0 => 6477bc0000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 42, 7 => 0077bc0000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 42, 14 => 0003bc0000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 42, 21 => 0000040000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 42, 28 => 6477bc00000072fa (00000000 00000000)
+ rldic 0000001cbe991def, 42, 35 => 6477bc00000072fa (00000000 00000000)
+ rldic 0000001cbe991def, 42, 42 => 6477bc00000072fa (00000000 00000000)
+ rldic 0000001cbe991def, 42, 49 => 6477bc00000072fa (00000000 00000000)
+ rldic 0000001cbe991def, 42, 56 => 6477bc00000000fa (00000000 00000000)
+ rldic 0000001cbe991def, 42, 63 => 6477bc0000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 49, 0 => 3bde000000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 49, 7 => 01de000000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 49, 14 => 0002000000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 49, 21 => 3bde000000397d32 (00000000 00000000)
+ rldic 0000001cbe991def, 49, 28 => 3bde000000397d32 (00000000 00000000)
+ rldic 0000001cbe991def, 49, 35 => 3bde000000397d32 (00000000 00000000)
+ rldic 0000001cbe991def, 49, 42 => 3bde000000397d32 (00000000 00000000)
+ rldic 0000001cbe991def, 49, 49 => 3bde000000007d32 (00000000 00000000)
+ rldic 0000001cbe991def, 49, 56 => 3bde000000000032 (00000000 00000000)
+ rldic 0000001cbe991def, 49, 63 => 3bde000000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 56, 0 => ef00000000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 56, 7 => 0100000000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 56, 14 => ef0000001cbe991d (00000000 00000000)
+ rldic 0000001cbe991def, 56, 21 => ef0000001cbe991d (00000000 00000000)
+ rldic 0000001cbe991def, 56, 28 => ef0000001cbe991d (00000000 00000000)
+ rldic 0000001cbe991def, 56, 35 => ef0000001cbe991d (00000000 00000000)
+ rldic 0000001cbe991def, 56, 42 => ef000000003e991d (00000000 00000000)
+ rldic 0000001cbe991def, 56, 49 => ef0000000000191d (00000000 00000000)
+ rldic 0000001cbe991def, 56, 56 => ef0000000000001d (00000000 00000000)
+ rldic 0000001cbe991def, 56, 63 => ef00000000000001 (00000000 00000000)
+ rldic 0000001cbe991def, 63, 0 => 8000000000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 63, 7 => 8000000e5f4c8ef7 (00000000 00000000)
+ rldic 0000001cbe991def, 63, 14 => 8000000e5f4c8ef7 (00000000 00000000)
+ rldic 0000001cbe991def, 63, 21 => 8000000e5f4c8ef7 (00000000 00000000)
+ rldic 0000001cbe991def, 63, 28 => 8000000e5f4c8ef7 (00000000 00000000)
+ rldic 0000001cbe991def, 63, 35 => 800000001f4c8ef7 (00000000 00000000)
+ rldic 0000001cbe991def, 63, 42 => 80000000000c8ef7 (00000000 00000000)
+ rldic 0000001cbe991def, 63, 49 => 8000000000000ef7 (00000000 00000000)
+ rldic 0000001cbe991def, 63, 56 => 80000000000000f7 (00000000 00000000)
+ rldic 0000001cbe991def, 63, 63 => 8000000000000001 (00000000 00000000)
+ rldic ffffffffffffffff, 0, 0 => ffffffffffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 0, 7 => 01ffffffffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 0, 14 => 0003ffffffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 0, 21 => 000007ffffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 0, 28 => 0000000fffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 0, 35 => 000000001fffffff (00000000 00000000)
+ rldic ffffffffffffffff, 0, 42 => 00000000003fffff (00000000 00000000)
+ rldic ffffffffffffffff, 0, 49 => 0000000000007fff (00000000 00000000)
+ rldic ffffffffffffffff, 0, 56 => 00000000000000ff (00000000 00000000)
+ rldic ffffffffffffffff, 0, 63 => 0000000000000001 (00000000 00000000)
+ rldic ffffffffffffffff, 7, 0 => ffffffffffffff80 (00000000 00000000)
+ rldic ffffffffffffffff, 7, 7 => 01ffffffffffff80 (00000000 00000000)
+ rldic ffffffffffffffff, 7, 14 => 0003ffffffffff80 (00000000 00000000)
+ rldic ffffffffffffffff, 7, 21 => 000007ffffffff80 (00000000 00000000)
+ rldic ffffffffffffffff, 7, 28 => 0000000fffffff80 (00000000 00000000)
+ rldic ffffffffffffffff, 7, 35 => 000000001fffff80 (00000000 00000000)
+ rldic ffffffffffffffff, 7, 42 => 00000000003fff80 (00000000 00000000)
+ rldic ffffffffffffffff, 7, 49 => 0000000000007f80 (00000000 00000000)
+ rldic ffffffffffffffff, 7, 56 => 0000000000000080 (00000000 00000000)
+ rldic ffffffffffffffff, 7, 63 => ffffffffffffff81 (00000000 00000000)
+ rldic ffffffffffffffff, 14, 0 => ffffffffffffc000 (00000000 00000000)
+ rldic ffffffffffffffff, 14, 7 => 01ffffffffffc000 (00000000 00000000)
+ rldic ffffffffffffffff, 14, 14 => 0003ffffffffc000 (00000000 00000000)
+ rldic ffffffffffffffff, 14, 21 => 000007ffffffc000 (00000000 00000000)
+ rldic ffffffffffffffff, 14, 28 => 0000000fffffc000 (00000000 00000000)
+ rldic ffffffffffffffff, 14, 35 => 000000001fffc000 (00000000 00000000)
+ rldic ffffffffffffffff, 14, 42 => 00000000003fc000 (00000000 00000000)
+ rldic ffffffffffffffff, 14, 49 => 0000000000004000 (00000000 00000000)
+ rldic ffffffffffffffff, 14, 56 => ffffffffffffc0ff (00000000 00000000)
+ rldic ffffffffffffffff, 14, 63 => ffffffffffffc001 (00000000 00000000)
+ rldic ffffffffffffffff, 21, 0 => ffffffffffe00000 (00000000 00000000)
+ rldic ffffffffffffffff, 21, 7 => 01ffffffffe00000 (00000000 00000000)
+ rldic ffffffffffffffff, 21, 14 => 0003ffffffe00000 (00000000 00000000)
+ rldic ffffffffffffffff, 21, 21 => 000007ffffe00000 (00000000 00000000)
+ rldic ffffffffffffffff, 21, 28 => 0000000fffe00000 (00000000 00000000)
+ rldic ffffffffffffffff, 21, 35 => 000000001fe00000 (00000000 00000000)
+ rldic ffffffffffffffff, 21, 42 => 0000000000200000 (00000000 00000000)
+ rldic ffffffffffffffff, 21, 49 => ffffffffffe07fff (00000000 00000000)
+ rldic ffffffffffffffff, 21, 56 => ffffffffffe000ff (00000000 00000000)
+ rldic ffffffffffffffff, 21, 63 => ffffffffffe00001 (00000000 00000000)
+ rldic ffffffffffffffff, 28, 0 => fffffffff0000000 (00000000 00000000)
+ rldic ffffffffffffffff, 28, 7 => 01fffffff0000000 (00000000 00000000)
+ rldic ffffffffffffffff, 28, 14 => 0003fffff0000000 (00000000 00000000)
+ rldic ffffffffffffffff, 28, 21 => 000007fff0000000 (00000000 00000000)
+ rldic ffffffffffffffff, 28, 28 => 0000000ff0000000 (00000000 00000000)
+ rldic ffffffffffffffff, 28, 35 => 0000000010000000 (00000000 00000000)
+ rldic ffffffffffffffff, 28, 42 => fffffffff03fffff (00000000 00000000)
+ rldic ffffffffffffffff, 28, 49 => fffffffff0007fff (00000000 00000000)
+ rldic ffffffffffffffff, 28, 56 => fffffffff00000ff (00000000 00000000)
+ rldic ffffffffffffffff, 28, 63 => fffffffff0000001 (00000000 00000000)
+ rldic ffffffffffffffff, 35, 0 => fffffff800000000 (00000000 00000000)
+ rldic ffffffffffffffff, 35, 7 => 01fffff800000000 (00000000 00000000)
+ rldic ffffffffffffffff, 35, 14 => 0003fff800000000 (00000000 00000000)
+ rldic ffffffffffffffff, 35, 21 => 000007f800000000 (00000000 00000000)
+ rldic ffffffffffffffff, 35, 28 => 0000000800000000 (00000000 00000000)
+ rldic ffffffffffffffff, 35, 35 => fffffff81fffffff (00000000 00000000)
+ rldic ffffffffffffffff, 35, 42 => fffffff8003fffff (00000000 00000000)
+ rldic ffffffffffffffff, 35, 49 => fffffff800007fff (00000000 00000000)
+ rldic ffffffffffffffff, 35, 56 => fffffff8000000ff (00000000 00000000)
+ rldic ffffffffffffffff, 35, 63 => fffffff800000001 (00000000 00000000)
+ rldic ffffffffffffffff, 42, 0 => fffffc0000000000 (00000000 00000000)
+ rldic ffffffffffffffff, 42, 7 => 01fffc0000000000 (00000000 00000000)
+ rldic ffffffffffffffff, 42, 14 => 0003fc0000000000 (00000000 00000000)
+ rldic ffffffffffffffff, 42, 21 => 0000040000000000 (00000000 00000000)
+ rldic ffffffffffffffff, 42, 28 => fffffc0fffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 42, 35 => fffffc001fffffff (00000000 00000000)
+ rldic ffffffffffffffff, 42, 42 => fffffc00003fffff (00000000 00000000)
+ rldic ffffffffffffffff, 42, 49 => fffffc0000007fff (00000000 00000000)
+ rldic ffffffffffffffff, 42, 56 => fffffc00000000ff (00000000 00000000)
+ rldic ffffffffffffffff, 42, 63 => fffffc0000000001 (00000000 00000000)
+ rldic ffffffffffffffff, 49, 0 => fffe000000000000 (00000000 00000000)
+ rldic ffffffffffffffff, 49, 7 => 01fe000000000000 (00000000 00000000)
+ rldic ffffffffffffffff, 49, 14 => 0002000000000000 (00000000 00000000)
+ rldic ffffffffffffffff, 49, 21 => fffe07ffffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 49, 28 => fffe000fffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 49, 35 => fffe00001fffffff (00000000 00000000)
+ rldic ffffffffffffffff, 49, 42 => fffe0000003fffff (00000000 00000000)
+ rldic ffffffffffffffff, 49, 49 => fffe000000007fff (00000000 00000000)
+ rldic ffffffffffffffff, 49, 56 => fffe0000000000ff (00000000 00000000)
+ rldic ffffffffffffffff, 49, 63 => fffe000000000001 (00000000 00000000)
+ rldic ffffffffffffffff, 56, 0 => ff00000000000000 (00000000 00000000)
+ rldic ffffffffffffffff, 56, 7 => 0100000000000000 (00000000 00000000)
+ rldic ffffffffffffffff, 56, 14 => ff03ffffffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 56, 21 => ff0007ffffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 56, 28 => ff00000fffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 56, 35 => ff0000001fffffff (00000000 00000000)
+ rldic ffffffffffffffff, 56, 42 => ff000000003fffff (00000000 00000000)
+ rldic ffffffffffffffff, 56, 49 => ff00000000007fff (00000000 00000000)
+ rldic ffffffffffffffff, 56, 56 => ff000000000000ff (00000000 00000000)
+ rldic ffffffffffffffff, 56, 63 => ff00000000000001 (00000000 00000000)
+ rldic ffffffffffffffff, 63, 0 => 8000000000000000 (00000000 00000000)
+ rldic ffffffffffffffff, 63, 7 => 81ffffffffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 63, 14 => 8003ffffffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 63, 21 => 800007ffffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 63, 28 => 8000000fffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 63, 35 => 800000001fffffff (00000000 00000000)
+ rldic ffffffffffffffff, 63, 42 => 80000000003fffff (00000000 00000000)
+ rldic ffffffffffffffff, 63, 49 => 8000000000007fff (00000000 00000000)
+ rldic ffffffffffffffff, 63, 56 => 80000000000000ff (00000000 00000000)
+ rldic ffffffffffffffff, 63, 63 => 8000000000000001 (00000000 00000000)
+
+ rldicl 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 0, 7 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 0, 14 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 0, 21 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 0, 28 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 0, 35 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 0, 42 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 0, 49 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 0, 56 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 0, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 7, 0 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 7, 7 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 7, 14 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 7, 21 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 7, 28 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 7, 35 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 7, 42 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 7, 49 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 7, 56 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 7, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 14, 0 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 14, 7 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 14, 14 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 14, 21 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 14, 28 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 14, 35 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 14, 42 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 14, 49 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 14, 56 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 14, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 21, 0 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 21, 7 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 21, 14 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 21, 21 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 21, 28 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 21, 35 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 21, 42 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 21, 49 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 21, 56 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 21, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 28, 0 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 28, 7 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 28, 14 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 28, 21 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 28, 28 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 28, 35 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 28, 42 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 28, 49 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 28, 56 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 28, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 35, 0 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 35, 7 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 35, 14 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 35, 21 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 35, 28 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 35, 35 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 35, 42 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 35, 49 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 35, 56 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 35, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 42, 0 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 42, 7 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 42, 14 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 42, 21 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 42, 28 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 42, 35 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 42, 42 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 42, 49 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 42, 56 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 42, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 49, 0 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 49, 7 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 49, 14 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 49, 21 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 49, 28 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 49, 35 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 49, 42 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 49, 49 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 49, 56 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 49, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 56, 0 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 56, 7 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 56, 14 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 56, 21 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 56, 28 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 56, 35 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 56, 42 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 56, 49 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 56, 56 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 56, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 63, 0 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 63, 7 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 63, 14 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 63, 21 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 63, 28 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 63, 35 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 63, 42 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 63, 49 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 63, 56 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 63, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000001cbe991def, 0, 0 => 0000001cbe991def (00000000 00000000)
+ rldicl 0000001cbe991def, 0, 7 => 0000001cbe991def (00000000 00000000)
+ rldicl 0000001cbe991def, 0, 14 => 0000001cbe991def (00000000 00000000)
+ rldicl 0000001cbe991def, 0, 21 => 0000001cbe991def (00000000 00000000)
+ rldicl 0000001cbe991def, 0, 28 => 0000000cbe991def (00000000 00000000)
+ rldicl 0000001cbe991def, 0, 35 => 000000001e991def (00000000 00000000)
+ rldicl 0000001cbe991def, 0, 42 => 0000000000191def (00000000 00000000)
+ rldicl 0000001cbe991def, 0, 49 => 0000000000001def (00000000 00000000)
+ rldicl 0000001cbe991def, 0, 56 => 00000000000000ef (00000000 00000000)
+ rldicl 0000001cbe991def, 0, 63 => 0000000000000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 7, 0 => 00000e5f4c8ef780 (00000000 00000000)
+ rldicl 0000001cbe991def, 7, 7 => 00000e5f4c8ef780 (00000000 00000000)
+ rldicl 0000001cbe991def, 7, 14 => 00000e5f4c8ef780 (00000000 00000000)
+ rldicl 0000001cbe991def, 7, 21 => 0000065f4c8ef780 (00000000 00000000)
+ rldicl 0000001cbe991def, 7, 28 => 0000000f4c8ef780 (00000000 00000000)
+ rldicl 0000001cbe991def, 7, 35 => 000000000c8ef780 (00000000 00000000)
+ rldicl 0000001cbe991def, 7, 42 => 00000000000ef780 (00000000 00000000)
+ rldicl 0000001cbe991def, 7, 49 => 0000000000007780 (00000000 00000000)
+ rldicl 0000001cbe991def, 7, 56 => 0000000000000080 (00000000 00000000)
+ rldicl 0000001cbe991def, 7, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000001cbe991def, 14, 0 => 00072fa6477bc000 (00000000 00000000)
+ rldicl 0000001cbe991def, 14, 7 => 00072fa6477bc000 (00000000 00000000)
+ rldicl 0000001cbe991def, 14, 14 => 00032fa6477bc000 (00000000 00000000)
+ rldicl 0000001cbe991def, 14, 21 => 000007a6477bc000 (00000000 00000000)
+ rldicl 0000001cbe991def, 14, 28 => 00000006477bc000 (00000000 00000000)
+ rldicl 0000001cbe991def, 14, 35 => 00000000077bc000 (00000000 00000000)
+ rldicl 0000001cbe991def, 14, 42 => 00000000003bc000 (00000000 00000000)
+ rldicl 0000001cbe991def, 14, 49 => 0000000000004000 (00000000 00000000)
+ rldicl 0000001cbe991def, 14, 56 => 0000000000000000 (00000000 00000000)
+ rldicl 0000001cbe991def, 14, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000001cbe991def, 21, 0 => 0397d323bde00000 (00000000 00000000)
+ rldicl 0000001cbe991def, 21, 7 => 0197d323bde00000 (00000000 00000000)
+ rldicl 0000001cbe991def, 21, 14 => 0003d323bde00000 (00000000 00000000)
+ rldicl 0000001cbe991def, 21, 21 => 00000323bde00000 (00000000 00000000)
+ rldicl 0000001cbe991def, 21, 28 => 00000003bde00000 (00000000 00000000)
+ rldicl 0000001cbe991def, 21, 35 => 000000001de00000 (00000000 00000000)
+ rldicl 0000001cbe991def, 21, 42 => 0000000000200000 (00000000 00000000)
+ rldicl 0000001cbe991def, 21, 49 => 0000000000000000 (00000000 00000000)
+ rldicl 0000001cbe991def, 21, 56 => 0000000000000000 (00000000 00000000)
+ rldicl 0000001cbe991def, 21, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000001cbe991def, 28, 0 => cbe991def0000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 28, 7 => 01e991def0000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 28, 14 => 000191def0000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 28, 21 => 000001def0000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 28, 28 => 0000000ef0000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 28, 35 => 0000000010000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 28, 42 => 0000000000000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 28, 49 => 0000000000000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 28, 56 => 0000000000000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 28, 63 => 0000000000000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 35, 0 => f4c8ef78000000e5 (00000000 00000000)
+ rldicl 0000001cbe991def, 35, 7 => 00c8ef78000000e5 (00000000 00000000)
+ rldicl 0000001cbe991def, 35, 14 => 0000ef78000000e5 (00000000 00000000)
+ rldicl 0000001cbe991def, 35, 21 => 00000778000000e5 (00000000 00000000)
+ rldicl 0000001cbe991def, 35, 28 => 00000008000000e5 (00000000 00000000)
+ rldicl 0000001cbe991def, 35, 35 => 00000000000000e5 (00000000 00000000)
+ rldicl 0000001cbe991def, 35, 42 => 00000000000000e5 (00000000 00000000)
+ rldicl 0000001cbe991def, 35, 49 => 00000000000000e5 (00000000 00000000)
+ rldicl 0000001cbe991def, 35, 56 => 00000000000000e5 (00000000 00000000)
+ rldicl 0000001cbe991def, 35, 63 => 0000000000000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 42, 0 => 6477bc00000072fa (00000000 00000000)
+ rldicl 0000001cbe991def, 42, 7 => 0077bc00000072fa (00000000 00000000)
+ rldicl 0000001cbe991def, 42, 14 => 0003bc00000072fa (00000000 00000000)
+ rldicl 0000001cbe991def, 42, 21 => 00000400000072fa (00000000 00000000)
+ rldicl 0000001cbe991def, 42, 28 => 00000000000072fa (00000000 00000000)
+ rldicl 0000001cbe991def, 42, 35 => 00000000000072fa (00000000 00000000)
+ rldicl 0000001cbe991def, 42, 42 => 00000000000072fa (00000000 00000000)
+ rldicl 0000001cbe991def, 42, 49 => 00000000000072fa (00000000 00000000)
+ rldicl 0000001cbe991def, 42, 56 => 00000000000000fa (00000000 00000000)
+ rldicl 0000001cbe991def, 42, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000001cbe991def, 49, 0 => 3bde000000397d32 (00000000 00000000)
+ rldicl 0000001cbe991def, 49, 7 => 01de000000397d32 (00000000 00000000)
+ rldicl 0000001cbe991def, 49, 14 => 0002000000397d32 (00000000 00000000)
+ rldicl 0000001cbe991def, 49, 21 => 0000000000397d32 (00000000 00000000)
+ rldicl 0000001cbe991def, 49, 28 => 0000000000397d32 (00000000 00000000)
+ rldicl 0000001cbe991def, 49, 35 => 0000000000397d32 (00000000 00000000)
+ rldicl 0000001cbe991def, 49, 42 => 0000000000397d32 (00000000 00000000)
+ rldicl 0000001cbe991def, 49, 49 => 0000000000007d32 (00000000 00000000)
+ rldicl 0000001cbe991def, 49, 56 => 0000000000000032 (00000000 00000000)
+ rldicl 0000001cbe991def, 49, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000001cbe991def, 56, 0 => ef0000001cbe991d (00000000 00000000)
+ rldicl 0000001cbe991def, 56, 7 => 010000001cbe991d (00000000 00000000)
+ rldicl 0000001cbe991def, 56, 14 => 000000001cbe991d (00000000 00000000)
+ rldicl 0000001cbe991def, 56, 21 => 000000001cbe991d (00000000 00000000)
+ rldicl 0000001cbe991def, 56, 28 => 000000001cbe991d (00000000 00000000)
+ rldicl 0000001cbe991def, 56, 35 => 000000001cbe991d (00000000 00000000)
+ rldicl 0000001cbe991def, 56, 42 => 00000000003e991d (00000000 00000000)
+ rldicl 0000001cbe991def, 56, 49 => 000000000000191d (00000000 00000000)
+ rldicl 0000001cbe991def, 56, 56 => 000000000000001d (00000000 00000000)
+ rldicl 0000001cbe991def, 56, 63 => 0000000000000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 63, 0 => 8000000e5f4c8ef7 (00000000 00000000)
+ rldicl 0000001cbe991def, 63, 7 => 0000000e5f4c8ef7 (00000000 00000000)
+ rldicl 0000001cbe991def, 63, 14 => 0000000e5f4c8ef7 (00000000 00000000)
+ rldicl 0000001cbe991def, 63, 21 => 0000000e5f4c8ef7 (00000000 00000000)
+ rldicl 0000001cbe991def, 63, 28 => 0000000e5f4c8ef7 (00000000 00000000)
+ rldicl 0000001cbe991def, 63, 35 => 000000001f4c8ef7 (00000000 00000000)
+ rldicl 0000001cbe991def, 63, 42 => 00000000000c8ef7 (00000000 00000000)
+ rldicl 0000001cbe991def, 63, 49 => 0000000000000ef7 (00000000 00000000)
+ rldicl 0000001cbe991def, 63, 56 => 00000000000000f7 (00000000 00000000)
+ rldicl 0000001cbe991def, 63, 63 => 0000000000000001 (00000000 00000000)
+ rldicl ffffffffffffffff, 0, 0 => ffffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 0, 7 => 01ffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 0, 14 => 0003ffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 0, 21 => 000007ffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 0, 28 => 0000000fffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 0, 35 => 000000001fffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 0, 42 => 00000000003fffff (00000000 00000000)
+ rldicl ffffffffffffffff, 0, 49 => 0000000000007fff (00000000 00000000)
+ rldicl ffffffffffffffff, 0, 56 => 00000000000000ff (00000000 00000000)
+ rldicl ffffffffffffffff, 0, 63 => 0000000000000001 (00000000 00000000)
+ rldicl ffffffffffffffff, 7, 0 => ffffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 7, 7 => 01ffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 7, 14 => 0003ffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 7, 21 => 000007ffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 7, 28 => 0000000fffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 7, 35 => 000000001fffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 7, 42 => 00000000003fffff (00000000 00000000)
+ rldicl ffffffffffffffff, 7, 49 => 0000000000007fff (00000000 00000000)
+ rldicl ffffffffffffffff, 7, 56 => 00000000000000ff (00000000 00000000)
+ rldicl ffffffffffffffff, 7, 63 => 0000000000000001 (00000000 00000000)
+ rldicl ffffffffffffffff, 14, 0 => ffffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 14, 7 => 01ffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 14, 14 => 0003ffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 14, 21 => 000007ffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 14, 28 => 0000000fffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 14, 35 => 000000001fffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 14, 42 => 00000000003fffff (00000000 00000000)
+ rldicl ffffffffffffffff, 14, 49 => 0000000000007fff (00000000 00000000)
+ rldicl ffffffffffffffff, 14, 56 => 00000000000000ff (00000000 00000000)
+ rldicl ffffffffffffffff, 14, 63 => 0000000000000001 (00000000 00000000)
+ rldicl ffffffffffffffff, 21, 0 => ffffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 21, 7 => 01ffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 21, 14 => 0003ffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 21, 21 => 000007ffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 21, 28 => 0000000fffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 21, 35 => 000000001fffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 21, 42 => 00000000003fffff (00000000 00000000)
+ rldicl ffffffffffffffff, 21, 49 => 0000000000007fff (00000000 00000000)
+ rldicl ffffffffffffffff, 21, 56 => 00000000000000ff (00000000 00000000)
+ rldicl ffffffffffffffff, 21, 63 => 0000000000000001 (00000000 00000000)
+ rldicl ffffffffffffffff, 28, 0 => ffffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 28, 7 => 01ffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 28, 14 => 0003ffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 28, 21 => 000007ffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 28, 28 => 0000000fffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 28, 35 => 000000001fffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 28, 42 => 00000000003fffff (00000000 00000000)
+ rldicl ffffffffffffffff, 28, 49 => 0000000000007fff (00000000 00000000)
+ rldicl ffffffffffffffff, 28, 56 => 00000000000000ff (00000000 00000000)
+ rldicl ffffffffffffffff, 28, 63 => 0000000000000001 (00000000 00000000)
+ rldicl ffffffffffffffff, 35, 0 => ffffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 35, 7 => 01ffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 35, 14 => 0003ffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 35, 21 => 000007ffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 35, 28 => 0000000fffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 35, 35 => 000000001fffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 35, 42 => 00000000003fffff (00000000 00000000)
+ rldicl ffffffffffffffff, 35, 49 => 0000000000007fff (00000000 00000000)
+ rldicl ffffffffffffffff, 35, 56 => 00000000000000ff (00000000 00000000)
+ rldicl ffffffffffffffff, 35, 63 => 0000000000000001 (00000000 00000000)
+ rldicl ffffffffffffffff, 42, 0 => ffffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 42, 7 => 01ffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 42, 14 => 0003ffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 42, 21 => 000007ffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 42, 28 => 0000000fffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 42, 35 => 000000001fffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 42, 42 => 00000000003fffff (00000000 00000000)
+ rldicl ffffffffffffffff, 42, 49 => 0000000000007fff (00000000 00000000)
+ rldicl ffffffffffffffff, 42, 56 => 00000000000000ff (00000000 00000000)
+ rldicl ffffffffffffffff, 42, 63 => 0000000000000001 (00000000 00000000)
+ rldicl ffffffffffffffff, 49, 0 => ffffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 49, 7 => 01ffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 49, 14 => 0003ffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 49, 21 => 000007ffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 49, 28 => 0000000fffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 49, 35 => 000000001fffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 49, 42 => 00000000003fffff (00000000 00000000)
+ rldicl ffffffffffffffff, 49, 49 => 0000000000007fff (00000000 00000000)
+ rldicl ffffffffffffffff, 49, 56 => 00000000000000ff (00000000 00000000)
+ rldicl ffffffffffffffff, 49, 63 => 0000000000000001 (00000000 00000000)
+ rldicl ffffffffffffffff, 56, 0 => ffffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 56, 7 => 01ffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 56, 14 => 0003ffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 56, 21 => 000007ffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 56, 28 => 0000000fffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 56, 35 => 000000001fffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 56, 42 => 00000000003fffff (00000000 00000000)
+ rldicl ffffffffffffffff, 56, 49 => 0000000000007fff (00000000 00000000)
+ rldicl ffffffffffffffff, 56, 56 => 00000000000000ff (00000000 00000000)
+ rldicl ffffffffffffffff, 56, 63 => 0000000000000001 (00000000 00000000)
+ rldicl ffffffffffffffff, 63, 0 => ffffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 63, 7 => 01ffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 63, 14 => 0003ffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 63, 21 => 000007ffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 63, 28 => 0000000fffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 63, 35 => 000000001fffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 63, 42 => 00000000003fffff (00000000 00000000)
+ rldicl ffffffffffffffff, 63, 49 => 0000000000007fff (00000000 00000000)
+ rldicl ffffffffffffffff, 63, 56 => 00000000000000ff (00000000 00000000)
+ rldicl ffffffffffffffff, 63, 63 => 0000000000000001 (00000000 00000000)
+
+ rldicr 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 0, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 0, 14 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 0, 21 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 0, 28 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 0, 35 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 0, 42 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 0, 49 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 0, 56 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 0, 63 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 7, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 7, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 7, 14 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 7, 21 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 7, 28 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 7, 35 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 7, 42 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 7, 49 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 7, 56 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 7, 63 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 14, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 14, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 14, 14 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 14, 21 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 14, 28 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 14, 35 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 14, 42 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 14, 49 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 14, 56 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 14, 63 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 21, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 21, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 21, 14 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 21, 21 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 21, 28 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 21, 35 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 21, 42 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 21, 49 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 21, 56 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 21, 63 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 28, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 28, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 28, 14 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 28, 21 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 28, 28 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 28, 35 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 28, 42 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 28, 49 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 28, 56 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 28, 63 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 35, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 35, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 35, 14 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 35, 21 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 35, 28 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 35, 35 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 35, 42 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 35, 49 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 35, 56 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 35, 63 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 42, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 42, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 42, 14 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 42, 21 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 42, 28 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 42, 35 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 42, 42 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 42, 49 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 42, 56 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 42, 63 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 49, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 49, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 49, 14 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 49, 21 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 49, 28 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 49, 35 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 49, 42 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 49, 49 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 49, 56 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 49, 63 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 56, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 56, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 56, 14 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 56, 21 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 56, 28 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 56, 35 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 56, 42 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 56, 49 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 56, 56 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 56, 63 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 63, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 63, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 63, 14 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 63, 21 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 63, 28 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 63, 35 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 63, 42 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 63, 49 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 63, 56 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 63, 63 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 0, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 0, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 0, 14 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 0, 21 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 0, 28 => 0000001800000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 0, 35 => 0000001cb0000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 0, 42 => 0000001cbe800000 (00000000 00000000)
+ rldicr 0000001cbe991def, 0, 49 => 0000001cbe990000 (00000000 00000000)
+ rldicr 0000001cbe991def, 0, 56 => 0000001cbe991d80 (00000000 00000000)
+ rldicr 0000001cbe991def, 0, 63 => 0000001cbe991def (00000000 00000000)
+ rldicr 0000001cbe991def, 7, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 7, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 7, 14 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 7, 21 => 00000c0000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 7, 28 => 00000e5800000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 7, 35 => 00000e5f40000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 7, 42 => 00000e5f4c800000 (00000000 00000000)
+ rldicr 0000001cbe991def, 7, 49 => 00000e5f4c8ec000 (00000000 00000000)
+ rldicr 0000001cbe991def, 7, 56 => 00000e5f4c8ef780 (00000000 00000000)
+ rldicr 0000001cbe991def, 7, 63 => 00000e5f4c8ef780 (00000000 00000000)
+ rldicr 0000001cbe991def, 14, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 14, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 14, 14 => 0006000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 14, 21 => 00072c0000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 14, 28 => 00072fa000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 14, 35 => 00072fa640000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 14, 42 => 00072fa647600000 (00000000 00000000)
+ rldicr 0000001cbe991def, 14, 49 => 00072fa6477bc000 (00000000 00000000)
+ rldicr 0000001cbe991def, 14, 56 => 00072fa6477bc000 (00000000 00000000)
+ rldicr 0000001cbe991def, 14, 63 => 00072fa6477bc000 (00000000 00000000)
+ rldicr 0000001cbe991def, 21, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 21, 7 => 0300000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 21, 14 => 0396000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 21, 21 => 0397d00000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 21, 28 => 0397d32000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 21, 35 => 0397d323b0000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 21, 42 => 0397d323bde00000 (00000000 00000000)
+ rldicr 0000001cbe991def, 21, 49 => 0397d323bde00000 (00000000 00000000)
+ rldicr 0000001cbe991def, 21, 56 => 0397d323bde00000 (00000000 00000000)
+ rldicr 0000001cbe991def, 21, 63 => 0397d323bde00000 (00000000 00000000)
+ rldicr 0000001cbe991def, 28, 0 => 8000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 28, 7 => cb00000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 28, 14 => cbe8000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 28, 21 => cbe9900000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 28, 28 => cbe991d800000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 28, 35 => cbe991def0000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 28, 42 => cbe991def0000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 28, 49 => cbe991def0000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 28, 56 => cbe991def0000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 28, 63 => cbe991def0000001 (00000000 00000000)
+ rldicr 0000001cbe991def, 35, 0 => 8000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 35, 7 => f400000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 35, 14 => f4c8000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 35, 21 => f4c8ec0000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 35, 28 => f4c8ef7800000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 35, 35 => f4c8ef7800000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 35, 42 => f4c8ef7800000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 35, 49 => f4c8ef7800000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 35, 56 => f4c8ef7800000080 (00000000 00000000)
+ rldicr 0000001cbe991def, 35, 63 => f4c8ef78000000e5 (00000000 00000000)
+ rldicr 0000001cbe991def, 42, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 42, 7 => 6400000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 42, 14 => 6476000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 42, 21 => 6477bc0000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 42, 28 => 6477bc0000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 42, 35 => 6477bc0000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 42, 42 => 6477bc0000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 42, 49 => 6477bc0000004000 (00000000 00000000)
+ rldicr 0000001cbe991def, 42, 56 => 6477bc0000007280 (00000000 00000000)
+ rldicr 0000001cbe991def, 42, 63 => 6477bc00000072fa (00000000 00000000)
+ rldicr 0000001cbe991def, 49, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 49, 7 => 3b00000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 49, 14 => 3bde000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 49, 21 => 3bde000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 49, 28 => 3bde000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 49, 35 => 3bde000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 49, 42 => 3bde000000200000 (00000000 00000000)
+ rldicr 0000001cbe991def, 49, 49 => 3bde000000394000 (00000000 00000000)
+ rldicr 0000001cbe991def, 49, 56 => 3bde000000397d00 (00000000 00000000)
+ rldicr 0000001cbe991def, 49, 63 => 3bde000000397d32 (00000000 00000000)
+ rldicr 0000001cbe991def, 56, 0 => 8000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 56, 7 => ef00000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 56, 14 => ef00000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 56, 21 => ef00000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 56, 28 => ef00000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 56, 35 => ef00000010000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 56, 42 => ef0000001ca00000 (00000000 00000000)
+ rldicr 0000001cbe991def, 56, 49 => ef0000001cbe8000 (00000000 00000000)
+ rldicr 0000001cbe991def, 56, 56 => ef0000001cbe9900 (00000000 00000000)
+ rldicr 0000001cbe991def, 56, 63 => ef0000001cbe991d (00000000 00000000)
+ rldicr 0000001cbe991def, 63, 0 => 8000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 63, 7 => 8000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 63, 14 => 8000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 63, 21 => 8000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 63, 28 => 8000000800000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 63, 35 => 8000000e50000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 63, 42 => 8000000e5f400000 (00000000 00000000)
+ rldicr 0000001cbe991def, 63, 49 => 8000000e5f4c8000 (00000000 00000000)
+ rldicr 0000001cbe991def, 63, 56 => 8000000e5f4c8e80 (00000000 00000000)
+ rldicr 0000001cbe991def, 63, 63 => 8000000e5f4c8ef7 (00000000 00000000)
+ rldicr ffffffffffffffff, 0, 0 => 8000000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 0, 7 => ff00000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 0, 14 => fffe000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 0, 21 => fffffc0000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 0, 28 => fffffff800000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 0, 35 => fffffffff0000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 0, 42 => ffffffffffe00000 (00000000 00000000)
+ rldicr ffffffffffffffff, 0, 49 => ffffffffffffc000 (00000000 00000000)
+ rldicr ffffffffffffffff, 0, 56 => ffffffffffffff80 (00000000 00000000)
+ rldicr ffffffffffffffff, 0, 63 => ffffffffffffffff (00000000 00000000)
+ rldicr ffffffffffffffff, 7, 0 => 8000000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 7, 7 => ff00000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 7, 14 => fffe000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 7, 21 => fffffc0000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 7, 28 => fffffff800000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 7, 35 => fffffffff0000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 7, 42 => ffffffffffe00000 (00000000 00000000)
+ rldicr ffffffffffffffff, 7, 49 => ffffffffffffc000 (00000000 00000000)
+ rldicr ffffffffffffffff, 7, 56 => ffffffffffffff80 (00000000 00000000)
+ rldicr ffffffffffffffff, 7, 63 => ffffffffffffffff (00000000 00000000)
+ rldicr ffffffffffffffff, 14, 0 => 8000000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 14, 7 => ff00000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 14, 14 => fffe000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 14, 21 => fffffc0000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 14, 28 => fffffff800000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 14, 35 => fffffffff0000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 14, 42 => ffffffffffe00000 (00000000 00000000)
+ rldicr ffffffffffffffff, 14, 49 => ffffffffffffc000 (00000000 00000000)
+ rldicr ffffffffffffffff, 14, 56 => ffffffffffffff80 (00000000 00000000)
+ rldicr ffffffffffffffff, 14, 63 => ffffffffffffffff (00000000 00000000)
+ rldicr ffffffffffffffff, 21, 0 => 8000000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 21, 7 => ff00000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 21, 14 => fffe000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 21, 21 => fffffc0000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 21, 28 => fffffff800000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 21, 35 => fffffffff0000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 21, 42 => ffffffffffe00000 (00000000 00000000)
+ rldicr ffffffffffffffff, 21, 49 => ffffffffffffc000 (00000000 00000000)
+ rldicr ffffffffffffffff, 21, 56 => ffffffffffffff80 (00000000 00000000)
+ rldicr ffffffffffffffff, 21, 63 => ffffffffffffffff (00000000 00000000)
+ rldicr ffffffffffffffff, 28, 0 => 8000000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 28, 7 => ff00000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 28, 14 => fffe000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 28, 21 => fffffc0000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 28, 28 => fffffff800000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 28, 35 => fffffffff0000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 28, 42 => ffffffffffe00000 (00000000 00000000)
+ rldicr ffffffffffffffff, 28, 49 => ffffffffffffc000 (00000000 00000000)
+ rldicr ffffffffffffffff, 28, 56 => ffffffffffffff80 (00000000 00000000)
+ rldicr ffffffffffffffff, 28, 63 => ffffffffffffffff (00000000 00000000)
+ rldicr ffffffffffffffff, 35, 0 => 8000000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 35, 7 => ff00000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 35, 14 => fffe000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 35, 21 => fffffc0000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 35, 28 => fffffff800000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 35, 35 => fffffffff0000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 35, 42 => ffffffffffe00000 (00000000 00000000)
+ rldicr ffffffffffffffff, 35, 49 => ffffffffffffc000 (00000000 00000000)
+ rldicr ffffffffffffffff, 35, 56 => ffffffffffffff80 (00000000 00000000)
+ rldicr ffffffffffffffff, 35, 63 => ffffffffffffffff (00000000 00000000)
+ rldicr ffffffffffffffff, 42, 0 => 8000000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 42, 7 => ff00000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 42, 14 => fffe000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 42, 21 => fffffc0000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 42, 28 => fffffff800000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 42, 35 => fffffffff0000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 42, 42 => ffffffffffe00000 (00000000 00000000)
+ rldicr ffffffffffffffff, 42, 49 => ffffffffffffc000 (00000000 00000000)
+ rldicr ffffffffffffffff, 42, 56 => ffffffffffffff80 (00000000 00000000)
+ rldicr ffffffffffffffff, 42, 63 => ffffffffffffffff (00000000 00000000)
+ rldicr ffffffffffffffff, 49, 0 => 8000000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 49, 7 => ff00000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 49, 14 => fffe000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 49, 21 => fffffc0000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 49, 28 => fffffff800000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 49, 35 => fffffffff0000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 49, 42 => ffffffffffe00000 (00000000 00000000)
+ rldicr ffffffffffffffff, 49, 49 => ffffffffffffc000 (00000000 00000000)
+ rldicr ffffffffffffffff, 49, 56 => ffffffffffffff80 (00000000 00000000)
+ rldicr ffffffffffffffff, 49, 63 => ffffffffffffffff (00000000 00000000)
+ rldicr ffffffffffffffff, 56, 0 => 8000000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 56, 7 => ff00000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 56, 14 => fffe000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 56, 21 => fffffc0000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 56, 28 => fffffff800000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 56, 35 => fffffffff0000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 56, 42 => ffffffffffe00000 (00000000 00000000)
+ rldicr ffffffffffffffff, 56, 49 => ffffffffffffc000 (00000000 00000000)
+ rldicr ffffffffffffffff, 56, 56 => ffffffffffffff80 (00000000 00000000)
+ rldicr ffffffffffffffff, 56, 63 => ffffffffffffffff (00000000 00000000)
+ rldicr ffffffffffffffff, 63, 0 => 8000000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 63, 7 => ff00000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 63, 14 => fffe000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 63, 21 => fffffc0000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 63, 28 => fffffff800000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 63, 35 => fffffffff0000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 63, 42 => ffffffffffe00000 (00000000 00000000)
+ rldicr ffffffffffffffff, 63, 49 => ffffffffffffc000 (00000000 00000000)
+ rldicr ffffffffffffffff, 63, 56 => ffffffffffffff80 (00000000 00000000)
+ rldicr ffffffffffffffff, 63, 63 => ffffffffffffffff (00000000 00000000)
+
+ rldimi 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 0, 7 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 0, 14 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 0, 21 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 0, 28 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 0, 35 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 0, 42 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 0, 49 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 0, 56 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 0, 63 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 7, 0 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 7, 7 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 7, 14 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 7, 21 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 7, 28 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 7, 35 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 7, 42 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 7, 49 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 7, 56 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 7, 63 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 14, 0 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 14, 7 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 14, 14 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 14, 21 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 14, 28 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 14, 35 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 14, 42 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 14, 49 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 14, 56 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 14, 63 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 21, 0 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 21, 7 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 21, 14 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 21, 21 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 21, 28 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 21, 35 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 21, 42 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 21, 49 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 21, 56 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 21, 63 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 28, 0 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 28, 7 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 28, 14 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 28, 21 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 28, 28 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 28, 35 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 28, 42 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 28, 49 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 28, 56 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 28, 63 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 35, 0 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 35, 7 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 35, 14 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 35, 21 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 35, 28 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 35, 35 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 35, 42 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 35, 49 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 35, 56 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 35, 63 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 42, 0 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 42, 7 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 42, 14 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 42, 21 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 42, 28 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 42, 35 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 42, 42 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 42, 49 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 42, 56 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 42, 63 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 49, 0 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 49, 7 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 49, 14 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 49, 21 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 49, 28 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 49, 35 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 49, 42 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 49, 49 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 49, 56 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 49, 63 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 56, 0 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 56, 7 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 56, 14 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 56, 21 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 56, 28 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 56, 35 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 56, 42 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 56, 49 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 56, 56 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 56, 63 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 63, 0 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 63, 7 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 63, 14 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 63, 21 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 63, 28 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 63, 35 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 63, 42 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 63, 49 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 63, 56 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 63, 63 => 0000000000000000 (00000000 00000000)
+ rldimi 0000001cbe991def, 0, 0 => 0000001cbe991def (00000000 00000000)
+ rldimi 0000001cbe991def, 0, 7 => 0000001cbe991def (00000000 00000000)
+ rldimi 0000001cbe991def, 0, 14 => 0000001cbe991def (00000000 00000000)
+ rldimi 0000001cbe991def, 0, 21 => 0000001cbe991def (00000000 00000000)
+ rldimi 0000001cbe991def, 0, 28 => 0000001cbe991def (00000000 00000000)
+ rldimi 0000001cbe991def, 0, 35 => 0000001cbe991def (00000000 00000000)
+ rldimi 0000001cbe991def, 0, 42 => 0000001cbe991def (00000000 00000000)
+ rldimi 0000001cbe991def, 0, 49 => 0000001cbe991def (00000000 00000000)
+ rldimi 0000001cbe991def, 0, 56 => 0000001cbe991def (00000000 00000000)
+ rldimi 0000001cbe991def, 0, 63 => 0000001cbe991def (00000000 00000000)
+ rldimi 0000001cbe991def, 7, 0 => 00000e5f4c8ef7ef (00000000 00000000)
+ rldimi 0000001cbe991def, 7, 7 => 00000e5f4c8ef7ef (00000000 00000000)
+ rldimi 0000001cbe991def, 7, 14 => 00000e5f4c8ef7ef (00000000 00000000)
+ rldimi 0000001cbe991def, 7, 21 => 00000e5f4c8ef7ef (00000000 00000000)
+ rldimi 0000001cbe991def, 7, 28 => 00000e5f4c8ef7ef (00000000 00000000)
+ rldimi 0000001cbe991def, 7, 35 => 00000e5f4c8ef7ef (00000000 00000000)
+ rldimi 0000001cbe991def, 7, 42 => 00000e5f4c8ef7ef (00000000 00000000)
+ rldimi 0000001cbe991def, 7, 49 => 00000e5f4c8ef7ef (00000000 00000000)
+ rldimi 0000001cbe991def, 7, 56 => 00000e5f4c8ef7ef (00000000 00000000)
+ rldimi 0000001cbe991def, 7, 63 => 00000e5f4c8ef7ee (00000000 00000000)
+ rldimi 0000001cbe991def, 14, 0 => 00072fa6477bf7ee (00000000 00000000)
+ rldimi 0000001cbe991def, 14, 7 => 00072fa6477bf7ee (00000000 00000000)
+ rldimi 0000001cbe991def, 14, 14 => 00072fa6477bf7ee (00000000 00000000)
+ rldimi 0000001cbe991def, 14, 21 => 00072fa6477bf7ee (00000000 00000000)
+ rldimi 0000001cbe991def, 14, 28 => 00072fa6477bf7ee (00000000 00000000)
+ rldimi 0000001cbe991def, 14, 35 => 00072fa6477bf7ee (00000000 00000000)
+ rldimi 0000001cbe991def, 14, 42 => 00072fa6477bf7ee (00000000 00000000)
+ rldimi 0000001cbe991def, 14, 49 => 00072fa6477bf7ee (00000000 00000000)
+ rldimi 0000001cbe991def, 14, 56 => 00072fa6477bf700 (00000000 00000000)
+ rldimi 0000001cbe991def, 14, 63 => 00072fa6477bf700 (00000000 00000000)
+ rldimi 0000001cbe991def, 21, 0 => 0397d323bdfbf700 (00000000 00000000)
+ rldimi 0000001cbe991def, 21, 7 => 0397d323bdfbf700 (00000000 00000000)
+ rldimi 0000001cbe991def, 21, 14 => 0397d323bdfbf700 (00000000 00000000)
+ rldimi 0000001cbe991def, 21, 21 => 0397d323bdfbf700 (00000000 00000000)
+ rldimi 0000001cbe991def, 21, 28 => 0397d323bdfbf700 (00000000 00000000)
+ rldimi 0000001cbe991def, 21, 35 => 0397d323bdfbf700 (00000000 00000000)
+ rldimi 0000001cbe991def, 21, 42 => 0397d323bdfbf700 (00000000 00000000)
+ rldimi 0000001cbe991def, 21, 49 => 0397d323bdfb8000 (00000000 00000000)
+ rldimi 0000001cbe991def, 21, 56 => 0397d323bdfb8000 (00000000 00000000)
+ rldimi 0000001cbe991def, 21, 63 => 0397d323bdfb8000 (00000000 00000000)
+ rldimi 0000001cbe991def, 28, 0 => cbe991defdfb8000 (00000000 00000000)
+ rldimi 0000001cbe991def, 28, 7 => cbe991defdfb8000 (00000000 00000000)
+ rldimi 0000001cbe991def, 28, 14 => cbe991defdfb8000 (00000000 00000000)
+ rldimi 0000001cbe991def, 28, 21 => cbe991defdfb8000 (00000000 00000000)
+ rldimi 0000001cbe991def, 28, 28 => cbe991defdfb8000 (00000000 00000000)
+ rldimi 0000001cbe991def, 28, 35 => cbe991defdfb8000 (00000000 00000000)
+ rldimi 0000001cbe991def, 28, 42 => cbe991defdc00001 (00000000 00000000)
+ rldimi 0000001cbe991def, 28, 49 => cbe991defdc00001 (00000000 00000000)
+ rldimi 0000001cbe991def, 28, 56 => cbe991defdc00001 (00000000 00000000)
+ rldimi 0000001cbe991def, 28, 63 => cbe991defdc00001 (00000000 00000000)
+ rldimi 0000001cbe991def, 35, 0 => f4c8ef7efdc00001 (00000000 00000000)
+ rldimi 0000001cbe991def, 35, 7 => f4c8ef7efdc00001 (00000000 00000000)
+ rldimi 0000001cbe991def, 35, 14 => f4c8ef7efdc00001 (00000000 00000000)
+ rldimi 0000001cbe991def, 35, 21 => f4c8ef7efdc00001 (00000000 00000000)
+ rldimi 0000001cbe991def, 35, 28 => f4c8ef7efdc00001 (00000000 00000000)
+ rldimi 0000001cbe991def, 35, 35 => f4c8ef7ee00000e5 (00000000 00000000)
+ rldimi 0000001cbe991def, 35, 42 => f4c8ef7ee00000e5 (00000000 00000000)
+ rldimi 0000001cbe991def, 35, 49 => f4c8ef7ee00000e5 (00000000 00000000)
+ rldimi 0000001cbe991def, 35, 56 => f4c8ef7ee00000e5 (00000000 00000000)
+ rldimi 0000001cbe991def, 35, 63 => f4c8ef7ee00000e5 (00000000 00000000)
+ rldimi 0000001cbe991def, 42, 0 => 6477bf7ee00000e5 (00000000 00000000)
+ rldimi 0000001cbe991def, 42, 7 => 6477bf7ee00000e5 (00000000 00000000)
+ rldimi 0000001cbe991def, 42, 14 => 6477bf7ee00000e5 (00000000 00000000)
+ rldimi 0000001cbe991def, 42, 21 => 6477bf7ee00000e5 (00000000 00000000)
+ rldimi 0000001cbe991def, 42, 28 => 6477bf70000072fa (00000000 00000000)
+ rldimi 0000001cbe991def, 42, 35 => 6477bf70000072fa (00000000 00000000)
+ rldimi 0000001cbe991def, 42, 42 => 6477bf70000072fa (00000000 00000000)
+ rldimi 0000001cbe991def, 42, 49 => 6477bf70000072fa (00000000 00000000)
+ rldimi 0000001cbe991def, 42, 56 => 6477bf70000072fa (00000000 00000000)
+ rldimi 0000001cbe991def, 42, 63 => 6477bf70000072fa (00000000 00000000)
+ rldimi 0000001cbe991def, 49, 0 => 3bdfbf70000072fa (00000000 00000000)
+ rldimi 0000001cbe991def, 49, 7 => 3bdfbf70000072fa (00000000 00000000)
+ rldimi 0000001cbe991def, 49, 14 => 3bdfbf70000072fa (00000000 00000000)
+ rldimi 0000001cbe991def, 49, 21 => 3bdfb80000397d32 (00000000 00000000)
+ rldimi 0000001cbe991def, 49, 28 => 3bdfb80000397d32 (00000000 00000000)
+ rldimi 0000001cbe991def, 49, 35 => 3bdfb80000397d32 (00000000 00000000)
+ rldimi 0000001cbe991def, 49, 42 => 3bdfb80000397d32 (00000000 00000000)
+ rldimi 0000001cbe991def, 49, 49 => 3bdfb80000397d32 (00000000 00000000)
+ rldimi 0000001cbe991def, 49, 56 => 3bdfb80000397d32 (00000000 00000000)
+ rldimi 0000001cbe991def, 49, 63 => 3bdfb80000397d32 (00000000 00000000)
+ rldimi 0000001cbe991def, 56, 0 => efdfb80000397d32 (00000000 00000000)
+ rldimi 0000001cbe991def, 56, 7 => efdfb80000397d32 (00000000 00000000)
+ rldimi 0000001cbe991def, 56, 14 => efdc00001cbe991d (00000000 00000000)
+ rldimi 0000001cbe991def, 56, 21 => efdc00001cbe991d (00000000 00000000)
+ rldimi 0000001cbe991def, 56, 28 => efdc00001cbe991d (00000000 00000000)
+ rldimi 0000001cbe991def, 56, 35 => efdc00001cbe991d (00000000 00000000)
+ rldimi 0000001cbe991def, 56, 42 => efdc00001cbe991d (00000000 00000000)
+ rldimi 0000001cbe991def, 56, 49 => efdc00001cbe991d (00000000 00000000)
+ rldimi 0000001cbe991def, 56, 56 => efdc00001cbe991d (00000000 00000000)
+ rldimi 0000001cbe991def, 56, 63 => efdc00001cbe991d (00000000 00000000)
+ rldimi 0000001cbe991def, 63, 0 => efdc00001cbe991d (00000000 00000000)
+ rldimi 0000001cbe991def, 63, 7 => ee00000e5f4c8ef7 (00000000 00000000)
+ rldimi 0000001cbe991def, 63, 14 => ee00000e5f4c8ef7 (00000000 00000000)
+ rldimi 0000001cbe991def, 63, 21 => ee00000e5f4c8ef7 (00000000 00000000)
+ rldimi 0000001cbe991def, 63, 28 => ee00000e5f4c8ef7 (00000000 00000000)
+ rldimi 0000001cbe991def, 63, 35 => ee00000e5f4c8ef7 (00000000 00000000)
+ rldimi 0000001cbe991def, 63, 42 => ee00000e5f4c8ef7 (00000000 00000000)
+ rldimi 0000001cbe991def, 63, 49 => ee00000e5f4c8ef7 (00000000 00000000)
+ rldimi 0000001cbe991def, 63, 56 => ee00000e5f4c8ef7 (00000000 00000000)
+ rldimi 0000001cbe991def, 63, 63 => ee00000e5f4c8ef7 (00000000 00000000)
+ rldimi ffffffffffffffff, 0, 0 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 0, 7 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 0, 14 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 0, 21 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 0, 28 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 0, 35 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 0, 42 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 0, 49 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 0, 56 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 0, 63 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 7, 0 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 7, 7 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 7, 14 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 7, 21 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 7, 28 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 7, 35 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 7, 42 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 7, 49 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 7, 56 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 7, 63 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 14, 0 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 14, 7 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 14, 14 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 14, 21 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 14, 28 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 14, 35 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 14, 42 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 14, 49 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 14, 56 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 14, 63 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 21, 0 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 21, 7 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 21, 14 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 21, 21 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 21, 28 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 21, 35 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 21, 42 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 21, 49 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 21, 56 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 21, 63 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 28, 0 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 28, 7 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 28, 14 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 28, 21 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 28, 28 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 28, 35 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 28, 42 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 28, 49 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 28, 56 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 28, 63 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 35, 0 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 35, 7 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 35, 14 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 35, 21 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 35, 28 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 35, 35 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 35, 42 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 35, 49 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 35, 56 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 35, 63 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 42, 0 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 42, 7 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 42, 14 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 42, 21 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 42, 28 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 42, 35 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 42, 42 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 42, 49 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 42, 56 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 42, 63 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 49, 0 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 49, 7 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 49, 14 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 49, 21 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 49, 28 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 49, 35 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 49, 42 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 49, 49 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 49, 56 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 49, 63 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 56, 0 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 56, 7 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 56, 14 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 56, 21 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 56, 28 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 56, 35 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 56, 42 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 56, 49 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 56, 56 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 56, 63 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 63, 0 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 63, 7 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 63, 14 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 63, 21 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 63, 28 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 63, 35 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 63, 42 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 63, 49 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 63, 56 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 63, 63 => ffffffffffffffff (00000000 00000000)
+
+ sradi 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
+ sradi 0000000000000000, 7 => 0000000000000000 (00000000 00000000)
+ sradi 0000000000000000, 14 => 0000000000000000 (00000000 00000000)
+ sradi 0000000000000000, 21 => 0000000000000000 (00000000 00000000)
+ sradi 0000000000000000, 28 => 0000000000000000 (00000000 00000000)
+ sradi 0000000000000000, 35 => 0000000000000000 (00000000 00000000)
+ sradi 0000000000000000, 42 => 0000000000000000 (00000000 00000000)
+ sradi 0000000000000000, 49 => 0000000000000000 (00000000 00000000)
+ sradi 0000000000000000, 56 => 0000000000000000 (00000000 00000000)
+ sradi 0000000000000000, 63 => 0000000000000000 (00000000 00000000)
+ sradi 0000001cbe991def, 0 => 0000001cbe991def (00000000 00000000)
+ sradi 0000001cbe991def, 7 => 00000000397d323b (00000000 00000000)
+ sradi 0000001cbe991def, 14 => 000000000072fa64 (00000000 00000000)
+ sradi 0000001cbe991def, 21 => 000000000000e5f4 (00000000 00000000)
+ sradi 0000001cbe991def, 28 => 00000000000001cb (00000000 00000000)
+ sradi 0000001cbe991def, 35 => 0000000000000003 (00000000 00000000)
+ sradi 0000001cbe991def, 42 => 0000000000000000 (00000000 00000000)
+ sradi 0000001cbe991def, 49 => 0000000000000000 (00000000 00000000)
+ sradi 0000001cbe991def, 56 => 0000000000000000 (00000000 00000000)
+ sradi 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000)
+ sradi ffffffffffffffff, 0 => ffffffffffffffff (00000000 00000000)
+ sradi ffffffffffffffff, 7 => ffffffffffffffff (00000000 20000000)
+ sradi ffffffffffffffff, 14 => ffffffffffffffff (00000000 20000000)
+ sradi ffffffffffffffff, 21 => ffffffffffffffff (00000000 20000000)
+ sradi ffffffffffffffff, 28 => ffffffffffffffff (00000000 20000000)
+ sradi ffffffffffffffff, 35 => ffffffffffffffff (00000000 20000000)
+ sradi ffffffffffffffff, 42 => ffffffffffffffff (00000000 20000000)
+ sradi ffffffffffffffff, 49 => ffffffffffffffff (00000000 20000000)
+ sradi ffffffffffffffff, 56 => ffffffffffffffff (00000000 20000000)
+ sradi ffffffffffffffff, 63 => ffffffffffffffff (00000000 20000000)
+
+PPC logical insns with special forms with flags update:
+ rlwimi. 0000000000000000, 0, 0, 0 => 0000000000000000 (20000000 00000000)
+ rlwimi. 0000000000000000, 0, 0, 31 => 0000000000000000 (20000000 00000000)
+ rlwimi. 0000000000000000, 0, 31, 0 => 0000000000000000 (20000000 00000000)
+ rlwimi. 0000000000000000, 0, 31, 31 => 0000000000000000 (20000000 00000000)
+ rlwimi. 0000000000000000, 31, 0, 0 => 0000000000000000 (20000000 00000000)
+ rlwimi. 0000000000000000, 31, 0, 31 => 0000000000000000 (20000000 00000000)
+ rlwimi. 0000000000000000, 31, 31, 0 => 0000000000000000 (20000000 00000000)
+ rlwimi. 0000000000000000, 31, 31, 31 => 0000000000000000 (20000000 00000000)
+ rlwimi. 0000001cbe991def, 0, 0, 0 => 0000000080000000 (40000000 00000000)
+ rlwimi. 0000001cbe991def, 0, 0, 31 => 00000000be991def (40000000 00000000)
+ rlwimi. 0000001cbe991def, 0, 31, 0 => be991defbe991def (80000000 00000000)
+ rlwimi. 0000001cbe991def, 0, 31, 31 => be991defbe991def (80000000 00000000)
+ rlwimi. 0000001cbe991def, 31, 0, 0 => be991defbe991def (80000000 00000000)
+ rlwimi. 0000001cbe991def, 31, 0, 31 => be991defdf4c8ef7 (80000000 00000000)
+ rlwimi. 0000001cbe991def, 31, 31, 0 => df4c8ef7df4c8ef7 (80000000 00000000)
+ rlwimi. 0000001cbe991def, 31, 31, 31 => df4c8ef7df4c8ef7 (80000000 00000000)
+ rlwimi. ffffffffffffffff, 0, 0, 0 => df4c8ef7df4c8ef7 (80000000 00000000)
+ rlwimi. ffffffffffffffff, 0, 0, 31 => df4c8ef7ffffffff (80000000 00000000)
+ rlwimi. ffffffffffffffff, 0, 31, 0 => ffffffffffffffff (80000000 00000000)
+ rlwimi. ffffffffffffffff, 0, 31, 31 => ffffffffffffffff (80000000 00000000)
+ rlwimi. ffffffffffffffff, 31, 0, 0 => ffffffffffffffff (80000000 00000000)
+ rlwimi. ffffffffffffffff, 31, 0, 31 => ffffffffffffffff (80000000 00000000)
+ rlwimi. ffffffffffffffff, 31, 31, 0 => ffffffffffffffff (80000000 00000000)
+ rlwimi. ffffffffffffffff, 31, 31, 31 => ffffffffffffffff (80000000 00000000)
+
+ rlwinm. 0000000000000000, 0, 0, 0 => 0000000000000000 (20000000 00000000)
+ rlwinm. 0000000000000000, 0, 0, 31 => 0000000000000000 (20000000 00000000)
+ rlwinm. 0000000000000000, 0, 31, 0 => 0000000000000000 (20000000 00000000)
+ rlwinm. 0000000000000000, 0, 31, 31 => 0000000000000000 (20000000 00000000)
+ rlwinm. 0000000000000000, 31, 0, 0 => 0000000000000000 (20000000 00000000)
+ rlwinm. 0000000000000000, 31, 0, 31 => 0000000000000000 (20000000 00000000)
+ rlwinm. 0000000000000000, 31, 31, 0 => 0000000000000000 (20000000 00000000)
+ rlwinm. 0000000000000000, 31, 31, 31 => 0000000000000000 (20000000 00000000)
+ rlwinm. 0000001cbe991def, 0, 0, 0 => 0000000080000000 (40000000 00000000)
+ rlwinm. 0000001cbe991def, 0, 0, 31 => 00000000be991def (40000000 00000000)
+ rlwinm. 0000001cbe991def, 0, 31, 0 => be991def80000001 (80000000 00000000)
+ rlwinm. 0000001cbe991def, 0, 31, 31 => 0000000000000001 (40000000 00000000)
+ rlwinm. 0000001cbe991def, 31, 0, 0 => 0000000080000000 (40000000 00000000)
+ rlwinm. 0000001cbe991def, 31, 0, 31 => 00000000df4c8ef7 (40000000 00000000)
+ rlwinm. 0000001cbe991def, 31, 31, 0 => df4c8ef780000001 (80000000 00000000)
+ rlwinm. 0000001cbe991def, 31, 31, 31 => 0000000000000001 (40000000 00000000)
+ rlwinm. ffffffffffffffff, 0, 0, 0 => 0000000080000000 (40000000 00000000)
+ rlwinm. ffffffffffffffff, 0, 0, 31 => 00000000ffffffff (40000000 00000000)
+ rlwinm. ffffffffffffffff, 0, 31, 0 => ffffffff80000001 (80000000 00000000)
+ rlwinm. ffffffffffffffff, 0, 31, 31 => 0000000000000001 (40000000 00000000)
+ rlwinm. ffffffffffffffff, 31, 0, 0 => 0000000080000000 (40000000 00000000)
+ rlwinm. ffffffffffffffff, 31, 0, 31 => 00000000ffffffff (40000000 00000000)
+ rlwinm. ffffffffffffffff, 31, 31, 0 => ffffffff80000001 (80000000 00000000)
+ rlwinm. ffffffffffffffff, 31, 31, 31 => 0000000000000001 (40000000 00000000)
+
+ rlwnm. 0000000000000000, 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000000000000000, 0000000000000000, 0, 31 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000000000000000, 0000000000000000, 31, 0 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000000000000000, 0000000000000000, 31, 31 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000000000000000, 0000001cbe991def, 0, 0 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000000000000000, 0000001cbe991def, 0, 31 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000000000000000, 0000001cbe991def, 31, 0 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000000000000000, 0000001cbe991def, 31, 31 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000000000000000, ffffffffffffffff, 0, 0 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000000000000000, ffffffffffffffff, 0, 31 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000000000000000, ffffffffffffffff, 31, 0 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000000000000000, ffffffffffffffff, 31, 31 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000001cbe991def, 0000000000000000, 0, 0 => 0000000080000000 (40000000 00000000)
+ rlwnm. 0000001cbe991def, 0000000000000000, 0, 31 => 00000000be991def (40000000 00000000)
+ rlwnm. 0000001cbe991def, 0000000000000000, 31, 0 => be991def80000001 (80000000 00000000)
+ rlwnm. 0000001cbe991def, 0000000000000000, 31, 31 => 0000000000000001 (40000000 00000000)
+ rlwnm. 0000001cbe991def, 0000001cbe991def, 0, 0 => 0000000080000000 (40000000 00000000)
+ rlwnm. 0000001cbe991def, 0000001cbe991def, 0, 31 => 000000008ef7df4c (40000000 00000000)
+ rlwnm. 0000001cbe991def, 0000001cbe991def, 31, 0 => 8ef7df4c80000000 (80000000 00000000)
+ rlwnm. 0000001cbe991def, 0000001cbe991def, 31, 31 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000001cbe991def, ffffffffffffffff, 0, 0 => 0000000080000000 (40000000 00000000)
+ rlwnm. 0000001cbe991def, ffffffffffffffff, 0, 31 => 00000000df4c8ef7 (40000000 00000000)
+ rlwnm. 0000001cbe991def, ffffffffffffffff, 31, 0 => df4c8ef780000001 (80000000 00000000)
+ rlwnm. 0000001cbe991def, ffffffffffffffff, 31, 31 => 0000000000000001 (40000000 00000000)
+ rlwnm. ffffffffffffffff, 0000000000000000, 0, 0 => 0000000080000000 (40000000 00000000)
+ rlwnm. ffffffffffffffff, 0000000000000000, 0, 31 => 00000000ffffffff (40000000 00000000)
+ rlwnm. ffffffffffffffff, 0000000000000000, 31, 0 => ffffffff80000001 (80000000 00000000)
+ rlwnm. ffffffffffffffff, 0000000000000000, 31, 31 => 0000000000000001 (40000000 00000000)
+ rlwnm. ffffffffffffffff, 0000001cbe991def, 0, 0 => 0000000080000000 (40000000 00000000)
+ rlwnm. ffffffffffffffff, 0000001cbe991def, 0, 31 => 00000000ffffffff (40000000 00000000)
+ rlwnm. ffffffffffffffff, 0000001cbe991def, 31, 0 => ffffffff80000001 (80000000 00000000)
+ rlwnm. ffffffffffffffff, 0000001cbe991def, 31, 31 => 0000000000000001 (40000000 00000000)
+ rlwnm. ffffffffffffffff, ffffffffffffffff, 0, 0 => 0000000080000000 (40000000 00000000)
+ rlwnm. ffffffffffffffff, ffffffffffffffff, 0, 31 => 00000000ffffffff (40000000 00000000)
+ rlwnm. ffffffffffffffff, ffffffffffffffff, 31, 0 => ffffffff80000001 (80000000 00000000)
+ rlwnm. ffffffffffffffff, ffffffffffffffff, 31, 31 => 0000000000000001 (40000000 00000000)
+
+ srawi. 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
+ srawi. 0000000000000000, 31 => 0000000000000000 (20000000 00000000)
+ srawi. 0000001cbe991def, 0 => ffffffffbe991def (80000000 00000000)
+ srawi. 0000001cbe991def, 31 => ffffffffffffffff (80000000 20000000)
+ srawi. ffffffffffffffff, 0 => ffffffffffffffff (80000000 00000000)
+ srawi. ffffffffffffffff, 31 => ffffffffffffffff (80000000 20000000)
+
+ mcrf 0, 0 (0000000000000000) => (00000000 00000000)
+ mcrf 0, 7 (0000000000000000) => (00000000 00000000)
+ mcrf 7, 0 (0000000000000000) => (00000000 00000000)
+ mcrf 7, 7 (0000000000000000) => (00000000 00000000)
+ mcrf 0, 0 (0000001cbe991def) => (be991def 00000000)
+ mcrf 0, 7 (0000001cbe991def) => (fe991def 00000000)
+ mcrf 7, 0 (0000001cbe991def) => (be991deb 00000000)
+ mcrf 7, 7 (0000001cbe991def) => (be991def 00000000)
+ mcrf 0, 0 (ffffffffffffffff) => (ffffffff 00000000)
+ mcrf 0, 7 (ffffffffffffffff) => (ffffffff 00000000)
+ mcrf 7, 0 (ffffffffffffffff) => (ffffffff 00000000)
+ mcrf 7, 7 (ffffffffffffffff) => (ffffffff 00000000)
+
+ mcrxr 0 (00000000) => (00000000 00000000)
+ mcrxr 1 (00000000) => (00000000 00000000)
+ mcrxr 2 (00000000) => (00000000 00000000)
+ mcrxr 3 (00000000) => (00000000 00000000)
+ mcrxr 4 (00000000) => (00000000 00000000)
+ mcrxr 5 (00000000) => (00000000 00000000)
+ mcrxr 6 (00000000) => (00000000 00000000)
+ mcrxr 7 (00000000) => (00000000 00000000)
+ mcrxr 0 (10000000) => (00000000 00000000)
+ mcrxr 1 (10000000) => (00000000 00000000)
+ mcrxr 2 (10000000) => (00000000 00000000)
+ mcrxr 3 (10000000) => (00000000 00000000)
+ mcrxr 4 (10000000) => (00000000 00000000)
+ mcrxr 5 (10000000) => (00000000 00000000)
+ mcrxr 6 (10000000) => (00000000 00000000)
+ mcrxr 7 (10000000) => (00000000 00000000)
+ mcrxr 0 (20000000) => (20000000 00000000)
+ mcrxr 1 (20000000) => (02000000 00000000)
+ mcrxr 2 (20000000) => (00200000 00000000)
+ mcrxr 3 (20000000) => (00020000 00000000)
+ mcrxr 4 (20000000) => (00002000 00000000)
+ mcrxr 5 (20000000) => (00000200 00000000)
+ mcrxr 6 (20000000) => (00000020 00000000)
+ mcrxr 7 (20000000) => (00000002 00000000)
+ mcrxr 0 (30000000) => (20000000 00000000)
+ mcrxr 1 (30000000) => (02000000 00000000)
+ mcrxr 2 (30000000) => (00200000 00000000)
+ mcrxr 3 (30000000) => (00020000 00000000)
+ mcrxr 4 (30000000) => (00002000 00000000)
+ mcrxr 5 (30000000) => (00000200 00000000)
+ mcrxr 6 (30000000) => (00000020 00000000)
+ mcrxr 7 (30000000) => (00000002 00000000)
+ mcrxr 0 (40000000) => (40000000 00000000)
+ mcrxr 1 (40000000) => (04000000 00000000)
+ mcrxr 2 (40000000) => (00400000 00000000)
+ mcrxr 3 (40000000) => (00040000 00000000)
+ mcrxr 4 (40000000) => (00004000 00000000)
+ mcrxr 5 (40000000) => (00000400 00000000)
+ mcrxr 6 (40000000) => (00000040 00000000)
+ mcrxr 7 (40000000) => (00000004 00000000)
+ mcrxr 0 (50000000) => (40000000 00000000)
+ mcrxr 1 (50000000) => (04000000 00000000)
+ mcrxr 2 (50000000) => (00400000 00000000)
+ mcrxr 3 (50000000) => (00040000 00000000)
+ mcrxr 4 (50000000) => (00004000 00000000)
+ mcrxr 5 (50000000) => (00000400 00000000)
+ mcrxr 6 (50000000) => (00000040 00000000)
+ mcrxr 7 (50000000) => (00000004 00000000)
+ mcrxr 0 (60000000) => (60000000 00000000)
+ mcrxr 1 (60000000) => (06000000 00000000)
+ mcrxr 2 (60000000) => (00600000 00000000)
+ mcrxr 3 (60000000) => (00060000 00000000)
+ mcrxr 4 (60000000) => (00006000 00000000)
+ mcrxr 5 (60000000) => (00000600 00000000)
+ mcrxr 6 (60000000) => (00000060 00000000)
+ mcrxr 7 (60000000) => (00000006 00000000)
+ mcrxr 0 (70000000) => (60000000 00000000)
+ mcrxr 1 (70000000) => (06000000 00000000)
+ mcrxr 2 (70000000) => (00600000 00000000)
+ mcrxr 3 (70000000) => (00060000 00000000)
+ mcrxr 4 (70000000) => (00006000 00000000)
+ mcrxr 5 (70000000) => (00000600 00000000)
+ mcrxr 6 (70000000) => (00000060 00000000)
+ mcrxr 7 (70000000) => (00000006 00000000)
+ mcrxr 0 (80000000) => (80000000 00000000)
+ mcrxr 1 (80000000) => (08000000 00000000)
+ mcrxr 2 (80000000) => (00800000 00000000)
+ mcrxr 3 (80000000) => (00080000 00000000)
+ mcrxr 4 (80000000) => (00008000 00000000)
+ mcrxr 5 (80000000) => (00000800 00000000)
+ mcrxr 6 (80000000) => (00000080 00000000)
+ mcrxr 7 (80000000) => (00000008 00000000)
+ mcrxr 0 (90000000) => (80000000 00000000)
+ mcrxr 1 (90000000) => (08000000 00000000)
+ mcrxr 2 (90000000) => (00800000 00000000)
+ mcrxr 3 (90000000) => (00080000 00000000)
+ mcrxr 4 (90000000) => (00008000 00000000)
+ mcrxr 5 (90000000) => (00000800 00000000)
+ mcrxr 6 (90000000) => (00000080 00000000)
+ mcrxr 7 (90000000) => (00000008 00000000)
+ mcrxr 0 (a0000000) => (a0000000 00000000)
+ mcrxr 1 (a0000000) => (0a000000 00000000)
+ mcrxr 2 (a0000000) => (00a00000 00000000)
+ mcrxr 3 (a0000000) => (000a0000 00000000)
+ mcrxr 4 (a0000000) => (0000a000 00000000)
+ mcrxr 5 (a0000000) => (00000a00 00000000)
+ mcrxr 6 (a0000000) => (000000a0 00000000)
+ mcrxr 7 (a0000000) => (0000000a 00000000)
+ mcrxr 0 (b0000000) => (a0000000 00000000)
+ mcrxr 1 (b0000000) => (0a000000 00000000)
+ mcrxr 2 (b0000000) => (00a00000 00000000)
+ mcrxr 3 (b0000000) => (000a0000 00000000)
+ mcrxr 4 (b0000000) => (0000a000 00000000)
+ mcrxr 5 (b0000000) => (00000a00 00000000)
+ mcrxr 6 (b0000000) => (000000a0 00000000)
+ mcrxr 7 (b0000000) => (0000000a 00000000)
+ mcrxr 0 (c0000000) => (c0000000 00000000)
+ mcrxr 1 (c0000000) => (0c000000 00000000)
+ mcrxr 2 (c0000000) => (00c00000 00000000)
+ mcrxr 3 (c0000000) => (000c0000 00000000)
+ mcrxr 4 (c0000000) => (0000c000 00000000)
+ mcrxr 5 (c0000000) => (00000c00 00000000)
+ mcrxr 6 (c0000000) => (000000c0 00000000)
+ mcrxr 7 (c0000000) => (0000000c 00000000)
+ mcrxr 0 (d0000000) => (c0000000 00000000)
+ mcrxr 1 (d0000000) => (0c000000 00000000)
+ mcrxr 2 (d0000000) => (00c00000 00000000)
+ mcrxr 3 (d0000000) => (000c0000 00000000)
+ mcrxr 4 (d0000000) => (0000c000 00000000)
+ mcrxr 5 (d0000000) => (00000c00 00000000)
+ mcrxr 6 (d0000000) => (000000c0 00000000)
+ mcrxr 7 (d0000000) => (0000000c 00000000)
+ mcrxr 0 (e0000000) => (e0000000 00000000)
+ mcrxr 1 (e0000000) => (0e000000 00000000)
+ mcrxr 2 (e0000000) => (00e00000 00000000)
+ mcrxr 3 (e0000000) => (000e0000 00000000)
+ mcrxr 4 (e0000000) => (0000e000 00000000)
+ mcrxr 5 (e0000000) => (00000e00 00000000)
+ mcrxr 6 (e0000000) => (000000e0 00000000)
+ mcrxr 7 (e0000000) => (0000000e 00000000)
+ mcrxr 0 (f0000000) => (e0000000 00000000)
+ mcrxr 1 (f0000000) => (0e000000 00000000)
+ mcrxr 2 (f0000000) => (00e00000 00000000)
+ mcrxr 3 (f0000000) => (000e0000 00000000)
+ mcrxr 4 (f0000000) => (0000e000 00000000)
+ mcrxr 5 (f0000000) => (00000e00 00000000)
+ mcrxr 6 (f0000000) => (000000e0 00000000)
+ mcrxr 7 (f0000000) => (0000000e 00000000)
+
+ mtcrf 0, 0000000000000000 => (00000000 00000000)
+ mtcrf 99, 0000000000000000 => (00000000 00000000)
+ mtcrf 198, 0000000000000000 => (00000000 00000000)
+ mtcrf 0, 0000001cbe991def => (00000000 00000000)
+ mtcrf 99, 0000001cbe991def => (0e9000ef 00000000)
+ mtcrf 198, 0000001cbe991def => (be000de0 00000000)
+ mtcrf 0, ffffffffffffffff => (00000000 00000000)
+ mtcrf 99, ffffffffffffffff => (0ff000ff 00000000)
+ mtcrf 198, ffffffffffffffff => (ff000ff0 00000000)
+
+ rldcl. 0000000000000000, 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000000000000000, 7 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000000000000000, 14 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000000000000000, 21 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000000000000000, 28 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000000000000000, 35 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000000000000000, 42 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000000000000000, 49 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000000000000000, 56 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000000000000000, 63 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000001cbe991def, 0 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000001cbe991def, 7 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000001cbe991def, 14 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000001cbe991def, 21 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000001cbe991def, 28 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000001cbe991def, 35 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000001cbe991def, 42 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000001cbe991def, 49 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000001cbe991def, 56 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, ffffffffffffffff, 0 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, ffffffffffffffff, 7 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, ffffffffffffffff, 14 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, ffffffffffffffff, 21 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, ffffffffffffffff, 28 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, ffffffffffffffff, 35 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, ffffffffffffffff, 42 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, ffffffffffffffff, 49 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, ffffffffffffffff, 56 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, ffffffffffffffff, 63 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000001cbe991def, 0000000000000000, 0 => 0000001cbe991def (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000000000000000, 7 => 0000001cbe991def (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000000000000000, 14 => 0000001cbe991def (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000000000000000, 21 => 0000001cbe991def (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000000000000000, 28 => 0000000cbe991def (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000000000000000, 35 => 000000001e991def (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000000000000000, 42 => 0000000000191def (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000000000000000, 49 => 0000000000001def (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000000000000000, 56 => 00000000000000ef (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000000000000000, 63 => 0000000000000001 (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000001cbe991def, 0 => 8ef78000000e5f4c (80000000 00000000)
+ rldcl. 0000001cbe991def, 0000001cbe991def, 7 => 00f78000000e5f4c (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000001cbe991def, 14 => 00038000000e5f4c (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000001cbe991def, 21 => 00000000000e5f4c (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000001cbe991def, 28 => 00000000000e5f4c (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000001cbe991def, 35 => 00000000000e5f4c (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000001cbe991def, 42 => 00000000000e5f4c (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000001cbe991def, 49 => 0000000000005f4c (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000001cbe991def, 56 => 000000000000004c (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000001cbe991def, ffffffffffffffff, 0 => 8000000e5f4c8ef7 (80000000 00000000)
+ rldcl. 0000001cbe991def, ffffffffffffffff, 7 => 0000000e5f4c8ef7 (40000000 00000000)
+ rldcl. 0000001cbe991def, ffffffffffffffff, 14 => 0000000e5f4c8ef7 (40000000 00000000)
+ rldcl. 0000001cbe991def, ffffffffffffffff, 21 => 0000000e5f4c8ef7 (40000000 00000000)
+ rldcl. 0000001cbe991def, ffffffffffffffff, 28 => 0000000e5f4c8ef7 (40000000 00000000)
+ rldcl. 0000001cbe991def, ffffffffffffffff, 35 => 000000001f4c8ef7 (40000000 00000000)
+ rldcl. 0000001cbe991def, ffffffffffffffff, 42 => 00000000000c8ef7 (40000000 00000000)
+ rldcl. 0000001cbe991def, ffffffffffffffff, 49 => 0000000000000ef7 (40000000 00000000)
+ rldcl. 0000001cbe991def, ffffffffffffffff, 56 => 00000000000000f7 (40000000 00000000)
+ rldcl. 0000001cbe991def, ffffffffffffffff, 63 => 0000000000000001 (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000000000000000, 0 => ffffffffffffffff (80000000 00000000)
+ rldcl. ffffffffffffffff, 0000000000000000, 7 => 01ffffffffffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000000000000000, 14 => 0003ffffffffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000000000000000, 21 => 000007ffffffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000000000000000, 28 => 0000000fffffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000000000000000, 35 => 000000001fffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000000000000000, 42 => 00000000003fffff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000000000000000, 49 => 0000000000007fff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000000000000000, 56 => 00000000000000ff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000000000000000, 63 => 0000000000000001 (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000001cbe991def, 0 => ffffffffffffffff (80000000 00000000)
+ rldcl. ffffffffffffffff, 0000001cbe991def, 7 => 01ffffffffffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000001cbe991def, 14 => 0003ffffffffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000001cbe991def, 21 => 000007ffffffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000001cbe991def, 28 => 0000000fffffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000001cbe991def, 35 => 000000001fffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000001cbe991def, 42 => 00000000003fffff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000001cbe991def, 49 => 0000000000007fff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000001cbe991def, 56 => 00000000000000ff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000001cbe991def, 63 => 0000000000000001 (40000000 00000000)
+ rldcl. ffffffffffffffff, ffffffffffffffff, 0 => ffffffffffffffff (80000000 00000000)
+ rldcl. ffffffffffffffff, ffffffffffffffff, 7 => 01ffffffffffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, ffffffffffffffff, 14 => 0003ffffffffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, ffffffffffffffff, 21 => 000007ffffffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, ffffffffffffffff, 28 => 0000000fffffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, ffffffffffffffff, 35 => 000000001fffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, ffffffffffffffff, 42 => 00000000003fffff (40000000 00000000)
+ rldcl. ffffffffffffffff, ffffffffffffffff, 49 => 0000000000007fff (40000000 00000000)
+ rldcl. ffffffffffffffff, ffffffffffffffff, 56 => 00000000000000ff (40000000 00000000)
+ rldcl. ffffffffffffffff, ffffffffffffffff, 63 => 0000000000000001 (40000000 00000000)
+
+ rldcr. 0000000000000000, 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000000000000000, 7 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000000000000000, 14 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000000000000000, 21 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000000000000000, 28 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000000000000000, 35 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000000000000000, 42 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000000000000000, 49 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000000000000000, 56 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000000000000000, 63 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000001cbe991def, 0 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000001cbe991def, 7 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000001cbe991def, 14 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000001cbe991def, 21 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000001cbe991def, 28 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000001cbe991def, 35 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000001cbe991def, 42 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000001cbe991def, 49 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000001cbe991def, 56 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, ffffffffffffffff, 0 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, ffffffffffffffff, 7 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, ffffffffffffffff, 14 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, ffffffffffffffff, 21 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, ffffffffffffffff, 28 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, ffffffffffffffff, 35 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, ffffffffffffffff, 42 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, ffffffffffffffff, 49 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, ffffffffffffffff, 56 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, ffffffffffffffff, 63 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000001cbe991def, 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000001cbe991def, 0000000000000000, 7 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000001cbe991def, 0000000000000000, 14 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000001cbe991def, 0000000000000000, 21 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000001cbe991def, 0000000000000000, 28 => 0000001800000000 (40000000 00000000)
+ rldcr. 0000001cbe991def, 0000000000000000, 35 => 0000001cb0000000 (40000000 00000000)
+ rldcr. 0000001cbe991def, 0000000000000000, 42 => 0000001cbe800000 (40000000 00000000)
+ rldcr. 0000001cbe991def, 0000000000000000, 49 => 0000001cbe990000 (40000000 00000000)
+ rldcr. 0000001cbe991def, 0000000000000000, 56 => 0000001cbe991d80 (40000000 00000000)
+ rldcr. 0000001cbe991def, 0000000000000000, 63 => 0000001cbe991def (40000000 00000000)
+ rldcr. 0000001cbe991def, 0000001cbe991def, 0 => 8000000000000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, 0000001cbe991def, 7 => 8e00000000000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, 0000001cbe991def, 14 => 8ef6000000000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, 0000001cbe991def, 21 => 8ef7800000000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, 0000001cbe991def, 28 => 8ef7800000000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, 0000001cbe991def, 35 => 8ef7800000000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, 0000001cbe991def, 42 => 8ef7800000000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, 0000001cbe991def, 49 => 8ef78000000e4000 (80000000 00000000)
+ rldcr. 0000001cbe991def, 0000001cbe991def, 56 => 8ef78000000e5f00 (80000000 00000000)
+ rldcr. 0000001cbe991def, 0000001cbe991def, 63 => 8ef78000000e5f4c (80000000 00000000)
+ rldcr. 0000001cbe991def, ffffffffffffffff, 0 => 8000000000000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, ffffffffffffffff, 7 => 8000000000000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, ffffffffffffffff, 14 => 8000000000000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, ffffffffffffffff, 21 => 8000000000000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, ffffffffffffffff, 28 => 8000000800000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, ffffffffffffffff, 35 => 8000000e50000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, ffffffffffffffff, 42 => 8000000e5f400000 (80000000 00000000)
+ rldcr. 0000001cbe991def, ffffffffffffffff, 49 => 8000000e5f4c8000 (80000000 00000000)
+ rldcr. 0000001cbe991def, ffffffffffffffff, 56 => 8000000e5f4c8e80 (80000000 00000000)
+ rldcr. 0000001cbe991def, ffffffffffffffff, 63 => 8000000e5f4c8ef7 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000000000000000, 0 => 8000000000000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000000000000000, 7 => ff00000000000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000000000000000, 14 => fffe000000000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000000000000000, 21 => fffffc0000000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000000000000000, 28 => fffffff800000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000000000000000, 35 => fffffffff0000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000000000000000, 42 => ffffffffffe00000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000000000000000, 49 => ffffffffffffc000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000000000000000, 56 => ffffffffffffff80 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000000000000000, 63 => ffffffffffffffff (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000001cbe991def, 0 => 8000000000000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000001cbe991def, 7 => ff00000000000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000001cbe991def, 14 => fffe000000000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000001cbe991def, 21 => fffffc0000000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000001cbe991def, 28 => fffffff800000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000001cbe991def, 35 => fffffffff0000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000001cbe991def, 42 => ffffffffffe00000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000001cbe991def, 49 => ffffffffffffc000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000001cbe991def, 56 => ffffffffffffff80 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000001cbe991def, 63 => ffffffffffffffff (80000000 00000000)
+ rldcr. ffffffffffffffff, ffffffffffffffff, 0 => 8000000000000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, ffffffffffffffff, 7 => ff00000000000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, ffffffffffffffff, 14 => fffe000000000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, ffffffffffffffff, 21 => fffffc0000000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, ffffffffffffffff, 28 => fffffff800000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, ffffffffffffffff, 35 => fffffffff0000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, ffffffffffffffff, 42 => ffffffffffe00000 (80000000 00000000)
+ rldcr. ffffffffffffffff, ffffffffffffffff, 49 => ffffffffffffc000 (80000000 00000000)
+ rldcr. ffffffffffffffff, ffffffffffffffff, 56 => ffffffffffffff80 (80000000 00000000)
+ rldcr. ffffffffffffffff, ffffffffffffffff, 63 => ffffffffffffffff (80000000 00000000)
+
+ rldic. 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 0, 7 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 0, 14 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 0, 21 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 0, 28 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 0, 35 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 0, 42 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 0, 49 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 0, 56 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 0, 63 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 7, 0 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 7, 7 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 7, 14 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 7, 21 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 7, 28 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 7, 35 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 7, 42 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 7, 49 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 7, 56 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 7, 63 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 14, 0 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 14, 7 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 14, 14 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 14, 21 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 14, 28 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 14, 35 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 14, 42 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 14, 49 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 14, 56 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 14, 63 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 21, 0 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 21, 7 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 21, 14 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 21, 21 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 21, 28 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 21, 35 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 21, 42 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 21, 49 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 21, 56 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 21, 63 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 28, 0 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 28, 7 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 28, 14 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 28, 21 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 28, 28 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 28, 35 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 28, 42 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 28, 49 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 28, 56 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 28, 63 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 35, 0 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 35, 7 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 35, 14 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 35, 21 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 35, 28 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 35, 35 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 35, 42 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 35, 49 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 35, 56 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 35, 63 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 42, 0 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 42, 7 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 42, 14 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 42, 21 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 42, 28 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 42, 35 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 42, 42 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 42, 49 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 42, 56 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 42, 63 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 49, 0 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 49, 7 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 49, 14 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 49, 21 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 49, 28 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 49, 35 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 49, 42 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 49, 49 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 49, 56 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 49, 63 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 56, 0 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 56, 7 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 56, 14 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 56, 21 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 56, 28 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 56, 35 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 56, 42 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 56, 49 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 56, 56 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 56, 63 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 63, 0 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 63, 7 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 63, 14 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 63, 21 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 63, 28 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 63, 35 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 63, 42 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 63, 49 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 63, 56 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 63, 63 => 0000000000000000 (20000000 00000000)
+ rldic. 0000001cbe991def, 0, 0 => 0000001cbe991def (40000000 00000000)
+ rldic. 0000001cbe991def, 0, 7 => 0000001cbe991def (40000000 00000000)
+ rldic. 0000001cbe991def, 0, 14 => 0000001cbe991def (40000000 00000000)
+ rldic. 0000001cbe991def, 0, 21 => 0000001cbe991def (40000000 00000000)
+ rldic. 0000001cbe991def, 0, 28 => 0000000cbe991def (40000000 00000000)
+ rldic. 0000001cbe991def, 0, 35 => 000000001e991def (40000000 00000000)
+ rldic. 0000001cbe991def, 0, 42 => 0000000000191def (40000000 00000000)
+ rldic. 0000001cbe991def, 0, 49 => 0000000000001def (40000000 00000000)
+ rldic. 0000001cbe991def, 0, 56 => 00000000000000ef (40000000 00000000)
+ rldic. 0000001cbe991def, 0, 63 => 0000000000000001 (40000000 00000000)
+ rldic. 0000001cbe991def, 7, 0 => 00000e5f4c8ef780 (40000000 00000000)
+ rldic. 0000001cbe991def, 7, 7 => 00000e5f4c8ef780 (40000000 00000000)
+ rldic. 0000001cbe991def, 7, 14 => 00000e5f4c8ef780 (40000000 00000000)
+ rldic. 0000001cbe991def, 7, 21 => 0000065f4c8ef780 (40000000 00000000)
+ rldic. 0000001cbe991def, 7, 28 => 0000000f4c8ef780 (40000000 00000000)
+ rldic. 0000001cbe991def, 7, 35 => 000000000c8ef780 (40000000 00000000)
+ rldic. 0000001cbe991def, 7, 42 => 00000000000ef780 (40000000 00000000)
+ rldic. 0000001cbe991def, 7, 49 => 0000000000007780 (40000000 00000000)
+ rldic. 0000001cbe991def, 7, 56 => 0000000000000080 (40000000 00000000)
+ rldic. 0000001cbe991def, 7, 63 => 00000e5f4c8ef780 (40000000 00000000)
+ rldic. 0000001cbe991def, 14, 0 => 00072fa6477bc000 (40000000 00000000)
+ rldic. 0000001cbe991def, 14, 7 => 00072fa6477bc000 (40000000 00000000)
+ rldic. 0000001cbe991def, 14, 14 => 00032fa6477bc000 (40000000 00000000)
+ rldic. 0000001cbe991def, 14, 21 => 000007a6477bc000 (40000000 00000000)
+ rldic. 0000001cbe991def, 14, 28 => 00000006477bc000 (40000000 00000000)
+ rldic. 0000001cbe991def, 14, 35 => 00000000077bc000 (40000000 00000000)
+ rldic. 0000001cbe991def, 14, 42 => 00000000003bc000 (40000000 00000000)
+ rldic. 0000001cbe991def, 14, 49 => 0000000000004000 (40000000 00000000)
+ rldic. 0000001cbe991def, 14, 56 => 00072fa6477bc000 (40000000 00000000)
+ rldic. 0000001cbe991def, 14, 63 => 00072fa6477bc000 (40000000 00000000)
+ rldic. 0000001cbe991def, 21, 0 => 0397d323bde00000 (40000000 00000000)
+ rldic. 0000001cbe991def, 21, 7 => 0197d323bde00000 (40000000 00000000)
+ rldic. 0000001cbe991def, 21, 14 => 0003d323bde00000 (40000000 00000000)
+ rldic. 0000001cbe991def, 21, 21 => 00000323bde00000 (40000000 00000000)
+ rldic. 0000001cbe991def, 21, 28 => 00000003bde00000 (40000000 00000000)
+ rldic. 0000001cbe991def, 21, 35 => 000000001de00000 (40000000 00000000)
+ rldic. 0000001cbe991def, 21, 42 => 0000000000200000 (40000000 00000000)
+ rldic. 0000001cbe991def, 21, 49 => 0397d323bde00000 (40000000 00000000)
+ rldic. 0000001cbe991def, 21, 56 => 0397d323bde00000 (40000000 00000000)
+ rldic. 0000001cbe991def, 21, 63 => 0397d323bde00000 (40000000 00000000)
+ rldic. 0000001cbe991def, 28, 0 => cbe991def0000000 (80000000 00000000)
+ rldic. 0000001cbe991def, 28, 7 => 01e991def0000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 28, 14 => 000191def0000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 28, 21 => 000001def0000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 28, 28 => 0000000ef0000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 28, 35 => 0000000010000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 28, 42 => cbe991def0000001 (80000000 00000000)
+ rldic. 0000001cbe991def, 28, 49 => cbe991def0000001 (80000000 00000000)
+ rldic. 0000001cbe991def, 28, 56 => cbe991def0000001 (80000000 00000000)
+ rldic. 0000001cbe991def, 28, 63 => cbe991def0000001 (80000000 00000000)
+ rldic. 0000001cbe991def, 35, 0 => f4c8ef7800000000 (80000000 00000000)
+ rldic. 0000001cbe991def, 35, 7 => 00c8ef7800000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 35, 14 => 0000ef7800000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 35, 21 => 0000077800000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 35, 28 => 0000000800000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 35, 35 => f4c8ef78000000e5 (80000000 00000000)
+ rldic. 0000001cbe991def, 35, 42 => f4c8ef78000000e5 (80000000 00000000)
+ rldic. 0000001cbe991def, 35, 49 => f4c8ef78000000e5 (80000000 00000000)
+ rldic. 0000001cbe991def, 35, 56 => f4c8ef78000000e5 (80000000 00000000)
+ rldic. 0000001cbe991def, 35, 63 => f4c8ef7800000001 (80000000 00000000)
+ rldic. 0000001cbe991def, 42, 0 => 6477bc0000000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 42, 7 => 0077bc0000000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 42, 14 => 0003bc0000000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 42, 21 => 0000040000000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 42, 28 => 6477bc00000072fa (40000000 00000000)
+ rldic. 0000001cbe991def, 42, 35 => 6477bc00000072fa (40000000 00000000)
+ rldic. 0000001cbe991def, 42, 42 => 6477bc00000072fa (40000000 00000000)
+ rldic. 0000001cbe991def, 42, 49 => 6477bc00000072fa (40000000 00000000)
+ rldic. 0000001cbe991def, 42, 56 => 6477bc00000000fa (40000000 00000000)
+ rldic. 0000001cbe991def, 42, 63 => 6477bc0000000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 49, 0 => 3bde000000000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 49, 7 => 01de000000000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 49, 14 => 0002000000000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 49, 21 => 3bde000000397d32 (40000000 00000000)
+ rldic. 0000001cbe991def, 49, 28 => 3bde000000397d32 (40000000 00000000)
+ rldic. 0000001cbe991def, 49, 35 => 3bde000000397d32 (40000000 00000000)
+ rldic. 0000001cbe991def, 49, 42 => 3bde000000397d32 (40000000 00000000)
+ rldic. 0000001cbe991def, 49, 49 => 3bde000000007d32 (40000000 00000000)
+ rldic. 0000001cbe991def, 49, 56 => 3bde000000000032 (40000000 00000000)
+ rldic. 0000001cbe991def, 49, 63 => 3bde000000000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 56, 0 => ef00000000000000 (80000000 00000000)
+ rldic. 0000001cbe991def, 56, 7 => 0100000000000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 56, 14 => ef0000001cbe991d (80000000 00000000)
+ rldic. 0000001cbe991def, 56, 21 => ef0000001cbe991d (80000000 00000000)
+ rldic. 0000001cbe991def, 56, 28 => ef0000001cbe991d (80000000 00000000)
+ rldic. 0000001cbe991def, 56, 35 => ef0000001cbe991d (80000000 00000000)
+ rldic. 0000001cbe991def, 56, 42 => ef000000003e991d (80000000 00000000)
+ rldic. 0000001cbe991def, 56, 49 => ef0000000000191d (80000000 00000000)
+ rldic. 0000001cbe991def, 56, 56 => ef0000000000001d (80000000 00000000)
+ rldic. 0000001cbe991def, 56, 63 => ef00000000000001 (80000000 00000000)
+ rldic. 0000001cbe991def, 63, 0 => 8000000000000000 (80000000 00000000)
+ rldic. 0000001cbe991def, 63, 7 => 8000000e5f4c8ef7 (80000000 00000000)
+ rldic. 0000001cbe991def, 63, 14 => 8000000e5f4c8ef7 (80000000 00000000)
+ rldic. 0000001cbe991def, 63, 21 => 8000000e5f4c8ef7 (80000000 00000000)
+ rldic. 0000001cbe991def, 63, 28 => 8000000e5f4c8ef7 (80000000 00000000)
+ rldic. 0000001cbe991def, 63, 35 => 800000001f4c8ef7 (80000000 00000000)
+ rldic. 0000001cbe991def, 63, 42 => 80000000000c8ef7 (80000000 00000000)
+ rldic. 0000001cbe991def, 63, 49 => 8000000000000ef7 (80000000 00000000)
+ rldic. 0000001cbe991def, 63, 56 => 80000000000000f7 (80000000 00000000)
+ rldic. 0000001cbe991def, 63, 63 => 8000000000000001 (80000000 00000000)
+ rldic. ffffffffffffffff, 0, 0 => ffffffffffffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 0, 7 => 01ffffffffffffff (40000000 00000000)
+ rldic. ffffffffffffffff, 0, 14 => 0003ffffffffffff (40000000 00000000)
+ rldic. ffffffffffffffff, 0, 21 => 000007ffffffffff (40000000 00000000)
+ rldic. ffffffffffffffff, 0, 28 => 0000000fffffffff (40000000 00000000)
+ rldic. ffffffffffffffff, 0, 35 => 000000001fffffff (40000000 00000000)
+ rldic. ffffffffffffffff, 0, 42 => 00000000003fffff (40000000 00000000)
+ rldic. ffffffffffffffff, 0, 49 => 0000000000007fff (40000000 00000000)
+ rldic. ffffffffffffffff, 0, 56 => 00000000000000ff (40000000 00000000)
+ rldic. ffffffffffffffff, 0, 63 => 0000000000000001 (40000000 00000000)
+ rldic. ffffffffffffffff, 7, 0 => ffffffffffffff80 (80000000 00000000)
+ rldic. ffffffffffffffff, 7, 7 => 01ffffffffffff80 (40000000 00000000)
+ rldic. ffffffffffffffff, 7, 14 => 0003ffffffffff80 (40000000 00000000)
+ rldic. ffffffffffffffff, 7, 21 => 000007ffffffff80 (40000000 00000000)
+ rldic. ffffffffffffffff, 7, 28 => 0000000fffffff80 (40000000 00000000)
+ rldic. ffffffffffffffff, 7, 35 => 000000001fffff80 (40000000 00000000)
+ rldic. ffffffffffffffff, 7, 42 => 00000000003fff80 (40000000 00000000)
+ rldic. ffffffffffffffff, 7, 49 => 0000000000007f80 (40000000 00000000)
+ rldic. ffffffffffffffff, 7, 56 => 0000000000000080 (40000000 00000000)
+ rldic. ffffffffffffffff, 7, 63 => ffffffffffffff81 (80000000 00000000)
+ rldic. ffffffffffffffff, 14, 0 => ffffffffffffc000 (80000000 00000000)
+ rldic. ffffffffffffffff, 14, 7 => 01ffffffffffc000 (40000000 00000000)
+ rldic. ffffffffffffffff, 14, 14 => 0003ffffffffc000 (40000000 00000000)
+ rldic. ffffffffffffffff, 14, 21 => 000007ffffffc000 (40000000 00000000)
+ rldic. ffffffffffffffff, 14, 28 => 0000000fffffc000 (40000000 00000000)
+ rldic. ffffffffffffffff, 14, 35 => 000000001fffc000 (40000000 00000000)
+ rldic. ffffffffffffffff, 14, 42 => 00000000003fc000 (40000000 00000000)
+ rldic. ffffffffffffffff, 14, 49 => 0000000000004000 (40000000 00000000)
+ rldic. ffffffffffffffff, 14, 56 => ffffffffffffc0ff (80000000 00000000)
+ rldic. ffffffffffffffff, 14, 63 => ffffffffffffc001 (80000000 00000000)
+ rldic. ffffffffffffffff, 21, 0 => ffffffffffe00000 (80000000 00000000)
+ rldic. ffffffffffffffff, 21, 7 => 01ffffffffe00000 (40000000 00000000)
+ rldic. ffffffffffffffff, 21, 14 => 0003ffffffe00000 (40000000 00000000)
+ rldic. ffffffffffffffff, 21, 21 => 000007ffffe00000 (40000000 00000000)
+ rldic. ffffffffffffffff, 21, 28 => 0000000fffe00000 (40000000 00000000)
+ rldic. ffffffffffffffff, 21, 35 => 000000001fe00000 (40000000 00000000)
+ rldic. ffffffffffffffff, 21, 42 => 0000000000200000 (40000000 00000000)
+ rldic. ffffffffffffffff, 21, 49 => ffffffffffe07fff (80000000 00000000)
+ rldic. ffffffffffffffff, 21, 56 => ffffffffffe000ff (80000000 00000000)
+ rldic. ffffffffffffffff, 21, 63 => ffffffffffe00001 (80000000 00000000)
+ rldic. ffffffffffffffff, 28, 0 => fffffffff0000000 (80000000 00000000)
+ rldic. ffffffffffffffff, 28, 7 => 01fffffff0000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 28, 14 => 0003fffff0000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 28, 21 => 000007fff0000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 28, 28 => 0000000ff0000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 28, 35 => 0000000010000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 28, 42 => fffffffff03fffff (80000000 00000000)
+ rldic. ffffffffffffffff, 28, 49 => fffffffff0007fff (80000000 00000000)
+ rldic. ffffffffffffffff, 28, 56 => fffffffff00000ff (80000000 00000000)
+ rldic. ffffffffffffffff, 28, 63 => fffffffff0000001 (80000000 00000000)
+ rldic. ffffffffffffffff, 35, 0 => fffffff800000000 (80000000 00000000)
+ rldic. ffffffffffffffff, 35, 7 => 01fffff800000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 35, 14 => 0003fff800000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 35, 21 => 000007f800000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 35, 28 => 0000000800000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 35, 35 => fffffff81fffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 35, 42 => fffffff8003fffff (80000000 00000000)
+ rldic. ffffffffffffffff, 35, 49 => fffffff800007fff (80000000 00000000)
+ rldic. ffffffffffffffff, 35, 56 => fffffff8000000ff (80000000 00000000)
+ rldic. ffffffffffffffff, 35, 63 => fffffff800000001 (80000000 00000000)
+ rldic. ffffffffffffffff, 42, 0 => fffffc0000000000 (80000000 00000000)
+ rldic. ffffffffffffffff, 42, 7 => 01fffc0000000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 42, 14 => 0003fc0000000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 42, 21 => 0000040000000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 42, 28 => fffffc0fffffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 42, 35 => fffffc001fffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 42, 42 => fffffc00003fffff (80000000 00000000)
+ rldic. ffffffffffffffff, 42, 49 => fffffc0000007fff (80000000 00000000)
+ rldic. ffffffffffffffff, 42, 56 => fffffc00000000ff (80000000 00000000)
+ rldic. ffffffffffffffff, 42, 63 => fffffc0000000001 (80000000 00000000)
+ rldic. ffffffffffffffff, 49, 0 => fffe000000000000 (80000000 00000000)
+ rldic. ffffffffffffffff, 49, 7 => 01fe000000000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 49, 14 => 0002000000000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 49, 21 => fffe07ffffffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 49, 28 => fffe000fffffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 49, 35 => fffe00001fffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 49, 42 => fffe0000003fffff (80000000 00000000)
+ rldic. ffffffffffffffff, 49, 49 => fffe000000007fff (80000000 00000000)
+ rldic. ffffffffffffffff, 49, 56 => fffe0000000000ff (80000000 00000000)
+ rldic. ffffffffffffffff, 49, 63 => fffe000000000001 (80000000 00000000)
+ rldic. ffffffffffffffff, 56, 0 => ff00000000000000 (80000000 00000000)
+ rldic. ffffffffffffffff, 56, 7 => 0100000000000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 56, 14 => ff03ffffffffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 56, 21 => ff0007ffffffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 56, 28 => ff00000fffffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 56, 35 => ff0000001fffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 56, 42 => ff000000003fffff (80000000 00000000)
+ rldic. ffffffffffffffff, 56, 49 => ff00000000007fff (80000000 00000000)
+ rldic. ffffffffffffffff, 56, 56 => ff000000000000ff (80000000 00000000)
+ rldic. ffffffffffffffff, 56, 63 => ff00000000000001 (80000000 00000000)
+ rldic. ffffffffffffffff, 63, 0 => 8000000000000000 (80000000 00000000)
+ rldic. ffffffffffffffff, 63, 7 => 81ffffffffffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 63, 14 => 8003ffffffffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 63, 21 => 800007ffffffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 63, 28 => 8000000fffffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 63, 35 => 800000001fffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 63, 42 => 80000000003fffff (80000000 00000000)
+ rldic. ffffffffffffffff, 63, 49 => 8000000000007fff (80000000 00000000)
+ rldic. ffffffffffffffff, 63, 56 => 80000000000000ff (80000000 00000000)
+ rldic. ffffffffffffffff, 63, 63 => 8000000000000001 (80000000 00000000)
+
+ rldicl. 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 0, 7 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 0, 14 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 0, 21 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 0, 28 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 0, 35 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 0, 42 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 0, 49 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 0, 56 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 0, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 7, 0 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 7, 7 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 7, 14 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 7, 21 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 7, 28 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 7, 35 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 7, 42 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 7, 49 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 7, 56 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 7, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 14, 0 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 14, 7 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 14, 14 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 14, 21 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 14, 28 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 14, 35 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 14, 42 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 14, 49 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 14, 56 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 14, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 21, 0 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 21, 7 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 21, 14 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 21, 21 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 21, 28 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 21, 35 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 21, 42 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 21, 49 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 21, 56 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 21, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 28, 0 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 28, 7 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 28, 14 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 28, 21 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 28, 28 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 28, 35 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 28, 42 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 28, 49 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 28, 56 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 28, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 35, 0 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 35, 7 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 35, 14 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 35, 21 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 35, 28 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 35, 35 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 35, 42 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 35, 49 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 35, 56 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 35, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 42, 0 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 42, 7 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 42, 14 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 42, 21 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 42, 28 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 42, 35 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 42, 42 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 42, 49 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 42, 56 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 42, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 49, 0 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 49, 7 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 49, 14 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 49, 21 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 49, 28 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 49, 35 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 49, 42 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 49, 49 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 49, 56 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 49, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 56, 0 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 56, 7 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 56, 14 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 56, 21 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 56, 28 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 56, 35 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 56, 42 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 56, 49 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 56, 56 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 56, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 63, 0 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 63, 7 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 63, 14 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 63, 21 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 63, 28 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 63, 35 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 63, 42 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 63, 49 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 63, 56 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 63, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000001cbe991def, 0, 0 => 0000001cbe991def (40000000 00000000)
+ rldicl. 0000001cbe991def, 0, 7 => 0000001cbe991def (40000000 00000000)
+ rldicl. 0000001cbe991def, 0, 14 => 0000001cbe991def (40000000 00000000)
+ rldicl. 0000001cbe991def, 0, 21 => 0000001cbe991def (40000000 00000000)
+ rldicl. 0000001cbe991def, 0, 28 => 0000000cbe991def (40000000 00000000)
+ rldicl. 0000001cbe991def, 0, 35 => 000000001e991def (40000000 00000000)
+ rldicl. 0000001cbe991def, 0, 42 => 0000000000191def (40000000 00000000)
+ rldicl. 0000001cbe991def, 0, 49 => 0000000000001def (40000000 00000000)
+ rldicl. 0000001cbe991def, 0, 56 => 00000000000000ef (40000000 00000000)
+ rldicl. 0000001cbe991def, 0, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. 0000001cbe991def, 7, 0 => 00000e5f4c8ef780 (40000000 00000000)
+ rldicl. 0000001cbe991def, 7, 7 => 00000e5f4c8ef780 (40000000 00000000)
+ rldicl. 0000001cbe991def, 7, 14 => 00000e5f4c8ef780 (40000000 00000000)
+ rldicl. 0000001cbe991def, 7, 21 => 0000065f4c8ef780 (40000000 00000000)
+ rldicl. 0000001cbe991def, 7, 28 => 0000000f4c8ef780 (40000000 00000000)
+ rldicl. 0000001cbe991def, 7, 35 => 000000000c8ef780 (40000000 00000000)
+ rldicl. 0000001cbe991def, 7, 42 => 00000000000ef780 (40000000 00000000)
+ rldicl. 0000001cbe991def, 7, 49 => 0000000000007780 (40000000 00000000)
+ rldicl. 0000001cbe991def, 7, 56 => 0000000000000080 (40000000 00000000)
+ rldicl. 0000001cbe991def, 7, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000001cbe991def, 14, 0 => 00072fa6477bc000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 14, 7 => 00072fa6477bc000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 14, 14 => 00032fa6477bc000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 14, 21 => 000007a6477bc000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 14, 28 => 00000006477bc000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 14, 35 => 00000000077bc000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 14, 42 => 00000000003bc000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 14, 49 => 0000000000004000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 14, 56 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000001cbe991def, 14, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000001cbe991def, 21, 0 => 0397d323bde00000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 21, 7 => 0197d323bde00000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 21, 14 => 0003d323bde00000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 21, 21 => 00000323bde00000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 21, 28 => 00000003bde00000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 21, 35 => 000000001de00000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 21, 42 => 0000000000200000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 21, 49 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000001cbe991def, 21, 56 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000001cbe991def, 21, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000001cbe991def, 28, 0 => cbe991def0000001 (80000000 00000000)
+ rldicl. 0000001cbe991def, 28, 7 => 01e991def0000001 (40000000 00000000)
+ rldicl. 0000001cbe991def, 28, 14 => 000191def0000001 (40000000 00000000)
+ rldicl. 0000001cbe991def, 28, 21 => 000001def0000001 (40000000 00000000)
+ rldicl. 0000001cbe991def, 28, 28 => 0000000ef0000001 (40000000 00000000)
+ rldicl. 0000001cbe991def, 28, 35 => 0000000010000001 (40000000 00000000)
+ rldicl. 0000001cbe991def, 28, 42 => 0000000000000001 (40000000 00000000)
+ rldicl. 0000001cbe991def, 28, 49 => 0000000000000001 (40000000 00000000)
+ rldicl. 0000001cbe991def, 28, 56 => 0000000000000001 (40000000 00000000)
+ rldicl. 0000001cbe991def, 28, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. 0000001cbe991def, 35, 0 => f4c8ef78000000e5 (80000000 00000000)
+ rldicl. 0000001cbe991def, 35, 7 => 00c8ef78000000e5 (40000000 00000000)
+ rldicl. 0000001cbe991def, 35, 14 => 0000ef78000000e5 (40000000 00000000)
+ rldicl. 0000001cbe991def, 35, 21 => 00000778000000e5 (40000000 00000000)
+ rldicl. 0000001cbe991def, 35, 28 => 00000008000000e5 (40000000 00000000)
+ rldicl. 0000001cbe991def, 35, 35 => 00000000000000e5 (40000000 00000000)
+ rldicl. 0000001cbe991def, 35, 42 => 00000000000000e5 (40000000 00000000)
+ rldicl. 0000001cbe991def, 35, 49 => 00000000000000e5 (40000000 00000000)
+ rldicl. 0000001cbe991def, 35, 56 => 00000000000000e5 (40000000 00000000)
+ rldicl. 0000001cbe991def, 35, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. 0000001cbe991def, 42, 0 => 6477bc00000072fa (40000000 00000000)
+ rldicl. 0000001cbe991def, 42, 7 => 0077bc00000072fa (40000000 00000000)
+ rldicl. 0000001cbe991def, 42, 14 => 0003bc00000072fa (40000000 00000000)
+ rldicl. 0000001cbe991def, 42, 21 => 00000400000072fa (40000000 00000000)
+ rldicl. 0000001cbe991def, 42, 28 => 00000000000072fa (40000000 00000000)
+ rldicl. 0000001cbe991def, 42, 35 => 00000000000072fa (40000000 00000000)
+ rldicl. 0000001cbe991def, 42, 42 => 00000000000072fa (40000000 00000000)
+ rldicl. 0000001cbe991def, 42, 49 => 00000000000072fa (40000000 00000000)
+ rldicl. 0000001cbe991def, 42, 56 => 00000000000000fa (40000000 00000000)
+ rldicl. 0000001cbe991def, 42, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000001cbe991def, 49, 0 => 3bde000000397d32 (40000000 00000000)
+ rldicl. 0000001cbe991def, 49, 7 => 01de000000397d32 (40000000 00000000)
+ rldicl. 0000001cbe991def, 49, 14 => 0002000000397d32 (40000000 00000000)
+ rldicl. 0000001cbe991def, 49, 21 => 0000000000397d32 (40000000 00000000)
+ rldicl. 0000001cbe991def, 49, 28 => 0000000000397d32 (40000000 00000000)
+ rldicl. 0000001cbe991def, 49, 35 => 0000000000397d32 (40000000 00000000)
+ rldicl. 0000001cbe991def, 49, 42 => 0000000000397d32 (40000000 00000000)
+ rldicl. 0000001cbe991def, 49, 49 => 0000000000007d32 (40000000 00000000)
+ rldicl. 0000001cbe991def, 49, 56 => 0000000000000032 (40000000 00000000)
+ rldicl. 0000001cbe991def, 49, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000001cbe991def, 56, 0 => ef0000001cbe991d (80000000 00000000)
+ rldicl. 0000001cbe991def, 56, 7 => 010000001cbe991d (40000000 00000000)
+ rldicl. 0000001cbe991def, 56, 14 => 000000001cbe991d (40000000 00000000)
+ rldicl. 0000001cbe991def, 56, 21 => 000000001cbe991d (40000000 00000000)
+ rldicl. 0000001cbe991def, 56, 28 => 000000001cbe991d (40000000 00000000)
+ rldicl. 0000001cbe991def, 56, 35 => 000000001cbe991d (40000000 00000000)
+ rldicl. 0000001cbe991def, 56, 42 => 00000000003e991d (40000000 00000000)
+ rldicl. 0000001cbe991def, 56, 49 => 000000000000191d (40000000 00000000)
+ rldicl. 0000001cbe991def, 56, 56 => 000000000000001d (40000000 00000000)
+ rldicl. 0000001cbe991def, 56, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. 0000001cbe991def, 63, 0 => 8000000e5f4c8ef7 (80000000 00000000)
+ rldicl. 0000001cbe991def, 63, 7 => 0000000e5f4c8ef7 (40000000 00000000)
+ rldicl. 0000001cbe991def, 63, 14 => 0000000e5f4c8ef7 (40000000 00000000)
+ rldicl. 0000001cbe991def, 63, 21 => 0000000e5f4c8ef7 (40000000 00000000)
+ rldicl. 0000001cbe991def, 63, 28 => 0000000e5f4c8ef7 (40000000 00000000)
+ rldicl. 0000001cbe991def, 63, 35 => 000000001f4c8ef7 (40000000 00000000)
+ rldicl. 0000001cbe991def, 63, 42 => 00000000000c8ef7 (40000000 00000000)
+ rldicl. 0000001cbe991def, 63, 49 => 0000000000000ef7 (40000000 00000000)
+ rldicl. 0000001cbe991def, 63, 56 => 00000000000000f7 (40000000 00000000)
+ rldicl. 0000001cbe991def, 63, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. ffffffffffffffff, 0, 0 => ffffffffffffffff (80000000 00000000)
+ rldicl. ffffffffffffffff, 0, 7 => 01ffffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 0, 14 => 0003ffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 0, 21 => 000007ffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 0, 28 => 0000000fffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 0, 35 => 000000001fffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 0, 42 => 00000000003fffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 0, 49 => 0000000000007fff (40000000 00000000)
+ rldicl. ffffffffffffffff, 0, 56 => 00000000000000ff (40000000 00000000)
+ rldicl. ffffffffffffffff, 0, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. ffffffffffffffff, 7, 0 => ffffffffffffffff (80000000 00000000)
+ rldicl. ffffffffffffffff, 7, 7 => 01ffffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 7, 14 => 0003ffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 7, 21 => 000007ffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 7, 28 => 0000000fffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 7, 35 => 000000001fffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 7, 42 => 00000000003fffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 7, 49 => 0000000000007fff (40000000 00000000)
+ rldicl. ffffffffffffffff, 7, 56 => 00000000000000ff (40000000 00000000)
+ rldicl. ffffffffffffffff, 7, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. ffffffffffffffff, 14, 0 => ffffffffffffffff (80000000 00000000)
+ rldicl. ffffffffffffffff, 14, 7 => 01ffffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 14, 14 => 0003ffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 14, 21 => 000007ffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 14, 28 => 0000000fffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 14, 35 => 000000001fffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 14, 42 => 00000000003fffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 14, 49 => 0000000000007fff (40000000 00000000)
+ rldicl. ffffffffffffffff, 14, 56 => 00000000000000ff (40000000 00000000)
+ rldicl. ffffffffffffffff, 14, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. ffffffffffffffff, 21, 0 => ffffffffffffffff (80000000 00000000)
+ rldicl. ffffffffffffffff, 21, 7 => 01ffffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 21, 14 => 0003ffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 21, 21 => 000007ffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 21, 28 => 0000000fffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 21, 35 => 000000001fffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 21, 42 => 00000000003fffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 21, 49 => 0000000000007fff (40000000 00000000)
+ rldicl. ffffffffffffffff, 21, 56 => 00000000000000ff (40000000 00000000)
+ rldicl. ffffffffffffffff, 21, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. ffffffffffffffff, 28, 0 => ffffffffffffffff (80000000 00000000)
+ rldicl. ffffffffffffffff, 28, 7 => 01ffffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 28, 14 => 0003ffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 28, 21 => 000007ffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 28, 28 => 0000000fffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 28, 35 => 000000001fffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 28, 42 => 00000000003fffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 28, 49 => 0000000000007fff (40000000 00000000)
+ rldicl. ffffffffffffffff, 28, 56 => 00000000000000ff (40000000 00000000)
+ rldicl. ffffffffffffffff, 28, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. ffffffffffffffff, 35, 0 => ffffffffffffffff (80000000 00000000)
+ rldicl. ffffffffffffffff, 35, 7 => 01ffffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 35, 14 => 0003ffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 35, 21 => 000007ffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 35, 28 => 0000000fffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 35, 35 => 000000001fffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 35, 42 => 00000000003fffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 35, 49 => 0000000000007fff (40000000 00000000)
+ rldicl. ffffffffffffffff, 35, 56 => 00000000000000ff (40000000 00000000)
+ rldicl. ffffffffffffffff, 35, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. ffffffffffffffff, 42, 0 => ffffffffffffffff (80000000 00000000)
+ rldicl. ffffffffffffffff, 42, 7 => 01ffffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 42, 14 => 0003ffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 42, 21 => 000007ffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 42, 28 => 0000000fffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 42, 35 => 000000001fffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 42, 42 => 00000000003fffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 42, 49 => 0000000000007fff (40000000 00000000)
+ rldicl. ffffffffffffffff, 42, 56 => 00000000000000ff (40000000 00000000)
+ rldicl. ffffffffffffffff, 42, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. ffffffffffffffff, 49, 0 => ffffffffffffffff (80000000 00000000)
+ rldicl. ffffffffffffffff, 49, 7 => 01ffffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 49, 14 => 0003ffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 49, 21 => 000007ffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 49, 28 => 0000000fffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 49, 35 => 000000001fffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 49, 42 => 00000000003fffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 49, 49 => 0000000000007fff (40000000 00000000)
+ rldicl. ffffffffffffffff, 49, 56 => 00000000000000ff (40000000 00000000)
+ rldicl. ffffffffffffffff, 49, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. ffffffffffffffff, 56, 0 => ffffffffffffffff (80000000 00000000)
+ rldicl. ffffffffffffffff, 56, 7 => 01ffffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 56, 14 => 0003ffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 56, 21 => 000007ffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 56, 28 => 0000000fffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 56, 35 => 000000001fffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 56, 42 => 00000000003fffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 56, 49 => 0000000000007fff (40000000 00000000)
+ rldicl. ffffffffffffffff, 56, 56 => 00000000000000ff (40000000 00000000)
+ rldicl. ffffffffffffffff, 56, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. ffffffffffffffff, 63, 0 => ffffffffffffffff (80000000 00000000)
+ rldicl. ffffffffffffffff, 63, 7 => 01ffffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 63, 14 => 0003ffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 63, 21 => 000007ffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 63, 28 => 0000000fffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 63, 35 => 000000001fffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 63, 42 => 00000000003fffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 63, 49 => 0000000000007fff (40000000 00000000)
+ rldicl. ffffffffffffffff, 63, 56 => 00000000000000ff (40000000 00000000)
+ rldicl. ffffffffffffffff, 63, 63 => 0000000000000001 (40000000 00000000)
+
+ rldicr. 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 0, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 0, 14 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 0, 21 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 0, 28 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 0, 35 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 0, 42 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 0, 49 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 0, 56 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 0, 63 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 7, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 7, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 7, 14 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 7, 21 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 7, 28 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 7, 35 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 7, 42 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 7, 49 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 7, 56 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 7, 63 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 14, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 14, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 14, 14 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 14, 21 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 14, 28 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 14, 35 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 14, 42 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 14, 49 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 14, 56 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 14, 63 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 21, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 21, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 21, 14 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 21, 21 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 21, 28 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 21, 35 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 21, 42 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 21, 49 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 21, 56 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 21, 63 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 28, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 28, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 28, 14 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 28, 21 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 28, 28 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 28, 35 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 28, 42 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 28, 49 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 28, 56 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 28, 63 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 35, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 35, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 35, 14 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 35, 21 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 35, 28 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 35, 35 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 35, 42 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 35, 49 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 35, 56 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 35, 63 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 42, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 42, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 42, 14 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 42, 21 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 42, 28 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 42, 35 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 42, 42 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 42, 49 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 42, 56 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 42, 63 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 49, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 49, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 49, 14 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 49, 21 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 49, 28 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 49, 35 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 49, 42 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 49, 49 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 49, 56 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 49, 63 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 56, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 56, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 56, 14 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 56, 21 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 56, 28 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 56, 35 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 56, 42 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 56, 49 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 56, 56 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 56, 63 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 63, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 63, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 63, 14 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 63, 21 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 63, 28 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 63, 35 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 63, 42 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 63, 49 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 63, 56 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 63, 63 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 0, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 0, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 0, 14 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 0, 21 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 0, 28 => 0000001800000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 0, 35 => 0000001cb0000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 0, 42 => 0000001cbe800000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 0, 49 => 0000001cbe990000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 0, 56 => 0000001cbe991d80 (40000000 00000000)
+ rldicr. 0000001cbe991def, 0, 63 => 0000001cbe991def (40000000 00000000)
+ rldicr. 0000001cbe991def, 7, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 7, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 7, 14 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 7, 21 => 00000c0000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 7, 28 => 00000e5800000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 7, 35 => 00000e5f40000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 7, 42 => 00000e5f4c800000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 7, 49 => 00000e5f4c8ec000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 7, 56 => 00000e5f4c8ef780 (40000000 00000000)
+ rldicr. 0000001cbe991def, 7, 63 => 00000e5f4c8ef780 (40000000 00000000)
+ rldicr. 0000001cbe991def, 14, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 14, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 14, 14 => 0006000000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 14, 21 => 00072c0000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 14, 28 => 00072fa000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 14, 35 => 00072fa640000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 14, 42 => 00072fa647600000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 14, 49 => 00072fa6477bc000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 14, 56 => 00072fa6477bc000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 14, 63 => 00072fa6477bc000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 21, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 21, 7 => 0300000000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 21, 14 => 0396000000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 21, 21 => 0397d00000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 21, 28 => 0397d32000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 21, 35 => 0397d323b0000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 21, 42 => 0397d323bde00000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 21, 49 => 0397d323bde00000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 21, 56 => 0397d323bde00000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 21, 63 => 0397d323bde00000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 28, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 28, 7 => cb00000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 28, 14 => cbe8000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 28, 21 => cbe9900000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 28, 28 => cbe991d800000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 28, 35 => cbe991def0000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 28, 42 => cbe991def0000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 28, 49 => cbe991def0000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 28, 56 => cbe991def0000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 28, 63 => cbe991def0000001 (80000000 00000000)
+ rldicr. 0000001cbe991def, 35, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 35, 7 => f400000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 35, 14 => f4c8000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 35, 21 => f4c8ec0000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 35, 28 => f4c8ef7800000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 35, 35 => f4c8ef7800000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 35, 42 => f4c8ef7800000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 35, 49 => f4c8ef7800000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 35, 56 => f4c8ef7800000080 (80000000 00000000)
+ rldicr. 0000001cbe991def, 35, 63 => f4c8ef78000000e5 (80000000 00000000)
+ rldicr. 0000001cbe991def, 42, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 42, 7 => 6400000000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 42, 14 => 6476000000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 42, 21 => 6477bc0000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 42, 28 => 6477bc0000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 42, 35 => 6477bc0000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 42, 42 => 6477bc0000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 42, 49 => 6477bc0000004000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 42, 56 => 6477bc0000007280 (40000000 00000000)
+ rldicr. 0000001cbe991def, 42, 63 => 6477bc00000072fa (40000000 00000000)
+ rldicr. 0000001cbe991def, 49, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 49, 7 => 3b00000000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 49, 14 => 3bde000000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 49, 21 => 3bde000000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 49, 28 => 3bde000000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 49, 35 => 3bde000000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 49, 42 => 3bde000000200000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 49, 49 => 3bde000000394000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 49, 56 => 3bde000000397d00 (40000000 00000000)
+ rldicr. 0000001cbe991def, 49, 63 => 3bde000000397d32 (40000000 00000000)
+ rldicr. 0000001cbe991def, 56, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 56, 7 => ef00000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 56, 14 => ef00000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 56, 21 => ef00000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 56, 28 => ef00000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 56, 35 => ef00000010000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 56, 42 => ef0000001ca00000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 56, 49 => ef0000001cbe8000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 56, 56 => ef0000001cbe9900 (80000000 00000000)
+ rldicr. 0000001cbe991def, 56, 63 => ef0000001cbe991d (80000000 00000000)
+ rldicr. 0000001cbe991def, 63, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 63, 7 => 8000000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 63, 14 => 8000000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 63, 21 => 8000000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 63, 28 => 8000000800000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 63, 35 => 8000000e50000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 63, 42 => 8000000e5f400000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 63, 49 => 8000000e5f4c8000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 63, 56 => 8000000e5f4c8e80 (80000000 00000000)
+ rldicr. 0000001cbe991def, 63, 63 => 8000000e5f4c8ef7 (80000000 00000000)
+ rldicr. ffffffffffffffff, 0, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 0, 7 => ff00000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 0, 14 => fffe000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 0, 21 => fffffc0000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 0, 28 => fffffff800000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 0, 35 => fffffffff0000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 0, 42 => ffffffffffe00000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 0, 49 => ffffffffffffc000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 0, 56 => ffffffffffffff80 (80000000 00000000)
+ rldicr. ffffffffffffffff, 0, 63 => ffffffffffffffff (80000000 00000000)
+ rldicr. ffffffffffffffff, 7, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 7, 7 => ff00000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 7, 14 => fffe000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 7, 21 => fffffc0000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 7, 28 => fffffff800000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 7, 35 => fffffffff0000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 7, 42 => ffffffffffe00000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 7, 49 => ffffffffffffc000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 7, 56 => ffffffffffffff80 (80000000 00000000)
+ rldicr. ffffffffffffffff, 7, 63 => ffffffffffffffff (80000000 00000000)
+ rldicr. ffffffffffffffff, 14, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 14, 7 => ff00000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 14, 14 => fffe000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 14, 21 => fffffc0000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 14, 28 => fffffff800000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 14, 35 => fffffffff0000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 14, 42 => ffffffffffe00000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 14, 49 => ffffffffffffc000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 14, 56 => ffffffffffffff80 (80000000 00000000)
+ rldicr. ffffffffffffffff, 14, 63 => ffffffffffffffff (80000000 00000000)
+ rldicr. ffffffffffffffff, 21, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 21, 7 => ff00000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 21, 14 => fffe000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 21, 21 => fffffc0000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 21, 28 => fffffff800000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 21, 35 => fffffffff0000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 21, 42 => ffffffffffe00000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 21, 49 => ffffffffffffc000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 21, 56 => ffffffffffffff80 (80000000 00000000)
+ rldicr. ffffffffffffffff, 21, 63 => ffffffffffffffff (80000000 00000000)
+ rldicr. ffffffffffffffff, 28, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 28, 7 => ff00000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 28, 14 => fffe000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 28, 21 => fffffc0000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 28, 28 => fffffff800000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 28, 35 => fffffffff0000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 28, 42 => ffffffffffe00000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 28, 49 => ffffffffffffc000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 28, 56 => ffffffffffffff80 (80000000 00000000)
+ rldicr. ffffffffffffffff, 28, 63 => ffffffffffffffff (80000000 00000000)
+ rldicr. ffffffffffffffff, 35, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 35, 7 => ff00000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 35, 14 => fffe000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 35, 21 => fffffc0000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 35, 28 => fffffff800000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 35, 35 => fffffffff0000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 35, 42 => ffffffffffe00000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 35, 49 => ffffffffffffc000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 35, 56 => ffffffffffffff80 (80000000 00000000)
+ rldicr. ffffffffffffffff, 35, 63 => ffffffffffffffff (80000000 00000000)
+ rldicr. ffffffffffffffff, 42, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 42, 7 => ff00000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 42, 14 => fffe000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 42, 21 => fffffc0000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 42, 28 => fffffff800000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 42, 35 => fffffffff0000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 42, 42 => ffffffffffe00000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 42, 49 => ffffffffffffc000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 42, 56 => ffffffffffffff80 (80000000 00000000)
+ rldicr. ffffffffffffffff, 42, 63 => ffffffffffffffff (80000000 00000000)
+ rldicr. ffffffffffffffff, 49, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 49, 7 => ff00000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 49, 14 => fffe000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 49, 21 => fffffc0000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 49, 28 => fffffff800000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 49, 35 => fffffffff0000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 49, 42 => ffffffffffe00000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 49, 49 => ffffffffffffc000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 49, 56 => ffffffffffffff80 (80000000 00000000)
+ rldicr. ffffffffffffffff, 49, 63 => ffffffffffffffff (80000000 00000000)
+ rldicr. ffffffffffffffff, 56, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 56, 7 => ff00000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 56, 14 => fffe000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 56, 21 => fffffc0000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 56, 28 => fffffff800000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 56, 35 => fffffffff0000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 56, 42 => ffffffffffe00000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 56, 49 => ffffffffffffc000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 56, 56 => ffffffffffffff80 (80000000 00000000)
+ rldicr. ffffffffffffffff, 56, 63 => ffffffffffffffff (80000000 00000000)
+ rldicr. ffffffffffffffff, 63, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 63, 7 => ff00000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 63, 14 => fffe000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 63, 21 => fffffc0000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 63, 28 => fffffff800000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 63, 35 => fffffffff0000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 63, 42 => ffffffffffe00000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 63, 49 => ffffffffffffc000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 63, 56 => ffffffffffffff80 (80000000 00000000)
+ rldicr. ffffffffffffffff, 63, 63 => ffffffffffffffff (80000000 00000000)
+
+ rldimi. 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 0, 7 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 0, 14 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 0, 21 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 0, 28 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 0, 35 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 0, 42 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 0, 49 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 0, 56 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 0, 63 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 7, 0 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 7, 7 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 7, 14 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 7, 21 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 7, 28 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 7, 35 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 7, 42 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 7, 49 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 7, 56 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 7, 63 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 14, 0 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 14, 7 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 14, 14 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 14, 21 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 14, 28 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 14, 35 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 14, 42 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 14, 49 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 14, 56 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 14, 63 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 21, 0 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 21, 7 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 21, 14 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 21, 21 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 21, 28 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 21, 35 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 21, 42 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 21, 49 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 21, 56 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 21, 63 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 28, 0 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 28, 7 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 28, 14 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 28, 21 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 28, 28 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 28, 35 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 28, 42 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 28, 49 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 28, 56 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 28, 63 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 35, 0 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 35, 7 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 35, 14 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 35, 21 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 35, 28 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 35, 35 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 35, 42 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 35, 49 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 35, 56 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 35, 63 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 42, 0 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 42, 7 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 42, 14 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 42, 21 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 42, 28 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 42, 35 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 42, 42 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 42, 49 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 42, 56 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 42, 63 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 49, 0 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 49, 7 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 49, 14 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 49, 21 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 49, 28 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 49, 35 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 49, 42 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 49, 49 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 49, 56 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 49, 63 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 56, 0 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 56, 7 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 56, 14 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 56, 21 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 56, 28 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 56, 35 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 56, 42 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 56, 49 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 56, 56 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 56, 63 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 63, 0 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 63, 7 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 63, 14 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 63, 21 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 63, 28 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 63, 35 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 63, 42 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 63, 49 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 63, 56 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 63, 63 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000001cbe991def, 0, 0 => 0000001cbe991def (40000000 00000000)
+ rldimi. 0000001cbe991def, 0, 7 => 0000001cbe991def (40000000 00000000)
+ rldimi. 0000001cbe991def, 0, 14 => 0000001cbe991def (40000000 00000000)
+ rldimi. 0000001cbe991def, 0, 21 => 0000001cbe991def (40000000 00000000)
+ rldimi. 0000001cbe991def, 0, 28 => 0000001cbe991def (40000000 00000000)
+ rldimi. 0000001cbe991def, 0, 35 => 0000001cbe991def (40000000 00000000)
+ rldimi. 0000001cbe991def, 0, 42 => 0000001cbe991def (40000000 00000000)
+ rldimi. 0000001cbe991def, 0, 49 => 0000001cbe991def (40000000 00000000)
+ rldimi. 0000001cbe991def, 0, 56 => 0000001cbe991def (40000000 00000000)
+ rldimi. 0000001cbe991def, 0, 63 => 0000001cbe991def (40000000 00000000)
+ rldimi. 0000001cbe991def, 7, 0 => 00000e5f4c8ef7ef (40000000 00000000)
+ rldimi. 0000001cbe991def, 7, 7 => 00000e5f4c8ef7ef (40000000 00000000)
+ rldimi. 0000001cbe991def, 7, 14 => 00000e5f4c8ef7ef (40000000 00000000)
+ rldimi. 0000001cbe991def, 7, 21 => 00000e5f4c8ef7ef (40000000 00000000)
+ rldimi. 0000001cbe991def, 7, 28 => 00000e5f4c8ef7ef (40000000 00000000)
+ rldimi. 0000001cbe991def, 7, 35 => 00000e5f4c8ef7ef (40000000 00000000)
+ rldimi. 0000001cbe991def, 7, 42 => 00000e5f4c8ef7ef (40000000 00000000)
+ rldimi. 0000001cbe991def, 7, 49 => 00000e5f4c8ef7ef (40000000 00000000)
+ rldimi. 0000001cbe991def, 7, 56 => 00000e5f4c8ef7ef (40000000 00000000)
+ rldimi. 0000001cbe991def, 7, 63 => 00000e5f4c8ef7ee (40000000 00000000)
+ rldimi. 0000001cbe991def, 14, 0 => 00072fa6477bf7ee (40000000 00000000)
+ rldimi. 0000001cbe991def, 14, 7 => 00072fa6477bf7ee (40000000 00000000)
+ rldimi. 0000001cbe991def, 14, 14 => 00072fa6477bf7ee (40000000 00000000)
+ rldimi. 0000001cbe991def, 14, 21 => 00072fa6477bf7ee (40000000 00000000)
+ rldimi. 0000001cbe991def, 14, 28 => 00072fa6477bf7ee (40000000 00000000)
+ rldimi. 0000001cbe991def, 14, 35 => 00072fa6477bf7ee (40000000 00000000)
+ rldimi. 0000001cbe991def, 14, 42 => 00072fa6477bf7ee (40000000 00000000)
+ rldimi. 0000001cbe991def, 14, 49 => 00072fa6477bf7ee (40000000 00000000)
+ rldimi. 0000001cbe991def, 14, 56 => 00072fa6477bf700 (40000000 00000000)
+ rldimi. 0000001cbe991def, 14, 63 => 00072fa6477bf700 (40000000 00000000)
+ rldimi. 0000001cbe991def, 21, 0 => 0397d323bdfbf700 (40000000 00000000)
+ rldimi. 0000001cbe991def, 21, 7 => 0397d323bdfbf700 (40000000 00000000)
+ rldimi. 0000001cbe991def, 21, 14 => 0397d323bdfbf700 (40000000 00000000)
+ rldimi. 0000001cbe991def, 21, 21 => 0397d323bdfbf700 (40000000 00000000)
+ rldimi. 0000001cbe991def, 21, 28 => 0397d323bdfbf700 (40000000 00000000)
+ rldimi. 0000001cbe991def, 21, 35 => 0397d323bdfbf700 (40000000 00000000)
+ rldimi. 0000001cbe991def, 21, 42 => 0397d323bdfbf700 (40000000 00000000)
+ rldimi. 0000001cbe991def, 21, 49 => 0397d323bdfb8000 (40000000 00000000)
+ rldimi. 0000001cbe991def, 21, 56 => 0397d323bdfb8000 (40000000 00000000)
+ rldimi. 0000001cbe991def, 21, 63 => 0397d323bdfb8000 (40000000 00000000)
+ rldimi. 0000001cbe991def, 28, 0 => cbe991defdfb8000 (80000000 00000000)
+ rldimi. 0000001cbe991def, 28, 7 => cbe991defdfb8000 (80000000 00000000)
+ rldimi. 0000001cbe991def, 28, 14 => cbe991defdfb8000 (80000000 00000000)
+ rldimi. 0000001cbe991def, 28, 21 => cbe991defdfb8000 (80000000 00000000)
+ rldimi. 0000001cbe991def, 28, 28 => cbe991defdfb8000 (80000000 00000000)
+ rldimi. 0000001cbe991def, 28, 35 => cbe991defdfb8000 (80000000 00000000)
+ rldimi. 0000001cbe991def, 28, 42 => cbe991defdc00001 (80000000 00000000)
+ rldimi. 0000001cbe991def, 28, 49 => cbe991defdc00001 (80000000 00000000)
+ rldimi. 0000001cbe991def, 28, 56 => cbe991defdc00001 (80000000 00000000)
+ rldimi. 0000001cbe991def, 28, 63 => cbe991defdc00001 (80000000 00000000)
+ rldimi. 0000001cbe991def, 35, 0 => f4c8ef7efdc00001 (80000000 00000000)
+ rldimi. 0000001cbe991def, 35, 7 => f4c8ef7efdc00001 (80000000 00000000)
+ rldimi. 0000001cbe991def, 35, 14 => f4c8ef7efdc00001 (80000000 00000000)
+ rldimi. 0000001cbe991def, 35, 21 => f4c8ef7efdc00001 (80000000 00000000)
+ rldimi. 0000001cbe991def, 35, 28 => f4c8ef7efdc00001 (80000000 00000000)
+ rldimi. 0000001cbe991def, 35, 35 => f4c8ef7ee00000e5 (80000000 00000000)
+ rldimi. 0000001cbe991def, 35, 42 => f4c8ef7ee00000e5 (80000000 00000000)
+ rldimi. 0000001cbe991def, 35, 49 => f4c8ef7ee00000e5 (80000000 00000000)
+ rldimi. 0000001cbe991def, 35, 56 => f4c8ef7ee00000e5 (80000000 00000000)
+ rldimi. 0000001cbe991def, 35, 63 => f4c8ef7ee00000e5 (80000000 00000000)
+ rldimi. 0000001cbe991def, 42, 0 => 6477bf7ee00000e5 (40000000 00000000)
+ rldimi. 0000001cbe991def, 42, 7 => 6477bf7ee00000e5 (40000000 00000000)
+ rldimi. 0000001cbe991def, 42, 14 => 6477bf7ee00000e5 (40000000 00000000)
+ rldimi. 0000001cbe991def, 42, 21 => 6477bf7ee00000e5 (40000000 00000000)
+ rldimi. 0000001cbe991def, 42, 28 => 6477bf70000072fa (40000000 00000000)
+ rldimi. 0000001cbe991def, 42, 35 => 6477bf70000072fa (40000000 00000000)
+ rldimi. 0000001cbe991def, 42, 42 => 6477bf70000072fa (40000000 00000000)
+ rldimi. 0000001cbe991def, 42, 49 => 6477bf70000072fa (40000000 00000000)
+ rldimi. 0000001cbe991def, 42, 56 => 6477bf70000072fa (40000000 00000000)
+ rldimi. 0000001cbe991def, 42, 63 => 6477bf70000072fa (40000000 00000000)
+ rldimi. 0000001cbe991def, 49, 0 => 3bdfbf70000072fa (40000000 00000000)
+ rldimi. 0000001cbe991def, 49, 7 => 3bdfbf70000072fa (40000000 00000000)
+ rldimi. 0000001cbe991def, 49, 14 => 3bdfbf70000072fa (40000000 00000000)
+ rldimi. 0000001cbe991def, 49, 21 => 3bdfb80000397d32 (40000000 00000000)
+ rldimi. 0000001cbe991def, 49, 28 => 3bdfb80000397d32 (40000000 00000000)
+ rldimi. 0000001cbe991def, 49, 35 => 3bdfb80000397d32 (40000000 00000000)
+ rldimi. 0000001cbe991def, 49, 42 => 3bdfb80000397d32 (40000000 00000000)
+ rldimi. 0000001cbe991def, 49, 49 => 3bdfb80000397d32 (40000000 00000000)
+ rldimi. 0000001cbe991def, 49, 56 => 3bdfb80000397d32 (40000000 00000000)
+ rldimi. 0000001cbe991def, 49, 63 => 3bdfb80000397d32 (40000000 00000000)
+ rldimi. 0000001cbe991def, 56, 0 => efdfb80000397d32 (80000000 00000000)
+ rldimi. 0000001cbe991def, 56, 7 => efdfb80000397d32 (80000000 00000000)
+ rldimi. 0000001cbe991def, 56, 14 => efdc00001cbe991d (80000000 00000000)
+ rldimi. 0000001cbe991def, 56, 21 => efdc00001cbe991d (80000000 00000000)
+ rldimi. 0000001cbe991def, 56, 28 => efdc00001cbe991d (80000000 00000000)
+ rldimi. 0000001cbe991def, 56, 35 => efdc00001cbe991d (80000000 00000000)
+ rldimi. 0000001cbe991def, 56, 42 => efdc00001cbe991d (80000000 00000000)
+ rldimi. 0000001cbe991def, 56, 49 => efdc00001cbe991d (80000000 00000000)
+ rldimi. 0000001cbe991def, 56, 56 => efdc00001cbe991d (80000000 00000000)
+ rldimi. 0000001cbe991def, 56, 63 => efdc00001cbe991d (80000000 00000000)
+ rldimi. 0000001cbe991def, 63, 0 => efdc00001cbe991d (80000000 00000000)
+ rldimi. 0000001cbe991def, 63, 7 => ee00000e5f4c8ef7 (80000000 00000000)
+ rldimi. 0000001cbe991def, 63, 14 => ee00000e5f4c8ef7 (80000000 00000000)
+ rldimi. 0000001cbe991def, 63, 21 => ee00000e5f4c8ef7 (80000000 00000000)
+ rldimi. 0000001cbe991def, 63, 28 => ee00000e5f4c8ef7 (80000000 00000000)
+ rldimi. 0000001cbe991def, 63, 35 => ee00000e5f4c8ef7 (80000000 00000000)
+ rldimi. 0000001cbe991def, 63, 42 => ee00000e5f4c8ef7 (80000000 00000000)
+ rldimi. 0000001cbe991def, 63, 49 => ee00000e5f4c8ef7 (80000000 00000000)
+ rldimi. 0000001cbe991def, 63, 56 => ee00000e5f4c8ef7 (80000000 00000000)
+ rldimi. 0000001cbe991def, 63, 63 => ee00000e5f4c8ef7 (80000000 00000000)
+ rldimi. ffffffffffffffff, 0, 0 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 0, 7 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 0, 14 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 0, 21 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 0, 28 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 0, 35 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 0, 42 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 0, 49 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 0, 56 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 0, 63 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 7, 0 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 7, 7 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 7, 14 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 7, 21 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 7, 28 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 7, 35 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 7, 42 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 7, 49 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 7, 56 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 7, 63 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 14, 0 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 14, 7 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 14, 14 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 14, 21 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 14, 28 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 14, 35 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 14, 42 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 14, 49 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 14, 56 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 14, 63 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 21, 0 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 21, 7 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 21, 14 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 21, 21 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 21, 28 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 21, 35 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 21, 42 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 21, 49 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 21, 56 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 21, 63 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 28, 0 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 28, 7 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 28, 14 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 28, 21 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 28, 28 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 28, 35 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 28, 42 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 28, 49 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 28, 56 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 28, 63 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 35, 0 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 35, 7 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 35, 14 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 35, 21 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 35, 28 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 35, 35 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 35, 42 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 35, 49 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 35, 56 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 35, 63 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 42, 0 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 42, 7 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 42, 14 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 42, 21 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 42, 28 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 42, 35 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 42, 42 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 42, 49 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 42, 56 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 42, 63 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 49, 0 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 49, 7 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 49, 14 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 49, 21 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 49, 28 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 49, 35 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 49, 42 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 49, 49 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 49, 56 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 49, 63 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 56, 0 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 56, 7 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 56, 14 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 56, 21 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 56, 28 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 56, 35 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 56, 42 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 56, 49 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 56, 56 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 56, 63 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 63, 0 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 63, 7 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 63, 14 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 63, 21 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 63, 28 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 63, 35 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 63, 42 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 63, 49 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 63, 56 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 63, 63 => ffffffffffffffff (80000000 00000000)
+
+ sradi. 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
+ sradi. 0000000000000000, 7 => 0000000000000000 (20000000 00000000)
+ sradi. 0000000000000000, 14 => 0000000000000000 (20000000 00000000)
+ sradi. 0000000000000000, 21 => 0000000000000000 (20000000 00000000)
+ sradi. 0000000000000000, 28 => 0000000000000000 (20000000 00000000)
+ sradi. 0000000000000000, 35 => 0000000000000000 (20000000 00000000)
+ sradi. 0000000000000000, 42 => 0000000000000000 (20000000 00000000)
+ sradi. 0000000000000000, 49 => 0000000000000000 (20000000 00000000)
+ sradi. 0000000000000000, 56 => 0000000000000000 (20000000 00000000)
+ sradi. 0000000000000000, 63 => 0000000000000000 (20000000 00000000)
+ sradi. 0000001cbe991def, 0 => 0000001cbe991def (40000000 00000000)
+ sradi. 0000001cbe991def, 7 => 00000000397d323b (40000000 00000000)
+ sradi. 0000001cbe991def, 14 => 000000000072fa64 (40000000 00000000)
+ sradi. 0000001cbe991def, 21 => 000000000000e5f4 (40000000 00000000)
+ sradi. 0000001cbe991def, 28 => 00000000000001cb (40000000 00000000)
+ sradi. 0000001cbe991def, 35 => 0000000000000003 (40000000 00000000)
+ sradi. 0000001cbe991def, 42 => 0000000000000000 (20000000 00000000)
+ sradi. 0000001cbe991def, 49 => 0000000000000000 (20000000 00000000)
+ sradi. 0000001cbe991def, 56 => 0000000000000000 (20000000 00000000)
+ sradi. 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000)
+ sradi. ffffffffffffffff, 0 => ffffffffffffffff (80000000 00000000)
+ sradi. ffffffffffffffff, 7 => ffffffffffffffff (80000000 20000000)
+ sradi. ffffffffffffffff, 14 => ffffffffffffffff (80000000 20000000)
+ sradi. ffffffffffffffff, 21 => ffffffffffffffff (80000000 20000000)
+ sradi. ffffffffffffffff, 28 => ffffffffffffffff (80000000 20000000)
+ sradi. ffffffffffffffff, 35 => ffffffffffffffff (80000000 20000000)
+ sradi. ffffffffffffffff, 42 => ffffffffffffffff (80000000 20000000)
+ sradi. ffffffffffffffff, 49 => ffffffffffffffff (80000000 20000000)
+ sradi. ffffffffffffffff, 56 => ffffffffffffffff (80000000 20000000)
+ sradi. ffffffffffffffff, 63 => ffffffffffffffff (80000000 20000000)
+
+PPC integer load insns
+ with one register + one 16 bits immediate args with flags update:
+ lbz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lbz 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
+ lbz 15, (ffffffffffffffff) => 00000000000000ef, 0 (00000000 00000000)
+ lbz 1, (ffffffffffffffff) => 00000000000000ff, 0 (00000000 00000000)
+ lbz -7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
+ lbz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+
+ lbzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lbzu 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000)
+ lbzu 15, (ffffffffffffffff) => 00000000000000ef, 15 (00000000 00000000)
+ lbzu 1, (ffffffffffffffff) => 00000000000000ff, 1 (00000000 00000000)
+ lbzu -7, (0000001cbe991def) => 0000000000000000, -7 (00000000 00000000)
+ lbzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
+
+ lha 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lha 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
+ lha 15, (ffffffffffffffff) => ffffffffffffefff, 0 (00000000 00000000)
+ lha 1, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
+ lha -7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
+ lha -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+
+ lhau 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lhau 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000)
+ lhau 15, (ffffffffffffffff) => ffffffffffffefff, 15 (00000000 00000000)
+ lhau 1, (ffffffffffffffff) => ffffffffffffffff, 1 (00000000 00000000)
+ lhau -7, (0000001cbe991def) => 0000000000000000, -7 (00000000 00000000)
+ lhau -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
+
+ lhz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lhz 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
+ lhz 15, (ffffffffffffffff) => 000000000000efff, 0 (00000000 00000000)
+ lhz 1, (ffffffffffffffff) => 000000000000ffff, 0 (00000000 00000000)
+ lhz -7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
+ lhz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+
+ lhzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lhzu 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000)
+ lhzu 15, (ffffffffffffffff) => 000000000000efff, 15 (00000000 00000000)
+ lhzu 1, (ffffffffffffffff) => 000000000000ffff, 1 (00000000 00000000)
+ lhzu -7, (0000001cbe991def) => 0000000000000000, -7 (00000000 00000000)
+ lhzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
+
+ lwz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lwz 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
+ lwz 15, (ffffffffffffffff) => 00000000efffffff, 0 (00000000 00000000)
+ lwz 1, (ffffffffffffffff) => 00000000ffffffff, 0 (00000000 00000000)
+ lwz -7, (0000001cbe991def) => 0000000000001cbe, 0 (00000000 00000000)
+ lwz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+
+ lwzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lwzu 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000)
+ lwzu 15, (ffffffffffffffff) => 00000000efffffff, 15 (00000000 00000000)
+ lwzu 1, (ffffffffffffffff) => 00000000ffffffff, 1 (00000000 00000000)
+ lwzu -7, (0000001cbe991def) => 0000000000001cbe, -7 (00000000 00000000)
+ lwzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
+
+ ld 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ ld 7, (0000001cbe991def) => 000000000000001c, 0 (00000000 00000000)
+ ld 15, (ffffffffffffffff) => be991defffffffff, 0 (00000000 00000000)
+ ld 1, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
+ ld -7, (0000001cbe991def) => 0000001cbe991def, -8 (00000000 00000000)
+ ld -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
+
+ ldu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ ldu 7, (0000001cbe991def) => 000000000000001c, 4 (00000000 00000000)
+ ldu 15, (ffffffffffffffff) => be991defffffffff, 12 (00000000 00000000)
+ ldu 1, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
+ ldu -7, (0000001cbe991def) => 0000001cbe991def, -8 (00000000 00000000)
+ ldu -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
+
+ lwa 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lwa 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
+ lwa 15, (ffffffffffffffff) => ffffffffbe991def, 0 (00000000 00000000)
+ lwa 1, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
+ lwa -7, (0000001cbe991def) => 0000001cbe991def, -8 (00000000 00000000)
+ lwa -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
+
+PPC integer load insns with two register args:
+ lbzx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lbzx 8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
+ lbzx 16, (ffffffffffffffff) => 00000000000000ff, 0 (00000000 00000000)
+
+ lbzux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lbzux 8, (0000001cbe991def) => 0000000000000000, 8 (00000000 00000000)
+ lbzux 16, (ffffffffffffffff) => 00000000000000ff, 16 (00000000 00000000)
+
+ lhax 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lhax 8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
+ lhax 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
+
+ lhaux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lhaux 8, (0000001cbe991def) => 0000000000000000, 8 (00000000 00000000)
+ lhaux 16, (ffffffffffffffff) => ffffffffffffffff, 16 (00000000 00000000)
+
+ lhzx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lhzx 8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
+ lhzx 16, (ffffffffffffffff) => 000000000000ffff, 0 (00000000 00000000)
+
+ lhzux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lhzux 8, (0000001cbe991def) => 0000000000000000, 8 (00000000 00000000)
+ lhzux 16, (ffffffffffffffff) => 000000000000ffff, 16 (00000000 00000000)
+
+ lwzx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lwzx 8, (0000001cbe991def) => 000000000000001c, 0 (00000000 00000000)
+ lwzx 16, (ffffffffffffffff) => 00000000ffffffff, 0 (00000000 00000000)
+
+ lwzux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lwzux 8, (0000001cbe991def) => 000000000000001c, 8 (00000000 00000000)
+ lwzux 16, (ffffffffffffffff) => 00000000ffffffff, 16 (00000000 00000000)
+
+ ldx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ ldx 8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000)
+ ldx 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
+
+ ldux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ ldux 8, (0000001cbe991def) => 0000001cbe991def, 8 (00000000 00000000)
+ ldux 16, (ffffffffffffffff) => ffffffffffffffff, 16 (00000000 00000000)
+
+ lwax 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lwax 8, (0000001cbe991def) => 000000000000001c, 0 (00000000 00000000)
+ lwax 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
+
+ lwaux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lwaux 8, (0000001cbe991def) => 000000000000001c, 8 (00000000 00000000)
+ lwaux 16, (ffffffffffffffff) => ffffffffffffffff, 16 (00000000 00000000)
+
+PPC integer store insns
+ with one register + one 16 bits immediate args with flags update:
+ stb 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ stb 0000001cbe991def, 8 => ef00000000000000, 0 (00000000 00000000)
+ stb ffffffffffffffff, 16 => ff00000000000000, 0 (00000000 00000000)
+ stb 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
+ stb 0000001cbe991def, -8 => ef00000000000000, 0 (00000000 00000000)
+ stb ffffffffffffffff, 0 => ff00000000000000, 0 (00000000 00000000)
+
+ stbu 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ stbu 0000001cbe991def, 8 => ef00000000000000, 8 (00000000 00000000)
+ stbu ffffffffffffffff, 16 => ff00000000000000, 16 (00000000 00000000)
+ stbu 0000000000000000, -16 => 0000000000000000, -16 (00000000 00000000)
+ stbu 0000001cbe991def, -8 => ef00000000000000, -8 (00000000 00000000)
+ stbu ffffffffffffffff, 0 => ff00000000000000, 0 (00000000 00000000)
+
+ sth 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ sth 0000001cbe991def, 8 => 1def000000000000, 0 (00000000 00000000)
+ sth ffffffffffffffff, 16 => ffff000000000000, 0 (00000000 00000000)
+ sth 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
+ sth 0000001cbe991def, -8 => 1def000000000000, 0 (00000000 00000000)
+ sth ffffffffffffffff, 0 => ffff000000000000, 0 (00000000 00000000)
+
+ sthu 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ sthu 0000001cbe991def, 8 => 1def000000000000, 8 (00000000 00000000)
+ sthu ffffffffffffffff, 16 => ffff000000000000, 16 (00000000 00000000)
+ sthu 0000000000000000, -16 => 0000000000000000, -16 (00000000 00000000)
+ sthu 0000001cbe991def, -8 => 1def000000000000, -8 (00000000 00000000)
+ sthu ffffffffffffffff, 0 => ffff000000000000, 0 (00000000 00000000)
+
+ stw 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ stw 0000001cbe991def, 8 => be991def00000000, 0 (00000000 00000000)
+ stw ffffffffffffffff, 16 => ffffffff00000000, 0 (00000000 00000000)
+ stw 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
+ stw 0000001cbe991def, -8 => be991def00000000, 0 (00000000 00000000)
+ stw ffffffffffffffff, 0 => ffffffff00000000, 0 (00000000 00000000)
+
+ stwu 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ stwu 0000001cbe991def, 8 => be991def00000000, 8 (00000000 00000000)
+ stwu ffffffffffffffff, 16 => ffffffff00000000, 16 (00000000 00000000)
+ stwu 0000000000000000, -16 => 0000000000000000, -16 (00000000 00000000)
+ stwu 0000001cbe991def, -8 => be991def00000000, -8 (00000000 00000000)
+ stwu ffffffffffffffff, 0 => ffffffff00000000, 0 (00000000 00000000)
+
+ std 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ std 0000001cbe991def, 8 => 0000001cbe991def, 0 (00000000 00000000)
+ std ffffffffffffffff, 16 => ffffffffffffffff, 0 (00000000 00000000)
+ std 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
+ std 0000001cbe991def, -8 => 0000001cbe991def, 0 (00000000 00000000)
+ std ffffffffffffffff, 0 => ffffffffffffffff, 0 (00000000 00000000)
+
+ stdu 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ stdu 0000001cbe991def, 8 => 0000001cbe991def, 0 (00000000 00000000)
+ stdu ffffffffffffffff, 16 => ffffffffffffffff, 0 (00000000 00000000)
+ stdu 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
+ stdu 0000001cbe991def, -8 => 0000001cbe991def, 0 (00000000 00000000)
+ stdu ffffffffffffffff, 0 => ffffffffffffffff, 0 (00000000 00000000)
+
+PPC integer store insns with three register args:
+ stbx 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ stbx 0000001cbe991def, 8 => ef00000000000000, 0 (00000000 00000000)
+ stbx ffffffffffffffff, 16 => ff00000000000000, 0 (00000000 00000000)
+
+ stbux 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ stbux 0000001cbe991def, 8 => ef00000000000000, 8 (00000000 00000000)
+ stbux ffffffffffffffff, 16 => ff00000000000000, 16 (00000000 00000000)
+
+ sthx 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ sthx 0000001cbe991def, 8 => 1def000000000000, 0 (00000000 00000000)
+ sthx ffffffffffffffff, 16 => ffff000000000000, 0 (00000000 00000000)
+
+ sthux 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ sthux 0000001cbe991def, 8 => 1def000000000000, 8 (00000000 00000000)
+ sthux ffffffffffffffff, 16 => ffff000000000000, 16 (00000000 00000000)
+
+ stwx 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ stwx 0000001cbe991def, 8 => be991def00000000, 0 (00000000 00000000)
+ stwx ffffffffffffffff, 16 => ffffffff00000000, 0 (00000000 00000000)
+
+ stwux 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ stwux 0000001cbe991def, 8 => be991def00000000, 8 (00000000 00000000)
+ stwux ffffffffffffffff, 16 => ffffffff00000000, 16 (00000000 00000000)
+
+ stdx 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ stdx 0000001cbe991def, 8 => 0000001cbe991def, 0 (00000000 00000000)
+ stdx ffffffffffffffff, 16 => ffffffffffffffff, 0 (00000000 00000000)
+
+ stdux 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ stdux 0000001cbe991def, 8 => 0000001cbe991def, 8 (00000000 00000000)
+ stdux ffffffffffffffff, 16 => ffffffffffffffff, 16 (00000000 00000000)
+
+All done. Tested 131 different instructions
diff --git a/none/tests/ppc64/jm-int_other.stdout.exp-LE b/none/tests/ppc64/jm-int_other.stdout.exp-LE
new file mode 100644
index 0000000..5cc903d
--- /dev/null
+++ b/none/tests/ppc64/jm-int_other.stdout.exp-LE
@@ -0,0 +1,3978 @@
+PPC integer logical insns with two args:
+ and 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ and 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ and 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ and 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ and 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+ and 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 00000000)
+ and ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ and ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+ and ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+
+ andc 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ andc 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ andc 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ andc 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
+ andc 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ andc 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ andc ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ andc ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
+ andc ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+ eqv 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ eqv 0000000000000000, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
+ eqv 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ eqv 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (00000000 00000000)
+ eqv 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
+ eqv 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 00000000)
+ eqv ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ eqv ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+ eqv ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+
+ nand 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ nand 0000000000000000, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
+ nand 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+ nand 0000001cbe991def, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ nand 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
+ nand 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 00000000)
+ nand ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ nand ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
+ nand ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+ nor 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ nor 0000000000000000, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
+ nor 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ nor 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (00000000 00000000)
+ nor 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
+ nor 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ nor ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ nor ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ nor ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+ or 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ or 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+ or 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+ or 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
+ or 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+ or 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+ or ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ or ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
+ or ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+
+ orc 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ orc 0000000000000000, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
+ orc 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ orc 0000001cbe991def, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ orc 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
+ orc 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 00000000)
+ orc ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ orc ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
+ orc ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+
+ xor 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ xor 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+ xor 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+ xor 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
+ xor 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ xor 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 00000000)
+ xor ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ xor ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
+ xor ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+ slw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ slw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ slw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ slw 0000001cbe991def, 0000000000000000 => 00000000be991def (00000000 00000000)
+ slw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ slw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ slw ffffffffffffffff, 0000000000000000 => 00000000ffffffff (00000000 00000000)
+ slw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ slw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+ sraw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ sraw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ sraw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ sraw 0000001cbe991def, 0000000000000000 => ffffffffbe991def (00000000 00000000)
+ sraw 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 20000000)
+ sraw 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
+ sraw ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ sraw ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 20000000)
+ sraw ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
+
+ srw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ srw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ srw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ srw 0000001cbe991def, 0000000000000000 => 00000000be991def (00000000 00000000)
+ srw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ srw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ srw ffffffffffffffff, 0000000000000000 => 00000000ffffffff (00000000 00000000)
+ srw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ srw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+ sld 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ sld 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ sld 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ sld 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
+ sld 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ sld 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ sld ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ sld ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ sld ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+ srad 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ srad 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ srad 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ srad 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
+ srad 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ srad 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ srad ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ srad ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 20000000)
+ srad ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
+
+ srd 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+ srd 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ srd 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ srd 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
+ srd 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ srd 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+ srd ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+ srd ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ srd ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+PPC integer logical insns with two args with flags update:
+ and. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ and. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ and. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ and. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ and. 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+ and. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 00000000)
+ and. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ and. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+ and. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+
+ andc. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ andc. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ andc. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ andc. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
+ andc. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ andc. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ andc. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ andc. ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
+ andc. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+ eqv. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ eqv. 0000000000000000, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
+ eqv. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ eqv. 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (80000000 00000000)
+ eqv. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
+ eqv. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 00000000)
+ eqv. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ eqv. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+ eqv. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+
+ nand. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ nand. 0000000000000000, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
+ nand. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+ nand. 0000001cbe991def, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ nand. 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
+ nand. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 00000000)
+ nand. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ nand. ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
+ nand. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+ nor. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ nor. 0000000000000000, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
+ nor. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ nor. 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (80000000 00000000)
+ nor. 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
+ nor. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ nor. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ nor. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ nor. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+ or. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ or. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+ or. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+ or. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
+ or. 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+ or. 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+ or. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ or. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
+ or. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+
+ orc. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ orc. 0000000000000000, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
+ orc. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ orc. 0000001cbe991def, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ orc. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
+ orc. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 00000000)
+ orc. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ orc. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
+ orc. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+
+ xor. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ xor. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+ xor. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+ xor. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
+ xor. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ xor. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 00000000)
+ xor. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ xor. ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
+ xor. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+ slw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ slw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ slw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ slw. 0000001cbe991def, 0000000000000000 => 00000000be991def (40000000 00000000)
+ slw. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ slw. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ slw. ffffffffffffffff, 0000000000000000 => 00000000ffffffff (40000000 00000000)
+ slw. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ slw. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+ sraw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ sraw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ sraw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ sraw. 0000001cbe991def, 0000000000000000 => ffffffffbe991def (80000000 00000000)
+ sraw. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 20000000)
+ sraw. 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
+ sraw. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ sraw. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 20000000)
+ sraw. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
+
+ srw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ srw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ srw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ srw. 0000001cbe991def, 0000000000000000 => 00000000be991def (40000000 00000000)
+ srw. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ srw. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ srw. ffffffffffffffff, 0000000000000000 => 00000000ffffffff (40000000 00000000)
+ srw. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ srw. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+ sld. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ sld. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ sld. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ sld. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
+ sld. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ sld. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ sld. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ sld. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ sld. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+ srad. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ srad. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ srad. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ srad. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
+ srad. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ srad. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ srad. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ srad. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 20000000)
+ srad. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
+
+ srd. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+ srd. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ srd. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ srd. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
+ srd. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ srd. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+ srd. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+ srd. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ srd. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+PPC integer compare insns (two args):
+ cmpw 0000000000000000, 0000000000000000 => 0000000000000000 (00200000 00000000)
+ cmpw 0000000000000000, 0000001cbe991def => 0000000000000000 (00400000 00000000)
+ cmpw 0000000000000000, ffffffffffffffff => 0000000000000000 (00400000 00000000)
+ cmpw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00800000 00000000)
+ cmpw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00200000 00000000)
+ cmpw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00800000 00000000)
+ cmpw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00800000 00000000)
+ cmpw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00400000 00000000)
+ cmpw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00200000 00000000)
+
+ cmplw 0000000000000000, 0000000000000000 => 0000000000000000 (00200000 00000000)
+ cmplw 0000000000000000, 0000001cbe991def => 0000000000000000 (00800000 00000000)
+ cmplw 0000000000000000, ffffffffffffffff => 0000000000000000 (00800000 00000000)
+ cmplw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00400000 00000000)
+ cmplw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00200000 00000000)
+ cmplw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00800000 00000000)
+ cmplw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00400000 00000000)
+ cmplw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00400000 00000000)
+ cmplw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00200000 00000000)
+
+ cmpd 0000000000000000, 0000000000000000 => 0000000000000000 (00200000 00000000)
+ cmpd 0000000000000000, 0000001cbe991def => 0000000000000000 (00800000 00000000)
+ cmpd 0000000000000000, ffffffffffffffff => 0000000000000000 (00400000 00000000)
+ cmpd 0000001cbe991def, 0000000000000000 => 0000000000000000 (00400000 00000000)
+ cmpd 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00200000 00000000)
+ cmpd 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00400000 00000000)
+ cmpd ffffffffffffffff, 0000000000000000 => 0000000000000000 (00800000 00000000)
+ cmpd ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00800000 00000000)
+ cmpd ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00200000 00000000)
+
+ cmpld 0000000000000000, 0000000000000000 => 0000000000000000 (00200000 00000000)
+ cmpld 0000000000000000, 0000001cbe991def => 0000000000000000 (00800000 00000000)
+ cmpld 0000000000000000, ffffffffffffffff => 0000000000000000 (00800000 00000000)
+ cmpld 0000001cbe991def, 0000000000000000 => 0000000000000000 (00400000 00000000)
+ cmpld 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00200000 00000000)
+ cmpld 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00800000 00000000)
+ cmpld ffffffffffffffff, 0000000000000000 => 0000000000000000 (00400000 00000000)
+ cmpld ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00400000 00000000)
+ cmpld ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00200000 00000000)
+
+PPC integer compare with immediate insns (two args):
+ cmpwi 0000000000000000, 00000000 => 0000000000000000 (00200000 00000000)
+ cmpwi 0000000000000000, 000003e7 => 0000000000000000 (00800000 00000000)
+ cmpwi 0000000000000000, 0000ffff => 0000000000000000 (00400000 00000000)
+ cmpwi 0000001cbe991def, 00000000 => 0000000000000000 (00800000 00000000)
+ cmpwi 0000001cbe991def, 000003e7 => 0000000000000000 (00800000 00000000)
+ cmpwi 0000001cbe991def, 0000ffff => 0000000000000000 (00800000 00000000)
+ cmpwi ffffffffffffffff, 00000000 => 0000000000000000 (00800000 00000000)
+ cmpwi ffffffffffffffff, 000003e7 => 0000000000000000 (00800000 00000000)
+ cmpwi ffffffffffffffff, 0000ffff => 0000000000000000 (00200000 00000000)
+
+ cmplwi 0000000000000000, 00000000 => 0000000000000000 (00200000 00000000)
+ cmplwi 0000000000000000, 000003e7 => 0000000000000000 (00800000 00000000)
+ cmplwi 0000000000000000, 0000ffff => 0000000000000000 (00800000 00000000)
+ cmplwi 0000001cbe991def, 00000000 => 0000000000000000 (00400000 00000000)
+ cmplwi 0000001cbe991def, 000003e7 => 0000000000000000 (00400000 00000000)
+ cmplwi 0000001cbe991def, 0000ffff => 0000000000000000 (00400000 00000000)
+ cmplwi ffffffffffffffff, 00000000 => 0000000000000000 (00400000 00000000)
+ cmplwi ffffffffffffffff, 000003e7 => 0000000000000000 (00400000 00000000)
+ cmplwi ffffffffffffffff, 0000ffff => 0000000000000000 (00400000 00000000)
+
+ cmpdi 0000000000000000, 00000000 => 0000000000000000 (00200000 00000000)
+ cmpdi 0000000000000000, 000003e7 => 0000000000000000 (00800000 00000000)
+ cmpdi 0000000000000000, 0000ffff => 0000000000000000 (00400000 00000000)
+ cmpdi 0000001cbe991def, 00000000 => 0000000000000000 (00400000 00000000)
+ cmpdi 0000001cbe991def, 000003e7 => 0000000000000000 (00400000 00000000)
+ cmpdi 0000001cbe991def, 0000ffff => 0000000000000000 (00400000 00000000)
+ cmpdi ffffffffffffffff, 00000000 => 0000000000000000 (00800000 00000000)
+ cmpdi ffffffffffffffff, 000003e7 => 0000000000000000 (00800000 00000000)
+ cmpdi ffffffffffffffff, 0000ffff => 0000000000000000 (00200000 00000000)
+
+ cmpldi 0000000000000000, 00000000 => 0000000000000000 (00200000 00000000)
+ cmpldi 0000000000000000, 000003e7 => 0000000000000000 (00800000 00000000)
+ cmpldi 0000000000000000, 0000ffff => 0000000000000000 (00800000 00000000)
+ cmpldi 0000001cbe991def, 00000000 => 0000000000000000 (00400000 00000000)
+ cmpldi 0000001cbe991def, 000003e7 => 0000000000000000 (00400000 00000000)
+ cmpldi 0000001cbe991def, 0000ffff => 0000000000000000 (00400000 00000000)
+ cmpldi ffffffffffffffff, 00000000 => 0000000000000000 (00400000 00000000)
+ cmpldi ffffffffffffffff, 000003e7 => 0000000000000000 (00400000 00000000)
+ cmpldi ffffffffffffffff, 0000ffff => 0000000000000000 (00400000 00000000)
+
+PPC integer logical insns
+ with one register + one 16 bits immediate args:
+ ori 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
+ ori 0000000000000000, 000003e7 => 00000000000003e7 (00000000 00000000)
+ ori 0000000000000000, 0000ffff => 000000000000ffff (00000000 00000000)
+ ori 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
+ ori 0000001cbe991def, 000003e7 => 0000001cbe991fef (00000000 00000000)
+ ori 0000001cbe991def, 0000ffff => 0000001cbe99ffff (00000000 00000000)
+ ori ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
+ ori ffffffffffffffff, 000003e7 => ffffffffffffffff (00000000 00000000)
+ ori ffffffffffffffff, 0000ffff => ffffffffffffffff (00000000 00000000)
+
+ oris 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
+ oris 0000000000000000, 000003e7 => 0000000003e70000 (00000000 00000000)
+ oris 0000000000000000, 0000ffff => 00000000ffff0000 (00000000 00000000)
+ oris 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
+ oris 0000001cbe991def, 000003e7 => 0000001cbfff1def (00000000 00000000)
+ oris 0000001cbe991def, 0000ffff => 0000001cffff1def (00000000 00000000)
+ oris ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
+ oris ffffffffffffffff, 000003e7 => ffffffffffffffff (00000000 00000000)
+ oris ffffffffffffffff, 0000ffff => ffffffffffffffff (00000000 00000000)
+
+ xori 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
+ xori 0000000000000000, 000003e7 => 00000000000003e7 (00000000 00000000)
+ xori 0000000000000000, 0000ffff => 000000000000ffff (00000000 00000000)
+ xori 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
+ xori 0000001cbe991def, 000003e7 => 0000001cbe991e08 (00000000 00000000)
+ xori 0000001cbe991def, 0000ffff => 0000001cbe99e210 (00000000 00000000)
+ xori ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
+ xori ffffffffffffffff, 000003e7 => fffffffffffffc18 (00000000 00000000)
+ xori ffffffffffffffff, 0000ffff => ffffffffffff0000 (00000000 00000000)
+
+ xoris 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
+ xoris 0000000000000000, 000003e7 => 0000000003e70000 (00000000 00000000)
+ xoris 0000000000000000, 0000ffff => 00000000ffff0000 (00000000 00000000)
+ xoris 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
+ xoris 0000001cbe991def, 000003e7 => 0000001cbd7e1def (00000000 00000000)
+ xoris 0000001cbe991def, 0000ffff => 0000001c41661def (00000000 00000000)
+ xoris ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
+ xoris ffffffffffffffff, 000003e7 => fffffffffc18ffff (00000000 00000000)
+ xoris ffffffffffffffff, 0000ffff => ffffffff0000ffff (00000000 00000000)
+
+PPC integer logical insns
+ with one register + one 16 bits immediate args with flags update:
+ andi. 0000000000000000, 00000000 => 0000000000000000 (20000000 00000000)
+ andi. 0000000000000000, 000003e7 => 0000000000000000 (20000000 00000000)
+ andi. 0000000000000000, 0000ffff => 0000000000000000 (20000000 00000000)
+ andi. 0000001cbe991def, 00000000 => 0000000000000000 (20000000 00000000)
+ andi. 0000001cbe991def, 000003e7 => 00000000000001e7 (40000000 00000000)
+ andi. 0000001cbe991def, 0000ffff => 0000000000001def (40000000 00000000)
+ andi. ffffffffffffffff, 00000000 => 0000000000000000 (20000000 00000000)
+ andi. ffffffffffffffff, 000003e7 => 00000000000003e7 (40000000 00000000)
+ andi. ffffffffffffffff, 0000ffff => 000000000000ffff (40000000 00000000)
+
+ andis. 0000000000000000, 00000000 => 0000000000000000 (20000000 00000000)
+ andis. 0000000000000000, 000003e7 => 0000000000000000 (20000000 00000000)
+ andis. 0000000000000000, 0000ffff => 0000000000000000 (20000000 00000000)
+ andis. 0000001cbe991def, 00000000 => 0000000000000000 (20000000 00000000)
+ andis. 0000001cbe991def, 000003e7 => 0000000002810000 (40000000 00000000)
+ andis. 0000001cbe991def, 0000ffff => 00000000be990000 (40000000 00000000)
+ andis. ffffffffffffffff, 00000000 => 0000000000000000 (20000000 00000000)
+ andis. ffffffffffffffff, 000003e7 => 0000000003e70000 (40000000 00000000)
+ andis. ffffffffffffffff, 0000ffff => 00000000ffff0000 (40000000 00000000)
+
+PPC condition register logical insns - two operands:
+ crand 0000000000000000, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
+ crand 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
+ crand 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
+ crand 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
+ crand 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
+ crand 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
+ crand ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
+ crand ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
+ crand ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
+
+ crandc 0000000000000000, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
+ crandc 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
+ crandc 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
+ crandc 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
+ crandc 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
+ crandc 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
+ crandc ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
+ crandc ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
+ crandc ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
+
+ creqv 0000000000000000, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
+ creqv 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
+ creqv 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
+ creqv 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
+ creqv 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
+ creqv 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
+ creqv ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
+ creqv ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
+ creqv ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
+
+ crnand 0000000000000000, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
+ crnand 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
+ crnand 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
+ crnand 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
+ crnand 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
+ crnand 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
+ crnand ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
+ crnand ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
+ crnand ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
+
+ crnor 0000000000000000, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
+ crnor 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
+ crnor 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
+ crnor 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
+ crnor 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
+ crnor 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
+ crnor ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
+ crnor ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
+ crnor ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
+
+ cror 0000000000000000, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
+ cror 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
+ cror 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
+ cror 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
+ cror 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
+ cror 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
+ cror ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
+ cror ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
+ cror ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
+
+ crorc 0000000000000000, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
+ crorc 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
+ crorc 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
+ crorc 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
+ crorc 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
+ crorc 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
+ crorc ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
+ crorc ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
+ crorc ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
+
+ crxor 0000000000000000, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
+ crxor 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
+ crxor 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
+ crxor 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
+ crxor 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
+ crxor 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
+ crxor ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
+ crxor ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
+ crxor ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
+
+PPC integer logical insns with one arg:
+ cntlzw 0000000000000000 => 0000000000000020 (00000000 00000000)
+ cntlzw 0000001cbe991def => 0000000000000000 (00000000 00000000)
+ cntlzw ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+ extsb 0000000000000000 => 0000000000000000 (00000000 00000000)
+ extsb 0000001cbe991def => ffffffffffffffef (00000000 00000000)
+ extsb ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+
+ extsh 0000000000000000 => 0000000000000000 (00000000 00000000)
+ extsh 0000001cbe991def => 0000000000001def (00000000 00000000)
+ extsh ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+
+ neg 0000000000000000 => 0000000000000000 (00000000 00000000)
+ neg 0000001cbe991def => ffffffe34166e211 (00000000 00000000)
+ neg ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+ nego 0000000000000000 => 0000000000000000 (00000000 00000000)
+ nego 0000001cbe991def => ffffffe34166e211 (00000000 00000000)
+ nego ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+ cntlzd 0000000000000000 => 0000000000000040 (00000000 00000000)
+ cntlzd 0000001cbe991def => 000000000000001b (00000000 00000000)
+ cntlzd ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+ extsw 0000000000000000 => 0000000000000000 (00000000 00000000)
+ extsw 0000001cbe991def => ffffffffbe991def (00000000 00000000)
+ extsw ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+
+PPC integer logical insns with one arg with flags update:
+ cntlzw. 0000000000000000 => 0000000000000020 (40000000 00000000)
+ cntlzw. 0000001cbe991def => 0000000000000000 (20000000 00000000)
+ cntlzw. ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+ extsb. 0000000000000000 => 0000000000000000 (20000000 00000000)
+ extsb. 0000001cbe991def => ffffffffffffffef (80000000 00000000)
+ extsb. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+
+ extsh. 0000000000000000 => 0000000000000000 (20000000 00000000)
+ extsh. 0000001cbe991def => 0000000000001def (40000000 00000000)
+ extsh. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+
+ neg. 0000000000000000 => 0000000000000000 (20000000 00000000)
+ neg. 0000001cbe991def => ffffffe34166e211 (80000000 00000000)
+ neg. ffffffffffffffff => 0000000000000001 (40000000 00000000)
+
+ nego. 0000000000000000 => 0000000000000000 (20000000 00000000)
+ nego. 0000001cbe991def => ffffffe34166e211 (80000000 00000000)
+ nego. ffffffffffffffff => 0000000000000001 (40000000 00000000)
+
+ cntlzd. 0000000000000000 => 0000000000000040 (40000000 00000000)
+ cntlzd. 0000001cbe991def => 000000000000001b (40000000 00000000)
+ cntlzd. ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+ extsw. 0000000000000000 => 0000000000000000 (20000000 00000000)
+ extsw. 0000001cbe991def => ffffffffbe991def (80000000 00000000)
+ extsw. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+
+PPC logical insns with special forms:
+ rlwimi 0000000000000000, 0, 0, 0 => 0000000000000000 (00000000 00000000)
+ rlwimi 0000000000000000, 0, 0, 31 => 0000000000000000 (00000000 00000000)
+ rlwimi 0000000000000000, 0, 31, 0 => 0000000000000000 (00000000 00000000)
+ rlwimi 0000000000000000, 0, 31, 31 => 0000000000000000 (00000000 00000000)
+ rlwimi 0000000000000000, 31, 0, 0 => 0000000000000000 (00000000 00000000)
+ rlwimi 0000000000000000, 31, 0, 31 => 0000000000000000 (00000000 00000000)
+ rlwimi 0000000000000000, 31, 31, 0 => 0000000000000000 (00000000 00000000)
+ rlwimi 0000000000000000, 31, 31, 31 => 0000000000000000 (00000000 00000000)
+ rlwimi 0000001cbe991def, 0, 0, 0 => 0000000080000000 (00000000 00000000)
+ rlwimi 0000001cbe991def, 0, 0, 31 => 00000000be991def (00000000 00000000)
+ rlwimi 0000001cbe991def, 0, 31, 0 => be991defbe991def (00000000 00000000)
+ rlwimi 0000001cbe991def, 0, 31, 31 => be991defbe991def (00000000 00000000)
+ rlwimi 0000001cbe991def, 31, 0, 0 => be991defbe991def (00000000 00000000)
+ rlwimi 0000001cbe991def, 31, 0, 31 => be991defdf4c8ef7 (00000000 00000000)
+ rlwimi 0000001cbe991def, 31, 31, 0 => df4c8ef7df4c8ef7 (00000000 00000000)
+ rlwimi 0000001cbe991def, 31, 31, 31 => df4c8ef7df4c8ef7 (00000000 00000000)
+ rlwimi ffffffffffffffff, 0, 0, 0 => df4c8ef7df4c8ef7 (00000000 00000000)
+ rlwimi ffffffffffffffff, 0, 0, 31 => df4c8ef7ffffffff (00000000 00000000)
+ rlwimi ffffffffffffffff, 0, 31, 0 => ffffffffffffffff (00000000 00000000)
+ rlwimi ffffffffffffffff, 0, 31, 31 => ffffffffffffffff (00000000 00000000)
+ rlwimi ffffffffffffffff, 31, 0, 0 => ffffffffffffffff (00000000 00000000)
+ rlwimi ffffffffffffffff, 31, 0, 31 => ffffffffffffffff (00000000 00000000)
+ rlwimi ffffffffffffffff, 31, 31, 0 => ffffffffffffffff (00000000 00000000)
+ rlwimi ffffffffffffffff, 31, 31, 31 => ffffffffffffffff (00000000 00000000)
+
+ rlwinm 0000000000000000, 0, 0, 0 => 0000000000000000 (00000000 00000000)
+ rlwinm 0000000000000000, 0, 0, 31 => 0000000000000000 (00000000 00000000)
+ rlwinm 0000000000000000, 0, 31, 0 => 0000000000000000 (00000000 00000000)
+ rlwinm 0000000000000000, 0, 31, 31 => 0000000000000000 (00000000 00000000)
+ rlwinm 0000000000000000, 31, 0, 0 => 0000000000000000 (00000000 00000000)
+ rlwinm 0000000000000000, 31, 0, 31 => 0000000000000000 (00000000 00000000)
+ rlwinm 0000000000000000, 31, 31, 0 => 0000000000000000 (00000000 00000000)
+ rlwinm 0000000000000000, 31, 31, 31 => 0000000000000000 (00000000 00000000)
+ rlwinm 0000001cbe991def, 0, 0, 0 => 0000000080000000 (00000000 00000000)
+ rlwinm 0000001cbe991def, 0, 0, 31 => 00000000be991def (00000000 00000000)
+ rlwinm 0000001cbe991def, 0, 31, 0 => be991def80000001 (00000000 00000000)
+ rlwinm 0000001cbe991def, 0, 31, 31 => 0000000000000001 (00000000 00000000)
+ rlwinm 0000001cbe991def, 31, 0, 0 => 0000000080000000 (00000000 00000000)
+ rlwinm 0000001cbe991def, 31, 0, 31 => 00000000df4c8ef7 (00000000 00000000)
+ rlwinm 0000001cbe991def, 31, 31, 0 => df4c8ef780000001 (00000000 00000000)
+ rlwinm 0000001cbe991def, 31, 31, 31 => 0000000000000001 (00000000 00000000)
+ rlwinm ffffffffffffffff, 0, 0, 0 => 0000000080000000 (00000000 00000000)
+ rlwinm ffffffffffffffff, 0, 0, 31 => 00000000ffffffff (00000000 00000000)
+ rlwinm ffffffffffffffff, 0, 31, 0 => ffffffff80000001 (00000000 00000000)
+ rlwinm ffffffffffffffff, 0, 31, 31 => 0000000000000001 (00000000 00000000)
+ rlwinm ffffffffffffffff, 31, 0, 0 => 0000000080000000 (00000000 00000000)
+ rlwinm ffffffffffffffff, 31, 0, 31 => 00000000ffffffff (00000000 00000000)
+ rlwinm ffffffffffffffff, 31, 31, 0 => ffffffff80000001 (00000000 00000000)
+ rlwinm ffffffffffffffff, 31, 31, 31 => 0000000000000001 (00000000 00000000)
+
+ rlwnm 0000000000000000, 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000000000000000, 0000000000000000, 0, 31 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000000000000000, 0000000000000000, 31, 0 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000000000000000, 0000000000000000, 31, 31 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000000000000000, 0000001cbe991def, 0, 0 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000000000000000, 0000001cbe991def, 0, 31 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000000000000000, 0000001cbe991def, 31, 0 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000000000000000, 0000001cbe991def, 31, 31 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000000000000000, ffffffffffffffff, 0, 0 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000000000000000, ffffffffffffffff, 0, 31 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000000000000000, ffffffffffffffff, 31, 0 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000000000000000, ffffffffffffffff, 31, 31 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000001cbe991def, 0000000000000000, 0, 0 => 0000000080000000 (00000000 00000000)
+ rlwnm 0000001cbe991def, 0000000000000000, 0, 31 => 00000000be991def (00000000 00000000)
+ rlwnm 0000001cbe991def, 0000000000000000, 31, 0 => be991def80000001 (00000000 00000000)
+ rlwnm 0000001cbe991def, 0000000000000000, 31, 31 => 0000000000000001 (00000000 00000000)
+ rlwnm 0000001cbe991def, 0000001cbe991def, 0, 0 => 0000000080000000 (00000000 00000000)
+ rlwnm 0000001cbe991def, 0000001cbe991def, 0, 31 => 000000008ef7df4c (00000000 00000000)
+ rlwnm 0000001cbe991def, 0000001cbe991def, 31, 0 => 8ef7df4c80000000 (00000000 00000000)
+ rlwnm 0000001cbe991def, 0000001cbe991def, 31, 31 => 0000000000000000 (00000000 00000000)
+ rlwnm 0000001cbe991def, ffffffffffffffff, 0, 0 => 0000000080000000 (00000000 00000000)
+ rlwnm 0000001cbe991def, ffffffffffffffff, 0, 31 => 00000000df4c8ef7 (00000000 00000000)
+ rlwnm 0000001cbe991def, ffffffffffffffff, 31, 0 => df4c8ef780000001 (00000000 00000000)
+ rlwnm 0000001cbe991def, ffffffffffffffff, 31, 31 => 0000000000000001 (00000000 00000000)
+ rlwnm ffffffffffffffff, 0000000000000000, 0, 0 => 0000000080000000 (00000000 00000000)
+ rlwnm ffffffffffffffff, 0000000000000000, 0, 31 => 00000000ffffffff (00000000 00000000)
+ rlwnm ffffffffffffffff, 0000000000000000, 31, 0 => ffffffff80000001 (00000000 00000000)
+ rlwnm ffffffffffffffff, 0000000000000000, 31, 31 => 0000000000000001 (00000000 00000000)
+ rlwnm ffffffffffffffff, 0000001cbe991def, 0, 0 => 0000000080000000 (00000000 00000000)
+ rlwnm ffffffffffffffff, 0000001cbe991def, 0, 31 => 00000000ffffffff (00000000 00000000)
+ rlwnm ffffffffffffffff, 0000001cbe991def, 31, 0 => ffffffff80000001 (00000000 00000000)
+ rlwnm ffffffffffffffff, 0000001cbe991def, 31, 31 => 0000000000000001 (00000000 00000000)
+ rlwnm ffffffffffffffff, ffffffffffffffff, 0, 0 => 0000000080000000 (00000000 00000000)
+ rlwnm ffffffffffffffff, ffffffffffffffff, 0, 31 => 00000000ffffffff (00000000 00000000)
+ rlwnm ffffffffffffffff, ffffffffffffffff, 31, 0 => ffffffff80000001 (00000000 00000000)
+ rlwnm ffffffffffffffff, ffffffffffffffff, 31, 31 => 0000000000000001 (00000000 00000000)
+
+ srawi 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
+ srawi 0000000000000000, 31 => 0000000000000000 (00000000 00000000)
+ srawi 0000001cbe991def, 0 => ffffffffbe991def (00000000 00000000)
+ srawi 0000001cbe991def, 31 => ffffffffffffffff (00000000 20000000)
+ srawi ffffffffffffffff, 0 => ffffffffffffffff (00000000 00000000)
+ srawi ffffffffffffffff, 31 => ffffffffffffffff (00000000 20000000)
+
+ mfcr (0000000000000000) => 0000000000000000 (00000000 00000000)
+ mfcr (0000001cbe991def) => 00000000be991def (be991def 00000000)
+ mfcr (ffffffffffffffff) => 00000000ffffffff (ffffffff 00000000)
+
+ mfspr 1 (00000000) -> mtxer -> mfxer => 0000000000000000
+ mfspr 1 (be991def) -> mtxer -> mfxer => 00000000a000006f
+ mfspr 1 (ffffffff) -> mtxer -> mfxer => 00000000e000007f
+ mfspr 8 (00000000) -> mtlr -> mflr => 0000000000000000
+ mfspr 8 (be991def) -> mtlr -> mflr => ffffffffbe991def
+ mfspr 8 (ffffffff) -> mtlr -> mflr => ffffffffffffffff
+ mfspr 9 (00000000) -> mtctr -> mfctr => 0000000000000000
+ mfspr 9 (be991def) -> mtctr -> mfctr => ffffffffbe991def
+ mfspr 9 (ffffffff) -> mtctr -> mfctr => ffffffffffffffff
+
+
+ rldcl 0000000000000000, 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000000000000000, 7 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000000000000000, 14 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000000000000000, 21 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000000000000000, 28 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000000000000000, 35 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000000000000000, 42 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000000000000000, 49 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000000000000000, 56 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000000000000000, 63 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000001cbe991def, 0 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000001cbe991def, 7 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000001cbe991def, 14 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000001cbe991def, 21 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000001cbe991def, 28 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000001cbe991def, 35 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000001cbe991def, 42 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000001cbe991def, 49 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000001cbe991def, 56 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, ffffffffffffffff, 0 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, ffffffffffffffff, 7 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, ffffffffffffffff, 14 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, ffffffffffffffff, 21 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, ffffffffffffffff, 28 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, ffffffffffffffff, 35 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, ffffffffffffffff, 42 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, ffffffffffffffff, 49 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, ffffffffffffffff, 56 => 0000000000000000 (00000000 00000000)
+ rldcl 0000000000000000, ffffffffffffffff, 63 => 0000000000000000 (00000000 00000000)
+ rldcl 0000001cbe991def, 0000000000000000, 0 => 0000001cbe991def (00000000 00000000)
+ rldcl 0000001cbe991def, 0000000000000000, 7 => 0000001cbe991def (00000000 00000000)
+ rldcl 0000001cbe991def, 0000000000000000, 14 => 0000001cbe991def (00000000 00000000)
+ rldcl 0000001cbe991def, 0000000000000000, 21 => 0000001cbe991def (00000000 00000000)
+ rldcl 0000001cbe991def, 0000000000000000, 28 => 0000000cbe991def (00000000 00000000)
+ rldcl 0000001cbe991def, 0000000000000000, 35 => 000000001e991def (00000000 00000000)
+ rldcl 0000001cbe991def, 0000000000000000, 42 => 0000000000191def (00000000 00000000)
+ rldcl 0000001cbe991def, 0000000000000000, 49 => 0000000000001def (00000000 00000000)
+ rldcl 0000001cbe991def, 0000000000000000, 56 => 00000000000000ef (00000000 00000000)
+ rldcl 0000001cbe991def, 0000000000000000, 63 => 0000000000000001 (00000000 00000000)
+ rldcl 0000001cbe991def, 0000001cbe991def, 0 => 8ef78000000e5f4c (00000000 00000000)
+ rldcl 0000001cbe991def, 0000001cbe991def, 7 => 00f78000000e5f4c (00000000 00000000)
+ rldcl 0000001cbe991def, 0000001cbe991def, 14 => 00038000000e5f4c (00000000 00000000)
+ rldcl 0000001cbe991def, 0000001cbe991def, 21 => 00000000000e5f4c (00000000 00000000)
+ rldcl 0000001cbe991def, 0000001cbe991def, 28 => 00000000000e5f4c (00000000 00000000)
+ rldcl 0000001cbe991def, 0000001cbe991def, 35 => 00000000000e5f4c (00000000 00000000)
+ rldcl 0000001cbe991def, 0000001cbe991def, 42 => 00000000000e5f4c (00000000 00000000)
+ rldcl 0000001cbe991def, 0000001cbe991def, 49 => 0000000000005f4c (00000000 00000000)
+ rldcl 0000001cbe991def, 0000001cbe991def, 56 => 000000000000004c (00000000 00000000)
+ rldcl 0000001cbe991def, 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000)
+ rldcl 0000001cbe991def, ffffffffffffffff, 0 => 8000000e5f4c8ef7 (00000000 00000000)
+ rldcl 0000001cbe991def, ffffffffffffffff, 7 => 0000000e5f4c8ef7 (00000000 00000000)
+ rldcl 0000001cbe991def, ffffffffffffffff, 14 => 0000000e5f4c8ef7 (00000000 00000000)
+ rldcl 0000001cbe991def, ffffffffffffffff, 21 => 0000000e5f4c8ef7 (00000000 00000000)
+ rldcl 0000001cbe991def, ffffffffffffffff, 28 => 0000000e5f4c8ef7 (00000000 00000000)
+ rldcl 0000001cbe991def, ffffffffffffffff, 35 => 000000001f4c8ef7 (00000000 00000000)
+ rldcl 0000001cbe991def, ffffffffffffffff, 42 => 00000000000c8ef7 (00000000 00000000)
+ rldcl 0000001cbe991def, ffffffffffffffff, 49 => 0000000000000ef7 (00000000 00000000)
+ rldcl 0000001cbe991def, ffffffffffffffff, 56 => 00000000000000f7 (00000000 00000000)
+ rldcl 0000001cbe991def, ffffffffffffffff, 63 => 0000000000000001 (00000000 00000000)
+ rldcl ffffffffffffffff, 0000000000000000, 0 => ffffffffffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000000000000000, 7 => 01ffffffffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000000000000000, 14 => 0003ffffffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000000000000000, 21 => 000007ffffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000000000000000, 28 => 0000000fffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000000000000000, 35 => 000000001fffffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000000000000000, 42 => 00000000003fffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000000000000000, 49 => 0000000000007fff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000000000000000, 56 => 00000000000000ff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000000000000000, 63 => 0000000000000001 (00000000 00000000)
+ rldcl ffffffffffffffff, 0000001cbe991def, 0 => ffffffffffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000001cbe991def, 7 => 01ffffffffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000001cbe991def, 14 => 0003ffffffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000001cbe991def, 21 => 000007ffffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000001cbe991def, 28 => 0000000fffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000001cbe991def, 35 => 000000001fffffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000001cbe991def, 42 => 00000000003fffff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000001cbe991def, 49 => 0000000000007fff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000001cbe991def, 56 => 00000000000000ff (00000000 00000000)
+ rldcl ffffffffffffffff, 0000001cbe991def, 63 => 0000000000000001 (00000000 00000000)
+ rldcl ffffffffffffffff, ffffffffffffffff, 0 => ffffffffffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, ffffffffffffffff, 7 => 01ffffffffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, ffffffffffffffff, 14 => 0003ffffffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, ffffffffffffffff, 21 => 000007ffffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, ffffffffffffffff, 28 => 0000000fffffffff (00000000 00000000)
+ rldcl ffffffffffffffff, ffffffffffffffff, 35 => 000000001fffffff (00000000 00000000)
+ rldcl ffffffffffffffff, ffffffffffffffff, 42 => 00000000003fffff (00000000 00000000)
+ rldcl ffffffffffffffff, ffffffffffffffff, 49 => 0000000000007fff (00000000 00000000)
+ rldcl ffffffffffffffff, ffffffffffffffff, 56 => 00000000000000ff (00000000 00000000)
+ rldcl ffffffffffffffff, ffffffffffffffff, 63 => 0000000000000001 (00000000 00000000)
+
+ rldcr 0000000000000000, 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000000000000000, 7 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000000000000000, 14 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000000000000000, 21 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000000000000000, 28 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000000000000000, 35 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000000000000000, 42 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000000000000000, 49 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000000000000000, 56 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000000000000000, 63 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000001cbe991def, 0 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000001cbe991def, 7 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000001cbe991def, 14 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000001cbe991def, 21 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000001cbe991def, 28 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000001cbe991def, 35 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000001cbe991def, 42 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000001cbe991def, 49 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000001cbe991def, 56 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, ffffffffffffffff, 0 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, ffffffffffffffff, 7 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, ffffffffffffffff, 14 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, ffffffffffffffff, 21 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, ffffffffffffffff, 28 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, ffffffffffffffff, 35 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, ffffffffffffffff, 42 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, ffffffffffffffff, 49 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, ffffffffffffffff, 56 => 0000000000000000 (00000000 00000000)
+ rldcr 0000000000000000, ffffffffffffffff, 63 => 0000000000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000000000000000, 7 => 0000000000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000000000000000, 14 => 0000000000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000000000000000, 21 => 0000000000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000000000000000, 28 => 0000001800000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000000000000000, 35 => 0000001cb0000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000000000000000, 42 => 0000001cbe800000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000000000000000, 49 => 0000001cbe990000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000000000000000, 56 => 0000001cbe991d80 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000000000000000, 63 => 0000001cbe991def (00000000 00000000)
+ rldcr 0000001cbe991def, 0000001cbe991def, 0 => 8000000000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000001cbe991def, 7 => 8e00000000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000001cbe991def, 14 => 8ef6000000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000001cbe991def, 21 => 8ef7800000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000001cbe991def, 28 => 8ef7800000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000001cbe991def, 35 => 8ef7800000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000001cbe991def, 42 => 8ef7800000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000001cbe991def, 49 => 8ef78000000e4000 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000001cbe991def, 56 => 8ef78000000e5f00 (00000000 00000000)
+ rldcr 0000001cbe991def, 0000001cbe991def, 63 => 8ef78000000e5f4c (00000000 00000000)
+ rldcr 0000001cbe991def, ffffffffffffffff, 0 => 8000000000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, ffffffffffffffff, 7 => 8000000000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, ffffffffffffffff, 14 => 8000000000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, ffffffffffffffff, 21 => 8000000000000000 (00000000 00000000)
+ rldcr 0000001cbe991def, ffffffffffffffff, 28 => 8000000800000000 (00000000 00000000)
+ rldcr 0000001cbe991def, ffffffffffffffff, 35 => 8000000e50000000 (00000000 00000000)
+ rldcr 0000001cbe991def, ffffffffffffffff, 42 => 8000000e5f400000 (00000000 00000000)
+ rldcr 0000001cbe991def, ffffffffffffffff, 49 => 8000000e5f4c8000 (00000000 00000000)
+ rldcr 0000001cbe991def, ffffffffffffffff, 56 => 8000000e5f4c8e80 (00000000 00000000)
+ rldcr 0000001cbe991def, ffffffffffffffff, 63 => 8000000e5f4c8ef7 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000000000000000, 0 => 8000000000000000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000000000000000, 7 => ff00000000000000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000000000000000, 14 => fffe000000000000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000000000000000, 21 => fffffc0000000000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000000000000000, 28 => fffffff800000000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000000000000000, 35 => fffffffff0000000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000000000000000, 42 => ffffffffffe00000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000000000000000, 49 => ffffffffffffc000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000000000000000, 56 => ffffffffffffff80 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000000000000000, 63 => ffffffffffffffff (00000000 00000000)
+ rldcr ffffffffffffffff, 0000001cbe991def, 0 => 8000000000000000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000001cbe991def, 7 => ff00000000000000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000001cbe991def, 14 => fffe000000000000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000001cbe991def, 21 => fffffc0000000000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000001cbe991def, 28 => fffffff800000000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000001cbe991def, 35 => fffffffff0000000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000001cbe991def, 42 => ffffffffffe00000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000001cbe991def, 49 => ffffffffffffc000 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000001cbe991def, 56 => ffffffffffffff80 (00000000 00000000)
+ rldcr ffffffffffffffff, 0000001cbe991def, 63 => ffffffffffffffff (00000000 00000000)
+ rldcr ffffffffffffffff, ffffffffffffffff, 0 => 8000000000000000 (00000000 00000000)
+ rldcr ffffffffffffffff, ffffffffffffffff, 7 => ff00000000000000 (00000000 00000000)
+ rldcr ffffffffffffffff, ffffffffffffffff, 14 => fffe000000000000 (00000000 00000000)
+ rldcr ffffffffffffffff, ffffffffffffffff, 21 => fffffc0000000000 (00000000 00000000)
+ rldcr ffffffffffffffff, ffffffffffffffff, 28 => fffffff800000000 (00000000 00000000)
+ rldcr ffffffffffffffff, ffffffffffffffff, 35 => fffffffff0000000 (00000000 00000000)
+ rldcr ffffffffffffffff, ffffffffffffffff, 42 => ffffffffffe00000 (00000000 00000000)
+ rldcr ffffffffffffffff, ffffffffffffffff, 49 => ffffffffffffc000 (00000000 00000000)
+ rldcr ffffffffffffffff, ffffffffffffffff, 56 => ffffffffffffff80 (00000000 00000000)
+ rldcr ffffffffffffffff, ffffffffffffffff, 63 => ffffffffffffffff (00000000 00000000)
+
+ rldic 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 0, 7 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 0, 14 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 0, 21 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 0, 28 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 0, 35 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 0, 42 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 0, 49 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 0, 56 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 0, 63 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 7, 0 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 7, 7 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 7, 14 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 7, 21 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 7, 28 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 7, 35 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 7, 42 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 7, 49 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 7, 56 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 7, 63 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 14, 0 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 14, 7 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 14, 14 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 14, 21 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 14, 28 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 14, 35 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 14, 42 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 14, 49 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 14, 56 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 14, 63 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 21, 0 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 21, 7 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 21, 14 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 21, 21 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 21, 28 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 21, 35 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 21, 42 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 21, 49 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 21, 56 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 21, 63 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 28, 0 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 28, 7 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 28, 14 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 28, 21 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 28, 28 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 28, 35 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 28, 42 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 28, 49 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 28, 56 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 28, 63 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 35, 0 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 35, 7 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 35, 14 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 35, 21 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 35, 28 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 35, 35 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 35, 42 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 35, 49 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 35, 56 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 35, 63 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 42, 0 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 42, 7 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 42, 14 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 42, 21 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 42, 28 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 42, 35 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 42, 42 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 42, 49 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 42, 56 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 42, 63 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 49, 0 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 49, 7 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 49, 14 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 49, 21 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 49, 28 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 49, 35 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 49, 42 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 49, 49 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 49, 56 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 49, 63 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 56, 0 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 56, 7 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 56, 14 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 56, 21 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 56, 28 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 56, 35 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 56, 42 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 56, 49 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 56, 56 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 56, 63 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 63, 0 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 63, 7 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 63, 14 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 63, 21 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 63, 28 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 63, 35 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 63, 42 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 63, 49 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 63, 56 => 0000000000000000 (00000000 00000000)
+ rldic 0000000000000000, 63, 63 => 0000000000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 0, 0 => 0000001cbe991def (00000000 00000000)
+ rldic 0000001cbe991def, 0, 7 => 0000001cbe991def (00000000 00000000)
+ rldic 0000001cbe991def, 0, 14 => 0000001cbe991def (00000000 00000000)
+ rldic 0000001cbe991def, 0, 21 => 0000001cbe991def (00000000 00000000)
+ rldic 0000001cbe991def, 0, 28 => 0000000cbe991def (00000000 00000000)
+ rldic 0000001cbe991def, 0, 35 => 000000001e991def (00000000 00000000)
+ rldic 0000001cbe991def, 0, 42 => 0000000000191def (00000000 00000000)
+ rldic 0000001cbe991def, 0, 49 => 0000000000001def (00000000 00000000)
+ rldic 0000001cbe991def, 0, 56 => 00000000000000ef (00000000 00000000)
+ rldic 0000001cbe991def, 0, 63 => 0000000000000001 (00000000 00000000)
+ rldic 0000001cbe991def, 7, 0 => 00000e5f4c8ef780 (00000000 00000000)
+ rldic 0000001cbe991def, 7, 7 => 00000e5f4c8ef780 (00000000 00000000)
+ rldic 0000001cbe991def, 7, 14 => 00000e5f4c8ef780 (00000000 00000000)
+ rldic 0000001cbe991def, 7, 21 => 0000065f4c8ef780 (00000000 00000000)
+ rldic 0000001cbe991def, 7, 28 => 0000000f4c8ef780 (00000000 00000000)
+ rldic 0000001cbe991def, 7, 35 => 000000000c8ef780 (00000000 00000000)
+ rldic 0000001cbe991def, 7, 42 => 00000000000ef780 (00000000 00000000)
+ rldic 0000001cbe991def, 7, 49 => 0000000000007780 (00000000 00000000)
+ rldic 0000001cbe991def, 7, 56 => 0000000000000080 (00000000 00000000)
+ rldic 0000001cbe991def, 7, 63 => 00000e5f4c8ef780 (00000000 00000000)
+ rldic 0000001cbe991def, 14, 0 => 00072fa6477bc000 (00000000 00000000)
+ rldic 0000001cbe991def, 14, 7 => 00072fa6477bc000 (00000000 00000000)
+ rldic 0000001cbe991def, 14, 14 => 00032fa6477bc000 (00000000 00000000)
+ rldic 0000001cbe991def, 14, 21 => 000007a6477bc000 (00000000 00000000)
+ rldic 0000001cbe991def, 14, 28 => 00000006477bc000 (00000000 00000000)
+ rldic 0000001cbe991def, 14, 35 => 00000000077bc000 (00000000 00000000)
+ rldic 0000001cbe991def, 14, 42 => 00000000003bc000 (00000000 00000000)
+ rldic 0000001cbe991def, 14, 49 => 0000000000004000 (00000000 00000000)
+ rldic 0000001cbe991def, 14, 56 => 00072fa6477bc000 (00000000 00000000)
+ rldic 0000001cbe991def, 14, 63 => 00072fa6477bc000 (00000000 00000000)
+ rldic 0000001cbe991def, 21, 0 => 0397d323bde00000 (00000000 00000000)
+ rldic 0000001cbe991def, 21, 7 => 0197d323bde00000 (00000000 00000000)
+ rldic 0000001cbe991def, 21, 14 => 0003d323bde00000 (00000000 00000000)
+ rldic 0000001cbe991def, 21, 21 => 00000323bde00000 (00000000 00000000)
+ rldic 0000001cbe991def, 21, 28 => 00000003bde00000 (00000000 00000000)
+ rldic 0000001cbe991def, 21, 35 => 000000001de00000 (00000000 00000000)
+ rldic 0000001cbe991def, 21, 42 => 0000000000200000 (00000000 00000000)
+ rldic 0000001cbe991def, 21, 49 => 0397d323bde00000 (00000000 00000000)
+ rldic 0000001cbe991def, 21, 56 => 0397d323bde00000 (00000000 00000000)
+ rldic 0000001cbe991def, 21, 63 => 0397d323bde00000 (00000000 00000000)
+ rldic 0000001cbe991def, 28, 0 => cbe991def0000000 (00000000 00000000)
+ rldic 0000001cbe991def, 28, 7 => 01e991def0000000 (00000000 00000000)
+ rldic 0000001cbe991def, 28, 14 => 000191def0000000 (00000000 00000000)
+ rldic 0000001cbe991def, 28, 21 => 000001def0000000 (00000000 00000000)
+ rldic 0000001cbe991def, 28, 28 => 0000000ef0000000 (00000000 00000000)
+ rldic 0000001cbe991def, 28, 35 => 0000000010000000 (00000000 00000000)
+ rldic 0000001cbe991def, 28, 42 => cbe991def0000001 (00000000 00000000)
+ rldic 0000001cbe991def, 28, 49 => cbe991def0000001 (00000000 00000000)
+ rldic 0000001cbe991def, 28, 56 => cbe991def0000001 (00000000 00000000)
+ rldic 0000001cbe991def, 28, 63 => cbe991def0000001 (00000000 00000000)
+ rldic 0000001cbe991def, 35, 0 => f4c8ef7800000000 (00000000 00000000)
+ rldic 0000001cbe991def, 35, 7 => 00c8ef7800000000 (00000000 00000000)
+ rldic 0000001cbe991def, 35, 14 => 0000ef7800000000 (00000000 00000000)
+ rldic 0000001cbe991def, 35, 21 => 0000077800000000 (00000000 00000000)
+ rldic 0000001cbe991def, 35, 28 => 0000000800000000 (00000000 00000000)
+ rldic 0000001cbe991def, 35, 35 => f4c8ef78000000e5 (00000000 00000000)
+ rldic 0000001cbe991def, 35, 42 => f4c8ef78000000e5 (00000000 00000000)
+ rldic 0000001cbe991def, 35, 49 => f4c8ef78000000e5 (00000000 00000000)
+ rldic 0000001cbe991def, 35, 56 => f4c8ef78000000e5 (00000000 00000000)
+ rldic 0000001cbe991def, 35, 63 => f4c8ef7800000001 (00000000 00000000)
+ rldic 0000001cbe991def, 42, 0 => 6477bc0000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 42, 7 => 0077bc0000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 42, 14 => 0003bc0000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 42, 21 => 0000040000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 42, 28 => 6477bc00000072fa (00000000 00000000)
+ rldic 0000001cbe991def, 42, 35 => 6477bc00000072fa (00000000 00000000)
+ rldic 0000001cbe991def, 42, 42 => 6477bc00000072fa (00000000 00000000)
+ rldic 0000001cbe991def, 42, 49 => 6477bc00000072fa (00000000 00000000)
+ rldic 0000001cbe991def, 42, 56 => 6477bc00000000fa (00000000 00000000)
+ rldic 0000001cbe991def, 42, 63 => 6477bc0000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 49, 0 => 3bde000000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 49, 7 => 01de000000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 49, 14 => 0002000000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 49, 21 => 3bde000000397d32 (00000000 00000000)
+ rldic 0000001cbe991def, 49, 28 => 3bde000000397d32 (00000000 00000000)
+ rldic 0000001cbe991def, 49, 35 => 3bde000000397d32 (00000000 00000000)
+ rldic 0000001cbe991def, 49, 42 => 3bde000000397d32 (00000000 00000000)
+ rldic 0000001cbe991def, 49, 49 => 3bde000000007d32 (00000000 00000000)
+ rldic 0000001cbe991def, 49, 56 => 3bde000000000032 (00000000 00000000)
+ rldic 0000001cbe991def, 49, 63 => 3bde000000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 56, 0 => ef00000000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 56, 7 => 0100000000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 56, 14 => ef0000001cbe991d (00000000 00000000)
+ rldic 0000001cbe991def, 56, 21 => ef0000001cbe991d (00000000 00000000)
+ rldic 0000001cbe991def, 56, 28 => ef0000001cbe991d (00000000 00000000)
+ rldic 0000001cbe991def, 56, 35 => ef0000001cbe991d (00000000 00000000)
+ rldic 0000001cbe991def, 56, 42 => ef000000003e991d (00000000 00000000)
+ rldic 0000001cbe991def, 56, 49 => ef0000000000191d (00000000 00000000)
+ rldic 0000001cbe991def, 56, 56 => ef0000000000001d (00000000 00000000)
+ rldic 0000001cbe991def, 56, 63 => ef00000000000001 (00000000 00000000)
+ rldic 0000001cbe991def, 63, 0 => 8000000000000000 (00000000 00000000)
+ rldic 0000001cbe991def, 63, 7 => 8000000e5f4c8ef7 (00000000 00000000)
+ rldic 0000001cbe991def, 63, 14 => 8000000e5f4c8ef7 (00000000 00000000)
+ rldic 0000001cbe991def, 63, 21 => 8000000e5f4c8ef7 (00000000 00000000)
+ rldic 0000001cbe991def, 63, 28 => 8000000e5f4c8ef7 (00000000 00000000)
+ rldic 0000001cbe991def, 63, 35 => 800000001f4c8ef7 (00000000 00000000)
+ rldic 0000001cbe991def, 63, 42 => 80000000000c8ef7 (00000000 00000000)
+ rldic 0000001cbe991def, 63, 49 => 8000000000000ef7 (00000000 00000000)
+ rldic 0000001cbe991def, 63, 56 => 80000000000000f7 (00000000 00000000)
+ rldic 0000001cbe991def, 63, 63 => 8000000000000001 (00000000 00000000)
+ rldic ffffffffffffffff, 0, 0 => ffffffffffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 0, 7 => 01ffffffffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 0, 14 => 0003ffffffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 0, 21 => 000007ffffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 0, 28 => 0000000fffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 0, 35 => 000000001fffffff (00000000 00000000)
+ rldic ffffffffffffffff, 0, 42 => 00000000003fffff (00000000 00000000)
+ rldic ffffffffffffffff, 0, 49 => 0000000000007fff (00000000 00000000)
+ rldic ffffffffffffffff, 0, 56 => 00000000000000ff (00000000 00000000)
+ rldic ffffffffffffffff, 0, 63 => 0000000000000001 (00000000 00000000)
+ rldic ffffffffffffffff, 7, 0 => ffffffffffffff80 (00000000 00000000)
+ rldic ffffffffffffffff, 7, 7 => 01ffffffffffff80 (00000000 00000000)
+ rldic ffffffffffffffff, 7, 14 => 0003ffffffffff80 (00000000 00000000)
+ rldic ffffffffffffffff, 7, 21 => 000007ffffffff80 (00000000 00000000)
+ rldic ffffffffffffffff, 7, 28 => 0000000fffffff80 (00000000 00000000)
+ rldic ffffffffffffffff, 7, 35 => 000000001fffff80 (00000000 00000000)
+ rldic ffffffffffffffff, 7, 42 => 00000000003fff80 (00000000 00000000)
+ rldic ffffffffffffffff, 7, 49 => 0000000000007f80 (00000000 00000000)
+ rldic ffffffffffffffff, 7, 56 => 0000000000000080 (00000000 00000000)
+ rldic ffffffffffffffff, 7, 63 => ffffffffffffff81 (00000000 00000000)
+ rldic ffffffffffffffff, 14, 0 => ffffffffffffc000 (00000000 00000000)
+ rldic ffffffffffffffff, 14, 7 => 01ffffffffffc000 (00000000 00000000)
+ rldic ffffffffffffffff, 14, 14 => 0003ffffffffc000 (00000000 00000000)
+ rldic ffffffffffffffff, 14, 21 => 000007ffffffc000 (00000000 00000000)
+ rldic ffffffffffffffff, 14, 28 => 0000000fffffc000 (00000000 00000000)
+ rldic ffffffffffffffff, 14, 35 => 000000001fffc000 (00000000 00000000)
+ rldic ffffffffffffffff, 14, 42 => 00000000003fc000 (00000000 00000000)
+ rldic ffffffffffffffff, 14, 49 => 0000000000004000 (00000000 00000000)
+ rldic ffffffffffffffff, 14, 56 => ffffffffffffc0ff (00000000 00000000)
+ rldic ffffffffffffffff, 14, 63 => ffffffffffffc001 (00000000 00000000)
+ rldic ffffffffffffffff, 21, 0 => ffffffffffe00000 (00000000 00000000)
+ rldic ffffffffffffffff, 21, 7 => 01ffffffffe00000 (00000000 00000000)
+ rldic ffffffffffffffff, 21, 14 => 0003ffffffe00000 (00000000 00000000)
+ rldic ffffffffffffffff, 21, 21 => 000007ffffe00000 (00000000 00000000)
+ rldic ffffffffffffffff, 21, 28 => 0000000fffe00000 (00000000 00000000)
+ rldic ffffffffffffffff, 21, 35 => 000000001fe00000 (00000000 00000000)
+ rldic ffffffffffffffff, 21, 42 => 0000000000200000 (00000000 00000000)
+ rldic ffffffffffffffff, 21, 49 => ffffffffffe07fff (00000000 00000000)
+ rldic ffffffffffffffff, 21, 56 => ffffffffffe000ff (00000000 00000000)
+ rldic ffffffffffffffff, 21, 63 => ffffffffffe00001 (00000000 00000000)
+ rldic ffffffffffffffff, 28, 0 => fffffffff0000000 (00000000 00000000)
+ rldic ffffffffffffffff, 28, 7 => 01fffffff0000000 (00000000 00000000)
+ rldic ffffffffffffffff, 28, 14 => 0003fffff0000000 (00000000 00000000)
+ rldic ffffffffffffffff, 28, 21 => 000007fff0000000 (00000000 00000000)
+ rldic ffffffffffffffff, 28, 28 => 0000000ff0000000 (00000000 00000000)
+ rldic ffffffffffffffff, 28, 35 => 0000000010000000 (00000000 00000000)
+ rldic ffffffffffffffff, 28, 42 => fffffffff03fffff (00000000 00000000)
+ rldic ffffffffffffffff, 28, 49 => fffffffff0007fff (00000000 00000000)
+ rldic ffffffffffffffff, 28, 56 => fffffffff00000ff (00000000 00000000)
+ rldic ffffffffffffffff, 28, 63 => fffffffff0000001 (00000000 00000000)
+ rldic ffffffffffffffff, 35, 0 => fffffff800000000 (00000000 00000000)
+ rldic ffffffffffffffff, 35, 7 => 01fffff800000000 (00000000 00000000)
+ rldic ffffffffffffffff, 35, 14 => 0003fff800000000 (00000000 00000000)
+ rldic ffffffffffffffff, 35, 21 => 000007f800000000 (00000000 00000000)
+ rldic ffffffffffffffff, 35, 28 => 0000000800000000 (00000000 00000000)
+ rldic ffffffffffffffff, 35, 35 => fffffff81fffffff (00000000 00000000)
+ rldic ffffffffffffffff, 35, 42 => fffffff8003fffff (00000000 00000000)
+ rldic ffffffffffffffff, 35, 49 => fffffff800007fff (00000000 00000000)
+ rldic ffffffffffffffff, 35, 56 => fffffff8000000ff (00000000 00000000)
+ rldic ffffffffffffffff, 35, 63 => fffffff800000001 (00000000 00000000)
+ rldic ffffffffffffffff, 42, 0 => fffffc0000000000 (00000000 00000000)
+ rldic ffffffffffffffff, 42, 7 => 01fffc0000000000 (00000000 00000000)
+ rldic ffffffffffffffff, 42, 14 => 0003fc0000000000 (00000000 00000000)
+ rldic ffffffffffffffff, 42, 21 => 0000040000000000 (00000000 00000000)
+ rldic ffffffffffffffff, 42, 28 => fffffc0fffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 42, 35 => fffffc001fffffff (00000000 00000000)
+ rldic ffffffffffffffff, 42, 42 => fffffc00003fffff (00000000 00000000)
+ rldic ffffffffffffffff, 42, 49 => fffffc0000007fff (00000000 00000000)
+ rldic ffffffffffffffff, 42, 56 => fffffc00000000ff (00000000 00000000)
+ rldic ffffffffffffffff, 42, 63 => fffffc0000000001 (00000000 00000000)
+ rldic ffffffffffffffff, 49, 0 => fffe000000000000 (00000000 00000000)
+ rldic ffffffffffffffff, 49, 7 => 01fe000000000000 (00000000 00000000)
+ rldic ffffffffffffffff, 49, 14 => 0002000000000000 (00000000 00000000)
+ rldic ffffffffffffffff, 49, 21 => fffe07ffffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 49, 28 => fffe000fffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 49, 35 => fffe00001fffffff (00000000 00000000)
+ rldic ffffffffffffffff, 49, 42 => fffe0000003fffff (00000000 00000000)
+ rldic ffffffffffffffff, 49, 49 => fffe000000007fff (00000000 00000000)
+ rldic ffffffffffffffff, 49, 56 => fffe0000000000ff (00000000 00000000)
+ rldic ffffffffffffffff, 49, 63 => fffe000000000001 (00000000 00000000)
+ rldic ffffffffffffffff, 56, 0 => ff00000000000000 (00000000 00000000)
+ rldic ffffffffffffffff, 56, 7 => 0100000000000000 (00000000 00000000)
+ rldic ffffffffffffffff, 56, 14 => ff03ffffffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 56, 21 => ff0007ffffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 56, 28 => ff00000fffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 56, 35 => ff0000001fffffff (00000000 00000000)
+ rldic ffffffffffffffff, 56, 42 => ff000000003fffff (00000000 00000000)
+ rldic ffffffffffffffff, 56, 49 => ff00000000007fff (00000000 00000000)
+ rldic ffffffffffffffff, 56, 56 => ff000000000000ff (00000000 00000000)
+ rldic ffffffffffffffff, 56, 63 => ff00000000000001 (00000000 00000000)
+ rldic ffffffffffffffff, 63, 0 => 8000000000000000 (00000000 00000000)
+ rldic ffffffffffffffff, 63, 7 => 81ffffffffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 63, 14 => 8003ffffffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 63, 21 => 800007ffffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 63, 28 => 8000000fffffffff (00000000 00000000)
+ rldic ffffffffffffffff, 63, 35 => 800000001fffffff (00000000 00000000)
+ rldic ffffffffffffffff, 63, 42 => 80000000003fffff (00000000 00000000)
+ rldic ffffffffffffffff, 63, 49 => 8000000000007fff (00000000 00000000)
+ rldic ffffffffffffffff, 63, 56 => 80000000000000ff (00000000 00000000)
+ rldic ffffffffffffffff, 63, 63 => 8000000000000001 (00000000 00000000)
+
+ rldicl 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 0, 7 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 0, 14 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 0, 21 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 0, 28 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 0, 35 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 0, 42 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 0, 49 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 0, 56 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 0, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 7, 0 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 7, 7 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 7, 14 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 7, 21 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 7, 28 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 7, 35 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 7, 42 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 7, 49 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 7, 56 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 7, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 14, 0 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 14, 7 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 14, 14 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 14, 21 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 14, 28 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 14, 35 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 14, 42 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 14, 49 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 14, 56 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 14, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 21, 0 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 21, 7 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 21, 14 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 21, 21 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 21, 28 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 21, 35 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 21, 42 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 21, 49 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 21, 56 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 21, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 28, 0 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 28, 7 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 28, 14 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 28, 21 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 28, 28 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 28, 35 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 28, 42 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 28, 49 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 28, 56 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 28, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 35, 0 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 35, 7 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 35, 14 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 35, 21 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 35, 28 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 35, 35 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 35, 42 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 35, 49 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 35, 56 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 35, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 42, 0 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 42, 7 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 42, 14 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 42, 21 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 42, 28 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 42, 35 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 42, 42 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 42, 49 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 42, 56 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 42, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 49, 0 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 49, 7 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 49, 14 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 49, 21 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 49, 28 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 49, 35 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 49, 42 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 49, 49 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 49, 56 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 49, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 56, 0 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 56, 7 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 56, 14 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 56, 21 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 56, 28 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 56, 35 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 56, 42 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 56, 49 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 56, 56 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 56, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 63, 0 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 63, 7 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 63, 14 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 63, 21 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 63, 28 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 63, 35 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 63, 42 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 63, 49 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 63, 56 => 0000000000000000 (00000000 00000000)
+ rldicl 0000000000000000, 63, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000001cbe991def, 0, 0 => 0000001cbe991def (00000000 00000000)
+ rldicl 0000001cbe991def, 0, 7 => 0000001cbe991def (00000000 00000000)
+ rldicl 0000001cbe991def, 0, 14 => 0000001cbe991def (00000000 00000000)
+ rldicl 0000001cbe991def, 0, 21 => 0000001cbe991def (00000000 00000000)
+ rldicl 0000001cbe991def, 0, 28 => 0000000cbe991def (00000000 00000000)
+ rldicl 0000001cbe991def, 0, 35 => 000000001e991def (00000000 00000000)
+ rldicl 0000001cbe991def, 0, 42 => 0000000000191def (00000000 00000000)
+ rldicl 0000001cbe991def, 0, 49 => 0000000000001def (00000000 00000000)
+ rldicl 0000001cbe991def, 0, 56 => 00000000000000ef (00000000 00000000)
+ rldicl 0000001cbe991def, 0, 63 => 0000000000000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 7, 0 => 00000e5f4c8ef780 (00000000 00000000)
+ rldicl 0000001cbe991def, 7, 7 => 00000e5f4c8ef780 (00000000 00000000)
+ rldicl 0000001cbe991def, 7, 14 => 00000e5f4c8ef780 (00000000 00000000)
+ rldicl 0000001cbe991def, 7, 21 => 0000065f4c8ef780 (00000000 00000000)
+ rldicl 0000001cbe991def, 7, 28 => 0000000f4c8ef780 (00000000 00000000)
+ rldicl 0000001cbe991def, 7, 35 => 000000000c8ef780 (00000000 00000000)
+ rldicl 0000001cbe991def, 7, 42 => 00000000000ef780 (00000000 00000000)
+ rldicl 0000001cbe991def, 7, 49 => 0000000000007780 (00000000 00000000)
+ rldicl 0000001cbe991def, 7, 56 => 0000000000000080 (00000000 00000000)
+ rldicl 0000001cbe991def, 7, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000001cbe991def, 14, 0 => 00072fa6477bc000 (00000000 00000000)
+ rldicl 0000001cbe991def, 14, 7 => 00072fa6477bc000 (00000000 00000000)
+ rldicl 0000001cbe991def, 14, 14 => 00032fa6477bc000 (00000000 00000000)
+ rldicl 0000001cbe991def, 14, 21 => 000007a6477bc000 (00000000 00000000)
+ rldicl 0000001cbe991def, 14, 28 => 00000006477bc000 (00000000 00000000)
+ rldicl 0000001cbe991def, 14, 35 => 00000000077bc000 (00000000 00000000)
+ rldicl 0000001cbe991def, 14, 42 => 00000000003bc000 (00000000 00000000)
+ rldicl 0000001cbe991def, 14, 49 => 0000000000004000 (00000000 00000000)
+ rldicl 0000001cbe991def, 14, 56 => 0000000000000000 (00000000 00000000)
+ rldicl 0000001cbe991def, 14, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000001cbe991def, 21, 0 => 0397d323bde00000 (00000000 00000000)
+ rldicl 0000001cbe991def, 21, 7 => 0197d323bde00000 (00000000 00000000)
+ rldicl 0000001cbe991def, 21, 14 => 0003d323bde00000 (00000000 00000000)
+ rldicl 0000001cbe991def, 21, 21 => 00000323bde00000 (00000000 00000000)
+ rldicl 0000001cbe991def, 21, 28 => 00000003bde00000 (00000000 00000000)
+ rldicl 0000001cbe991def, 21, 35 => 000000001de00000 (00000000 00000000)
+ rldicl 0000001cbe991def, 21, 42 => 0000000000200000 (00000000 00000000)
+ rldicl 0000001cbe991def, 21, 49 => 0000000000000000 (00000000 00000000)
+ rldicl 0000001cbe991def, 21, 56 => 0000000000000000 (00000000 00000000)
+ rldicl 0000001cbe991def, 21, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000001cbe991def, 28, 0 => cbe991def0000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 28, 7 => 01e991def0000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 28, 14 => 000191def0000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 28, 21 => 000001def0000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 28, 28 => 0000000ef0000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 28, 35 => 0000000010000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 28, 42 => 0000000000000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 28, 49 => 0000000000000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 28, 56 => 0000000000000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 28, 63 => 0000000000000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 35, 0 => f4c8ef78000000e5 (00000000 00000000)
+ rldicl 0000001cbe991def, 35, 7 => 00c8ef78000000e5 (00000000 00000000)
+ rldicl 0000001cbe991def, 35, 14 => 0000ef78000000e5 (00000000 00000000)
+ rldicl 0000001cbe991def, 35, 21 => 00000778000000e5 (00000000 00000000)
+ rldicl 0000001cbe991def, 35, 28 => 00000008000000e5 (00000000 00000000)
+ rldicl 0000001cbe991def, 35, 35 => 00000000000000e5 (00000000 00000000)
+ rldicl 0000001cbe991def, 35, 42 => 00000000000000e5 (00000000 00000000)
+ rldicl 0000001cbe991def, 35, 49 => 00000000000000e5 (00000000 00000000)
+ rldicl 0000001cbe991def, 35, 56 => 00000000000000e5 (00000000 00000000)
+ rldicl 0000001cbe991def, 35, 63 => 0000000000000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 42, 0 => 6477bc00000072fa (00000000 00000000)
+ rldicl 0000001cbe991def, 42, 7 => 0077bc00000072fa (00000000 00000000)
+ rldicl 0000001cbe991def, 42, 14 => 0003bc00000072fa (00000000 00000000)
+ rldicl 0000001cbe991def, 42, 21 => 00000400000072fa (00000000 00000000)
+ rldicl 0000001cbe991def, 42, 28 => 00000000000072fa (00000000 00000000)
+ rldicl 0000001cbe991def, 42, 35 => 00000000000072fa (00000000 00000000)
+ rldicl 0000001cbe991def, 42, 42 => 00000000000072fa (00000000 00000000)
+ rldicl 0000001cbe991def, 42, 49 => 00000000000072fa (00000000 00000000)
+ rldicl 0000001cbe991def, 42, 56 => 00000000000000fa (00000000 00000000)
+ rldicl 0000001cbe991def, 42, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000001cbe991def, 49, 0 => 3bde000000397d32 (00000000 00000000)
+ rldicl 0000001cbe991def, 49, 7 => 01de000000397d32 (00000000 00000000)
+ rldicl 0000001cbe991def, 49, 14 => 0002000000397d32 (00000000 00000000)
+ rldicl 0000001cbe991def, 49, 21 => 0000000000397d32 (00000000 00000000)
+ rldicl 0000001cbe991def, 49, 28 => 0000000000397d32 (00000000 00000000)
+ rldicl 0000001cbe991def, 49, 35 => 0000000000397d32 (00000000 00000000)
+ rldicl 0000001cbe991def, 49, 42 => 0000000000397d32 (00000000 00000000)
+ rldicl 0000001cbe991def, 49, 49 => 0000000000007d32 (00000000 00000000)
+ rldicl 0000001cbe991def, 49, 56 => 0000000000000032 (00000000 00000000)
+ rldicl 0000001cbe991def, 49, 63 => 0000000000000000 (00000000 00000000)
+ rldicl 0000001cbe991def, 56, 0 => ef0000001cbe991d (00000000 00000000)
+ rldicl 0000001cbe991def, 56, 7 => 010000001cbe991d (00000000 00000000)
+ rldicl 0000001cbe991def, 56, 14 => 000000001cbe991d (00000000 00000000)
+ rldicl 0000001cbe991def, 56, 21 => 000000001cbe991d (00000000 00000000)
+ rldicl 0000001cbe991def, 56, 28 => 000000001cbe991d (00000000 00000000)
+ rldicl 0000001cbe991def, 56, 35 => 000000001cbe991d (00000000 00000000)
+ rldicl 0000001cbe991def, 56, 42 => 00000000003e991d (00000000 00000000)
+ rldicl 0000001cbe991def, 56, 49 => 000000000000191d (00000000 00000000)
+ rldicl 0000001cbe991def, 56, 56 => 000000000000001d (00000000 00000000)
+ rldicl 0000001cbe991def, 56, 63 => 0000000000000001 (00000000 00000000)
+ rldicl 0000001cbe991def, 63, 0 => 8000000e5f4c8ef7 (00000000 00000000)
+ rldicl 0000001cbe991def, 63, 7 => 0000000e5f4c8ef7 (00000000 00000000)
+ rldicl 0000001cbe991def, 63, 14 => 0000000e5f4c8ef7 (00000000 00000000)
+ rldicl 0000001cbe991def, 63, 21 => 0000000e5f4c8ef7 (00000000 00000000)
+ rldicl 0000001cbe991def, 63, 28 => 0000000e5f4c8ef7 (00000000 00000000)
+ rldicl 0000001cbe991def, 63, 35 => 000000001f4c8ef7 (00000000 00000000)
+ rldicl 0000001cbe991def, 63, 42 => 00000000000c8ef7 (00000000 00000000)
+ rldicl 0000001cbe991def, 63, 49 => 0000000000000ef7 (00000000 00000000)
+ rldicl 0000001cbe991def, 63, 56 => 00000000000000f7 (00000000 00000000)
+ rldicl 0000001cbe991def, 63, 63 => 0000000000000001 (00000000 00000000)
+ rldicl ffffffffffffffff, 0, 0 => ffffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 0, 7 => 01ffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 0, 14 => 0003ffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 0, 21 => 000007ffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 0, 28 => 0000000fffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 0, 35 => 000000001fffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 0, 42 => 00000000003fffff (00000000 00000000)
+ rldicl ffffffffffffffff, 0, 49 => 0000000000007fff (00000000 00000000)
+ rldicl ffffffffffffffff, 0, 56 => 00000000000000ff (00000000 00000000)
+ rldicl ffffffffffffffff, 0, 63 => 0000000000000001 (00000000 00000000)
+ rldicl ffffffffffffffff, 7, 0 => ffffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 7, 7 => 01ffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 7, 14 => 0003ffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 7, 21 => 000007ffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 7, 28 => 0000000fffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 7, 35 => 000000001fffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 7, 42 => 00000000003fffff (00000000 00000000)
+ rldicl ffffffffffffffff, 7, 49 => 0000000000007fff (00000000 00000000)
+ rldicl ffffffffffffffff, 7, 56 => 00000000000000ff (00000000 00000000)
+ rldicl ffffffffffffffff, 7, 63 => 0000000000000001 (00000000 00000000)
+ rldicl ffffffffffffffff, 14, 0 => ffffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 14, 7 => 01ffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 14, 14 => 0003ffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 14, 21 => 000007ffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 14, 28 => 0000000fffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 14, 35 => 000000001fffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 14, 42 => 00000000003fffff (00000000 00000000)
+ rldicl ffffffffffffffff, 14, 49 => 0000000000007fff (00000000 00000000)
+ rldicl ffffffffffffffff, 14, 56 => 00000000000000ff (00000000 00000000)
+ rldicl ffffffffffffffff, 14, 63 => 0000000000000001 (00000000 00000000)
+ rldicl ffffffffffffffff, 21, 0 => ffffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 21, 7 => 01ffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 21, 14 => 0003ffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 21, 21 => 000007ffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 21, 28 => 0000000fffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 21, 35 => 000000001fffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 21, 42 => 00000000003fffff (00000000 00000000)
+ rldicl ffffffffffffffff, 21, 49 => 0000000000007fff (00000000 00000000)
+ rldicl ffffffffffffffff, 21, 56 => 00000000000000ff (00000000 00000000)
+ rldicl ffffffffffffffff, 21, 63 => 0000000000000001 (00000000 00000000)
+ rldicl ffffffffffffffff, 28, 0 => ffffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 28, 7 => 01ffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 28, 14 => 0003ffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 28, 21 => 000007ffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 28, 28 => 0000000fffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 28, 35 => 000000001fffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 28, 42 => 00000000003fffff (00000000 00000000)
+ rldicl ffffffffffffffff, 28, 49 => 0000000000007fff (00000000 00000000)
+ rldicl ffffffffffffffff, 28, 56 => 00000000000000ff (00000000 00000000)
+ rldicl ffffffffffffffff, 28, 63 => 0000000000000001 (00000000 00000000)
+ rldicl ffffffffffffffff, 35, 0 => ffffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 35, 7 => 01ffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 35, 14 => 0003ffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 35, 21 => 000007ffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 35, 28 => 0000000fffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 35, 35 => 000000001fffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 35, 42 => 00000000003fffff (00000000 00000000)
+ rldicl ffffffffffffffff, 35, 49 => 0000000000007fff (00000000 00000000)
+ rldicl ffffffffffffffff, 35, 56 => 00000000000000ff (00000000 00000000)
+ rldicl ffffffffffffffff, 35, 63 => 0000000000000001 (00000000 00000000)
+ rldicl ffffffffffffffff, 42, 0 => ffffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 42, 7 => 01ffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 42, 14 => 0003ffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 42, 21 => 000007ffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 42, 28 => 0000000fffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 42, 35 => 000000001fffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 42, 42 => 00000000003fffff (00000000 00000000)
+ rldicl ffffffffffffffff, 42, 49 => 0000000000007fff (00000000 00000000)
+ rldicl ffffffffffffffff, 42, 56 => 00000000000000ff (00000000 00000000)
+ rldicl ffffffffffffffff, 42, 63 => 0000000000000001 (00000000 00000000)
+ rldicl ffffffffffffffff, 49, 0 => ffffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 49, 7 => 01ffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 49, 14 => 0003ffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 49, 21 => 000007ffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 49, 28 => 0000000fffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 49, 35 => 000000001fffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 49, 42 => 00000000003fffff (00000000 00000000)
+ rldicl ffffffffffffffff, 49, 49 => 0000000000007fff (00000000 00000000)
+ rldicl ffffffffffffffff, 49, 56 => 00000000000000ff (00000000 00000000)
+ rldicl ffffffffffffffff, 49, 63 => 0000000000000001 (00000000 00000000)
+ rldicl ffffffffffffffff, 56, 0 => ffffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 56, 7 => 01ffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 56, 14 => 0003ffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 56, 21 => 000007ffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 56, 28 => 0000000fffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 56, 35 => 000000001fffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 56, 42 => 00000000003fffff (00000000 00000000)
+ rldicl ffffffffffffffff, 56, 49 => 0000000000007fff (00000000 00000000)
+ rldicl ffffffffffffffff, 56, 56 => 00000000000000ff (00000000 00000000)
+ rldicl ffffffffffffffff, 56, 63 => 0000000000000001 (00000000 00000000)
+ rldicl ffffffffffffffff, 63, 0 => ffffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 63, 7 => 01ffffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 63, 14 => 0003ffffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 63, 21 => 000007ffffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 63, 28 => 0000000fffffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 63, 35 => 000000001fffffff (00000000 00000000)
+ rldicl ffffffffffffffff, 63, 42 => 00000000003fffff (00000000 00000000)
+ rldicl ffffffffffffffff, 63, 49 => 0000000000007fff (00000000 00000000)
+ rldicl ffffffffffffffff, 63, 56 => 00000000000000ff (00000000 00000000)
+ rldicl ffffffffffffffff, 63, 63 => 0000000000000001 (00000000 00000000)
+
+ rldicr 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 0, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 0, 14 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 0, 21 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 0, 28 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 0, 35 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 0, 42 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 0, 49 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 0, 56 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 0, 63 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 7, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 7, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 7, 14 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 7, 21 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 7, 28 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 7, 35 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 7, 42 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 7, 49 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 7, 56 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 7, 63 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 14, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 14, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 14, 14 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 14, 21 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 14, 28 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 14, 35 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 14, 42 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 14, 49 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 14, 56 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 14, 63 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 21, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 21, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 21, 14 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 21, 21 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 21, 28 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 21, 35 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 21, 42 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 21, 49 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 21, 56 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 21, 63 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 28, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 28, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 28, 14 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 28, 21 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 28, 28 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 28, 35 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 28, 42 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 28, 49 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 28, 56 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 28, 63 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 35, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 35, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 35, 14 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 35, 21 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 35, 28 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 35, 35 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 35, 42 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 35, 49 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 35, 56 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 35, 63 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 42, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 42, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 42, 14 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 42, 21 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 42, 28 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 42, 35 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 42, 42 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 42, 49 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 42, 56 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 42, 63 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 49, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 49, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 49, 14 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 49, 21 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 49, 28 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 49, 35 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 49, 42 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 49, 49 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 49, 56 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 49, 63 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 56, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 56, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 56, 14 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 56, 21 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 56, 28 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 56, 35 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 56, 42 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 56, 49 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 56, 56 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 56, 63 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 63, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 63, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 63, 14 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 63, 21 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 63, 28 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 63, 35 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 63, 42 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 63, 49 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 63, 56 => 0000000000000000 (00000000 00000000)
+ rldicr 0000000000000000, 63, 63 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 0, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 0, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 0, 14 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 0, 21 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 0, 28 => 0000001800000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 0, 35 => 0000001cb0000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 0, 42 => 0000001cbe800000 (00000000 00000000)
+ rldicr 0000001cbe991def, 0, 49 => 0000001cbe990000 (00000000 00000000)
+ rldicr 0000001cbe991def, 0, 56 => 0000001cbe991d80 (00000000 00000000)
+ rldicr 0000001cbe991def, 0, 63 => 0000001cbe991def (00000000 00000000)
+ rldicr 0000001cbe991def, 7, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 7, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 7, 14 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 7, 21 => 00000c0000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 7, 28 => 00000e5800000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 7, 35 => 00000e5f40000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 7, 42 => 00000e5f4c800000 (00000000 00000000)
+ rldicr 0000001cbe991def, 7, 49 => 00000e5f4c8ec000 (00000000 00000000)
+ rldicr 0000001cbe991def, 7, 56 => 00000e5f4c8ef780 (00000000 00000000)
+ rldicr 0000001cbe991def, 7, 63 => 00000e5f4c8ef780 (00000000 00000000)
+ rldicr 0000001cbe991def, 14, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 14, 7 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 14, 14 => 0006000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 14, 21 => 00072c0000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 14, 28 => 00072fa000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 14, 35 => 00072fa640000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 14, 42 => 00072fa647600000 (00000000 00000000)
+ rldicr 0000001cbe991def, 14, 49 => 00072fa6477bc000 (00000000 00000000)
+ rldicr 0000001cbe991def, 14, 56 => 00072fa6477bc000 (00000000 00000000)
+ rldicr 0000001cbe991def, 14, 63 => 00072fa6477bc000 (00000000 00000000)
+ rldicr 0000001cbe991def, 21, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 21, 7 => 0300000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 21, 14 => 0396000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 21, 21 => 0397d00000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 21, 28 => 0397d32000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 21, 35 => 0397d323b0000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 21, 42 => 0397d323bde00000 (00000000 00000000)
+ rldicr 0000001cbe991def, 21, 49 => 0397d323bde00000 (00000000 00000000)
+ rldicr 0000001cbe991def, 21, 56 => 0397d323bde00000 (00000000 00000000)
+ rldicr 0000001cbe991def, 21, 63 => 0397d323bde00000 (00000000 00000000)
+ rldicr 0000001cbe991def, 28, 0 => 8000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 28, 7 => cb00000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 28, 14 => cbe8000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 28, 21 => cbe9900000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 28, 28 => cbe991d800000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 28, 35 => cbe991def0000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 28, 42 => cbe991def0000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 28, 49 => cbe991def0000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 28, 56 => cbe991def0000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 28, 63 => cbe991def0000001 (00000000 00000000)
+ rldicr 0000001cbe991def, 35, 0 => 8000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 35, 7 => f400000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 35, 14 => f4c8000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 35, 21 => f4c8ec0000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 35, 28 => f4c8ef7800000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 35, 35 => f4c8ef7800000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 35, 42 => f4c8ef7800000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 35, 49 => f4c8ef7800000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 35, 56 => f4c8ef7800000080 (00000000 00000000)
+ rldicr 0000001cbe991def, 35, 63 => f4c8ef78000000e5 (00000000 00000000)
+ rldicr 0000001cbe991def, 42, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 42, 7 => 6400000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 42, 14 => 6476000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 42, 21 => 6477bc0000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 42, 28 => 6477bc0000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 42, 35 => 6477bc0000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 42, 42 => 6477bc0000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 42, 49 => 6477bc0000004000 (00000000 00000000)
+ rldicr 0000001cbe991def, 42, 56 => 6477bc0000007280 (00000000 00000000)
+ rldicr 0000001cbe991def, 42, 63 => 6477bc00000072fa (00000000 00000000)
+ rldicr 0000001cbe991def, 49, 0 => 0000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 49, 7 => 3b00000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 49, 14 => 3bde000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 49, 21 => 3bde000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 49, 28 => 3bde000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 49, 35 => 3bde000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 49, 42 => 3bde000000200000 (00000000 00000000)
+ rldicr 0000001cbe991def, 49, 49 => 3bde000000394000 (00000000 00000000)
+ rldicr 0000001cbe991def, 49, 56 => 3bde000000397d00 (00000000 00000000)
+ rldicr 0000001cbe991def, 49, 63 => 3bde000000397d32 (00000000 00000000)
+ rldicr 0000001cbe991def, 56, 0 => 8000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 56, 7 => ef00000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 56, 14 => ef00000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 56, 21 => ef00000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 56, 28 => ef00000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 56, 35 => ef00000010000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 56, 42 => ef0000001ca00000 (00000000 00000000)
+ rldicr 0000001cbe991def, 56, 49 => ef0000001cbe8000 (00000000 00000000)
+ rldicr 0000001cbe991def, 56, 56 => ef0000001cbe9900 (00000000 00000000)
+ rldicr 0000001cbe991def, 56, 63 => ef0000001cbe991d (00000000 00000000)
+ rldicr 0000001cbe991def, 63, 0 => 8000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 63, 7 => 8000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 63, 14 => 8000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 63, 21 => 8000000000000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 63, 28 => 8000000800000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 63, 35 => 8000000e50000000 (00000000 00000000)
+ rldicr 0000001cbe991def, 63, 42 => 8000000e5f400000 (00000000 00000000)
+ rldicr 0000001cbe991def, 63, 49 => 8000000e5f4c8000 (00000000 00000000)
+ rldicr 0000001cbe991def, 63, 56 => 8000000e5f4c8e80 (00000000 00000000)
+ rldicr 0000001cbe991def, 63, 63 => 8000000e5f4c8ef7 (00000000 00000000)
+ rldicr ffffffffffffffff, 0, 0 => 8000000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 0, 7 => ff00000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 0, 14 => fffe000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 0, 21 => fffffc0000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 0, 28 => fffffff800000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 0, 35 => fffffffff0000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 0, 42 => ffffffffffe00000 (00000000 00000000)
+ rldicr ffffffffffffffff, 0, 49 => ffffffffffffc000 (00000000 00000000)
+ rldicr ffffffffffffffff, 0, 56 => ffffffffffffff80 (00000000 00000000)
+ rldicr ffffffffffffffff, 0, 63 => ffffffffffffffff (00000000 00000000)
+ rldicr ffffffffffffffff, 7, 0 => 8000000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 7, 7 => ff00000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 7, 14 => fffe000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 7, 21 => fffffc0000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 7, 28 => fffffff800000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 7, 35 => fffffffff0000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 7, 42 => ffffffffffe00000 (00000000 00000000)
+ rldicr ffffffffffffffff, 7, 49 => ffffffffffffc000 (00000000 00000000)
+ rldicr ffffffffffffffff, 7, 56 => ffffffffffffff80 (00000000 00000000)
+ rldicr ffffffffffffffff, 7, 63 => ffffffffffffffff (00000000 00000000)
+ rldicr ffffffffffffffff, 14, 0 => 8000000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 14, 7 => ff00000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 14, 14 => fffe000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 14, 21 => fffffc0000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 14, 28 => fffffff800000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 14, 35 => fffffffff0000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 14, 42 => ffffffffffe00000 (00000000 00000000)
+ rldicr ffffffffffffffff, 14, 49 => ffffffffffffc000 (00000000 00000000)
+ rldicr ffffffffffffffff, 14, 56 => ffffffffffffff80 (00000000 00000000)
+ rldicr ffffffffffffffff, 14, 63 => ffffffffffffffff (00000000 00000000)
+ rldicr ffffffffffffffff, 21, 0 => 8000000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 21, 7 => ff00000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 21, 14 => fffe000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 21, 21 => fffffc0000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 21, 28 => fffffff800000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 21, 35 => fffffffff0000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 21, 42 => ffffffffffe00000 (00000000 00000000)
+ rldicr ffffffffffffffff, 21, 49 => ffffffffffffc000 (00000000 00000000)
+ rldicr ffffffffffffffff, 21, 56 => ffffffffffffff80 (00000000 00000000)
+ rldicr ffffffffffffffff, 21, 63 => ffffffffffffffff (00000000 00000000)
+ rldicr ffffffffffffffff, 28, 0 => 8000000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 28, 7 => ff00000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 28, 14 => fffe000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 28, 21 => fffffc0000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 28, 28 => fffffff800000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 28, 35 => fffffffff0000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 28, 42 => ffffffffffe00000 (00000000 00000000)
+ rldicr ffffffffffffffff, 28, 49 => ffffffffffffc000 (00000000 00000000)
+ rldicr ffffffffffffffff, 28, 56 => ffffffffffffff80 (00000000 00000000)
+ rldicr ffffffffffffffff, 28, 63 => ffffffffffffffff (00000000 00000000)
+ rldicr ffffffffffffffff, 35, 0 => 8000000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 35, 7 => ff00000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 35, 14 => fffe000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 35, 21 => fffffc0000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 35, 28 => fffffff800000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 35, 35 => fffffffff0000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 35, 42 => ffffffffffe00000 (00000000 00000000)
+ rldicr ffffffffffffffff, 35, 49 => ffffffffffffc000 (00000000 00000000)
+ rldicr ffffffffffffffff, 35, 56 => ffffffffffffff80 (00000000 00000000)
+ rldicr ffffffffffffffff, 35, 63 => ffffffffffffffff (00000000 00000000)
+ rldicr ffffffffffffffff, 42, 0 => 8000000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 42, 7 => ff00000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 42, 14 => fffe000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 42, 21 => fffffc0000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 42, 28 => fffffff800000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 42, 35 => fffffffff0000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 42, 42 => ffffffffffe00000 (00000000 00000000)
+ rldicr ffffffffffffffff, 42, 49 => ffffffffffffc000 (00000000 00000000)
+ rldicr ffffffffffffffff, 42, 56 => ffffffffffffff80 (00000000 00000000)
+ rldicr ffffffffffffffff, 42, 63 => ffffffffffffffff (00000000 00000000)
+ rldicr ffffffffffffffff, 49, 0 => 8000000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 49, 7 => ff00000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 49, 14 => fffe000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 49, 21 => fffffc0000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 49, 28 => fffffff800000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 49, 35 => fffffffff0000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 49, 42 => ffffffffffe00000 (00000000 00000000)
+ rldicr ffffffffffffffff, 49, 49 => ffffffffffffc000 (00000000 00000000)
+ rldicr ffffffffffffffff, 49, 56 => ffffffffffffff80 (00000000 00000000)
+ rldicr ffffffffffffffff, 49, 63 => ffffffffffffffff (00000000 00000000)
+ rldicr ffffffffffffffff, 56, 0 => 8000000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 56, 7 => ff00000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 56, 14 => fffe000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 56, 21 => fffffc0000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 56, 28 => fffffff800000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 56, 35 => fffffffff0000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 56, 42 => ffffffffffe00000 (00000000 00000000)
+ rldicr ffffffffffffffff, 56, 49 => ffffffffffffc000 (00000000 00000000)
+ rldicr ffffffffffffffff, 56, 56 => ffffffffffffff80 (00000000 00000000)
+ rldicr ffffffffffffffff, 56, 63 => ffffffffffffffff (00000000 00000000)
+ rldicr ffffffffffffffff, 63, 0 => 8000000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 63, 7 => ff00000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 63, 14 => fffe000000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 63, 21 => fffffc0000000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 63, 28 => fffffff800000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 63, 35 => fffffffff0000000 (00000000 00000000)
+ rldicr ffffffffffffffff, 63, 42 => ffffffffffe00000 (00000000 00000000)
+ rldicr ffffffffffffffff, 63, 49 => ffffffffffffc000 (00000000 00000000)
+ rldicr ffffffffffffffff, 63, 56 => ffffffffffffff80 (00000000 00000000)
+ rldicr ffffffffffffffff, 63, 63 => ffffffffffffffff (00000000 00000000)
+
+ rldimi 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 0, 7 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 0, 14 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 0, 21 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 0, 28 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 0, 35 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 0, 42 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 0, 49 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 0, 56 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 0, 63 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 7, 0 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 7, 7 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 7, 14 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 7, 21 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 7, 28 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 7, 35 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 7, 42 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 7, 49 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 7, 56 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 7, 63 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 14, 0 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 14, 7 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 14, 14 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 14, 21 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 14, 28 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 14, 35 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 14, 42 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 14, 49 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 14, 56 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 14, 63 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 21, 0 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 21, 7 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 21, 14 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 21, 21 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 21, 28 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 21, 35 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 21, 42 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 21, 49 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 21, 56 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 21, 63 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 28, 0 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 28, 7 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 28, 14 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 28, 21 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 28, 28 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 28, 35 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 28, 42 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 28, 49 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 28, 56 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 28, 63 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 35, 0 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 35, 7 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 35, 14 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 35, 21 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 35, 28 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 35, 35 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 35, 42 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 35, 49 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 35, 56 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 35, 63 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 42, 0 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 42, 7 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 42, 14 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 42, 21 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 42, 28 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 42, 35 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 42, 42 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 42, 49 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 42, 56 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 42, 63 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 49, 0 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 49, 7 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 49, 14 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 49, 21 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 49, 28 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 49, 35 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 49, 42 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 49, 49 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 49, 56 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 49, 63 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 56, 0 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 56, 7 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 56, 14 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 56, 21 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 56, 28 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 56, 35 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 56, 42 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 56, 49 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 56, 56 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 56, 63 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 63, 0 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 63, 7 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 63, 14 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 63, 21 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 63, 28 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 63, 35 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 63, 42 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 63, 49 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 63, 56 => 0000000000000000 (00000000 00000000)
+ rldimi 0000000000000000, 63, 63 => 0000000000000000 (00000000 00000000)
+ rldimi 0000001cbe991def, 0, 0 => 0000001cbe991def (00000000 00000000)
+ rldimi 0000001cbe991def, 0, 7 => 0000001cbe991def (00000000 00000000)
+ rldimi 0000001cbe991def, 0, 14 => 0000001cbe991def (00000000 00000000)
+ rldimi 0000001cbe991def, 0, 21 => 0000001cbe991def (00000000 00000000)
+ rldimi 0000001cbe991def, 0, 28 => 0000001cbe991def (00000000 00000000)
+ rldimi 0000001cbe991def, 0, 35 => 0000001cbe991def (00000000 00000000)
+ rldimi 0000001cbe991def, 0, 42 => 0000001cbe991def (00000000 00000000)
+ rldimi 0000001cbe991def, 0, 49 => 0000001cbe991def (00000000 00000000)
+ rldimi 0000001cbe991def, 0, 56 => 0000001cbe991def (00000000 00000000)
+ rldimi 0000001cbe991def, 0, 63 => 0000001cbe991def (00000000 00000000)
+ rldimi 0000001cbe991def, 7, 0 => 00000e5f4c8ef7ef (00000000 00000000)
+ rldimi 0000001cbe991def, 7, 7 => 00000e5f4c8ef7ef (00000000 00000000)
+ rldimi 0000001cbe991def, 7, 14 => 00000e5f4c8ef7ef (00000000 00000000)
+ rldimi 0000001cbe991def, 7, 21 => 00000e5f4c8ef7ef (00000000 00000000)
+ rldimi 0000001cbe991def, 7, 28 => 00000e5f4c8ef7ef (00000000 00000000)
+ rldimi 0000001cbe991def, 7, 35 => 00000e5f4c8ef7ef (00000000 00000000)
+ rldimi 0000001cbe991def, 7, 42 => 00000e5f4c8ef7ef (00000000 00000000)
+ rldimi 0000001cbe991def, 7, 49 => 00000e5f4c8ef7ef (00000000 00000000)
+ rldimi 0000001cbe991def, 7, 56 => 00000e5f4c8ef7ef (00000000 00000000)
+ rldimi 0000001cbe991def, 7, 63 => 00000e5f4c8ef7ee (00000000 00000000)
+ rldimi 0000001cbe991def, 14, 0 => 00072fa6477bf7ee (00000000 00000000)
+ rldimi 0000001cbe991def, 14, 7 => 00072fa6477bf7ee (00000000 00000000)
+ rldimi 0000001cbe991def, 14, 14 => 00072fa6477bf7ee (00000000 00000000)
+ rldimi 0000001cbe991def, 14, 21 => 00072fa6477bf7ee (00000000 00000000)
+ rldimi 0000001cbe991def, 14, 28 => 00072fa6477bf7ee (00000000 00000000)
+ rldimi 0000001cbe991def, 14, 35 => 00072fa6477bf7ee (00000000 00000000)
+ rldimi 0000001cbe991def, 14, 42 => 00072fa6477bf7ee (00000000 00000000)
+ rldimi 0000001cbe991def, 14, 49 => 00072fa6477bf7ee (00000000 00000000)
+ rldimi 0000001cbe991def, 14, 56 => 00072fa6477bf700 (00000000 00000000)
+ rldimi 0000001cbe991def, 14, 63 => 00072fa6477bf700 (00000000 00000000)
+ rldimi 0000001cbe991def, 21, 0 => 0397d323bdfbf700 (00000000 00000000)
+ rldimi 0000001cbe991def, 21, 7 => 0397d323bdfbf700 (00000000 00000000)
+ rldimi 0000001cbe991def, 21, 14 => 0397d323bdfbf700 (00000000 00000000)
+ rldimi 0000001cbe991def, 21, 21 => 0397d323bdfbf700 (00000000 00000000)
+ rldimi 0000001cbe991def, 21, 28 => 0397d323bdfbf700 (00000000 00000000)
+ rldimi 0000001cbe991def, 21, 35 => 0397d323bdfbf700 (00000000 00000000)
+ rldimi 0000001cbe991def, 21, 42 => 0397d323bdfbf700 (00000000 00000000)
+ rldimi 0000001cbe991def, 21, 49 => 0397d323bdfb8000 (00000000 00000000)
+ rldimi 0000001cbe991def, 21, 56 => 0397d323bdfb8000 (00000000 00000000)
+ rldimi 0000001cbe991def, 21, 63 => 0397d323bdfb8000 (00000000 00000000)
+ rldimi 0000001cbe991def, 28, 0 => cbe991defdfb8000 (00000000 00000000)
+ rldimi 0000001cbe991def, 28, 7 => cbe991defdfb8000 (00000000 00000000)
+ rldimi 0000001cbe991def, 28, 14 => cbe991defdfb8000 (00000000 00000000)
+ rldimi 0000001cbe991def, 28, 21 => cbe991defdfb8000 (00000000 00000000)
+ rldimi 0000001cbe991def, 28, 28 => cbe991defdfb8000 (00000000 00000000)
+ rldimi 0000001cbe991def, 28, 35 => cbe991defdfb8000 (00000000 00000000)
+ rldimi 0000001cbe991def, 28, 42 => cbe991defdc00001 (00000000 00000000)
+ rldimi 0000001cbe991def, 28, 49 => cbe991defdc00001 (00000000 00000000)
+ rldimi 0000001cbe991def, 28, 56 => cbe991defdc00001 (00000000 00000000)
+ rldimi 0000001cbe991def, 28, 63 => cbe991defdc00001 (00000000 00000000)
+ rldimi 0000001cbe991def, 35, 0 => f4c8ef7efdc00001 (00000000 00000000)
+ rldimi 0000001cbe991def, 35, 7 => f4c8ef7efdc00001 (00000000 00000000)
+ rldimi 0000001cbe991def, 35, 14 => f4c8ef7efdc00001 (00000000 00000000)
+ rldimi 0000001cbe991def, 35, 21 => f4c8ef7efdc00001 (00000000 00000000)
+ rldimi 0000001cbe991def, 35, 28 => f4c8ef7efdc00001 (00000000 00000000)
+ rldimi 0000001cbe991def, 35, 35 => f4c8ef7ee00000e5 (00000000 00000000)
+ rldimi 0000001cbe991def, 35, 42 => f4c8ef7ee00000e5 (00000000 00000000)
+ rldimi 0000001cbe991def, 35, 49 => f4c8ef7ee00000e5 (00000000 00000000)
+ rldimi 0000001cbe991def, 35, 56 => f4c8ef7ee00000e5 (00000000 00000000)
+ rldimi 0000001cbe991def, 35, 63 => f4c8ef7ee00000e5 (00000000 00000000)
+ rldimi 0000001cbe991def, 42, 0 => 6477bf7ee00000e5 (00000000 00000000)
+ rldimi 0000001cbe991def, 42, 7 => 6477bf7ee00000e5 (00000000 00000000)
+ rldimi 0000001cbe991def, 42, 14 => 6477bf7ee00000e5 (00000000 00000000)
+ rldimi 0000001cbe991def, 42, 21 => 6477bf7ee00000e5 (00000000 00000000)
+ rldimi 0000001cbe991def, 42, 28 => 6477bf70000072fa (00000000 00000000)
+ rldimi 0000001cbe991def, 42, 35 => 6477bf70000072fa (00000000 00000000)
+ rldimi 0000001cbe991def, 42, 42 => 6477bf70000072fa (00000000 00000000)
+ rldimi 0000001cbe991def, 42, 49 => 6477bf70000072fa (00000000 00000000)
+ rldimi 0000001cbe991def, 42, 56 => 6477bf70000072fa (00000000 00000000)
+ rldimi 0000001cbe991def, 42, 63 => 6477bf70000072fa (00000000 00000000)
+ rldimi 0000001cbe991def, 49, 0 => 3bdfbf70000072fa (00000000 00000000)
+ rldimi 0000001cbe991def, 49, 7 => 3bdfbf70000072fa (00000000 00000000)
+ rldimi 0000001cbe991def, 49, 14 => 3bdfbf70000072fa (00000000 00000000)
+ rldimi 0000001cbe991def, 49, 21 => 3bdfb80000397d32 (00000000 00000000)
+ rldimi 0000001cbe991def, 49, 28 => 3bdfb80000397d32 (00000000 00000000)
+ rldimi 0000001cbe991def, 49, 35 => 3bdfb80000397d32 (00000000 00000000)
+ rldimi 0000001cbe991def, 49, 42 => 3bdfb80000397d32 (00000000 00000000)
+ rldimi 0000001cbe991def, 49, 49 => 3bdfb80000397d32 (00000000 00000000)
+ rldimi 0000001cbe991def, 49, 56 => 3bdfb80000397d32 (00000000 00000000)
+ rldimi 0000001cbe991def, 49, 63 => 3bdfb80000397d32 (00000000 00000000)
+ rldimi 0000001cbe991def, 56, 0 => efdfb80000397d32 (00000000 00000000)
+ rldimi 0000001cbe991def, 56, 7 => efdfb80000397d32 (00000000 00000000)
+ rldimi 0000001cbe991def, 56, 14 => efdc00001cbe991d (00000000 00000000)
+ rldimi 0000001cbe991def, 56, 21 => efdc00001cbe991d (00000000 00000000)
+ rldimi 0000001cbe991def, 56, 28 => efdc00001cbe991d (00000000 00000000)
+ rldimi 0000001cbe991def, 56, 35 => efdc00001cbe991d (00000000 00000000)
+ rldimi 0000001cbe991def, 56, 42 => efdc00001cbe991d (00000000 00000000)
+ rldimi 0000001cbe991def, 56, 49 => efdc00001cbe991d (00000000 00000000)
+ rldimi 0000001cbe991def, 56, 56 => efdc00001cbe991d (00000000 00000000)
+ rldimi 0000001cbe991def, 56, 63 => efdc00001cbe991d (00000000 00000000)
+ rldimi 0000001cbe991def, 63, 0 => efdc00001cbe991d (00000000 00000000)
+ rldimi 0000001cbe991def, 63, 7 => ee00000e5f4c8ef7 (00000000 00000000)
+ rldimi 0000001cbe991def, 63, 14 => ee00000e5f4c8ef7 (00000000 00000000)
+ rldimi 0000001cbe991def, 63, 21 => ee00000e5f4c8ef7 (00000000 00000000)
+ rldimi 0000001cbe991def, 63, 28 => ee00000e5f4c8ef7 (00000000 00000000)
+ rldimi 0000001cbe991def, 63, 35 => ee00000e5f4c8ef7 (00000000 00000000)
+ rldimi 0000001cbe991def, 63, 42 => ee00000e5f4c8ef7 (00000000 00000000)
+ rldimi 0000001cbe991def, 63, 49 => ee00000e5f4c8ef7 (00000000 00000000)
+ rldimi 0000001cbe991def, 63, 56 => ee00000e5f4c8ef7 (00000000 00000000)
+ rldimi 0000001cbe991def, 63, 63 => ee00000e5f4c8ef7 (00000000 00000000)
+ rldimi ffffffffffffffff, 0, 0 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 0, 7 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 0, 14 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 0, 21 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 0, 28 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 0, 35 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 0, 42 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 0, 49 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 0, 56 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 0, 63 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 7, 0 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 7, 7 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 7, 14 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 7, 21 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 7, 28 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 7, 35 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 7, 42 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 7, 49 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 7, 56 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 7, 63 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 14, 0 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 14, 7 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 14, 14 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 14, 21 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 14, 28 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 14, 35 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 14, 42 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 14, 49 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 14, 56 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 14, 63 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 21, 0 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 21, 7 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 21, 14 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 21, 21 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 21, 28 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 21, 35 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 21, 42 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 21, 49 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 21, 56 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 21, 63 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 28, 0 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 28, 7 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 28, 14 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 28, 21 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 28, 28 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 28, 35 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 28, 42 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 28, 49 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 28, 56 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 28, 63 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 35, 0 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 35, 7 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 35, 14 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 35, 21 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 35, 28 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 35, 35 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 35, 42 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 35, 49 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 35, 56 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 35, 63 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 42, 0 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 42, 7 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 42, 14 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 42, 21 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 42, 28 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 42, 35 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 42, 42 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 42, 49 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 42, 56 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 42, 63 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 49, 0 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 49, 7 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 49, 14 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 49, 21 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 49, 28 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 49, 35 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 49, 42 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 49, 49 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 49, 56 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 49, 63 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 56, 0 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 56, 7 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 56, 14 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 56, 21 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 56, 28 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 56, 35 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 56, 42 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 56, 49 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 56, 56 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 56, 63 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 63, 0 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 63, 7 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 63, 14 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 63, 21 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 63, 28 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 63, 35 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 63, 42 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 63, 49 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 63, 56 => ffffffffffffffff (00000000 00000000)
+ rldimi ffffffffffffffff, 63, 63 => ffffffffffffffff (00000000 00000000)
+
+ sradi 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
+ sradi 0000000000000000, 7 => 0000000000000000 (00000000 00000000)
+ sradi 0000000000000000, 14 => 0000000000000000 (00000000 00000000)
+ sradi 0000000000000000, 21 => 0000000000000000 (00000000 00000000)
+ sradi 0000000000000000, 28 => 0000000000000000 (00000000 00000000)
+ sradi 0000000000000000, 35 => 0000000000000000 (00000000 00000000)
+ sradi 0000000000000000, 42 => 0000000000000000 (00000000 00000000)
+ sradi 0000000000000000, 49 => 0000000000000000 (00000000 00000000)
+ sradi 0000000000000000, 56 => 0000000000000000 (00000000 00000000)
+ sradi 0000000000000000, 63 => 0000000000000000 (00000000 00000000)
+ sradi 0000001cbe991def, 0 => 0000001cbe991def (00000000 00000000)
+ sradi 0000001cbe991def, 7 => 00000000397d323b (00000000 00000000)
+ sradi 0000001cbe991def, 14 => 000000000072fa64 (00000000 00000000)
+ sradi 0000001cbe991def, 21 => 000000000000e5f4 (00000000 00000000)
+ sradi 0000001cbe991def, 28 => 00000000000001cb (00000000 00000000)
+ sradi 0000001cbe991def, 35 => 0000000000000003 (00000000 00000000)
+ sradi 0000001cbe991def, 42 => 0000000000000000 (00000000 00000000)
+ sradi 0000001cbe991def, 49 => 0000000000000000 (00000000 00000000)
+ sradi 0000001cbe991def, 56 => 0000000000000000 (00000000 00000000)
+ sradi 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000)
+ sradi ffffffffffffffff, 0 => ffffffffffffffff (00000000 00000000)
+ sradi ffffffffffffffff, 7 => ffffffffffffffff (00000000 20000000)
+ sradi ffffffffffffffff, 14 => ffffffffffffffff (00000000 20000000)
+ sradi ffffffffffffffff, 21 => ffffffffffffffff (00000000 20000000)
+ sradi ffffffffffffffff, 28 => ffffffffffffffff (00000000 20000000)
+ sradi ffffffffffffffff, 35 => ffffffffffffffff (00000000 20000000)
+ sradi ffffffffffffffff, 42 => ffffffffffffffff (00000000 20000000)
+ sradi ffffffffffffffff, 49 => ffffffffffffffff (00000000 20000000)
+ sradi ffffffffffffffff, 56 => ffffffffffffffff (00000000 20000000)
+ sradi ffffffffffffffff, 63 => ffffffffffffffff (00000000 20000000)
+
+PPC logical insns with special forms with flags update:
+ rlwimi. 0000000000000000, 0, 0, 0 => 0000000000000000 (20000000 00000000)
+ rlwimi. 0000000000000000, 0, 0, 31 => 0000000000000000 (20000000 00000000)
+ rlwimi. 0000000000000000, 0, 31, 0 => 0000000000000000 (20000000 00000000)
+ rlwimi. 0000000000000000, 0, 31, 31 => 0000000000000000 (20000000 00000000)
+ rlwimi. 0000000000000000, 31, 0, 0 => 0000000000000000 (20000000 00000000)
+ rlwimi. 0000000000000000, 31, 0, 31 => 0000000000000000 (20000000 00000000)
+ rlwimi. 0000000000000000, 31, 31, 0 => 0000000000000000 (20000000 00000000)
+ rlwimi. 0000000000000000, 31, 31, 31 => 0000000000000000 (20000000 00000000)
+ rlwimi. 0000001cbe991def, 0, 0, 0 => 0000000080000000 (40000000 00000000)
+ rlwimi. 0000001cbe991def, 0, 0, 31 => 00000000be991def (40000000 00000000)
+ rlwimi. 0000001cbe991def, 0, 31, 0 => be991defbe991def (80000000 00000000)
+ rlwimi. 0000001cbe991def, 0, 31, 31 => be991defbe991def (80000000 00000000)
+ rlwimi. 0000001cbe991def, 31, 0, 0 => be991defbe991def (80000000 00000000)
+ rlwimi. 0000001cbe991def, 31, 0, 31 => be991defdf4c8ef7 (80000000 00000000)
+ rlwimi. 0000001cbe991def, 31, 31, 0 => df4c8ef7df4c8ef7 (80000000 00000000)
+ rlwimi. 0000001cbe991def, 31, 31, 31 => df4c8ef7df4c8ef7 (80000000 00000000)
+ rlwimi. ffffffffffffffff, 0, 0, 0 => df4c8ef7df4c8ef7 (80000000 00000000)
+ rlwimi. ffffffffffffffff, 0, 0, 31 => df4c8ef7ffffffff (80000000 00000000)
+ rlwimi. ffffffffffffffff, 0, 31, 0 => ffffffffffffffff (80000000 00000000)
+ rlwimi. ffffffffffffffff, 0, 31, 31 => ffffffffffffffff (80000000 00000000)
+ rlwimi. ffffffffffffffff, 31, 0, 0 => ffffffffffffffff (80000000 00000000)
+ rlwimi. ffffffffffffffff, 31, 0, 31 => ffffffffffffffff (80000000 00000000)
+ rlwimi. ffffffffffffffff, 31, 31, 0 => ffffffffffffffff (80000000 00000000)
+ rlwimi. ffffffffffffffff, 31, 31, 31 => ffffffffffffffff (80000000 00000000)
+
+ rlwinm. 0000000000000000, 0, 0, 0 => 0000000000000000 (20000000 00000000)
+ rlwinm. 0000000000000000, 0, 0, 31 => 0000000000000000 (20000000 00000000)
+ rlwinm. 0000000000000000, 0, 31, 0 => 0000000000000000 (20000000 00000000)
+ rlwinm. 0000000000000000, 0, 31, 31 => 0000000000000000 (20000000 00000000)
+ rlwinm. 0000000000000000, 31, 0, 0 => 0000000000000000 (20000000 00000000)
+ rlwinm. 0000000000000000, 31, 0, 31 => 0000000000000000 (20000000 00000000)
+ rlwinm. 0000000000000000, 31, 31, 0 => 0000000000000000 (20000000 00000000)
+ rlwinm. 0000000000000000, 31, 31, 31 => 0000000000000000 (20000000 00000000)
+ rlwinm. 0000001cbe991def, 0, 0, 0 => 0000000080000000 (40000000 00000000)
+ rlwinm. 0000001cbe991def, 0, 0, 31 => 00000000be991def (40000000 00000000)
+ rlwinm. 0000001cbe991def, 0, 31, 0 => be991def80000001 (80000000 00000000)
+ rlwinm. 0000001cbe991def, 0, 31, 31 => 0000000000000001 (40000000 00000000)
+ rlwinm. 0000001cbe991def, 31, 0, 0 => 0000000080000000 (40000000 00000000)
+ rlwinm. 0000001cbe991def, 31, 0, 31 => 00000000df4c8ef7 (40000000 00000000)
+ rlwinm. 0000001cbe991def, 31, 31, 0 => df4c8ef780000001 (80000000 00000000)
+ rlwinm. 0000001cbe991def, 31, 31, 31 => 0000000000000001 (40000000 00000000)
+ rlwinm. ffffffffffffffff, 0, 0, 0 => 0000000080000000 (40000000 00000000)
+ rlwinm. ffffffffffffffff, 0, 0, 31 => 00000000ffffffff (40000000 00000000)
+ rlwinm. ffffffffffffffff, 0, 31, 0 => ffffffff80000001 (80000000 00000000)
+ rlwinm. ffffffffffffffff, 0, 31, 31 => 0000000000000001 (40000000 00000000)
+ rlwinm. ffffffffffffffff, 31, 0, 0 => 0000000080000000 (40000000 00000000)
+ rlwinm. ffffffffffffffff, 31, 0, 31 => 00000000ffffffff (40000000 00000000)
+ rlwinm. ffffffffffffffff, 31, 31, 0 => ffffffff80000001 (80000000 00000000)
+ rlwinm. ffffffffffffffff, 31, 31, 31 => 0000000000000001 (40000000 00000000)
+
+ rlwnm. 0000000000000000, 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000000000000000, 0000000000000000, 0, 31 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000000000000000, 0000000000000000, 31, 0 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000000000000000, 0000000000000000, 31, 31 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000000000000000, 0000001cbe991def, 0, 0 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000000000000000, 0000001cbe991def, 0, 31 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000000000000000, 0000001cbe991def, 31, 0 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000000000000000, 0000001cbe991def, 31, 31 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000000000000000, ffffffffffffffff, 0, 0 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000000000000000, ffffffffffffffff, 0, 31 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000000000000000, ffffffffffffffff, 31, 0 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000000000000000, ffffffffffffffff, 31, 31 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000001cbe991def, 0000000000000000, 0, 0 => 0000000080000000 (40000000 00000000)
+ rlwnm. 0000001cbe991def, 0000000000000000, 0, 31 => 00000000be991def (40000000 00000000)
+ rlwnm. 0000001cbe991def, 0000000000000000, 31, 0 => be991def80000001 (80000000 00000000)
+ rlwnm. 0000001cbe991def, 0000000000000000, 31, 31 => 0000000000000001 (40000000 00000000)
+ rlwnm. 0000001cbe991def, 0000001cbe991def, 0, 0 => 0000000080000000 (40000000 00000000)
+ rlwnm. 0000001cbe991def, 0000001cbe991def, 0, 31 => 000000008ef7df4c (40000000 00000000)
+ rlwnm. 0000001cbe991def, 0000001cbe991def, 31, 0 => 8ef7df4c80000000 (80000000 00000000)
+ rlwnm. 0000001cbe991def, 0000001cbe991def, 31, 31 => 0000000000000000 (20000000 00000000)
+ rlwnm. 0000001cbe991def, ffffffffffffffff, 0, 0 => 0000000080000000 (40000000 00000000)
+ rlwnm. 0000001cbe991def, ffffffffffffffff, 0, 31 => 00000000df4c8ef7 (40000000 00000000)
+ rlwnm. 0000001cbe991def, ffffffffffffffff, 31, 0 => df4c8ef780000001 (80000000 00000000)
+ rlwnm. 0000001cbe991def, ffffffffffffffff, 31, 31 => 0000000000000001 (40000000 00000000)
+ rlwnm. ffffffffffffffff, 0000000000000000, 0, 0 => 0000000080000000 (40000000 00000000)
+ rlwnm. ffffffffffffffff, 0000000000000000, 0, 31 => 00000000ffffffff (40000000 00000000)
+ rlwnm. ffffffffffffffff, 0000000000000000, 31, 0 => ffffffff80000001 (80000000 00000000)
+ rlwnm. ffffffffffffffff, 0000000000000000, 31, 31 => 0000000000000001 (40000000 00000000)
+ rlwnm. ffffffffffffffff, 0000001cbe991def, 0, 0 => 0000000080000000 (40000000 00000000)
+ rlwnm. ffffffffffffffff, 0000001cbe991def, 0, 31 => 00000000ffffffff (40000000 00000000)
+ rlwnm. ffffffffffffffff, 0000001cbe991def, 31, 0 => ffffffff80000001 (80000000 00000000)
+ rlwnm. ffffffffffffffff, 0000001cbe991def, 31, 31 => 0000000000000001 (40000000 00000000)
+ rlwnm. ffffffffffffffff, ffffffffffffffff, 0, 0 => 0000000080000000 (40000000 00000000)
+ rlwnm. ffffffffffffffff, ffffffffffffffff, 0, 31 => 00000000ffffffff (40000000 00000000)
+ rlwnm. ffffffffffffffff, ffffffffffffffff, 31, 0 => ffffffff80000001 (80000000 00000000)
+ rlwnm. ffffffffffffffff, ffffffffffffffff, 31, 31 => 0000000000000001 (40000000 00000000)
+
+ srawi. 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
+ srawi. 0000000000000000, 31 => 0000000000000000 (20000000 00000000)
+ srawi. 0000001cbe991def, 0 => ffffffffbe991def (80000000 00000000)
+ srawi. 0000001cbe991def, 31 => ffffffffffffffff (80000000 20000000)
+ srawi. ffffffffffffffff, 0 => ffffffffffffffff (80000000 00000000)
+ srawi. ffffffffffffffff, 31 => ffffffffffffffff (80000000 20000000)
+
+ mcrf 0, 0 (0000000000000000) => (00000000 00000000)
+ mcrf 0, 7 (0000000000000000) => (00000000 00000000)
+ mcrf 7, 0 (0000000000000000) => (00000000 00000000)
+ mcrf 7, 7 (0000000000000000) => (00000000 00000000)
+ mcrf 0, 0 (0000001cbe991def) => (be991def 00000000)
+ mcrf 0, 7 (0000001cbe991def) => (fe991def 00000000)
+ mcrf 7, 0 (0000001cbe991def) => (be991deb 00000000)
+ mcrf 7, 7 (0000001cbe991def) => (be991def 00000000)
+ mcrf 0, 0 (ffffffffffffffff) => (ffffffff 00000000)
+ mcrf 0, 7 (ffffffffffffffff) => (ffffffff 00000000)
+ mcrf 7, 0 (ffffffffffffffff) => (ffffffff 00000000)
+ mcrf 7, 7 (ffffffffffffffff) => (ffffffff 00000000)
+
+ mcrxr 0 (00000000) => (00000000 00000000)
+ mcrxr 1 (00000000) => (00000000 00000000)
+ mcrxr 2 (00000000) => (00000000 00000000)
+ mcrxr 3 (00000000) => (00000000 00000000)
+ mcrxr 4 (00000000) => (00000000 00000000)
+ mcrxr 5 (00000000) => (00000000 00000000)
+ mcrxr 6 (00000000) => (00000000 00000000)
+ mcrxr 7 (00000000) => (00000000 00000000)
+ mcrxr 0 (10000000) => (00000000 00000000)
+ mcrxr 1 (10000000) => (00000000 00000000)
+ mcrxr 2 (10000000) => (00000000 00000000)
+ mcrxr 3 (10000000) => (00000000 00000000)
+ mcrxr 4 (10000000) => (00000000 00000000)
+ mcrxr 5 (10000000) => (00000000 00000000)
+ mcrxr 6 (10000000) => (00000000 00000000)
+ mcrxr 7 (10000000) => (00000000 00000000)
+ mcrxr 0 (20000000) => (20000000 00000000)
+ mcrxr 1 (20000000) => (02000000 00000000)
+ mcrxr 2 (20000000) => (00200000 00000000)
+ mcrxr 3 (20000000) => (00020000 00000000)
+ mcrxr 4 (20000000) => (00002000 00000000)
+ mcrxr 5 (20000000) => (00000200 00000000)
+ mcrxr 6 (20000000) => (00000020 00000000)
+ mcrxr 7 (20000000) => (00000002 00000000)
+ mcrxr 0 (30000000) => (20000000 00000000)
+ mcrxr 1 (30000000) => (02000000 00000000)
+ mcrxr 2 (30000000) => (00200000 00000000)
+ mcrxr 3 (30000000) => (00020000 00000000)
+ mcrxr 4 (30000000) => (00002000 00000000)
+ mcrxr 5 (30000000) => (00000200 00000000)
+ mcrxr 6 (30000000) => (00000020 00000000)
+ mcrxr 7 (30000000) => (00000002 00000000)
+ mcrxr 0 (40000000) => (40000000 00000000)
+ mcrxr 1 (40000000) => (04000000 00000000)
+ mcrxr 2 (40000000) => (00400000 00000000)
+ mcrxr 3 (40000000) => (00040000 00000000)
+ mcrxr 4 (40000000) => (00004000 00000000)
+ mcrxr 5 (40000000) => (00000400 00000000)
+ mcrxr 6 (40000000) => (00000040 00000000)
+ mcrxr 7 (40000000) => (00000004 00000000)
+ mcrxr 0 (50000000) => (40000000 00000000)
+ mcrxr 1 (50000000) => (04000000 00000000)
+ mcrxr 2 (50000000) => (00400000 00000000)
+ mcrxr 3 (50000000) => (00040000 00000000)
+ mcrxr 4 (50000000) => (00004000 00000000)
+ mcrxr 5 (50000000) => (00000400 00000000)
+ mcrxr 6 (50000000) => (00000040 00000000)
+ mcrxr 7 (50000000) => (00000004 00000000)
+ mcrxr 0 (60000000) => (60000000 00000000)
+ mcrxr 1 (60000000) => (06000000 00000000)
+ mcrxr 2 (60000000) => (00600000 00000000)
+ mcrxr 3 (60000000) => (00060000 00000000)
+ mcrxr 4 (60000000) => (00006000 00000000)
+ mcrxr 5 (60000000) => (00000600 00000000)
+ mcrxr 6 (60000000) => (00000060 00000000)
+ mcrxr 7 (60000000) => (00000006 00000000)
+ mcrxr 0 (70000000) => (60000000 00000000)
+ mcrxr 1 (70000000) => (06000000 00000000)
+ mcrxr 2 (70000000) => (00600000 00000000)
+ mcrxr 3 (70000000) => (00060000 00000000)
+ mcrxr 4 (70000000) => (00006000 00000000)
+ mcrxr 5 (70000000) => (00000600 00000000)
+ mcrxr 6 (70000000) => (00000060 00000000)
+ mcrxr 7 (70000000) => (00000006 00000000)
+ mcrxr 0 (80000000) => (80000000 00000000)
+ mcrxr 1 (80000000) => (08000000 00000000)
+ mcrxr 2 (80000000) => (00800000 00000000)
+ mcrxr 3 (80000000) => (00080000 00000000)
+ mcrxr 4 (80000000) => (00008000 00000000)
+ mcrxr 5 (80000000) => (00000800 00000000)
+ mcrxr 6 (80000000) => (00000080 00000000)
+ mcrxr 7 (80000000) => (00000008 00000000)
+ mcrxr 0 (90000000) => (80000000 00000000)
+ mcrxr 1 (90000000) => (08000000 00000000)
+ mcrxr 2 (90000000) => (00800000 00000000)
+ mcrxr 3 (90000000) => (00080000 00000000)
+ mcrxr 4 (90000000) => (00008000 00000000)
+ mcrxr 5 (90000000) => (00000800 00000000)
+ mcrxr 6 (90000000) => (00000080 00000000)
+ mcrxr 7 (90000000) => (00000008 00000000)
+ mcrxr 0 (a0000000) => (a0000000 00000000)
+ mcrxr 1 (a0000000) => (0a000000 00000000)
+ mcrxr 2 (a0000000) => (00a00000 00000000)
+ mcrxr 3 (a0000000) => (000a0000 00000000)
+ mcrxr 4 (a0000000) => (0000a000 00000000)
+ mcrxr 5 (a0000000) => (00000a00 00000000)
+ mcrxr 6 (a0000000) => (000000a0 00000000)
+ mcrxr 7 (a0000000) => (0000000a 00000000)
+ mcrxr 0 (b0000000) => (a0000000 00000000)
+ mcrxr 1 (b0000000) => (0a000000 00000000)
+ mcrxr 2 (b0000000) => (00a00000 00000000)
+ mcrxr 3 (b0000000) => (000a0000 00000000)
+ mcrxr 4 (b0000000) => (0000a000 00000000)
+ mcrxr 5 (b0000000) => (00000a00 00000000)
+ mcrxr 6 (b0000000) => (000000a0 00000000)
+ mcrxr 7 (b0000000) => (0000000a 00000000)
+ mcrxr 0 (c0000000) => (c0000000 00000000)
+ mcrxr 1 (c0000000) => (0c000000 00000000)
+ mcrxr 2 (c0000000) => (00c00000 00000000)
+ mcrxr 3 (c0000000) => (000c0000 00000000)
+ mcrxr 4 (c0000000) => (0000c000 00000000)
+ mcrxr 5 (c0000000) => (00000c00 00000000)
+ mcrxr 6 (c0000000) => (000000c0 00000000)
+ mcrxr 7 (c0000000) => (0000000c 00000000)
+ mcrxr 0 (d0000000) => (c0000000 00000000)
+ mcrxr 1 (d0000000) => (0c000000 00000000)
+ mcrxr 2 (d0000000) => (00c00000 00000000)
+ mcrxr 3 (d0000000) => (000c0000 00000000)
+ mcrxr 4 (d0000000) => (0000c000 00000000)
+ mcrxr 5 (d0000000) => (00000c00 00000000)
+ mcrxr 6 (d0000000) => (000000c0 00000000)
+ mcrxr 7 (d0000000) => (0000000c 00000000)
+ mcrxr 0 (e0000000) => (e0000000 00000000)
+ mcrxr 1 (e0000000) => (0e000000 00000000)
+ mcrxr 2 (e0000000) => (00e00000 00000000)
+ mcrxr 3 (e0000000) => (000e0000 00000000)
+ mcrxr 4 (e0000000) => (0000e000 00000000)
+ mcrxr 5 (e0000000) => (00000e00 00000000)
+ mcrxr 6 (e0000000) => (000000e0 00000000)
+ mcrxr 7 (e0000000) => (0000000e 00000000)
+ mcrxr 0 (f0000000) => (e0000000 00000000)
+ mcrxr 1 (f0000000) => (0e000000 00000000)
+ mcrxr 2 (f0000000) => (00e00000 00000000)
+ mcrxr 3 (f0000000) => (000e0000 00000000)
+ mcrxr 4 (f0000000) => (0000e000 00000000)
+ mcrxr 5 (f0000000) => (00000e00 00000000)
+ mcrxr 6 (f0000000) => (000000e0 00000000)
+ mcrxr 7 (f0000000) => (0000000e 00000000)
+
+ mtcrf 0, 0000000000000000 => (00000000 00000000)
+ mtcrf 99, 0000000000000000 => (00000000 00000000)
+ mtcrf 198, 0000000000000000 => (00000000 00000000)
+ mtcrf 0, 0000001cbe991def => (00000000 00000000)
+ mtcrf 99, 0000001cbe991def => (0e9000ef 00000000)
+ mtcrf 198, 0000001cbe991def => (be000de0 00000000)
+ mtcrf 0, ffffffffffffffff => (00000000 00000000)
+ mtcrf 99, ffffffffffffffff => (0ff000ff 00000000)
+ mtcrf 198, ffffffffffffffff => (ff000ff0 00000000)
+
+ rldcl. 0000000000000000, 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000000000000000, 7 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000000000000000, 14 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000000000000000, 21 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000000000000000, 28 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000000000000000, 35 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000000000000000, 42 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000000000000000, 49 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000000000000000, 56 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000000000000000, 63 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000001cbe991def, 0 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000001cbe991def, 7 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000001cbe991def, 14 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000001cbe991def, 21 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000001cbe991def, 28 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000001cbe991def, 35 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000001cbe991def, 42 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000001cbe991def, 49 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000001cbe991def, 56 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, ffffffffffffffff, 0 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, ffffffffffffffff, 7 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, ffffffffffffffff, 14 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, ffffffffffffffff, 21 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, ffffffffffffffff, 28 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, ffffffffffffffff, 35 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, ffffffffffffffff, 42 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, ffffffffffffffff, 49 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, ffffffffffffffff, 56 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000000000000000, ffffffffffffffff, 63 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000001cbe991def, 0000000000000000, 0 => 0000001cbe991def (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000000000000000, 7 => 0000001cbe991def (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000000000000000, 14 => 0000001cbe991def (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000000000000000, 21 => 0000001cbe991def (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000000000000000, 28 => 0000000cbe991def (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000000000000000, 35 => 000000001e991def (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000000000000000, 42 => 0000000000191def (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000000000000000, 49 => 0000000000001def (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000000000000000, 56 => 00000000000000ef (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000000000000000, 63 => 0000000000000001 (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000001cbe991def, 0 => 8ef78000000e5f4c (80000000 00000000)
+ rldcl. 0000001cbe991def, 0000001cbe991def, 7 => 00f78000000e5f4c (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000001cbe991def, 14 => 00038000000e5f4c (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000001cbe991def, 21 => 00000000000e5f4c (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000001cbe991def, 28 => 00000000000e5f4c (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000001cbe991def, 35 => 00000000000e5f4c (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000001cbe991def, 42 => 00000000000e5f4c (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000001cbe991def, 49 => 0000000000005f4c (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000001cbe991def, 56 => 000000000000004c (40000000 00000000)
+ rldcl. 0000001cbe991def, 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000)
+ rldcl. 0000001cbe991def, ffffffffffffffff, 0 => 8000000e5f4c8ef7 (80000000 00000000)
+ rldcl. 0000001cbe991def, ffffffffffffffff, 7 => 0000000e5f4c8ef7 (40000000 00000000)
+ rldcl. 0000001cbe991def, ffffffffffffffff, 14 => 0000000e5f4c8ef7 (40000000 00000000)
+ rldcl. 0000001cbe991def, ffffffffffffffff, 21 => 0000000e5f4c8ef7 (40000000 00000000)
+ rldcl. 0000001cbe991def, ffffffffffffffff, 28 => 0000000e5f4c8ef7 (40000000 00000000)
+ rldcl. 0000001cbe991def, ffffffffffffffff, 35 => 000000001f4c8ef7 (40000000 00000000)
+ rldcl. 0000001cbe991def, ffffffffffffffff, 42 => 00000000000c8ef7 (40000000 00000000)
+ rldcl. 0000001cbe991def, ffffffffffffffff, 49 => 0000000000000ef7 (40000000 00000000)
+ rldcl. 0000001cbe991def, ffffffffffffffff, 56 => 00000000000000f7 (40000000 00000000)
+ rldcl. 0000001cbe991def, ffffffffffffffff, 63 => 0000000000000001 (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000000000000000, 0 => ffffffffffffffff (80000000 00000000)
+ rldcl. ffffffffffffffff, 0000000000000000, 7 => 01ffffffffffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000000000000000, 14 => 0003ffffffffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000000000000000, 21 => 000007ffffffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000000000000000, 28 => 0000000fffffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000000000000000, 35 => 000000001fffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000000000000000, 42 => 00000000003fffff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000000000000000, 49 => 0000000000007fff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000000000000000, 56 => 00000000000000ff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000000000000000, 63 => 0000000000000001 (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000001cbe991def, 0 => ffffffffffffffff (80000000 00000000)
+ rldcl. ffffffffffffffff, 0000001cbe991def, 7 => 01ffffffffffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000001cbe991def, 14 => 0003ffffffffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000001cbe991def, 21 => 000007ffffffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000001cbe991def, 28 => 0000000fffffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000001cbe991def, 35 => 000000001fffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000001cbe991def, 42 => 00000000003fffff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000001cbe991def, 49 => 0000000000007fff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000001cbe991def, 56 => 00000000000000ff (40000000 00000000)
+ rldcl. ffffffffffffffff, 0000001cbe991def, 63 => 0000000000000001 (40000000 00000000)
+ rldcl. ffffffffffffffff, ffffffffffffffff, 0 => ffffffffffffffff (80000000 00000000)
+ rldcl. ffffffffffffffff, ffffffffffffffff, 7 => 01ffffffffffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, ffffffffffffffff, 14 => 0003ffffffffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, ffffffffffffffff, 21 => 000007ffffffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, ffffffffffffffff, 28 => 0000000fffffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, ffffffffffffffff, 35 => 000000001fffffff (40000000 00000000)
+ rldcl. ffffffffffffffff, ffffffffffffffff, 42 => 00000000003fffff (40000000 00000000)
+ rldcl. ffffffffffffffff, ffffffffffffffff, 49 => 0000000000007fff (40000000 00000000)
+ rldcl. ffffffffffffffff, ffffffffffffffff, 56 => 00000000000000ff (40000000 00000000)
+ rldcl. ffffffffffffffff, ffffffffffffffff, 63 => 0000000000000001 (40000000 00000000)
+
+ rldcr. 0000000000000000, 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000000000000000, 7 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000000000000000, 14 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000000000000000, 21 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000000000000000, 28 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000000000000000, 35 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000000000000000, 42 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000000000000000, 49 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000000000000000, 56 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000000000000000, 63 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000001cbe991def, 0 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000001cbe991def, 7 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000001cbe991def, 14 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000001cbe991def, 21 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000001cbe991def, 28 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000001cbe991def, 35 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000001cbe991def, 42 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000001cbe991def, 49 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000001cbe991def, 56 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, ffffffffffffffff, 0 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, ffffffffffffffff, 7 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, ffffffffffffffff, 14 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, ffffffffffffffff, 21 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, ffffffffffffffff, 28 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, ffffffffffffffff, 35 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, ffffffffffffffff, 42 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, ffffffffffffffff, 49 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, ffffffffffffffff, 56 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000000000000000, ffffffffffffffff, 63 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000001cbe991def, 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000001cbe991def, 0000000000000000, 7 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000001cbe991def, 0000000000000000, 14 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000001cbe991def, 0000000000000000, 21 => 0000000000000000 (20000000 00000000)
+ rldcr. 0000001cbe991def, 0000000000000000, 28 => 0000001800000000 (40000000 00000000)
+ rldcr. 0000001cbe991def, 0000000000000000, 35 => 0000001cb0000000 (40000000 00000000)
+ rldcr. 0000001cbe991def, 0000000000000000, 42 => 0000001cbe800000 (40000000 00000000)
+ rldcr. 0000001cbe991def, 0000000000000000, 49 => 0000001cbe990000 (40000000 00000000)
+ rldcr. 0000001cbe991def, 0000000000000000, 56 => 0000001cbe991d80 (40000000 00000000)
+ rldcr. 0000001cbe991def, 0000000000000000, 63 => 0000001cbe991def (40000000 00000000)
+ rldcr. 0000001cbe991def, 0000001cbe991def, 0 => 8000000000000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, 0000001cbe991def, 7 => 8e00000000000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, 0000001cbe991def, 14 => 8ef6000000000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, 0000001cbe991def, 21 => 8ef7800000000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, 0000001cbe991def, 28 => 8ef7800000000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, 0000001cbe991def, 35 => 8ef7800000000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, 0000001cbe991def, 42 => 8ef7800000000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, 0000001cbe991def, 49 => 8ef78000000e4000 (80000000 00000000)
+ rldcr. 0000001cbe991def, 0000001cbe991def, 56 => 8ef78000000e5f00 (80000000 00000000)
+ rldcr. 0000001cbe991def, 0000001cbe991def, 63 => 8ef78000000e5f4c (80000000 00000000)
+ rldcr. 0000001cbe991def, ffffffffffffffff, 0 => 8000000000000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, ffffffffffffffff, 7 => 8000000000000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, ffffffffffffffff, 14 => 8000000000000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, ffffffffffffffff, 21 => 8000000000000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, ffffffffffffffff, 28 => 8000000800000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, ffffffffffffffff, 35 => 8000000e50000000 (80000000 00000000)
+ rldcr. 0000001cbe991def, ffffffffffffffff, 42 => 8000000e5f400000 (80000000 00000000)
+ rldcr. 0000001cbe991def, ffffffffffffffff, 49 => 8000000e5f4c8000 (80000000 00000000)
+ rldcr. 0000001cbe991def, ffffffffffffffff, 56 => 8000000e5f4c8e80 (80000000 00000000)
+ rldcr. 0000001cbe991def, ffffffffffffffff, 63 => 8000000e5f4c8ef7 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000000000000000, 0 => 8000000000000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000000000000000, 7 => ff00000000000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000000000000000, 14 => fffe000000000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000000000000000, 21 => fffffc0000000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000000000000000, 28 => fffffff800000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000000000000000, 35 => fffffffff0000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000000000000000, 42 => ffffffffffe00000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000000000000000, 49 => ffffffffffffc000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000000000000000, 56 => ffffffffffffff80 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000000000000000, 63 => ffffffffffffffff (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000001cbe991def, 0 => 8000000000000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000001cbe991def, 7 => ff00000000000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000001cbe991def, 14 => fffe000000000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000001cbe991def, 21 => fffffc0000000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000001cbe991def, 28 => fffffff800000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000001cbe991def, 35 => fffffffff0000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000001cbe991def, 42 => ffffffffffe00000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000001cbe991def, 49 => ffffffffffffc000 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000001cbe991def, 56 => ffffffffffffff80 (80000000 00000000)
+ rldcr. ffffffffffffffff, 0000001cbe991def, 63 => ffffffffffffffff (80000000 00000000)
+ rldcr. ffffffffffffffff, ffffffffffffffff, 0 => 8000000000000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, ffffffffffffffff, 7 => ff00000000000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, ffffffffffffffff, 14 => fffe000000000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, ffffffffffffffff, 21 => fffffc0000000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, ffffffffffffffff, 28 => fffffff800000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, ffffffffffffffff, 35 => fffffffff0000000 (80000000 00000000)
+ rldcr. ffffffffffffffff, ffffffffffffffff, 42 => ffffffffffe00000 (80000000 00000000)
+ rldcr. ffffffffffffffff, ffffffffffffffff, 49 => ffffffffffffc000 (80000000 00000000)
+ rldcr. ffffffffffffffff, ffffffffffffffff, 56 => ffffffffffffff80 (80000000 00000000)
+ rldcr. ffffffffffffffff, ffffffffffffffff, 63 => ffffffffffffffff (80000000 00000000)
+
+ rldic. 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 0, 7 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 0, 14 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 0, 21 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 0, 28 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 0, 35 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 0, 42 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 0, 49 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 0, 56 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 0, 63 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 7, 0 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 7, 7 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 7, 14 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 7, 21 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 7, 28 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 7, 35 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 7, 42 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 7, 49 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 7, 56 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 7, 63 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 14, 0 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 14, 7 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 14, 14 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 14, 21 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 14, 28 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 14, 35 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 14, 42 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 14, 49 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 14, 56 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 14, 63 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 21, 0 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 21, 7 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 21, 14 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 21, 21 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 21, 28 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 21, 35 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 21, 42 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 21, 49 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 21, 56 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 21, 63 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 28, 0 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 28, 7 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 28, 14 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 28, 21 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 28, 28 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 28, 35 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 28, 42 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 28, 49 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 28, 56 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 28, 63 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 35, 0 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 35, 7 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 35, 14 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 35, 21 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 35, 28 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 35, 35 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 35, 42 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 35, 49 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 35, 56 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 35, 63 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 42, 0 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 42, 7 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 42, 14 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 42, 21 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 42, 28 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 42, 35 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 42, 42 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 42, 49 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 42, 56 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 42, 63 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 49, 0 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 49, 7 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 49, 14 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 49, 21 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 49, 28 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 49, 35 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 49, 42 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 49, 49 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 49, 56 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 49, 63 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 56, 0 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 56, 7 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 56, 14 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 56, 21 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 56, 28 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 56, 35 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 56, 42 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 56, 49 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 56, 56 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 56, 63 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 63, 0 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 63, 7 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 63, 14 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 63, 21 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 63, 28 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 63, 35 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 63, 42 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 63, 49 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 63, 56 => 0000000000000000 (20000000 00000000)
+ rldic. 0000000000000000, 63, 63 => 0000000000000000 (20000000 00000000)
+ rldic. 0000001cbe991def, 0, 0 => 0000001cbe991def (40000000 00000000)
+ rldic. 0000001cbe991def, 0, 7 => 0000001cbe991def (40000000 00000000)
+ rldic. 0000001cbe991def, 0, 14 => 0000001cbe991def (40000000 00000000)
+ rldic. 0000001cbe991def, 0, 21 => 0000001cbe991def (40000000 00000000)
+ rldic. 0000001cbe991def, 0, 28 => 0000000cbe991def (40000000 00000000)
+ rldic. 0000001cbe991def, 0, 35 => 000000001e991def (40000000 00000000)
+ rldic. 0000001cbe991def, 0, 42 => 0000000000191def (40000000 00000000)
+ rldic. 0000001cbe991def, 0, 49 => 0000000000001def (40000000 00000000)
+ rldic. 0000001cbe991def, 0, 56 => 00000000000000ef (40000000 00000000)
+ rldic. 0000001cbe991def, 0, 63 => 0000000000000001 (40000000 00000000)
+ rldic. 0000001cbe991def, 7, 0 => 00000e5f4c8ef780 (40000000 00000000)
+ rldic. 0000001cbe991def, 7, 7 => 00000e5f4c8ef780 (40000000 00000000)
+ rldic. 0000001cbe991def, 7, 14 => 00000e5f4c8ef780 (40000000 00000000)
+ rldic. 0000001cbe991def, 7, 21 => 0000065f4c8ef780 (40000000 00000000)
+ rldic. 0000001cbe991def, 7, 28 => 0000000f4c8ef780 (40000000 00000000)
+ rldic. 0000001cbe991def, 7, 35 => 000000000c8ef780 (40000000 00000000)
+ rldic. 0000001cbe991def, 7, 42 => 00000000000ef780 (40000000 00000000)
+ rldic. 0000001cbe991def, 7, 49 => 0000000000007780 (40000000 00000000)
+ rldic. 0000001cbe991def, 7, 56 => 0000000000000080 (40000000 00000000)
+ rldic. 0000001cbe991def, 7, 63 => 00000e5f4c8ef780 (40000000 00000000)
+ rldic. 0000001cbe991def, 14, 0 => 00072fa6477bc000 (40000000 00000000)
+ rldic. 0000001cbe991def, 14, 7 => 00072fa6477bc000 (40000000 00000000)
+ rldic. 0000001cbe991def, 14, 14 => 00032fa6477bc000 (40000000 00000000)
+ rldic. 0000001cbe991def, 14, 21 => 000007a6477bc000 (40000000 00000000)
+ rldic. 0000001cbe991def, 14, 28 => 00000006477bc000 (40000000 00000000)
+ rldic. 0000001cbe991def, 14, 35 => 00000000077bc000 (40000000 00000000)
+ rldic. 0000001cbe991def, 14, 42 => 00000000003bc000 (40000000 00000000)
+ rldic. 0000001cbe991def, 14, 49 => 0000000000004000 (40000000 00000000)
+ rldic. 0000001cbe991def, 14, 56 => 00072fa6477bc000 (40000000 00000000)
+ rldic. 0000001cbe991def, 14, 63 => 00072fa6477bc000 (40000000 00000000)
+ rldic. 0000001cbe991def, 21, 0 => 0397d323bde00000 (40000000 00000000)
+ rldic. 0000001cbe991def, 21, 7 => 0197d323bde00000 (40000000 00000000)
+ rldic. 0000001cbe991def, 21, 14 => 0003d323bde00000 (40000000 00000000)
+ rldic. 0000001cbe991def, 21, 21 => 00000323bde00000 (40000000 00000000)
+ rldic. 0000001cbe991def, 21, 28 => 00000003bde00000 (40000000 00000000)
+ rldic. 0000001cbe991def, 21, 35 => 000000001de00000 (40000000 00000000)
+ rldic. 0000001cbe991def, 21, 42 => 0000000000200000 (40000000 00000000)
+ rldic. 0000001cbe991def, 21, 49 => 0397d323bde00000 (40000000 00000000)
+ rldic. 0000001cbe991def, 21, 56 => 0397d323bde00000 (40000000 00000000)
+ rldic. 0000001cbe991def, 21, 63 => 0397d323bde00000 (40000000 00000000)
+ rldic. 0000001cbe991def, 28, 0 => cbe991def0000000 (80000000 00000000)
+ rldic. 0000001cbe991def, 28, 7 => 01e991def0000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 28, 14 => 000191def0000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 28, 21 => 000001def0000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 28, 28 => 0000000ef0000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 28, 35 => 0000000010000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 28, 42 => cbe991def0000001 (80000000 00000000)
+ rldic. 0000001cbe991def, 28, 49 => cbe991def0000001 (80000000 00000000)
+ rldic. 0000001cbe991def, 28, 56 => cbe991def0000001 (80000000 00000000)
+ rldic. 0000001cbe991def, 28, 63 => cbe991def0000001 (80000000 00000000)
+ rldic. 0000001cbe991def, 35, 0 => f4c8ef7800000000 (80000000 00000000)
+ rldic. 0000001cbe991def, 35, 7 => 00c8ef7800000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 35, 14 => 0000ef7800000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 35, 21 => 0000077800000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 35, 28 => 0000000800000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 35, 35 => f4c8ef78000000e5 (80000000 00000000)
+ rldic. 0000001cbe991def, 35, 42 => f4c8ef78000000e5 (80000000 00000000)
+ rldic. 0000001cbe991def, 35, 49 => f4c8ef78000000e5 (80000000 00000000)
+ rldic. 0000001cbe991def, 35, 56 => f4c8ef78000000e5 (80000000 00000000)
+ rldic. 0000001cbe991def, 35, 63 => f4c8ef7800000001 (80000000 00000000)
+ rldic. 0000001cbe991def, 42, 0 => 6477bc0000000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 42, 7 => 0077bc0000000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 42, 14 => 0003bc0000000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 42, 21 => 0000040000000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 42, 28 => 6477bc00000072fa (40000000 00000000)
+ rldic. 0000001cbe991def, 42, 35 => 6477bc00000072fa (40000000 00000000)
+ rldic. 0000001cbe991def, 42, 42 => 6477bc00000072fa (40000000 00000000)
+ rldic. 0000001cbe991def, 42, 49 => 6477bc00000072fa (40000000 00000000)
+ rldic. 0000001cbe991def, 42, 56 => 6477bc00000000fa (40000000 00000000)
+ rldic. 0000001cbe991def, 42, 63 => 6477bc0000000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 49, 0 => 3bde000000000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 49, 7 => 01de000000000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 49, 14 => 0002000000000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 49, 21 => 3bde000000397d32 (40000000 00000000)
+ rldic. 0000001cbe991def, 49, 28 => 3bde000000397d32 (40000000 00000000)
+ rldic. 0000001cbe991def, 49, 35 => 3bde000000397d32 (40000000 00000000)
+ rldic. 0000001cbe991def, 49, 42 => 3bde000000397d32 (40000000 00000000)
+ rldic. 0000001cbe991def, 49, 49 => 3bde000000007d32 (40000000 00000000)
+ rldic. 0000001cbe991def, 49, 56 => 3bde000000000032 (40000000 00000000)
+ rldic. 0000001cbe991def, 49, 63 => 3bde000000000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 56, 0 => ef00000000000000 (80000000 00000000)
+ rldic. 0000001cbe991def, 56, 7 => 0100000000000000 (40000000 00000000)
+ rldic. 0000001cbe991def, 56, 14 => ef0000001cbe991d (80000000 00000000)
+ rldic. 0000001cbe991def, 56, 21 => ef0000001cbe991d (80000000 00000000)
+ rldic. 0000001cbe991def, 56, 28 => ef0000001cbe991d (80000000 00000000)
+ rldic. 0000001cbe991def, 56, 35 => ef0000001cbe991d (80000000 00000000)
+ rldic. 0000001cbe991def, 56, 42 => ef000000003e991d (80000000 00000000)
+ rldic. 0000001cbe991def, 56, 49 => ef0000000000191d (80000000 00000000)
+ rldic. 0000001cbe991def, 56, 56 => ef0000000000001d (80000000 00000000)
+ rldic. 0000001cbe991def, 56, 63 => ef00000000000001 (80000000 00000000)
+ rldic. 0000001cbe991def, 63, 0 => 8000000000000000 (80000000 00000000)
+ rldic. 0000001cbe991def, 63, 7 => 8000000e5f4c8ef7 (80000000 00000000)
+ rldic. 0000001cbe991def, 63, 14 => 8000000e5f4c8ef7 (80000000 00000000)
+ rldic. 0000001cbe991def, 63, 21 => 8000000e5f4c8ef7 (80000000 00000000)
+ rldic. 0000001cbe991def, 63, 28 => 8000000e5f4c8ef7 (80000000 00000000)
+ rldic. 0000001cbe991def, 63, 35 => 800000001f4c8ef7 (80000000 00000000)
+ rldic. 0000001cbe991def, 63, 42 => 80000000000c8ef7 (80000000 00000000)
+ rldic. 0000001cbe991def, 63, 49 => 8000000000000ef7 (80000000 00000000)
+ rldic. 0000001cbe991def, 63, 56 => 80000000000000f7 (80000000 00000000)
+ rldic. 0000001cbe991def, 63, 63 => 8000000000000001 (80000000 00000000)
+ rldic. ffffffffffffffff, 0, 0 => ffffffffffffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 0, 7 => 01ffffffffffffff (40000000 00000000)
+ rldic. ffffffffffffffff, 0, 14 => 0003ffffffffffff (40000000 00000000)
+ rldic. ffffffffffffffff, 0, 21 => 000007ffffffffff (40000000 00000000)
+ rldic. ffffffffffffffff, 0, 28 => 0000000fffffffff (40000000 00000000)
+ rldic. ffffffffffffffff, 0, 35 => 000000001fffffff (40000000 00000000)
+ rldic. ffffffffffffffff, 0, 42 => 00000000003fffff (40000000 00000000)
+ rldic. ffffffffffffffff, 0, 49 => 0000000000007fff (40000000 00000000)
+ rldic. ffffffffffffffff, 0, 56 => 00000000000000ff (40000000 00000000)
+ rldic. ffffffffffffffff, 0, 63 => 0000000000000001 (40000000 00000000)
+ rldic. ffffffffffffffff, 7, 0 => ffffffffffffff80 (80000000 00000000)
+ rldic. ffffffffffffffff, 7, 7 => 01ffffffffffff80 (40000000 00000000)
+ rldic. ffffffffffffffff, 7, 14 => 0003ffffffffff80 (40000000 00000000)
+ rldic. ffffffffffffffff, 7, 21 => 000007ffffffff80 (40000000 00000000)
+ rldic. ffffffffffffffff, 7, 28 => 0000000fffffff80 (40000000 00000000)
+ rldic. ffffffffffffffff, 7, 35 => 000000001fffff80 (40000000 00000000)
+ rldic. ffffffffffffffff, 7, 42 => 00000000003fff80 (40000000 00000000)
+ rldic. ffffffffffffffff, 7, 49 => 0000000000007f80 (40000000 00000000)
+ rldic. ffffffffffffffff, 7, 56 => 0000000000000080 (40000000 00000000)
+ rldic. ffffffffffffffff, 7, 63 => ffffffffffffff81 (80000000 00000000)
+ rldic. ffffffffffffffff, 14, 0 => ffffffffffffc000 (80000000 00000000)
+ rldic. ffffffffffffffff, 14, 7 => 01ffffffffffc000 (40000000 00000000)
+ rldic. ffffffffffffffff, 14, 14 => 0003ffffffffc000 (40000000 00000000)
+ rldic. ffffffffffffffff, 14, 21 => 000007ffffffc000 (40000000 00000000)
+ rldic. ffffffffffffffff, 14, 28 => 0000000fffffc000 (40000000 00000000)
+ rldic. ffffffffffffffff, 14, 35 => 000000001fffc000 (40000000 00000000)
+ rldic. ffffffffffffffff, 14, 42 => 00000000003fc000 (40000000 00000000)
+ rldic. ffffffffffffffff, 14, 49 => 0000000000004000 (40000000 00000000)
+ rldic. ffffffffffffffff, 14, 56 => ffffffffffffc0ff (80000000 00000000)
+ rldic. ffffffffffffffff, 14, 63 => ffffffffffffc001 (80000000 00000000)
+ rldic. ffffffffffffffff, 21, 0 => ffffffffffe00000 (80000000 00000000)
+ rldic. ffffffffffffffff, 21, 7 => 01ffffffffe00000 (40000000 00000000)
+ rldic. ffffffffffffffff, 21, 14 => 0003ffffffe00000 (40000000 00000000)
+ rldic. ffffffffffffffff, 21, 21 => 000007ffffe00000 (40000000 00000000)
+ rldic. ffffffffffffffff, 21, 28 => 0000000fffe00000 (40000000 00000000)
+ rldic. ffffffffffffffff, 21, 35 => 000000001fe00000 (40000000 00000000)
+ rldic. ffffffffffffffff, 21, 42 => 0000000000200000 (40000000 00000000)
+ rldic. ffffffffffffffff, 21, 49 => ffffffffffe07fff (80000000 00000000)
+ rldic. ffffffffffffffff, 21, 56 => ffffffffffe000ff (80000000 00000000)
+ rldic. ffffffffffffffff, 21, 63 => ffffffffffe00001 (80000000 00000000)
+ rldic. ffffffffffffffff, 28, 0 => fffffffff0000000 (80000000 00000000)
+ rldic. ffffffffffffffff, 28, 7 => 01fffffff0000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 28, 14 => 0003fffff0000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 28, 21 => 000007fff0000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 28, 28 => 0000000ff0000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 28, 35 => 0000000010000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 28, 42 => fffffffff03fffff (80000000 00000000)
+ rldic. ffffffffffffffff, 28, 49 => fffffffff0007fff (80000000 00000000)
+ rldic. ffffffffffffffff, 28, 56 => fffffffff00000ff (80000000 00000000)
+ rldic. ffffffffffffffff, 28, 63 => fffffffff0000001 (80000000 00000000)
+ rldic. ffffffffffffffff, 35, 0 => fffffff800000000 (80000000 00000000)
+ rldic. ffffffffffffffff, 35, 7 => 01fffff800000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 35, 14 => 0003fff800000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 35, 21 => 000007f800000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 35, 28 => 0000000800000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 35, 35 => fffffff81fffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 35, 42 => fffffff8003fffff (80000000 00000000)
+ rldic. ffffffffffffffff, 35, 49 => fffffff800007fff (80000000 00000000)
+ rldic. ffffffffffffffff, 35, 56 => fffffff8000000ff (80000000 00000000)
+ rldic. ffffffffffffffff, 35, 63 => fffffff800000001 (80000000 00000000)
+ rldic. ffffffffffffffff, 42, 0 => fffffc0000000000 (80000000 00000000)
+ rldic. ffffffffffffffff, 42, 7 => 01fffc0000000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 42, 14 => 0003fc0000000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 42, 21 => 0000040000000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 42, 28 => fffffc0fffffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 42, 35 => fffffc001fffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 42, 42 => fffffc00003fffff (80000000 00000000)
+ rldic. ffffffffffffffff, 42, 49 => fffffc0000007fff (80000000 00000000)
+ rldic. ffffffffffffffff, 42, 56 => fffffc00000000ff (80000000 00000000)
+ rldic. ffffffffffffffff, 42, 63 => fffffc0000000001 (80000000 00000000)
+ rldic. ffffffffffffffff, 49, 0 => fffe000000000000 (80000000 00000000)
+ rldic. ffffffffffffffff, 49, 7 => 01fe000000000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 49, 14 => 0002000000000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 49, 21 => fffe07ffffffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 49, 28 => fffe000fffffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 49, 35 => fffe00001fffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 49, 42 => fffe0000003fffff (80000000 00000000)
+ rldic. ffffffffffffffff, 49, 49 => fffe000000007fff (80000000 00000000)
+ rldic. ffffffffffffffff, 49, 56 => fffe0000000000ff (80000000 00000000)
+ rldic. ffffffffffffffff, 49, 63 => fffe000000000001 (80000000 00000000)
+ rldic. ffffffffffffffff, 56, 0 => ff00000000000000 (80000000 00000000)
+ rldic. ffffffffffffffff, 56, 7 => 0100000000000000 (40000000 00000000)
+ rldic. ffffffffffffffff, 56, 14 => ff03ffffffffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 56, 21 => ff0007ffffffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 56, 28 => ff00000fffffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 56, 35 => ff0000001fffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 56, 42 => ff000000003fffff (80000000 00000000)
+ rldic. ffffffffffffffff, 56, 49 => ff00000000007fff (80000000 00000000)
+ rldic. ffffffffffffffff, 56, 56 => ff000000000000ff (80000000 00000000)
+ rldic. ffffffffffffffff, 56, 63 => ff00000000000001 (80000000 00000000)
+ rldic. ffffffffffffffff, 63, 0 => 8000000000000000 (80000000 00000000)
+ rldic. ffffffffffffffff, 63, 7 => 81ffffffffffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 63, 14 => 8003ffffffffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 63, 21 => 800007ffffffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 63, 28 => 8000000fffffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 63, 35 => 800000001fffffff (80000000 00000000)
+ rldic. ffffffffffffffff, 63, 42 => 80000000003fffff (80000000 00000000)
+ rldic. ffffffffffffffff, 63, 49 => 8000000000007fff (80000000 00000000)
+ rldic. ffffffffffffffff, 63, 56 => 80000000000000ff (80000000 00000000)
+ rldic. ffffffffffffffff, 63, 63 => 8000000000000001 (80000000 00000000)
+
+ rldicl. 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 0, 7 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 0, 14 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 0, 21 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 0, 28 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 0, 35 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 0, 42 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 0, 49 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 0, 56 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 0, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 7, 0 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 7, 7 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 7, 14 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 7, 21 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 7, 28 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 7, 35 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 7, 42 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 7, 49 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 7, 56 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 7, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 14, 0 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 14, 7 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 14, 14 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 14, 21 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 14, 28 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 14, 35 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 14, 42 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 14, 49 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 14, 56 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 14, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 21, 0 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 21, 7 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 21, 14 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 21, 21 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 21, 28 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 21, 35 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 21, 42 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 21, 49 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 21, 56 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 21, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 28, 0 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 28, 7 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 28, 14 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 28, 21 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 28, 28 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 28, 35 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 28, 42 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 28, 49 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 28, 56 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 28, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 35, 0 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 35, 7 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 35, 14 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 35, 21 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 35, 28 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 35, 35 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 35, 42 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 35, 49 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 35, 56 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 35, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 42, 0 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 42, 7 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 42, 14 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 42, 21 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 42, 28 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 42, 35 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 42, 42 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 42, 49 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 42, 56 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 42, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 49, 0 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 49, 7 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 49, 14 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 49, 21 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 49, 28 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 49, 35 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 49, 42 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 49, 49 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 49, 56 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 49, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 56, 0 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 56, 7 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 56, 14 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 56, 21 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 56, 28 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 56, 35 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 56, 42 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 56, 49 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 56, 56 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 56, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 63, 0 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 63, 7 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 63, 14 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 63, 21 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 63, 28 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 63, 35 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 63, 42 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 63, 49 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 63, 56 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000000000000000, 63, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000001cbe991def, 0, 0 => 0000001cbe991def (40000000 00000000)
+ rldicl. 0000001cbe991def, 0, 7 => 0000001cbe991def (40000000 00000000)
+ rldicl. 0000001cbe991def, 0, 14 => 0000001cbe991def (40000000 00000000)
+ rldicl. 0000001cbe991def, 0, 21 => 0000001cbe991def (40000000 00000000)
+ rldicl. 0000001cbe991def, 0, 28 => 0000000cbe991def (40000000 00000000)
+ rldicl. 0000001cbe991def, 0, 35 => 000000001e991def (40000000 00000000)
+ rldicl. 0000001cbe991def, 0, 42 => 0000000000191def (40000000 00000000)
+ rldicl. 0000001cbe991def, 0, 49 => 0000000000001def (40000000 00000000)
+ rldicl. 0000001cbe991def, 0, 56 => 00000000000000ef (40000000 00000000)
+ rldicl. 0000001cbe991def, 0, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. 0000001cbe991def, 7, 0 => 00000e5f4c8ef780 (40000000 00000000)
+ rldicl. 0000001cbe991def, 7, 7 => 00000e5f4c8ef780 (40000000 00000000)
+ rldicl. 0000001cbe991def, 7, 14 => 00000e5f4c8ef780 (40000000 00000000)
+ rldicl. 0000001cbe991def, 7, 21 => 0000065f4c8ef780 (40000000 00000000)
+ rldicl. 0000001cbe991def, 7, 28 => 0000000f4c8ef780 (40000000 00000000)
+ rldicl. 0000001cbe991def, 7, 35 => 000000000c8ef780 (40000000 00000000)
+ rldicl. 0000001cbe991def, 7, 42 => 00000000000ef780 (40000000 00000000)
+ rldicl. 0000001cbe991def, 7, 49 => 0000000000007780 (40000000 00000000)
+ rldicl. 0000001cbe991def, 7, 56 => 0000000000000080 (40000000 00000000)
+ rldicl. 0000001cbe991def, 7, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000001cbe991def, 14, 0 => 00072fa6477bc000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 14, 7 => 00072fa6477bc000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 14, 14 => 00032fa6477bc000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 14, 21 => 000007a6477bc000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 14, 28 => 00000006477bc000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 14, 35 => 00000000077bc000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 14, 42 => 00000000003bc000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 14, 49 => 0000000000004000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 14, 56 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000001cbe991def, 14, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000001cbe991def, 21, 0 => 0397d323bde00000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 21, 7 => 0197d323bde00000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 21, 14 => 0003d323bde00000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 21, 21 => 00000323bde00000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 21, 28 => 00000003bde00000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 21, 35 => 000000001de00000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 21, 42 => 0000000000200000 (40000000 00000000)
+ rldicl. 0000001cbe991def, 21, 49 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000001cbe991def, 21, 56 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000001cbe991def, 21, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000001cbe991def, 28, 0 => cbe991def0000001 (80000000 00000000)
+ rldicl. 0000001cbe991def, 28, 7 => 01e991def0000001 (40000000 00000000)
+ rldicl. 0000001cbe991def, 28, 14 => 000191def0000001 (40000000 00000000)
+ rldicl. 0000001cbe991def, 28, 21 => 000001def0000001 (40000000 00000000)
+ rldicl. 0000001cbe991def, 28, 28 => 0000000ef0000001 (40000000 00000000)
+ rldicl. 0000001cbe991def, 28, 35 => 0000000010000001 (40000000 00000000)
+ rldicl. 0000001cbe991def, 28, 42 => 0000000000000001 (40000000 00000000)
+ rldicl. 0000001cbe991def, 28, 49 => 0000000000000001 (40000000 00000000)
+ rldicl. 0000001cbe991def, 28, 56 => 0000000000000001 (40000000 00000000)
+ rldicl. 0000001cbe991def, 28, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. 0000001cbe991def, 35, 0 => f4c8ef78000000e5 (80000000 00000000)
+ rldicl. 0000001cbe991def, 35, 7 => 00c8ef78000000e5 (40000000 00000000)
+ rldicl. 0000001cbe991def, 35, 14 => 0000ef78000000e5 (40000000 00000000)
+ rldicl. 0000001cbe991def, 35, 21 => 00000778000000e5 (40000000 00000000)
+ rldicl. 0000001cbe991def, 35, 28 => 00000008000000e5 (40000000 00000000)
+ rldicl. 0000001cbe991def, 35, 35 => 00000000000000e5 (40000000 00000000)
+ rldicl. 0000001cbe991def, 35, 42 => 00000000000000e5 (40000000 00000000)
+ rldicl. 0000001cbe991def, 35, 49 => 00000000000000e5 (40000000 00000000)
+ rldicl. 0000001cbe991def, 35, 56 => 00000000000000e5 (40000000 00000000)
+ rldicl. 0000001cbe991def, 35, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. 0000001cbe991def, 42, 0 => 6477bc00000072fa (40000000 00000000)
+ rldicl. 0000001cbe991def, 42, 7 => 0077bc00000072fa (40000000 00000000)
+ rldicl. 0000001cbe991def, 42, 14 => 0003bc00000072fa (40000000 00000000)
+ rldicl. 0000001cbe991def, 42, 21 => 00000400000072fa (40000000 00000000)
+ rldicl. 0000001cbe991def, 42, 28 => 00000000000072fa (40000000 00000000)
+ rldicl. 0000001cbe991def, 42, 35 => 00000000000072fa (40000000 00000000)
+ rldicl. 0000001cbe991def, 42, 42 => 00000000000072fa (40000000 00000000)
+ rldicl. 0000001cbe991def, 42, 49 => 00000000000072fa (40000000 00000000)
+ rldicl. 0000001cbe991def, 42, 56 => 00000000000000fa (40000000 00000000)
+ rldicl. 0000001cbe991def, 42, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000001cbe991def, 49, 0 => 3bde000000397d32 (40000000 00000000)
+ rldicl. 0000001cbe991def, 49, 7 => 01de000000397d32 (40000000 00000000)
+ rldicl. 0000001cbe991def, 49, 14 => 0002000000397d32 (40000000 00000000)
+ rldicl. 0000001cbe991def, 49, 21 => 0000000000397d32 (40000000 00000000)
+ rldicl. 0000001cbe991def, 49, 28 => 0000000000397d32 (40000000 00000000)
+ rldicl. 0000001cbe991def, 49, 35 => 0000000000397d32 (40000000 00000000)
+ rldicl. 0000001cbe991def, 49, 42 => 0000000000397d32 (40000000 00000000)
+ rldicl. 0000001cbe991def, 49, 49 => 0000000000007d32 (40000000 00000000)
+ rldicl. 0000001cbe991def, 49, 56 => 0000000000000032 (40000000 00000000)
+ rldicl. 0000001cbe991def, 49, 63 => 0000000000000000 (20000000 00000000)
+ rldicl. 0000001cbe991def, 56, 0 => ef0000001cbe991d (80000000 00000000)
+ rldicl. 0000001cbe991def, 56, 7 => 010000001cbe991d (40000000 00000000)
+ rldicl. 0000001cbe991def, 56, 14 => 000000001cbe991d (40000000 00000000)
+ rldicl. 0000001cbe991def, 56, 21 => 000000001cbe991d (40000000 00000000)
+ rldicl. 0000001cbe991def, 56, 28 => 000000001cbe991d (40000000 00000000)
+ rldicl. 0000001cbe991def, 56, 35 => 000000001cbe991d (40000000 00000000)
+ rldicl. 0000001cbe991def, 56, 42 => 00000000003e991d (40000000 00000000)
+ rldicl. 0000001cbe991def, 56, 49 => 000000000000191d (40000000 00000000)
+ rldicl. 0000001cbe991def, 56, 56 => 000000000000001d (40000000 00000000)
+ rldicl. 0000001cbe991def, 56, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. 0000001cbe991def, 63, 0 => 8000000e5f4c8ef7 (80000000 00000000)
+ rldicl. 0000001cbe991def, 63, 7 => 0000000e5f4c8ef7 (40000000 00000000)
+ rldicl. 0000001cbe991def, 63, 14 => 0000000e5f4c8ef7 (40000000 00000000)
+ rldicl. 0000001cbe991def, 63, 21 => 0000000e5f4c8ef7 (40000000 00000000)
+ rldicl. 0000001cbe991def, 63, 28 => 0000000e5f4c8ef7 (40000000 00000000)
+ rldicl. 0000001cbe991def, 63, 35 => 000000001f4c8ef7 (40000000 00000000)
+ rldicl. 0000001cbe991def, 63, 42 => 00000000000c8ef7 (40000000 00000000)
+ rldicl. 0000001cbe991def, 63, 49 => 0000000000000ef7 (40000000 00000000)
+ rldicl. 0000001cbe991def, 63, 56 => 00000000000000f7 (40000000 00000000)
+ rldicl. 0000001cbe991def, 63, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. ffffffffffffffff, 0, 0 => ffffffffffffffff (80000000 00000000)
+ rldicl. ffffffffffffffff, 0, 7 => 01ffffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 0, 14 => 0003ffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 0, 21 => 000007ffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 0, 28 => 0000000fffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 0, 35 => 000000001fffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 0, 42 => 00000000003fffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 0, 49 => 0000000000007fff (40000000 00000000)
+ rldicl. ffffffffffffffff, 0, 56 => 00000000000000ff (40000000 00000000)
+ rldicl. ffffffffffffffff, 0, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. ffffffffffffffff, 7, 0 => ffffffffffffffff (80000000 00000000)
+ rldicl. ffffffffffffffff, 7, 7 => 01ffffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 7, 14 => 0003ffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 7, 21 => 000007ffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 7, 28 => 0000000fffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 7, 35 => 000000001fffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 7, 42 => 00000000003fffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 7, 49 => 0000000000007fff (40000000 00000000)
+ rldicl. ffffffffffffffff, 7, 56 => 00000000000000ff (40000000 00000000)
+ rldicl. ffffffffffffffff, 7, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. ffffffffffffffff, 14, 0 => ffffffffffffffff (80000000 00000000)
+ rldicl. ffffffffffffffff, 14, 7 => 01ffffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 14, 14 => 0003ffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 14, 21 => 000007ffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 14, 28 => 0000000fffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 14, 35 => 000000001fffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 14, 42 => 00000000003fffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 14, 49 => 0000000000007fff (40000000 00000000)
+ rldicl. ffffffffffffffff, 14, 56 => 00000000000000ff (40000000 00000000)
+ rldicl. ffffffffffffffff, 14, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. ffffffffffffffff, 21, 0 => ffffffffffffffff (80000000 00000000)
+ rldicl. ffffffffffffffff, 21, 7 => 01ffffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 21, 14 => 0003ffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 21, 21 => 000007ffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 21, 28 => 0000000fffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 21, 35 => 000000001fffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 21, 42 => 00000000003fffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 21, 49 => 0000000000007fff (40000000 00000000)
+ rldicl. ffffffffffffffff, 21, 56 => 00000000000000ff (40000000 00000000)
+ rldicl. ffffffffffffffff, 21, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. ffffffffffffffff, 28, 0 => ffffffffffffffff (80000000 00000000)
+ rldicl. ffffffffffffffff, 28, 7 => 01ffffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 28, 14 => 0003ffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 28, 21 => 000007ffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 28, 28 => 0000000fffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 28, 35 => 000000001fffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 28, 42 => 00000000003fffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 28, 49 => 0000000000007fff (40000000 00000000)
+ rldicl. ffffffffffffffff, 28, 56 => 00000000000000ff (40000000 00000000)
+ rldicl. ffffffffffffffff, 28, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. ffffffffffffffff, 35, 0 => ffffffffffffffff (80000000 00000000)
+ rldicl. ffffffffffffffff, 35, 7 => 01ffffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 35, 14 => 0003ffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 35, 21 => 000007ffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 35, 28 => 0000000fffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 35, 35 => 000000001fffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 35, 42 => 00000000003fffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 35, 49 => 0000000000007fff (40000000 00000000)
+ rldicl. ffffffffffffffff, 35, 56 => 00000000000000ff (40000000 00000000)
+ rldicl. ffffffffffffffff, 35, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. ffffffffffffffff, 42, 0 => ffffffffffffffff (80000000 00000000)
+ rldicl. ffffffffffffffff, 42, 7 => 01ffffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 42, 14 => 0003ffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 42, 21 => 000007ffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 42, 28 => 0000000fffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 42, 35 => 000000001fffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 42, 42 => 00000000003fffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 42, 49 => 0000000000007fff (40000000 00000000)
+ rldicl. ffffffffffffffff, 42, 56 => 00000000000000ff (40000000 00000000)
+ rldicl. ffffffffffffffff, 42, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. ffffffffffffffff, 49, 0 => ffffffffffffffff (80000000 00000000)
+ rldicl. ffffffffffffffff, 49, 7 => 01ffffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 49, 14 => 0003ffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 49, 21 => 000007ffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 49, 28 => 0000000fffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 49, 35 => 000000001fffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 49, 42 => 00000000003fffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 49, 49 => 0000000000007fff (40000000 00000000)
+ rldicl. ffffffffffffffff, 49, 56 => 00000000000000ff (40000000 00000000)
+ rldicl. ffffffffffffffff, 49, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. ffffffffffffffff, 56, 0 => ffffffffffffffff (80000000 00000000)
+ rldicl. ffffffffffffffff, 56, 7 => 01ffffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 56, 14 => 0003ffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 56, 21 => 000007ffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 56, 28 => 0000000fffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 56, 35 => 000000001fffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 56, 42 => 00000000003fffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 56, 49 => 0000000000007fff (40000000 00000000)
+ rldicl. ffffffffffffffff, 56, 56 => 00000000000000ff (40000000 00000000)
+ rldicl. ffffffffffffffff, 56, 63 => 0000000000000001 (40000000 00000000)
+ rldicl. ffffffffffffffff, 63, 0 => ffffffffffffffff (80000000 00000000)
+ rldicl. ffffffffffffffff, 63, 7 => 01ffffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 63, 14 => 0003ffffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 63, 21 => 000007ffffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 63, 28 => 0000000fffffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 63, 35 => 000000001fffffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 63, 42 => 00000000003fffff (40000000 00000000)
+ rldicl. ffffffffffffffff, 63, 49 => 0000000000007fff (40000000 00000000)
+ rldicl. ffffffffffffffff, 63, 56 => 00000000000000ff (40000000 00000000)
+ rldicl. ffffffffffffffff, 63, 63 => 0000000000000001 (40000000 00000000)
+
+ rldicr. 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 0, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 0, 14 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 0, 21 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 0, 28 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 0, 35 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 0, 42 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 0, 49 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 0, 56 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 0, 63 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 7, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 7, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 7, 14 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 7, 21 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 7, 28 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 7, 35 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 7, 42 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 7, 49 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 7, 56 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 7, 63 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 14, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 14, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 14, 14 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 14, 21 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 14, 28 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 14, 35 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 14, 42 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 14, 49 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 14, 56 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 14, 63 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 21, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 21, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 21, 14 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 21, 21 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 21, 28 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 21, 35 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 21, 42 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 21, 49 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 21, 56 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 21, 63 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 28, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 28, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 28, 14 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 28, 21 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 28, 28 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 28, 35 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 28, 42 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 28, 49 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 28, 56 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 28, 63 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 35, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 35, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 35, 14 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 35, 21 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 35, 28 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 35, 35 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 35, 42 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 35, 49 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 35, 56 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 35, 63 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 42, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 42, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 42, 14 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 42, 21 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 42, 28 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 42, 35 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 42, 42 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 42, 49 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 42, 56 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 42, 63 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 49, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 49, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 49, 14 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 49, 21 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 49, 28 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 49, 35 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 49, 42 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 49, 49 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 49, 56 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 49, 63 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 56, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 56, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 56, 14 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 56, 21 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 56, 28 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 56, 35 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 56, 42 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 56, 49 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 56, 56 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 56, 63 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 63, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 63, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 63, 14 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 63, 21 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 63, 28 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 63, 35 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 63, 42 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 63, 49 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 63, 56 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000000000000000, 63, 63 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 0, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 0, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 0, 14 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 0, 21 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 0, 28 => 0000001800000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 0, 35 => 0000001cb0000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 0, 42 => 0000001cbe800000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 0, 49 => 0000001cbe990000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 0, 56 => 0000001cbe991d80 (40000000 00000000)
+ rldicr. 0000001cbe991def, 0, 63 => 0000001cbe991def (40000000 00000000)
+ rldicr. 0000001cbe991def, 7, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 7, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 7, 14 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 7, 21 => 00000c0000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 7, 28 => 00000e5800000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 7, 35 => 00000e5f40000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 7, 42 => 00000e5f4c800000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 7, 49 => 00000e5f4c8ec000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 7, 56 => 00000e5f4c8ef780 (40000000 00000000)
+ rldicr. 0000001cbe991def, 7, 63 => 00000e5f4c8ef780 (40000000 00000000)
+ rldicr. 0000001cbe991def, 14, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 14, 7 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 14, 14 => 0006000000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 14, 21 => 00072c0000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 14, 28 => 00072fa000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 14, 35 => 00072fa640000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 14, 42 => 00072fa647600000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 14, 49 => 00072fa6477bc000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 14, 56 => 00072fa6477bc000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 14, 63 => 00072fa6477bc000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 21, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 21, 7 => 0300000000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 21, 14 => 0396000000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 21, 21 => 0397d00000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 21, 28 => 0397d32000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 21, 35 => 0397d323b0000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 21, 42 => 0397d323bde00000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 21, 49 => 0397d323bde00000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 21, 56 => 0397d323bde00000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 21, 63 => 0397d323bde00000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 28, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 28, 7 => cb00000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 28, 14 => cbe8000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 28, 21 => cbe9900000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 28, 28 => cbe991d800000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 28, 35 => cbe991def0000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 28, 42 => cbe991def0000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 28, 49 => cbe991def0000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 28, 56 => cbe991def0000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 28, 63 => cbe991def0000001 (80000000 00000000)
+ rldicr. 0000001cbe991def, 35, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 35, 7 => f400000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 35, 14 => f4c8000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 35, 21 => f4c8ec0000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 35, 28 => f4c8ef7800000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 35, 35 => f4c8ef7800000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 35, 42 => f4c8ef7800000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 35, 49 => f4c8ef7800000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 35, 56 => f4c8ef7800000080 (80000000 00000000)
+ rldicr. 0000001cbe991def, 35, 63 => f4c8ef78000000e5 (80000000 00000000)
+ rldicr. 0000001cbe991def, 42, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 42, 7 => 6400000000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 42, 14 => 6476000000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 42, 21 => 6477bc0000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 42, 28 => 6477bc0000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 42, 35 => 6477bc0000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 42, 42 => 6477bc0000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 42, 49 => 6477bc0000004000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 42, 56 => 6477bc0000007280 (40000000 00000000)
+ rldicr. 0000001cbe991def, 42, 63 => 6477bc00000072fa (40000000 00000000)
+ rldicr. 0000001cbe991def, 49, 0 => 0000000000000000 (20000000 00000000)
+ rldicr. 0000001cbe991def, 49, 7 => 3b00000000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 49, 14 => 3bde000000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 49, 21 => 3bde000000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 49, 28 => 3bde000000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 49, 35 => 3bde000000000000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 49, 42 => 3bde000000200000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 49, 49 => 3bde000000394000 (40000000 00000000)
+ rldicr. 0000001cbe991def, 49, 56 => 3bde000000397d00 (40000000 00000000)
+ rldicr. 0000001cbe991def, 49, 63 => 3bde000000397d32 (40000000 00000000)
+ rldicr. 0000001cbe991def, 56, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 56, 7 => ef00000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 56, 14 => ef00000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 56, 21 => ef00000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 56, 28 => ef00000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 56, 35 => ef00000010000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 56, 42 => ef0000001ca00000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 56, 49 => ef0000001cbe8000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 56, 56 => ef0000001cbe9900 (80000000 00000000)
+ rldicr. 0000001cbe991def, 56, 63 => ef0000001cbe991d (80000000 00000000)
+ rldicr. 0000001cbe991def, 63, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 63, 7 => 8000000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 63, 14 => 8000000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 63, 21 => 8000000000000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 63, 28 => 8000000800000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 63, 35 => 8000000e50000000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 63, 42 => 8000000e5f400000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 63, 49 => 8000000e5f4c8000 (80000000 00000000)
+ rldicr. 0000001cbe991def, 63, 56 => 8000000e5f4c8e80 (80000000 00000000)
+ rldicr. 0000001cbe991def, 63, 63 => 8000000e5f4c8ef7 (80000000 00000000)
+ rldicr. ffffffffffffffff, 0, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 0, 7 => ff00000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 0, 14 => fffe000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 0, 21 => fffffc0000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 0, 28 => fffffff800000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 0, 35 => fffffffff0000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 0, 42 => ffffffffffe00000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 0, 49 => ffffffffffffc000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 0, 56 => ffffffffffffff80 (80000000 00000000)
+ rldicr. ffffffffffffffff, 0, 63 => ffffffffffffffff (80000000 00000000)
+ rldicr. ffffffffffffffff, 7, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 7, 7 => ff00000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 7, 14 => fffe000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 7, 21 => fffffc0000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 7, 28 => fffffff800000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 7, 35 => fffffffff0000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 7, 42 => ffffffffffe00000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 7, 49 => ffffffffffffc000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 7, 56 => ffffffffffffff80 (80000000 00000000)
+ rldicr. ffffffffffffffff, 7, 63 => ffffffffffffffff (80000000 00000000)
+ rldicr. ffffffffffffffff, 14, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 14, 7 => ff00000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 14, 14 => fffe000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 14, 21 => fffffc0000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 14, 28 => fffffff800000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 14, 35 => fffffffff0000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 14, 42 => ffffffffffe00000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 14, 49 => ffffffffffffc000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 14, 56 => ffffffffffffff80 (80000000 00000000)
+ rldicr. ffffffffffffffff, 14, 63 => ffffffffffffffff (80000000 00000000)
+ rldicr. ffffffffffffffff, 21, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 21, 7 => ff00000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 21, 14 => fffe000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 21, 21 => fffffc0000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 21, 28 => fffffff800000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 21, 35 => fffffffff0000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 21, 42 => ffffffffffe00000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 21, 49 => ffffffffffffc000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 21, 56 => ffffffffffffff80 (80000000 00000000)
+ rldicr. ffffffffffffffff, 21, 63 => ffffffffffffffff (80000000 00000000)
+ rldicr. ffffffffffffffff, 28, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 28, 7 => ff00000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 28, 14 => fffe000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 28, 21 => fffffc0000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 28, 28 => fffffff800000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 28, 35 => fffffffff0000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 28, 42 => ffffffffffe00000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 28, 49 => ffffffffffffc000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 28, 56 => ffffffffffffff80 (80000000 00000000)
+ rldicr. ffffffffffffffff, 28, 63 => ffffffffffffffff (80000000 00000000)
+ rldicr. ffffffffffffffff, 35, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 35, 7 => ff00000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 35, 14 => fffe000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 35, 21 => fffffc0000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 35, 28 => fffffff800000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 35, 35 => fffffffff0000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 35, 42 => ffffffffffe00000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 35, 49 => ffffffffffffc000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 35, 56 => ffffffffffffff80 (80000000 00000000)
+ rldicr. ffffffffffffffff, 35, 63 => ffffffffffffffff (80000000 00000000)
+ rldicr. ffffffffffffffff, 42, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 42, 7 => ff00000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 42, 14 => fffe000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 42, 21 => fffffc0000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 42, 28 => fffffff800000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 42, 35 => fffffffff0000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 42, 42 => ffffffffffe00000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 42, 49 => ffffffffffffc000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 42, 56 => ffffffffffffff80 (80000000 00000000)
+ rldicr. ffffffffffffffff, 42, 63 => ffffffffffffffff (80000000 00000000)
+ rldicr. ffffffffffffffff, 49, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 49, 7 => ff00000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 49, 14 => fffe000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 49, 21 => fffffc0000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 49, 28 => fffffff800000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 49, 35 => fffffffff0000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 49, 42 => ffffffffffe00000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 49, 49 => ffffffffffffc000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 49, 56 => ffffffffffffff80 (80000000 00000000)
+ rldicr. ffffffffffffffff, 49, 63 => ffffffffffffffff (80000000 00000000)
+ rldicr. ffffffffffffffff, 56, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 56, 7 => ff00000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 56, 14 => fffe000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 56, 21 => fffffc0000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 56, 28 => fffffff800000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 56, 35 => fffffffff0000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 56, 42 => ffffffffffe00000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 56, 49 => ffffffffffffc000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 56, 56 => ffffffffffffff80 (80000000 00000000)
+ rldicr. ffffffffffffffff, 56, 63 => ffffffffffffffff (80000000 00000000)
+ rldicr. ffffffffffffffff, 63, 0 => 8000000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 63, 7 => ff00000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 63, 14 => fffe000000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 63, 21 => fffffc0000000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 63, 28 => fffffff800000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 63, 35 => fffffffff0000000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 63, 42 => ffffffffffe00000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 63, 49 => ffffffffffffc000 (80000000 00000000)
+ rldicr. ffffffffffffffff, 63, 56 => ffffffffffffff80 (80000000 00000000)
+ rldicr. ffffffffffffffff, 63, 63 => ffffffffffffffff (80000000 00000000)
+
+ rldimi. 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 0, 7 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 0, 14 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 0, 21 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 0, 28 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 0, 35 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 0, 42 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 0, 49 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 0, 56 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 0, 63 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 7, 0 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 7, 7 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 7, 14 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 7, 21 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 7, 28 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 7, 35 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 7, 42 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 7, 49 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 7, 56 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 7, 63 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 14, 0 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 14, 7 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 14, 14 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 14, 21 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 14, 28 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 14, 35 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 14, 42 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 14, 49 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 14, 56 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 14, 63 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 21, 0 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 21, 7 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 21, 14 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 21, 21 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 21, 28 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 21, 35 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 21, 42 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 21, 49 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 21, 56 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 21, 63 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 28, 0 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 28, 7 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 28, 14 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 28, 21 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 28, 28 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 28, 35 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 28, 42 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 28, 49 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 28, 56 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 28, 63 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 35, 0 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 35, 7 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 35, 14 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 35, 21 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 35, 28 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 35, 35 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 35, 42 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 35, 49 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 35, 56 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 35, 63 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 42, 0 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 42, 7 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 42, 14 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 42, 21 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 42, 28 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 42, 35 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 42, 42 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 42, 49 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 42, 56 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 42, 63 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 49, 0 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 49, 7 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 49, 14 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 49, 21 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 49, 28 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 49, 35 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 49, 42 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 49, 49 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 49, 56 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 49, 63 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 56, 0 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 56, 7 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 56, 14 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 56, 21 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 56, 28 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 56, 35 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 56, 42 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 56, 49 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 56, 56 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 56, 63 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 63, 0 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 63, 7 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 63, 14 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 63, 21 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 63, 28 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 63, 35 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 63, 42 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 63, 49 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 63, 56 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000000000000000, 63, 63 => 0000000000000000 (20000000 00000000)
+ rldimi. 0000001cbe991def, 0, 0 => 0000001cbe991def (40000000 00000000)
+ rldimi. 0000001cbe991def, 0, 7 => 0000001cbe991def (40000000 00000000)
+ rldimi. 0000001cbe991def, 0, 14 => 0000001cbe991def (40000000 00000000)
+ rldimi. 0000001cbe991def, 0, 21 => 0000001cbe991def (40000000 00000000)
+ rldimi. 0000001cbe991def, 0, 28 => 0000001cbe991def (40000000 00000000)
+ rldimi. 0000001cbe991def, 0, 35 => 0000001cbe991def (40000000 00000000)
+ rldimi. 0000001cbe991def, 0, 42 => 0000001cbe991def (40000000 00000000)
+ rldimi. 0000001cbe991def, 0, 49 => 0000001cbe991def (40000000 00000000)
+ rldimi. 0000001cbe991def, 0, 56 => 0000001cbe991def (40000000 00000000)
+ rldimi. 0000001cbe991def, 0, 63 => 0000001cbe991def (40000000 00000000)
+ rldimi. 0000001cbe991def, 7, 0 => 00000e5f4c8ef7ef (40000000 00000000)
+ rldimi. 0000001cbe991def, 7, 7 => 00000e5f4c8ef7ef (40000000 00000000)
+ rldimi. 0000001cbe991def, 7, 14 => 00000e5f4c8ef7ef (40000000 00000000)
+ rldimi. 0000001cbe991def, 7, 21 => 00000e5f4c8ef7ef (40000000 00000000)
+ rldimi. 0000001cbe991def, 7, 28 => 00000e5f4c8ef7ef (40000000 00000000)
+ rldimi. 0000001cbe991def, 7, 35 => 00000e5f4c8ef7ef (40000000 00000000)
+ rldimi. 0000001cbe991def, 7, 42 => 00000e5f4c8ef7ef (40000000 00000000)
+ rldimi. 0000001cbe991def, 7, 49 => 00000e5f4c8ef7ef (40000000 00000000)
+ rldimi. 0000001cbe991def, 7, 56 => 00000e5f4c8ef7ef (40000000 00000000)
+ rldimi. 0000001cbe991def, 7, 63 => 00000e5f4c8ef7ee (40000000 00000000)
+ rldimi. 0000001cbe991def, 14, 0 => 00072fa6477bf7ee (40000000 00000000)
+ rldimi. 0000001cbe991def, 14, 7 => 00072fa6477bf7ee (40000000 00000000)
+ rldimi. 0000001cbe991def, 14, 14 => 00072fa6477bf7ee (40000000 00000000)
+ rldimi. 0000001cbe991def, 14, 21 => 00072fa6477bf7ee (40000000 00000000)
+ rldimi. 0000001cbe991def, 14, 28 => 00072fa6477bf7ee (40000000 00000000)
+ rldimi. 0000001cbe991def, 14, 35 => 00072fa6477bf7ee (40000000 00000000)
+ rldimi. 0000001cbe991def, 14, 42 => 00072fa6477bf7ee (40000000 00000000)
+ rldimi. 0000001cbe991def, 14, 49 => 00072fa6477bf7ee (40000000 00000000)
+ rldimi. 0000001cbe991def, 14, 56 => 00072fa6477bf700 (40000000 00000000)
+ rldimi. 0000001cbe991def, 14, 63 => 00072fa6477bf700 (40000000 00000000)
+ rldimi. 0000001cbe991def, 21, 0 => 0397d323bdfbf700 (40000000 00000000)
+ rldimi. 0000001cbe991def, 21, 7 => 0397d323bdfbf700 (40000000 00000000)
+ rldimi. 0000001cbe991def, 21, 14 => 0397d323bdfbf700 (40000000 00000000)
+ rldimi. 0000001cbe991def, 21, 21 => 0397d323bdfbf700 (40000000 00000000)
+ rldimi. 0000001cbe991def, 21, 28 => 0397d323bdfbf700 (40000000 00000000)
+ rldimi. 0000001cbe991def, 21, 35 => 0397d323bdfbf700 (40000000 00000000)
+ rldimi. 0000001cbe991def, 21, 42 => 0397d323bdfbf700 (40000000 00000000)
+ rldimi. 0000001cbe991def, 21, 49 => 0397d323bdfb8000 (40000000 00000000)
+ rldimi. 0000001cbe991def, 21, 56 => 0397d323bdfb8000 (40000000 00000000)
+ rldimi. 0000001cbe991def, 21, 63 => 0397d323bdfb8000 (40000000 00000000)
+ rldimi. 0000001cbe991def, 28, 0 => cbe991defdfb8000 (80000000 00000000)
+ rldimi. 0000001cbe991def, 28, 7 => cbe991defdfb8000 (80000000 00000000)
+ rldimi. 0000001cbe991def, 28, 14 => cbe991defdfb8000 (80000000 00000000)
+ rldimi. 0000001cbe991def, 28, 21 => cbe991defdfb8000 (80000000 00000000)
+ rldimi. 0000001cbe991def, 28, 28 => cbe991defdfb8000 (80000000 00000000)
+ rldimi. 0000001cbe991def, 28, 35 => cbe991defdfb8000 (80000000 00000000)
+ rldimi. 0000001cbe991def, 28, 42 => cbe991defdc00001 (80000000 00000000)
+ rldimi. 0000001cbe991def, 28, 49 => cbe991defdc00001 (80000000 00000000)
+ rldimi. 0000001cbe991def, 28, 56 => cbe991defdc00001 (80000000 00000000)
+ rldimi. 0000001cbe991def, 28, 63 => cbe991defdc00001 (80000000 00000000)
+ rldimi. 0000001cbe991def, 35, 0 => f4c8ef7efdc00001 (80000000 00000000)
+ rldimi. 0000001cbe991def, 35, 7 => f4c8ef7efdc00001 (80000000 00000000)
+ rldimi. 0000001cbe991def, 35, 14 => f4c8ef7efdc00001 (80000000 00000000)
+ rldimi. 0000001cbe991def, 35, 21 => f4c8ef7efdc00001 (80000000 00000000)
+ rldimi. 0000001cbe991def, 35, 28 => f4c8ef7efdc00001 (80000000 00000000)
+ rldimi. 0000001cbe991def, 35, 35 => f4c8ef7ee00000e5 (80000000 00000000)
+ rldimi. 0000001cbe991def, 35, 42 => f4c8ef7ee00000e5 (80000000 00000000)
+ rldimi. 0000001cbe991def, 35, 49 => f4c8ef7ee00000e5 (80000000 00000000)
+ rldimi. 0000001cbe991def, 35, 56 => f4c8ef7ee00000e5 (80000000 00000000)
+ rldimi. 0000001cbe991def, 35, 63 => f4c8ef7ee00000e5 (80000000 00000000)
+ rldimi. 0000001cbe991def, 42, 0 => 6477bf7ee00000e5 (40000000 00000000)
+ rldimi. 0000001cbe991def, 42, 7 => 6477bf7ee00000e5 (40000000 00000000)
+ rldimi. 0000001cbe991def, 42, 14 => 6477bf7ee00000e5 (40000000 00000000)
+ rldimi. 0000001cbe991def, 42, 21 => 6477bf7ee00000e5 (40000000 00000000)
+ rldimi. 0000001cbe991def, 42, 28 => 6477bf70000072fa (40000000 00000000)
+ rldimi. 0000001cbe991def, 42, 35 => 6477bf70000072fa (40000000 00000000)
+ rldimi. 0000001cbe991def, 42, 42 => 6477bf70000072fa (40000000 00000000)
+ rldimi. 0000001cbe991def, 42, 49 => 6477bf70000072fa (40000000 00000000)
+ rldimi. 0000001cbe991def, 42, 56 => 6477bf70000072fa (40000000 00000000)
+ rldimi. 0000001cbe991def, 42, 63 => 6477bf70000072fa (40000000 00000000)
+ rldimi. 0000001cbe991def, 49, 0 => 3bdfbf70000072fa (40000000 00000000)
+ rldimi. 0000001cbe991def, 49, 7 => 3bdfbf70000072fa (40000000 00000000)
+ rldimi. 0000001cbe991def, 49, 14 => 3bdfbf70000072fa (40000000 00000000)
+ rldimi. 0000001cbe991def, 49, 21 => 3bdfb80000397d32 (40000000 00000000)
+ rldimi. 0000001cbe991def, 49, 28 => 3bdfb80000397d32 (40000000 00000000)
+ rldimi. 0000001cbe991def, 49, 35 => 3bdfb80000397d32 (40000000 00000000)
+ rldimi. 0000001cbe991def, 49, 42 => 3bdfb80000397d32 (40000000 00000000)
+ rldimi. 0000001cbe991def, 49, 49 => 3bdfb80000397d32 (40000000 00000000)
+ rldimi. 0000001cbe991def, 49, 56 => 3bdfb80000397d32 (40000000 00000000)
+ rldimi. 0000001cbe991def, 49, 63 => 3bdfb80000397d32 (40000000 00000000)
+ rldimi. 0000001cbe991def, 56, 0 => efdfb80000397d32 (80000000 00000000)
+ rldimi. 0000001cbe991def, 56, 7 => efdfb80000397d32 (80000000 00000000)
+ rldimi. 0000001cbe991def, 56, 14 => efdc00001cbe991d (80000000 00000000)
+ rldimi. 0000001cbe991def, 56, 21 => efdc00001cbe991d (80000000 00000000)
+ rldimi. 0000001cbe991def, 56, 28 => efdc00001cbe991d (80000000 00000000)
+ rldimi. 0000001cbe991def, 56, 35 => efdc00001cbe991d (80000000 00000000)
+ rldimi. 0000001cbe991def, 56, 42 => efdc00001cbe991d (80000000 00000000)
+ rldimi. 0000001cbe991def, 56, 49 => efdc00001cbe991d (80000000 00000000)
+ rldimi. 0000001cbe991def, 56, 56 => efdc00001cbe991d (80000000 00000000)
+ rldimi. 0000001cbe991def, 56, 63 => efdc00001cbe991d (80000000 00000000)
+ rldimi. 0000001cbe991def, 63, 0 => efdc00001cbe991d (80000000 00000000)
+ rldimi. 0000001cbe991def, 63, 7 => ee00000e5f4c8ef7 (80000000 00000000)
+ rldimi. 0000001cbe991def, 63, 14 => ee00000e5f4c8ef7 (80000000 00000000)
+ rldimi. 0000001cbe991def, 63, 21 => ee00000e5f4c8ef7 (80000000 00000000)
+ rldimi. 0000001cbe991def, 63, 28 => ee00000e5f4c8ef7 (80000000 00000000)
+ rldimi. 0000001cbe991def, 63, 35 => ee00000e5f4c8ef7 (80000000 00000000)
+ rldimi. 0000001cbe991def, 63, 42 => ee00000e5f4c8ef7 (80000000 00000000)
+ rldimi. 0000001cbe991def, 63, 49 => ee00000e5f4c8ef7 (80000000 00000000)
+ rldimi. 0000001cbe991def, 63, 56 => ee00000e5f4c8ef7 (80000000 00000000)
+ rldimi. 0000001cbe991def, 63, 63 => ee00000e5f4c8ef7 (80000000 00000000)
+ rldimi. ffffffffffffffff, 0, 0 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 0, 7 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 0, 14 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 0, 21 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 0, 28 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 0, 35 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 0, 42 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 0, 49 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 0, 56 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 0, 63 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 7, 0 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 7, 7 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 7, 14 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 7, 21 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 7, 28 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 7, 35 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 7, 42 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 7, 49 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 7, 56 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 7, 63 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 14, 0 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 14, 7 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 14, 14 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 14, 21 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 14, 28 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 14, 35 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 14, 42 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 14, 49 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 14, 56 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 14, 63 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 21, 0 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 21, 7 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 21, 14 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 21, 21 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 21, 28 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 21, 35 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 21, 42 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 21, 49 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 21, 56 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 21, 63 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 28, 0 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 28, 7 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 28, 14 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 28, 21 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 28, 28 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 28, 35 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 28, 42 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 28, 49 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 28, 56 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 28, 63 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 35, 0 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 35, 7 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 35, 14 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 35, 21 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 35, 28 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 35, 35 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 35, 42 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 35, 49 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 35, 56 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 35, 63 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 42, 0 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 42, 7 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 42, 14 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 42, 21 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 42, 28 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 42, 35 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 42, 42 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 42, 49 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 42, 56 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 42, 63 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 49, 0 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 49, 7 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 49, 14 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 49, 21 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 49, 28 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 49, 35 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 49, 42 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 49, 49 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 49, 56 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 49, 63 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 56, 0 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 56, 7 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 56, 14 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 56, 21 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 56, 28 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 56, 35 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 56, 42 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 56, 49 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 56, 56 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 56, 63 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 63, 0 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 63, 7 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 63, 14 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 63, 21 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 63, 28 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 63, 35 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 63, 42 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 63, 49 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 63, 56 => ffffffffffffffff (80000000 00000000)
+ rldimi. ffffffffffffffff, 63, 63 => ffffffffffffffff (80000000 00000000)
+
+ sradi. 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
+ sradi. 0000000000000000, 7 => 0000000000000000 (20000000 00000000)
+ sradi. 0000000000000000, 14 => 0000000000000000 (20000000 00000000)
+ sradi. 0000000000000000, 21 => 0000000000000000 (20000000 00000000)
+ sradi. 0000000000000000, 28 => 0000000000000000 (20000000 00000000)
+ sradi. 0000000000000000, 35 => 0000000000000000 (20000000 00000000)
+ sradi. 0000000000000000, 42 => 0000000000000000 (20000000 00000000)
+ sradi. 0000000000000000, 49 => 0000000000000000 (20000000 00000000)
+ sradi. 0000000000000000, 56 => 0000000000000000 (20000000 00000000)
+ sradi. 0000000000000000, 63 => 0000000000000000 (20000000 00000000)
+ sradi. 0000001cbe991def, 0 => 0000001cbe991def (40000000 00000000)
+ sradi. 0000001cbe991def, 7 => 00000000397d323b (40000000 00000000)
+ sradi. 0000001cbe991def, 14 => 000000000072fa64 (40000000 00000000)
+ sradi. 0000001cbe991def, 21 => 000000000000e5f4 (40000000 00000000)
+ sradi. 0000001cbe991def, 28 => 00000000000001cb (40000000 00000000)
+ sradi. 0000001cbe991def, 35 => 0000000000000003 (40000000 00000000)
+ sradi. 0000001cbe991def, 42 => 0000000000000000 (20000000 00000000)
+ sradi. 0000001cbe991def, 49 => 0000000000000000 (20000000 00000000)
+ sradi. 0000001cbe991def, 56 => 0000000000000000 (20000000 00000000)
+ sradi. 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000)
+ sradi. ffffffffffffffff, 0 => ffffffffffffffff (80000000 00000000)
+ sradi. ffffffffffffffff, 7 => ffffffffffffffff (80000000 20000000)
+ sradi. ffffffffffffffff, 14 => ffffffffffffffff (80000000 20000000)
+ sradi. ffffffffffffffff, 21 => ffffffffffffffff (80000000 20000000)
+ sradi. ffffffffffffffff, 28 => ffffffffffffffff (80000000 20000000)
+ sradi. ffffffffffffffff, 35 => ffffffffffffffff (80000000 20000000)
+ sradi. ffffffffffffffff, 42 => ffffffffffffffff (80000000 20000000)
+ sradi. ffffffffffffffff, 49 => ffffffffffffffff (80000000 20000000)
+ sradi. ffffffffffffffff, 56 => ffffffffffffffff (80000000 20000000)
+ sradi. ffffffffffffffff, 63 => ffffffffffffffff (80000000 20000000)
+
+PPC integer load insns
+ with one register + one 16 bits immediate args with flags update:
+ lbz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lbz 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
+ lbz 15, (ffffffffffffffff) => 0000000000000000, 0 (00000000 00000000)
+ lbz 1, (ffffffffffffffff) => 00000000000000ff, 0 (00000000 00000000)
+ lbz -7, (0000001cbe991def) => 000000000000001d, 0 (00000000 00000000)
+ lbz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+
+ lbzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lbzu 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000)
+ lbzu 15, (ffffffffffffffff) => 0000000000000000, 15 (00000000 00000000)
+ lbzu 1, (ffffffffffffffff) => 00000000000000ff, 1 (00000000 00000000)
+ lbzu -7, (0000001cbe991def) => 000000000000001d, -7 (00000000 00000000)
+ lbzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
+
+ lha 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lha 7, (0000001cbe991def) => ffffffffffffef00, 0 (00000000 00000000)
+ lha 15, (ffffffffffffffff) => ffffffffffffff00, 0 (00000000 00000000)
+ lha 1, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
+ lha -7, (0000001cbe991def) => ffffffffffff991d, 0 (00000000 00000000)
+ lha -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+
+ lhau 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lhau 7, (0000001cbe991def) => ffffffffffffef00, 7 (00000000 00000000)
+ lhau 15, (ffffffffffffffff) => ffffffffffffff00, 15 (00000000 00000000)
+ lhau 1, (ffffffffffffffff) => ffffffffffffffff, 1 (00000000 00000000)
+ lhau -7, (0000001cbe991def) => ffffffffffff991d, -7 (00000000 00000000)
+ lhau -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
+
+ lhz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lhz 7, (0000001cbe991def) => 000000000000ef00, 0 (00000000 00000000)
+ lhz 15, (ffffffffffffffff) => 000000000000ff00, 0 (00000000 00000000)
+ lhz 1, (ffffffffffffffff) => 000000000000ffff, 0 (00000000 00000000)
+ lhz -7, (0000001cbe991def) => 000000000000991d, 0 (00000000 00000000)
+ lhz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+
+ lhzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lhzu 7, (0000001cbe991def) => 000000000000ef00, 7 (00000000 00000000)
+ lhzu 15, (ffffffffffffffff) => 000000000000ff00, 15 (00000000 00000000)
+ lhzu 1, (ffffffffffffffff) => 000000000000ffff, 1 (00000000 00000000)
+ lhzu -7, (0000001cbe991def) => 000000000000991d, -7 (00000000 00000000)
+ lhzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
+
+ lwz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lwz 7, (0000001cbe991def) => 00000000991def00, 0 (00000000 00000000)
+ lwz 15, (ffffffffffffffff) => 00000000ffffff00, 0 (00000000 00000000)
+ lwz 1, (ffffffffffffffff) => 00000000ffffffff, 0 (00000000 00000000)
+ lwz -7, (0000001cbe991def) => 000000001cbe991d, 0 (00000000 00000000)
+ lwz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+
+ lwzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lwzu 7, (0000001cbe991def) => 00000000991def00, 7 (00000000 00000000)
+ lwzu 15, (ffffffffffffffff) => 00000000ffffff00, 15 (00000000 00000000)
+ lwzu 1, (ffffffffffffffff) => 00000000ffffffff, 1 (00000000 00000000)
+ lwzu -7, (0000001cbe991def) => 000000001cbe991d, -7 (00000000 00000000)
+ lwzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
+
+ ld 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ ld 7, (0000001cbe991def) => be991def00000000, 0 (00000000 00000000)
+ ld 15, (ffffffffffffffff) => ffffffff0000001c, 0 (00000000 00000000)
+ ld 1, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
+ ld -7, (0000001cbe991def) => 0000001cbe991def, -8 (00000000 00000000)
+ ld -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
+
+ ldu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ ldu 7, (0000001cbe991def) => be991def00000000, 4 (00000000 00000000)
+ ldu 15, (ffffffffffffffff) => ffffffff0000001c, 12 (00000000 00000000)
+ ldu 1, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
+ ldu -7, (0000001cbe991def) => 0000001cbe991def, -8 (00000000 00000000)
+ ldu -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
+
+ lwa 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lwa 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
+ lwa 15, (ffffffffffffffff) => 000000000000001c, 0 (00000000 00000000)
+ lwa 1, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
+ lwa -7, (0000001cbe991def) => 0000001cbe991def, -8 (00000000 00000000)
+ lwa -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
+
+PPC integer load insns with two register args:
+ lbzx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lbzx 8, (0000001cbe991def) => 00000000000000ef, 0 (00000000 00000000)
+ lbzx 16, (ffffffffffffffff) => 00000000000000ff, 0 (00000000 00000000)
+
+ lbzux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lbzux 8, (0000001cbe991def) => 00000000000000ef, 8 (00000000 00000000)
+ lbzux 16, (ffffffffffffffff) => 00000000000000ff, 16 (00000000 00000000)
+
+ lhax 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lhax 8, (0000001cbe991def) => 0000000000001def, 0 (00000000 00000000)
+ lhax 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
+
+ lhaux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lhaux 8, (0000001cbe991def) => 0000000000001def, 8 (00000000 00000000)
+ lhaux 16, (ffffffffffffffff) => ffffffffffffffff, 16 (00000000 00000000)
+
+ lhzx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lhzx 8, (0000001cbe991def) => 0000000000001def, 0 (00000000 00000000)
+ lhzx 16, (ffffffffffffffff) => 000000000000ffff, 0 (00000000 00000000)
+
+ lhzux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lhzux 8, (0000001cbe991def) => 0000000000001def, 8 (00000000 00000000)
+ lhzux 16, (ffffffffffffffff) => 000000000000ffff, 16 (00000000 00000000)
+
+ lwzx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lwzx 8, (0000001cbe991def) => 00000000be991def, 0 (00000000 00000000)
+ lwzx 16, (ffffffffffffffff) => 00000000ffffffff, 0 (00000000 00000000)
+
+ lwzux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lwzux 8, (0000001cbe991def) => 00000000be991def, 8 (00000000 00000000)
+ lwzux 16, (ffffffffffffffff) => 00000000ffffffff, 16 (00000000 00000000)
+
+ ldx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ ldx 8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000)
+ ldx 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
+
+ ldux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ ldux 8, (0000001cbe991def) => 0000001cbe991def, 8 (00000000 00000000)
+ ldux 16, (ffffffffffffffff) => ffffffffffffffff, 16 (00000000 00000000)
+
+ lwax 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lwax 8, (0000001cbe991def) => ffffffffbe991def, 0 (00000000 00000000)
+ lwax 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
+
+ lwaux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+ lwaux 8, (0000001cbe991def) => ffffffffbe991def, 8 (00000000 00000000)
+ lwaux 16, (ffffffffffffffff) => ffffffffffffffff, 16 (00000000 00000000)
+
+PPC integer store insns
+ with one register + one 16 bits immediate args with flags update:
+ stb 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ stb 0000001cbe991def, 8 => 00000000000000ef, 0 (00000000 00000000)
+ stb ffffffffffffffff, 16 => 00000000000000ff, 0 (00000000 00000000)
+ stb 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
+ stb 0000001cbe991def, -8 => 00000000000000ef, 0 (00000000 00000000)
+ stb ffffffffffffffff, 0 => 00000000000000ff, 0 (00000000 00000000)
+
+ stbu 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ stbu 0000001cbe991def, 8 => 00000000000000ef, 8 (00000000 00000000)
+ stbu ffffffffffffffff, 16 => 00000000000000ff, 16 (00000000 00000000)
+ stbu 0000000000000000, -16 => 0000000000000000, -16 (00000000 00000000)
+ stbu 0000001cbe991def, -8 => 00000000000000ef, -8 (00000000 00000000)
+ stbu ffffffffffffffff, 0 => 00000000000000ff, 0 (00000000 00000000)
+
+ sth 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ sth 0000001cbe991def, 8 => 0000000000001def, 0 (00000000 00000000)
+ sth ffffffffffffffff, 16 => 000000000000ffff, 0 (00000000 00000000)
+ sth 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
+ sth 0000001cbe991def, -8 => 0000000000001def, 0 (00000000 00000000)
+ sth ffffffffffffffff, 0 => 000000000000ffff, 0 (00000000 00000000)
+
+ sthu 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ sthu 0000001cbe991def, 8 => 0000000000001def, 8 (00000000 00000000)
+ sthu ffffffffffffffff, 16 => 000000000000ffff, 16 (00000000 00000000)
+ sthu 0000000000000000, -16 => 0000000000000000, -16 (00000000 00000000)
+ sthu 0000001cbe991def, -8 => 0000000000001def, -8 (00000000 00000000)
+ sthu ffffffffffffffff, 0 => 000000000000ffff, 0 (00000000 00000000)
+
+ stw 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ stw 0000001cbe991def, 8 => 00000000be991def, 0 (00000000 00000000)
+ stw ffffffffffffffff, 16 => 00000000ffffffff, 0 (00000000 00000000)
+ stw 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
+ stw 0000001cbe991def, -8 => 00000000be991def, 0 (00000000 00000000)
+ stw ffffffffffffffff, 0 => 00000000ffffffff, 0 (00000000 00000000)
+
+ stwu 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ stwu 0000001cbe991def, 8 => 00000000be991def, 8 (00000000 00000000)
+ stwu ffffffffffffffff, 16 => 00000000ffffffff, 16 (00000000 00000000)
+ stwu 0000000000000000, -16 => 0000000000000000, -16 (00000000 00000000)
+ stwu 0000001cbe991def, -8 => 00000000be991def, -8 (00000000 00000000)
+ stwu ffffffffffffffff, 0 => 00000000ffffffff, 0 (00000000 00000000)
+
+ std 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ std 0000001cbe991def, 8 => 0000001cbe991def, 0 (00000000 00000000)
+ std ffffffffffffffff, 16 => ffffffffffffffff, 0 (00000000 00000000)
+ std 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
+ std 0000001cbe991def, -8 => 0000001cbe991def, 0 (00000000 00000000)
+ std ffffffffffffffff, 0 => ffffffffffffffff, 0 (00000000 00000000)
+
+ stdu 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ stdu 0000001cbe991def, 8 => 0000001cbe991def, 0 (00000000 00000000)
+ stdu ffffffffffffffff, 16 => ffffffffffffffff, 0 (00000000 00000000)
+ stdu 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
+ stdu 0000001cbe991def, -8 => 0000001cbe991def, 0 (00000000 00000000)
+ stdu ffffffffffffffff, 0 => ffffffffffffffff, 0 (00000000 00000000)
+
+PPC integer store insns with three register args:
+ stbx 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ stbx 0000001cbe991def, 8 => 00000000000000ef, 0 (00000000 00000000)
+ stbx ffffffffffffffff, 16 => 00000000000000ff, 0 (00000000 00000000)
+
+ stbux 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ stbux 0000001cbe991def, 8 => 00000000000000ef, 8 (00000000 00000000)
+ stbux ffffffffffffffff, 16 => 00000000000000ff, 16 (00000000 00000000)
+
+ sthx 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ sthx 0000001cbe991def, 8 => 0000000000001def, 0 (00000000 00000000)
+ sthx ffffffffffffffff, 16 => 000000000000ffff, 0 (00000000 00000000)
+
+ sthux 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ sthux 0000001cbe991def, 8 => 0000000000001def, 8 (00000000 00000000)
+ sthux ffffffffffffffff, 16 => 000000000000ffff, 16 (00000000 00000000)
+
+ stwx 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ stwx 0000001cbe991def, 8 => 00000000be991def, 0 (00000000 00000000)
+ stwx ffffffffffffffff, 16 => 00000000ffffffff, 0 (00000000 00000000)
+
+ stwux 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ stwux 0000001cbe991def, 8 => 00000000be991def, 8 (00000000 00000000)
+ stwux ffffffffffffffff, 16 => 00000000ffffffff, 16 (00000000 00000000)
+
+ stdx 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ stdx 0000001cbe991def, 8 => 0000001cbe991def, 0 (00000000 00000000)
+ stdx ffffffffffffffff, 16 => ffffffffffffffff, 0 (00000000 00000000)
+
+ stdux 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
+ stdux 0000001cbe991def, 8 => 0000001cbe991def, 8 (00000000 00000000)
+ stdux ffffffffffffffff, 16 => ffffffffffffffff, 16 (00000000 00000000)
+
+All done. Tested 131 different instructions
diff --git a/none/tests/ppc64/jm-int_other.vgtest b/none/tests/ppc64/jm-int_other.vgtest
new file mode 100644
index 0000000..42255ae
--- /dev/null
+++ b/none/tests/ppc64/jm-int_other.vgtest
@@ -0,0 +1 @@
+prog: jm-insns -l -L -c
diff --git a/none/tests/ppc64/ppc64_helpers.h b/none/tests/ppc64/ppc64_helpers.h
index 8dca231..f149d8a 100644
--- a/none/tests/ppc64/ppc64_helpers.h
+++ b/none/tests/ppc64/ppc64_helpers.h
@@ -1,6 +1,6 @@
/*
* ppc64_helpers.h
- * Copyright (c) 2016 Will Schmidt <will_schmidt@vnet.ibm.com>
+ * Copyright (C) 2016-2017 Will Schmidt <will_schmidt@vnet.ibm.com>
*
* This file contains helper functions for the ISA 3.0 test suite.
*/
@@ -123,7 +123,7 @@
" 7-RSVD", " 8-RSVD", " 9-RSVD", "10-RSVD", "11-RSVD", "12-RSVD", "13-RSVD",
"14-RSVD", "15-RSVD", "16-RSVD", "17-RSVD", "18-RSVD", "19-RSVD", "20-RSVD",
"21-RSVD", "22-RSVD", "23-RSVD", "24-RSVD", "25-RSVD", "26-RSVD", "27-RSVD",
-"28-RSVD", "29-RSVD", "30-RSVD", "31-RSVD",
+"28-RSVD", "29-DRN0", "30-DRN1", "31-DRN2",
/* 32 */ "FX", "FEX", "VX",
/* 35 */ "OX", "UX", "ZX", "XX", "VXSNAN",
/* 40 */ "VXISI (inf-inf)", "VXIDI (inf/inf)", "VXZDZ (0/0)",
@@ -217,15 +217,32 @@
}
/* dissect the fpscr bits that are valid under valgrind.
- * Valgrind itself only tracks the C and FPCC fields from the
- * FPSCR.
+ * Valgrind tracks the C (FPSCR[47]), FPCC (FPSCR[48:51)
+ * DRN (FPSCR[29:31]) and RN (FPSCR[62:63]).
*/
static void dissect_fpscr_valgrind(unsigned long local_fpscr) {
int i;
- int mybit;
+ long mybit;
+ /* Print DRN fields */
+ for (i = 29; i < 32; i++) {
+ mybit = 1LL << (63 - i);
+ if (mybit & local_fpscr) {
+ printf(" %s",fpscr_strings[i]);
+ }
+ }
+
+ /* Print C and FPCC fields */
for (i = 47; i < 52; i++) {
- mybit = 1 << (63 - i);
+ mybit = 1LL << (63 - i);
+ if (mybit & local_fpscr) {
+ printf(" %s",fpscr_strings[i]);
+ }
+ }
+
+ /* Print RN field */
+ for (i = 62; i < 64; i++) {
+ mybit = 1LL << (63 - i);
if (mybit & local_fpscr) {
printf(" %s",fpscr_strings[i]);
}
@@ -240,11 +257,11 @@
/* Due to the additional involved logic, the rounding mode (RN) bits 61-62
* are handled within dissect_fpscr_rounding_mode(). */
int i;
- int mybit;
+ long mybit;
for (i = 0; i < 61; i++) {
/* also note that the bit numbering is backwards. */
- mybit = 1 << (63 - i);
+ mybit = 1LL << (63 - i);
if (mybit & local_fpscr) {
printf(" %s", fpscr_strings[i]);
}
@@ -358,6 +375,45 @@
if (verbose > 1) printf("%s ", (local_fpscr&FPCC_FE_BIT) ? "SP" : "");
}
+/* dissect_xer helpers*/
+static char * xer_strings[] = {
+" 0-RSVD", " 1-RSVD", " 2-RSVD", " 3-RSVD", " 4-RSVD", " 5-RSVD", " 6-RSVD",
+" 7-RSVD", " 8-RSVD", " 9-RSVD", "10-RSVD", "11-RSVD", "12-RSVD", "13-RSVD",
+"14-RSVD", "15-RSVD", "16-RSVD", "17-RSVD", "18-RSVD", "19-RSVD",
+"20-RSVD", "21-RSVD", "22-RSVD", "23-RSVD", "24-RSVD", "25-RSVD",
+"26-RSVD", "27-RSVD", "28-RSVD", "29-RSVD", "30-RSVD", "31-RSVD",
+/* 32 */ "SO", "OV", "CA",
+/* 35 */ "35-RSVD", "36-RSVD", "37-RSVD", "38-RSVD", "39-RSVD",
+/* 40 */ "40-RSVD", "41-RSVD", "42-RSVD", "43-RSVD",
+/* 44 */ "OV32", "CA32",
+/* 46 */ "46-RSVD", "47-RSVD", "48-RSVD", "49-RSVD", "50-RSVD", "51-RSVD",
+ "52-RSVD", "53-RSVD", "54-RSVD", "55-RSVD", "56-RSVD",
+/* 57:63 # bytes transferred by a Load/Store String Indexed instruction. */
+ "LSI/SSI-0", "LSI/SSI-1", "LSI/SSI-2", "LSI/SSI-3",
+ "LSI/SSI-4", "LSI/SSI-5", "LSI/SSI-6",
+};
+
+/* Dissect the XER register contents.
+ */
+static void dissect_xer_raw(unsigned long local_xer) {
+ int i;
+ long mybit;
+
+ for (i = 0; i <= 63; i++) {
+ mybit = 1ULL << (63 - i); /* compensate for reversed bit numbering. */
+ if (mybit & local_xer)
+ printf(" %s", xer_strings[i]);
+ }
+}
+
+/* */
+static void dissect_xer(unsigned long local_xer) {
+ if (verbose > 1)
+ printf(" [[ xer:%lx ]]", local_xer);
+ dissect_xer_raw(local_xer);
+}
+
+
/* DFP helpers for bcd-to-dpd, dpd-to-bcd, misc.
* pulled from vex/.../host_generic_simd64.c
*/
diff --git a/none/tests/ppc64/test_isa_2_06_part2-div.stderr.exp b/none/tests/ppc64/test_isa_2_06_part2-div.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/none/tests/ppc64/test_isa_2_06_part2-div.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/none/tests/ppc64/test_isa_2_06_part2-div.stdout.exp b/none/tests/ppc64/test_isa_2_06_part2-div.stdout.exp
new file mode 100644
index 0000000..cff4157
--- /dev/null
+++ b/none/tests/ppc64/test_isa_2_06_part2-div.stdout.exp
@@ -0,0 +1,89 @@
+Test div extensions
+#0: divde: 0x0000000000000004 / 0xfffffffffffffffc = 0x0000000000000000; CR=0; XER=0
+#1: divde: 0x0000000000000004 / 0xfffffffffffffffd = 0x0000000000000000; CR=0; XER=0
+#2: divde: 0x0000000000000004 / 0x0000000000000004 = 0x0000000000000000; CR=0; XER=0
+#3: divde: 0x0000000000000004 / 0xfffffffffffffffb = 0x0000000000000000; CR=0; XER=0
+#4: divde: 0x0000000000000003 / 0x0000000000000008 = 0x6000000000000000; CR=0; XER=0
+#5: divde: 0x8000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=0; XER=0
+#6: divde: 0x000000000000050c / 0xffffffffffffffff = 0x0000000000000000; CR=0; XER=0
+#7: divde: 0x000000000000050c / 0xfffffffffffff000 = 0xaf40000000000000; CR=0; XER=0
+#8: divde: 0x000000001234fedc / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=0; XER=0
+#9: divde: 0xabcd87651234fedc / 0x00000000a123b893 = 0x0000000000000000; CR=0; XER=0
+#10: divde: 0x000123456789abdc / 0x0000000000000000 = 0x0000000000000000; CR=0; XER=0
+#11: divde: 0x0000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=0; XER=0
+#12: divde: 0x0000000000000077 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=0; XER=0
+
+#0: divde.: 0x0000000000000004 / 0xfffffffffffffffc = 0x0000000000000000; CR=2; XER=0
+#1: divde.: 0x0000000000000004 / 0xfffffffffffffffd = 0x0000000000000000; CR=2; XER=0
+#2: divde.: 0x0000000000000004 / 0x0000000000000004 = 0x0000000000000000; CR=2; XER=0
+#3: divde.: 0x0000000000000004 / 0xfffffffffffffffb = 0x0000000000000000; CR=2; XER=0
+#4: divde.: 0x0000000000000003 / 0x0000000000000008 = 0x6000000000000000; CR=4; XER=0
+#5: divde.: 0x8000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=2; XER=0
+#6: divde.: 0x000000000000050c / 0xffffffffffffffff = 0x0000000000000000; CR=2; XER=0
+#7: divde.: 0x000000000000050c / 0xfffffffffffff000 = 0xaf40000000000000; CR=8; XER=0
+#8: divde.: 0x000000001234fedc / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=4; XER=0
+#9: divde.: 0xabcd87651234fedc / 0x00000000a123b893 = 0x0000000000000000; CR=2; XER=0
+#10: divde.: 0x000123456789abdc / 0x0000000000000000 = 0x0000000000000000; CR=2; XER=0
+#11: divde.: 0x0000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=2; XER=0
+#12: divde.: 0x0000000000000077 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=4; XER=0
+
+
+#0: divdeo: 0x0000000000000004 / 0xfffffffffffffffc = 0x0000000000000000; CR=0; XER=c0000000
+#1: divdeo: 0x0000000000000004 / 0xfffffffffffffffd = 0x0000000000000000; CR=0; XER=c0000000
+#2: divdeo: 0x0000000000000004 / 0x0000000000000004 = 0x0000000000000000; CR=0; XER=c0000000
+#3: divdeo: 0x0000000000000004 / 0xfffffffffffffffb = 0x0000000000000000; CR=0; XER=c0000000
+#4: divdeo: 0x0000000000000003 / 0x0000000000000008 = 0x6000000000000000; CR=0; XER=0
+#5: divdeo: 0x8000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=0; XER=c0000000
+#6: divdeo: 0x000000000000050c / 0xffffffffffffffff = 0x0000000000000000; CR=0; XER=c0000000
+#7: divdeo: 0x000000000000050c / 0xfffffffffffff000 = 0xaf40000000000000; CR=0; XER=0
+#8: divdeo: 0x000000001234fedc / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=0; XER=0
+#9: divdeo: 0xabcd87651234fedc / 0x00000000a123b893 = 0x0000000000000000; CR=0; XER=c0000000
+#10: divdeo: 0x000123456789abdc / 0x0000000000000000 = 0x0000000000000000; CR=0; XER=c0000000
+#11: divdeo: 0x0000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=0; XER=0
+#12: divdeo: 0x0000000000000077 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=0; XER=0
+
+#0: divdeo.: 0x0000000000000004 / 0xfffffffffffffffc = 0x0000000000000000; CR=3; XER=c0000000
+#1: divdeo.: 0x0000000000000004 / 0xfffffffffffffffd = 0x0000000000000000; CR=3; XER=c0000000
+#2: divdeo.: 0x0000000000000004 / 0x0000000000000004 = 0x0000000000000000; CR=3; XER=c0000000
+#3: divdeo.: 0x0000000000000004 / 0xfffffffffffffffb = 0x0000000000000000; CR=3; XER=c0000000
+#4: divdeo.: 0x0000000000000003 / 0x0000000000000008 = 0x6000000000000000; CR=4; XER=0
+#5: divdeo.: 0x8000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=3; XER=c0000000
+#6: divdeo.: 0x000000000000050c / 0xffffffffffffffff = 0x0000000000000000; CR=3; XER=c0000000
+#7: divdeo.: 0x000000000000050c / 0xfffffffffffff000 = 0xaf40000000000000; CR=8; XER=0
+#8: divdeo.: 0x000000001234fedc / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=4; XER=0
+#9: divdeo.: 0xabcd87651234fedc / 0x00000000a123b893 = 0x0000000000000000; CR=3; XER=c0000000
+#10: divdeo.: 0x000123456789abdc / 0x0000000000000000 = 0x0000000000000000; CR=3; XER=c0000000
+#11: divdeo.: 0x0000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=2; XER=0
+#12: divdeo.: 0x0000000000000077 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=4; XER=0
+
+
+#0: divweu: 0x00000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divweu: 0x00000002 / 0x00000000 = 0x00000000; CR=0; XER=0
+#2: divweu: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=0; XER=0
+#3: divweu: 0xfabc1234 / 0x00000005 = 0x00000000; CR=0; XER=0
+#4: divweu: 0x0000004d / 0x00000042 = 0x00000000; CR=0; XER=0
+#5: divweu: 0x00000005 / 0xfabc1234 = 0x00000005; CR=0; XER=0
+
+#0: divweu.: 0x00000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divweu.: 0x00000002 / 0x00000000 = 0x00000000; CR=2; XER=0
+#2: divweu.: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=4; XER=0
+#3: divweu.: 0xfabc1234 / 0x00000005 = 0x00000000; CR=2; XER=0
+#4: divweu.: 0x0000004d / 0x00000042 = 0x00000000; CR=2; XER=0
+#5: divweu.: 0x00000005 / 0xfabc1234 = 0x00000005; CR=4; XER=0
+
+
+#0: divweuo: 0x00000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divweuo: 0x00000002 / 0x00000000 = 0x00000000; CR=0; XER=c0000000
+#2: divweuo: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=0; XER=0
+#3: divweuo: 0xfabc1234 / 0x00000005 = 0x00000000; CR=0; XER=c0000000
+#4: divweuo: 0x0000004d / 0x00000042 = 0x00000000; CR=0; XER=c0000000
+#5: divweuo: 0x00000005 / 0xfabc1234 = 0x00000005; CR=0; XER=0
+
+#0: divweuo.: 0x00000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divweuo.: 0x00000002 / 0x00000000 = 0x00000000; CR=3; XER=c0000000
+#2: divweuo.: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=4; XER=0
+#3: divweuo.: 0xfabc1234 / 0x00000005 = 0x00000000; CR=3; XER=c0000000
+#4: divweuo.: 0x0000004d / 0x00000042 = 0x00000000; CR=3; XER=c0000000
+#5: divweuo.: 0x00000005 / 0xfabc1234 = 0x00000005; CR=4; XER=0
+
+
diff --git a/none/tests/ppc64/test_isa_2_06_part2-div.stdout.exp-LE-ISA3_0 b/none/tests/ppc64/test_isa_2_06_part2-div.stdout.exp-LE-ISA3_0
new file mode 100644
index 0000000..6750771
--- /dev/null
+++ b/none/tests/ppc64/test_isa_2_06_part2-div.stdout.exp-LE-ISA3_0
@@ -0,0 +1,89 @@
+Test div extensions
+#0: divde: 0x0000000000000004 / 0xfffffffffffffffc = 0x0000000000000000; CR=0; XER=0
+#1: divde: 0x0000000000000004 / 0xfffffffffffffffd = 0x0000000000000000; CR=0; XER=0
+#2: divde: 0x0000000000000004 / 0x0000000000000004 = 0x0000000000000000; CR=0; XER=0
+#3: divde: 0x0000000000000004 / 0xfffffffffffffffb = 0x0000000000000000; CR=0; XER=0
+#4: divde: 0x0000000000000003 / 0x0000000000000008 = 0x6000000000000000; CR=0; XER=0
+#5: divde: 0x8000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=0; XER=0
+#6: divde: 0x000000000000050c / 0xffffffffffffffff = 0x0000000000000000; CR=0; XER=0
+#7: divde: 0x000000000000050c / 0xfffffffffffff000 = 0xaf40000000000000; CR=0; XER=0
+#8: divde: 0x000000001234fedc / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=0; XER=0
+#9: divde: 0xabcd87651234fedc / 0x00000000a123b893 = 0x0000000000000000; CR=0; XER=0
+#10: divde: 0x000123456789abdc / 0x0000000000000000 = 0x0000000000000000; CR=0; XER=0
+#11: divde: 0x0000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=0; XER=0
+#12: divde: 0x0000000000000077 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=0; XER=0
+
+#0: divde.: 0x0000000000000004 / 0xfffffffffffffffc = 0x0000000000000000; CR=2; XER=0
+#1: divde.: 0x0000000000000004 / 0xfffffffffffffffd = 0x0000000000000000; CR=2; XER=0
+#2: divde.: 0x0000000000000004 / 0x0000000000000004 = 0x0000000000000000; CR=2; XER=0
+#3: divde.: 0x0000000000000004 / 0xfffffffffffffffb = 0x0000000000000000; CR=2; XER=0
+#4: divde.: 0x0000000000000003 / 0x0000000000000008 = 0x6000000000000000; CR=4; XER=0
+#5: divde.: 0x8000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=2; XER=0
+#6: divde.: 0x000000000000050c / 0xffffffffffffffff = 0x0000000000000000; CR=2; XER=0
+#7: divde.: 0x000000000000050c / 0xfffffffffffff000 = 0xaf40000000000000; CR=8; XER=0
+#8: divde.: 0x000000001234fedc / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=4; XER=0
+#9: divde.: 0xabcd87651234fedc / 0x00000000a123b893 = 0x0000000000000000; CR=2; XER=0
+#10: divde.: 0x000123456789abdc / 0x0000000000000000 = 0x0000000000000000; CR=2; XER=0
+#11: divde.: 0x0000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=2; XER=0
+#12: divde.: 0x0000000000000077 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=4; XER=0
+
+
+#0: divdeo: 0x0000000000000004 / 0xfffffffffffffffc = 0x0000000000000000; CR=0; XER=c0080000
+#1: divdeo: 0x0000000000000004 / 0xfffffffffffffffd = 0x0000000000000000; CR=0; XER=c0080000
+#2: divdeo: 0x0000000000000004 / 0x0000000000000004 = 0x0000000000000000; CR=0; XER=c0080000
+#3: divdeo: 0x0000000000000004 / 0xfffffffffffffffb = 0x0000000000000000; CR=0; XER=c0080000
+#4: divdeo: 0x0000000000000003 / 0x0000000000000008 = 0x6000000000000000; CR=0; XER=0
+#5: divdeo: 0x8000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=0; XER=c0080000
+#6: divdeo: 0x000000000000050c / 0xffffffffffffffff = 0x0000000000000000; CR=0; XER=c0080000
+#7: divdeo: 0x000000000000050c / 0xfffffffffffff000 = 0xaf40000000000000; CR=0; XER=0
+#8: divdeo: 0x000000001234fedc / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=0; XER=0
+#9: divdeo: 0xabcd87651234fedc / 0x00000000a123b893 = 0x0000000000000000; CR=0; XER=c0080000
+#10: divdeo: 0x000123456789abdc / 0x0000000000000000 = 0x0000000000000000; CR=0; XER=c0080000
+#11: divdeo: 0x0000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=0; XER=0
+#12: divdeo: 0x0000000000000077 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=0; XER=0
+
+#0: divdeo.: 0x0000000000000004 / 0xfffffffffffffffc = 0x0000000000000000; CR=3; XER=c0080000
+#1: divdeo.: 0x0000000000000004 / 0xfffffffffffffffd = 0x0000000000000000; CR=3; XER=c0080000
+#2: divdeo.: 0x0000000000000004 / 0x0000000000000004 = 0x0000000000000000; CR=3; XER=c0080000
+#3: divdeo.: 0x0000000000000004 / 0xfffffffffffffffb = 0x0000000000000000; CR=3; XER=c0080000
+#4: divdeo.: 0x0000000000000003 / 0x0000000000000008 = 0x6000000000000000; CR=4; XER=0
+#5: divdeo.: 0x8000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=3; XER=c0080000
+#6: divdeo.: 0x000000000000050c / 0xffffffffffffffff = 0x0000000000000000; CR=3; XER=c0080000
+#7: divdeo.: 0x000000000000050c / 0xfffffffffffff000 = 0xaf40000000000000; CR=8; XER=0
+#8: divdeo.: 0x000000001234fedc / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=4; XER=0
+#9: divdeo.: 0xabcd87651234fedc / 0x00000000a123b893 = 0x0000000000000000; CR=3; XER=c0080000
+#10: divdeo.: 0x000123456789abdc / 0x0000000000000000 = 0x0000000000000000; CR=3; XER=c0080000
+#11: divdeo.: 0x0000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=2; XER=0
+#12: divdeo.: 0x0000000000000077 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=4; XER=0
+
+
+#0: divweu: 0x00000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divweu: 0x00000002 / 0x00000000 = 0x00000000; CR=0; XER=0
+#2: divweu: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=0; XER=0
+#3: divweu: 0xfabc1234 / 0x00000005 = 0x00000000; CR=0; XER=0
+#4: divweu: 0x0000004d / 0x00000042 = 0x00000000; CR=0; XER=0
+#5: divweu: 0x00000005 / 0xfabc1234 = 0x00000005; CR=0; XER=0
+
+#0: divweu.: 0x00000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divweu.: 0x00000002 / 0x00000000 = 0x00000000; CR=2; XER=0
+#2: divweu.: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=4; XER=0
+#3: divweu.: 0xfabc1234 / 0x00000005 = 0x00000000; CR=2; XER=0
+#4: divweu.: 0x0000004d / 0x00000042 = 0x00000000; CR=2; XER=0
+#5: divweu.: 0x00000005 / 0xfabc1234 = 0x00000005; CR=4; XER=0
+
+
+#0: divweuo: 0x00000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divweuo: 0x00000002 / 0x00000000 = 0x00000000; CR=0; XER=c0080000
+#2: divweuo: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=0; XER=0
+#3: divweuo: 0xfabc1234 / 0x00000005 = 0x00000000; CR=0; XER=c0080000
+#4: divweuo: 0x0000004d / 0x00000042 = 0x00000000; CR=0; XER=c0080000
+#5: divweuo: 0x00000005 / 0xfabc1234 = 0x00000005; CR=0; XER=0
+
+#0: divweuo.: 0x00000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divweuo.: 0x00000002 / 0x00000000 = 0x00000000; CR=3; XER=c0080000
+#2: divweuo.: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=4; XER=0
+#3: divweuo.: 0xfabc1234 / 0x00000005 = 0x00000000; CR=3; XER=c0080000
+#4: divweuo.: 0x0000004d / 0x00000042 = 0x00000000; CR=3; XER=c0080000
+#5: divweuo.: 0x00000005 / 0xfabc1234 = 0x00000005; CR=4; XER=0
+
+
diff --git a/none/tests/ppc64/test_isa_2_06_part2-div.vgtest b/none/tests/ppc64/test_isa_2_06_part2-div.vgtest
new file mode 100644
index 0000000..7f9e006
--- /dev/null
+++ b/none/tests/ppc64/test_isa_2_06_part2-div.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_ppc64_auxv_cap arch_2_06
+prog: test_isa_2_06_part2 -d
diff --git a/none/tests/ppc64/test_isa_2_06_part2.c b/none/tests/ppc64/test_isa_2_06_part2.c
index b33849a..c7bf4fe 100644
--- a/none/tests/ppc64/test_isa_2_06_part2.c
+++ b/none/tests/ppc64/test_isa_2_06_part2.c
@@ -29,6 +29,7 @@
#include <malloc.h>
#include <altivec.h>
#include <math.h>
+#include <unistd.h> // getopt
#ifndef __powerpc64__
typedef uint32_t HWord_t;
@@ -92,6 +93,9 @@
typedef void (*test_func_t)(void);
typedef struct test_table test_table_t;
+/* Defines for the instructiion groups, use bit field to identify */
+#define SCALAR_DIV_INST 0x0001
+#define OTHER_INST 0x0002
/* These functions below that construct a table of floating point
* values were lifted from none/tests/ppc32/jm-insns.c.
@@ -541,6 +545,7 @@
{
test_func_t test_category;
char * name;
+ unsigned int test_group;
};
typedef enum {
@@ -1741,33 +1746,44 @@
all_tests[] =
{
{ &test_vx_vector_one_fp_arg,
- "Test VSX vector single arg instructions"},
+ "Test VSX vector single arg instructions", OTHER_INST },
{ &test_vx_vector_fp_ops,
- "Test VSX floating point compare and basic arithmetic instructions" },
+ "Test VSX floating point compare and basic arithmetic instructions", OTHER_INST },
#ifdef __powerpc64__
{ &test_bpermd,
- "Test bit permute double"},
+ "Test bit permute double", OTHER_INST },
#endif
{ &test_xxsel,
- "Test xxsel instruction" },
+ "Test xxsel instruction", OTHER_INST },
{ &test_xxspltw,
- "Test xxspltw instruction" },
+ "Test xxspltw instruction", OTHER_INST },
{ &test_div_extensions,
- "Test div extensions" },
+ "Test div extensions", SCALAR_DIV_INST },
{ &test_fct_ops,
- "Test floating point convert [word | doubleword] unsigned, with round toward zero" },
+ "Test floating point convert [word | doubleword] unsigned, with round toward zero", OTHER_INST },
#ifdef __powerpc64__
{ &test_stdbrx,
- "Test stdbrx instruction"},
+ "Test stdbrx instruction", OTHER_INST },
#endif
{ &test_vx_aORm_fp_ops,
- "Test floating point arithmetic instructions -- with a{d|s}p or m{d|s}p"},
+ "Test floating point arithmetic instructions -- with a{d|s}p or m{d|s}p", OTHER_INST },
{ &test_vx_simple_scalar_fp_ops,
- "Test scalar floating point arithmetic instructions"},
+ "Test scalar floating point arithmetic instructions", OTHER_INST },
{ NULL, NULL }
};
#endif // HAS_VSX
+static void usage (void)
+{
+ fprintf(stderr,
+ "Usage: test_isa_3_0 [OPTIONS]\n"
+ "\t-d: test scalar division instructions (default)\n"
+ "\t-o: test non scalar division instructions (default)\n"
+ "\t-A: test all instructions (default)\n"
+ "\t-h: display this help and exit\n"
+ );
+}
+
int main(int argc, char *argv[])
{
#ifdef HAS_VSX
@@ -1775,11 +1791,47 @@
test_table_t aTest;
test_func_t func;
int i = 0;
+ int c;
+ unsigned int test_run_mask = 0;
+
+ /* NOTE, ISA 3.0 introduces the OV32 and CA32 bits in the FPSCR. These
+ * bits are set on various arithimetic instructions. This means this
+ * test generates different FPSCR output for pre ISA 3.0 versus ISA 3.0
+ * hardware. The tests have been grouped so that the tests that generate
+ * different results are in one test and the rest are in a different test.
+ * this minimizes the size of the result expect files for the two cases.
+ */
+
+ while ((c = getopt(argc, argv, "doAh")) != -1) {
+ switch (c) {
+ case 'd':
+ test_run_mask |= SCALAR_DIV_INST;
+ break;
+ case 'o':
+ test_run_mask |= OTHER_INST;
+ break;
+ case 'A':
+ test_run_mask = 0xFFFF;
+ break;
+ case 'h':
+ usage();
+ return 0;
+
+ default:
+ usage();
+ fprintf(stderr, "Unknown argument: '%c'\n", c);
+ return 1;
+ }
+ }
while ((func = all_tests[i].test_category)) {
aTest = all_tests[i];
- printf( "%s\n", aTest.name );
- (*func)();
+ if(test_run_mask & aTest.test_group) {
+ /* Test group specified on command line */
+
+ printf( "%s\n", aTest.name );
+ (*func)();
+ }
i++;
}
if (spec_fargs)
diff --git a/none/tests/ppc64/test_isa_2_06_part2.stdout.exp b/none/tests/ppc64/test_isa_2_06_part2.stdout.exp
index 22631d0..2a67112 100644
--- a/none/tests/ppc64/test_isa_2_06_part2.stdout.exp
+++ b/none/tests/ppc64/test_isa_2_06_part2.stdout.exp
@@ -702,95 +702,6 @@
xxspltw 0xfedc432124681235f1e2d3c4e0057708 2=> 0xf1e2d3c4f1e2d3c4f1e2d3c4f1e2d3c4
xxspltw 0xfedc432124681235f1e2d3c4e0057708 3=> 0xe0057708e0057708e0057708e0057708
-Test div extensions
-#0: divde: 0x0000000000000004 / 0xfffffffffffffffc = 0x0000000000000000; CR=0; XER=0
-#1: divde: 0x0000000000000004 / 0xfffffffffffffffd = 0x0000000000000000; CR=0; XER=0
-#2: divde: 0x0000000000000004 / 0x0000000000000004 = 0x0000000000000000; CR=0; XER=0
-#3: divde: 0x0000000000000004 / 0xfffffffffffffffb = 0x0000000000000000; CR=0; XER=0
-#4: divde: 0x0000000000000003 / 0x0000000000000008 = 0x6000000000000000; CR=0; XER=0
-#5: divde: 0x8000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=0; XER=0
-#6: divde: 0x000000000000050c / 0xffffffffffffffff = 0x0000000000000000; CR=0; XER=0
-#7: divde: 0x000000000000050c / 0xfffffffffffff000 = 0xaf40000000000000; CR=0; XER=0
-#8: divde: 0x000000001234fedc / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=0; XER=0
-#9: divde: 0xabcd87651234fedc / 0x00000000a123b893 = 0x0000000000000000; CR=0; XER=0
-#10: divde: 0x000123456789abdc / 0x0000000000000000 = 0x0000000000000000; CR=0; XER=0
-#11: divde: 0x0000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=0; XER=0
-#12: divde: 0x0000000000000077 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=0; XER=0
-
-#0: divde.: 0x0000000000000004 / 0xfffffffffffffffc = 0x0000000000000000; CR=2; XER=0
-#1: divde.: 0x0000000000000004 / 0xfffffffffffffffd = 0x0000000000000000; CR=2; XER=0
-#2: divde.: 0x0000000000000004 / 0x0000000000000004 = 0x0000000000000000; CR=2; XER=0
-#3: divde.: 0x0000000000000004 / 0xfffffffffffffffb = 0x0000000000000000; CR=2; XER=0
-#4: divde.: 0x0000000000000003 / 0x0000000000000008 = 0x6000000000000000; CR=4; XER=0
-#5: divde.: 0x8000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=2; XER=0
-#6: divde.: 0x000000000000050c / 0xffffffffffffffff = 0x0000000000000000; CR=2; XER=0
-#7: divde.: 0x000000000000050c / 0xfffffffffffff000 = 0xaf40000000000000; CR=8; XER=0
-#8: divde.: 0x000000001234fedc / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=4; XER=0
-#9: divde.: 0xabcd87651234fedc / 0x00000000a123b893 = 0x0000000000000000; CR=2; XER=0
-#10: divde.: 0x000123456789abdc / 0x0000000000000000 = 0x0000000000000000; CR=2; XER=0
-#11: divde.: 0x0000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=2; XER=0
-#12: divde.: 0x0000000000000077 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=4; XER=0
-
-
-#0: divdeo: 0x0000000000000004 / 0xfffffffffffffffc = 0x0000000000000000; CR=0; XER=c0000000
-#1: divdeo: 0x0000000000000004 / 0xfffffffffffffffd = 0x0000000000000000; CR=0; XER=c0000000
-#2: divdeo: 0x0000000000000004 / 0x0000000000000004 = 0x0000000000000000; CR=0; XER=c0000000
-#3: divdeo: 0x0000000000000004 / 0xfffffffffffffffb = 0x0000000000000000; CR=0; XER=c0000000
-#4: divdeo: 0x0000000000000003 / 0x0000000000000008 = 0x6000000000000000; CR=0; XER=0
-#5: divdeo: 0x8000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=0; XER=c0000000
-#6: divdeo: 0x000000000000050c / 0xffffffffffffffff = 0x0000000000000000; CR=0; XER=c0000000
-#7: divdeo: 0x000000000000050c / 0xfffffffffffff000 = 0xaf40000000000000; CR=0; XER=0
-#8: divdeo: 0x000000001234fedc / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=0; XER=0
-#9: divdeo: 0xabcd87651234fedc / 0x00000000a123b893 = 0x0000000000000000; CR=0; XER=c0000000
-#10: divdeo: 0x000123456789abdc / 0x0000000000000000 = 0x0000000000000000; CR=0; XER=c0000000
-#11: divdeo: 0x0000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=0; XER=0
-#12: divdeo: 0x0000000000000077 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=0; XER=0
-
-#0: divdeo.: 0x0000000000000004 / 0xfffffffffffffffc = 0x0000000000000000; CR=3; XER=c0000000
-#1: divdeo.: 0x0000000000000004 / 0xfffffffffffffffd = 0x0000000000000000; CR=3; XER=c0000000
-#2: divdeo.: 0x0000000000000004 / 0x0000000000000004 = 0x0000000000000000; CR=3; XER=c0000000
-#3: divdeo.: 0x0000000000000004 / 0xfffffffffffffffb = 0x0000000000000000; CR=3; XER=c0000000
-#4: divdeo.: 0x0000000000000003 / 0x0000000000000008 = 0x6000000000000000; CR=4; XER=0
-#5: divdeo.: 0x8000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=3; XER=c0000000
-#6: divdeo.: 0x000000000000050c / 0xffffffffffffffff = 0x0000000000000000; CR=3; XER=c0000000
-#7: divdeo.: 0x000000000000050c / 0xfffffffffffff000 = 0xaf40000000000000; CR=8; XER=0
-#8: divdeo.: 0x000000001234fedc / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=4; XER=0
-#9: divdeo.: 0xabcd87651234fedc / 0x00000000a123b893 = 0x0000000000000000; CR=3; XER=c0000000
-#10: divdeo.: 0x000123456789abdc / 0x0000000000000000 = 0x0000000000000000; CR=3; XER=c0000000
-#11: divdeo.: 0x0000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=2; XER=0
-#12: divdeo.: 0x0000000000000077 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=4; XER=0
-
-
-#0: divweu: 0x00000000 / 0x00000002 = 0x00000000; CR=0; XER=0
-#1: divweu: 0x00000002 / 0x00000000 = 0x00000000; CR=0; XER=0
-#2: divweu: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=0; XER=0
-#3: divweu: 0xfabc1234 / 0x00000005 = 0x00000000; CR=0; XER=0
-#4: divweu: 0x0000004d / 0x00000042 = 0x00000000; CR=0; XER=0
-#5: divweu: 0x00000005 / 0xfabc1234 = 0x00000005; CR=0; XER=0
-
-#0: divweu.: 0x00000000 / 0x00000002 = 0x00000000; CR=2; XER=0
-#1: divweu.: 0x00000002 / 0x00000000 = 0x00000000; CR=2; XER=0
-#2: divweu.: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=4; XER=0
-#3: divweu.: 0xfabc1234 / 0x00000005 = 0x00000000; CR=2; XER=0
-#4: divweu.: 0x0000004d / 0x00000042 = 0x00000000; CR=2; XER=0
-#5: divweu.: 0x00000005 / 0xfabc1234 = 0x00000005; CR=4; XER=0
-
-
-#0: divweuo: 0x00000000 / 0x00000002 = 0x00000000; CR=0; XER=0
-#1: divweuo: 0x00000002 / 0x00000000 = 0x00000000; CR=0; XER=c0000000
-#2: divweuo: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=0; XER=0
-#3: divweuo: 0xfabc1234 / 0x00000005 = 0x00000000; CR=0; XER=c0000000
-#4: divweuo: 0x0000004d / 0x00000042 = 0x00000000; CR=0; XER=c0000000
-#5: divweuo: 0x00000005 / 0xfabc1234 = 0x00000005; CR=0; XER=0
-
-#0: divweuo.: 0x00000000 / 0x00000002 = 0x00000000; CR=2; XER=0
-#1: divweuo.: 0x00000002 / 0x00000000 = 0x00000000; CR=3; XER=c0000000
-#2: divweuo.: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=4; XER=0
-#3: divweuo.: 0xfabc1234 / 0x00000005 = 0x00000000; CR=3; XER=c0000000
-#4: divweuo.: 0x0000004d / 0x00000042 = 0x00000000; CR=3; XER=c0000000
-#5: divweuo.: 0x00000005 / 0xfabc1234 = 0x00000005; CR=4; XER=0
-
-
Test floating point convert [word | doubleword] unsigned, with round toward zero
#0: fctiduz: 0x3fd8000000000000 (3.750000e-01) ==> 0x0000000000000000
#1: fctiduz: 0x404f000000000000 (6.200000e+01) ==> 0x000000000000003e
diff --git a/none/tests/ppc64/test_isa_2_06_part2.vgtest b/none/tests/ppc64/test_isa_2_06_part2.vgtest
index 7783c5e..fe4d659 100644
--- a/none/tests/ppc64/test_isa_2_06_part2.vgtest
+++ b/none/tests/ppc64/test_isa_2_06_part2.vgtest
@@ -1,2 +1,2 @@
prereq: ../../../tests/check_ppc64_auxv_cap arch_2_06
-prog: test_isa_2_06_part2
+prog: test_isa_2_06_part2 -o
diff --git a/none/tests/ppc64/test_isa_2_06_part3-div.stderr.exp b/none/tests/ppc64/test_isa_2_06_part3-div.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/none/tests/ppc64/test_isa_2_06_part3-div.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/none/tests/ppc64/test_isa_2_06_part3-div.stdout.exp b/none/tests/ppc64/test_isa_2_06_part3-div.stdout.exp
new file mode 100644
index 0000000..2ee5a93
--- /dev/null
+++ b/none/tests/ppc64/test_isa_2_06_part3-div.stdout.exp
@@ -0,0 +1,89 @@
+Test div extensions
+#0: divdeu: 0x00000000000000040000000000000000 / 0xfffffffffffffffc = 0x0000000000000004; CR=0; XER=0
+#1: divdeu: 0x00000000000000040000000000000000 / 0xfffffffffffffffd = 0x0000000000000004; CR=0; XER=0
+#2: divdeu: 0x00000000000000040000000000000000 / 0x0000000000000004 = 0x0000000000000000; CR=0; XER=0
+#3: divdeu: 0x00000000000000040000000000000000 / 0xfffffffffffffffb = 0x0000000000000004; CR=0; XER=0
+#4: divdeu: 0x00000000000000030000000000000000 / 0x0000000000000008 = 0x6000000000000000; CR=0; XER=0
+#5: divdeu: 0x80000000000000000000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=0; XER=0
+#6: divdeu: 0x000000000000050c0000000000000000 / 0xffffffffffffffff = 0x000000000000050c; CR=0; XER=0
+#7: divdeu: 0x000000000000050c0000000000000000 / 0xfffffffffffff000 = 0x000000000000050c; CR=0; XER=0
+#8: divdeu: 0x000000001234fedc0000000000000000 / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=0; XER=0
+#9: divdeu: 0xabcd87651234fedc0000000000000000 / 0x00000000a123b893 = 0x0000000000000000; CR=0; XER=0
+#10: divdeu: 0x000123456789abdc0000000000000000 / 0x0000000000000000 = 0x0000000000000000; CR=0; XER=0
+#11: divdeu: 0x00000000000000000000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=0; XER=0
+#12: divdeu: 0x00000000000000770000000000000000 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=0; XER=0
+
+#0: divdeu.: 0x00000000000000040000000000000000 / 0xfffffffffffffffc = 0x0000000000000004; CR=4; XER=0
+#1: divdeu.: 0x00000000000000040000000000000000 / 0xfffffffffffffffd = 0x0000000000000004; CR=4; XER=0
+#2: divdeu.: 0x00000000000000040000000000000000 / 0x0000000000000004 = 0x0000000000000000; CR=2; XER=0
+#3: divdeu.: 0x00000000000000040000000000000000 / 0xfffffffffffffffb = 0x0000000000000004; CR=4; XER=0
+#4: divdeu.: 0x00000000000000030000000000000000 / 0x0000000000000008 = 0x6000000000000000; CR=4; XER=0
+#5: divdeu.: 0x80000000000000000000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=2; XER=0
+#6: divdeu.: 0x000000000000050c0000000000000000 / 0xffffffffffffffff = 0x000000000000050c; CR=4; XER=0
+#7: divdeu.: 0x000000000000050c0000000000000000 / 0xfffffffffffff000 = 0x000000000000050c; CR=4; XER=0
+#8: divdeu.: 0x000000001234fedc0000000000000000 / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=4; XER=0
+#9: divdeu.: 0xabcd87651234fedc0000000000000000 / 0x00000000a123b893 = 0x0000000000000000; CR=2; XER=0
+#10: divdeu.: 0x000123456789abdc0000000000000000 / 0x0000000000000000 = 0x0000000000000000; CR=2; XER=0
+#11: divdeu.: 0x00000000000000000000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=2; XER=0
+#12: divdeu.: 0x00000000000000770000000000000000 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=4; XER=0
+
+
+#0: divdeuo: 0x00000000000000040000000000000000 / 0xfffffffffffffffc = 0x0000000000000004; CR=0; XER=0
+#1: divdeuo: 0x00000000000000040000000000000000 / 0xfffffffffffffffd = 0x0000000000000004; CR=0; XER=0
+#2: divdeuo: 0x00000000000000040000000000000000 / 0x0000000000000004 = 0x0000000000000000; CR=0; XER=c0000000
+#3: divdeuo: 0x00000000000000040000000000000000 / 0xfffffffffffffffb = 0x0000000000000004; CR=0; XER=0
+#4: divdeuo: 0x00000000000000030000000000000000 / 0x0000000000000008 = 0x6000000000000000; CR=0; XER=0
+#5: divdeuo: 0x80000000000000000000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=0; XER=c0000000
+#6: divdeuo: 0x000000000000050c0000000000000000 / 0xffffffffffffffff = 0x000000000000050c; CR=0; XER=0
+#7: divdeuo: 0x000000000000050c0000000000000000 / 0xfffffffffffff000 = 0x000000000000050c; CR=0; XER=0
+#8: divdeuo: 0x000000001234fedc0000000000000000 / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=0; XER=0
+#9: divdeuo: 0xabcd87651234fedc0000000000000000 / 0x00000000a123b893 = 0x0000000000000000; CR=0; XER=c0000000
+#10: divdeuo: 0x000123456789abdc0000000000000000 / 0x0000000000000000 = 0x0000000000000000; CR=0; XER=c0000000
+#11: divdeuo: 0x00000000000000000000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=0; XER=0
+#12: divdeuo: 0x00000000000000770000000000000000 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=0; XER=0
+
+#0: divdeuo.: 0x00000000000000040000000000000000 / 0xfffffffffffffffc = 0x0000000000000004; CR=4; XER=0
+#1: divdeuo.: 0x00000000000000040000000000000000 / 0xfffffffffffffffd = 0x0000000000000004; CR=4; XER=0
+#2: divdeuo.: 0x00000000000000040000000000000000 / 0x0000000000000004 = 0x0000000000000000; CR=3; XER=c0000000
+#3: divdeuo.: 0x00000000000000040000000000000000 / 0xfffffffffffffffb = 0x0000000000000004; CR=4; XER=0
+#4: divdeuo.: 0x00000000000000030000000000000000 / 0x0000000000000008 = 0x6000000000000000; CR=4; XER=0
+#5: divdeuo.: 0x80000000000000000000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=3; XER=c0000000
+#6: divdeuo.: 0x000000000000050c0000000000000000 / 0xffffffffffffffff = 0x000000000000050c; CR=4; XER=0
+#7: divdeuo.: 0x000000000000050c0000000000000000 / 0xfffffffffffff000 = 0x000000000000050c; CR=4; XER=0
+#8: divdeuo.: 0x000000001234fedc0000000000000000 / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=4; XER=0
+#9: divdeuo.: 0xabcd87651234fedc0000000000000000 / 0x00000000a123b893 = 0x0000000000000000; CR=3; XER=c0000000
+#10: divdeuo.: 0x000123456789abdc0000000000000000 / 0x0000000000000000 = 0x0000000000000000; CR=3; XER=c0000000
+#11: divdeuo.: 0x00000000000000000000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=2; XER=0
+#12: divdeuo.: 0x00000000000000770000000000000000 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=4; XER=0
+
+
+#0: divwe: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divwe: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=0; XER=0
+#2: divwe: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=0; XER=0
+#3: divwe: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=0; XER=0
+#4: divwe: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=0; XER=0
+#5: divwe: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=0; XER=0
+
+#0: divwe.: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divwe.: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=2; XER=0
+#2: divwe.: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=2; XER=0
+#3: divwe.: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=2; XER=0
+#4: divwe.: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=2; XER=0
+#5: divwe.: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=4; XER=0
+
+
+#0: divweo: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divweo: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=0; XER=c0000000
+#2: divweo: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=0; XER=c0000000
+#3: divweo: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=0; XER=c0000000
+#4: divweo: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=0; XER=c0000000
+#5: divweo: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=0; XER=0
+
+#0: divweo.: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divweo.: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=3; XER=c0000000
+#2: divweo.: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=3; XER=c0000000
+#3: divweo.: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=3; XER=c0000000
+#4: divweo.: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=3; XER=c0000000
+#5: divweo.: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=4; XER=0
+
+
diff --git a/none/tests/ppc64/test_isa_2_06_part3-div.stdout.exp-LE-ISA3_0 b/none/tests/ppc64/test_isa_2_06_part3-div.stdout.exp-LE-ISA3_0
new file mode 100644
index 0000000..4f39158
--- /dev/null
+++ b/none/tests/ppc64/test_isa_2_06_part3-div.stdout.exp-LE-ISA3_0
@@ -0,0 +1,89 @@
+Test div extensions
+#0: divdeu: 0x00000000000000040000000000000000 / 0xfffffffffffffffc = 0x0000000000000004; CR=0; XER=0
+#1: divdeu: 0x00000000000000040000000000000000 / 0xfffffffffffffffd = 0x0000000000000004; CR=0; XER=0
+#2: divdeu: 0x00000000000000040000000000000000 / 0x0000000000000004 = 0x0000000000000000; CR=0; XER=0
+#3: divdeu: 0x00000000000000040000000000000000 / 0xfffffffffffffffb = 0x0000000000000004; CR=0; XER=0
+#4: divdeu: 0x00000000000000030000000000000000 / 0x0000000000000008 = 0x6000000000000000; CR=0; XER=0
+#5: divdeu: 0x80000000000000000000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=0; XER=0
+#6: divdeu: 0x000000000000050c0000000000000000 / 0xffffffffffffffff = 0x000000000000050c; CR=0; XER=0
+#7: divdeu: 0x000000000000050c0000000000000000 / 0xfffffffffffff000 = 0x000000000000050c; CR=0; XER=0
+#8: divdeu: 0x000000001234fedc0000000000000000 / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=0; XER=0
+#9: divdeu: 0xabcd87651234fedc0000000000000000 / 0x00000000a123b893 = 0x0000000000000000; CR=0; XER=0
+#10: divdeu: 0x000123456789abdc0000000000000000 / 0x0000000000000000 = 0x0000000000000000; CR=0; XER=0
+#11: divdeu: 0x00000000000000000000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=0; XER=0
+#12: divdeu: 0x00000000000000770000000000000000 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=0; XER=0
+
+#0: divdeu.: 0x00000000000000040000000000000000 / 0xfffffffffffffffc = 0x0000000000000004; CR=4; XER=0
+#1: divdeu.: 0x00000000000000040000000000000000 / 0xfffffffffffffffd = 0x0000000000000004; CR=4; XER=0
+#2: divdeu.: 0x00000000000000040000000000000000 / 0x0000000000000004 = 0x0000000000000000; CR=2; XER=0
+#3: divdeu.: 0x00000000000000040000000000000000 / 0xfffffffffffffffb = 0x0000000000000004; CR=4; XER=0
+#4: divdeu.: 0x00000000000000030000000000000000 / 0x0000000000000008 = 0x6000000000000000; CR=4; XER=0
+#5: divdeu.: 0x80000000000000000000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=2; XER=0
+#6: divdeu.: 0x000000000000050c0000000000000000 / 0xffffffffffffffff = 0x000000000000050c; CR=4; XER=0
+#7: divdeu.: 0x000000000000050c0000000000000000 / 0xfffffffffffff000 = 0x000000000000050c; CR=4; XER=0
+#8: divdeu.: 0x000000001234fedc0000000000000000 / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=4; XER=0
+#9: divdeu.: 0xabcd87651234fedc0000000000000000 / 0x00000000a123b893 = 0x0000000000000000; CR=2; XER=0
+#10: divdeu.: 0x000123456789abdc0000000000000000 / 0x0000000000000000 = 0x0000000000000000; CR=2; XER=0
+#11: divdeu.: 0x00000000000000000000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=2; XER=0
+#12: divdeu.: 0x00000000000000770000000000000000 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=4; XER=0
+
+
+#0: divdeuo: 0x00000000000000040000000000000000 / 0xfffffffffffffffc = 0x0000000000000004; CR=0; XER=0
+#1: divdeuo: 0x00000000000000040000000000000000 / 0xfffffffffffffffd = 0x0000000000000004; CR=0; XER=0
+#2: divdeuo: 0x00000000000000040000000000000000 / 0x0000000000000004 = 0x0000000000000000; CR=0; XER=c0080000
+#3: divdeuo: 0x00000000000000040000000000000000 / 0xfffffffffffffffb = 0x0000000000000004; CR=0; XER=0
+#4: divdeuo: 0x00000000000000030000000000000000 / 0x0000000000000008 = 0x6000000000000000; CR=0; XER=0
+#5: divdeuo: 0x80000000000000000000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=0; XER=c0080000
+#6: divdeuo: 0x000000000000050c0000000000000000 / 0xffffffffffffffff = 0x000000000000050c; CR=0; XER=0
+#7: divdeuo: 0x000000000000050c0000000000000000 / 0xfffffffffffff000 = 0x000000000000050c; CR=0; XER=0
+#8: divdeuo: 0x000000001234fedc0000000000000000 / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=0; XER=0
+#9: divdeuo: 0xabcd87651234fedc0000000000000000 / 0x00000000a123b893 = 0x0000000000000000; CR=0; XER=c0080000
+#10: divdeuo: 0x000123456789abdc0000000000000000 / 0x0000000000000000 = 0x0000000000000000; CR=0; XER=c0080000
+#11: divdeuo: 0x00000000000000000000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=0; XER=0
+#12: divdeuo: 0x00000000000000770000000000000000 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=0; XER=0
+
+#0: divdeuo.: 0x00000000000000040000000000000000 / 0xfffffffffffffffc = 0x0000000000000004; CR=4; XER=0
+#1: divdeuo.: 0x00000000000000040000000000000000 / 0xfffffffffffffffd = 0x0000000000000004; CR=4; XER=0
+#2: divdeuo.: 0x00000000000000040000000000000000 / 0x0000000000000004 = 0x0000000000000000; CR=3; XER=c0080000
+#3: divdeuo.: 0x00000000000000040000000000000000 / 0xfffffffffffffffb = 0x0000000000000004; CR=4; XER=0
+#4: divdeuo.: 0x00000000000000030000000000000000 / 0x0000000000000008 = 0x6000000000000000; CR=4; XER=0
+#5: divdeuo.: 0x80000000000000000000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=3; XER=c0080000
+#6: divdeuo.: 0x000000000000050c0000000000000000 / 0xffffffffffffffff = 0x000000000000050c; CR=4; XER=0
+#7: divdeuo.: 0x000000000000050c0000000000000000 / 0xfffffffffffff000 = 0x000000000000050c; CR=4; XER=0
+#8: divdeuo.: 0x000000001234fedc0000000000000000 / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=4; XER=0
+#9: divdeuo.: 0xabcd87651234fedc0000000000000000 / 0x00000000a123b893 = 0x0000000000000000; CR=3; XER=c0080000
+#10: divdeuo.: 0x000123456789abdc0000000000000000 / 0x0000000000000000 = 0x0000000000000000; CR=3; XER=c0080000
+#11: divdeuo.: 0x00000000000000000000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=2; XER=0
+#12: divdeuo.: 0x00000000000000770000000000000000 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=4; XER=0
+
+
+#0: divwe: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divwe: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=0; XER=0
+#2: divwe: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=0; XER=0
+#3: divwe: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=0; XER=0
+#4: divwe: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=0; XER=0
+#5: divwe: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=0; XER=0
+
+#0: divwe.: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divwe.: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=2; XER=0
+#2: divwe.: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=2; XER=0
+#3: divwe.: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=2; XER=0
+#4: divwe.: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=2; XER=0
+#5: divwe.: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=4; XER=0
+
+
+#0: divweo: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divweo: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=0; XER=c0080000
+#2: divweo: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=0; XER=c0080000
+#3: divweo: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=0; XER=c0080000
+#4: divweo: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=0; XER=c0080000
+#5: divweo: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=0; XER=0
+
+#0: divweo.: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divweo.: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=3; XER=c0080000
+#2: divweo.: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=3; XER=c0080000
+#3: divweo.: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=3; XER=c0080000
+#4: divweo.: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=3; XER=c0080000
+#5: divweo.: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=4; XER=0
+
+
diff --git a/none/tests/ppc64/test_isa_2_06_part3-div.vgtest b/none/tests/ppc64/test_isa_2_06_part3-div.vgtest
new file mode 100644
index 0000000..5ab8320
--- /dev/null
+++ b/none/tests/ppc64/test_isa_2_06_part3-div.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_ppc64_auxv_cap arch_2_06
+prog: test_isa_2_06_part3 -d
diff --git a/none/tests/ppc64/test_isa_2_06_part3.c b/none/tests/ppc64/test_isa_2_06_part3.c
index 9f9cd79..8c74c09 100644
--- a/none/tests/ppc64/test_isa_2_06_part3.c
+++ b/none/tests/ppc64/test_isa_2_06_part3.c
@@ -29,6 +29,7 @@
#include <malloc.h>
#include <altivec.h>
#include <math.h>
+#include <unistd.h> // getopt
#ifndef __powerpc64__
typedef uint32_t HWord_t;
@@ -91,6 +92,9 @@
typedef void (*test_func_t)(void);
typedef struct test_table test_table_t;
+/* Defines for the instructiion groups, use bit field to identify */
+#define SCALAR_DIV_INST 0x0001
+#define OTHER_INST 0x0002
/* These functions below that construct a table of floating point
* values were lifted from none/tests/ppc32/jm-insns.c.
@@ -401,6 +405,7 @@
{
test_func_t test_category;
char * name;
+ unsigned int test_group;
};
/* Type of input for floating point operations.*/
@@ -1586,33 +1591,81 @@
{
{ &test_vsx_one_fp_arg,
- "Test VSX vector and scalar single argument instructions"} ,
+ "Test VSX vector and scalar single argument instructions", OTHER_INST } ,
{ &test_int_to_fp_convert,
- "Test VSX vector integer to float conversion instructions" },
+ "Test VSX vector integer to float conversion instructions", OTHER_INST },
{ &test_div_extensions,
- "Test div extensions" },
+ "Test div extensions", SCALAR_DIV_INST },
{ &test_ftsqrt,
- "Test ftsqrt instruction" },
+ "Test ftsqrt instruction", OTHER_INST },
{ &test_vx_tdivORtsqrt,
- "Test vector and scalar tdiv and tsqrt instructions" },
+ "Test vector and scalar tdiv and tsqrt instructions", OTHER_INST },
{ &test_popcntw,
- "Test popcntw instruction" },
+ "Test popcntw instruction", OTHER_INST },
{ NULL, NULL }
};
#endif // HAS_VSX
-int main(int argc, char *argv[])
+static void usage (void)
+{
+ fprintf(stderr,
+ "Usage: test_isa_3_0 [OPTIONS]\n"
+ "\t-d: test scalar division instructions (default)\n"
+ "\t-o: test non scalar division instructions (default)\n"
+ "\t-A: test all instructions (default)\n"
+ "\t-h: display this help and exit\n"
+ );
+}
+
+int main(int argc, char **argv)
{
#ifdef HAS_VSX
test_table_t aTest;
test_func_t func;
+ int c;
int i = 0;
+ unsigned int test_run_mask = 0;
+
+ /* NOTE, ISA 3.0 introduces the OV32 and CA32 bits in the FPSCR. These
+ * bits are set on various arithimetic instructions. This means this
+ * test generates different FPSCR output for pre ISA 3.0 versus ISA 3.0
+ * hardware. The tests have been grouped so that the tests that generate
+ * different results are in one test and the rest are in a different test.
+ * this minimizes the size of the result expect files for the two cases.
+ */
+
+ while ((c = getopt(argc, argv, "doAh")) != -1) {
+ switch (c) {
+ case 'd':
+ test_run_mask |= SCALAR_DIV_INST;
+ break;
+ case 'o':
+ test_run_mask |= OTHER_INST;
+ break;
+ case 'A':
+ test_run_mask = 0xFFFF;
+ break;
+ case 'h':
+ usage();
+ return 0;
+
+ default:
+ usage();
+ fprintf(stderr, "Unknown argument: '%c'\n", c);
+ return 1;
+ }
+ }
while ((func = all_tests[i].test_category)) {
aTest = all_tests[i];
- printf( "%s\n", aTest.name );
- (*func)();
+
+ if(test_run_mask & aTest.test_group) {
+ /* Test group specified on command line */
+
+ printf( "%s\n", aTest.name );
+ (*func)();
+ }
i++;
}
if (spec_fargs)
diff --git a/none/tests/ppc64/test_isa_2_06_part3.stdout.exp b/none/tests/ppc64/test_isa_2_06_part3.stdout.exp
index 90f17a4..1658a6e 100644
--- a/none/tests/ppc64/test_isa_2_06_part3.stdout.exp
+++ b/none/tests/ppc64/test_isa_2_06_part3.stdout.exp
@@ -455,95 +455,6 @@
#0: xvcvuxwsp conv(00000000) = 00000000; conv(ffff0000) = 4f7fff00; conv(0000ffff) = 477fff00; conv(ffffffff) = 4f800000
#1: xvcvuxwsp conv(89a73522) = 4f09a735; conv(01020304) = 4b810182; conv(0000abcd) = 472bcd00; conv(11223344) = 4d89119a
-Test div extensions
-#0: divdeu: 0x00000000000000040000000000000000 / 0xfffffffffffffffc = 0x0000000000000004; CR=0; XER=0
-#1: divdeu: 0x00000000000000040000000000000000 / 0xfffffffffffffffd = 0x0000000000000004; CR=0; XER=0
-#2: divdeu: 0x00000000000000040000000000000000 / 0x0000000000000004 = 0x0000000000000000; CR=0; XER=0
-#3: divdeu: 0x00000000000000040000000000000000 / 0xfffffffffffffffb = 0x0000000000000004; CR=0; XER=0
-#4: divdeu: 0x00000000000000030000000000000000 / 0x0000000000000008 = 0x6000000000000000; CR=0; XER=0
-#5: divdeu: 0x80000000000000000000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=0; XER=0
-#6: divdeu: 0x000000000000050c0000000000000000 / 0xffffffffffffffff = 0x000000000000050c; CR=0; XER=0
-#7: divdeu: 0x000000000000050c0000000000000000 / 0xfffffffffffff000 = 0x000000000000050c; CR=0; XER=0
-#8: divdeu: 0x000000001234fedc0000000000000000 / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=0; XER=0
-#9: divdeu: 0xabcd87651234fedc0000000000000000 / 0x00000000a123b893 = 0x0000000000000000; CR=0; XER=0
-#10: divdeu: 0x000123456789abdc0000000000000000 / 0x0000000000000000 = 0x0000000000000000; CR=0; XER=0
-#11: divdeu: 0x00000000000000000000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=0; XER=0
-#12: divdeu: 0x00000000000000770000000000000000 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=0; XER=0
-
-#0: divdeu.: 0x00000000000000040000000000000000 / 0xfffffffffffffffc = 0x0000000000000004; CR=4; XER=0
-#1: divdeu.: 0x00000000000000040000000000000000 / 0xfffffffffffffffd = 0x0000000000000004; CR=4; XER=0
-#2: divdeu.: 0x00000000000000040000000000000000 / 0x0000000000000004 = 0x0000000000000000; CR=2; XER=0
-#3: divdeu.: 0x00000000000000040000000000000000 / 0xfffffffffffffffb = 0x0000000000000004; CR=4; XER=0
-#4: divdeu.: 0x00000000000000030000000000000000 / 0x0000000000000008 = 0x6000000000000000; CR=4; XER=0
-#5: divdeu.: 0x80000000000000000000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=2; XER=0
-#6: divdeu.: 0x000000000000050c0000000000000000 / 0xffffffffffffffff = 0x000000000000050c; CR=4; XER=0
-#7: divdeu.: 0x000000000000050c0000000000000000 / 0xfffffffffffff000 = 0x000000000000050c; CR=4; XER=0
-#8: divdeu.: 0x000000001234fedc0000000000000000 / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=4; XER=0
-#9: divdeu.: 0xabcd87651234fedc0000000000000000 / 0x00000000a123b893 = 0x0000000000000000; CR=2; XER=0
-#10: divdeu.: 0x000123456789abdc0000000000000000 / 0x0000000000000000 = 0x0000000000000000; CR=2; XER=0
-#11: divdeu.: 0x00000000000000000000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=2; XER=0
-#12: divdeu.: 0x00000000000000770000000000000000 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=4; XER=0
-
-
-#0: divdeuo: 0x00000000000000040000000000000000 / 0xfffffffffffffffc = 0x0000000000000004; CR=0; XER=0
-#1: divdeuo: 0x00000000000000040000000000000000 / 0xfffffffffffffffd = 0x0000000000000004; CR=0; XER=0
-#2: divdeuo: 0x00000000000000040000000000000000 / 0x0000000000000004 = 0x0000000000000000; CR=0; XER=c0000000
-#3: divdeuo: 0x00000000000000040000000000000000 / 0xfffffffffffffffb = 0x0000000000000004; CR=0; XER=0
-#4: divdeuo: 0x00000000000000030000000000000000 / 0x0000000000000008 = 0x6000000000000000; CR=0; XER=0
-#5: divdeuo: 0x80000000000000000000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=0; XER=c0000000
-#6: divdeuo: 0x000000000000050c0000000000000000 / 0xffffffffffffffff = 0x000000000000050c; CR=0; XER=0
-#7: divdeuo: 0x000000000000050c0000000000000000 / 0xfffffffffffff000 = 0x000000000000050c; CR=0; XER=0
-#8: divdeuo: 0x000000001234fedc0000000000000000 / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=0; XER=0
-#9: divdeuo: 0xabcd87651234fedc0000000000000000 / 0x00000000a123b893 = 0x0000000000000000; CR=0; XER=c0000000
-#10: divdeuo: 0x000123456789abdc0000000000000000 / 0x0000000000000000 = 0x0000000000000000; CR=0; XER=c0000000
-#11: divdeuo: 0x00000000000000000000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=0; XER=0
-#12: divdeuo: 0x00000000000000770000000000000000 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=0; XER=0
-
-#0: divdeuo.: 0x00000000000000040000000000000000 / 0xfffffffffffffffc = 0x0000000000000004; CR=4; XER=0
-#1: divdeuo.: 0x00000000000000040000000000000000 / 0xfffffffffffffffd = 0x0000000000000004; CR=4; XER=0
-#2: divdeuo.: 0x00000000000000040000000000000000 / 0x0000000000000004 = 0x0000000000000000; CR=3; XER=c0000000
-#3: divdeuo.: 0x00000000000000040000000000000000 / 0xfffffffffffffffb = 0x0000000000000004; CR=4; XER=0
-#4: divdeuo.: 0x00000000000000030000000000000000 / 0x0000000000000008 = 0x6000000000000000; CR=4; XER=0
-#5: divdeuo.: 0x80000000000000000000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=3; XER=c0000000
-#6: divdeuo.: 0x000000000000050c0000000000000000 / 0xffffffffffffffff = 0x000000000000050c; CR=4; XER=0
-#7: divdeuo.: 0x000000000000050c0000000000000000 / 0xfffffffffffff000 = 0x000000000000050c; CR=4; XER=0
-#8: divdeuo.: 0x000000001234fedc0000000000000000 / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=4; XER=0
-#9: divdeuo.: 0xabcd87651234fedc0000000000000000 / 0x00000000a123b893 = 0x0000000000000000; CR=3; XER=c0000000
-#10: divdeuo.: 0x000123456789abdc0000000000000000 / 0x0000000000000000 = 0x0000000000000000; CR=3; XER=c0000000
-#11: divdeuo.: 0x00000000000000000000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=2; XER=0
-#12: divdeuo.: 0x00000000000000770000000000000000 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=4; XER=0
-
-
-#0: divwe: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=0; XER=0
-#1: divwe: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=0; XER=0
-#2: divwe: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=0; XER=0
-#3: divwe: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=0; XER=0
-#4: divwe: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=0; XER=0
-#5: divwe: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=0; XER=0
-
-#0: divwe.: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=2; XER=0
-#1: divwe.: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=2; XER=0
-#2: divwe.: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=2; XER=0
-#3: divwe.: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=2; XER=0
-#4: divwe.: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=2; XER=0
-#5: divwe.: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=4; XER=0
-
-
-#0: divweo: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=0; XER=0
-#1: divweo: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=0; XER=c0000000
-#2: divweo: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=0; XER=c0000000
-#3: divweo: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=0; XER=c0000000
-#4: divweo: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=0; XER=c0000000
-#5: divweo: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=0; XER=0
-
-#0: divweo.: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=2; XER=0
-#1: divweo.: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=3; XER=c0000000
-#2: divweo.: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=3; XER=c0000000
-#3: divweo.: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=3; XER=c0000000
-#4: divweo.: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=3; XER=c0000000
-#5: divweo.: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=4; XER=0
-
-
Test ftsqrt instruction
ftsqrt: 3fd8000000000000 ? 8 (CRx)
ftsqrt: 404f000000000000 ? 8 (CRx)
diff --git a/none/tests/ppc64/test_isa_2_06_part3.vgtest b/none/tests/ppc64/test_isa_2_06_part3.vgtest
index e4ccfee..843fc16 100644
--- a/none/tests/ppc64/test_isa_2_06_part3.vgtest
+++ b/none/tests/ppc64/test_isa_2_06_part3.vgtest
@@ -1,2 +1,2 @@
prereq: ../../../tests/check_ppc64_auxv_cap arch_2_06
-prog: test_isa_2_06_part3
+prog: test_isa_2_06_part3 -o
diff --git a/none/tests/ppc64/test_isa_3_0.c b/none/tests/ppc64/test_isa_3_0.c
index 5f5cd18..6e4e7dc 100644
--- a/none/tests/ppc64/test_isa_3_0.c
+++ b/none/tests/ppc64/test_isa_3_0.c
@@ -5,8 +5,8 @@
/*
* test_isa_3_0.c:
- * Copyright (c) 2016 Carl Love <cel@us.ibm.com>
- * Copyright (c) 2016 Will Schmidt <will_schmidt@vnet.ibm.com>
+ * Copyright (C) 2016-2017 Carl Love <cel@us.ibm.com>
+ * Copyright (C) 2016-2017 Will Schmidt <will_schmidt@vnet.ibm.com>
*
* This testfile contains tests for the ISA 3.0 instructions.
* The framework of this test file was based on the framework
@@ -147,6 +147,7 @@
*/
unsigned long local_cr;
unsigned long local_fpscr;
+unsigned long local_xer;
volatile unsigned int cr_value;
/* global for holding the DFP values */
@@ -178,6 +179,7 @@
volatile int x_index;
/* global variable, used to pass shift info down to the test functions.*/
+/* Also used to control DRM,RM values for mffs* functions. */
volatile int x_shift;
/* groups of instruction tests, calling individual tests */
@@ -217,6 +219,7 @@
PPC_MISC = 0x00080000,
PPC_NO_OP = 0x00090000,
PPC_PC_IMMEDIATE = 0x000A0000,
+ PPC_MFFS = 0x000B0000,
PPC_FAMILY_MASK = 0x000F0000,
/* Flags: these may be combined, so use separate bit-fields. */
@@ -272,12 +275,18 @@
__asm__ __volatile__ ("modud 17, 14, 15");
}
+static void test_addex(void) {
+ /* addex RT,RA,RB,CY # at the time of this writing, only CY=0 is valid. CY values of 1,2,3 are reserved. */
+ __asm__ __volatile__ ("addex %0, %1, %2, 0" : "=r" (r17) : "r" (r14), "r" (r15) );
+}
+
static test_list_t testgroup_ia_ops_two[] = {
- { &test_modsw, "modsw" },
- { &test_moduw, "moduw" },
- { &test_modsd, "modsd" },
- { &test_modud, "modud" },
- { NULL , NULL },
+ { &test_modsw, "modsw" },
+ { &test_moduw, "moduw" },
+ { &test_modsd, "modsd" },
+ { &test_modud, "modud" },
+ //{ &test_addex, "addex" },
+ { NULL , NULL },
};
static void test_dotted_extswsli (void)
@@ -492,9 +501,15 @@
__asm__ __volatile__ ("vpermr %0, %1, %2, %3 " : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb), "v" (vec_xc));
}
+static void test_vmsumudm(void)
+{ /* vector multiply-sum unsigned byte modulo. */
+ __asm__ __volatile__ ("vmsumudm %0, %1, %2, %3 " : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb), "v" (vec_xc));
+}
+
/* vector, 3->1 unique; four arguments. xt, xa, xb, xc (xc = permute) */
static test_list_t testgroup_vector_four[] = {
- { &test_vpermr, "vpermr" },
+ { &test_vpermr, "vpermr" },
+ // { &test_vmsumudm, "vmsumudm" },
{ NULL , NULL },
};
@@ -1138,7 +1153,7 @@
SET_FPSCR_ZERO \
SET_CR_ZERO \
__asm__ __volatile__ \
- ("xscmpexpdp %0, %1, %2"::"i"(x), "v"(vec_xa), "v"(vec_xb));\
+ ("xscmpexpdp %0, %1, %2"::"i"(x), "wa"(vec_xa), "wa"(vec_xb));\
GET_CR(local_cr); \
GET_FPSCR(local_fpscr);
@@ -2069,6 +2084,99 @@
{ NULL , NULL },
};
+/* Move From FPSCR variants:
+ * Move From FpScr [ &
+ * Clear Enables |
+ * Lightweight |
+ * Control [&
+ * set DRN [ Immediate] |
+ * set RN [ Immediate ] ]]
+ */
+/* mffs FRT # Move From FPSCR*/
+static void test_mffs (void) {
+ __asm__ __volatile__ ("mffs %0" : "=f"(f14) );
+ GET_FPSCR(local_fpscr);
+}
+
+/* mffsce FRT # Move From FPSCR and Clear Enables */
+static void test_mffsce (void) {
+ __asm__ __volatile__ ("mffsce %0" : "=f"(f14) );
+ GET_FPSCR(local_fpscr);
+}
+
+/* mffscdrn FRT,FRB # Move From FpScr and Control &set DRN */
+static void test_mffscdrn (void) {
+ __asm__ __volatile__ ("mffscdrn %0,%1" : "=f"(f14): "f"(f15) );
+ GET_FPSCR(local_fpscr);
+}
+
+/* mffscdrni FRT,DRM # Move From FpScr & Control &set DRN Immediate*/
+static void test_mffscdrni (void) {
+ switch(x_shift) {
+ default:
+ case 0:
+ __asm__ __volatile__ ("mffscdrni %0,0" : "=f"(f14) );
+ GET_FPSCR(local_fpscr);
+ break;
+ case 1:
+ __asm__ __volatile__ ("mffscdrni %0,1" : "=f"(f14) );
+ GET_FPSCR(local_fpscr);
+ break;
+ case 2:
+ __asm__ __volatile__ ("mffscdrni %0,2" : "=f"(f14) );
+ GET_FPSCR(local_fpscr);
+ break;
+ }
+}
+
+/* mffscrn FRT,FRB # Move From FpScr and Control &set RN*/
+static void test_mffscrn (void) {
+ __asm__ __volatile__ ("mffscrn %0,%1" : "=f"(f14):"f"(f15));
+ GET_FPSCR(local_fpscr);
+}
+
+/* mffscrni FRT,RM # Move from FpScr and Control &set RN Immediate*/
+static void test_mffscrni (void) {
+ switch(x_shift) {
+ case 0:
+ __asm__ __volatile__ ("mffscrni %0,0" : "=f"(f14) );
+ GET_FPSCR(local_fpscr);
+ break;
+ case 1:
+ __asm__ __volatile__ ("mffscrni %0,1" : "=f"(f14) );
+ GET_FPSCR(local_fpscr);
+ break;
+ case 2:
+ __asm__ __volatile__ ("mffscrni %0,2" : "=f"(f14) );
+ GET_FPSCR(local_fpscr);
+ break;
+ }
+}
+
+/* mffsl FRT # Move From FpScr Lightweight */
+static void test_mffsl (void) {
+ __asm__ __volatile__ ("mffsl %0" : "=f"(f14) );
+ GET_FPSCR(local_fpscr);
+}
+
+/* mffs* instructions using FRT only. */
+/* Note to self - Watch DRM,RM fields. */
+static test_list_t testgroup_mffs_misc[] = {
+ // { &test_mffsce, "mffsce" },
+ // { &test_mffsl, "mffsl" },
+ { &test_mffs, "mffs" },
+ { NULL , NULL },
+};
+
+/* mffs* instructions using FRT,FRB. */
+static test_list_t testgroup_mffs_misc_one[] = {
+ // { &test_mffscdrni, "mffscdrni" },
+ // { &test_mffscdrn, "mffscdrn" },
+ // { &test_mffscrni, "mffscrni" },
+ // { &test_mffscrn, "mffscrn" },
+ { NULL , NULL },
+};
+
/* ###### begin all_tests table. */
@@ -2227,9 +2335,22 @@
"ppc addpc_misc",
PPC_PC_IMMEDIATE,
},
+ {
+ testgroup_mffs_misc,
+ "ppc mffpscr",
+ PPC_MFFS,
+ },
+ {
+ testgroup_mffs_misc_one,
+ "ppc mffpscr",
+ PPC_MFFS,
+ },
{ NULL, NULL, 0x00000000, },
};
+#define instruction_touches_xer(instruction_name) \
+ (strncmp(instruction_name, "addex", 5) == 0)
+
static void testfunction_int_two_args (const char* instruction_name,
test_func_t func,
unsigned int test_flags)
@@ -2249,12 +2370,17 @@
SET_CR_ZERO;
(*func)();
GET_CR(cr);
+ GET_XER(local_xer);
res = r17;
- printf("%s %016lx, %016lx => %016lx (%08x)\n",
+ printf("%s %016lx, %016lx => %016lx (%08x)",
instruction_name, (long unsigned)iargs[i],
(long unsigned)iargs[j], (long unsigned)res,
cr);
+ if (instruction_touches_xer(instruction_name)) {
+ dissect_xer(local_xer);
+ }
+ printf("\n");
}
if (verbose) printf("\n");
}
@@ -3601,7 +3727,82 @@
printf(" %016x ", x_index);
printf(" => ");
(*test_function)();
- printf(" %016lx\n", r14);
+ /* printf(" %016lx\n", r14); */
+ printf(" %016x\n", 0); /* test is not portable just print zero */
+ }
+}
+
+/* Identify those mffs* variants that take additional arguments.
+ * This includes the immediate mffs*i variants. */
+#define is_not_simple_mffs_instruction(instruction_name) \
+ ( (strncmp(instruction_name,"mffscdrn",8)==0) || \
+ (strncmp(instruction_name,"mffscrn",7)==0) )
+
+/* Because some of the mffs* variants here are updating the fpscr as part
+ * of the read, be sure to dissect both the retrieved (f14) and the updated
+ * (local_fpscr) fpscr values. */
+static void testfunction_mffs(const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags)
+{
+ union reg_t {
+ unsigned long int uli;
+ double dble;
+ } f14_reg, f15_reg;
+
+ /*This function uses global variable x_shift */
+ VERBOSE_FUNCTION_CALLOUT
+
+ if (is_not_simple_mffs_instruction(instruction_name)) {
+ /* iterate x_shift across values used for RN,RM */
+ for (x_shift = 0; x_shift < 3; x_shift++) {
+ printf("%s ", instruction_name);
+ /* make sure bits in f14 get cleared so we can
+ see correct resulg*/
+ f14_reg.uli = 0x3FFFFFFFFUL;
+
+ if (strcmp("mffscdrn", instruction_name) == 0) {
+ /* instruction uses input reg f15 as input for DRN field */
+ f15_reg.uli = (unsigned long int)x_shift << 32;
+ printf(" f15 0X%lx ", f15_reg.uli);
+
+ /* Setup input register value */
+ f15 = f15_reg.dble;
+
+ } else if (strcmp("mffscrn", instruction_name) == 0) {
+ /* instruction uses input reg f15 as input for RN field */
+ f15_reg.uli = (unsigned long int)x_shift;
+ printf(" f15 0X%lx ", f15_reg.uli);
+
+ /* Setup input register value */
+ f15 = f15_reg.dble;
+
+ } else {
+ printf(" %x ", x_shift);
+ }
+
+
+ (*test_function)();
+ printf(" => ");
+ f14_reg.dble = f14;
+ printf(" 0X%lx\n", f14_reg.uli);
+ printf(" fpscr: f14 ");
+ dissect_fpscr(f14);
+ printf(" local_fpscr: ");
+ dissect_fpscr(local_fpscr);
+ printf("\n");
+ }
+ } else {
+ printf("%s ", instruction_name);
+ printf(" => ");
+ (*test_function)();
+ printf(" %016f\n", f14);
+ printf(" fpscr: f14 ");
+ dissect_fpscr(f14);
+ printf("\n");
+ printf(" local_fpscr: ");
+ dissect_fpscr(local_fpscr);
+ printf("\n");
}
}
@@ -3610,7 +3811,7 @@
unsigned int one_arg, two_args, three_args, four_args, cmp_args, ld_args, st_args,
one_imed_args;
unsigned int arith, logical, compare, popcnt, ldst, insert_extract, permute, round;
- unsigned int integer, altivec, altivec_quad, altivec_double, dfp, bcd, misc,
+ unsigned int integer, altivec, altivec_quad, altivec_double, dfp, bcd, misc, mffs,
no_op, pc_immediate;
unsigned int cr;
} insn_sel_flags_t;
@@ -3639,6 +3840,12 @@
dissect_fpscr_rounding_mode(0x0000000000000001);
dissect_fpscr_rounding_mode(0x0000000000000000);
printf("\n");
+ printf("XER bits: (64)");
+ dissect_xer(0xffffffffffffffff);
+ printf("\n");
+ printf("XER bits: (32)");
+ dissect_xer(0xffffffff);
+ printf("\n\n");
}
for (i=0; all_tests[i].name != NULL; i++) {
@@ -3674,6 +3881,7 @@
if (family == PPC_BCD && seln_flags.bcd == 0) continue;
if (family == PPC_NO_OP && seln_flags.no_op == 0) continue;
if (family == PPC_MISC && seln_flags.misc == 0) continue;
+ if (family == PPC_MFFS && seln_flags.mffs == 0) continue;
if (family == PPC_ALTIVEC_DOUBLE && seln_flags.altivec_double == 0)
continue;
@@ -3693,6 +3901,10 @@
/* Select the test group */
switch (family) {
+ case PPC_MFFS:
+ group_function = &testfunction_mffs;
+ break;
+
case PPC_INTEGER:
switch(type) {
case PPC_ARITH:
@@ -3952,6 +4164,7 @@
"\t-N: test No Op instructions\n"
"\t-P: test PC Immediate Shifted instructions\n"
"\t-m: test miscellaneous instructions\n"
+ "\t-M: test MFFS instructions\n"
"\t-v: be verbose\n"
"\t-h: display this help and exit\n"
);
@@ -3998,13 +4211,14 @@
flags.dfp = 0;
flags.bcd = 0;
flags.misc = 0;
+ flags.mffs = 0;
flags.no_op = 0;
flags.pc_immediate = 0;
// Flags
flags.cr = 2;
- while ((c = getopt(argc, argv, "ifmadqhvADBNP")) != -1) {
+ while ((c = getopt(argc, argv, "ifmadqhvADBMNP")) != -1) {
switch (c) {
case 'i':
flags.integer = 1;
@@ -4034,6 +4248,10 @@
flags.misc = 1;
break;
+ case 'M':
+ flags.mffs = 1;
+ break;
+
case 'N':
flags.no_op = 1;
break;
diff --git a/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE b/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE
index 63c3c89..c4ad35f 100644
--- a/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE
+++ b/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE
@@ -53316,964 +53316,964 @@
xscmpexpdp 0000000000000000 0000000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
xscmpexpdp 0000000000000000 0000000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
xscmpexpdp 0000000000000000 0000000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0000000000000000 0000000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0000000000000000 0000000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 0000000000000000 0000000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 0000000000000000 0000000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0000000000000000 0000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0000000000000000 0000000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0000000000000000 0000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
xscmpexpdp 0000000000000000 0000000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
xscmpexpdp 0000000000000000 0000000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
xscmpexpdp 0000000000000000 0000000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
xscmpexpdp 0000000000000000 0000000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0000000000000000 0000000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0000000000000000 0000000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 0000000000000000 0000000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 0000000000000000 0000000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0000000000000000 0000000000000000 fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0000000000000000 0000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0000000000000000 0000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0000000000000000 0000000000000000 fff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0000000000000000 0000000000000000 fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0000000000000000 0000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0000000000000000 0000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
xscmpexpdp 00007fffffffffff 0000000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
xscmpexpdp 00007fffffffffff 0000000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
xscmpexpdp 00007fffffffffff 0000000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 0000000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 0000000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 0000000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 0000000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 0000000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 0000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 0000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 0000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 0000000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 0000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 0000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 0000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 0000000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 0000000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 0000000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 0000000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
xscmpexpdp 00007fffffffffff 0000000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
xscmpexpdp 00007fffffffffff 0000000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
xscmpexpdp 00007fffffffffff 0000000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
xscmpexpdp 00007fffffffffff 0000000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 0000000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 0000000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 0000000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 0000000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 0000000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 0000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 0000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 0000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 0000000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 0000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 0000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 0000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 0000000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 0000000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 0000000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 0000000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
xscmpexpdp 00007fffffffffff 00007fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
xscmpexpdp 00007fffffffffff 00007fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
xscmpexpdp 00007fffffffffff 00007fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 00007fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 00007fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 00007fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 00007fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 00007fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
xscmpexpdp 00007fffffffffff 00007fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
xscmpexpdp 00007fffffffffff 00007fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
xscmpexpdp 00007fffffffffff 00007fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 00007fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 00007fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 00007fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 00007fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 00007fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 00007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 00007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 00007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 00007fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 00007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 00007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 00007fffffffffff 00007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
xscmpexpdp 0ff0000000000000 00007fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
xscmpexpdp 0ff0000000000000 00007fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
xscmpexpdp 0ff0000000000000 00007fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 00007fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 00007fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 00007fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 00007fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 00007fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
xscmpexpdp 0ff0000000000000 00007fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
xscmpexpdp 0ff0000000000000 00007fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
xscmpexpdp 0ff0000000000000 00007fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 00007fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 00007fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 00007fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 00007fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 00007fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 00007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 00007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 00007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 00007fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 00007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 00007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 00007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 0ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 0ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 0ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 0000000000000000 0000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp 0ff0000000000000 0ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 0ff0000000000000 0ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 0ff0000000000000 0ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
xscmpexpdp 0ff0000000000000 0ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 0ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 0ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 0ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 0ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 8000000000000000 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp 0ff0000000000000 0ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 0ff0000000000000 0ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 0ff0000000000000 0ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
xscmpexpdp 0ff0000000000000 0ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 0ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 0ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 0ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 0ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 0ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 0ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 0ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff0000000000000 0ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0000000000000000 0000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp 0ff07fffffffffff 0ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8000000000000000 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp 0ff07fffffffffff 0ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 0ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp 7ff0000000000000 0ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 0ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp 7ff0000000000000 0ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0000000000000000 0000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8000000000000000 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0000000000000000 0000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8000000000000000 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0000000000000000 0000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8000000000000000 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0000000000000000 0000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8000000000000000 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
xscmpexpdp 8000000000000000 8000000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
xscmpexpdp 8000000000000000 8000000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
xscmpexpdp 8000000000000000 8000000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 8000000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 8000000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 8000000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 8000000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 8000000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 8000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 8000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 8000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 8000000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 8000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 8000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 8000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8000000000000000 8000000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8000000000000000 8000000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 8000000000000000 8000000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 8000000000000000 8000000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8000000000000000 8000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8000000000000000 8000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 8000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 8000000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8000000000000000 8000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8000000000000000 8000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 8000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
xscmpexpdp 8000000000000000 8000000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
xscmpexpdp 8000000000000000 8000000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
xscmpexpdp 8000000000000000 8000000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
xscmpexpdp 8000000000000000 8000000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 8000000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 8000000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 8000000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 8000000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 8000000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 8000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 8000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 8000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 8000000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 8000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 8000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8000000000000000 8000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8000000000000000 8000000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8000000000000000 8000000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 8000000000000000 8000000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 8000000000000000 8000000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8000000000000000 8000000000000000 fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8000000000000000 8000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 8000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 8000000000000000 fff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8000000000000000 8000000000000000 fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8000000000000000 8000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8000000000000000 8000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
xscmpexpdp 80007fffffffffff 8000000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
xscmpexpdp 80007fffffffffff 8000000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
xscmpexpdp 80007fffffffffff 8000000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 8000000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 8000000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 8000000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 8000000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 8000000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 8000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 8000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 8000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 8000000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 8000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 8000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 8000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 8000000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 8000000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 8000000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 8000000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
xscmpexpdp 80007fffffffffff 8000000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
xscmpexpdp 80007fffffffffff 8000000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
xscmpexpdp 80007fffffffffff 8000000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
xscmpexpdp 80007fffffffffff 8000000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 8000000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 8000000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 8000000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 8000000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 8000000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 8000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 8000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 8000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 8000000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 8000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 8000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 8000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 8000000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 8000000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 8000000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 8000000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
xscmpexpdp 80007fffffffffff 80007fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
xscmpexpdp 80007fffffffffff 80007fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
xscmpexpdp 80007fffffffffff 80007fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 80007fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 80007fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 80007fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 80007fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 80007fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
xscmpexpdp 80007fffffffffff 80007fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
xscmpexpdp 80007fffffffffff 80007fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
xscmpexpdp 80007fffffffffff 80007fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 80007fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 80007fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 80007fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 80007fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 80007fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 80007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 80007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 80007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 80007fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 80007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 80007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 80007fffffffffff 80007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
xscmpexpdp 8ff0000000000000 80007fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
xscmpexpdp 8ff0000000000000 80007fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
xscmpexpdp 8ff0000000000000 80007fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 80007fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 80007fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 80007fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 80007fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 80007fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
xscmpexpdp 8ff0000000000000 80007fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
xscmpexpdp 8ff0000000000000 80007fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
xscmpexpdp 8ff0000000000000 80007fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 80007fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 80007fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 80007fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 80007fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 80007fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 80007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 80007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 80007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 80007fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 80007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 80007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 80007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 8ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 8ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 8ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 0000000000000000 0000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp 8ff0000000000000 8ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 8ff0000000000000 8ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 8ff0000000000000 8ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
xscmpexpdp 8ff0000000000000 8ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 8ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 8ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 8ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 8ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 8000000000000000 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp 8ff0000000000000 8ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 8ff0000000000000 8ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 8ff0000000000000 8ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
xscmpexpdp 8ff0000000000000 8ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 8ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 8ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 8ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 8ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 8ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 8ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 8ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff0000000000000 8ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0000000000000000 0000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp 8ff07fffffffffff 8ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8000000000000000 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp 8ff07fffffffffff 8ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 8ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 8ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 8ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp fff0000000000000 8ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp fff0000000000000 8ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp fff0000000000000 8ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
xscmpexpdp fff0000000000000 8ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 8ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 8ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 8ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 8ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp fff0000000000000 8ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp fff0000000000000 8ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp fff0000000000000 8ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
xscmpexpdp fff0000000000000 8ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 8ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 8ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 8ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 8ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 8ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 8ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 8ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff0000000000000 0000000000000000 0000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 0000000000000000 00007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp fff0000000000000 fff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 8000000000000000 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 8000000000000000 80007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp fff0000000000000 fff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff0000000000000 0000000000000000 0000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 0000000000000000 00007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp fff07fffffffffff fff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 8000000000000000 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 8000000000000000 80007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp fff07fffffffffff fff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff0000000000000 0000000000000000 0000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 0000000000000000 00007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp fff0000000000000 fff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 8000000000000000 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 8000000000000000 80007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp fff0000000000000 fff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff0000000000000 0000000000000000 0000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 0000000000000000 00007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp fff07fffffffffff fff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 8000000000000000 8000000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 8000000000000000 80007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FG+Normalized (GT)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FG+Normalized (GT)
xscmpexpdp fff07fffffffffff fff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
All done. Tested 136 different instructions
ppc vector scalar test data class tests:
@@ -54281,6 +54281,7 @@
xststdcqp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54288,6 +54289,7 @@
xststdcqp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00007fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54295,6 +54297,7 @@
xststdcqp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00007fffffffffff DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54302,6 +54305,7 @@
xststdcqp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00ff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54309,6 +54313,7 @@
xststdcqp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00ff000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54316,6 +54321,7 @@
xststdcqp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00ff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54323,6 +54329,7 @@
xststdcqp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00ff7fffffffffff DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54330,6 +54337,7 @@
xststdcqp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 07ff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54337,6 +54345,7 @@
xststdcqp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 07ff000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54344,6 +54353,7 @@
xststdcqp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 07ff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54351,6 +54361,7 @@
xststdcqp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 07ff7fffffffffff DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54358,6 +54369,7 @@
xststdcqp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54365,6 +54377,7 @@
xststdcqp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 7fff000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54372,6 +54385,7 @@
xststdcqp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54379,6 +54393,7 @@
xststdcqp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 7fff7fffffffffff DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54386,6 +54401,7 @@
xststdcqp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 8000000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54393,6 +54409,7 @@
xststdcqp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 8000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54400,6 +54417,7 @@
xststdcqp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 80007fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54407,6 +54425,7 @@
xststdcqp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 80007fffffffffff DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54414,6 +54433,7 @@
xststdcqp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 80ff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54421,6 +54441,7 @@
xststdcqp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 80ff000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54428,6 +54449,7 @@
xststdcqp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 80ff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54435,6 +54457,7 @@
xststdcqp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 80ff7fffffffffff DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54442,6 +54465,7 @@
xststdcqp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 87ff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54449,6 +54473,7 @@
xststdcqp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 87ff000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54456,6 +54481,7 @@
xststdcqp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 87ff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54463,6 +54489,7 @@
xststdcqp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 87ff7fffffffffff DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54470,6 +54497,7 @@
xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54477,6 +54505,7 @@
xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54484,6 +54513,7 @@
xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -54491,6 +54521,7 @@
xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff7fffffffffff DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
diff --git a/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE b/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE
index 35a4e99..fdc5250 100644
--- a/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE
+++ b/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE
@@ -1720,6 +1720,9590 @@
cmpeqb 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
All done. Tested 17 different instructions
+ppc vector scalar quad:
+Test instruction group [ppc vector scalar quad]
+xsabsqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xsabsqp 0102010201020102 0102030405060708 => 0102010201020102 0102030405060708
+xsabsqp 8899aabbccddeeff 0011223344556677 => 0899aabbccddeeff 0011223344556677
+xsabsqp 7060504030201000 f0e0d0c0b0a09080 => 7060504030201000 f0e0d0c0b0a09080
+xsabsqp 0000100800001010 0000100000001002 => 0000100800001010 0000100000001002
+xsabsqp 0010100800101010 0010100000101002 => 0010100800101010 0010100000101002
+xsabsqp 00001c0800001c10 00001c0000001c02 => 00001c0800001c10 00001c0000001c02
+xsabsqp 00101c0800101c10 00101c0000101c02 => 00101c0800101c10 00101c0000101c02
+xsabsqp 00001f0800001f10 00001f0000001f02 => 00001f0800001f10 00001f0000001f02
+xsabsqp 00101f0800101f10 00101f0000101f02 => 00101f0800101f10 00101f0000101f02
+
+xscvdpqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvdpqp 0102010201020102 0102030405060708 => 3c10201020102010 2000000000000000 FPCC-FG
+xscvdpqp 8899aabbccddeeff 0011223344556677 => bc899aabbccddeef f000000000000000 FPCC-FL
+xscvdpqp 7060504030201000 f0e0d0c0b0a09080 => 4306050403020100 0000000000000000 FPCC-FG
+xscvdpqp 0000100800001010 0000100000001002 => 3bf9008000010100 0000000000000000 FPCC-FG
+xscvdpqp 0010100800101010 0010100000101002 => 3c01010080010101 0000000000000000 FPCC-FG
+xscvdpqp 00001c0800001c10 00001c0000001c02 => 3bf9c0800001c100 0000000000000000 FPCC-FG
+xscvdpqp 00101c0800101c10 00101c0000101c02 => 3c0101c0800101c1 0000000000000000 FPCC-FG
+xscvdpqp 00001f0800001f10 00001f0000001f02 => 3bf9f0800001f100 0000000000000000 FPCC-FG
+xscvdpqp 00101f0800101f10 00101f0000101f02 => 3c0101f0800101f1 0000000000000000 FPCC-FG
+
+xscvqpdp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 8899aabbccddeeff 0011223344556677 => 8000000000000000 0000000000000000 FPRF-C FPCC-FE
+xscvqpdp 7060504030201000 f0e0d0c0b0a09080 => 7ff0000000000000 0000000000000000 FPCC-FG FPCC-FU
+xscvqpdp 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000000 FPCC-FE
+
+xscvqpdpo 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdpo 0102010201020102 0102030405060708 => 0000000000000001 0000000000000000 FPRF-C FPCC-FG
+xscvqpdpo 8899aabbccddeeff 0011223344556677 => 8000000000000001 0000000000000000 FPRF-C FPCC-FL
+xscvqpdpo 7060504030201000 f0e0d0c0b0a09080 => 7fefffffffffffff 0000000000000000 FPCC-FG
+xscvqpdpo 0000100800001010 0000100000001002 => 0000000000000001 0000000000000000 FPRF-C FPCC-FG
+xscvqpdpo 0010100800101010 0010100000101002 => 0000000000000001 0000000000000000 FPRF-C FPCC-FG
+xscvqpdpo 00001c0800001c10 00001c0000001c02 => 0000000000000001 0000000000000000 FPRF-C FPCC-FG
+xscvqpdpo 00101c0800101c10 00101c0000101c02 => 0000000000000001 0000000000000000 FPRF-C FPCC-FG
+xscvqpdpo 00001f0800001f10 00001f0000001f02 => 0000000000000001 0000000000000000 FPRF-C FPCC-FG
+xscvqpdpo 00101f0800101f10 00101f0000101f02 => 0000000000000001 0000000000000000 FPRF-C FPCC-FG
+
+xscvqpsdz 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xscvqpsdz 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000
+xscvqpsdz 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+xscvqpsdz 7060504030201000 f0e0d0c0b0a09080 => 7fffffffffffffff 0000000000000000
+xscvqpsdz 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+xscvqpsdz 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000
+xscvqpsdz 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+xscvqpsdz 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000
+xscvqpsdz 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000
+xscvqpsdz 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000000
+
+xscvqpswz 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xscvqpswz 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000
+xscvqpswz 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+xscvqpswz 7060504030201000 f0e0d0c0b0a09080 => 000000007fffffff 0000000000000000
+xscvqpswz 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+xscvqpswz 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000
+xscvqpswz 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+xscvqpswz 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000
+xscvqpswz 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000
+xscvqpswz 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000000
+
+xscvqpudz 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xscvqpudz 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000
+xscvqpudz 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+xscvqpudz 7060504030201000 f0e0d0c0b0a09080 => ffffffffffffffff 0000000000000000
+xscvqpudz 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+xscvqpudz 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000
+xscvqpudz 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+xscvqpudz 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000
+xscvqpudz 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000
+xscvqpudz 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000000
+
+xscvqpuwz 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xscvqpuwz 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000
+xscvqpuwz 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+xscvqpuwz 7060504030201000 f0e0d0c0b0a09080 => 00000000ffffffff 0000000000000000
+xscvqpuwz 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+xscvqpuwz 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000
+xscvqpuwz 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+xscvqpuwz 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000
+xscvqpuwz 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000
+xscvqpuwz 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000000
+
+xscvsdqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvsdqp 0102010201020102 0102030405060708 => 4037020102010201 0200000000000000 FPCC-FG
+xscvsdqp 8899aabbccddeeff 0011223344556677 => c03ddd995510cc88 4404000000000000 FPCC-FL
+xscvsdqp 7060504030201000 f0e0d0c0b0a09080 => 403dc1814100c080 4000000000000000 FPCC-FG
+xscvsdqp 0000100800001010 0000100000001002 => 402b008000010100 0000000000000000 FPCC-FG
+xscvsdqp 0010100800101010 0010100000101002 => 4033010080010101 0000000000000000 FPCC-FG
+xscvsdqp 00001c0800001c10 00001c0000001c02 => 402bc0800001c100 0000000000000000 FPCC-FG
+xscvsdqp 00101c0800101c10 00101c0000101c02 => 403301c0800101c1 0000000000000000 FPCC-FG
+xscvsdqp 00001f0800001f10 00001f0000001f02 => 402bf0800001f100 0000000000000000 FPCC-FG
+xscvsdqp 00101f0800101f10 00101f0000101f02 => 403301f0800101f1 0000000000000000 FPCC-FG
+
+xscvudqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvudqp 0102010201020102 0102030405060708 => 4037020102010201 0200000000000000 FPCC-FG
+xscvudqp 8899aabbccddeeff 0011223344556677 => 403e1133557799bb ddfe000000000000 FPCC-FG
+xscvudqp 7060504030201000 f0e0d0c0b0a09080 => 403dc1814100c080 4000000000000000 FPCC-FG
+xscvudqp 0000100800001010 0000100000001002 => 402b008000010100 0000000000000000 FPCC-FG
+xscvudqp 0010100800101010 0010100000101002 => 4033010080010101 0000000000000000 FPCC-FG
+xscvudqp 00001c0800001c10 00001c0000001c02 => 402bc0800001c100 0000000000000000 FPCC-FG
+xscvudqp 00101c0800101c10 00101c0000101c02 => 403301c0800101c1 0000000000000000 FPCC-FG
+xscvudqp 00001f0800001f10 00001f0000001f02 => 402bf0800001f100 0000000000000000 FPCC-FG
+xscvudqp 00101f0800101f10 00101f0000101f02 => 403301f0800101f1 0000000000000000 FPCC-FG
+
+xsxexpqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xsxexpqp 0102010201020102 0102030405060708 => 0000000000000102 0000000000000000
+xsxexpqp 8899aabbccddeeff 0011223344556677 => 0000000000000899 0000000000000000
+xsxexpqp 7060504030201000 f0e0d0c0b0a09080 => 0000000000007060 0000000000000000
+xsxexpqp 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+xsxexpqp 0010100800101010 0010100000101002 => 0000000000000010 0000000000000000
+xsxexpqp 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+xsxexpqp 00101c0800101c10 00101c0000101c02 => 0000000000000010 0000000000000000
+xsxexpqp 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000
+xsxexpqp 00101f0800101f10 00101f0000101f02 => 0000000000000010 0000000000000000
+
+xsxsigqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xsxsigqp 0102010201020102 0102030405060708 => 0001010201020102 0102030405060708
+xsxsigqp 8899aabbccddeeff 0011223344556677 => 0001aabbccddeeff 0011223344556677
+xsxsigqp 7060504030201000 f0e0d0c0b0a09080 => 0001504030201000 f0e0d0c0b0a09080
+xsxsigqp 0000100800001010 0000100000001002 => 0000100800001010 0000100000001002
+xsxsigqp 0010100800101010 0010100000101002 => 0001100800101010 0010100000101002
+xsxsigqp 00001c0800001c10 00001c0000001c02 => 00001c0800001c10 00001c0000001c02
+xsxsigqp 00101c0800101c10 00101c0000101c02 => 00011c0800101c10 00101c0000101c02
+xsxsigqp 00001f0800001f10 00001f0000001f02 => 00001f0800001f10 00001f0000001f02
+xsxsigqp 00101f0800101f10 00101f0000101f02 => 00011f0800101f10 00101f0000101f02
+
+xsnegqp 0000000000000000 0000000000000000 => 8000000000000000 0000000000000000
+xsnegqp 0102010201020102 0102030405060708 => 8102010201020102 0102030405060708
+xsnegqp 8899aabbccddeeff 0011223344556677 => 0899aabbccddeeff 0011223344556677
+xsnegqp 7060504030201000 f0e0d0c0b0a09080 => f060504030201000 f0e0d0c0b0a09080
+xsnegqp 0000100800001010 0000100000001002 => 8000100800001010 0000100000001002
+xsnegqp 0010100800101010 0010100000101002 => 8010100800101010 0010100000101002
+xsnegqp 00001c0800001c10 00001c0000001c02 => 80001c0800001c10 00001c0000001c02
+xsnegqp 00101c0800101c10 00101c0000101c02 => 80101c0800101c10 00101c0000101c02
+xsnegqp 00001f0800001f10 00001f0000001f02 => 80001f0800001f10 00001f0000001f02
+xsnegqp 00101f0800101f10 00101f0000101f02 => 80101f0800101f10 00101f0000101f02
+
+xsnabsqp 0000000000000000 0000000000000000 => 8000000000000000 0000000000000000
+xsnabsqp 0102010201020102 0102030405060708 => 8102010201020102 0102030405060708
+xsnabsqp 8899aabbccddeeff 0011223344556677 => 8899aabbccddeeff 0011223344556677
+xsnabsqp 7060504030201000 f0e0d0c0b0a09080 => f060504030201000 f0e0d0c0b0a09080
+xsnabsqp 0000100800001010 0000100000001002 => 8000100800001010 0000100000001002
+xsnabsqp 0010100800101010 0010100000101002 => 8010100800101010 0010100000101002
+xsnabsqp 00001c0800001c10 00001c0000001c02 => 80001c0800001c10 00001c0000001c02
+xsnabsqp 00101c0800101c10 00101c0000101c02 => 80101c0800101c10 00101c0000101c02
+xsnabsqp 00001f0800001f10 00001f0000001f02 => 80001f0800001f10 00001f0000001f02
+xsnabsqp 00101f0800101f10 00101f0000101f02 => 80101f0800101f10 00101f0000101f02
+
+xssqrtqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xssqrtqp 0102010201020102 0102030405060708 => 20806ac0283b4649 8c0632d6a11d770a FPCC-FG
+xssqrtqp 8899aabbccddeeff 0011223344556677 => 7fff800000000000 0000000000000000 FPRF-C FPCC-FU
+xssqrtqp 7060504030201000 f0e0d0c0b0a09080 => 582f9eec10deec2d 14b6d4051d1809ae FPCC-FG
+xssqrtqp 0000100800001010 0000100000001002 => 1ffe003ff8027fc0 23f26525e7dab5d6 FPCC-FG
+xssqrtqp 0010100800101010 0010100000101002 => 20077533cdc68455 038f4ca025c1dc6e FPCC-FG
+xssqrtqp 00001c0800001c10 00001c0000001c02 => 1ffe52d8584d7da4 9620bb68d1dc754f FPCC-FG
+xssqrtqp 00101c0800101c10 00101c0000101c02 => 20077d58512fcec9 1634733d8b112799 FPCC-FG
+xssqrtqp 00001f0800001f10 00001f0000001f02 => 1ffe648437fd2de6 cb7713e7fab3286e FPCC-FG
+xssqrtqp 00101f0800101f10 00101f0000101f02 => 20077f5a870e5f2b c13ab6ba2329d3e0 FPCC-FG
+
+xssqrtqpo 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xssqrtqpo 0102010201020102 0102030405060708 => 20806ac0283b4649 8c0632d6a11d770b FPCC-FG
+xssqrtqpo 8899aabbccddeeff 0011223344556677 => 7fff800000000000 0000000000000000 FPRF-C FPCC-FU
+xssqrtqpo 7060504030201000 f0e0d0c0b0a09080 => 582f9eec10deec2d 14b6d4051d1809af FPCC-FG
+xssqrtqpo 0000100800001010 0000100000001002 => 1ffe003ff8027fc0 23f26525e7dab5d5 FPCC-FG
+xssqrtqpo 0010100800101010 0010100000101002 => 20077533cdc68455 038f4ca025c1dc6f FPCC-FG
+xssqrtqpo 00001c0800001c10 00001c0000001c02 => 1ffe52d8584d7da4 9620bb68d1dc754f FPCC-FG
+xssqrtqpo 00101c0800101c10 00101c0000101c02 => 20077d58512fcec9 1634733d8b112799 FPCC-FG
+xssqrtqpo 00001f0800001f10 00001f0000001f02 => 1ffe648437fd2de6 cb7713e7fab3286f FPCC-FG
+xssqrtqpo 00101f0800101f10 00101f0000101f02 => 20077f5a870e5f2b c13ab6ba2329d3df FPCC-FG
+
+All done. Tested 33 different instructions
+ppc vector scalar compare exponents quads:
+Test instruction group [ppc vector scalar compare exponents quads]
+xscmpexpqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+
+xscmpoqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpoqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpoqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpoqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpoqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpoqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+
+xscmpuqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpuqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpuqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpuqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpuqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpuqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+
+All done. Tested 36 different instructions
+ppc vector scalar rounding quads:
+Test instruction group [ppc vector scalar rounding quads]
+xsrqpi 00000000000000000000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=0) (RMC=2) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=1) (RMC=2) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00007fffffffffff0000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00007fffffffffff0000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00007fffffffffff0000000000000000 (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 00007fffffffffff0000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00007fffffffffff0000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00007fffffffffff0000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00007fffffffffff0000000000000000 (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 00007fffffffffff0000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000007fffffffffff (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000007fffffffffff (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000007fffffffffff (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000000007fffffffffff (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000007fffffffffff (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000007fffffffffff (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000007fffffffffff (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000000007fffffffffff (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff0000000000000000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff0000000000000000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff0000000000000000000000000000 (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 00ff0000000000000000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff0000000000000000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff0000000000000000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff0000000000000000000000000000 (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 00ff0000000000000000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff000000000000 (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000000ff000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff000000000000 (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000000ff000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff7fffffffffff0000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff7fffffffffff0000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff7fffffffffff0000000000000000 (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 00ff7fffffffffff0000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff7fffffffffff0000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff7fffffffffff0000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff7fffffffffff0000000000000000 (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 00ff7fffffffffff0000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff7fffffffffff (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff7fffffffffff (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff7fffffffffff (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000000ff7fffffffffff (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff7fffffffffff (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff7fffffffffff (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff7fffffffffff (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000000ff7fffffffffff (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff0000000000000000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff0000000000000000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff0000000000000000000000000000 (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 07ff0000000000000000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff0000000000000000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff0000000000000000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff0000000000000000000000000000 (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 07ff0000000000000000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff000000000000 (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000007ff000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff000000000000 (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000007ff000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff7fffffffffff0000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff7fffffffffff0000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff7fffffffffff0000000000000000 (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 07ff7fffffffffff0000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff7fffffffffff0000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff7fffffffffff0000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff7fffffffffff0000000000000000 (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 07ff7fffffffffff0000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff7fffffffffff (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff7fffffffffff (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff7fffffffffff (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000007ff7fffffffffff (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff7fffffffffff (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff7fffffffffff (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff7fffffffffff (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000007ff7fffffffffff (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 7fff0000000000000000000000000000 (R=0) (RMC=0) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpi 7fff0000000000000000000000000000 (R=0) (RMC=1) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpi 7fff0000000000000000000000000000 (R=0) (RMC=2) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpi 7fff0000000000000000000000000000 (R=0) (RMC=3) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpi 7fff0000000000000000000000000000 (R=1) (RMC=0) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpi 7fff0000000000000000000000000000 (R=1) (RMC=1) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpi 7fff0000000000000000000000000000 (R=1) (RMC=2) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpi 7fff0000000000000000000000000000 (R=1) (RMC=3) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpi 00000000000000007fff000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000007fff000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
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+xsrqpxp 7fff0000000000000000000000000000 (R=1) (RMC=1) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpxp 7fff0000000000000000000000000000 (R=1) (RMC=2) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpxp 7fff0000000000000000000000000000 (R=1) (RMC=3) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpxp 00000000000000007fff000000000000 (R=0) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff000000000000 (R=0) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff000000000000 (R=0) (RMC=2) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff000000000000 (R=0) (RMC=3) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff000000000000 (R=1) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff000000000000 (R=1) (RMC=1) => 00000000000000007ffe000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff000000000000 (R=1) (RMC=2) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff000000000000 (R=1) (RMC=3) => 00000000000000007ffe000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=0) (RMC=0) => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=0) (RMC=1) => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=0) (RMC=2) => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=0) (RMC=3) => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=1) (RMC=0) => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=1) (RMC=1) => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=1) (RMC=2) => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=1) (RMC=3) => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp 00000000000000007fff7fffffffffff (R=0) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff7fffffffffff (R=0) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff7fffffffffff (R=0) (RMC=2) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff7fffffffffff (R=0) (RMC=3) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff7fffffffffff (R=1) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff7fffffffffff (R=1) (RMC=1) => 00000000000000007ffe000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff7fffffffffff (R=1) (RMC=2) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff7fffffffffff (R=1) (RMC=3) => 00000000000000007ffe000000000000 FPRF-C FPCC-FG
+xsrqpxp 80000000000000000000000000000000 (R=0) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpxp 80000000000000000000000000000000 (R=0) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpxp 80000000000000000000000000000000 (R=0) (RMC=2) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpxp 80000000000000000000000000000000 (R=0) (RMC=3) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpxp 80000000000000000000000000000000 (R=1) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpxp 80000000000000000000000000000000 (R=1) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpxp 80000000000000000000000000000000 (R=1) (RMC=2) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpxp 80000000000000000000000000000000 (R=1) (RMC=3) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpxp 00000000000000008000000000000000 (R=0) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000008000000000000000 (R=0) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000008000000000000000 (R=0) (RMC=2) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000008000000000000000 (R=0) (RMC=3) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000008000000000000000 (R=1) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000008000000000000000 (R=1) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000008000000000000000 (R=1) (RMC=2) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000008000000000000000 (R=1) (RMC=3) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80007fffffffffff0000000000000000 (R=0) (RMC=0) => 80007fffffffffff0000000000000000 FPRF-C FPCC-FL
+xsrqpxp 80007fffffffffff0000000000000000 (R=0) (RMC=1) => 80007fffffffffff0000000000000000 FPRF-C FPCC-FL
+xsrqpxp 80007fffffffffff0000000000000000 (R=0) (RMC=2) => 80007fffffffffff0000000000000000 FPRF-C FPCC-FL
+xsrqpxp 80007fffffffffff0000000000000000 (R=0) (RMC=3) => 80007fffffffffff0000000000000000 FPRF-C FPCC-FL
+xsrqpxp 80007fffffffffff0000000000000000 (R=1) (RMC=0) => 80007fffffffffff0000000000000000 FPRF-C FPCC-FL
+xsrqpxp 80007fffffffffff0000000000000000 (R=1) (RMC=1) => 80007fffffffffff0000000000000000 FPRF-C FPCC-FL
+xsrqpxp 80007fffffffffff0000000000000000 (R=1) (RMC=2) => 80007fffffffffff0000000000000000 FPRF-C FPCC-FL
+xsrqpxp 80007fffffffffff0000000000000000 (R=1) (RMC=3) => 80007fffffffffff0000000000000000 FPRF-C FPCC-FL
+xsrqpxp 000000000000000080007fffffffffff (R=0) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080007fffffffffff (R=0) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080007fffffffffff (R=0) (RMC=2) => 00000000000000008002000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080007fffffffffff (R=0) (RMC=3) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080007fffffffffff (R=1) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080007fffffffffff (R=1) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080007fffffffffff (R=1) (RMC=2) => 00000000000000008002000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080007fffffffffff (R=1) (RMC=3) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80ff0000000000000000000000000000 (R=0) (RMC=0) => 80ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 80ff0000000000000000000000000000 (R=0) (RMC=1) => 80ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 80ff0000000000000000000000000000 (R=0) (RMC=2) => 80ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 80ff0000000000000000000000000000 (R=0) (RMC=3) => 80ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 80ff0000000000000000000000000000 (R=1) (RMC=0) => 80ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 80ff0000000000000000000000000000 (R=1) (RMC=1) => 80ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 80ff0000000000000000000000000000 (R=1) (RMC=2) => 80ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 80ff0000000000000000000000000000 (R=1) (RMC=3) => 80ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 000000000000000080ff000000000000 (R=0) (RMC=0) => 00000000000000008100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff000000000000 (R=0) (RMC=1) => 00000000000000008100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff000000000000 (R=0) (RMC=2) => 00000000000000008100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff000000000000 (R=0) (RMC=3) => 00000000000000008100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff000000000000 (R=1) (RMC=0) => 00000000000000008100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff000000000000 (R=1) (RMC=1) => 000000000000000080fe000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff000000000000 (R=1) (RMC=2) => 00000000000000008100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff000000000000 (R=1) (RMC=3) => 000000000000000080fe000000000000 FPRF-C FPCC-FG
+xsrqpxp 80ff7fffffffffff0000000000000000 (R=0) (RMC=0) => 80ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 80ff7fffffffffff0000000000000000 (R=0) (RMC=1) => 80ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 80ff7fffffffffff0000000000000000 (R=0) (RMC=2) => 80ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 80ff7fffffffffff0000000000000000 (R=0) (RMC=3) => 80ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 80ff7fffffffffff0000000000000000 (R=1) (RMC=0) => 80ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 80ff7fffffffffff0000000000000000 (R=1) (RMC=1) => 80ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 80ff7fffffffffff0000000000000000 (R=1) (RMC=2) => 80ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 80ff7fffffffffff0000000000000000 (R=1) (RMC=3) => 80ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 000000000000000080ff7fffffffffff (R=0) (RMC=0) => 00000000000000008100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff7fffffffffff (R=0) (RMC=1) => 00000000000000008100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff7fffffffffff (R=0) (RMC=2) => 00000000000000008100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff7fffffffffff (R=0) (RMC=3) => 00000000000000008100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff7fffffffffff (R=1) (RMC=0) => 00000000000000008100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff7fffffffffff (R=1) (RMC=1) => 000000000000000080fe000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff7fffffffffff (R=1) (RMC=2) => 00000000000000008100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff7fffffffffff (R=1) (RMC=3) => 000000000000000080fe000000000000 FPRF-C FPCC-FG
+xsrqpxp 87ff0000000000000000000000000000 (R=0) (RMC=0) => 87ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 87ff0000000000000000000000000000 (R=0) (RMC=1) => 87ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 87ff0000000000000000000000000000 (R=0) (RMC=2) => 87ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 87ff0000000000000000000000000000 (R=0) (RMC=3) => 87ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 87ff0000000000000000000000000000 (R=1) (RMC=0) => 87ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 87ff0000000000000000000000000000 (R=1) (RMC=1) => 87ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 87ff0000000000000000000000000000 (R=1) (RMC=2) => 87ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 87ff0000000000000000000000000000 (R=1) (RMC=3) => 87ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 000000000000000087ff000000000000 (R=0) (RMC=0) => 00000000000000008800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff000000000000 (R=0) (RMC=1) => 00000000000000008800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff000000000000 (R=0) (RMC=2) => 00000000000000008800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff000000000000 (R=0) (RMC=3) => 00000000000000008800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff000000000000 (R=1) (RMC=0) => 00000000000000008800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff000000000000 (R=1) (RMC=1) => 000000000000000087fe000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff000000000000 (R=1) (RMC=2) => 00000000000000008800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff000000000000 (R=1) (RMC=3) => 000000000000000087fe000000000000 FPRF-C FPCC-FG
+xsrqpxp 87ff7fffffffffff0000000000000000 (R=0) (RMC=0) => 87ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 87ff7fffffffffff0000000000000000 (R=0) (RMC=1) => 87ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 87ff7fffffffffff0000000000000000 (R=0) (RMC=2) => 87ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 87ff7fffffffffff0000000000000000 (R=0) (RMC=3) => 87ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 87ff7fffffffffff0000000000000000 (R=1) (RMC=0) => 87ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 87ff7fffffffffff0000000000000000 (R=1) (RMC=1) => 87ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 87ff7fffffffffff0000000000000000 (R=1) (RMC=2) => 87ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 87ff7fffffffffff0000000000000000 (R=1) (RMC=3) => 87ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 000000000000000087ff7fffffffffff (R=0) (RMC=0) => 00000000000000008800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff7fffffffffff (R=0) (RMC=1) => 00000000000000008800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff7fffffffffff (R=0) (RMC=2) => 00000000000000008800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff7fffffffffff (R=0) (RMC=3) => 00000000000000008800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff7fffffffffff (R=1) (RMC=0) => 00000000000000008800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff7fffffffffff (R=1) (RMC=1) => 000000000000000087fe000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff7fffffffffff (R=1) (RMC=2) => 00000000000000008800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff7fffffffffff (R=1) (RMC=3) => 000000000000000087fe000000000000 FPRF-C FPCC-FG
+xsrqpxp ffff0000000000000000000000000000 (R=0) (RMC=0) => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsrqpxp ffff0000000000000000000000000000 (R=0) (RMC=1) => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsrqpxp ffff0000000000000000000000000000 (R=0) (RMC=2) => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsrqpxp ffff0000000000000000000000000000 (R=0) (RMC=3) => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsrqpxp ffff0000000000000000000000000000 (R=1) (RMC=0) => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsrqpxp ffff0000000000000000000000000000 (R=1) (RMC=1) => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsrqpxp ffff0000000000000000000000000000 (R=1) (RMC=2) => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsrqpxp ffff0000000000000000000000000000 (R=1) (RMC=3) => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsrqpxp 0000000000000000ffff000000000000 (R=0) (RMC=0) => 00000000000000010000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff000000000000 (R=0) (RMC=1) => 00000000000000010000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff000000000000 (R=0) (RMC=2) => 00000000000000010000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff000000000000 (R=0) (RMC=3) => 00000000000000010000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff000000000000 (R=1) (RMC=0) => 00000000000000010000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff000000000000 (R=1) (RMC=1) => 0000000000000000fffe000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff000000000000 (R=1) (RMC=2) => 00000000000000010000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff000000000000 (R=1) (RMC=3) => 0000000000000000fffe000000000000 FPRF-C FPCC-FG
+xsrqpxp ffff7fffffffffff0000000000000000 (R=0) (RMC=0) => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp ffff7fffffffffff0000000000000000 (R=0) (RMC=1) => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp ffff7fffffffffff0000000000000000 (R=0) (RMC=2) => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp ffff7fffffffffff0000000000000000 (R=0) (RMC=3) => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp ffff7fffffffffff0000000000000000 (R=1) (RMC=0) => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp ffff7fffffffffff0000000000000000 (R=1) (RMC=1) => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp ffff7fffffffffff0000000000000000 (R=1) (RMC=2) => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp ffff7fffffffffff0000000000000000 (R=1) (RMC=3) => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp 0000000000000000ffff7fffffffffff (R=0) (RMC=0) => 00000000000000010000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff7fffffffffff (R=0) (RMC=1) => 00000000000000010000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff7fffffffffff (R=0) (RMC=2) => 00000000000000010000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff7fffffffffff (R=0) (RMC=3) => 00000000000000010000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff7fffffffffff (R=1) (RMC=0) => 00000000000000010000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff7fffffffffff (R=1) (RMC=1) => 0000000000000000fffe000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff7fffffffffff (R=1) (RMC=2) => 00000000000000010000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff7fffffffffff (R=1) (RMC=3) => 0000000000000000fffe000000000000 FPRF-C FPCC-FG
+
+All done. Tested 39 different instructions
ppc vector scalar move to/from:
Test instruction group [ppc vector scalar move to/from]
mfvsrld aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa ffffffffffffffff
@@ -1785,7 +11369,7 @@
mtvsrws 5152535455565758 5152535455565758 0 ffaa5599113377cc => 113377cc113377cc 113377cc113377cc 0 ffaa5599113377cc
mtvsrws 0000000000000000 0000000000000000 0 ffaa5599113377cc => 113377cc113377cc 113377cc113377cc 0 ffaa5599113377cc
-All done. Tested 20 different instructions
+All done. Tested 42 different instructions
ppc dfp significance:
Test instruction group [ppc dfp significance]
dtstsfi significance(0x00) +Finite 0 * 10 ^ -12 (GT) (4)
@@ -1869,56 +11453,56 @@
dtstsfiq significance(0x20) -inf (GT) (4)
dtstsfiq significance(0x30) -inf (GT) (4)
dtstsfiq significance(0x3f) -inf (GT) (4)
-dtstsfiq significance(0x00) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (GT) (4)
-dtstsfiq significance(0x04) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
-dtstsfiq significance(0x08) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
-dtstsfiq significance(0x10) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
-dtstsfiq significance(0x18) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
-dtstsfiq significance(0x20) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
-dtstsfiq significance(0x30) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
-dtstsfiq significance(0x3f) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
-dtstsfiq significance(0x00) +Finite 9437157672933646850861933435956461 * 10 ^ -1691 (GT) (4)
-dtstsfiq significance(0x04) +Finite 9437157672933646850861933435956461 * 10 ^ -1691 (LT) (8)
-dtstsfiq significance(0x08) +Finite 9437157672933646850861933435956461 * 10 ^ -1691 (LT) (8)
-dtstsfiq significance(0x10) +Finite 9437157672933646850861933435956461 * 10 ^ -1691 (LT) (8)
-dtstsfiq significance(0x18) +Finite 9437157672933646850861933435956461 * 10 ^ -1691 (LT) (8)
-dtstsfiq significance(0x20) +Finite 9437157672933646850861933435956461 * 10 ^ -1691 (LT) (8)
-dtstsfiq significance(0x30) +Finite 9437157672933646850861933435956461 * 10 ^ -1691 (LT) (8)
-dtstsfiq significance(0x3f) +Finite 9437157672933646850861933435956461 * 10 ^ -1691 (LT) (8)
-dtstsfiq significance(0x00) +Finite 9607419299315620000000315546911889 * 10 ^ -5795 (GT) (4)
-dtstsfiq significance(0x04) +Finite 9607419299315620000000315546911889 * 10 ^ -5795 (LT) (8)
-dtstsfiq significance(0x08) +Finite 9607419299315620000000315546911889 * 10 ^ -5795 (LT) (8)
-dtstsfiq significance(0x10) +Finite 9607419299315620000000315546911889 * 10 ^ -5795 (LT) (8)
-dtstsfiq significance(0x18) +Finite 9607419299315620000000315546911889 * 10 ^ -5795 (LT) (8)
-dtstsfiq significance(0x20) +Finite 9607419299315620000000315546911889 * 10 ^ -5795 (GT) (4)
-dtstsfiq significance(0x30) +Finite 9607419299315620000000315546911889 * 10 ^ -5795 (GT) (4)
-dtstsfiq significance(0x3f) +Finite 9607419299315620000000315546911889 * 10 ^ -5795 (GT) (4)
-dtstsfiq significance(0x00) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (GT) (4)
-dtstsfiq significance(0x04) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
-dtstsfiq significance(0x08) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
-dtstsfiq significance(0x10) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
-dtstsfiq significance(0x18) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
-dtstsfiq significance(0x20) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
-dtstsfiq significance(0x30) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
-dtstsfiq significance(0x3f) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
-dtstsfiq significance(0x00) +Finite 9437157672933645758274305445956461 * 10 ^ -1691 (GT) (4)
-dtstsfiq significance(0x04) +Finite 9437157672933645758274305445956461 * 10 ^ -1691 (LT) (8)
-dtstsfiq significance(0x08) +Finite 9437157672933645758274305445956461 * 10 ^ -1691 (LT) (8)
-dtstsfiq significance(0x10) +Finite 9437157672933645758274305445956461 * 10 ^ -1691 (LT) (8)
-dtstsfiq significance(0x18) +Finite 9437157672933645758274305445956461 * 10 ^ -1691 (LT) (8)
-dtstsfiq significance(0x20) +Finite 9437157672933645758274305445956461 * 10 ^ -1691 (LT) (8)
-dtstsfiq significance(0x30) +Finite 9437157672933645758274305445956461 * 10 ^ -1691 (LT) (8)
-dtstsfiq significance(0x3f) +Finite 9437157672933645758274305445956461 * 10 ^ -1691 (LT) (8)
-dtstsfiq significance(0x00) +Finite 007950661331436195475319647159274 * 10 ^ -6176 (GT) (4)
-dtstsfiq significance(0x04) +Finite 007950661331436195475319647159274 * 10 ^ -6176 (LT) (8)
-dtstsfiq significance(0x08) +Finite 007950661331436195475319647159274 * 10 ^ -6176 (LT) (8)
-dtstsfiq significance(0x10) +Finite 007950661331436195475319647159274 * 10 ^ -6176 (LT) (8)
-dtstsfiq significance(0x18) +Finite 007950661331436195475319647159274 * 10 ^ -6176 (LT) (8)
-dtstsfiq significance(0x20) +Finite 007950661331436195475319647159274 * 10 ^ -6176 (LT) (8)
-dtstsfiq significance(0x30) +Finite 007950661331436195475319647159274 * 10 ^ -6176 (LT) (8)
-dtstsfiq significance(0x3f) +Finite 007950661331436195475319647159274 * 10 ^ -6176 (LT) (8)
+dtstsfiq significance(0x00) +Finite 8656913073315646094063873566794274 * 10 ^ -2663 (GT) (4)
+dtstsfiq significance(0x04) +Finite 8656913073315646094063873566794274 * 10 ^ -2663 (LT) (8)
+dtstsfiq significance(0x08) +Finite 8656913073315646094063873566794274 * 10 ^ -2663 (LT) (8)
+dtstsfiq significance(0x10) +Finite 8656913073315646094063873566794274 * 10 ^ -2663 (LT) (8)
+dtstsfiq significance(0x18) +Finite 8656913073315646094063873566794274 * 10 ^ -2663 (LT) (8)
+dtstsfiq significance(0x20) +Finite 8656913073315646094063873566794274 * 10 ^ -2663 (LT) (8)
+dtstsfiq significance(0x30) +Finite 8656913073315646094063873566794274 * 10 ^ -2663 (LT) (8)
+dtstsfiq significance(0x3f) +Finite 8656913073315646094063873566794274 * 10 ^ -2663 (LT) (8)
+dtstsfiq significance(0x00) +Finite 8606695663873620000000000000000065 * 10 ^ 4453 (GT) (4)
+dtstsfiq significance(0x04) +Finite 8606695663873620000000000000000065 * 10 ^ 4453 (LT) (8)
+dtstsfiq significance(0x08) +Finite 8606695663873620000000000000000065 * 10 ^ 4453 (LT) (8)
+dtstsfiq significance(0x10) +Finite 8606695663873620000000000000000065 * 10 ^ 4453 (LT) (8)
+dtstsfiq significance(0x18) +Finite 8606695663873620000000000000000065 * 10 ^ 4453 (GT) (4)
+dtstsfiq significance(0x20) +Finite 8606695663873620000000000000000065 * 10 ^ 4453 (GT) (4)
+dtstsfiq significance(0x30) +Finite 8606695663873620000000000000000065 * 10 ^ 4453 (GT) (4)
+dtstsfiq significance(0x3f) +Finite 8606695663873620000000000000000065 * 10 ^ 4453 (GT) (4)
+dtstsfiq significance(0x00) +Finite 9376291069355425798073359377218889 * 10 ^ -1671 (GT) (4)
+dtstsfiq significance(0x04) +Finite 9376291069355425798073359377218889 * 10 ^ -1671 (LT) (8)
+dtstsfiq significance(0x08) +Finite 9376291069355425798073359377218889 * 10 ^ -1671 (LT) (8)
+dtstsfiq significance(0x10) +Finite 9376291069355425798073359377218889 * 10 ^ -1671 (LT) (8)
+dtstsfiq significance(0x18) +Finite 9376291069355425798073359377218889 * 10 ^ -1671 (LT) (8)
+dtstsfiq significance(0x20) +Finite 9376291069355425798073359377218889 * 10 ^ -1671 (LT) (8)
+dtstsfiq significance(0x30) +Finite 9376291069355425798073359377218889 * 10 ^ -1671 (LT) (8)
+dtstsfiq significance(0x3f) +Finite 9376291069355425798073359377218889 * 10 ^ -1671 (LT) (8)
+dtstsfiq significance(0x00) +Finite 636295062305646458499311546855262 * 10 ^ -6175 (GT) (4)
+dtstsfiq significance(0x04) +Finite 636295062305646458499311546855262 * 10 ^ -6175 (LT) (8)
+dtstsfiq significance(0x08) +Finite 636295062305646458499311546855262 * 10 ^ -6175 (LT) (8)
+dtstsfiq significance(0x10) +Finite 636295062305646458499311546855262 * 10 ^ -6175 (LT) (8)
+dtstsfiq significance(0x18) +Finite 636295062305646458499311546855262 * 10 ^ -6175 (LT) (8)
+dtstsfiq significance(0x20) +Finite 636295062305646458499311546855262 * 10 ^ -6175 (LT) (8)
+dtstsfiq significance(0x30) +Finite 636295062305646458499311546855262 * 10 ^ -6175 (LT) (8)
+dtstsfiq significance(0x3f) +Finite 636295062305646458499311546855262 * 10 ^ -6175 (LT) (8)
+dtstsfiq significance(0x00) +Finite 7623098272305560000000351416795066 * 10 ^ 5312 (GT) (4)
+dtstsfiq significance(0x04) +Finite 7623098272305560000000351416795066 * 10 ^ 5312 (LT) (8)
+dtstsfiq significance(0x08) +Finite 7623098272305560000000351416795066 * 10 ^ 5312 (LT) (8)
+dtstsfiq significance(0x10) +Finite 7623098272305560000000351416795066 * 10 ^ 5312 (LT) (8)
+dtstsfiq significance(0x18) +Finite 7623098272305560000000351416795066 * 10 ^ 5312 (LT) (8)
+dtstsfiq significance(0x20) +Finite 7623098272305560000000351416795066 * 10 ^ 5312 (GT) (4)
+dtstsfiq significance(0x30) +Finite 7623098272305560000000351416795066 * 10 ^ 5312 (GT) (4)
+dtstsfiq significance(0x3f) +Finite 7623098272305560000000351416795066 * 10 ^ 5312 (GT) (4)
+dtstsfiq significance(0x00) +Finite 8376291069355426317634159717118888 * 10 ^ -663 (GT) (4)
+dtstsfiq significance(0x04) +Finite 8376291069355426317634159717118888 * 10 ^ -663 (LT) (8)
+dtstsfiq significance(0x08) +Finite 8376291069355426317634159717118888 * 10 ^ -663 (LT) (8)
+dtstsfiq significance(0x10) +Finite 8376291069355426317634159717118888 * 10 ^ -663 (LT) (8)
+dtstsfiq significance(0x18) +Finite 8376291069355426317634159717118888 * 10 ^ -663 (LT) (8)
+dtstsfiq significance(0x20) +Finite 8376291069355426317634159717118888 * 10 ^ -663 (LT) (8)
+dtstsfiq significance(0x30) +Finite 8376291069355426317634159717118888 * 10 ^ -663 (LT) (8)
+dtstsfiq significance(0x3f) +Finite 8376291069355426317634159717118888 * 10 ^ -663 (LT) (8)
-All done. Tested 22 different instructions
+All done. Tested 44 different instructions
ppc bcd misc:
Test instruction group [ppc bcd misc]
bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
@@ -33394,46 +42978,56 @@
bcdcfsq. p1 xa:000000000000000c 0000000000000000 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:000000305419901f 0000000000000000(+|0)
-All done. Tested 51 different instructions
+All done. Tested 73 different instructions
ppc noop misc:
Test instruction group [ppc noop misc]
wait =>
-All done. Tested 52 different instructions
+All done. Tested 74 different instructions
ppc addpc_misc:
Test instruction group [ppc addpc_misc]
-addpcis 0000000000000000 => 0000000010003de4
-addpcis 0000000000000001 => 0000000010013dec
-addpcis 0000000000000002 => 0000000010023df4
-addpcis 0000000000000003 => 0000000010403dfc
-addpcis 0000000000000004 => 0000000018003e04
-addpcis 0000000000000005 => 0000000030003e0c
-addpcis 0000000000000006 => 000000008fff3e14
-addpcis 0000000000000007 => ffffffff90003e1c
-addpcis 0000000000000008 => 0000000010003e24
-addpcis 0000000000000009 => 000000000fff3e2c
-addpcis 000000000000000a => 000000000ffe3e34
-addpcis 000000000000000b => 000000000fc03e3c
-addpcis 000000000000000c => 0000000008003e44
-addpcis 000000000000000d => fffffffff0003e4c
-addpcis 000000000000000e => ffffffff90013e54
-addpcis 000000000000000f => ffffffff90003e5c
+addpcis 0000000000000000 => 0000000000000000
+addpcis 0000000000000001 => 0000000000000000
+addpcis 0000000000000002 => 0000000000000000
+addpcis 0000000000000003 => 0000000000000000
+addpcis 0000000000000004 => 0000000000000000
+addpcis 0000000000000005 => 0000000000000000
+addpcis 0000000000000006 => 0000000000000000
+addpcis 0000000000000007 => 0000000000000000
+addpcis 0000000000000008 => 0000000000000000
+addpcis 0000000000000009 => 0000000000000000
+addpcis 000000000000000a => 0000000000000000
+addpcis 000000000000000b => 0000000000000000
+addpcis 000000000000000c => 0000000000000000
+addpcis 000000000000000d => 0000000000000000
+addpcis 000000000000000e => 0000000000000000
+addpcis 000000000000000f => 0000000000000000
-subpcis 0000000000000000 => 0000000010003ee8
-subpcis 0000000000000001 => 000000000fff3ef0
-subpcis 0000000000000002 => 000000000ffe3ef8
-subpcis 0000000000000003 => 000000000fc03f00
-subpcis 0000000000000004 => 0000000008003f08
-subpcis 0000000000000005 => fffffffff0003f10
-subpcis 0000000000000006 => ffffffff90013f18
-subpcis 0000000000000007 => ffffffff90003f20
-subpcis 0000000000000008 => 0000000010003f28
-subpcis 0000000000000009 => 0000000010013f30
-subpcis 000000000000000a => 0000000010023f38
-subpcis 000000000000000b => 0000000010403f40
-subpcis 000000000000000c => 0000000010803f48
-subpcis 000000000000000d => 0000000012003f50
-subpcis 000000000000000e => 000000008fff3f58
-subpcis 000000000000000f => ffffffff90003f60
+subpcis 0000000000000000 => 0000000000000000
+subpcis 0000000000000001 => 0000000000000000
+subpcis 0000000000000002 => 0000000000000000
+subpcis 0000000000000003 => 0000000000000000
+subpcis 0000000000000004 => 0000000000000000
+subpcis 0000000000000005 => 0000000000000000
+subpcis 0000000000000006 => 0000000000000000
+subpcis 0000000000000007 => 0000000000000000
+subpcis 0000000000000008 => 0000000000000000
+subpcis 0000000000000009 => 0000000000000000
+subpcis 000000000000000a => 0000000000000000
+subpcis 000000000000000b => 0000000000000000
+subpcis 000000000000000c => 0000000000000000
+subpcis 000000000000000d => 0000000000000000
+subpcis 000000000000000e => 0000000000000000
+subpcis 000000000000000f => 0000000000000000
-All done. Tested 54 different instructions
+All done. Tested 76 different instructions
+ppc mffpscr:
+Test instruction group [ppc mffpscr]
+mffs => 000000000.000000
+ fpscr: f14
+ local_fpscr: FPRF-C FPCC-FL
+
+All done. Tested 77 different instructions
+ppc mffpscr:
+Test instruction group [ppc mffpscr]
+All done. Tested 77 different instructions
diff --git a/none/tests/ppc64/test_isa_3_0_other.vgtest b/none/tests/ppc64/test_isa_3_0_other.vgtest
index 817f7ef..4aea573 100644
--- a/none/tests/ppc64/test_isa_3_0_other.vgtest
+++ b/none/tests/ppc64/test_isa_3_0_other.vgtest
@@ -1,2 +1,2 @@
prereq: ../../../tests/check_ppc64_auxv_cap arch_3_00
-prog: test_isa_3_0 -i -m -D -B -N -P
+prog: test_isa_3_0 -i -m -D -B -N -P -M
diff --git a/none/tests/pth_2sig.c b/none/tests/pth_2sig.c
new file mode 100644
index 0000000..56e6904
--- /dev/null
+++ b/none/tests/pth_2sig.c
@@ -0,0 +1,42 @@
+#include <pthread.h>
+#include <signal.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include <sys/wait.h>
+
+void *slavethread(void *arg)
+{
+ while (1)
+ pause();
+}
+
+int main(int argc, char **argv)
+{
+ int i;
+ for (i = 0; i < 10; i++) {
+ pthread_t slave;
+ if (pthread_create(&slave, 0, slavethread, 0)) {
+ perror("pthread_create");
+ exit(2);
+ }
+ }
+
+ pid_t pid = getpid();
+ switch (fork()) {
+ case 0: // child
+ sleep(2); // Should be enough to ensure (some) threads are created
+ for (i = 0; i < 20 && kill(pid, SIGTERM) == 0; i++)
+ ;
+ exit(0);
+ case -1:
+ perror("fork");
+ exit(4);
+ }
+
+ while (1)
+ pause();
+ fprintf(stderr, "strange, this program is supposed to be killed!\n");
+ return 1;
+}
diff --git a/none/tests/pth_2sig.stderr.exp-linux b/none/tests/pth_2sig.stderr.exp-linux
new file mode 100644
index 0000000..e45928c
--- /dev/null
+++ b/none/tests/pth_2sig.stderr.exp-linux
@@ -0,0 +1 @@
+Terminated
diff --git a/none/tests/pth_2sig.stderr.exp-solaris b/none/tests/pth_2sig.stderr.exp-solaris
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/pth_2sig.stderr.exp-solaris
diff --git a/none/tests/pth_2sig.vgtest b/none/tests/pth_2sig.vgtest
new file mode 100644
index 0000000..b7c2b14
--- /dev/null
+++ b/none/tests/pth_2sig.vgtest
@@ -0,0 +1,2 @@
+prog: pth_2sig
+vgopts: -q
diff --git a/none/tests/s390x/Makefile.in b/none/tests/s390x/Makefile.in
index ee07464..fc2675d 100644
--- a/none/tests/s390x/Makefile.in
+++ b/none/tests/s390x/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -707,6 +707,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -877,6 +878,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -887,6 +889,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -961,8 +964,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -1007,7 +1008,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/none/tests/s390x/op_exception.c b/none/tests/s390x/op_exception.c
index 35c8602..f8dcb9d 100644
--- a/none/tests/s390x/op_exception.c
+++ b/none/tests/s390x/op_exception.c
@@ -2,7 +2,7 @@
suppressing. That means that the program check old psw will point to
the instruction after the illegal one (according to the calculated length).
There are some programs out there that use this mechanism to detect available
-intruction (sigh).
+instruction (sigh).
This patch checks, that valgrind makes forard progress. */
#include <signal.h>
#include <stdio.h>
diff --git a/none/tests/scripts/Makefile.in b/none/tests/scripts/Makefile.in
index eece669..63fd277 100644
--- a/none/tests/scripts/Makefile.in
+++ b/none/tests/scripts/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -199,6 +199,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -369,6 +370,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -379,6 +381,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -453,8 +456,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -499,7 +500,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/none/tests/sigsusp.c b/none/tests/sigsusp.c
new file mode 100644
index 0000000..0977e26
--- /dev/null
+++ b/none/tests/sigsusp.c
@@ -0,0 +1,24 @@
+#include <stdlib.h>
+#include <pthread.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <signal.h>
+static void* t_fn(void* v)
+{
+ sigset_t mask;
+
+ sigfillset(&mask);
+ sigsuspend(&mask);
+ return NULL;
+}
+
+int main (int argc, char *argv[])
+{
+ pthread_t t1;
+
+ pthread_create(&t1, NULL, t_fn, NULL);
+
+ sleep(1); // Should be enough to have the thread in sigsuspend
+ // printf("dying\n");
+ exit(0);
+}
diff --git a/none/tests/sigsusp.stderr.exp b/none/tests/sigsusp.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/sigsusp.stderr.exp
diff --git a/none/tests/sigsusp.vgtest b/none/tests/sigsusp.vgtest
new file mode 100644
index 0000000..4b3931d
--- /dev/null
+++ b/none/tests/sigsusp.vgtest
@@ -0,0 +1,2 @@
+prog: sigsusp
+vgopts: -q
diff --git a/none/tests/solaris/Makefile.in b/none/tests/solaris/Makefile.in
index 859f548..6cbcd90 100644
--- a/none/tests/solaris/Makefile.in
+++ b/none/tests/solaris/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -331,6 +331,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -501,6 +502,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -511,6 +513,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -585,8 +588,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -631,7 +632,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/none/tests/tilegx/Makefile.am b/none/tests/tilegx/Makefile.am
deleted file mode 100644
index e779ce6..0000000
--- a/none/tests/tilegx/Makefile.am
+++ /dev/null
@@ -1,1617 +0,0 @@
-
-include $(top_srcdir)/Makefile.tool-tests.am
-
-dist_noinst_SCRIPTS = \
- filter_stderr
-
-EXTRA_DIST = gen_test.sh
-
-if VGCONF_ARCHS_INCLUDE_TILEGX
-EXTRA_DIST += \
- insn_test_move_X0.stdout.exp insn_test_move_X0.stderr.exp \
- insn_test_move_X0.vgtest \
- insn_test_move_X1.stdout.exp insn_test_move_X1.stderr.exp \
- insn_test_move_X1.vgtest \
- insn_test_move_Y0.stdout.exp insn_test_move_Y0.stderr.exp \
- insn_test_move_Y0.vgtest \
- insn_test_move_Y1.stdout.exp insn_test_move_Y1.stderr.exp \
- insn_test_move_Y1.vgtest \
- insn_test_movei_X0.stdout.exp insn_test_movei_X0.stderr.exp \
- insn_test_movei_X0.vgtest \
- insn_test_movei_X1.stdout.exp insn_test_movei_X1.stderr.exp \
- insn_test_movei_X1.vgtest \
- insn_test_movei_Y0.stdout.exp insn_test_movei_Y0.stderr.exp \
- insn_test_movei_Y0.vgtest \
- insn_test_movei_Y1.stdout.exp insn_test_movei_Y1.stderr.exp \
- insn_test_movei_Y1.vgtest \
- insn_test_moveli_X0.stdout.exp insn_test_moveli_X0.stderr.exp \
- insn_test_moveli_X0.vgtest \
- insn_test_moveli_X1.stdout.exp insn_test_moveli_X1.stderr.exp \
- insn_test_moveli_X1.vgtest \
- insn_test_prefetch_X1.stdout.exp insn_test_prefetch_X1.stderr.exp \
- insn_test_prefetch_X1.vgtest \
- insn_test_prefetch_Y2.stdout.exp insn_test_prefetch_Y2.stderr.exp \
- insn_test_prefetch_Y2.vgtest \
- insn_test_prefetch_l1_X1.stdout.exp \
- insn_test_prefetch_l1_X1.stderr.exp \
- insn_test_prefetch_l1_X1.vgtest \
- insn_test_prefetch_l1_Y2.stdout.exp \
- insn_test_prefetch_l1_Y2.stderr.exp \
- insn_test_prefetch_l1_Y2.vgtest \
- insn_test_prefetch_l2_X1.stdout.exp \
- insn_test_prefetch_l2_X1.stderr.exp \
- insn_test_prefetch_l2_X1.vgtest \
- insn_test_prefetch_l2_Y2.stdout.exp \
- insn_test_prefetch_l2_Y2.stderr.exp \
- insn_test_prefetch_l2_Y2.vgtest \
- insn_test_prefetch_l3_X1.stdout.exp \
- insn_test_prefetch_l3_X1.stderr.exp \
- insn_test_prefetch_l3_X1.vgtest \
- insn_test_prefetch_l3_Y2.stdout.exp \
- insn_test_prefetch_l3_Y2.stderr.exp \
- insn_test_prefetch_l3_Y2.vgtest \
- insn_test_add_X0.stdout.exp insn_test_add_X0.stderr.exp \
- insn_test_add_X0.vgtest \
- insn_test_add_X1.stdout.exp insn_test_add_X1.stderr.exp \
- insn_test_add_X1.vgtest \
- insn_test_add_Y0.stdout.exp insn_test_add_Y0.stderr.exp \
- insn_test_add_Y0.vgtest \
- insn_test_add_Y1.stdout.exp insn_test_add_Y1.stderr.exp \
- insn_test_add_Y1.vgtest \
- insn_test_addi_X0.stdout.exp insn_test_addi_X0.stderr.exp \
- insn_test_addi_X0.vgtest \
- insn_test_addi_X1.stdout.exp insn_test_addi_X1.stderr.exp \
- insn_test_addi_X1.vgtest \
- insn_test_addi_Y0.stdout.exp insn_test_addi_Y0.stderr.exp \
- insn_test_addi_Y0.vgtest \
- insn_test_addi_Y1.stdout.exp insn_test_addi_Y1.stderr.exp \
- insn_test_addi_Y1.vgtest \
- insn_test_addli_X0.stdout.exp insn_test_addli_X0.stderr.exp \
- insn_test_addli_X0.vgtest \
- insn_test_addli_X1.stdout.exp insn_test_addli_X1.stderr.exp \
- insn_test_addli_X1.vgtest \
- insn_test_addx_X0.stdout.exp insn_test_addx_X0.stderr.exp \
- insn_test_addx_X0.vgtest \
- insn_test_addx_X1.stdout.exp insn_test_addx_X1.stderr.exp \
- insn_test_addx_X1.vgtest \
- insn_test_addx_Y0.stdout.exp insn_test_addx_Y0.stderr.exp \
- insn_test_addx_Y0.vgtest \
- insn_test_addx_Y1.stdout.exp insn_test_addx_Y1.stderr.exp \
- insn_test_addx_Y1.vgtest \
- insn_test_addxi_X0.stdout.exp insn_test_addxi_X0.stderr.exp \
- insn_test_addxi_X0.vgtest \
- insn_test_addxi_X1.stdout.exp insn_test_addxi_X1.stderr.exp \
- insn_test_addxi_X1.vgtest \
- insn_test_addxi_Y0.stdout.exp insn_test_addxi_Y0.stderr.exp \
- insn_test_addxi_Y0.vgtest \
- insn_test_addxi_Y1.stdout.exp insn_test_addxi_Y1.stderr.exp \
- insn_test_addxi_Y1.vgtest \
- insn_test_addxli_X0.stdout.exp insn_test_addxli_X0.stderr.exp \
- insn_test_addxli_X0.vgtest \
- insn_test_addxli_X1.stdout.exp insn_test_addxli_X1.stderr.exp \
- insn_test_addxli_X1.vgtest \
- insn_test_addxsc_X0.stdout.exp insn_test_addxsc_X0.stderr.exp \
- insn_test_addxsc_X0.vgtest \
- insn_test_addxsc_X1.stdout.exp insn_test_addxsc_X1.stderr.exp \
- insn_test_addxsc_X1.vgtest \
- insn_test_and_X0.stdout.exp insn_test_and_X0.stderr.exp \
- insn_test_and_X0.vgtest \
- insn_test_and_X1.stdout.exp insn_test_and_X1.stderr.exp \
- insn_test_and_X1.vgtest \
- insn_test_and_Y0.stdout.exp insn_test_and_Y0.stderr.exp \
- insn_test_and_Y0.vgtest \
- insn_test_and_Y1.stdout.exp insn_test_and_Y1.stderr.exp \
- insn_test_and_Y1.vgtest \
- insn_test_andi_X0.stdout.exp insn_test_andi_X0.stderr.exp \
- insn_test_andi_X0.vgtest \
- insn_test_andi_X1.stdout.exp insn_test_andi_X1.stderr.exp \
- insn_test_andi_X1.vgtest \
- insn_test_andi_Y0.stdout.exp insn_test_andi_Y0.stderr.exp \
- insn_test_andi_Y0.vgtest \
- insn_test_andi_Y1.stdout.exp insn_test_andi_Y1.stderr.exp \
- insn_test_andi_Y1.vgtest \
- insn_test_beqz_X1.stdout.exp insn_test_beqz_X1.stderr.exp \
- insn_test_beqz_X1.vgtest \
- insn_test_beqzt_X1.stdout.exp insn_test_beqzt_X1.stderr.exp \
- insn_test_beqzt_X1.vgtest \
- insn_test_bfexts_X0.stdout.exp insn_test_bfexts_X0.stderr.exp \
- insn_test_bfexts_X0.vgtest \
- insn_test_bfextu_X0.stdout.exp insn_test_bfextu_X0.stderr.exp \
- insn_test_bfextu_X0.vgtest \
- insn_test_bfins_X0.stdout.exp insn_test_bfins_X0.stderr.exp \
- insn_test_bfins_X0.vgtest \
- insn_test_bgez_X1.stdout.exp insn_test_bgez_X1.stderr.exp \
- insn_test_bgez_X1.vgtest \
- insn_test_bgezt_X1.stdout.exp insn_test_bgezt_X1.stderr.exp \
- insn_test_bgezt_X1.vgtest \
- insn_test_bgtz_X1.stdout.exp insn_test_bgtz_X1.stderr.exp \
- insn_test_bgtz_X1.vgtest \
- insn_test_bgtzt_X1.stdout.exp insn_test_bgtzt_X1.stderr.exp \
- insn_test_bgtzt_X1.vgtest \
- insn_test_blbc_X1.stdout.exp insn_test_blbc_X1.stderr.exp \
- insn_test_blbc_X1.vgtest \
- insn_test_blbct_X1.stdout.exp insn_test_blbct_X1.stderr.exp \
- insn_test_blbct_X1.vgtest \
- insn_test_blbs_X1.stdout.exp insn_test_blbs_X1.stderr.exp \
- insn_test_blbs_X1.vgtest \
- insn_test_blbst_X1.stdout.exp insn_test_blbst_X1.stderr.exp \
- insn_test_blbst_X1.vgtest \
- insn_test_blez_X1.stdout.exp insn_test_blez_X1.stderr.exp \
- insn_test_blez_X1.vgtest \
- insn_test_blezt_X1.stdout.exp insn_test_blezt_X1.stderr.exp \
- insn_test_blezt_X1.vgtest \
- insn_test_bltz_X1.stdout.exp insn_test_bltz_X1.stderr.exp \
- insn_test_bltz_X1.vgtest \
- insn_test_bltzt_X1.stdout.exp insn_test_bltzt_X1.stderr.exp \
- insn_test_bltzt_X1.vgtest \
- insn_test_bnez_X1.stdout.exp insn_test_bnez_X1.stderr.exp \
- insn_test_bnez_X1.vgtest \
- insn_test_bnezt_X1.stdout.exp insn_test_bnezt_X1.stderr.exp \
- insn_test_bnezt_X1.vgtest \
- insn_test_clz_X0.stdout.exp insn_test_clz_X0.stderr.exp \
- insn_test_clz_X0.vgtest \
- insn_test_clz_Y0.stdout.exp insn_test_clz_Y0.stderr.exp \
- insn_test_clz_Y0.vgtest \
- insn_test_cmoveqz_X0.stdout.exp insn_test_cmoveqz_X0.stderr.exp \
- insn_test_cmoveqz_X0.vgtest \
- insn_test_cmoveqz_Y0.stdout.exp insn_test_cmoveqz_Y0.stderr.exp \
- insn_test_cmoveqz_Y0.vgtest \
- insn_test_cmovnez_X0.stdout.exp insn_test_cmovnez_X0.stderr.exp \
- insn_test_cmovnez_X0.vgtest \
- insn_test_cmovnez_Y0.stdout.exp insn_test_cmovnez_Y0.stderr.exp \
- insn_test_cmovnez_Y0.vgtest \
- insn_test_cmpeq_X0.stdout.exp insn_test_cmpeq_X0.stderr.exp \
- insn_test_cmpeq_X0.vgtest \
- insn_test_cmpeq_X1.stdout.exp insn_test_cmpeq_X1.stderr.exp \
- insn_test_cmpeq_X1.vgtest \
- insn_test_cmpeq_Y0.stdout.exp insn_test_cmpeq_Y0.stderr.exp \
- insn_test_cmpeq_Y0.vgtest \
- insn_test_cmpeq_Y1.stdout.exp insn_test_cmpeq_Y1.stderr.exp \
- insn_test_cmpeq_Y1.vgtest \
- insn_test_cmpeqi_X0.stdout.exp insn_test_cmpeqi_X0.stderr.exp \
- insn_test_cmpeqi_X0.vgtest \
- insn_test_cmpeqi_X1.stdout.exp insn_test_cmpeqi_X1.stderr.exp \
- insn_test_cmpeqi_X1.vgtest \
- insn_test_cmpeqi_Y0.stdout.exp insn_test_cmpeqi_Y0.stderr.exp \
- insn_test_cmpeqi_Y0.vgtest \
- insn_test_cmpeqi_Y1.stdout.exp insn_test_cmpeqi_Y1.stderr.exp \
- insn_test_cmpeqi_Y1.vgtest \
- insn_test_cmples_X0.stdout.exp insn_test_cmples_X0.stderr.exp \
- insn_test_cmples_X0.vgtest \
- insn_test_cmples_X1.stdout.exp insn_test_cmples_X1.stderr.exp \
- insn_test_cmples_X1.vgtest \
- insn_test_cmples_Y0.stdout.exp insn_test_cmples_Y0.stderr.exp \
- insn_test_cmples_Y0.vgtest \
- insn_test_cmples_Y1.stdout.exp insn_test_cmples_Y1.stderr.exp \
- insn_test_cmples_Y1.vgtest \
- insn_test_cmpleu_X0.stdout.exp insn_test_cmpleu_X0.stderr.exp \
- insn_test_cmpleu_X0.vgtest \
- insn_test_cmpleu_X1.stdout.exp insn_test_cmpleu_X1.stderr.exp \
- insn_test_cmpleu_X1.vgtest \
- insn_test_cmpleu_Y0.stdout.exp insn_test_cmpleu_Y0.stderr.exp \
- insn_test_cmpleu_Y0.vgtest \
- insn_test_cmpleu_Y1.stdout.exp insn_test_cmpleu_Y1.stderr.exp \
- insn_test_cmpleu_Y1.vgtest \
- insn_test_cmplts_X0.stdout.exp insn_test_cmplts_X0.stderr.exp \
- insn_test_cmplts_X0.vgtest \
- insn_test_cmplts_X1.stdout.exp insn_test_cmplts_X1.stderr.exp \
- insn_test_cmplts_X1.vgtest \
- insn_test_cmplts_Y0.stdout.exp insn_test_cmplts_Y0.stderr.exp \
- insn_test_cmplts_Y0.vgtest \
- insn_test_cmplts_Y1.stdout.exp insn_test_cmplts_Y1.stderr.exp \
- insn_test_cmplts_Y1.vgtest \
- insn_test_cmpltsi_X0.stdout.exp insn_test_cmpltsi_X0.stderr.exp \
- insn_test_cmpltsi_X0.vgtest \
- insn_test_cmpltsi_X1.stdout.exp insn_test_cmpltsi_X1.stderr.exp \
- insn_test_cmpltsi_X1.vgtest \
- insn_test_cmpltsi_Y0.stdout.exp insn_test_cmpltsi_Y0.stderr.exp \
- insn_test_cmpltsi_Y0.vgtest \
- insn_test_cmpltsi_Y1.stdout.exp insn_test_cmpltsi_Y1.stderr.exp \
- insn_test_cmpltsi_Y1.vgtest \
- insn_test_cmpltu_X0.stdout.exp insn_test_cmpltu_X0.stderr.exp \
- insn_test_cmpltu_X0.vgtest \
- insn_test_cmpltu_X1.stdout.exp insn_test_cmpltu_X1.stderr.exp \
- insn_test_cmpltu_X1.vgtest \
- insn_test_cmpltu_Y0.stdout.exp insn_test_cmpltu_Y0.stderr.exp \
- insn_test_cmpltu_Y0.vgtest \
- insn_test_cmpltu_Y1.stdout.exp insn_test_cmpltu_Y1.stderr.exp \
- insn_test_cmpltu_Y1.vgtest \
- insn_test_cmpltui_X0.stdout.exp insn_test_cmpltui_X0.stderr.exp \
- insn_test_cmpltui_X0.vgtest \
- insn_test_cmpltui_X1.stdout.exp insn_test_cmpltui_X1.stderr.exp \
- insn_test_cmpltui_X1.vgtest \
- insn_test_cmpne_X0.stdout.exp insn_test_cmpne_X0.stderr.exp \
- insn_test_cmpne_X0.vgtest \
- insn_test_cmpne_X1.stdout.exp insn_test_cmpne_X1.stderr.exp \
- insn_test_cmpne_X1.vgtest \
- insn_test_cmpne_Y0.stdout.exp insn_test_cmpne_Y0.stderr.exp \
- insn_test_cmpne_Y0.vgtest \
- insn_test_cmpne_Y1.stdout.exp insn_test_cmpne_Y1.stderr.exp \
- insn_test_cmpne_Y1.vgtest \
- insn_test_cmul_X0.stdout.exp insn_test_cmul_X0.stderr.exp \
- insn_test_cmul_X0.vgtest \
- insn_test_cmula_X0.stdout.exp insn_test_cmula_X0.stderr.exp \
- insn_test_cmula_X0.vgtest \
- insn_test_cmulaf_X0.stdout.exp insn_test_cmulaf_X0.stderr.exp \
- insn_test_cmulaf_X0.vgtest \
- insn_test_cmulf_X0.stdout.exp insn_test_cmulf_X0.stderr.exp \
- insn_test_cmulf_X0.vgtest \
- insn_test_cmulfr_X0.stdout.exp insn_test_cmulfr_X0.stderr.exp \
- insn_test_cmulfr_X0.vgtest \
- insn_test_cmulh_X0.stdout.exp insn_test_cmulh_X0.stderr.exp \
- insn_test_cmulh_X0.vgtest \
- insn_test_cmulhr_X0.stdout.exp insn_test_cmulhr_X0.stderr.exp \
- insn_test_cmulhr_X0.vgtest \
- insn_test_crc32_32_X0.stdout.exp insn_test_crc32_32_X0.stderr.exp \
- insn_test_crc32_32_X0.vgtest \
- insn_test_crc32_8_X0.stdout.exp insn_test_crc32_8_X0.stderr.exp \
- insn_test_crc32_8_X0.vgtest \
- insn_test_ctz_X0.stdout.exp insn_test_ctz_X0.stderr.exp \
- insn_test_ctz_X0.vgtest \
- insn_test_ctz_Y0.stdout.exp insn_test_ctz_Y0.stderr.exp \
- insn_test_ctz_Y0.vgtest \
- insn_test_dblalign_X0.stdout.exp insn_test_dblalign_X0.stderr.exp \
- insn_test_dblalign_X0.vgtest \
- insn_test_dblalign2_X0.stdout.exp insn_test_dblalign2_X0.stderr.exp \
- insn_test_dblalign2_X0.vgtest \
- insn_test_dblalign2_X1.stdout.exp insn_test_dblalign2_X1.stderr.exp \
- insn_test_dblalign2_X1.vgtest \
- insn_test_dblalign4_X0.stdout.exp insn_test_dblalign4_X0.stderr.exp \
- insn_test_dblalign4_X0.vgtest \
- insn_test_dblalign4_X1.stdout.exp insn_test_dblalign4_X1.stderr.exp \
- insn_test_dblalign4_X1.vgtest \
- insn_test_dblalign6_X0.stdout.exp insn_test_dblalign6_X0.stderr.exp \
- insn_test_dblalign6_X0.vgtest \
- insn_test_dblalign6_X1.stdout.exp insn_test_dblalign6_X1.stderr.exp \
- insn_test_dblalign6_X1.vgtest \
- insn_test_dtlbpr_X1.stdout.exp insn_test_dtlbpr_X1.stderr.exp \
- insn_test_dtlbpr_X1.vgtest \
- insn_test_fdouble_add_flags_X0.stdout.exp \
- insn_test_fdouble_add_flags_X0.stderr.exp \
- insn_test_fdouble_add_flags_X0.vgtest \
- insn_test_fdouble_addsub_X0.stdout.exp \
- insn_test_fdouble_addsub_X0.stderr.exp \
- insn_test_fdouble_addsub_X0.vgtest \
- insn_test_fdouble_mul_flags_X0.stdout.exp \
- insn_test_fdouble_mul_flags_X0.stderr.exp \
- insn_test_fdouble_mul_flags_X0.vgtest \
- insn_test_fdouble_pack1_X0.stdout.exp \
- insn_test_fdouble_pack1_X0.stderr.exp \
- insn_test_fdouble_pack1_X0.vgtest \
- insn_test_fdouble_pack2_X0.stdout.exp \
- insn_test_fdouble_pack2_X0.stderr.exp \
- insn_test_fdouble_pack2_X0.vgtest \
- insn_test_fdouble_sub_flags_X0.stdout.exp \
- insn_test_fdouble_sub_flags_X0.stderr.exp \
- insn_test_fdouble_sub_flags_X0.vgtest \
- insn_test_fdouble_unpack_max_X0.stdout.exp \
- insn_test_fdouble_unpack_max_X0.stderr.exp \
- insn_test_fdouble_unpack_max_X0.vgtest \
- insn_test_fdouble_unpack_min_X0.stdout.exp \
- insn_test_fdouble_unpack_min_X0.stderr.exp \
- insn_test_fdouble_unpack_min_X0.vgtest \
- insn_test_flushwb_X1.stdout.exp insn_test_flushwb_X1.stderr.exp \
- insn_test_flushwb_X1.vgtest \
- insn_test_fnop_X0.stdout.exp insn_test_fnop_X0.stderr.exp \
- insn_test_fnop_X0.vgtest \
- insn_test_fnop_X1.stdout.exp insn_test_fnop_X1.stderr.exp \
- insn_test_fnop_X1.vgtest \
- insn_test_fnop_Y0.stdout.exp insn_test_fnop_Y0.stderr.exp \
- insn_test_fnop_Y0.vgtest \
- insn_test_fnop_Y1.stdout.exp insn_test_fnop_Y1.stderr.exp \
- insn_test_fnop_Y1.vgtest \
- insn_test_fsingle_add1_X0.stdout.exp \
- insn_test_fsingle_add1_X0.stderr.exp \
- insn_test_fsingle_add1_X0.vgtest \
- insn_test_fsingle_addsub2_X0.stdout.exp \
- insn_test_fsingle_addsub2_X0.stderr.exp \
- insn_test_fsingle_addsub2_X0.vgtest \
- insn_test_fsingle_mul1_X0.stdout.exp \
- insn_test_fsingle_mul1_X0.stderr.exp \
- insn_test_fsingle_mul1_X0.vgtest \
- insn_test_fsingle_mul2_X0.stdout.exp \
- insn_test_fsingle_mul2_X0.stderr.exp \
- insn_test_fsingle_mul2_X0.vgtest \
- insn_test_fsingle_pack1_X0.stdout.exp \
- insn_test_fsingle_pack1_X0.stderr.exp \
- insn_test_fsingle_pack1_X0.vgtest \
- insn_test_fsingle_pack1_Y0.stdout.exp \
- insn_test_fsingle_pack1_Y0.stderr.exp \
- insn_test_fsingle_pack1_Y0.vgtest \
- insn_test_fsingle_pack2_X0.stdout.exp \
- insn_test_fsingle_pack2_X0.stderr.exp \
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- insn_test_fsingle_sub1_X0.vgtest \
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- insn_test_icoh_X1.vgtest \
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- insn_test_j_X1.vgtest \
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- insn_test_jal_X1.vgtest \
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- insn_test_jalr_X1.vgtest \
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- insn_test_jalr_Y1.vgtest \
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- insn_test_jalrp_X1.vgtest \
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- insn_test_jalrp_Y1.vgtest \
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- insn_test_jr_X1.vgtest \
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- insn_test_jr_Y1.vgtest \
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- insn_test_jrp_X1.vgtest \
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- insn_test_ld_X1.vgtest \
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- insn_test_ld_Y2.vgtest \
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- insn_test_ld1s_Y2.vgtest \
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- insn_test_ld1s_add_X1.vgtest \
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- insn_test_ld1u_X1.vgtest \
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- insn_test_ld1u_Y2.vgtest \
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- insn_test_ld1u_add_X1.vgtest \
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- insn_test_ld2s_X1.vgtest \
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- insn_test_ld2s_Y2.vgtest \
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- insn_test_ld2u_X1.vgtest \
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- insn_test_ld2u_Y2.vgtest \
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- insn_test_ld4s_X1.vgtest \
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- insn_test_ld4s_add_X1.vgtest \
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- insn_test_ld4u_X1.vgtest \
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- insn_test_ld4u_Y2.vgtest \
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- insn_test_ld4u_add_X1.vgtest \
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- insn_test_ld_add_X1.vgtest \
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- insn_test_ldna_X1.vgtest \
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- insn_test_ldna_add_X1.vgtest \
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- insn_test_ldnt1s_X1.vgtest \
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- insn_test_ldnt1s_add_X1.vgtest \
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- insn_test_ldnt1u_X1.vgtest \
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- insn_test_ldnt1u_add_X1.vgtest \
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- insn_test_ldnt2s_X1.vgtest \
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- insn_test_ldnt2s_add_X1.vgtest \
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- insn_test_ldnt2u_add_X1.vgtest \
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- insn_test_ldnt4u_add_X1.vgtest \
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- insn_test_ldnt_add_X1.vgtest \
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- insn_test_mm_X0.vgtest \
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- insn_test_mnz_Y1.vgtest \
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- insn_test_mul_hs_hu_X0.vgtest \
- insn_test_mul_hs_ls_X0.stdout.exp insn_test_mul_hs_ls_X0.stderr.exp \
- insn_test_mul_hs_ls_X0.vgtest \
- insn_test_mul_hs_lu_X0.stdout.exp insn_test_mul_hs_lu_X0.stderr.exp \
- insn_test_mul_hs_lu_X0.vgtest \
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- insn_test_mul_hu_hu_X0.vgtest \
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- insn_test_mul_hu_lu_X0.vgtest \
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- insn_test_mul_ls_ls_X0.vgtest \
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- insn_test_mul_ls_ls_Y0.vgtest \
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- insn_test_mul_ls_lu_X0.vgtest \
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- insn_test_mul_lu_lu_X0.vgtest \
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- insn_test_mul_lu_lu_Y0.vgtest \
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- insn_test_mula_hs_hs_X0.vgtest \
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- insn_test_mula_hu_lu_X0.vgtest \
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- insn_test_mula_ls_ls_X0.vgtest \
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- insn_test_mula_ls_ls_Y0.vgtest \
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- insn_test_mula_ls_lu_X0.vgtest \
- insn_test_mula_lu_lu_X0.stdout.exp insn_test_mula_lu_lu_X0.stderr.exp \
- insn_test_mula_lu_lu_X0.vgtest \
- insn_test_mula_lu_lu_Y0.stdout.exp insn_test_mula_lu_lu_Y0.stderr.exp \
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- insn_test_v2maxs_X0.stdout.exp insn_test_v2maxs_X0.stderr.exp \
- insn_test_v2maxs_X0.vgtest \
- insn_test_v2maxs_X1.stdout.exp insn_test_v2maxs_X1.stderr.exp \
- insn_test_v2maxs_X1.vgtest \
- insn_test_v2mins_X0.stdout.exp insn_test_v2mins_X0.stderr.exp \
- insn_test_v2mins_X0.vgtest \
- insn_test_v2mins_X1.stdout.exp insn_test_v2mins_X1.stderr.exp \
- insn_test_v2mins_X1.vgtest \
- insn_test_v2mnz_X0.stdout.exp insn_test_v2mnz_X0.stderr.exp \
- insn_test_v2mnz_X0.vgtest \
- insn_test_v2mnz_X1.stdout.exp insn_test_v2mnz_X1.stderr.exp \
- insn_test_v2mnz_X1.vgtest \
- insn_test_v2mulfsc_X0.stdout.exp insn_test_v2mulfsc_X0.stderr.exp \
- insn_test_v2mulfsc_X0.vgtest \
- insn_test_v2muls_X0.stdout.exp insn_test_v2muls_X0.stderr.exp \
- insn_test_v2muls_X0.vgtest \
- insn_test_v2mults_X0.stdout.exp insn_test_v2mults_X0.stderr.exp \
- insn_test_v2mults_X0.vgtest \
- insn_test_v2mz_X0.stdout.exp insn_test_v2mz_X0.stderr.exp \
- insn_test_v2mz_X0.vgtest \
- insn_test_v2mz_X1.stdout.exp insn_test_v2mz_X1.stderr.exp \
- insn_test_v2mz_X1.vgtest \
- insn_test_v2packh_X0.stdout.exp insn_test_v2packh_X0.stderr.exp \
- insn_test_v2packh_X0.vgtest \
- insn_test_v2packh_X1.stdout.exp insn_test_v2packh_X1.stderr.exp \
- insn_test_v2packh_X1.vgtest \
- insn_test_v2packl_X0.stdout.exp insn_test_v2packl_X0.stderr.exp \
- insn_test_v2packl_X0.vgtest \
- insn_test_v2packl_X1.stdout.exp insn_test_v2packl_X1.stderr.exp \
- insn_test_v2packl_X1.vgtest \
- insn_test_v2packuc_X0.stdout.exp insn_test_v2packuc_X0.stderr.exp \
- insn_test_v2packuc_X0.vgtest \
- insn_test_v2packuc_X1.stdout.exp insn_test_v2packuc_X1.stderr.exp \
- insn_test_v2packuc_X1.vgtest \
- insn_test_v2sadas_X0.stdout.exp insn_test_v2sadas_X0.stderr.exp \
- insn_test_v2sadas_X0.vgtest \
- insn_test_v2sadau_X0.stdout.exp insn_test_v2sadau_X0.stderr.exp \
- insn_test_v2sadau_X0.vgtest \
- insn_test_v2sads_X0.stdout.exp insn_test_v2sads_X0.stderr.exp \
- insn_test_v2sads_X0.vgtest \
- insn_test_v2sadu_X0.stdout.exp insn_test_v2sadu_X0.stderr.exp \
- insn_test_v2sadu_X0.vgtest \
- insn_test_v2shl_X0.stdout.exp insn_test_v2shl_X0.stderr.exp \
- insn_test_v2shl_X0.vgtest \
- insn_test_v2shl_X1.stdout.exp insn_test_v2shl_X1.stderr.exp \
- insn_test_v2shl_X1.vgtest \
- insn_test_v2shli_X0.stdout.exp insn_test_v2shli_X0.stderr.exp \
- insn_test_v2shli_X0.vgtest \
- insn_test_v2shli_X1.stdout.exp insn_test_v2shli_X1.stderr.exp \
- insn_test_v2shli_X1.vgtest \
- insn_test_v2shlsc_X0.stdout.exp insn_test_v2shlsc_X0.stderr.exp \
- insn_test_v2shlsc_X0.vgtest \
- insn_test_v2shlsc_X1.stdout.exp insn_test_v2shlsc_X1.stderr.exp \
- insn_test_v2shlsc_X1.vgtest \
- insn_test_v2shrs_X0.stdout.exp insn_test_v2shrs_X0.stderr.exp \
- insn_test_v2shrs_X0.vgtest \
- insn_test_v2shrs_X1.stdout.exp insn_test_v2shrs_X1.stderr.exp \
- insn_test_v2shrs_X1.vgtest \
- insn_test_v2shrsi_X0.stdout.exp insn_test_v2shrsi_X0.stderr.exp \
- insn_test_v2shrsi_X0.vgtest \
- insn_test_v2shrsi_X1.stdout.exp insn_test_v2shrsi_X1.stderr.exp \
- insn_test_v2shrsi_X1.vgtest \
- insn_test_v2shru_X0.stdout.exp insn_test_v2shru_X0.stderr.exp \
- insn_test_v2shru_X0.vgtest \
- insn_test_v2shru_X1.stdout.exp insn_test_v2shru_X1.stderr.exp \
- insn_test_v2shru_X1.vgtest \
- insn_test_v2shrui_X0.stdout.exp insn_test_v2shrui_X0.stderr.exp \
- insn_test_v2shrui_X0.vgtest \
- insn_test_v2shrui_X1.stdout.exp insn_test_v2shrui_X1.stderr.exp \
- insn_test_v2shrui_X1.vgtest \
- insn_test_v2sub_X0.stdout.exp insn_test_v2sub_X0.stderr.exp \
- insn_test_v2sub_X0.vgtest \
- insn_test_v2sub_X1.stdout.exp insn_test_v2sub_X1.stderr.exp \
- insn_test_v2sub_X1.vgtest \
- insn_test_v2subsc_X0.stdout.exp insn_test_v2subsc_X0.stderr.exp \
- insn_test_v2subsc_X0.vgtest \
- insn_test_v2subsc_X1.stdout.exp insn_test_v2subsc_X1.stderr.exp \
- insn_test_v2subsc_X1.vgtest \
- insn_test_v4add_X0.stdout.exp insn_test_v4add_X0.stderr.exp \
- insn_test_v4add_X0.vgtest \
- insn_test_v4add_X1.stdout.exp insn_test_v4add_X1.stderr.exp \
- insn_test_v4add_X1.vgtest \
- insn_test_v4addsc_X0.stdout.exp insn_test_v4addsc_X0.stderr.exp \
- insn_test_v4addsc_X0.vgtest \
- insn_test_v4addsc_X1.stdout.exp insn_test_v4addsc_X1.stderr.exp \
- insn_test_v4addsc_X1.vgtest \
- insn_test_v4int_h_X0.stdout.exp insn_test_v4int_h_X0.stderr.exp \
- insn_test_v4int_h_X0.vgtest \
- insn_test_v4int_h_X1.stdout.exp insn_test_v4int_h_X1.stderr.exp \
- insn_test_v4int_h_X1.vgtest \
- insn_test_v4int_l_X0.stdout.exp insn_test_v4int_l_X0.stderr.exp \
- insn_test_v4int_l_X0.vgtest \
- insn_test_v4int_l_X1.stdout.exp insn_test_v4int_l_X1.stderr.exp \
- insn_test_v4int_l_X1.vgtest \
- insn_test_v4packsc_X0.stdout.exp insn_test_v4packsc_X0.stderr.exp \
- insn_test_v4packsc_X0.vgtest \
- insn_test_v4packsc_X1.stdout.exp insn_test_v4packsc_X1.stderr.exp \
- insn_test_v4packsc_X1.vgtest \
- insn_test_v4shl_X0.stdout.exp insn_test_v4shl_X0.stderr.exp \
- insn_test_v4shl_X0.vgtest \
- insn_test_v4shl_X1.stdout.exp insn_test_v4shl_X1.stderr.exp \
- insn_test_v4shl_X1.vgtest \
- insn_test_v4shlsc_X0.stdout.exp insn_test_v4shlsc_X0.stderr.exp \
- insn_test_v4shlsc_X0.vgtest \
- insn_test_v4shlsc_X1.stdout.exp insn_test_v4shlsc_X1.stderr.exp \
- insn_test_v4shlsc_X1.vgtest \
- insn_test_v4shrs_X0.stdout.exp insn_test_v4shrs_X0.stderr.exp \
- insn_test_v4shrs_X0.vgtest \
- insn_test_v4shrs_X1.stdout.exp insn_test_v4shrs_X1.stderr.exp \
- insn_test_v4shrs_X1.vgtest \
- insn_test_v4shru_X0.stdout.exp insn_test_v4shru_X0.stderr.exp \
- insn_test_v4shru_X0.vgtest \
- insn_test_v4shru_X1.stdout.exp insn_test_v4shru_X1.stderr.exp \
- insn_test_v4shru_X1.vgtest \
- insn_test_v4sub_X0.stdout.exp insn_test_v4sub_X0.stderr.exp \
- insn_test_v4sub_X0.vgtest \
- insn_test_v4sub_X1.stdout.exp insn_test_v4sub_X1.stderr.exp \
- insn_test_v4sub_X1.vgtest \
- insn_test_v4subsc_X0.stdout.exp insn_test_v4subsc_X0.stderr.exp \
- insn_test_v4subsc_X0.vgtest \
- insn_test_v4subsc_X1.stdout.exp insn_test_v4subsc_X1.stderr.exp \
- insn_test_v4subsc_X1.vgtest \
- insn_test_wh64_X1.stdout.exp insn_test_wh64_X1.stderr.exp \
- insn_test_wh64_X1.vgtest \
- insn_test_xor_X0.stdout.exp insn_test_xor_X0.stderr.exp \
- insn_test_xor_X0.vgtest \
- insn_test_xor_X1.stdout.exp insn_test_xor_X1.stderr.exp \
- insn_test_xor_X1.vgtest \
- insn_test_xor_Y0.stdout.exp insn_test_xor_Y0.stderr.exp \
- insn_test_xor_Y0.vgtest \
- insn_test_xor_Y1.stdout.exp insn_test_xor_Y1.stderr.exp \
- insn_test_xor_Y1.vgtest \
- insn_test_xori_X0.stdout.exp insn_test_xori_X0.stderr.exp \
- insn_test_xori_X0.vgtest \
- insn_test_xori_X1.stdout.exp insn_test_xori_X1.stderr.exp \
- insn_test_xori_X1.vgtest
-endif
-
-bin_PROGRAMS = gen_insn_test
-
-insn_tests =
-
-insn_tests += \
- insn_test_move_X0 \
- insn_test_move_X1 \
- insn_test_move_Y0 \
- insn_test_move_Y1 \
- insn_test_movei_X0 \
- insn_test_movei_X1 \
- insn_test_movei_Y0 \
- insn_test_movei_Y1 \
- insn_test_moveli_X0 \
- insn_test_moveli_X1 \
- insn_test_prefetch_X1 \
- insn_test_prefetch_Y2 \
- insn_test_prefetch_l1_X1 \
- insn_test_prefetch_l1_Y2 \
- insn_test_prefetch_l2_X1 \
- insn_test_prefetch_l2_Y2 \
- insn_test_prefetch_l3_X1 \
- insn_test_prefetch_l3_Y2 \
- insn_test_add_X0 \
- insn_test_add_X1 \
- insn_test_add_Y0 \
- insn_test_add_Y1 \
- insn_test_addi_X0 \
- insn_test_addi_X1 \
- insn_test_addi_Y0 \
- insn_test_addi_Y1 \
- insn_test_addli_X0 \
- insn_test_addli_X1 \
- insn_test_addx_X0 \
- insn_test_addx_X1 \
- insn_test_addx_Y0 \
- insn_test_addx_Y1 \
- insn_test_addxi_X0 \
- insn_test_addxi_X1 \
- insn_test_addxi_Y0 \
- insn_test_addxi_Y1 \
- insn_test_addxli_X0 \
- insn_test_addxli_X1 \
- insn_test_addxsc_X0 \
- insn_test_addxsc_X1 \
- insn_test_and_X0 \
- insn_test_and_X1 \
- insn_test_and_Y0 \
- insn_test_and_Y1 \
- insn_test_andi_X0 \
- insn_test_andi_X1 \
- insn_test_andi_Y0 \
- insn_test_andi_Y1 \
- insn_test_beqz_X1 \
- insn_test_beqzt_X1 \
- insn_test_bfexts_X0 \
- insn_test_bfextu_X0 \
- insn_test_bfins_X0 \
- insn_test_bgez_X1 \
- insn_test_bgezt_X1 \
- insn_test_bgtz_X1 \
- insn_test_bgtzt_X1 \
- insn_test_blbc_X1 \
- insn_test_blbct_X1 \
- insn_test_blbs_X1 \
- insn_test_blbst_X1 \
- insn_test_blez_X1 \
- insn_test_blezt_X1 \
- insn_test_bltz_X1 \
- insn_test_bltzt_X1 \
- insn_test_bnez_X1 \
- insn_test_bnezt_X1 \
- insn_test_clz_X0 \
- insn_test_clz_Y0 \
- insn_test_cmoveqz_X0 \
- insn_test_cmoveqz_Y0 \
- insn_test_cmovnez_X0 \
- insn_test_cmovnez_Y0 \
- insn_test_cmpeq_X0 \
- insn_test_cmpeq_X1 \
- insn_test_cmpeq_Y0 \
- insn_test_cmpeq_Y1 \
- insn_test_cmpeqi_X0 \
- insn_test_cmpeqi_X1 \
- insn_test_cmpeqi_Y0 \
- insn_test_cmpeqi_Y1 \
- insn_test_cmples_X0 \
- insn_test_cmples_X1 \
- insn_test_cmples_Y0 \
- insn_test_cmples_Y1 \
- insn_test_cmpleu_X0 \
- insn_test_cmpleu_X1 \
- insn_test_cmpleu_Y0 \
- insn_test_cmpleu_Y1 \
- insn_test_cmplts_X0 \
- insn_test_cmplts_X1 \
- insn_test_cmplts_Y0 \
- insn_test_cmplts_Y1 \
- insn_test_cmpltsi_X0 \
- insn_test_cmpltsi_X1 \
- insn_test_cmpltsi_Y0 \
- insn_test_cmpltsi_Y1 \
- insn_test_cmpltu_X0 \
- insn_test_cmpltu_X1 \
- insn_test_cmpltu_Y0 \
- insn_test_cmpltu_Y1 \
- insn_test_cmpltui_X0 \
- insn_test_cmpltui_X1 \
- insn_test_cmpne_X0 \
- insn_test_cmpne_X1 \
- insn_test_cmpne_Y0 \
- insn_test_cmpne_Y1 \
- insn_test_cmul_X0 \
- insn_test_cmula_X0 \
- insn_test_cmulaf_X0 \
- insn_test_cmulf_X0 \
- insn_test_cmulfr_X0 \
- insn_test_cmulh_X0 \
- insn_test_cmulhr_X0 \
- insn_test_crc32_32_X0 \
- insn_test_crc32_8_X0 \
- insn_test_ctz_X0 \
- insn_test_ctz_Y0 \
- insn_test_dblalign_X0 \
- insn_test_dblalign2_X0 \
- insn_test_dblalign2_X1 \
- insn_test_dblalign4_X0 \
- insn_test_dblalign4_X1 \
- insn_test_dblalign6_X0 \
- insn_test_dblalign6_X1 \
- insn_test_dtlbpr_X1 \
- insn_test_fdouble_add_flags_X0 \
- insn_test_fdouble_addsub_X0 \
- insn_test_fdouble_mul_flags_X0 \
- insn_test_fdouble_pack1_X0 \
- insn_test_fdouble_pack2_X0 \
- insn_test_fdouble_sub_flags_X0 \
- insn_test_fdouble_unpack_max_X0 \
- insn_test_fdouble_unpack_min_X0 \
- insn_test_flushwb_X1 \
- insn_test_fnop_X0 \
- insn_test_fnop_X1 \
- insn_test_fnop_Y0 \
- insn_test_fnop_Y1 \
- insn_test_fsingle_add1_X0 \
- insn_test_fsingle_addsub2_X0 \
- insn_test_fsingle_mul1_X0 \
- insn_test_fsingle_mul2_X0 \
- insn_test_fsingle_pack1_X0 \
- insn_test_fsingle_pack1_Y0 \
- insn_test_fsingle_pack2_X0 \
- insn_test_fsingle_sub1_X0 \
- insn_test_icoh_X1 \
- insn_test_j_X1 \
- insn_test_jal_X1 \
- insn_test_jalr_X1 \
- insn_test_jalr_Y1 \
- insn_test_jalrp_X1 \
- insn_test_jalrp_Y1 \
- insn_test_jr_X1 \
- insn_test_jr_Y1 \
- insn_test_jrp_X1 \
- insn_test_jrp_Y1 \
- insn_test_ld_X1 \
- insn_test_ld_Y2 \
- insn_test_ld1s_X1 \
- insn_test_ld1s_Y2 \
- insn_test_ld1s_add_X1 \
- insn_test_ld1u_X1 \
- insn_test_ld1u_Y2 \
- insn_test_ld1u_add_X1 \
- insn_test_ld2s_X1 \
- insn_test_ld2s_Y2 \
- insn_test_ld2u_X1 \
- insn_test_ld2u_Y2 \
- insn_test_ld4s_X1 \
- insn_test_ld4s_add_X1 \
- insn_test_ld4u_X1 \
- insn_test_ld4u_Y2 \
- insn_test_ld4u_add_X1 \
- insn_test_ld_add_X1 \
- insn_test_ldna_X1 \
- insn_test_ldna_add_X1 \
- insn_test_ldnt_X1 \
- insn_test_ldnt1s_X1 \
- insn_test_ldnt1s_add_X1 \
- insn_test_ldnt1u_X1 \
- insn_test_ldnt1u_add_X1 \
- insn_test_ldnt2s_X1 \
- insn_test_ldnt2s_add_X1 \
- insn_test_ldnt2u_add_X1 \
- insn_test_ldnt4s_X1 \
- insn_test_ldnt4s_add_X1 \
- insn_test_ldnt4u_X1 \
- insn_test_ldnt4u_add_X1 \
- insn_test_ldnt_add_X1 \
- insn_test_lnk_X1 \
- insn_test_lnk_Y1 \
- insn_test_mf_X1 \
- insn_test_mm_X0 \
- insn_test_mnz_X0 \
- insn_test_mnz_X1 \
- insn_test_mnz_Y0 \
- insn_test_mnz_Y1 \
- insn_test_mul_hs_hs_X0 \
- insn_test_mul_hs_hs_Y0 \
- insn_test_mul_hs_hu_X0 \
- insn_test_mul_hs_ls_X0 \
- insn_test_mul_hs_lu_X0 \
- insn_test_mul_hu_hu_X0 \
- insn_test_mul_hu_hu_Y0 \
- insn_test_mul_hu_lu_X0 \
- insn_test_mul_ls_ls_X0 \
- insn_test_mul_ls_ls_Y0 \
- insn_test_mul_ls_lu_X0 \
- insn_test_mul_lu_lu_X0 \
- insn_test_mul_lu_lu_Y0 \
- insn_test_mula_hs_hs_X0 \
- insn_test_mula_hs_hs_Y0 \
- insn_test_mula_hs_hu_X0 \
- insn_test_mula_hs_ls_X0 \
- insn_test_mula_hs_lu_X0 \
- insn_test_mula_hu_hu_X0 \
- insn_test_mula_hu_hu_Y0 \
- insn_test_mula_hu_ls_X0 \
- insn_test_mula_hu_lu_X0 \
- insn_test_mula_ls_ls_X0 \
- insn_test_mula_ls_ls_Y0 \
- insn_test_mula_ls_lu_X0 \
- insn_test_mula_lu_lu_X0 \
- insn_test_mula_lu_lu_Y0 \
- insn_test_mulax_X0 \
- insn_test_mulax_Y0 \
- insn_test_mulx_X0 \
- insn_test_mulx_Y0 \
- insn_test_mz_X0 \
- insn_test_mz_X1 \
- insn_test_mz_Y0 \
- insn_test_mz_Y1 \
- insn_test_nop_X0 \
- insn_test_nop_X1 \
- insn_test_nop_Y0 \
- insn_test_nop_Y1 \
- insn_test_nor_X0 \
- insn_test_nor_X1 \
- insn_test_nor_Y0 \
- insn_test_nor_Y1 \
- insn_test_or_X0 \
- insn_test_or_X1 \
- insn_test_or_Y0 \
- insn_test_or_Y1 \
- insn_test_ori_X0 \
- insn_test_ori_X1 \
- insn_test_pcnt_X0 \
- insn_test_pcnt_Y0 \
- insn_test_revbits_X0 \
- insn_test_revbits_Y0 \
- insn_test_revbytes_X0 \
- insn_test_revbytes_Y0 \
- insn_test_rotl_X0 \
- insn_test_rotl_X1 \
- insn_test_rotl_Y0 \
- insn_test_rotl_Y1 \
- insn_test_rotli_X0 \
- insn_test_rotli_X1 \
- insn_test_rotli_Y0 \
- insn_test_rotli_Y1 \
- insn_test_shl_X0 \
- insn_test_shl_X1 \
- insn_test_shl_Y0 \
- insn_test_shl_Y1 \
- insn_test_shl16insli_X0 \
- insn_test_shl16insli_X1 \
- insn_test_shl1add_X0 \
- insn_test_shl1add_X1 \
- insn_test_shl1add_Y0 \
- insn_test_shl1add_Y1 \
- insn_test_shl1addx_X0 \
- insn_test_shl1addx_X1 \
- insn_test_shl1addx_Y0 \
- insn_test_shl1addx_Y1 \
- insn_test_shl2add_X0 \
- insn_test_shl2add_X1 \
- insn_test_shl2add_Y0 \
- insn_test_shl2add_Y1 \
- insn_test_shl2addx_X0 \
- insn_test_shl2addx_X1 \
- insn_test_shl2addx_Y0 \
- insn_test_shl2addx_Y1 \
- insn_test_shl3add_X0 \
- insn_test_shl3add_X1 \
- insn_test_shl3add_Y0 \
- insn_test_shl3add_Y1 \
- insn_test_shl3addx_X0 \
- insn_test_shl3addx_X1 \
- insn_test_shl3addx_Y0 \
- insn_test_shl3addx_Y1 \
- insn_test_shli_X0 \
- insn_test_shli_X1 \
- insn_test_shli_Y0 \
- insn_test_shli_Y1 \
- insn_test_shlx_X0 \
- insn_test_shlx_X1 \
- insn_test_shlxi_X0 \
- insn_test_shlxi_X1 \
- insn_test_shrs_X0 \
- insn_test_shrs_X1 \
- insn_test_shrs_Y0 \
- insn_test_shrs_Y1 \
- insn_test_shrsi_X0 \
- insn_test_shrsi_X1 \
- insn_test_shrsi_Y0 \
- insn_test_shrsi_Y1 \
- insn_test_shru_X0 \
- insn_test_shru_X1 \
- insn_test_shru_Y0 \
- insn_test_shru_Y1 \
- insn_test_shrui_X0 \
- insn_test_shrui_X1 \
- insn_test_shrui_Y0 \
- insn_test_shrui_Y1 \
- insn_test_shrux_X0 \
- insn_test_shrux_X1 \
- insn_test_shufflebytes_X0 \
- insn_test_st_X1 \
- insn_test_st_Y2 \
- insn_test_st1_X1 \
- insn_test_st1_Y2 \
- insn_test_st1_add_X1 \
- insn_test_st2_X1 \
- insn_test_st2_Y2 \
- insn_test_st2_add_X1 \
- insn_test_st4_X1 \
- insn_test_st4_Y2 \
- insn_test_st4_add_X1 \
- insn_test_st_add_X1 \
- insn_test_stnt_X1 \
- insn_test_stnt1_X1 \
- insn_test_stnt2_X1 \
- insn_test_stnt2_add_X1 \
- insn_test_stnt4_X1 \
- insn_test_stnt4_add_X1 \
- insn_test_stnt_add_X1 \
- insn_test_sub_X0 \
- insn_test_sub_X1 \
- insn_test_sub_Y0 \
- insn_test_sub_Y1 \
- insn_test_subx_X0 \
- insn_test_subx_X1 \
- insn_test_subx_Y0 \
- insn_test_subx_Y1 \
- insn_test_tblidxb0_X0 \
- insn_test_tblidxb0_Y0 \
- insn_test_tblidxb1_X0 \
- insn_test_tblidxb1_Y0 \
- insn_test_tblidxb2_X0 \
- insn_test_tblidxb2_Y0 \
- insn_test_tblidxb3_X0 \
- insn_test_tblidxb3_Y0 \
- insn_test_v1add_X0 \
- insn_test_v1add_X1 \
- insn_test_v1adduc_X0 \
- insn_test_v1adduc_X1 \
- insn_test_v1adiffu_X0 \
- insn_test_v1avgu_X0 \
- insn_test_v1cmpeq_X0 \
- insn_test_v1cmpeq_X1 \
- insn_test_v1cmpeqi_X0 \
- insn_test_v1cmpeqi_X1 \
- insn_test_v1cmples_X0 \
- insn_test_v1cmples_X1 \
- insn_test_v1cmpleu_X0 \
- insn_test_v1cmpleu_X1 \
- insn_test_v1cmplts_X0 \
- insn_test_v1cmplts_X1 \
- insn_test_v1cmpltu_X0 \
- insn_test_v1cmpltu_X1 \
- insn_test_v1cmpne_X0 \
- insn_test_v1cmpne_X1 \
- insn_test_v1ddotpu_X0 \
- insn_test_v1ddotpua_X0 \
- insn_test_v1ddotpus_X0 \
- insn_test_v1ddotpusa_X0 \
- insn_test_v1dotp_X0 \
- insn_test_v1dotpa_X0 \
- insn_test_v1dotpu_X0 \
- insn_test_v1dotpua_X0 \
- insn_test_v1dotpus_X0 \
- insn_test_v1dotpusa_X0 \
- insn_test_v1int_h_X0 \
- insn_test_v1int_h_X1 \
- insn_test_v1int_l_X0 \
- insn_test_v1int_l_X1 \
- insn_test_v1maxu_X0 \
- insn_test_v1maxu_X1 \
- insn_test_v1minu_X0 \
- insn_test_v1minu_X1 \
- insn_test_v1mnz_X0 \
- insn_test_v1mnz_X1 \
- insn_test_v1multu_X0 \
- insn_test_v1mulu_X0 \
- insn_test_v1mulus_X0 \
- insn_test_v1mz_X0 \
- insn_test_v1mz_X1 \
- insn_test_v1sadau_X0 \
- insn_test_v1sadu_X0 \
- insn_test_v1shl_X0 \
- insn_test_v1shl_X1 \
- insn_test_v1shli_X0 \
- insn_test_v1shli_X1 \
- insn_test_v1shrs_X0 \
- insn_test_v1shrs_X1 \
- insn_test_v1shrsi_X0 \
- insn_test_v1shrsi_X1 \
- insn_test_v1shru_X0 \
- insn_test_v1shru_X1 \
- insn_test_v1shrui_X0 \
- insn_test_v1shrui_X1 \
- insn_test_v1sub_X0 \
- insn_test_v1sub_X1 \
- insn_test_v1subuc_X0 \
- insn_test_v1subuc_X1 \
- insn_test_v2add_X0 \
- insn_test_v2add_X1 \
- insn_test_v2addsc_X0 \
- insn_test_v2addsc_X1 \
- insn_test_v2adiffs_X0 \
- insn_test_v2avgs_X0 \
- insn_test_v2cmpeq_X0 \
- insn_test_v2cmpeq_X1 \
- insn_test_v2cmpeqi_X0 \
- insn_test_v2cmpeqi_X1 \
- insn_test_v2cmples_X0 \
- insn_test_v2cmples_X1 \
- insn_test_v2cmpleu_X0 \
- insn_test_v2cmpleu_X1 \
- insn_test_v2cmplts_X0 \
- insn_test_v2cmplts_X1 \
- insn_test_v2cmpltsi_X0 \
- insn_test_v2cmpltsi_X1 \
- insn_test_v2cmpltu_X0 \
- insn_test_v2cmpltu_X1 \
- insn_test_v2cmpltui_X0 \
- insn_test_v2cmpltui_X1 \
- insn_test_v2cmpne_X0 \
- insn_test_v2cmpne_X1 \
- insn_test_v2dotp_X0 \
- insn_test_v2dotpa_X0 \
- insn_test_v2int_h_X0 \
- insn_test_v2int_h_X1 \
- insn_test_v2int_l_X0 \
- insn_test_v2int_l_X1 \
- insn_test_v2maxs_X0 \
- insn_test_v2maxs_X1 \
- insn_test_v2mins_X0 \
- insn_test_v2mins_X1 \
- insn_test_v2mnz_X0 \
- insn_test_v2mnz_X1 \
- insn_test_v2mulfsc_X0 \
- insn_test_v2muls_X0 \
- insn_test_v2mults_X0 \
- insn_test_v2mz_X0 \
- insn_test_v2mz_X1 \
- insn_test_v2packh_X0 \
- insn_test_v2packh_X1 \
- insn_test_v2packl_X0 \
- insn_test_v2packl_X1 \
- insn_test_v2packuc_X0 \
- insn_test_v2packuc_X1 \
- insn_test_v2sadas_X0 \
- insn_test_v2sadau_X0 \
- insn_test_v2sads_X0 \
- insn_test_v2sadu_X0 \
- insn_test_v2shl_X0 \
- insn_test_v2shl_X1 \
- insn_test_v2shli_X0 \
- insn_test_v2shli_X1 \
- insn_test_v2shlsc_X0 \
- insn_test_v2shlsc_X1 \
- insn_test_v2shrs_X0 \
- insn_test_v2shrs_X1 \
- insn_test_v2shrsi_X0 \
- insn_test_v2shrsi_X1 \
- insn_test_v2shru_X0 \
- insn_test_v2shru_X1 \
- insn_test_v2shrui_X0 \
- insn_test_v2shrui_X1 \
- insn_test_v2sub_X0 \
- insn_test_v2sub_X1 \
- insn_test_v2subsc_X0 \
- insn_test_v2subsc_X1 \
- insn_test_v4add_X0 \
- insn_test_v4add_X1 \
- insn_test_v4addsc_X0 \
- insn_test_v4addsc_X1 \
- insn_test_v4int_h_X0 \
- insn_test_v4int_h_X1 \
- insn_test_v4int_l_X0 \
- insn_test_v4int_l_X1 \
- insn_test_v4packsc_X0 \
- insn_test_v4packsc_X1 \
- insn_test_v4shl_X0 \
- insn_test_v4shl_X1 \
- insn_test_v4shlsc_X0 \
- insn_test_v4shlsc_X1 \
- insn_test_v4shrs_X0 \
- insn_test_v4shrs_X1 \
- insn_test_v4shru_X0 \
- insn_test_v4shru_X1 \
- insn_test_v4sub_X0 \
- insn_test_v4sub_X1 \
- insn_test_v4subsc_X0 \
- insn_test_v4subsc_X1 \
- insn_test_wh64_X1 \
- insn_test_xor_X0 \
- insn_test_xor_X1 \
- insn_test_xor_Y0 \
- insn_test_xor_Y1 \
- insn_test_xori_X0 \
- insn_test_xori_X1
-
-check_PROGRAMS = \
- allexec \
- $(insn_tests)
-
-AM_CFLAGS += @FLAG_M64@ -w
-AM_CXXFLAGS += @FLAG_M64@
-AM_CCASFLAGS += @FLAG_M64@
-
-allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
-gen_insn_test_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@ -I$(top_srcdir)/VEX/priv
-gen_insn_test_LDADD = ../../../VEX/priv/tilegx_disasm.o
-
-$(addsuffix .c, $(insn_tests)) : gen_insn_test
- @$(srcdir)/gen_test.sh $@
-
-$(addsuffix .stdout.exp, $(insn_tests)) : $(insn_tests)
- ./$(basename $(basename $@)) > $@
-
-$(addsuffix .stderr.exp, $(insn_tests)) :
- touch $@
-
-$(addsuffix .vgtest, $(insn_tests)) :
- echo -e "prog: $(basename $@)\nvgopts: -q" > $@
-
-check-am : $(addsuffix .stdout.exp, $(insn_tests)) $(addsuffix .stderr.exp, $(insn_tests)) $(addsuffix .vgtest, $(insn_tests))
-
-clean-am :
- @rm -f *.stderr.exp *.stdout.exp *.vgtest $(addsuffix .c, $(insn_tests)) $(addsuffix .o, $(insn_tests)) $(insn_tests)
- @rm -f *.o $(bin_PROGRAMS)
-
-distclean-am : clean-am
diff --git a/none/tests/tilegx/Makefile.in b/none/tests/tilegx/Makefile.in
deleted file mode 100644
index 1d19f73..0000000
--- a/none/tests/tilegx/Makefile.in
+++ /dev/null
@@ -1,7162 +0,0 @@
-# Makefile.in generated by automake 1.15 from Makefile.am.
-# @configure_input@
-
-# Copyright (C) 1994-2014 Free Software Foundation, Inc.
-
-# This Makefile.in is free software; the Free Software Foundation
-# gives unlimited permission to copy and/or distribute it,
-# with or without modifications, as long as this notice is preserved.
-
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
-# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-# PARTICULAR PURPOSE.
-
-@SET_MAKE@
-
-# This file is used for tool tests, and also in perf/Makefile.am.
-
-# This file should be included (directly or indirectly) by every
-# Makefile.am that builds programs. And also the top-level Makefile.am.
-
-#----------------------------------------------------------------------------
-# Global stuff
-#----------------------------------------------------------------------------
-
-
-VPATH = @srcdir@
-am__is_gnu_make = { \
- if test -z '$(MAKELEVEL)'; then \
- false; \
- elif test -n '$(MAKE_HOST)'; then \
- true; \
- elif test -n '$(MAKE_VERSION)' && test -n '$(CURDIR)'; then \
- true; \
- else \
- false; \
- fi; \
-}
-am__make_running_with_option = \
- case $${target_option-} in \
- ?) ;; \
- *) echo "am__make_running_with_option: internal error: invalid" \
- "target option '$${target_option-}' specified" >&2; \
- exit 1;; \
- esac; \
- has_opt=no; \
- sane_makeflags=$$MAKEFLAGS; \
- if $(am__is_gnu_make); then \
- sane_makeflags=$$MFLAGS; \
- else \
- case $$MAKEFLAGS in \
- *\\[\ \ ]*) \
- bs=\\; \
- sane_makeflags=`printf '%s\n' "$$MAKEFLAGS" \
- | sed "s/$$bs$$bs[$$bs $$bs ]*//g"`;; \
- esac; \
- fi; \
- skip_next=no; \
- strip_trailopt () \
- { \
- flg=`printf '%s\n' "$$flg" | sed "s/$$1.*$$//"`; \
- }; \
- for flg in $$sane_makeflags; do \
- test $$skip_next = yes && { skip_next=no; continue; }; \
- case $$flg in \
- *=*|--*) continue;; \
- -*I) strip_trailopt 'I'; skip_next=yes;; \
- -*I?*) strip_trailopt 'I';; \
- -*O) strip_trailopt 'O'; skip_next=yes;; \
- -*O?*) strip_trailopt 'O';; \
- -*l) strip_trailopt 'l'; skip_next=yes;; \
- -*l?*) strip_trailopt 'l';; \
- -[dEDm]) skip_next=yes;; \
- -[JT]) skip_next=yes;; \
- esac; \
- case $$flg in \
- *$$target_option*) has_opt=yes; break;; \
- esac; \
- done; \
- test $$has_opt = yes
-am__make_dryrun = (target_option=n; $(am__make_running_with_option))
-am__make_keepgoing = (target_option=k; $(am__make_running_with_option))
-pkgdatadir = $(datadir)/@PACKAGE@
-pkgincludedir = $(includedir)/@PACKAGE@
-pkglibdir = $(libdir)/@PACKAGE@
-pkglibexecdir = $(libexecdir)/@PACKAGE@
-am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
-install_sh_DATA = $(install_sh) -c -m 644
-install_sh_PROGRAM = $(install_sh) -c
-install_sh_SCRIPT = $(install_sh) -c
-INSTALL_HEADER = $(INSTALL_DATA)
-transform = $(program_transform_name)
-NORMAL_INSTALL = :
-PRE_INSTALL = :
-POST_INSTALL = :
-NORMAL_UNINSTALL = :
-PRE_UNINSTALL = :
-POST_UNINSTALL = :
-build_triplet = @build@
-host_triplet = @host@
-@COMPILER_IS_CLANG_TRUE@am__append_1 = -Wno-cast-align -Wno-self-assign \
-@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-compare
-
-@SOLARIS_XPG_SYMBOLS_PRESENT_TRUE@am__append_2 = -Wl,-M,$(top_srcdir)/solaris/vgpreload-solaris.mapfile
-
-# The Android toolchain includes all kinds of stdlib helpers present in
-# bionic which is bad because we are not linking with it and the Android
-# linker will panic.
-@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_3 = -nostdlib
-@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_4 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
-@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
-
-
-# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
-@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
-@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
-@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
-@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-constant-out-of-range-compare \
-@COMPILER_IS_CLANG_TRUE@ -Wno-self-assign -Wno-string-plus-int \
-@COMPILER_IS_CLANG_TRUE@ -Wno-uninitialized -Wno-unused-value # \
-@COMPILER_IS_CLANG_TRUE@ clang 3.0.0
-@COMPILER_IS_CLANG_TRUE@am__append_7 = -Wno-unused-private-field # drd/tests/tsan_unittest.cpp
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@am__append_8 = \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_move_X0.stdout.exp insn_test_move_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_move_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_move_X1.stdout.exp insn_test_move_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_move_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_move_Y0.stdout.exp insn_test_move_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_move_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_move_Y1.stdout.exp insn_test_move_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_move_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_movei_X0.stdout.exp insn_test_movei_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_movei_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_movei_X1.stdout.exp insn_test_movei_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_movei_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_movei_Y0.stdout.exp insn_test_movei_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_movei_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_movei_Y1.stdout.exp insn_test_movei_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_movei_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_moveli_X0.stdout.exp insn_test_moveli_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_moveli_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_moveli_X1.stdout.exp insn_test_moveli_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_moveli_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_X1.stdout.exp insn_test_prefetch_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_Y2.stdout.exp insn_test_prefetch_Y2.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_Y2.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l1_X1.stdout.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l1_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l1_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l1_Y2.stdout.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l1_Y2.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l1_Y2.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l2_X1.stdout.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l2_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l2_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l2_Y2.stdout.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l2_Y2.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l2_Y2.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l3_X1.stdout.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l3_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l3_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l3_Y2.stdout.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l3_Y2.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l3_Y2.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_add_X0.stdout.exp insn_test_add_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_add_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_add_X1.stdout.exp insn_test_add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_add_Y0.stdout.exp insn_test_add_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_add_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_add_Y1.stdout.exp insn_test_add_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_add_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addi_X0.stdout.exp insn_test_addi_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addi_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addi_X1.stdout.exp insn_test_addi_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addi_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addi_Y0.stdout.exp insn_test_addi_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addi_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addi_Y1.stdout.exp insn_test_addi_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addi_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addli_X0.stdout.exp insn_test_addli_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addli_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addli_X1.stdout.exp insn_test_addli_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addli_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addx_X0.stdout.exp insn_test_addx_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addx_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addx_X1.stdout.exp insn_test_addx_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addx_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addx_Y0.stdout.exp insn_test_addx_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addx_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addx_Y1.stdout.exp insn_test_addx_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addx_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addxi_X0.stdout.exp insn_test_addxi_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addxi_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addxi_X1.stdout.exp insn_test_addxi_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addxi_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addxi_Y0.stdout.exp insn_test_addxi_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addxi_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addxi_Y1.stdout.exp insn_test_addxi_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addxi_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addxli_X0.stdout.exp insn_test_addxli_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addxli_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addxli_X1.stdout.exp insn_test_addxli_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addxli_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addxsc_X0.stdout.exp insn_test_addxsc_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addxsc_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addxsc_X1.stdout.exp insn_test_addxsc_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addxsc_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_and_X0.stdout.exp insn_test_and_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_and_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_and_X1.stdout.exp insn_test_and_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_and_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_and_Y0.stdout.exp insn_test_and_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_and_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_and_Y1.stdout.exp insn_test_and_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_and_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_andi_X0.stdout.exp insn_test_andi_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_andi_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_andi_X1.stdout.exp insn_test_andi_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_andi_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_andi_Y0.stdout.exp insn_test_andi_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_andi_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_andi_Y1.stdout.exp insn_test_andi_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_andi_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_beqz_X1.stdout.exp insn_test_beqz_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_beqz_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_beqzt_X1.stdout.exp insn_test_beqzt_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_beqzt_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_bfexts_X0.stdout.exp insn_test_bfexts_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_bfexts_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_bfextu_X0.stdout.exp insn_test_bfextu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_bfextu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_bfins_X0.stdout.exp insn_test_bfins_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_bfins_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_bgez_X1.stdout.exp insn_test_bgez_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_bgez_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_bgezt_X1.stdout.exp insn_test_bgezt_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_bgezt_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_bgtz_X1.stdout.exp insn_test_bgtz_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_bgtz_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_bgtzt_X1.stdout.exp insn_test_bgtzt_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_bgtzt_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_blbc_X1.stdout.exp insn_test_blbc_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_blbc_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_blbct_X1.stdout.exp insn_test_blbct_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_blbct_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_blbs_X1.stdout.exp insn_test_blbs_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_blbs_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_blbst_X1.stdout.exp insn_test_blbst_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_blbst_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_blez_X1.stdout.exp insn_test_blez_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_blez_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_blezt_X1.stdout.exp insn_test_blezt_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_blezt_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_bltz_X1.stdout.exp insn_test_bltz_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_bltz_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_bltzt_X1.stdout.exp insn_test_bltzt_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_bltzt_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_bnez_X1.stdout.exp insn_test_bnez_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_bnez_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_bnezt_X1.stdout.exp insn_test_bnezt_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_bnezt_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_clz_X0.stdout.exp insn_test_clz_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_clz_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_clz_Y0.stdout.exp insn_test_clz_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_clz_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmoveqz_X0.stdout.exp insn_test_cmoveqz_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmoveqz_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmoveqz_Y0.stdout.exp insn_test_cmoveqz_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmoveqz_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmovnez_X0.stdout.exp insn_test_cmovnez_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmovnez_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmovnez_Y0.stdout.exp insn_test_cmovnez_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmovnez_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpeq_X0.stdout.exp insn_test_cmpeq_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpeq_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpeq_X1.stdout.exp insn_test_cmpeq_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpeq_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpeq_Y0.stdout.exp insn_test_cmpeq_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpeq_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpeq_Y1.stdout.exp insn_test_cmpeq_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpeq_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpeqi_X0.stdout.exp insn_test_cmpeqi_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpeqi_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpeqi_X1.stdout.exp insn_test_cmpeqi_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpeqi_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpeqi_Y0.stdout.exp insn_test_cmpeqi_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpeqi_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpeqi_Y1.stdout.exp insn_test_cmpeqi_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpeqi_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmples_X0.stdout.exp insn_test_cmples_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmples_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmples_X1.stdout.exp insn_test_cmples_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmples_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmples_Y0.stdout.exp insn_test_cmples_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmples_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmples_Y1.stdout.exp insn_test_cmples_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmples_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpleu_X0.stdout.exp insn_test_cmpleu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpleu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpleu_X1.stdout.exp insn_test_cmpleu_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpleu_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpleu_Y0.stdout.exp insn_test_cmpleu_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpleu_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpleu_Y1.stdout.exp insn_test_cmpleu_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpleu_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmplts_X0.stdout.exp insn_test_cmplts_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmplts_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmplts_X1.stdout.exp insn_test_cmplts_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmplts_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmplts_Y0.stdout.exp insn_test_cmplts_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmplts_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmplts_Y1.stdout.exp insn_test_cmplts_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmplts_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpltsi_X0.stdout.exp insn_test_cmpltsi_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpltsi_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpltsi_X1.stdout.exp insn_test_cmpltsi_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpltsi_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpltsi_Y0.stdout.exp insn_test_cmpltsi_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpltsi_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpltsi_Y1.stdout.exp insn_test_cmpltsi_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpltsi_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpltu_X0.stdout.exp insn_test_cmpltu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpltu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpltu_X1.stdout.exp insn_test_cmpltu_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpltu_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpltu_Y0.stdout.exp insn_test_cmpltu_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpltu_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpltu_Y1.stdout.exp insn_test_cmpltu_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpltu_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpltui_X0.stdout.exp insn_test_cmpltui_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpltui_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpltui_X1.stdout.exp insn_test_cmpltui_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpltui_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpne_X0.stdout.exp insn_test_cmpne_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpne_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpne_X1.stdout.exp insn_test_cmpne_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpne_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpne_Y0.stdout.exp insn_test_cmpne_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpne_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpne_Y1.stdout.exp insn_test_cmpne_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmpne_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmul_X0.stdout.exp insn_test_cmul_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmul_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmula_X0.stdout.exp insn_test_cmula_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmula_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmulaf_X0.stdout.exp insn_test_cmulaf_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmulaf_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmulf_X0.stdout.exp insn_test_cmulf_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmulf_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmulfr_X0.stdout.exp insn_test_cmulfr_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmulfr_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmulh_X0.stdout.exp insn_test_cmulh_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmulh_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmulhr_X0.stdout.exp insn_test_cmulhr_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_cmulhr_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_crc32_32_X0.stdout.exp insn_test_crc32_32_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_crc32_32_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_crc32_8_X0.stdout.exp insn_test_crc32_8_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_crc32_8_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ctz_X0.stdout.exp insn_test_ctz_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ctz_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ctz_Y0.stdout.exp insn_test_ctz_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ctz_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_dblalign_X0.stdout.exp insn_test_dblalign_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_dblalign_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_dblalign2_X0.stdout.exp insn_test_dblalign2_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_dblalign2_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_dblalign2_X1.stdout.exp insn_test_dblalign2_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_dblalign2_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_dblalign4_X0.stdout.exp insn_test_dblalign4_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_dblalign4_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_dblalign4_X1.stdout.exp insn_test_dblalign4_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_dblalign4_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_dblalign6_X0.stdout.exp insn_test_dblalign6_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_dblalign6_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_dblalign6_X1.stdout.exp insn_test_dblalign6_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_dblalign6_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_dtlbpr_X1.stdout.exp insn_test_dtlbpr_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_dtlbpr_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fdouble_add_flags_X0.stdout.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fdouble_add_flags_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fdouble_add_flags_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fdouble_addsub_X0.stdout.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fdouble_addsub_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fdouble_addsub_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fdouble_mul_flags_X0.stdout.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fdouble_mul_flags_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fdouble_mul_flags_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fdouble_pack1_X0.stdout.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fdouble_pack1_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fdouble_pack1_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fdouble_pack2_X0.stdout.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fdouble_pack2_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fdouble_pack2_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fdouble_sub_flags_X0.stdout.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fdouble_sub_flags_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fdouble_sub_flags_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fdouble_unpack_max_X0.stdout.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fdouble_unpack_max_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fdouble_unpack_max_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fdouble_unpack_min_X0.stdout.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fdouble_unpack_min_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fdouble_unpack_min_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_flushwb_X1.stdout.exp insn_test_flushwb_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_flushwb_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fnop_X0.stdout.exp insn_test_fnop_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fnop_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fnop_X1.stdout.exp insn_test_fnop_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fnop_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fnop_Y0.stdout.exp insn_test_fnop_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fnop_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fnop_Y1.stdout.exp insn_test_fnop_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fnop_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fsingle_add1_X0.stdout.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fsingle_add1_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fsingle_add1_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fsingle_addsub2_X0.stdout.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fsingle_addsub2_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fsingle_addsub2_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fsingle_mul1_X0.stdout.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fsingle_mul1_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fsingle_mul1_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fsingle_mul2_X0.stdout.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fsingle_mul2_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fsingle_mul2_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fsingle_pack1_X0.stdout.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fsingle_pack1_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fsingle_pack1_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fsingle_pack1_Y0.stdout.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fsingle_pack1_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fsingle_pack1_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fsingle_pack2_X0.stdout.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fsingle_pack2_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fsingle_pack2_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fsingle_sub1_X0.stdout.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fsingle_sub1_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_fsingle_sub1_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_icoh_X1.stdout.exp insn_test_icoh_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_icoh_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_j_X1.stdout.exp insn_test_j_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_j_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_jal_X1.stdout.exp insn_test_jal_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_jal_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_jalr_X1.stdout.exp insn_test_jalr_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_jalr_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_jalr_Y1.stdout.exp insn_test_jalr_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_jalr_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_jalrp_X1.stdout.exp insn_test_jalrp_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_jalrp_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_jalrp_Y1.stdout.exp insn_test_jalrp_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_jalrp_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_jr_X1.stdout.exp insn_test_jr_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_jr_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_jr_Y1.stdout.exp insn_test_jr_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_jr_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_jrp_X1.stdout.exp insn_test_jrp_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_jrp_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_jrp_Y1.stdout.exp insn_test_jrp_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_jrp_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld_X1.stdout.exp insn_test_ld_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld_Y2.stdout.exp insn_test_ld_Y2.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld_Y2.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld1s_X1.stdout.exp insn_test_ld1s_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld1s_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld1s_Y2.stdout.exp insn_test_ld1s_Y2.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld1s_Y2.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld1s_add_X1.stdout.exp insn_test_ld1s_add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld1s_add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld1u_X1.stdout.exp insn_test_ld1u_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld1u_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld1u_Y2.stdout.exp insn_test_ld1u_Y2.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld1u_Y2.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld1u_add_X1.stdout.exp insn_test_ld1u_add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld1u_add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld2s_X1.stdout.exp insn_test_ld2s_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld2s_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld2s_Y2.stdout.exp insn_test_ld2s_Y2.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld2s_Y2.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld2u_X1.stdout.exp insn_test_ld2u_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld2u_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld2u_Y2.stdout.exp insn_test_ld2u_Y2.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld2u_Y2.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld4s_X1.stdout.exp insn_test_ld4s_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld4s_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld4s_add_X1.stdout.exp insn_test_ld4s_add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld4s_add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld4u_X1.stdout.exp insn_test_ld4u_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld4u_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld4u_Y2.stdout.exp insn_test_ld4u_Y2.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld4u_Y2.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld4u_add_X1.stdout.exp insn_test_ld4u_add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld4u_add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld_add_X1.stdout.exp insn_test_ld_add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ld_add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldna_X1.stdout.exp insn_test_ldna_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldna_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldna_add_X1.stdout.exp insn_test_ldna_add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldna_add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt_X1.stdout.exp insn_test_ldnt_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt1s_X1.stdout.exp insn_test_ldnt1s_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt1s_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt1s_add_X1.stdout.exp insn_test_ldnt1s_add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt1s_add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt1u_X1.stdout.exp insn_test_ldnt1u_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt1u_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt1u_add_X1.stdout.exp insn_test_ldnt1u_add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt1u_add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt2s_X1.stdout.exp insn_test_ldnt2s_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt2s_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt2s_add_X1.stdout.exp insn_test_ldnt2s_add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt2s_add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt2u_add_X1.stdout.exp insn_test_ldnt2u_add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt2u_add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt4s_X1.stdout.exp insn_test_ldnt4s_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt4s_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt4s_add_X1.stdout.exp insn_test_ldnt4s_add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt4s_add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt4u_X1.stdout.exp insn_test_ldnt4u_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt4u_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt4u_add_X1.stdout.exp insn_test_ldnt4u_add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt4u_add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt_add_X1.stdout.exp insn_test_ldnt_add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ldnt_add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_lnk_X1.stdout.exp insn_test_lnk_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_lnk_X1.vgtest \
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-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_lnk_Y1.vgtest \
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-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mf_X1.vgtest \
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-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mm_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mnz_X0.stdout.exp insn_test_mnz_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mnz_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mnz_X1.stdout.exp insn_test_mnz_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mnz_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mnz_Y0.stdout.exp insn_test_mnz_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mnz_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mnz_Y1.stdout.exp insn_test_mnz_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mnz_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_hs_hs_X0.stdout.exp insn_test_mul_hs_hs_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_hs_hs_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_hs_hs_Y0.stdout.exp insn_test_mul_hs_hs_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_hs_hs_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_hs_hu_X0.stdout.exp insn_test_mul_hs_hu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_hs_hu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_hs_ls_X0.stdout.exp insn_test_mul_hs_ls_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_hs_ls_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_hs_lu_X0.stdout.exp insn_test_mul_hs_lu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_hs_lu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_hu_hu_X0.stdout.exp insn_test_mul_hu_hu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_hu_hu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_hu_hu_Y0.stdout.exp insn_test_mul_hu_hu_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_hu_hu_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_hu_lu_X0.stdout.exp insn_test_mul_hu_lu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_hu_lu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_ls_ls_X0.stdout.exp insn_test_mul_ls_ls_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_ls_ls_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_ls_ls_Y0.stdout.exp insn_test_mul_ls_ls_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_ls_ls_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_ls_lu_X0.stdout.exp insn_test_mul_ls_lu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_ls_lu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_lu_lu_X0.stdout.exp insn_test_mul_lu_lu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_lu_lu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_lu_lu_Y0.stdout.exp insn_test_mul_lu_lu_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mul_lu_lu_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_hs_hs_X0.stdout.exp insn_test_mula_hs_hs_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_hs_hs_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_hs_hs_Y0.stdout.exp insn_test_mula_hs_hs_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_hs_hs_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_hs_hu_X0.stdout.exp insn_test_mula_hs_hu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_hs_hu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_hs_ls_X0.stdout.exp insn_test_mula_hs_ls_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_hs_ls_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_hs_lu_X0.stdout.exp insn_test_mula_hs_lu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_hs_lu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_hu_hu_X0.stdout.exp insn_test_mula_hu_hu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_hu_hu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_hu_hu_Y0.stdout.exp insn_test_mula_hu_hu_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_hu_hu_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_hu_ls_X0.stdout.exp insn_test_mula_hu_ls_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_hu_ls_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_hu_lu_X0.stdout.exp insn_test_mula_hu_lu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_hu_lu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_ls_ls_X0.stdout.exp insn_test_mula_ls_ls_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_ls_ls_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_ls_ls_Y0.stdout.exp insn_test_mula_ls_ls_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_ls_ls_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_ls_lu_X0.stdout.exp insn_test_mula_ls_lu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_ls_lu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_lu_lu_X0.stdout.exp insn_test_mula_lu_lu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_lu_lu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_lu_lu_Y0.stdout.exp insn_test_mula_lu_lu_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mula_lu_lu_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mulax_X0.stdout.exp insn_test_mulax_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mulax_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mulax_Y0.stdout.exp insn_test_mulax_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mulax_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mulx_X0.stdout.exp insn_test_mulx_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mulx_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mulx_Y0.stdout.exp insn_test_mulx_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mulx_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mz_X0.stdout.exp insn_test_mz_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mz_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mz_X1.stdout.exp insn_test_mz_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mz_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mz_Y0.stdout.exp insn_test_mz_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mz_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mz_Y1.stdout.exp insn_test_mz_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_mz_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_nop_X0.stdout.exp insn_test_nop_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_nop_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_nop_X1.stdout.exp insn_test_nop_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_nop_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_nop_Y0.stdout.exp insn_test_nop_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_nop_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_nop_Y1.stdout.exp insn_test_nop_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_nop_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_nor_X0.stdout.exp insn_test_nor_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_nor_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_nor_X1.stdout.exp insn_test_nor_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_nor_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_nor_Y0.stdout.exp insn_test_nor_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_nor_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_nor_Y1.stdout.exp insn_test_nor_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_nor_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_or_X0.stdout.exp insn_test_or_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_or_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_or_X1.stdout.exp insn_test_or_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_or_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_or_Y0.stdout.exp insn_test_or_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_or_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_or_Y1.stdout.exp insn_test_or_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_or_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ori_X0.stdout.exp insn_test_ori_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ori_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ori_X1.stdout.exp insn_test_ori_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_ori_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_pcnt_X0.stdout.exp insn_test_pcnt_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_pcnt_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_pcnt_Y0.stdout.exp insn_test_pcnt_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_pcnt_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_revbits_X0.stdout.exp insn_test_revbits_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_revbits_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_revbits_Y0.stdout.exp insn_test_revbits_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_revbits_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_revbytes_X0.stdout.exp insn_test_revbytes_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_revbytes_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_revbytes_Y0.stdout.exp insn_test_revbytes_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_revbytes_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_rotl_X0.stdout.exp insn_test_rotl_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_rotl_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_rotl_X1.stdout.exp insn_test_rotl_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_rotl_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_rotl_Y0.stdout.exp insn_test_rotl_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_rotl_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_rotl_Y1.stdout.exp insn_test_rotl_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_rotl_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_rotli_X0.stdout.exp insn_test_rotli_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_rotli_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_rotli_X1.stdout.exp insn_test_rotli_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_rotli_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_rotli_Y0.stdout.exp insn_test_rotli_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_rotli_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_rotli_Y1.stdout.exp insn_test_rotli_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_rotli_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl_X0.stdout.exp insn_test_shl_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl_X1.stdout.exp insn_test_shl_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl_Y0.stdout.exp insn_test_shl_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl_Y1.stdout.exp insn_test_shl_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl16insli_X0.stdout.exp insn_test_shl16insli_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl16insli_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl16insli_X1.stdout.exp insn_test_shl16insli_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl16insli_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl1add_X0.stdout.exp insn_test_shl1add_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl1add_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl1add_X1.stdout.exp insn_test_shl1add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl1add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl1add_Y0.stdout.exp insn_test_shl1add_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl1add_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl1add_Y1.stdout.exp insn_test_shl1add_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl1add_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl1addx_X0.stdout.exp insn_test_shl1addx_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl1addx_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl1addx_X1.stdout.exp insn_test_shl1addx_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl1addx_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl1addx_Y0.stdout.exp insn_test_shl1addx_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl1addx_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl1addx_Y1.stdout.exp insn_test_shl1addx_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl1addx_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl2add_X0.stdout.exp insn_test_shl2add_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl2add_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl2add_X1.stdout.exp insn_test_shl2add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl2add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl2add_Y0.stdout.exp insn_test_shl2add_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl2add_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl2add_Y1.stdout.exp insn_test_shl2add_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl2add_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl2addx_X0.stdout.exp insn_test_shl2addx_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl2addx_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl2addx_X1.stdout.exp insn_test_shl2addx_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl2addx_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl2addx_Y0.stdout.exp insn_test_shl2addx_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl2addx_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl2addx_Y1.stdout.exp insn_test_shl2addx_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl2addx_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl3add_X0.stdout.exp insn_test_shl3add_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl3add_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl3add_X1.stdout.exp insn_test_shl3add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl3add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl3add_Y0.stdout.exp insn_test_shl3add_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl3add_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl3add_Y1.stdout.exp insn_test_shl3add_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl3add_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl3addx_X0.stdout.exp insn_test_shl3addx_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl3addx_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl3addx_X1.stdout.exp insn_test_shl3addx_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl3addx_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl3addx_Y0.stdout.exp insn_test_shl3addx_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl3addx_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl3addx_Y1.stdout.exp insn_test_shl3addx_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shl3addx_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shli_X0.stdout.exp insn_test_shli_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shli_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shli_X1.stdout.exp insn_test_shli_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shli_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shli_Y0.stdout.exp insn_test_shli_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shli_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shli_Y1.stdout.exp insn_test_shli_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shli_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shlx_X0.stdout.exp insn_test_shlx_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shlx_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shlx_X1.stdout.exp insn_test_shlx_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shlx_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shlxi_X0.stdout.exp insn_test_shlxi_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shlxi_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shlxi_X1.stdout.exp insn_test_shlxi_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shlxi_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrs_X0.stdout.exp insn_test_shrs_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrs_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrs_X1.stdout.exp insn_test_shrs_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrs_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrs_Y0.stdout.exp insn_test_shrs_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrs_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrs_Y1.stdout.exp insn_test_shrs_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrs_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrsi_X0.stdout.exp insn_test_shrsi_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrsi_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrsi_X1.stdout.exp insn_test_shrsi_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrsi_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrsi_Y0.stdout.exp insn_test_shrsi_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrsi_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrsi_Y1.stdout.exp insn_test_shrsi_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrsi_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shru_X0.stdout.exp insn_test_shru_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shru_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shru_X1.stdout.exp insn_test_shru_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shru_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shru_Y0.stdout.exp insn_test_shru_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shru_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shru_Y1.stdout.exp insn_test_shru_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shru_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrui_X0.stdout.exp insn_test_shrui_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrui_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrui_X1.stdout.exp insn_test_shrui_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrui_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrui_Y0.stdout.exp insn_test_shrui_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrui_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrui_Y1.stdout.exp insn_test_shrui_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrui_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrux_X0.stdout.exp insn_test_shrux_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrux_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrux_X1.stdout.exp insn_test_shrux_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shrux_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shufflebytes_X0.stdout.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shufflebytes_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_shufflebytes_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_st_X1.stdout.exp insn_test_st_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_st_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_st_Y2.stdout.exp insn_test_st_Y2.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_st_Y2.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_st1_X1.stdout.exp insn_test_st1_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_st1_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_st1_Y2.stdout.exp insn_test_st1_Y2.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_st1_Y2.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_st1_add_X1.stdout.exp insn_test_st1_add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_st1_add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_st2_X1.stdout.exp insn_test_st2_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_st2_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_st2_Y2.stdout.exp insn_test_st2_Y2.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_st2_Y2.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_st2_add_X1.stdout.exp insn_test_st2_add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_st2_add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_st4_X1.stdout.exp insn_test_st4_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_st4_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_st4_Y2.stdout.exp insn_test_st4_Y2.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_st4_Y2.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_st4_add_X1.stdout.exp insn_test_st4_add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_st4_add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_st_add_X1.stdout.exp insn_test_st_add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_st_add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_stnt_X1.stdout.exp insn_test_stnt_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_stnt_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_stnt1_X1.stdout.exp insn_test_stnt1_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_stnt1_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_stnt2_X1.stdout.exp insn_test_stnt2_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_stnt2_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_stnt2_add_X1.stdout.exp insn_test_stnt2_add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_stnt2_add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_stnt4_X1.stdout.exp insn_test_stnt4_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_stnt4_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_stnt4_add_X1.stdout.exp insn_test_stnt4_add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_stnt4_add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_stnt_add_X1.stdout.exp insn_test_stnt_add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_stnt_add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_sub_X0.stdout.exp insn_test_sub_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_sub_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_sub_X1.stdout.exp insn_test_sub_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_sub_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_sub_Y0.stdout.exp insn_test_sub_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_sub_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_sub_Y1.stdout.exp insn_test_sub_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_sub_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_subx_X0.stdout.exp insn_test_subx_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_subx_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_subx_X1.stdout.exp insn_test_subx_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_subx_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_subx_Y0.stdout.exp insn_test_subx_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_subx_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_subx_Y1.stdout.exp insn_test_subx_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_subx_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_tblidxb0_X0.stdout.exp insn_test_tblidxb0_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_tblidxb0_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_tblidxb0_Y0.stdout.exp insn_test_tblidxb0_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_tblidxb0_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_tblidxb1_X0.stdout.exp insn_test_tblidxb1_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_tblidxb1_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_tblidxb1_Y0.stdout.exp insn_test_tblidxb1_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_tblidxb1_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_tblidxb2_X0.stdout.exp insn_test_tblidxb2_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_tblidxb2_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_tblidxb2_Y0.stdout.exp insn_test_tblidxb2_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_tblidxb2_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_tblidxb3_X0.stdout.exp insn_test_tblidxb3_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_tblidxb3_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_tblidxb3_Y0.stdout.exp insn_test_tblidxb3_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_tblidxb3_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1add_X0.stdout.exp insn_test_v1add_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1add_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1add_X1.stdout.exp insn_test_v1add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1adduc_X0.stdout.exp insn_test_v1adduc_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1adduc_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1adduc_X1.stdout.exp insn_test_v1adduc_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1adduc_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1adiffu_X0.stdout.exp insn_test_v1adiffu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1adiffu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1avgu_X0.stdout.exp insn_test_v1avgu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1avgu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmpeq_X0.stdout.exp insn_test_v1cmpeq_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmpeq_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmpeq_X1.stdout.exp insn_test_v1cmpeq_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmpeq_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmpeqi_X0.stdout.exp insn_test_v1cmpeqi_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmpeqi_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmpeqi_X1.stdout.exp insn_test_v1cmpeqi_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmpeqi_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmples_X0.stdout.exp insn_test_v1cmples_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmples_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmples_X1.stdout.exp insn_test_v1cmples_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmples_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmpleu_X0.stdout.exp insn_test_v1cmpleu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmpleu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmpleu_X1.stdout.exp insn_test_v1cmpleu_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmpleu_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmplts_X0.stdout.exp insn_test_v1cmplts_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmplts_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmplts_X1.stdout.exp insn_test_v1cmplts_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmplts_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmpltu_X0.stdout.exp insn_test_v1cmpltu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmpltu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmpltu_X1.stdout.exp insn_test_v1cmpltu_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmpltu_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmpne_X0.stdout.exp insn_test_v1cmpne_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmpne_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmpne_X1.stdout.exp insn_test_v1cmpne_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1cmpne_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1ddotpu_X0.stdout.exp insn_test_v1ddotpu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1ddotpu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1ddotpua_X0.stdout.exp insn_test_v1ddotpua_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1ddotpua_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1ddotpus_X0.stdout.exp insn_test_v1ddotpus_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1ddotpus_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1ddotpusa_X0.stdout.exp insn_test_v1ddotpusa_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1ddotpusa_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1dotp_X0.stdout.exp insn_test_v1dotp_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1dotp_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1dotpa_X0.stdout.exp insn_test_v1dotpa_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1dotpa_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1dotpu_X0.stdout.exp insn_test_v1dotpu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1dotpu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1dotpua_X0.stdout.exp insn_test_v1dotpua_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1dotpua_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1dotpus_X0.stdout.exp insn_test_v1dotpus_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1dotpus_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1dotpusa_X0.stdout.exp insn_test_v1dotpusa_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1dotpusa_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1int_h_X0.stdout.exp insn_test_v1int_h_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1int_h_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1int_h_X1.stdout.exp insn_test_v1int_h_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1int_h_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1int_l_X0.stdout.exp insn_test_v1int_l_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1int_l_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1int_l_X1.stdout.exp insn_test_v1int_l_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1int_l_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1maxu_X0.stdout.exp insn_test_v1maxu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1maxu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1maxu_X1.stdout.exp insn_test_v1maxu_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1maxu_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1minu_X0.stdout.exp insn_test_v1minu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1minu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1minu_X1.stdout.exp insn_test_v1minu_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1minu_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1mnz_X0.stdout.exp insn_test_v1mnz_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1mnz_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1mnz_X1.stdout.exp insn_test_v1mnz_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1mnz_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1multu_X0.stdout.exp insn_test_v1multu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1multu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1mulu_X0.stdout.exp insn_test_v1mulu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1mulu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1mulus_X0.stdout.exp insn_test_v1mulus_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1mulus_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1mz_X0.stdout.exp insn_test_v1mz_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1mz_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1mz_X1.stdout.exp insn_test_v1mz_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1mz_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1sadau_X0.stdout.exp insn_test_v1sadau_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1sadau_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1sadu_X0.stdout.exp insn_test_v1sadu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1sadu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1shl_X0.stdout.exp insn_test_v1shl_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1shl_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1shl_X1.stdout.exp insn_test_v1shl_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1shl_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1shli_X0.stdout.exp insn_test_v1shli_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1shli_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1shli_X1.stdout.exp insn_test_v1shli_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1shli_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1shrs_X0.stdout.exp insn_test_v1shrs_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1shrs_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1shrs_X1.stdout.exp insn_test_v1shrs_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1shrs_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1shrsi_X0.stdout.exp insn_test_v1shrsi_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1shrsi_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1shrsi_X1.stdout.exp insn_test_v1shrsi_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1shrsi_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1shru_X0.stdout.exp insn_test_v1shru_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1shru_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1shru_X1.stdout.exp insn_test_v1shru_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1shru_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1shrui_X0.stdout.exp insn_test_v1shrui_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1shrui_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1shrui_X1.stdout.exp insn_test_v1shrui_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1shrui_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1sub_X0.stdout.exp insn_test_v1sub_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1sub_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1sub_X1.stdout.exp insn_test_v1sub_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1sub_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1subuc_X0.stdout.exp insn_test_v1subuc_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1subuc_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1subuc_X1.stdout.exp insn_test_v1subuc_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v1subuc_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2add_X0.stdout.exp insn_test_v2add_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2add_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2add_X1.stdout.exp insn_test_v2add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2addsc_X0.stdout.exp insn_test_v2addsc_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2addsc_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2addsc_X1.stdout.exp insn_test_v2addsc_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2addsc_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2adiffs_X0.stdout.exp insn_test_v2adiffs_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2adiffs_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2avgs_X0.stdout.exp insn_test_v2avgs_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2avgs_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpeq_X0.stdout.exp insn_test_v2cmpeq_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpeq_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpeq_X1.stdout.exp insn_test_v2cmpeq_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpeq_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpeqi_X0.stdout.exp insn_test_v2cmpeqi_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpeqi_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpeqi_X1.stdout.exp insn_test_v2cmpeqi_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpeqi_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmples_X0.stdout.exp insn_test_v2cmples_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmples_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmples_X1.stdout.exp insn_test_v2cmples_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmples_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpleu_X0.stdout.exp insn_test_v2cmpleu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpleu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpleu_X1.stdout.exp insn_test_v2cmpleu_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpleu_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmplts_X0.stdout.exp insn_test_v2cmplts_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmplts_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmplts_X1.stdout.exp insn_test_v2cmplts_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmplts_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpltsi_X0.stdout.exp insn_test_v2cmpltsi_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpltsi_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpltsi_X1.stdout.exp insn_test_v2cmpltsi_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpltsi_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpltu_X0.stdout.exp insn_test_v2cmpltu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpltu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpltu_X1.stdout.exp insn_test_v2cmpltu_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpltu_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpltui_X0.stdout.exp insn_test_v2cmpltui_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpltui_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpltui_X1.stdout.exp insn_test_v2cmpltui_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpltui_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpne_X0.stdout.exp insn_test_v2cmpne_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpne_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpne_X1.stdout.exp insn_test_v2cmpne_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2cmpne_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2dotp_X0.stdout.exp insn_test_v2dotp_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2dotp_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2dotpa_X0.stdout.exp insn_test_v2dotpa_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2dotpa_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2int_h_X0.stdout.exp insn_test_v2int_h_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2int_h_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2int_h_X1.stdout.exp insn_test_v2int_h_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2int_h_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2int_l_X0.stdout.exp insn_test_v2int_l_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2int_l_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2int_l_X1.stdout.exp insn_test_v2int_l_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2int_l_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2maxs_X0.stdout.exp insn_test_v2maxs_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2maxs_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2maxs_X1.stdout.exp insn_test_v2maxs_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2maxs_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2mins_X0.stdout.exp insn_test_v2mins_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2mins_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2mins_X1.stdout.exp insn_test_v2mins_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2mins_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2mnz_X0.stdout.exp insn_test_v2mnz_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2mnz_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2mnz_X1.stdout.exp insn_test_v2mnz_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2mnz_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2mulfsc_X0.stdout.exp insn_test_v2mulfsc_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2mulfsc_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2muls_X0.stdout.exp insn_test_v2muls_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2muls_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2mults_X0.stdout.exp insn_test_v2mults_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2mults_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2mz_X0.stdout.exp insn_test_v2mz_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2mz_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2mz_X1.stdout.exp insn_test_v2mz_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2mz_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2packh_X0.stdout.exp insn_test_v2packh_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2packh_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2packh_X1.stdout.exp insn_test_v2packh_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2packh_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2packl_X0.stdout.exp insn_test_v2packl_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2packl_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2packl_X1.stdout.exp insn_test_v2packl_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2packl_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2packuc_X0.stdout.exp insn_test_v2packuc_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2packuc_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2packuc_X1.stdout.exp insn_test_v2packuc_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2packuc_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2sadas_X0.stdout.exp insn_test_v2sadas_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2sadas_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2sadau_X0.stdout.exp insn_test_v2sadau_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2sadau_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2sads_X0.stdout.exp insn_test_v2sads_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2sads_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2sadu_X0.stdout.exp insn_test_v2sadu_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2sadu_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shl_X0.stdout.exp insn_test_v2shl_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shl_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shl_X1.stdout.exp insn_test_v2shl_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shl_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shli_X0.stdout.exp insn_test_v2shli_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shli_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shli_X1.stdout.exp insn_test_v2shli_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shli_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shlsc_X0.stdout.exp insn_test_v2shlsc_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shlsc_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shlsc_X1.stdout.exp insn_test_v2shlsc_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shlsc_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shrs_X0.stdout.exp insn_test_v2shrs_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shrs_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shrs_X1.stdout.exp insn_test_v2shrs_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shrs_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shrsi_X0.stdout.exp insn_test_v2shrsi_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shrsi_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shrsi_X1.stdout.exp insn_test_v2shrsi_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shrsi_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shru_X0.stdout.exp insn_test_v2shru_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shru_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shru_X1.stdout.exp insn_test_v2shru_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shru_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shrui_X0.stdout.exp insn_test_v2shrui_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shrui_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shrui_X1.stdout.exp insn_test_v2shrui_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2shrui_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2sub_X0.stdout.exp insn_test_v2sub_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2sub_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2sub_X1.stdout.exp insn_test_v2sub_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2sub_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2subsc_X0.stdout.exp insn_test_v2subsc_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2subsc_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2subsc_X1.stdout.exp insn_test_v2subsc_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2subsc_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4add_X0.stdout.exp insn_test_v4add_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4add_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4add_X1.stdout.exp insn_test_v4add_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4add_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4addsc_X0.stdout.exp insn_test_v4addsc_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4addsc_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4addsc_X1.stdout.exp insn_test_v4addsc_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4addsc_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4int_h_X0.stdout.exp insn_test_v4int_h_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4int_h_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4int_h_X1.stdout.exp insn_test_v4int_h_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4int_h_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4int_l_X0.stdout.exp insn_test_v4int_l_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4int_l_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4int_l_X1.stdout.exp insn_test_v4int_l_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4int_l_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4packsc_X0.stdout.exp insn_test_v4packsc_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4packsc_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4packsc_X1.stdout.exp insn_test_v4packsc_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4packsc_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shl_X0.stdout.exp insn_test_v4shl_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shl_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shl_X1.stdout.exp insn_test_v4shl_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shl_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shlsc_X0.stdout.exp insn_test_v4shlsc_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shlsc_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shlsc_X1.stdout.exp insn_test_v4shlsc_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shlsc_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shrs_X0.stdout.exp insn_test_v4shrs_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shrs_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shrs_X1.stdout.exp insn_test_v4shrs_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shrs_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shru_X0.stdout.exp insn_test_v4shru_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shru_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shru_X1.stdout.exp insn_test_v4shru_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shru_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4sub_X0.stdout.exp insn_test_v4sub_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4sub_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4sub_X1.stdout.exp insn_test_v4sub_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4sub_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4subsc_X0.stdout.exp insn_test_v4subsc_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4subsc_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4subsc_X1.stdout.exp insn_test_v4subsc_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4subsc_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_wh64_X1.stdout.exp insn_test_wh64_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_wh64_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_xor_X0.stdout.exp insn_test_xor_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_xor_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_xor_X1.stdout.exp insn_test_xor_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_xor_X1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_xor_Y0.stdout.exp insn_test_xor_Y0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_xor_Y0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_xor_Y1.stdout.exp insn_test_xor_Y1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_xor_Y1.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_xori_X0.stdout.exp insn_test_xori_X0.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_xori_X0.vgtest \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_xori_X1.stdout.exp insn_test_xori_X1.stderr.exp \
-@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_xori_X1.vgtest
-
-bin_PROGRAMS = gen_insn_test$(EXEEXT)
-check_PROGRAMS = allexec$(EXEEXT) $(am__EXEEXT_1)
-subdir = none/tests/tilegx
-ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
-am__aclocal_m4_deps = $(top_srcdir)/configure.ac
-am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
- $(ACLOCAL_M4)
-DIST_COMMON = $(srcdir)/Makefile.am $(dist_noinst_SCRIPTS) \
- $(am__DIST_COMMON)
-mkinstalldirs = $(install_sh) -d
-CONFIG_HEADER = $(top_builddir)/config.h
-CONFIG_CLEAN_FILES =
-CONFIG_CLEAN_VPATH_FILES =
-am__installdirs = "$(DESTDIR)$(bindir)"
-am__EXEEXT_1 = insn_test_move_X0$(EXEEXT) insn_test_move_X1$(EXEEXT) \
- insn_test_move_Y0$(EXEEXT) insn_test_move_Y1$(EXEEXT) \
- insn_test_movei_X0$(EXEEXT) insn_test_movei_X1$(EXEEXT) \
- insn_test_movei_Y0$(EXEEXT) insn_test_movei_Y1$(EXEEXT) \
- insn_test_moveli_X0$(EXEEXT) insn_test_moveli_X1$(EXEEXT) \
- insn_test_prefetch_X1$(EXEEXT) insn_test_prefetch_Y2$(EXEEXT) \
- insn_test_prefetch_l1_X1$(EXEEXT) \
- insn_test_prefetch_l1_Y2$(EXEEXT) \
- insn_test_prefetch_l2_X1$(EXEEXT) \
- insn_test_prefetch_l2_Y2$(EXEEXT) \
- insn_test_prefetch_l3_X1$(EXEEXT) \
- insn_test_prefetch_l3_Y2$(EXEEXT) insn_test_add_X0$(EXEEXT) \
- insn_test_add_X1$(EXEEXT) insn_test_add_Y0$(EXEEXT) \
- insn_test_add_Y1$(EXEEXT) insn_test_addi_X0$(EXEEXT) \
- insn_test_addi_X1$(EXEEXT) insn_test_addi_Y0$(EXEEXT) \
- insn_test_addi_Y1$(EXEEXT) insn_test_addli_X0$(EXEEXT) \
- insn_test_addli_X1$(EXEEXT) insn_test_addx_X0$(EXEEXT) \
- insn_test_addx_X1$(EXEEXT) insn_test_addx_Y0$(EXEEXT) \
- insn_test_addx_Y1$(EXEEXT) insn_test_addxi_X0$(EXEEXT) \
- insn_test_addxi_X1$(EXEEXT) insn_test_addxi_Y0$(EXEEXT) \
- insn_test_addxi_Y1$(EXEEXT) insn_test_addxli_X0$(EXEEXT) \
- insn_test_addxli_X1$(EXEEXT) insn_test_addxsc_X0$(EXEEXT) \
- insn_test_addxsc_X1$(EXEEXT) insn_test_and_X0$(EXEEXT) \
- insn_test_and_X1$(EXEEXT) insn_test_and_Y0$(EXEEXT) \
- insn_test_and_Y1$(EXEEXT) insn_test_andi_X0$(EXEEXT) \
- insn_test_andi_X1$(EXEEXT) insn_test_andi_Y0$(EXEEXT) \
- insn_test_andi_Y1$(EXEEXT) insn_test_beqz_X1$(EXEEXT) \
- insn_test_beqzt_X1$(EXEEXT) insn_test_bfexts_X0$(EXEEXT) \
- insn_test_bfextu_X0$(EXEEXT) insn_test_bfins_X0$(EXEEXT) \
- insn_test_bgez_X1$(EXEEXT) insn_test_bgezt_X1$(EXEEXT) \
- insn_test_bgtz_X1$(EXEEXT) insn_test_bgtzt_X1$(EXEEXT) \
- insn_test_blbc_X1$(EXEEXT) insn_test_blbct_X1$(EXEEXT) \
- insn_test_blbs_X1$(EXEEXT) insn_test_blbst_X1$(EXEEXT) \
- insn_test_blez_X1$(EXEEXT) insn_test_blezt_X1$(EXEEXT) \
- insn_test_bltz_X1$(EXEEXT) insn_test_bltzt_X1$(EXEEXT) \
- insn_test_bnez_X1$(EXEEXT) insn_test_bnezt_X1$(EXEEXT) \
- insn_test_clz_X0$(EXEEXT) insn_test_clz_Y0$(EXEEXT) \
- insn_test_cmoveqz_X0$(EXEEXT) insn_test_cmoveqz_Y0$(EXEEXT) \
- insn_test_cmovnez_X0$(EXEEXT) insn_test_cmovnez_Y0$(EXEEXT) \
- insn_test_cmpeq_X0$(EXEEXT) insn_test_cmpeq_X1$(EXEEXT) \
- insn_test_cmpeq_Y0$(EXEEXT) insn_test_cmpeq_Y1$(EXEEXT) \
- insn_test_cmpeqi_X0$(EXEEXT) insn_test_cmpeqi_X1$(EXEEXT) \
- insn_test_cmpeqi_Y0$(EXEEXT) insn_test_cmpeqi_Y1$(EXEEXT) \
- insn_test_cmples_X0$(EXEEXT) insn_test_cmples_X1$(EXEEXT) \
- insn_test_cmples_Y0$(EXEEXT) insn_test_cmples_Y1$(EXEEXT) \
- insn_test_cmpleu_X0$(EXEEXT) insn_test_cmpleu_X1$(EXEEXT) \
- insn_test_cmpleu_Y0$(EXEEXT) insn_test_cmpleu_Y1$(EXEEXT) \
- insn_test_cmplts_X0$(EXEEXT) insn_test_cmplts_X1$(EXEEXT) \
- insn_test_cmplts_Y0$(EXEEXT) insn_test_cmplts_Y1$(EXEEXT) \
- insn_test_cmpltsi_X0$(EXEEXT) insn_test_cmpltsi_X1$(EXEEXT) \
- insn_test_cmpltsi_Y0$(EXEEXT) insn_test_cmpltsi_Y1$(EXEEXT) \
- insn_test_cmpltu_X0$(EXEEXT) insn_test_cmpltu_X1$(EXEEXT) \
- insn_test_cmpltu_Y0$(EXEEXT) insn_test_cmpltu_Y1$(EXEEXT) \
- insn_test_cmpltui_X0$(EXEEXT) insn_test_cmpltui_X1$(EXEEXT) \
- insn_test_cmpne_X0$(EXEEXT) insn_test_cmpne_X1$(EXEEXT) \
- insn_test_cmpne_Y0$(EXEEXT) insn_test_cmpne_Y1$(EXEEXT) \
- insn_test_cmul_X0$(EXEEXT) insn_test_cmula_X0$(EXEEXT) \
- insn_test_cmulaf_X0$(EXEEXT) insn_test_cmulf_X0$(EXEEXT) \
- insn_test_cmulfr_X0$(EXEEXT) insn_test_cmulh_X0$(EXEEXT) \
- insn_test_cmulhr_X0$(EXEEXT) insn_test_crc32_32_X0$(EXEEXT) \
- insn_test_crc32_8_X0$(EXEEXT) insn_test_ctz_X0$(EXEEXT) \
- insn_test_ctz_Y0$(EXEEXT) insn_test_dblalign_X0$(EXEEXT) \
- insn_test_dblalign2_X0$(EXEEXT) \
- insn_test_dblalign2_X1$(EXEEXT) \
- insn_test_dblalign4_X0$(EXEEXT) \
- insn_test_dblalign4_X1$(EXEEXT) \
- insn_test_dblalign6_X0$(EXEEXT) \
- insn_test_dblalign6_X1$(EXEEXT) insn_test_dtlbpr_X1$(EXEEXT) \
- insn_test_fdouble_add_flags_X0$(EXEEXT) \
- insn_test_fdouble_addsub_X0$(EXEEXT) \
- insn_test_fdouble_mul_flags_X0$(EXEEXT) \
- insn_test_fdouble_pack1_X0$(EXEEXT) \
- insn_test_fdouble_pack2_X0$(EXEEXT) \
- insn_test_fdouble_sub_flags_X0$(EXEEXT) \
- insn_test_fdouble_unpack_max_X0$(EXEEXT) \
- insn_test_fdouble_unpack_min_X0$(EXEEXT) \
- insn_test_flushwb_X1$(EXEEXT) insn_test_fnop_X0$(EXEEXT) \
- insn_test_fnop_X1$(EXEEXT) insn_test_fnop_Y0$(EXEEXT) \
- insn_test_fnop_Y1$(EXEEXT) insn_test_fsingle_add1_X0$(EXEEXT) \
- insn_test_fsingle_addsub2_X0$(EXEEXT) \
- insn_test_fsingle_mul1_X0$(EXEEXT) \
- insn_test_fsingle_mul2_X0$(EXEEXT) \
- insn_test_fsingle_pack1_X0$(EXEEXT) \
- insn_test_fsingle_pack1_Y0$(EXEEXT) \
- insn_test_fsingle_pack2_X0$(EXEEXT) \
- insn_test_fsingle_sub1_X0$(EXEEXT) insn_test_icoh_X1$(EXEEXT) \
- insn_test_j_X1$(EXEEXT) insn_test_jal_X1$(EXEEXT) \
- insn_test_jalr_X1$(EXEEXT) insn_test_jalr_Y1$(EXEEXT) \
- insn_test_jalrp_X1$(EXEEXT) insn_test_jalrp_Y1$(EXEEXT) \
- insn_test_jr_X1$(EXEEXT) insn_test_jr_Y1$(EXEEXT) \
- insn_test_jrp_X1$(EXEEXT) insn_test_jrp_Y1$(EXEEXT) \
- insn_test_ld_X1$(EXEEXT) insn_test_ld_Y2$(EXEEXT) \
- insn_test_ld1s_X1$(EXEEXT) insn_test_ld1s_Y2$(EXEEXT) \
- insn_test_ld1s_add_X1$(EXEEXT) insn_test_ld1u_X1$(EXEEXT) \
- insn_test_ld1u_Y2$(EXEEXT) insn_test_ld1u_add_X1$(EXEEXT) \
- insn_test_ld2s_X1$(EXEEXT) insn_test_ld2s_Y2$(EXEEXT) \
- insn_test_ld2u_X1$(EXEEXT) insn_test_ld2u_Y2$(EXEEXT) \
- insn_test_ld4s_X1$(EXEEXT) insn_test_ld4s_add_X1$(EXEEXT) \
- insn_test_ld4u_X1$(EXEEXT) insn_test_ld4u_Y2$(EXEEXT) \
- insn_test_ld4u_add_X1$(EXEEXT) insn_test_ld_add_X1$(EXEEXT) \
- insn_test_ldna_X1$(EXEEXT) insn_test_ldna_add_X1$(EXEEXT) \
- insn_test_ldnt_X1$(EXEEXT) insn_test_ldnt1s_X1$(EXEEXT) \
- insn_test_ldnt1s_add_X1$(EXEEXT) insn_test_ldnt1u_X1$(EXEEXT) \
- insn_test_ldnt1u_add_X1$(EXEEXT) insn_test_ldnt2s_X1$(EXEEXT) \
- insn_test_ldnt2s_add_X1$(EXEEXT) \
- insn_test_ldnt2u_add_X1$(EXEEXT) insn_test_ldnt4s_X1$(EXEEXT) \
- insn_test_ldnt4s_add_X1$(EXEEXT) insn_test_ldnt4u_X1$(EXEEXT) \
- insn_test_ldnt4u_add_X1$(EXEEXT) \
- insn_test_ldnt_add_X1$(EXEEXT) insn_test_lnk_X1$(EXEEXT) \
- insn_test_lnk_Y1$(EXEEXT) insn_test_mf_X1$(EXEEXT) \
- insn_test_mm_X0$(EXEEXT) insn_test_mnz_X0$(EXEEXT) \
- insn_test_mnz_X1$(EXEEXT) insn_test_mnz_Y0$(EXEEXT) \
- insn_test_mnz_Y1$(EXEEXT) insn_test_mul_hs_hs_X0$(EXEEXT) \
- insn_test_mul_hs_hs_Y0$(EXEEXT) \
- insn_test_mul_hs_hu_X0$(EXEEXT) \
- insn_test_mul_hs_ls_X0$(EXEEXT) \
- insn_test_mul_hs_lu_X0$(EXEEXT) \
- insn_test_mul_hu_hu_X0$(EXEEXT) \
- insn_test_mul_hu_hu_Y0$(EXEEXT) \
- insn_test_mul_hu_lu_X0$(EXEEXT) \
- insn_test_mul_ls_ls_X0$(EXEEXT) \
- insn_test_mul_ls_ls_Y0$(EXEEXT) \
- insn_test_mul_ls_lu_X0$(EXEEXT) \
- insn_test_mul_lu_lu_X0$(EXEEXT) \
- insn_test_mul_lu_lu_Y0$(EXEEXT) \
- insn_test_mula_hs_hs_X0$(EXEEXT) \
- insn_test_mula_hs_hs_Y0$(EXEEXT) \
- insn_test_mula_hs_hu_X0$(EXEEXT) \
- insn_test_mula_hs_ls_X0$(EXEEXT) \
- insn_test_mula_hs_lu_X0$(EXEEXT) \
- insn_test_mula_hu_hu_X0$(EXEEXT) \
- insn_test_mula_hu_hu_Y0$(EXEEXT) \
- insn_test_mula_hu_ls_X0$(EXEEXT) \
- insn_test_mula_hu_lu_X0$(EXEEXT) \
- insn_test_mula_ls_ls_X0$(EXEEXT) \
- insn_test_mula_ls_ls_Y0$(EXEEXT) \
- insn_test_mula_ls_lu_X0$(EXEEXT) \
- insn_test_mula_lu_lu_X0$(EXEEXT) \
- insn_test_mula_lu_lu_Y0$(EXEEXT) insn_test_mulax_X0$(EXEEXT) \
- insn_test_mulax_Y0$(EXEEXT) insn_test_mulx_X0$(EXEEXT) \
- insn_test_mulx_Y0$(EXEEXT) insn_test_mz_X0$(EXEEXT) \
- insn_test_mz_X1$(EXEEXT) insn_test_mz_Y0$(EXEEXT) \
- insn_test_mz_Y1$(EXEEXT) insn_test_nop_X0$(EXEEXT) \
- insn_test_nop_X1$(EXEEXT) insn_test_nop_Y0$(EXEEXT) \
- insn_test_nop_Y1$(EXEEXT) insn_test_nor_X0$(EXEEXT) \
- insn_test_nor_X1$(EXEEXT) insn_test_nor_Y0$(EXEEXT) \
- insn_test_nor_Y1$(EXEEXT) insn_test_or_X0$(EXEEXT) \
- insn_test_or_X1$(EXEEXT) insn_test_or_Y0$(EXEEXT) \
- insn_test_or_Y1$(EXEEXT) insn_test_ori_X0$(EXEEXT) \
- insn_test_ori_X1$(EXEEXT) insn_test_pcnt_X0$(EXEEXT) \
- insn_test_pcnt_Y0$(EXEEXT) insn_test_revbits_X0$(EXEEXT) \
- insn_test_revbits_Y0$(EXEEXT) insn_test_revbytes_X0$(EXEEXT) \
- insn_test_revbytes_Y0$(EXEEXT) insn_test_rotl_X0$(EXEEXT) \
- insn_test_rotl_X1$(EXEEXT) insn_test_rotl_Y0$(EXEEXT) \
- insn_test_rotl_Y1$(EXEEXT) insn_test_rotli_X0$(EXEEXT) \
- insn_test_rotli_X1$(EXEEXT) insn_test_rotli_Y0$(EXEEXT) \
- insn_test_rotli_Y1$(EXEEXT) insn_test_shl_X0$(EXEEXT) \
- insn_test_shl_X1$(EXEEXT) insn_test_shl_Y0$(EXEEXT) \
- insn_test_shl_Y1$(EXEEXT) insn_test_shl16insli_X0$(EXEEXT) \
- insn_test_shl16insli_X1$(EXEEXT) insn_test_shl1add_X0$(EXEEXT) \
- insn_test_shl1add_X1$(EXEEXT) insn_test_shl1add_Y0$(EXEEXT) \
- insn_test_shl1add_Y1$(EXEEXT) insn_test_shl1addx_X0$(EXEEXT) \
- insn_test_shl1addx_X1$(EXEEXT) insn_test_shl1addx_Y0$(EXEEXT) \
- insn_test_shl1addx_Y1$(EXEEXT) insn_test_shl2add_X0$(EXEEXT) \
- insn_test_shl2add_X1$(EXEEXT) insn_test_shl2add_Y0$(EXEEXT) \
- insn_test_shl2add_Y1$(EXEEXT) insn_test_shl2addx_X0$(EXEEXT) \
- insn_test_shl2addx_X1$(EXEEXT) insn_test_shl2addx_Y0$(EXEEXT) \
- insn_test_shl2addx_Y1$(EXEEXT) insn_test_shl3add_X0$(EXEEXT) \
- insn_test_shl3add_X1$(EXEEXT) insn_test_shl3add_Y0$(EXEEXT) \
- insn_test_shl3add_Y1$(EXEEXT) insn_test_shl3addx_X0$(EXEEXT) \
- insn_test_shl3addx_X1$(EXEEXT) insn_test_shl3addx_Y0$(EXEEXT) \
- insn_test_shl3addx_Y1$(EXEEXT) insn_test_shli_X0$(EXEEXT) \
- insn_test_shli_X1$(EXEEXT) insn_test_shli_Y0$(EXEEXT) \
- insn_test_shli_Y1$(EXEEXT) insn_test_shlx_X0$(EXEEXT) \
- insn_test_shlx_X1$(EXEEXT) insn_test_shlxi_X0$(EXEEXT) \
- insn_test_shlxi_X1$(EXEEXT) insn_test_shrs_X0$(EXEEXT) \
- insn_test_shrs_X1$(EXEEXT) insn_test_shrs_Y0$(EXEEXT) \
- insn_test_shrs_Y1$(EXEEXT) insn_test_shrsi_X0$(EXEEXT) \
- insn_test_shrsi_X1$(EXEEXT) insn_test_shrsi_Y0$(EXEEXT) \
- insn_test_shrsi_Y1$(EXEEXT) insn_test_shru_X0$(EXEEXT) \
- insn_test_shru_X1$(EXEEXT) insn_test_shru_Y0$(EXEEXT) \
- insn_test_shru_Y1$(EXEEXT) insn_test_shrui_X0$(EXEEXT) \
- insn_test_shrui_X1$(EXEEXT) insn_test_shrui_Y0$(EXEEXT) \
- insn_test_shrui_Y1$(EXEEXT) insn_test_shrux_X0$(EXEEXT) \
- insn_test_shrux_X1$(EXEEXT) insn_test_shufflebytes_X0$(EXEEXT) \
- insn_test_st_X1$(EXEEXT) insn_test_st_Y2$(EXEEXT) \
- insn_test_st1_X1$(EXEEXT) insn_test_st1_Y2$(EXEEXT) \
- insn_test_st1_add_X1$(EXEEXT) insn_test_st2_X1$(EXEEXT) \
- insn_test_st2_Y2$(EXEEXT) insn_test_st2_add_X1$(EXEEXT) \
- insn_test_st4_X1$(EXEEXT) insn_test_st4_Y2$(EXEEXT) \
- insn_test_st4_add_X1$(EXEEXT) insn_test_st_add_X1$(EXEEXT) \
- insn_test_stnt_X1$(EXEEXT) insn_test_stnt1_X1$(EXEEXT) \
- insn_test_stnt2_X1$(EXEEXT) insn_test_stnt2_add_X1$(EXEEXT) \
- insn_test_stnt4_X1$(EXEEXT) insn_test_stnt4_add_X1$(EXEEXT) \
- insn_test_stnt_add_X1$(EXEEXT) insn_test_sub_X0$(EXEEXT) \
- insn_test_sub_X1$(EXEEXT) insn_test_sub_Y0$(EXEEXT) \
- insn_test_sub_Y1$(EXEEXT) insn_test_subx_X0$(EXEEXT) \
- insn_test_subx_X1$(EXEEXT) insn_test_subx_Y0$(EXEEXT) \
- insn_test_subx_Y1$(EXEEXT) insn_test_tblidxb0_X0$(EXEEXT) \
- insn_test_tblidxb0_Y0$(EXEEXT) insn_test_tblidxb1_X0$(EXEEXT) \
- insn_test_tblidxb1_Y0$(EXEEXT) insn_test_tblidxb2_X0$(EXEEXT) \
- insn_test_tblidxb2_Y0$(EXEEXT) insn_test_tblidxb3_X0$(EXEEXT) \
- insn_test_tblidxb3_Y0$(EXEEXT) insn_test_v1add_X0$(EXEEXT) \
- insn_test_v1add_X1$(EXEEXT) insn_test_v1adduc_X0$(EXEEXT) \
- insn_test_v1adduc_X1$(EXEEXT) insn_test_v1adiffu_X0$(EXEEXT) \
- insn_test_v1avgu_X0$(EXEEXT) insn_test_v1cmpeq_X0$(EXEEXT) \
- insn_test_v1cmpeq_X1$(EXEEXT) insn_test_v1cmpeqi_X0$(EXEEXT) \
- insn_test_v1cmpeqi_X1$(EXEEXT) insn_test_v1cmples_X0$(EXEEXT) \
- insn_test_v1cmples_X1$(EXEEXT) insn_test_v1cmpleu_X0$(EXEEXT) \
- insn_test_v1cmpleu_X1$(EXEEXT) insn_test_v1cmplts_X0$(EXEEXT) \
- insn_test_v1cmplts_X1$(EXEEXT) insn_test_v1cmpltu_X0$(EXEEXT) \
- insn_test_v1cmpltu_X1$(EXEEXT) insn_test_v1cmpne_X0$(EXEEXT) \
- insn_test_v1cmpne_X1$(EXEEXT) insn_test_v1ddotpu_X0$(EXEEXT) \
- insn_test_v1ddotpua_X0$(EXEEXT) \
- insn_test_v1ddotpus_X0$(EXEEXT) \
- insn_test_v1ddotpusa_X0$(EXEEXT) insn_test_v1dotp_X0$(EXEEXT) \
- insn_test_v1dotpa_X0$(EXEEXT) insn_test_v1dotpu_X0$(EXEEXT) \
- insn_test_v1dotpua_X0$(EXEEXT) insn_test_v1dotpus_X0$(EXEEXT) \
- insn_test_v1dotpusa_X0$(EXEEXT) insn_test_v1int_h_X0$(EXEEXT) \
- insn_test_v1int_h_X1$(EXEEXT) insn_test_v1int_l_X0$(EXEEXT) \
- insn_test_v1int_l_X1$(EXEEXT) insn_test_v1maxu_X0$(EXEEXT) \
- insn_test_v1maxu_X1$(EXEEXT) insn_test_v1minu_X0$(EXEEXT) \
- insn_test_v1minu_X1$(EXEEXT) insn_test_v1mnz_X0$(EXEEXT) \
- insn_test_v1mnz_X1$(EXEEXT) insn_test_v1multu_X0$(EXEEXT) \
- insn_test_v1mulu_X0$(EXEEXT) insn_test_v1mulus_X0$(EXEEXT) \
- insn_test_v1mz_X0$(EXEEXT) insn_test_v1mz_X1$(EXEEXT) \
- insn_test_v1sadau_X0$(EXEEXT) insn_test_v1sadu_X0$(EXEEXT) \
- insn_test_v1shl_X0$(EXEEXT) insn_test_v1shl_X1$(EXEEXT) \
- insn_test_v1shli_X0$(EXEEXT) insn_test_v1shli_X1$(EXEEXT) \
- insn_test_v1shrs_X0$(EXEEXT) insn_test_v1shrs_X1$(EXEEXT) \
- insn_test_v1shrsi_X0$(EXEEXT) insn_test_v1shrsi_X1$(EXEEXT) \
- insn_test_v1shru_X0$(EXEEXT) insn_test_v1shru_X1$(EXEEXT) \
- insn_test_v1shrui_X0$(EXEEXT) insn_test_v1shrui_X1$(EXEEXT) \
- insn_test_v1sub_X0$(EXEEXT) insn_test_v1sub_X1$(EXEEXT) \
- insn_test_v1subuc_X0$(EXEEXT) insn_test_v1subuc_X1$(EXEEXT) \
- insn_test_v2add_X0$(EXEEXT) insn_test_v2add_X1$(EXEEXT) \
- insn_test_v2addsc_X0$(EXEEXT) insn_test_v2addsc_X1$(EXEEXT) \
- insn_test_v2adiffs_X0$(EXEEXT) insn_test_v2avgs_X0$(EXEEXT) \
- insn_test_v2cmpeq_X0$(EXEEXT) insn_test_v2cmpeq_X1$(EXEEXT) \
- insn_test_v2cmpeqi_X0$(EXEEXT) insn_test_v2cmpeqi_X1$(EXEEXT) \
- insn_test_v2cmples_X0$(EXEEXT) insn_test_v2cmples_X1$(EXEEXT) \
- insn_test_v2cmpleu_X0$(EXEEXT) insn_test_v2cmpleu_X1$(EXEEXT) \
- insn_test_v2cmplts_X0$(EXEEXT) insn_test_v2cmplts_X1$(EXEEXT) \
- insn_test_v2cmpltsi_X0$(EXEEXT) \
- insn_test_v2cmpltsi_X1$(EXEEXT) insn_test_v2cmpltu_X0$(EXEEXT) \
- insn_test_v2cmpltu_X1$(EXEEXT) insn_test_v2cmpltui_X0$(EXEEXT) \
- insn_test_v2cmpltui_X1$(EXEEXT) insn_test_v2cmpne_X0$(EXEEXT) \
- insn_test_v2cmpne_X1$(EXEEXT) insn_test_v2dotp_X0$(EXEEXT) \
- insn_test_v2dotpa_X0$(EXEEXT) insn_test_v2int_h_X0$(EXEEXT) \
- insn_test_v2int_h_X1$(EXEEXT) insn_test_v2int_l_X0$(EXEEXT) \
- insn_test_v2int_l_X1$(EXEEXT) insn_test_v2maxs_X0$(EXEEXT) \
- insn_test_v2maxs_X1$(EXEEXT) insn_test_v2mins_X0$(EXEEXT) \
- insn_test_v2mins_X1$(EXEEXT) insn_test_v2mnz_X0$(EXEEXT) \
- insn_test_v2mnz_X1$(EXEEXT) insn_test_v2mulfsc_X0$(EXEEXT) \
- insn_test_v2muls_X0$(EXEEXT) insn_test_v2mults_X0$(EXEEXT) \
- insn_test_v2mz_X0$(EXEEXT) insn_test_v2mz_X1$(EXEEXT) \
- insn_test_v2packh_X0$(EXEEXT) insn_test_v2packh_X1$(EXEEXT) \
- insn_test_v2packl_X0$(EXEEXT) insn_test_v2packl_X1$(EXEEXT) \
- insn_test_v2packuc_X0$(EXEEXT) insn_test_v2packuc_X1$(EXEEXT) \
- insn_test_v2sadas_X0$(EXEEXT) insn_test_v2sadau_X0$(EXEEXT) \
- insn_test_v2sads_X0$(EXEEXT) insn_test_v2sadu_X0$(EXEEXT) \
- insn_test_v2shl_X0$(EXEEXT) insn_test_v2shl_X1$(EXEEXT) \
- insn_test_v2shli_X0$(EXEEXT) insn_test_v2shli_X1$(EXEEXT) \
- insn_test_v2shlsc_X0$(EXEEXT) insn_test_v2shlsc_X1$(EXEEXT) \
- insn_test_v2shrs_X0$(EXEEXT) insn_test_v2shrs_X1$(EXEEXT) \
- insn_test_v2shrsi_X0$(EXEEXT) insn_test_v2shrsi_X1$(EXEEXT) \
- insn_test_v2shru_X0$(EXEEXT) insn_test_v2shru_X1$(EXEEXT) \
- insn_test_v2shrui_X0$(EXEEXT) insn_test_v2shrui_X1$(EXEEXT) \
- insn_test_v2sub_X0$(EXEEXT) insn_test_v2sub_X1$(EXEEXT) \
- insn_test_v2subsc_X0$(EXEEXT) insn_test_v2subsc_X1$(EXEEXT) \
- insn_test_v4add_X0$(EXEEXT) insn_test_v4add_X1$(EXEEXT) \
- insn_test_v4addsc_X0$(EXEEXT) insn_test_v4addsc_X1$(EXEEXT) \
- insn_test_v4int_h_X0$(EXEEXT) insn_test_v4int_h_X1$(EXEEXT) \
- insn_test_v4int_l_X0$(EXEEXT) insn_test_v4int_l_X1$(EXEEXT) \
- insn_test_v4packsc_X0$(EXEEXT) insn_test_v4packsc_X1$(EXEEXT) \
- insn_test_v4shl_X0$(EXEEXT) insn_test_v4shl_X1$(EXEEXT) \
- insn_test_v4shlsc_X0$(EXEEXT) insn_test_v4shlsc_X1$(EXEEXT) \
- insn_test_v4shrs_X0$(EXEEXT) insn_test_v4shrs_X1$(EXEEXT) \
- insn_test_v4shru_X0$(EXEEXT) insn_test_v4shru_X1$(EXEEXT) \
- insn_test_v4sub_X0$(EXEEXT) insn_test_v4sub_X1$(EXEEXT) \
- insn_test_v4subsc_X0$(EXEEXT) insn_test_v4subsc_X1$(EXEEXT) \
- insn_test_wh64_X1$(EXEEXT) insn_test_xor_X0$(EXEEXT) \
- insn_test_xor_X1$(EXEEXT) insn_test_xor_Y0$(EXEEXT) \
- insn_test_xor_Y1$(EXEEXT) insn_test_xori_X0$(EXEEXT) \
- insn_test_xori_X1$(EXEEXT)
-PROGRAMS = $(bin_PROGRAMS)
-allexec_SOURCES = allexec.c
-allexec_OBJECTS = allexec-allexec.$(OBJEXT)
-allexec_LDADD = $(LDADD)
-allexec_LINK = $(CCLD) $(allexec_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
- $(LDFLAGS) -o $@
-gen_insn_test_SOURCES = gen_insn_test.c
-gen_insn_test_OBJECTS = gen_insn_test-gen_insn_test.$(OBJEXT)
-gen_insn_test_DEPENDENCIES = ../../../VEX/priv/tilegx_disasm.o
-gen_insn_test_LINK = $(CCLD) $(gen_insn_test_CFLAGS) $(CFLAGS) \
- $(AM_LDFLAGS) $(LDFLAGS) -o $@
-insn_test_add_X0_SOURCES = insn_test_add_X0.c
-insn_test_add_X0_OBJECTS = insn_test_add_X0.$(OBJEXT)
-insn_test_add_X0_LDADD = $(LDADD)
-insn_test_add_X1_SOURCES = insn_test_add_X1.c
-insn_test_add_X1_OBJECTS = insn_test_add_X1.$(OBJEXT)
-insn_test_add_X1_LDADD = $(LDADD)
-insn_test_add_Y0_SOURCES = insn_test_add_Y0.c
-insn_test_add_Y0_OBJECTS = insn_test_add_Y0.$(OBJEXT)
-insn_test_add_Y0_LDADD = $(LDADD)
-insn_test_add_Y1_SOURCES = insn_test_add_Y1.c
-insn_test_add_Y1_OBJECTS = insn_test_add_Y1.$(OBJEXT)
-insn_test_add_Y1_LDADD = $(LDADD)
-insn_test_addi_X0_SOURCES = insn_test_addi_X0.c
-insn_test_addi_X0_OBJECTS = insn_test_addi_X0.$(OBJEXT)
-insn_test_addi_X0_LDADD = $(LDADD)
-insn_test_addi_X1_SOURCES = insn_test_addi_X1.c
-insn_test_addi_X1_OBJECTS = insn_test_addi_X1.$(OBJEXT)
-insn_test_addi_X1_LDADD = $(LDADD)
-insn_test_addi_Y0_SOURCES = insn_test_addi_Y0.c
-insn_test_addi_Y0_OBJECTS = insn_test_addi_Y0.$(OBJEXT)
-insn_test_addi_Y0_LDADD = $(LDADD)
-insn_test_addi_Y1_SOURCES = insn_test_addi_Y1.c
-insn_test_addi_Y1_OBJECTS = insn_test_addi_Y1.$(OBJEXT)
-insn_test_addi_Y1_LDADD = $(LDADD)
-insn_test_addli_X0_SOURCES = insn_test_addli_X0.c
-insn_test_addli_X0_OBJECTS = insn_test_addli_X0.$(OBJEXT)
-insn_test_addli_X0_LDADD = $(LDADD)
-insn_test_addli_X1_SOURCES = insn_test_addli_X1.c
-insn_test_addli_X1_OBJECTS = insn_test_addli_X1.$(OBJEXT)
-insn_test_addli_X1_LDADD = $(LDADD)
-insn_test_addx_X0_SOURCES = insn_test_addx_X0.c
-insn_test_addx_X0_OBJECTS = insn_test_addx_X0.$(OBJEXT)
-insn_test_addx_X0_LDADD = $(LDADD)
-insn_test_addx_X1_SOURCES = insn_test_addx_X1.c
-insn_test_addx_X1_OBJECTS = insn_test_addx_X1.$(OBJEXT)
-insn_test_addx_X1_LDADD = $(LDADD)
-insn_test_addx_Y0_SOURCES = insn_test_addx_Y0.c
-insn_test_addx_Y0_OBJECTS = insn_test_addx_Y0.$(OBJEXT)
-insn_test_addx_Y0_LDADD = $(LDADD)
-insn_test_addx_Y1_SOURCES = insn_test_addx_Y1.c
-insn_test_addx_Y1_OBJECTS = insn_test_addx_Y1.$(OBJEXT)
-insn_test_addx_Y1_LDADD = $(LDADD)
-insn_test_addxi_X0_SOURCES = insn_test_addxi_X0.c
-insn_test_addxi_X0_OBJECTS = insn_test_addxi_X0.$(OBJEXT)
-insn_test_addxi_X0_LDADD = $(LDADD)
-insn_test_addxi_X1_SOURCES = insn_test_addxi_X1.c
-insn_test_addxi_X1_OBJECTS = insn_test_addxi_X1.$(OBJEXT)
-insn_test_addxi_X1_LDADD = $(LDADD)
-insn_test_addxi_Y0_SOURCES = insn_test_addxi_Y0.c
-insn_test_addxi_Y0_OBJECTS = insn_test_addxi_Y0.$(OBJEXT)
-insn_test_addxi_Y0_LDADD = $(LDADD)
-insn_test_addxi_Y1_SOURCES = insn_test_addxi_Y1.c
-insn_test_addxi_Y1_OBJECTS = insn_test_addxi_Y1.$(OBJEXT)
-insn_test_addxi_Y1_LDADD = $(LDADD)
-insn_test_addxli_X0_SOURCES = insn_test_addxli_X0.c
-insn_test_addxli_X0_OBJECTS = insn_test_addxli_X0.$(OBJEXT)
-insn_test_addxli_X0_LDADD = $(LDADD)
-insn_test_addxli_X1_SOURCES = insn_test_addxli_X1.c
-insn_test_addxli_X1_OBJECTS = insn_test_addxli_X1.$(OBJEXT)
-insn_test_addxli_X1_LDADD = $(LDADD)
-insn_test_addxsc_X0_SOURCES = insn_test_addxsc_X0.c
-insn_test_addxsc_X0_OBJECTS = insn_test_addxsc_X0.$(OBJEXT)
-insn_test_addxsc_X0_LDADD = $(LDADD)
-insn_test_addxsc_X1_SOURCES = insn_test_addxsc_X1.c
-insn_test_addxsc_X1_OBJECTS = insn_test_addxsc_X1.$(OBJEXT)
-insn_test_addxsc_X1_LDADD = $(LDADD)
-insn_test_and_X0_SOURCES = insn_test_and_X0.c
-insn_test_and_X0_OBJECTS = insn_test_and_X0.$(OBJEXT)
-insn_test_and_X0_LDADD = $(LDADD)
-insn_test_and_X1_SOURCES = insn_test_and_X1.c
-insn_test_and_X1_OBJECTS = insn_test_and_X1.$(OBJEXT)
-insn_test_and_X1_LDADD = $(LDADD)
-insn_test_and_Y0_SOURCES = insn_test_and_Y0.c
-insn_test_and_Y0_OBJECTS = insn_test_and_Y0.$(OBJEXT)
-insn_test_and_Y0_LDADD = $(LDADD)
-insn_test_and_Y1_SOURCES = insn_test_and_Y1.c
-insn_test_and_Y1_OBJECTS = insn_test_and_Y1.$(OBJEXT)
-insn_test_and_Y1_LDADD = $(LDADD)
-insn_test_andi_X0_SOURCES = insn_test_andi_X0.c
-insn_test_andi_X0_OBJECTS = insn_test_andi_X0.$(OBJEXT)
-insn_test_andi_X0_LDADD = $(LDADD)
-insn_test_andi_X1_SOURCES = insn_test_andi_X1.c
-insn_test_andi_X1_OBJECTS = insn_test_andi_X1.$(OBJEXT)
-insn_test_andi_X1_LDADD = $(LDADD)
-insn_test_andi_Y0_SOURCES = insn_test_andi_Y0.c
-insn_test_andi_Y0_OBJECTS = insn_test_andi_Y0.$(OBJEXT)
-insn_test_andi_Y0_LDADD = $(LDADD)
-insn_test_andi_Y1_SOURCES = insn_test_andi_Y1.c
-insn_test_andi_Y1_OBJECTS = insn_test_andi_Y1.$(OBJEXT)
-insn_test_andi_Y1_LDADD = $(LDADD)
-insn_test_beqz_X1_SOURCES = insn_test_beqz_X1.c
-insn_test_beqz_X1_OBJECTS = insn_test_beqz_X1.$(OBJEXT)
-insn_test_beqz_X1_LDADD = $(LDADD)
-insn_test_beqzt_X1_SOURCES = insn_test_beqzt_X1.c
-insn_test_beqzt_X1_OBJECTS = insn_test_beqzt_X1.$(OBJEXT)
-insn_test_beqzt_X1_LDADD = $(LDADD)
-insn_test_bfexts_X0_SOURCES = insn_test_bfexts_X0.c
-insn_test_bfexts_X0_OBJECTS = insn_test_bfexts_X0.$(OBJEXT)
-insn_test_bfexts_X0_LDADD = $(LDADD)
-insn_test_bfextu_X0_SOURCES = insn_test_bfextu_X0.c
-insn_test_bfextu_X0_OBJECTS = insn_test_bfextu_X0.$(OBJEXT)
-insn_test_bfextu_X0_LDADD = $(LDADD)
-insn_test_bfins_X0_SOURCES = insn_test_bfins_X0.c
-insn_test_bfins_X0_OBJECTS = insn_test_bfins_X0.$(OBJEXT)
-insn_test_bfins_X0_LDADD = $(LDADD)
-insn_test_bgez_X1_SOURCES = insn_test_bgez_X1.c
-insn_test_bgez_X1_OBJECTS = insn_test_bgez_X1.$(OBJEXT)
-insn_test_bgez_X1_LDADD = $(LDADD)
-insn_test_bgezt_X1_SOURCES = insn_test_bgezt_X1.c
-insn_test_bgezt_X1_OBJECTS = insn_test_bgezt_X1.$(OBJEXT)
-insn_test_bgezt_X1_LDADD = $(LDADD)
-insn_test_bgtz_X1_SOURCES = insn_test_bgtz_X1.c
-insn_test_bgtz_X1_OBJECTS = insn_test_bgtz_X1.$(OBJEXT)
-insn_test_bgtz_X1_LDADD = $(LDADD)
-insn_test_bgtzt_X1_SOURCES = insn_test_bgtzt_X1.c
-insn_test_bgtzt_X1_OBJECTS = insn_test_bgtzt_X1.$(OBJEXT)
-insn_test_bgtzt_X1_LDADD = $(LDADD)
-insn_test_blbc_X1_SOURCES = insn_test_blbc_X1.c
-insn_test_blbc_X1_OBJECTS = insn_test_blbc_X1.$(OBJEXT)
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-insn_test_mulx_X0_OBJECTS = insn_test_mulx_X0.$(OBJEXT)
-insn_test_mulx_X0_LDADD = $(LDADD)
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-insn_test_mulx_Y0_OBJECTS = insn_test_mulx_Y0.$(OBJEXT)
-insn_test_mulx_Y0_LDADD = $(LDADD)
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-insn_test_mz_X0_OBJECTS = insn_test_mz_X0.$(OBJEXT)
-insn_test_mz_X0_LDADD = $(LDADD)
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-insn_test_mz_X1_LDADD = $(LDADD)
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-insn_test_mz_Y0_OBJECTS = insn_test_mz_Y0.$(OBJEXT)
-insn_test_mz_Y0_LDADD = $(LDADD)
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-insn_test_mz_Y1_OBJECTS = insn_test_mz_Y1.$(OBJEXT)
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-insn_test_nop_X0_LDADD = $(LDADD)
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-insn_test_shrui_Y0_LDADD = $(LDADD)
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-insn_test_shrui_Y1_OBJECTS = insn_test_shrui_Y1.$(OBJEXT)
-insn_test_shrui_Y1_LDADD = $(LDADD)
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-insn_test_shrux_X0_LDADD = $(LDADD)
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-insn_test_shrux_X1_OBJECTS = insn_test_shrux_X1.$(OBJEXT)
-insn_test_shrux_X1_LDADD = $(LDADD)
-insn_test_shufflebytes_X0_SOURCES = insn_test_shufflebytes_X0.c
-insn_test_shufflebytes_X0_OBJECTS = \
- insn_test_shufflebytes_X0.$(OBJEXT)
-insn_test_shufflebytes_X0_LDADD = $(LDADD)
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-insn_test_st1_add_X1_LDADD = $(LDADD)
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-insn_test_v4int_h_X0_LDADD = $(LDADD)
-insn_test_v4int_h_X1_SOURCES = insn_test_v4int_h_X1.c
-insn_test_v4int_h_X1_OBJECTS = insn_test_v4int_h_X1.$(OBJEXT)
-insn_test_v4int_h_X1_LDADD = $(LDADD)
-insn_test_v4int_l_X0_SOURCES = insn_test_v4int_l_X0.c
-insn_test_v4int_l_X0_OBJECTS = insn_test_v4int_l_X0.$(OBJEXT)
-insn_test_v4int_l_X0_LDADD = $(LDADD)
-insn_test_v4int_l_X1_SOURCES = insn_test_v4int_l_X1.c
-insn_test_v4int_l_X1_OBJECTS = insn_test_v4int_l_X1.$(OBJEXT)
-insn_test_v4int_l_X1_LDADD = $(LDADD)
-insn_test_v4packsc_X0_SOURCES = insn_test_v4packsc_X0.c
-insn_test_v4packsc_X0_OBJECTS = insn_test_v4packsc_X0.$(OBJEXT)
-insn_test_v4packsc_X0_LDADD = $(LDADD)
-insn_test_v4packsc_X1_SOURCES = insn_test_v4packsc_X1.c
-insn_test_v4packsc_X1_OBJECTS = insn_test_v4packsc_X1.$(OBJEXT)
-insn_test_v4packsc_X1_LDADD = $(LDADD)
-insn_test_v4shl_X0_SOURCES = insn_test_v4shl_X0.c
-insn_test_v4shl_X0_OBJECTS = insn_test_v4shl_X0.$(OBJEXT)
-insn_test_v4shl_X0_LDADD = $(LDADD)
-insn_test_v4shl_X1_SOURCES = insn_test_v4shl_X1.c
-insn_test_v4shl_X1_OBJECTS = insn_test_v4shl_X1.$(OBJEXT)
-insn_test_v4shl_X1_LDADD = $(LDADD)
-insn_test_v4shlsc_X0_SOURCES = insn_test_v4shlsc_X0.c
-insn_test_v4shlsc_X0_OBJECTS = insn_test_v4shlsc_X0.$(OBJEXT)
-insn_test_v4shlsc_X0_LDADD = $(LDADD)
-insn_test_v4shlsc_X1_SOURCES = insn_test_v4shlsc_X1.c
-insn_test_v4shlsc_X1_OBJECTS = insn_test_v4shlsc_X1.$(OBJEXT)
-insn_test_v4shlsc_X1_LDADD = $(LDADD)
-insn_test_v4shrs_X0_SOURCES = insn_test_v4shrs_X0.c
-insn_test_v4shrs_X0_OBJECTS = insn_test_v4shrs_X0.$(OBJEXT)
-insn_test_v4shrs_X0_LDADD = $(LDADD)
-insn_test_v4shrs_X1_SOURCES = insn_test_v4shrs_X1.c
-insn_test_v4shrs_X1_OBJECTS = insn_test_v4shrs_X1.$(OBJEXT)
-insn_test_v4shrs_X1_LDADD = $(LDADD)
-insn_test_v4shru_X0_SOURCES = insn_test_v4shru_X0.c
-insn_test_v4shru_X0_OBJECTS = insn_test_v4shru_X0.$(OBJEXT)
-insn_test_v4shru_X0_LDADD = $(LDADD)
-insn_test_v4shru_X1_SOURCES = insn_test_v4shru_X1.c
-insn_test_v4shru_X1_OBJECTS = insn_test_v4shru_X1.$(OBJEXT)
-insn_test_v4shru_X1_LDADD = $(LDADD)
-insn_test_v4sub_X0_SOURCES = insn_test_v4sub_X0.c
-insn_test_v4sub_X0_OBJECTS = insn_test_v4sub_X0.$(OBJEXT)
-insn_test_v4sub_X0_LDADD = $(LDADD)
-insn_test_v4sub_X1_SOURCES = insn_test_v4sub_X1.c
-insn_test_v4sub_X1_OBJECTS = insn_test_v4sub_X1.$(OBJEXT)
-insn_test_v4sub_X1_LDADD = $(LDADD)
-insn_test_v4subsc_X0_SOURCES = insn_test_v4subsc_X0.c
-insn_test_v4subsc_X0_OBJECTS = insn_test_v4subsc_X0.$(OBJEXT)
-insn_test_v4subsc_X0_LDADD = $(LDADD)
-insn_test_v4subsc_X1_SOURCES = insn_test_v4subsc_X1.c
-insn_test_v4subsc_X1_OBJECTS = insn_test_v4subsc_X1.$(OBJEXT)
-insn_test_v4subsc_X1_LDADD = $(LDADD)
-insn_test_wh64_X1_SOURCES = insn_test_wh64_X1.c
-insn_test_wh64_X1_OBJECTS = insn_test_wh64_X1.$(OBJEXT)
-insn_test_wh64_X1_LDADD = $(LDADD)
-insn_test_xor_X0_SOURCES = insn_test_xor_X0.c
-insn_test_xor_X0_OBJECTS = insn_test_xor_X0.$(OBJEXT)
-insn_test_xor_X0_LDADD = $(LDADD)
-insn_test_xor_X1_SOURCES = insn_test_xor_X1.c
-insn_test_xor_X1_OBJECTS = insn_test_xor_X1.$(OBJEXT)
-insn_test_xor_X1_LDADD = $(LDADD)
-insn_test_xor_Y0_SOURCES = insn_test_xor_Y0.c
-insn_test_xor_Y0_OBJECTS = insn_test_xor_Y0.$(OBJEXT)
-insn_test_xor_Y0_LDADD = $(LDADD)
-insn_test_xor_Y1_SOURCES = insn_test_xor_Y1.c
-insn_test_xor_Y1_OBJECTS = insn_test_xor_Y1.$(OBJEXT)
-insn_test_xor_Y1_LDADD = $(LDADD)
-insn_test_xori_X0_SOURCES = insn_test_xori_X0.c
-insn_test_xori_X0_OBJECTS = insn_test_xori_X0.$(OBJEXT)
-insn_test_xori_X0_LDADD = $(LDADD)
-insn_test_xori_X1_SOURCES = insn_test_xori_X1.c
-insn_test_xori_X1_OBJECTS = insn_test_xori_X1.$(OBJEXT)
-insn_test_xori_X1_LDADD = $(LDADD)
-SCRIPTS = $(dist_noinst_SCRIPTS)
-AM_V_P = $(am__v_P_@AM_V@)
-am__v_P_ = $(am__v_P_@AM_DEFAULT_V@)
-am__v_P_0 = false
-am__v_P_1 = :
-AM_V_GEN = $(am__v_GEN_@AM_V@)
-am__v_GEN_ = $(am__v_GEN_@AM_DEFAULT_V@)
-am__v_GEN_0 = @echo " GEN " $@;
-am__v_GEN_1 =
-AM_V_at = $(am__v_at_@AM_V@)
-am__v_at_ = $(am__v_at_@AM_DEFAULT_V@)
-am__v_at_0 = @
-am__v_at_1 =
-DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
-depcomp = $(SHELL) $(top_srcdir)/depcomp
-am__depfiles_maybe = depfiles
-am__mv = mv -f
-AM_V_lt = $(am__v_lt_@AM_V@)
-am__v_lt_ = $(am__v_lt_@AM_DEFAULT_V@)
-am__v_lt_0 = --silent
-am__v_lt_1 =
-COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
- $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
-AM_V_CC = $(am__v_CC_@AM_V@)
-am__v_CC_ = $(am__v_CC_@AM_DEFAULT_V@)
-am__v_CC_0 = @echo " CC " $@;
-am__v_CC_1 =
-CCLD = $(CC)
-LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
-AM_V_CCLD = $(am__v_CCLD_@AM_V@)
-am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@)
-am__v_CCLD_0 = @echo " CCLD " $@;
-am__v_CCLD_1 =
-SOURCES = allexec.c gen_insn_test.c insn_test_add_X0.c \
- insn_test_add_X1.c insn_test_add_Y0.c insn_test_add_Y1.c \
- insn_test_addi_X0.c insn_test_addi_X1.c insn_test_addi_Y0.c \
- insn_test_addi_Y1.c insn_test_addli_X0.c insn_test_addli_X1.c \
- insn_test_addx_X0.c insn_test_addx_X1.c insn_test_addx_Y0.c \
- insn_test_addx_Y1.c insn_test_addxi_X0.c insn_test_addxi_X1.c \
- insn_test_addxi_Y0.c insn_test_addxi_Y1.c \
- insn_test_addxli_X0.c insn_test_addxli_X1.c \
- insn_test_addxsc_X0.c insn_test_addxsc_X1.c insn_test_and_X0.c \
- insn_test_and_X1.c insn_test_and_Y0.c insn_test_and_Y1.c \
- insn_test_andi_X0.c insn_test_andi_X1.c insn_test_andi_Y0.c \
- insn_test_andi_Y1.c insn_test_beqz_X1.c insn_test_beqzt_X1.c \
- insn_test_bfexts_X0.c insn_test_bfextu_X0.c \
- insn_test_bfins_X0.c insn_test_bgez_X1.c insn_test_bgezt_X1.c \
- insn_test_bgtz_X1.c insn_test_bgtzt_X1.c insn_test_blbc_X1.c \
- insn_test_blbct_X1.c insn_test_blbs_X1.c insn_test_blbst_X1.c \
- insn_test_blez_X1.c insn_test_blezt_X1.c insn_test_bltz_X1.c \
- insn_test_bltzt_X1.c insn_test_bnez_X1.c insn_test_bnezt_X1.c \
- insn_test_clz_X0.c insn_test_clz_Y0.c insn_test_cmoveqz_X0.c \
- insn_test_cmoveqz_Y0.c insn_test_cmovnez_X0.c \
- insn_test_cmovnez_Y0.c insn_test_cmpeq_X0.c \
- insn_test_cmpeq_X1.c insn_test_cmpeq_Y0.c insn_test_cmpeq_Y1.c \
- insn_test_cmpeqi_X0.c insn_test_cmpeqi_X1.c \
- insn_test_cmpeqi_Y0.c insn_test_cmpeqi_Y1.c \
- insn_test_cmples_X0.c insn_test_cmples_X1.c \
- insn_test_cmples_Y0.c insn_test_cmples_Y1.c \
- insn_test_cmpleu_X0.c insn_test_cmpleu_X1.c \
- insn_test_cmpleu_Y0.c insn_test_cmpleu_Y1.c \
- insn_test_cmplts_X0.c insn_test_cmplts_X1.c \
- insn_test_cmplts_Y0.c insn_test_cmplts_Y1.c \
- insn_test_cmpltsi_X0.c insn_test_cmpltsi_X1.c \
- insn_test_cmpltsi_Y0.c insn_test_cmpltsi_Y1.c \
- insn_test_cmpltu_X0.c insn_test_cmpltu_X1.c \
- insn_test_cmpltu_Y0.c insn_test_cmpltu_Y1.c \
- insn_test_cmpltui_X0.c insn_test_cmpltui_X1.c \
- insn_test_cmpne_X0.c insn_test_cmpne_X1.c insn_test_cmpne_Y0.c \
- insn_test_cmpne_Y1.c insn_test_cmul_X0.c insn_test_cmula_X0.c \
- insn_test_cmulaf_X0.c insn_test_cmulf_X0.c \
- insn_test_cmulfr_X0.c insn_test_cmulh_X0.c \
- insn_test_cmulhr_X0.c insn_test_crc32_32_X0.c \
- insn_test_crc32_8_X0.c insn_test_ctz_X0.c insn_test_ctz_Y0.c \
- insn_test_dblalign2_X0.c insn_test_dblalign2_X1.c \
- insn_test_dblalign4_X0.c insn_test_dblalign4_X1.c \
- insn_test_dblalign6_X0.c insn_test_dblalign6_X1.c \
- insn_test_dblalign_X0.c insn_test_dtlbpr_X1.c \
- insn_test_fdouble_add_flags_X0.c insn_test_fdouble_addsub_X0.c \
- insn_test_fdouble_mul_flags_X0.c insn_test_fdouble_pack1_X0.c \
- insn_test_fdouble_pack2_X0.c insn_test_fdouble_sub_flags_X0.c \
- insn_test_fdouble_unpack_max_X0.c \
- insn_test_fdouble_unpack_min_X0.c insn_test_flushwb_X1.c \
- insn_test_fnop_X0.c insn_test_fnop_X1.c insn_test_fnop_Y0.c \
- insn_test_fnop_Y1.c insn_test_fsingle_add1_X0.c \
- insn_test_fsingle_addsub2_X0.c insn_test_fsingle_mul1_X0.c \
- insn_test_fsingle_mul2_X0.c insn_test_fsingle_pack1_X0.c \
- insn_test_fsingle_pack1_Y0.c insn_test_fsingle_pack2_X0.c \
- insn_test_fsingle_sub1_X0.c insn_test_icoh_X1.c \
- insn_test_j_X1.c insn_test_jal_X1.c insn_test_jalr_X1.c \
- insn_test_jalr_Y1.c insn_test_jalrp_X1.c insn_test_jalrp_Y1.c \
- insn_test_jr_X1.c insn_test_jr_Y1.c insn_test_jrp_X1.c \
- insn_test_jrp_Y1.c insn_test_ld1s_X1.c insn_test_ld1s_Y2.c \
- insn_test_ld1s_add_X1.c insn_test_ld1u_X1.c \
- insn_test_ld1u_Y2.c insn_test_ld1u_add_X1.c \
- insn_test_ld2s_X1.c insn_test_ld2s_Y2.c insn_test_ld2u_X1.c \
- insn_test_ld2u_Y2.c insn_test_ld4s_X1.c \
- insn_test_ld4s_add_X1.c insn_test_ld4u_X1.c \
- insn_test_ld4u_Y2.c insn_test_ld4u_add_X1.c insn_test_ld_X1.c \
- insn_test_ld_Y2.c insn_test_ld_add_X1.c insn_test_ldna_X1.c \
- insn_test_ldna_add_X1.c insn_test_ldnt1s_X1.c \
- insn_test_ldnt1s_add_X1.c insn_test_ldnt1u_X1.c \
- insn_test_ldnt1u_add_X1.c insn_test_ldnt2s_X1.c \
- insn_test_ldnt2s_add_X1.c insn_test_ldnt2u_add_X1.c \
- insn_test_ldnt4s_X1.c insn_test_ldnt4s_add_X1.c \
- insn_test_ldnt4u_X1.c insn_test_ldnt4u_add_X1.c \
- insn_test_ldnt_X1.c insn_test_ldnt_add_X1.c insn_test_lnk_X1.c \
- insn_test_lnk_Y1.c insn_test_mf_X1.c insn_test_mm_X0.c \
- insn_test_mnz_X0.c insn_test_mnz_X1.c insn_test_mnz_Y0.c \
- insn_test_mnz_Y1.c insn_test_move_X0.c insn_test_move_X1.c \
- insn_test_move_Y0.c insn_test_move_Y1.c insn_test_movei_X0.c \
- insn_test_movei_X1.c insn_test_movei_Y0.c insn_test_movei_Y1.c \
- insn_test_moveli_X0.c insn_test_moveli_X1.c \
- insn_test_mul_hs_hs_X0.c insn_test_mul_hs_hs_Y0.c \
- insn_test_mul_hs_hu_X0.c insn_test_mul_hs_ls_X0.c \
- insn_test_mul_hs_lu_X0.c insn_test_mul_hu_hu_X0.c \
- insn_test_mul_hu_hu_Y0.c insn_test_mul_hu_lu_X0.c \
- insn_test_mul_ls_ls_X0.c insn_test_mul_ls_ls_Y0.c \
- insn_test_mul_ls_lu_X0.c insn_test_mul_lu_lu_X0.c \
- insn_test_mul_lu_lu_Y0.c insn_test_mula_hs_hs_X0.c \
- insn_test_mula_hs_hs_Y0.c insn_test_mula_hs_hu_X0.c \
- insn_test_mula_hs_ls_X0.c insn_test_mula_hs_lu_X0.c \
- insn_test_mula_hu_hu_X0.c insn_test_mula_hu_hu_Y0.c \
- insn_test_mula_hu_ls_X0.c insn_test_mula_hu_lu_X0.c \
- insn_test_mula_ls_ls_X0.c insn_test_mula_ls_ls_Y0.c \
- insn_test_mula_ls_lu_X0.c insn_test_mula_lu_lu_X0.c \
- insn_test_mula_lu_lu_Y0.c insn_test_mulax_X0.c \
- insn_test_mulax_Y0.c insn_test_mulx_X0.c insn_test_mulx_Y0.c \
- insn_test_mz_X0.c insn_test_mz_X1.c insn_test_mz_Y0.c \
- insn_test_mz_Y1.c insn_test_nop_X0.c insn_test_nop_X1.c \
- insn_test_nop_Y0.c insn_test_nop_Y1.c insn_test_nor_X0.c \
- insn_test_nor_X1.c insn_test_nor_Y0.c insn_test_nor_Y1.c \
- insn_test_or_X0.c insn_test_or_X1.c insn_test_or_Y0.c \
- insn_test_or_Y1.c insn_test_ori_X0.c insn_test_ori_X1.c \
- insn_test_pcnt_X0.c insn_test_pcnt_Y0.c \
- insn_test_prefetch_X1.c insn_test_prefetch_Y2.c \
- insn_test_prefetch_l1_X1.c insn_test_prefetch_l1_Y2.c \
- insn_test_prefetch_l2_X1.c insn_test_prefetch_l2_Y2.c \
- insn_test_prefetch_l3_X1.c insn_test_prefetch_l3_Y2.c \
- insn_test_revbits_X0.c insn_test_revbits_Y0.c \
- insn_test_revbytes_X0.c insn_test_revbytes_Y0.c \
- insn_test_rotl_X0.c insn_test_rotl_X1.c insn_test_rotl_Y0.c \
- insn_test_rotl_Y1.c insn_test_rotli_X0.c insn_test_rotli_X1.c \
- insn_test_rotli_Y0.c insn_test_rotli_Y1.c \
- insn_test_shl16insli_X0.c insn_test_shl16insli_X1.c \
- insn_test_shl1add_X0.c insn_test_shl1add_X1.c \
- insn_test_shl1add_Y0.c insn_test_shl1add_Y1.c \
- insn_test_shl1addx_X0.c insn_test_shl1addx_X1.c \
- insn_test_shl1addx_Y0.c insn_test_shl1addx_Y1.c \
- insn_test_shl2add_X0.c insn_test_shl2add_X1.c \
- insn_test_shl2add_Y0.c insn_test_shl2add_Y1.c \
- insn_test_shl2addx_X0.c insn_test_shl2addx_X1.c \
- insn_test_shl2addx_Y0.c insn_test_shl2addx_Y1.c \
- insn_test_shl3add_X0.c insn_test_shl3add_X1.c \
- insn_test_shl3add_Y0.c insn_test_shl3add_Y1.c \
- insn_test_shl3addx_X0.c insn_test_shl3addx_X1.c \
- insn_test_shl3addx_Y0.c insn_test_shl3addx_Y1.c \
- insn_test_shl_X0.c insn_test_shl_X1.c insn_test_shl_Y0.c \
- insn_test_shl_Y1.c insn_test_shli_X0.c insn_test_shli_X1.c \
- insn_test_shli_Y0.c insn_test_shli_Y1.c insn_test_shlx_X0.c \
- insn_test_shlx_X1.c insn_test_shlxi_X0.c insn_test_shlxi_X1.c \
- insn_test_shrs_X0.c insn_test_shrs_X1.c insn_test_shrs_Y0.c \
- insn_test_shrs_Y1.c insn_test_shrsi_X0.c insn_test_shrsi_X1.c \
- insn_test_shrsi_Y0.c insn_test_shrsi_Y1.c insn_test_shru_X0.c \
- insn_test_shru_X1.c insn_test_shru_Y0.c insn_test_shru_Y1.c \
- insn_test_shrui_X0.c insn_test_shrui_X1.c insn_test_shrui_Y0.c \
- insn_test_shrui_Y1.c insn_test_shrux_X0.c insn_test_shrux_X1.c \
- insn_test_shufflebytes_X0.c insn_test_st1_X1.c \
- insn_test_st1_Y2.c insn_test_st1_add_X1.c insn_test_st2_X1.c \
- insn_test_st2_Y2.c insn_test_st2_add_X1.c insn_test_st4_X1.c \
- insn_test_st4_Y2.c insn_test_st4_add_X1.c insn_test_st_X1.c \
- insn_test_st_Y2.c insn_test_st_add_X1.c insn_test_stnt1_X1.c \
- insn_test_stnt2_X1.c insn_test_stnt2_add_X1.c \
- insn_test_stnt4_X1.c insn_test_stnt4_add_X1.c \
- insn_test_stnt_X1.c insn_test_stnt_add_X1.c insn_test_sub_X0.c \
- insn_test_sub_X1.c insn_test_sub_Y0.c insn_test_sub_Y1.c \
- insn_test_subx_X0.c insn_test_subx_X1.c insn_test_subx_Y0.c \
- insn_test_subx_Y1.c insn_test_tblidxb0_X0.c \
- insn_test_tblidxb0_Y0.c insn_test_tblidxb1_X0.c \
- insn_test_tblidxb1_Y0.c insn_test_tblidxb2_X0.c \
- insn_test_tblidxb2_Y0.c insn_test_tblidxb3_X0.c \
- insn_test_tblidxb3_Y0.c insn_test_v1add_X0.c \
- insn_test_v1add_X1.c insn_test_v1adduc_X0.c \
- insn_test_v1adduc_X1.c insn_test_v1adiffu_X0.c \
- insn_test_v1avgu_X0.c insn_test_v1cmpeq_X0.c \
- insn_test_v1cmpeq_X1.c insn_test_v1cmpeqi_X0.c \
- insn_test_v1cmpeqi_X1.c insn_test_v1cmples_X0.c \
- insn_test_v1cmples_X1.c insn_test_v1cmpleu_X0.c \
- insn_test_v1cmpleu_X1.c insn_test_v1cmplts_X0.c \
- insn_test_v1cmplts_X1.c insn_test_v1cmpltu_X0.c \
- insn_test_v1cmpltu_X1.c insn_test_v1cmpne_X0.c \
- insn_test_v1cmpne_X1.c insn_test_v1ddotpu_X0.c \
- insn_test_v1ddotpua_X0.c insn_test_v1ddotpus_X0.c \
- insn_test_v1ddotpusa_X0.c insn_test_v1dotp_X0.c \
- insn_test_v1dotpa_X0.c insn_test_v1dotpu_X0.c \
- insn_test_v1dotpua_X0.c insn_test_v1dotpus_X0.c \
- insn_test_v1dotpusa_X0.c insn_test_v1int_h_X0.c \
- insn_test_v1int_h_X1.c insn_test_v1int_l_X0.c \
- insn_test_v1int_l_X1.c insn_test_v1maxu_X0.c \
- insn_test_v1maxu_X1.c insn_test_v1minu_X0.c \
- insn_test_v1minu_X1.c insn_test_v1mnz_X0.c \
- insn_test_v1mnz_X1.c insn_test_v1multu_X0.c \
- insn_test_v1mulu_X0.c insn_test_v1mulus_X0.c \
- insn_test_v1mz_X0.c insn_test_v1mz_X1.c insn_test_v1sadau_X0.c \
- insn_test_v1sadu_X0.c insn_test_v1shl_X0.c \
- insn_test_v1shl_X1.c insn_test_v1shli_X0.c \
- insn_test_v1shli_X1.c insn_test_v1shrs_X0.c \
- insn_test_v1shrs_X1.c insn_test_v1shrsi_X0.c \
- insn_test_v1shrsi_X1.c insn_test_v1shru_X0.c \
- insn_test_v1shru_X1.c insn_test_v1shrui_X0.c \
- insn_test_v1shrui_X1.c insn_test_v1sub_X0.c \
- insn_test_v1sub_X1.c insn_test_v1subuc_X0.c \
- insn_test_v1subuc_X1.c insn_test_v2add_X0.c \
- insn_test_v2add_X1.c insn_test_v2addsc_X0.c \
- insn_test_v2addsc_X1.c insn_test_v2adiffs_X0.c \
- insn_test_v2avgs_X0.c insn_test_v2cmpeq_X0.c \
- insn_test_v2cmpeq_X1.c insn_test_v2cmpeqi_X0.c \
- insn_test_v2cmpeqi_X1.c insn_test_v2cmples_X0.c \
- insn_test_v2cmples_X1.c insn_test_v2cmpleu_X0.c \
- insn_test_v2cmpleu_X1.c insn_test_v2cmplts_X0.c \
- insn_test_v2cmplts_X1.c insn_test_v2cmpltsi_X0.c \
- insn_test_v2cmpltsi_X1.c insn_test_v2cmpltu_X0.c \
- insn_test_v2cmpltu_X1.c insn_test_v2cmpltui_X0.c \
- insn_test_v2cmpltui_X1.c insn_test_v2cmpne_X0.c \
- insn_test_v2cmpne_X1.c insn_test_v2dotp_X0.c \
- insn_test_v2dotpa_X0.c insn_test_v2int_h_X0.c \
- insn_test_v2int_h_X1.c insn_test_v2int_l_X0.c \
- insn_test_v2int_l_X1.c insn_test_v2maxs_X0.c \
- insn_test_v2maxs_X1.c insn_test_v2mins_X0.c \
- insn_test_v2mins_X1.c insn_test_v2mnz_X0.c \
- insn_test_v2mnz_X1.c insn_test_v2mulfsc_X0.c \
- insn_test_v2muls_X0.c insn_test_v2mults_X0.c \
- insn_test_v2mz_X0.c insn_test_v2mz_X1.c insn_test_v2packh_X0.c \
- insn_test_v2packh_X1.c insn_test_v2packl_X0.c \
- insn_test_v2packl_X1.c insn_test_v2packuc_X0.c \
- insn_test_v2packuc_X1.c insn_test_v2sadas_X0.c \
- insn_test_v2sadau_X0.c insn_test_v2sads_X0.c \
- insn_test_v2sadu_X0.c insn_test_v2shl_X0.c \
- insn_test_v2shl_X1.c insn_test_v2shli_X0.c \
- insn_test_v2shli_X1.c insn_test_v2shlsc_X0.c \
- insn_test_v2shlsc_X1.c insn_test_v2shrs_X0.c \
- insn_test_v2shrs_X1.c insn_test_v2shrsi_X0.c \
- insn_test_v2shrsi_X1.c insn_test_v2shru_X0.c \
- insn_test_v2shru_X1.c insn_test_v2shrui_X0.c \
- insn_test_v2shrui_X1.c insn_test_v2sub_X0.c \
- insn_test_v2sub_X1.c insn_test_v2subsc_X0.c \
- insn_test_v2subsc_X1.c insn_test_v4add_X0.c \
- insn_test_v4add_X1.c insn_test_v4addsc_X0.c \
- insn_test_v4addsc_X1.c insn_test_v4int_h_X0.c \
- insn_test_v4int_h_X1.c insn_test_v4int_l_X0.c \
- insn_test_v4int_l_X1.c insn_test_v4packsc_X0.c \
- insn_test_v4packsc_X1.c insn_test_v4shl_X0.c \
- insn_test_v4shl_X1.c insn_test_v4shlsc_X0.c \
- insn_test_v4shlsc_X1.c insn_test_v4shrs_X0.c \
- insn_test_v4shrs_X1.c insn_test_v4shru_X0.c \
- insn_test_v4shru_X1.c insn_test_v4sub_X0.c \
- insn_test_v4sub_X1.c insn_test_v4subsc_X0.c \
- insn_test_v4subsc_X1.c insn_test_wh64_X1.c insn_test_xor_X0.c \
- insn_test_xor_X1.c insn_test_xor_Y0.c insn_test_xor_Y1.c \
- insn_test_xori_X0.c insn_test_xori_X1.c
-DIST_SOURCES = allexec.c gen_insn_test.c insn_test_add_X0.c \
- insn_test_add_X1.c insn_test_add_Y0.c insn_test_add_Y1.c \
- insn_test_addi_X0.c insn_test_addi_X1.c insn_test_addi_Y0.c \
- insn_test_addi_Y1.c insn_test_addli_X0.c insn_test_addli_X1.c \
- insn_test_addx_X0.c insn_test_addx_X1.c insn_test_addx_Y0.c \
- insn_test_addx_Y1.c insn_test_addxi_X0.c insn_test_addxi_X1.c \
- insn_test_addxi_Y0.c insn_test_addxi_Y1.c \
- insn_test_addxli_X0.c insn_test_addxli_X1.c \
- insn_test_addxsc_X0.c insn_test_addxsc_X1.c insn_test_and_X0.c \
- insn_test_and_X1.c insn_test_and_Y0.c insn_test_and_Y1.c \
- insn_test_andi_X0.c insn_test_andi_X1.c insn_test_andi_Y0.c \
- insn_test_andi_Y1.c insn_test_beqz_X1.c insn_test_beqzt_X1.c \
- insn_test_bfexts_X0.c insn_test_bfextu_X0.c \
- insn_test_bfins_X0.c insn_test_bgez_X1.c insn_test_bgezt_X1.c \
- insn_test_bgtz_X1.c insn_test_bgtzt_X1.c insn_test_blbc_X1.c \
- insn_test_blbct_X1.c insn_test_blbs_X1.c insn_test_blbst_X1.c \
- insn_test_blez_X1.c insn_test_blezt_X1.c insn_test_bltz_X1.c \
- insn_test_bltzt_X1.c insn_test_bnez_X1.c insn_test_bnezt_X1.c \
- insn_test_clz_X0.c insn_test_clz_Y0.c insn_test_cmoveqz_X0.c \
- insn_test_cmoveqz_Y0.c insn_test_cmovnez_X0.c \
- insn_test_cmovnez_Y0.c insn_test_cmpeq_X0.c \
- insn_test_cmpeq_X1.c insn_test_cmpeq_Y0.c insn_test_cmpeq_Y1.c \
- insn_test_cmpeqi_X0.c insn_test_cmpeqi_X1.c \
- insn_test_cmpeqi_Y0.c insn_test_cmpeqi_Y1.c \
- insn_test_cmples_X0.c insn_test_cmples_X1.c \
- insn_test_cmples_Y0.c insn_test_cmples_Y1.c \
- insn_test_cmpleu_X0.c insn_test_cmpleu_X1.c \
- insn_test_cmpleu_Y0.c insn_test_cmpleu_Y1.c \
- insn_test_cmplts_X0.c insn_test_cmplts_X1.c \
- insn_test_cmplts_Y0.c insn_test_cmplts_Y1.c \
- insn_test_cmpltsi_X0.c insn_test_cmpltsi_X1.c \
- insn_test_cmpltsi_Y0.c insn_test_cmpltsi_Y1.c \
- insn_test_cmpltu_X0.c insn_test_cmpltu_X1.c \
- insn_test_cmpltu_Y0.c insn_test_cmpltu_Y1.c \
- insn_test_cmpltui_X0.c insn_test_cmpltui_X1.c \
- insn_test_cmpne_X0.c insn_test_cmpne_X1.c insn_test_cmpne_Y0.c \
- insn_test_cmpne_Y1.c insn_test_cmul_X0.c insn_test_cmula_X0.c \
- insn_test_cmulaf_X0.c insn_test_cmulf_X0.c \
- insn_test_cmulfr_X0.c insn_test_cmulh_X0.c \
- insn_test_cmulhr_X0.c insn_test_crc32_32_X0.c \
- insn_test_crc32_8_X0.c insn_test_ctz_X0.c insn_test_ctz_Y0.c \
- insn_test_dblalign2_X0.c insn_test_dblalign2_X1.c \
- insn_test_dblalign4_X0.c insn_test_dblalign4_X1.c \
- insn_test_dblalign6_X0.c insn_test_dblalign6_X1.c \
- insn_test_dblalign_X0.c insn_test_dtlbpr_X1.c \
- insn_test_fdouble_add_flags_X0.c insn_test_fdouble_addsub_X0.c \
- insn_test_fdouble_mul_flags_X0.c insn_test_fdouble_pack1_X0.c \
- insn_test_fdouble_pack2_X0.c insn_test_fdouble_sub_flags_X0.c \
- insn_test_fdouble_unpack_max_X0.c \
- insn_test_fdouble_unpack_min_X0.c insn_test_flushwb_X1.c \
- insn_test_fnop_X0.c insn_test_fnop_X1.c insn_test_fnop_Y0.c \
- insn_test_fnop_Y1.c insn_test_fsingle_add1_X0.c \
- insn_test_fsingle_addsub2_X0.c insn_test_fsingle_mul1_X0.c \
- insn_test_fsingle_mul2_X0.c insn_test_fsingle_pack1_X0.c \
- insn_test_fsingle_pack1_Y0.c insn_test_fsingle_pack2_X0.c \
- insn_test_fsingle_sub1_X0.c insn_test_icoh_X1.c \
- insn_test_j_X1.c insn_test_jal_X1.c insn_test_jalr_X1.c \
- insn_test_jalr_Y1.c insn_test_jalrp_X1.c insn_test_jalrp_Y1.c \
- insn_test_jr_X1.c insn_test_jr_Y1.c insn_test_jrp_X1.c \
- insn_test_jrp_Y1.c insn_test_ld1s_X1.c insn_test_ld1s_Y2.c \
- insn_test_ld1s_add_X1.c insn_test_ld1u_X1.c \
- insn_test_ld1u_Y2.c insn_test_ld1u_add_X1.c \
- insn_test_ld2s_X1.c insn_test_ld2s_Y2.c insn_test_ld2u_X1.c \
- insn_test_ld2u_Y2.c insn_test_ld4s_X1.c \
- insn_test_ld4s_add_X1.c insn_test_ld4u_X1.c \
- insn_test_ld4u_Y2.c insn_test_ld4u_add_X1.c insn_test_ld_X1.c \
- insn_test_ld_Y2.c insn_test_ld_add_X1.c insn_test_ldna_X1.c \
- insn_test_ldna_add_X1.c insn_test_ldnt1s_X1.c \
- insn_test_ldnt1s_add_X1.c insn_test_ldnt1u_X1.c \
- insn_test_ldnt1u_add_X1.c insn_test_ldnt2s_X1.c \
- insn_test_ldnt2s_add_X1.c insn_test_ldnt2u_add_X1.c \
- insn_test_ldnt4s_X1.c insn_test_ldnt4s_add_X1.c \
- insn_test_ldnt4u_X1.c insn_test_ldnt4u_add_X1.c \
- insn_test_ldnt_X1.c insn_test_ldnt_add_X1.c insn_test_lnk_X1.c \
- insn_test_lnk_Y1.c insn_test_mf_X1.c insn_test_mm_X0.c \
- insn_test_mnz_X0.c insn_test_mnz_X1.c insn_test_mnz_Y0.c \
- insn_test_mnz_Y1.c insn_test_move_X0.c insn_test_move_X1.c \
- insn_test_move_Y0.c insn_test_move_Y1.c insn_test_movei_X0.c \
- insn_test_movei_X1.c insn_test_movei_Y0.c insn_test_movei_Y1.c \
- insn_test_moveli_X0.c insn_test_moveli_X1.c \
- insn_test_mul_hs_hs_X0.c insn_test_mul_hs_hs_Y0.c \
- insn_test_mul_hs_hu_X0.c insn_test_mul_hs_ls_X0.c \
- insn_test_mul_hs_lu_X0.c insn_test_mul_hu_hu_X0.c \
- insn_test_mul_hu_hu_Y0.c insn_test_mul_hu_lu_X0.c \
- insn_test_mul_ls_ls_X0.c insn_test_mul_ls_ls_Y0.c \
- insn_test_mul_ls_lu_X0.c insn_test_mul_lu_lu_X0.c \
- insn_test_mul_lu_lu_Y0.c insn_test_mula_hs_hs_X0.c \
- insn_test_mula_hs_hs_Y0.c insn_test_mula_hs_hu_X0.c \
- insn_test_mula_hs_ls_X0.c insn_test_mula_hs_lu_X0.c \
- insn_test_mula_hu_hu_X0.c insn_test_mula_hu_hu_Y0.c \
- insn_test_mula_hu_ls_X0.c insn_test_mula_hu_lu_X0.c \
- insn_test_mula_ls_ls_X0.c insn_test_mula_ls_ls_Y0.c \
- insn_test_mula_ls_lu_X0.c insn_test_mula_lu_lu_X0.c \
- insn_test_mula_lu_lu_Y0.c insn_test_mulax_X0.c \
- insn_test_mulax_Y0.c insn_test_mulx_X0.c insn_test_mulx_Y0.c \
- insn_test_mz_X0.c insn_test_mz_X1.c insn_test_mz_Y0.c \
- insn_test_mz_Y1.c insn_test_nop_X0.c insn_test_nop_X1.c \
- insn_test_nop_Y0.c insn_test_nop_Y1.c insn_test_nor_X0.c \
- insn_test_nor_X1.c insn_test_nor_Y0.c insn_test_nor_Y1.c \
- insn_test_or_X0.c insn_test_or_X1.c insn_test_or_Y0.c \
- insn_test_or_Y1.c insn_test_ori_X0.c insn_test_ori_X1.c \
- insn_test_pcnt_X0.c insn_test_pcnt_Y0.c \
- insn_test_prefetch_X1.c insn_test_prefetch_Y2.c \
- insn_test_prefetch_l1_X1.c insn_test_prefetch_l1_Y2.c \
- insn_test_prefetch_l2_X1.c insn_test_prefetch_l2_Y2.c \
- insn_test_prefetch_l3_X1.c insn_test_prefetch_l3_Y2.c \
- insn_test_revbits_X0.c insn_test_revbits_Y0.c \
- insn_test_revbytes_X0.c insn_test_revbytes_Y0.c \
- insn_test_rotl_X0.c insn_test_rotl_X1.c insn_test_rotl_Y0.c \
- insn_test_rotl_Y1.c insn_test_rotli_X0.c insn_test_rotli_X1.c \
- insn_test_rotli_Y0.c insn_test_rotli_Y1.c \
- insn_test_shl16insli_X0.c insn_test_shl16insli_X1.c \
- insn_test_shl1add_X0.c insn_test_shl1add_X1.c \
- insn_test_shl1add_Y0.c insn_test_shl1add_Y1.c \
- insn_test_shl1addx_X0.c insn_test_shl1addx_X1.c \
- insn_test_shl1addx_Y0.c insn_test_shl1addx_Y1.c \
- insn_test_shl2add_X0.c insn_test_shl2add_X1.c \
- insn_test_shl2add_Y0.c insn_test_shl2add_Y1.c \
- insn_test_shl2addx_X0.c insn_test_shl2addx_X1.c \
- insn_test_shl2addx_Y0.c insn_test_shl2addx_Y1.c \
- insn_test_shl3add_X0.c insn_test_shl3add_X1.c \
- insn_test_shl3add_Y0.c insn_test_shl3add_Y1.c \
- insn_test_shl3addx_X0.c insn_test_shl3addx_X1.c \
- insn_test_shl3addx_Y0.c insn_test_shl3addx_Y1.c \
- insn_test_shl_X0.c insn_test_shl_X1.c insn_test_shl_Y0.c \
- insn_test_shl_Y1.c insn_test_shli_X0.c insn_test_shli_X1.c \
- insn_test_shli_Y0.c insn_test_shli_Y1.c insn_test_shlx_X0.c \
- insn_test_shlx_X1.c insn_test_shlxi_X0.c insn_test_shlxi_X1.c \
- insn_test_shrs_X0.c insn_test_shrs_X1.c insn_test_shrs_Y0.c \
- insn_test_shrs_Y1.c insn_test_shrsi_X0.c insn_test_shrsi_X1.c \
- insn_test_shrsi_Y0.c insn_test_shrsi_Y1.c insn_test_shru_X0.c \
- insn_test_shru_X1.c insn_test_shru_Y0.c insn_test_shru_Y1.c \
- insn_test_shrui_X0.c insn_test_shrui_X1.c insn_test_shrui_Y0.c \
- insn_test_shrui_Y1.c insn_test_shrux_X0.c insn_test_shrux_X1.c \
- insn_test_shufflebytes_X0.c insn_test_st1_X1.c \
- insn_test_st1_Y2.c insn_test_st1_add_X1.c insn_test_st2_X1.c \
- insn_test_st2_Y2.c insn_test_st2_add_X1.c insn_test_st4_X1.c \
- insn_test_st4_Y2.c insn_test_st4_add_X1.c insn_test_st_X1.c \
- insn_test_st_Y2.c insn_test_st_add_X1.c insn_test_stnt1_X1.c \
- insn_test_stnt2_X1.c insn_test_stnt2_add_X1.c \
- insn_test_stnt4_X1.c insn_test_stnt4_add_X1.c \
- insn_test_stnt_X1.c insn_test_stnt_add_X1.c insn_test_sub_X0.c \
- insn_test_sub_X1.c insn_test_sub_Y0.c insn_test_sub_Y1.c \
- insn_test_subx_X0.c insn_test_subx_X1.c insn_test_subx_Y0.c \
- insn_test_subx_Y1.c insn_test_tblidxb0_X0.c \
- insn_test_tblidxb0_Y0.c insn_test_tblidxb1_X0.c \
- insn_test_tblidxb1_Y0.c insn_test_tblidxb2_X0.c \
- insn_test_tblidxb2_Y0.c insn_test_tblidxb3_X0.c \
- insn_test_tblidxb3_Y0.c insn_test_v1add_X0.c \
- insn_test_v1add_X1.c insn_test_v1adduc_X0.c \
- insn_test_v1adduc_X1.c insn_test_v1adiffu_X0.c \
- insn_test_v1avgu_X0.c insn_test_v1cmpeq_X0.c \
- insn_test_v1cmpeq_X1.c insn_test_v1cmpeqi_X0.c \
- insn_test_v1cmpeqi_X1.c insn_test_v1cmples_X0.c \
- insn_test_v1cmples_X1.c insn_test_v1cmpleu_X0.c \
- insn_test_v1cmpleu_X1.c insn_test_v1cmplts_X0.c \
- insn_test_v1cmplts_X1.c insn_test_v1cmpltu_X0.c \
- insn_test_v1cmpltu_X1.c insn_test_v1cmpne_X0.c \
- insn_test_v1cmpne_X1.c insn_test_v1ddotpu_X0.c \
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-AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@
-AM_CFLAGS_PSO_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@ \
- $(AM_CFLAGS_PSO_BASE)
-
-AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -g @FLAG_MIPS32@
-AM_FLAG_M3264_MIPS64_LINUX = @FLAG_M64@
-AM_CFLAGS_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@
-AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@ \
- $(AM_CFLAGS_PSO_BASE)
-
-AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
-AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
-AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
- $(AM_CFLAGS_BASE) -fomit-frame-pointer \
- @SOLARIS_UNDEF_LARGESOURCE@
-
-AM_CFLAGS_PSO_X86_SOLARIS = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
-AM_CCASFLAGS_X86_SOLARIS = @FLAG_M32@ -g -D_ASM
-AM_FLAG_M3264_AMD64_SOLARIS = @FLAG_M64@
-AM_CFLAGS_AMD64_SOLARIS = @FLAG_M64@ \
- $(AM_CFLAGS_BASE) -fomit-frame-pointer
-
-AM_CFLAGS_PSO_AMD64_SOLARIS = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
-AM_CCASFLAGS_AMD64_SOLARIS = @FLAG_M64@ -g -D_ASM
-
-# Flags for the primary target. These must be used to build the
-# regtests and performance tests. In fact, these must be used to
-# build anything which is built only once on a dual-arch build.
-#
-AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
-AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
-AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
-AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
-@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
-@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
-
-# Baseline link flags for making vgpreload shared objects.
-#
-PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
- -Wl,-z,interpose,-z,initfirst $(am__append_3)
-PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
-PRELOAD_LDFLAGS_COMMON_SOLARIS = -nodefaultlibs -shared \
- -Wl,-z,interpose,-z,initfirst $(am__append_2)
-PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
-PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
-PRELOAD_LDFLAGS_PPC64BE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
-PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
-PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
-PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
-PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
-PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
-AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
- -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
- -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \
- -DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \
- -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
- -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
- $(am__append_4)
-
-# Nb: Tools need to augment these flags with an arch-selection option, such
-# as $(AM_FLAG_M3264_PRI).
-AM_CFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
- @FLAG_FNO_STACK_PROTECTOR@ $(am__append_5) $(am__append_6) \
- @FLAG_M64@ -w
-AM_CXXFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
- @FLAG_FNO_STACK_PROTECTOR@ $(am__append_7) @FLAG_M64@
-# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
-# automake; see comments in Makefile.all.am for more detail.
-AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M64@
-@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
-dist_noinst_SCRIPTS = \
- filter_stderr
-
-EXTRA_DIST = gen_test.sh $(am__append_8)
-insn_tests = insn_test_move_X0 insn_test_move_X1 insn_test_move_Y0 \
- insn_test_move_Y1 insn_test_movei_X0 insn_test_movei_X1 \
- insn_test_movei_Y0 insn_test_movei_Y1 insn_test_moveli_X0 \
- insn_test_moveli_X1 insn_test_prefetch_X1 \
- insn_test_prefetch_Y2 insn_test_prefetch_l1_X1 \
- insn_test_prefetch_l1_Y2 insn_test_prefetch_l2_X1 \
- insn_test_prefetch_l2_Y2 insn_test_prefetch_l3_X1 \
- insn_test_prefetch_l3_Y2 insn_test_add_X0 insn_test_add_X1 \
- insn_test_add_Y0 insn_test_add_Y1 insn_test_addi_X0 \
- insn_test_addi_X1 insn_test_addi_Y0 insn_test_addi_Y1 \
- insn_test_addli_X0 insn_test_addli_X1 insn_test_addx_X0 \
- insn_test_addx_X1 insn_test_addx_Y0 insn_test_addx_Y1 \
- insn_test_addxi_X0 insn_test_addxi_X1 insn_test_addxi_Y0 \
- insn_test_addxi_Y1 insn_test_addxli_X0 insn_test_addxli_X1 \
- insn_test_addxsc_X0 insn_test_addxsc_X1 insn_test_and_X0 \
- insn_test_and_X1 insn_test_and_Y0 insn_test_and_Y1 \
- insn_test_andi_X0 insn_test_andi_X1 insn_test_andi_Y0 \
- insn_test_andi_Y1 insn_test_beqz_X1 insn_test_beqzt_X1 \
- insn_test_bfexts_X0 insn_test_bfextu_X0 insn_test_bfins_X0 \
- insn_test_bgez_X1 insn_test_bgezt_X1 insn_test_bgtz_X1 \
- insn_test_bgtzt_X1 insn_test_blbc_X1 insn_test_blbct_X1 \
- insn_test_blbs_X1 insn_test_blbst_X1 insn_test_blez_X1 \
- insn_test_blezt_X1 insn_test_bltz_X1 insn_test_bltzt_X1 \
- insn_test_bnez_X1 insn_test_bnezt_X1 insn_test_clz_X0 \
- insn_test_clz_Y0 insn_test_cmoveqz_X0 insn_test_cmoveqz_Y0 \
- insn_test_cmovnez_X0 insn_test_cmovnez_Y0 insn_test_cmpeq_X0 \
- insn_test_cmpeq_X1 insn_test_cmpeq_Y0 insn_test_cmpeq_Y1 \
- insn_test_cmpeqi_X0 insn_test_cmpeqi_X1 insn_test_cmpeqi_Y0 \
- insn_test_cmpeqi_Y1 insn_test_cmples_X0 insn_test_cmples_X1 \
- insn_test_cmples_Y0 insn_test_cmples_Y1 insn_test_cmpleu_X0 \
- insn_test_cmpleu_X1 insn_test_cmpleu_Y0 insn_test_cmpleu_Y1 \
- insn_test_cmplts_X0 insn_test_cmplts_X1 insn_test_cmplts_Y0 \
- insn_test_cmplts_Y1 insn_test_cmpltsi_X0 insn_test_cmpltsi_X1 \
- insn_test_cmpltsi_Y0 insn_test_cmpltsi_Y1 insn_test_cmpltu_X0 \
- insn_test_cmpltu_X1 insn_test_cmpltu_Y0 insn_test_cmpltu_Y1 \
- insn_test_cmpltui_X0 insn_test_cmpltui_X1 insn_test_cmpne_X0 \
- insn_test_cmpne_X1 insn_test_cmpne_Y0 insn_test_cmpne_Y1 \
- insn_test_cmul_X0 insn_test_cmula_X0 insn_test_cmulaf_X0 \
- insn_test_cmulf_X0 insn_test_cmulfr_X0 insn_test_cmulh_X0 \
- insn_test_cmulhr_X0 insn_test_crc32_32_X0 insn_test_crc32_8_X0 \
- insn_test_ctz_X0 insn_test_ctz_Y0 insn_test_dblalign_X0 \
- insn_test_dblalign2_X0 insn_test_dblalign2_X1 \
- insn_test_dblalign4_X0 insn_test_dblalign4_X1 \
- insn_test_dblalign6_X0 insn_test_dblalign6_X1 \
- insn_test_dtlbpr_X1 insn_test_fdouble_add_flags_X0 \
- insn_test_fdouble_addsub_X0 insn_test_fdouble_mul_flags_X0 \
- insn_test_fdouble_pack1_X0 insn_test_fdouble_pack2_X0 \
- insn_test_fdouble_sub_flags_X0 insn_test_fdouble_unpack_max_X0 \
- insn_test_fdouble_unpack_min_X0 insn_test_flushwb_X1 \
- insn_test_fnop_X0 insn_test_fnop_X1 insn_test_fnop_Y0 \
- insn_test_fnop_Y1 insn_test_fsingle_add1_X0 \
- insn_test_fsingle_addsub2_X0 insn_test_fsingle_mul1_X0 \
- insn_test_fsingle_mul2_X0 insn_test_fsingle_pack1_X0 \
- insn_test_fsingle_pack1_Y0 insn_test_fsingle_pack2_X0 \
- insn_test_fsingle_sub1_X0 insn_test_icoh_X1 insn_test_j_X1 \
- insn_test_jal_X1 insn_test_jalr_X1 insn_test_jalr_Y1 \
- insn_test_jalrp_X1 insn_test_jalrp_Y1 insn_test_jr_X1 \
- insn_test_jr_Y1 insn_test_jrp_X1 insn_test_jrp_Y1 \
- insn_test_ld_X1 insn_test_ld_Y2 insn_test_ld1s_X1 \
- insn_test_ld1s_Y2 insn_test_ld1s_add_X1 insn_test_ld1u_X1 \
- insn_test_ld1u_Y2 insn_test_ld1u_add_X1 insn_test_ld2s_X1 \
- insn_test_ld2s_Y2 insn_test_ld2u_X1 insn_test_ld2u_Y2 \
- insn_test_ld4s_X1 insn_test_ld4s_add_X1 insn_test_ld4u_X1 \
- insn_test_ld4u_Y2 insn_test_ld4u_add_X1 insn_test_ld_add_X1 \
- insn_test_ldna_X1 insn_test_ldna_add_X1 insn_test_ldnt_X1 \
- insn_test_ldnt1s_X1 insn_test_ldnt1s_add_X1 \
- insn_test_ldnt1u_X1 insn_test_ldnt1u_add_X1 \
- insn_test_ldnt2s_X1 insn_test_ldnt2s_add_X1 \
- insn_test_ldnt2u_add_X1 insn_test_ldnt4s_X1 \
- insn_test_ldnt4s_add_X1 insn_test_ldnt4u_X1 \
- insn_test_ldnt4u_add_X1 insn_test_ldnt_add_X1 insn_test_lnk_X1 \
- insn_test_lnk_Y1 insn_test_mf_X1 insn_test_mm_X0 \
- insn_test_mnz_X0 insn_test_mnz_X1 insn_test_mnz_Y0 \
- insn_test_mnz_Y1 insn_test_mul_hs_hs_X0 insn_test_mul_hs_hs_Y0 \
- insn_test_mul_hs_hu_X0 insn_test_mul_hs_ls_X0 \
- insn_test_mul_hs_lu_X0 insn_test_mul_hu_hu_X0 \
- insn_test_mul_hu_hu_Y0 insn_test_mul_hu_lu_X0 \
- insn_test_mul_ls_ls_X0 insn_test_mul_ls_ls_Y0 \
- insn_test_mul_ls_lu_X0 insn_test_mul_lu_lu_X0 \
- insn_test_mul_lu_lu_Y0 insn_test_mula_hs_hs_X0 \
- insn_test_mula_hs_hs_Y0 insn_test_mula_hs_hu_X0 \
- insn_test_mula_hs_ls_X0 insn_test_mula_hs_lu_X0 \
- insn_test_mula_hu_hu_X0 insn_test_mula_hu_hu_Y0 \
- insn_test_mula_hu_ls_X0 insn_test_mula_hu_lu_X0 \
- insn_test_mula_ls_ls_X0 insn_test_mula_ls_ls_Y0 \
- insn_test_mula_ls_lu_X0 insn_test_mula_lu_lu_X0 \
- insn_test_mula_lu_lu_Y0 insn_test_mulax_X0 insn_test_mulax_Y0 \
- insn_test_mulx_X0 insn_test_mulx_Y0 insn_test_mz_X0 \
- insn_test_mz_X1 insn_test_mz_Y0 insn_test_mz_Y1 \
- insn_test_nop_X0 insn_test_nop_X1 insn_test_nop_Y0 \
- insn_test_nop_Y1 insn_test_nor_X0 insn_test_nor_X1 \
- insn_test_nor_Y0 insn_test_nor_Y1 insn_test_or_X0 \
- insn_test_or_X1 insn_test_or_Y0 insn_test_or_Y1 \
- insn_test_ori_X0 insn_test_ori_X1 insn_test_pcnt_X0 \
- insn_test_pcnt_Y0 insn_test_revbits_X0 insn_test_revbits_Y0 \
- insn_test_revbytes_X0 insn_test_revbytes_Y0 insn_test_rotl_X0 \
- insn_test_rotl_X1 insn_test_rotl_Y0 insn_test_rotl_Y1 \
- insn_test_rotli_X0 insn_test_rotli_X1 insn_test_rotli_Y0 \
- insn_test_rotli_Y1 insn_test_shl_X0 insn_test_shl_X1 \
- insn_test_shl_Y0 insn_test_shl_Y1 insn_test_shl16insli_X0 \
- insn_test_shl16insli_X1 insn_test_shl1add_X0 \
- insn_test_shl1add_X1 insn_test_shl1add_Y0 insn_test_shl1add_Y1 \
- insn_test_shl1addx_X0 insn_test_shl1addx_X1 \
- insn_test_shl1addx_Y0 insn_test_shl1addx_Y1 \
- insn_test_shl2add_X0 insn_test_shl2add_X1 insn_test_shl2add_Y0 \
- insn_test_shl2add_Y1 insn_test_shl2addx_X0 \
- insn_test_shl2addx_X1 insn_test_shl2addx_Y0 \
- insn_test_shl2addx_Y1 insn_test_shl3add_X0 \
- insn_test_shl3add_X1 insn_test_shl3add_Y0 insn_test_shl3add_Y1 \
- insn_test_shl3addx_X0 insn_test_shl3addx_X1 \
- insn_test_shl3addx_Y0 insn_test_shl3addx_Y1 insn_test_shli_X0 \
- insn_test_shli_X1 insn_test_shli_Y0 insn_test_shli_Y1 \
- insn_test_shlx_X0 insn_test_shlx_X1 insn_test_shlxi_X0 \
- insn_test_shlxi_X1 insn_test_shrs_X0 insn_test_shrs_X1 \
- insn_test_shrs_Y0 insn_test_shrs_Y1 insn_test_shrsi_X0 \
- insn_test_shrsi_X1 insn_test_shrsi_Y0 insn_test_shrsi_Y1 \
- insn_test_shru_X0 insn_test_shru_X1 insn_test_shru_Y0 \
- insn_test_shru_Y1 insn_test_shrui_X0 insn_test_shrui_X1 \
- insn_test_shrui_Y0 insn_test_shrui_Y1 insn_test_shrux_X0 \
- insn_test_shrux_X1 insn_test_shufflebytes_X0 insn_test_st_X1 \
- insn_test_st_Y2 insn_test_st1_X1 insn_test_st1_Y2 \
- insn_test_st1_add_X1 insn_test_st2_X1 insn_test_st2_Y2 \
- insn_test_st2_add_X1 insn_test_st4_X1 insn_test_st4_Y2 \
- insn_test_st4_add_X1 insn_test_st_add_X1 insn_test_stnt_X1 \
- insn_test_stnt1_X1 insn_test_stnt2_X1 insn_test_stnt2_add_X1 \
- insn_test_stnt4_X1 insn_test_stnt4_add_X1 \
- insn_test_stnt_add_X1 insn_test_sub_X0 insn_test_sub_X1 \
- insn_test_sub_Y0 insn_test_sub_Y1 insn_test_subx_X0 \
- insn_test_subx_X1 insn_test_subx_Y0 insn_test_subx_Y1 \
- insn_test_tblidxb0_X0 insn_test_tblidxb0_Y0 \
- insn_test_tblidxb1_X0 insn_test_tblidxb1_Y0 \
- insn_test_tblidxb2_X0 insn_test_tblidxb2_Y0 \
- insn_test_tblidxb3_X0 insn_test_tblidxb3_Y0 insn_test_v1add_X0 \
- insn_test_v1add_X1 insn_test_v1adduc_X0 insn_test_v1adduc_X1 \
- insn_test_v1adiffu_X0 insn_test_v1avgu_X0 insn_test_v1cmpeq_X0 \
- insn_test_v1cmpeq_X1 insn_test_v1cmpeqi_X0 \
- insn_test_v1cmpeqi_X1 insn_test_v1cmples_X0 \
- insn_test_v1cmples_X1 insn_test_v1cmpleu_X0 \
- insn_test_v1cmpleu_X1 insn_test_v1cmplts_X0 \
- insn_test_v1cmplts_X1 insn_test_v1cmpltu_X0 \
- insn_test_v1cmpltu_X1 insn_test_v1cmpne_X0 \
- insn_test_v1cmpne_X1 insn_test_v1ddotpu_X0 \
- insn_test_v1ddotpua_X0 insn_test_v1ddotpus_X0 \
- insn_test_v1ddotpusa_X0 insn_test_v1dotp_X0 \
- insn_test_v1dotpa_X0 insn_test_v1dotpu_X0 \
- insn_test_v1dotpua_X0 insn_test_v1dotpus_X0 \
- insn_test_v1dotpusa_X0 insn_test_v1int_h_X0 \
- insn_test_v1int_h_X1 insn_test_v1int_l_X0 insn_test_v1int_l_X1 \
- insn_test_v1maxu_X0 insn_test_v1maxu_X1 insn_test_v1minu_X0 \
- insn_test_v1minu_X1 insn_test_v1mnz_X0 insn_test_v1mnz_X1 \
- insn_test_v1multu_X0 insn_test_v1mulu_X0 insn_test_v1mulus_X0 \
- insn_test_v1mz_X0 insn_test_v1mz_X1 insn_test_v1sadau_X0 \
- insn_test_v1sadu_X0 insn_test_v1shl_X0 insn_test_v1shl_X1 \
- insn_test_v1shli_X0 insn_test_v1shli_X1 insn_test_v1shrs_X0 \
- insn_test_v1shrs_X1 insn_test_v1shrsi_X0 insn_test_v1shrsi_X1 \
- insn_test_v1shru_X0 insn_test_v1shru_X1 insn_test_v1shrui_X0 \
- insn_test_v1shrui_X1 insn_test_v1sub_X0 insn_test_v1sub_X1 \
- insn_test_v1subuc_X0 insn_test_v1subuc_X1 insn_test_v2add_X0 \
- insn_test_v2add_X1 insn_test_v2addsc_X0 insn_test_v2addsc_X1 \
- insn_test_v2adiffs_X0 insn_test_v2avgs_X0 insn_test_v2cmpeq_X0 \
- insn_test_v2cmpeq_X1 insn_test_v2cmpeqi_X0 \
- insn_test_v2cmpeqi_X1 insn_test_v2cmples_X0 \
- insn_test_v2cmples_X1 insn_test_v2cmpleu_X0 \
- insn_test_v2cmpleu_X1 insn_test_v2cmplts_X0 \
- insn_test_v2cmplts_X1 insn_test_v2cmpltsi_X0 \
- insn_test_v2cmpltsi_X1 insn_test_v2cmpltu_X0 \
- insn_test_v2cmpltu_X1 insn_test_v2cmpltui_X0 \
- insn_test_v2cmpltui_X1 insn_test_v2cmpne_X0 \
- insn_test_v2cmpne_X1 insn_test_v2dotp_X0 insn_test_v2dotpa_X0 \
- insn_test_v2int_h_X0 insn_test_v2int_h_X1 insn_test_v2int_l_X0 \
- insn_test_v2int_l_X1 insn_test_v2maxs_X0 insn_test_v2maxs_X1 \
- insn_test_v2mins_X0 insn_test_v2mins_X1 insn_test_v2mnz_X0 \
- insn_test_v2mnz_X1 insn_test_v2mulfsc_X0 insn_test_v2muls_X0 \
- insn_test_v2mults_X0 insn_test_v2mz_X0 insn_test_v2mz_X1 \
- insn_test_v2packh_X0 insn_test_v2packh_X1 insn_test_v2packl_X0 \
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-.PRECIOUS: Makefile
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-
-#----------------------------------------------------------------------------
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-# executes 'dsymutil' after linking, but that's a pain. Instead we use this
-# hook so that every time "make check" is run, we subsequently invoke
-# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
-# newer than their corresponding .dSYM directory.
-build-noinst_DSYMS: $(noinst_DSYMS)
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- if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
- echo "dsymutil $$f"; \
- dsymutil $$f; \
- fi; \
- done
-
-# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
-# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
-# It needs to be depended on by an 'all-local' rule.
-inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
- mkdir -p $(inplacedir); \
- for f in $(noinst_PROGRAMS) ; do \
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-# Similar to inplace-noinst_PROGRAMS
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- mkdir -p $(inplacedir); \
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- done
-
-# Similar to install-noinst_PROGRAMS.
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-# correct when using 'cp -R'...
-install-noinst_DSYMS: build-noinst_DSYMS
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-clean-noinst_DSYMS:
- for f in $(noinst_DSYMS); do \
- rm -rf $$f.dSYM; \
- done
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-check-local: build-noinst_DSYMS
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-
-$(addsuffix .c, $(insn_tests)) : gen_insn_test
- @$(srcdir)/gen_test.sh $@
-
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-
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- touch $@
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-distclean-am : clean-am
-
-# Tell versions [3.59,3.63) of GNU make to not export all variables.
-# Otherwise a system limit (for SysV at least) may be exceeded.
-.NOEXPORT:
diff --git a/none/tests/tilegx/allexec.c b/none/tests/tilegx/allexec.c
deleted file mode 100644
index 69e1208..0000000
--- a/none/tests/tilegx/allexec.c
+++ /dev/null
@@ -1,56 +0,0 @@
-#include <assert.h>
-#include <stdio.h>
-#include <string.h>
-#include <sys/types.h>
-#include <sys/wait.h>
-#include <unistd.h>
-
-extern char **environ;
-
-#define S(...) (fprintf(stdout, __VA_ARGS__),fflush(stdout))
-#define FORKEXECWAIT(exec_call) do { \
- int status;\
- pid_t child = fork(); \
- if (child == 0) {exec_call; perror ("exec failed");} \
- else if (child == -1) perror ("cannot fork\n"); \
- else if (child != wait (&status)) perror ("error waiting child"); \
- else S("child exited\n"); \
- } while (0)
-
-void test_allexec (char *exec)
-{
- FORKEXECWAIT (execlp(exec, exec, (char *) NULL));
- FORKEXECWAIT (execlp(exec, exec, "constant_arg1", "constant_arg2",
- (char *) NULL));
- {
- /* Solaris requires that the argv parameter to execve() isn't NULL, so
- set it. Note that this isn't necessary on Linux. */
- char *const argv[] = {exec, NULL};
- FORKEXECWAIT (execve(exec, argv, environ));
- }
-}
-
-
-/* If a single argument "exec" is given, will execute itself
- (in bi-arch, a 32 bit and 64 bit variant) via various exec system calls.
- Note that this test can only be run after the prerequisite have been
- prepared by allexec_prepare_prereq, which will a.o. make links
- for the allexec32 and allexec64 executables. On single arch build,
- these links points to the same executable to ensure this test works
- everywhere the same.
- No arguments or more arguments means just print its args. */
-int main(int argc, char **argv, char **envp)
-{
- if ( (argc == 2) && (strcmp (argv[1], "exec") == 0)) {
- S("%s will exec ./allexec32\n", argv[0]);
- test_allexec ("./allexec32");
- S("%s will exec ./allexec64\n", argv[0]);
- test_allexec ("./allexec64");
- } else {
- int i;
- S("program exec-ed:");
- for (i = 0; i < argc; i++) S(" %s", argv[i]);
- S("\n");
- }
- return 0;
-}
diff --git a/none/tests/tilegx/filter_stderr b/none/tests/tilegx/filter_stderr
deleted file mode 100644
index 616ce05..0000000
--- a/none/tests/tilegx/filter_stderr
+++ /dev/null
@@ -1,4 +0,0 @@
-#! /bin/sh
-
-../filter_stderr
-
diff --git a/none/tests/tilegx/gen_insn_test.c b/none/tests/tilegx/gen_insn_test.c
deleted file mode 100644
index d3a6ad5..0000000
--- a/none/tests/tilegx/gen_insn_test.c
+++ /dev/null
@@ -1,711 +0,0 @@
-//gcc a.c ../../../VEX/priv/tilegx_disasm.c -I ../../../ -I ../../../VEX/priv/ -I ../../../VEX/pub/
-
-#include <stdio.h>
-#include <stdint.h>
-#include <string.h>
-#include <stdlib.h>
-#include "tilegx_disasm.h"
-
-#undef DGB
-
-static unsigned char op_abnorm[TILEGX_OPC_NONE] = {
- /* Black list */
- [ TILEGX_OPC_BPT ] = 1,
- [ TILEGX_OPC_INFO ] = 1,
- [ TILEGX_OPC_INFOL ] = 1,
- [ TILEGX_OPC_DRAIN ] = 1,
- [ TILEGX_OPC_IRET ] = 1,
- [ TILEGX_OPC_SWINT0 ] = 1,
- [ TILEGX_OPC_SWINT1 ] = 1,
- [ TILEGX_OPC_SWINT2 ] = 1,
- [ TILEGX_OPC_SWINT3 ] = 1,
- [ TILEGX_OPC_LD4S_TLS ] = 1,
- [ TILEGX_OPC_LD_TLS ] = 1,
- [ TILEGX_OPC_MFSPR ] = 1,
- [ TILEGX_OPC_MTSPR ] = 1,
- [ TILEGX_OPC_ILL ] = 1,
- [ TILEGX_OPC_NAP ] = 1,
-
- /* mem load */
- [ TILEGX_OPC_LD ] = 2,
- [ TILEGX_OPC_LD_ADD ] = 2,
- [ TILEGX_OPC_LD1S ] = 2,
- [ TILEGX_OPC_LD1S_ADD ] = 2,
- [ TILEGX_OPC_LD1U ] = 2,
- [ TILEGX_OPC_LD1U_ADD ] = 2,
- [ TILEGX_OPC_LD2S ] = 2,
- [ TILEGX_OPC_LD2S_ADD ] = 2,
- [ TILEGX_OPC_LD2U ] = 2,
- [ TILEGX_OPC_LD2U_ADD ] = 2,
- [ TILEGX_OPC_LD4S ] = 2,
- [ TILEGX_OPC_LD4S_ADD ] = 2,
- [ TILEGX_OPC_LD4U ] = 2,
- [ TILEGX_OPC_LD4U_ADD ] = 2,
- [ TILEGX_OPC_LDNA ] = 2,
- [ TILEGX_OPC_LDNA_ADD ] = 2,
- [ TILEGX_OPC_LDNT ] = 2,
- [ TILEGX_OPC_LDNT1S ] = 2,
- [ TILEGX_OPC_LDNT1S_ADD ] = 2,
- [ TILEGX_OPC_LDNT1U ] = 2,
- [ TILEGX_OPC_LDNT1U_ADD ] = 2,
- [ TILEGX_OPC_LDNT2S ] = 2,
- [ TILEGX_OPC_LDNT2S_ADD ] = 2,
- [ TILEGX_OPC_LDNT2U ] = 2,
- [ TILEGX_OPC_LDNT2U_ADD ] = 2,
- [ TILEGX_OPC_LDNT4S ] = 2,
- [ TILEGX_OPC_LDNT4S_ADD ] = 2,
- [ TILEGX_OPC_LDNT4U ] = 2,
- [ TILEGX_OPC_LDNT4U_ADD ] = 2,
- [ TILEGX_OPC_LDNT_ADD ] = 2,
-
- /* mem store */
- [ TILEGX_OPC_ST ] = 4,
- [ TILEGX_OPC_ST1 ] = 4,
- [ TILEGX_OPC_ST1_ADD ] = 4,
- [ TILEGX_OPC_ST2 ] = 4,
- [ TILEGX_OPC_ST2_ADD ] = 4,
- [ TILEGX_OPC_ST4 ] = 4,
- [ TILEGX_OPC_ST4_ADD ] = 4,
- [ TILEGX_OPC_ST_ADD ] = 4,
- [ TILEGX_OPC_STNT ] = 4,
- [ TILEGX_OPC_STNT1 ] = 4,
- [ TILEGX_OPC_STNT1_ADD ] = 4,
- [ TILEGX_OPC_STNT2 ] = 4,
- [ TILEGX_OPC_STNT2_ADD ] = 4,
- [ TILEGX_OPC_STNT4 ] = 4,
- [ TILEGX_OPC_STNT4_ADD ] = 4,
- [ TILEGX_OPC_STNT_ADD ] = 4,
-
- /* conditional branch */
- [ TILEGX_OPC_BEQZ ] = 8,
- [ TILEGX_OPC_BEQZT ] = 8,
- [ TILEGX_OPC_BGEZ ] = 8,
- [ TILEGX_OPC_BGEZT ] = 8,
- [ TILEGX_OPC_BGTZ ] = 8,
- [ TILEGX_OPC_BGTZT ] = 8,
- [ TILEGX_OPC_BLBC ] = 8,
- [ TILEGX_OPC_BLBCT ] = 8,
- [ TILEGX_OPC_BLBS ] = 8,
- [ TILEGX_OPC_BLBST ] = 8,
- [ TILEGX_OPC_BLEZ ] = 8,
- [ TILEGX_OPC_BLEZT ] = 8,
- [ TILEGX_OPC_BLTZ ] = 8,
- [ TILEGX_OPC_BLTZT ] = 8,
- [ TILEGX_OPC_BNEZ ] = 8,
- [ TILEGX_OPC_BNEZT ] = 8,
-};
-
-
-static tilegx_bundle_bits
-encode_insn_tilegx_X (int p, struct tilegx_decoded_instruction decoded);
-
-static tilegx_bundle_bits
-encode_insn_tilegx_Y (int p, struct tilegx_decoded_instruction decoded);
-
-static int decode( tilegx_bundle_bits *p, int count, ULong pc );
-
-static uint64_t
-RAND(int round) {
- static volatile uint64_t rand_seed = 0;
- while (round-- > 0)
- rand_seed = (rand_seed >> 8) * 201520052007 + 1971;
-#ifdef DBG
- printf("RAND: %d\n", (int)rand_seed);
-#endif
- return rand_seed;
-}
-
-
-int main(int argc, char* argv[])
-{
- int i, start, end, pipe;
- struct tilegx_decoded_instruction decoded;
- if (argc == 1) {
- pipe = 0x1F;
- start = 0;
- end = TILEGX_OPC_NONE;
- } else if (argc == 3) {
- start = atoi(argv[1]);
-
- if (start >= TILEGX_OPC_NONE)
- return -1;
-
- end = start + 1;
- /* pipes: X: bit 0,1; Y: bit 2-4 */
- pipe = atoi(argv[2]);
- } else {
- return -1;
- }
-
- for (i = start; i < end; i++) {
- memset(&decoded, 0, sizeof(decoded));
- const struct tilegx_opcode *opcode = &tilegx_opcodes[i];
- decoded.opcode = opcode;
-#ifdef DBG
- const char *op_name = decoded.opcode->name;
- printf("\n\n%d) %s\n", i, op_name);
-#endif
-
- if (op_abnorm[i] & 1)
- continue;
-
- /* X0 pipeline */
- if (tilegx_opcodes[i].pipes & 1 & pipe)
- encode_insn_tilegx_X(0, decoded);
-
- /* X1 pipeline */
- if (tilegx_opcodes[i].pipes & 2 & pipe)
- encode_insn_tilegx_X(1, decoded);
-
- /* Y0 pipleline */
- if (tilegx_opcodes[i].pipes & 4 & pipe)
- encode_insn_tilegx_Y(0, decoded);
-
- /* Y1 pipleline */
- if (tilegx_opcodes[i].pipes & 8 & pipe)
- encode_insn_tilegx_Y(1, decoded);
-
- /* Y2 pipleline */
- if (tilegx_opcodes[i].pipes & 16 & pipe)
- encode_insn_tilegx_Y(2, decoded);
- }
-
- return 0;
-}
-
-static tilegx_bundle_bits
-encode_insn_tilegx_X(int p, struct tilegx_decoded_instruction decoded)
-{
- const struct tilegx_opcode *opc =
- decoded.opcode;
- int op_idx = decoded.opcode->mnemonic;
-
- tilegx_bundle_bits insn = 0;
- //int pipeX01 = (opc->pipes & 0x01) ? 0 : 1;
- int op_num = opc->num_operands;
-
- /* Assume either X0 or X1. */
- if ((opc->pipes & 3) == 0)
- return -1;
-
- /* Insert fnop in other pipe. */
- insn = tilegx_opcodes[TILEGX_OPC_FNOP].
- fixed_bit_values[p ? 0 : 1];
-#ifdef DBG
- printf(" X%d, ", p);
-#endif
-
- insn |= opc->fixed_bit_values[p];
-
- printf("//file: _insn_test_%s_X%d.c\n", decoded.opcode->name, p);
- printf("//op=%d\n", op_idx);
- printf("#include <stdio.h>\n");
- printf("#include <stdlib.h>\n");
-
- printf("\n"
- "void func_exit(void) {\n"
- " printf(\"%cs\\n\", __func__);\n"
- " exit(0);\n"
- "}\n"
- "\n"
- "void func_call(void) {\n"
- " printf(\"%cs\\n\", __func__);\n"
- " exit(0);\n"
- "}\n"
- "\n"
- "unsigned long mem[2] = { 0x%lx, 0x%lx };\n"
- "\n", '%', '%', RAND(op_idx), RAND(op_idx));
-
- printf("int main(void) {\n");
- printf(" unsigned long a[4] = { 0, 0 };\n");
-
- printf(" asm __volatile__ (\n");
-
- int i, n = 0;
-
- if (op_abnorm[op_idx] & 6)
- {
- /* loop for each operand. */
- for (i = 0 ; i < op_num; i++)
- {
- const struct tilegx_operand *opd =
- &tilegx_operands[opc->operands[p][i]];
-
- if (opd->type == TILEGX_OP_TYPE_REGISTER) {
- /* A register operand, pick register 0-50 randomly. */
- decoded.operand_values[i] = RAND(op_idx) % 51;
- int r = decoded.operand_values[i];
- int64_t d = RAND(op_idx);
-#ifdef DBG
- printf(" %d) r%-2d %016lx\n", i, (int)r, (unsigned long)d);
-#endif
- int k = 0;
- for (k = 3; k >= 0 ; k--) {
- if (d >> (16 * k) || k == 0) {
- printf(" \"moveli r%d, %d\\n\"\n", r, (int)(d >> (16 * k)));
- for (k--; k >= 0; k--)
- printf(" \"shl16insli r%d, r%d, %d\\n\"\n", r, r, (int)(int16_t)(d >> (16 * k)));
- break;
- }
- }
- } else {
- /* An immediate operand, pick a random value. */
- decoded.operand_values[i] = RAND(op_idx);
-#ifdef DBG
- printf(" %d) %016lx\n", (int)i, (unsigned long)decoded.operand_values[i]);
-#endif
- }
-
- Long op = decoded.operand_values[i];
- decoded.operands[i] = opd;
- ULong x = opd->insert(op);
- insn |= x;
- }
- printf(" \"");
- if (op_abnorm[op_idx] & 2)
- printf("move r%d, %c2\\n\"\n", (int)decoded.operand_values[1], '%');
- else
- printf("move r%d, %c2\\n\"\n", (int)decoded.operand_values[0], '%');
-
- printf(" \"");
- decode(&insn, 2, 0);
- printf("\\n\"\n");
-
- /* loop for each operand. */
- n = 0;
- for (i = 0 ; i < op_num; i++)
- {
- const struct tilegx_operand *opd =
- &tilegx_operands[opc->operands[p][i]];
-
- if (opd->type == TILEGX_OP_TYPE_REGISTER) {
- /* A register operand */
- printf(" \"move %c%d, r%d\\n\"\n", '%', n, (int)decoded.operand_values[i]);
- n++;
- }
- }
-
- printf(" ");
- if (n)
- printf(":");
- for (i = 0; i < n; i++)
- {
- printf("\"=r\"(a[%d])", i);
- if (i != n - 1)
- printf(",");
- }
- printf(" : \"r\"(mem)");
-
- printf(");\n");
-
- printf(" printf(\"%c016lx %c016lx\\n\", mem[0], mem[1]);\n", '%', '%');
-
- }
- else if (op_idx == TILEGX_OPC_J)
- {
- printf(" \"%s %c0\\n\"\n", decoded.opcode->name, '%');
- printf(" :: \"i\"(func_exit));\n");
- }
- else if (op_idx == TILEGX_OPC_JAL)
- {
- printf(" \"%s %c0\\n\"\n", decoded.opcode->name, '%');
- printf(" :: \"i\"(func_call));\n");
- }
- else if (op_idx == TILEGX_OPC_JR || op_idx == TILEGX_OPC_JRP)
- {
- printf(" \"%s %c0\\n\"\n", decoded.opcode->name, '%');
- printf(" :: \"r\"(func_exit));\n");
- }
- else if (op_idx == TILEGX_OPC_JALR || op_idx == TILEGX_OPC_JALRP )
- {
- printf(" \"%s %c0\\n\"\n", decoded.opcode->name, '%');
- printf(" :: \"r\"(func_call));\n");
- }
- else if (op_abnorm[op_idx] & 8)
- {
- // OPC_BXXX conditional branch
- int r = RAND(op_idx) % 51;
- int d = RAND(op_idx) & 1;
- printf(" \"movei r%d, %d\\n\"\n", r, d);
- printf(" \"%s r%d, %c0\\n\"\n", decoded.opcode->name, r, '%');
- printf(" \"jal %c1\\n\"\n", '%');
- printf(" :: \"i\"(func_exit), \"i\"(func_call));\n");
- }
- else
- {
- /* loop for each operand. */
- for (i = 0 ; i < op_num; i++)
- {
- const struct tilegx_operand *opd =
- &tilegx_operands[opc->operands[p][i]];
-
- if (opd->type == TILEGX_OP_TYPE_REGISTER) {
- /* A register operand, pick register 0-50 randomly. */
- decoded.operand_values[i] = RAND(op_idx) % 51;
- int r = decoded.operand_values[i];
- int64_t d = RAND(op_idx);
-
-#ifdef DBG
- printf(" %d) r%-2d %016lx\n", i, (int)r, (unsigned long)d);
-#endif
- int k = 0;
- for (k = 3; k >= 0 ; k--) {
- if (d >> (16 * k) || k == 0) {
- printf(" \"moveli r%d, %d\\n\"\n", r, (int)(d >> (16 * k)));
- for (k--; k >= 0; k--)
- printf(" \"shl16insli r%d, r%d, %d\\n\"\n", r, r, (int)(int16_t)(d >> (16 * k)));
- break;
- }
- }
- } else {
- /* An immediate operand, pick a random value. */
- decoded.operand_values[i] = RAND(op_idx);
-#ifdef DBG
- printf(" %d) %016lx\n", (int)i, (unsigned long)decoded.operand_values[i]);
-#endif
- }
-
- Long op = decoded.operand_values[i];
- decoded.operands[i] = opd;
- ULong x = opd->insert(op);
- insn |= x;
- }
- printf(" \"");
- decode(&insn, 2, 0);
- printf("\\n\"\n");
-
- /* loop for each operand. */
- n = 0;
- for (i = 0 ; i < op_num; i++)
- {
- const struct tilegx_operand *opd =
- &tilegx_operands[opc->operands[p][i]];
-
- if (opd->type == TILEGX_OP_TYPE_REGISTER) {
- /* A register operand */
- printf(" \"move %c%d, r%d\\n\"\n", '%', n, (int)decoded.operand_values[i]);
- n++;
- }
- }
-
- printf(" ");
- if (n)
- printf(":");
- for (i = 0; i < n; i++)
- {
- printf("\"=r\"(a[%d])", i);
- if (i != n - 1)
- printf(",");
- }
-
- printf(");\n");
- }
-
- for (i = 0; i < n; i++)
- {
- printf(" printf(\"%c016lx\\n\", a[%d]);\n", '%', i);
- }
- printf(" return 0;\n");
- printf("}\n");
- return insn;
-}
-
-static tilegx_bundle_bits
-encode_insn_tilegx_Y (int p, struct tilegx_decoded_instruction decoded )
-{
- int i;
- const struct tilegx_opcode *opc =
- decoded.opcode;
- int op_idx = decoded.opcode->mnemonic;
-
- const struct tilegx_operand *opd;
-
- tilegx_bundle_bits insn = 0;
- Int op_num = opc->num_operands;
-
- /* Insert fnop in Y0 and Y1 pipeline. */
- if (p != 0)
- insn |= tilegx_opcodes[TILEGX_OPC_FNOP].
- fixed_bit_values[2];
-
- if (p != 1)
- insn |= tilegx_opcodes[TILEGX_OPC_FNOP].
- fixed_bit_values[3];
-
- /* Fill-in Y2 as dumy load "ld zero, sp" */
- if (p != 2) {
- insn |= tilegx_opcodes[TILEGX_OPC_LD].
- fixed_bit_values[4];
- opd = &tilegx_operands[tilegx_opcodes[TILEGX_OPC_LD].operands[4][0]];
- insn |= opd->insert(63);
- opd = &tilegx_operands[tilegx_opcodes[TILEGX_OPC_LD].operands[4][1]];
- insn |= opd->insert(54);
- }
-#ifdef DBG
- printf(" Y%d, ", p);
-#endif
-
- insn |= opc->fixed_bit_values[2 + p];
-
- printf("//file: _insn_test_%s_Y%d.c\n", decoded.opcode->name, p);
- printf("//op=%d\n", op_idx);
- printf("#include <stdio.h>\n");
- printf("#include <stdlib.h>\n");
-
- printf("\n"
- "void func_exit(void) {\n"
- " printf(\"%cs\\n\", __func__);\n"
- " exit(0);\n"
- "}\n"
- "\n"
- "void func_call(void) {\n"
- " printf(\"%cs\\n\", __func__);\n"
- " exit(0);\n"
- "}\n"
- "\n"
- "unsigned long mem[2] = { 0x%lx, 0x%lx };\n"
- "\n", '%', '%', RAND(op_idx), RAND(op_idx));
-
- printf("int main(void) {\n");
- printf(" unsigned long a[4] = { 0, 0 };\n");
-
- printf(" asm __volatile__ (\n");
-
- int n = 0;
-
- if (op_abnorm[op_idx] & 6)
- {
- /* loop for each operand. */
- for (i = 0 ; i < op_num; i++)
- {
- opd = &tilegx_operands[opc->operands[2 + p][i]];
-
- if (opd->type == TILEGX_OP_TYPE_REGISTER) {
- /* A register operand, pick register 0-53 randomly. */
- decoded.operand_values[i] = RAND(op_idx) % 53;
- int r = decoded.operand_values[i];
- int64_t d = RAND(op_idx);
-#ifdef DBG
- printf(" %d) r%-2d %016lx\n", i, (int)r, (unsigned long)d);
-#endif
- int k = 0;
- for (k = 3; k >= 0 ; k--) {
- if (d >> (16 * k) || k == 0) {
- printf(" \"moveli r%d, %d\\n\"\n", r, (int)(d >> (16 * k)));
- for (k--; k >= 0; k--)
- printf(" \"shl16insli r%d, r%d, %d\\n\"\n", r, r, (int)(int16_t)(d >> (16 * k)));
- break;
- }
- }
- } else {
- /* An immediate operand, pick a random value. */
- decoded.operand_values[i] = RAND(op_idx);
-#ifdef DBG
- printf(" %d) %016lx\n", (int)i, (unsigned long)decoded.operand_values[i]);
-#endif
- }
-
- Long op = decoded.operand_values[i];
- decoded.operands[i] = opd;
- ULong x = opd->insert(op);
- insn |= x;
- }
- printf(" \"");
- if (op_abnorm[op_idx] & 2)
- printf("move r%d, %c2\\n\"\n", (int)decoded.operand_values[1], '%');
- else
- printf("move r%d, %c2\\n\"\n", (int)decoded.operand_values[0], '%');
-
- printf(" \"");
- decode(&insn, 3, 0);
- printf("\\n\"\n");
-
- /* loop for each operand. */
- n = 0;
- for (i = 0 ; i < op_num; i++)
- {
- opd = &tilegx_operands[opc->operands[2 + p][i]];
-
- if (opd->type == TILEGX_OP_TYPE_REGISTER) {
- /* A register operand */
- printf(" \"move %c%d, r%d\\n\"\n", '%', n, (int)decoded.operand_values[i]);
- n++;
- }
- }
-
- printf(" ");
- if (n)
- printf(":");
- for (i = 0; i < n; i++)
- {
- printf("\"=r\"(a[%d])", i);
- if (i != n - 1)
- printf(",");
- }
- printf(" : \"r\"(mem)");
-
- printf(");\n");
-
- printf(" printf(\"%c016lx %c016lx\\n\", mem[0], mem[1]);\n", '%', '%');
-
- }
- else if (op_idx == TILEGX_OPC_J)
- {
- printf(" \"%s %c0\\n\"\n", decoded.opcode->name, '%');
- printf(" :: \"i\"(func_exit));\n");
- }
- else if (op_idx == TILEGX_OPC_JAL)
- {
- printf(" \"%s %c0\\n\"\n", decoded.opcode->name, '%');
- printf(" :: \"i\"(func_call));\n");
- }
- else if (op_idx == TILEGX_OPC_JR || op_idx == TILEGX_OPC_JRP)
- {
- printf(" \"%s %c0\\n\"\n", decoded.opcode->name, '%');
- printf(" :: \"r\"(func_exit));\n");
- }
- else if (op_idx == TILEGX_OPC_JALR || op_idx == TILEGX_OPC_JALRP )
- {
- printf(" \"%s %c0\\n\"\n", decoded.opcode->name, '%');
- printf(" :: \"r\"(func_call));\n");
- }
- else if (op_abnorm[op_idx] & 8)
- {
- // OPC_BXXX conditional branch
- int r = RAND(op_idx) % 51;
- int d = RAND(op_idx) & 1;
- printf(" \"movei r%d, %d\\n\"\n", r, d);
- printf(" \"%s r%d, %c0\\n\"\n", decoded.opcode->name, r, '%');
- printf(" \"jal %c1\\n\"\n", '%');
- printf(" :: \"i\"(func_exit), \"i\"(func_call));\n");
- }
- else
- {
- /* loop for each operand. */
- for (i = 0 ; i < op_num; i++)
- {
- opd = &tilegx_operands[opc->operands[2 + p][i]];
-
- if (opd->type == TILEGX_OP_TYPE_REGISTER) {
- /* A register operand, pick register 0-50 randomly. */
- decoded.operand_values[i] = RAND(op_idx) % 51;
- int r = decoded.operand_values[i];
- int64_t d = RAND(op_idx);
-
-#ifdef DBG
- printf(" %d) r%-2d %016lx\n", i, (int)r, (unsigned long)d);
-#endif
- int k = 0;
- for (k = 3; k >= 0 ; k--) {
- if (d >> (16 * k) || k == 0) {
- printf(" \"moveli r%d, %d\\n\"\n", r, (int)(d >> (16 * k)));
- for (k--; k >= 0; k--)
- printf(" \"shl16insli r%d, r%d, %d\\n\"\n", r, r, (int)(int16_t)(d >> (16 * k)));
- break;
- }
- }
- } else {
- /* An immediate operand, pick a random value. */
- decoded.operand_values[i] = RAND(op_idx);
-#ifdef DBG
- printf(" %d) %016lx\n", (int)i, (unsigned long)decoded.operand_values[i]);
-#endif
- }
-
- Long op = decoded.operand_values[i];
- decoded.operands[i] = opd;
- ULong x = opd->insert(op);
- insn |= x;
- }
- printf(" \"");
- decode(&insn, 3, 0);
- printf("\\n\"\n");
-
- /* loop for each operand. */
- n = 0;
- for (i = 0 ; i < op_num; i++)
- {
- opd = &tilegx_operands[opc->operands[2 + p][i]];
-
- if (opd->type == TILEGX_OP_TYPE_REGISTER) {
- /* A register operand */
- printf(" \"move %c%d, r%d\\n\"\n", '%', n, (int)decoded.operand_values[i]);
- n++;
- }
- }
-
- printf(" ");
- if (n)
- printf(":");
- for (i = 0; i < n; i++)
- {
- printf("\"=r\"(a[%d])", i);
- if (i != n - 1)
- printf(",");
- }
-
- printf(");\n");
- }
-
- for (i = 0; i < n; i++)
- {
- printf(" printf(\"%c016lx\\n\", a[%d]);\n", '%', i);
- }
- printf(" return 0;\n");
- printf("}\n");
- return insn;
-}
-
-static int display_insn ( struct tilegx_decoded_instruction
- decoded[1] )
-{
- int i;
- for (i = 0;
- decoded[i].opcode && (i < 1);
- i++) {
- int n;
- printf("%s ", decoded[i].opcode->name);
-
- for (n = 0; n < decoded[i].opcode->num_operands; n++) {
- const struct tilegx_operand *op = decoded[i].operands[n];
-
- if (op->type == TILEGX_OP_TYPE_REGISTER)
- printf("r%d", (int) decoded[i].operand_values[n]);
- else
- printf("%ld", (unsigned long)decoded[i].operand_values[n]);
-
- if (n != (decoded[i].opcode->num_operands - 1))
- printf(", ");
- }
- printf(" ");
- }
- return i;
-}
-
-int decode( tilegx_bundle_bits *p, int count, ULong pc )
-{
- struct tilegx_decoded_instruction
- decode[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE];
-
- if (pc) {
- printf("%012llx %016llx ", pc, (ULong)p[0]);
- pc += 8;
- }
- parse_insn_tilegx(p[0], 0, decode);
-
- int k;
-
- printf("{ ");
-
- for(k = 0; decode[k].opcode && (k <TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE);
- k++) {
-
- display_insn(&decode[k]);
- if (--count > 0)
- printf("; ");
- }
-
- printf(" }");
-
- return count;
-}
diff --git a/none/tests/tilegx/gen_test.sh b/none/tests/tilegx/gen_test.sh
deleted file mode 100755
index 1b6537e..0000000
--- a/none/tests/tilegx/gen_test.sh
+++ /dev/null
@@ -1,600 +0,0 @@
-#!/bin/bash
-
-FILES=( "5 1 insn_test_move_X0.c"
- "5 2 insn_test_move_X1.c"
- "5 4 insn_test_move_Y0.c"
- "5 8 insn_test_move_Y1.c"
- "6 1 insn_test_movei_X0.c"
- "6 2 insn_test_movei_X1.c"
- "6 4 insn_test_movei_Y0.c"
- "6 8 insn_test_movei_Y1.c"
- "7 1 insn_test_moveli_X0.c"
- "7 2 insn_test_moveli_X1.c"
- "8 2 insn_test_prefetch_X1.c"
- "8 16 insn_test_prefetch_Y2.c"
- "9 2 insn_test_prefetch_add_l1_X1.c"
- "10 2 insn_test_prefetch_add_l1_fault_X1.c"
- "11 2 insn_test_prefetch_add_l2_X1.c"
- "12 2 insn_test_prefetch_add_l2_fault_X1.c"
- "13 2 insn_test_prefetch_add_l3_X1.c"
- "14 2 insn_test_prefetch_add_l3_fault_X1.c"
- "15 2 insn_test_prefetch_l1_X1.c"
- "15 16 insn_test_prefetch_l1_Y2.c"
- "16 2 insn_test_prefetch_l1_fault_X1.c"
- "16 16 insn_test_prefetch_l1_fault_Y2.c"
- "17 2 insn_test_prefetch_l2_X1.c"
- "17 16 insn_test_prefetch_l2_Y2.c"
- "18 2 insn_test_prefetch_l2_fault_X1.c"
- "18 16 insn_test_prefetch_l2_fault_Y2.c"
- "19 2 insn_test_prefetch_l3_X1.c"
- "19 16 insn_test_prefetch_l3_Y2.c"
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- "20 16 insn_test_prefetch_l3_fault_Y2.c"
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- "29 1 insn_test_and_X0.c"
- "29 2 insn_test_and_X1.c"
- "29 4 insn_test_and_Y0.c"
- "29 8 insn_test_and_Y1.c"
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- "197 1 insn_test_shlx_X0.c"
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- "246 2 insn_test_v1cmpne_X1.c"
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- "248 1 insn_test_v1ddotpua_X0.c"
- "249 1 insn_test_v1ddotpus_X0.c"
- "250 1 insn_test_v1ddotpusa_X0.c"
- "251 1 insn_test_v1dotp_X0.c"
- "252 1 insn_test_v1dotpa_X0.c"
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- "254 1 insn_test_v1dotpua_X0.c"
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- "256 1 insn_test_v1dotpusa_X0.c"
- "257 1 insn_test_v1int_h_X0.c"
- "257 2 insn_test_v1int_h_X1.c"
- "258 1 insn_test_v1int_l_X0.c"
- "258 2 insn_test_v1int_l_X1.c"
- "259 1 insn_test_v1maxu_X0.c"
- "259 2 insn_test_v1maxu_X1.c"
- "260 1 insn_test_v1maxui_X0.c"
- "260 2 insn_test_v1maxui_X1.c"
- "261 1 insn_test_v1minu_X0.c"
- "261 2 insn_test_v1minu_X1.c"
- "262 1 insn_test_v1minui_X0.c"
- "262 2 insn_test_v1minui_X1.c"
- "263 1 insn_test_v1mnz_X0.c"
- "263 2 insn_test_v1mnz_X1.c"
- "264 1 insn_test_v1multu_X0.c"
- "265 1 insn_test_v1mulu_X0.c"
- "266 1 insn_test_v1mulus_X0.c"
- "267 1 insn_test_v1mz_X0.c"
- "267 2 insn_test_v1mz_X1.c"
- "268 1 insn_test_v1sadau_X0.c"
- "269 1 insn_test_v1sadu_X0.c"
- "270 1 insn_test_v1shl_X0.c"
- "270 2 insn_test_v1shl_X1.c"
- "271 1 insn_test_v1shli_X0.c"
- "271 2 insn_test_v1shli_X1.c"
- "272 1 insn_test_v1shrs_X0.c"
- "272 2 insn_test_v1shrs_X1.c"
- "273 1 insn_test_v1shrsi_X0.c"
- "273 2 insn_test_v1shrsi_X1.c"
- "274 1 insn_test_v1shru_X0.c"
- "274 2 insn_test_v1shru_X1.c"
- "275 1 insn_test_v1shrui_X0.c"
- "275 2 insn_test_v1shrui_X1.c"
- "276 1 insn_test_v1sub_X0.c"
- "276 2 insn_test_v1sub_X1.c"
- "277 1 insn_test_v1subuc_X0.c"
- "277 2 insn_test_v1subuc_X1.c"
- "278 1 insn_test_v2add_X0.c"
- "278 2 insn_test_v2add_X1.c"
- "279 1 insn_test_v2addi_X0.c"
- "279 2 insn_test_v2addi_X1.c"
- "280 1 insn_test_v2addsc_X0.c"
- "280 2 insn_test_v2addsc_X1.c"
- "281 1 insn_test_v2adiffs_X0.c"
- "282 1 insn_test_v2avgs_X0.c"
- "283 1 insn_test_v2cmpeq_X0.c"
- "283 2 insn_test_v2cmpeq_X1.c"
- "284 1 insn_test_v2cmpeqi_X0.c"
- "284 2 insn_test_v2cmpeqi_X1.c"
- "285 1 insn_test_v2cmples_X0.c"
- "285 2 insn_test_v2cmples_X1.c"
- "286 1 insn_test_v2cmpleu_X0.c"
- "286 2 insn_test_v2cmpleu_X1.c"
- "287 1 insn_test_v2cmplts_X0.c"
- "287 2 insn_test_v2cmplts_X1.c"
- "288 1 insn_test_v2cmpltsi_X0.c"
- "288 2 insn_test_v2cmpltsi_X1.c"
- "289 1 insn_test_v2cmpltu_X0.c"
- "289 2 insn_test_v2cmpltu_X1.c"
- "290 1 insn_test_v2cmpltui_X0.c"
- "290 2 insn_test_v2cmpltui_X1.c"
- "291 1 insn_test_v2cmpne_X0.c"
- "291 2 insn_test_v2cmpne_X1.c"
- "292 1 insn_test_v2dotp_X0.c"
- "293 1 insn_test_v2dotpa_X0.c"
- "294 1 insn_test_v2int_h_X0.c"
- "294 2 insn_test_v2int_h_X1.c"
- "295 1 insn_test_v2int_l_X0.c"
- "295 2 insn_test_v2int_l_X1.c"
- "296 1 insn_test_v2maxs_X0.c"
- "296 2 insn_test_v2maxs_X1.c"
- "297 1 insn_test_v2maxsi_X0.c"
- "297 2 insn_test_v2maxsi_X1.c"
- "298 1 insn_test_v2mins_X0.c"
- "298 2 insn_test_v2mins_X1.c"
- "299 1 insn_test_v2minsi_X0.c"
- "299 2 insn_test_v2minsi_X1.c"
- "300 1 insn_test_v2mnz_X0.c"
- "300 2 insn_test_v2mnz_X1.c"
- "301 1 insn_test_v2mulfsc_X0.c"
- "302 1 insn_test_v2muls_X0.c"
- "303 1 insn_test_v2mults_X0.c"
- "304 1 insn_test_v2mz_X0.c"
- "304 2 insn_test_v2mz_X1.c"
- "305 1 insn_test_v2packh_X0.c"
- "305 2 insn_test_v2packh_X1.c"
- "306 1 insn_test_v2packl_X0.c"
- "306 2 insn_test_v2packl_X1.c"
- "307 1 insn_test_v2packuc_X0.c"
- "307 2 insn_test_v2packuc_X1.c"
- "308 1 insn_test_v2sadas_X0.c"
- "309 1 insn_test_v2sadau_X0.c"
- "310 1 insn_test_v2sads_X0.c"
- "311 1 insn_test_v2sadu_X0.c"
- "312 1 insn_test_v2shl_X0.c"
- "312 2 insn_test_v2shl_X1.c"
- "313 1 insn_test_v2shli_X0.c"
- "313 2 insn_test_v2shli_X1.c"
- "314 1 insn_test_v2shlsc_X0.c"
- "314 2 insn_test_v2shlsc_X1.c"
- "315 1 insn_test_v2shrs_X0.c"
- "315 2 insn_test_v2shrs_X1.c"
- "316 1 insn_test_v2shrsi_X0.c"
- "316 2 insn_test_v2shrsi_X1.c"
- "317 1 insn_test_v2shru_X0.c"
- "317 2 insn_test_v2shru_X1.c"
- "318 1 insn_test_v2shrui_X0.c"
- "318 2 insn_test_v2shrui_X1.c"
- "319 1 insn_test_v2sub_X0.c"
- "319 2 insn_test_v2sub_X1.c"
- "320 1 insn_test_v2subsc_X0.c"
- "320 2 insn_test_v2subsc_X1.c"
- "321 1 insn_test_v4add_X0.c"
- "321 2 insn_test_v4add_X1.c"
- "322 1 insn_test_v4addsc_X0.c"
- "322 2 insn_test_v4addsc_X1.c"
- "323 1 insn_test_v4int_h_X0.c"
- "323 2 insn_test_v4int_h_X1.c"
- "324 1 insn_test_v4int_l_X0.c"
- "324 2 insn_test_v4int_l_X1.c"
- "325 1 insn_test_v4packsc_X0.c"
- "325 2 insn_test_v4packsc_X1.c"
- "326 1 insn_test_v4shl_X0.c"
- "326 2 insn_test_v4shl_X1.c"
- "327 1 insn_test_v4shlsc_X0.c"
- "327 2 insn_test_v4shlsc_X1.c"
- "328 1 insn_test_v4shrs_X0.c"
- "328 2 insn_test_v4shrs_X1.c"
- "329 1 insn_test_v4shru_X0.c"
- "329 2 insn_test_v4shru_X1.c"
- "330 1 insn_test_v4sub_X0.c"
- "330 2 insn_test_v4sub_X1.c"
- "331 1 insn_test_v4subsc_X0.c"
- "331 2 insn_test_v4subsc_X1.c"
- "332 2 insn_test_wh64_X1.c"
- "333 1 insn_test_xor_X0.c"
- "333 2 insn_test_xor_X1.c"
- "333 4 insn_test_xor_Y0.c"
- "333 8 insn_test_xor_Y1.c"
- "334 1 insn_test_xori_X0.c"
- "334 2 insn_test_xori_X1.c"
-)
-
-if [ $# -gt 0 ]; then
-#fname = "$1"
-
-for f in "${FILES[@]}"
-do
- array=(${f// / })
- if [ ${array[2]} = $1 ]; then
- ./gen_insn_test ${array[0]} ${array[1]} > ${array[2]}
- exit 0
- fi
-done
-
-exit -1
-
-else
-
-for f in "${FILES[@]}"
-do
- echo $i $f
- array=(${f// / })
- ./gen_insn_test ${array[0]} ${array[1]} > ${array[2]}
-done
-
-fi
-
-
-
diff --git a/none/tests/tilegx/insn_test_add_X0.c b/none/tests/tilegx/insn_test_add_X0.c
deleted file mode 100644
index a460e2b..0000000
--- a/none/tests/tilegx/insn_test_add_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_add_X0.c
-//op=22
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xcbf6dda12670067, 0x15063831748c3911 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r35, -22068\n"
- "shl16insli r35, r35, -316\n"
- "shl16insli r35, r35, -2663\n"
- "shl16insli r35, r35, 29773\n"
- "moveli r25, 14446\n"
- "shl16insli r25, r25, 26605\n"
- "shl16insli r25, r25, 31496\n"
- "shl16insli r25, r25, -24631\n"
- "moveli r34, -21610\n"
- "shl16insli r34, r34, 7292\n"
- "shl16insli r34, r34, -8245\n"
- "shl16insli r34, r34, 30416\n"
- "{ add r35, r25, r34 ; fnop }\n"
- "move %0, r35\n"
- "move %1, r25\n"
- "move %2, r34\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_add_X1.c b/none/tests/tilegx/insn_test_add_X1.c
deleted file mode 100644
index 9f2e174..0000000
--- a/none/tests/tilegx/insn_test_add_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_add_X1.c
-//op=22
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xcbf6dda12670067, 0x15063831748c3911 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r35, -22068\n"
- "shl16insli r35, r35, -316\n"
- "shl16insli r35, r35, -2663\n"
- "shl16insli r35, r35, 29773\n"
- "moveli r25, 14446\n"
- "shl16insli r25, r25, 26605\n"
- "shl16insli r25, r25, 31496\n"
- "shl16insli r25, r25, -24631\n"
- "moveli r34, -21610\n"
- "shl16insli r34, r34, 7292\n"
- "shl16insli r34, r34, -8245\n"
- "shl16insli r34, r34, 30416\n"
- "{ fnop ; add r35, r25, r34 }\n"
- "move %0, r35\n"
- "move %1, r25\n"
- "move %2, r34\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_add_Y0.c b/none/tests/tilegx/insn_test_add_Y0.c
deleted file mode 100644
index cf6bca0..0000000
--- a/none/tests/tilegx/insn_test_add_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_add_Y0.c
-//op=22
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xcbf6dda12670067, 0x15063831748c3911 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r35, -22068\n"
- "shl16insli r35, r35, -316\n"
- "shl16insli r35, r35, -2663\n"
- "shl16insli r35, r35, 29773\n"
- "moveli r25, 14446\n"
- "shl16insli r25, r25, 26605\n"
- "shl16insli r25, r25, 31496\n"
- "shl16insli r25, r25, -24631\n"
- "moveli r34, -21610\n"
- "shl16insli r34, r34, 7292\n"
- "shl16insli r34, r34, -8245\n"
- "shl16insli r34, r34, 30416\n"
- "{ add r35, r25, r34 ; fnop ; ld r63, r54 }\n"
- "move %0, r35\n"
- "move %1, r25\n"
- "move %2, r34\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_add_Y1.c b/none/tests/tilegx/insn_test_add_Y1.c
deleted file mode 100644
index 071c9b5..0000000
--- a/none/tests/tilegx/insn_test_add_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_add_Y1.c
-//op=22
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xcbf6dda12670067, 0x15063831748c3911 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r35, -22068\n"
- "shl16insli r35, r35, -316\n"
- "shl16insli r35, r35, -2663\n"
- "shl16insli r35, r35, 29773\n"
- "moveli r25, 14446\n"
- "shl16insli r25, r25, 26605\n"
- "shl16insli r25, r25, 31496\n"
- "shl16insli r25, r25, -24631\n"
- "moveli r34, -21610\n"
- "shl16insli r34, r34, 7292\n"
- "shl16insli r34, r34, -8245\n"
- "shl16insli r34, r34, 30416\n"
- "{ fnop ; add r35, r25, r34 ; ld r63, r54 }\n"
- "move %0, r35\n"
- "move %1, r25\n"
- "move %2, r34\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_addi_X0.c b/none/tests/tilegx/insn_test_addi_X0.c
deleted file mode 100644
index 7393bdb..0000000
--- a/none/tests/tilegx/insn_test_addi_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_addi_X0.c
-//op=23
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc50a9ede838fadbb, 0xc2d6db3411b6362 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r10, -29553\n"
- "shl16insli r10, r10, 1035\n"
- "shl16insli r10, r10, 5152\n"
- "shl16insli r10, r10, -10394\n"
- "moveli r3, 16496\n"
- "shl16insli r3, r3, 1901\n"
- "shl16insli r3, r3, -17744\n"
- "shl16insli r3, r3, 5578\n"
- "{ addi r10, r3, 13 ; fnop }\n"
- "move %0, r10\n"
- "move %1, r3\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_addi_X1.c b/none/tests/tilegx/insn_test_addi_X1.c
deleted file mode 100644
index b52a8fe..0000000
--- a/none/tests/tilegx/insn_test_addi_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_addi_X1.c
-//op=23
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc50a9ede838fadbb, 0xc2d6db3411b6362 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r10, -29553\n"
- "shl16insli r10, r10, 1035\n"
- "shl16insli r10, r10, 5152\n"
- "shl16insli r10, r10, -10394\n"
- "moveli r3, 16496\n"
- "shl16insli r3, r3, 1901\n"
- "shl16insli r3, r3, -17744\n"
- "shl16insli r3, r3, 5578\n"
- "{ fnop ; addi r10, r3, 13 }\n"
- "move %0, r10\n"
- "move %1, r3\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_addi_Y0.c b/none/tests/tilegx/insn_test_addi_Y0.c
deleted file mode 100644
index 0fbcb9b..0000000
--- a/none/tests/tilegx/insn_test_addi_Y0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_addi_Y0.c
-//op=23
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc50a9ede838fadbb, 0xc2d6db3411b6362 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r10, -29553\n"
- "shl16insli r10, r10, 1035\n"
- "shl16insli r10, r10, 5152\n"
- "shl16insli r10, r10, -10394\n"
- "moveli r3, 16496\n"
- "shl16insli r3, r3, 1901\n"
- "shl16insli r3, r3, -17744\n"
- "shl16insli r3, r3, 5578\n"
- "{ addi r10, r3, 13 ; fnop ; ld r63, r54 }\n"
- "move %0, r10\n"
- "move %1, r3\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_addi_Y1.c b/none/tests/tilegx/insn_test_addi_Y1.c
deleted file mode 100644
index 8cb9af8..0000000
--- a/none/tests/tilegx/insn_test_addi_Y1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_addi_Y1.c
-//op=23
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc50a9ede838fadbb, 0xc2d6db3411b6362 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r10, -29553\n"
- "shl16insli r10, r10, 1035\n"
- "shl16insli r10, r10, 5152\n"
- "shl16insli r10, r10, -10394\n"
- "moveli r3, 16496\n"
- "shl16insli r3, r3, 1901\n"
- "shl16insli r3, r3, -17744\n"
- "shl16insli r3, r3, 5578\n"
- "{ fnop ; addi r10, r3, 13 ; ld r63, r54 }\n"
- "move %0, r10\n"
- "move %1, r3\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_addli_X0.c b/none/tests/tilegx/insn_test_addli_X0.c
deleted file mode 100644
index 8521ddf..0000000
--- a/none/tests/tilegx/insn_test_addli_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_addli_X0.c
-//op=24
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xeebea8448496854d, 0x9fc8faed728cb8c8 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r7, -15865\n"
- "shl16insli r7, r7, -8928\n"
- "shl16insli r7, r7, 2151\n"
- "shl16insli r7, r7, -8089\n"
- "moveli r8, 18685\n"
- "shl16insli r8, r8, 5716\n"
- "shl16insli r8, r8, -22554\n"
- "shl16insli r8, r8, 27127\n"
- "{ addli r7, r8, 12693 ; fnop }\n"
- "move %0, r7\n"
- "move %1, r8\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_addli_X1.c b/none/tests/tilegx/insn_test_addli_X1.c
deleted file mode 100644
index b26007f..0000000
--- a/none/tests/tilegx/insn_test_addli_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_addli_X1.c
-//op=24
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xeebea8448496854d, 0x9fc8faed728cb8c8 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r7, -15865\n"
- "shl16insli r7, r7, -8928\n"
- "shl16insli r7, r7, 2151\n"
- "shl16insli r7, r7, -8089\n"
- "moveli r8, 18685\n"
- "shl16insli r8, r8, 5716\n"
- "shl16insli r8, r8, -22554\n"
- "shl16insli r8, r8, 27127\n"
- "{ fnop ; addli r7, r8, 12693 }\n"
- "move %0, r7\n"
- "move %1, r8\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_addx_X0.c b/none/tests/tilegx/insn_test_addx_X0.c
deleted file mode 100644
index 29a7480..0000000
--- a/none/tests/tilegx/insn_test_addx_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_addx_X0.c
-//op=25
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xa866c1efe28f7aab, 0x422260f8cf40ffbb };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r16, 16437\n"
- "shl16insli r16, r16, -17949\n"
- "shl16insli r16, r16, -5049\n"
- "shl16insli r16, r16, 16324\n"
- "moveli r19, 21012\n"
- "shl16insli r19, r19, -29133\n"
- "shl16insli r19, r19, -8710\n"
- "shl16insli r19, r19, -16472\n"
- "moveli r2, -10150\n"
- "shl16insli r2, r2, -32553\n"
- "shl16insli r2, r2, -18908\n"
- "shl16insli r2, r2, 23364\n"
- "{ addx r16, r19, r2 ; fnop }\n"
- "move %0, r16\n"
- "move %1, r19\n"
- "move %2, r2\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_addx_X1.c b/none/tests/tilegx/insn_test_addx_X1.c
deleted file mode 100644
index 776df63..0000000
--- a/none/tests/tilegx/insn_test_addx_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_addx_X1.c
-//op=25
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xa866c1efe28f7aab, 0x422260f8cf40ffbb };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r16, 16437\n"
- "shl16insli r16, r16, -17949\n"
- "shl16insli r16, r16, -5049\n"
- "shl16insli r16, r16, 16324\n"
- "moveli r19, 21012\n"
- "shl16insli r19, r19, -29133\n"
- "shl16insli r19, r19, -8710\n"
- "shl16insli r19, r19, -16472\n"
- "moveli r2, -10150\n"
- "shl16insli r2, r2, -32553\n"
- "shl16insli r2, r2, -18908\n"
- "shl16insli r2, r2, 23364\n"
- "{ fnop ; addx r16, r19, r2 }\n"
- "move %0, r16\n"
- "move %1, r19\n"
- "move %2, r2\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_addx_Y0.c b/none/tests/tilegx/insn_test_addx_Y0.c
deleted file mode 100644
index c2e11dc..0000000
--- a/none/tests/tilegx/insn_test_addx_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_addx_Y0.c
-//op=25
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xa866c1efe28f7aab, 0x422260f8cf40ffbb };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r16, 16437\n"
- "shl16insli r16, r16, -17949\n"
- "shl16insli r16, r16, -5049\n"
- "shl16insli r16, r16, 16324\n"
- "moveli r19, 21012\n"
- "shl16insli r19, r19, -29133\n"
- "shl16insli r19, r19, -8710\n"
- "shl16insli r19, r19, -16472\n"
- "moveli r2, -10150\n"
- "shl16insli r2, r2, -32553\n"
- "shl16insli r2, r2, -18908\n"
- "shl16insli r2, r2, 23364\n"
- "{ addx r16, r19, r2 ; fnop ; ld r63, r54 }\n"
- "move %0, r16\n"
- "move %1, r19\n"
- "move %2, r2\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_addx_Y1.c b/none/tests/tilegx/insn_test_addx_Y1.c
deleted file mode 100644
index cc2b370..0000000
--- a/none/tests/tilegx/insn_test_addx_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_addx_Y1.c
-//op=25
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xa866c1efe28f7aab, 0x422260f8cf40ffbb };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r16, 16437\n"
- "shl16insli r16, r16, -17949\n"
- "shl16insli r16, r16, -5049\n"
- "shl16insli r16, r16, 16324\n"
- "moveli r19, 21012\n"
- "shl16insli r19, r19, -29133\n"
- "shl16insli r19, r19, -8710\n"
- "shl16insli r19, r19, -16472\n"
- "moveli r2, -10150\n"
- "shl16insli r2, r2, -32553\n"
- "shl16insli r2, r2, -18908\n"
- "shl16insli r2, r2, 23364\n"
- "{ fnop ; addx r16, r19, r2 ; ld r63, r54 }\n"
- "move %0, r16\n"
- "move %1, r19\n"
- "move %2, r2\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_addxi_X0.c b/none/tests/tilegx/insn_test_addxi_X0.c
deleted file mode 100644
index 3033632..0000000
--- a/none/tests/tilegx/insn_test_addxi_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_addxi_X0.c
-//op=26
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x82cd9e74ccb2b602, 0xb405f09d3ac1f78c };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r16, -28042\n"
- "shl16insli r16, r16, 29759\n"
- "shl16insli r16, r16, 8449\n"
- "shl16insli r16, r16, -25778\n"
- "moveli r19, 15873\n"
- "shl16insli r19, r19, -26278\n"
- "shl16insli r19, r19, -22224\n"
- "shl16insli r19, r19, 11419\n"
- "{ addxi r16, r19, -1 ; fnop }\n"
- "move %0, r16\n"
- "move %1, r19\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_addxi_X1.c b/none/tests/tilegx/insn_test_addxi_X1.c
deleted file mode 100644
index 90ebe4d..0000000
--- a/none/tests/tilegx/insn_test_addxi_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_addxi_X1.c
-//op=26
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x82cd9e74ccb2b602, 0xb405f09d3ac1f78c };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r16, -28042\n"
- "shl16insli r16, r16, 29759\n"
- "shl16insli r16, r16, 8449\n"
- "shl16insli r16, r16, -25778\n"
- "moveli r19, 15873\n"
- "shl16insli r19, r19, -26278\n"
- "shl16insli r19, r19, -22224\n"
- "shl16insli r19, r19, 11419\n"
- "{ fnop ; addxi r16, r19, -1 }\n"
- "move %0, r16\n"
- "move %1, r19\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_addxi_Y0.c b/none/tests/tilegx/insn_test_addxi_Y0.c
deleted file mode 100644
index 83a7a11..0000000
--- a/none/tests/tilegx/insn_test_addxi_Y0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_addxi_Y0.c
-//op=26
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x82cd9e74ccb2b602, 0xb405f09d3ac1f78c };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r16, -28042\n"
- "shl16insli r16, r16, 29759\n"
- "shl16insli r16, r16, 8449\n"
- "shl16insli r16, r16, -25778\n"
- "moveli r19, 15873\n"
- "shl16insli r19, r19, -26278\n"
- "shl16insli r19, r19, -22224\n"
- "shl16insli r19, r19, 11419\n"
- "{ addxi r16, r19, -1 ; fnop ; ld r63, r54 }\n"
- "move %0, r16\n"
- "move %1, r19\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_addxi_Y1.c b/none/tests/tilegx/insn_test_addxi_Y1.c
deleted file mode 100644
index df15bdc..0000000
--- a/none/tests/tilegx/insn_test_addxi_Y1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_addxi_Y1.c
-//op=26
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x82cd9e74ccb2b602, 0xb405f09d3ac1f78c };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r16, -28042\n"
- "shl16insli r16, r16, 29759\n"
- "shl16insli r16, r16, 8449\n"
- "shl16insli r16, r16, -25778\n"
- "moveli r19, 15873\n"
- "shl16insli r19, r19, -26278\n"
- "shl16insli r19, r19, -22224\n"
- "shl16insli r19, r19, 11419\n"
- "{ fnop ; addxi r16, r19, -1 ; ld r63, r54 }\n"
- "move %0, r16\n"
- "move %1, r19\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_addxli_X0.c b/none/tests/tilegx/insn_test_addxli_X0.c
deleted file mode 100644
index 21e230b..0000000
--- a/none/tests/tilegx/insn_test_addxli_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_addxli_X0.c
-//op=27
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd5875ac284be5010, 0xfeec3c7ab59e554 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r45, -16303\n"
- "shl16insli r45, r45, -6468\n"
- "shl16insli r45, r45, -24288\n"
- "shl16insli r45, r45, 22752\n"
- "moveli r45, 5983\n"
- "shl16insli r45, r45, 27427\n"
- "shl16insli r45, r45, 451\n"
- "shl16insli r45, r45, -26979\n"
- "{ addxli r45, r45, -23808 ; fnop }\n"
- "move %0, r45\n"
- "move %1, r45\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_addxli_X1.c b/none/tests/tilegx/insn_test_addxli_X1.c
deleted file mode 100644
index 2829261..0000000
--- a/none/tests/tilegx/insn_test_addxli_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_addxli_X1.c
-//op=27
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd5875ac284be5010, 0xfeec3c7ab59e554 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r45, -16303\n"
- "shl16insli r45, r45, -6468\n"
- "shl16insli r45, r45, -24288\n"
- "shl16insli r45, r45, 22752\n"
- "moveli r45, 5983\n"
- "shl16insli r45, r45, 27427\n"
- "shl16insli r45, r45, 451\n"
- "shl16insli r45, r45, -26979\n"
- "{ fnop ; addxli r45, r45, -23808 }\n"
- "move %0, r45\n"
- "move %1, r45\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_addxsc_X0.c b/none/tests/tilegx/insn_test_addxsc_X0.c
deleted file mode 100644
index 12bfca1..0000000
--- a/none/tests/tilegx/insn_test_addxsc_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_addxsc_X0.c
-//op=28
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd9528fcf37ad6ac6, 0xe41f03815d99ac96 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r16, 27624\n"
- "shl16insli r16, r16, 3804\n"
- "shl16insli r16, r16, -16569\n"
- "shl16insli r16, r16, -19918\n"
- "moveli r12, -8205\n"
- "shl16insli r12, r12, 24120\n"
- "shl16insli r12, r12, 20070\n"
- "shl16insli r12, r12, 12693\n"
- "moveli r5, 11830\n"
- "shl16insli r5, r5, -1700\n"
- "shl16insli r5, r5, 8629\n"
- "shl16insli r5, r5, -24868\n"
- "{ addxsc r16, r12, r5 ; fnop }\n"
- "move %0, r16\n"
- "move %1, r12\n"
- "move %2, r5\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_addxsc_X1.c b/none/tests/tilegx/insn_test_addxsc_X1.c
deleted file mode 100644
index 2d1fae4..0000000
--- a/none/tests/tilegx/insn_test_addxsc_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_addxsc_X1.c
-//op=28
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd9528fcf37ad6ac6, 0xe41f03815d99ac96 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r16, 27624\n"
- "shl16insli r16, r16, 3804\n"
- "shl16insli r16, r16, -16569\n"
- "shl16insli r16, r16, -19918\n"
- "moveli r12, -8205\n"
- "shl16insli r12, r12, 24120\n"
- "shl16insli r12, r12, 20070\n"
- "shl16insli r12, r12, 12693\n"
- "moveli r5, 11830\n"
- "shl16insli r5, r5, -1700\n"
- "shl16insli r5, r5, 8629\n"
- "shl16insli r5, r5, -24868\n"
- "{ fnop ; addxsc r16, r12, r5 }\n"
- "move %0, r16\n"
- "move %1, r12\n"
- "move %2, r5\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_and_X0.c b/none/tests/tilegx/insn_test_and_X0.c
deleted file mode 100644
index d9ac40f..0000000
--- a/none/tests/tilegx/insn_test_and_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_and_X0.c
-//op=29
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x6fd6d80e8b18c9bb, 0xe18dcaef23b64e7 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r38, -25962\n"
- "shl16insli r38, r38, -29618\n"
- "shl16insli r38, r38, 9810\n"
- "shl16insli r38, r38, -7855\n"
- "moveli r16, -14420\n"
- "shl16insli r16, r16, 14085\n"
- "shl16insli r16, r16, 14918\n"
- "shl16insli r16, r16, 4353\n"
- "moveli r13, -12524\n"
- "shl16insli r13, r13, -16020\n"
- "shl16insli r13, r13, -28698\n"
- "shl16insli r13, r13, -10230\n"
- "{ and r38, r16, r13 ; fnop }\n"
- "move %0, r38\n"
- "move %1, r16\n"
- "move %2, r13\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_and_X1.c b/none/tests/tilegx/insn_test_and_X1.c
deleted file mode 100644
index c15dfc1..0000000
--- a/none/tests/tilegx/insn_test_and_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_and_X1.c
-//op=29
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x6fd6d80e8b18c9bb, 0xe18dcaef23b64e7 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r38, -25962\n"
- "shl16insli r38, r38, -29618\n"
- "shl16insli r38, r38, 9810\n"
- "shl16insli r38, r38, -7855\n"
- "moveli r16, -14420\n"
- "shl16insli r16, r16, 14085\n"
- "shl16insli r16, r16, 14918\n"
- "shl16insli r16, r16, 4353\n"
- "moveli r13, -12524\n"
- "shl16insli r13, r13, -16020\n"
- "shl16insli r13, r13, -28698\n"
- "shl16insli r13, r13, -10230\n"
- "{ fnop ; and r38, r16, r13 }\n"
- "move %0, r38\n"
- "move %1, r16\n"
- "move %2, r13\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_and_Y0.c b/none/tests/tilegx/insn_test_and_Y0.c
deleted file mode 100644
index f5088a8..0000000
--- a/none/tests/tilegx/insn_test_and_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_and_Y0.c
-//op=29
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x6fd6d80e8b18c9bb, 0xe18dcaef23b64e7 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r38, -25962\n"
- "shl16insli r38, r38, -29618\n"
- "shl16insli r38, r38, 9810\n"
- "shl16insli r38, r38, -7855\n"
- "moveli r16, -14420\n"
- "shl16insli r16, r16, 14085\n"
- "shl16insli r16, r16, 14918\n"
- "shl16insli r16, r16, 4353\n"
- "moveli r13, -12524\n"
- "shl16insli r13, r13, -16020\n"
- "shl16insli r13, r13, -28698\n"
- "shl16insli r13, r13, -10230\n"
- "{ and r38, r16, r13 ; fnop ; ld r63, r54 }\n"
- "move %0, r38\n"
- "move %1, r16\n"
- "move %2, r13\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_and_Y1.c b/none/tests/tilegx/insn_test_and_Y1.c
deleted file mode 100644
index ad153bb..0000000
--- a/none/tests/tilegx/insn_test_and_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_and_Y1.c
-//op=29
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x6fd6d80e8b18c9bb, 0xe18dcaef23b64e7 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r38, -25962\n"
- "shl16insli r38, r38, -29618\n"
- "shl16insli r38, r38, 9810\n"
- "shl16insli r38, r38, -7855\n"
- "moveli r16, -14420\n"
- "shl16insli r16, r16, 14085\n"
- "shl16insli r16, r16, 14918\n"
- "shl16insli r16, r16, 4353\n"
- "moveli r13, -12524\n"
- "shl16insli r13, r13, -16020\n"
- "shl16insli r13, r13, -28698\n"
- "shl16insli r13, r13, -10230\n"
- "{ fnop ; and r38, r16, r13 ; ld r63, r54 }\n"
- "move %0, r38\n"
- "move %1, r16\n"
- "move %2, r13\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_andi_X0.c b/none/tests/tilegx/insn_test_andi_X0.c
deleted file mode 100644
index a2fdff0..0000000
--- a/none/tests/tilegx/insn_test_andi_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_andi_X0.c
-//op=30
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd5c03dafaeab4e7e, 0xbca200a47bf08fef };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r46, -22782\n"
- "shl16insli r46, r46, -24188\n"
- "shl16insli r46, r46, -5494\n"
- "shl16insli r46, r46, 12791\n"
- "moveli r3, -24353\n"
- "shl16insli r3, r3, 7605\n"
- "shl16insli r3, r3, -19417\n"
- "shl16insli r3, r3, 15971\n"
- "{ andi r46, r3, 96 ; fnop }\n"
- "move %0, r46\n"
- "move %1, r3\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_andi_X1.c b/none/tests/tilegx/insn_test_andi_X1.c
deleted file mode 100644
index 0248411..0000000
--- a/none/tests/tilegx/insn_test_andi_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_andi_X1.c
-//op=30
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd5c03dafaeab4e7e, 0xbca200a47bf08fef };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r46, -22782\n"
- "shl16insli r46, r46, -24188\n"
- "shl16insli r46, r46, -5494\n"
- "shl16insli r46, r46, 12791\n"
- "moveli r3, -24353\n"
- "shl16insli r3, r3, 7605\n"
- "shl16insli r3, r3, -19417\n"
- "shl16insli r3, r3, 15971\n"
- "{ fnop ; andi r46, r3, 96 }\n"
- "move %0, r46\n"
- "move %1, r3\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_andi_Y0.c b/none/tests/tilegx/insn_test_andi_Y0.c
deleted file mode 100644
index 2e1dc50..0000000
--- a/none/tests/tilegx/insn_test_andi_Y0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_andi_Y0.c
-//op=30
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd5c03dafaeab4e7e, 0xbca200a47bf08fef };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r46, -22782\n"
- "shl16insli r46, r46, -24188\n"
- "shl16insli r46, r46, -5494\n"
- "shl16insli r46, r46, 12791\n"
- "moveli r3, -24353\n"
- "shl16insli r3, r3, 7605\n"
- "shl16insli r3, r3, -19417\n"
- "shl16insli r3, r3, 15971\n"
- "{ andi r46, r3, 96 ; fnop ; ld r63, r54 }\n"
- "move %0, r46\n"
- "move %1, r3\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_andi_Y1.c b/none/tests/tilegx/insn_test_andi_Y1.c
deleted file mode 100644
index 180fdac..0000000
--- a/none/tests/tilegx/insn_test_andi_Y1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_andi_Y1.c
-//op=30
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd5c03dafaeab4e7e, 0xbca200a47bf08fef };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r46, -22782\n"
- "shl16insli r46, r46, -24188\n"
- "shl16insli r46, r46, -5494\n"
- "shl16insli r46, r46, 12791\n"
- "moveli r3, -24353\n"
- "shl16insli r3, r3, 7605\n"
- "shl16insli r3, r3, -19417\n"
- "shl16insli r3, r3, 15971\n"
- "{ fnop ; andi r46, r3, 96 ; ld r63, r54 }\n"
- "move %0, r46\n"
- "move %1, r3\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_beqz_X1.c b/none/tests/tilegx/insn_test_beqz_X1.c
deleted file mode 100644
index 0226c39..0000000
--- a/none/tests/tilegx/insn_test_beqz_X1.c
+++ /dev/null
@@ -1,26 +0,0 @@
-//file: _insn_test_beqz_X1.c
-//op=31
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xa3f9a29247d48ea1, 0xb0a509adc464a67c };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "movei r0, 0\n"
- "beqz r0, %0\n"
- "jal %1\n"
- :: "i"(func_exit), "i"(func_call));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_beqzt_X1.c b/none/tests/tilegx/insn_test_beqzt_X1.c
deleted file mode 100644
index 4321ab8..0000000
--- a/none/tests/tilegx/insn_test_beqzt_X1.c
+++ /dev/null
@@ -1,26 +0,0 @@
-//file: _insn_test_beqzt_X1.c
-//op=32
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x4eb70a2cb8e0ad00, 0xae0d7beb6b9186fd };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "movei r25, 0\n"
- "beqzt r25, %0\n"
- "jal %1\n"
- :: "i"(func_exit), "i"(func_call));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_bfexts_X0.c b/none/tests/tilegx/insn_test_bfexts_X0.c
deleted file mode 100644
index 2cb8ad5..0000000
--- a/none/tests/tilegx/insn_test_bfexts_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_bfexts_X0.c
-//op=33
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x159952beef1e2d8e, 0x344fa86966757d1d };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r29, 14446\n"
- "shl16insli r29, r29, 26605\n"
- "shl16insli r29, r29, 31496\n"
- "shl16insli r29, r29, -24631\n"
- "moveli r9, -15179\n"
- "shl16insli r9, r9, 29659\n"
- "shl16insli r9, r9, 32207\n"
- "shl16insli r9, r9, 7899\n"
- "{ bfexts r29, r9, 11, 9 ; fnop }\n"
- "move %0, r29\n"
- "move %1, r9\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_bfextu_X0.c b/none/tests/tilegx/insn_test_bfextu_X0.c
deleted file mode 100644
index 7baca72..0000000
--- a/none/tests/tilegx/insn_test_bfextu_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_bfextu_X0.c
-//op=34
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x7eda32ada2f5060, 0xbcd5fb19de288be };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r15, -32243\n"
- "shl16insli r15, r15, 5581\n"
- "shl16insli r15, r15, 25121\n"
- "shl16insli r15, r15, 18660\n"
- "moveli r32, -2571\n"
- "shl16insli r32, r32, 10073\n"
- "shl16insli r32, r32, -8744\n"
- "shl16insli r32, r32, 32440\n"
- "{ bfextu r15, r32, 13, 52 ; fnop }\n"
- "move %0, r15\n"
- "move %1, r32\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_bfins_X0.c b/none/tests/tilegx/insn_test_bfins_X0.c
deleted file mode 100644
index af34f5a..0000000
--- a/none/tests/tilegx/insn_test_bfins_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_bfins_X0.c
-//op=35
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x6873aadf3e763127, 0x74d4eb98b256c26b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r49, 16197\n"
- "shl16insli r49, r49, -9240\n"
- "shl16insli r49, r49, -11331\n"
- "shl16insli r49, r49, -8418\n"
- "moveli r2, 17433\n"
- "shl16insli r2, r2, 14709\n"
- "shl16insli r2, r2, 26320\n"
- "shl16insli r2, r2, -3232\n"
- "{ bfins r49, r2, 21, 63 ; fnop }\n"
- "move %0, r49\n"
- "move %1, r2\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_bgez_X1.c b/none/tests/tilegx/insn_test_bgez_X1.c
deleted file mode 100644
index b46646d..0000000
--- a/none/tests/tilegx/insn_test_bgez_X1.c
+++ /dev/null
@@ -1,26 +0,0 @@
-//file: _insn_test_bgez_X1.c
-//op=36
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x3c14fa8c76bb7fe3, 0xc8b092c42b2e6d41 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "movei r23, 1\n"
- "bgez r23, %0\n"
- "jal %1\n"
- :: "i"(func_exit), "i"(func_call));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_bgezt_X1.c b/none/tests/tilegx/insn_test_bgezt_X1.c
deleted file mode 100644
index a61ef68..0000000
--- a/none/tests/tilegx/insn_test_bgezt_X1.c
+++ /dev/null
@@ -1,26 +0,0 @@
-//file: _insn_test_bgezt_X1.c
-//op=37
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x712fa2e35cfc84ba, 0xd82bef9b16da454e };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "movei r31, 1\n"
- "bgezt r31, %0\n"
- "jal %1\n"
- :: "i"(func_exit), "i"(func_call));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_bgtz_X1.c b/none/tests/tilegx/insn_test_bgtz_X1.c
deleted file mode 100644
index 2a1cd10..0000000
--- a/none/tests/tilegx/insn_test_bgtz_X1.c
+++ /dev/null
@@ -1,26 +0,0 @@
-//file: _insn_test_bgtz_X1.c
-//op=38
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x2220b583f77f7510, 0xb026dbf41e76db36 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "movei r46, 0\n"
- "bgtz r46, %0\n"
- "jal %1\n"
- :: "i"(func_exit), "i"(func_call));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_bgtzt_X1.c b/none/tests/tilegx/insn_test_bgtzt_X1.c
deleted file mode 100644
index 25683ea..0000000
--- a/none/tests/tilegx/insn_test_bgtzt_X1.c
+++ /dev/null
@@ -1,26 +0,0 @@
-//file: _insn_test_bgtzt_X1.c
-//op=39
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x7b1d4eb76be6dea6, 0x54e332914bce7010 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "movei r24, 1\n"
- "bgtzt r24, %0\n"
- "jal %1\n"
- :: "i"(func_exit), "i"(func_call));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_blbc_X1.c b/none/tests/tilegx/insn_test_blbc_X1.c
deleted file mode 100644
index fa7bd53..0000000
--- a/none/tests/tilegx/insn_test_blbc_X1.c
+++ /dev/null
@@ -1,26 +0,0 @@
-//file: _insn_test_blbc_X1.c
-//op=40
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x27ec0f0e74369816, 0x4aceb47ef3ca8ac3 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "movei r8, 0\n"
- "blbc r8, %0\n"
- "jal %1\n"
- :: "i"(func_exit), "i"(func_call));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_blbct_X1.c b/none/tests/tilegx/insn_test_blbct_X1.c
deleted file mode 100644
index df5de61..0000000
--- a/none/tests/tilegx/insn_test_blbct_X1.c
+++ /dev/null
@@ -1,26 +0,0 @@
-//file: _insn_test_blbct_X1.c
-//op=41
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xec57de1f0b8de6b3, 0xba5cc6450c5508b9 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "movei r39, 0\n"
- "blbct r39, %0\n"
- "jal %1\n"
- :: "i"(func_exit), "i"(func_call));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_blbs_X1.c b/none/tests/tilegx/insn_test_blbs_X1.c
deleted file mode 100644
index e6f0e90..0000000
--- a/none/tests/tilegx/insn_test_blbs_X1.c
+++ /dev/null
@@ -1,26 +0,0 @@
-//file: _insn_test_blbs_X1.c
-//op=42
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xce5c4dd59315697c, 0x420f71d29a23b3eb };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "movei r42, 1\n"
- "blbs r42, %0\n"
- "jal %1\n"
- :: "i"(func_exit), "i"(func_call));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_blbst_X1.c b/none/tests/tilegx/insn_test_blbst_X1.c
deleted file mode 100644
index 49edd77..0000000
--- a/none/tests/tilegx/insn_test_blbst_X1.c
+++ /dev/null
@@ -1,26 +0,0 @@
-//file: _insn_test_blbst_X1.c
-//op=43
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc2c31988eb4ca702, 0x400324c1f2522cf8 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "movei r33, 0\n"
- "blbst r33, %0\n"
- "jal %1\n"
- :: "i"(func_exit), "i"(func_call));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_blez_X1.c b/none/tests/tilegx/insn_test_blez_X1.c
deleted file mode 100644
index 2d23f40..0000000
--- a/none/tests/tilegx/insn_test_blez_X1.c
+++ /dev/null
@@ -1,26 +0,0 @@
-//file: _insn_test_blez_X1.c
-//op=44
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xa9ccfec4f599744d, 0xcbf6dda12670067 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "movei r28, 0\n"
- "blez r28, %0\n"
- "jal %1\n"
- :: "i"(func_exit), "i"(func_call));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_blezt_X1.c b/none/tests/tilegx/insn_test_blezt_X1.c
deleted file mode 100644
index 6e715da..0000000
--- a/none/tests/tilegx/insn_test_blezt_X1.c
+++ /dev/null
@@ -1,26 +0,0 @@
-//file: _insn_test_blezt_X1.c
-//op=45
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x22577cfa5789437f, 0x480f8d654b2eb8b3 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "movei r45, 1\n"
- "blezt r45, %0\n"
- "jal %1\n"
- :: "i"(func_exit), "i"(func_call));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_bltz_X1.c b/none/tests/tilegx/insn_test_bltz_X1.c
deleted file mode 100644
index 3106baf..0000000
--- a/none/tests/tilegx/insn_test_bltz_X1.c
+++ /dev/null
@@ -1,26 +0,0 @@
-//file: _insn_test_bltz_X1.c
-//op=46
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x8c8f040b1420d766, 0xc50a9ede838fadbb };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "movei r10, 0\n"
- "bltz r10, %0\n"
- "jal %1\n"
- :: "i"(func_exit), "i"(func_call));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_bltzt_X1.c b/none/tests/tilegx/insn_test_bltzt_X1.c
deleted file mode 100644
index a98b69b..0000000
--- a/none/tests/tilegx/insn_test_bltzt_X1.c
+++ /dev/null
@@ -1,26 +0,0 @@
-//file: _insn_test_bltzt_X1.c
-//op=47
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xfb39d803fce5e022, 0xa6f1d43f68e5d60e };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "movei r31, 0\n"
- "bltzt r31, %0\n"
- "jal %1\n"
- :: "i"(func_exit), "i"(func_call));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_bnez_X1.c b/none/tests/tilegx/insn_test_bnez_X1.c
deleted file mode 100644
index f24d670..0000000
--- a/none/tests/tilegx/insn_test_bnez_X1.c
+++ /dev/null
@@ -1,26 +0,0 @@
-//file: _insn_test_bnez_X1.c
-//op=48
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc207dd200867e067, 0xeebea8448496854d };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "movei r7, 1\n"
- "bnez r7, %0\n"
- "jal %1\n"
- :: "i"(func_exit), "i"(func_call));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_bnezt_X1.c b/none/tests/tilegx/insn_test_bnezt_X1.c
deleted file mode 100644
index e24473f..0000000
--- a/none/tests/tilegx/insn_test_bnezt_X1.c
+++ /dev/null
@@ -1,26 +0,0 @@
-//file: _insn_test_bnezt_X1.c
-//op=49
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xbe6bcf910f7bc3c9, 0xcfc849bbd49048f6 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "movei r34, 0\n"
- "bnezt r34, %0\n"
- "jal %1\n"
- :: "i"(func_exit), "i"(func_call));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_clz_X0.c b/none/tests/tilegx/insn_test_clz_X0.c
deleted file mode 100644
index 0a71047..0000000
--- a/none/tests/tilegx/insn_test_clz_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_clz_X0.c
-//op=50
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x4035b9e3ec473fc4, 0xa866c1efe28f7aab };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r3, -10150\n"
- "shl16insli r3, r3, -32553\n"
- "shl16insli r3, r3, -18908\n"
- "shl16insli r3, r3, 23364\n"
- "moveli r33, -27243\n"
- "shl16insli r33, r33, 13585\n"
- "shl16insli r33, r33, -1554\n"
- "shl16insli r33, r33, 17682\n"
- "{ clz r3, r33 ; fnop }\n"
- "move %0, r3\n"
- "move %1, r33\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_clz_Y0.c b/none/tests/tilegx/insn_test_clz_Y0.c
deleted file mode 100644
index 08ddb97..0000000
--- a/none/tests/tilegx/insn_test_clz_Y0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_clz_Y0.c
-//op=50
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x4035b9e3ec473fc4, 0xa866c1efe28f7aab };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r3, -10150\n"
- "shl16insli r3, r3, -32553\n"
- "shl16insli r3, r3, -18908\n"
- "shl16insli r3, r3, 23364\n"
- "moveli r33, -27243\n"
- "shl16insli r33, r33, 13585\n"
- "shl16insli r33, r33, -1554\n"
- "shl16insli r33, r33, 17682\n"
- "{ clz r3, r33 ; fnop ; ld r63, r54 }\n"
- "move %0, r3\n"
- "move %1, r33\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmoveqz_X0.c b/none/tests/tilegx/insn_test_cmoveqz_X0.c
deleted file mode 100644
index dcf7904..0000000
--- a/none/tests/tilegx/insn_test_cmoveqz_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmoveqz_X0.c
-//op=51
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x8e9efd621a0271c0, 0xe6fd0819cb489949 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r50, -2571\n"
- "shl16insli r50, r50, 10073\n"
- "shl16insli r50, r50, -8744\n"
- "shl16insli r50, r50, 32440\n"
- "moveli r28, -14135\n"
- "shl16insli r28, r28, -9714\n"
- "shl16insli r28, r28, -28553\n"
- "shl16insli r28, r28, 1624\n"
- "moveli r42, -6121\n"
- "shl16insli r42, r42, -23936\n"
- "shl16insli r42, r42, -6621\n"
- "shl16insli r42, r42, -11778\n"
- "{ cmoveqz r50, r28, r42 ; fnop }\n"
- "move %0, r50\n"
- "move %1, r28\n"
- "move %2, r42\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmoveqz_Y0.c b/none/tests/tilegx/insn_test_cmoveqz_Y0.c
deleted file mode 100644
index 00677fb..0000000
--- a/none/tests/tilegx/insn_test_cmoveqz_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmoveqz_Y0.c
-//op=51
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x8e9efd621a0271c0, 0xe6fd0819cb489949 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r50, -2571\n"
- "shl16insli r50, r50, 10073\n"
- "shl16insli r50, r50, -8744\n"
- "shl16insli r50, r50, 32440\n"
- "moveli r28, -14135\n"
- "shl16insli r28, r28, -9714\n"
- "shl16insli r28, r28, -28553\n"
- "shl16insli r28, r28, 1624\n"
- "moveli r42, -6121\n"
- "shl16insli r42, r42, -23936\n"
- "shl16insli r42, r42, -6621\n"
- "shl16insli r42, r42, -11778\n"
- "{ cmoveqz r50, r28, r42 ; fnop ; ld r63, r54 }\n"
- "move %0, r50\n"
- "move %1, r28\n"
- "move %2, r42\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmovnez_X0.c b/none/tests/tilegx/insn_test_cmovnez_X0.c
deleted file mode 100644
index b539654..0000000
--- a/none/tests/tilegx/insn_test_cmovnez_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmovnez_X0.c
-//op=52
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9276743f21019b4e, 0x82cd9e74ccb2b602 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r8, -7642\n"
- "shl16insli r8, r8, 2224\n"
- "shl16insli r8, r8, 3897\n"
- "shl16insli r8, r8, -23355\n"
- "moveli r24, 12753\n"
- "shl16insli r24, r24, 12718\n"
- "shl16insli r24, r24, 27517\n"
- "shl16insli r24, r24, -23530\n"
- "moveli r27, -27396\n"
- "shl16insli r27, r27, -8056\n"
- "shl16insli r27, r27, 23879\n"
- "shl16insli r27, r27, 14131\n"
- "{ cmovnez r8, r24, r27 ; fnop }\n"
- "move %0, r8\n"
- "move %1, r24\n"
- "move %2, r27\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmovnez_Y0.c b/none/tests/tilegx/insn_test_cmovnez_Y0.c
deleted file mode 100644
index f792e11..0000000
--- a/none/tests/tilegx/insn_test_cmovnez_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmovnez_Y0.c
-//op=52
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9276743f21019b4e, 0x82cd9e74ccb2b602 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r8, -7642\n"
- "shl16insli r8, r8, 2224\n"
- "shl16insli r8, r8, 3897\n"
- "shl16insli r8, r8, -23355\n"
- "moveli r24, 12753\n"
- "shl16insli r24, r24, 12718\n"
- "shl16insli r24, r24, 27517\n"
- "shl16insli r24, r24, -23530\n"
- "moveli r27, -27396\n"
- "shl16insli r27, r27, -8056\n"
- "shl16insli r27, r27, 23879\n"
- "shl16insli r27, r27, 14131\n"
- "{ cmovnez r8, r24, r27 ; fnop ; ld r63, r54 }\n"
- "move %0, r8\n"
- "move %1, r24\n"
- "move %2, r27\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpeq_X0.c b/none/tests/tilegx/insn_test_cmpeq_X0.c
deleted file mode 100644
index 55d23a9..0000000
--- a/none/tests/tilegx/insn_test_cmpeq_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmpeq_X0.c
-//op=53
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x5fced320ec74ecd8, 0x28e0d2889b96db6d };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r0, -26485\n"
- "shl16insli r0, r0, 5854\n"
- "shl16insli r0, r0, 20645\n"
- "shl16insli r0, r0, 14858\n"
- "moveli r9, 12048\n"
- "shl16insli r9, r9, -17261\n"
- "shl16insli r9, r9, -23773\n"
- "shl16insli r9, r9, -13811\n"
- "moveli r7, -30106\n"
- "shl16insli r7, r7, 24510\n"
- "shl16insli r7, r7, -6618\n"
- "shl16insli r7, r7, 11033\n"
- "{ cmpeq r0, r9, r7 ; fnop }\n"
- "move %0, r0\n"
- "move %1, r9\n"
- "move %2, r7\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpeq_X1.c b/none/tests/tilegx/insn_test_cmpeq_X1.c
deleted file mode 100644
index f47dc6e..0000000
--- a/none/tests/tilegx/insn_test_cmpeq_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmpeq_X1.c
-//op=53
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x5fced320ec74ecd8, 0x28e0d2889b96db6d };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r0, -26485\n"
- "shl16insli r0, r0, 5854\n"
- "shl16insli r0, r0, 20645\n"
- "shl16insli r0, r0, 14858\n"
- "moveli r9, 12048\n"
- "shl16insli r9, r9, -17261\n"
- "shl16insli r9, r9, -23773\n"
- "shl16insli r9, r9, -13811\n"
- "moveli r7, -30106\n"
- "shl16insli r7, r7, 24510\n"
- "shl16insli r7, r7, -6618\n"
- "shl16insli r7, r7, 11033\n"
- "{ fnop ; cmpeq r0, r9, r7 }\n"
- "move %0, r0\n"
- "move %1, r9\n"
- "move %2, r7\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpeq_Y0.c b/none/tests/tilegx/insn_test_cmpeq_Y0.c
deleted file mode 100644
index 9fd2a78..0000000
--- a/none/tests/tilegx/insn_test_cmpeq_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmpeq_Y0.c
-//op=53
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x5fced320ec74ecd8, 0x28e0d2889b96db6d };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r0, -26485\n"
- "shl16insli r0, r0, 5854\n"
- "shl16insli r0, r0, 20645\n"
- "shl16insli r0, r0, 14858\n"
- "moveli r9, 12048\n"
- "shl16insli r9, r9, -17261\n"
- "shl16insli r9, r9, -23773\n"
- "shl16insli r9, r9, -13811\n"
- "moveli r7, -30106\n"
- "shl16insli r7, r7, 24510\n"
- "shl16insli r7, r7, -6618\n"
- "shl16insli r7, r7, 11033\n"
- "{ cmpeq r0, r9, r7 ; fnop ; ld r63, r54 }\n"
- "move %0, r0\n"
- "move %1, r9\n"
- "move %2, r7\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpeq_Y1.c b/none/tests/tilegx/insn_test_cmpeq_Y1.c
deleted file mode 100644
index 16f74c8..0000000
--- a/none/tests/tilegx/insn_test_cmpeq_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmpeq_Y1.c
-//op=53
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x5fced320ec74ecd8, 0x28e0d2889b96db6d };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r0, -26485\n"
- "shl16insli r0, r0, 5854\n"
- "shl16insli r0, r0, 20645\n"
- "shl16insli r0, r0, 14858\n"
- "moveli r9, 12048\n"
- "shl16insli r9, r9, -17261\n"
- "shl16insli r9, r9, -23773\n"
- "shl16insli r9, r9, -13811\n"
- "moveli r7, -30106\n"
- "shl16insli r7, r7, 24510\n"
- "shl16insli r7, r7, -6618\n"
- "shl16insli r7, r7, 11033\n"
- "{ fnop ; cmpeq r0, r9, r7 ; ld r63, r54 }\n"
- "move %0, r0\n"
- "move %1, r9\n"
- "move %2, r7\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpeqi_X0.c b/none/tests/tilegx/insn_test_cmpeqi_X0.c
deleted file mode 100644
index 015abf1..0000000
--- a/none/tests/tilegx/insn_test_cmpeqi_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_cmpeqi_X0.c
-//op=54
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc051e6bca12058e0, 0xd5875ac284be5010 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r49, -29338\n"
- "shl16insli r49, r49, 4578\n"
- "shl16insli r49, r49, -8168\n"
- "shl16insli r49, r49, -29363\n"
- "moveli r17, 8846\n"
- "shl16insli r17, r17, -29053\n"
- "shl16insli r17, r17, -18602\n"
- "shl16insli r17, r17, 7817\n"
- "{ cmpeqi r49, r17, -1 ; fnop }\n"
- "move %0, r49\n"
- "move %1, r17\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpeqi_X1.c b/none/tests/tilegx/insn_test_cmpeqi_X1.c
deleted file mode 100644
index 67a2536..0000000
--- a/none/tests/tilegx/insn_test_cmpeqi_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_cmpeqi_X1.c
-//op=54
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc051e6bca12058e0, 0xd5875ac284be5010 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r49, -29338\n"
- "shl16insli r49, r49, 4578\n"
- "shl16insli r49, r49, -8168\n"
- "shl16insli r49, r49, -29363\n"
- "moveli r17, 8846\n"
- "shl16insli r17, r17, -29053\n"
- "shl16insli r17, r17, -18602\n"
- "shl16insli r17, r17, 7817\n"
- "{ fnop ; cmpeqi r49, r17, -1 }\n"
- "move %0, r49\n"
- "move %1, r17\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpeqi_Y0.c b/none/tests/tilegx/insn_test_cmpeqi_Y0.c
deleted file mode 100644
index 0131ce1..0000000
--- a/none/tests/tilegx/insn_test_cmpeqi_Y0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_cmpeqi_Y0.c
-//op=54
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc051e6bca12058e0, 0xd5875ac284be5010 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r49, -29338\n"
- "shl16insli r49, r49, 4578\n"
- "shl16insli r49, r49, -8168\n"
- "shl16insli r49, r49, -29363\n"
- "moveli r17, 8846\n"
- "shl16insli r17, r17, -29053\n"
- "shl16insli r17, r17, -18602\n"
- "shl16insli r17, r17, 7817\n"
- "{ cmpeqi r49, r17, -1 ; fnop ; ld r63, r54 }\n"
- "move %0, r49\n"
- "move %1, r17\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpeqi_Y1.c b/none/tests/tilegx/insn_test_cmpeqi_Y1.c
deleted file mode 100644
index e810546..0000000
--- a/none/tests/tilegx/insn_test_cmpeqi_Y1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_cmpeqi_Y1.c
-//op=54
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc051e6bca12058e0, 0xd5875ac284be5010 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r49, -29338\n"
- "shl16insli r49, r49, 4578\n"
- "shl16insli r49, r49, -8168\n"
- "shl16insli r49, r49, -29363\n"
- "moveli r17, 8846\n"
- "shl16insli r17, r17, -29053\n"
- "shl16insli r17, r17, -18602\n"
- "shl16insli r17, r17, 7817\n"
- "{ fnop ; cmpeqi r49, r17, -1 ; ld r63, r54 }\n"
- "move %0, r49\n"
- "move %1, r17\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmples_X0.c b/none/tests/tilegx/insn_test_cmples_X0.c
deleted file mode 100644
index 462bdda..0000000
--- a/none/tests/tilegx/insn_test_cmples_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmples_X0.c
-//op=57
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd4017cfe9fa6ebaa, 0x98d3e0700ab2b8d9 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r34, -26683\n"
- "shl16insli r34, r34, 3096\n"
- "shl16insli r34, r34, 25335\n"
- "shl16insli r34, r34, 30983\n"
- "moveli r26, -7486\n"
- "shl16insli r26, r26, 24081\n"
- "shl16insli r26, r26, 2997\n"
- "shl16insli r26, r26, -26298\n"
- "moveli r32, -10199\n"
- "shl16insli r32, r32, -13638\n"
- "shl16insli r32, r32, 17992\n"
- "shl16insli r32, r32, -16829\n"
- "{ cmples r34, r26, r32 ; fnop }\n"
- "move %0, r34\n"
- "move %1, r26\n"
- "move %2, r32\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmples_X1.c b/none/tests/tilegx/insn_test_cmples_X1.c
deleted file mode 100644
index 08525d0..0000000
--- a/none/tests/tilegx/insn_test_cmples_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmples_X1.c
-//op=57
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd4017cfe9fa6ebaa, 0x98d3e0700ab2b8d9 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r34, -26683\n"
- "shl16insli r34, r34, 3096\n"
- "shl16insli r34, r34, 25335\n"
- "shl16insli r34, r34, 30983\n"
- "moveli r26, -7486\n"
- "shl16insli r26, r26, 24081\n"
- "shl16insli r26, r26, 2997\n"
- "shl16insli r26, r26, -26298\n"
- "moveli r32, -10199\n"
- "shl16insli r32, r32, -13638\n"
- "shl16insli r32, r32, 17992\n"
- "shl16insli r32, r32, -16829\n"
- "{ fnop ; cmples r34, r26, r32 }\n"
- "move %0, r34\n"
- "move %1, r26\n"
- "move %2, r32\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmples_Y0.c b/none/tests/tilegx/insn_test_cmples_Y0.c
deleted file mode 100644
index be3865e..0000000
--- a/none/tests/tilegx/insn_test_cmples_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmples_Y0.c
-//op=57
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd4017cfe9fa6ebaa, 0x98d3e0700ab2b8d9 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r34, -26683\n"
- "shl16insli r34, r34, 3096\n"
- "shl16insli r34, r34, 25335\n"
- "shl16insli r34, r34, 30983\n"
- "moveli r26, -7486\n"
- "shl16insli r26, r26, 24081\n"
- "shl16insli r26, r26, 2997\n"
- "shl16insli r26, r26, -26298\n"
- "moveli r32, -10199\n"
- "shl16insli r32, r32, -13638\n"
- "shl16insli r32, r32, 17992\n"
- "shl16insli r32, r32, -16829\n"
- "{ cmples r34, r26, r32 ; fnop ; ld r63, r54 }\n"
- "move %0, r34\n"
- "move %1, r26\n"
- "move %2, r32\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmples_Y1.c b/none/tests/tilegx/insn_test_cmples_Y1.c
deleted file mode 100644
index dba3c58..0000000
--- a/none/tests/tilegx/insn_test_cmples_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmples_Y1.c
-//op=57
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd4017cfe9fa6ebaa, 0x98d3e0700ab2b8d9 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r34, -26683\n"
- "shl16insli r34, r34, 3096\n"
- "shl16insli r34, r34, 25335\n"
- "shl16insli r34, r34, 30983\n"
- "moveli r26, -7486\n"
- "shl16insli r26, r26, 24081\n"
- "shl16insli r26, r26, 2997\n"
- "shl16insli r26, r26, -26298\n"
- "moveli r32, -10199\n"
- "shl16insli r32, r32, -13638\n"
- "shl16insli r32, r32, 17992\n"
- "shl16insli r32, r32, -16829\n"
- "{ fnop ; cmples r34, r26, r32 ; ld r63, r54 }\n"
- "move %0, r34\n"
- "move %1, r26\n"
- "move %2, r32\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpleu_X0.c b/none/tests/tilegx/insn_test_cmpleu_X0.c
deleted file mode 100644
index 0c3866f..0000000
--- a/none/tests/tilegx/insn_test_cmpleu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmpleu_X0.c
-//op=58
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9a968c4e2652e151, 0x6fd6d80e8b18c9bb };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r16, -12524\n"
- "shl16insli r16, r16, -16020\n"
- "shl16insli r16, r16, -28698\n"
- "shl16insli r16, r16, -10230\n"
- "moveli r20, -25048\n"
- "shl16insli r20, r20, -26391\n"
- "shl16insli r20, r20, -12179\n"
- "shl16insli r20, r20, -11222\n"
- "moveli r10, -656\n"
- "shl16insli r10, r10, 236\n"
- "shl16insli r10, r10, -4273\n"
- "shl16insli r10, r10, -1226\n"
- "{ cmpleu r16, r20, r10 ; fnop }\n"
- "move %0, r16\n"
- "move %1, r20\n"
- "move %2, r10\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpleu_X1.c b/none/tests/tilegx/insn_test_cmpleu_X1.c
deleted file mode 100644
index b78705a..0000000
--- a/none/tests/tilegx/insn_test_cmpleu_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmpleu_X1.c
-//op=58
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9a968c4e2652e151, 0x6fd6d80e8b18c9bb };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r16, -12524\n"
- "shl16insli r16, r16, -16020\n"
- "shl16insli r16, r16, -28698\n"
- "shl16insli r16, r16, -10230\n"
- "moveli r20, -25048\n"
- "shl16insli r20, r20, -26391\n"
- "shl16insli r20, r20, -12179\n"
- "shl16insli r20, r20, -11222\n"
- "moveli r10, -656\n"
- "shl16insli r10, r10, 236\n"
- "shl16insli r10, r10, -4273\n"
- "shl16insli r10, r10, -1226\n"
- "{ fnop ; cmpleu r16, r20, r10 }\n"
- "move %0, r16\n"
- "move %1, r20\n"
- "move %2, r10\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpleu_Y0.c b/none/tests/tilegx/insn_test_cmpleu_Y0.c
deleted file mode 100644
index a454205..0000000
--- a/none/tests/tilegx/insn_test_cmpleu_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmpleu_Y0.c
-//op=58
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9a968c4e2652e151, 0x6fd6d80e8b18c9bb };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r16, -12524\n"
- "shl16insli r16, r16, -16020\n"
- "shl16insli r16, r16, -28698\n"
- "shl16insli r16, r16, -10230\n"
- "moveli r20, -25048\n"
- "shl16insli r20, r20, -26391\n"
- "shl16insli r20, r20, -12179\n"
- "shl16insli r20, r20, -11222\n"
- "moveli r10, -656\n"
- "shl16insli r10, r10, 236\n"
- "shl16insli r10, r10, -4273\n"
- "shl16insli r10, r10, -1226\n"
- "{ cmpleu r16, r20, r10 ; fnop ; ld r63, r54 }\n"
- "move %0, r16\n"
- "move %1, r20\n"
- "move %2, r10\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpleu_Y1.c b/none/tests/tilegx/insn_test_cmpleu_Y1.c
deleted file mode 100644
index 00a0fa7..0000000
--- a/none/tests/tilegx/insn_test_cmpleu_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmpleu_Y1.c
-//op=58
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9a968c4e2652e151, 0x6fd6d80e8b18c9bb };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r16, -12524\n"
- "shl16insli r16, r16, -16020\n"
- "shl16insli r16, r16, -28698\n"
- "shl16insli r16, r16, -10230\n"
- "moveli r20, -25048\n"
- "shl16insli r20, r20, -26391\n"
- "shl16insli r20, r20, -12179\n"
- "shl16insli r20, r20, -11222\n"
- "moveli r10, -656\n"
- "shl16insli r10, r10, 236\n"
- "shl16insli r10, r10, -4273\n"
- "shl16insli r10, r10, -1226\n"
- "{ fnop ; cmpleu r16, r20, r10 ; ld r63, r54 }\n"
- "move %0, r16\n"
- "move %1, r20\n"
- "move %2, r10\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmplts_X0.c b/none/tests/tilegx/insn_test_cmplts_X0.c
deleted file mode 100644
index f7302a7..0000000
--- a/none/tests/tilegx/insn_test_cmplts_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmplts_X0.c
-//op=59
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xdfe94ab09fee22a5, 0x379c002b0119bd52 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r3, -11368\n"
- "shl16insli r3, r3, -9764\n"
- "shl16insli r3, r3, -880\n"
- "shl16insli r3, r3, -31125\n"
- "moveli r31, -25744\n"
- "shl16insli r31, r31, -23478\n"
- "shl16insli r31, r31, -21167\n"
- "shl16insli r31, r31, -9956\n"
- "moveli r9, 19348\n"
- "shl16insli r9, r9, 13914\n"
- "shl16insli r9, r9, -27396\n"
- "shl16insli r9, r9, -31879\n"
- "{ cmplts r3, r31, r9 ; fnop }\n"
- "move %0, r3\n"
- "move %1, r31\n"
- "move %2, r9\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmplts_X1.c b/none/tests/tilegx/insn_test_cmplts_X1.c
deleted file mode 100644
index e4eafba..0000000
--- a/none/tests/tilegx/insn_test_cmplts_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmplts_X1.c
-//op=59
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xdfe94ab09fee22a5, 0x379c002b0119bd52 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r3, -11368\n"
- "shl16insli r3, r3, -9764\n"
- "shl16insli r3, r3, -880\n"
- "shl16insli r3, r3, -31125\n"
- "moveli r31, -25744\n"
- "shl16insli r31, r31, -23478\n"
- "shl16insli r31, r31, -21167\n"
- "shl16insli r31, r31, -9956\n"
- "moveli r9, 19348\n"
- "shl16insli r9, r9, 13914\n"
- "shl16insli r9, r9, -27396\n"
- "shl16insli r9, r9, -31879\n"
- "{ fnop ; cmplts r3, r31, r9 }\n"
- "move %0, r3\n"
- "move %1, r31\n"
- "move %2, r9\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmplts_Y0.c b/none/tests/tilegx/insn_test_cmplts_Y0.c
deleted file mode 100644
index b5d1b6b..0000000
--- a/none/tests/tilegx/insn_test_cmplts_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmplts_Y0.c
-//op=59
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xdfe94ab09fee22a5, 0x379c002b0119bd52 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r3, -11368\n"
- "shl16insli r3, r3, -9764\n"
- "shl16insli r3, r3, -880\n"
- "shl16insli r3, r3, -31125\n"
- "moveli r31, -25744\n"
- "shl16insli r31, r31, -23478\n"
- "shl16insli r31, r31, -21167\n"
- "shl16insli r31, r31, -9956\n"
- "moveli r9, 19348\n"
- "shl16insli r9, r9, 13914\n"
- "shl16insli r9, r9, -27396\n"
- "shl16insli r9, r9, -31879\n"
- "{ cmplts r3, r31, r9 ; fnop ; ld r63, r54 }\n"
- "move %0, r3\n"
- "move %1, r31\n"
- "move %2, r9\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmplts_Y1.c b/none/tests/tilegx/insn_test_cmplts_Y1.c
deleted file mode 100644
index 341c09d..0000000
--- a/none/tests/tilegx/insn_test_cmplts_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmplts_Y1.c
-//op=59
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xdfe94ab09fee22a5, 0x379c002b0119bd52 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r3, -11368\n"
- "shl16insli r3, r3, -9764\n"
- "shl16insli r3, r3, -880\n"
- "shl16insli r3, r3, -31125\n"
- "moveli r31, -25744\n"
- "shl16insli r31, r31, -23478\n"
- "shl16insli r31, r31, -21167\n"
- "shl16insli r31, r31, -9956\n"
- "moveli r9, 19348\n"
- "shl16insli r9, r9, 13914\n"
- "shl16insli r9, r9, -27396\n"
- "shl16insli r9, r9, -31879\n"
- "{ fnop ; cmplts r3, r31, r9 ; ld r63, r54 }\n"
- "move %0, r3\n"
- "move %1, r31\n"
- "move %2, r9\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpltsi_X0.c b/none/tests/tilegx/insn_test_cmpltsi_X0.c
deleted file mode 100644
index 69b6836..0000000
--- a/none/tests/tilegx/insn_test_cmpltsi_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_cmpltsi_X0.c
-//op=60
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xa702a184ea8a31f7, 0xd5c03dafaeab4e7e };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r4, -686\n"
- "shl16insli r4, r4, -26042\n"
- "shl16insli r4, r4, 8081\n"
- "shl16insli r4, r4, -25541\n"
- "moveli r24, -12028\n"
- "shl16insli r24, r24, -6402\n"
- "shl16insli r24, r24, -9261\n"
- "shl16insli r24, r24, 9978\n"
- "{ cmpltsi r4, r24, -23 ; fnop }\n"
- "move %0, r4\n"
- "move %1, r24\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpltsi_X1.c b/none/tests/tilegx/insn_test_cmpltsi_X1.c
deleted file mode 100644
index 37de364..0000000
--- a/none/tests/tilegx/insn_test_cmpltsi_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_cmpltsi_X1.c
-//op=60
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xa702a184ea8a31f7, 0xd5c03dafaeab4e7e };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r4, -686\n"
- "shl16insli r4, r4, -26042\n"
- "shl16insli r4, r4, 8081\n"
- "shl16insli r4, r4, -25541\n"
- "moveli r24, -12028\n"
- "shl16insli r24, r24, -6402\n"
- "shl16insli r24, r24, -9261\n"
- "shl16insli r24, r24, 9978\n"
- "{ fnop ; cmpltsi r4, r24, -23 }\n"
- "move %0, r4\n"
- "move %1, r24\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpltsi_Y0.c b/none/tests/tilegx/insn_test_cmpltsi_Y0.c
deleted file mode 100644
index 74e9a2e..0000000
--- a/none/tests/tilegx/insn_test_cmpltsi_Y0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_cmpltsi_Y0.c
-//op=60
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xa702a184ea8a31f7, 0xd5c03dafaeab4e7e };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r4, -686\n"
- "shl16insli r4, r4, -26042\n"
- "shl16insli r4, r4, 8081\n"
- "shl16insli r4, r4, -25541\n"
- "moveli r24, -12028\n"
- "shl16insli r24, r24, -6402\n"
- "shl16insli r24, r24, -9261\n"
- "shl16insli r24, r24, 9978\n"
- "{ cmpltsi r4, r24, -23 ; fnop ; ld r63, r54 }\n"
- "move %0, r4\n"
- "move %1, r24\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpltsi_Y1.c b/none/tests/tilegx/insn_test_cmpltsi_Y1.c
deleted file mode 100644
index a1e3d03..0000000
--- a/none/tests/tilegx/insn_test_cmpltsi_Y1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_cmpltsi_Y1.c
-//op=60
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xa702a184ea8a31f7, 0xd5c03dafaeab4e7e };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r4, -686\n"
- "shl16insli r4, r4, -26042\n"
- "shl16insli r4, r4, 8081\n"
- "shl16insli r4, r4, -25541\n"
- "moveli r24, -12028\n"
- "shl16insli r24, r24, -6402\n"
- "shl16insli r24, r24, -9261\n"
- "shl16insli r24, r24, 9978\n"
- "{ fnop ; cmpltsi r4, r24, -23 ; ld r63, r54 }\n"
- "move %0, r4\n"
- "move %1, r24\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpltu_X0.c b/none/tests/tilegx/insn_test_cmpltu_X0.c
deleted file mode 100644
index e680a68..0000000
--- a/none/tests/tilegx/insn_test_cmpltu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmpltu_X0.c
-//op=61
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x26836d784e440ab7, 0xef3b92483b066295 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r13, -20987\n"
- "shl16insli r13, r13, 15474\n"
- "shl16insli r13, r13, 14956\n"
- "shl16insli r13, r13, -29129\n"
- "moveli r6, 6095\n"
- "shl16insli r6, r6, -319\n"
- "shl16insli r6, r6, -21787\n"
- "shl16insli r6, r6, -21356\n"
- "moveli r35, 8260\n"
- "shl16insli r35, r35, -7206\n"
- "shl16insli r35, r35, -24567\n"
- "shl16insli r35, r35, -8840\n"
- "{ cmpltu r13, r6, r35 ; fnop }\n"
- "move %0, r13\n"
- "move %1, r6\n"
- "move %2, r35\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpltu_X1.c b/none/tests/tilegx/insn_test_cmpltu_X1.c
deleted file mode 100644
index 355764d..0000000
--- a/none/tests/tilegx/insn_test_cmpltu_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmpltu_X1.c
-//op=61
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x26836d784e440ab7, 0xef3b92483b066295 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r13, -20987\n"
- "shl16insli r13, r13, 15474\n"
- "shl16insli r13, r13, 14956\n"
- "shl16insli r13, r13, -29129\n"
- "moveli r6, 6095\n"
- "shl16insli r6, r6, -319\n"
- "shl16insli r6, r6, -21787\n"
- "shl16insli r6, r6, -21356\n"
- "moveli r35, 8260\n"
- "shl16insli r35, r35, -7206\n"
- "shl16insli r35, r35, -24567\n"
- "shl16insli r35, r35, -8840\n"
- "{ fnop ; cmpltu r13, r6, r35 }\n"
- "move %0, r13\n"
- "move %1, r6\n"
- "move %2, r35\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpltu_Y0.c b/none/tests/tilegx/insn_test_cmpltu_Y0.c
deleted file mode 100644
index 79a73d9..0000000
--- a/none/tests/tilegx/insn_test_cmpltu_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmpltu_Y0.c
-//op=61
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x26836d784e440ab7, 0xef3b92483b066295 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r13, -20987\n"
- "shl16insli r13, r13, 15474\n"
- "shl16insli r13, r13, 14956\n"
- "shl16insli r13, r13, -29129\n"
- "moveli r6, 6095\n"
- "shl16insli r6, r6, -319\n"
- "shl16insli r6, r6, -21787\n"
- "shl16insli r6, r6, -21356\n"
- "moveli r35, 8260\n"
- "shl16insli r35, r35, -7206\n"
- "shl16insli r35, r35, -24567\n"
- "shl16insli r35, r35, -8840\n"
- "{ cmpltu r13, r6, r35 ; fnop ; ld r63, r54 }\n"
- "move %0, r13\n"
- "move %1, r6\n"
- "move %2, r35\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpltu_Y1.c b/none/tests/tilegx/insn_test_cmpltu_Y1.c
deleted file mode 100644
index 4169565..0000000
--- a/none/tests/tilegx/insn_test_cmpltu_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmpltu_Y1.c
-//op=61
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x26836d784e440ab7, 0xef3b92483b066295 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r13, -20987\n"
- "shl16insli r13, r13, 15474\n"
- "shl16insli r13, r13, 14956\n"
- "shl16insli r13, r13, -29129\n"
- "moveli r6, 6095\n"
- "shl16insli r6, r6, -319\n"
- "shl16insli r6, r6, -21787\n"
- "shl16insli r6, r6, -21356\n"
- "moveli r35, 8260\n"
- "shl16insli r35, r35, -7206\n"
- "shl16insli r35, r35, -24567\n"
- "shl16insli r35, r35, -8840\n"
- "{ fnop ; cmpltu r13, r6, r35 ; ld r63, r54 }\n"
- "move %0, r13\n"
- "move %1, r6\n"
- "move %2, r35\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpltui_X0.c b/none/tests/tilegx/insn_test_cmpltui_X0.c
deleted file mode 100644
index 0639bea..0000000
--- a/none/tests/tilegx/insn_test_cmpltui_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_cmpltui_X0.c
-//op=62
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x6a0cb98ab56a8e60, 0xa3f9a29247d48ea1 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r30, 27938\n"
- "shl16insli r30, r30, -31883\n"
- "shl16insli r30, r30, -15298\n"
- "shl16insli r30, r30, 10238\n"
- "moveli r29, -25838\n"
- "shl16insli r29, r29, 23398\n"
- "shl16insli r29, r29, 16827\n"
- "shl16insli r29, r29, -24775\n"
- "{ cmpltui r30, r29, 114 ; fnop }\n"
- "move %0, r30\n"
- "move %1, r29\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpltui_X1.c b/none/tests/tilegx/insn_test_cmpltui_X1.c
deleted file mode 100644
index 24e4151..0000000
--- a/none/tests/tilegx/insn_test_cmpltui_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_cmpltui_X1.c
-//op=62
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x6a0cb98ab56a8e60, 0xa3f9a29247d48ea1 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r30, 27938\n"
- "shl16insli r30, r30, -31883\n"
- "shl16insli r30, r30, -15298\n"
- "shl16insli r30, r30, 10238\n"
- "moveli r29, -25838\n"
- "shl16insli r29, r29, 23398\n"
- "shl16insli r29, r29, 16827\n"
- "shl16insli r29, r29, -24775\n"
- "{ fnop ; cmpltui r30, r29, 114 }\n"
- "move %0, r30\n"
- "move %1, r29\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpne_X0.c b/none/tests/tilegx/insn_test_cmpne_X0.c
deleted file mode 100644
index 79f08c1..0000000
--- a/none/tests/tilegx/insn_test_cmpne_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmpne_X0.c
-//op=63
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x11b59d6276787136, 0x78c2286b07e86b55 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r45, -19189\n"
- "shl16insli r45, r45, 6578\n"
- "shl16insli r45, r45, 17580\n"
- "shl16insli r45, r45, 32436\n"
- "moveli r36, -31697\n"
- "shl16insli r36, r36, 8179\n"
- "shl16insli r36, r36, -19147\n"
- "shl16insli r36, r36, -16129\n"
- "moveli r19, -12252\n"
- "shl16insli r19, r19, 5860\n"
- "shl16insli r19, r19, 15129\n"
- "shl16insli r19, r19, -15375\n"
- "{ cmpne r45, r36, r19 ; fnop }\n"
- "move %0, r45\n"
- "move %1, r36\n"
- "move %2, r19\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpne_X1.c b/none/tests/tilegx/insn_test_cmpne_X1.c
deleted file mode 100644
index 469a95d..0000000
--- a/none/tests/tilegx/insn_test_cmpne_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmpne_X1.c
-//op=63
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x11b59d6276787136, 0x78c2286b07e86b55 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r45, -19189\n"
- "shl16insli r45, r45, 6578\n"
- "shl16insli r45, r45, 17580\n"
- "shl16insli r45, r45, 32436\n"
- "moveli r36, -31697\n"
- "shl16insli r36, r36, 8179\n"
- "shl16insli r36, r36, -19147\n"
- "shl16insli r36, r36, -16129\n"
- "moveli r19, -12252\n"
- "shl16insli r19, r19, 5860\n"
- "shl16insli r19, r19, 15129\n"
- "shl16insli r19, r19, -15375\n"
- "{ fnop ; cmpne r45, r36, r19 }\n"
- "move %0, r45\n"
- "move %1, r36\n"
- "move %2, r19\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpne_Y0.c b/none/tests/tilegx/insn_test_cmpne_Y0.c
deleted file mode 100644
index 731941b..0000000
--- a/none/tests/tilegx/insn_test_cmpne_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmpne_Y0.c
-//op=63
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x11b59d6276787136, 0x78c2286b07e86b55 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r45, -19189\n"
- "shl16insli r45, r45, 6578\n"
- "shl16insli r45, r45, 17580\n"
- "shl16insli r45, r45, 32436\n"
- "moveli r36, -31697\n"
- "shl16insli r36, r36, 8179\n"
- "shl16insli r36, r36, -19147\n"
- "shl16insli r36, r36, -16129\n"
- "moveli r19, -12252\n"
- "shl16insli r19, r19, 5860\n"
- "shl16insli r19, r19, 15129\n"
- "shl16insli r19, r19, -15375\n"
- "{ cmpne r45, r36, r19 ; fnop ; ld r63, r54 }\n"
- "move %0, r45\n"
- "move %1, r36\n"
- "move %2, r19\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmpne_Y1.c b/none/tests/tilegx/insn_test_cmpne_Y1.c
deleted file mode 100644
index 70a3ced..0000000
--- a/none/tests/tilegx/insn_test_cmpne_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmpne_Y1.c
-//op=63
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x11b59d6276787136, 0x78c2286b07e86b55 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r45, -19189\n"
- "shl16insli r45, r45, 6578\n"
- "shl16insli r45, r45, 17580\n"
- "shl16insli r45, r45, 32436\n"
- "moveli r36, -31697\n"
- "shl16insli r36, r36, 8179\n"
- "shl16insli r36, r36, -19147\n"
- "shl16insli r36, r36, -16129\n"
- "moveli r19, -12252\n"
- "shl16insli r19, r19, 5860\n"
- "shl16insli r19, r19, 15129\n"
- "shl16insli r19, r19, -15375\n"
- "{ fnop ; cmpne r45, r36, r19 ; ld r63, r54 }\n"
- "move %0, r45\n"
- "move %1, r36\n"
- "move %2, r19\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmul_X0.c b/none/tests/tilegx/insn_test_cmul_X0.c
deleted file mode 100644
index e2deb0c..0000000
--- a/none/tests/tilegx/insn_test_cmul_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmul_X0.c
-//op=64
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x411d3fc3fc916064, 0x4eb70a2cb8e0ad00 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r35, -12554\n"
- "shl16insli r35, r35, 3660\n"
- "shl16insli r35, r35, -31312\n"
- "shl16insli r35, r35, 5700\n"
- "moveli r21, 31847\n"
- "shl16insli r21, r21, 16845\n"
- "shl16insli r21, r21, -32108\n"
- "shl16insli r21, r21, -3821\n"
- "moveli r42, -5570\n"
- "shl16insli r42, r42, -29385\n"
- "shl16insli r42, r42, -18769\n"
- "shl16insli r42, r42, -2309\n"
- "{ cmul r35, r21, r42 ; fnop }\n"
- "move %0, r35\n"
- "move %1, r21\n"
- "move %2, r42\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmula_X0.c b/none/tests/tilegx/insn_test_cmula_X0.c
deleted file mode 100644
index aed073f..0000000
--- a/none/tests/tilegx/insn_test_cmula_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmula_X0.c
-//op=65
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x553c16d3559d1cee, 0xe53c5e867b2c2d0e };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r35, -20478\n"
- "shl16insli r35, r35, -22564\n"
- "shl16insli r35, r35, 7251\n"
- "shl16insli r35, r35, -29417\n"
- "moveli r35, 23890\n"
- "shl16insli r35, r35, 28671\n"
- "shl16insli r35, r35, -167\n"
- "shl16insli r35, r35, 16603\n"
- "moveli r5, 20445\n"
- "shl16insli r5, r5, -17976\n"
- "shl16insli r5, r5, -29438\n"
- "shl16insli r5, r5, -12912\n"
- "{ cmula r35, r35, r5 ; fnop }\n"
- "move %0, r35\n"
- "move %1, r35\n"
- "move %2, r5\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmulaf_X0.c b/none/tests/tilegx/insn_test_cmulaf_X0.c
deleted file mode 100644
index 611fc6d..0000000
--- a/none/tests/tilegx/insn_test_cmulaf_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmulaf_X0.c
-//op=66
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x386e67ed7b089fc9, 0x159952beef1e2d8e };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r17, 12406\n"
- "shl16insli r17, r17, -7608\n"
- "shl16insli r17, r17, -24144\n"
- "shl16insli r17, r17, 13065\n"
- "moveli r20, 14943\n"
- "shl16insli r20, r20, -18119\n"
- "shl16insli r20, r20, -10933\n"
- "shl16insli r20, r20, 517\n"
- "moveli r30, 26677\n"
- "shl16insli r30, r30, 32003\n"
- "shl16insli r30, r30, 16745\n"
- "shl16insli r30, r30, -29543\n"
- "{ cmulaf r17, r20, r30 ; fnop }\n"
- "move %0, r17\n"
- "move %1, r20\n"
- "move %2, r30\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmulf_X0.c b/none/tests/tilegx/insn_test_cmulf_X0.c
deleted file mode 100644
index ff0a7fa..0000000
--- a/none/tests/tilegx/insn_test_cmulf_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmulf_X0.c
-//op=67
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x20a35a283e09bcf3, 0xf918ceb605460b8e };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r47, 12090\n"
- "shl16insli r47, r47, -15392\n"
- "shl16insli r47, r47, 393\n"
- "shl16insli r47, r47, 9111\n"
- "moveli r2, 22012\n"
- "shl16insli r2, r2, 18909\n"
- "shl16insli r2, r2, 17994\n"
- "shl16insli r2, r2, -10137\n"
- "moveli r46, 30081\n"
- "shl16insli r46, r46, 2888\n"
- "shl16insli r46, r46, 17535\n"
- "shl16insli r46, r46, -29480\n"
- "{ cmulf r47, r2, r46 ; fnop }\n"
- "move %0, r47\n"
- "move %1, r2\n"
- "move %2, r46\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmulfr_X0.c b/none/tests/tilegx/insn_test_cmulfr_X0.c
deleted file mode 100644
index 12c83f7..0000000
--- a/none/tests/tilegx/insn_test_cmulfr_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmulfr_X0.c
-//op=68
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x820d15cd622148e4, 0x7eda32ada2f5060 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r39, 9587\n"
- "shl16insli r39, r39, 15755\n"
- "shl16insli r39, r39, 24004\n"
- "shl16insli r39, r39, 30644\n"
- "moveli r16, -6121\n"
- "shl16insli r16, r16, -23936\n"
- "shl16insli r16, r16, -6621\n"
- "shl16insli r16, r16, -11778\n"
- "moveli r25, 25551\n"
- "shl16insli r25, r25, 28722\n"
- "shl16insli r25, r25, -26847\n"
- "shl16insli r25, r25, 5345\n"
- "{ cmulfr r39, r16, r25 ; fnop }\n"
- "move %0, r39\n"
- "move %1, r16\n"
- "move %2, r25\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmulh_X0.c b/none/tests/tilegx/insn_test_cmulh_X0.c
deleted file mode 100644
index 941cc33..0000000
--- a/none/tests/tilegx/insn_test_cmulh_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmulh_X0.c
-//op=69
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x4070076dbab015ca, 0x741405116e136ce3 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r26, 30607\n"
- "shl16insli r26, r26, 12143\n"
- "shl16insli r26, r26, 6105\n"
- "shl16insli r26, r26, 59\n"
- "moveli r3, -10033\n"
- "shl16insli r3, r3, 14176\n"
- "shl16insli r3, r3, -28670\n"
- "shl16insli r3, r3, 13765\n"
- "moveli r10, 8165\n"
- "shl16insli r10, r10, 18793\n"
- "shl16insli r10, r10, -22214\n"
- "shl16insli r10, r10, 5498\n"
- "{ cmulh r26, r3, r10 ; fnop }\n"
- "move %0, r26\n"
- "move %1, r3\n"
- "move %2, r10\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_cmulhr_X0.c b/none/tests/tilegx/insn_test_cmulhr_X0.c
deleted file mode 100644
index 2cbfe0c..0000000
--- a/none/tests/tilegx/insn_test_cmulhr_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_cmulhr_X0.c
-//op=70
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x3f45dbe8d3bddf1e, 0x6873aadf3e763127 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r49, 17759\n"
- "shl16insli r49, r49, -31178\n"
- "shl16insli r49, r49, -28954\n"
- "shl16insli r49, r49, -24129\n"
- "moveli r30, 15980\n"
- "shl16insli r30, r30, 6185\n"
- "shl16insli r30, r30, -3610\n"
- "shl16insli r30, r30, -10263\n"
- "moveli r31, 26063\n"
- "shl16insli r31, r31, 27563\n"
- "shl16insli r31, r31, 24059\n"
- "shl16insli r31, r31, -1753\n"
- "{ cmulhr r49, r30, r31 ; fnop }\n"
- "move %0, r49\n"
- "move %1, r30\n"
- "move %2, r31\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_crc32_32_X0.c b/none/tests/tilegx/insn_test_crc32_32_X0.c
deleted file mode 100644
index a3a9a78..0000000
--- a/none/tests/tilegx/insn_test_crc32_32_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_crc32_32_X0.c
-//op=71
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x5797c115d06a021e, 0xcec6c9aa9564502a };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r21, -22875\n"
- "shl16insli r21, r21, -32077\n"
- "shl16insli r21, r21, -9073\n"
- "shl16insli r21, r21, 28291\n"
- "moveli r18, -19329\n"
- "shl16insli r18, r18, -4231\n"
- "shl16insli r18, r18, 22518\n"
- "shl16insli r18, r18, 1958\n"
- "moveli r23, -31981\n"
- "shl16insli r23, r23, -84\n"
- "shl16insli r23, r23, 2678\n"
- "shl16insli r23, r23, 4570\n"
- "{ crc32_32 r21, r18, r23 ; fnop }\n"
- "move %0, r21\n"
- "move %1, r18\n"
- "move %2, r23\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_crc32_8_X0.c b/none/tests/tilegx/insn_test_crc32_8_X0.c
deleted file mode 100644
index f1f3596..0000000
--- a/none/tests/tilegx/insn_test_crc32_8_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_crc32_8_X0.c
-//op=72
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x48fd1654a7e669f7, 0x3c14fa8c76bb7fe3 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r34, -1456\n"
- "shl16insli r34, r34, -8976\n"
- "shl16insli r34, r34, -20412\n"
- "shl16insli r34, r34, -10854\n"
- "moveli r38, -32379\n"
- "shl16insli r38, r38, -17242\n"
- "shl16insli r38, r38, -8818\n"
- "shl16insli r38, r38, 7579\n"
- "moveli r45, 26010\n"
- "shl16insli r45, r45, -10170\n"
- "shl16insli r45, r45, -10239\n"
- "shl16insli r45, r45, -24168\n"
- "{ crc32_8 r34, r38, r45 ; fnop }\n"
- "move %0, r34\n"
- "move %1, r38\n"
- "move %2, r45\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ctz_X0.c b/none/tests/tilegx/insn_test_ctz_X0.c
deleted file mode 100644
index 1c100f1..0000000
--- a/none/tests/tilegx/insn_test_ctz_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_ctz_X0.c
-//op=73
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xea70c8b3ffd336c3, 0x4dcbb13e69f7210c };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r20, 21188\n"
- "shl16insli r20, r20, -26615\n"
- "shl16insli r20, r20, -6842\n"
- "shl16insli r20, r20, 23302\n"
- "moveli r15, -28043\n"
- "shl16insli r15, r15, -17799\n"
- "shl16insli r15, r15, -27340\n"
- "shl16insli r15, r15, -22535\n"
- "{ ctz r20, r15 ; fnop }\n"
- "move %0, r20\n"
- "move %1, r15\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ctz_Y0.c b/none/tests/tilegx/insn_test_ctz_Y0.c
deleted file mode 100644
index 9c0fbf9..0000000
--- a/none/tests/tilegx/insn_test_ctz_Y0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_ctz_Y0.c
-//op=73
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xea70c8b3ffd336c3, 0x4dcbb13e69f7210c };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r20, 21188\n"
- "shl16insli r20, r20, -26615\n"
- "shl16insli r20, r20, -6842\n"
- "shl16insli r20, r20, 23302\n"
- "moveli r15, -28043\n"
- "shl16insli r15, r15, -17799\n"
- "shl16insli r15, r15, -27340\n"
- "shl16insli r15, r15, -22535\n"
- "{ ctz r20, r15 ; fnop ; ld r63, r54 }\n"
- "move %0, r20\n"
- "move %1, r15\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_dblalign2_X0.c b/none/tests/tilegx/insn_test_dblalign2_X0.c
deleted file mode 100644
index 819891d..0000000
--- a/none/tests/tilegx/insn_test_dblalign2_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_dblalign2_X0.c
-//op=75
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x52148e33ddfabfa8, 0xc6860cbdb069dbcf };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r39, -27243\n"
- "shl16insli r39, r39, 13585\n"
- "shl16insli r39, r39, -1554\n"
- "shl16insli r39, r39, 17682\n"
- "moveli r19, -3548\n"
- "shl16insli r19, r19, -18819\n"
- "shl16insli r19, r19, -5126\n"
- "shl16insli r19, r19, -7819\n"
- "moveli r48, 10648\n"
- "shl16insli r48, r48, -21072\n"
- "shl16insli r48, r48, -30644\n"
- "shl16insli r48, r48, -24292\n"
- "{ dblalign2 r39, r19, r48 ; fnop }\n"
- "move %0, r39\n"
- "move %1, r19\n"
- "move %2, r48\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_dblalign2_X1.c b/none/tests/tilegx/insn_test_dblalign2_X1.c
deleted file mode 100644
index e3b7a13..0000000
--- a/none/tests/tilegx/insn_test_dblalign2_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_dblalign2_X1.c
-//op=75
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x52148e33ddfabfa8, 0xc6860cbdb069dbcf };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r39, -27243\n"
- "shl16insli r39, r39, 13585\n"
- "shl16insli r39, r39, -1554\n"
- "shl16insli r39, r39, 17682\n"
- "moveli r19, -3548\n"
- "shl16insli r19, r19, -18819\n"
- "shl16insli r19, r19, -5126\n"
- "shl16insli r19, r19, -7819\n"
- "moveli r48, 10648\n"
- "shl16insli r48, r48, -21072\n"
- "shl16insli r48, r48, -30644\n"
- "shl16insli r48, r48, -24292\n"
- "{ fnop ; dblalign2 r39, r19, r48 }\n"
- "move %0, r39\n"
- "move %1, r19\n"
- "move %2, r48\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_dblalign4_X0.c b/none/tests/tilegx/insn_test_dblalign4_X0.c
deleted file mode 100644
index 101d3c8..0000000
--- a/none/tests/tilegx/insn_test_dblalign4_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_dblalign4_X0.c
-//op=76
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xb17341a0d542c8a8, 0x2220b583f77f7510 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r41, -25189\n"
- "shl16insli r41, r41, 30892\n"
- "shl16insli r41, r41, 12292\n"
- "shl16insli r41, r41, 9859\n"
- "moveli r10, -10199\n"
- "shl16insli r10, r10, -13638\n"
- "shl16insli r10, r10, 17992\n"
- "shl16insli r10, r10, -16829\n"
- "moveli r16, -8310\n"
- "shl16insli r16, r16, -28931\n"
- "shl16insli r16, r16, 16317\n"
- "shl16insli r16, r16, -2081\n"
- "{ dblalign4 r41, r10, r16 ; fnop }\n"
- "move %0, r41\n"
- "move %1, r10\n"
- "move %2, r16\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_dblalign4_X1.c b/none/tests/tilegx/insn_test_dblalign4_X1.c
deleted file mode 100644
index a5a587d..0000000
--- a/none/tests/tilegx/insn_test_dblalign4_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_dblalign4_X1.c
-//op=76
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xb17341a0d542c8a8, 0x2220b583f77f7510 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r41, -25189\n"
- "shl16insli r41, r41, 30892\n"
- "shl16insli r41, r41, 12292\n"
- "shl16insli r41, r41, 9859\n"
- "moveli r10, -10199\n"
- "shl16insli r10, r10, -13638\n"
- "shl16insli r10, r10, 17992\n"
- "shl16insli r10, r10, -16829\n"
- "moveli r16, -8310\n"
- "shl16insli r16, r16, -28931\n"
- "shl16insli r16, r16, 16317\n"
- "shl16insli r16, r16, -2081\n"
- "{ fnop ; dblalign4 r41, r10, r16 }\n"
- "move %0, r41\n"
- "move %1, r10\n"
- "move %2, r16\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_dblalign6_X0.c b/none/tests/tilegx/insn_test_dblalign6_X0.c
deleted file mode 100644
index 29f370b..0000000
--- a/none/tests/tilegx/insn_test_dblalign6_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_dblalign6_X0.c
-//op=77
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x32e0ae3536cebe67, 0x8917ce8584615586 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r45, 30164\n"
- "shl16insli r45, r45, 21219\n"
- "shl16insli r45, r45, -24252\n"
- "shl16insli r45, r45, -4168\n"
- "moveli r35, 27921\n"
- "shl16insli r35, r35, 15394\n"
- "shl16insli r35, r35, -22195\n"
- "shl16insli r35, r35, 26084\n"
- "moveli r2, 25320\n"
- "shl16insli r2, r2, 3164\n"
- "shl16insli r2, r2, 17326\n"
- "shl16insli r2, r2, 5238\n"
- "{ dblalign6 r45, r35, r2 ; fnop }\n"
- "move %0, r45\n"
- "move %1, r35\n"
- "move %2, r2\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_dblalign6_X1.c b/none/tests/tilegx/insn_test_dblalign6_X1.c
deleted file mode 100644
index 0a23aaa..0000000
--- a/none/tests/tilegx/insn_test_dblalign6_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_dblalign6_X1.c
-//op=77
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x32e0ae3536cebe67, 0x8917ce8584615586 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r45, 30164\n"
- "shl16insli r45, r45, 21219\n"
- "shl16insli r45, r45, -24252\n"
- "shl16insli r45, r45, -4168\n"
- "moveli r35, 27921\n"
- "shl16insli r35, r35, 15394\n"
- "shl16insli r35, r35, -22195\n"
- "shl16insli r35, r35, 26084\n"
- "moveli r2, 25320\n"
- "shl16insli r2, r2, 3164\n"
- "shl16insli r2, r2, 17326\n"
- "shl16insli r2, r2, 5238\n"
- "{ fnop ; dblalign6 r45, r35, r2 }\n"
- "move %0, r45\n"
- "move %1, r35\n"
- "move %2, r2\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_dblalign_X0.c b/none/tests/tilegx/insn_test_dblalign_X0.c
deleted file mode 100644
index f258c21..0000000
--- a/none/tests/tilegx/insn_test_dblalign_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_dblalign_X0.c
-//op=74
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x68fb6e92c7467995, 0x712fa2e35cfc84ba };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r14, -10628\n"
- "shl16insli r14, r14, 21331\n"
- "shl16insli r14, r14, -19208\n"
- "shl16insli r14, r14, 14673\n"
- "moveli r28, -30755\n"
- "shl16insli r28, r28, 5835\n"
- "shl16insli r28, r28, -24471\n"
- "shl16insli r28, r28, -4179\n"
- "moveli r29, -10637\n"
- "shl16insli r29, r29, -13587\n"
- "shl16insli r29, r29, 6072\n"
- "shl16insli r29, r29, -2381\n"
- "{ dblalign r14, r28, r29 ; fnop }\n"
- "move %0, r14\n"
- "move %1, r28\n"
- "move %2, r29\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_dtlbpr_X1.c b/none/tests/tilegx/insn_test_dtlbpr_X1.c
deleted file mode 100644
index 1c528a6..0000000
--- a/none/tests/tilegx/insn_test_dtlbpr_X1.c
+++ /dev/null
@@ -1,30 +0,0 @@
-//file: _insn_test_dtlbpr_X1.c
-//op=79
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x910a2955c6e71b1, 0x884eacaf96426585 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r6, 6476\n"
- "shl16insli r6, r6, -30926\n"
- "shl16insli r6, r6, 24920\n"
- "shl16insli r6, r6, 10073\n"
- "{ fnop ; dtlbpr r6 }\n"
- "move %0, r6\n"
- :"=r"(a[0]));
- printf("%016lx\n", a[0]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_fdouble_add_flags_X0.c b/none/tests/tilegx/insn_test_fdouble_add_flags_X0.c
deleted file mode 100644
index bbe3c7a..0000000
--- a/none/tests/tilegx/insn_test_fdouble_add_flags_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_fdouble_add_flags_X0.c
-//op=82
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x5ff5d41ce72b342e, 0xec57de1f0b8de6b3 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r40, -10411\n"
- "shl16insli r40, r40, 28866\n"
- "shl16insli r40, r40, 30647\n"
- "shl16insli r40, r40, 15107\n"
- "moveli r21, 13116\n"
- "shl16insli r21, r21, 11172\n"
- "shl16insli r21, r21, -2564\n"
- "shl16insli r21, r21, 1912\n"
- "moveli r44, 10847\n"
- "shl16insli r44, r44, -21273\n"
- "shl16insli r44, r44, -26560\n"
- "shl16insli r44, r44, -2137\n"
- "{ fdouble_add_flags r40, r21, r44 ; fnop }\n"
- "move %0, r40\n"
- "move %1, r21\n"
- "move %2, r44\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_fdouble_addsub_X0.c b/none/tests/tilegx/insn_test_fdouble_addsub_X0.c
deleted file mode 100644
index f1a2970..0000000
--- a/none/tests/tilegx/insn_test_fdouble_addsub_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_fdouble_addsub_X0.c
-//op=83
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x57b488292bdd9c2b, 0xfd7e2c78d6f58fbd };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r50, 9884\n"
- "shl16insli r50, r50, -18142\n"
- "shl16insli r50, r50, -24129\n"
- "shl16insli r50, r50, 11296\n"
- "moveli r9, -26512\n"
- "shl16insli r9, r9, -8064\n"
- "shl16insli r9, r9, 9043\n"
- "shl16insli r9, r9, 18472\n"
- "moveli r20, 4246\n"
- "shl16insli r20, r20, 6079\n"
- "shl16insli r20, r20, 8698\n"
- "shl16insli r20, r20, -2697\n"
- "{ fdouble_addsub r50, r9, r20 ; fnop }\n"
- "move %0, r50\n"
- "move %1, r9\n"
- "move %2, r20\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_fdouble_mul_flags_X0.c b/none/tests/tilegx/insn_test_fdouble_mul_flags_X0.c
deleted file mode 100644
index c939561..0000000
--- a/none/tests/tilegx/insn_test_fdouble_mul_flags_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_fdouble_mul_flags_X0.c
-//op=84
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xdff35e384e663195, 0xce5c4dd59315697c };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r23, -2482\n"
- "shl16insli r23, r23, 1883\n"
- "shl16insli r23, r23, 757\n"
- "shl16insli r23, r23, 5578\n"
- "moveli r32, -12252\n"
- "shl16insli r32, r32, 5860\n"
- "shl16insli r32, r32, 15129\n"
- "shl16insli r32, r32, -15375\n"
- "moveli r3, -4690\n"
- "shl16insli r3, r3, 18437\n"
- "shl16insli r3, r3, 14549\n"
- "shl16insli r3, r3, -22291\n"
- "{ fdouble_mul_flags r23, r32, r3 ; fnop }\n"
- "move %0, r23\n"
- "move %1, r32\n"
- "move %2, r3\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_fdouble_pack1_X0.c b/none/tests/tilegx/insn_test_fdouble_pack1_X0.c
deleted file mode 100644
index 74e5a6f..0000000
--- a/none/tests/tilegx/insn_test_fdouble_pack1_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_fdouble_pack1_X0.c
-//op=85
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x8a6bdf08a51f10d3, 0xbb06a702206f99b2 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r28, 31787\n"
- "shl16insli r28, r28, 188\n"
- "shl16insli r28, r28, -30112\n"
- "shl16insli r28, r28, -13987\n"
- "moveli r28, -217\n"
- "shl16insli r28, r28, -31069\n"
- "shl16insli r28, r28, 14592\n"
- "shl16insli r28, r28, 26557\n"
- "moveli r26, -8315\n"
- "shl16insli r26, r26, 5404\n"
- "shl16insli r26, r26, 15177\n"
- "shl16insli r26, r26, -6931\n"
- "{ fdouble_pack1 r28, r28, r26 ; fnop }\n"
- "move %0, r28\n"
- "move %1, r28\n"
- "move %2, r26\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_fdouble_pack2_X0.c b/none/tests/tilegx/insn_test_fdouble_pack2_X0.c
deleted file mode 100644
index 0cc8f9b..0000000
--- a/none/tests/tilegx/insn_test_fdouble_pack2_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_fdouble_pack2_X0.c
-//op=86
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x38646a3eaf613478, 0xc2c31988eb4ca702 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r9, 18459\n"
- "shl16insli r9, r9, -11831\n"
- "shl16insli r9, r9, -23522\n"
- "shl16insli r9, r9, -17142\n"
- "moveli r9, 9504\n"
- "shl16insli r9, r9, 15930\n"
- "shl16insli r9, r9, -27963\n"
- "shl16insli r9, r9, -6534\n"
- "moveli r12, -19781\n"
- "shl16insli r12, r12, 4441\n"
- "shl16insli r12, r12, -25151\n"
- "shl16insli r12, r12, -1099\n"
- "{ fdouble_pack2 r9, r9, r12 ; fnop }\n"
- "move %0, r9\n"
- "move %1, r9\n"
- "move %2, r12\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_fdouble_sub_flags_X0.c b/none/tests/tilegx/insn_test_fdouble_sub_flags_X0.c
deleted file mode 100644
index 750d218..0000000
--- a/none/tests/tilegx/insn_test_fdouble_sub_flags_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_fdouble_sub_flags_X0.c
-//op=87
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc7ac37053a461101, 0xf55855739bded624 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r1, -25048\n"
- "shl16insli r1, r1, -26391\n"
- "shl16insli r1, r1, -12179\n"
- "shl16insli r1, r1, -11222\n"
- "moveli r17, -6657\n"
- "shl16insli r17, r17, -8617\n"
- "shl16insli r17, r17, 10307\n"
- "shl16insli r17, r17, 8268\n"
- "moveli r42, -11842\n"
- "shl16insli r42, r42, 25434\n"
- "shl16insli r42, r42, -11416\n"
- "shl16insli r42, r42, -1334\n"
- "{ fdouble_sub_flags r1, r17, r42 ; fnop }\n"
- "move %0, r1\n"
- "move %1, r17\n"
- "move %2, r42\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_fdouble_unpack_max_X0.c b/none/tests/tilegx/insn_test_fdouble_unpack_max_X0.c
deleted file mode 100644
index 8272651..0000000
--- a/none/tests/tilegx/insn_test_fdouble_unpack_max_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_fdouble_unpack_max_X0.c
-//op=88
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xab961c7cdfcb76d0, 0xa9ccfec4f599744d };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r45, -7064\n"
- "shl16insli r45, r45, -20382\n"
- "shl16insli r45, r45, -30133\n"
- "shl16insli r45, r45, 11394\n"
- "moveli r5, 26677\n"
- "shl16insli r5, r5, 32003\n"
- "shl16insli r5, r5, 16745\n"
- "shl16insli r5, r5, -29543\n"
- "moveli r48, -17450\n"
- "shl16insli r48, r48, 24652\n"
- "shl16insli r48, r48, 22143\n"
- "shl16insli r48, r48, -2590\n"
- "{ fdouble_unpack_max r45, r5, r48 ; fnop }\n"
- "move %0, r45\n"
- "move %1, r5\n"
- "move %2, r48\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_fdouble_unpack_min_X0.c b/none/tests/tilegx/insn_test_fdouble_unpack_min_X0.c
deleted file mode 100644
index 921e604..0000000
--- a/none/tests/tilegx/insn_test_fdouble_unpack_min_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_fdouble_unpack_min_X0.c
-//op=89
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc7396f52c760a9d3, 0x4bf0ef1260a5545f };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r34, -29325\n"
- "shl16insli r34, r34, 23863\n"
- "shl16insli r34, r34, -25021\n"
- "shl16insli r34, r34, -17019\n"
- "moveli r35, 6975\n"
- "shl16insli r35, r35, -3872\n"
- "shl16insli r35, r35, 17466\n"
- "shl16insli r35, r35, 15329\n"
- "moveli r3, -10923\n"
- "shl16insli r3, r3, 19053\n"
- "shl16insli r3, r3, 1173\n"
- "shl16insli r3, r3, -17395\n"
- "{ fdouble_unpack_min r34, r35, r3 ; fnop }\n"
- "move %0, r34\n"
- "move %1, r35\n"
- "move %2, r3\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_flushwb_X1.c b/none/tests/tilegx/insn_test_flushwb_X1.c
deleted file mode 100644
index 89dd33b..0000000
--- a/none/tests/tilegx/insn_test_flushwb_X1.c
+++ /dev/null
@@ -1,24 +0,0 @@
-//file: _insn_test_flushwb_X1.c
-//op=100
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd85a80d7b6245b44, 0x4035b9e3ec473fc4 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "{ fnop ; flushwb }\n"
- );
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_fnop_X0.c b/none/tests/tilegx/insn_test_fnop_X0.c
deleted file mode 100644
index 7935cbc..0000000
--- a/none/tests/tilegx/insn_test_fnop_X0.c
+++ /dev/null
@@ -1,24 +0,0 @@
-//file: _insn_test_fnop_X0.c
-//op=101
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x1b58c82cfa9e7805, 0xeb546e8d18f5ab4c };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "{ fnop ; fnop }\n"
- );
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_fnop_X1.c b/none/tests/tilegx/insn_test_fnop_X1.c
deleted file mode 100644
index 21ac123..0000000
--- a/none/tests/tilegx/insn_test_fnop_X1.c
+++ /dev/null
@@ -1,24 +0,0 @@
-//file: _insn_test_fnop_X1.c
-//op=101
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x1b58c82cfa9e7805, 0xeb546e8d18f5ab4c };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "{ fnop ; fnop }\n"
- );
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_fnop_Y0.c b/none/tests/tilegx/insn_test_fnop_Y0.c
deleted file mode 100644
index 5c13e5b..0000000
--- a/none/tests/tilegx/insn_test_fnop_Y0.c
+++ /dev/null
@@ -1,24 +0,0 @@
-//file: _insn_test_fnop_Y0.c
-//op=101
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x1b58c82cfa9e7805, 0xeb546e8d18f5ab4c };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "{ fnop ; fnop ; ld r63, r54 }\n"
- );
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_fnop_Y1.c b/none/tests/tilegx/insn_test_fnop_Y1.c
deleted file mode 100644
index b9df4b5..0000000
--- a/none/tests/tilegx/insn_test_fnop_Y1.c
+++ /dev/null
@@ -1,24 +0,0 @@
-//file: _insn_test_fnop_Y1.c
-//op=101
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x1b58c82cfa9e7805, 0xeb546e8d18f5ab4c };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "{ fnop ; fnop ; ld r63, r54 }\n"
- );
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_fsingle_add1_X0.c b/none/tests/tilegx/insn_test_fsingle_add1_X0.c
deleted file mode 100644
index 9d933e7..0000000
--- a/none/tests/tilegx/insn_test_fsingle_add1_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_fsingle_add1_X0.c
-//op=102
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xf5f52759ddd87eb8, 0x8e9efd621a0271c0 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r21, -6121\n"
- "shl16insli r21, r21, -23936\n"
- "shl16insli r21, r21, -6621\n"
- "shl16insli r21, r21, -11778\n"
- "moveli r22, 24848\n"
- "shl16insli r22, r22, -12444\n"
- "shl16insli r22, r22, -9823\n"
- "shl16insli r22, r22, -18157\n"
- "moveli r3, -29477\n"
- "shl16insli r3, r3, 10834\n"
- "shl16insli r3, r3, -26605\n"
- "shl16insli r3, r3, 14005\n"
- "{ fsingle_add1 r21, r22, r3 ; fnop }\n"
- "move %0, r21\n"
- "move %1, r22\n"
- "move %2, r3\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_fsingle_addsub2_X0.c b/none/tests/tilegx/insn_test_fsingle_addsub2_X0.c
deleted file mode 100644
index 24ba0d2..0000000
--- a/none/tests/tilegx/insn_test_fsingle_addsub2_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_fsingle_addsub2_X0.c
-//op=103
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x2c24dd020e9fa33f, 0xc279be840ee86dea };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r16, -8392\n"
- "shl16insli r16, r16, -23005\n"
- "shl16insli r16, r16, -28857\n"
- "shl16insli r16, r16, -4517\n"
- "moveli r18, -23753\n"
- "shl16insli r18, r18, -24851\n"
- "shl16insli r18, r18, 4221\n"
- "shl16insli r18, r18, 16539\n"
- "moveli r13, -2884\n"
- "shl16insli r13, r13, 28785\n"
- "shl16insli r13, r13, 7136\n"
- "shl16insli r13, r13, 32281\n"
- "{ fsingle_addsub2 r16, r18, r13 ; fnop }\n"
- "move %0, r16\n"
- "move %1, r18\n"
- "move %2, r13\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_fsingle_mul1_X0.c b/none/tests/tilegx/insn_test_fsingle_mul1_X0.c
deleted file mode 100644
index 2f7b6aa..0000000
--- a/none/tests/tilegx/insn_test_fsingle_mul1_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_fsingle_mul1_X0.c
-//op=104
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xe22608b00f39a4c5, 0x9276743f21019b4e };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r32, -27396\n"
- "shl16insli r32, r32, -8056\n"
- "shl16insli r32, r32, 23879\n"
- "shl16insli r32, r32, 14131\n"
- "moveli r4, 4550\n"
- "shl16insli r4, r4, 29355\n"
- "shl16insli r4, r4, 30941\n"
- "shl16insli r4, r4, 29755\n"
- "moveli r38, -21466\n"
- "shl16insli r38, r38, 11354\n"
- "shl16insli r38, r38, -10374\n"
- "shl16insli r38, r38, 87\n"
- "{ fsingle_mul1 r32, r4, r38 ; fnop }\n"
- "move %0, r32\n"
- "move %1, r4\n"
- "move %2, r38\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_fsingle_mul2_X0.c b/none/tests/tilegx/insn_test_fsingle_mul2_X0.c
deleted file mode 100644
index 72aa38d..0000000
--- a/none/tests/tilegx/insn_test_fsingle_mul2_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_fsingle_mul2_X0.c
-//op=105
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x4419397566d0f360, 0xebc915599850d350 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r36, 15980\n"
- "shl16insli r36, r36, 6185\n"
- "shl16insli r36, r36, -3610\n"
- "shl16insli r36, r36, -10263\n"
- "moveli r48, 11819\n"
- "shl16insli r48, r48, -3940\n"
- "shl16insli r48, r48, 25912\n"
- "shl16insli r48, r48, 22355\n"
- "moveli r9, -832\n"
- "shl16insli r9, r9, -16346\n"
- "shl16insli r9, r9, -24487\n"
- "shl16insli r9, r9, 31724\n"
- "{ fsingle_mul2 r36, r48, r9 ; fnop }\n"
- "move %0, r36\n"
- "move %1, r48\n"
- "move %2, r9\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_fsingle_pack1_X0.c b/none/tests/tilegx/insn_test_fsingle_pack1_X0.c
deleted file mode 100644
index 59272f9..0000000
--- a/none/tests/tilegx/insn_test_fsingle_pack1_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_fsingle_pack1_X0.c
-//op=106
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x988b16de50a53a0a, 0x5fced320ec74ecd8 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r46, -30106\n"
- "shl16insli r46, r46, 24510\n"
- "shl16insli r46, r46, -6618\n"
- "shl16insli r46, r46, 11033\n"
- "moveli r26, -11405\n"
- "shl16insli r26, r26, -6947\n"
- "shl16insli r26, r26, 19133\n"
- "shl16insli r26, r26, -19900\n"
- "{ fsingle_pack1 r46, r26 ; fnop }\n"
- "move %0, r46\n"
- "move %1, r26\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_fsingle_pack1_Y0.c b/none/tests/tilegx/insn_test_fsingle_pack1_Y0.c
deleted file mode 100644
index d85d6c6..0000000
--- a/none/tests/tilegx/insn_test_fsingle_pack1_Y0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_fsingle_pack1_Y0.c
-//op=106
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x988b16de50a53a0a, 0x5fced320ec74ecd8 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r46, -30106\n"
- "shl16insli r46, r46, 24510\n"
- "shl16insli r46, r46, -6618\n"
- "shl16insli r46, r46, 11033\n"
- "moveli r26, -11405\n"
- "shl16insli r26, r26, -6947\n"
- "shl16insli r26, r26, 19133\n"
- "shl16insli r26, r26, -19900\n"
- "{ fsingle_pack1 r46, r26 ; fnop ; ld r63, r54 }\n"
- "move %0, r46\n"
- "move %1, r26\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_fsingle_pack2_X0.c b/none/tests/tilegx/insn_test_fsingle_pack2_X0.c
deleted file mode 100644
index 6d2b3a4..0000000
--- a/none/tests/tilegx/insn_test_fsingle_pack2_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_fsingle_pack2_X0.c
-//op=107
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x4463a2383032e2f2, 0x4a32a55c75498ba7 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r25, 27454\n"
- "shl16insli r25, r25, -25613\n"
- "shl16insli r25, r25, -25678\n"
- "shl16insli r25, r25, -280\n"
- "moveli r33, -5991\n"
- "shl16insli r33, r33, 9025\n"
- "shl16insli r33, r33, -5431\n"
- "shl16insli r33, r33, 19958\n"
- "moveli r28, 10868\n"
- "shl16insli r28, r28, 28978\n"
- "shl16insli r28, r28, -7157\n"
- "shl16insli r28, r28, 19796\n"
- "{ fsingle_pack2 r25, r33, r28 ; fnop }\n"
- "move %0, r25\n"
- "move %1, r33\n"
- "move %2, r28\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_fsingle_sub1_X0.c b/none/tests/tilegx/insn_test_fsingle_sub1_X0.c
deleted file mode 100644
index 75823d8..0000000
--- a/none/tests/tilegx/insn_test_fsingle_sub1_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_fsingle_sub1_X0.c
-//op=108
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x8d6611e2e0188d4d, 0xc051e6bca12058e0 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r18, -32379\n"
- "shl16insli r18, r18, -17242\n"
- "shl16insli r18, r18, -8818\n"
- "shl16insli r18, r18, 7579\n"
- "moveli r22, 9145\n"
- "shl16insli r22, r22, 16129\n"
- "shl16insli r22, r22, -28988\n"
- "shl16insli r22, r22, -28265\n"
- "moveli r4, 23316\n"
- "shl16insli r4, r4, 27509\n"
- "shl16insli r4, r4, 21179\n"
- "shl16insli r4, r4, 13422\n"
- "{ fsingle_sub1 r18, r22, r4 ; fnop }\n"
- "move %0, r18\n"
- "move %1, r22\n"
- "move %2, r4\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_icoh_X1.c b/none/tests/tilegx/insn_test_icoh_X1.c
deleted file mode 100644
index 2275236..0000000
--- a/none/tests/tilegx/insn_test_icoh_X1.c
+++ /dev/null
@@ -1,30 +0,0 @@
-//file: _insn_test_icoh_X1.c
-//op=109
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x1fe3ff849620d963, 0x911b4b9f0928dd1b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r31, 15613\n"
- "shl16insli r31, r31, -26390\n"
- "shl16insli r31, r31, -13320\n"
- "shl16insli r31, r31, 11345\n"
- "{ fnop ; icoh r31 }\n"
- "move %0, r31\n"
- :"=r"(a[0]));
- printf("%016lx\n", a[0]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_j_X1.c b/none/tests/tilegx/insn_test_j_X1.c
deleted file mode 100644
index 285ac1f..0000000
--- a/none/tests/tilegx/insn_test_j_X1.c
+++ /dev/null
@@ -1,24 +0,0 @@
-//file: _insn_test_j_X1.c
-//op=113
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x721ddf3c2c82992f, 0xdc2f92eb642eb1d1 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "j %0\n"
- :: "i"(func_exit));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_jal_X1.c b/none/tests/tilegx/insn_test_jal_X1.c
deleted file mode 100644
index 0a6ce83..0000000
--- a/none/tests/tilegx/insn_test_jal_X1.c
+++ /dev/null
@@ -1,24 +0,0 @@
-//file: _insn_test_jal_X1.c
-//op=114
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x97c50c1862f77907, 0xd4017cfe9fa6ebaa };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "jal %0\n"
- :: "i"(func_call));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_jalr_X1.c b/none/tests/tilegx/insn_test_jalr_X1.c
deleted file mode 100644
index fdde6c4..0000000
--- a/none/tests/tilegx/insn_test_jalr_X1.c
+++ /dev/null
@@ -1,24 +0,0 @@
-//file: _insn_test_jalr_X1.c
-//op=115
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x4826371b074e6849, 0xf512a65b934c3280 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "jalr %0\n"
- :: "r"(func_call));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_jalr_Y1.c b/none/tests/tilegx/insn_test_jalr_Y1.c
deleted file mode 100644
index c6a66a3..0000000
--- a/none/tests/tilegx/insn_test_jalr_Y1.c
+++ /dev/null
@@ -1,24 +0,0 @@
-//file: _insn_test_jalr_Y1.c
-//op=115
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x4826371b074e6849, 0xf512a65b934c3280 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "jalr %0\n"
- :: "r"(func_call));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_jalrp_X1.c b/none/tests/tilegx/insn_test_jalrp_X1.c
deleted file mode 100644
index d53cbfb..0000000
--- a/none/tests/tilegx/insn_test_jalrp_X1.c
+++ /dev/null
@@ -1,24 +0,0 @@
-//file: _insn_test_jalrp_X1.c
-//op=116
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xcf14c16c8fe6d80a, 0x9a968c4e2652e151 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "jalrp %0\n"
- :: "r"(func_call));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_jalrp_Y1.c b/none/tests/tilegx/insn_test_jalrp_Y1.c
deleted file mode 100644
index 8ae4c84..0000000
--- a/none/tests/tilegx/insn_test_jalrp_Y1.c
+++ /dev/null
@@ -1,24 +0,0 @@
-//file: _insn_test_jalrp_Y1.c
-//op=116
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xcf14c16c8fe6d80a, 0x9a968c4e2652e151 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "jalrp %0\n"
- :: "r"(func_call));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_jr_X1.c b/none/tests/tilegx/insn_test_jr_X1.c
deleted file mode 100644
index ecba26f..0000000
--- a/none/tests/tilegx/insn_test_jr_X1.c
+++ /dev/null
@@ -1,24 +0,0 @@
-//file: _insn_test_jr_X1.c
-//op=117
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x5468060e74455729, 0x796b977f2174befa };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "jr %0\n"
- :: "r"(func_exit));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_jr_Y1.c b/none/tests/tilegx/insn_test_jr_Y1.c
deleted file mode 100644
index aace76b..0000000
--- a/none/tests/tilegx/insn_test_jr_Y1.c
+++ /dev/null
@@ -1,24 +0,0 @@
-//file: _insn_test_jr_Y1.c
-//op=117
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x5468060e74455729, 0x796b977f2174befa };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "jr %0\n"
- :: "r"(func_exit));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_jrp_X1.c b/none/tests/tilegx/insn_test_jrp_X1.c
deleted file mode 100644
index 38d4b9f..0000000
--- a/none/tests/tilegx/insn_test_jrp_X1.c
+++ /dev/null
@@ -1,24 +0,0 @@
-//file: _insn_test_jrp_X1.c
-//op=118
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd398d9dcfc90866b, 0xdfe94ab09fee22a5 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "jrp %0\n"
- :: "r"(func_exit));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_jrp_Y1.c b/none/tests/tilegx/insn_test_jrp_Y1.c
deleted file mode 100644
index f9af56d..0000000
--- a/none/tests/tilegx/insn_test_jrp_Y1.c
+++ /dev/null
@@ -1,24 +0,0 @@
-//file: _insn_test_jrp_Y1.c
-//op=118
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd398d9dcfc90866b, 0xdfe94ab09fee22a5 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "jrp %0\n"
- :: "r"(func_exit));
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ld1s_X1.c b/none/tests/tilegx/insn_test_ld1s_X1.c
deleted file mode 100644
index 8c60563..0000000
--- a/none/tests/tilegx/insn_test_ld1s_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ld1s_X1.c
-//op=120
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xfd529a461f919c3b, 0xa702a184ea8a31f7 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r38, -25406\n"
- "shl16insli r38, r38, 4116\n"
- "shl16insli r38, r38, 26061\n"
- "shl16insli r38, r38, -21556\n"
- "moveli r25, 9517\n"
- "shl16insli r25, r25, -14743\n"
- "shl16insli r25, r25, 28886\n"
- "shl16insli r25, r25, 23646\n"
- "move r25, %2\n"
- "{ fnop ; ld1s r38, r25 }\n"
- "move %0, r38\n"
- "move %1, r25\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ld1s_Y2.c b/none/tests/tilegx/insn_test_ld1s_Y2.c
deleted file mode 100644
index 3cb93b0..0000000
--- a/none/tests/tilegx/insn_test_ld1s_Y2.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ld1s_Y2.c
-//op=120
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xfd529a461f919c3b, 0xa702a184ea8a31f7 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r11, -25406\n"
- "shl16insli r11, r11, 4116\n"
- "shl16insli r11, r11, 26061\n"
- "shl16insli r11, r11, -21556\n"
- "moveli r20, 9517\n"
- "shl16insli r20, r20, -14743\n"
- "shl16insli r20, r20, 28886\n"
- "shl16insli r20, r20, 23646\n"
- "move r20, %2\n"
- "{ fnop ; fnop ; ld1s r11, r20 }\n"
- "move %0, r11\n"
- "move %1, r20\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ld1s_add_X1.c b/none/tests/tilegx/insn_test_ld1s_add_X1.c
deleted file mode 100644
index 1a07d59..0000000
--- a/none/tests/tilegx/insn_test_ld1s_add_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ld1s_add_X1.c
-//op=121
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xbf944e471ed68a09, 0xc750773165e75c2a };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r11, 2389\n"
- "shl16insli r11, r11, -8821\n"
- "shl16insli r11, r11, -19715\n"
- "shl16insli r11, r11, 21029\n"
- "moveli r19, 8794\n"
- "shl16insli r19, r19, -28834\n"
- "shl16insli r19, r19, 6092\n"
- "shl16insli r19, r19, 15960\n"
- "move r19, %2\n"
- "{ fnop ; ld1s_add r11, r19, -82 }\n"
- "move %0, r11\n"
- "move %1, r19\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ld1u_X1.c b/none/tests/tilegx/insn_test_ld1u_X1.c
deleted file mode 100644
index 457af2e..0000000
--- a/none/tests/tilegx/insn_test_ld1u_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ld1u_X1.c
-//op=122
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xae053c723a6c8e37, 0x26836d784e440ab7 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r19, 8260\n"
- "shl16insli r19, r19, -7206\n"
- "shl16insli r19, r19, -24567\n"
- "shl16insli r19, r19, -8840\n"
- "moveli r23, -18757\n"
- "shl16insli r23, r23, 26178\n"
- "shl16insli r23, r23, 32618\n"
- "shl16insli r23, r23, 22067\n"
- "move r23, %2\n"
- "{ fnop ; ld1u r19, r23 }\n"
- "move %0, r19\n"
- "move %1, r23\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ld1u_Y2.c b/none/tests/tilegx/insn_test_ld1u_Y2.c
deleted file mode 100644
index 9159214..0000000
--- a/none/tests/tilegx/insn_test_ld1u_Y2.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ld1u_Y2.c
-//op=122
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xae053c723a6c8e37, 0x26836d784e440ab7 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r35, 8260\n"
- "shl16insli r35, r35, -7206\n"
- "shl16insli r35, r35, -24567\n"
- "shl16insli r35, r35, -8840\n"
- "moveli r9, -18757\n"
- "shl16insli r9, r9, 26178\n"
- "shl16insli r9, r9, 32618\n"
- "shl16insli r9, r9, 22067\n"
- "move r9, %2\n"
- "{ fnop ; fnop ; ld1u r35, r9 }\n"
- "move %0, r35\n"
- "move %1, r9\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ld1u_add_X1.c b/none/tests/tilegx/insn_test_ld1u_add_X1.c
deleted file mode 100644
index e8f754a..0000000
--- a/none/tests/tilegx/insn_test_ld1u_add_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ld1u_add_X1.c
-//op=123
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x71782df005cc3618, 0x98e72847e6d80b39 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r33, 13116\n"
- "shl16insli r33, r33, 11172\n"
- "shl16insli r33, r33, -2564\n"
- "shl16insli r33, r33, 1912\n"
- "moveli r32, 28219\n"
- "shl16insli r32, r32, -17492\n"
- "shl16insli r32, r32, -19727\n"
- "shl16insli r32, r32, 7684\n"
- "move r32, %2\n"
- "{ fnop ; ld1u_add r33, r32, -75 }\n"
- "move %0, r33\n"
- "move %1, r32\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ld2s_X1.c b/none/tests/tilegx/insn_test_ld2s_X1.c
deleted file mode 100644
index 4f19ed7..0000000
--- a/none/tests/tilegx/insn_test_ld2s_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ld2s_X1.c
-//op=124
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x6d228375c43e27fe, 0x6a0cb98ab56a8e60 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r18, -2019\n"
- "shl16insli r18, r18, 30837\n"
- "shl16insli r18, r18, -1194\n"
- "shl16insli r18, r18, -12623\n"
- "moveli r46, -17868\n"
- "shl16insli r46, r46, -15637\n"
- "shl16insli r46, r46, -21854\n"
- "shl16insli r46, r46, 31769\n"
- "move r46, %2\n"
- "{ fnop ; ld2s r18, r46 }\n"
- "move %0, r18\n"
- "move %1, r46\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ld2s_Y2.c b/none/tests/tilegx/insn_test_ld2s_Y2.c
deleted file mode 100644
index 0759176..0000000
--- a/none/tests/tilegx/insn_test_ld2s_Y2.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ld2s_Y2.c
-//op=124
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x6d228375c43e27fe, 0x6a0cb98ab56a8e60 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r43, -2019\n"
- "shl16insli r43, r43, 30837\n"
- "shl16insli r43, r43, -1194\n"
- "shl16insli r43, r43, -12623\n"
- "moveli r41, -17868\n"
- "shl16insli r41, r41, -15637\n"
- "shl16insli r41, r41, -21854\n"
- "shl16insli r41, r41, 31769\n"
- "move r41, %2\n"
- "{ fnop ; fnop ; ld2s r43, r41 }\n"
- "move %0, r43\n"
- "move %1, r41\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ld2u_X1.c b/none/tests/tilegx/insn_test_ld2u_X1.c
deleted file mode 100644
index 9983db1..0000000
--- a/none/tests/tilegx/insn_test_ld2u_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ld2u_X1.c
-//op=126
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xb50b19b244ac7eb4, 0x11b59d6276787136 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r12, -12252\n"
- "shl16insli r12, r12, 5860\n"
- "shl16insli r12, r12, 15129\n"
- "shl16insli r12, r12, -15375\n"
- "moveli r47, -11895\n"
- "shl16insli r47, r47, 21718\n"
- "shl16insli r47, r47, -14088\n"
- "shl16insli r47, r47, -5322\n"
- "move r47, %2\n"
- "{ fnop ; ld2u r12, r47 }\n"
- "move %0, r12\n"
- "move %1, r47\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ld2u_Y2.c b/none/tests/tilegx/insn_test_ld2u_Y2.c
deleted file mode 100644
index 9396a0d..0000000
--- a/none/tests/tilegx/insn_test_ld2u_Y2.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ld2u_Y2.c
-//op=126
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xb50b19b244ac7eb4, 0x11b59d6276787136 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r42, -12252\n"
- "shl16insli r42, r42, 5860\n"
- "shl16insli r42, r42, 15129\n"
- "shl16insli r42, r42, -15375\n"
- "moveli r4, -11895\n"
- "shl16insli r4, r4, 21718\n"
- "shl16insli r4, r4, -14088\n"
- "shl16insli r4, r4, -5322\n"
- "move r4, %2\n"
- "{ fnop ; fnop ; ld2u r42, r4 }\n"
- "move %0, r42\n"
- "move %1, r4\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ld4s_X1.c b/none/tests/tilegx/insn_test_ld4s_X1.c
deleted file mode 100644
index 36d7f9e..0000000
--- a/none/tests/tilegx/insn_test_ld4s_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ld4s_X1.c
-//op=128
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xcef60e4c85b01644, 0x411d3fc3fc916064 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r15, -5570\n"
- "shl16insli r15, r15, -29385\n"
- "shl16insli r15, r15, -18769\n"
- "shl16insli r15, r15, -2309\n"
- "moveli r48, -28670\n"
- "shl16insli r48, r48, -6265\n"
- "shl16insli r48, r48, 15425\n"
- "shl16insli r48, r48, 17326\n"
- "move r48, %2\n"
- "{ fnop ; ld4s r15, r48 }\n"
- "move %0, r15\n"
- "move %1, r48\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ld4s_add_X1.c b/none/tests/tilegx/insn_test_ld4s_add_X1.c
deleted file mode 100644
index 7c05420..0000000
--- a/none/tests/tilegx/insn_test_ld4s_add_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ld4s_add_X1.c
-//op=129
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x3ab13aa81a1f8e6, 0xa0f4db3555dcd53 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r7, 9504\n"
- "shl16insli r7, r7, 15930\n"
- "shl16insli r7, r7, -27963\n"
- "shl16insli r7, r7, -6534\n"
- "moveli r33, 7720\n"
- "shl16insli r33, r33, -13533\n"
- "shl16insli r33, r33, 10333\n"
- "shl16insli r33, r33, -5169\n"
- "move r33, %2\n"
- "{ fnop ; ld4s_add r7, r33, 106 }\n"
- "move %0, r7\n"
- "move %1, r33\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ld4u_X1.c b/none/tests/tilegx/insn_test_ld4u_X1.c
deleted file mode 100644
index 2f60d93..0000000
--- a/none/tests/tilegx/insn_test_ld4u_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ld4u_X1.c
-//op=130
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xb002a7dc1c538d17, 0x553c16d3559d1cee };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r46, 20445\n"
- "shl16insli r46, r46, -17976\n"
- "shl16insli r46, r46, -29438\n"
- "shl16insli r46, r46, -12912\n"
- "moveli r2, 6570\n"
- "shl16insli r2, r2, -30096\n"
- "shl16insli r2, r2, -3418\n"
- "shl16insli r2, r2, 9405\n"
- "move r2, %2\n"
- "{ fnop ; ld4u r46, r2 }\n"
- "move %0, r46\n"
- "move %1, r2\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ld4u_Y2.c b/none/tests/tilegx/insn_test_ld4u_Y2.c
deleted file mode 100644
index 847bf1d..0000000
--- a/none/tests/tilegx/insn_test_ld4u_Y2.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ld4u_Y2.c
-//op=130
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xb002a7dc1c538d17, 0x553c16d3559d1cee };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r42, 20445\n"
- "shl16insli r42, r42, -17976\n"
- "shl16insli r42, r42, -29438\n"
- "shl16insli r42, r42, -12912\n"
- "moveli r15, 6570\n"
- "shl16insli r15, r15, -30096\n"
- "shl16insli r15, r15, -3418\n"
- "shl16insli r15, r15, 9405\n"
- "move r15, %2\n"
- "{ fnop ; fnop ; ld4u r42, r15 }\n"
- "move %0, r42\n"
- "move %1, r15\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ld4u_add_X1.c b/none/tests/tilegx/insn_test_ld4u_add_X1.c
deleted file mode 100644
index d4fabf7..0000000
--- a/none/tests/tilegx/insn_test_ld4u_add_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ld4u_add_X1.c
-//op=131
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x7f88e5945a40e9ee, 0xe76171c85a64faf7 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r31, -14377\n"
- "shl16insli r31, r31, -7231\n"
- "shl16insli r31, r31, -29806\n"
- "shl16insli r31, r31, 3514\n"
- "moveli r50, 16073\n"
- "shl16insli r50, r50, -20366\n"
- "shl16insli r50, r50, -10414\n"
- "shl16insli r50, r50, 4096\n"
- "move r50, %2\n"
- "{ fnop ; ld4u_add r31, r50, -16 }\n"
- "move %0, r31\n"
- "move %1, r50\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ld_X1.c b/none/tests/tilegx/insn_test_ld_X1.c
deleted file mode 100644
index 830f1fa..0000000
--- a/none/tests/tilegx/insn_test_ld_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ld_X1.c
-//op=119
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xdd853a2377c4c1cd, 0x7f7658d7010e1ce1 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r42, -17282\n"
- "shl16insli r42, r42, 6317\n"
- "shl16insli r42, r42, -15116\n"
- "shl16insli r42, r42, -17196\n"
- "moveli r26, -9435\n"
- "shl16insli r26, r26, 12124\n"
- "shl16insli r26, r26, -6695\n"
- "shl16insli r26, r26, 1712\n"
- "move r26, %2\n"
- "{ fnop ; ld r42, r26 }\n"
- "move %0, r42\n"
- "move %1, r26\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ld_Y2.c b/none/tests/tilegx/insn_test_ld_Y2.c
deleted file mode 100644
index e127f07..0000000
--- a/none/tests/tilegx/insn_test_ld_Y2.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ld_Y2.c
-//op=119
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xdd853a2377c4c1cd, 0x7f7658d7010e1ce1 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r19, -17282\n"
- "shl16insli r19, r19, 6317\n"
- "shl16insli r19, r19, -15116\n"
- "shl16insli r19, r19, -17196\n"
- "moveli r34, -9435\n"
- "shl16insli r34, r34, 12124\n"
- "shl16insli r34, r34, -6695\n"
- "shl16insli r34, r34, 1712\n"
- "move r34, %2\n"
- "{ fnop ; fnop ; ld r19, r34 }\n"
- "move %0, r19\n"
- "move %1, r34\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ld_add_X1.c b/none/tests/tilegx/insn_test_ld_add_X1.c
deleted file mode 100644
index 1d32c97..0000000
--- a/none/tests/tilegx/insn_test_ld_add_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ld_add_X1.c
-//op=132
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x3076e248a1b03309, 0x386e67ed7b089fc9 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r27, 26677\n"
- "shl16insli r27, r27, 32003\n"
- "shl16insli r27, r27, 16745\n"
- "shl16insli r27, r27, -29543\n"
- "moveli r39, 27432\n"
- "shl16insli r39, r39, -22439\n"
- "shl16insli r39, r39, 15226\n"
- "shl16insli r39, r39, -19568\n"
- "move r39, %2\n"
- "{ fnop ; ld_add r27, r39, 118 }\n"
- "move %0, r27\n"
- "move %1, r39\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ldna_X1.c b/none/tests/tilegx/insn_test_ldna_X1.c
deleted file mode 100644
index 8be9693..0000000
--- a/none/tests/tilegx/insn_test_ldna_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ldna_X1.c
-//op=133
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xe99ff6bbb270ebf, 0xc708d15463e8c0ec };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r32, -30640\n"
- "shl16insli r32, r32, 31848\n"
- "shl16insli r32, r32, 11423\n"
- "shl16insli r32, r32, -20012\n"
- "moveli r16, -24423\n"
- "shl16insli r16, r16, -14237\n"
- "shl16insli r16, r16, 18232\n"
- "shl16insli r16, r16, -32601\n"
- "move r16, %2\n"
- "{ fnop ; ldna r32, r16 }\n"
- "move %0, r32\n"
- "move %1, r16\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ldna_add_X1.c b/none/tests/tilegx/insn_test_ldna_add_X1.c
deleted file mode 100644
index e7741f2..0000000
--- a/none/tests/tilegx/insn_test_ldna_add_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ldna_add_X1.c
-//op=134
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x2f3ac3e001892397, 0x20a35a283e09bcf3 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r23, 30081\n"
- "shl16insli r23, r23, 2888\n"
- "shl16insli r23, r23, 17535\n"
- "shl16insli r23, r23, -29480\n"
- "moveli r20, -32745\n"
- "shl16insli r20, r20, -15929\n"
- "shl16insli r20, r20, -787\n"
- "shl16insli r20, r20, 26982\n"
- "move r20, %2\n"
- "{ fnop ; ldna_add r23, r20, 11 }\n"
- "move %0, r23\n"
- "move %1, r20\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ldnt1s_X1.c b/none/tests/tilegx/insn_test_ldnt1s_X1.c
deleted file mode 100644
index 99d7d3c..0000000
--- a/none/tests/tilegx/insn_test_ldnt1s_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ldnt1s_X1.c
-//op=136
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x25733d8b5dc477b4, 0x820d15cd622148e4 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r49, 25551\n"
- "shl16insli r49, r49, 28722\n"
- "shl16insli r49, r49, -26847\n"
- "shl16insli r49, r49, 5345\n"
- "moveli r33, -29477\n"
- "shl16insli r33, r33, 10834\n"
- "shl16insli r33, r33, -26605\n"
- "shl16insli r33, r33, 14005\n"
- "move r33, %2\n"
- "{ fnop ; ldnt1s r49, r33 }\n"
- "move %0, r49\n"
- "move %1, r33\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ldnt1s_add_X1.c b/none/tests/tilegx/insn_test_ldnt1s_add_X1.c
deleted file mode 100644
index fbd9b49..0000000
--- a/none/tests/tilegx/insn_test_ldnt1s_add_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ldnt1s_add_X1.c
-//op=137
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xe11d6a52db1557dd, 0x601a65b89d0791ab };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r46, -25023\n"
- "shl16insli r46, r46, 14244\n"
- "shl16insli r46, r46, -1027\n"
- "shl16insli r46, r46, 6652\n"
- "moveli r19, -22946\n"
- "shl16insli r19, r19, -5784\n"
- "shl16insli r19, r19, 19718\n"
- "shl16insli r19, r19, -7802\n"
- "move r19, %2\n"
- "{ fnop ; ldnt1s_add r46, r19, -111 }\n"
- "move %0, r46\n"
- "move %1, r19\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ldnt1u_X1.c b/none/tests/tilegx/insn_test_ldnt1u_X1.c
deleted file mode 100644
index 688ceb8..0000000
--- a/none/tests/tilegx/insn_test_ldnt1u_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ldnt1u_X1.c
-//op=138
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x778f2f6f17d9003b, 0x4070076dbab015ca };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r1, 8165\n"
- "shl16insli r1, r1, 18793\n"
- "shl16insli r1, r1, -22214\n"
- "shl16insli r1, r1, 5498\n"
- "moveli r10, 31115\n"
- "shl16insli r10, r10, -26645\n"
- "shl16insli r10, r10, -28059\n"
- "shl16insli r10, r10, -26401\n"
- "move r10, %2\n"
- "{ fnop ; ldnt1u r1, r10 }\n"
- "move %0, r1\n"
- "move %1, r10\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ldnt1u_add_X1.c b/none/tests/tilegx/insn_test_ldnt1u_add_X1.c
deleted file mode 100644
index 30d4d72..0000000
--- a/none/tests/tilegx/insn_test_ldnt1u_add_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ldnt1u_add_X1.c
-//op=139
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xab1fe60bd5f86c0d, 0xd3191cdcf9681de6 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r32, -30537\n"
- "shl16insli r32, r32, 27764\n"
- "shl16insli r32, r32, 16739\n"
- "shl16insli r32, r32, 8330\n"
- "moveli r3, -26924\n"
- "shl16insli r3, r3, -3594\n"
- "shl16insli r3, r3, -24949\n"
- "shl16insli r3, r3, 31134\n"
- "move r3, %2\n"
- "{ fnop ; ldnt1u_add r32, r3, 90 }\n"
- "move %0, r32\n"
- "move %1, r3\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ldnt2s_X1.c b/none/tests/tilegx/insn_test_ldnt2s_X1.c
deleted file mode 100644
index e7b7597..0000000
--- a/none/tests/tilegx/insn_test_ldnt2s_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ldnt2s_X1.c
-//op=140
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x455f86368ee6a1bf, 0x3f45dbe8d3bddf1e };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r32, 26063\n"
- "shl16insli r32, r32, 27563\n"
- "shl16insli r32, r32, 24059\n"
- "shl16insli r32, r32, -1753\n"
- "moveli r8, -832\n"
- "shl16insli r8, r8, -16346\n"
- "shl16insli r8, r8, -24487\n"
- "shl16insli r8, r8, 31724\n"
- "move r8, %2\n"
- "{ fnop ; ldnt2s r32, r8 }\n"
- "move %0, r32\n"
- "move %1, r8\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ldnt2s_add_X1.c b/none/tests/tilegx/insn_test_ldnt2s_add_X1.c
deleted file mode 100644
index ee07ed4..0000000
--- a/none/tests/tilegx/insn_test_ldnt2s_add_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ldnt2s_add_X1.c
-//op=141
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x818b8dda9648095a, 0xa1c9172b9a0d1dac };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r6, 29106\n"
- "shl16insli r6, r6, 15753\n"
- "shl16insli r6, r6, -26093\n"
- "shl16insli r6, r6, -30730\n"
- "moveli r14, -23898\n"
- "shl16insli r14, r14, 12060\n"
- "shl16insli r14, r14, 9181\n"
- "shl16insli r14, r14, 3478\n"
- "move r14, %2\n"
- "{ fnop ; ldnt2s_add r6, r14, 107 }\n"
- "move %0, r6\n"
- "move %1, r14\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ldnt2u_add_X1.c b/none/tests/tilegx/insn_test_ldnt2u_add_X1.c
deleted file mode 100644
index a67b144..0000000
--- a/none/tests/tilegx/insn_test_ldnt2u_add_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ldnt2u_add_X1.c
-//op=143
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x59fad680489ec628, 0xc20f490a26161c01 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r30, 16120\n"
- "shl16insli r30, r30, -22959\n"
- "shl16insli r30, r30, 22252\n"
- "shl16insli r30, r30, 172\n"
- "moveli r2, -28491\n"
- "shl16insli r2, r2, 5201\n"
- "shl16insli r2, r2, 4373\n"
- "shl16insli r2, r2, 26208\n"
- "move r2, %2\n"
- "{ fnop ; ldnt2u_add r30, r2, -25 }\n"
- "move %0, r30\n"
- "move %1, r2\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ldnt4s_X1.c b/none/tests/tilegx/insn_test_ldnt4s_X1.c
deleted file mode 100644
index 9e8723c..0000000
--- a/none/tests/tilegx/insn_test_ldnt4s_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ldnt4s_X1.c
-//op=144
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xfa50dcf0b044d59a, 0x48fd1654a7e669f7 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r41, 26010\n"
- "shl16insli r41, r41, -10170\n"
- "shl16insli r41, r41, -10239\n"
- "shl16insli r41, r41, -24168\n"
- "moveli r30, 23316\n"
- "shl16insli r30, r30, 27509\n"
- "shl16insli r30, r30, 21179\n"
- "shl16insli r30, r30, 13422\n"
- "move r30, %2\n"
- "{ fnop ; ldnt4s r41, r30 }\n"
- "move %0, r41\n"
- "move %1, r30\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ldnt4s_add_X1.c b/none/tests/tilegx/insn_test_ldnt4s_add_X1.c
deleted file mode 100644
index 4ee1a41..0000000
--- a/none/tests/tilegx/insn_test_ldnt4s_add_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ldnt4s_add_X1.c
-//op=145
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd6233f383d6fcac4, 0xa3f745ffc94270b2 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r17, 20154\n"
- "shl16insli r17, r17, -1171\n"
- "shl16insli r17, r17, 18338\n"
- "shl16insli r17, r17, -23205\n"
- "moveli r32, -21605\n"
- "shl16insli r32, r32, -21137\n"
- "shl16insli r32, r32, 22949\n"
- "shl16insli r32, r32, -13067\n"
- "move r32, %2\n"
- "{ fnop ; ldnt4s_add r17, r32, 77 }\n"
- "move %0, r17\n"
- "move %1, r32\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ldnt4u_X1.c b/none/tests/tilegx/insn_test_ldnt4u_X1.c
deleted file mode 100644
index 9c2fc26..0000000
--- a/none/tests/tilegx/insn_test_ldnt4u_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ldnt4u_X1.c
-//op=146
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x52c49809e5465b06, 0xea70c8b3ffd336c3 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r14, 27619\n"
- "shl16insli r14, r14, 17289\n"
- "shl16insli r14, r14, 12105\n"
- "shl16insli r14, r14, -30968\n"
- "moveli r34, -1549\n"
- "shl16insli r34, r34, 17842\n"
- "shl16insli r34, r34, 24501\n"
- "shl16insli r34, r34, -29822\n"
- "move r34, %2\n"
- "{ fnop ; ldnt4u r14, r34 }\n"
- "move %0, r14\n"
- "move %1, r34\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ldnt4u_add_X1.c b/none/tests/tilegx/insn_test_ldnt4u_add_X1.c
deleted file mode 100644
index 72e70cd..0000000
--- a/none/tests/tilegx/insn_test_ldnt4u_add_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ldnt4u_add_X1.c
-//op=147
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x5d9ea0967d2b4507, 0x65938abe343c4eed };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r19, -26655\n"
- "shl16insli r19, r19, 14881\n"
- "shl16insli r19, r19, 22810\n"
- "shl16insli r19, r19, 12324\n"
- "moveli r9, 10449\n"
- "shl16insli r9, r9, -23499\n"
- "shl16insli r9, r9, -25395\n"
- "shl16insli r9, r9, 17474\n"
- "move r9, %2\n"
- "{ fnop ; ldnt4u_add r19, r9, -95 }\n"
- "move %0, r19\n"
- "move %1, r9\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ldnt_X1.c b/none/tests/tilegx/insn_test_ldnt_X1.c
deleted file mode 100644
index d8ca7c9..0000000
--- a/none/tests/tilegx/insn_test_ldnt_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ldnt_X1.c
-//op=135
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x8f37eee6381b10aa, 0xa536cafeb2fbe757 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r18, -5987\n"
- "shl16insli r18, r18, -16935\n"
- "shl16insli r18, r18, 638\n"
- "shl16insli r18, r18, 32300\n"
- "moveli r2, -15250\n"
- "shl16insli r2, r2, 18129\n"
- "shl16insli r2, r2, -22479\n"
- "shl16insli r2, r2, 7405\n"
- "move r2, %2\n"
- "{ fnop ; ldnt r18, r2 }\n"
- "move %0, r18\n"
- "move %1, r2\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ldnt_add_X1.c b/none/tests/tilegx/insn_test_ldnt_add_X1.c
deleted file mode 100644
index 2638a7c..0000000
--- a/none/tests/tilegx/insn_test_ldnt_add_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_ldnt_add_X1.c
-//op=148
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd67c5353b4f83951, 0x68fb6e92c7467995 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r34, -10637\n"
- "shl16insli r34, r34, -13587\n"
- "shl16insli r34, r34, 6072\n"
- "shl16insli r34, r34, -2381\n"
- "moveli r42, -31836\n"
- "shl16insli r42, r42, -15605\n"
- "shl16insli r42, r42, -32767\n"
- "shl16insli r42, r42, -3062\n"
- "move r42, %2\n"
- "{ fnop ; ldnt_add r34, r42, 11 }\n"
- "move %0, r34\n"
- "move %1, r42\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_lnk_X1.c b/none/tests/tilegx/insn_test_lnk_X1.c
deleted file mode 100644
index e93fca6..0000000
--- a/none/tests/tilegx/insn_test_lnk_X1.c
+++ /dev/null
@@ -1,30 +0,0 @@
-//file: _insn_test_lnk_X1.c
-//op=149
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x74d04934d1d15274, 0xd270fbfbde298322 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r26, -23588\n"
- "shl16insli r26, r26, 9244\n"
- "shl16insli r26, r26, 32109\n"
- "shl16insli r26, r26, -30144\n"
- "{ fnop ; lnk r26 }\n"
- "move %0, r26\n"
- :"=r"(a[0]));
- printf("%016lx\n", a[0]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_lnk_Y1.c b/none/tests/tilegx/insn_test_lnk_Y1.c
deleted file mode 100644
index fe34ffd..0000000
--- a/none/tests/tilegx/insn_test_lnk_Y1.c
+++ /dev/null
@@ -1,30 +0,0 @@
-//file: _insn_test_lnk_Y1.c
-//op=149
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x74d04934d1d15274, 0xd270fbfbde298322 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r26, -23588\n"
- "shl16insli r26, r26, 9244\n"
- "shl16insli r26, r26, 32109\n"
- "shl16insli r26, r26, -30144\n"
- "{ fnop ; lnk r26 ; ld r63, r54 }\n"
- "move %0, r26\n"
- :"=r"(a[0]));
- printf("%016lx\n", a[0]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mf_X1.c b/none/tests/tilegx/insn_test_mf_X1.c
deleted file mode 100644
index ccf9c8b..0000000
--- a/none/tests/tilegx/insn_test_mf_X1.c
+++ /dev/null
@@ -1,24 +0,0 @@
-//file: _insn_test_mf_X1.c
-//op=150
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x95953511f9ee4512, 0x52148e33ddfabfa8 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "{ fnop ; mf }\n"
- );
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mm_X0.c b/none/tests/tilegx/insn_test_mm_X0.c
deleted file mode 100644
index 1500c60..0000000
--- a/none/tests/tilegx/insn_test_mm_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_mm_X0.c
-//op=152
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9d9b78ac30042683, 0xb17341a0d542c8a8 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r24, -8310\n"
- "shl16insli r24, r24, -28931\n"
- "shl16insli r24, r24, 16317\n"
- "shl16insli r24, r24, -2081\n"
- "moveli r31, -8094\n"
- "shl16insli r31, r31, -3077\n"
- "shl16insli r31, r31, 14718\n"
- "shl16insli r31, r31, -8598\n"
- "{ mm r24, r31, 34, 41 ; fnop }\n"
- "move %0, r24\n"
- "move %1, r31\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mnz_X0.c b/none/tests/tilegx/insn_test_mnz_X0.c
deleted file mode 100644
index 07ff1c6..0000000
--- a/none/tests/tilegx/insn_test_mnz_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mnz_X0.c
-//op=153
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc8c9da0e90770658, 0x3dce75e113642c2b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r11, 24848\n"
- "shl16insli r11, r11, -12444\n"
- "shl16insli r11, r11, -9823\n"
- "shl16insli r11, r11, -18157\n"
- "moveli r30, 11291\n"
- "shl16insli r30, r30, -29222\n"
- "shl16insli r30, r30, 27249\n"
- "shl16insli r30, r30, -15038\n"
- "moveli r22, 31329\n"
- "shl16insli r22, r22, 2611\n"
- "shl16insli r22, r22, -21984\n"
- "shl16insli r22, r22, -27173\n"
- "{ mnz r11, r30, r22 ; fnop }\n"
- "move %0, r11\n"
- "move %1, r30\n"
- "move %2, r22\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mnz_X1.c b/none/tests/tilegx/insn_test_mnz_X1.c
deleted file mode 100644
index a061ada..0000000
--- a/none/tests/tilegx/insn_test_mnz_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mnz_X1.c
-//op=153
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc8c9da0e90770658, 0x3dce75e113642c2b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r11, 24848\n"
- "shl16insli r11, r11, -12444\n"
- "shl16insli r11, r11, -9823\n"
- "shl16insli r11, r11, -18157\n"
- "moveli r30, 11291\n"
- "shl16insli r30, r30, -29222\n"
- "shl16insli r30, r30, 27249\n"
- "shl16insli r30, r30, -15038\n"
- "moveli r22, 31329\n"
- "shl16insli r22, r22, 2611\n"
- "shl16insli r22, r22, -21984\n"
- "shl16insli r22, r22, -27173\n"
- "{ fnop ; mnz r11, r30, r22 }\n"
- "move %0, r11\n"
- "move %1, r30\n"
- "move %2, r22\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mnz_Y0.c b/none/tests/tilegx/insn_test_mnz_Y0.c
deleted file mode 100644
index 858a94a..0000000
--- a/none/tests/tilegx/insn_test_mnz_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mnz_Y0.c
-//op=153
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc8c9da0e90770658, 0x3dce75e113642c2b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r11, 24848\n"
- "shl16insli r11, r11, -12444\n"
- "shl16insli r11, r11, -9823\n"
- "shl16insli r11, r11, -18157\n"
- "moveli r30, 11291\n"
- "shl16insli r30, r30, -29222\n"
- "shl16insli r30, r30, 27249\n"
- "shl16insli r30, r30, -15038\n"
- "moveli r22, 31329\n"
- "shl16insli r22, r22, 2611\n"
- "shl16insli r22, r22, -21984\n"
- "shl16insli r22, r22, -27173\n"
- "{ mnz r11, r30, r22 ; fnop ; ld r63, r54 }\n"
- "move %0, r11\n"
- "move %1, r30\n"
- "move %2, r22\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mnz_Y1.c b/none/tests/tilegx/insn_test_mnz_Y1.c
deleted file mode 100644
index 36b8cc5..0000000
--- a/none/tests/tilegx/insn_test_mnz_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mnz_Y1.c
-//op=153
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc8c9da0e90770658, 0x3dce75e113642c2b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r11, 24848\n"
- "shl16insli r11, r11, -12444\n"
- "shl16insli r11, r11, -9823\n"
- "shl16insli r11, r11, -18157\n"
- "moveli r30, 11291\n"
- "shl16insli r30, r30, -29222\n"
- "shl16insli r30, r30, 27249\n"
- "shl16insli r30, r30, -15038\n"
- "moveli r22, 31329\n"
- "shl16insli r22, r22, 2611\n"
- "shl16insli r22, r22, -21984\n"
- "shl16insli r22, r22, -27173\n"
- "{ fnop ; mnz r11, r30, r22 ; ld r63, r54 }\n"
- "move %0, r11\n"
- "move %1, r30\n"
- "move %2, r22\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_move_X0.c b/none/tests/tilegx/insn_test_move_X0.c
deleted file mode 100644
index d7a3b41..0000000
--- a/none/tests/tilegx/insn_test_move_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_move_X0.c
-//op=5
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xbccc64192e474b2d, 0xae4a1eebcf0aa6f1 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r22, -6666\n"
- "shl16insli r22, r22, 9055\n"
- "shl16insli r22, r22, 10215\n"
- "shl16insli r22, r22, -15289\n"
- "moveli r35, -17246\n"
- "shl16insli r35, r35, 164\n"
- "shl16insli r35, r35, 31728\n"
- "shl16insli r35, r35, -28689\n"
- "{ move r22, r35 ; fnop }\n"
- "move %0, r22\n"
- "move %1, r35\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_move_X1.c b/none/tests/tilegx/insn_test_move_X1.c
deleted file mode 100644
index 10bffd9..0000000
--- a/none/tests/tilegx/insn_test_move_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_move_X1.c
-//op=5
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xbccc64192e474b2d, 0xae4a1eebcf0aa6f1 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r22, -6666\n"
- "shl16insli r22, r22, 9055\n"
- "shl16insli r22, r22, 10215\n"
- "shl16insli r22, r22, -15289\n"
- "moveli r35, -17246\n"
- "shl16insli r35, r35, 164\n"
- "shl16insli r35, r35, 31728\n"
- "shl16insli r35, r35, -28689\n"
- "{ fnop ; move r22, r35 }\n"
- "move %0, r22\n"
- "move %1, r35\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_move_Y0.c b/none/tests/tilegx/insn_test_move_Y0.c
deleted file mode 100644
index c9e3682..0000000
--- a/none/tests/tilegx/insn_test_move_Y0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_move_Y0.c
-//op=5
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xbccc64192e474b2d, 0xae4a1eebcf0aa6f1 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r22, -6666\n"
- "shl16insli r22, r22, 9055\n"
- "shl16insli r22, r22, 10215\n"
- "shl16insli r22, r22, -15289\n"
- "moveli r35, -17246\n"
- "shl16insli r35, r35, 164\n"
- "shl16insli r35, r35, 31728\n"
- "shl16insli r35, r35, -28689\n"
- "{ move r22, r35 ; fnop ; ld r63, r54 }\n"
- "move %0, r22\n"
- "move %1, r35\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_move_Y1.c b/none/tests/tilegx/insn_test_move_Y1.c
deleted file mode 100644
index 30a6ca7..0000000
--- a/none/tests/tilegx/insn_test_move_Y1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_move_Y1.c
-//op=5
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xbccc64192e474b2d, 0xae4a1eebcf0aa6f1 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r22, -6666\n"
- "shl16insli r22, r22, 9055\n"
- "shl16insli r22, r22, 10215\n"
- "shl16insli r22, r22, -15289\n"
- "moveli r35, -17246\n"
- "shl16insli r35, r35, 164\n"
- "shl16insli r35, r35, 31728\n"
- "shl16insli r35, r35, -28689\n"
- "{ fnop ; move r22, r35 ; ld r63, r54 }\n"
- "move %0, r22\n"
- "move %1, r35\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_movei_X0.c b/none/tests/tilegx/insn_test_movei_X0.c
deleted file mode 100644
index bbef693..0000000
--- a/none/tests/tilegx/insn_test_movei_X0.c
+++ /dev/null
@@ -1,30 +0,0 @@
-//file: _insn_test_movei_X0.c
-//op=6
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd65eb4d9fa5bdd9a, 0x1c0a7303af5ad0fd };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r38, -24632\n"
- "shl16insli r38, r38, -1299\n"
- "shl16insli r38, r38, 29324\n"
- "shl16insli r38, r38, -18232\n"
- "{ movei r38, -17 ; fnop }\n"
- "move %0, r38\n"
- :"=r"(a[0]));
- printf("%016lx\n", a[0]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_movei_X1.c b/none/tests/tilegx/insn_test_movei_X1.c
deleted file mode 100644
index 65878b7..0000000
--- a/none/tests/tilegx/insn_test_movei_X1.c
+++ /dev/null
@@ -1,30 +0,0 @@
-//file: _insn_test_movei_X1.c
-//op=6
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd65eb4d9fa5bdd9a, 0x1c0a7303af5ad0fd };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r38, -24632\n"
- "shl16insli r38, r38, -1299\n"
- "shl16insli r38, r38, 29324\n"
- "shl16insli r38, r38, -18232\n"
- "{ fnop ; movei r38, -17 }\n"
- "move %0, r38\n"
- :"=r"(a[0]));
- printf("%016lx\n", a[0]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_movei_Y0.c b/none/tests/tilegx/insn_test_movei_Y0.c
deleted file mode 100644
index 7455ae6..0000000
--- a/none/tests/tilegx/insn_test_movei_Y0.c
+++ /dev/null
@@ -1,30 +0,0 @@
-//file: _insn_test_movei_Y0.c
-//op=6
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd65eb4d9fa5bdd9a, 0x1c0a7303af5ad0fd };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r38, -24632\n"
- "shl16insli r38, r38, -1299\n"
- "shl16insli r38, r38, 29324\n"
- "shl16insli r38, r38, -18232\n"
- "{ movei r38, -17 ; fnop ; ld r63, r54 }\n"
- "move %0, r38\n"
- :"=r"(a[0]));
- printf("%016lx\n", a[0]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_movei_Y1.c b/none/tests/tilegx/insn_test_movei_Y1.c
deleted file mode 100644
index ecdd4c0..0000000
--- a/none/tests/tilegx/insn_test_movei_Y1.c
+++ /dev/null
@@ -1,30 +0,0 @@
-//file: _insn_test_movei_Y1.c
-//op=6
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd65eb4d9fa5bdd9a, 0x1c0a7303af5ad0fd };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r38, -24632\n"
- "shl16insli r38, r38, -1299\n"
- "shl16insli r38, r38, 29324\n"
- "shl16insli r38, r38, -18232\n"
- "{ fnop ; movei r38, -17 ; ld r63, r54 }\n"
- "move %0, r38\n"
- :"=r"(a[0]));
- printf("%016lx\n", a[0]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_moveli_X0.c b/none/tests/tilegx/insn_test_moveli_X0.c
deleted file mode 100644
index 7d4fabf..0000000
--- a/none/tests/tilegx/insn_test_moveli_X0.c
+++ /dev/null
@@ -1,30 +0,0 @@
-//file: _insn_test_moveli_X0.c
-//op=7
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x4448037363c51f9a, 0xd2e5cb4994058d63 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r45, -7137\n"
- "shl16insli r45, r45, 897\n"
- "shl16insli r45, r45, 23961\n"
- "shl16insli r45, r45, -21354\n"
- "{ moveli r45, -15765 ; fnop }\n"
- "move %0, r45\n"
- :"=r"(a[0]));
- printf("%016lx\n", a[0]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_moveli_X1.c b/none/tests/tilegx/insn_test_moveli_X1.c
deleted file mode 100644
index 6114841..0000000
--- a/none/tests/tilegx/insn_test_moveli_X1.c
+++ /dev/null
@@ -1,30 +0,0 @@
-//file: _insn_test_moveli_X1.c
-//op=7
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x4448037363c51f9a, 0xd2e5cb4994058d63 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r45, -7137\n"
- "shl16insli r45, r45, 897\n"
- "shl16insli r45, r45, 23961\n"
- "shl16insli r45, r45, -21354\n"
- "{ fnop ; moveli r45, -15765 }\n"
- "move %0, r45\n"
- :"=r"(a[0]));
- printf("%016lx\n", a[0]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mul_hs_hs_X0.c b/none/tests/tilegx/insn_test_mul_hs_hs_X0.c
deleted file mode 100644
index 62e1afd..0000000
--- a/none/tests/tilegx/insn_test_mul_hs_hs_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mul_hs_hs_X0.c
-//op=155
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc707c0e7f8704eba, 0x1518d5b56d04d8a5 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r39, 2892\n"
- "shl16insli r39, r39, -15734\n"
- "shl16insli r39, r39, -18162\n"
- "shl16insli r39, r39, -30153\n"
- "moveli r32, 31894\n"
- "shl16insli r32, r32, -18512\n"
- "shl16insli r32, r32, 13763\n"
- "shl16insli r32, r32, -9785\n"
- "moveli r18, 14299\n"
- "shl16insli r18, r18, -16601\n"
- "shl16insli r18, r18, -30080\n"
- "shl16insli r18, r18, 10179\n"
- "{ mul_hs_hs r39, r32, r18 ; fnop }\n"
- "move %0, r39\n"
- "move %1, r32\n"
- "move %2, r18\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mul_hs_hs_Y0.c b/none/tests/tilegx/insn_test_mul_hs_hs_Y0.c
deleted file mode 100644
index 8d4f536..0000000
--- a/none/tests/tilegx/insn_test_mul_hs_hs_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mul_hs_hs_Y0.c
-//op=155
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc707c0e7f8704eba, 0x1518d5b56d04d8a5 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r39, 2892\n"
- "shl16insli r39, r39, -15734\n"
- "shl16insli r39, r39, -18162\n"
- "shl16insli r39, r39, -30153\n"
- "moveli r32, 31894\n"
- "shl16insli r32, r32, -18512\n"
- "shl16insli r32, r32, 13763\n"
- "shl16insli r32, r32, -9785\n"
- "moveli r18, 14299\n"
- "shl16insli r18, r18, -16601\n"
- "shl16insli r18, r18, -30080\n"
- "shl16insli r18, r18, 10179\n"
- "{ mul_hs_hs r39, r32, r18 ; fnop ; ld r63, r54 }\n"
- "move %0, r39\n"
- "move %1, r32\n"
- "move %2, r18\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mul_hs_hu_X0.c b/none/tests/tilegx/insn_test_mul_hs_hu_X0.c
deleted file mode 100644
index 19ae691..0000000
--- a/none/tests/tilegx/insn_test_mul_hs_hu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mul_hs_hu_X0.c
-//op=156
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x31d131ae6b7da416, 0x3e01995aa9302c9b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r35, 4550\n"
- "shl16insli r35, r35, 29355\n"
- "shl16insli r35, r35, 30941\n"
- "shl16insli r35, r35, 29755\n"
- "moveli r7, -18630\n"
- "shl16insli r7, r7, -31252\n"
- "shl16insli r7, r7, -15964\n"
- "shl16insli r7, r7, 8400\n"
- "moveli r22, 29514\n"
- "shl16insli r22, r22, 14828\n"
- "shl16insli r22, r22, 1013\n"
- "shl16insli r22, r22, 14302\n"
- "{ mul_hs_hu r35, r7, r22 ; fnop }\n"
- "move %0, r35\n"
- "move %1, r7\n"
- "move %2, r22\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mul_hs_ls_X0.c b/none/tests/tilegx/insn_test_mul_hs_ls_X0.c
deleted file mode 100644
index a8a31c4..0000000
--- a/none/tests/tilegx/insn_test_mul_hs_ls_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mul_hs_ls_X0.c
-//op=157
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc2cac20f9054ab64, 0xc57bfb2ed874d267 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r22, 30145\n"
- "shl16insli r22, r22, 20983\n"
- "shl16insli r22, r22, 7997\n"
- "shl16insli r22, r22, -21347\n"
- "moveli r0, 3083\n"
- "shl16insli r0, r0, -6125\n"
- "shl16insli r0, r0, -10642\n"
- "shl16insli r0, r0, 872\n"
- "moveli r19, -14850\n"
- "shl16insli r19, r19, -32360\n"
- "shl16insli r19, r19, 12889\n"
- "shl16insli r19, r19, 3288\n"
- "{ mul_hs_ls r22, r0, r19 ; fnop }\n"
- "move %0, r22\n"
- "move %1, r0\n"
- "move %2, r19\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mul_hs_lu_X0.c b/none/tests/tilegx/insn_test_mul_hs_lu_X0.c
deleted file mode 100644
index 69eb7f3..0000000
--- a/none/tests/tilegx/insn_test_mul_hs_lu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mul_hs_lu_X0.c
-//op=158
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x194c873261582759, 0x910a2955c6e71b1 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r6, 31890\n"
- "shl16insli r6, r6, 22503\n"
- "shl16insli r6, r6, 26461\n"
- "shl16insli r6, r6, -16338\n"
- "moveli r25, 31333\n"
- "shl16insli r25, r25, 15554\n"
- "shl16insli r25, r25, 16035\n"
- "shl16insli r25, r25, -6284\n"
- "moveli r17, -19874\n"
- "shl16insli r17, r17, -32652\n"
- "shl16insli r17, r17, -27551\n"
- "shl16insli r17, r17, 14010\n"
- "{ mul_hs_lu r6, r25, r17 ; fnop }\n"
- "move %0, r6\n"
- "move %1, r25\n"
- "move %2, r17\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mul_hu_hu_X0.c b/none/tests/tilegx/insn_test_mul_hu_hu_X0.c
deleted file mode 100644
index 5bf53bd..0000000
--- a/none/tests/tilegx/insn_test_mul_hu_hu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mul_hu_hu_X0.c
-//op=159
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x2f10bc93a323ca0d, 0x9be2dc4ee83ae1ea };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r18, -11405\n"
- "shl16insli r18, r18, -6947\n"
- "shl16insli r18, r18, 19133\n"
- "shl16insli r18, r18, -19900\n"
- "moveli r27, 31983\n"
- "shl16insli r27, r27, 16872\n"
- "shl16insli r27, r27, 25578\n"
- "shl16insli r27, r27, 12902\n"
- "moveli r10, 20609\n"
- "shl16insli r10, r10, -28665\n"
- "shl16insli r10, r10, -5637\n"
- "shl16insli r10, r10, -7979\n"
- "{ mul_hu_hu r18, r27, r10 ; fnop }\n"
- "move %0, r18\n"
- "move %1, r27\n"
- "move %2, r10\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mul_hu_hu_Y0.c b/none/tests/tilegx/insn_test_mul_hu_hu_Y0.c
deleted file mode 100644
index ede94dd..0000000
--- a/none/tests/tilegx/insn_test_mul_hu_hu_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mul_hu_hu_Y0.c
-//op=159
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x2f10bc93a323ca0d, 0x9be2dc4ee83ae1ea };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r18, -11405\n"
- "shl16insli r18, r18, -6947\n"
- "shl16insli r18, r18, 19133\n"
- "shl16insli r18, r18, -19900\n"
- "moveli r27, 31983\n"
- "shl16insli r27, r27, 16872\n"
- "shl16insli r27, r27, 25578\n"
- "shl16insli r27, r27, 12902\n"
- "moveli r10, 20609\n"
- "shl16insli r10, r10, -28665\n"
- "shl16insli r10, r10, -5637\n"
- "shl16insli r10, r10, -7979\n"
- "{ mul_hu_hu r18, r27, r10 ; fnop ; ld r63, r54 }\n"
- "move %0, r18\n"
- "move %1, r27\n"
- "move %2, r10\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mul_hu_lu_X0.c b/none/tests/tilegx/insn_test_mul_hu_lu_X0.c
deleted file mode 100644
index cae7ebd..0000000
--- a/none/tests/tilegx/insn_test_mul_hu_lu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mul_hu_lu_X0.c
-//op=161
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x4639d63ca03e5e4e, 0x5e51bd49489c060d };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r10, -11099\n"
- "shl16insli r10, r10, 22725\n"
- "shl16insli r10, r10, -18659\n"
- "shl16insli r10, r10, 28990\n"
- "moveli r19, -7114\n"
- "shl16insli r19, r19, -4623\n"
- "shl16insli r19, r19, 4807\n"
- "shl16insli r19, r19, -17110\n"
- "moveli r31, 5393\n"
- "shl16insli r31, r31, -22253\n"
- "shl16insli r31, r31, 25749\n"
- "shl16insli r31, r31, -7203\n"
- "{ mul_hu_lu r10, r19, r31 ; fnop }\n"
- "move %0, r10\n"
- "move %1, r19\n"
- "move %2, r31\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mul_ls_ls_X0.c b/none/tests/tilegx/insn_test_mul_ls_ls_X0.c
deleted file mode 100644
index b9f0bf0..0000000
--- a/none/tests/tilegx/insn_test_mul_ls_ls_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mul_ls_ls_X0.c
-//op=162
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x228e8e83b7561e89, 0x175f6b2301c3969d };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r33, 9145\n"
- "shl16insli r33, r33, 16129\n"
- "shl16insli r33, r33, -28988\n"
- "shl16insli r33, r33, -28265\n"
- "moveli r47, -17072\n"
- "shl16insli r47, r47, 26742\n"
- "shl16insli r47, r47, -10023\n"
- "shl16insli r47, r47, -32380\n"
- "moveli r19, 7549\n"
- "shl16insli r19, r19, -19041\n"
- "shl16insli r19, r19, -30505\n"
- "shl16insli r19, r19, -15011\n"
- "{ mul_ls_ls r33, r47, r19 ; fnop }\n"
- "move %0, r33\n"
- "move %1, r47\n"
- "move %2, r19\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mul_ls_ls_Y0.c b/none/tests/tilegx/insn_test_mul_ls_ls_Y0.c
deleted file mode 100644
index 84ad175..0000000
--- a/none/tests/tilegx/insn_test_mul_ls_ls_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mul_ls_ls_Y0.c
-//op=162
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x228e8e83b7561e89, 0x175f6b2301c3969d };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r33, 9145\n"
- "shl16insli r33, r33, 16129\n"
- "shl16insli r33, r33, -28988\n"
- "shl16insli r33, r33, -28265\n"
- "moveli r47, -17072\n"
- "shl16insli r47, r47, 26742\n"
- "shl16insli r47, r47, -10023\n"
- "shl16insli r47, r47, -32380\n"
- "moveli r19, 7549\n"
- "shl16insli r19, r19, -19041\n"
- "shl16insli r19, r19, -30505\n"
- "shl16insli r19, r19, -15011\n"
- "{ mul_ls_ls r33, r47, r19 ; fnop ; ld r63, r54 }\n"
- "move %0, r33\n"
- "move %1, r47\n"
- "move %2, r19\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mul_ls_lu_X0.c b/none/tests/tilegx/insn_test_mul_ls_lu_X0.c
deleted file mode 100644
index 2808862..0000000
--- a/none/tests/tilegx/insn_test_mul_ls_lu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mul_ls_lu_X0.c
-//op=163
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xcdce8cd30da8f45b, 0x85932185df148d8d };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r2, -19516\n"
- "shl16insli r2, r2, -21805\n"
- "shl16insli r2, r2, -31810\n"
- "shl16insli r2, r2, 31088\n"
- "moveli r32, 3846\n"
- "shl16insli r32, r32, -1507\n"
- "shl16insli r32, r32, -17183\n"
- "shl16insli r32, r32, -527\n"
- "moveli r4, 25062\n"
- "shl16insli r4, r4, -3688\n"
- "shl16insli r4, r4, 15670\n"
- "shl16insli r4, r4, 15480\n"
- "{ mul_ls_lu r2, r32, r4 ; fnop }\n"
- "move %0, r2\n"
- "move %1, r32\n"
- "move %2, r4\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mul_lu_lu_X0.c b/none/tests/tilegx/insn_test_mul_lu_lu_X0.c
deleted file mode 100644
index 89ed777..0000000
--- a/none/tests/tilegx/insn_test_mul_lu_lu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mul_lu_lu_X0.c
-//op=164
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd75570c277b73b03, 0x5ff5d41ce72b342e };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r24, 10847\n"
- "shl16insli r24, r24, -21273\n"
- "shl16insli r24, r24, -26560\n"
- "shl16insli r24, r24, -2137\n"
- "moveli r22, -4257\n"
- "shl16insli r22, r22, 16637\n"
- "shl16insli r22, r22, -13862\n"
- "shl16insli r22, r22, 2993\n"
- "moveli r2, 2928\n"
- "shl16insli r2, r2, -22351\n"
- "shl16insli r2, r2, 15965\n"
- "shl16insli r2, r2, -15676\n"
- "{ mul_lu_lu r24, r22, r2 ; fnop }\n"
- "move %0, r24\n"
- "move %1, r22\n"
- "move %2, r2\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mul_lu_lu_Y0.c b/none/tests/tilegx/insn_test_mul_lu_lu_Y0.c
deleted file mode 100644
index 9119189..0000000
--- a/none/tests/tilegx/insn_test_mul_lu_lu_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mul_lu_lu_Y0.c
-//op=164
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd75570c277b73b03, 0x5ff5d41ce72b342e };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r24, 10847\n"
- "shl16insli r24, r24, -21273\n"
- "shl16insli r24, r24, -26560\n"
- "shl16insli r24, r24, -2137\n"
- "moveli r22, -4257\n"
- "shl16insli r22, r22, 16637\n"
- "shl16insli r22, r22, -13862\n"
- "shl16insli r22, r22, 2993\n"
- "moveli r2, 2928\n"
- "shl16insli r2, r2, -22351\n"
- "shl16insli r2, r2, 15965\n"
- "shl16insli r2, r2, -15676\n"
- "{ mul_lu_lu r24, r22, r2 ; fnop ; ld r63, r54 }\n"
- "move %0, r24\n"
- "move %1, r22\n"
- "move %2, r2\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mula_hs_hs_X0.c b/none/tests/tilegx/insn_test_mula_hs_hs_X0.c
deleted file mode 100644
index ba063d6..0000000
--- a/none/tests/tilegx/insn_test_mula_hs_hs_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mula_hs_hs_X0.c
-//op=165
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xec7e102d827fb085, 0x2fbb511bf652c89f };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r42, -23610\n"
- "shl16insli r42, r42, -23703\n"
- "shl16insli r42, r42, 2719\n"
- "shl16insli r42, r42, -32635\n"
- "moveli r11, 21737\n"
- "shl16insli r11, r11, 21508\n"
- "shl16insli r11, r11, 4642\n"
- "shl16insli r11, r11, -1298\n"
- "moveli r45, 16489\n"
- "shl16insli r45, r45, 1852\n"
- "shl16insli r45, r45, -22328\n"
- "shl16insli r45, r45, -20016\n"
- "{ mula_hs_hs r42, r11, r45 ; fnop }\n"
- "move %0, r42\n"
- "move %1, r11\n"
- "move %2, r45\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mula_hs_hs_Y0.c b/none/tests/tilegx/insn_test_mula_hs_hs_Y0.c
deleted file mode 100644
index c932dcc..0000000
--- a/none/tests/tilegx/insn_test_mula_hs_hs_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mula_hs_hs_Y0.c
-//op=165
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xec7e102d827fb085, 0x2fbb511bf652c89f };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r42, -23610\n"
- "shl16insli r42, r42, -23703\n"
- "shl16insli r42, r42, 2719\n"
- "shl16insli r42, r42, -32635\n"
- "moveli r11, 21737\n"
- "shl16insli r11, r11, 21508\n"
- "shl16insli r11, r11, 4642\n"
- "shl16insli r11, r11, -1298\n"
- "moveli r45, 16489\n"
- "shl16insli r45, r45, 1852\n"
- "shl16insli r45, r45, -22328\n"
- "shl16insli r45, r45, -20016\n"
- "{ mula_hs_hs r42, r11, r45 ; fnop ; ld r63, r54 }\n"
- "move %0, r42\n"
- "move %1, r11\n"
- "move %2, r45\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mula_hs_hu_X0.c b/none/tests/tilegx/insn_test_mula_hs_hu_X0.c
deleted file mode 100644
index 173128b..0000000
--- a/none/tests/tilegx/insn_test_mula_hs_hu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mula_hs_hu_X0.c
-//op=166
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x269cb922a1bf2c20, 0x57b488292bdd9c2b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r30, 4246\n"
- "shl16insli r30, r30, 6079\n"
- "shl16insli r30, r30, 8698\n"
- "shl16insli r30, r30, -2697\n"
- "moveli r29, 27899\n"
- "shl16insli r29, r29, -1363\n"
- "shl16insli r29, r29, 695\n"
- "shl16insli r29, r29, -3150\n"
- "moveli r29, -29126\n"
- "shl16insli r29, r29, -20326\n"
- "shl16insli r29, r29, 27689\n"
- "shl16insli r29, r29, 15548\n"
- "{ mula_hs_hu r30, r29, r29 ; fnop }\n"
- "move %0, r30\n"
- "move %1, r29\n"
- "move %2, r29\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mula_hs_ls_X0.c b/none/tests/tilegx/insn_test_mula_hs_ls_X0.c
deleted file mode 100644
index 3b0f9ed..0000000
--- a/none/tests/tilegx/insn_test_mula_hs_ls_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mula_hs_ls_X0.c
-//op=167
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x334d1321b4c11950, 0x4406ad0fa9c44e77 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r37, 47\n"
- "shl16insli r37, r37, 27756\n"
- "shl16insli r37, r37, -285\n"
- "shl16insli r37, r37, 5847\n"
- "moveli r14, -22393\n"
- "shl16insli r14, r14, -5429\n"
- "shl16insli r14, r14, -14300\n"
- "shl16insli r14, r14, 11616\n"
- "moveli r1, 31370\n"
- "shl16insli r1, r1, -7442\n"
- "shl16insli r1, r1, 26409\n"
- "shl16insli r1, r1, 25903\n"
- "{ mula_hs_ls r37, r14, r1 ; fnop }\n"
- "move %0, r37\n"
- "move %1, r14\n"
- "move %2, r1\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mula_hs_lu_X0.c b/none/tests/tilegx/insn_test_mula_hs_lu_X0.c
deleted file mode 100644
index 8279c24..0000000
--- a/none/tests/tilegx/insn_test_mula_hs_lu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mula_hs_lu_X0.c
-//op=168
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xf64e075b02f515ca, 0xdff35e384e663195 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r45, -4690\n"
- "shl16insli r45, r45, 18437\n"
- "shl16insli r45, r45, 14549\n"
- "shl16insli r45, r45, -22291\n"
- "moveli r7, 15584\n"
- "shl16insli r7, r7, -16025\n"
- "shl16insli r7, r7, 24621\n"
- "shl16insli r7, r7, -25450\n"
- "moveli r2, -16204\n"
- "shl16insli r2, r2, -989\n"
- "shl16insli r2, r2, -29843\n"
- "shl16insli r2, r2, -32026\n"
- "{ mula_hs_lu r45, r7, r2 ; fnop }\n"
- "move %0, r45\n"
- "move %1, r7\n"
- "move %2, r2\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mula_hu_hu_X0.c b/none/tests/tilegx/insn_test_mula_hu_hu_X0.c
deleted file mode 100644
index 52429d7..0000000
--- a/none/tests/tilegx/insn_test_mula_hu_hu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mula_hu_hu_X0.c
-//op=169
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xa479dc4ef3600b13, 0x286401a31761e02a };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r0, -9560\n"
- "shl16insli r0, r0, 27577\n"
- "shl16insli r0, r0, -8798\n"
- "shl16insli r0, r0, 25385\n"
- "moveli r47, -17024\n"
- "shl16insli r47, r47, -8491\n"
- "shl16insli r47, r47, 31461\n"
- "shl16insli r47, r47, -10531\n"
- "moveli r35, 13663\n"
- "shl16insli r35, r35, 11635\n"
- "shl16insli r35, r35, -24944\n"
- "shl16insli r35, r35, -3616\n"
- "{ mula_hu_hu r0, r47, r35 ; fnop }\n"
- "move %0, r0\n"
- "move %1, r47\n"
- "move %2, r35\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mula_hu_hu_Y0.c b/none/tests/tilegx/insn_test_mula_hu_hu_Y0.c
deleted file mode 100644
index 54d848c..0000000
--- a/none/tests/tilegx/insn_test_mula_hu_hu_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mula_hu_hu_Y0.c
-//op=169
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xa479dc4ef3600b13, 0x286401a31761e02a };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r0, -9560\n"
- "shl16insli r0, r0, 27577\n"
- "shl16insli r0, r0, -8798\n"
- "shl16insli r0, r0, 25385\n"
- "moveli r47, -17024\n"
- "shl16insli r47, r47, -8491\n"
- "shl16insli r47, r47, 31461\n"
- "shl16insli r47, r47, -10531\n"
- "moveli r35, 13663\n"
- "shl16insli r35, r35, 11635\n"
- "shl16insli r35, r35, -24944\n"
- "shl16insli r35, r35, -3616\n"
- "{ mula_hu_hu r0, r47, r35 ; fnop ; ld r63, r54 }\n"
- "move %0, r0\n"
- "move %1, r47\n"
- "move %2, r35\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mula_hu_ls_X0.c b/none/tests/tilegx/insn_test_mula_hu_ls_X0.c
deleted file mode 100644
index db45f92..0000000
--- a/none/tests/tilegx/insn_test_mula_hu_ls_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mula_hu_ls_X0.c
-//op=170
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x7c2b00bc8a60c95d, 0x8a6bdf08a51f10d3 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r22, -8315\n"
- "shl16insli r22, r22, 5404\n"
- "shl16insli r22, r22, 15177\n"
- "shl16insli r22, r22, -6931\n"
- "moveli r12, -20178\n"
- "shl16insli r12, r12, 16109\n"
- "shl16insli r12, r12, -17955\n"
- "shl16insli r12, r12, 766\n"
- "moveli r43, -29874\n"
- "shl16insli r43, r43, -7795\n"
- "shl16insli r43, r43, -2712\n"
- "shl16insli r43, r43, 26506\n"
- "{ mula_hu_ls r22, r12, r43 ; fnop }\n"
- "move %0, r22\n"
- "move %1, r12\n"
- "move %2, r43\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mula_hu_lu_X0.c b/none/tests/tilegx/insn_test_mula_hu_lu_X0.c
deleted file mode 100644
index d411a28..0000000
--- a/none/tests/tilegx/insn_test_mula_hu_lu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mula_hu_lu_X0.c
-//op=171
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xe2c25e110bb59946, 0xd06357c8b3903323 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r36, -11276\n"
- "shl16insli r36, r36, -71\n"
- "shl16insli r36, r36, -26089\n"
- "shl16insli r36, r36, 30233\n"
- "moveli r22, 9301\n"
- "shl16insli r22, r22, -32656\n"
- "shl16insli r22, r22, -4555\n"
- "shl16insli r22, r22, 17657\n"
- "moveli r24, 17032\n"
- "shl16insli r24, r24, 29889\n"
- "shl16insli r24, r24, 32576\n"
- "shl16insli r24, r24, 8242\n"
- "{ mula_hu_lu r36, r22, r24 ; fnop }\n"
- "move %0, r36\n"
- "move %1, r22\n"
- "move %2, r24\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mula_ls_ls_X0.c b/none/tests/tilegx/insn_test_mula_ls_ls_X0.c
deleted file mode 100644
index baaa378..0000000
--- a/none/tests/tilegx/insn_test_mula_ls_ls_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mula_ls_ls_X0.c
-//op=172
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x481bd1c9a41ebd0a, 0x38646a3eaf613478 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r17, -19781\n"
- "shl16insli r17, r17, 4441\n"
- "shl16insli r17, r17, -25151\n"
- "shl16insli r17, r17, -1099\n"
- "moveli r30, 16040\n"
- "shl16insli r30, r30, 13539\n"
- "shl16insli r30, r30, -10611\n"
- "shl16insli r30, r30, 18456\n"
- "moveli r43, 9010\n"
- "shl16insli r43, r43, -28846\n"
- "shl16insli r43, r43, 3819\n"
- "shl16insli r43, r43, -25218\n"
- "{ mula_ls_ls r17, r30, r43 ; fnop }\n"
- "move %0, r17\n"
- "move %1, r30\n"
- "move %2, r43\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mula_ls_ls_Y0.c b/none/tests/tilegx/insn_test_mula_ls_ls_Y0.c
deleted file mode 100644
index 80c88ed..0000000
--- a/none/tests/tilegx/insn_test_mula_ls_ls_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mula_ls_ls_Y0.c
-//op=172
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x481bd1c9a41ebd0a, 0x38646a3eaf613478 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r17, -19781\n"
- "shl16insli r17, r17, 4441\n"
- "shl16insli r17, r17, -25151\n"
- "shl16insli r17, r17, -1099\n"
- "moveli r30, 16040\n"
- "shl16insli r30, r30, 13539\n"
- "shl16insli r30, r30, -10611\n"
- "shl16insli r30, r30, 18456\n"
- "moveli r43, 9010\n"
- "shl16insli r43, r43, -28846\n"
- "shl16insli r43, r43, 3819\n"
- "shl16insli r43, r43, -25218\n"
- "{ mula_ls_ls r17, r30, r43 ; fnop ; ld r63, r54 }\n"
- "move %0, r17\n"
- "move %1, r30\n"
- "move %2, r43\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mula_ls_lu_X0.c b/none/tests/tilegx/insn_test_mula_ls_lu_X0.c
deleted file mode 100644
index ecfbbfb..0000000
--- a/none/tests/tilegx/insn_test_mula_ls_lu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mula_ls_lu_X0.c
-//op=173
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x4a40d1e28d4a3d4a, 0x308f52b9c1ed029f };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r3, 14076\n"
- "shl16insli r3, r3, -13318\n"
- "shl16insli r3, r3, -31064\n"
- "shl16insli r3, r3, 24882\n"
- "moveli r2, 1130\n"
- "shl16insli r2, r2, 19735\n"
- "shl16insli r2, r2, 18026\n"
- "shl16insli r2, r2, 2783\n"
- "moveli r34, 22540\n"
- "shl16insli r34, r34, -22507\n"
- "shl16insli r34, r34, 24248\n"
- "shl16insli r34, r34, 23620\n"
- "{ mula_ls_lu r3, r2, r34 ; fnop }\n"
- "move %0, r3\n"
- "move %1, r2\n"
- "move %2, r34\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mula_lu_lu_X0.c b/none/tests/tilegx/insn_test_mula_lu_lu_X0.c
deleted file mode 100644
index 38ef23f..0000000
--- a/none/tests/tilegx/insn_test_mula_lu_lu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mula_lu_lu_X0.c
-//op=174
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9e2898e9d06dd42a, 0xc7ac37053a461101 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r39, -11842\n"
- "shl16insli r39, r39, 25434\n"
- "shl16insli r39, r39, -11416\n"
- "shl16insli r39, r39, -1334\n"
- "moveli r38, -8159\n"
- "shl16insli r38, r38, -19405\n"
- "shl16insli r38, r38, -6882\n"
- "shl16insli r38, r38, 24332\n"
- "moveli r36, 11583\n"
- "shl16insli r36, r36, -32720\n"
- "shl16insli r36, r36, 17409\n"
- "shl16insli r36, r36, -25838\n"
- "{ mula_lu_lu r39, r38, r36 ; fnop }\n"
- "move %0, r39\n"
- "move %1, r38\n"
- "move %2, r36\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mula_lu_lu_Y0.c b/none/tests/tilegx/insn_test_mula_lu_lu_Y0.c
deleted file mode 100644
index 59f9712..0000000
--- a/none/tests/tilegx/insn_test_mula_lu_lu_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mula_lu_lu_Y0.c
-//op=174
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9e2898e9d06dd42a, 0xc7ac37053a461101 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r39, -11842\n"
- "shl16insli r39, r39, 25434\n"
- "shl16insli r39, r39, -11416\n"
- "shl16insli r39, r39, -1334\n"
- "moveli r38, -8159\n"
- "shl16insli r38, r38, -19405\n"
- "shl16insli r38, r38, -6882\n"
- "shl16insli r38, r38, 24332\n"
- "moveli r36, 11583\n"
- "shl16insli r36, r36, -32720\n"
- "shl16insli r36, r36, 17409\n"
- "shl16insli r36, r36, -25838\n"
- "{ mula_lu_lu r39, r38, r36 ; fnop ; ld r63, r54 }\n"
- "move %0, r39\n"
- "move %1, r38\n"
- "move %2, r36\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mulax_X0.c b/none/tests/tilegx/insn_test_mulax_X0.c
deleted file mode 100644
index ce091a9..0000000
--- a/none/tests/tilegx/insn_test_mulax_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mulax_X0.c
-//op=175
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xf2b0303a92767195, 0x8dd298793721b4a };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r48, -15789\n"
- "shl16insli r48, r48, 590\n"
- "shl16insli r48, r48, -26270\n"
- "shl16insli r48, r48, -21766\n"
- "moveli r44, 23264\n"
- "shl16insli r44, r44, -28907\n"
- "shl16insli r44, r44, -1813\n"
- "shl16insli r44, r44, -17554\n"
- "moveli r46, -2982\n"
- "shl16insli r46, r46, -29749\n"
- "shl16insli r46, r46, 881\n"
- "shl16insli r46, r46, 9838\n"
- "{ mulax r48, r44, r46 ; fnop }\n"
- "move %0, r48\n"
- "move %1, r44\n"
- "move %2, r46\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mulax_Y0.c b/none/tests/tilegx/insn_test_mulax_Y0.c
deleted file mode 100644
index 8c2153f..0000000
--- a/none/tests/tilegx/insn_test_mulax_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mulax_Y0.c
-//op=175
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xf2b0303a92767195, 0x8dd298793721b4a };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r48, -15789\n"
- "shl16insli r48, r48, 590\n"
- "shl16insli r48, r48, -26270\n"
- "shl16insli r48, r48, -21766\n"
- "moveli r44, 23264\n"
- "shl16insli r44, r44, -28907\n"
- "shl16insli r44, r44, -1813\n"
- "shl16insli r44, r44, -17554\n"
- "moveli r46, -2982\n"
- "shl16insli r46, r46, -29749\n"
- "shl16insli r46, r46, 881\n"
- "shl16insli r46, r46, 9838\n"
- "{ mulax r48, r44, r46 ; fnop ; ld r63, r54 }\n"
- "move %0, r48\n"
- "move %1, r44\n"
- "move %2, r46\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mulx_X0.c b/none/tests/tilegx/insn_test_mulx_X0.c
deleted file mode 100644
index d37f2a3..0000000
--- a/none/tests/tilegx/insn_test_mulx_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mulx_X0.c
-//op=176
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xe468b0628a4b2c82, 0xab961c7cdfcb76d0 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r34, -17450\n"
- "shl16insli r34, r34, 24652\n"
- "shl16insli r34, r34, 22143\n"
- "shl16insli r34, r34, -2590\n"
- "moveli r20, 3184\n"
- "shl16insli r20, r20, 7750\n"
- "shl16insli r20, r20, -24327\n"
- "shl16insli r20, r20, 22846\n"
- "moveli r43, -31998\n"
- "shl16insli r43, r43, 23863\n"
- "shl16insli r43, r43, -12992\n"
- "shl16insli r43, r43, -15691\n"
- "{ mulx r34, r20, r43 ; fnop }\n"
- "move %0, r34\n"
- "move %1, r20\n"
- "move %2, r43\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mulx_Y0.c b/none/tests/tilegx/insn_test_mulx_Y0.c
deleted file mode 100644
index 2ce09b6..0000000
--- a/none/tests/tilegx/insn_test_mulx_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mulx_Y0.c
-//op=176
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xe468b0628a4b2c82, 0xab961c7cdfcb76d0 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r34, -17450\n"
- "shl16insli r34, r34, 24652\n"
- "shl16insli r34, r34, 22143\n"
- "shl16insli r34, r34, -2590\n"
- "moveli r20, 3184\n"
- "shl16insli r20, r20, 7750\n"
- "shl16insli r20, r20, -24327\n"
- "shl16insli r20, r20, 22846\n"
- "moveli r43, -31998\n"
- "shl16insli r43, r43, 23863\n"
- "shl16insli r43, r43, -12992\n"
- "shl16insli r43, r43, -15691\n"
- "{ mulx r34, r20, r43 ; fnop ; ld r63, r54 }\n"
- "move %0, r34\n"
- "move %1, r20\n"
- "move %2, r43\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mz_X0.c b/none/tests/tilegx/insn_test_mz_X0.c
deleted file mode 100644
index 89d802c..0000000
--- a/none/tests/tilegx/insn_test_mz_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mz_X0.c
-//op=177
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9b70a44aad51d91c, 0x67d733d090a0e0ad };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r47, -6674\n"
- "shl16insli r47, r47, -26653\n"
- "shl16insli r47, r47, -16240\n"
- "shl16insli r47, r47, 300\n"
- "moveli r39, -14350\n"
- "shl16insli r39, r39, -13718\n"
- "shl16insli r39, r39, -10168\n"
- "shl16insli r39, r39, -15190\n"
- "moveli r40, 208\n"
- "shl16insli r40, r40, 20913\n"
- "shl16insli r40, r40, 19131\n"
- "shl16insli r40, r40, -17081\n"
- "{ mz r47, r39, r40 ; fnop }\n"
- "move %0, r47\n"
- "move %1, r39\n"
- "move %2, r40\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mz_X1.c b/none/tests/tilegx/insn_test_mz_X1.c
deleted file mode 100644
index f4b0421..0000000
--- a/none/tests/tilegx/insn_test_mz_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mz_X1.c
-//op=177
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9b70a44aad51d91c, 0x67d733d090a0e0ad };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r47, -6674\n"
- "shl16insli r47, r47, -26653\n"
- "shl16insli r47, r47, -16240\n"
- "shl16insli r47, r47, 300\n"
- "moveli r39, -14350\n"
- "shl16insli r39, r39, -13718\n"
- "shl16insli r39, r39, -10168\n"
- "shl16insli r39, r39, -15190\n"
- "moveli r40, 208\n"
- "shl16insli r40, r40, 20913\n"
- "shl16insli r40, r40, 19131\n"
- "shl16insli r40, r40, -17081\n"
- "{ fnop ; mz r47, r39, r40 }\n"
- "move %0, r47\n"
- "move %1, r39\n"
- "move %2, r40\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mz_Y0.c b/none/tests/tilegx/insn_test_mz_Y0.c
deleted file mode 100644
index c538f06..0000000
--- a/none/tests/tilegx/insn_test_mz_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mz_Y0.c
-//op=177
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9b70a44aad51d91c, 0x67d733d090a0e0ad };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r47, -6674\n"
- "shl16insli r47, r47, -26653\n"
- "shl16insli r47, r47, -16240\n"
- "shl16insli r47, r47, 300\n"
- "moveli r39, -14350\n"
- "shl16insli r39, r39, -13718\n"
- "shl16insli r39, r39, -10168\n"
- "shl16insli r39, r39, -15190\n"
- "moveli r40, 208\n"
- "shl16insli r40, r40, 20913\n"
- "shl16insli r40, r40, 19131\n"
- "shl16insli r40, r40, -17081\n"
- "{ mz r47, r39, r40 ; fnop ; ld r63, r54 }\n"
- "move %0, r47\n"
- "move %1, r39\n"
- "move %2, r40\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_mz_Y1.c b/none/tests/tilegx/insn_test_mz_Y1.c
deleted file mode 100644
index 1046e3a..0000000
--- a/none/tests/tilegx/insn_test_mz_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_mz_Y1.c
-//op=177
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9b70a44aad51d91c, 0x67d733d090a0e0ad };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r47, -6674\n"
- "shl16insli r47, r47, -26653\n"
- "shl16insli r47, r47, -16240\n"
- "shl16insli r47, r47, 300\n"
- "moveli r39, -14350\n"
- "shl16insli r39, r39, -13718\n"
- "shl16insli r39, r39, -10168\n"
- "shl16insli r39, r39, -15190\n"
- "moveli r40, 208\n"
- "shl16insli r40, r40, 20913\n"
- "shl16insli r40, r40, 19131\n"
- "shl16insli r40, r40, -17081\n"
- "{ fnop ; mz r47, r39, r40 ; ld r63, r54 }\n"
- "move %0, r47\n"
- "move %1, r39\n"
- "move %2, r40\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_nop_X0.c b/none/tests/tilegx/insn_test_nop_X0.c
deleted file mode 100644
index 7d13191..0000000
--- a/none/tests/tilegx/insn_test_nop_X0.c
+++ /dev/null
@@ -1,24 +0,0 @@
-//file: _insn_test_nop_X0.c
-//op=179
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x592fbed956a8fd1f, 0xb149341116c1d072 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "{ nop ; fnop }\n"
- );
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_nop_X1.c b/none/tests/tilegx/insn_test_nop_X1.c
deleted file mode 100644
index 3bd4c91..0000000
--- a/none/tests/tilegx/insn_test_nop_X1.c
+++ /dev/null
@@ -1,24 +0,0 @@
-//file: _insn_test_nop_X1.c
-//op=179
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x592fbed956a8fd1f, 0xb149341116c1d072 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "{ fnop ; nop }\n"
- );
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_nop_Y0.c b/none/tests/tilegx/insn_test_nop_Y0.c
deleted file mode 100644
index c525921..0000000
--- a/none/tests/tilegx/insn_test_nop_Y0.c
+++ /dev/null
@@ -1,24 +0,0 @@
-//file: _insn_test_nop_Y0.c
-//op=179
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x592fbed956a8fd1f, 0xb149341116c1d072 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "{ nop ; fnop ; ld r63, r54 }\n"
- );
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_nop_Y1.c b/none/tests/tilegx/insn_test_nop_Y1.c
deleted file mode 100644
index 3a06aba..0000000
--- a/none/tests/tilegx/insn_test_nop_Y1.c
+++ /dev/null
@@ -1,24 +0,0 @@
-//file: _insn_test_nop_Y1.c
-//op=179
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x592fbed956a8fd1f, 0xb149341116c1d072 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "{ fnop ; nop ; ld r63, r54 }\n"
- );
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_nor_X0.c b/none/tests/tilegx/insn_test_nor_X0.c
deleted file mode 100644
index a86a1fb..0000000
--- a/none/tests/tilegx/insn_test_nor_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_nor_X0.c
-//op=180
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd104e6fedbd326fa, 0xa0df1db5b4273e63 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r22, 9517\n"
- "shl16insli r22, r22, -14743\n"
- "shl16insli r22, r22, 28886\n"
- "shl16insli r22, r22, 23646\n"
- "moveli r8, 31287\n"
- "shl16insli r8, r8, -16865\n"
- "shl16insli r8, r8, 32203\n"
- "shl16insli r8, r8, 26808\n"
- "moveli r7, -18162\n"
- "shl16insli r7, r7, 4413\n"
- "shl16insli r7, r7, 14247\n"
- "shl16insli r7, r7, 14892\n"
- "{ nor r22, r8, r7 ; fnop }\n"
- "move %0, r22\n"
- "move %1, r8\n"
- "move %2, r7\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_nor_X1.c b/none/tests/tilegx/insn_test_nor_X1.c
deleted file mode 100644
index 8b2ed2f..0000000
--- a/none/tests/tilegx/insn_test_nor_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_nor_X1.c
-//op=180
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd104e6fedbd326fa, 0xa0df1db5b4273e63 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r22, 9517\n"
- "shl16insli r22, r22, -14743\n"
- "shl16insli r22, r22, 28886\n"
- "shl16insli r22, r22, 23646\n"
- "moveli r8, 31287\n"
- "shl16insli r8, r8, -16865\n"
- "shl16insli r8, r8, 32203\n"
- "shl16insli r8, r8, 26808\n"
- "moveli r7, -18162\n"
- "shl16insli r7, r7, 4413\n"
- "shl16insli r7, r7, 14247\n"
- "shl16insli r7, r7, 14892\n"
- "{ fnop ; nor r22, r8, r7 }\n"
- "move %0, r22\n"
- "move %1, r8\n"
- "move %2, r7\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_nor_Y0.c b/none/tests/tilegx/insn_test_nor_Y0.c
deleted file mode 100644
index 558eb7f..0000000
--- a/none/tests/tilegx/insn_test_nor_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_nor_Y0.c
-//op=180
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd104e6fedbd326fa, 0xa0df1db5b4273e63 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r22, 9517\n"
- "shl16insli r22, r22, -14743\n"
- "shl16insli r22, r22, 28886\n"
- "shl16insli r22, r22, 23646\n"
- "moveli r8, 31287\n"
- "shl16insli r8, r8, -16865\n"
- "shl16insli r8, r8, 32203\n"
- "shl16insli r8, r8, 26808\n"
- "moveli r7, -18162\n"
- "shl16insli r7, r7, 4413\n"
- "shl16insli r7, r7, 14247\n"
- "shl16insli r7, r7, 14892\n"
- "{ nor r22, r8, r7 ; fnop ; ld r63, r54 }\n"
- "move %0, r22\n"
- "move %1, r8\n"
- "move %2, r7\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_nor_Y1.c b/none/tests/tilegx/insn_test_nor_Y1.c
deleted file mode 100644
index 8faa86b..0000000
--- a/none/tests/tilegx/insn_test_nor_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_nor_Y1.c
-//op=180
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd104e6fedbd326fa, 0xa0df1db5b4273e63 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r22, 9517\n"
- "shl16insli r22, r22, -14743\n"
- "shl16insli r22, r22, 28886\n"
- "shl16insli r22, r22, 23646\n"
- "moveli r8, 31287\n"
- "shl16insli r8, r8, -16865\n"
- "shl16insli r8, r8, 32203\n"
- "shl16insli r8, r8, 26808\n"
- "moveli r7, -18162\n"
- "shl16insli r7, r7, 4413\n"
- "shl16insli r7, r7, 14247\n"
- "shl16insli r7, r7, 14892\n"
- "{ fnop ; nor r22, r8, r7 ; ld r63, r54 }\n"
- "move %0, r22\n"
- "move %1, r8\n"
- "move %2, r7\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_or_X0.c b/none/tests/tilegx/insn_test_or_X0.c
deleted file mode 100644
index a2deee9..0000000
--- a/none/tests/tilegx/insn_test_or_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_or_X0.c
-//op=181
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xbda18e421a932d37, 0xe49de7021c00d425 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r13, 4269\n"
- "shl16insli r13, r13, 12585\n"
- "shl16insli r13, r13, 23528\n"
- "shl16insli r13, r13, -28113\n"
- "moveli r36, 3720\n"
- "shl16insli r36, r36, 21467\n"
- "shl16insli r36, r36, 16503\n"
- "shl16insli r36, r36, -15551\n"
- "moveli r7, -17228\n"
- "shl16insli r7, r7, -9907\n"
- "shl16insli r7, r7, 11604\n"
- "shl16insli r7, r7, -13348\n"
- "{ or r13, r36, r7 ; fnop }\n"
- "move %0, r13\n"
- "move %1, r36\n"
- "move %2, r7\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_or_X1.c b/none/tests/tilegx/insn_test_or_X1.c
deleted file mode 100644
index 91d51e1..0000000
--- a/none/tests/tilegx/insn_test_or_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_or_X1.c
-//op=181
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xbda18e421a932d37, 0xe49de7021c00d425 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r13, 4269\n"
- "shl16insli r13, r13, 12585\n"
- "shl16insli r13, r13, 23528\n"
- "shl16insli r13, r13, -28113\n"
- "moveli r36, 3720\n"
- "shl16insli r36, r36, 21467\n"
- "shl16insli r36, r36, 16503\n"
- "shl16insli r36, r36, -15551\n"
- "moveli r7, -17228\n"
- "shl16insli r7, r7, -9907\n"
- "shl16insli r7, r7, 11604\n"
- "shl16insli r7, r7, -13348\n"
- "{ fnop ; or r13, r36, r7 }\n"
- "move %0, r13\n"
- "move %1, r36\n"
- "move %2, r7\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_or_Y0.c b/none/tests/tilegx/insn_test_or_Y0.c
deleted file mode 100644
index e8576ea..0000000
--- a/none/tests/tilegx/insn_test_or_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_or_Y0.c
-//op=181
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xbda18e421a932d37, 0xe49de7021c00d425 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r13, 4269\n"
- "shl16insli r13, r13, 12585\n"
- "shl16insli r13, r13, 23528\n"
- "shl16insli r13, r13, -28113\n"
- "moveli r36, 3720\n"
- "shl16insli r36, r36, 21467\n"
- "shl16insli r36, r36, 16503\n"
- "shl16insli r36, r36, -15551\n"
- "moveli r7, -17228\n"
- "shl16insli r7, r7, -9907\n"
- "shl16insli r7, r7, 11604\n"
- "shl16insli r7, r7, -13348\n"
- "{ or r13, r36, r7 ; fnop ; ld r63, r54 }\n"
- "move %0, r13\n"
- "move %1, r36\n"
- "move %2, r7\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_or_Y1.c b/none/tests/tilegx/insn_test_or_Y1.c
deleted file mode 100644
index 43d1f2a..0000000
--- a/none/tests/tilegx/insn_test_or_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_or_Y1.c
-//op=181
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xbda18e421a932d37, 0xe49de7021c00d425 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r13, 4269\n"
- "shl16insli r13, r13, 12585\n"
- "shl16insli r13, r13, 23528\n"
- "shl16insli r13, r13, -28113\n"
- "moveli r36, 3720\n"
- "shl16insli r36, r36, 21467\n"
- "shl16insli r36, r36, 16503\n"
- "shl16insli r36, r36, -15551\n"
- "moveli r7, -17228\n"
- "shl16insli r7, r7, -9907\n"
- "shl16insli r7, r7, 11604\n"
- "shl16insli r7, r7, -13348\n"
- "{ fnop ; or r13, r36, r7 ; ld r63, r54 }\n"
- "move %0, r13\n"
- "move %1, r36\n"
- "move %2, r7\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ori_X0.c b/none/tests/tilegx/insn_test_ori_X0.c
deleted file mode 100644
index b4e22d9..0000000
--- a/none/tests/tilegx/insn_test_ori_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_ori_X0.c
-//op=182
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xfefebc9ad18eac85, 0x6bf7e8d962dcb3ff };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r40, 29084\n"
- "shl16insli r40, r40, 17620\n"
- "shl16insli r40, r40, -5765\n"
- "shl16insli r40, r40, 17748\n"
- "moveli r36, -12155\n"
- "shl16insli r36, r36, -29090\n"
- "shl16insli r36, r36, 11972\n"
- "shl16insli r36, r36, -26553\n"
- "{ ori r40, r36, 29 ; fnop }\n"
- "move %0, r40\n"
- "move %1, r36\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_ori_X1.c b/none/tests/tilegx/insn_test_ori_X1.c
deleted file mode 100644
index 8d524cc..0000000
--- a/none/tests/tilegx/insn_test_ori_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_ori_X1.c
-//op=182
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xfefebc9ad18eac85, 0x6bf7e8d962dcb3ff };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r40, 29084\n"
- "shl16insli r40, r40, 17620\n"
- "shl16insli r40, r40, -5765\n"
- "shl16insli r40, r40, 17748\n"
- "moveli r36, -12155\n"
- "shl16insli r36, r36, -29090\n"
- "shl16insli r36, r36, 11972\n"
- "shl16insli r36, r36, -26553\n"
- "{ fnop ; ori r40, r36, 29 }\n"
- "move %0, r40\n"
- "move %1, r36\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_pcnt_X0.c b/none/tests/tilegx/insn_test_pcnt_X0.c
deleted file mode 100644
index f2818c0..0000000
--- a/none/tests/tilegx/insn_test_pcnt_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_pcnt_X0.c
-//op=183
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x17cffec1aae5ac94, 0xc7c07a1c34655bf8 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r21, -18757\n"
- "shl16insli r21, r21, 26178\n"
- "shl16insli r21, r21, 32618\n"
- "shl16insli r21, r21, 22067\n"
- "moveli r31, -1083\n"
- "shl16insli r31, r31, 30832\n"
- "shl16insli r31, r31, 25967\n"
- "shl16insli r31, r31, 4463\n"
- "{ pcnt r21, r31 ; fnop }\n"
- "move %0, r21\n"
- "move %1, r31\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_pcnt_Y0.c b/none/tests/tilegx/insn_test_pcnt_Y0.c
deleted file mode 100644
index db18321..0000000
--- a/none/tests/tilegx/insn_test_pcnt_Y0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_pcnt_Y0.c
-//op=183
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x17cffec1aae5ac94, 0xc7c07a1c34655bf8 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r21, -18757\n"
- "shl16insli r21, r21, 26178\n"
- "shl16insli r21, r21, 32618\n"
- "shl16insli r21, r21, 22067\n"
- "moveli r31, -1083\n"
- "shl16insli r31, r31, 30832\n"
- "shl16insli r31, r31, 25967\n"
- "shl16insli r31, r31, 4463\n"
- "{ pcnt r21, r31 ; fnop ; ld r63, r54 }\n"
- "move %0, r21\n"
- "move %1, r31\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_prefetch_X1.c b/none/tests/tilegx/insn_test_prefetch_X1.c
deleted file mode 100644
index 639d501..0000000
--- a/none/tests/tilegx/insn_test_prefetch_X1.c
+++ /dev/null
@@ -1,30 +0,0 @@
-//file: _insn_test_prefetch_X1.c
-//op=8
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd941c90b89d1197b, 0x9f2fd3736342eb2e };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r5, -20979\n"
- "shl16insli r5, r5, 31723\n"
- "shl16insli r5, r5, 27537\n"
- "shl16insli r5, r5, -30979\n"
- "{ fnop ; prefetch r5 }\n"
- "move %0, r5\n"
- :"=r"(a[0]));
- printf("%016lx\n", a[0]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_prefetch_Y2.c b/none/tests/tilegx/insn_test_prefetch_Y2.c
deleted file mode 100644
index 5226cbb..0000000
--- a/none/tests/tilegx/insn_test_prefetch_Y2.c
+++ /dev/null
@@ -1,30 +0,0 @@
-//file: _insn_test_prefetch_Y2.c
-//op=8
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd941c90b89d1197b, 0x9f2fd3736342eb2e };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r5, -20979\n"
- "shl16insli r5, r5, 31723\n"
- "shl16insli r5, r5, 27537\n"
- "shl16insli r5, r5, -30979\n"
- "{ fnop ; fnop ; prefetch r5 }\n"
- "move %0, r5\n"
- :"=r"(a[0]));
- printf("%016lx\n", a[0]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_prefetch_l1_X1.c b/none/tests/tilegx/insn_test_prefetch_l1_X1.c
deleted file mode 100644
index 6b71a3c..0000000
--- a/none/tests/tilegx/insn_test_prefetch_l1_X1.c
+++ /dev/null
@@ -1,30 +0,0 @@
-//file: _insn_test_prefetch_l1_X1.c
-//op=15
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xbca200a47bf08fef, 0xcc8e27fe3fbcf86c };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r48, -10816\n"
- "shl16insli r48, r48, 15791\n"
- "shl16insli r48, r48, -20821\n"
- "shl16insli r48, r48, 20094\n"
- "{ fnop ; prefetch r48 }\n"
- "move %0, r48\n"
- :"=r"(a[0]));
- printf("%016lx\n", a[0]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_prefetch_l1_Y2.c b/none/tests/tilegx/insn_test_prefetch_l1_Y2.c
deleted file mode 100644
index 1b66ad0..0000000
--- a/none/tests/tilegx/insn_test_prefetch_l1_Y2.c
+++ /dev/null
@@ -1,30 +0,0 @@
-//file: _insn_test_prefetch_l1_Y2.c
-//op=15
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xbca200a47bf08fef, 0xcc8e27fe3fbcf86c };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r48, -10816\n"
- "shl16insli r48, r48, 15791\n"
- "shl16insli r48, r48, -20821\n"
- "shl16insli r48, r48, 20094\n"
- "{ fnop ; fnop ; prefetch r48 }\n"
- "move %0, r48\n"
- :"=r"(a[0]));
- printf("%016lx\n", a[0]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_prefetch_l2_X1.c b/none/tests/tilegx/insn_test_prefetch_l2_X1.c
deleted file mode 100644
index eca64a0..0000000
--- a/none/tests/tilegx/insn_test_prefetch_l2_X1.c
+++ /dev/null
@@ -1,30 +0,0 @@
-//file: _insn_test_prefetch_l2_X1.c
-//op=17
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xbcd5fb19de288be, 0x10f22adff1ed0182 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r48, 2029\n"
- "shl16insli r48, r48, -23766\n"
- "shl16insli r48, r48, -9681\n"
- "shl16insli r48, r48, 20576\n"
- "{ fnop ; prefetch_l2 r48 }\n"
- "move %0, r48\n"
- :"=r"(a[0]));
- printf("%016lx\n", a[0]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_prefetch_l2_Y2.c b/none/tests/tilegx/insn_test_prefetch_l2_Y2.c
deleted file mode 100644
index 142a648..0000000
--- a/none/tests/tilegx/insn_test_prefetch_l2_Y2.c
+++ /dev/null
@@ -1,30 +0,0 @@
-//file: _insn_test_prefetch_l2_Y2.c
-//op=17
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xbcd5fb19de288be, 0x10f22adff1ed0182 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r48, 2029\n"
- "shl16insli r48, r48, -23766\n"
- "shl16insli r48, r48, -9681\n"
- "shl16insli r48, r48, 20576\n"
- "{ fnop ; fnop ; prefetch_l2 r48 }\n"
- "move %0, r48\n"
- :"=r"(a[0]));
- printf("%016lx\n", a[0]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_prefetch_l3_X1.c b/none/tests/tilegx/insn_test_prefetch_l3_X1.c
deleted file mode 100644
index 0ffb076..0000000
--- a/none/tests/tilegx/insn_test_prefetch_l3_X1.c
+++ /dev/null
@@ -1,30 +0,0 @@
-//file: _insn_test_prefetch_l3_X1.c
-//op=19
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xb026dbf41e76db36, 0x3030888d84db4c82 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r13, 8736\n"
- "shl16insli r13, r13, -19069\n"
- "shl16insli r13, r13, -2177\n"
- "shl16insli r13, r13, 29968\n"
- "{ fnop ; prefetch_l3 r13 }\n"
- "move %0, r13\n"
- :"=r"(a[0]));
- printf("%016lx\n", a[0]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_prefetch_l3_Y2.c b/none/tests/tilegx/insn_test_prefetch_l3_Y2.c
deleted file mode 100644
index 5af7d41..0000000
--- a/none/tests/tilegx/insn_test_prefetch_l3_Y2.c
+++ /dev/null
@@ -1,30 +0,0 @@
-//file: _insn_test_prefetch_l3_Y2.c
-//op=19
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xb026dbf41e76db36, 0x3030888d84db4c82 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r13, 8736\n"
- "shl16insli r13, r13, -19069\n"
- "shl16insli r13, r13, -2177\n"
- "shl16insli r13, r13, 29968\n"
- "{ fnop ; fnop ; prefetch_l3 r13 }\n"
- "move %0, r13\n"
- :"=r"(a[0]));
- printf("%016lx\n", a[0]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_revbits_X0.c b/none/tests/tilegx/insn_test_revbits_X0.c
deleted file mode 100644
index 3711ac7..0000000
--- a/none/tests/tilegx/insn_test_revbits_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_revbits_X0.c
-//op=184
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x683c0bdf5b51687b, 0x82d752d6d5c34590 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r43, -27981\n"
- "shl16insli r43, r43, -3839\n"
- "shl16insli r43, r43, -10726\n"
- "shl16insli r43, r43, 16403\n"
- "moveli r48, 21888\n"
- "shl16insli r48, r48, -8663\n"
- "shl16insli r48, r48, -14905\n"
- "shl16insli r48, r48, -14362\n"
- "{ revbits r43, r48 ; fnop }\n"
- "move %0, r43\n"
- "move %1, r48\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_revbits_Y0.c b/none/tests/tilegx/insn_test_revbits_Y0.c
deleted file mode 100644
index 3898146..0000000
--- a/none/tests/tilegx/insn_test_revbits_Y0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_revbits_Y0.c
-//op=184
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x683c0bdf5b51687b, 0x82d752d6d5c34590 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r43, -27981\n"
- "shl16insli r43, r43, -3839\n"
- "shl16insli r43, r43, -10726\n"
- "shl16insli r43, r43, 16403\n"
- "moveli r48, 21888\n"
- "shl16insli r48, r48, -8663\n"
- "shl16insli r48, r48, -14905\n"
- "shl16insli r48, r48, -14362\n"
- "{ revbits r43, r48 ; fnop ; ld r63, r54 }\n"
- "move %0, r43\n"
- "move %1, r48\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_revbytes_X0.c b/none/tests/tilegx/insn_test_revbytes_X0.c
deleted file mode 100644
index 8f58aa0..0000000
--- a/none/tests/tilegx/insn_test_revbytes_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_revbytes_X0.c
-//op=185
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x8855e8634340c3dd, 0x83fe56474a5b5a36 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r38, 2393\n"
- "shl16insli r38, r38, 12415\n"
- "shl16insli r38, r38, -29425\n"
- "shl16insli r38, r38, -12730\n"
- "moveli r41, -12869\n"
- "shl16insli r41, r41, -19528\n"
- "shl16insli r41, r41, 27018\n"
- "shl16insli r41, r41, -20432\n"
- "{ revbytes r38, r41 ; fnop }\n"
- "move %0, r38\n"
- "move %1, r41\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_revbytes_Y0.c b/none/tests/tilegx/insn_test_revbytes_Y0.c
deleted file mode 100644
index d9ad9ad..0000000
--- a/none/tests/tilegx/insn_test_revbytes_Y0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_revbytes_Y0.c
-//op=185
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x8855e8634340c3dd, 0x83fe56474a5b5a36 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r38, 2393\n"
- "shl16insli r38, r38, 12415\n"
- "shl16insli r38, r38, -29425\n"
- "shl16insli r38, r38, -12730\n"
- "moveli r41, -12869\n"
- "shl16insli r41, r41, -19528\n"
- "shl16insli r41, r41, 27018\n"
- "shl16insli r41, r41, -20432\n"
- "{ revbytes r38, r41 ; fnop ; ld r63, r54 }\n"
- "move %0, r38\n"
- "move %1, r41\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_rotl_X0.c b/none/tests/tilegx/insn_test_rotl_X0.c
deleted file mode 100644
index b57885b..0000000
--- a/none/tests/tilegx/insn_test_rotl_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_rotl_X0.c
-//op=186
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9b125b6641bb9f39, 0x90ce422b64edc869 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r43, -17868\n"
- "shl16insli r43, r43, -15637\n"
- "shl16insli r43, r43, -21854\n"
- "shl16insli r43, r43, 31769\n"
- "moveli r22, -19055\n"
- "shl16insli r22, r22, -26082\n"
- "shl16insli r22, r22, -18335\n"
- "shl16insli r22, r22, -26425\n"
- "moveli r43, -28917\n"
- "shl16insli r43, r43, -6384\n"
- "shl16insli r43, r43, -11771\n"
- "shl16insli r43, r43, -16008\n"
- "{ rotl r43, r22, r43 ; fnop }\n"
- "move %0, r43\n"
- "move %1, r22\n"
- "move %2, r43\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_rotl_X1.c b/none/tests/tilegx/insn_test_rotl_X1.c
deleted file mode 100644
index 96bfcb4..0000000
--- a/none/tests/tilegx/insn_test_rotl_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_rotl_X1.c
-//op=186
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9b125b6641bb9f39, 0x90ce422b64edc869 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r43, -17868\n"
- "shl16insli r43, r43, -15637\n"
- "shl16insli r43, r43, -21854\n"
- "shl16insli r43, r43, 31769\n"
- "moveli r22, -19055\n"
- "shl16insli r22, r22, -26082\n"
- "shl16insli r22, r22, -18335\n"
- "shl16insli r22, r22, -26425\n"
- "moveli r43, -28917\n"
- "shl16insli r43, r43, -6384\n"
- "shl16insli r43, r43, -11771\n"
- "shl16insli r43, r43, -16008\n"
- "{ fnop ; rotl r43, r22, r43 }\n"
- "move %0, r43\n"
- "move %1, r22\n"
- "move %2, r43\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_rotl_Y0.c b/none/tests/tilegx/insn_test_rotl_Y0.c
deleted file mode 100644
index 4f097fb..0000000
--- a/none/tests/tilegx/insn_test_rotl_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_rotl_Y0.c
-//op=186
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9b125b6641bb9f39, 0x90ce422b64edc869 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r43, -17868\n"
- "shl16insli r43, r43, -15637\n"
- "shl16insli r43, r43, -21854\n"
- "shl16insli r43, r43, 31769\n"
- "moveli r22, -19055\n"
- "shl16insli r22, r22, -26082\n"
- "shl16insli r22, r22, -18335\n"
- "shl16insli r22, r22, -26425\n"
- "moveli r43, -28917\n"
- "shl16insli r43, r43, -6384\n"
- "shl16insli r43, r43, -11771\n"
- "shl16insli r43, r43, -16008\n"
- "{ rotl r43, r22, r43 ; fnop ; ld r63, r54 }\n"
- "move %0, r43\n"
- "move %1, r22\n"
- "move %2, r43\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_rotl_Y1.c b/none/tests/tilegx/insn_test_rotl_Y1.c
deleted file mode 100644
index e414352..0000000
--- a/none/tests/tilegx/insn_test_rotl_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_rotl_Y1.c
-//op=186
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9b125b6641bb9f39, 0x90ce422b64edc869 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r43, -17868\n"
- "shl16insli r43, r43, -15637\n"
- "shl16insli r43, r43, -21854\n"
- "shl16insli r43, r43, 31769\n"
- "moveli r22, -19055\n"
- "shl16insli r22, r22, -26082\n"
- "shl16insli r22, r22, -18335\n"
- "shl16insli r22, r22, -26425\n"
- "moveli r43, -28917\n"
- "shl16insli r43, r43, -6384\n"
- "shl16insli r43, r43, -11771\n"
- "shl16insli r43, r43, -16008\n"
- "{ fnop ; rotl r43, r22, r43 ; ld r63, r54 }\n"
- "move %0, r43\n"
- "move %1, r22\n"
- "move %2, r43\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_rotli_X0.c b/none/tests/tilegx/insn_test_rotli_X0.c
deleted file mode 100644
index ac473a1..0000000
--- a/none/tests/tilegx/insn_test_rotli_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_rotli_X0.c
-//op=187
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x7703657413b27076, 0x1bee8662fa44392b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r38, 16585\n"
- "shl16insli r38, r38, 19462\n"
- "shl16insli r38, r38, 29122\n"
- "shl16insli r38, r38, -30058\n"
- "moveli r7, 3682\n"
- "shl16insli r7, r7, 7348\n"
- "shl16insli r7, r7, -12127\n"
- "shl16insli r7, r7, 24558\n"
- "{ rotli r38, r7, 53 ; fnop }\n"
- "move %0, r38\n"
- "move %1, r7\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_rotli_X1.c b/none/tests/tilegx/insn_test_rotli_X1.c
deleted file mode 100644
index 1552082..0000000
--- a/none/tests/tilegx/insn_test_rotli_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_rotli_X1.c
-//op=187
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x7703657413b27076, 0x1bee8662fa44392b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r38, 16585\n"
- "shl16insli r38, r38, 19462\n"
- "shl16insli r38, r38, 29122\n"
- "shl16insli r38, r38, -30058\n"
- "moveli r7, 3682\n"
- "shl16insli r7, r7, 7348\n"
- "shl16insli r7, r7, -12127\n"
- "shl16insli r7, r7, 24558\n"
- "{ fnop ; rotli r38, r7, 53 }\n"
- "move %0, r38\n"
- "move %1, r7\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_rotli_Y0.c b/none/tests/tilegx/insn_test_rotli_Y0.c
deleted file mode 100644
index bb5188f..0000000
--- a/none/tests/tilegx/insn_test_rotli_Y0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_rotli_Y0.c
-//op=187
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x7703657413b27076, 0x1bee8662fa44392b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r38, 16585\n"
- "shl16insli r38, r38, 19462\n"
- "shl16insli r38, r38, 29122\n"
- "shl16insli r38, r38, -30058\n"
- "moveli r7, 3682\n"
- "shl16insli r7, r7, 7348\n"
- "shl16insli r7, r7, -12127\n"
- "shl16insli r7, r7, 24558\n"
- "{ rotli r38, r7, 53 ; fnop ; ld r63, r54 }\n"
- "move %0, r38\n"
- "move %1, r7\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_rotli_Y1.c b/none/tests/tilegx/insn_test_rotli_Y1.c
deleted file mode 100644
index 695a3fe..0000000
--- a/none/tests/tilegx/insn_test_rotli_Y1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_rotli_Y1.c
-//op=187
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x7703657413b27076, 0x1bee8662fa44392b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r38, 16585\n"
- "shl16insli r38, r38, 19462\n"
- "shl16insli r38, r38, 29122\n"
- "shl16insli r38, r38, -30058\n"
- "moveli r7, 3682\n"
- "shl16insli r7, r7, 7348\n"
- "shl16insli r7, r7, -12127\n"
- "shl16insli r7, r7, 24558\n"
- "{ fnop ; rotli r38, r7, 53 ; ld r63, r54 }\n"
- "move %0, r38\n"
- "move %1, r7\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl16insli_X0.c b/none/tests/tilegx/insn_test_shl16insli_X0.c
deleted file mode 100644
index 4d3addd..0000000
--- a/none/tests/tilegx/insn_test_shl16insli_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_shl16insli_X0.c
-//op=189
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x842f1ff3b535c0ff, 0xb4e168d3b1d1a300 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r29, -11895\n"
- "shl16insli r29, r29, 21718\n"
- "shl16insli r29, r29, -14088\n"
- "shl16insli r29, r29, -5322\n"
- "moveli r27, -18517\n"
- "shl16insli r27, r27, 12387\n"
- "shl16insli r27, r27, 27111\n"
- "shl16insli r27, r27, 15808\n"
- "{ shl16insli r29, r27, -27202 ; fnop }\n"
- "move %0, r29\n"
- "move %1, r27\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl16insli_X1.c b/none/tests/tilegx/insn_test_shl16insli_X1.c
deleted file mode 100644
index 4b30057..0000000
--- a/none/tests/tilegx/insn_test_shl16insli_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_shl16insli_X1.c
-//op=189
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x842f1ff3b535c0ff, 0xb4e168d3b1d1a300 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r29, -11895\n"
- "shl16insli r29, r29, 21718\n"
- "shl16insli r29, r29, -14088\n"
- "shl16insli r29, r29, -5322\n"
- "moveli r27, -18517\n"
- "shl16insli r27, r27, 12387\n"
- "shl16insli r27, r27, 27111\n"
- "shl16insli r27, r27, 15808\n"
- "{ fnop ; shl16insli r29, r27, -27202 }\n"
- "move %0, r29\n"
- "move %1, r27\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl1add_X0.c b/none/tests/tilegx/insn_test_shl1add_X0.c
deleted file mode 100644
index 1468ac4..0000000
--- a/none/tests/tilegx/insn_test_shl1add_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl1add_X0.c
-//op=190
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x811d401994a9cbd4, 0xc39a04b8ff503c88 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r36, 30711\n"
- "shl16insli r36, r36, -23959\n"
- "shl16insli r36, r36, 22299\n"
- "shl16insli r36, r36, 25192\n"
- "moveli r33, 24574\n"
- "shl16insli r33, r33, -7860\n"
- "shl16insli r33, r33, 22844\n"
- "shl16insli r33, r33, -25856\n"
- "moveli r3, -8773\n"
- "shl16insli r3, r3, 2664\n"
- "shl16insli r3, r3, -12396\n"
- "shl16insli r3, r3, -20538\n"
- "{ shl1add r36, r33, r3 ; fnop }\n"
- "move %0, r36\n"
- "move %1, r33\n"
- "move %2, r3\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl1add_X1.c b/none/tests/tilegx/insn_test_shl1add_X1.c
deleted file mode 100644
index ca4566a..0000000
--- a/none/tests/tilegx/insn_test_shl1add_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl1add_X1.c
-//op=190
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x811d401994a9cbd4, 0xc39a04b8ff503c88 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r36, 30711\n"
- "shl16insli r36, r36, -23959\n"
- "shl16insli r36, r36, 22299\n"
- "shl16insli r36, r36, 25192\n"
- "moveli r33, 24574\n"
- "shl16insli r33, r33, -7860\n"
- "shl16insli r33, r33, 22844\n"
- "shl16insli r33, r33, -25856\n"
- "moveli r3, -8773\n"
- "shl16insli r3, r3, 2664\n"
- "shl16insli r3, r3, -12396\n"
- "shl16insli r3, r3, -20538\n"
- "{ fnop ; shl1add r36, r33, r3 }\n"
- "move %0, r36\n"
- "move %1, r33\n"
- "move %2, r3\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl1add_Y0.c b/none/tests/tilegx/insn_test_shl1add_Y0.c
deleted file mode 100644
index 2f78c35..0000000
--- a/none/tests/tilegx/insn_test_shl1add_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl1add_Y0.c
-//op=190
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x811d401994a9cbd4, 0xc39a04b8ff503c88 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r36, 30711\n"
- "shl16insli r36, r36, -23959\n"
- "shl16insli r36, r36, 22299\n"
- "shl16insli r36, r36, 25192\n"
- "moveli r33, 24574\n"
- "shl16insli r33, r33, -7860\n"
- "shl16insli r33, r33, 22844\n"
- "shl16insli r33, r33, -25856\n"
- "moveli r3, -8773\n"
- "shl16insli r3, r3, 2664\n"
- "shl16insli r3, r3, -12396\n"
- "shl16insli r3, r3, -20538\n"
- "{ shl1add r36, r33, r3 ; fnop ; ld r63, r54 }\n"
- "move %0, r36\n"
- "move %1, r33\n"
- "move %2, r3\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl1add_Y1.c b/none/tests/tilegx/insn_test_shl1add_Y1.c
deleted file mode 100644
index 8e9a4a7..0000000
--- a/none/tests/tilegx/insn_test_shl1add_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl1add_Y1.c
-//op=190
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x811d401994a9cbd4, 0xc39a04b8ff503c88 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r36, 30711\n"
- "shl16insli r36, r36, -23959\n"
- "shl16insli r36, r36, 22299\n"
- "shl16insli r36, r36, 25192\n"
- "moveli r33, 24574\n"
- "shl16insli r33, r33, -7860\n"
- "shl16insli r33, r33, 22844\n"
- "shl16insli r33, r33, -25856\n"
- "moveli r3, -8773\n"
- "shl16insli r3, r3, 2664\n"
- "shl16insli r3, r3, -12396\n"
- "shl16insli r3, r3, -20538\n"
- "{ fnop ; shl1add r36, r33, r3 ; ld r63, r54 }\n"
- "move %0, r36\n"
- "move %1, r33\n"
- "move %2, r3\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl1addx_X0.c b/none/tests/tilegx/insn_test_shl1addx_X0.c
deleted file mode 100644
index e25f8a3..0000000
--- a/none/tests/tilegx/insn_test_shl1addx_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl1addx_X0.c
-//op=191
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xf057c60d59f89641, 0xa3975d48e8f324d7 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r46, -17307\n"
- "shl16insli r46, r46, 5811\n"
- "shl16insli r46, r46, -14070\n"
- "shl16insli r46, r46, 1938\n"
- "moveli r24, 31602\n"
- "shl16insli r24, r24, 20410\n"
- "shl16insli r24, r24, 32651\n"
- "shl16insli r24, r24, -17296\n"
- "moveli r33, 1206\n"
- "shl16insli r33, r33, 4007\n"
- "shl16insli r33, r33, -27712\n"
- "shl16insli r33, r33, 3824\n"
- "{ shl1addx r46, r24, r33 ; fnop }\n"
- "move %0, r46\n"
- "move %1, r24\n"
- "move %2, r33\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl1addx_X1.c b/none/tests/tilegx/insn_test_shl1addx_X1.c
deleted file mode 100644
index dff1075..0000000
--- a/none/tests/tilegx/insn_test_shl1addx_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl1addx_X1.c
-//op=191
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xf057c60d59f89641, 0xa3975d48e8f324d7 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r46, -17307\n"
- "shl16insli r46, r46, 5811\n"
- "shl16insli r46, r46, -14070\n"
- "shl16insli r46, r46, 1938\n"
- "moveli r24, 31602\n"
- "shl16insli r24, r24, 20410\n"
- "shl16insli r24, r24, 32651\n"
- "shl16insli r24, r24, -17296\n"
- "moveli r33, 1206\n"
- "shl16insli r33, r33, 4007\n"
- "shl16insli r33, r33, -27712\n"
- "shl16insli r33, r33, 3824\n"
- "{ fnop ; shl1addx r46, r24, r33 }\n"
- "move %0, r46\n"
- "move %1, r24\n"
- "move %2, r33\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl1addx_Y0.c b/none/tests/tilegx/insn_test_shl1addx_Y0.c
deleted file mode 100644
index 6a5aa88..0000000
--- a/none/tests/tilegx/insn_test_shl1addx_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl1addx_Y0.c
-//op=191
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xf057c60d59f89641, 0xa3975d48e8f324d7 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r46, -17307\n"
- "shl16insli r46, r46, 5811\n"
- "shl16insli r46, r46, -14070\n"
- "shl16insli r46, r46, 1938\n"
- "moveli r24, 31602\n"
- "shl16insli r24, r24, 20410\n"
- "shl16insli r24, r24, 32651\n"
- "shl16insli r24, r24, -17296\n"
- "moveli r33, 1206\n"
- "shl16insli r33, r33, 4007\n"
- "shl16insli r33, r33, -27712\n"
- "shl16insli r33, r33, 3824\n"
- "{ shl1addx r46, r24, r33 ; fnop ; ld r63, r54 }\n"
- "move %0, r46\n"
- "move %1, r24\n"
- "move %2, r33\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl1addx_Y1.c b/none/tests/tilegx/insn_test_shl1addx_Y1.c
deleted file mode 100644
index 31ee968..0000000
--- a/none/tests/tilegx/insn_test_shl1addx_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl1addx_Y1.c
-//op=191
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xf057c60d59f89641, 0xa3975d48e8f324d7 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r46, -17307\n"
- "shl16insli r46, r46, 5811\n"
- "shl16insli r46, r46, -14070\n"
- "shl16insli r46, r46, 1938\n"
- "moveli r24, 31602\n"
- "shl16insli r24, r24, 20410\n"
- "shl16insli r24, r24, 32651\n"
- "shl16insli r24, r24, -17296\n"
- "moveli r33, 1206\n"
- "shl16insli r33, r33, 4007\n"
- "shl16insli r33, r33, -27712\n"
- "shl16insli r33, r33, 3824\n"
- "{ fnop ; shl1addx r46, r24, r33 ; ld r63, r54 }\n"
- "move %0, r46\n"
- "move %1, r24\n"
- "move %2, r33\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl2add_X0.c b/none/tests/tilegx/insn_test_shl2add_X0.c
deleted file mode 100644
index 7085cf9..0000000
--- a/none/tests/tilegx/insn_test_shl2add_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl2add_X0.c
-//op=192
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x7c6741cd8294f113, 0x7df20b112210ce2f };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r0, -28670\n"
- "shl16insli r0, r0, -6265\n"
- "shl16insli r0, r0, 15425\n"
- "shl16insli r0, r0, 17326\n"
- "moveli r19, 7596\n"
- "shl16insli r19, r19, -10648\n"
- "shl16insli r19, r19, 15573\n"
- "shl16insli r19, r19, -25790\n"
- "moveli r43, -7218\n"
- "shl16insli r43, r43, 7896\n"
- "shl16insli r43, r43, -22888\n"
- "shl16insli r43, r43, -25968\n"
- "{ shl2add r0, r19, r43 ; fnop }\n"
- "move %0, r0\n"
- "move %1, r19\n"
- "move %2, r43\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl2add_X1.c b/none/tests/tilegx/insn_test_shl2add_X1.c
deleted file mode 100644
index 7edbdb1..0000000
--- a/none/tests/tilegx/insn_test_shl2add_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl2add_X1.c
-//op=192
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x7c6741cd8294f113, 0x7df20b112210ce2f };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r0, -28670\n"
- "shl16insli r0, r0, -6265\n"
- "shl16insli r0, r0, 15425\n"
- "shl16insli r0, r0, 17326\n"
- "moveli r19, 7596\n"
- "shl16insli r19, r19, -10648\n"
- "shl16insli r19, r19, 15573\n"
- "shl16insli r19, r19, -25790\n"
- "moveli r43, -7218\n"
- "shl16insli r43, r43, 7896\n"
- "shl16insli r43, r43, -22888\n"
- "shl16insli r43, r43, -25968\n"
- "{ fnop ; shl2add r0, r19, r43 }\n"
- "move %0, r0\n"
- "move %1, r19\n"
- "move %2, r43\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl2add_Y0.c b/none/tests/tilegx/insn_test_shl2add_Y0.c
deleted file mode 100644
index 0820039..0000000
--- a/none/tests/tilegx/insn_test_shl2add_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl2add_Y0.c
-//op=192
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x7c6741cd8294f113, 0x7df20b112210ce2f };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r0, -28670\n"
- "shl16insli r0, r0, -6265\n"
- "shl16insli r0, r0, 15425\n"
- "shl16insli r0, r0, 17326\n"
- "moveli r19, 7596\n"
- "shl16insli r19, r19, -10648\n"
- "shl16insli r19, r19, 15573\n"
- "shl16insli r19, r19, -25790\n"
- "moveli r43, -7218\n"
- "shl16insli r43, r43, 7896\n"
- "shl16insli r43, r43, -22888\n"
- "shl16insli r43, r43, -25968\n"
- "{ shl2add r0, r19, r43 ; fnop ; ld r63, r54 }\n"
- "move %0, r0\n"
- "move %1, r19\n"
- "move %2, r43\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl2add_Y1.c b/none/tests/tilegx/insn_test_shl2add_Y1.c
deleted file mode 100644
index e24a20e..0000000
--- a/none/tests/tilegx/insn_test_shl2add_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl2add_Y1.c
-//op=192
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x7c6741cd8294f113, 0x7df20b112210ce2f };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r0, -28670\n"
- "shl16insli r0, r0, -6265\n"
- "shl16insli r0, r0, 15425\n"
- "shl16insli r0, r0, 17326\n"
- "moveli r19, 7596\n"
- "shl16insli r19, r19, -10648\n"
- "shl16insli r19, r19, 15573\n"
- "shl16insli r19, r19, -25790\n"
- "moveli r43, -7218\n"
- "shl16insli r43, r43, 7896\n"
- "shl16insli r43, r43, -22888\n"
- "shl16insli r43, r43, -25968\n"
- "{ fnop ; shl2add r0, r19, r43 ; ld r63, r54 }\n"
- "move %0, r0\n"
- "move %1, r19\n"
- "move %2, r43\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl2addx_X0.c b/none/tests/tilegx/insn_test_shl2addx_X0.c
deleted file mode 100644
index 611c8ae..0000000
--- a/none/tests/tilegx/insn_test_shl2addx_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl2addx_X0.c
-//op=193
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x853e551b961eaa4c, 0x7867e09f71095915 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r50, -28023\n"
- "shl16insli r50, r50, -28331\n"
- "shl16insli r50, r50, 32085\n"
- "shl16insli r50, r50, -17473\n"
- "moveli r49, -5833\n"
- "shl16insli r49, r49, -31753\n"
- "shl16insli r49, r49, -27071\n"
- "shl16insli r49, r49, -23683\n"
- "moveli r21, 6443\n"
- "shl16insli r21, r21, 17296\n"
- "shl16insli r21, r21, 8461\n"
- "shl16insli r21, r21, -6245\n"
- "{ shl2addx r50, r49, r21 ; fnop }\n"
- "move %0, r50\n"
- "move %1, r49\n"
- "move %2, r21\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl2addx_X1.c b/none/tests/tilegx/insn_test_shl2addx_X1.c
deleted file mode 100644
index f0164f6..0000000
--- a/none/tests/tilegx/insn_test_shl2addx_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl2addx_X1.c
-//op=193
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x853e551b961eaa4c, 0x7867e09f71095915 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r50, -28023\n"
- "shl16insli r50, r50, -28331\n"
- "shl16insli r50, r50, 32085\n"
- "shl16insli r50, r50, -17473\n"
- "moveli r49, -5833\n"
- "shl16insli r49, r49, -31753\n"
- "shl16insli r49, r49, -27071\n"
- "shl16insli r49, r49, -23683\n"
- "moveli r21, 6443\n"
- "shl16insli r21, r21, 17296\n"
- "shl16insli r21, r21, 8461\n"
- "shl16insli r21, r21, -6245\n"
- "{ fnop ; shl2addx r50, r49, r21 }\n"
- "move %0, r50\n"
- "move %1, r49\n"
- "move %2, r21\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl2addx_Y0.c b/none/tests/tilegx/insn_test_shl2addx_Y0.c
deleted file mode 100644
index d4b7586..0000000
--- a/none/tests/tilegx/insn_test_shl2addx_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl2addx_Y0.c
-//op=193
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x853e551b961eaa4c, 0x7867e09f71095915 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r50, -28023\n"
- "shl16insli r50, r50, -28331\n"
- "shl16insli r50, r50, 32085\n"
- "shl16insli r50, r50, -17473\n"
- "moveli r49, -5833\n"
- "shl16insli r49, r49, -31753\n"
- "shl16insli r49, r49, -27071\n"
- "shl16insli r49, r49, -23683\n"
- "moveli r21, 6443\n"
- "shl16insli r21, r21, 17296\n"
- "shl16insli r21, r21, 8461\n"
- "shl16insli r21, r21, -6245\n"
- "{ shl2addx r50, r49, r21 ; fnop ; ld r63, r54 }\n"
- "move %0, r50\n"
- "move %1, r49\n"
- "move %2, r21\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl2addx_Y1.c b/none/tests/tilegx/insn_test_shl2addx_Y1.c
deleted file mode 100644
index e191e2e..0000000
--- a/none/tests/tilegx/insn_test_shl2addx_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl2addx_Y1.c
-//op=193
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x853e551b961eaa4c, 0x7867e09f71095915 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r50, -28023\n"
- "shl16insli r50, r50, -28331\n"
- "shl16insli r50, r50, 32085\n"
- "shl16insli r50, r50, -17473\n"
- "moveli r49, -5833\n"
- "shl16insli r49, r49, -31753\n"
- "shl16insli r49, r49, -27071\n"
- "shl16insli r49, r49, -23683\n"
- "moveli r21, 6443\n"
- "shl16insli r21, r21, 17296\n"
- "shl16insli r21, r21, 8461\n"
- "shl16insli r21, r21, -6245\n"
- "{ fnop ; shl2addx r50, r49, r21 ; ld r63, r54 }\n"
- "move %0, r50\n"
- "move %1, r49\n"
- "move %2, r21\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl3add_X0.c b/none/tests/tilegx/insn_test_shl3add_X0.c
deleted file mode 100644
index ea72911..0000000
--- a/none/tests/tilegx/insn_test_shl3add_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl3add_X0.c
-//op=194
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc8704900d8de98e2, 0xdeb2133cfb2c5342 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r9, 9269\n"
- "shl16insli r9, r9, 23416\n"
- "shl16insli r9, r9, -14988\n"
- "shl16insli r9, r9, 22168\n"
- "moveli r44, -12324\n"
- "shl16insli r44, r44, -28627\n"
- "shl16insli r44, r44, 16604\n"
- "shl16insli r44, r44, -17536\n"
- "moveli r1, 7448\n"
- "shl16insli r1, r1, 10894\n"
- "shl16insli r1, r1, 29909\n"
- "shl16insli r1, r1, 28991\n"
- "{ shl3add r9, r44, r1 ; fnop }\n"
- "move %0, r9\n"
- "move %1, r44\n"
- "move %2, r1\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl3add_X1.c b/none/tests/tilegx/insn_test_shl3add_X1.c
deleted file mode 100644
index 702ba90..0000000
--- a/none/tests/tilegx/insn_test_shl3add_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl3add_X1.c
-//op=194
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc8704900d8de98e2, 0xdeb2133cfb2c5342 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r9, 9269\n"
- "shl16insli r9, r9, 23416\n"
- "shl16insli r9, r9, -14988\n"
- "shl16insli r9, r9, 22168\n"
- "moveli r44, -12324\n"
- "shl16insli r44, r44, -28627\n"
- "shl16insli r44, r44, 16604\n"
- "shl16insli r44, r44, -17536\n"
- "moveli r1, 7448\n"
- "shl16insli r1, r1, 10894\n"
- "shl16insli r1, r1, 29909\n"
- "shl16insli r1, r1, 28991\n"
- "{ fnop ; shl3add r9, r44, r1 }\n"
- "move %0, r9\n"
- "move %1, r44\n"
- "move %2, r1\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl3add_Y0.c b/none/tests/tilegx/insn_test_shl3add_Y0.c
deleted file mode 100644
index 91d353a..0000000
--- a/none/tests/tilegx/insn_test_shl3add_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl3add_Y0.c
-//op=194
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc8704900d8de98e2, 0xdeb2133cfb2c5342 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r9, 9269\n"
- "shl16insli r9, r9, 23416\n"
- "shl16insli r9, r9, -14988\n"
- "shl16insli r9, r9, 22168\n"
- "moveli r44, -12324\n"
- "shl16insli r44, r44, -28627\n"
- "shl16insli r44, r44, 16604\n"
- "shl16insli r44, r44, -17536\n"
- "moveli r1, 7448\n"
- "shl16insli r1, r1, 10894\n"
- "shl16insli r1, r1, 29909\n"
- "shl16insli r1, r1, 28991\n"
- "{ shl3add r9, r44, r1 ; fnop ; ld r63, r54 }\n"
- "move %0, r9\n"
- "move %1, r44\n"
- "move %2, r1\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl3add_Y1.c b/none/tests/tilegx/insn_test_shl3add_Y1.c
deleted file mode 100644
index de28d4f..0000000
--- a/none/tests/tilegx/insn_test_shl3add_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl3add_Y1.c
-//op=194
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc8704900d8de98e2, 0xdeb2133cfb2c5342 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r9, 9269\n"
- "shl16insli r9, r9, 23416\n"
- "shl16insli r9, r9, -14988\n"
- "shl16insli r9, r9, 22168\n"
- "moveli r44, -12324\n"
- "shl16insli r44, r44, -28627\n"
- "shl16insli r44, r44, 16604\n"
- "shl16insli r44, r44, -17536\n"
- "moveli r1, 7448\n"
- "shl16insli r1, r1, 10894\n"
- "shl16insli r1, r1, 29909\n"
- "shl16insli r1, r1, 28991\n"
- "{ fnop ; shl3add r9, r44, r1 ; ld r63, r54 }\n"
- "move %0, r9\n"
- "move %1, r44\n"
- "move %2, r1\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl3addx_X0.c b/none/tests/tilegx/insn_test_shl3addx_X0.c
deleted file mode 100644
index 754ee78..0000000
--- a/none/tests/tilegx/insn_test_shl3addx_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl3addx_X0.c
-//op=195
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x5d526fffff5940db, 0x85ff61d332ccdd58 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r2, 6570\n"
- "shl16insli r2, r2, -30096\n"
- "shl16insli r2, r2, -3418\n"
- "shl16insli r2, r2, 9405\n"
- "moveli r11, -1170\n"
- "shl16insli r11, r11, -1505\n"
- "shl16insli r11, r11, -1810\n"
- "shl16insli r11, r11, 12649\n"
- "moveli r17, -7548\n"
- "shl16insli r17, r17, -12942\n"
- "shl16insli r17, r17, -2876\n"
- "shl16insli r17, r17, 29349\n"
- "{ shl3addx r2, r11, r17 ; fnop }\n"
- "move %0, r2\n"
- "move %1, r11\n"
- "move %2, r17\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl3addx_X1.c b/none/tests/tilegx/insn_test_shl3addx_X1.c
deleted file mode 100644
index 9296c71..0000000
--- a/none/tests/tilegx/insn_test_shl3addx_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl3addx_X1.c
-//op=195
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x5d526fffff5940db, 0x85ff61d332ccdd58 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r2, 6570\n"
- "shl16insli r2, r2, -30096\n"
- "shl16insli r2, r2, -3418\n"
- "shl16insli r2, r2, 9405\n"
- "moveli r11, -1170\n"
- "shl16insli r11, r11, -1505\n"
- "shl16insli r11, r11, -1810\n"
- "shl16insli r11, r11, 12649\n"
- "moveli r17, -7548\n"
- "shl16insli r17, r17, -12942\n"
- "shl16insli r17, r17, -2876\n"
- "shl16insli r17, r17, 29349\n"
- "{ fnop ; shl3addx r2, r11, r17 }\n"
- "move %0, r2\n"
- "move %1, r11\n"
- "move %2, r17\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl3addx_Y0.c b/none/tests/tilegx/insn_test_shl3addx_Y0.c
deleted file mode 100644
index e38b9f9..0000000
--- a/none/tests/tilegx/insn_test_shl3addx_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl3addx_Y0.c
-//op=195
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x5d526fffff5940db, 0x85ff61d332ccdd58 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r2, 6570\n"
- "shl16insli r2, r2, -30096\n"
- "shl16insli r2, r2, -3418\n"
- "shl16insli r2, r2, 9405\n"
- "moveli r11, -1170\n"
- "shl16insli r11, r11, -1505\n"
- "shl16insli r11, r11, -1810\n"
- "shl16insli r11, r11, 12649\n"
- "moveli r17, -7548\n"
- "shl16insli r17, r17, -12942\n"
- "shl16insli r17, r17, -2876\n"
- "shl16insli r17, r17, 29349\n"
- "{ shl3addx r2, r11, r17 ; fnop ; ld r63, r54 }\n"
- "move %0, r2\n"
- "move %1, r11\n"
- "move %2, r17\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl3addx_Y1.c b/none/tests/tilegx/insn_test_shl3addx_Y1.c
deleted file mode 100644
index 43923be..0000000
--- a/none/tests/tilegx/insn_test_shl3addx_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl3addx_Y1.c
-//op=195
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x5d526fffff5940db, 0x85ff61d332ccdd58 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r2, 6570\n"
- "shl16insli r2, r2, -30096\n"
- "shl16insli r2, r2, -3418\n"
- "shl16insli r2, r2, 9405\n"
- "moveli r11, -1170\n"
- "shl16insli r11, r11, -1505\n"
- "shl16insli r11, r11, -1810\n"
- "shl16insli r11, r11, 12649\n"
- "moveli r17, -7548\n"
- "shl16insli r17, r17, -12942\n"
- "shl16insli r17, r17, -2876\n"
- "shl16insli r17, r17, 29349\n"
- "{ fnop ; shl3addx r2, r11, r17 ; ld r63, r54 }\n"
- "move %0, r2\n"
- "move %1, r11\n"
- "move %2, r17\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl_X0.c b/none/tests/tilegx/insn_test_shl_X0.c
deleted file mode 100644
index cb48a17..0000000
--- a/none/tests/tilegx/insn_test_shl_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl_X0.c
-//op=188
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x53094f44a07b725d, 0xe61730d0d9026b62 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r23, -28145\n"
- "shl16insli r23, r23, -7915\n"
- "shl16insli r23, r23, 2786\n"
- "shl16insli r23, r23, 4140\n"
- "moveli r19, -17474\n"
- "shl16insli r19, r19, 5541\n"
- "shl16insli r19, r19, 25238\n"
- "shl16insli r19, r19, 6803\n"
- "moveli r48, -9071\n"
- "shl16insli r48, r48, -18527\n"
- "shl16insli r48, r48, -17369\n"
- "shl16insli r48, r48, 13142\n"
- "{ shl r23, r19, r48 ; fnop }\n"
- "move %0, r23\n"
- "move %1, r19\n"
- "move %2, r48\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl_X1.c b/none/tests/tilegx/insn_test_shl_X1.c
deleted file mode 100644
index aae8993..0000000
--- a/none/tests/tilegx/insn_test_shl_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl_X1.c
-//op=188
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x53094f44a07b725d, 0xe61730d0d9026b62 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r23, -28145\n"
- "shl16insli r23, r23, -7915\n"
- "shl16insli r23, r23, 2786\n"
- "shl16insli r23, r23, 4140\n"
- "moveli r19, -17474\n"
- "shl16insli r19, r19, 5541\n"
- "shl16insli r19, r19, 25238\n"
- "shl16insli r19, r19, 6803\n"
- "moveli r48, -9071\n"
- "shl16insli r48, r48, -18527\n"
- "shl16insli r48, r48, -17369\n"
- "shl16insli r48, r48, 13142\n"
- "{ fnop ; shl r23, r19, r48 }\n"
- "move %0, r23\n"
- "move %1, r19\n"
- "move %2, r48\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl_Y0.c b/none/tests/tilegx/insn_test_shl_Y0.c
deleted file mode 100644
index bdb4360..0000000
--- a/none/tests/tilegx/insn_test_shl_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl_Y0.c
-//op=188
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x53094f44a07b725d, 0xe61730d0d9026b62 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r23, -28145\n"
- "shl16insli r23, r23, -7915\n"
- "shl16insli r23, r23, 2786\n"
- "shl16insli r23, r23, 4140\n"
- "moveli r19, -17474\n"
- "shl16insli r19, r19, 5541\n"
- "shl16insli r19, r19, 25238\n"
- "shl16insli r19, r19, 6803\n"
- "moveli r48, -9071\n"
- "shl16insli r48, r48, -18527\n"
- "shl16insli r48, r48, -17369\n"
- "shl16insli r48, r48, 13142\n"
- "{ shl r23, r19, r48 ; fnop ; ld r63, r54 }\n"
- "move %0, r23\n"
- "move %1, r19\n"
- "move %2, r48\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shl_Y1.c b/none/tests/tilegx/insn_test_shl_Y1.c
deleted file mode 100644
index cae39e7..0000000
--- a/none/tests/tilegx/insn_test_shl_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shl_Y1.c
-//op=188
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x53094f44a07b725d, 0xe61730d0d9026b62 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r23, -28145\n"
- "shl16insli r23, r23, -7915\n"
- "shl16insli r23, r23, 2786\n"
- "shl16insli r23, r23, 4140\n"
- "moveli r19, -17474\n"
- "shl16insli r19, r19, 5541\n"
- "shl16insli r19, r19, 25238\n"
- "shl16insli r19, r19, 6803\n"
- "moveli r48, -9071\n"
- "shl16insli r48, r48, -18527\n"
- "shl16insli r48, r48, -17369\n"
- "shl16insli r48, r48, 13142\n"
- "{ fnop ; shl r23, r19, r48 ; ld r63, r54 }\n"
- "move %0, r23\n"
- "move %1, r19\n"
- "move %2, r48\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shli_X0.c b/none/tests/tilegx/insn_test_shli_X0.c
deleted file mode 100644
index 3c0b7c7..0000000
--- a/none/tests/tilegx/insn_test_shli_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_shli_X0.c
-//op=196
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x555a73f8e7686b53, 0xca681c3c17f1785e };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r3, -17698\n"
- "shl16insli r3, r3, -1407\n"
- "shl16insli r3, r3, 3238\n"
- "shl16insli r3, r3, 14331\n"
- "moveli r38, -19915\n"
- "shl16insli r38, r38, -2852\n"
- "shl16insli r38, r38, 32613\n"
- "shl16insli r38, r38, 14940\n"
- "{ shli r3, r38, 16 ; fnop }\n"
- "move %0, r3\n"
- "move %1, r38\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shli_X1.c b/none/tests/tilegx/insn_test_shli_X1.c
deleted file mode 100644
index 82f5787..0000000
--- a/none/tests/tilegx/insn_test_shli_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_shli_X1.c
-//op=196
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x555a73f8e7686b53, 0xca681c3c17f1785e };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r3, -17698\n"
- "shl16insli r3, r3, -1407\n"
- "shl16insli r3, r3, 3238\n"
- "shl16insli r3, r3, 14331\n"
- "moveli r38, -19915\n"
- "shl16insli r38, r38, -2852\n"
- "shl16insli r38, r38, 32613\n"
- "shl16insli r38, r38, 14940\n"
- "{ fnop ; shli r3, r38, 16 }\n"
- "move %0, r3\n"
- "move %1, r38\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shli_Y0.c b/none/tests/tilegx/insn_test_shli_Y0.c
deleted file mode 100644
index 8154cfc..0000000
--- a/none/tests/tilegx/insn_test_shli_Y0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_shli_Y0.c
-//op=196
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x555a73f8e7686b53, 0xca681c3c17f1785e };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r3, -17698\n"
- "shl16insli r3, r3, -1407\n"
- "shl16insli r3, r3, 3238\n"
- "shl16insli r3, r3, 14331\n"
- "moveli r38, -19915\n"
- "shl16insli r38, r38, -2852\n"
- "shl16insli r38, r38, 32613\n"
- "shl16insli r38, r38, 14940\n"
- "{ shli r3, r38, 16 ; fnop ; ld r63, r54 }\n"
- "move %0, r3\n"
- "move %1, r38\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shli_Y1.c b/none/tests/tilegx/insn_test_shli_Y1.c
deleted file mode 100644
index a96f1b9..0000000
--- a/none/tests/tilegx/insn_test_shli_Y1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_shli_Y1.c
-//op=196
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x555a73f8e7686b53, 0xca681c3c17f1785e };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r3, -17698\n"
- "shl16insli r3, r3, -1407\n"
- "shl16insli r3, r3, 3238\n"
- "shl16insli r3, r3, 14331\n"
- "moveli r38, -19915\n"
- "shl16insli r38, r38, -2852\n"
- "shl16insli r38, r38, 32613\n"
- "shl16insli r38, r38, 14940\n"
- "{ fnop ; shli r3, r38, 16 ; ld r63, r54 }\n"
- "move %0, r3\n"
- "move %1, r38\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shlx_X0.c b/none/tests/tilegx/insn_test_shlx_X0.c
deleted file mode 100644
index c908daa..0000000
--- a/none/tests/tilegx/insn_test_shlx_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shlx_X0.c
-//op=197
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc50a1fac55b8148e, 0x7a42921bfe898fb };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r4, -11574\n"
- "shl16insli r4, r4, 5546\n"
- "shl16insli r4, r4, -19680\n"
- "shl16insli r4, r4, -25733\n"
- "moveli r4, -7090\n"
- "shl16insli r4, r4, -11125\n"
- "shl16insli r4, r4, -23773\n"
- "shl16insli r4, r4, 7384\n"
- "moveli r42, -25884\n"
- "shl16insli r42, r42, -16117\n"
- "shl16insli r42, r42, 21894\n"
- "shl16insli r42, r42, -22287\n"
- "{ shlx r4, r4, r42 ; fnop }\n"
- "move %0, r4\n"
- "move %1, r4\n"
- "move %2, r42\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shlx_X1.c b/none/tests/tilegx/insn_test_shlx_X1.c
deleted file mode 100644
index b37a90a..0000000
--- a/none/tests/tilegx/insn_test_shlx_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shlx_X1.c
-//op=197
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc50a1fac55b8148e, 0x7a42921bfe898fb };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r4, -11574\n"
- "shl16insli r4, r4, 5546\n"
- "shl16insli r4, r4, -19680\n"
- "shl16insli r4, r4, -25733\n"
- "moveli r4, -7090\n"
- "shl16insli r4, r4, -11125\n"
- "shl16insli r4, r4, -23773\n"
- "shl16insli r4, r4, 7384\n"
- "moveli r42, -25884\n"
- "shl16insli r42, r42, -16117\n"
- "shl16insli r42, r42, 21894\n"
- "shl16insli r42, r42, -22287\n"
- "{ fnop ; shlx r4, r4, r42 }\n"
- "move %0, r4\n"
- "move %1, r4\n"
- "move %2, r42\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shlxi_X0.c b/none/tests/tilegx/insn_test_shlxi_X0.c
deleted file mode 100644
index 8a9a03c..0000000
--- a/none/tests/tilegx/insn_test_shlxi_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_shlxi_X0.c
-//op=198
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x3a5fb939d54b0205, 0xc4b573db7dcf1edb };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r28, 27432\n"
- "shl16insli r28, r28, -22439\n"
- "shl16insli r28, r28, 15226\n"
- "shl16insli r28, r28, -19568\n"
- "moveli r27, -20710\n"
- "shl16insli r27, r27, 2588\n"
- "shl16insli r27, r27, -32310\n"
- "shl16insli r27, r27, 10817\n"
- "{ shlxi r28, r27, 58 ; fnop }\n"
- "move %0, r28\n"
- "move %1, r27\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shlxi_X1.c b/none/tests/tilegx/insn_test_shlxi_X1.c
deleted file mode 100644
index 06bf4f8..0000000
--- a/none/tests/tilegx/insn_test_shlxi_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_shlxi_X1.c
-//op=198
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x3a5fb939d54b0205, 0xc4b573db7dcf1edb };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r28, 27432\n"
- "shl16insli r28, r28, -22439\n"
- "shl16insli r28, r28, 15226\n"
- "shl16insli r28, r28, -19568\n"
- "moveli r27, -20710\n"
- "shl16insli r27, r27, 2588\n"
- "shl16insli r27, r27, -32310\n"
- "shl16insli r27, r27, 10817\n"
- "{ fnop ; shlxi r28, r27, 58 }\n"
- "move %0, r28\n"
- "move %1, r27\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shrs_X0.c b/none/tests/tilegx/insn_test_shrs_X0.c
deleted file mode 100644
index c2fc5fd..0000000
--- a/none/tests/tilegx/insn_test_shrs_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shrs_X0.c
-//op=199
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x744ac897b12768c8, 0x643ae14995d28745 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r32, -3067\n"
- "shl16insli r32, r32, -406\n"
- "shl16insli r32, r32, 4305\n"
- "shl16insli r32, r32, -13947\n"
- "moveli r26, -23554\n"
- "shl16insli r26, r26, 503\n"
- "shl16insli r26, r26, -18013\n"
- "shl16insli r26, r26, 27535\n"
- "moveli r26, -13851\n"
- "shl16insli r26, r26, 4596\n"
- "shl16insli r26, r26, -18309\n"
- "shl16insli r26, r26, -24130\n"
- "{ shrs r32, r26, r26 ; fnop }\n"
- "move %0, r32\n"
- "move %1, r26\n"
- "move %2, r26\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shrs_X1.c b/none/tests/tilegx/insn_test_shrs_X1.c
deleted file mode 100644
index 6d86101..0000000
--- a/none/tests/tilegx/insn_test_shrs_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shrs_X1.c
-//op=199
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x744ac897b12768c8, 0x643ae14995d28745 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r32, -3067\n"
- "shl16insli r32, r32, -406\n"
- "shl16insli r32, r32, 4305\n"
- "shl16insli r32, r32, -13947\n"
- "moveli r26, -23554\n"
- "shl16insli r26, r26, 503\n"
- "shl16insli r26, r26, -18013\n"
- "shl16insli r26, r26, 27535\n"
- "moveli r26, -13851\n"
- "shl16insli r26, r26, 4596\n"
- "shl16insli r26, r26, -18309\n"
- "shl16insli r26, r26, -24130\n"
- "{ fnop ; shrs r32, r26, r26 }\n"
- "move %0, r32\n"
- "move %1, r26\n"
- "move %2, r26\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shrs_Y0.c b/none/tests/tilegx/insn_test_shrs_Y0.c
deleted file mode 100644
index ffaac0a..0000000
--- a/none/tests/tilegx/insn_test_shrs_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shrs_Y0.c
-//op=199
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x744ac897b12768c8, 0x643ae14995d28745 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r32, -3067\n"
- "shl16insli r32, r32, -406\n"
- "shl16insli r32, r32, 4305\n"
- "shl16insli r32, r32, -13947\n"
- "moveli r26, -23554\n"
- "shl16insli r26, r26, 503\n"
- "shl16insli r26, r26, -18013\n"
- "shl16insli r26, r26, 27535\n"
- "moveli r26, -13851\n"
- "shl16insli r26, r26, 4596\n"
- "shl16insli r26, r26, -18309\n"
- "shl16insli r26, r26, -24130\n"
- "{ shrs r32, r26, r26 ; fnop ; ld r63, r54 }\n"
- "move %0, r32\n"
- "move %1, r26\n"
- "move %2, r26\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shrs_Y1.c b/none/tests/tilegx/insn_test_shrs_Y1.c
deleted file mode 100644
index 7dfada3..0000000
--- a/none/tests/tilegx/insn_test_shrs_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shrs_Y1.c
-//op=199
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x744ac897b12768c8, 0x643ae14995d28745 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r32, -3067\n"
- "shl16insli r32, r32, -406\n"
- "shl16insli r32, r32, 4305\n"
- "shl16insli r32, r32, -13947\n"
- "moveli r26, -23554\n"
- "shl16insli r26, r26, 503\n"
- "shl16insli r26, r26, -18013\n"
- "shl16insli r26, r26, 27535\n"
- "moveli r26, -13851\n"
- "shl16insli r26, r26, 4596\n"
- "shl16insli r26, r26, -18309\n"
- "shl16insli r26, r26, -24130\n"
- "{ fnop ; shrs r32, r26, r26 ; ld r63, r54 }\n"
- "move %0, r32\n"
- "move %1, r26\n"
- "move %2, r26\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shrsi_X0.c b/none/tests/tilegx/insn_test_shrsi_X0.c
deleted file mode 100644
index f265855..0000000
--- a/none/tests/tilegx/insn_test_shrsi_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_shrsi_X0.c
-//op=200
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xf248472b636bec53, 0xd85a80d7b6245b44 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r25, -26255\n"
- "shl16insli r25, r25, -13898\n"
- "shl16insli r25, r25, 12833\n"
- "shl16insli r25, r25, 32008\n"
- "moveli r35, -25986\n"
- "shl16insli r35, r35, -11739\n"
- "shl16insli r35, r35, 13313\n"
- "shl16insli r35, r35, -12374\n"
- "{ shrsi r25, r35, 46 ; fnop }\n"
- "move %0, r25\n"
- "move %1, r35\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shrsi_X1.c b/none/tests/tilegx/insn_test_shrsi_X1.c
deleted file mode 100644
index 83c4efe..0000000
--- a/none/tests/tilegx/insn_test_shrsi_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_shrsi_X1.c
-//op=200
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xf248472b636bec53, 0xd85a80d7b6245b44 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r25, -26255\n"
- "shl16insli r25, r25, -13898\n"
- "shl16insli r25, r25, 12833\n"
- "shl16insli r25, r25, 32008\n"
- "moveli r35, -25986\n"
- "shl16insli r35, r35, -11739\n"
- "shl16insli r35, r35, 13313\n"
- "shl16insli r35, r35, -12374\n"
- "{ fnop ; shrsi r25, r35, 46 }\n"
- "move %0, r25\n"
- "move %1, r35\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shrsi_Y0.c b/none/tests/tilegx/insn_test_shrsi_Y0.c
deleted file mode 100644
index 5d06453..0000000
--- a/none/tests/tilegx/insn_test_shrsi_Y0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_shrsi_Y0.c
-//op=200
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xf248472b636bec53, 0xd85a80d7b6245b44 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r25, -26255\n"
- "shl16insli r25, r25, -13898\n"
- "shl16insli r25, r25, 12833\n"
- "shl16insli r25, r25, 32008\n"
- "moveli r35, -25986\n"
- "shl16insli r35, r35, -11739\n"
- "shl16insli r35, r35, 13313\n"
- "shl16insli r35, r35, -12374\n"
- "{ shrsi r25, r35, 46 ; fnop ; ld r63, r54 }\n"
- "move %0, r25\n"
- "move %1, r35\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shrsi_Y1.c b/none/tests/tilegx/insn_test_shrsi_Y1.c
deleted file mode 100644
index a8eb62c..0000000
--- a/none/tests/tilegx/insn_test_shrsi_Y1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_shrsi_Y1.c
-//op=200
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xf248472b636bec53, 0xd85a80d7b6245b44 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r25, -26255\n"
- "shl16insli r25, r25, -13898\n"
- "shl16insli r25, r25, 12833\n"
- "shl16insli r25, r25, 32008\n"
- "moveli r35, -25986\n"
- "shl16insli r35, r35, -11739\n"
- "shl16insli r35, r35, 13313\n"
- "shl16insli r35, r35, -12374\n"
- "{ fnop ; shrsi r25, r35, 46 ; ld r63, r54 }\n"
- "move %0, r25\n"
- "move %1, r35\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shru_X0.c b/none/tests/tilegx/insn_test_shru_X0.c
deleted file mode 100644
index 5b92a8d..0000000
--- a/none/tests/tilegx/insn_test_shru_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shru_X0.c
-//op=201
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x55fc49dd464ad867, 0xa2f896884ed05e90 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r38, -32745\n"
- "shl16insli r38, r38, -15929\n"
- "shl16insli r38, r38, -787\n"
- "shl16insli r38, r38, 26982\n"
- "moveli r21, 11986\n"
- "shl16insli r21, r21, 6051\n"
- "shl16insli r21, r21, 28164\n"
- "shl16insli r21, r21, -14685\n"
- "moveli r41, -32304\n"
- "shl16insli r41, r41, 5880\n"
- "shl16insli r41, r41, 26751\n"
- "shl16insli r41, r41, 15077\n"
- "{ shru r38, r21, r41 ; fnop }\n"
- "move %0, r38\n"
- "move %1, r21\n"
- "move %2, r41\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shru_X1.c b/none/tests/tilegx/insn_test_shru_X1.c
deleted file mode 100644
index 274cbcd..0000000
--- a/none/tests/tilegx/insn_test_shru_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shru_X1.c
-//op=201
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x55fc49dd464ad867, 0xa2f896884ed05e90 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r38, -32745\n"
- "shl16insli r38, r38, -15929\n"
- "shl16insli r38, r38, -787\n"
- "shl16insli r38, r38, 26982\n"
- "moveli r21, 11986\n"
- "shl16insli r21, r21, 6051\n"
- "shl16insli r21, r21, 28164\n"
- "shl16insli r21, r21, -14685\n"
- "moveli r41, -32304\n"
- "shl16insli r41, r41, 5880\n"
- "shl16insli r41, r41, 26751\n"
- "shl16insli r41, r41, 15077\n"
- "{ fnop ; shru r38, r21, r41 }\n"
- "move %0, r38\n"
- "move %1, r21\n"
- "move %2, r41\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shru_Y0.c b/none/tests/tilegx/insn_test_shru_Y0.c
deleted file mode 100644
index 3d57d5e..0000000
--- a/none/tests/tilegx/insn_test_shru_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shru_Y0.c
-//op=201
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x55fc49dd464ad867, 0xa2f896884ed05e90 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r38, -32745\n"
- "shl16insli r38, r38, -15929\n"
- "shl16insli r38, r38, -787\n"
- "shl16insli r38, r38, 26982\n"
- "moveli r21, 11986\n"
- "shl16insli r21, r21, 6051\n"
- "shl16insli r21, r21, 28164\n"
- "shl16insli r21, r21, -14685\n"
- "moveli r41, -32304\n"
- "shl16insli r41, r41, 5880\n"
- "shl16insli r41, r41, 26751\n"
- "shl16insli r41, r41, 15077\n"
- "{ shru r38, r21, r41 ; fnop ; ld r63, r54 }\n"
- "move %0, r38\n"
- "move %1, r21\n"
- "move %2, r41\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shru_Y1.c b/none/tests/tilegx/insn_test_shru_Y1.c
deleted file mode 100644
index 243bd0c..0000000
--- a/none/tests/tilegx/insn_test_shru_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shru_Y1.c
-//op=201
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x55fc49dd464ad867, 0xa2f896884ed05e90 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r38, -32745\n"
- "shl16insli r38, r38, -15929\n"
- "shl16insli r38, r38, -787\n"
- "shl16insli r38, r38, 26982\n"
- "moveli r21, 11986\n"
- "shl16insli r21, r21, 6051\n"
- "shl16insli r21, r21, 28164\n"
- "shl16insli r21, r21, -14685\n"
- "moveli r41, -32304\n"
- "shl16insli r41, r41, 5880\n"
- "shl16insli r41, r41, 26751\n"
- "shl16insli r41, r41, 15077\n"
- "{ fnop ; shru r38, r21, r41 ; ld r63, r54 }\n"
- "move %0, r38\n"
- "move %1, r21\n"
- "move %2, r41\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shrui_X0.c b/none/tests/tilegx/insn_test_shrui_X0.c
deleted file mode 100644
index 1d379ff..0000000
--- a/none/tests/tilegx/insn_test_shrui_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_shrui_X0.c
-//op=202
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xf903c34a732ec74d, 0x1b58c82cfa9e7805 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r44, 22940\n"
- "shl16insli r44, r44, -25012\n"
- "shl16insli r44, r44, 1293\n"
- "shl16insli r44, r44, 20844\n"
- "moveli r5, 4497\n"
- "shl16insli r5, r5, 8011\n"
- "shl16insli r5, r5, -29488\n"
- "shl16insli r5, r5, -23563\n"
- "{ shrui r44, r5, 30 ; fnop }\n"
- "move %0, r44\n"
- "move %1, r5\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shrui_X1.c b/none/tests/tilegx/insn_test_shrui_X1.c
deleted file mode 100644
index 0d9621f..0000000
--- a/none/tests/tilegx/insn_test_shrui_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_shrui_X1.c
-//op=202
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xf903c34a732ec74d, 0x1b58c82cfa9e7805 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r44, 22940\n"
- "shl16insli r44, r44, -25012\n"
- "shl16insli r44, r44, 1293\n"
- "shl16insli r44, r44, 20844\n"
- "moveli r5, 4497\n"
- "shl16insli r5, r5, 8011\n"
- "shl16insli r5, r5, -29488\n"
- "shl16insli r5, r5, -23563\n"
- "{ fnop ; shrui r44, r5, 30 }\n"
- "move %0, r44\n"
- "move %1, r5\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shrui_Y0.c b/none/tests/tilegx/insn_test_shrui_Y0.c
deleted file mode 100644
index da2014a..0000000
--- a/none/tests/tilegx/insn_test_shrui_Y0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_shrui_Y0.c
-//op=202
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xf903c34a732ec74d, 0x1b58c82cfa9e7805 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r44, 22940\n"
- "shl16insli r44, r44, -25012\n"
- "shl16insli r44, r44, 1293\n"
- "shl16insli r44, r44, 20844\n"
- "moveli r5, 4497\n"
- "shl16insli r5, r5, 8011\n"
- "shl16insli r5, r5, -29488\n"
- "shl16insli r5, r5, -23563\n"
- "{ shrui r44, r5, 30 ; fnop ; ld r63, r54 }\n"
- "move %0, r44\n"
- "move %1, r5\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shrui_Y1.c b/none/tests/tilegx/insn_test_shrui_Y1.c
deleted file mode 100644
index e19c40c..0000000
--- a/none/tests/tilegx/insn_test_shrui_Y1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_shrui_Y1.c
-//op=202
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xf903c34a732ec74d, 0x1b58c82cfa9e7805 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r44, 22940\n"
- "shl16insli r44, r44, -25012\n"
- "shl16insli r44, r44, 1293\n"
- "shl16insli r44, r44, 20844\n"
- "moveli r5, 4497\n"
- "shl16insli r5, r5, 8011\n"
- "shl16insli r5, r5, -29488\n"
- "shl16insli r5, r5, -23563\n"
- "{ fnop ; shrui r44, r5, 30 ; ld r63, r54 }\n"
- "move %0, r44\n"
- "move %1, r5\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shrux_X0.c b/none/tests/tilegx/insn_test_shrux_X0.c
deleted file mode 100644
index 17e34f4..0000000
--- a/none/tests/tilegx/insn_test_shrux_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shrux_X0.c
-//op=203
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc37f982bb51ed5f2, 0xeb5eb16625bf3fb };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r42, -7121\n"
- "shl16insli r42, r42, -30624\n"
- "shl16insli r42, r42, -1997\n"
- "shl16insli r42, r42, 26909\n"
- "moveli r49, -18112\n"
- "shl16insli r49, r49, -30675\n"
- "shl16insli r49, r49, -20511\n"
- "shl16insli r49, r49, 26134\n"
- "moveli r35, 5545\n"
- "shl16insli r35, r35, 27154\n"
- "shl16insli r35, r35, -18159\n"
- "shl16insli r35, r35, 26569\n"
- "{ shrux r42, r49, r35 ; fnop }\n"
- "move %0, r42\n"
- "move %1, r49\n"
- "move %2, r35\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shrux_X1.c b/none/tests/tilegx/insn_test_shrux_X1.c
deleted file mode 100644
index fd4960e..0000000
--- a/none/tests/tilegx/insn_test_shrux_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shrux_X1.c
-//op=203
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc37f982bb51ed5f2, 0xeb5eb16625bf3fb };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r42, -7121\n"
- "shl16insli r42, r42, -30624\n"
- "shl16insli r42, r42, -1997\n"
- "shl16insli r42, r42, 26909\n"
- "moveli r49, -18112\n"
- "shl16insli r49, r49, -30675\n"
- "shl16insli r49, r49, -20511\n"
- "shl16insli r49, r49, 26134\n"
- "moveli r35, 5545\n"
- "shl16insli r35, r35, 27154\n"
- "shl16insli r35, r35, -18159\n"
- "shl16insli r35, r35, 26569\n"
- "{ fnop ; shrux r42, r49, r35 }\n"
- "move %0, r42\n"
- "move %1, r49\n"
- "move %2, r35\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_shufflebytes_X0.c b/none/tests/tilegx/insn_test_shufflebytes_X0.c
deleted file mode 100644
index 7c2dffc..0000000
--- a/none/tests/tilegx/insn_test_shufflebytes_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_shufflebytes_X0.c
-//op=205
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xa6483705cd54508, 0x21d4110911f94e5 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r32, -22776\n"
- "shl16insli r32, r32, 13201\n"
- "shl16insli r32, r32, 12503\n"
- "shl16insli r32, r32, -18616\n"
- "moveli r31, -22828\n"
- "shl16insli r31, r31, -15690\n"
- "shl16insli r31, r31, 1274\n"
- "shl16insli r31, r31, 1723\n"
- "moveli r45, -14449\n"
- "shl16insli r45, r45, -2545\n"
- "shl16insli r45, r45, -8339\n"
- "shl16insli r45, r45, 221\n"
- "{ shufflebytes r32, r31, r45 ; fnop }\n"
- "move %0, r32\n"
- "move %1, r31\n"
- "move %2, r45\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_st1_X1.c b/none/tests/tilegx/insn_test_st1_X1.c
deleted file mode 100644
index 3de74d5..0000000
--- a/none/tests/tilegx/insn_test_st1_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_st1_X1.c
-//op=207
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd8cf3760900235c5, 0x4e5b0c323c359e88 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r17, 31115\n"
- "shl16insli r17, r17, -26645\n"
- "shl16insli r17, r17, -28059\n"
- "shl16insli r17, r17, -26401\n"
- "moveli r40, -23165\n"
- "shl16insli r40, r40, 1139\n"
- "shl16insli r40, r40, -11511\n"
- "shl16insli r40, r40, -24395\n"
- "move r17, %2\n"
- "{ fnop ; st1 r17, r40 }\n"
- "move %0, r17\n"
- "move %1, r40\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_st1_Y2.c b/none/tests/tilegx/insn_test_st1_Y2.c
deleted file mode 100644
index 9173a07..0000000
--- a/none/tests/tilegx/insn_test_st1_Y2.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_st1_Y2.c
-//op=207
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd8cf3760900235c5, 0x4e5b0c323c359e88 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r32, 31115\n"
- "shl16insli r32, r32, -26645\n"
- "shl16insli r32, r32, -28059\n"
- "shl16insli r32, r32, -26401\n"
- "moveli r51, -23165\n"
- "shl16insli r51, r51, 1139\n"
- "shl16insli r51, r51, -11511\n"
- "shl16insli r51, r51, -24395\n"
- "move r32, %2\n"
- "{ fnop ; fnop ; st1 r32, r51 }\n"
- "move %0, r32\n"
- "move %1, r51\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_st1_add_X1.c b/none/tests/tilegx/insn_test_st1_add_X1.c
deleted file mode 100644
index 86f751b..0000000
--- a/none/tests/tilegx/insn_test_st1_add_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_st1_add_X1.c
-//op=208
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x94fce0885d473733, 0xe22608b00f39a4c5 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r47, -21466\n"
- "shl16insli r47, r47, 11354\n"
- "shl16insli r47, r47, -10374\n"
- "shl16insli r47, r47, 87\n"
- "moveli r29, 29514\n"
- "shl16insli r29, r29, 14828\n"
- "shl16insli r29, r29, 1013\n"
- "shl16insli r29, r29, 14302\n"
- "move r47, %2\n"
- "{ fnop ; st1_add r47, r29, -39 }\n"
- "move %0, r47\n"
- "move %1, r29\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_st2_X1.c b/none/tests/tilegx/insn_test_st2_X1.c
deleted file mode 100644
index c85395e..0000000
--- a/none/tests/tilegx/insn_test_st2_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_st2_X1.c
-//op=209
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd28f375e560f9e91, 0x155a9a746b0baf };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r29, 31479\n"
- "shl16insli r29, r29, 14417\n"
- "shl16insli r29, r29, -15390\n"
- "shl16insli r29, r29, -30051\n"
- "moveli r11, -26026\n"
- "shl16insli r11, r11, 10353\n"
- "shl16insli r11, r11, 13698\n"
- "shl16insli r11, r11, 29702\n"
- "move r29, %2\n"
- "{ fnop ; st2 r29, r11 }\n"
- "move %0, r29\n"
- "move %1, r11\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_st2_Y2.c b/none/tests/tilegx/insn_test_st2_Y2.c
deleted file mode 100644
index 2927bff..0000000
--- a/none/tests/tilegx/insn_test_st2_Y2.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_st2_Y2.c
-//op=209
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd28f375e560f9e91, 0x155a9a746b0baf };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r27, 31479\n"
- "shl16insli r27, r27, 14417\n"
- "shl16insli r27, r27, -15390\n"
- "shl16insli r27, r27, -30051\n"
- "moveli r21, -26026\n"
- "shl16insli r21, r21, 10353\n"
- "shl16insli r21, r21, 13698\n"
- "shl16insli r21, r21, 29702\n"
- "move r27, %2\n"
- "{ fnop ; fnop ; st2 r27, r21 }\n"
- "move %0, r27\n"
- "move %1, r21\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_st2_add_X1.c b/none/tests/tilegx/insn_test_st2_add_X1.c
deleted file mode 100644
index 7f6f844..0000000
--- a/none/tests/tilegx/insn_test_st2_add_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_st2_add_X1.c
-//op=210
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x3e6c1829f1e6d7e9, 0x4419397566d0f360 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r47, -832\n"
- "shl16insli r47, r47, -16346\n"
- "shl16insli r47, r47, -24487\n"
- "shl16insli r47, r47, 31724\n"
- "moveli r34, -11697\n"
- "shl16insli r34, r34, 28366\n"
- "shl16insli r34, r34, -10445\n"
- "shl16insli r34, r34, -26110\n"
- "move r47, %2\n"
- "{ fnop ; st2_add r47, r34, 123 }\n"
- "move %0, r47\n"
- "move %1, r34\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_st4_X1.c b/none/tests/tilegx/insn_test_st4_X1.c
deleted file mode 100644
index 64df1bd..0000000
--- a/none/tests/tilegx/insn_test_st4_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_st4_X1.c
-//op=211
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x559c13b7886a9188, 0xe3421eb8576951b8 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r20, -22718\n"
- "shl16insli r20, r20, 15821\n"
- "shl16insli r20, r20, -14581\n"
- "shl16insli r20, r20, -14875\n"
- "moveli r12, -13950\n"
- "shl16insli r12, r12, 11169\n"
- "shl16insli r12, r12, -18391\n"
- "shl16insli r12, r12, -19133\n"
- "move r20, %2\n"
- "{ fnop ; st4 r20, r12 }\n"
- "move %0, r20\n"
- "move %1, r12\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_st4_Y2.c b/none/tests/tilegx/insn_test_st4_Y2.c
deleted file mode 100644
index 43b287b..0000000
--- a/none/tests/tilegx/insn_test_st4_Y2.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_st4_Y2.c
-//op=211
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x559c13b7886a9188, 0xe3421eb8576951b8 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r29, -22718\n"
- "shl16insli r29, r29, 15821\n"
- "shl16insli r29, r29, -14581\n"
- "shl16insli r29, r29, -14875\n"
- "moveli r38, -13950\n"
- "shl16insli r38, r38, 11169\n"
- "shl16insli r38, r38, -18391\n"
- "shl16insli r38, r38, -19133\n"
- "move r29, %2\n"
- "{ fnop ; fnop ; st4 r29, r38 }\n"
- "move %0, r29\n"
- "move %1, r38\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_st4_add_X1.c b/none/tests/tilegx/insn_test_st4_add_X1.c
deleted file mode 100644
index 1fa7538..0000000
--- a/none/tests/tilegx/insn_test_st4_add_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_st4_add_X1.c
-//op=212
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x8a665fbee6262b19, 0x988b16de50a53a0a };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r9, -5920\n"
- "shl16insli r9, r9, 6097\n"
- "shl16insli r9, r9, -2456\n"
- "shl16insli r9, r9, 10572\n"
- "moveli r45, 20609\n"
- "shl16insli r45, r45, -28665\n"
- "shl16insli r45, r45, -5637\n"
- "shl16insli r45, r45, -7979\n"
- "move r9, %2\n"
- "{ fnop ; st4_add r9, r45, -34 }\n"
- "move %0, r9\n"
- "move %1, r45\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_st_X1.c b/none/tests/tilegx/insn_test_st_X1.c
deleted file mode 100644
index c13e1f6..0000000
--- a/none/tests/tilegx/insn_test_st_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_st_X1.c
-//op=206
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xdf38a6238f47ee5b, 0x2c24dd020e9fa33f };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r4, -2884\n"
- "shl16insli r4, r4, 28785\n"
- "shl16insli r4, r4, 7136\n"
- "shl16insli r4, r4, 32281\n"
- "moveli r7, -14930\n"
- "shl16insli r7, r7, -27555\n"
- "shl16insli r7, r7, -15233\n"
- "shl16insli r7, r7, -7776\n"
- "move r4, %2\n"
- "{ fnop ; st r4, r7 }\n"
- "move %0, r4\n"
- "move %1, r7\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_st_Y2.c b/none/tests/tilegx/insn_test_st_Y2.c
deleted file mode 100644
index 599304f..0000000
--- a/none/tests/tilegx/insn_test_st_Y2.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_st_Y2.c
-//op=206
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xdf38a6238f47ee5b, 0x2c24dd020e9fa33f };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r29, -2884\n"
- "shl16insli r29, r29, 28785\n"
- "shl16insli r29, r29, 7136\n"
- "shl16insli r29, r29, 32281\n"
- "moveli r6, -14930\n"
- "shl16insli r6, r6, -27555\n"
- "shl16insli r6, r6, -15233\n"
- "shl16insli r6, r6, -7776\n"
- "move r29, %2\n"
- "{ fnop ; fnop ; st r29, r6 }\n"
- "move %0, r29\n"
- "move %1, r6\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_st_add_X1.c b/none/tests/tilegx/insn_test_st_add_X1.c
deleted file mode 100644
index 7c6202f..0000000
--- a/none/tests/tilegx/insn_test_st_add_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_st_add_X1.c
-//op=213
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xb47fef7957f607a6, 0x8f11359b0d4a2989 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r29, -13060\n"
- "shl16insli r29, r29, 30193\n"
- "shl16insli r29, r29, -17572\n"
- "shl16insli r29, r29, -9789\n"
- "moveli r42, 27632\n"
- "shl16insli r42, r42, 12264\n"
- "shl16insli r42, r42, 18107\n"
- "shl16insli r42, r42, 1639\n"
- "move r29, %2\n"
- "{ fnop ; st_add r29, r42, 41 }\n"
- "move %0, r29\n"
- "move %1, r42\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_stnt1_X1.c b/none/tests/tilegx/insn_test_stnt1_X1.c
deleted file mode 100644
index 2a222d8..0000000
--- a/none/tests/tilegx/insn_test_stnt1_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_stnt1_X1.c
-//op=215
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x40001b1a5c71f305, 0x9355b6a95b9dd621 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r33, -20990\n"
- "shl16insli r33, r33, -3887\n"
- "shl16insli r33, r33, 1674\n"
- "shl16insli r33, r33, 11807\n"
- "moveli r21, 13070\n"
- "shl16insli r21, r21, 14309\n"
- "shl16insli r21, r21, -28472\n"
- "shl16insli r21, r21, 23329\n"
- "move r33, %2\n"
- "{ fnop ; stnt1 r33, r21 }\n"
- "move %0, r33\n"
- "move %1, r21\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_stnt2_X1.c b/none/tests/tilegx/insn_test_stnt2_X1.c
deleted file mode 100644
index 82e5027..0000000
--- a/none/tests/tilegx/insn_test_stnt2_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_stnt2_X1.c
-//op=217
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x4264771eb976f72, 0x85fc92ac292ed02e };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r8, 5764\n"
- "shl16insli r8, r8, 30540\n"
- "shl16insli r8, r8, 17158\n"
- "shl16insli r8, r8, -20975\n"
- "moveli r18, 25827\n"
- "shl16insli r18, r18, 7973\n"
- "shl16insli r18, r18, 5233\n"
- "shl16insli r18, r18, 29962\n"
- "move r8, %2\n"
- "{ fnop ; stnt2 r8, r18 }\n"
- "move %0, r8\n"
- "move %1, r18\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_stnt2_add_X1.c b/none/tests/tilegx/insn_test_stnt2_add_X1.c
deleted file mode 100644
index 09b5dad..0000000
--- a/none/tests/tilegx/insn_test_stnt2_add_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_stnt2_add_X1.c
-//op=218
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x3cfd98eacbf82c51, 0x1fe3ff849620d963 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r32, 31983\n"
- "shl16insli r32, r32, -22770\n"
- "shl16insli r32, r32, 20146\n"
- "shl16insli r32, r32, -3298\n"
- "moveli r49, -616\n"
- "shl16insli r49, r49, -17536\n"
- "shl16insli r49, r49, -4093\n"
- "shl16insli r49, r49, -4473\n"
- "move r32, %2\n"
- "{ fnop ; stnt2_add r32, r49, 102 }\n"
- "move %0, r32\n"
- "move %1, r49\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_stnt4_X1.c b/none/tests/tilegx/insn_test_stnt4_X1.c
deleted file mode 100644
index 124b872..0000000
--- a/none/tests/tilegx/insn_test_stnt4_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_stnt4_X1.c
-//op=219
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9275ba799534a7f9, 0x6745e72a91ff67c2 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r40, -1549\n"
- "shl16insli r40, r40, 17842\n"
- "shl16insli r40, r40, 24501\n"
- "shl16insli r40, r40, -29822\n"
- "moveli r41, 17684\n"
- "shl16insli r41, r41, 2987\n"
- "shl16insli r41, r41, 15358\n"
- "shl16insli r41, r41, 2277\n"
- "move r40, %2\n"
- "{ fnop ; stnt4 r40, r41 }\n"
- "move %0, r40\n"
- "move %1, r41\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_stnt4_add_X1.c b/none/tests/tilegx/insn_test_stnt4_add_X1.c
deleted file mode 100644
index 964e28e..0000000
--- a/none/tests/tilegx/insn_test_stnt4_add_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_stnt4_add_X1.c
-//op=220
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x6f255d688978bfb5, 0x6b650d3d95fb5164 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r39, -25531\n"
- "shl16insli r39, r39, -23858\n"
- "shl16insli r39, r39, 24910\n"
- "shl16insli r39, r39, -31706\n"
- "moveli r1, 16489\n"
- "shl16insli r1, r1, 1852\n"
- "shl16insli r1, r1, -22328\n"
- "shl16insli r1, r1, -20016\n"
- "move r39, %2\n"
- "{ fnop ; stnt4_add r39, r1, 104 }\n"
- "move %0, r39\n"
- "move %1, r1\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_stnt_X1.c b/none/tests/tilegx/insn_test_stnt_X1.c
deleted file mode 100644
index b917f7f..0000000
--- a/none/tests/tilegx/insn_test_stnt_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_stnt_X1.c
-//op=214
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x6b3e9bf39bb2fee8, 0x4463a2383032e2f2 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r19, 10868\n"
- "shl16insli r19, r19, 28978\n"
- "shl16insli r19, r19, -7157\n"
- "shl16insli r19, r19, 19796\n"
- "moveli r24, -15907\n"
- "shl16insli r24, r24, -20157\n"
- "shl16insli r24, r24, 22361\n"
- "shl16insli r24, r24, -24834\n"
- "move r19, %2\n"
- "{ fnop ; stnt r19, r24 }\n"
- "move %0, r19\n"
- "move %1, r24\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_stnt_add_X1.c b/none/tests/tilegx/insn_test_stnt_add_X1.c
deleted file mode 100644
index 3431f66..0000000
--- a/none/tests/tilegx/insn_test_stnt_add_X1.c
+++ /dev/null
@@ -1,38 +0,0 @@
-//file: _insn_test_stnt_add_X1.c
-//op=221
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x8886d34e2ec2c46, 0x31537bc8fa0b780a };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r13, 27578\n"
- "shl16insli r13, r13, -12921\n"
- "shl16insli r13, r13, 10612\n"
- "shl16insli r13, r13, -6350\n"
- "moveli r38, -29644\n"
- "shl16insli r38, r38, -25434\n"
- "shl16insli r38, r38, -11296\n"
- "shl16insli r38, r38, -14614\n"
- "move r13, %2\n"
- "{ fnop ; stnt_add r13, r38, -75 }\n"
- "move %0, r13\n"
- "move %1, r38\n"
- :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
- printf("%016lx %016lx\n", mem[0], mem[1]);
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_sub_X0.c b/none/tests/tilegx/insn_test_sub_X0.c
deleted file mode 100644
index eb94de0..0000000
--- a/none/tests/tilegx/insn_test_sub_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_sub_X0.c
-//op=222
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x87dd16cba069efad, 0x63c2bab813708efb };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r31, -31836\n"
- "shl16insli r31, r31, -15605\n"
- "shl16insli r31, r31, -32767\n"
- "shl16insli r31, r31, -3062\n"
- "moveli r49, 15126\n"
- "shl16insli r49, r49, -17631\n"
- "shl16insli r49, r49, 31423\n"
- "shl16insli r49, r49, 10557\n"
- "moveli r28, -7514\n"
- "shl16insli r28, r28, -32499\n"
- "shl16insli r28, r28, -9013\n"
- "shl16insli r28, r28, -11291\n"
- "{ sub r31, r49, r28 ; fnop }\n"
- "move %0, r31\n"
- "move %1, r49\n"
- "move %2, r28\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_sub_X1.c b/none/tests/tilegx/insn_test_sub_X1.c
deleted file mode 100644
index 8ab3dc0..0000000
--- a/none/tests/tilegx/insn_test_sub_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_sub_X1.c
-//op=222
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x87dd16cba069efad, 0x63c2bab813708efb };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r31, -31836\n"
- "shl16insli r31, r31, -15605\n"
- "shl16insli r31, r31, -32767\n"
- "shl16insli r31, r31, -3062\n"
- "moveli r49, 15126\n"
- "shl16insli r49, r49, -17631\n"
- "shl16insli r49, r49, 31423\n"
- "shl16insli r49, r49, 10557\n"
- "moveli r28, -7514\n"
- "shl16insli r28, r28, -32499\n"
- "shl16insli r28, r28, -9013\n"
- "shl16insli r28, r28, -11291\n"
- "{ fnop ; sub r31, r49, r28 }\n"
- "move %0, r31\n"
- "move %1, r49\n"
- "move %2, r28\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_sub_Y0.c b/none/tests/tilegx/insn_test_sub_Y0.c
deleted file mode 100644
index 323df5b..0000000
--- a/none/tests/tilegx/insn_test_sub_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_sub_Y0.c
-//op=222
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x87dd16cba069efad, 0x63c2bab813708efb };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r31, -31836\n"
- "shl16insli r31, r31, -15605\n"
- "shl16insli r31, r31, -32767\n"
- "shl16insli r31, r31, -3062\n"
- "moveli r49, 15126\n"
- "shl16insli r49, r49, -17631\n"
- "shl16insli r49, r49, 31423\n"
- "shl16insli r49, r49, 10557\n"
- "moveli r28, -7514\n"
- "shl16insli r28, r28, -32499\n"
- "shl16insli r28, r28, -9013\n"
- "shl16insli r28, r28, -11291\n"
- "{ sub r31, r49, r28 ; fnop ; ld r63, r54 }\n"
- "move %0, r31\n"
- "move %1, r49\n"
- "move %2, r28\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_sub_Y1.c b/none/tests/tilegx/insn_test_sub_Y1.c
deleted file mode 100644
index b328149..0000000
--- a/none/tests/tilegx/insn_test_sub_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_sub_Y1.c
-//op=222
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x87dd16cba069efad, 0x63c2bab813708efb };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r31, -31836\n"
- "shl16insli r31, r31, -15605\n"
- "shl16insli r31, r31, -32767\n"
- "shl16insli r31, r31, -3062\n"
- "moveli r49, 15126\n"
- "shl16insli r49, r49, -17631\n"
- "shl16insli r49, r49, 31423\n"
- "shl16insli r49, r49, 10557\n"
- "moveli r28, -7514\n"
- "shl16insli r28, r28, -32499\n"
- "shl16insli r28, r28, -9013\n"
- "shl16insli r28, r28, -11291\n"
- "{ fnop ; sub r31, r49, r28 ; ld r63, r54 }\n"
- "move %0, r31\n"
- "move %1, r49\n"
- "move %2, r28\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_subx_X0.c b/none/tests/tilegx/insn_test_subx_X0.c
deleted file mode 100644
index 362691a..0000000
--- a/none/tests/tilegx/insn_test_subx_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_subx_X0.c
-//op=223
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xb80daced7a10c38f, 0x7b03f62381712f55 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r11, -11286\n"
- "shl16insli r11, r11, 24130\n"
- "shl16insli r11, r11, -21471\n"
- "shl16insli r11, r11, -29764\n"
- "moveli r6, -5788\n"
- "shl16insli r6, r6, -20401\n"
- "shl16insli r6, r6, 13325\n"
- "shl16insli r6, r6, -17582\n"
- "moveli r31, 1590\n"
- "shl16insli r31, r31, 2484\n"
- "shl16insli r31, r31, 10483\n"
- "shl16insli r31, r31, -30014\n"
- "{ subx r11, r6, r31 ; fnop }\n"
- "move %0, r11\n"
- "move %1, r6\n"
- "move %2, r31\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_subx_X1.c b/none/tests/tilegx/insn_test_subx_X1.c
deleted file mode 100644
index b3a7273..0000000
--- a/none/tests/tilegx/insn_test_subx_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_subx_X1.c
-//op=223
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xb80daced7a10c38f, 0x7b03f62381712f55 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r11, -11286\n"
- "shl16insli r11, r11, 24130\n"
- "shl16insli r11, r11, -21471\n"
- "shl16insli r11, r11, -29764\n"
- "moveli r6, -5788\n"
- "shl16insli r6, r6, -20401\n"
- "shl16insli r6, r6, 13325\n"
- "shl16insli r6, r6, -17582\n"
- "moveli r31, 1590\n"
- "shl16insli r31, r31, 2484\n"
- "shl16insli r31, r31, 10483\n"
- "shl16insli r31, r31, -30014\n"
- "{ fnop ; subx r11, r6, r31 }\n"
- "move %0, r11\n"
- "move %1, r6\n"
- "move %2, r31\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_subx_Y0.c b/none/tests/tilegx/insn_test_subx_Y0.c
deleted file mode 100644
index 7e76300..0000000
--- a/none/tests/tilegx/insn_test_subx_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_subx_Y0.c
-//op=223
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xb80daced7a10c38f, 0x7b03f62381712f55 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r11, -11286\n"
- "shl16insli r11, r11, 24130\n"
- "shl16insli r11, r11, -21471\n"
- "shl16insli r11, r11, -29764\n"
- "moveli r6, -5788\n"
- "shl16insli r6, r6, -20401\n"
- "shl16insli r6, r6, 13325\n"
- "shl16insli r6, r6, -17582\n"
- "moveli r31, 1590\n"
- "shl16insli r31, r31, 2484\n"
- "shl16insli r31, r31, 10483\n"
- "shl16insli r31, r31, -30014\n"
- "{ subx r11, r6, r31 ; fnop ; ld r63, r54 }\n"
- "move %0, r11\n"
- "move %1, r6\n"
- "move %2, r31\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_subx_Y1.c b/none/tests/tilegx/insn_test_subx_Y1.c
deleted file mode 100644
index 857470a..0000000
--- a/none/tests/tilegx/insn_test_subx_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_subx_Y1.c
-//op=223
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xb80daced7a10c38f, 0x7b03f62381712f55 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r11, -11286\n"
- "shl16insli r11, r11, 24130\n"
- "shl16insli r11, r11, -21471\n"
- "shl16insli r11, r11, -29764\n"
- "moveli r6, -5788\n"
- "shl16insli r6, r6, -20401\n"
- "shl16insli r6, r6, 13325\n"
- "shl16insli r6, r6, -17582\n"
- "moveli r31, 1590\n"
- "shl16insli r31, r31, 2484\n"
- "shl16insli r31, r31, 10483\n"
- "shl16insli r31, r31, -30014\n"
- "{ fnop ; subx r11, r6, r31 ; ld r63, r54 }\n"
- "move %0, r11\n"
- "move %1, r6\n"
- "move %2, r31\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_tblidxb0_X0.c b/none/tests/tilegx/insn_test_tblidxb0_X0.c
deleted file mode 100644
index 04237ad..0000000
--- a/none/tests/tilegx/insn_test_tblidxb0_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_tblidxb0_X0.c
-//op=229
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x31b68d06344a9475, 0xebc9dd79c7a87a22 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r5, -1618\n"
- "shl16insli r5, r5, -6082\n"
- "shl16insli r5, r5, 16233\n"
- "shl16insli r5, r5, -1212\n"
- "moveli r13, -29258\n"
- "shl16insli r13, r13, -8488\n"
- "shl16insli r13, r13, -31577\n"
- "shl16insli r13, r13, 27843\n"
- "{ tblidxb0 r5, r13 ; fnop }\n"
- "move %0, r5\n"
- "move %1, r13\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_tblidxb0_Y0.c b/none/tests/tilegx/insn_test_tblidxb0_Y0.c
deleted file mode 100644
index 375f323..0000000
--- a/none/tests/tilegx/insn_test_tblidxb0_Y0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_tblidxb0_Y0.c
-//op=229
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x31b68d06344a9475, 0xebc9dd79c7a87a22 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r5, -1618\n"
- "shl16insli r5, r5, -6082\n"
- "shl16insli r5, r5, 16233\n"
- "shl16insli r5, r5, -1212\n"
- "moveli r13, -29258\n"
- "shl16insli r13, r13, -8488\n"
- "shl16insli r13, r13, -31577\n"
- "shl16insli r13, r13, 27843\n"
- "{ tblidxb0 r5, r13 ; fnop ; ld r63, r54 }\n"
- "move %0, r5\n"
- "move %1, r13\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_tblidxb1_X0.c b/none/tests/tilegx/insn_test_tblidxb1_X0.c
deleted file mode 100644
index 317e110..0000000
--- a/none/tests/tilegx/insn_test_tblidxb1_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_tblidxb1_X0.c
-//op=230
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x5c5f60b8899f2703, 0x4826371b074e6849 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r10, 27846\n"
- "shl16insli r10, r10, 314\n"
- "shl16insli r10, r10, -26424\n"
- "shl16insli r10, r10, 10908\n"
- "moveli r2, -32180\n"
- "shl16insli r2, r2, 27477\n"
- "shl16insli r2, r2, 9680\n"
- "shl16insli r2, r2, 16927\n"
- "{ tblidxb1 r10, r2 ; fnop }\n"
- "move %0, r10\n"
- "move %1, r2\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_tblidxb1_Y0.c b/none/tests/tilegx/insn_test_tblidxb1_Y0.c
deleted file mode 100644
index 9921515..0000000
--- a/none/tests/tilegx/insn_test_tblidxb1_Y0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_tblidxb1_Y0.c
-//op=230
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x5c5f60b8899f2703, 0x4826371b074e6849 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r10, 27846\n"
- "shl16insli r10, r10, 314\n"
- "shl16insli r10, r10, -26424\n"
- "shl16insli r10, r10, 10908\n"
- "moveli r2, -32180\n"
- "shl16insli r2, r2, 27477\n"
- "shl16insli r2, r2, 9680\n"
- "shl16insli r2, r2, 16927\n"
- "{ tblidxb1 r10, r2 ; fnop ; ld r63, r54 }\n"
- "move %0, r10\n"
- "move %1, r2\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_tblidxb2_X0.c b/none/tests/tilegx/insn_test_tblidxb2_X0.c
deleted file mode 100644
index 83c49c0..0000000
--- a/none/tests/tilegx/insn_test_tblidxb2_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_tblidxb2_X0.c
-//op=231
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x6d113c22a94d65e4, 0x400c09fcfb9b518b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r48, -831\n"
- "shl16insli r48, r48, -21707\n"
- "shl16insli r48, r48, 21243\n"
- "shl16insli r48, r48, 32630\n"
- "moveli r45, 5379\n"
- "shl16insli r45, r45, 17793\n"
- "shl16insli r45, r45, 30101\n"
- "shl16insli r45, r45, 16122\n"
- "{ tblidxb2 r48, r45 ; fnop }\n"
- "move %0, r48\n"
- "move %1, r45\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_tblidxb2_Y0.c b/none/tests/tilegx/insn_test_tblidxb2_Y0.c
deleted file mode 100644
index e4d1fc4..0000000
--- a/none/tests/tilegx/insn_test_tblidxb2_Y0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_tblidxb2_Y0.c
-//op=231
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x6d113c22a94d65e4, 0x400c09fcfb9b518b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r48, -831\n"
- "shl16insli r48, r48, -21707\n"
- "shl16insli r48, r48, 21243\n"
- "shl16insli r48, r48, 32630\n"
- "moveli r45, 5379\n"
- "shl16insli r45, r45, 17793\n"
- "shl16insli r45, r45, 30101\n"
- "shl16insli r45, r45, 16122\n"
- "{ tblidxb2 r48, r45 ; fnop ; ld r63, r54 }\n"
- "move %0, r48\n"
- "move %1, r45\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_tblidxb3_X0.c b/none/tests/tilegx/insn_test_tblidxb3_X0.c
deleted file mode 100644
index d8cfb75..0000000
--- a/none/tests/tilegx/insn_test_tblidxb3_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_tblidxb3_X0.c
-//op=232
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xfd7000ecef4ffb36, 0xcf14c16c8fe6d80a };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r29, 21338\n"
- "shl16insli r29, r29, -8055\n"
- "shl16insli r29, r29, -7131\n"
- "shl16insli r29, r29, 21377\n"
- "moveli r28, 11583\n"
- "shl16insli r28, r28, -32720\n"
- "shl16insli r28, r28, 17409\n"
- "shl16insli r28, r28, -25838\n"
- "{ tblidxb3 r29, r28 ; fnop }\n"
- "move %0, r29\n"
- "move %1, r28\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_tblidxb3_Y0.c b/none/tests/tilegx/insn_test_tblidxb3_Y0.c
deleted file mode 100644
index 4f90f5d..0000000
--- a/none/tests/tilegx/insn_test_tblidxb3_Y0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_tblidxb3_Y0.c
-//op=232
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xfd7000ecef4ffb36, 0xcf14c16c8fe6d80a };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r29, 21338\n"
- "shl16insli r29, r29, -8055\n"
- "shl16insli r29, r29, -7131\n"
- "shl16insli r29, r29, 21377\n"
- "moveli r28, 11583\n"
- "shl16insli r28, r28, -32720\n"
- "shl16insli r28, r28, 17409\n"
- "shl16insli r28, r28, -25838\n"
- "{ tblidxb3 r29, r28 ; fnop ; ld r63, r54 }\n"
- "move %0, r29\n"
- "move %1, r28\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1add_X0.c b/none/tests/tilegx/insn_test_v1add_X0.c
deleted file mode 100644
index 3d3208d..0000000
--- a/none/tests/tilegx/insn_test_v1add_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1add_X0.c
-//op=233
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xb6f11f94786226c8, 0xef169cd1658e9a9b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r20, 27682\n"
- "shl16insli r20, r20, 13107\n"
- "shl16insli r20, r20, 1100\n"
- "shl16insli r20, r20, -12585\n"
- "moveli r21, 32493\n"
- "shl16insli r21, r21, 14979\n"
- "shl16insli r21, r21, 26024\n"
- "shl16insli r21, r21, 32141\n"
- "moveli r17, -26698\n"
- "shl16insli r17, r17, 18738\n"
- "shl16insli r17, r17, -23994\n"
- "shl16insli r17, r17, -32450\n"
- "{ v1add r20, r21, r17 ; fnop }\n"
- "move %0, r20\n"
- "move %1, r21\n"
- "move %2, r17\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1add_X1.c b/none/tests/tilegx/insn_test_v1add_X1.c
deleted file mode 100644
index 606818f..0000000
--- a/none/tests/tilegx/insn_test_v1add_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1add_X1.c
-//op=233
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xb6f11f94786226c8, 0xef169cd1658e9a9b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r20, 27682\n"
- "shl16insli r20, r20, 13107\n"
- "shl16insli r20, r20, 1100\n"
- "shl16insli r20, r20, -12585\n"
- "moveli r21, 32493\n"
- "shl16insli r21, r21, 14979\n"
- "shl16insli r21, r21, 26024\n"
- "shl16insli r21, r21, 32141\n"
- "moveli r17, -26698\n"
- "shl16insli r17, r17, 18738\n"
- "shl16insli r17, r17, -23994\n"
- "shl16insli r17, r17, -32450\n"
- "{ fnop ; v1add r20, r21, r17 }\n"
- "move %0, r20\n"
- "move %1, r21\n"
- "move %2, r17\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1adduc_X0.c b/none/tests/tilegx/insn_test_v1adduc_X0.c
deleted file mode 100644
index 78936dd..0000000
--- a/none/tests/tilegx/insn_test_v1adduc_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1adduc_X0.c
-//op=235
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x22ce703cb6ffeac4, 0x80948177d07e88f4 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r14, -13316\n"
- "shl16insli r14, r14, -18141\n"
- "shl16insli r14, r14, -11937\n"
- "shl16insli r14, r14, -15394\n"
- "moveli r19, -22708\n"
- "shl16insli r19, r19, -32336\n"
- "shl16insli r19, r19, -14907\n"
- "shl16insli r19, r19, -32360\n"
- "moveli r50, -3633\n"
- "shl16insli r50, r50, -22778\n"
- "shl16insli r50, r50, -18593\n"
- "shl16insli r50, r50, -30611\n"
- "{ v1adduc r14, r19, r50 ; fnop }\n"
- "move %0, r14\n"
- "move %1, r19\n"
- "move %2, r50\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1adduc_X1.c b/none/tests/tilegx/insn_test_v1adduc_X1.c
deleted file mode 100644
index 051e024..0000000
--- a/none/tests/tilegx/insn_test_v1adduc_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1adduc_X1.c
-//op=235
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x22ce703cb6ffeac4, 0x80948177d07e88f4 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r14, -13316\n"
- "shl16insli r14, r14, -18141\n"
- "shl16insli r14, r14, -11937\n"
- "shl16insli r14, r14, -15394\n"
- "moveli r19, -22708\n"
- "shl16insli r19, r19, -32336\n"
- "shl16insli r19, r19, -14907\n"
- "shl16insli r19, r19, -32360\n"
- "moveli r50, -3633\n"
- "shl16insli r50, r50, -22778\n"
- "shl16insli r50, r50, -18593\n"
- "shl16insli r50, r50, -30611\n"
- "{ fnop ; v1adduc r14, r19, r50 }\n"
- "move %0, r14\n"
- "move %1, r19\n"
- "move %2, r50\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1adiffu_X0.c b/none/tests/tilegx/insn_test_v1adiffu_X0.c
deleted file mode 100644
index c8d0973..0000000
--- a/none/tests/tilegx/insn_test_v1adiffu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1adiffu_X0.c
-//op=236
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x4b94365a94fc8379, 0xd398d9dcfc90866b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r2, 21980\n"
- "shl16insli r2, r2, 6619\n"
- "shl16insli r2, r2, -5633\n"
- "shl16insli r2, r2, 14172\n"
- "moveli r35, 208\n"
- "shl16insli r35, r35, 20913\n"
- "shl16insli r35, r35, 19131\n"
- "shl16insli r35, r35, -17081\n"
- "moveli r33, 25300\n"
- "shl16insli r33, r33, 18828\n"
- "shl16insli r33, r33, 835\n"
- "shl16insli r33, r33, 10241\n"
- "{ v1adiffu r2, r35, r33 ; fnop }\n"
- "move %0, r2\n"
- "move %1, r35\n"
- "move %2, r33\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1avgu_X0.c b/none/tests/tilegx/insn_test_v1avgu_X0.c
deleted file mode 100644
index c77f514..0000000
--- a/none/tests/tilegx/insn_test_v1avgu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1avgu_X0.c
-//op=237
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xeaf60994f1256f, 0x96d7d7579295561d };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r43, 31333\n"
- "shl16insli r43, r43, 15554\n"
- "shl16insli r43, r43, 16035\n"
- "shl16insli r43, r43, -6284\n"
- "moveli r15, -6999\n"
- "shl16insli r15, r15, -24670\n"
- "shl16insli r15, r15, -31990\n"
- "shl16insli r15, r15, -6084\n"
- "moveli r9, -29195\n"
- "shl16insli r9, r9, -14971\n"
- "shl16insli r9, r9, 21267\n"
- "shl16insli r9, r9, -6933\n"
- "{ v1avgu r43, r15, r9 ; fnop }\n"
- "move %0, r43\n"
- "move %1, r15\n"
- "move %2, r9\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1cmpeq_X0.c b/none/tests/tilegx/insn_test_v1cmpeq_X0.c
deleted file mode 100644
index 26c2436..0000000
--- a/none/tests/tilegx/insn_test_v1cmpeq_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1cmpeq_X0.c
-//op=238
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xbc7e18adc4f4bcd4, 0xdd853a2377c4c1cd };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r3, -28260\n"
- "shl16insli r3, r3, -3800\n"
- "shl16insli r3, r3, 26206\n"
- "shl16insli r3, r3, 20590\n"
- "moveli r43, -7555\n"
- "shl16insli r43, r43, -10473\n"
- "shl16insli r43, r43, 1769\n"
- "shl16insli r43, r43, 20859\n"
- "moveli r22, 31720\n"
- "shl16insli r22, r22, -26184\n"
- "shl16insli r22, r22, -29280\n"
- "shl16insli r22, r22, 21783\n"
- "{ v1cmpeq r3, r43, r22 ; fnop }\n"
- "move %0, r3\n"
- "move %1, r43\n"
- "move %2, r22\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1cmpeq_X1.c b/none/tests/tilegx/insn_test_v1cmpeq_X1.c
deleted file mode 100644
index d453b03..0000000
--- a/none/tests/tilegx/insn_test_v1cmpeq_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1cmpeq_X1.c
-//op=238
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xbc7e18adc4f4bcd4, 0xdd853a2377c4c1cd };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r3, -28260\n"
- "shl16insli r3, r3, -3800\n"
- "shl16insli r3, r3, 26206\n"
- "shl16insli r3, r3, 20590\n"
- "moveli r43, -7555\n"
- "shl16insli r43, r43, -10473\n"
- "shl16insli r43, r43, 1769\n"
- "shl16insli r43, r43, 20859\n"
- "moveli r22, 31720\n"
- "shl16insli r22, r22, -26184\n"
- "shl16insli r22, r22, -29280\n"
- "shl16insli r22, r22, 21783\n"
- "{ fnop ; v1cmpeq r3, r43, r22 }\n"
- "move %0, r3\n"
- "move %1, r43\n"
- "move %2, r22\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1cmpeqi_X0.c b/none/tests/tilegx/insn_test_v1cmpeqi_X0.c
deleted file mode 100644
index b5300a6..0000000
--- a/none/tests/tilegx/insn_test_v1cmpeqi_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_v1cmpeqi_X0.c
-//op=239
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x645d1ce0b9aa791f, 0xdd076487e2dc381a };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r33, 6146\n"
- "shl16insli r33, r33, -18709\n"
- "shl16insli r33, r33, -4572\n"
- "shl16insli r33, r33, -2632\n"
- "moveli r27, 18247\n"
- "shl16insli r27, r27, 6533\n"
- "shl16insli r27, r27, 16990\n"
- "shl16insli r27, r27, 10640\n"
- "{ v1cmpeqi r33, r27, 110 ; fnop }\n"
- "move %0, r33\n"
- "move %1, r27\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1cmpeqi_X1.c b/none/tests/tilegx/insn_test_v1cmpeqi_X1.c
deleted file mode 100644
index e93dda4..0000000
--- a/none/tests/tilegx/insn_test_v1cmpeqi_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_v1cmpeqi_X1.c
-//op=239
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x645d1ce0b9aa791f, 0xdd076487e2dc381a };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r33, 6146\n"
- "shl16insli r33, r33, -18709\n"
- "shl16insli r33, r33, -4572\n"
- "shl16insli r33, r33, -2632\n"
- "moveli r27, 18247\n"
- "shl16insli r27, r27, 6533\n"
- "shl16insli r27, r27, 16990\n"
- "shl16insli r27, r27, 10640\n"
- "{ fnop ; v1cmpeqi r33, r27, 110 }\n"
- "move %0, r33\n"
- "move %1, r27\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1cmples_X0.c b/none/tests/tilegx/insn_test_v1cmples_X0.c
deleted file mode 100644
index 136d35b..0000000
--- a/none/tests/tilegx/insn_test_v1cmples_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1cmples_X0.c
-//op=240
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9cc2101465cdabcc, 0xfd529a461f919c3b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r30, -398\n"
- "shl16insli r30, r30, 9724\n"
- "shl16insli r30, r30, -28764\n"
- "shl16insli r30, r30, 25983\n"
- "moveli r39, -18162\n"
- "shl16insli r39, r39, 4413\n"
- "shl16insli r39, r39, 14247\n"
- "shl16insli r39, r39, 14892\n"
- "moveli r9, 10415\n"
- "shl16insli r9, r9, -24373\n"
- "shl16insli r9, r9, 23725\n"
- "shl16insli r9, r9, -29919\n"
- "{ v1cmples r30, r39, r9 ; fnop }\n"
- "move %0, r30\n"
- "move %1, r39\n"
- "move %2, r9\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1cmples_X1.c b/none/tests/tilegx/insn_test_v1cmples_X1.c
deleted file mode 100644
index 37bc683..0000000
--- a/none/tests/tilegx/insn_test_v1cmples_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1cmples_X1.c
-//op=240
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9cc2101465cdabcc, 0xfd529a461f919c3b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r30, -398\n"
- "shl16insli r30, r30, 9724\n"
- "shl16insli r30, r30, -28764\n"
- "shl16insli r30, r30, 25983\n"
- "moveli r39, -18162\n"
- "shl16insli r39, r39, 4413\n"
- "shl16insli r39, r39, 14247\n"
- "shl16insli r39, r39, 14892\n"
- "moveli r9, 10415\n"
- "shl16insli r9, r9, -24373\n"
- "shl16insli r9, r9, 23725\n"
- "shl16insli r9, r9, -29919\n"
- "{ fnop ; v1cmples r30, r39, r9 }\n"
- "move %0, r30\n"
- "move %1, r39\n"
- "move %2, r9\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1cmpleu_X0.c b/none/tests/tilegx/insn_test_v1cmpleu_X0.c
deleted file mode 100644
index 21d676d..0000000
--- a/none/tests/tilegx/insn_test_v1cmpleu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1cmpleu_X0.c
-//op=241
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xf650c1dfb5e7ad42, 0x58b08e812190ba77 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r3, -2057\n"
- "shl16insli r3, r3, 27159\n"
- "shl16insli r3, r3, -22172\n"
- "shl16insli r3, r3, 8048\n"
- "moveli r8, -12225\n"
- "shl16insli r8, r8, -10603\n"
- "shl16insli r8, r8, 1383\n"
- "shl16insli r8, r8, -9619\n"
- "moveli r14, -24673\n"
- "shl16insli r14, r14, 32616\n"
- "shl16insli r14, r14, 28197\n"
- "shl16insli r14, r14, -4516\n"
- "{ v1cmpleu r3, r8, r14 ; fnop }\n"
- "move %0, r3\n"
- "move %1, r8\n"
- "move %2, r14\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1cmpleu_X1.c b/none/tests/tilegx/insn_test_v1cmpleu_X1.c
deleted file mode 100644
index 9d80d16..0000000
--- a/none/tests/tilegx/insn_test_v1cmpleu_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1cmpleu_X1.c
-//op=241
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xf650c1dfb5e7ad42, 0x58b08e812190ba77 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r3, -2057\n"
- "shl16insli r3, r3, 27159\n"
- "shl16insli r3, r3, -22172\n"
- "shl16insli r3, r3, 8048\n"
- "moveli r8, -12225\n"
- "shl16insli r8, r8, -10603\n"
- "shl16insli r8, r8, 1383\n"
- "shl16insli r8, r8, -9619\n"
- "moveli r14, -24673\n"
- "shl16insli r14, r14, 32616\n"
- "shl16insli r14, r14, 28197\n"
- "shl16insli r14, r14, -4516\n"
- "{ fnop ; v1cmpleu r3, r8, r14 }\n"
- "move %0, r3\n"
- "move %1, r8\n"
- "move %2, r14\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1cmplts_X0.c b/none/tests/tilegx/insn_test_v1cmplts_X0.c
deleted file mode 100644
index ff6420f..0000000
--- a/none/tests/tilegx/insn_test_v1cmplts_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1cmplts_X0.c
-//op=242
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x955dd8bb2fd5225, 0xbf944e471ed68a09 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r24, -6390\n"
- "shl16insli r24, r24, 7138\n"
- "shl16insli r24, r24, -13688\n"
- "shl16insli r24, r24, 18787\n"
- "moveli r40, 19035\n"
- "shl16insli r40, r40, -3036\n"
- "shl16insli r40, r40, -31964\n"
- "shl16insli r40, r40, -9865\n"
- "moveli r0, -31939\n"
- "shl16insli r0, r0, 30972\n"
- "shl16insli r0, r0, 13500\n"
- "shl16insli r0, r0, 23688\n"
- "{ v1cmplts r24, r40, r0 ; fnop }\n"
- "move %0, r24\n"
- "move %1, r40\n"
- "move %2, r0\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1cmplts_X1.c b/none/tests/tilegx/insn_test_v1cmplts_X1.c
deleted file mode 100644
index be39062..0000000
--- a/none/tests/tilegx/insn_test_v1cmplts_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1cmplts_X1.c
-//op=242
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x955dd8bb2fd5225, 0xbf944e471ed68a09 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r24, -6390\n"
- "shl16insli r24, r24, 7138\n"
- "shl16insli r24, r24, -13688\n"
- "shl16insli r24, r24, 18787\n"
- "moveli r40, 19035\n"
- "shl16insli r40, r40, -3036\n"
- "shl16insli r40, r40, -31964\n"
- "shl16insli r40, r40, -9865\n"
- "moveli r0, -31939\n"
- "shl16insli r0, r0, 30972\n"
- "shl16insli r0, r0, 13500\n"
- "shl16insli r0, r0, 23688\n"
- "{ fnop ; v1cmplts r24, r40, r0 }\n"
- "move %0, r24\n"
- "move %1, r40\n"
- "move %2, r0\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1cmpltu_X0.c b/none/tests/tilegx/insn_test_v1cmpltu_X0.c
deleted file mode 100644
index af45358..0000000
--- a/none/tests/tilegx/insn_test_v1cmpltu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1cmpltu_X0.c
-//op=244
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x2044e3daa009dd78, 0xae053c723a6c8e37 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r40, 25454\n"
- "shl16insli r40, r40, 27378\n"
- "shl16insli r40, r40, 27144\n"
- "shl16insli r40, r40, -1050\n"
- "moveli r29, -3584\n"
- "shl16insli r29, r29, -12139\n"
- "shl16insli r29, r29, 27236\n"
- "shl16insli r29, r29, -11299\n"
- "moveli r36, -23497\n"
- "shl16insli r36, r36, 11245\n"
- "shl16insli r36, r36, 19779\n"
- "shl16insli r36, r36, 27653\n"
- "{ v1cmpltu r40, r29, r36 ; fnop }\n"
- "move %0, r40\n"
- "move %1, r29\n"
- "move %2, r36\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1cmpltu_X1.c b/none/tests/tilegx/insn_test_v1cmpltu_X1.c
deleted file mode 100644
index 05f8403..0000000
--- a/none/tests/tilegx/insn_test_v1cmpltu_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1cmpltu_X1.c
-//op=244
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x2044e3daa009dd78, 0xae053c723a6c8e37 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r40, 25454\n"
- "shl16insli r40, r40, 27378\n"
- "shl16insli r40, r40, 27144\n"
- "shl16insli r40, r40, -1050\n"
- "moveli r29, -3584\n"
- "shl16insli r29, r29, -12139\n"
- "shl16insli r29, r29, 27236\n"
- "shl16insli r29, r29, -11299\n"
- "moveli r36, -23497\n"
- "shl16insli r36, r36, 11245\n"
- "shl16insli r36, r36, 19779\n"
- "shl16insli r36, r36, 27653\n"
- "{ fnop ; v1cmpltu r40, r29, r36 }\n"
- "move %0, r40\n"
- "move %1, r29\n"
- "move %2, r36\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1cmpne_X0.c b/none/tests/tilegx/insn_test_v1cmpne_X0.c
deleted file mode 100644
index e666e77..0000000
--- a/none/tests/tilegx/insn_test_v1cmpne_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1cmpne_X0.c
-//op=246
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x333c2ba4f5fc0778, 0x71782df005cc3618 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r12, -4257\n"
- "shl16insli r12, r12, 16637\n"
- "shl16insli r12, r12, -13862\n"
- "shl16insli r12, r12, 2993\n"
- "moveli r28, 19170\n"
- "shl16insli r28, r28, -5999\n"
- "shl16insli r28, r28, 20031\n"
- "shl16insli r28, r28, -9404\n"
- "moveli r13, 24886\n"
- "shl16insli r13, r13, 6119\n"
- "shl16insli r13, r13, -23856\n"
- "shl16insli r13, r13, -8685\n"
- "{ v1cmpne r12, r28, r13 ; fnop }\n"
- "move %0, r12\n"
- "move %1, r28\n"
- "move %2, r13\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1cmpne_X1.c b/none/tests/tilegx/insn_test_v1cmpne_X1.c
deleted file mode 100644
index 7ab2489..0000000
--- a/none/tests/tilegx/insn_test_v1cmpne_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1cmpne_X1.c
-//op=246
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x333c2ba4f5fc0778, 0x71782df005cc3618 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r12, -4257\n"
- "shl16insli r12, r12, 16637\n"
- "shl16insli r12, r12, -13862\n"
- "shl16insli r12, r12, 2993\n"
- "moveli r28, 19170\n"
- "shl16insli r28, r28, -5999\n"
- "shl16insli r28, r28, 20031\n"
- "shl16insli r28, r28, -9404\n"
- "moveli r13, 24886\n"
- "shl16insli r13, r13, 6119\n"
- "shl16insli r13, r13, -23856\n"
- "shl16insli r13, r13, -8685\n"
- "{ fnop ; v1cmpne r12, r28, r13 }\n"
- "move %0, r12\n"
- "move %1, r28\n"
- "move %2, r13\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1ddotpu_X0.c b/none/tests/tilegx/insn_test_v1ddotpu_X0.c
deleted file mode 100644
index 4508259..0000000
--- a/none/tests/tilegx/insn_test_v1ddotpu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1ddotpu_X0.c
-//op=247
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc5185c9ad40a6c8e, 0x38d738cd6b643ded };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r38, -30305\n"
- "shl16insli r38, r38, -15724\n"
- "shl16insli r38, r38, 16680\n"
- "shl16insli r38, r38, -25985\n"
- "moveli r11, -14413\n"
- "shl16insli r11, r11, -6278\n"
- "shl16insli r11, r11, -14697\n"
- "shl16insli r11, r11, -23431\n"
- "moveli r4, 122\n"
- "shl16insli r4, r4, 8399\n"
- "shl16insli r4, r4, -22661\n"
- "shl16insli r4, r4, -9174\n"
- "{ v1ddotpu r38, r11, r4 ; fnop }\n"
- "move %0, r38\n"
- "move %1, r11\n"
- "move %2, r4\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1ddotpua_X0.c b/none/tests/tilegx/insn_test_v1ddotpua_X0.c
deleted file mode 100644
index 002537e..0000000
--- a/none/tests/tilegx/insn_test_v1ddotpua_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1ddotpua_X0.c
-//op=248
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xf81d7875fb56ceb1, 0x6d228375c43e27fe };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r26, 5758\n"
- "shl16insli r26, r26, -26380\n"
- "shl16insli r26, r26, 10010\n"
- "shl16insli r26, r26, 27850\n"
- "moveli r35, -28917\n"
- "shl16insli r35, r35, -6384\n"
- "shl16insli r35, r35, -11771\n"
- "shl16insli r35, r35, -16008\n"
- "moveli r48, -8573\n"
- "shl16insli r48, r48, 9318\n"
- "shl16insli r48, r48, -9607\n"
- "shl16insli r48, r48, 22154\n"
- "{ v1ddotpua r26, r35, r48 ; fnop }\n"
- "move %0, r26\n"
- "move %1, r35\n"
- "move %2, r48\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1ddotpus_X0.c b/none/tests/tilegx/insn_test_v1ddotpus_X0.c
deleted file mode 100644
index 99e822a..0000000
--- a/none/tests/tilegx/insn_test_v1ddotpus_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1ddotpus_X0.c
-//op=249
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9870e08023534828, 0x669e8333dc6e20a4 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r35, 27899\n"
- "shl16insli r35, r35, -1363\n"
- "shl16insli r35, r35, 695\n"
- "shl16insli r35, r35, -3150\n"
- "moveli r47, -31722\n"
- "shl16insli r47, r47, 28986\n"
- "shl16insli r47, r47, -27906\n"
- "shl16insli r47, r47, -13798\n"
- "moveli r39, 32546\n"
- "shl16insli r39, r39, -25949\n"
- "shl16insli r39, r39, -2759\n"
- "shl16insli r39, r39, -21019\n"
- "{ v1ddotpus r35, r47, r39 ; fnop }\n"
- "move %0, r35\n"
- "move %1, r47\n"
- "move %2, r39\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1ddotpusa_X0.c b/none/tests/tilegx/insn_test_v1ddotpusa_X0.c
deleted file mode 100644
index ce1e557..0000000
--- a/none/tests/tilegx/insn_test_v1ddotpusa_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1ddotpusa_X0.c
-//op=250
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x3ae24f779a8d3dc, 0x6bfa391c07b5ae93 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r29, 11405\n"
- "shl16insli r29, r29, 16621\n"
- "shl16insli r29, r29, -29926\n"
- "shl16insli r29, r29, -21425\n"
- "moveli r22, 29339\n"
- "shl16insli r22, r22, -30280\n"
- "shl16insli r22, r22, 6890\n"
- "shl16insli r22, r22, 27358\n"
- "moveli r1, 30556\n"
- "shl16insli r1, r1, -25484\n"
- "shl16insli r1, r1, 28103\n"
- "shl16insli r1, r1, 12543\n"
- "{ v1ddotpusa r29, r22, r1 ; fnop }\n"
- "move %0, r29\n"
- "move %1, r22\n"
- "move %2, r1\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1dotp_X0.c b/none/tests/tilegx/insn_test_v1dotp_X0.c
deleted file mode 100644
index b23f637..0000000
--- a/none/tests/tilegx/insn_test_v1dotp_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1dotp_X0.c
-//op=251
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x7b812106b9ba177f, 0xa91bb9da3e399735 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r3, -2452\n"
- "shl16insli r3, r3, -32096\n"
- "shl16insli r3, r3, -11540\n"
- "shl16insli r3, r3, 18694\n"
- "moveli r42, -335\n"
- "shl16insli r42, r42, -26011\n"
- "shl16insli r42, r42, -23631\n"
- "shl16insli r42, r42, -1594\n"
- "moveli r44, -16908\n"
- "shl16insli r44, r44, -28320\n"
- "shl16insli r44, r44, 5956\n"
- "shl16insli r44, r44, 28904\n"
- "{ v1dotp r3, r42, r44 ; fnop }\n"
- "move %0, r3\n"
- "move %1, r42\n"
- "move %2, r44\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1dotpa_X0.c b/none/tests/tilegx/insn_test_v1dotpa_X0.c
deleted file mode 100644
index 8914add..0000000
--- a/none/tests/tilegx/insn_test_v1dotpa_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1dotpa_X0.c
-//op=252
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd02416e43b19c3f1, 0xb50b19b244ac7eb4 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r4, 15584\n"
- "shl16insli r4, r4, -16025\n"
- "shl16insli r4, r4, 24621\n"
- "shl16insli r4, r4, -25450\n"
- "moveli r7, 14194\n"
- "shl16insli r7, r7, 6886\n"
- "shl16insli r7, r7, -25858\n"
- "shl16insli r7, r7, -24609\n"
- "moveli r0, 12923\n"
- "shl16insli r0, r0, -8055\n"
- "shl16insli r0, r0, -31361\n"
- "shl16insli r0, r0, -7893\n"
- "{ v1dotpa r4, r7, r0 ; fnop }\n"
- "move %0, r4\n"
- "move %1, r7\n"
- "move %2, r0\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1dotpu_X0.c b/none/tests/tilegx/insn_test_v1dotpu_X0.c
deleted file mode 100644
index 21d304f..0000000
--- a/none/tests/tilegx/insn_test_v1dotpu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1dotpu_X0.c
-//op=253
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xb9d12319fbf02182, 0x42d3871d0b55e0e5 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r20, 7058\n"
- "shl16insli r20, r20, -10273\n"
- "shl16insli r20, r20, -27400\n"
- "shl16insli r20, r20, 410\n"
- "moveli r27, -1572\n"
- "shl16insli r27, r27, 7162\n"
- "shl16insli r27, r27, -2477\n"
- "shl16insli r27, r27, -2756\n"
- "moveli r46, -23264\n"
- "shl16insli r46, r46, 16614\n"
- "shl16insli r46, r46, 28637\n"
- "shl16insli r46, r46, 17411\n"
- "{ v1dotpu r20, r27, r46 ; fnop }\n"
- "move %0, r20\n"
- "move %1, r27\n"
- "move %2, r46\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1dotpua_X0.c b/none/tests/tilegx/insn_test_v1dotpua_X0.c
deleted file mode 100644
index 420c372..0000000
--- a/none/tests/tilegx/insn_test_v1dotpua_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1dotpua_X0.c
-//op=254
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xba522198b7685638, 0x5038bdaa45b53cd3 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r20, -30432\n"
- "shl16insli r20, r20, -21685\n"
- "shl16insli r20, r20, -14635\n"
- "shl16insli r20, r20, 15094\n"
- "moveli r49, 3435\n"
- "shl16insli r49, r49, 5337\n"
- "shl16insli r49, r49, 12729\n"
- "shl16insli r49, r49, -31162\n"
- "moveli r38, -23611\n"
- "shl16insli r38, r38, 9907\n"
- "shl16insli r38, r38, 19129\n"
- "shl16insli r38, r38, 30763\n"
- "{ v1dotpua r20, r49, r38 ; fnop }\n"
- "move %0, r20\n"
- "move %1, r49\n"
- "move %2, r38\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1dotpus_X0.c b/none/tests/tilegx/insn_test_v1dotpus_X0.c
deleted file mode 100644
index 4663f44..0000000
--- a/none/tests/tilegx/insn_test_v1dotpus_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1dotpus_X0.c
-//op=255
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xff2786a3390067bd, 0x12d0fd16d91f87d7 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r30, -20178\n"
- "shl16insli r30, r30, 16109\n"
- "shl16insli r30, r30, -17955\n"
- "shl16insli r30, r30, 766\n"
- "moveli r30, -16791\n"
- "shl16insli r30, r30, -775\n"
- "shl16insli r30, r30, 8064\n"
- "shl16insli r30, r30, 31392\n"
- "moveli r48, 2300\n"
- "shl16insli r48, r48, 6845\n"
- "shl16insli r48, r48, -2405\n"
- "shl16insli r48, r48, 31247\n"
- "{ v1dotpus r30, r30, r48 ; fnop }\n"
- "move %0, r30\n"
- "move %1, r30\n"
- "move %2, r48\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1dotpusa_X0.c b/none/tests/tilegx/insn_test_v1dotpusa_X0.c
deleted file mode 100644
index 64fa1fe..0000000
--- a/none/tests/tilegx/insn_test_v1dotpusa_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1dotpusa_X0.c
-//op=256
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xea3e8d37b6aff6fb, 0xcef60e4c85b01644 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r11, 26537\n"
- "shl16insli r11, r11, -7716\n"
- "shl16insli r11, r11, 24513\n"
- "shl16insli r11, r11, 8687\n"
- "moveli r35, -7218\n"
- "shl16insli r35, r35, 7896\n"
- "shl16insli r35, r35, -22888\n"
- "shl16insli r35, r35, -25968\n"
- "moveli r39, -6406\n"
- "shl16insli r39, r39, -8101\n"
- "shl16insli r39, r39, 21933\n"
- "shl16insli r39, r39, 5916\n"
- "{ v1dotpusa r11, r35, r39 ; fnop }\n"
- "move %0, r11\n"
- "move %1, r35\n"
- "move %2, r39\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1int_h_X0.c b/none/tests/tilegx/insn_test_v1int_h_X0.c
deleted file mode 100644
index 935bc44..0000000
--- a/none/tests/tilegx/insn_test_v1int_h_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1int_h_X0.c
-//op=257
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xe9a8302931b95203, 0x70bdff1ab2dd150d };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r21, 8325\n"
- "shl16insli r21, r21, -18852\n"
- "shl16insli r21, r21, 5136\n"
- "shl16insli r21, r21, 25114\n"
- "moveli r14, -28465\n"
- "shl16insli r14, r14, -20971\n"
- "shl16insli r14, r14, 28669\n"
- "shl16insli r14, r14, 5613\n"
- "moveli r17, -533\n"
- "shl16insli r17, r17, -12789\n"
- "shl16insli r17, r17, -10981\n"
- "shl16insli r17, r17, -30754\n"
- "{ v1int_h r21, r14, r17 ; fnop }\n"
- "move %0, r21\n"
- "move %1, r14\n"
- "move %2, r17\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1int_h_X1.c b/none/tests/tilegx/insn_test_v1int_h_X1.c
deleted file mode 100644
index 982962c..0000000
--- a/none/tests/tilegx/insn_test_v1int_h_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1int_h_X1.c
-//op=257
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xe9a8302931b95203, 0x70bdff1ab2dd150d };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r21, 8325\n"
- "shl16insli r21, r21, -18852\n"
- "shl16insli r21, r21, 5136\n"
- "shl16insli r21, r21, 25114\n"
- "moveli r14, -28465\n"
- "shl16insli r14, r14, -20971\n"
- "shl16insli r14, r14, 28669\n"
- "shl16insli r14, r14, 5613\n"
- "moveli r17, -533\n"
- "shl16insli r17, r17, -12789\n"
- "shl16insli r17, r17, -10981\n"
- "shl16insli r17, r17, -30754\n"
- "{ fnop ; v1int_h r21, r14, r17 }\n"
- "move %0, r21\n"
- "move %1, r14\n"
- "move %2, r17\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1int_l_X0.c b/none/tests/tilegx/insn_test_v1int_l_X0.c
deleted file mode 100644
index 4bac650..0000000
--- a/none/tests/tilegx/insn_test_v1int_l_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1int_l_X0.c
-//op=258
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x25203e3a92c5e67a, 0x3ab13aa81a1f8e6 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r16, 16040\n"
- "shl16insli r16, r16, 13539\n"
- "shl16insli r16, r16, -10611\n"
- "shl16insli r16, r16, 18456\n"
- "moveli r1, -8860\n"
- "shl16insli r1, r1, 10696\n"
- "shl16insli r1, r1, -32518\n"
- "shl16insli r1, r1, 20582\n"
- "moveli r32, 25660\n"
- "shl16insli r32, r32, -31058\n"
- "shl16insli r32, r32, 3321\n"
- "shl16insli r32, r32, 742\n"
- "{ v1int_l r16, r1, r32 ; fnop }\n"
- "move %0, r16\n"
- "move %1, r1\n"
- "move %2, r32\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1int_l_X1.c b/none/tests/tilegx/insn_test_v1int_l_X1.c
deleted file mode 100644
index a610b85..0000000
--- a/none/tests/tilegx/insn_test_v1int_l_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1int_l_X1.c
-//op=258
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x25203e3a92c5e67a, 0x3ab13aa81a1f8e6 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r16, 16040\n"
- "shl16insli r16, r16, 13539\n"
- "shl16insli r16, r16, -10611\n"
- "shl16insli r16, r16, 18456\n"
- "moveli r1, -8860\n"
- "shl16insli r1, r1, 10696\n"
- "shl16insli r1, r1, -32518\n"
- "shl16insli r1, r1, 20582\n"
- "moveli r32, 25660\n"
- "shl16insli r32, r32, -31058\n"
- "shl16insli r32, r32, 3321\n"
- "shl16insli r32, r32, 742\n"
- "{ fnop ; v1int_l r16, r1, r32 }\n"
- "move %0, r16\n"
- "move %1, r1\n"
- "move %2, r32\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1maxu_X0.c b/none/tests/tilegx/insn_test_v1maxu_X0.c
deleted file mode 100644
index 4098831..0000000
--- a/none/tests/tilegx/insn_test_v1maxu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1maxu_X0.c
-//op=259
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x5555b89e33103d34, 0x72ce0e1d1ecdfc7b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r7, 31643\n"
- "shl16insli r7, r7, -418\n"
- "shl16insli r7, r7, -25830\n"
- "shl16insli r7, r7, 267\n"
- "moveli r17, 21415\n"
- "shl16insli r17, r17, 28561\n"
- "shl16insli r17, r17, 26253\n"
- "shl16insli r17, r17, -24335\n"
- "moveli r5, -8528\n"
- "shl16insli r5, r5, 8536\n"
- "shl16insli r5, r5, -30783\n"
- "shl16insli r5, r5, 721\n"
- "{ v1maxu r7, r17, r5 ; fnop }\n"
- "move %0, r7\n"
- "move %1, r17\n"
- "move %2, r5\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1maxu_X1.c b/none/tests/tilegx/insn_test_v1maxu_X1.c
deleted file mode 100644
index baaa366..0000000
--- a/none/tests/tilegx/insn_test_v1maxu_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1maxu_X1.c
-//op=259
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x5555b89e33103d34, 0x72ce0e1d1ecdfc7b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r7, 31643\n"
- "shl16insli r7, r7, -418\n"
- "shl16insli r7, r7, -25830\n"
- "shl16insli r7, r7, 267\n"
- "moveli r17, 21415\n"
- "shl16insli r17, r17, 28561\n"
- "shl16insli r17, r17, 26253\n"
- "shl16insli r17, r17, -24335\n"
- "moveli r5, -8528\n"
- "shl16insli r5, r5, 8536\n"
- "shl16insli r5, r5, -30783\n"
- "shl16insli r5, r5, 721\n"
- "{ fnop ; v1maxu r7, r17, r5 }\n"
- "move %0, r7\n"
- "move %1, r17\n"
- "move %2, r5\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1minu_X0.c b/none/tests/tilegx/insn_test_v1minu_X0.c
deleted file mode 100644
index a29cd79..0000000
--- a/none/tests/tilegx/insn_test_v1minu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1minu_X0.c
-//op=261
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xe5ffde572843204c, 0xf80a73ea5b48cd2e };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r48, -8159\n"
- "shl16insli r48, r48, -19405\n"
- "shl16insli r48, r48, -6882\n"
- "shl16insli r48, r48, 24332\n"
- "moveli r5, 588\n"
- "shl16insli r5, r5, 25418\n"
- "shl16insli r5, r5, -27674\n"
- "shl16insli r5, r5, 2111\n"
- "moveli r23, -19496\n"
- "shl16insli r23, r23, -22831\n"
- "shl16insli r23, r23, -22278\n"
- "shl16insli r23, r23, 2692\n"
- "{ v1minu r48, r5, r23 ; fnop }\n"
- "move %0, r48\n"
- "move %1, r5\n"
- "move %2, r23\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1minu_X1.c b/none/tests/tilegx/insn_test_v1minu_X1.c
deleted file mode 100644
index 5ed1440..0000000
--- a/none/tests/tilegx/insn_test_v1minu_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1minu_X1.c
-//op=261
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xe5ffde572843204c, 0xf80a73ea5b48cd2e };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r48, -8159\n"
- "shl16insli r48, r48, -19405\n"
- "shl16insli r48, r48, -6882\n"
- "shl16insli r48, r48, 24332\n"
- "moveli r5, 588\n"
- "shl16insli r5, r5, 25418\n"
- "shl16insli r5, r5, -27674\n"
- "shl16insli r5, r5, 2111\n"
- "moveli r23, -19496\n"
- "shl16insli r23, r23, -22831\n"
- "shl16insli r23, r23, -22278\n"
- "shl16insli r23, r23, 2692\n"
- "{ fnop ; v1minu r48, r5, r23 }\n"
- "move %0, r48\n"
- "move %1, r5\n"
- "move %2, r23\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1mnz_X0.c b/none/tests/tilegx/insn_test_v1mnz_X0.c
deleted file mode 100644
index b5b2d8f..0000000
--- a/none/tests/tilegx/insn_test_v1mnz_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1mnz_X0.c
-//op=263
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x3713ce4eed37fdb1, 0xb8fb1c28cc3fba32 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r37, -32459\n"
- "shl16insli r37, r37, 16523\n"
- "shl16insli r37, r37, 2092\n"
- "shl16insli r37, r37, -8699\n"
- "moveli r5, 8954\n"
- "shl16insli r5, r5, 9384\n"
- "shl16insli r5, r5, 3635\n"
- "shl16insli r5, r5, -28024\n"
- "moveli r22, 7513\n"
- "shl16insli r22, r22, -1317\n"
- "shl16insli r22, r22, 32450\n"
- "shl16insli r22, r22, -11880\n"
- "{ v1mnz r37, r5, r22 ; fnop }\n"
- "move %0, r37\n"
- "move %1, r5\n"
- "move %2, r22\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1mnz_X1.c b/none/tests/tilegx/insn_test_v1mnz_X1.c
deleted file mode 100644
index 1dd3d93..0000000
--- a/none/tests/tilegx/insn_test_v1mnz_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1mnz_X1.c
-//op=263
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x3713ce4eed37fdb1, 0xb8fb1c28cc3fba32 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r37, -32459\n"
- "shl16insli r37, r37, 16523\n"
- "shl16insli r37, r37, 2092\n"
- "shl16insli r37, r37, -8699\n"
- "moveli r5, 8954\n"
- "shl16insli r5, r5, 9384\n"
- "shl16insli r5, r5, 3635\n"
- "shl16insli r5, r5, -28024\n"
- "moveli r22, 7513\n"
- "shl16insli r22, r22, -1317\n"
- "shl16insli r22, r22, 32450\n"
- "shl16insli r22, r22, -11880\n"
- "{ fnop ; v1mnz r37, r5, r22 }\n"
- "move %0, r37\n"
- "move %1, r5\n"
- "move %2, r22\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1multu_X0.c b/none/tests/tilegx/insn_test_v1multu_X0.c
deleted file mode 100644
index b83e49f..0000000
--- a/none/tests/tilegx/insn_test_v1multu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1multu_X0.c
-//op=264
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x68357d0341698c99, 0x3076e248a1b03309 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r41, 3184\n"
- "shl16insli r41, r41, 7750\n"
- "shl16insli r41, r41, -24327\n"
- "shl16insli r41, r41, 22846\n"
- "moveli r20, -22618\n"
- "shl16insli r20, r20, 24630\n"
- "shl16insli r20, r20, -15349\n"
- "shl16insli r20, r20, 29173\n"
- "moveli r44, 21939\n"
- "shl16insli r44, r44, 20800\n"
- "shl16insli r44, r44, 15363\n"
- "shl16insli r44, r44, -32405\n"
- "{ v1multu r41, r20, r44 ; fnop }\n"
- "move %0, r41\n"
- "move %1, r20\n"
- "move %2, r44\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1mulu_X0.c b/none/tests/tilegx/insn_test_v1mulu_X0.c
deleted file mode 100644
index 5103f66..0000000
--- a/none/tests/tilegx/insn_test_v1mulu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1mulu_X0.c
-//op=265
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xc6ae3df2f165e603, 0x4124d3b9cd881478 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r27, -8005\n"
- "shl16insli r27, r27, 29496\n"
- "shl16insli r27, r27, 24596\n"
- "shl16insli r27, r27, 10312\n"
- "moveli r8, -21695\n"
- "shl16insli r8, r8, 9862\n"
- "shl16insli r8, r8, -14356\n"
- "shl16insli r8, r8, -32187\n"
- "moveli r13, -16854\n"
- "shl16insli r13, r13, 30079\n"
- "shl16insli r13, r13, -7543\n"
- "shl16insli r13, r13, 13209\n"
- "{ v1mulu r27, r8, r13 ; fnop }\n"
- "move %0, r27\n"
- "move %1, r8\n"
- "move %2, r13\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1mulus_X0.c b/none/tests/tilegx/insn_test_v1mulus_X0.c
deleted file mode 100644
index 1494618..0000000
--- a/none/tests/tilegx/insn_test_v1mulus_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1mulus_X0.c
-//op=266
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x88507c682c9fb1d4, 0xe99ff6bbb270ebf };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r14, -18039\n"
- "shl16insli r14, r14, 4267\n"
- "shl16insli r14, r14, 12150\n"
- "shl16insli r14, r14, 11106\n"
- "moveli r3, 24521\n"
- "shl16insli r3, r3, -15738\n"
- "shl16insli r3, r3, -31870\n"
- "shl16insli r3, r3, -24660\n"
- "moveli r15, -31630\n"
- "shl16insli r15, r15, -11693\n"
- "shl16insli r15, r15, 19273\n"
- "shl16insli r15, r15, 31577\n"
- "{ v1mulus r14, r3, r15 ; fnop }\n"
- "move %0, r14\n"
- "move %1, r3\n"
- "move %2, r15\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1mz_X0.c b/none/tests/tilegx/insn_test_v1mz_X0.c
deleted file mode 100644
index a152275..0000000
--- a/none/tests/tilegx/insn_test_v1mz_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1mz_X0.c
-//op=267
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x1b3ff0e0443a3be1, 0x220687ea6e937cd5 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r38, 4964\n"
- "shl16insli r38, r38, -27298\n"
- "shl16insli r38, r38, 27287\n"
- "shl16insli r38, r38, 25242\n"
- "moveli r45, 12630\n"
- "shl16insli r45, r45, 24867\n"
- "shl16insli r45, r45, -32060\n"
- "shl16insli r45, r45, 29383\n"
- "moveli r38, -6355\n"
- "shl16insli r38, r38, -29829\n"
- "shl16insli r38, r38, 8624\n"
- "shl16insli r38, r38, -6732\n"
- "{ v1mz r38, r45, r38 ; fnop }\n"
- "move %0, r38\n"
- "move %1, r45\n"
- "move %2, r38\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1mz_X1.c b/none/tests/tilegx/insn_test_v1mz_X1.c
deleted file mode 100644
index d7c8755..0000000
--- a/none/tests/tilegx/insn_test_v1mz_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1mz_X1.c
-//op=267
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x1b3ff0e0443a3be1, 0x220687ea6e937cd5 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r38, 4964\n"
- "shl16insli r38, r38, -27298\n"
- "shl16insli r38, r38, 27287\n"
- "shl16insli r38, r38, 25242\n"
- "moveli r45, 12630\n"
- "shl16insli r45, r45, 24867\n"
- "shl16insli r45, r45, -32060\n"
- "shl16insli r45, r45, 29383\n"
- "moveli r38, -6355\n"
- "shl16insli r38, r38, -29829\n"
- "shl16insli r38, r38, 8624\n"
- "shl16insli r38, r38, -6732\n"
- "{ fnop ; v1mz r38, r45, r38 }\n"
- "move %0, r38\n"
- "move %1, r45\n"
- "move %2, r38\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1sadau_X0.c b/none/tests/tilegx/insn_test_v1sadau_X0.c
deleted file mode 100644
index 155f814..0000000
--- a/none/tests/tilegx/insn_test_v1sadau_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1sadau_X0.c
-//op=268
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x75810b48447f8cd8, 0x2f3ac3e001892397 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r15, 16969\n"
- "shl16insli r15, r15, 21355\n"
- "shl16insli r15, r15, -13594\n"
- "shl16insli r15, r15, 31543\n"
- "moveli r46, -32304\n"
- "shl16insli r46, r46, 5880\n"
- "shl16insli r46, r46, 26751\n"
- "shl16insli r46, r46, 15077\n"
- "moveli r45, -22749\n"
- "shl16insli r45, r45, -6105\n"
- "shl16insli r45, r45, 23283\n"
- "shl16insli r45, r45, 28386\n"
- "{ v1sadau r15, r46, r45 ; fnop }\n"
- "move %0, r15\n"
- "move %1, r46\n"
- "move %2, r45\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1sadu_X0.c b/none/tests/tilegx/insn_test_v1sadu_X0.c
deleted file mode 100644
index 99b77bf..0000000
--- a/none/tests/tilegx/insn_test_v1sadu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1sadu_X0.c
-//op=269
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xdb49fd06b08ce7b9, 0xa5181ef50e01b108 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r23, 21116\n"
- "shl16insli r23, r23, 9443\n"
- "shl16insli r23, r23, -5433\n"
- "shl16insli r23, r23, -6455\n"
- "moveli r15, 21546\n"
- "shl16insli r15, r15, -20814\n"
- "shl16insli r15, r15, -29149\n"
- "shl16insli r15, r15, 28694\n"
- "moveli r5, 9956\n"
- "shl16insli r5, r5, -29770\n"
- "shl16insli r5, r5, 32138\n"
- "shl16insli r5, r5, 24785\n"
- "{ v1sadu r23, r15, r5 ; fnop }\n"
- "move %0, r23\n"
- "move %1, r15\n"
- "move %2, r5\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1shl_X0.c b/none/tests/tilegx/insn_test_v1shl_X0.c
deleted file mode 100644
index 3fd853d..0000000
--- a/none/tests/tilegx/insn_test_v1shl_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1shl_X0.c
-//op=270
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xe89dbdd9027e7e2c, 0x8f37eee6381b10aa };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r47, 31287\n"
- "shl16insli r47, r47, -16865\n"
- "shl16insli r47, r47, 32203\n"
- "shl16insli r47, r47, 26808\n"
- "moveli r20, -31597\n"
- "shl16insli r20, r20, -25798\n"
- "shl16insli r20, r20, 24137\n"
- "shl16insli r20, r20, -18758\n"
- "moveli r18, 29925\n"
- "shl16insli r18, r18, -28562\n"
- "shl16insli r18, r18, 19610\n"
- "shl16insli r18, r18, 28019\n"
- "{ v1shl r47, r20, r18 ; fnop }\n"
- "move %0, r47\n"
- "move %1, r20\n"
- "move %2, r18\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1shl_X1.c b/none/tests/tilegx/insn_test_v1shl_X1.c
deleted file mode 100644
index c183230..0000000
--- a/none/tests/tilegx/insn_test_v1shl_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1shl_X1.c
-//op=270
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xe89dbdd9027e7e2c, 0x8f37eee6381b10aa };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r47, 31287\n"
- "shl16insli r47, r47, -16865\n"
- "shl16insli r47, r47, 32203\n"
- "shl16insli r47, r47, 26808\n"
- "moveli r20, -31597\n"
- "shl16insli r20, r20, -25798\n"
- "shl16insli r20, r20, 24137\n"
- "shl16insli r20, r20, -18758\n"
- "moveli r18, 29925\n"
- "shl16insli r18, r18, -28562\n"
- "shl16insli r18, r18, 19610\n"
- "shl16insli r18, r18, 28019\n"
- "{ fnop ; v1shl r47, r20, r18 }\n"
- "move %0, r47\n"
- "move %1, r20\n"
- "move %2, r18\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1shli_X0.c b/none/tests/tilegx/insn_test_v1shli_X0.c
deleted file mode 100644
index 981c25e..0000000
--- a/none/tests/tilegx/insn_test_v1shli_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_v1shli_X0.c
-//op=271
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x83de1f8744af2d85, 0x6f2ecad32a189723 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r16, -23389\n"
- "shl16insli r16, r16, 14250\n"
- "shl16insli r16, r16, -12431\n"
- "shl16insli r16, r16, 3789\n"
- "moveli r46, 12068\n"
- "shl16insli r46, r46, 8339\n"
- "shl16insli r46, r46, 11978\n"
- "shl16insli r46, r46, 15868\n"
- "{ v1shli r16, r46, 47 ; fnop }\n"
- "move %0, r16\n"
- "move %1, r46\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1shli_X1.c b/none/tests/tilegx/insn_test_v1shli_X1.c
deleted file mode 100644
index 9515057..0000000
--- a/none/tests/tilegx/insn_test_v1shli_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_v1shli_X1.c
-//op=271
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x83de1f8744af2d85, 0x6f2ecad32a189723 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r16, -23389\n"
- "shl16insli r16, r16, 14250\n"
- "shl16insli r16, r16, -12431\n"
- "shl16insli r16, r16, 3789\n"
- "moveli r46, 12068\n"
- "shl16insli r46, r46, 8339\n"
- "shl16insli r46, r46, 11978\n"
- "shl16insli r46, r46, 15868\n"
- "{ fnop ; v1shli r16, r46, 47 }\n"
- "move %0, r16\n"
- "move %1, r46\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1shrs_X0.c b/none/tests/tilegx/insn_test_v1shrs_X0.c
deleted file mode 100644
index ac5bfdf..0000000
--- a/none/tests/tilegx/insn_test_v1shrs_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1shrs_X0.c
-//op=272
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x63cf7032972114e1, 0x25733d8b5dc477b4 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r22, -18049\n"
- "shl16insli r22, r22, 22607\n"
- "shl16insli r22, r22, -26435\n"
- "shl16insli r22, r22, 16640\n"
- "moveli r0, -23960\n"
- "shl16insli r0, r0, 21412\n"
- "shl16insli r0, r0, 5756\n"
- "shl16insli r0, r0, -23361\n"
- "moveli r30, -27381\n"
- "shl16insli r30, r30, -5985\n"
- "shl16insli r30, r30, 29874\n"
- "shl16insli r30, r30, 15106\n"
- "{ v1shrs r22, r0, r30 ; fnop }\n"
- "move %0, r22\n"
- "move %1, r0\n"
- "move %2, r30\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1shrs_X1.c b/none/tests/tilegx/insn_test_v1shrs_X1.c
deleted file mode 100644
index c5c27ae..0000000
--- a/none/tests/tilegx/insn_test_v1shrs_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1shrs_X1.c
-//op=272
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x63cf7032972114e1, 0x25733d8b5dc477b4 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r22, -18049\n"
- "shl16insli r22, r22, 22607\n"
- "shl16insli r22, r22, -26435\n"
- "shl16insli r22, r22, 16640\n"
- "moveli r0, -23960\n"
- "shl16insli r0, r0, 21412\n"
- "shl16insli r0, r0, 5756\n"
- "shl16insli r0, r0, -23361\n"
- "moveli r30, -27381\n"
- "shl16insli r30, r30, -5985\n"
- "shl16insli r30, r30, 29874\n"
- "shl16insli r30, r30, 15106\n"
- "{ fnop ; v1shrs r22, r0, r30 }\n"
- "move %0, r22\n"
- "move %1, r0\n"
- "move %2, r30\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1shrsi_X0.c b/none/tests/tilegx/insn_test_v1shrsi_X0.c
deleted file mode 100644
index c416ab7..0000000
--- a/none/tests/tilegx/insn_test_v1shrsi_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_v1shrsi_X0.c
-//op=273
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x99db15856c0b4de, 0x7721cf058b98c6d4 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r5, -12155\n"
- "shl16insli r5, r5, -29090\n"
- "shl16insli r5, r5, 11972\n"
- "shl16insli r5, r5, -26553\n"
- "moveli r17, 13958\n"
- "shl16insli r17, r17, -23061\n"
- "shl16insli r17, r17, -20\n"
- "shl16insli r17, r17, 9148\n"
- "{ v1shrsi r5, r17, 58 ; fnop }\n"
- "move %0, r5\n"
- "move %1, r17\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1shrsi_X1.c b/none/tests/tilegx/insn_test_v1shrsi_X1.c
deleted file mode 100644
index 9227f28..0000000
--- a/none/tests/tilegx/insn_test_v1shrsi_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_v1shrsi_X1.c
-//op=273
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x99db15856c0b4de, 0x7721cf058b98c6d4 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r5, -12155\n"
- "shl16insli r5, r5, -29090\n"
- "shl16insli r5, r5, 11972\n"
- "shl16insli r5, r5, -26553\n"
- "moveli r17, 13958\n"
- "shl16insli r17, r17, -23061\n"
- "shl16insli r17, r17, -20\n"
- "shl16insli r17, r17, 9148\n"
- "{ fnop ; v1shrsi r5, r17, 58 }\n"
- "move %0, r5\n"
- "move %1, r17\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1shru_X0.c b/none/tests/tilegx/insn_test_v1shru_X0.c
deleted file mode 100644
index 70da6ba..0000000
--- a/none/tests/tilegx/insn_test_v1shru_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1shru_X0.c
-//op=274
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9e4137a4fbfd19fc, 0xe11d6a52db1557dd };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r19, -27667\n"
- "shl16insli r19, r19, -7882\n"
- "shl16insli r19, r19, 17186\n"
- "shl16insli r19, r19, 17173\n"
- "moveli r1, 31681\n"
- "shl16insli r1, r1, 6366\n"
- "shl16insli r1, r1, -2389\n"
- "shl16insli r1, r1, 19110\n"
- "moveli r25, 16926\n"
- "shl16insli r25, r25, -28231\n"
- "shl16insli r25, r25, -13659\n"
- "shl16insli r25, r25, 19027\n"
- "{ v1shru r19, r1, r25 ; fnop }\n"
- "move %0, r19\n"
- "move %1, r1\n"
- "move %2, r25\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1shru_X1.c b/none/tests/tilegx/insn_test_v1shru_X1.c
deleted file mode 100644
index f28a8c0..0000000
--- a/none/tests/tilegx/insn_test_v1shru_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1shru_X1.c
-//op=274
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9e4137a4fbfd19fc, 0xe11d6a52db1557dd };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r19, -27667\n"
- "shl16insli r19, r19, -7882\n"
- "shl16insli r19, r19, 17186\n"
- "shl16insli r19, r19, 17173\n"
- "moveli r1, 31681\n"
- "shl16insli r1, r1, 6366\n"
- "shl16insli r1, r1, -2389\n"
- "shl16insli r1, r1, 19110\n"
- "moveli r25, 16926\n"
- "shl16insli r25, r25, -28231\n"
- "shl16insli r25, r25, -13659\n"
- "shl16insli r25, r25, 19027\n"
- "{ fnop ; v1shru r19, r1, r25 }\n"
- "move %0, r19\n"
- "move %1, r1\n"
- "move %2, r25\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1shrui_X0.c b/none/tests/tilegx/insn_test_v1shrui_X0.c
deleted file mode 100644
index 081c275..0000000
--- a/none/tests/tilegx/insn_test_v1shrui_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_v1shrui_X0.c
-//op=275
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x420e29019dd4c946, 0x562bb4e51ed838f4 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r11, -14185\n"
- "shl16insli r11, r11, 11751\n"
- "shl16insli r11, r11, 25109\n"
- "shl16insli r11, r11, 30569\n"
- "moveli r18, 3022\n"
- "shl16insli r18, r18, -17758\n"
- "shl16insli r18, r18, 25795\n"
- "shl16insli r18, r18, 7417\n"
- "{ v1shrui r11, r18, 41 ; fnop }\n"
- "move %0, r11\n"
- "move %1, r18\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1shrui_X1.c b/none/tests/tilegx/insn_test_v1shrui_X1.c
deleted file mode 100644
index 792afcb..0000000
--- a/none/tests/tilegx/insn_test_v1shrui_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_v1shrui_X1.c
-//op=275
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x420e29019dd4c946, 0x562bb4e51ed838f4 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r11, -14185\n"
- "shl16insli r11, r11, 11751\n"
- "shl16insli r11, r11, 25109\n"
- "shl16insli r11, r11, 30569\n"
- "moveli r18, 3022\n"
- "shl16insli r18, r18, -17758\n"
- "shl16insli r18, r18, 25795\n"
- "shl16insli r18, r18, 7417\n"
- "{ fnop ; v1shrui r11, r18, 41 }\n"
- "move %0, r11\n"
- "move %1, r18\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1sub_X0.c b/none/tests/tilegx/insn_test_v1sub_X0.c
deleted file mode 100644
index d32340f..0000000
--- a/none/tests/tilegx/insn_test_v1sub_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1sub_X0.c
-//op=276
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x1fe54969a93a157a, 0x778f2f6f17d9003b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r44, 21888\n"
- "shl16insli r44, r44, -8663\n"
- "shl16insli r44, r44, -14905\n"
- "shl16insli r44, r44, -14362\n"
- "moveli r26, -18766\n"
- "shl16insli r26, r26, 19438\n"
- "shl16insli r26, r26, 15394\n"
- "shl16insli r26, r26, -6172\n"
- "moveli r24, 28503\n"
- "shl16insli r24, r24, 24946\n"
- "shl16insli r24, r24, 28527\n"
- "shl16insli r24, r24, 6539\n"
- "{ v1sub r44, r26, r24 ; fnop }\n"
- "move %0, r44\n"
- "move %1, r26\n"
- "move %2, r24\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1sub_X1.c b/none/tests/tilegx/insn_test_v1sub_X1.c
deleted file mode 100644
index 4c97b9d..0000000
--- a/none/tests/tilegx/insn_test_v1sub_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1sub_X1.c
-//op=276
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x1fe54969a93a157a, 0x778f2f6f17d9003b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r44, 21888\n"
- "shl16insli r44, r44, -8663\n"
- "shl16insli r44, r44, -14905\n"
- "shl16insli r44, r44, -14362\n"
- "moveli r26, -18766\n"
- "shl16insli r26, r26, 19438\n"
- "shl16insli r26, r26, 15394\n"
- "shl16insli r26, r26, -6172\n"
- "moveli r24, 28503\n"
- "shl16insli r24, r24, 24946\n"
- "shl16insli r24, r24, 28527\n"
- "shl16insli r24, r24, 6539\n"
- "{ fnop ; v1sub r44, r26, r24 }\n"
- "move %0, r44\n"
- "move %1, r26\n"
- "move %2, r24\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1subuc_X0.c b/none/tests/tilegx/insn_test_v1subuc_X0.c
deleted file mode 100644
index a7911d3..0000000
--- a/none/tests/tilegx/insn_test_v1subuc_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1subuc_X0.c
-//op=277
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xaec371f1597db508, 0x70a50c305e0116b3 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r1, -32522\n"
- "shl16insli r1, r1, -12465\n"
- "shl16insli r1, r1, 13861\n"
- "shl16insli r1, r1, 7011\n"
- "moveli r13, 25648\n"
- "shl16insli r13, r13, 19640\n"
- "shl16insli r13, r13, -32625\n"
- "shl16insli r13, r13, -6642\n"
- "moveli r6, 4519\n"
- "shl16insli r6, r6, 25115\n"
- "shl16insli r6, r6, 25290\n"
- "shl16insli r6, r6, -28916\n"
- "{ v1subuc r1, r13, r6 ; fnop }\n"
- "move %0, r1\n"
- "move %1, r13\n"
- "move %2, r6\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v1subuc_X1.c b/none/tests/tilegx/insn_test_v1subuc_X1.c
deleted file mode 100644
index aa0abe0..0000000
--- a/none/tests/tilegx/insn_test_v1subuc_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v1subuc_X1.c
-//op=277
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xaec371f1597db508, 0x70a50c305e0116b3 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r1, -32522\n"
- "shl16insli r1, r1, -12465\n"
- "shl16insli r1, r1, 13861\n"
- "shl16insli r1, r1, 7011\n"
- "moveli r13, 25648\n"
- "shl16insli r13, r13, 19640\n"
- "shl16insli r13, r13, -32625\n"
- "shl16insli r13, r13, -6642\n"
- "moveli r6, 4519\n"
- "shl16insli r6, r6, 25115\n"
- "shl16insli r6, r6, 25290\n"
- "shl16insli r6, r6, -28916\n"
- "{ fnop ; v1subuc r1, r13, r6 }\n"
- "move %0, r1\n"
- "move %1, r13\n"
- "move %2, r6\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2add_X0.c b/none/tests/tilegx/insn_test_v2add_X0.c
deleted file mode 100644
index edff8f6..0000000
--- a/none/tests/tilegx/insn_test_v2add_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2add_X0.c
-//op=278
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x88b76c744163208a, 0xab1fe60bd5f86c0d };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r48, -20701\n"
- "shl16insli r48, r48, 19319\n"
- "shl16insli r48, r48, -14144\n"
- "shl16insli r48, r48, -17797\n"
- "moveli r42, -26180\n"
- "shl16insli r42, r42, -32480\n"
- "shl16insli r42, r42, -16635\n"
- "shl16insli r42, r42, -11404\n"
- "moveli r12, 15399\n"
- "shl16insli r12, r12, 19647\n"
- "shl16insli r12, r12, -13624\n"
- "shl16insli r12, r12, 29718\n"
- "{ v2add r48, r42, r12 ; fnop }\n"
- "move %0, r48\n"
- "move %1, r42\n"
- "move %2, r12\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2add_X1.c b/none/tests/tilegx/insn_test_v2add_X1.c
deleted file mode 100644
index 9cbed50..0000000
--- a/none/tests/tilegx/insn_test_v2add_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2add_X1.c
-//op=278
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x88b76c744163208a, 0xab1fe60bd5f86c0d };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r48, -20701\n"
- "shl16insli r48, r48, 19319\n"
- "shl16insli r48, r48, -14144\n"
- "shl16insli r48, r48, -17797\n"
- "moveli r42, -26180\n"
- "shl16insli r42, r42, -32480\n"
- "shl16insli r42, r42, -16635\n"
- "shl16insli r42, r42, -11404\n"
- "moveli r12, 15399\n"
- "shl16insli r12, r12, 19647\n"
- "shl16insli r12, r12, -13624\n"
- "shl16insli r12, r12, 29718\n"
- "{ fnop ; v2add r48, r42, r12 }\n"
- "move %0, r48\n"
- "move %1, r42\n"
- "move %2, r12\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2addsc_X0.c b/none/tests/tilegx/insn_test_v2addsc_X0.c
deleted file mode 100644
index 5caf009..0000000
--- a/none/tests/tilegx/insn_test_v2addsc_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2addsc_X0.c
-//op=280
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x65cf6bab5dfbf927, 0x455f86368ee6a1bf };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r7, 9473\n"
- "shl16insli r7, r7, -14156\n"
- "shl16insli r7, r7, 12314\n"
- "shl16insli r7, r7, -12172\n"
- "moveli r22, 28628\n"
- "shl16insli r22, r22, -15724\n"
- "shl16insli r22, r22, 22937\n"
- "shl16insli r22, r22, -21350\n"
- "moveli r23, -4550\n"
- "shl16insli r23, r23, 10548\n"
- "shl16insli r23, r23, -3563\n"
- "shl16insli r23, r23, -26830\n"
- "{ v2addsc r7, r22, r23 ; fnop }\n"
- "move %0, r7\n"
- "move %1, r22\n"
- "move %2, r23\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2addsc_X1.c b/none/tests/tilegx/insn_test_v2addsc_X1.c
deleted file mode 100644
index 3e08b25..0000000
--- a/none/tests/tilegx/insn_test_v2addsc_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2addsc_X1.c
-//op=280
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x65cf6bab5dfbf927, 0x455f86368ee6a1bf };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r7, 9473\n"
- "shl16insli r7, r7, -14156\n"
- "shl16insli r7, r7, 12314\n"
- "shl16insli r7, r7, -12172\n"
- "moveli r22, 28628\n"
- "shl16insli r22, r22, -15724\n"
- "shl16insli r22, r22, 22937\n"
- "shl16insli r22, r22, -21350\n"
- "moveli r23, -4550\n"
- "shl16insli r23, r23, 10548\n"
- "shl16insli r23, r23, -3563\n"
- "shl16insli r23, r23, -26830\n"
- "{ fnop ; v2addsc r7, r22, r23 }\n"
- "move %0, r7\n"
- "move %1, r22\n"
- "move %2, r23\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2adiffs_X0.c b/none/tests/tilegx/insn_test_v2adiffs_X0.c
deleted file mode 100644
index 0eefc9e..0000000
--- a/none/tests/tilegx/insn_test_v2adiffs_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2adiffs_X0.c
-//op=281
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x6f21f4f815dfb72, 0x5b4570159a31813a };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r10, -15907\n"
- "shl16insli r10, r10, 8951\n"
- "shl16insli r10, r10, -9037\n"
- "shl16insli r10, r10, 10333\n"
- "moveli r5, -798\n"
- "shl16insli r5, r5, -2293\n"
- "shl16insli r5, r5, -26610\n"
- "shl16insli r5, r5, -17\n"
- "moveli r39, -3845\n"
- "shl16insli r39, r39, -15318\n"
- "shl16insli r39, r39, 29335\n"
- "shl16insli r39, r39, 30594\n"
- "{ v2adiffs r10, r5, r39 ; fnop }\n"
- "move %0, r10\n"
- "move %1, r5\n"
- "move %2, r39\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2avgs_X0.c b/none/tests/tilegx/insn_test_v2avgs_X0.c
deleted file mode 100644
index 11ca6e9..0000000
--- a/none/tests/tilegx/insn_test_v2avgs_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2avgs_X0.c
-//op=282
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x71b23d899a1387f6, 0x818b8dda9648095a };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r6, -17474\n"
- "shl16insli r6, r6, 5541\n"
- "shl16insli r6, r6, 25238\n"
- "shl16insli r6, r6, 6803\n"
- "moveli r50, -5690\n"
- "shl16insli r50, r50, 12649\n"
- "shl16insli r50, r50, 15657\n"
- "shl16insli r50, r50, -29970\n"
- "moveli r50, 29145\n"
- "shl16insli r50, r50, 12637\n"
- "shl16insli r50, r50, -13093\n"
- "shl16insli r50, r50, 10273\n"
- "{ v2avgs r6, r50, r50 ; fnop }\n"
- "move %0, r6\n"
- "move %1, r50\n"
- "move %2, r50\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2cmpeq_X0.c b/none/tests/tilegx/insn_test_v2cmpeq_X0.c
deleted file mode 100644
index 53577af..0000000
--- a/none/tests/tilegx/insn_test_v2cmpeq_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2cmpeq_X0.c
-//op=283
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x81ebfd4038066c1, 0x27d94b818c24b012 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r28, 18704\n"
- "shl16insli r28, r28, -13143\n"
- "shl16insli r28, r28, 20980\n"
- "shl16insli r28, r28, -16967\n"
- "moveli r38, 2058\n"
- "shl16insli r38, r38, -13098\n"
- "shl16insli r38, r38, 23303\n"
- "shl16insli r38, r38, -31712\n"
- "moveli r16, 6420\n"
- "shl16insli r16, r16, 31924\n"
- "shl16insli r16, r16, -30519\n"
- "shl16insli r16, r16, 32754\n"
- "{ v2cmpeq r28, r38, r16 ; fnop }\n"
- "move %0, r28\n"
- "move %1, r38\n"
- "move %2, r16\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2cmpeq_X1.c b/none/tests/tilegx/insn_test_v2cmpeq_X1.c
deleted file mode 100644
index f37f536..0000000
--- a/none/tests/tilegx/insn_test_v2cmpeq_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2cmpeq_X1.c
-//op=283
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x81ebfd4038066c1, 0x27d94b818c24b012 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r28, 18704\n"
- "shl16insli r28, r28, -13143\n"
- "shl16insli r28, r28, 20980\n"
- "shl16insli r28, r28, -16967\n"
- "moveli r38, 2058\n"
- "shl16insli r38, r38, -13098\n"
- "shl16insli r38, r38, 23303\n"
- "shl16insli r38, r38, -31712\n"
- "moveli r16, 6420\n"
- "shl16insli r16, r16, 31924\n"
- "shl16insli r16, r16, -30519\n"
- "shl16insli r16, r16, 32754\n"
- "{ fnop ; v2cmpeq r28, r38, r16 }\n"
- "move %0, r28\n"
- "move %1, r38\n"
- "move %2, r16\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2cmpeqi_X0.c b/none/tests/tilegx/insn_test_v2cmpeqi_X0.c
deleted file mode 100644
index 49733d8..0000000
--- a/none/tests/tilegx/insn_test_v2cmpeqi_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_v2cmpeqi_X0.c
-//op=284
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x8313ffac0a7611da, 0xa6a582b3dc8f6e83 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r26, -30297\n"
- "shl16insli r26, r26, -30363\n"
- "shl16insli r26, r26, -30605\n"
- "shl16insli r26, r26, 3831\n"
- "moveli r35, 7782\n"
- "shl16insli r35, r35, 2739\n"
- "shl16insli r35, r35, -10491\n"
- "shl16insli r35, r35, -19368\n"
- "{ v2cmpeqi r26, r35, 63 ; fnop }\n"
- "move %0, r26\n"
- "move %1, r35\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2cmpeqi_X1.c b/none/tests/tilegx/insn_test_v2cmpeqi_X1.c
deleted file mode 100644
index 2d8cfea..0000000
--- a/none/tests/tilegx/insn_test_v2cmpeqi_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_v2cmpeqi_X1.c
-//op=284
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x8313ffac0a7611da, 0xa6a582b3dc8f6e83 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r26, -30297\n"
- "shl16insli r26, r26, -30363\n"
- "shl16insli r26, r26, -30605\n"
- "shl16insli r26, r26, 3831\n"
- "moveli r35, 7782\n"
- "shl16insli r35, r35, 2739\n"
- "shl16insli r35, r35, -10491\n"
- "shl16insli r35, r35, -19368\n"
- "{ fnop ; v2cmpeqi r26, r35, 63 }\n"
- "move %0, r26\n"
- "move %1, r35\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2cmples_X0.c b/none/tests/tilegx/insn_test_v2cmples_X0.c
deleted file mode 100644
index 3eee3ae..0000000
--- a/none/tests/tilegx/insn_test_v2cmples_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2cmples_X0.c
-//op=285
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x6bc7185f1c32c400, 0x77be6930d1ff0375 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r22, 24574\n"
- "shl16insli r22, r22, -7860\n"
- "shl16insli r22, r22, 22844\n"
- "shl16insli r22, r22, -25856\n"
- "moveli r9, 30705\n"
- "shl16insli r9, r9, -3754\n"
- "shl16insli r9, r9, 28337\n"
- "shl16insli r9, r9, -16712\n"
- "moveli r50, -1269\n"
- "shl16insli r50, r50, -3807\n"
- "shl16insli r50, r50, -5572\n"
- "shl16insli r50, r50, -28620\n"
- "{ v2cmples r22, r9, r50 ; fnop }\n"
- "move %0, r22\n"
- "move %1, r9\n"
- "move %2, r50\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2cmples_X1.c b/none/tests/tilegx/insn_test_v2cmples_X1.c
deleted file mode 100644
index 5ed4e02..0000000
--- a/none/tests/tilegx/insn_test_v2cmples_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2cmples_X1.c
-//op=285
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x6bc7185f1c32c400, 0x77be6930d1ff0375 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r22, 24574\n"
- "shl16insli r22, r22, -7860\n"
- "shl16insli r22, r22, 22844\n"
- "shl16insli r22, r22, -25856\n"
- "moveli r9, 30705\n"
- "shl16insli r9, r9, -3754\n"
- "shl16insli r9, r9, 28337\n"
- "shl16insli r9, r9, -16712\n"
- "moveli r50, -1269\n"
- "shl16insli r50, r50, -3807\n"
- "shl16insli r50, r50, -5572\n"
- "shl16insli r50, r50, -28620\n"
- "{ fnop ; v2cmples r22, r9, r50 }\n"
- "move %0, r22\n"
- "move %1, r9\n"
- "move %2, r50\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2cmpleu_X0.c b/none/tests/tilegx/insn_test_v2cmpleu_X0.c
deleted file mode 100644
index 1c06e62..0000000
--- a/none/tests/tilegx/insn_test_v2cmpleu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2cmpleu_X0.c
-//op=286
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x3ef8a65156ec00ac, 0x59fad680489ec628 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r50, 27539\n"
- "shl16insli r50, r50, -29737\n"
- "shl16insli r50, r50, 27831\n"
- "shl16insli r50, r50, -25163\n"
- "moveli r13, 694\n"
- "shl16insli r13, r13, -3893\n"
- "shl16insli r13, r13, 5047\n"
- "shl16insli r13, r13, -7475\n"
- "moveli r2, -31766\n"
- "shl16insli r2, r2, 20217\n"
- "shl16insli r2, r2, -13682\n"
- "shl16insli r2, r2, -10053\n"
- "{ v2cmpleu r50, r13, r2 ; fnop }\n"
- "move %0, r50\n"
- "move %1, r13\n"
- "move %2, r2\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2cmpleu_X1.c b/none/tests/tilegx/insn_test_v2cmpleu_X1.c
deleted file mode 100644
index fc201ad..0000000
--- a/none/tests/tilegx/insn_test_v2cmpleu_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2cmpleu_X1.c
-//op=286
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x3ef8a65156ec00ac, 0x59fad680489ec628 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r50, 27539\n"
- "shl16insli r50, r50, -29737\n"
- "shl16insli r50, r50, 27831\n"
- "shl16insli r50, r50, -25163\n"
- "moveli r13, 694\n"
- "shl16insli r13, r13, -3893\n"
- "shl16insli r13, r13, 5047\n"
- "shl16insli r13, r13, -7475\n"
- "moveli r2, -31766\n"
- "shl16insli r2, r2, 20217\n"
- "shl16insli r2, r2, -13682\n"
- "shl16insli r2, r2, -10053\n"
- "{ fnop ; v2cmpleu r50, r13, r2 }\n"
- "move %0, r50\n"
- "move %1, r13\n"
- "move %2, r2\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2cmplts_X0.c b/none/tests/tilegx/insn_test_v2cmplts_X0.c
deleted file mode 100644
index 7280ebe..0000000
--- a/none/tests/tilegx/insn_test_v2cmplts_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2cmplts_X0.c
-//op=287
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xee16007d198e11f0, 0x1aa7041318ab41dd };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r36, 31237\n"
- "shl16insli r36, r36, -13233\n"
- "shl16insli r36, r36, -23176\n"
- "shl16insli r36, r36, 582\n"
- "moveli r45, 10053\n"
- "shl16insli r45, r45, 8734\n"
- "shl16insli r45, r45, 386\n"
- "shl16insli r45, r45, -2790\n"
- "moveli r20, 27000\n"
- "shl16insli r20, r20, -5959\n"
- "shl16insli r20, r20, 7411\n"
- "shl16insli r20, r20, 17645\n"
- "{ v2cmplts r36, r45, r20 ; fnop }\n"
- "move %0, r36\n"
- "move %1, r45\n"
- "move %2, r20\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2cmplts_X1.c b/none/tests/tilegx/insn_test_v2cmplts_X1.c
deleted file mode 100644
index 18a0cbf..0000000
--- a/none/tests/tilegx/insn_test_v2cmplts_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2cmplts_X1.c
-//op=287
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xee16007d198e11f0, 0x1aa7041318ab41dd };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r36, 31237\n"
- "shl16insli r36, r36, -13233\n"
- "shl16insli r36, r36, -23176\n"
- "shl16insli r36, r36, 582\n"
- "moveli r45, 10053\n"
- "shl16insli r45, r45, 8734\n"
- "shl16insli r45, r45, 386\n"
- "shl16insli r45, r45, -2790\n"
- "moveli r20, 27000\n"
- "shl16insli r20, r20, -5959\n"
- "shl16insli r20, r20, 7411\n"
- "shl16insli r20, r20, 17645\n"
- "{ fnop ; v2cmplts r36, r45, r20 }\n"
- "move %0, r36\n"
- "move %1, r45\n"
- "move %2, r20\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2cmpltsi_X0.c b/none/tests/tilegx/insn_test_v2cmpltsi_X0.c
deleted file mode 100644
index 7e9e929..0000000
--- a/none/tests/tilegx/insn_test_v2cmpltsi_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_v2cmpltsi_X0.c
-//op=288
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x659ad846d801a198, 0xfa50dcf0b044d59a };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r1, 7596\n"
- "shl16insli r1, r1, -10648\n"
- "shl16insli r1, r1, 15573\n"
- "shl16insli r1, r1, -25790\n"
- "moveli r40, -27339\n"
- "shl16insli r40, r40, -13420\n"
- "shl16insli r40, r40, 19273\n"
- "shl16insli r40, r40, -27678\n"
- "{ v2cmpltsi r1, r40, 43 ; fnop }\n"
- "move %0, r1\n"
- "move %1, r40\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2cmpltsi_X1.c b/none/tests/tilegx/insn_test_v2cmpltsi_X1.c
deleted file mode 100644
index e13063e..0000000
--- a/none/tests/tilegx/insn_test_v2cmpltsi_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_v2cmpltsi_X1.c
-//op=288
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x659ad846d801a198, 0xfa50dcf0b044d59a };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r1, 7596\n"
- "shl16insli r1, r1, -10648\n"
- "shl16insli r1, r1, 15573\n"
- "shl16insli r1, r1, -25790\n"
- "moveli r40, -27339\n"
- "shl16insli r40, r40, -13420\n"
- "shl16insli r40, r40, 19273\n"
- "shl16insli r40, r40, -27678\n"
- "{ fnop ; v2cmpltsi r1, r40, 43 }\n"
- "move %0, r1\n"
- "move %1, r40\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2cmpltu_X0.c b/none/tests/tilegx/insn_test_v2cmpltu_X0.c
deleted file mode 100644
index 40887f3..0000000
--- a/none/tests/tilegx/insn_test_v2cmpltu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2cmpltu_X0.c
-//op=289
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x5bebf9affeed58c5, 0x5f48984c90970726 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r17, -4172\n"
- "shl16insli r17, r17, 3357\n"
- "shl16insli r17, r17, 24413\n"
- "shl16insli r17, r17, -20526\n"
- "moveli r27, 301\n"
- "shl16insli r27, r27, -10739\n"
- "shl16insli r27, r27, -13582\n"
- "shl16insli r27, r27, 11244\n"
- "moveli r10, 9533\n"
- "shl16insli r10, r10, -1340\n"
- "shl16insli r10, r10, -4688\n"
- "shl16insli r10, r10, 849\n"
- "{ v2cmpltu r17, r27, r10 ; fnop }\n"
- "move %0, r17\n"
- "move %1, r27\n"
- "move %2, r10\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2cmpltu_X1.c b/none/tests/tilegx/insn_test_v2cmpltu_X1.c
deleted file mode 100644
index d076173..0000000
--- a/none/tests/tilegx/insn_test_v2cmpltu_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2cmpltu_X1.c
-//op=289
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x5bebf9affeed58c5, 0x5f48984c90970726 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r17, -4172\n"
- "shl16insli r17, r17, 3357\n"
- "shl16insli r17, r17, 24413\n"
- "shl16insli r17, r17, -20526\n"
- "moveli r27, 301\n"
- "shl16insli r27, r27, -10739\n"
- "shl16insli r27, r27, -13582\n"
- "shl16insli r27, r27, 11244\n"
- "moveli r10, 9533\n"
- "shl16insli r10, r10, -1340\n"
- "shl16insli r10, r10, -4688\n"
- "shl16insli r10, r10, 849\n"
- "{ fnop ; v2cmpltu r17, r27, r10 }\n"
- "move %0, r17\n"
- "move %1, r27\n"
- "move %2, r10\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2cmpltui_X0.c b/none/tests/tilegx/insn_test_v2cmpltui_X0.c
deleted file mode 100644
index 4c30390..0000000
--- a/none/tests/tilegx/insn_test_v2cmpltui_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_v2cmpltui_X0.c
-//op=290
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x4ebafb6d47a2a55b, 0xd6233f383d6fcac4 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r38, -25706\n"
- "shl16insli r38, r38, -25275\n"
- "shl16insli r38, r38, 17720\n"
- "shl16insli r38, r38, 16967\n"
- "moveli r24, -18642\n"
- "shl16insli r24, r24, -25898\n"
- "shl16insli r24, r24, -7881\n"
- "shl16insli r24, r24, 8833\n"
- "{ v2cmpltui r38, r24, -54 ; fnop }\n"
- "move %0, r38\n"
- "move %1, r24\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2cmpltui_X1.c b/none/tests/tilegx/insn_test_v2cmpltui_X1.c
deleted file mode 100644
index 2707b53..0000000
--- a/none/tests/tilegx/insn_test_v2cmpltui_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_v2cmpltui_X1.c
-//op=290
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x4ebafb6d47a2a55b, 0xd6233f383d6fcac4 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r38, -25706\n"
- "shl16insli r38, r38, -25275\n"
- "shl16insli r38, r38, 17720\n"
- "shl16insli r38, r38, 16967\n"
- "moveli r24, -18642\n"
- "shl16insli r24, r24, -25898\n"
- "shl16insli r24, r24, -7881\n"
- "shl16insli r24, r24, 8833\n"
- "{ fnop ; v2cmpltui r38, r24, -54 }\n"
- "move %0, r38\n"
- "move %1, r24\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2cmpne_X0.c b/none/tests/tilegx/insn_test_v2cmpne_X0.c
deleted file mode 100644
index 5c049d0..0000000
--- a/none/tests/tilegx/insn_test_v2cmpne_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2cmpne_X0.c
-//op=291
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x73bf93bc04d834da, 0x76a2823539bdf579 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r22, -12324\n"
- "shl16insli r22, r22, -28627\n"
- "shl16insli r22, r22, 16604\n"
- "shl16insli r22, r22, -17536\n"
- "moveli r4, -7766\n"
- "shl16insli r4, r4, 5697\n"
- "shl16insli r4, r4, 28357\n"
- "shl16insli r4, r4, -6412\n"
- "moveli r17, 864\n"
- "shl16insli r17, r17, 29519\n"
- "shl16insli r17, r17, 2450\n"
- "shl16insli r17, r17, -17857\n"
- "{ v2cmpne r22, r4, r17 ; fnop }\n"
- "move %0, r22\n"
- "move %1, r4\n"
- "move %2, r17\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2cmpne_X1.c b/none/tests/tilegx/insn_test_v2cmpne_X1.c
deleted file mode 100644
index 35031b2..0000000
--- a/none/tests/tilegx/insn_test_v2cmpne_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2cmpne_X1.c
-//op=291
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x73bf93bc04d834da, 0x76a2823539bdf579 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r22, -12324\n"
- "shl16insli r22, r22, -28627\n"
- "shl16insli r22, r22, 16604\n"
- "shl16insli r22, r22, -17536\n"
- "moveli r4, -7766\n"
- "shl16insli r4, r4, 5697\n"
- "shl16insli r4, r4, 28357\n"
- "shl16insli r4, r4, -6412\n"
- "moveli r17, 864\n"
- "shl16insli r17, r17, 29519\n"
- "shl16insli r17, r17, 2450\n"
- "shl16insli r17, r17, -17857\n"
- "{ fnop ; v2cmpne r22, r4, r17 }\n"
- "move %0, r22\n"
- "move %1, r4\n"
- "move %2, r17\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2dotp_X0.c b/none/tests/tilegx/insn_test_v2dotp_X0.c
deleted file mode 100644
index f81bb0a..0000000
--- a/none/tests/tilegx/insn_test_v2dotp_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2dotp_X0.c
-//op=292
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x6be343892f498708, 0x52c49809e5465b06 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r9, 25552\n"
- "shl16insli r9, r9, -32365\n"
- "shl16insli r9, r9, 7253\n"
- "shl16insli r9, r9, 12258\n"
- "moveli r16, 31670\n"
- "shl16insli r16, r16, 10120\n"
- "shl16insli r16, r16, -14289\n"
- "shl16insli r16, r16, -12244\n"
- "moveli r25, 2217\n"
- "shl16insli r25, r25, 23167\n"
- "shl16insli r25, r25, 4870\n"
- "shl16insli r25, r25, 31812\n"
- "{ v2dotp r9, r16, r25 ; fnop }\n"
- "move %0, r9\n"
- "move %1, r16\n"
- "move %2, r25\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2dotpa_X0.c b/none/tests/tilegx/insn_test_v2dotpa_X0.c
deleted file mode 100644
index be29012..0000000
--- a/none/tests/tilegx/insn_test_v2dotpa_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2dotpa_X0.c
-//op=293
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xf3a626370b91d897, 0xecbff88d5bcc8c90 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r17, 6194\n"
- "shl16insli r17, r17, 2413\n"
- "shl16insli r17, r17, 21362\n"
- "shl16insli r17, r17, 21211\n"
- "moveli r8, 14829\n"
- "shl16insli r8, r8, 23848\n"
- "shl16insli r8, r8, 17951\n"
- "shl16insli r8, r8, -953\n"
- "moveli r25, 21203\n"
- "shl16insli r25, r25, -13101\n"
- "shl16insli r25, r25, 14734\n"
- "shl16insli r25, r25, -27100\n"
- "{ v2dotpa r17, r8, r25 ; fnop }\n"
- "move %0, r17\n"
- "move %1, r8\n"
- "move %2, r25\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2int_h_X0.c b/none/tests/tilegx/insn_test_v2int_h_X0.c
deleted file mode 100644
index 5c11542..0000000
--- a/none/tests/tilegx/insn_test_v2int_h_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2int_h_X0.c
-//op=294
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x97e13a21591a3024, 0x5d9ea0967d2b4507 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r43, -19915\n"
- "shl16insli r43, r43, -2852\n"
- "shl16insli r43, r43, 32613\n"
- "shl16insli r43, r43, 14940\n"
- "moveli r42, -8260\n"
- "shl16insli r42, r42, -23578\n"
- "shl16insli r42, r42, -18362\n"
- "shl16insli r42, r42, 19495\n"
- "moveli r21, -29446\n"
- "shl16insli r21, r21, -10554\n"
- "shl16insli r21, r21, 9903\n"
- "shl16insli r21, r21, -20470\n"
- "{ v2int_h r43, r42, r21 ; fnop }\n"
- "move %0, r43\n"
- "move %1, r42\n"
- "move %2, r21\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2int_h_X1.c b/none/tests/tilegx/insn_test_v2int_h_X1.c
deleted file mode 100644
index f43e7bd..0000000
--- a/none/tests/tilegx/insn_test_v2int_h_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2int_h_X1.c
-//op=294
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x97e13a21591a3024, 0x5d9ea0967d2b4507 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r43, -19915\n"
- "shl16insli r43, r43, -2852\n"
- "shl16insli r43, r43, 32613\n"
- "shl16insli r43, r43, 14940\n"
- "moveli r42, -8260\n"
- "shl16insli r42, r42, -23578\n"
- "shl16insli r42, r42, -18362\n"
- "shl16insli r42, r42, 19495\n"
- "moveli r21, -29446\n"
- "shl16insli r21, r21, -10554\n"
- "shl16insli r21, r21, 9903\n"
- "shl16insli r21, r21, -20470\n"
- "{ fnop ; v2int_h r43, r42, r21 }\n"
- "move %0, r43\n"
- "move %1, r42\n"
- "move %2, r21\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2int_l_X0.c b/none/tests/tilegx/insn_test_v2int_l_X0.c
deleted file mode 100644
index a6aa8a3..0000000
--- a/none/tests/tilegx/insn_test_v2int_l_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2int_l_X0.c
-//op=295
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xcfb4af8744c008a6, 0x7da224c9da343236 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r39, -7263\n"
- "shl16insli r39, r39, -2165\n"
- "shl16insli r39, r39, 15401\n"
- "shl16insli r39, r39, 3495\n"
- "moveli r50, -16001\n"
- "shl16insli r50, r50, 28334\n"
- "shl16insli r50, r50, 10964\n"
- "shl16insli r50, r50, -18458\n"
- "moveli r49, -15860\n"
- "shl16insli r49, r49, -32482\n"
- "shl16insli r49, r49, 31946\n"
- "shl16insli r49, r49, -29777\n"
- "{ v2int_l r39, r50, r49 ; fnop }\n"
- "move %0, r39\n"
- "move %1, r50\n"
- "move %2, r49\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2int_l_X1.c b/none/tests/tilegx/insn_test_v2int_l_X1.c
deleted file mode 100644
index 5a1bddb..0000000
--- a/none/tests/tilegx/insn_test_v2int_l_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2int_l_X1.c
-//op=295
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xcfb4af8744c008a6, 0x7da224c9da343236 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r39, -7263\n"
- "shl16insli r39, r39, -2165\n"
- "shl16insli r39, r39, 15401\n"
- "shl16insli r39, r39, 3495\n"
- "moveli r50, -16001\n"
- "shl16insli r50, r50, 28334\n"
- "shl16insli r50, r50, 10964\n"
- "shl16insli r50, r50, -18458\n"
- "moveli r49, -15860\n"
- "shl16insli r49, r49, -32482\n"
- "shl16insli r49, r49, 31946\n"
- "shl16insli r49, r49, -29777\n"
- "{ fnop ; v2int_l r39, r50, r49 }\n"
- "move %0, r39\n"
- "move %1, r50\n"
- "move %2, r49\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2maxs_X0.c b/none/tests/tilegx/insn_test_v2maxs_X0.c
deleted file mode 100644
index a466202..0000000
--- a/none/tests/tilegx/insn_test_v2maxs_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2maxs_X0.c
-//op=296
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd673caed17b8f6b3, 0xd67c5353b4f83951 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r17, -9565\n"
- "shl16insli r17, r17, -2221\n"
- "shl16insli r17, r17, 28285\n"
- "shl16insli r17, r17, -15121\n"
- "moveli r49, -7514\n"
- "shl16insli r49, r49, -32499\n"
- "shl16insli r49, r49, -9013\n"
- "shl16insli r49, r49, -11291\n"
- "moveli r38, -30570\n"
- "shl16insli r38, r38, 23912\n"
- "shl16insli r38, r38, -22856\n"
- "shl16insli r38, r38, 8963\n"
- "{ v2maxs r17, r49, r38 ; fnop }\n"
- "move %0, r17\n"
- "move %1, r49\n"
- "move %2, r38\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2maxs_X1.c b/none/tests/tilegx/insn_test_v2maxs_X1.c
deleted file mode 100644
index 7f2ec99..0000000
--- a/none/tests/tilegx/insn_test_v2maxs_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2maxs_X1.c
-//op=296
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd673caed17b8f6b3, 0xd67c5353b4f83951 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r17, -9565\n"
- "shl16insli r17, r17, -2221\n"
- "shl16insli r17, r17, 28285\n"
- "shl16insli r17, r17, -15121\n"
- "moveli r49, -7514\n"
- "shl16insli r49, r49, -32499\n"
- "shl16insli r49, r49, -9013\n"
- "shl16insli r49, r49, -11291\n"
- "moveli r38, -30570\n"
- "shl16insli r38, r38, 23912\n"
- "shl16insli r38, r38, -22856\n"
- "shl16insli r38, r38, 8963\n"
- "{ fnop ; v2maxs r17, r49, r38 }\n"
- "move %0, r17\n"
- "move %1, r49\n"
- "move %2, r38\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2mins_X0.c b/none/tests/tilegx/insn_test_v2mins_X0.c
deleted file mode 100644
index 608b217..0000000
--- a/none/tests/tilegx/insn_test_v2mins_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2mins_X0.c
-//op=298
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xa3dc241c7d6d8a40, 0x74d04934d1d15274 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r11, -6438\n"
- "shl16insli r11, r11, 23407\n"
- "shl16insli r11, r11, -8776\n"
- "shl16insli r11, r11, -3925\n"
- "moveli r49, -16630\n"
- "shl16insli r49, r49, 3480\n"
- "shl16insli r49, r49, -23548\n"
- "shl16insli r49, r49, -31140\n"
- "moveli r31, 15345\n"
- "shl16insli r31, r31, 9943\n"
- "shl16insli r31, r31, 20819\n"
- "shl16insli r31, r31, 16223\n"
- "{ v2mins r11, r49, r31 ; fnop }\n"
- "move %0, r11\n"
- "move %1, r49\n"
- "move %2, r31\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2mins_X1.c b/none/tests/tilegx/insn_test_v2mins_X1.c
deleted file mode 100644
index 57c7f7b..0000000
--- a/none/tests/tilegx/insn_test_v2mins_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2mins_X1.c
-//op=298
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xa3dc241c7d6d8a40, 0x74d04934d1d15274 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r11, -6438\n"
- "shl16insli r11, r11, 23407\n"
- "shl16insli r11, r11, -8776\n"
- "shl16insli r11, r11, -3925\n"
- "moveli r49, -16630\n"
- "shl16insli r49, r49, 3480\n"
- "shl16insli r49, r49, -23548\n"
- "shl16insli r49, r49, -31140\n"
- "moveli r31, 15345\n"
- "shl16insli r31, r31, 9943\n"
- "shl16insli r31, r31, 20819\n"
- "shl16insli r31, r31, 16223\n"
- "{ fnop ; v2mins r11, r49, r31 }\n"
- "move %0, r11\n"
- "move %1, r49\n"
- "move %2, r31\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2mnz_X0.c b/none/tests/tilegx/insn_test_v2mnz_X0.c
deleted file mode 100644
index 7df50e1..0000000
--- a/none/tests/tilegx/insn_test_v2mnz_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2mnz_X0.c
-//op=300
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x2998adb0884ca11c, 0x95953511f9ee4512 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r8, -25986\n"
- "shl16insli r8, r8, -11739\n"
- "shl16insli r8, r8, 13313\n"
- "shl16insli r8, r8, -12374\n"
- "moveli r5, 8557\n"
- "shl16insli r5, r5, 20208\n"
- "shl16insli r5, r5, -26295\n"
- "shl16insli r5, r5, -27540\n"
- "moveli r49, 24429\n"
- "shl16insli r49, r49, 18925\n"
- "shl16insli r49, r49, 30717\n"
- "shl16insli r49, r49, -32703\n"
- "{ v2mnz r8, r5, r49 ; fnop }\n"
- "move %0, r8\n"
- "move %1, r5\n"
- "move %2, r49\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2mnz_X1.c b/none/tests/tilegx/insn_test_v2mnz_X1.c
deleted file mode 100644
index 81e8b76..0000000
--- a/none/tests/tilegx/insn_test_v2mnz_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2mnz_X1.c
-//op=300
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x2998adb0884ca11c, 0x95953511f9ee4512 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r8, -25986\n"
- "shl16insli r8, r8, -11739\n"
- "shl16insli r8, r8, 13313\n"
- "shl16insli r8, r8, -12374\n"
- "moveli r5, 8557\n"
- "shl16insli r5, r5, 20208\n"
- "shl16insli r5, r5, -26295\n"
- "shl16insli r5, r5, -27540\n"
- "moveli r49, 24429\n"
- "shl16insli r49, r49, 18925\n"
- "shl16insli r49, r49, 30717\n"
- "shl16insli r49, r49, -32703\n"
- "{ fnop ; v2mnz r8, r5, r49 }\n"
- "move %0, r8\n"
- "move %1, r5\n"
- "move %2, r49\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2mulfsc_X0.c b/none/tests/tilegx/insn_test_v2mulfsc_X0.c
deleted file mode 100644
index 236df3b..0000000
--- a/none/tests/tilegx/insn_test_v2mulfsc_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2mulfsc_X0.c
-//op=301
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xfc4c1139fffb1c60, 0xb25a859df5ae736 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r42, -31119\n"
- "shl16insli r42, r42, -1080\n"
- "shl16insli r42, r42, 6437\n"
- "shl16insli r42, r42, 1017\n"
- "moveli r19, 18489\n"
- "shl16insli r19, r19, -6115\n"
- "shl16insli r19, r19, -11917\n"
- "shl16insli r19, r19, -887\n"
- "moveli r6, -7581\n"
- "shl16insli r6, r6, -24479\n"
- "shl16insli r6, r6, 27035\n"
- "shl16insli r6, r6, -19583\n"
- "{ v2mulfsc r42, r19, r6 ; fnop }\n"
- "move %0, r42\n"
- "move %1, r19\n"
- "move %2, r6\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2muls_X0.c b/none/tests/tilegx/insn_test_v2muls_X0.c
deleted file mode 100644
index f47e89e..0000000
--- a/none/tests/tilegx/insn_test_v2muls_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2muls_X0.c
-//op=302
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x16cf0b15dab31447, 0x4f71ee192e8cc1e4 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r35, 14213\n"
- "shl16insli r35, r35, -12906\n"
- "shl16insli r35, r35, -10898\n"
- "shl16insli r35, r35, 21664\n"
- "moveli r33, -3303\n"
- "shl16insli r33, r33, -18198\n"
- "shl16insli r33, r33, 17267\n"
- "shl16insli r33, r33, -25748\n"
- "moveli r48, -32118\n"
- "shl16insli r48, r48, -21438\n"
- "shl16insli r48, r48, -21975\n"
- "shl16insli r48, r48, -17458\n"
- "{ v2muls r35, r33, r48 ; fnop }\n"
- "move %0, r35\n"
- "move %1, r33\n"
- "move %2, r48\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2mults_X0.c b/none/tests/tilegx/insn_test_v2mults_X0.c
deleted file mode 100644
index 6815340..0000000
--- a/none/tests/tilegx/insn_test_v2mults_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2mults_X0.c
-//op=303
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x10a358c86acccf50, 0xdf11630124acb01a };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r9, 4497\n"
- "shl16insli r9, r9, 8011\n"
- "shl16insli r9, r9, -29488\n"
- "shl16insli r9, r9, -23563\n"
- "moveli r39, -24360\n"
- "shl16insli r39, r39, 26052\n"
- "shl16insli r39, r39, -30688\n"
- "shl16insli r39, r39, -6964\n"
- "moveli r46, 14490\n"
- "shl16insli r46, r46, 13586\n"
- "shl16insli r46, r46, -31514\n"
- "shl16insli r46, r46, -17044\n"
- "{ v2mults r9, r39, r46 ; fnop }\n"
- "move %0, r9\n"
- "move %1, r39\n"
- "move %2, r46\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2mz_X0.c b/none/tests/tilegx/insn_test_v2mz_X0.c
deleted file mode 100644
index c7db681..0000000
--- a/none/tests/tilegx/insn_test_v2mz_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2mz_X0.c
-//op=304
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xdf8a8efd3fbdf7df, 0x9d9b78ac30042683 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r1, -1899\n"
- "shl16insli r1, r1, -8825\n"
- "shl16insli r1, r1, -7773\n"
- "shl16insli r1, r1, -2647\n"
- "moveli r26, -32534\n"
- "shl16insli r26, r26, -13813\n"
- "shl16insli r26, r26, -14272\n"
- "shl16insli r26, r26, -25134\n"
- "moveli r32, -5907\n"
- "shl16insli r32, r32, 24588\n"
- "shl16insli r32, r32, -15094\n"
- "shl16insli r32, r32, 11658\n"
- "{ v2mz r1, r26, r32 ; fnop }\n"
- "move %0, r1\n"
- "move %1, r26\n"
- "move %2, r32\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2mz_X1.c b/none/tests/tilegx/insn_test_v2mz_X1.c
deleted file mode 100644
index 0953ec8..0000000
--- a/none/tests/tilegx/insn_test_v2mz_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2mz_X1.c
-//op=304
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xdf8a8efd3fbdf7df, 0x9d9b78ac30042683 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r1, -1899\n"
- "shl16insli r1, r1, -8825\n"
- "shl16insli r1, r1, -7773\n"
- "shl16insli r1, r1, -2647\n"
- "moveli r26, -32534\n"
- "shl16insli r26, r26, -13813\n"
- "shl16insli r26, r26, -14272\n"
- "shl16insli r26, r26, -25134\n"
- "moveli r32, -5907\n"
- "shl16insli r32, r32, 24588\n"
- "shl16insli r32, r32, -15094\n"
- "shl16insli r32, r32, 11658\n"
- "{ fnop ; v2mz r1, r26, r32 }\n"
- "move %0, r1\n"
- "move %1, r26\n"
- "move %2, r32\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2packh_X0.c b/none/tests/tilegx/insn_test_v2packh_X0.c
deleted file mode 100644
index 9991c1d..0000000
--- a/none/tests/tilegx/insn_test_v2packh_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2packh_X0.c
-//op=305
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xbe377398fe6841d2, 0xdc57bd79a15b537d };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r31, 4830\n"
- "shl16insli r31, r31, 30571\n"
- "shl16insli r31, r31, -14162\n"
- "shl16insli r31, r31, 16427\n"
- "moveli r48, 26721\n"
- "shl16insli r48, r48, 13661\n"
- "shl16insli r48, r48, 14804\n"
- "shl16insli r48, r48, 23341\n"
- "moveli r24, -18421\n"
- "shl16insli r24, r24, -1115\n"
- "shl16insli r24, r24, 24581\n"
- "shl16insli r24, r24, 17697\n"
- "{ v2packh r31, r48, r24 ; fnop }\n"
- "move %0, r31\n"
- "move %1, r48\n"
- "move %2, r24\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2packh_X1.c b/none/tests/tilegx/insn_test_v2packh_X1.c
deleted file mode 100644
index fa93ab2..0000000
--- a/none/tests/tilegx/insn_test_v2packh_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2packh_X1.c
-//op=305
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xbe377398fe6841d2, 0xdc57bd79a15b537d };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r31, 4830\n"
- "shl16insli r31, r31, 30571\n"
- "shl16insli r31, r31, -14162\n"
- "shl16insli r31, r31, 16427\n"
- "moveli r48, 26721\n"
- "shl16insli r48, r48, 13661\n"
- "shl16insli r48, r48, 14804\n"
- "shl16insli r48, r48, 23341\n"
- "moveli r24, -18421\n"
- "shl16insli r24, r24, -1115\n"
- "shl16insli r24, r24, 24581\n"
- "shl16insli r24, r24, 17697\n"
- "{ fnop ; v2packh r31, r48, r24 }\n"
- "move %0, r31\n"
- "move %1, r48\n"
- "move %2, r24\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2packl_X0.c b/none/tests/tilegx/insn_test_v2packl_X0.c
deleted file mode 100644
index d699781..0000000
--- a/none/tests/tilegx/insn_test_v2packl_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2packl_X0.c
-//op=306
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x6110cf64d9a1b913, 0xc8c9da0e90770658 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r45, 31329\n"
- "shl16insli r45, r45, 2611\n"
- "shl16insli r45, r45, -21984\n"
- "shl16insli r45, r45, -27173\n"
- "moveli r13, 29208\n"
- "shl16insli r13, r13, -3828\n"
- "shl16insli r13, r13, 13042\n"
- "shl16insli r13, r13, 9981\n"
- "moveli r40, 2094\n"
- "shl16insli r40, r40, 8442\n"
- "shl16insli r40, r40, -10144\n"
- "shl16insli r40, r40, -21625\n"
- "{ v2packl r45, r13, r40 ; fnop }\n"
- "move %0, r45\n"
- "move %1, r13\n"
- "move %2, r40\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2packl_X1.c b/none/tests/tilegx/insn_test_v2packl_X1.c
deleted file mode 100644
index b54834c..0000000
--- a/none/tests/tilegx/insn_test_v2packl_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2packl_X1.c
-//op=306
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x6110cf64d9a1b913, 0xc8c9da0e90770658 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r45, 31329\n"
- "shl16insli r45, r45, 2611\n"
- "shl16insli r45, r45, -21984\n"
- "shl16insli r45, r45, -27173\n"
- "moveli r13, 29208\n"
- "shl16insli r13, r13, -3828\n"
- "shl16insli r13, r13, 13042\n"
- "shl16insli r13, r13, 9981\n"
- "moveli r40, 2094\n"
- "shl16insli r40, r40, 8442\n"
- "shl16insli r40, r40, -10144\n"
- "shl16insli r40, r40, -21625\n"
- "{ fnop ; v2packl r45, r13, r40 }\n"
- "move %0, r45\n"
- "move %1, r13\n"
- "move %2, r40\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2packuc_X0.c b/none/tests/tilegx/insn_test_v2packuc_X0.c
deleted file mode 100644
index 26df79f..0000000
--- a/none/tests/tilegx/insn_test_v2packuc_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2packuc_X0.c
-//op=307
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xe14980afe3a8dcf2, 0x14a9d2cae102f39d };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r48, -14873\n"
- "shl16insli r48, r48, 20437\n"
- "shl16insli r48, r48, 1647\n"
- "shl16insli r48, r48, -19288\n"
- "moveli r2, 30869\n"
- "shl16insli r2, r2, -5643\n"
- "shl16insli r2, r2, 25290\n"
- "shl16insli r2, r2, -10746\n"
- "moveli r10, -14292\n"
- "shl16insli r10, r10, -10131\n"
- "shl16insli r10, r10, -22412\n"
- "shl16insli r10, r10, -22005\n"
- "{ v2packuc r48, r2, r10 ; fnop }\n"
- "move %0, r48\n"
- "move %1, r2\n"
- "move %2, r10\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2packuc_X1.c b/none/tests/tilegx/insn_test_v2packuc_X1.c
deleted file mode 100644
index 7c23086..0000000
--- a/none/tests/tilegx/insn_test_v2packuc_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2packuc_X1.c
-//op=307
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xe14980afe3a8dcf2, 0x14a9d2cae102f39d };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r48, -14873\n"
- "shl16insli r48, r48, 20437\n"
- "shl16insli r48, r48, 1647\n"
- "shl16insli r48, r48, -19288\n"
- "moveli r2, 30869\n"
- "shl16insli r2, r2, -5643\n"
- "shl16insli r2, r2, 25290\n"
- "shl16insli r2, r2, -10746\n"
- "moveli r10, -14292\n"
- "shl16insli r10, r10, -10131\n"
- "shl16insli r10, r10, -22412\n"
- "shl16insli r10, r10, -22005\n"
- "{ fnop ; v2packuc r48, r2, r10 }\n"
- "move %0, r48\n"
- "move %1, r2\n"
- "move %2, r10\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2sadas_X0.c b/none/tests/tilegx/insn_test_v2sadas_X0.c
deleted file mode 100644
index 1bab24d..0000000
--- a/none/tests/tilegx/insn_test_v2sadas_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2sadas_X0.c
-//op=308
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x62e80c5c43ae1476, 0x75d452e3a144efb8 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r23, 241\n"
- "shl16insli r23, r23, -14815\n"
- "shl16insli r23, r23, -21901\n"
- "shl16insli r23, r23, -3061\n"
- "moveli r7, -22129\n"
- "shl16insli r7, r7, -14930\n"
- "shl16insli r7, r7, -14368\n"
- "shl16insli r7, r7, -8560\n"
- "moveli r29, -18028\n"
- "shl16insli r29, r29, -11276\n"
- "shl16insli r29, r29, 30167\n"
- "shl16insli r29, r29, -30797\n"
- "{ v2sadas r23, r7, r29 ; fnop }\n"
- "move %0, r23\n"
- "move %1, r7\n"
- "move %2, r29\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2sadau_X0.c b/none/tests/tilegx/insn_test_v2sadau_X0.c
deleted file mode 100644
index 792c5ef..0000000
--- a/none/tests/tilegx/insn_test_v2sadau_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2sadau_X0.c
-//op=309
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xa3379eed107d409b, 0xb774c986061d211c };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r47, -14930\n"
- "shl16insli r47, r47, -27555\n"
- "shl16insli r47, r47, -15233\n"
- "shl16insli r47, r47, -7776\n"
- "moveli r46, 28855\n"
- "shl16insli r46, r46, 12220\n"
- "shl16insli r46, r46, -21108\n"
- "shl16insli r46, r46, 22056\n"
- "moveli r28, -20567\n"
- "shl16insli r28, r28, -30793\n"
- "shl16insli r28, r28, -6577\n"
- "shl16insli r28, r28, -29356\n"
- "{ v2sadau r47, r46, r28 ; fnop }\n"
- "move %0, r47\n"
- "move %1, r46\n"
- "move %2, r28\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2sads_X0.c b/none/tests/tilegx/insn_test_v2sads_X0.c
deleted file mode 100644
index 5a4b7c4..0000000
--- a/none/tests/tilegx/insn_test_v2sads_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2sads_X0.c
-//op=310
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xb4cc28ab90e8a37, 0xc707c0e7f8704eba };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r22, 14299\n"
- "shl16insli r22, r22, -16601\n"
- "shl16insli r22, r22, -30080\n"
- "shl16insli r22, r22, 10179\n"
- "moveli r10, -32760\n"
- "shl16insli r10, r10, 21279\n"
- "shl16insli r10, r10, 9681\n"
- "shl16insli r10, r10, 15414\n"
- "moveli r21, 29123\n"
- "shl16insli r21, r21, -20065\n"
- "shl16insli r21, r21, 10672\n"
- "shl16insli r21, r21, -17765\n"
- "{ v2sads r22, r10, r21 ; fnop }\n"
- "move %0, r22\n"
- "move %1, r10\n"
- "move %2, r21\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2sadu_X0.c b/none/tests/tilegx/insn_test_v2sadu_X0.c
deleted file mode 100644
index acc1206..0000000
--- a/none/tests/tilegx/insn_test_v2sadu_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2sadu_X0.c
-//op=311
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x16b1b65c0b6644ef, 0x11cdf52de566595 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r9, 31657\n"
- "shl16insli r9, r9, -25836\n"
- "shl16insli r9, r9, 8322\n"
- "shl16insli r9, r9, -9300\n"
- "moveli r34, -25603\n"
- "shl16insli r34, r34, -29751\n"
- "shl16insli r34, r34, 11341\n"
- "shl16insli r34, r34, 7895\n"
- "moveli r1, 15964\n"
- "shl16insli r1, r1, 23061\n"
- "shl16insli r1, r1, -7003\n"
- "shl16insli r1, r1, 27153\n"
- "{ v2sadu r9, r34, r1 ; fnop }\n"
- "move %0, r9\n"
- "move %1, r34\n"
- "move %2, r1\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2shl_X0.c b/none/tests/tilegx/insn_test_v2shl_X0.c
deleted file mode 100644
index bac9889..0000000
--- a/none/tests/tilegx/insn_test_v2shl_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2shl_X0.c
-//op=312
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x11c672ab78dd743b, 0x31d131ae6b7da416 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r34, 29514\n"
- "shl16insli r34, r34, 14828\n"
- "shl16insli r34, r34, 1013\n"
- "shl16insli r34, r34, 14302\n"
- "moveli r19, -22322\n"
- "shl16insli r19, r19, -9600\n"
- "shl16insli r19, r19, 31146\n"
- "shl16insli r19, r19, -10762\n"
- "moveli r19, 1482\n"
- "shl16insli r19, r19, 23578\n"
- "shl16insli r19, r19, 5382\n"
- "shl16insli r19, r19, 26331\n"
- "{ v2shl r34, r19, r19 ; fnop }\n"
- "move %0, r34\n"
- "move %1, r19\n"
- "move %2, r19\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2shl_X1.c b/none/tests/tilegx/insn_test_v2shl_X1.c
deleted file mode 100644
index b3af644..0000000
--- a/none/tests/tilegx/insn_test_v2shl_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2shl_X1.c
-//op=312
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x11c672ab78dd743b, 0x31d131ae6b7da416 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r34, 29514\n"
- "shl16insli r34, r34, 14828\n"
- "shl16insli r34, r34, 1013\n"
- "shl16insli r34, r34, 14302\n"
- "moveli r19, -22322\n"
- "shl16insli r19, r19, -9600\n"
- "shl16insli r19, r19, 31146\n"
- "shl16insli r19, r19, -10762\n"
- "moveli r19, 1482\n"
- "shl16insli r19, r19, 23578\n"
- "shl16insli r19, r19, 5382\n"
- "shl16insli r19, r19, 26331\n"
- "{ fnop ; v2shl r34, r19, r19 }\n"
- "move %0, r34\n"
- "move %1, r19\n"
- "move %2, r19\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2shli_X0.c b/none/tests/tilegx/insn_test_v2shli_X0.c
deleted file mode 100644
index b1edc20..0000000
--- a/none/tests/tilegx/insn_test_v2shli_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_v2shli_X0.c
-//op=313
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x499ada215a6ab283, 0x5c0e0858161567af };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r34, -21610\n"
- "shl16insli r34, r34, -29358\n"
- "shl16insli r34, r34, -13412\n"
- "shl16insli r34, r34, 28660\n"
- "moveli r48, 16361\n"
- "shl16insli r48, r48, 2055\n"
- "shl16insli r48, r48, 4220\n"
- "shl16insli r48, r48, 9151\n"
- "{ v2shli r34, r48, 2 ; fnop }\n"
- "move %0, r34\n"
- "move %1, r48\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2shli_X1.c b/none/tests/tilegx/insn_test_v2shli_X1.c
deleted file mode 100644
index 4802022..0000000
--- a/none/tests/tilegx/insn_test_v2shli_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_v2shli_X1.c
-//op=313
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x499ada215a6ab283, 0x5c0e0858161567af };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r34, -21610\n"
- "shl16insli r34, r34, -29358\n"
- "shl16insli r34, r34, -13412\n"
- "shl16insli r34, r34, 28660\n"
- "moveli r48, 16361\n"
- "shl16insli r48, r48, 2055\n"
- "shl16insli r48, r48, 4220\n"
- "shl16insli r48, r48, 9151\n"
- "{ fnop ; v2shli r34, r48, 2 }\n"
- "move %0, r34\n"
- "move %1, r48\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2shlsc_X0.c b/none/tests/tilegx/insn_test_v2shlsc_X0.c
deleted file mode 100644
index a769286..0000000
--- a/none/tests/tilegx/insn_test_v2shlsc_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2shlsc_X0.c
-//op=314
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x75c151f71f3dac9d, 0xc2cac20f9054ab64 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r42, -14850\n"
- "shl16insli r42, r42, -32360\n"
- "shl16insli r42, r42, 12889\n"
- "shl16insli r42, r42, 3288\n"
- "moveli r27, -3965\n"
- "shl16insli r27, r27, -6372\n"
- "shl16insli r27, r27, 21671\n"
- "shl16insli r27, r27, 553\n"
- "moveli r24, -19347\n"
- "shl16insli r24, r24, 16492\n"
- "shl16insli r24, r24, 10067\n"
- "shl16insli r24, r24, 7567\n"
- "{ v2shlsc r42, r27, r24 ; fnop }\n"
- "move %0, r42\n"
- "move %1, r27\n"
- "move %2, r24\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2shlsc_X1.c b/none/tests/tilegx/insn_test_v2shlsc_X1.c
deleted file mode 100644
index 88a5b76..0000000
--- a/none/tests/tilegx/insn_test_v2shlsc_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2shlsc_X1.c
-//op=314
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x75c151f71f3dac9d, 0xc2cac20f9054ab64 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r42, -14850\n"
- "shl16insli r42, r42, -32360\n"
- "shl16insli r42, r42, 12889\n"
- "shl16insli r42, r42, 3288\n"
- "moveli r27, -3965\n"
- "shl16insli r27, r27, -6372\n"
- "shl16insli r27, r27, 21671\n"
- "shl16insli r27, r27, 553\n"
- "moveli r24, -19347\n"
- "shl16insli r24, r24, 16492\n"
- "shl16insli r24, r24, 10067\n"
- "shl16insli r24, r24, 7567\n"
- "{ fnop ; v2shlsc r42, r27, r24 }\n"
- "move %0, r42\n"
- "move %1, r27\n"
- "move %2, r24\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2shrs_X0.c b/none/tests/tilegx/insn_test_v2shrs_X0.c
deleted file mode 100644
index 8bb9af6..0000000
--- a/none/tests/tilegx/insn_test_v2shrs_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2shrs_X0.c
-//op=315
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x2e2bf09c65385753, 0xebdd0a243fdaeac0 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r27, -11697\n"
- "shl16insli r27, r27, 28366\n"
- "shl16insli r27, r27, -10445\n"
- "shl16insli r27, r27, -26110\n"
- "moveli r43, 19765\n"
- "shl16insli r43, r43, 31767\n"
- "shl16insli r43, r43, 18729\n"
- "shl16insli r43, r43, 27881\n"
- "moveli r4, -18306\n"
- "shl16insli r4, r4, 19057\n"
- "shl16insli r4, r4, 16125\n"
- "shl16insli r4, r4, -18666\n"
- "{ v2shrs r27, r43, r4 ; fnop }\n"
- "move %0, r27\n"
- "move %1, r43\n"
- "move %2, r4\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2shrs_X1.c b/none/tests/tilegx/insn_test_v2shrs_X1.c
deleted file mode 100644
index f55532f..0000000
--- a/none/tests/tilegx/insn_test_v2shrs_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2shrs_X1.c
-//op=315
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x2e2bf09c65385753, 0xebdd0a243fdaeac0 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r27, -11697\n"
- "shl16insli r27, r27, 28366\n"
- "shl16insli r27, r27, -10445\n"
- "shl16insli r27, r27, -26110\n"
- "moveli r43, 19765\n"
- "shl16insli r43, r43, 31767\n"
- "shl16insli r43, r43, 18729\n"
- "shl16insli r43, r43, 27881\n"
- "moveli r4, -18306\n"
- "shl16insli r4, r4, 19057\n"
- "shl16insli r4, r4, 16125\n"
- "shl16insli r4, r4, -18666\n"
- "{ fnop ; v2shrs r27, r43, r4 }\n"
- "move %0, r27\n"
- "move %1, r43\n"
- "move %2, r4\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2shrsi_X0.c b/none/tests/tilegx/insn_test_v2shrsi_X0.c
deleted file mode 100644
index 09c6987..0000000
--- a/none/tests/tilegx/insn_test_v2shrsi_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_v2shrsi_X0.c
-//op=316
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x7c9257e7675dc02e, 0x194c873261582759 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r29, -19874\n"
- "shl16insli r29, r29, -32652\n"
- "shl16insli r29, r29, -27551\n"
- "shl16insli r29, r29, 14010\n"
- "moveli r39, -29195\n"
- "shl16insli r39, r39, -14971\n"
- "shl16insli r39, r39, 21267\n"
- "shl16insli r39, r39, -6933\n"
- "{ v2shrsi r29, r39, 29 ; fnop }\n"
- "move %0, r29\n"
- "move %1, r39\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2shrsi_X1.c b/none/tests/tilegx/insn_test_v2shrsi_X1.c
deleted file mode 100644
index c6b5c86..0000000
--- a/none/tests/tilegx/insn_test_v2shrsi_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_v2shrsi_X1.c
-//op=316
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x7c9257e7675dc02e, 0x194c873261582759 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r29, -19874\n"
- "shl16insli r29, r29, -32652\n"
- "shl16insli r29, r29, -27551\n"
- "shl16insli r29, r29, 14010\n"
- "moveli r39, -29195\n"
- "shl16insli r39, r39, -14971\n"
- "shl16insli r39, r39, 21267\n"
- "shl16insli r39, r39, -6933\n"
- "{ fnop ; v2shrsi r29, r39, 29 }\n"
- "move %0, r29\n"
- "move %1, r39\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2shru_X0.c b/none/tests/tilegx/insn_test_v2shru_X0.c
deleted file mode 100644
index 71b6179..0000000
--- a/none/tests/tilegx/insn_test_v2shru_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2shru_X0.c
-//op=317
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x57bcf4c2092d9b7c, 0xf0b9de77e27316a4 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r50, 5090\n"
- "shl16insli r50, r50, -3949\n"
- "shl16insli r50, r50, -32171\n"
- "shl16insli r50, r50, -2954\n"
- "moveli r25, -17595\n"
- "shl16insli r25, r25, 2853\n"
- "shl16insli r25, r25, -2027\n"
- "shl16insli r25, r25, 1813\n"
- "moveli r0, 31428\n"
- "shl16insli r0, r0, -7946\n"
- "shl16insli r0, r0, -26525\n"
- "shl16insli r0, r0, -15747\n"
- "{ v2shru r50, r25, r0 ; fnop }\n"
- "move %0, r50\n"
- "move %1, r25\n"
- "move %2, r0\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2shru_X1.c b/none/tests/tilegx/insn_test_v2shru_X1.c
deleted file mode 100644
index dd2b369..0000000
--- a/none/tests/tilegx/insn_test_v2shru_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2shru_X1.c
-//op=317
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x57bcf4c2092d9b7c, 0xf0b9de77e27316a4 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r50, 5090\n"
- "shl16insli r50, r50, -3949\n"
- "shl16insli r50, r50, -32171\n"
- "shl16insli r50, r50, -2954\n"
- "moveli r25, -17595\n"
- "shl16insli r25, r25, 2853\n"
- "shl16insli r25, r25, -2027\n"
- "shl16insli r25, r25, 1813\n"
- "moveli r0, 31428\n"
- "shl16insli r0, r0, -7946\n"
- "shl16insli r0, r0, -26525\n"
- "shl16insli r0, r0, -15747\n"
- "{ fnop ; v2shru r50, r25, r0 }\n"
- "move %0, r50\n"
- "move %1, r25\n"
- "move %2, r0\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2shrui_X0.c b/none/tests/tilegx/insn_test_v2shrui_X0.c
deleted file mode 100644
index 990a05b..0000000
--- a/none/tests/tilegx/insn_test_v2shrui_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_v2shrui_X0.c
-//op=318
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd373e4dd4abdb244, 0x2f10bc93a323ca0d };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r23, 20609\n"
- "shl16insli r23, r23, -28665\n"
- "shl16insli r23, r23, -5637\n"
- "shl16insli r23, r23, -7979\n"
- "moveli r22, -6693\n"
- "shl16insli r22, r22, 32122\n"
- "shl16insli r22, r22, 32283\n"
- "shl16insli r22, r22, -22128\n"
- "{ v2shrui r23, r22, 62 ; fnop }\n"
- "move %0, r23\n"
- "move %1, r22\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2shrui_X1.c b/none/tests/tilegx/insn_test_v2shrui_X1.c
deleted file mode 100644
index 91bdb88..0000000
--- a/none/tests/tilegx/insn_test_v2shrui_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_v2shrui_X1.c
-//op=318
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd373e4dd4abdb244, 0x2f10bc93a323ca0d };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r23, 20609\n"
- "shl16insli r23, r23, -28665\n"
- "shl16insli r23, r23, -5637\n"
- "shl16insli r23, r23, -7979\n"
- "moveli r22, -6693\n"
- "shl16insli r22, r22, 32122\n"
- "shl16insli r22, r22, 32283\n"
- "shl16insli r22, r22, -22128\n"
- "{ fnop ; v2shrui r23, r22, 62 }\n"
- "move %0, r23\n"
- "move %1, r22\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2sub_X0.c b/none/tests/tilegx/insn_test_v2sub_X0.c
deleted file mode 100644
index 62db68f..0000000
--- a/none/tests/tilegx/insn_test_v2sub_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2sub_X0.c
-//op=319
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x61c13e55406befc0, 0xe69a8a5b32e86179 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r39, -19019\n"
- "shl16insli r39, r39, 19818\n"
- "shl16insli r39, r39, 30879\n"
- "shl16insli r39, r39, -27712\n"
- "moveli r20, 15911\n"
- "shl16insli r20, r20, 26398\n"
- "shl16insli r20, r20, -12667\n"
- "shl16insli r20, r20, 29760\n"
- "moveli r38, -21567\n"
- "shl16insli r38, r38, -21338\n"
- "shl16insli r38, r38, -1807\n"
- "shl16insli r38, r38, -13303\n"
- "{ v2sub r39, r20, r38 ; fnop }\n"
- "move %0, r39\n"
- "move %1, r20\n"
- "move %2, r38\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2sub_X1.c b/none/tests/tilegx/insn_test_v2sub_X1.c
deleted file mode 100644
index f69f4eb..0000000
--- a/none/tests/tilegx/insn_test_v2sub_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2sub_X1.c
-//op=319
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x61c13e55406befc0, 0xe69a8a5b32e86179 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r39, -19019\n"
- "shl16insli r39, r39, 19818\n"
- "shl16insli r39, r39, 30879\n"
- "shl16insli r39, r39, -27712\n"
- "moveli r20, 15911\n"
- "shl16insli r20, r20, 26398\n"
- "shl16insli r20, r20, -12667\n"
- "shl16insli r20, r20, 29760\n"
- "moveli r38, -21567\n"
- "shl16insli r38, r38, -21338\n"
- "shl16insli r38, r38, -1807\n"
- "shl16insli r38, r38, -13303\n"
- "{ fnop ; v2sub r39, r20, r38 }\n"
- "move %0, r39\n"
- "move %1, r20\n"
- "move %2, r38\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2subsc_X0.c b/none/tests/tilegx/insn_test_v2subsc_X0.c
deleted file mode 100644
index 2fde659..0000000
--- a/none/tests/tilegx/insn_test_v2subsc_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2subsc_X0.c
-//op=320
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd8c6caab057cf371, 0x86109da9991e057a };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r19, 13645\n"
- "shl16insli r19, r19, 12702\n"
- "shl16insli r19, r19, -22722\n"
- "shl16insli r19, r19, 25020\n"
- "moveli r19, 10415\n"
- "shl16insli r19, r19, -24373\n"
- "shl16insli r19, r19, 23725\n"
- "shl16insli r19, r19, -29919\n"
- "moveli r37, 12018\n"
- "shl16insli r37, r37, -2612\n"
- "shl16insli r37, r37, 2644\n"
- "shl16insli r37, r37, -1447\n"
- "{ v2subsc r19, r19, r37 ; fnop }\n"
- "move %0, r19\n"
- "move %1, r19\n"
- "move %2, r37\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v2subsc_X1.c b/none/tests/tilegx/insn_test_v2subsc_X1.c
deleted file mode 100644
index cd42c16..0000000
--- a/none/tests/tilegx/insn_test_v2subsc_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v2subsc_X1.c
-//op=320
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd8c6caab057cf371, 0x86109da9991e057a };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r19, 13645\n"
- "shl16insli r19, r19, 12702\n"
- "shl16insli r19, r19, -22722\n"
- "shl16insli r19, r19, 25020\n"
- "moveli r19, 10415\n"
- "shl16insli r19, r19, -24373\n"
- "shl16insli r19, r19, 23725\n"
- "shl16insli r19, r19, -29919\n"
- "moveli r37, 12018\n"
- "shl16insli r37, r37, -2612\n"
- "shl16insli r37, r37, 2644\n"
- "shl16insli r37, r37, -1447\n"
- "{ fnop ; v2subsc r19, r19, r37 }\n"
- "move %0, r19\n"
- "move %1, r19\n"
- "move %2, r37\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v4add_X0.c b/none/tests/tilegx/insn_test_v4add_X0.c
deleted file mode 100644
index 37ffc31..0000000
--- a/none/tests/tilegx/insn_test_v4add_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v4add_X0.c
-//op=321
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xe8992341eac94df6, 0x65cc09dafded6d76 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r37, -15907\n"
- "shl16insli r37, r37, -20157\n"
- "shl16insli r37, r37, 22361\n"
- "shl16insli r37, r37, -24834\n"
- "moveli r23, 11074\n"
- "shl16insli r23, r23, 24074\n"
- "shl16insli r23, r23, 17669\n"
- "shl16insli r23, r23, 8301\n"
- "moveli r15, -19606\n"
- "shl16insli r15, r15, 31855\n"
- "shl16insli r15, r15, -1361\n"
- "shl16insli r15, r15, -31541\n"
- "{ v4add r37, r23, r15 ; fnop }\n"
- "move %0, r37\n"
- "move %1, r23\n"
- "move %2, r15\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v4add_X1.c b/none/tests/tilegx/insn_test_v4add_X1.c
deleted file mode 100644
index 010316c..0000000
--- a/none/tests/tilegx/insn_test_v4add_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v4add_X1.c
-//op=321
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xe8992341eac94df6, 0x65cc09dafded6d76 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r37, -15907\n"
- "shl16insli r37, r37, -20157\n"
- "shl16insli r37, r37, 22361\n"
- "shl16insli r37, r37, -24834\n"
- "moveli r23, 11074\n"
- "shl16insli r23, r23, 24074\n"
- "shl16insli r23, r23, 17669\n"
- "shl16insli r23, r23, 8301\n"
- "moveli r15, -19606\n"
- "shl16insli r15, r15, 31855\n"
- "shl16insli r15, r15, -1361\n"
- "shl16insli r15, r15, -31541\n"
- "{ fnop ; v4add r37, r23, r15 }\n"
- "move %0, r37\n"
- "move %1, r23\n"
- "move %2, r15\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v4addsc_X0.c b/none/tests/tilegx/insn_test_v4addsc_X0.c
deleted file mode 100644
index 5852801..0000000
--- a/none/tests/tilegx/insn_test_v4addsc_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v4addsc_X0.c
-//op=322
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd4a558c5b71d713e, 0x4639d63ca03e5e4e };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r35, 5393\n"
- "shl16insli r35, r35, -22253\n"
- "shl16insli r35, r35, 25749\n"
- "shl16insli r35, r35, -7203\n"
- "moveli r9, 21658\n"
- "shl16insli r9, r9, 7462\n"
- "shl16insli r9, r9, -214\n"
- "shl16insli r9, r9, -426\n"
- "moveli r15, -17213\n"
- "shl16insli r15, r15, 15408\n"
- "shl16insli r15, r15, -28656\n"
- "shl16insli r15, r15, 10623\n"
- "{ v4addsc r35, r9, r15 ; fnop }\n"
- "move %0, r35\n"
- "move %1, r9\n"
- "move %2, r15\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v4addsc_X1.c b/none/tests/tilegx/insn_test_v4addsc_X1.c
deleted file mode 100644
index 09923dc..0000000
--- a/none/tests/tilegx/insn_test_v4addsc_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v4addsc_X1.c
-//op=322
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xd4a558c5b71d713e, 0x4639d63ca03e5e4e };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r35, 5393\n"
- "shl16insli r35, r35, -22253\n"
- "shl16insli r35, r35, 25749\n"
- "shl16insli r35, r35, -7203\n"
- "moveli r9, 21658\n"
- "shl16insli r9, r9, 7462\n"
- "shl16insli r9, r9, -214\n"
- "shl16insli r9, r9, -426\n"
- "moveli r15, -17213\n"
- "shl16insli r15, r15, 15408\n"
- "shl16insli r15, r15, -28656\n"
- "shl16insli r15, r15, 10623\n"
- "{ fnop ; v4addsc r35, r9, r15 }\n"
- "move %0, r35\n"
- "move %1, r9\n"
- "move %2, r15\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v4int_h_X0.c b/none/tests/tilegx/insn_test_v4int_h_X0.c
deleted file mode 100644
index bcecbee..0000000
--- a/none/tests/tilegx/insn_test_v4int_h_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v4int_h_X0.c
-//op=323
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x41bcf962c564feb9, 0xdaeccac706283a05 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r13, -28418\n"
- "shl16insli r13, r13, 24424\n"
- "shl16insli r13, r13, 6148\n"
- "shl16insli r13, r13, -14231\n"
- "moveli r43, -26849\n"
- "shl16insli r43, r43, 4171\n"
- "shl16insli r43, r43, -14537\n"
- "shl16insli r43, r43, -11074\n"
- "moveli r45, 356\n"
- "shl16insli r45, r45, 21071\n"
- "shl16insli r45, r45, -4609\n"
- "shl16insli r45, r45, 18199\n"
- "{ v4int_h r13, r43, r45 ; fnop }\n"
- "move %0, r13\n"
- "move %1, r43\n"
- "move %2, r45\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v4int_h_X1.c b/none/tests/tilegx/insn_test_v4int_h_X1.c
deleted file mode 100644
index b1ba5c4..0000000
--- a/none/tests/tilegx/insn_test_v4int_h_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v4int_h_X1.c
-//op=323
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x41bcf962c564feb9, 0xdaeccac706283a05 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r13, -28418\n"
- "shl16insli r13, r13, 24424\n"
- "shl16insli r13, r13, 6148\n"
- "shl16insli r13, r13, -14231\n"
- "moveli r43, -26849\n"
- "shl16insli r43, r43, 4171\n"
- "shl16insli r43, r43, -14537\n"
- "shl16insli r43, r43, -11074\n"
- "moveli r45, 356\n"
- "shl16insli r45, r45, 21071\n"
- "shl16insli r45, r45, -4609\n"
- "shl16insli r45, r45, 18199\n"
- "{ fnop ; v4int_h r13, r43, r45 }\n"
- "move %0, r13\n"
- "move %1, r43\n"
- "move %2, r45\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v4int_l_X0.c b/none/tests/tilegx/insn_test_v4int_l_X0.c
deleted file mode 100644
index cfa1062..0000000
--- a/none/tests/tilegx/insn_test_v4int_l_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v4int_l_X0.c
-//op=324
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x23b93f018ec49197, 0x228e8e83b7561e89 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r12, 7549\n"
- "shl16insli r12, r12, -19041\n"
- "shl16insli r12, r12, -30505\n"
- "shl16insli r12, r12, -15011\n"
- "moveli r7, 13064\n"
- "shl16insli r7, r7, -5615\n"
- "shl16insli r7, r7, -31470\n"
- "shl16insli r7, r7, -17239\n"
- "moveli r23, -24056\n"
- "shl16insli r23, r23, -14095\n"
- "shl16insli r23, r23, 1863\n"
- "shl16insli r23, r23, -26485\n"
- "{ v4int_l r12, r7, r23 ; fnop }\n"
- "move %0, r12\n"
- "move %1, r7\n"
- "move %2, r23\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v4int_l_X1.c b/none/tests/tilegx/insn_test_v4int_l_X1.c
deleted file mode 100644
index 0b52233..0000000
--- a/none/tests/tilegx/insn_test_v4int_l_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v4int_l_X1.c
-//op=324
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x23b93f018ec49197, 0x228e8e83b7561e89 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r12, 7549\n"
- "shl16insli r12, r12, -19041\n"
- "shl16insli r12, r12, -30505\n"
- "shl16insli r12, r12, -15011\n"
- "moveli r7, 13064\n"
- "shl16insli r7, r7, -5615\n"
- "shl16insli r7, r7, -31470\n"
- "shl16insli r7, r7, -17239\n"
- "moveli r23, -24056\n"
- "shl16insli r23, r23, -14095\n"
- "shl16insli r23, r23, 1863\n"
- "shl16insli r23, r23, -26485\n"
- "{ fnop ; v4int_l r12, r7, r23 }\n"
- "move %0, r12\n"
- "move %1, r7\n"
- "move %2, r23\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v4packsc_X0.c b/none/tests/tilegx/insn_test_v4packsc_X0.c
deleted file mode 100644
index 817edc9..0000000
--- a/none/tests/tilegx/insn_test_v4packsc_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v4packsc_X0.c
-//op=325
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9662ab02d3651bd3, 0x7d173ebe8d71845 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r11, 8404\n"
- "shl16insli r11, r11, -13138\n"
- "shl16insli r11, r11, -8174\n"
- "shl16insli r11, r11, 18247\n"
- "moveli r42, 26140\n"
- "shl16insli r42, r42, 28081\n"
- "shl16insli r42, r42, -4734\n"
- "shl16insli r42, r42, -2567\n"
- "moveli r34, 1665\n"
- "shl16insli r34, r34, -24287\n"
- "shl16insli r34, r34, 25276\n"
- "shl16insli r34, r34, 26188\n"
- "{ v4packsc r11, r42, r34 ; fnop }\n"
- "move %0, r11\n"
- "move %1, r42\n"
- "move %2, r34\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v4packsc_X1.c b/none/tests/tilegx/insn_test_v4packsc_X1.c
deleted file mode 100644
index 7f7189d..0000000
--- a/none/tests/tilegx/insn_test_v4packsc_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v4packsc_X1.c
-//op=325
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x9662ab02d3651bd3, 0x7d173ebe8d71845 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r11, 8404\n"
- "shl16insli r11, r11, -13138\n"
- "shl16insli r11, r11, -8174\n"
- "shl16insli r11, r11, 18247\n"
- "moveli r42, 26140\n"
- "shl16insli r42, r42, 28081\n"
- "shl16insli r42, r42, -4734\n"
- "shl16insli r42, r42, -2567\n"
- "moveli r34, 1665\n"
- "shl16insli r34, r34, -24287\n"
- "shl16insli r34, r34, 25276\n"
- "shl16insli r34, r34, 26188\n"
- "{ fnop ; v4packsc r11, r42, r34 }\n"
- "move %0, r11\n"
- "move %1, r42\n"
- "move %2, r34\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v4shl_X0.c b/none/tests/tilegx/insn_test_v4shl_X0.c
deleted file mode 100644
index da693dd..0000000
--- a/none/tests/tilegx/insn_test_v4shl_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v4shl_X0.c
-//op=326
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xb3c4aad383be7970, 0xcdce8cd30da8f45b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r34, 25062\n"
- "shl16insli r34, r34, -3688\n"
- "shl16insli r34, r34, 15670\n"
- "shl16insli r34, r34, 15480\n"
- "moveli r41, 6763\n"
- "shl16insli r41, r41, -31823\n"
- "shl16insli r41, r41, 3289\n"
- "shl16insli r41, r41, 2018\n"
- "moveli r35, -12490\n"
- "shl16insli r35, r35, 25114\n"
- "shl16insli r35, r35, -6270\n"
- "shl16insli r35, r35, -17183\n"
- "{ v4shl r34, r41, r35 ; fnop }\n"
- "move %0, r34\n"
- "move %1, r41\n"
- "move %2, r35\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v4shl_X1.c b/none/tests/tilegx/insn_test_v4shl_X1.c
deleted file mode 100644
index 2c34587..0000000
--- a/none/tests/tilegx/insn_test_v4shl_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v4shl_X1.c
-//op=326
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xb3c4aad383be7970, 0xcdce8cd30da8f45b };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r34, 25062\n"
- "shl16insli r34, r34, -3688\n"
- "shl16insli r34, r34, 15670\n"
- "shl16insli r34, r34, 15480\n"
- "moveli r41, 6763\n"
- "shl16insli r41, r41, -31823\n"
- "shl16insli r41, r41, 3289\n"
- "shl16insli r41, r41, 2018\n"
- "moveli r35, -12490\n"
- "shl16insli r35, r35, 25114\n"
- "shl16insli r35, r35, -6270\n"
- "shl16insli r35, r35, -17183\n"
- "{ fnop ; v4shl r34, r41, r35 }\n"
- "move %0, r34\n"
- "move %1, r41\n"
- "move %2, r35\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v4shlsc_X0.c b/none/tests/tilegx/insn_test_v4shlsc_X0.c
deleted file mode 100644
index d8dd118..0000000
--- a/none/tests/tilegx/insn_test_v4shlsc_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v4shlsc_X0.c
-//op=327
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x2568a113544174a0, 0xd019893a69c430df };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r13, -616\n"
- "shl16insli r13, r13, -17536\n"
- "shl16insli r13, r13, -4093\n"
- "shl16insli r13, r13, -4473\n"
- "moveli r27, 28804\n"
- "shl16insli r27, r27, -24345\n"
- "shl16insli r27, r27, 3201\n"
- "shl16insli r27, r27, -21187\n"
- "moveli r33, 2083\n"
- "shl16insli r33, r33, -15312\n"
- "shl16insli r33, r33, -6918\n"
- "shl16insli r33, r33, -23024\n"
- "{ v4shlsc r13, r27, r33 ; fnop }\n"
- "move %0, r13\n"
- "move %1, r27\n"
- "move %2, r33\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v4shlsc_X1.c b/none/tests/tilegx/insn_test_v4shlsc_X1.c
deleted file mode 100644
index a6ef69d..0000000
--- a/none/tests/tilegx/insn_test_v4shlsc_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v4shlsc_X1.c
-//op=327
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x2568a113544174a0, 0xd019893a69c430df };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r13, -616\n"
- "shl16insli r13, r13, -17536\n"
- "shl16insli r13, r13, -4093\n"
- "shl16insli r13, r13, -4473\n"
- "moveli r27, 28804\n"
- "shl16insli r27, r27, -24345\n"
- "shl16insli r27, r27, 3201\n"
- "shl16insli r27, r27, -21187\n"
- "moveli r33, 2083\n"
- "shl16insli r33, r33, -15312\n"
- "shl16insli r33, r33, -6918\n"
- "shl16insli r33, r33, -23024\n"
- "{ fnop ; v4shlsc r13, r27, r33 }\n"
- "move %0, r13\n"
- "move %1, r27\n"
- "move %2, r33\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v4shrs_X0.c b/none/tests/tilegx/insn_test_v4shrs_X0.c
deleted file mode 100644
index 9bf37e2..0000000
--- a/none/tests/tilegx/insn_test_v4shrs_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v4shrs_X0.c
-//op=328
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x2a5face79840f7a7, 0xd75570c277b73b03 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r34, 2928\n"
- "shl16insli r34, r34, -22351\n"
- "shl16insli r34, r34, 15965\n"
- "shl16insli r34, r34, -15676\n"
- "moveli r34, 24886\n"
- "shl16insli r34, r34, 6119\n"
- "shl16insli r34, r34, -23856\n"
- "shl16insli r34, r34, -8685\n"
- "moveli r45, 1295\n"
- "shl16insli r45, r45, -12278\n"
- "shl16insli r45, r45, -23875\n"
- "shl16insli r45, r45, 20883\n"
- "{ v4shrs r34, r34, r45 ; fnop }\n"
- "move %0, r34\n"
- "move %1, r34\n"
- "move %2, r45\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v4shrs_X1.c b/none/tests/tilegx/insn_test_v4shrs_X1.c
deleted file mode 100644
index 1fb011b..0000000
--- a/none/tests/tilegx/insn_test_v4shrs_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v4shrs_X1.c
-//op=328
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x2a5face79840f7a7, 0xd75570c277b73b03 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r34, 2928\n"
- "shl16insli r34, r34, -22351\n"
- "shl16insli r34, r34, 15965\n"
- "shl16insli r34, r34, -15676\n"
- "moveli r34, 24886\n"
- "shl16insli r34, r34, 6119\n"
- "shl16insli r34, r34, -23856\n"
- "shl16insli r34, r34, -8685\n"
- "moveli r45, 1295\n"
- "shl16insli r45, r45, -12278\n"
- "shl16insli r45, r45, -23875\n"
- "shl16insli r45, r45, 20883\n"
- "{ fnop ; v4shrs r34, r34, r45 }\n"
- "move %0, r34\n"
- "move %1, r34\n"
- "move %2, r45\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v4shru_X0.c b/none/tests/tilegx/insn_test_v4shru_X0.c
deleted file mode 100644
index f5d8d2b..0000000
--- a/none/tests/tilegx/insn_test_v4shru_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v4shru_X0.c
-//op=329
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xf942b109f0cbea25, 0x66bb2ebdeb23deb0 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r32, -17067\n"
- "shl16insli r32, r32, 30779\n"
- "shl16insli r32, r32, -22230\n"
- "shl16insli r32, r32, -5615\n"
- "moveli r50, -4121\n"
- "shl16insli r50, r50, 16135\n"
- "shl16insli r50, r50, -13858\n"
- "shl16insli r50, r50, 4952\n"
- "moveli r32, 12419\n"
- "shl16insli r32, r32, -25174\n"
- "shl16insli r32, r32, -23501\n"
- "shl16insli r32, r32, 7961\n"
- "{ v4shru r32, r50, r32 ; fnop }\n"
- "move %0, r32\n"
- "move %1, r50\n"
- "move %2, r32\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v4shru_X1.c b/none/tests/tilegx/insn_test_v4shru_X1.c
deleted file mode 100644
index c77d354..0000000
--- a/none/tests/tilegx/insn_test_v4shru_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v4shru_X1.c
-//op=329
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xf942b109f0cbea25, 0x66bb2ebdeb23deb0 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r32, -17067\n"
- "shl16insli r32, r32, 30779\n"
- "shl16insli r32, r32, -22230\n"
- "shl16insli r32, r32, -5615\n"
- "moveli r50, -4121\n"
- "shl16insli r50, r50, 16135\n"
- "shl16insli r50, r50, -13858\n"
- "shl16insli r50, r50, 4952\n"
- "moveli r32, 12419\n"
- "shl16insli r32, r32, -25174\n"
- "shl16insli r32, r32, -23501\n"
- "shl16insli r32, r32, 7961\n"
- "{ fnop ; v4shru r32, r50, r32 }\n"
- "move %0, r32\n"
- "move %1, r50\n"
- "move %2, r32\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v4sub_X0.c b/none/tests/tilegx/insn_test_v4sub_X0.c
deleted file mode 100644
index b2d9500..0000000
--- a/none/tests/tilegx/insn_test_v4sub_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v4sub_X0.c
-//op=330
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xa3c6a3690a9f8085, 0xec7e102d827fb085 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r27, 16489\n"
- "shl16insli r27, r27, 1852\n"
- "shl16insli r27, r27, -22328\n"
- "shl16insli r27, r27, -20016\n"
- "moveli r15, -8129\n"
- "shl16insli r15, r15, -16265\n"
- "shl16insli r15, r15, -27946\n"
- "shl16insli r15, r15, 22744\n"
- "moveli r28, 12168\n"
- "shl16insli r28, r28, 24071\n"
- "shl16insli r28, r28, 5574\n"
- "shl16insli r28, r28, 21456\n"
- "{ v4sub r27, r15, r28 ; fnop }\n"
- "move %0, r27\n"
- "move %1, r15\n"
- "move %2, r28\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v4sub_X1.c b/none/tests/tilegx/insn_test_v4sub_X1.c
deleted file mode 100644
index 481bb20..0000000
--- a/none/tests/tilegx/insn_test_v4sub_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v4sub_X1.c
-//op=330
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0xa3c6a3690a9f8085, 0xec7e102d827fb085 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r27, 16489\n"
- "shl16insli r27, r27, 1852\n"
- "shl16insli r27, r27, -22328\n"
- "shl16insli r27, r27, -20016\n"
- "moveli r15, -8129\n"
- "shl16insli r15, r15, -16265\n"
- "shl16insli r15, r15, -27946\n"
- "shl16insli r15, r15, 22744\n"
- "moveli r28, 12168\n"
- "shl16insli r28, r28, 24071\n"
- "shl16insli r28, r28, 5574\n"
- "shl16insli r28, r28, 21456\n"
- "{ fnop ; v4sub r27, r15, r28 }\n"
- "move %0, r27\n"
- "move %1, r15\n"
- "move %2, r28\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v4subsc_X0.c b/none/tests/tilegx/insn_test_v4subsc_X0.c
deleted file mode 100644
index f74f7c1..0000000
--- a/none/tests/tilegx/insn_test_v4subsc_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v4subsc_X0.c
-//op=331
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x92adb447873201ff, 0xd36a8d07bde44b83 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r42, 30010\n"
- "shl16insli r42, r42, 8476\n"
- "shl16insli r42, r42, 20122\n"
- "shl16insli r42, r42, -20634\n"
- "moveli r44, 26115\n"
- "shl16insli r44, r44, 9284\n"
- "shl16insli r44, r44, 29287\n"
- "shl16insli r44, r44, 8638\n"
- "moveli r29, 19275\n"
- "shl16insli r29, r29, -29979\n"
- "shl16insli r29, r29, 31395\n"
- "shl16insli r29, r29, -21694\n"
- "{ v4subsc r42, r44, r29 ; fnop }\n"
- "move %0, r42\n"
- "move %1, r44\n"
- "move %2, r29\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_v4subsc_X1.c b/none/tests/tilegx/insn_test_v4subsc_X1.c
deleted file mode 100644
index df250e7..0000000
--- a/none/tests/tilegx/insn_test_v4subsc_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_v4subsc_X1.c
-//op=331
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x92adb447873201ff, 0xd36a8d07bde44b83 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r42, 30010\n"
- "shl16insli r42, r42, 8476\n"
- "shl16insli r42, r42, 20122\n"
- "shl16insli r42, r42, -20634\n"
- "moveli r44, 26115\n"
- "shl16insli r44, r44, 9284\n"
- "shl16insli r44, r44, 29287\n"
- "shl16insli r44, r44, 8638\n"
- "moveli r29, 19275\n"
- "shl16insli r29, r29, -29979\n"
- "shl16insli r29, r29, 31395\n"
- "shl16insli r29, r29, -21694\n"
- "{ fnop ; v4subsc r42, r44, r29 }\n"
- "move %0, r42\n"
- "move %1, r44\n"
- "move %2, r29\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_wh64_X1.c b/none/tests/tilegx/insn_test_wh64_X1.c
deleted file mode 100644
index 827d7e3..0000000
--- a/none/tests/tilegx/insn_test_wh64_X1.c
+++ /dev/null
@@ -1,30 +0,0 @@
-//file: _insn_test_wh64_X1.c
-//op=332
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x109617bf21faf577, 0x269cb922a1bf2c20 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r11, -29126\n"
- "shl16insli r11, r11, -20326\n"
- "shl16insli r11, r11, 27689\n"
- "shl16insli r11, r11, 15548\n"
- "{ fnop ; wh64 r11 }\n"
- "move %0, r11\n"
- :"=r"(a[0]));
- printf("%016lx\n", a[0]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_xor_X0.c b/none/tests/tilegx/insn_test_xor_X0.c
deleted file mode 100644
index f1ee19c..0000000
--- a/none/tests/tilegx/insn_test_xor_X0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_xor_X0.c
-//op=333
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x4f4d9c00e64f18fd, 0x1894984f8a4b9b67 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r23, 15126\n"
- "shl16insli r23, r23, -17631\n"
- "shl16insli r23, r23, 31423\n"
- "shl16insli r23, r23, 10557\n"
- "moveli r20, -9320\n"
- "shl16insli r20, r20, -29957\n"
- "shl16insli r20, r20, 7281\n"
- "shl16insli r20, r20, 3173\n"
- "moveli r33, 2487\n"
- "shl16insli r33, r33, 6184\n"
- "shl16insli r33, r33, 10965\n"
- "shl16insli r33, r33, -25198\n"
- "{ xor r23, r20, r33 ; fnop }\n"
- "move %0, r23\n"
- "move %1, r20\n"
- "move %2, r33\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_xor_X1.c b/none/tests/tilegx/insn_test_xor_X1.c
deleted file mode 100644
index dd4af38..0000000
--- a/none/tests/tilegx/insn_test_xor_X1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_xor_X1.c
-//op=333
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x4f4d9c00e64f18fd, 0x1894984f8a4b9b67 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r23, 15126\n"
- "shl16insli r23, r23, -17631\n"
- "shl16insli r23, r23, 31423\n"
- "shl16insli r23, r23, 10557\n"
- "moveli r20, -9320\n"
- "shl16insli r20, r20, -29957\n"
- "shl16insli r20, r20, 7281\n"
- "shl16insli r20, r20, 3173\n"
- "moveli r33, 2487\n"
- "shl16insli r33, r33, 6184\n"
- "shl16insli r33, r33, 10965\n"
- "shl16insli r33, r33, -25198\n"
- "{ fnop ; xor r23, r20, r33 }\n"
- "move %0, r23\n"
- "move %1, r20\n"
- "move %2, r33\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_xor_Y0.c b/none/tests/tilegx/insn_test_xor_Y0.c
deleted file mode 100644
index bd345d2..0000000
--- a/none/tests/tilegx/insn_test_xor_Y0.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_xor_Y0.c
-//op=333
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x4f4d9c00e64f18fd, 0x1894984f8a4b9b67 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r23, 15126\n"
- "shl16insli r23, r23, -17631\n"
- "shl16insli r23, r23, 31423\n"
- "shl16insli r23, r23, 10557\n"
- "moveli r20, -9320\n"
- "shl16insli r20, r20, -29957\n"
- "shl16insli r20, r20, 7281\n"
- "shl16insli r20, r20, 3173\n"
- "moveli r33, 2487\n"
- "shl16insli r33, r33, 6184\n"
- "shl16insli r33, r33, 10965\n"
- "shl16insli r33, r33, -25198\n"
- "{ xor r23, r20, r33 ; fnop ; ld r63, r54 }\n"
- "move %0, r23\n"
- "move %1, r20\n"
- "move %2, r33\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_xor_Y1.c b/none/tests/tilegx/insn_test_xor_Y1.c
deleted file mode 100644
index c756d99..0000000
--- a/none/tests/tilegx/insn_test_xor_Y1.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//file: _insn_test_xor_Y1.c
-//op=333
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x4f4d9c00e64f18fd, 0x1894984f8a4b9b67 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r23, 15126\n"
- "shl16insli r23, r23, -17631\n"
- "shl16insli r23, r23, 31423\n"
- "shl16insli r23, r23, 10557\n"
- "moveli r20, -9320\n"
- "shl16insli r20, r20, -29957\n"
- "shl16insli r20, r20, 7281\n"
- "shl16insli r20, r20, 3173\n"
- "moveli r33, 2487\n"
- "shl16insli r33, r33, 6184\n"
- "shl16insli r33, r33, 10965\n"
- "shl16insli r33, r33, -25198\n"
- "{ fnop ; xor r23, r20, r33 ; ld r63, r54 }\n"
- "move %0, r23\n"
- "move %1, r20\n"
- "move %2, r33\n"
- :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- printf("%016lx\n", a[2]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_xori_X0.c b/none/tests/tilegx/insn_test_xori_X0.c
deleted file mode 100644
index d966409..0000000
--- a/none/tests/tilegx/insn_test_xori_X0.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_xori_X0.c
-//op=334
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x2f6c6cfee316d7, 0x334d1321b4c11950 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r46, 31370\n"
- "shl16insli r46, r46, -7442\n"
- "shl16insli r46, r46, 26409\n"
- "shl16insli r46, r46, 25903\n"
- "moveli r40, 2219\n"
- "shl16insli r40, r40, -14686\n"
- "shl16insli r40, r40, 5250\n"
- "shl16insli r40, r40, 16891\n"
- "{ xori r46, r40, 75 ; fnop }\n"
- "move %0, r46\n"
- "move %1, r40\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/tilegx/insn_test_xori_X1.c b/none/tests/tilegx/insn_test_xori_X1.c
deleted file mode 100644
index f061be5..0000000
--- a/none/tests/tilegx/insn_test_xori_X1.c
+++ /dev/null
@@ -1,36 +0,0 @@
-//file: _insn_test_xori_X1.c
-//op=334
-#include <stdio.h>
-#include <stdlib.h>
-
-void func_exit(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-void func_call(void) {
- printf("%s\n", __func__);
- exit(0);
-}
-
-unsigned long mem[2] = { 0x2f6c6cfee316d7, 0x334d1321b4c11950 };
-
-int main(void) {
- unsigned long a[4] = { 0, 0 };
- asm __volatile__ (
- "moveli r46, 31370\n"
- "shl16insli r46, r46, -7442\n"
- "shl16insli r46, r46, 26409\n"
- "shl16insli r46, r46, 25903\n"
- "moveli r40, 2219\n"
- "shl16insli r40, r40, -14686\n"
- "shl16insli r40, r40, 5250\n"
- "shl16insli r40, r40, 16891\n"
- "{ fnop ; xori r46, r40, 75 }\n"
- "move %0, r46\n"
- "move %1, r40\n"
- :"=r"(a[0]),"=r"(a[1]));
- printf("%016lx\n", a[0]);
- printf("%016lx\n", a[1]);
- return 0;
-}
diff --git a/none/tests/vgprintf_nvalgrind.stderr.exp b/none/tests/vgprintf_nvalgrind.stderr.exp
new file mode 100644
index 0000000..0a9dbe6
--- /dev/null
+++ b/none/tests/vgprintf_nvalgrind.stderr.exp
@@ -0,0 +1,4 @@
+
+0
+0
+
diff --git a/none/tests/vgprintf_nvalgrind.vgtest b/none/tests/vgprintf_nvalgrind.vgtest
new file mode 100644
index 0000000..e6e6253
--- /dev/null
+++ b/none/tests/vgprintf_nvalgrind.vgtest
@@ -0,0 +1 @@
+prog: vgprintf_nvalgrind
diff --git a/none/tests/x86-darwin/Makefile.am b/none/tests/x86-darwin/Makefile.am
index a11fd45..e9c33e5 100644
--- a/none/tests/x86-darwin/Makefile.am
+++ b/none/tests/x86-darwin/Makefile.am
@@ -6,11 +6,13 @@
EXTRA_DIST = \
bug341419.vgtest bug341419.stderr.exp \
- bug350062.vgtest bug350062.stderr.exp
+ bug350062.vgtest bug350062.stderr.exp \
+ cet_nops_gs.stderr.exp cet_nops_gs.stdout.exp cet_nops_gs.vgtest
check_PROGRAMS = \
bug341419 \
- bug350062
+ bug350062 \
+ cet_nops_gs
AM_CFLAGS += @FLAG_M32@ $(FLAG_MMMX) $(FLAG_MSSE)
AM_CXXFLAGS += @FLAG_M32@ $(FLAG_MMMX) $(FLAG_MSSE)
diff --git a/none/tests/x86-darwin/Makefile.in b/none/tests/x86-darwin/Makefile.in
index 76e67d9..2e7215e 100644
--- a/none/tests/x86-darwin/Makefile.in
+++ b/none/tests/x86-darwin/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -120,7 +120,8 @@
@COMPILER_IS_CLANG_TRUE@ -Wno-uninitialized -Wno-unused-value # \
@COMPILER_IS_CLANG_TRUE@ clang 3.0.0
@COMPILER_IS_CLANG_TRUE@am__append_7 = -Wno-unused-private-field # drd/tests/tsan_unittest.cpp
-check_PROGRAMS = bug341419$(EXEEXT) bug350062$(EXEEXT)
+check_PROGRAMS = bug341419$(EXEEXT) bug350062$(EXEEXT) \
+ cet_nops_gs$(EXEEXT)
subdir = none/tests/x86-darwin
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/configure.ac
@@ -138,6 +139,9 @@
bug350062_SOURCES = bug350062.c
bug350062_OBJECTS = bug350062.$(OBJEXT)
bug350062_LDADD = $(LDADD)
+cet_nops_gs_SOURCES = cet_nops_gs.c
+cet_nops_gs_OBJECTS = cet_nops_gs.$(OBJEXT)
+cet_nops_gs_LDADD = $(LDADD)
SCRIPTS = $(dist_noinst_SCRIPTS)
AM_V_P = $(am__v_P_@AM_V@)
am__v_P_ = $(am__v_P_@AM_DEFAULT_V@)
@@ -167,8 +171,8 @@
am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@)
am__v_CCLD_0 = @echo " CCLD " $@;
am__v_CCLD_1 =
-SOURCES = bug341419.c bug350062.c
-DIST_SOURCES = bug341419.c bug350062.c
+SOURCES = bug341419.c bug350062.c cet_nops_gs.c
+DIST_SOURCES = bug341419.c bug350062.c cet_nops_gs.c
am__can_run_installinfo = \
case $$AM_UPDATE_INFO_DIR in \
n|no|NO) false;; \
@@ -240,6 +244,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -410,6 +415,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -420,6 +426,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -494,8 +501,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -540,7 +545,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
@@ -568,7 +572,8 @@
EXTRA_DIST = \
bug341419.vgtest bug341419.stderr.exp \
- bug350062.vgtest bug350062.stderr.exp
+ bug350062.vgtest bug350062.stderr.exp \
+ cet_nops_gs.stderr.exp cet_nops_gs.stdout.exp cet_nops_gs.vgtest
all: all-am
@@ -616,6 +621,10 @@
@rm -f bug350062$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(bug350062_OBJECTS) $(bug350062_LDADD) $(LIBS)
+cet_nops_gs$(EXEEXT): $(cet_nops_gs_OBJECTS) $(cet_nops_gs_DEPENDENCIES) $(EXTRA_cet_nops_gs_DEPENDENCIES)
+ @rm -f cet_nops_gs$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(cet_nops_gs_OBJECTS) $(cet_nops_gs_LDADD) $(LIBS)
+
mostlyclean-compile:
-rm -f *.$(OBJEXT)
@@ -624,6 +633,7 @@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug341419.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug350062.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cet_nops_gs.Po@am__quote@
.c.o:
@am__fastdepCC_TRUE@ $(AM_V_CC)depbase=`echo $@ | sed 's|[^/]*$$|$(DEPDIR)/&|;s|\.o$$||'`;\
diff --git a/none/tests/x86-darwin/cet_nops_gs.c b/none/tests/x86-darwin/cet_nops_gs.c
new file mode 100644
index 0000000..c03f02c
--- /dev/null
+++ b/none/tests/x86-darwin/cet_nops_gs.c
@@ -0,0 +1,311 @@
+#include <stdio.h>
+
+int main ()
+{
+ printf("start testing GS prefix ..\n");
+ fflush(stdout);
+
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
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+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+
+ printf ("done\n");
+ return 0;
+}
diff --git a/none/tests/x86-darwin/cet_nops_gs.stderr.exp b/none/tests/x86-darwin/cet_nops_gs.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/x86-darwin/cet_nops_gs.stderr.exp
diff --git a/none/tests/x86-darwin/cet_nops_gs.stdout.exp b/none/tests/x86-darwin/cet_nops_gs.stdout.exp
new file mode 100644
index 0000000..b9673a7
--- /dev/null
+++ b/none/tests/x86-darwin/cet_nops_gs.stdout.exp
@@ -0,0 +1,2 @@
+start testing GS prefix ..
+done
diff --git a/none/tests/x86-darwin/cet_nops_gs.vgtest b/none/tests/x86-darwin/cet_nops_gs.vgtest
new file mode 100644
index 0000000..085e266
--- /dev/null
+++ b/none/tests/x86-darwin/cet_nops_gs.vgtest
@@ -0,0 +1,2 @@
+prog: cet_nops_gs
+vgopts: -q
diff --git a/none/tests/x86-linux/Makefile.am b/none/tests/x86-linux/Makefile.am
index 2c86693..21953ff 100644
--- a/none/tests/x86-linux/Makefile.am
+++ b/none/tests/x86-linux/Makefile.am
@@ -6,12 +6,16 @@
EXTRA_DIST = \
bug345887.stderr.exp bug345887.vgtest \
+ cet_nops_fs.stderr.exp cet_nops_fs.stdout.exp cet_nops_fs.vgtest \
+ cet_nops_gs.stderr.exp cet_nops_gs.stdout.exp cet_nops_gs.vgtest \
hang.stderr.exp hang.vgtest \
seg_override.stderr.exp seg_override.stdout.exp seg_override.vgtest \
sigcontext.stdout.exp sigcontext.stderr.exp sigcontext.vgtest
check_PROGRAMS = \
bug345887 \
+ cet_nops_fs \
+ cet_nops_gs \
hang \
seg_override \
sigcontext
diff --git a/none/tests/x86-linux/Makefile.in b/none/tests/x86-linux/Makefile.in
index 50677fa..d4f00f7 100644
--- a/none/tests/x86-linux/Makefile.in
+++ b/none/tests/x86-linux/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -120,8 +120,9 @@
@COMPILER_IS_CLANG_TRUE@ -Wno-uninitialized -Wno-unused-value # \
@COMPILER_IS_CLANG_TRUE@ clang 3.0.0
@COMPILER_IS_CLANG_TRUE@am__append_7 = -Wno-unused-private-field # drd/tests/tsan_unittest.cpp
-check_PROGRAMS = bug345887$(EXEEXT) hang$(EXEEXT) \
- seg_override$(EXEEXT) sigcontext$(EXEEXT)
+check_PROGRAMS = bug345887$(EXEEXT) cet_nops_fs$(EXEEXT) \
+ cet_nops_gs$(EXEEXT) hang$(EXEEXT) seg_override$(EXEEXT) \
+ sigcontext$(EXEEXT)
subdir = none/tests/x86-linux
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/configure.ac
@@ -136,6 +137,12 @@
bug345887_SOURCES = bug345887.c
bug345887_OBJECTS = bug345887.$(OBJEXT)
bug345887_LDADD = $(LDADD)
+cet_nops_fs_SOURCES = cet_nops_fs.c
+cet_nops_fs_OBJECTS = cet_nops_fs.$(OBJEXT)
+cet_nops_fs_LDADD = $(LDADD)
+cet_nops_gs_SOURCES = cet_nops_gs.c
+cet_nops_gs_OBJECTS = cet_nops_gs.$(OBJEXT)
+cet_nops_gs_LDADD = $(LDADD)
hang_SOURCES = hang.c
hang_OBJECTS = hang.$(OBJEXT)
hang_LDADD = $(LDADD)
@@ -174,8 +181,10 @@
am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@)
am__v_CCLD_0 = @echo " CCLD " $@;
am__v_CCLD_1 =
-SOURCES = bug345887.c hang.c seg_override.c sigcontext.c
-DIST_SOURCES = bug345887.c hang.c seg_override.c sigcontext.c
+SOURCES = bug345887.c cet_nops_fs.c cet_nops_gs.c hang.c \
+ seg_override.c sigcontext.c
+DIST_SOURCES = bug345887.c cet_nops_fs.c cet_nops_gs.c hang.c \
+ seg_override.c sigcontext.c
am__can_run_installinfo = \
case $$AM_UPDATE_INFO_DIR in \
n|no|NO) false;; \
@@ -247,6 +256,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -417,6 +427,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -427,6 +438,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -501,8 +513,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -547,7 +557,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
@@ -575,6 +584,8 @@
EXTRA_DIST = \
bug345887.stderr.exp bug345887.vgtest \
+ cet_nops_fs.stderr.exp cet_nops_fs.stdout.exp cet_nops_fs.vgtest \
+ cet_nops_gs.stderr.exp cet_nops_gs.stdout.exp cet_nops_gs.vgtest \
hang.stderr.exp hang.vgtest \
seg_override.stderr.exp seg_override.stdout.exp seg_override.vgtest \
sigcontext.stdout.exp sigcontext.stderr.exp sigcontext.vgtest
@@ -621,6 +632,14 @@
@rm -f bug345887$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(bug345887_OBJECTS) $(bug345887_LDADD) $(LIBS)
+cet_nops_fs$(EXEEXT): $(cet_nops_fs_OBJECTS) $(cet_nops_fs_DEPENDENCIES) $(EXTRA_cet_nops_fs_DEPENDENCIES)
+ @rm -f cet_nops_fs$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(cet_nops_fs_OBJECTS) $(cet_nops_fs_LDADD) $(LIBS)
+
+cet_nops_gs$(EXEEXT): $(cet_nops_gs_OBJECTS) $(cet_nops_gs_DEPENDENCIES) $(EXTRA_cet_nops_gs_DEPENDENCIES)
+ @rm -f cet_nops_gs$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(cet_nops_gs_OBJECTS) $(cet_nops_gs_LDADD) $(LIBS)
+
hang$(EXEEXT): $(hang_OBJECTS) $(hang_DEPENDENCIES) $(EXTRA_hang_DEPENDENCIES)
@rm -f hang$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(hang_OBJECTS) $(hang_LDADD) $(LIBS)
@@ -640,6 +659,8 @@
-rm -f *.tab.c
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug345887.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cet_nops_fs.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cet_nops_gs.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/hang.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/seg_override.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sigcontext.Po@am__quote@
diff --git a/none/tests/x86-linux/cet_nops_fs.c b/none/tests/x86-linux/cet_nops_fs.c
new file mode 100644
index 0000000..70645f7
--- /dev/null
+++ b/none/tests/x86-linux/cet_nops_fs.c
@@ -0,0 +1,311 @@
+#include <stdio.h>
+
+int main ()
+{
+ printf("start testing FS prefix ..\n");
+ fflush(stdout);
+
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+
+ printf ("done\n");
+ return 0;
+}
diff --git a/none/tests/x86-linux/cet_nops_fs.stderr.exp b/none/tests/x86-linux/cet_nops_fs.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/x86-linux/cet_nops_fs.stderr.exp
diff --git a/none/tests/x86-linux/cet_nops_fs.stdout.exp b/none/tests/x86-linux/cet_nops_fs.stdout.exp
new file mode 100644
index 0000000..909e188
--- /dev/null
+++ b/none/tests/x86-linux/cet_nops_fs.stdout.exp
@@ -0,0 +1,2 @@
+start testing FS prefix ..
+done
diff --git a/none/tests/x86-linux/cet_nops_fs.vgtest b/none/tests/x86-linux/cet_nops_fs.vgtest
new file mode 100644
index 0000000..8681e9a
--- /dev/null
+++ b/none/tests/x86-linux/cet_nops_fs.vgtest
@@ -0,0 +1,2 @@
+prog: cet_nops_fs
+vgopts: -q
diff --git a/none/tests/x86-linux/cet_nops_gs.c b/none/tests/x86-linux/cet_nops_gs.c
new file mode 100644
index 0000000..c03f02c
--- /dev/null
+++ b/none/tests/x86-linux/cet_nops_gs.c
@@ -0,0 +1,311 @@
+#include <stdio.h>
+
+int main ()
+{
+ printf("start testing GS prefix ..\n");
+ fflush(stdout);
+
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0x0" :::"cc","memory");
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+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
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+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
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+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
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+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
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+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
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+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
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+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
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+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1d, 0xff" :::"cc","memory");
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+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
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+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0xff" :::"cc","memory");
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+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1e, 0x0" :::"cc","memory");
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+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
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+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x65, 0x0f, 0x1f, 0xff" :::"cc","memory");
+
+ printf ("done\n");
+ return 0;
+}
diff --git a/none/tests/x86-linux/cet_nops_gs.stderr.exp b/none/tests/x86-linux/cet_nops_gs.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/x86-linux/cet_nops_gs.stderr.exp
diff --git a/none/tests/x86-linux/cet_nops_gs.stdout.exp b/none/tests/x86-linux/cet_nops_gs.stdout.exp
new file mode 100644
index 0000000..b9673a7
--- /dev/null
+++ b/none/tests/x86-linux/cet_nops_gs.stdout.exp
@@ -0,0 +1,2 @@
+start testing GS prefix ..
+done
diff --git a/none/tests/x86-linux/cet_nops_gs.vgtest b/none/tests/x86-linux/cet_nops_gs.vgtest
new file mode 100644
index 0000000..085e266
--- /dev/null
+++ b/none/tests/x86-linux/cet_nops_gs.vgtest
@@ -0,0 +1,2 @@
+prog: cet_nops_gs
+vgopts: -q
diff --git a/none/tests/x86-solaris/Makefile.am b/none/tests/x86-solaris/Makefile.am
index ee69b23..b81733c 100644
--- a/none/tests/x86-solaris/Makefile.am
+++ b/none/tests/x86-solaris/Makefile.am
@@ -8,6 +8,7 @@
EXTRA_DIST = \
+ cet_nops_fs.stderr.exp cet_nops_fs.stdout.exp cet_nops_fs.vgtest \
coredump_single_thread.post.exp coredump_single_thread.stderr.exp \
coredump_single_thread.stdout.exp coredump_single_thread.vgtest \
coredump_single_thread_sse.post.exp coredump_single_thread_sse.stderr.exp \
@@ -15,6 +16,7 @@
syscalls.stderr.exp syscalls.stdout.exp syscalls.vgtest
check_PROGRAMS = \
+ cet_nops_fs \
coredump_single_thread \
coredump_single_thread_sse \
syscalls
diff --git a/none/tests/x86-solaris/Makefile.in b/none/tests/x86-solaris/Makefile.in
index ac32535..d792ea6 100644
--- a/none/tests/x86-solaris/Makefile.in
+++ b/none/tests/x86-solaris/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -120,7 +120,7 @@
@COMPILER_IS_CLANG_TRUE@ -Wno-uninitialized -Wno-unused-value # \
@COMPILER_IS_CLANG_TRUE@ clang 3.0.0
@COMPILER_IS_CLANG_TRUE@am__append_7 = -Wno-unused-private-field # drd/tests/tsan_unittest.cpp
-check_PROGRAMS = coredump_single_thread$(EXEEXT) \
+check_PROGRAMS = cet_nops_fs$(EXEEXT) coredump_single_thread$(EXEEXT) \
coredump_single_thread_sse$(EXEEXT) syscalls$(EXEEXT)
subdir = none/tests/x86-solaris
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
@@ -133,6 +133,9 @@
CONFIG_HEADER = $(top_builddir)/config.h
CONFIG_CLEAN_FILES =
CONFIG_CLEAN_VPATH_FILES =
+cet_nops_fs_SOURCES = cet_nops_fs.c
+cet_nops_fs_OBJECTS = cet_nops_fs.$(OBJEXT)
+cet_nops_fs_LDADD = $(LDADD)
coredump_single_thread_SOURCES = coredump_single_thread.c
coredump_single_thread_OBJECTS = coredump_single_thread.$(OBJEXT)
coredump_single_thread_LDADD = $(LDADD)
@@ -172,10 +175,10 @@
am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@)
am__v_CCLD_0 = @echo " CCLD " $@;
am__v_CCLD_1 =
-SOURCES = coredump_single_thread.c coredump_single_thread_sse.c \
- syscalls.c
-DIST_SOURCES = coredump_single_thread.c coredump_single_thread_sse.c \
- syscalls.c
+SOURCES = cet_nops_fs.c coredump_single_thread.c \
+ coredump_single_thread_sse.c syscalls.c
+DIST_SOURCES = cet_nops_fs.c coredump_single_thread.c \
+ coredump_single_thread_sse.c syscalls.c
am__can_run_installinfo = \
case $$AM_UPDATE_INFO_DIR in \
n|no|NO) false;; \
@@ -247,6 +250,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -417,6 +421,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -427,6 +432,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -501,8 +507,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -547,7 +551,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
@@ -575,6 +578,7 @@
filter_stderr
EXTRA_DIST = \
+ cet_nops_fs.stderr.exp cet_nops_fs.stdout.exp cet_nops_fs.vgtest \
coredump_single_thread.post.exp coredump_single_thread.stderr.exp \
coredump_single_thread.stdout.exp coredump_single_thread.vgtest \
coredump_single_thread_sse.post.exp coredump_single_thread_sse.stderr.exp \
@@ -619,6 +623,10 @@
clean-checkPROGRAMS:
-test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+cet_nops_fs$(EXEEXT): $(cet_nops_fs_OBJECTS) $(cet_nops_fs_DEPENDENCIES) $(EXTRA_cet_nops_fs_DEPENDENCIES)
+ @rm -f cet_nops_fs$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(cet_nops_fs_OBJECTS) $(cet_nops_fs_LDADD) $(LIBS)
+
coredump_single_thread$(EXEEXT): $(coredump_single_thread_OBJECTS) $(coredump_single_thread_DEPENDENCIES) $(EXTRA_coredump_single_thread_DEPENDENCIES)
@rm -f coredump_single_thread$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(coredump_single_thread_OBJECTS) $(coredump_single_thread_LDADD) $(LIBS)
@@ -637,6 +645,7 @@
distclean-compile:
-rm -f *.tab.c
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cet_nops_fs.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coredump_single_thread.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coredump_single_thread_sse.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/syscalls.Po@am__quote@
diff --git a/none/tests/x86-solaris/cet_nops_fs.c b/none/tests/x86-solaris/cet_nops_fs.c
new file mode 100644
index 0000000..70645f7
--- /dev/null
+++ b/none/tests/x86-solaris/cet_nops_fs.c
@@ -0,0 +1,311 @@
+#include <stdio.h>
+
+int main ()
+{
+ printf("start testing FS prefix ..\n");
+ fflush(stdout);
+
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x64, 0x0f, 0x1f, 0xff" :::"cc","memory");
+
+ printf ("done\n");
+ return 0;
+}
diff --git a/none/tests/x86-solaris/cet_nops_fs.stderr.exp b/none/tests/x86-solaris/cet_nops_fs.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/x86-solaris/cet_nops_fs.stderr.exp
diff --git a/none/tests/x86-solaris/cet_nops_fs.stdout.exp b/none/tests/x86-solaris/cet_nops_fs.stdout.exp
new file mode 100644
index 0000000..909e188
--- /dev/null
+++ b/none/tests/x86-solaris/cet_nops_fs.stdout.exp
@@ -0,0 +1,2 @@
+start testing FS prefix ..
+done
diff --git a/none/tests/x86-solaris/cet_nops_fs.vgtest b/none/tests/x86-solaris/cet_nops_fs.vgtest
new file mode 100644
index 0000000..8681e9a
--- /dev/null
+++ b/none/tests/x86-solaris/cet_nops_fs.vgtest
@@ -0,0 +1,2 @@
+prog: cet_nops_fs
+vgopts: -q
diff --git a/none/tests/x86/Makefile.am b/none/tests/x86/Makefile.am
index 2b35cd9..bc9615e 100644
--- a/none/tests/x86/Makefile.am
+++ b/none/tests/x86/Makefile.am
@@ -43,6 +43,7 @@
bug135421-x86.stderr.exp bug135421-x86.stdout.exp bug135421-x86.vgtest \
bug137714-x86.stderr.exp bug137714-x86.stdout.exp bug137714-x86.vgtest \
bug152818-x86.stderr.exp bug152818-x86.stdout.exp bug152818-x86.vgtest \
+ cet_nops.stderr.exp cet_nops.stdout.exp cet_nops.vgtest \
cmpxchg8b.stderr.exp cmpxchg8b.stdout.exp cmpxchg8b.vgtest \
cpuid.stderr.exp cpuid.stdout.exp cpuid.vgtest \
cse_fail.stderr.exp cse_fail.stdout.exp cse_fail.vgtest \
@@ -92,6 +93,7 @@
bug135421-x86 \
bug137714-x86 \
bug152818-x86 \
+ cet_nops \
cmpxchg8b \
cpuid \
cse_fail \
diff --git a/none/tests/x86/Makefile.in b/none/tests/x86/Makefile.in
index fa4f777..847a5c8 100644
--- a/none/tests/x86/Makefile.in
+++ b/none/tests/x86/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -132,14 +132,15 @@
bug125959-x86$(EXEEXT) bug126147-x86$(EXEEXT) \
bug132813-x86$(EXEEXT) bug135421-x86$(EXEEXT) \
bug137714-x86$(EXEEXT) bug152818-x86$(EXEEXT) \
- cmpxchg8b$(EXEEXT) cpuid$(EXEEXT) cse_fail$(EXEEXT) \
- fcmovnu$(EXEEXT) fpu_lazy_eflags$(EXEEXT) fxtract$(EXEEXT) \
- getseg$(EXEEXT) incdec_alt$(EXEEXT) $(am__EXEEXT_5) \
- int$(EXEEXT) jcxz$(EXEEXT) lahf$(EXEEXT) looper$(EXEEXT) \
- movx$(EXEEXT) sbbmisc$(EXEEXT) shift_ndep$(EXEEXT) \
- smc1$(EXEEXT) x86locked$(EXEEXT) x87trigOOR$(EXEEXT) \
- yield$(EXEEXT) xadd$(EXEEXT) $(am__EXEEXT_6) $(am__EXEEXT_7) \
- $(am__EXEEXT_8) $(am__EXEEXT_9) $(am__EXEEXT_10)
+ cet_nops$(EXEEXT) cmpxchg8b$(EXEEXT) cpuid$(EXEEXT) \
+ cse_fail$(EXEEXT) fcmovnu$(EXEEXT) fpu_lazy_eflags$(EXEEXT) \
+ fxtract$(EXEEXT) getseg$(EXEEXT) incdec_alt$(EXEEXT) \
+ $(am__EXEEXT_5) int$(EXEEXT) jcxz$(EXEEXT) lahf$(EXEEXT) \
+ looper$(EXEEXT) movx$(EXEEXT) sbbmisc$(EXEEXT) \
+ shift_ndep$(EXEEXT) smc1$(EXEEXT) x86locked$(EXEEXT) \
+ x87trigOOR$(EXEEXT) yield$(EXEEXT) xadd$(EXEEXT) \
+ $(am__EXEEXT_6) $(am__EXEEXT_7) $(am__EXEEXT_8) \
+ $(am__EXEEXT_9) $(am__EXEEXT_10)
@BUILD_SSSE3_TESTS_TRUE@am__append_12 = ssse3_misaligned
@BUILD_LZCNT_TESTS_TRUE@am__append_13 = lzcnt32
@BUILD_MOVBE_TESTS_TRUE@am__append_14 = movbe
@@ -215,6 +216,9 @@
bug152818_x86_SOURCES = bug152818-x86.c
bug152818_x86_OBJECTS = bug152818-x86.$(OBJEXT)
bug152818_x86_LDADD = $(LDADD)
+cet_nops_SOURCES = cet_nops.c
+cet_nops_OBJECTS = cet_nops.$(OBJEXT)
+cet_nops_LDADD = $(LDADD)
cmpxchg8b_SOURCES = cmpxchg8b.c
cmpxchg8b_OBJECTS = cmpxchg8b.$(OBJEXT)
cmpxchg8b_LDADD = $(LDADD)
@@ -364,9 +368,9 @@
am__v_CCLD_1 =
SOURCES = aad_aam.c allexec.c badseg.c bt_everything.c bt_literal.c \
bug125959-x86.c bug126147-x86.c bug132813-x86.c \
- bug135421-x86.c bug137714-x86.c bug152818-x86.c cmpxchg8b.c \
- $(cpuid_SOURCES) cse_fail.c faultstatus.c fcmovnu.c \
- fpu_lazy_eflags.c fxtract.c getseg.c incdec_alt.c \
+ bug135421-x86.c bug137714-x86.c bug152818-x86.c cet_nops.c \
+ cmpxchg8b.c $(cpuid_SOURCES) cse_fail.c faultstatus.c \
+ fcmovnu.c fpu_lazy_eflags.c fxtract.c getseg.c incdec_alt.c \
$(insn_basic_SOURCES) $(insn_cmov_SOURCES) $(insn_fpu_SOURCES) \
$(insn_mmx_SOURCES) $(insn_mmxext_SOURCES) $(insn_sse_SOURCES) \
$(insn_sse2_SOURCES) $(insn_sse3_SOURCES) \
@@ -375,9 +379,9 @@
ssse3_misaligned.c x86locked.c x87trigOOR.c xadd.c yield.c
DIST_SOURCES = aad_aam.c allexec.c badseg.c bt_everything.c \
bt_literal.c bug125959-x86.c bug126147-x86.c bug132813-x86.c \
- bug135421-x86.c bug137714-x86.c bug152818-x86.c cmpxchg8b.c \
- $(cpuid_SOURCES) cse_fail.c faultstatus.c fcmovnu.c \
- fpu_lazy_eflags.c fxtract.c getseg.c incdec_alt.c \
+ bug135421-x86.c bug137714-x86.c bug152818-x86.c cet_nops.c \
+ cmpxchg8b.c $(cpuid_SOURCES) cse_fail.c faultstatus.c \
+ fcmovnu.c fpu_lazy_eflags.c fxtract.c getseg.c incdec_alt.c \
$(insn_basic_SOURCES) $(insn_cmov_SOURCES) $(insn_fpu_SOURCES) \
$(insn_mmx_SOURCES) $(insn_mmxext_SOURCES) $(insn_sse_SOURCES) \
$(insn_sse2_SOURCES) $(insn_sse3_SOURCES) \
@@ -455,6 +459,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -625,6 +630,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -635,6 +641,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -709,8 +716,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -755,7 +760,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
@@ -798,6 +802,7 @@
bug135421-x86.stderr.exp bug135421-x86.stdout.exp bug135421-x86.vgtest \
bug137714-x86.stderr.exp bug137714-x86.stdout.exp bug137714-x86.vgtest \
bug152818-x86.stderr.exp bug152818-x86.stdout.exp bug152818-x86.vgtest \
+ cet_nops.stderr.exp cet_nops.stdout.exp cet_nops.vgtest \
cmpxchg8b.stderr.exp cmpxchg8b.stdout.exp cmpxchg8b.vgtest \
cpuid.stderr.exp cpuid.stdout.exp cpuid.vgtest \
cse_fail.stderr.exp cse_fail.stdout.exp cse_fail.vgtest \
@@ -943,6 +948,10 @@
@rm -f bug152818-x86$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(bug152818_x86_OBJECTS) $(bug152818_x86_LDADD) $(LIBS)
+cet_nops$(EXEEXT): $(cet_nops_OBJECTS) $(cet_nops_DEPENDENCIES) $(EXTRA_cet_nops_DEPENDENCIES)
+ @rm -f cet_nops$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(cet_nops_OBJECTS) $(cet_nops_LDADD) $(LIBS)
+
cmpxchg8b$(EXEEXT): $(cmpxchg8b_OBJECTS) $(cmpxchg8b_DEPENDENCIES) $(EXTRA_cmpxchg8b_DEPENDENCIES)
@rm -f cmpxchg8b$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(cmpxchg8b_OBJECTS) $(cmpxchg8b_LDADD) $(LIBS)
@@ -1096,6 +1105,7 @@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug135421-x86.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug137714-x86.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug152818-x86.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cet_nops.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cmpxchg8b.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpuid_c.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpuid_s.Po@am__quote@
diff --git a/none/tests/x86/cet_nops.c b/none/tests/x86/cet_nops.c
new file mode 100644
index 0000000..7f1644e
--- /dev/null
+++ b/none/tests/x86/cet_nops.c
@@ -0,0 +1,1511 @@
+#include <stdio.h>
+
+int main ()
+{
+ printf("start doing absolutely nothing without fs and gs prefixes ..\n");
+ fflush(stdout);
+__asm__ __volatile__ (".byte 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x19, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x19, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x19, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x19, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x19, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x19, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x19, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x19, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x19, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1d, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1d, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1d, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1d, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1d, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1d, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1d, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1d, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1d, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1e, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1f, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1f, 0x40, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1f, 0x44, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1f, 0x5A, 0x22" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1f, 0x9C, 0x1D, 0x11, 0x22, 0x33, 0x44" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1f, 0x04, 0x60" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x2e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x2e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x2e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x2e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x2e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x2e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x36, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x36, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x36, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x36, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x36, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x36, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x3e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x3e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x3e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x3e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x3e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x3e, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x26, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0x66, 0x26, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x26, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x26, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf2, 0x66, 0x26, 0x0f, 0x1f, 0xff" :::"cc","memory");
+__asm__ __volatile__ (".byte 0xf3, 0x66, 0x26, 0x0f, 0x1f, 0xff" :::"cc","memory");
+
+ printf ("done\n");
+ return 0;
+}
diff --git a/none/tests/x86/cet_nops.stderr.exp b/none/tests/x86/cet_nops.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/x86/cet_nops.stderr.exp
diff --git a/none/tests/x86/cet_nops.stdout.exp b/none/tests/x86/cet_nops.stdout.exp
new file mode 100644
index 0000000..7186474
--- /dev/null
+++ b/none/tests/x86/cet_nops.stdout.exp
@@ -0,0 +1,2 @@
+start doing absolutely nothing without fs and gs prefixes ..
+done
diff --git a/none/tests/x86/cet_nops.vgtest b/none/tests/x86/cet_nops.vgtest
new file mode 100644
index 0000000..025eefe
--- /dev/null
+++ b/none/tests/x86/cet_nops.vgtest
@@ -0,0 +1,2 @@
+prog: cet_nops
+vgopts: -q
diff --git a/none/tests/x86/shift_ndep.c b/none/tests/x86/shift_ndep.c
index 7fc34c9..10f0a8d 100644
--- a/none/tests/x86/shift_ndep.c
+++ b/none/tests/x86/shift_ndep.c
@@ -18,7 +18,7 @@
expected final value for x is -2 + 1 + 1 = 0.
If instead the shift clears CC_NDEP (as it would legally do if
- the shift amount were non-zero), this will be interpeted as
+ the shift amount were non-zero), this will be interpreted as
clearing the carry bit, so the adc will be a no-op and the final
value of %x will instead be -1.
*/
diff --git a/perf/Makefile.in b/perf/Makefile.in
index 5655e0e..2643acc 100644
--- a/perf/Makefile.in
+++ b/perf/Makefile.in
@@ -111,7 +111,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -281,6 +281,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -451,6 +452,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -461,6 +463,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -535,8 +538,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -581,7 +582,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
diff --git a/perf/bigcode.c b/perf/bigcode.c
index ae31cbb..02e069d 100644
--- a/perf/bigcode.c
+++ b/perf/bigcode.c
@@ -28,8 +28,6 @@
#if defined(__mips__)
#include <asm/cachectl.h>
#include <sys/syscall.h>
-#elif defined(__tilegx__)
-#include <asm/cachectl.h>
#endif
#include "tests/sys_mman.h"
@@ -75,7 +73,7 @@
printf("%d copies of f(), %d reps\n", n_fns, n_reps);
char* a = mmap(0, FN_SIZE * n_fns,
- PROT_EXEC|PROT_WRITE,
+ PROT_EXEC|PROT_WRITE|PROT_READ,
MAP_PRIVATE|MAP_ANONYMOUS, -1,0);
assert(a != (char*)MAP_FAILED);
@@ -87,8 +85,6 @@
#if defined(__mips__)
syscall(__NR_cacheflush, a, FN_SIZE * n_fns, ICACHE);
-#elif defined(__tilegx__)
- cacheflush(a, FN_SIZE * n_fns, ICACHE);
#endif
for (h = 0; h < n_reps; h += 1) {
diff --git a/perf/memrw.c b/perf/memrw.c
index 10b9598..10b909c 100644
--- a/perf/memrw.c
+++ b/perf/memrw.c
@@ -26,7 +26,7 @@
static int nr_thr; // nr of threads (hardcoded to 1 currently)
static int nr_repeat; // nr of times we will allocate, use, then free total+ws
-// Note: the total nr of MB is what is explicitely allocated.
+// Note: the total nr of MB is what is explicitly allocated.
// On top of that, we have the stacks, local vars, lib vars, ...
// The working set is just the first nr_b_ws blocks of nr_b.
diff --git a/perf/tinycc.c b/perf/tinycc.c
index 0652d1a..ff757a0 100644
--- a/perf/tinycc.c
+++ b/perf/tinycc.c
@@ -2309,7 +2309,7 @@
static int ch, tok;
static CValue tokc;
static CString tokcstr; /* current parsed string, if any */
-/* additional informations about token */
+/* additional information about token */
static int tok_flags;
#define TOK_FLAG_BOL 0x0001 /* beginning of line before */
#define TOK_FLAG_BOF 0x0002 /* beginning of file before */
@@ -2435,7 +2435,7 @@
Section *plt;
unsigned long *got_offsets;
int nb_got_offsets;
- /* give the correspondance from symtab indexes to dynsym indexes */
+ /* give the correspondence from symtab indexes to dynsym indexes */
int *symtab_to_dynsym;
/* temporary dynamic symbol sections (for dll loading) */
@@ -5508,7 +5508,7 @@
#define MAX_ASM_OPERANDS 30
typedef struct ASMOperand {
- int id; /* GCC 3 optionnal identifier (0 if number only supported */
+ int id; /* GCC 3 optional identifier (0 if number only supported */
char *constraint;
char asm_str[16]; /* computed asm string for operand */
SValue *vt; /* C value of the expression */
@@ -10846,7 +10846,7 @@
c = (int)vtop->c.i;
/* constant: simpler */
/* NOTE: all comments are for SHL. the other cases are
- done by swaping words */
+ done by swapping words */
vpop();
if (op != TOK_SHL)
vswap();
@@ -11821,7 +11821,7 @@
goto type_ok;
}
type1 = pointed_type(dt);
- /* a function is implicitely a function pointer */
+ /* a function is implicitly a function pointer */
if (sbt == VT_FUNC) {
if ((type1->t & VT_BTYPE) != VT_VOID &&
!is_compatible_types(pointed_type(dt), st))
@@ -18803,7 +18803,7 @@
}
/* put a got entry corresponding to a symbol in symtab_section. 'size'
- and 'info' can be modifed if more precise info comes from the DLL */
+ and 'info' can be modified if more precise info comes from the DLL */
static void put_got_entry(TCCState *s1,
int reloc_type, unsigned long size, int info,
int sym_index)
@@ -19579,7 +19579,7 @@
}
}
- /* if interpreter, then add corresponing program header */
+ /* if interpreter, then add corresponding program header */
if (interp) {
ph = &phdr[0];
@@ -19593,7 +19593,7 @@
ph->p_align = interp->sh_addralign;
}
- /* if dynamic section, then add corresponing program header */
+ /* if dynamic section, then add corresponding program header */
if (dynamic) {
Elf32_Sym *sym_end;
@@ -21285,7 +21285,7 @@
void help(void)
{
- printf("tcc version " TCC_VERSION " - Tiny C Compiler - Copyright (C) 2001-2015 Fabrice Bellard\n"
+ printf("tcc version " TCC_VERSION " - Tiny C Compiler - Copyright (C) 2001-2017 Fabrice Bellard\n"
"usage: tcc [-v] [-c] [-o outfile] [-Bdir] [-bench] [-Idir] [-Dsym[=val]] [-Usym]\n"
" [-Wwarn] [-g] [-b] [-bt N] [-Ldir] [-llib] [-shared] [-static]\n"
" [infile1 infile2...] [-run infile args...]\n"
diff --git a/perf/vg_perf b/perf/vg_perf
index 28f6156..773c008 100644
--- a/perf/vg_perf
+++ b/perf/vg_perf
@@ -6,7 +6,7 @@
# This file is part of Valgrind, a dynamic binary instrumentation
# framework.
#
-# Copyright (C) 2005-2015 Nicholas Nethercote
+# Copyright (C) 2005-2017 Nicholas Nethercote
# njn@valgrind.org
#
# This program is free software; you can redistribute it and/or
@@ -71,7 +71,9 @@
--outer-valgrind: run these Valgrind(s) under the given outer valgrind.
These Valgrind(s) must be configured with --enable-inner.
--outer-tool: tool to use by the outer valgrind (default cachegrind).
- --outer-args: use this as outer tool args.
+ --outer-args: use this as outer tool args. If the outer args are starting
+ with +, the given outer args are appended to the outer args predefined
+ by vg_perf.
Any tools named in --tools must be present in all directories specified
with --vg. (This is not checked.)
@@ -321,7 +323,7 @@
$tool_abbrev =~ s/(..).*/$1/;
printf(" %s:", $tool_abbrev);
my $run_outer_args = "";
- if (not defined $outer_args) {
+ if ((not defined $outer_args) || ($outer_args =~ /^\+/)) {
$run_outer_args =
" -v --command-line-only=yes"
. " --run-libc-freeres=no --sim-hints=enable-outer"
@@ -335,6 +337,10 @@
. " --callgrind:dump-instr=yes --callgrind:collect-jumps=yes"
. " --callgrind:callgrind-out-file=callgrind.out.$vgdirname.$tool_abbrev.$name.%p"
. " ";
+ if (defined $outer_args) {
+ $outer_args =~ s/^\+(.*)/$1/;
+ $run_outer_args = $run_outer_args . $outer_args;
+ }
} else {
$run_outer_args = $outer_args;
}
@@ -351,8 +357,8 @@
$vgsetup = "VALGRIND_LIB_INNER=$vgdir/.in_place ";
$vgcmd = "$outer_valgrind "
. "--tool=" . $outer_tool . " "
- . "$run_outer_args "
. "--log-file=" . "$outer_tool.outer.log.$vgdirname.$tool_abbrev.$name.%p "
+ . "$run_outer_args "
. $vgcmd;
} else {
# Set both VALGRIND_LIB and VALGRIND_LIB_INNER
diff --git a/perf/vg_perf.in b/perf/vg_perf.in
index 7a80cb0..727857f 100644
--- a/perf/vg_perf.in
+++ b/perf/vg_perf.in
@@ -6,7 +6,7 @@
# This file is part of Valgrind, a dynamic binary instrumentation
# framework.
#
-# Copyright (C) 2005-2015 Nicholas Nethercote
+# Copyright (C) 2005-2017 Nicholas Nethercote
# njn@valgrind.org
#
# This program is free software; you can redistribute it and/or
@@ -71,7 +71,9 @@
--outer-valgrind: run these Valgrind(s) under the given outer valgrind.
These Valgrind(s) must be configured with --enable-inner.
--outer-tool: tool to use by the outer valgrind (default cachegrind).
- --outer-args: use this as outer tool args.
+ --outer-args: use this as outer tool args. If the outer args are starting
+ with +, the given outer args are appended to the outer args predefined
+ by vg_perf.
Any tools named in --tools must be present in all directories specified
with --vg. (This is not checked.)
@@ -321,7 +323,7 @@
$tool_abbrev =~ s/(..).*/$1/;
printf(" %s:", $tool_abbrev);
my $run_outer_args = "";
- if (not defined $outer_args) {
+ if ((not defined $outer_args) || ($outer_args =~ /^\+/)) {
$run_outer_args =
" -v --command-line-only=yes"
. " --run-libc-freeres=no --sim-hints=enable-outer"
@@ -335,6 +337,10 @@
. " --callgrind:dump-instr=yes --callgrind:collect-jumps=yes"
. " --callgrind:callgrind-out-file=callgrind.out.$vgdirname.$tool_abbrev.$name.%p"
. " ";
+ if (defined $outer_args) {
+ $outer_args =~ s/^\+(.*)/$1/;
+ $run_outer_args = $run_outer_args . $outer_args;
+ }
} else {
$run_outer_args = $outer_args;
}
@@ -351,8 +357,8 @@
$vgsetup = "VALGRIND_LIB_INNER=$vgdir/.in_place ";
$vgcmd = "$outer_valgrind "
. "--tool=" . $outer_tool . " "
- . "$run_outer_args "
. "--log-file=" . "$outer_tool.outer.log.$vgdirname.$tool_abbrev.$name.%p "
+ . "$run_outer_args "
. $vgcmd;
} else {
# Set both VALGRIND_LIB and VALGRIND_LIB_INNER
diff --git a/shared/Makefile.in b/shared/Makefile.in
index 505e6b7..27892f9 100644
--- a/shared/Makefile.in
+++ b/shared/Makefile.in
@@ -163,6 +163,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
diff --git a/shared/vg_replace_strmem.c b/shared/vg_replace_strmem.c
index f3be419..f2875fc 100644
--- a/shared/vg_replace_strmem.c
+++ b/shared/vg_replace_strmem.c
@@ -8,7 +8,7 @@
/*
This file is part of Valgrind.
- Copyright (C) 2000-2015 Julian Seward
+ Copyright (C) 2000-2017 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -254,6 +254,10 @@
STRCHR(VG_Z_LD_LINUX_X86_64_SO_2, index)
# endif
+#if defined(VGPV_mips32_linux_android)
+ STRCHR(NONE, __dl_strchr)
+#endif
+
#elif defined(VGO_darwin)
STRCHR(VG_Z_LIBC_SONAME, strchr)
# if DARWIN_VERS == DARWIN_10_9
@@ -1040,6 +1044,7 @@
#elif defined(VGO_solaris)
MEMCPY(VG_Z_LIBC_SONAME, memcpy)
+ MEMCPY(VG_Z_LIBC_SONAME, memcpyZPZa)
MEMCPY(VG_Z_LD_SO_1, memcpy)
#endif
@@ -1187,9 +1192,9 @@
pointless. */
#define MEMSET(soname, fnname) \
- void* VG_REPLACE_FUNCTION_EZU(20210,soname,fnname) \
+ void* VG_REPLACE_FUNCTION_EZZ(20210,soname,fnname) \
(void *s, Int c, SizeT n); \
- void* VG_REPLACE_FUNCTION_EZU(20210,soname,fnname) \
+ void* VG_REPLACE_FUNCTION_EZZ(20210,soname,fnname) \
(void *s, Int c, SizeT n) \
{ \
if (sizeof(void*) == 8) { \
@@ -1240,6 +1245,7 @@
#elif defined(VGO_solaris)
MEMSET(VG_Z_LIBC_SONAME, memset)
+ MEMSET(VG_Z_LIBC_SONAME, memsetZPZa)
#endif
@@ -1269,6 +1275,7 @@
#elif defined(VGO_solaris)
MEMMOVE(VG_Z_LIBC_SONAME, memmove)
+ MEMMOVE(VG_Z_LIBC_SONAME, memmoveZPZa)
MEMMOVE(VG_Z_LD_SO_1, memmove)
#endif
@@ -1714,6 +1721,7 @@
#if defined(VGO_linux)
STRCSPN(VG_Z_LIBC_SONAME, strcspn)
+ STRCSPN(VG_Z_LIBC_SONAME, __GI_strcspn)
#elif defined(VGO_darwin)
diff --git a/solaris/Makefile.in b/solaris/Makefile.in
index 699a823..3b1d8ba 100644
--- a/solaris/Makefile.in
+++ b/solaris/Makefile.in
@@ -169,6 +169,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
diff --git a/tests/Makefile.am b/tests/Makefile.am
index 9c0cc3a..7233626 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -44,6 +44,7 @@
check_PROGRAMS = \
arch_test \
os_test \
+ libc_test \
true \
x86_amd64_features \
s390x_features \
diff --git a/tests/Makefile.in b/tests/Makefile.in
index f9c4bdb..3f7ef4d 100644
--- a/tests/Makefile.in
+++ b/tests/Makefile.in
@@ -112,7 +112,7 @@
# Make sure that all test programs have threaded errno.
-# Disable largefile support as there are test cases explictly enabling it.
+# Disable largefile support as there are test cases explicitly enabling it.
@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
@@ -121,10 +121,11 @@
@COMPILER_IS_CLANG_TRUE@ -Wno-uninitialized -Wno-unused-value # \
@COMPILER_IS_CLANG_TRUE@ clang 3.0.0
@COMPILER_IS_CLANG_TRUE@am__append_7 = -Wno-unused-private-field # drd/tests/tsan_unittest.cpp
-check_PROGRAMS = arch_test$(EXEEXT) os_test$(EXEEXT) true$(EXEEXT) \
- x86_amd64_features$(EXEEXT) s390x_features$(EXEEXT) \
- mips_features$(EXEEXT) power_insn_available$(EXEEXT) \
- is_ppc64_BE$(EXEEXT) min_power_isa$(EXEEXT)
+check_PROGRAMS = arch_test$(EXEEXT) os_test$(EXEEXT) \
+ libc_test$(EXEEXT) true$(EXEEXT) x86_amd64_features$(EXEEXT) \
+ s390x_features$(EXEEXT) mips_features$(EXEEXT) \
+ power_insn_available$(EXEEXT) is_ppc64_BE$(EXEEXT) \
+ min_power_isa$(EXEEXT)
subdir = tests
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/configure.ac
@@ -142,6 +143,9 @@
is_ppc64_BE_SOURCES = is_ppc64_BE.c
is_ppc64_BE_OBJECTS = is_ppc64_BE.$(OBJEXT)
is_ppc64_BE_LDADD = $(LDADD)
+libc_test_SOURCES = libc_test.c
+libc_test_OBJECTS = libc_test.$(OBJEXT)
+libc_test_LDADD = $(LDADD)
min_power_isa_SOURCES = min_power_isa.c
min_power_isa_OBJECTS = min_power_isa-min_power_isa.$(OBJEXT)
min_power_isa_LDADD = $(LDADD)
@@ -201,10 +205,10 @@
am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@)
am__v_CCLD_0 = @echo " CCLD " $@;
am__v_CCLD_1 =
-SOURCES = arch_test.c is_ppc64_BE.c min_power_isa.c mips_features.c \
- os_test.c power_insn_available.c s390x_features.c true.c \
- x86_amd64_features.c
-DIST_SOURCES = arch_test.c is_ppc64_BE.c min_power_isa.c \
+SOURCES = arch_test.c is_ppc64_BE.c libc_test.c min_power_isa.c \
+ mips_features.c os_test.c power_insn_available.c \
+ s390x_features.c true.c x86_amd64_features.c
+DIST_SOURCES = arch_test.c is_ppc64_BE.c libc_test.c min_power_isa.c \
mips_features.c os_test.c power_insn_available.c \
s390x_features.c true.c x86_amd64_features.c
am__can_run_installinfo = \
@@ -280,6 +284,7 @@
FLAG_MMMX = @FLAG_MMMX@
FLAG_MSSE = @FLAG_MSSE@
FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_NO_PIE = @FLAG_NO_PIE@
FLAG_OCTEON = @FLAG_OCTEON@
FLAG_OCTEON2 = @FLAG_OCTEON2@
FLAG_T_TEXT = @FLAG_T_TEXT@
@@ -450,6 +455,7 @@
AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
-I$(top_srcdir) \
-I$(top_srcdir)/include \
+ -I$(top_builddir)/include \
-I$(top_srcdir)/VEX/pub \
-I$(top_builddir)/VEX/pub \
-DVGA_@VGCONF_ARCH_PRI@=1 \
@@ -460,6 +466,7 @@
@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
@@ -534,8 +541,6 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
-AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
-AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
$(AM_CFLAGS_BASE) -fomit-frame-pointer \
@@ -580,7 +585,6 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
@@ -681,6 +685,10 @@
@rm -f is_ppc64_BE$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(is_ppc64_BE_OBJECTS) $(is_ppc64_BE_LDADD) $(LIBS)
+libc_test$(EXEEXT): $(libc_test_OBJECTS) $(libc_test_DEPENDENCIES) $(EXTRA_libc_test_DEPENDENCIES)
+ @rm -f libc_test$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(libc_test_OBJECTS) $(libc_test_LDADD) $(LIBS)
+
min_power_isa$(EXEEXT): $(min_power_isa_OBJECTS) $(min_power_isa_DEPENDENCIES) $(EXTRA_min_power_isa_DEPENDENCIES)
@rm -f min_power_isa$(EXEEXT)
$(AM_V_CCLD)$(min_power_isa_LINK) $(min_power_isa_OBJECTS) $(min_power_isa_LDADD) $(LIBS)
@@ -717,6 +725,7 @@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arch_test.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is_ppc64_BE.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libc_test.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/min_power_isa-min_power_isa.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mips_features.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/os_test.Po@am__quote@
diff --git a/tests/arch_test.c b/tests/arch_test.c
index d83f0e5..1c90dac 100644
--- a/tests/arch_test.c
+++ b/tests/arch_test.c
@@ -33,7 +33,6 @@
"s390x",
"mips32",
"mips64",
- "tilegx",
NULL
};
@@ -77,9 +76,6 @@
#elif defined(VGP_mips64_linux)
if ( 0 == strcmp( arch, "mips64" ) ) return True;
-#elif defined(VGP_tilegx_linux)
- if ( 0 == strcmp( arch, "tilegx" ) ) return True;
-
#else
# error Unknown platform
#endif // VGP_*
diff --git a/tests/libc_test.c b/tests/libc_test.c
new file mode 100644
index 0000000..7a6c70c
--- /dev/null
+++ b/tests/libc_test.c
@@ -0,0 +1,78 @@
+// Compare given libc name and version number to system name and version.
+
+// Returns
+// - 0 if the libc name matches is at least the minimum version (if given).
+// - 1 if the libc name doesn't match or the version is lower than requested.
+// - 2 if the requested libc name isn't recognised.
+// - 3 if there was a usage error (it also prints an error message).
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#ifdef __GLIBC__
+#include <gnu/libc-version.h>
+#endif
+
+#define False 0
+#define True 1
+typedef int Bool;
+
+/* Assumes the versions are x.y.z, with y and z optional. */
+static __attribute__((unused)) Bool matches_version(char *min_version) {
+ int a1=0, a2=0, a3=0, g1=0, g2=0, g3=0; // 'a' = actual; 'g' = given
+ const char *aversion;
+
+ if (min_version == NULL) return True; // no version specified
+
+ // get actual version number
+#ifdef __GLIBC__
+ aversion = gnu_get_libc_version();
+#else
+ aversion = "unknown";
+#endif
+ // We expect at least one number.
+ if (sscanf(aversion, "%d.%d.%d", &a1, &a2, &a3) < 1) return False;
+
+ // parse given version number.
+ if (sscanf(min_version, "%d.%d.%d", &g1, &g2, &g3) < 1) return False;
+
+ if (a1 > g1) return True;
+ if (a1 < g1) return False;
+ if (a2 > g2) return True;
+ if (a2 < g2) return False;
+ if (a3 >= g3) return True;
+
+ return False;
+}
+
+static Bool go(char* libc, char *min_version)
+{
+#ifdef __GLIBC__
+ if ( 0 == strcmp( libc, "glibc" )
+ && matches_version( min_version ))
+ return True;
+#endif
+
+ return False;
+}
+
+//---------------------------------------------------------------------------
+// main
+//---------------------------------------------------------------------------
+int main(int argc, char **argv)
+{
+ if ( argc < 2 ) {
+ fprintf( stderr, "usage: libc_test <libc-name> [<min-version>]\n" );
+ exit(3); // Usage error.
+ }
+ if (go( argv[1], argv[2] )) {
+ return 0; // Matched.
+ }
+
+ if ( 0 == strcmp ( argv[1], "glibc" ) ) {
+ return 1; // Requested libc name known, but this isn't it.
+ // Or it wasn't the minimum requested version.
+ }
+ return 2; // Didn't match any known libc name.
+}
diff --git a/tests/vg_regtest b/tests/vg_regtest
index fd9ce23..87c98a5 100644
--- a/tests/vg_regtest
+++ b/tests/vg_regtest
@@ -6,7 +6,7 @@
# This file is part of Valgrind, a dynamic binary instrumentation
# framework.
#
-# Copyright (C) 2003-2015 Nicholas Nethercote
+# Copyright (C) 2003-2017 Nicholas Nethercote
# njn@valgrind.org
#
# This program is free software; you can redistribute it and/or
@@ -43,7 +43,9 @@
# --outer-valgrind: run this valgrind under the given outer valgrind.
# This valgrind must be configured with --enable-inner.
# --outer-tool: tool to use by the outer valgrind (default memcheck).
-# --outer-args: use this as outer tool args.
+# --outer-args: use this as outer tool args. If the outer args are starting
+# with +, the given outer args are appended to the outer args predefined
+# by vg_regtest.
# --loop-till-fail: loops on the test(s) till one fail, then exit
# This is useful to obtain detailed trace or --keep-unfiltered
# output of a non deterministic test failure
@@ -182,6 +184,7 @@
my $outer_valgrind;
my $outer_tool = "memcheck";
my $outer_args;
+my $run_outer_args = "";
my $valgrind_lib = "$tests_dir/.in_place";
my $keepunfiltered = 0;
@@ -255,8 +258,8 @@
if (defined $outer_valgrind) {
$outer_valgrind = validate_program($tests_dir, $outer_valgrind, 1, 1);
- if (not defined $outer_args) {
- $outer_args =
+ if ((not defined $outer_args) || ($outer_args =~ /^\+/)) {
+ $run_outer_args =
" --command-line-only=yes"
. " --run-libc-freeres=no --sim-hints=enable-outer"
. " --smc-check=all-non-file"
@@ -265,7 +268,16 @@
. " --suppressions="
. validate_program($tests_dir,"./tests/outer_inner.supp",1,0)
. " --memcheck:leak-check=full --memcheck:show-reachable=no"
+ . " --num-callers=40"
. " ";
+ # we use a (relatively) big --num-callers, to allow the outer to report
+ # also the inner guest stack trace, when reporting an error.
+ if (defined $outer_args) {
+ $outer_args =~ s/^\+(.*)/$1/;
+ $run_outer_args = $run_outer_args . $outer_args;
+ }
+ } else {
+ $run_outer_args = $outer_args;
}
}
@@ -505,8 +517,8 @@
mysystem( "$envvars VALGRIND_LIB_INNER=$valgrind_lib "
. "$outer_valgrind "
. "--tool=" . $outer_tool . " "
- . "$outer_args "
. "--log-file=" . "$name.outer.log "
+ . "$run_outer_args "
. "$valgrind --command-line-only=yes --memcheck:leak-check=no "
. "--sim-hints=no-inner-prefix "
. "--tool=$tool $extraopts $vgopts "
diff --git a/tests/vg_regtest.in b/tests/vg_regtest.in
index a441f42..2c323f9 100755
--- a/tests/vg_regtest.in
+++ b/tests/vg_regtest.in
@@ -6,7 +6,7 @@
# This file is part of Valgrind, a dynamic binary instrumentation
# framework.
#
-# Copyright (C) 2003-2015 Nicholas Nethercote
+# Copyright (C) 2003-2017 Nicholas Nethercote
# njn@valgrind.org
#
# This program is free software; you can redistribute it and/or
@@ -43,7 +43,9 @@
# --outer-valgrind: run this valgrind under the given outer valgrind.
# This valgrind must be configured with --enable-inner.
# --outer-tool: tool to use by the outer valgrind (default memcheck).
-# --outer-args: use this as outer tool args.
+# --outer-args: use this as outer tool args. If the outer args are starting
+# with +, the given outer args are appended to the outer args predefined
+# by vg_regtest.
# --loop-till-fail: loops on the test(s) till one fail, then exit
# This is useful to obtain detailed trace or --keep-unfiltered
# output of a non deterministic test failure
@@ -182,6 +184,7 @@
my $outer_valgrind;
my $outer_tool = "memcheck";
my $outer_args;
+my $run_outer_args = "";
my $valgrind_lib = "$tests_dir/.in_place";
my $keepunfiltered = 0;
@@ -255,8 +258,8 @@
if (defined $outer_valgrind) {
$outer_valgrind = validate_program($tests_dir, $outer_valgrind, 1, 1);
- if (not defined $outer_args) {
- $outer_args =
+ if ((not defined $outer_args) || ($outer_args =~ /^\+/)) {
+ $run_outer_args =
" --command-line-only=yes"
. " --run-libc-freeres=no --sim-hints=enable-outer"
. " --smc-check=all-non-file"
@@ -265,7 +268,16 @@
. " --suppressions="
. validate_program($tests_dir,"./tests/outer_inner.supp",1,0)
. " --memcheck:leak-check=full --memcheck:show-reachable=no"
+ . " --num-callers=40"
. " ";
+ # we use a (relatively) big --num-callers, to allow the outer to report
+ # also the inner guest stack trace, when reporting an error.
+ if (defined $outer_args) {
+ $outer_args =~ s/^\+(.*)/$1/;
+ $run_outer_args = $run_outer_args . $outer_args;
+ }
+ } else {
+ $run_outer_args = $outer_args;
}
}
@@ -505,8 +517,8 @@
mysystem( "$envvars VALGRIND_LIB_INNER=$valgrind_lib "
. "$outer_valgrind "
. "--tool=" . $outer_tool . " "
- . "$outer_args "
. "--log-file=" . "$name.outer.log "
+ . "$run_outer_args "
. "$valgrind --command-line-only=yes --memcheck:leak-check=no "
. "--sim-hints=no-inner-prefix "
. "--tool=$tool $extraopts $vgopts "
diff --git a/valgrind.spec b/valgrind.spec
index 8b78cce..3940d29 100644
--- a/valgrind.spec
+++ b/valgrind.spec
@@ -1,13 +1,13 @@
Summary: Valgrind Memory Debugger
Name: valgrind
-Version: 3.12.0
+Version: 3.13.0
Release: 1
Epoch: 1
License: GPL
URL: http://www.valgrind.org/
Group: Development/Debuggers
Packager: Julian Seward <jseward@acm.org>
-Source: valgrind-3.12.0.tar.bz2
+Source: valgrind-3.13.0.tar.bz2
Buildroot: %{_tmppath}/%{name}-root
@@ -21,7 +21,7 @@
AMD64/MacOSX.
%prep
-%setup -n valgrind-3.12.0
+%setup -n valgrind-3.13.0
%build
%configure
