Rename and rationalise the vector narrowing and widening primops, so
as to give them a consistent, understandable naming scheme. Finishes
off the process that was begun in r2159.
git-svn-id: svn://svn.valgrind.org/vex/trunk@2163 8f6e269a-dfd6-0310-a8e1-e2731360e62c
diff --git a/priv/guest_amd64_toIR.c b/priv/guest_amd64_toIR.c
index d0cc3e4..4234537 100644
--- a/priv/guest_amd64_toIR.c
+++ b/priv/guest_amd64_toIR.c
@@ -6504,9 +6504,9 @@
case 0x65: op = Iop_CmpGT16Sx4; break;
case 0x66: op = Iop_CmpGT32Sx2; break;
- case 0x6B: op = Iop_QNarrow32Sto16Sx4; eLeft = True; break;
- case 0x63: op = Iop_QNarrow16Sto8Sx8; eLeft = True; break;
- case 0x67: op = Iop_QNarrow16Sto8Ux8; eLeft = True; break;
+ case 0x6B: op = Iop_QNarrowBin32Sto16Sx4; eLeft = True; break;
+ case 0x63: op = Iop_QNarrowBin16Sto8Sx8; eLeft = True; break;
+ case 0x67: op = Iop_QNarrowBin16Sto8Ux8; eLeft = True; break;
case 0x68: op = Iop_InterleaveHI8x8; eLeft = True; break;
case 0x69: op = Iop_InterleaveHI16x4; eLeft = True; break;
@@ -11787,7 +11787,7 @@
&& insn[0] == 0x0F && insn[1] == 0x6B) {
delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
"packssdw",
- Iop_QNarrow32Sto16Sx8, True );
+ Iop_QNarrowBin32Sto16Sx8, True );
goto decode_success;
}
@@ -11796,7 +11796,7 @@
&& insn[0] == 0x0F && insn[1] == 0x63) {
delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
"packsswb",
- Iop_QNarrow16Sto8Sx16, True );
+ Iop_QNarrowBin16Sto8Sx16, True );
goto decode_success;
}
@@ -11805,7 +11805,7 @@
&& insn[0] == 0x0F && insn[1] == 0x67) {
delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
"packuswb",
- Iop_QNarrow16Sto8Ux16, True );
+ Iop_QNarrowBin16Sto8Ux16, True );
goto decode_success;
}
@@ -16028,7 +16028,8 @@
assign(argR, getXMMReg( gregOfRexRM(pfx, modrm) ));
putXMMReg( gregOfRexRM(pfx, modrm),
- binop( Iop_QNarrow32Sto16Ux8, mkexpr(argL), mkexpr(argR)) );
+ binop( Iop_QNarrowBin32Sto16Ux8,
+ mkexpr(argL), mkexpr(argR)) );
goto decode_success;
}
diff --git a/priv/guest_arm_toIR.c b/priv/guest_arm_toIR.c
index cbcda0c..b52ed4a 100644
--- a/priv/guest_arm_toIR.c
+++ b/priv/guest_arm_toIR.c
@@ -4815,15 +4815,15 @@
size = B;
switch (size) {
case 0:
- cvt = U ? Iop_Longen8Ux8 : Iop_Longen8Sx8;
+ cvt = U ? Iop_Widen8Uto16x8 : Iop_Widen8Sto16x8;
op = (A & 2) ? Iop_Sub16x8 : Iop_Add16x8;
break;
case 1:
- cvt = U ? Iop_Longen16Ux4 : Iop_Longen16Sx4;
+ cvt = U ? Iop_Widen16Uto32x4 : Iop_Widen16Sto32x4;
op = (A & 2) ? Iop_Sub32x4 : Iop_Add32x4;
break;
case 2:
- cvt = U ? Iop_Longen32Ux2 : Iop_Longen32Sx2;
+ cvt = U ? Iop_Widen32Uto64x2 : Iop_Widen32Sto64x2;
op = (A & 2) ? Iop_Sub64x2 : Iop_Add64x2;
break;
case 3:
@@ -4860,7 +4860,7 @@
switch (size) {
case 0:
op = Iop_Add16x8;
- cvt = Iop_Shorten16x8;
+ cvt = Iop_NarrowUn16to8x8;
sh = Iop_ShrN16x8;
imm = 1U << 7;
imm = (imm << 16) | imm;
@@ -4868,14 +4868,14 @@
break;
case 1:
op = Iop_Add32x4;
- cvt = Iop_Shorten32x4;
+ cvt = Iop_NarrowUn32to16x4;
sh = Iop_ShrN32x4;
imm = 1U << 15;
imm = (imm << 32) | imm;
break;
case 2:
op = Iop_Add64x2;
- cvt = Iop_Shorten64x2;
+ cvt = Iop_NarrowUn64to32x2;
sh = Iop_ShrN64x2;
imm = 1U << 31;
break;
@@ -4910,22 +4910,22 @@
switch (size) {
case 0:
cmp = U ? Iop_CmpGT8Ux8 : Iop_CmpGT8Sx8;
- cvt = U ? Iop_Longen8Ux8 : Iop_Longen8Sx8;
- cvt2 = Iop_Longen8Sx8;
+ cvt = U ? Iop_Widen8Uto16x8 : Iop_Widen8Sto16x8;
+ cvt2 = Iop_Widen8Sto16x8;
op = Iop_Sub16x8;
op2 = Iop_Add16x8;
break;
case 1:
cmp = U ? Iop_CmpGT16Ux4 : Iop_CmpGT16Sx4;
- cvt = U ? Iop_Longen16Ux4 : Iop_Longen16Sx4;
- cvt2 = Iop_Longen16Sx4;
+ cvt = U ? Iop_Widen16Uto32x4 : Iop_Widen16Sto32x4;
+ cvt2 = Iop_Widen16Sto32x4;
op = Iop_Sub32x4;
op2 = Iop_Add32x4;
break;
case 2:
cmp = U ? Iop_CmpGT32Ux2 : Iop_CmpGT32Sx2;
- cvt = U ? Iop_Longen32Ux2 : Iop_Longen32Sx2;
- cvt2 = Iop_Longen32Sx2;
+ cvt = U ? Iop_Widen32Uto64x2 : Iop_Widen32Sto64x2;
+ cvt2 = Iop_Widen32Sto64x2;
op = Iop_Sub64x2;
op2 = Iop_Add64x2;
break;
@@ -4968,7 +4968,7 @@
case 0:
op = Iop_Sub16x8;
op2 = Iop_Add16x8;
- cvt = Iop_Shorten16x8;
+ cvt = Iop_NarrowUn16to8x8;
sh = Iop_ShrN16x8;
imm = 1U << 7;
imm = (imm << 16) | imm;
@@ -4977,7 +4977,7 @@
case 1:
op = Iop_Sub32x4;
op2 = Iop_Add32x4;
- cvt = Iop_Shorten32x4;
+ cvt = Iop_NarrowUn32to16x4;
sh = Iop_ShrN32x4;
imm = 1U << 15;
imm = (imm << 32) | imm;
@@ -4985,7 +4985,7 @@
case 2:
op = Iop_Sub64x2;
op2 = Iop_Add64x2;
- cvt = Iop_Shorten64x2;
+ cvt = Iop_NarrowUn64to32x2;
sh = Iop_ShrN64x2;
imm = 1U << 31;
break;
@@ -5020,20 +5020,20 @@
switch (size) {
case 0:
cmp = U ? Iop_CmpGT8Ux8 : Iop_CmpGT8Sx8;
- cvt = U ? Iop_Longen8Ux8 : Iop_Longen8Sx8;
- cvt2 = Iop_Longen8Sx8;
+ cvt = U ? Iop_Widen8Uto16x8 : Iop_Widen8Sto16x8;
+ cvt2 = Iop_Widen8Sto16x8;
op = Iop_Sub16x8;
break;
case 1:
cmp = U ? Iop_CmpGT16Ux4 : Iop_CmpGT16Sx4;
- cvt = U ? Iop_Longen16Ux4 : Iop_Longen16Sx4;
- cvt2 = Iop_Longen16Sx4;
+ cvt = U ? Iop_Widen16Uto32x4 : Iop_Widen16Sto32x4;
+ cvt2 = Iop_Widen16Sto32x4;
op = Iop_Sub32x4;
break;
case 2:
cmp = U ? Iop_CmpGT32Ux2 : Iop_CmpGT32Sx2;
- cvt = U ? Iop_Longen32Ux2 : Iop_Longen32Sx2;
- cvt2 = Iop_Longen32Sx2;
+ cvt = U ? Iop_Widen32Uto64x2 : Iop_Widen32Sto64x2;
+ cvt2 = Iop_Widen32Sto64x2;
op = Iop_Sub64x2;
break;
case 3:
@@ -6339,15 +6339,15 @@
switch (size) {
case 1:
op = Iop_ShrN16x8;
- narOp = Iop_Shorten16x8;
+ narOp = Iop_NarrowUn16to8x8;
break;
case 2:
op = Iop_ShrN32x4;
- narOp = Iop_Shorten32x4;
+ narOp = Iop_NarrowUn32to16x4;
break;
case 3:
op = Iop_ShrN64x2;
- narOp = Iop_Shorten64x2;
+ narOp = Iop_NarrowUn64to32x2;
break;
default:
vassert(0);
@@ -6380,17 +6380,17 @@
case 1:
addOp = Iop_Add16x8;
shOp = Iop_ShrN16x8;
- narOp = Iop_Shorten16x8;
+ narOp = Iop_NarrowUn16to8x8;
break;
case 2:
addOp = Iop_Add32x4;
shOp = Iop_ShrN32x4;
- narOp = Iop_Shorten32x4;
+ narOp = Iop_NarrowUn32to16x4;
break;
case 3:
addOp = Iop_Add64x2;
shOp = Iop_ShrN64x2;
- narOp = Iop_Shorten64x2;
+ narOp = Iop_NarrowUn64to32x2;
break;
default:
vassert(0);
@@ -6429,18 +6429,18 @@
switch (size) {
case 1:
op = U ? Iop_ShrN16x8 : Iop_SarN16x8;
- cvt = U ? Iop_QShortenU16Ux8 : Iop_QShortenS16Sx8;
- cvt2 = U ? Iop_Longen8Ux8 : Iop_Longen8Sx8;
+ cvt = U ? Iop_QNarrowUn16Uto8Ux8 : Iop_QNarrowUn16Sto8Sx8;
+ cvt2 = U ? Iop_Widen8Uto16x8 : Iop_Widen8Sto16x8;
break;
case 2:
op = U ? Iop_ShrN32x4 : Iop_SarN32x4;
- cvt = U ? Iop_QShortenU32Ux4 : Iop_QShortenS32Sx4;
- cvt2 = U ? Iop_Longen16Ux4 : Iop_Longen16Sx4;
+ cvt = U ? Iop_QNarrowUn32Uto16Ux4 : Iop_QNarrowUn32Sto16Sx4;
+ cvt2 = U ? Iop_Widen16Uto32x4 : Iop_Widen16Sto32x4;
break;
case 3:
op = U ? Iop_ShrN64x2 : Iop_SarN64x2;
- cvt = U ? Iop_QShortenU64Ux2 : Iop_QShortenS64Sx2;
- cvt2 = U ? Iop_Longen32Ux2 : Iop_Longen32Sx2;
+ cvt = U ? Iop_QNarrowUn64Uto32Ux2 : Iop_QNarrowUn64Sto32Sx2;
+ cvt2 = U ? Iop_Widen32Uto64x2 : Iop_Widen32Sto64x2;
break;
default:
vassert(0);
@@ -6452,18 +6452,18 @@
switch (size) {
case 1:
op = Iop_SarN16x8;
- cvt = Iop_QShortenU16Sx8;
- cvt2 = Iop_Longen8Ux8;
+ cvt = Iop_QNarrowUn16Sto8Ux8;
+ cvt2 = Iop_Widen8Uto16x8;
break;
case 2:
op = Iop_SarN32x4;
- cvt = Iop_QShortenU32Sx4;
- cvt2 = Iop_Longen16Ux4;
+ cvt = Iop_QNarrowUn32Sto16Ux4;
+ cvt2 = Iop_Widen16Uto32x4;
break;
case 3:
op = Iop_SarN64x2;
- cvt = Iop_QShortenU64Sx2;
- cvt2 = Iop_Longen32Ux2;
+ cvt = Iop_QNarrowUn64Sto32Ux2;
+ cvt2 = Iop_Widen32Uto64x2;
break;
default:
vassert(0);
@@ -6523,15 +6523,15 @@
switch (size) {
case 0:
op = Iop_ShlN16x8;
- cvt = U ? Iop_Longen8Ux8 : Iop_Longen8Sx8;
+ cvt = U ? Iop_Widen8Uto16x8 : Iop_Widen8Sto16x8;
break;
case 1:
op = Iop_ShlN32x4;
- cvt = U ? Iop_Longen16Ux4 : Iop_Longen16Sx4;
+ cvt = U ? Iop_Widen16Uto32x4 : Iop_Widen16Sto32x4;
break;
case 2:
op = Iop_ShlN64x2;
- cvt = U ? Iop_Longen32Ux2 : Iop_Longen32Sx2;
+ cvt = U ? Iop_Widen32Uto64x2 : Iop_Widen32Sto64x2;
break;
case 3:
return False;
@@ -7340,9 +7340,9 @@
IROp op;
mreg >>= 1;
switch (size) {
- case 0: op = Iop_Shorten16x8; break;
- case 1: op = Iop_Shorten32x4; break;
- case 2: op = Iop_Shorten64x2; break;
+ case 0: op = Iop_NarrowUn16to8x8; break;
+ case 1: op = Iop_NarrowUn32to16x4; break;
+ case 2: op = Iop_NarrowUn64to32x2; break;
case 3: return False;
default: vassert(0);
}
@@ -7359,9 +7359,9 @@
return False;
mreg >>= 1;
switch (size) {
- case 0: op2 = Iop_Shorten16x8; break;
- case 1: op2 = Iop_Shorten32x4; break;
- case 2: op2 = Iop_Shorten64x2; break;
+ case 0: op2 = Iop_NarrowUn16to8x8; break;
+ case 1: op2 = Iop_NarrowUn32to16x4; break;
+ case 2: op2 = Iop_NarrowUn64to32x2; break;
case 3: return False;
default: vassert(0);
}
@@ -7370,9 +7370,9 @@
vassert(0);
case 1:
switch (size) {
- case 0: op = Iop_QShortenU16Sx8; break;
- case 1: op = Iop_QShortenU32Sx4; break;
- case 2: op = Iop_QShortenU64Sx2; break;
+ case 0: op = Iop_QNarrowUn16Sto8Ux8; break;
+ case 1: op = Iop_QNarrowUn32Sto16Ux4; break;
+ case 2: op = Iop_QNarrowUn64Sto32Ux2; break;
case 3: return False;
default: vassert(0);
}
@@ -7380,9 +7380,9 @@
break;
case 2:
switch (size) {
- case 0: op = Iop_QShortenS16Sx8; break;
- case 1: op = Iop_QShortenS32Sx4; break;
- case 2: op = Iop_QShortenS64Sx2; break;
+ case 0: op = Iop_QNarrowUn16Sto8Sx8; break;
+ case 1: op = Iop_QNarrowUn32Sto16Sx4; break;
+ case 2: op = Iop_QNarrowUn64Sto32Sx2; break;
case 3: return False;
default: vassert(0);
}
@@ -7390,9 +7390,9 @@
break;
case 3:
switch (size) {
- case 0: op = Iop_QShortenU16Ux8; break;
- case 1: op = Iop_QShortenU32Ux4; break;
- case 2: op = Iop_QShortenU64Ux2; break;
+ case 0: op = Iop_QNarrowUn16Uto8Ux8; break;
+ case 1: op = Iop_QNarrowUn32Uto16Ux4; break;
+ case 2: op = Iop_QNarrowUn64Uto32Ux2; break;
case 3: return False;
default: vassert(0);
}
@@ -7422,9 +7422,9 @@
shift_imm = 8 << size;
res = newTemp(Ity_V128);
switch (size) {
- case 0: op = Iop_ShlN16x8; cvt = Iop_Longen8Ux8; break;
- case 1: op = Iop_ShlN32x4; cvt = Iop_Longen16Ux4; break;
- case 2: op = Iop_ShlN64x2; cvt = Iop_Longen32Ux2; break;
+ case 0: op = Iop_ShlN16x8; cvt = Iop_Widen8Uto16x8; break;
+ case 1: op = Iop_ShlN32x4; cvt = Iop_Widen16Uto32x4; break;
+ case 2: op = Iop_ShlN64x2; cvt = Iop_Widen32Uto64x2; break;
case 3: return False;
default: vassert(0);
}
diff --git a/priv/guest_ppc_toIR.c b/priv/guest_ppc_toIR.c
index 6cf7c9d..ce7cf5d 100644
--- a/priv/guest_ppc_toIR.c
+++ b/priv/guest_ppc_toIR.c
@@ -9418,7 +9418,7 @@
mkU8(15))) );
putVReg( vD_addr,
- binop(Iop_QNarrow32Sto16Sx8, mkexpr(zHi), mkexpr(zLo)) );
+ binop(Iop_QNarrowBin32Sto16Sx8, mkexpr(zHi), mkexpr(zLo)) );
break;
}
case 0x21: { // vmhraddshs (Mult High Round, Add Signed HW Saturate, AV p186)
@@ -9453,7 +9453,7 @@
mkU8(15))) );
putVReg( vD_addr,
- binop(Iop_QNarrow32Sto16Sx8, mkexpr(zHi), mkexpr(zLo)) );
+ binop(Iop_QNarrowBin32Sto16Sx8, mkexpr(zHi), mkexpr(zLo)) );
break;
}
case 0x22: { // vmladduhm (Mult Low, Add Unsigned HW Modulo, AV p194)
@@ -9471,7 +9471,8 @@
assign(zHi, binop(Iop_Add32x4,
binop(Iop_MullEven16Ux8, mkexpr(aHi), mkexpr(bHi)),
mkexpr(cHi)));
- putVReg(vD_addr, binop(Iop_Narrow32x4, mkexpr(zHi), mkexpr(zLo)));
+ putVReg( vD_addr,
+ binop(Iop_NarrowBin32to16x8, mkexpr(zHi), mkexpr(zLo)) );
break;
}
@@ -9955,25 +9956,27 @@
/* Packing */
case 0x00E: // vpkuhum (Pack Unsigned HW Unsigned Modulo, AV p224)
DIP("vpkuhum v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- putVReg( vD_addr, binop(Iop_Narrow16x8, mkexpr(vA), mkexpr(vB)) );
+ putVReg( vD_addr,
+ binop(Iop_NarrowBin16to8x16, mkexpr(vA), mkexpr(vB)) );
return True;
case 0x04E: // vpkuwum (Pack Unsigned W Unsigned Modulo, AV p226)
DIP("vpkuwum v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- putVReg( vD_addr, binop(Iop_Narrow32x4, mkexpr(vA), mkexpr(vB)) );
+ putVReg( vD_addr,
+ binop(Iop_NarrowBin32to16x8, mkexpr(vA), mkexpr(vB)) );
return True;
case 0x08E: // vpkuhus (Pack Unsigned HW Unsigned Saturate, AV p225)
DIP("vpkuhus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
putVReg( vD_addr,
- binop(Iop_QNarrow16Uto8Ux16, mkexpr(vA), mkexpr(vB)) );
+ binop(Iop_QNarrowBin16Uto8Ux16, mkexpr(vA), mkexpr(vB)) );
// TODO: set VSCR[SAT]
return True;
case 0x0CE: // vpkuwus (Pack Unsigned W Unsigned Saturate, AV p227)
DIP("vpkuwus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
putVReg( vD_addr,
- binop(Iop_QNarrow32Uto16Ux8, mkexpr(vA), mkexpr(vB)) );
+ binop(Iop_QNarrowBin32Uto16Ux8, mkexpr(vA), mkexpr(vB)) );
// TODO: set VSCR[SAT]
return True;
@@ -9992,7 +9995,7 @@
unop(Iop_NotV128,
binop(Iop_SarN16x8,
mkexpr(vB), mkU8(15)))) );
- putVReg( vD_addr, binop(Iop_QNarrow16Uto8Ux16,
+ putVReg( vD_addr, binop(Iop_QNarrowBin16Uto8Ux16,
mkexpr(vA_tmp), mkexpr(vB_tmp)) );
// TODO: set VSCR[SAT]
return True;
@@ -10012,7 +10015,7 @@
unop(Iop_NotV128,
binop(Iop_SarN32x4,
mkexpr(vB), mkU8(31)))) );
- putVReg( vD_addr, binop(Iop_QNarrow32Uto16Ux8,
+ putVReg( vD_addr, binop(Iop_QNarrowBin32Uto16Ux8,
mkexpr(vA_tmp), mkexpr(vB_tmp)) );
// TODO: set VSCR[SAT]
return True;
@@ -10020,14 +10023,14 @@
case 0x18E: // vpkshss (Pack Signed HW Signed Saturate, AV p220)
DIP("vpkshss v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
putVReg( vD_addr,
- binop(Iop_QNarrow16Sto8Sx16, mkexpr(vA), mkexpr(vB)) );
+ binop(Iop_QNarrowBin16Sto8Sx16, mkexpr(vA), mkexpr(vB)) );
// TODO: set VSCR[SAT]
return True;
case 0x1CE: // vpkswss (Pack Signed W Signed Saturate, AV p222)
DIP("vpkswss v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
putVReg( vD_addr,
- binop(Iop_QNarrow32Sto16Sx8, mkexpr(vA), mkexpr(vB)) );
+ binop(Iop_QNarrowBin32Sto16Sx8, mkexpr(vA), mkexpr(vB)) );
// TODO: set VSCR[SAT]
return True;
@@ -10067,7 +10070,7 @@
assign( b_tmp, binop(Iop_OrV128, mkexpr(b1),
binop(Iop_OrV128, mkexpr(b2), mkexpr(b3))) );
- putVReg( vD_addr, binop(Iop_Narrow32x4,
+ putVReg( vD_addr, binop(Iop_NarrowBin32to16x8,
mkexpr(a_tmp), mkexpr(b_tmp)) );
return True;
}
diff --git a/priv/guest_x86_toIR.c b/priv/guest_x86_toIR.c
index c8398a8..3f5bf91 100644
--- a/priv/guest_x86_toIR.c
+++ b/priv/guest_x86_toIR.c
@@ -5475,9 +5475,9 @@
case 0x65: op = Iop_CmpGT16Sx4; break;
case 0x66: op = Iop_CmpGT32Sx2; break;
- case 0x6B: op = Iop_QNarrow32Sto16Sx4; eLeft = True; break;
- case 0x63: op = Iop_QNarrow16Sto8Sx8; eLeft = True; break;
- case 0x67: op = Iop_QNarrow16Sto8Ux8; eLeft = True; break;
+ case 0x6B: op = Iop_QNarrowBin32Sto16Sx4; eLeft = True; break;
+ case 0x63: op = Iop_QNarrowBin16Sto8Sx8; eLeft = True; break;
+ case 0x67: op = Iop_QNarrowBin16Sto8Ux8; eLeft = True; break;
case 0x68: op = Iop_InterleaveHI8x8; eLeft = True; break;
case 0x69: op = Iop_InterleaveHI16x4; eLeft = True; break;
@@ -10533,7 +10533,7 @@
if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x6B) {
delta = dis_SSEint_E_to_G( sorb, delta+2,
"packssdw",
- Iop_QNarrow32Sto16Sx8, True );
+ Iop_QNarrowBin32Sto16Sx8, True );
goto decode_success;
}
@@ -10541,7 +10541,7 @@
if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x63) {
delta = dis_SSEint_E_to_G( sorb, delta+2,
"packsswb",
- Iop_QNarrow16Sto8Sx16, True );
+ Iop_QNarrowBin16Sto8Sx16, True );
goto decode_success;
}
@@ -10549,7 +10549,7 @@
if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x67) {
delta = dis_SSEint_E_to_G( sorb, delta+2,
"packuswb",
- Iop_QNarrow16Sto8Ux16, True );
+ Iop_QNarrowBin16Sto8Ux16, True );
goto decode_success;
}
diff --git a/priv/host_amd64_isel.c b/priv/host_amd64_isel.c
index b428ca0..c887ca3 100644
--- a/priv/host_amd64_isel.c
+++ b/priv/host_amd64_isel.c
@@ -1094,12 +1094,12 @@
case Iop_QAdd16Ux4:
fn = (HWord)h_generic_calc_QAdd16Ux4; break;
- case Iop_QNarrow32Sto16Sx4:
- fn = (HWord)h_generic_calc_QNarrow32Sto16Sx4; break;
- case Iop_QNarrow16Sto8Sx8:
- fn = (HWord)h_generic_calc_QNarrow16Sto8Sx8; break;
- case Iop_QNarrow16Sto8Ux8:
- fn = (HWord)h_generic_calc_QNarrow16Sto8Ux8; break;
+ case Iop_QNarrowBin32Sto16Sx4:
+ fn = (HWord)h_generic_calc_QNarrowBin32Sto16Sx4; break;
+ case Iop_QNarrowBin16Sto8Sx8:
+ fn = (HWord)h_generic_calc_QNarrowBin16Sto8Sx8; break;
+ case Iop_QNarrowBin16Sto8Ux8:
+ fn = (HWord)h_generic_calc_QNarrowBin16Sto8Ux8; break;
case Iop_QSub8Sx8:
fn = (HWord)h_generic_calc_QSub8Sx8; break;
@@ -3544,11 +3544,11 @@
return dst;
}
- case Iop_QNarrow32Sto16Sx8:
+ case Iop_QNarrowBin32Sto16Sx8:
op = Asse_PACKSSD; arg1isEReg = True; goto do_SseReRg;
- case Iop_QNarrow16Sto8Sx16:
+ case Iop_QNarrowBin16Sto8Sx16:
op = Asse_PACKSSW; arg1isEReg = True; goto do_SseReRg;
- case Iop_QNarrow16Sto8Ux16:
+ case Iop_QNarrowBin16Sto8Ux16:
op = Asse_PACKUSW; arg1isEReg = True; goto do_SseReRg;
case Iop_InterleaveHI8x16:
@@ -3660,8 +3660,8 @@
goto do_SseAssistedBinary;
case Iop_CmpGT64Sx2: fn = (HWord)h_generic_calc_CmpGT64Sx2;
goto do_SseAssistedBinary;
- case Iop_QNarrow32Sto16Ux8:
- fn = (HWord)h_generic_calc_QNarrow32Sto16Ux8;
+ case Iop_QNarrowBin32Sto16Ux8:
+ fn = (HWord)h_generic_calc_QNarrowBin32Sto16Ux8;
goto do_SseAssistedBinary;
do_SseAssistedBinary: {
/* RRRufff! RRRufff code is what we're generating here. Oh
diff --git a/priv/host_arm_isel.c b/priv/host_arm_isel.c
index a2987ee..d4d9c86 100644
--- a/priv/host_arm_isel.c
+++ b/priv/host_arm_isel.c
@@ -3351,64 +3351,64 @@
addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, tmp, 4, False));
return res;
}
- case Iop_Shorten16x8:
- case Iop_Shorten32x4:
- case Iop_Shorten64x2: {
+ case Iop_NarrowUn16to8x8:
+ case Iop_NarrowUn32to16x4:
+ case Iop_NarrowUn64to32x2: {
HReg res = newVRegD(env);
HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
UInt size = 0;
switch(e->Iex.Binop.op) {
- case Iop_Shorten16x8: size = 0; break;
- case Iop_Shorten32x4: size = 1; break;
- case Iop_Shorten64x2: size = 2; break;
+ case Iop_NarrowUn16to8x8: size = 0; break;
+ case Iop_NarrowUn32to16x4: size = 1; break;
+ case Iop_NarrowUn64to32x2: size = 2; break;
default: vassert(0);
}
addInstr(env, ARMInstr_NUnary(ARMneon_COPYN,
res, arg, size, False));
return res;
}
- case Iop_QShortenS16Sx8:
- case Iop_QShortenS32Sx4:
- case Iop_QShortenS64Sx2: {
+ case Iop_QNarrowUn16Sto8Sx8:
+ case Iop_QNarrowUn32Sto16Sx4:
+ case Iop_QNarrowUn64Sto32Sx2: {
HReg res = newVRegD(env);
HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
UInt size = 0;
switch(e->Iex.Binop.op) {
- case Iop_QShortenS16Sx8: size = 0; break;
- case Iop_QShortenS32Sx4: size = 1; break;
- case Iop_QShortenS64Sx2: size = 2; break;
+ case Iop_QNarrowUn16Sto8Sx8: size = 0; break;
+ case Iop_QNarrowUn32Sto16Sx4: size = 1; break;
+ case Iop_QNarrowUn64Sto32Sx2: size = 2; break;
default: vassert(0);
}
addInstr(env, ARMInstr_NUnary(ARMneon_COPYQNSS,
res, arg, size, False));
return res;
}
- case Iop_QShortenU16Sx8:
- case Iop_QShortenU32Sx4:
- case Iop_QShortenU64Sx2: {
+ case Iop_QNarrowUn16Sto8Ux8:
+ case Iop_QNarrowUn32Sto16Ux4:
+ case Iop_QNarrowUn64Sto32Ux2: {
HReg res = newVRegD(env);
HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
UInt size = 0;
switch(e->Iex.Binop.op) {
- case Iop_QShortenU16Sx8: size = 0; break;
- case Iop_QShortenU32Sx4: size = 1; break;
- case Iop_QShortenU64Sx2: size = 2; break;
+ case Iop_QNarrowUn16Sto8Ux8: size = 0; break;
+ case Iop_QNarrowUn32Sto16Ux4: size = 1; break;
+ case Iop_QNarrowUn64Sto32Ux2: size = 2; break;
default: vassert(0);
}
addInstr(env, ARMInstr_NUnary(ARMneon_COPYQNUS,
res, arg, size, False));
return res;
}
- case Iop_QShortenU16Ux8:
- case Iop_QShortenU32Ux4:
- case Iop_QShortenU64Ux2: {
+ case Iop_QNarrowUn16Uto8Ux8:
+ case Iop_QNarrowUn32Uto16Ux4:
+ case Iop_QNarrowUn64Uto32Ux2: {
HReg res = newVRegD(env);
HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
UInt size = 0;
switch(e->Iex.Binop.op) {
- case Iop_QShortenU16Ux8: size = 0; break;
- case Iop_QShortenU32Ux4: size = 1; break;
- case Iop_QShortenU64Ux2: size = 2; break;
+ case Iop_QNarrowUn16Uto8Ux8: size = 0; break;
+ case Iop_QNarrowUn32Uto16Ux4: size = 1; break;
+ case Iop_QNarrowUn64Uto32Ux2: size = 2; break;
default: vassert(0);
}
addInstr(env, ARMInstr_NUnary(ARMneon_COPYQNUU,
@@ -3974,32 +3974,32 @@
addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, tmp, 4, True));
return res;
}
- case Iop_Longen8Ux8:
- case Iop_Longen16Ux4:
- case Iop_Longen32Ux2: {
+ case Iop_Widen8Uto16x8:
+ case Iop_Widen16Uto32x4:
+ case Iop_Widen32Uto64x2: {
HReg res = newVRegV(env);
HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
UInt size;
switch (e->Iex.Unop.op) {
- case Iop_Longen8Ux8: size = 0; break;
- case Iop_Longen16Ux4: size = 1; break;
- case Iop_Longen32Ux2: size = 2; break;
+ case Iop_Widen8Uto16x8: size = 0; break;
+ case Iop_Widen16Uto32x4: size = 1; break;
+ case Iop_Widen32Uto64x2: size = 2; break;
default: vassert(0);
}
addInstr(env, ARMInstr_NUnary(ARMneon_COPYLU,
res, arg, size, True));
return res;
}
- case Iop_Longen8Sx8:
- case Iop_Longen16Sx4:
- case Iop_Longen32Sx2: {
+ case Iop_Widen8Sto16x8:
+ case Iop_Widen16Sto32x4:
+ case Iop_Widen32Sto64x2: {
HReg res = newVRegV(env);
HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
UInt size;
switch (e->Iex.Unop.op) {
- case Iop_Longen8Sx8: size = 0; break;
- case Iop_Longen16Sx4: size = 1; break;
- case Iop_Longen32Sx2: size = 2; break;
+ case Iop_Widen8Sto16x8: size = 0; break;
+ case Iop_Widen16Sto32x4: size = 1; break;
+ case Iop_Widen32Sto64x2: size = 2; break;
default: vassert(0);
}
addInstr(env, ARMInstr_NUnary(ARMneon_COPYLS,
diff --git a/priv/host_generic_simd128.c b/priv/host_generic_simd128.c
index 2a839f7..4fd1df5 100644
--- a/priv/host_generic_simd128.c
+++ b/priv/host_generic_simd128.c
@@ -271,8 +271,8 @@
res->w8[15] = sar8(argL->w8[15], nn);
}
-void h_generic_calc_QNarrow32Sto16Ux8 ( /*OUT*/V128* res,
- V128* argL, V128* argR )
+void h_generic_calc_QNarrowBin32Sto16Ux8 ( /*OUT*/V128* res,
+ V128* argL, V128* argR )
{
res->w16[0] = qnarrow32Sto16U(argR->w32[0]);
res->w16[1] = qnarrow32Sto16U(argR->w32[1]);
diff --git a/priv/host_generic_simd128.h b/priv/host_generic_simd128.h
index f690bda..ed8a7db 100644
--- a/priv/host_generic_simd128.h
+++ b/priv/host_generic_simd128.h
@@ -61,7 +61,7 @@
extern void h_generic_calc_SarN64x2 ( /*OUT*/V128*, V128*, UInt );
extern void h_generic_calc_SarN8x16 ( /*OUT*/V128*, V128*, UInt );
-extern void h_generic_calc_QNarrow32Sto16Ux8
+extern void h_generic_calc_QNarrowBin32Sto16Ux8
( /*OUT*/V128*, V128*, V128* );
diff --git a/priv/host_generic_simd64.c b/priv/host_generic_simd64.c
index 58ebc7b..61bdbd3 100644
--- a/priv/host_generic_simd64.c
+++ b/priv/host_generic_simd64.c
@@ -759,7 +759,7 @@
/* ------------ Saturating narrowing ------------ */
-ULong h_generic_calc_QNarrow32Sto16Sx4 ( ULong aa, ULong bb )
+ULong h_generic_calc_QNarrowBin32Sto16Sx4 ( ULong aa, ULong bb )
{
UInt d = sel32x2_1(aa);
UInt c = sel32x2_0(aa);
@@ -773,7 +773,7 @@
);
}
-ULong h_generic_calc_QNarrow16Sto8Sx8 ( ULong aa, ULong bb )
+ULong h_generic_calc_QNarrowBin16Sto8Sx8 ( ULong aa, ULong bb )
{
UShort h = sel16x4_3(aa);
UShort g = sel16x4_2(aa);
@@ -795,7 +795,7 @@
);
}
-ULong h_generic_calc_QNarrow16Sto8Ux8 ( ULong aa, ULong bb )
+ULong h_generic_calc_QNarrowBin16Sto8Ux8 ( ULong aa, ULong bb )
{
UShort h = sel16x4_3(aa);
UShort g = sel16x4_2(aa);
diff --git a/priv/host_generic_simd64.h b/priv/host_generic_simd64.h
index 05ac560..1807ed7 100644
--- a/priv/host_generic_simd64.h
+++ b/priv/host_generic_simd64.h
@@ -87,9 +87,9 @@
extern ULong h_generic_calc_CmpNEZ16x4 ( ULong );
extern ULong h_generic_calc_CmpNEZ8x8 ( ULong );
-extern ULong h_generic_calc_QNarrow32Sto16Sx4 ( ULong, ULong );
-extern ULong h_generic_calc_QNarrow16Sto8Sx8 ( ULong, ULong );
-extern ULong h_generic_calc_QNarrow16Sto8Ux8 ( ULong, ULong );
+extern ULong h_generic_calc_QNarrowBin32Sto16Sx4 ( ULong, ULong );
+extern ULong h_generic_calc_QNarrowBin16Sto8Sx8 ( ULong, ULong );
+extern ULong h_generic_calc_QNarrowBin16Sto8Ux8 ( ULong, ULong );
extern ULong h_generic_calc_InterleaveHI8x8 ( ULong, ULong );
extern ULong h_generic_calc_InterleaveLO8x8 ( ULong, ULong );
diff --git a/priv/host_ppc_isel.c b/priv/host_ppc_isel.c
index f3885eb..3d349e2 100644
--- a/priv/host_ppc_isel.c
+++ b/priv/host_ppc_isel.c
@@ -3678,9 +3678,9 @@
case Iop_Shr16x8: op = Pav_SHR; goto do_AvBin16x8;
case Iop_Sar16x8: op = Pav_SAR; goto do_AvBin16x8;
case Iop_Rol16x8: op = Pav_ROTL; goto do_AvBin16x8;
- case Iop_Narrow16x8: op = Pav_PACKUU; goto do_AvBin16x8;
- case Iop_QNarrow16Uto8Ux16: op = Pav_QPACKUU; goto do_AvBin16x8;
- case Iop_QNarrow16Sto8Sx16: op = Pav_QPACKSS; goto do_AvBin16x8;
+ case Iop_NarrowBin16to8x16: op = Pav_PACKUU; goto do_AvBin16x8;
+ case Iop_QNarrowBin16Uto8Ux16: op = Pav_QPACKUU; goto do_AvBin16x8;
+ case Iop_QNarrowBin16Sto8Sx16: op = Pav_QPACKSS; goto do_AvBin16x8;
case Iop_InterleaveHI16x8: op = Pav_MRGHI; goto do_AvBin16x8;
case Iop_InterleaveLO16x8: op = Pav_MRGLO; goto do_AvBin16x8;
case Iop_Add16x8: op = Pav_ADDU; goto do_AvBin16x8;
@@ -3712,9 +3712,9 @@
case Iop_Shr32x4: op = Pav_SHR; goto do_AvBin32x4;
case Iop_Sar32x4: op = Pav_SAR; goto do_AvBin32x4;
case Iop_Rol32x4: op = Pav_ROTL; goto do_AvBin32x4;
- case Iop_Narrow32x4: op = Pav_PACKUU; goto do_AvBin32x4;
- case Iop_QNarrow32Uto16Ux8: op = Pav_QPACKUU; goto do_AvBin32x4;
- case Iop_QNarrow32Sto16Sx8: op = Pav_QPACKSS; goto do_AvBin32x4;
+ case Iop_NarrowBin32to16x8: op = Pav_PACKUU; goto do_AvBin32x4;
+ case Iop_QNarrowBin32Uto16Ux8: op = Pav_QPACKUU; goto do_AvBin32x4;
+ case Iop_QNarrowBin32Sto16Sx8: op = Pav_QPACKSS; goto do_AvBin32x4;
case Iop_InterleaveHI32x4: op = Pav_MRGHI; goto do_AvBin32x4;
case Iop_InterleaveLO32x4: op = Pav_MRGLO; goto do_AvBin32x4;
case Iop_Add32x4: op = Pav_ADDU; goto do_AvBin32x4;
diff --git a/priv/host_x86_isel.c b/priv/host_x86_isel.c
index 74552da..7ec6305 100644
--- a/priv/host_x86_isel.c
+++ b/priv/host_x86_isel.c
@@ -2386,12 +2386,12 @@
case Iop_QAdd16Ux4:
fn = (HWord)h_generic_calc_QAdd16Ux4; goto binnish;
- case Iop_QNarrow32Sto16Sx4:
- fn = (HWord)h_generic_calc_QNarrow32Sto16Sx4; goto binnish;
- case Iop_QNarrow16Sto8Sx8:
- fn = (HWord)h_generic_calc_QNarrow16Sto8Sx8; goto binnish;
- case Iop_QNarrow16Sto8Ux8:
- fn = (HWord)h_generic_calc_QNarrow16Sto8Ux8; goto binnish;
+ case Iop_QNarrowBin32Sto16Sx4:
+ fn = (HWord)h_generic_calc_QNarrowBin32Sto16Sx4; goto binnish;
+ case Iop_QNarrowBin16Sto8Sx8:
+ fn = (HWord)h_generic_calc_QNarrowBin16Sto8Sx8; goto binnish;
+ case Iop_QNarrowBin16Sto8Ux8:
+ fn = (HWord)h_generic_calc_QNarrowBin16Sto8Ux8; goto binnish;
case Iop_QSub8Sx8:
fn = (HWord)h_generic_calc_QSub8Sx8; goto binnish;
@@ -3500,11 +3500,11 @@
return dst;
}
- case Iop_QNarrow32Sto16Sx8:
+ case Iop_QNarrowBin32Sto16Sx8:
op = Xsse_PACKSSD; arg1isEReg = True; goto do_SseReRg;
- case Iop_QNarrow16Sto8Sx16:
+ case Iop_QNarrowBin16Sto8Sx16:
op = Xsse_PACKSSW; arg1isEReg = True; goto do_SseReRg;
- case Iop_QNarrow16Sto8Ux16:
+ case Iop_QNarrowBin16Sto8Ux16:
op = Xsse_PACKUSW; arg1isEReg = True; goto do_SseReRg;
case Iop_InterleaveHI8x16:
diff --git a/priv/ir_defs.c b/priv/ir_defs.c
index 0418520..f5ac5fc 100644
--- a/priv/ir_defs.c
+++ b/priv/ir_defs.c
@@ -506,9 +506,9 @@
case Iop_SarN8x8: vex_printf("SarN8x8"); return;
case Iop_SarN16x4: vex_printf("SarN16x4"); return;
case Iop_SarN32x2: vex_printf("SarN32x2"); return;
- case Iop_QNarrow16Sto8Ux8: vex_printf("QNarrow16Sto8Ux8"); return;
- case Iop_QNarrow16Sto8Sx8: vex_printf("QNarrow16Sto8Sx8"); return;
- case Iop_QNarrow32Sto16Sx4: vex_printf("QNarrow32Sto16Sx4"); return;
+ case Iop_QNarrowBin16Sto8Ux8: vex_printf("QNarrowBin16Sto8Ux8"); return;
+ case Iop_QNarrowBin16Sto8Sx8: vex_printf("QNarrowBin16Sto8Sx8"); return;
+ case Iop_QNarrowBin32Sto16Sx4: vex_printf("QNarrowBin32Sto16Sx4"); return;
case Iop_InterleaveHI8x8: vex_printf("InterleaveHI8x8"); return;
case Iop_InterleaveHI16x4: vex_printf("InterleaveHI16x4"); return;
case Iop_InterleaveHI32x2: vex_printf("InterleaveHI32x2"); return;
@@ -844,32 +844,32 @@
case Iop_Rol16x8: vex_printf("Rol16x8"); return;
case Iop_Rol32x4: vex_printf("Rol32x4"); return;
- case Iop_Narrow16x8: vex_printf("Narrow16x8"); return;
- case Iop_Narrow32x4: vex_printf("Narrow32x4"); return;
- case Iop_QNarrow16Uto8Ux16: vex_printf("QNarrow16Uto8Ux16"); return;
- case Iop_QNarrow32Sto16Ux8: vex_printf("QNarrow32Sto16Ux8"); return;
- case Iop_QNarrow16Sto8Ux16: vex_printf("QNarrow16Sto8Ux16"); return;
- case Iop_QNarrow32Uto16Ux8: vex_printf("QNarrow32Uto16Ux8"); return;
- case Iop_QNarrow16Sto8Sx16: vex_printf("QNarrow16Sto8Sx16"); return;
- case Iop_QNarrow32Sto16Sx8: vex_printf("QNarrow32Sto16Sx8"); return;
- case Iop_Shorten16x8: vex_printf("Shorten16x8"); return;
- case Iop_Shorten32x4: vex_printf("Shorten32x4"); return;
- case Iop_Shorten64x2: vex_printf("Shorten64x2"); return;
- case Iop_QShortenU16Ux8: vex_printf("QShortenU16Ux8"); return;
- case Iop_QShortenU32Ux4: vex_printf("QShortenU32Ux4"); return;
- case Iop_QShortenU64Ux2: vex_printf("QShortenU64Ux2"); return;
- case Iop_QShortenS16Sx8: vex_printf("QShortenS16Sx8"); return;
- case Iop_QShortenS32Sx4: vex_printf("QShortenS32Sx4"); return;
- case Iop_QShortenS64Sx2: vex_printf("QShortenS64Sx2"); return;
- case Iop_QShortenU16Sx8: vex_printf("QShortenU16Sx8"); return;
- case Iop_QShortenU32Sx4: vex_printf("QShortenU32Sx4"); return;
- case Iop_QShortenU64Sx2: vex_printf("QShortenU64Sx2"); return;
- case Iop_Longen8Ux8: vex_printf("Longen8Ux8"); return;
- case Iop_Longen16Ux4: vex_printf("Longen16Ux4"); return;
- case Iop_Longen32Ux2: vex_printf("Longen32Ux2"); return;
- case Iop_Longen8Sx8: vex_printf("Longen8Sx8"); return;
- case Iop_Longen16Sx4: vex_printf("Longen16Sx4"); return;
- case Iop_Longen32Sx2: vex_printf("Longen32Sx2"); return;
+ case Iop_NarrowBin16to8x16: vex_printf("NarrowBin16to8x16"); return;
+ case Iop_NarrowBin32to16x8: vex_printf("NarrowBin32to16x8"); return;
+ case Iop_QNarrowBin16Uto8Ux16: vex_printf("QNarrowBin16Uto8Ux16"); return;
+ case Iop_QNarrowBin32Sto16Ux8: vex_printf("QNarrowBin32Sto16Ux8"); return;
+ case Iop_QNarrowBin16Sto8Ux16: vex_printf("QNarrowBin16Sto8Ux16"); return;
+ case Iop_QNarrowBin32Uto16Ux8: vex_printf("QNarrowBin32Uto16Ux8"); return;
+ case Iop_QNarrowBin16Sto8Sx16: vex_printf("QNarrowBin16Sto8Sx16"); return;
+ case Iop_QNarrowBin32Sto16Sx8: vex_printf("QNarrowBin32Sto16Sx8"); return;
+ case Iop_NarrowUn16to8x8: vex_printf("NarrowUn16to8x8"); return;
+ case Iop_NarrowUn32to16x4: vex_printf("NarrowUn32to16x4"); return;
+ case Iop_NarrowUn64to32x2: vex_printf("NarrowUn64to32x2"); return;
+ case Iop_QNarrowUn16Uto8Ux8: vex_printf("QNarrowUn16Uto8Ux8"); return;
+ case Iop_QNarrowUn32Uto16Ux4: vex_printf("QNarrowUn32Uto16Ux4"); return;
+ case Iop_QNarrowUn64Uto32Ux2: vex_printf("QNarrowUn64Uto32Ux2"); return;
+ case Iop_QNarrowUn16Sto8Sx8: vex_printf("QNarrowUn16Sto8Sx8"); return;
+ case Iop_QNarrowUn32Sto16Sx4: vex_printf("QNarrowUn32Sto16Sx4"); return;
+ case Iop_QNarrowUn64Sto32Sx2: vex_printf("QNarrowUn64Sto32Sx2"); return;
+ case Iop_QNarrowUn16Sto8Ux8: vex_printf("QNarrowUn16Sto8Ux8"); return;
+ case Iop_QNarrowUn32Sto16Ux4: vex_printf("QNarrowUn32Sto16Ux4"); return;
+ case Iop_QNarrowUn64Sto32Ux2: vex_printf("QNarrowUn64Sto32Ux2"); return;
+ case Iop_Widen8Uto16x8: vex_printf("Widen8Uto16x8"); return;
+ case Iop_Widen16Uto32x4: vex_printf("Widen16Uto32x4"); return;
+ case Iop_Widen32Uto64x2: vex_printf("Widen32Uto64x2"); return;
+ case Iop_Widen8Sto16x8: vex_printf("Widen8Sto16x8"); return;
+ case Iop_Widen16Sto32x4: vex_printf("Widen16Sto32x4"); return;
+ case Iop_Widen32Sto64x2: vex_printf("Widen32Sto64x2"); return;
case Iop_InterleaveHI8x16: vex_printf("InterleaveHI8x16"); return;
case Iop_InterleaveHI16x8: vex_printf("InterleaveHI16x8"); return;
@@ -2054,8 +2054,8 @@
case Iop_QAdd32Ux2: case Iop_QAdd64Ux1:
case Iop_PwAdd8x8: case Iop_PwAdd16x4: case Iop_PwAdd32x2:
case Iop_PwAdd32Fx2:
- case Iop_QNarrow32Sto16Sx4:
- case Iop_QNarrow16Sto8Sx8: case Iop_QNarrow16Sto8Ux8:
+ case Iop_QNarrowBin32Sto16Sx4:
+ case Iop_QNarrowBin16Sto8Sx8: case Iop_QNarrowBin16Sto8Ux8:
case Iop_Sub8x8: case Iop_Sub16x4: case Iop_Sub32x2:
case Iop_QSub8Sx8: case Iop_QSub16Sx4:
case Iop_QSub32Sx2: case Iop_QSub64Sx1:
@@ -2332,17 +2332,31 @@
case Iop_Rsqrte32x4:
UNARY(Ity_V128, Ity_V128);
- case Iop_64HLtoV128: BINARY(Ity_I64,Ity_I64, Ity_V128);
+ case Iop_64HLtoV128:
+ BINARY(Ity_I64,Ity_I64, Ity_V128);
+
case Iop_V128to64: case Iop_V128HIto64:
- case Iop_Shorten16x8: case Iop_Shorten32x4: case Iop_Shorten64x2:
- case Iop_QShortenU16Ux8: case Iop_QShortenU32Ux4: case Iop_QShortenU64Ux2:
- case Iop_QShortenS16Sx8: case Iop_QShortenS32Sx4: case Iop_QShortenS64Sx2:
- case Iop_QShortenU16Sx8: case Iop_QShortenU32Sx4: case Iop_QShortenU64Sx2:
+ case Iop_NarrowUn16to8x8:
+ case Iop_NarrowUn32to16x4:
+ case Iop_NarrowUn64to32x2:
+ case Iop_QNarrowUn16Uto8Ux8:
+ case Iop_QNarrowUn32Uto16Ux4:
+ case Iop_QNarrowUn64Uto32Ux2:
+ case Iop_QNarrowUn16Sto8Sx8:
+ case Iop_QNarrowUn32Sto16Sx4:
+ case Iop_QNarrowUn64Sto32Sx2:
+ case Iop_QNarrowUn16Sto8Ux8:
+ case Iop_QNarrowUn32Sto16Ux4:
+ case Iop_QNarrowUn64Sto32Ux2:
case Iop_F32toF16x4:
UNARY(Ity_V128, Ity_I64);
- case Iop_Longen8Ux8: case Iop_Longen16Ux4: case Iop_Longen32Ux2:
- case Iop_Longen8Sx8: case Iop_Longen16Sx4: case Iop_Longen32Sx2:
+ case Iop_Widen8Uto16x8:
+ case Iop_Widen16Uto32x4:
+ case Iop_Widen32Uto64x2:
+ case Iop_Widen8Sto16x8:
+ case Iop_Widen16Sto32x4:
+ case Iop_Widen32Sto64x2:
case Iop_F16toF32x4:
UNARY(Ity_I64, Ity_V128);
@@ -2414,16 +2428,18 @@
case Iop_CmpGT64Sx2:
case Iop_CmpGT8Ux16: case Iop_CmpGT16Ux8: case Iop_CmpGT32Ux4:
case Iop_Shl8x16: case Iop_Shl16x8: case Iop_Shl32x4: case Iop_Shl64x2:
- case Iop_QShl8x16: case Iop_QShl16x8: case Iop_QShl32x4: case Iop_QShl64x2:
- case Iop_QSal8x16: case Iop_QSal16x8: case Iop_QSal32x4: case Iop_QSal64x2:
+ case Iop_QShl8x16: case Iop_QShl16x8:
+ case Iop_QShl32x4: case Iop_QShl64x2:
+ case Iop_QSal8x16: case Iop_QSal16x8:
+ case Iop_QSal32x4: case Iop_QSal64x2:
case Iop_Shr8x16: case Iop_Shr16x8: case Iop_Shr32x4: case Iop_Shr64x2:
case Iop_Sar8x16: case Iop_Sar16x8: case Iop_Sar32x4: case Iop_Sar64x2:
case Iop_Sal8x16: case Iop_Sal16x8: case Iop_Sal32x4: case Iop_Sal64x2:
case Iop_Rol8x16: case Iop_Rol16x8: case Iop_Rol32x4:
- case Iop_QNarrow16Sto8Ux16: case Iop_QNarrow32Sto16Ux8:
- case Iop_QNarrow16Sto8Sx16: case Iop_QNarrow32Sto16Sx8:
- case Iop_QNarrow16Uto8Ux16: case Iop_QNarrow32Uto16Ux8:
- case Iop_Narrow16x8: case Iop_Narrow32x4:
+ case Iop_QNarrowBin16Sto8Ux16: case Iop_QNarrowBin32Sto16Ux8:
+ case Iop_QNarrowBin16Sto8Sx16: case Iop_QNarrowBin32Sto16Sx8:
+ case Iop_QNarrowBin16Uto8Ux16: case Iop_QNarrowBin32Uto16Ux8:
+ case Iop_NarrowBin16to8x16: case Iop_NarrowBin32to16x8:
case Iop_InterleaveHI8x16: case Iop_InterleaveHI16x8:
case Iop_InterleaveHI32x4: case Iop_InterleaveHI64x2:
case Iop_InterleaveLO8x16: case Iop_InterleaveLO16x8: